Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

171 files changed, 55551 insertions, 12976 deletions

diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c
new file mode 100644
index 000000000000..19241576b6b5
--- /dev/null
+++ b/sound/soc/codecs/88pm860x-codec.c
@@ -0,0 +1,1490 @@
+/*
+ * 88pm860x-codec.c -- 88PM860x ALSA SoC Audio Driver
+ *
+ * Copyright 2010 Marvell International Ltd.
+ * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/88pm860x.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include <sound/initval.h>
+#include <sound/jack.h>
+#include <trace/events/asoc.h>
+
+#include "88pm860x-codec.h"
+
+#define MAX_NAME_LEN            20
+#define REG_CACHE_SIZE          0x40
+#define REG_CACHE_BASE          0xb0
+
+/* Status Register 1 (0x01) */
+#define REG_STATUS_1            0x01
+#define MIC_STATUS              (1 << 7)
+#define HOOK_STATUS             (1 << 6)
+#define HEADSET_STATUS          (1 << 5)
+
+/* Mic Detection Register (0x37) */
+#define REG_MIC_DET             0x37
+#define CONTINUOUS_POLLING      (3 << 1)
+#define EN_MIC_DET              (1 << 0)
+#define MICDET_MASK             0x07
+
+/* Headset Detection Register (0x38) */
+#define REG_HS_DET              0x38
+#define EN_HS_DET               (1 << 0)
+
+/* Misc2 Register (0x42) */
+#define REG_MISC2               0x42
+#define AUDIO_PLL               (1 << 5)
+#define AUDIO_SECTION_RESET     (1 << 4)
+#define AUDIO_SECTION_ON        (1 << 3)
+
+/* PCM Interface Register 2 (0xb1) */
+#define PCM_INF2_BCLK           (1 << 6)        /* Bit clock polarity */
+#define PCM_INF2_FS             (1 << 5)        /* Frame Sync polarity */
+#define PCM_INF2_MASTER         (1 << 4)        /* Master / Slave */
+#define PCM_INF2_18WL           (1 << 3)        /* 18 / 16 bits */
+#define PCM_GENERAL_I2S         0
+#define PCM_EXACT_I2S           1
+#define PCM_LEFT_I2S            2
+#define PCM_RIGHT_I2S           3
+#define PCM_SHORT_FS            4
+#define PCM_LONG_FS             5
+#define PCM_MODE_MASK           7
+
+/* I2S Interface Register 4 (0xbe) */
+#define I2S_EQU_BYP             (1 << 6)
+
+/* DAC Offset Register (0xcb) */
+#define DAC_MUTE                (1 << 7)
+#define MUTE_LEFT               (1 << 6)
+#define MUTE_RIGHT              (1 << 2)
+
+/* ADC Analog Register 1 (0xd0) */
+#define REG_ADC_ANA_1           0xd0
+#define MIC1BIAS_MASK           0x60
+
+/* Earpiece/Speaker Control Register 2 (0xda) */
+#define REG_EAR2                0xda
+#define RSYNC_CHANGE            (1 << 2)
+
+/* Audio Supplies Register 2 (0xdc) */
+#define REG_SUPPLIES2           0xdc
+#define LDO15_READY             (1 << 4)
+#define LDO15_EN                (1 << 3)
+#define CPUMP_READY             (1 << 2)
+#define CPUMP_EN                (1 << 1)
+#define AUDIO_EN                (1 << 0)
+#define SUPPLY_MASK             (LDO15_EN | CPUMP_EN | AUDIO_EN)
+
+/* Audio Enable Register 1 (0xdd) */
+#define ADC_MOD_RIGHT           (1 << 1)
+#define ADC_MOD_LEFT            (1 << 0)
+
+/* Audio Enable Register 2 (0xde) */
+#define ADC_LEFT                (1 << 5)
+#define ADC_RIGHT               (1 << 4)
+
+/* DAC Enable Register 2 (0xe1) */
+#define DAC_LEFT                (1 << 5)
+#define DAC_RIGHT               (1 << 4)
+#define MODULATOR               (1 << 3)
+
+/* Shorts Register (0xeb) */
+#define REG_SHORTS              0xeb
+#define CLR_SHORT_LO2           (1 << 7)
+#define SHORT_LO2               (1 << 6)
+#define CLR_SHORT_LO1           (1 << 5)
+#define SHORT_LO1               (1 << 4)
+#define CLR_SHORT_HS2           (1 << 3)
+#define SHORT_HS2               (1 << 2)
+#define CLR_SHORT_HS1           (1 << 1)
+#define SHORT_HS1               (1 << 0)
+
+/*
+ * This widget should be just after DAC & PGA in DAPM power-on sequence and
+ * before DAC & PGA in DAPM power-off sequence.
+ */
+#define PM860X_DAPM_OUTPUT(wname, wevent)       \
+{       .id = snd_soc_dapm_pga, .name = wname, .reg = SND_SOC_NOPM, \
+        .shift = 0, .invert = 0, .kcontrol_news = NULL, \
+        .num_kcontrols = 0, .event = wevent, \
+        .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD, }
+
+struct pm860x_det {
+        struct snd_soc_jack     *hp_jack;
+        struct snd_soc_jack     *mic_jack;
+        int                     hp_det;
+        int                     mic_det;
+        int                     hook_det;
+        int                     hs_shrt;
+        int                     lo_shrt;
+};
+
+struct pm860x_priv {
+        unsigned int            sysclk;
+        unsigned int            pcmclk;
+        unsigned int            dir;
+        unsigned int            filter;
+        struct snd_soc_codec    *codec;
+        struct i2c_client       *i2c;
+        struct pm860x_chip      *chip;
+        struct pm860x_det       det;
+
+        int                     irq[4];
+        unsigned char           name[4][MAX_NAME_LEN];
+};
+
+/* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */
+static const DECLARE_TLV_DB_SCALE(dpga_tlv, -9450, 150, 1);
+
+/* -9dB to 0db in 3dB steps */
+static const DECLARE_TLV_DB_SCALE(adc_tlv, -900, 300, 0);
+
+/* {-23, -17, -13.5, -11, -9, -6, -3, 0}dB */
+static const unsigned int mic_tlv[] = {
+        TLV_DB_RANGE_HEAD(5),
+        0, 0, TLV_DB_SCALE_ITEM(-2300, 0, 0),
+        1, 1, TLV_DB_SCALE_ITEM(-1700, 0, 0),
+        2, 2, TLV_DB_SCALE_ITEM(-1350, 0, 0),
+        3, 3, TLV_DB_SCALE_ITEM(-1100, 0, 0),
+        4, 7, TLV_DB_SCALE_ITEM(-900, 300, 0),
+};
+
+/* {0, 0, 0, -6, 0, 6, 12, 18}dB */
+static const unsigned int aux_tlv[] = {
+        TLV_DB_RANGE_HEAD(2),
+        0, 2, TLV_DB_SCALE_ITEM(0, 0, 0),
+        3, 7, TLV_DB_SCALE_ITEM(-600, 600, 0),
+};
+
+/* {-16, -13, -10, -7, -5.2, -3,3, -2.2, 0}dB, mute instead of -16dB */
+static const unsigned int out_tlv[] = {
+        TLV_DB_RANGE_HEAD(4),
+        0, 3, TLV_DB_SCALE_ITEM(-1600, 300, 1),
+        4, 4, TLV_DB_SCALE_ITEM(-520, 0, 0),
+        5, 5, TLV_DB_SCALE_ITEM(-330, 0, 0),
+        6, 7, TLV_DB_SCALE_ITEM(-220, 220, 0),
+};
+
+static const unsigned int st_tlv[] = {
+        TLV_DB_RANGE_HEAD(8),
+        0, 1, TLV_DB_SCALE_ITEM(-12041, 602, 0),
+        2, 3, TLV_DB_SCALE_ITEM(-11087, 250, 0),
+        4, 5, TLV_DB_SCALE_ITEM(-10643, 158, 0),
+        6, 7, TLV_DB_SCALE_ITEM(-10351, 116, 0),
+        8, 9, TLV_DB_SCALE_ITEM(-10133, 92, 0),
+        10, 13, TLV_DB_SCALE_ITEM(-9958, 70, 0),
+        14, 17, TLV_DB_SCALE_ITEM(-9689, 53, 0),
+        18, 271, TLV_DB_SCALE_ITEM(-9484, 37, 0),
+};
+
+/* Sidetone Gain = M * 2^(-5-N) */
+struct st_gain {
+        unsigned int    db;
+        unsigned int    m;
+        unsigned int    n;
+};
+
+static struct st_gain st_table[] = {
+        {-12041,  1, 15}, {-11439,  1, 14}, {-11087,  3, 15}, {-10837,  1, 13},
+        {-10643,  5, 15}, {-10485,  3, 14}, {-10351,  7, 15}, {-10235,  1, 12},
+        {-10133,  9, 15}, {-10041,  5, 14}, { -9958, 11, 15}, { -9883,  3, 13},
+        { -9813, 13, 15}, { -9749,  7, 14}, { -9689, 15, 15}, { -9633,  1, 11},
+        { -9580, 17, 15}, { -9531,  9, 14}, { -9484, 19, 15}, { -9439,  5, 13},
+        { -9397, 21, 15}, { -9356, 11, 14}, { -9318, 23, 15}, { -9281,  3, 12},
+        { -9245, 25, 15}, { -9211, 13, 14}, { -9178, 27, 15}, { -9147,  7, 13},
+        { -9116, 29, 15}, { -9087, 15, 14}, { -9058, 31, 15}, { -9031,  1, 10},
+        { -8978, 17, 14}, { -8929,  9, 13}, { -8882, 19, 14}, { -8837,  5, 12},
+        { -8795, 21, 14}, { -8754, 11, 13}, { -8716, 23, 14}, { -8679,  3, 11},
+        { -8643, 25, 14}, { -8609, 13, 13}, { -8576, 27, 14}, { -8545,  7, 12},
+        { -8514, 29, 14}, { -8485, 15, 13}, { -8456, 31, 14}, { -8429,  1,  9},
+        { -8376, 17, 13}, { -8327,  9, 12}, { -8280, 19, 13}, { -8235,  5, 11},
+        { -8193, 21, 13}, { -8152, 11, 12}, { -8114, 23, 13}, { -8077,  3, 10},
+        { -8041, 25, 13}, { -8007, 13, 12}, { -7974, 27, 13}, { -7943,  7, 11},
+        { -7912, 29, 13}, { -7883, 15, 12}, { -7854, 31, 13}, { -7827,  1,  8},
+        { -7774, 17, 12}, { -7724,  9, 11}, { -7678, 19, 12}, { -7633,  5, 10},
+        { -7591, 21, 12}, { -7550, 11, 11}, { -7512, 23, 12}, { -7475,  3,  9},
+        { -7439, 25, 12}, { -7405, 13, 11}, { -7372, 27, 12}, { -7341,  7, 10},
+        { -7310, 29, 12}, { -7281, 15, 11}, { -7252, 31, 12}, { -7225,  1,  7},
+        { -7172, 17, 11}, { -7122,  9, 10}, { -7075, 19, 11}, { -7031,  5,  9},
+        { -6989, 21, 11}, { -6948, 11, 10}, { -6910, 23, 11}, { -6873,  3,  8},
+        { -6837, 25, 11}, { -6803, 13, 10}, { -6770, 27, 11}, { -6739,  7,  9},
+        { -6708, 29, 11}, { -6679, 15, 10}, { -6650, 31, 11}, { -6623,  1,  6},
+        { -6570, 17, 10}, { -6520,  9,  9}, { -6473, 19, 10}, { -6429,  5,  8},
+        { -6386, 21, 10}, { -6346, 11,  9}, { -6307, 23, 10}, { -6270,  3,  7},
+        { -6235, 25, 10}, { -6201, 13,  9}, { -6168, 27, 10}, { -6137,  7,  8},
+        { -6106, 29, 10}, { -6077, 15,  9}, { -6048, 31, 10}, { -6021,  1,  5},
+        { -5968, 17,  9}, { -5918,  9,  8}, { -5871, 19,  9}, { -5827,  5,  7},
+        { -5784, 21,  9}, { -5744, 11,  8}, { -5705, 23,  9}, { -5668,  3,  6},
+        { -5633, 25,  9}, { -5599, 13,  8}, { -5566, 27,  9}, { -5535,  7,  7},
+        { -5504, 29,  9}, { -5475, 15,  8}, { -5446, 31,  9}, { -5419,  1,  4},
+        { -5366, 17,  8}, { -5316,  9,  7}, { -5269, 19,  8}, { -5225,  5,  6},
+        { -5182, 21,  8}, { -5142, 11,  7}, { -5103, 23,  8}, { -5066,  3,  5},
+        { -5031, 25,  8}, { -4997, 13,  7}, { -4964, 27,  8}, { -4932,  7,  6},
+        { -4902, 29,  8}, { -4873, 15,  7}, { -4844, 31,  8}, { -4816,  1,  3},
+        { -4764, 17,  7}, { -4714,  9,  6}, { -4667, 19,  7}, { -4623,  5,  5},
+        { -4580, 21,  7}, { -4540, 11,  6}, { -4501, 23,  7}, { -4464,  3,  4},
+        { -4429, 25,  7}, { -4395, 13,  6}, { -4362, 27,  7}, { -4330,  7,  5},
+        { -4300, 29,  7}, { -4270, 15,  6}, { -4242, 31,  7}, { -4214,  1,  2},
+        { -4162, 17,  6}, { -4112,  9,  5}, { -4065, 19,  6}, { -4021,  5,  4},
+        { -3978, 21,  6}, { -3938, 11,  5}, { -3899, 23,  6}, { -3862,  3,  3},
+        { -3827, 25,  6}, { -3793, 13,  5}, { -3760, 27,  6}, { -3728,  7,  4},
+        { -3698, 29,  6}, { -3668, 15,  5}, { -3640, 31,  6}, { -3612,  1,  1},
+        { -3560, 17,  5}, { -3510,  9,  4}, { -3463, 19,  5}, { -3419,  5,  3},
+        { -3376, 21,  5}, { -3336, 11,  4}, { -3297, 23,  5}, { -3260,  3,  2},
+        { -3225, 25,  5}, { -3191, 13,  4}, { -3158, 27,  5}, { -3126,  7,  3},
+        { -3096, 29,  5}, { -3066, 15,  4}, { -3038, 31,  5}, { -3010,  1,  0},
+        { -2958, 17,  4}, { -2908,  9,  3}, { -2861, 19,  4}, { -2816,  5,  2},
+        { -2774, 21,  4}, { -2734, 11,  3}, { -2695, 23,  4}, { -2658,  3,  1},
+        { -2623, 25,  4}, { -2589, 13,  3}, { -2556, 27,  4}, { -2524,  7,  2},
+        { -2494, 29,  4}, { -2464, 15,  3}, { -2436, 31,  4}, { -2408,  2,  0},
+        { -2356, 17,  3}, { -2306,  9,  2}, { -2259, 19,  3}, { -2214,  5,  1},
+        { -2172, 21,  3}, { -2132, 11,  2}, { -2093, 23,  3}, { -2056,  3,  0},
+        { -2021, 25,  3}, { -1987, 13,  2}, { -1954, 27,  3}, { -1922,  7,  1},
+        { -1892, 29,  3}, { -1862, 15,  2}, { -1834, 31,  3}, { -1806,  4,  0},
+        { -1754, 17,  2}, { -1704,  9,  1}, { -1657, 19,  2}, { -1612,  5,  0},
+        { -1570, 21,  2}, { -1530, 11,  1}, { -1491, 23,  2}, { -1454,  6,  0},
+        { -1419, 25,  2}, { -1384, 13,  1}, { -1352, 27,  2}, { -1320,  7,  0},
+        { -1290, 29,  2}, { -1260, 15,  1}, { -1232, 31,  2}, { -1204,  8,  0},
+        { -1151, 17,  1}, { -1102,  9,  0}, { -1055, 19,  1}, { -1010, 10,  0},
+        {  -968, 21,  1}, {  -928, 11,  0}, {  -889, 23,  1}, {  -852, 12,  0},
+        {  -816, 25,  1}, {  -782, 13,  0}, {  -750, 27,  1}, {  -718, 14,  0},
+        {  -688, 29,  1}, {  -658, 15,  0}, {  -630, 31,  1}, {  -602, 16,  0},
+        {  -549, 17,  0}, {  -500, 18,  0}, {  -453, 19,  0}, {  -408, 20,  0},
+        {  -366, 21,  0}, {  -325, 22,  0}, {  -287, 23,  0}, {  -250, 24,  0},
+        {  -214, 25,  0}, {  -180, 26,  0}, {  -148, 27,  0}, {  -116, 28,  0},
+        {   -86, 29,  0}, {   -56, 30,  0}, {   -28, 31,  0}, {     0,  0,  0},
+};
+
+static int pm860x_volatile(unsigned int reg)
+{
+        BUG_ON(reg >= REG_CACHE_SIZE);
+
+        switch (reg) {
+        case PM860X_AUDIO_SUPPLIES_2:
+                return 1;
+        }
+
+        return 0;
+}
+
+static unsigned int pm860x_read_reg_cache(struct snd_soc_codec *codec,
+                                          unsigned int reg)
+{
+        unsigned char *cache = codec->reg_cache;
+
+        BUG_ON(reg >= REG_CACHE_SIZE);
+
+        if (pm860x_volatile(reg))
+                return cache[reg];
+
+        reg += REG_CACHE_BASE;
+
+        return pm860x_reg_read(codec->control_data, reg);
+}
+
+static int pm860x_write_reg_cache(struct snd_soc_codec *codec,
+                                  unsigned int reg, unsigned int value)
+{
+        unsigned char *cache = codec->reg_cache;
+
+        BUG_ON(reg >= REG_CACHE_SIZE);
+
+        if (!pm860x_volatile(reg))
+                cache[reg] = (unsigned char)value;
+
+        reg += REG_CACHE_BASE;
+
+        return pm860x_reg_write(codec->control_data, reg, value);
+}
+
+static int snd_soc_get_volsw_2r_st(struct snd_kcontrol *kcontrol,
+                                   struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int reg = mc->reg;
+        unsigned int reg2 = mc->rreg;
+        int val[2], val2[2], i;
+
+        val[0] = snd_soc_read(codec, reg) & 0x3f;
+        val[1] = (snd_soc_read(codec, PM860X_SIDETONE_SHIFT) >> 4) & 0xf;
+        val2[0] = snd_soc_read(codec, reg2) & 0x3f;
+        val2[1] = (snd_soc_read(codec, PM860X_SIDETONE_SHIFT)) & 0xf;
+
+        for (i = 0; i < ARRAY_SIZE(st_table); i++) {
+                if ((st_table[i].m == val[0]) && (st_table[i].n == val[1]))
+                        ucontrol->value.integer.value[0] = i;
+                if ((st_table[i].m == val2[0]) && (st_table[i].n == val2[1]))
+                        ucontrol->value.integer.value[1] = i;
+        }
+        return 0;
+}
+
+static int snd_soc_put_volsw_2r_st(struct snd_kcontrol *kcontrol,
+                                   struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int reg = mc->reg;
+        unsigned int reg2 = mc->rreg;
+        int err;
+        unsigned int val, val2;
+
+        val = ucontrol->value.integer.value[0];
+        val2 = ucontrol->value.integer.value[1];
+
+        err = snd_soc_update_bits(codec, reg, 0x3f, st_table[val].m);
+        if (err < 0)
+                return err;
+        err = snd_soc_update_bits(codec, PM860X_SIDETONE_SHIFT, 0xf0,
+                                  st_table[val].n << 4);
+        if (err < 0)
+                return err;
+
+        err = snd_soc_update_bits(codec, reg2, 0x3f, st_table[val2].m);
+        if (err < 0)
+                return err;
+        err = snd_soc_update_bits(codec, PM860X_SIDETONE_SHIFT, 0x0f,
+                                  st_table[val2].n);
+        return err;
+}
+
+static int snd_soc_get_volsw_2r_out(struct snd_kcontrol *kcontrol,
+                                    struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int reg = mc->reg;
+        unsigned int reg2 = mc->rreg;
+        unsigned int shift = mc->shift;
+        int max = mc->max, val, val2;
+        unsigned int mask = (1 << fls(max)) - 1;
+
+        val = snd_soc_read(codec, reg) >> shift;
+        val2 = snd_soc_read(codec, reg2) >> shift;
+        ucontrol->value.integer.value[0] = (max - val) & mask;
+        ucontrol->value.integer.value[1] = (max - val2) & mask;
+
+        return 0;
+}
+
+static int snd_soc_put_volsw_2r_out(struct snd_kcontrol *kcontrol,
+                                    struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int reg = mc->reg;
+        unsigned int reg2 = mc->rreg;
+        unsigned int shift = mc->shift;
+        int max = mc->max;
+        unsigned int mask = (1 << fls(max)) - 1;
+        int err;
+        unsigned int val, val2, val_mask;
+
+        val_mask = mask << shift;
+        val = ((max - ucontrol->value.integer.value[0]) & mask);
+        val2 = ((max - ucontrol->value.integer.value[1]) & mask);
+
+        val = val << shift;
+        val2 = val2 << shift;
+
+        err = snd_soc_update_bits(codec, reg, val_mask, val);
+        if (err < 0)
+                return err;
+
+        err = snd_soc_update_bits(codec, reg2, val_mask, val2);
+        return err;
+}
+
+/* DAPM Widget Events */
+/*
+ * A lot registers are belong to RSYNC domain. It requires enabling RSYNC bit
+ * after updating these registers. Otherwise, these updated registers won't
+ * be effective.
+ */
+static int pm860x_rsync_event(struct snd_soc_dapm_widget *w,
+                              struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+
+        /*
+         * In order to avoid current on the load, mute power-on and power-off
+         * should be transients.
+         * Unmute by DAC_MUTE. It should be unmuted when DAPM sequence is
+         * finished.
+         */
+        snd_soc_update_bits(codec, PM860X_DAC_OFFSET, DAC_MUTE, 0);
+        snd_soc_update_bits(codec, PM860X_EAR_CTRL_2,
+                            RSYNC_CHANGE, RSYNC_CHANGE);
+        return 0;
+}
+
+static int pm860x_dac_event(struct snd_soc_dapm_widget *w,
+                            struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        unsigned int dac = 0;
+        int data;
+
+        if (!strcmp(w->name, "Left DAC"))
+                dac = DAC_LEFT;
+        if (!strcmp(w->name, "Right DAC"))
+                dac = DAC_RIGHT;
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                if (dac) {
+                        /* Auto mute in power-on sequence. */
+                        dac |= MODULATOR;
+                        snd_soc_update_bits(codec, PM860X_DAC_OFFSET,
+                                            DAC_MUTE, DAC_MUTE);
+                        snd_soc_update_bits(codec, PM860X_EAR_CTRL_2,
+                                            RSYNC_CHANGE, RSYNC_CHANGE);
+                        /* update dac */
+                        snd_soc_update_bits(codec, PM860X_DAC_EN_2,
+                                            dac, dac);
+                }
+                break;
+        case SND_SOC_DAPM_PRE_PMD:
+                if (dac) {
+                        /* Auto mute in power-off sequence. */
+                        snd_soc_update_bits(codec, PM860X_DAC_OFFSET,
+                                            DAC_MUTE, DAC_MUTE);
+                        snd_soc_update_bits(codec, PM860X_EAR_CTRL_2,
+                                            RSYNC_CHANGE, RSYNC_CHANGE);
+                        /* update dac */
+                        data = snd_soc_read(codec, PM860X_DAC_EN_2);
+                        data &= ~dac;
+                        if (!(data & (DAC_LEFT | DAC_RIGHT)))
+                                data &= ~MODULATOR;
+                        snd_soc_write(codec, PM860X_DAC_EN_2, data);
+                }
+                break;
+        }
+        return 0;
+}
+
+static const char *pm860x_opamp_texts[] = {"-50%", "-25%", "0%", "75%"};
+
+static const char *pm860x_pa_texts[] = {"-33%", "0%", "33%", "66%"};
+
+static const struct soc_enum pm860x_hs1_opamp_enum =
+        SOC_ENUM_SINGLE(PM860X_HS1_CTRL, 5, 4, pm860x_opamp_texts);
+
+static const struct soc_enum pm860x_hs2_opamp_enum =
+        SOC_ENUM_SINGLE(PM860X_HS2_CTRL, 5, 4, pm860x_opamp_texts);
+
+static const struct soc_enum pm860x_hs1_pa_enum =
+        SOC_ENUM_SINGLE(PM860X_HS1_CTRL, 3, 4, pm860x_pa_texts);
+
+static const struct soc_enum pm860x_hs2_pa_enum =
+        SOC_ENUM_SINGLE(PM860X_HS2_CTRL, 3, 4, pm860x_pa_texts);
+
+static const struct soc_enum pm860x_lo1_opamp_enum =
+        SOC_ENUM_SINGLE(PM860X_LO1_CTRL, 5, 4, pm860x_opamp_texts);
+
+static const struct soc_enum pm860x_lo2_opamp_enum =
+        SOC_ENUM_SINGLE(PM860X_LO2_CTRL, 5, 4, pm860x_opamp_texts);
+
+static const struct soc_enum pm860x_lo1_pa_enum =
+        SOC_ENUM_SINGLE(PM860X_LO1_CTRL, 3, 4, pm860x_pa_texts);
+
+static const struct soc_enum pm860x_lo2_pa_enum =
+        SOC_ENUM_SINGLE(PM860X_LO2_CTRL, 3, 4, pm860x_pa_texts);
+
+static const struct soc_enum pm860x_spk_pa_enum =
+        SOC_ENUM_SINGLE(PM860X_EAR_CTRL_1, 5, 4, pm860x_pa_texts);
+
+static const struct soc_enum pm860x_ear_pa_enum =
+        SOC_ENUM_SINGLE(PM860X_EAR_CTRL_2, 0, 4, pm860x_pa_texts);
+
+static const struct soc_enum pm860x_spk_ear_opamp_enum =
+        SOC_ENUM_SINGLE(PM860X_EAR_CTRL_1, 3, 4, pm860x_opamp_texts);
+
+static const struct snd_kcontrol_new pm860x_snd_controls[] = {
+        SOC_DOUBLE_R_TLV("ADC Capture Volume", PM860X_ADC_ANA_2,
+                        PM860X_ADC_ANA_3, 6, 3, 0, adc_tlv),
+        SOC_DOUBLE_TLV("AUX Capture Volume", PM860X_ADC_ANA_3, 0, 3, 7, 0,
+                        aux_tlv),
+        SOC_SINGLE_TLV("MIC1 Capture Volume", PM860X_ADC_ANA_2, 0, 7, 0,
+                        mic_tlv),
+        SOC_SINGLE_TLV("MIC3 Capture Volume", PM860X_ADC_ANA_2, 3, 7, 0,
+                        mic_tlv),
+        SOC_DOUBLE_R_EXT_TLV("Sidetone Volume", PM860X_SIDETONE_L_GAIN,
+                             PM860X_SIDETONE_R_GAIN, 0, ARRAY_SIZE(st_table)-1,
+                             0, snd_soc_get_volsw_2r_st,
+                             snd_soc_put_volsw_2r_st, st_tlv),
+        SOC_SINGLE_TLV("Speaker Playback Volume", PM860X_EAR_CTRL_1,
+                        0, 7, 0, out_tlv),
+        SOC_DOUBLE_R_TLV("Line Playback Volume", PM860X_LO1_CTRL,
+                         PM860X_LO2_CTRL, 0, 7, 0, out_tlv),
+        SOC_DOUBLE_R_TLV("Headset Playback Volume", PM860X_HS1_CTRL,
+                         PM860X_HS2_CTRL, 0, 7, 0, out_tlv),
+        SOC_DOUBLE_R_EXT_TLV("Hifi Left Playback Volume",
+                             PM860X_HIFIL_GAIN_LEFT,
+                             PM860X_HIFIL_GAIN_RIGHT, 0, 63, 0,
+                             snd_soc_get_volsw_2r_out,
+                             snd_soc_put_volsw_2r_out, dpga_tlv),
+        SOC_DOUBLE_R_EXT_TLV("Hifi Right Playback Volume",
+                             PM860X_HIFIR_GAIN_LEFT,
+                             PM860X_HIFIR_GAIN_RIGHT, 0, 63, 0,
+                             snd_soc_get_volsw_2r_out,
+                             snd_soc_put_volsw_2r_out, dpga_tlv),
+        SOC_DOUBLE_R_EXT_TLV("Lofi Playback Volume", PM860X_LOFI_GAIN_LEFT,
+                             PM860X_LOFI_GAIN_RIGHT, 0, 63, 0,
+                             snd_soc_get_volsw_2r_out,
+                             snd_soc_put_volsw_2r_out, dpga_tlv),
+        SOC_ENUM("Headset1 Operational Amplifier Current",
+                 pm860x_hs1_opamp_enum),
+        SOC_ENUM("Headset2 Operational Amplifier Current",
+                 pm860x_hs2_opamp_enum),
+        SOC_ENUM("Headset1 Amplifier Current", pm860x_hs1_pa_enum),
+        SOC_ENUM("Headset2 Amplifier Current", pm860x_hs2_pa_enum),
+        SOC_ENUM("Lineout1 Operational Amplifier Current",
+                 pm860x_lo1_opamp_enum),
+        SOC_ENUM("Lineout2 Operational Amplifier Current",
+                 pm860x_lo2_opamp_enum),
+        SOC_ENUM("Lineout1 Amplifier Current", pm860x_lo1_pa_enum),
+        SOC_ENUM("Lineout2 Amplifier Current", pm860x_lo2_pa_enum),
+        SOC_ENUM("Speaker Operational Amplifier Current",
+                 pm860x_spk_ear_opamp_enum),
+        SOC_ENUM("Speaker Amplifier Current", pm860x_spk_pa_enum),
+        SOC_ENUM("Earpiece Amplifier Current", pm860x_ear_pa_enum),
+};
+
+/*
+ * DAPM Controls
+ */
+
+/* PCM Switch / PCM Interface */
+static const struct snd_kcontrol_new pcm_switch_controls =
+        SOC_DAPM_SINGLE("Switch", PM860X_ADC_EN_2, 0, 1, 0);
+
+/* AUX1 Switch */
+static const struct snd_kcontrol_new aux1_switch_controls =
+        SOC_DAPM_SINGLE("Switch", PM860X_ANA_TO_ANA, 4, 1, 0);
+
+/* AUX2 Switch */
+static const struct snd_kcontrol_new aux2_switch_controls =
+        SOC_DAPM_SINGLE("Switch", PM860X_ANA_TO_ANA, 5, 1, 0);
+
+/* Left Ex. PA Switch */
+static const struct snd_kcontrol_new lepa_switch_controls =
+        SOC_DAPM_SINGLE("Switch", PM860X_DAC_EN_2, 2, 1, 0);
+
+/* Right Ex. PA Switch */
+static const struct snd_kcontrol_new repa_switch_controls =
+        SOC_DAPM_SINGLE("Switch", PM860X_DAC_EN_2, 1, 1, 0);
+
+/* PCM Mux / Mux7 */
+static const char *aif1_text[] = {
+        "PCM L", "PCM R",
+};
+
+static const struct soc_enum aif1_enum =
+        SOC_ENUM_SINGLE(PM860X_PCM_IFACE_3, 6, 2, aif1_text);
+
+static const struct snd_kcontrol_new aif1_mux =
+        SOC_DAPM_ENUM("PCM Mux", aif1_enum);
+
+/* I2S Mux / Mux9 */
+static const char *i2s_din_text[] = {
+        "DIN", "DIN1",
+};
+
+static const struct soc_enum i2s_din_enum =
+        SOC_ENUM_SINGLE(PM860X_I2S_IFACE_3, 1, 2, i2s_din_text);
+
+static const struct snd_kcontrol_new i2s_din_mux =
+        SOC_DAPM_ENUM("I2S DIN Mux", i2s_din_enum);
+
+/* I2S Mic Mux / Mux8 */
+static const char *i2s_mic_text[] = {
+        "Ex PA", "ADC",
+};
+
+static const struct soc_enum i2s_mic_enum =
+        SOC_ENUM_SINGLE(PM860X_I2S_IFACE_3, 4, 2, i2s_mic_text);
+
+static const struct snd_kcontrol_new i2s_mic_mux =
+        SOC_DAPM_ENUM("I2S Mic Mux", i2s_mic_enum);
+
+/* ADCL Mux / Mux2 */
+static const char *adcl_text[] = {
+        "ADCR", "ADCL",
+};
+
+static const struct soc_enum adcl_enum =
+        SOC_ENUM_SINGLE(PM860X_PCM_IFACE_3, 4, 2, adcl_text);
+
+static const struct snd_kcontrol_new adcl_mux =
+        SOC_DAPM_ENUM("ADC Left Mux", adcl_enum);
+
+/* ADCR Mux / Mux3 */
+static const char *adcr_text[] = {
+        "ADCL", "ADCR",
+};
+
+static const struct soc_enum adcr_enum =
+        SOC_ENUM_SINGLE(PM860X_PCM_IFACE_3, 2, 2, adcr_text);
+
+static const struct snd_kcontrol_new adcr_mux =
+        SOC_DAPM_ENUM("ADC Right Mux", adcr_enum);
+
+/* ADCR EC Mux / Mux6 */
+static const char *adcr_ec_text[] = {
+        "ADCR", "EC",
+};
+
+static const struct soc_enum adcr_ec_enum =
+        SOC_ENUM_SINGLE(PM860X_ADC_EN_2, 3, 2, adcr_ec_text);
+
+static const struct snd_kcontrol_new adcr_ec_mux =
+        SOC_DAPM_ENUM("ADCR EC Mux", adcr_ec_enum);
+
+/* EC Mux / Mux4 */
+static const char *ec_text[] = {
+        "Left", "Right", "Left + Right",
+};
+
+static const struct soc_enum ec_enum =
+        SOC_ENUM_SINGLE(PM860X_EC_PATH, 1, 3, ec_text);
+
+static const struct snd_kcontrol_new ec_mux =
+        SOC_DAPM_ENUM("EC Mux", ec_enum);
+
+static const char *dac_text[] = {
+        "No input", "Right", "Left", "No input",
+};
+
+/* DAC Headset 1 Mux / Mux10 */
+static const struct soc_enum dac_hs1_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_INPUT_SEL_1, 0, 4, dac_text);
+
+static const struct snd_kcontrol_new dac_hs1_mux =
+        SOC_DAPM_ENUM("DAC HS1 Mux", dac_hs1_enum);
+
+/* DAC Headset 2 Mux / Mux11 */
+static const struct soc_enum dac_hs2_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_INPUT_SEL_1, 2, 4, dac_text);
+
+static const struct snd_kcontrol_new dac_hs2_mux =
+        SOC_DAPM_ENUM("DAC HS2 Mux", dac_hs2_enum);
+
+/* DAC Lineout 1 Mux / Mux12 */
+static const struct soc_enum dac_lo1_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_INPUT_SEL_1, 4, 4, dac_text);
+
+static const struct snd_kcontrol_new dac_lo1_mux =
+        SOC_DAPM_ENUM("DAC LO1 Mux", dac_lo1_enum);
+
+/* DAC Lineout 2 Mux / Mux13 */
+static const struct soc_enum dac_lo2_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_INPUT_SEL_1, 6, 4, dac_text);
+
+static const struct snd_kcontrol_new dac_lo2_mux =
+        SOC_DAPM_ENUM("DAC LO2 Mux", dac_lo2_enum);
+
+/* DAC Spearker Earphone Mux / Mux14 */
+static const struct soc_enum dac_spk_ear_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_INPUT_SEL_2, 0, 4, dac_text);
+
+static const struct snd_kcontrol_new dac_spk_ear_mux =
+        SOC_DAPM_ENUM("DAC SP Mux", dac_spk_ear_enum);
+
+/* Headset 1 Mux / Mux15 */
+static const char *in_text[] = {
+        "Digital", "Analog",
+};
+
+static const struct soc_enum hs1_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_TO_ANA, 0, 2, in_text);
+
+static const struct snd_kcontrol_new hs1_mux =
+        SOC_DAPM_ENUM("Headset1 Mux", hs1_enum);
+
+/* Headset 2 Mux / Mux16 */
+static const struct soc_enum hs2_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_TO_ANA, 1, 2, in_text);
+
+static const struct snd_kcontrol_new hs2_mux =
+        SOC_DAPM_ENUM("Headset2 Mux", hs2_enum);
+
+/* Lineout 1 Mux / Mux17 */
+static const struct soc_enum lo1_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_TO_ANA, 2, 2, in_text);
+
+static const struct snd_kcontrol_new lo1_mux =
+        SOC_DAPM_ENUM("Lineout1 Mux", lo1_enum);
+
+/* Lineout 2 Mux / Mux18 */
+static const struct soc_enum lo2_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_TO_ANA, 3, 2, in_text);
+
+static const struct snd_kcontrol_new lo2_mux =
+        SOC_DAPM_ENUM("Lineout2 Mux", lo2_enum);
+
+/* Speaker Earpiece Demux */
+static const char *spk_text[] = {
+        "Earpiece", "Speaker",
+};
+
+static const struct soc_enum spk_enum =
+        SOC_ENUM_SINGLE(PM860X_ANA_TO_ANA, 6, 2, spk_text);
+
+static const struct snd_kcontrol_new spk_demux =
+        SOC_DAPM_ENUM("Speaker Earpiece Demux", spk_enum);
+
+/* MIC Mux / Mux1 */
+static const char *mic_text[] = {
+        "Mic 1", "Mic 2",
+};
+
+static const struct soc_enum mic_enum =
+        SOC_ENUM_SINGLE(PM860X_ADC_ANA_4, 4, 2, mic_text);
+
+static const struct snd_kcontrol_new mic_mux =
+        SOC_DAPM_ENUM("MIC Mux", mic_enum);
+
+static const struct snd_soc_dapm_widget pm860x_dapm_widgets[] = {
+        SND_SOC_DAPM_AIF_IN("PCM SDI", "PCM Playback", 0,
+                            PM860X_ADC_EN_2, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("PCM SDO", "PCM Capture", 0,
+                             PM860X_PCM_IFACE_3, 1, 1),
+
+
+        SND_SOC_DAPM_AIF_IN("I2S DIN", "I2S Playback", 0,
+                            PM860X_DAC_EN_2, 0, 0),
+        SND_SOC_DAPM_AIF_IN("I2S DIN1", "I2S Playback", 0,
+                            PM860X_DAC_EN_2, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("I2S DOUT", "I2S Capture", 0,
+                             PM860X_I2S_IFACE_3, 5, 1),
+        SND_SOC_DAPM_MUX("I2S Mic Mux", SND_SOC_NOPM, 0, 0, &i2s_mic_mux),
+        SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adcl_mux),
+        SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
+        SND_SOC_DAPM_MUX("EC Mux", SND_SOC_NOPM, 0, 0, &ec_mux),
+        SND_SOC_DAPM_MUX("ADCR EC Mux", SND_SOC_NOPM, 0, 0, &adcr_ec_mux),
+        SND_SOC_DAPM_SWITCH("Left EPA", SND_SOC_NOPM, 0, 0,
+                            &lepa_switch_controls),
+        SND_SOC_DAPM_SWITCH("Right EPA", SND_SOC_NOPM, 0, 0,
+                            &repa_switch_controls),
+
+        SND_SOC_DAPM_REG(snd_soc_dapm_supply, "Left ADC MOD", PM860X_ADC_EN_1,
+                         0, 1, 1, 0),
+        SND_SOC_DAPM_REG(snd_soc_dapm_supply, "Right ADC MOD", PM860X_ADC_EN_1,
+                         1, 1, 1, 0),
+        SND_SOC_DAPM_ADC("Left ADC", NULL, PM860X_ADC_EN_2, 5, 0),
+        SND_SOC_DAPM_ADC("Right ADC", NULL, PM860X_ADC_EN_2, 4, 0),
+
+        SND_SOC_DAPM_SWITCH("AUX1 Switch", SND_SOC_NOPM, 0, 0,
+                            &aux1_switch_controls),
+        SND_SOC_DAPM_SWITCH("AUX2 Switch", SND_SOC_NOPM, 0, 0,
+                            &aux2_switch_controls),
+
+        SND_SOC_DAPM_MUX("MIC Mux", SND_SOC_NOPM, 0, 0, &mic_mux),
+        SND_SOC_DAPM_MICBIAS("Mic1 Bias", PM860X_ADC_ANA_1, 2, 0),
+        SND_SOC_DAPM_MICBIAS("Mic3 Bias", PM860X_ADC_ANA_1, 7, 0),
+        SND_SOC_DAPM_PGA("MIC1 Volume", PM860X_ADC_EN_1, 2, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("MIC3 Volume", PM860X_ADC_EN_1, 3, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("AUX1 Volume", PM860X_ADC_EN_1, 4, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("AUX2 Volume", PM860X_ADC_EN_1, 5, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Sidetone PGA", PM860X_ADC_EN_2, 1, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Lofi PGA", PM860X_ADC_EN_2, 2, 0, NULL, 0),
+
+        SND_SOC_DAPM_INPUT("AUX1"),
+        SND_SOC_DAPM_INPUT("AUX2"),
+        SND_SOC_DAPM_INPUT("MIC1P"),
+        SND_SOC_DAPM_INPUT("MIC1N"),
+        SND_SOC_DAPM_INPUT("MIC2P"),
+        SND_SOC_DAPM_INPUT("MIC2N"),
+        SND_SOC_DAPM_INPUT("MIC3P"),
+        SND_SOC_DAPM_INPUT("MIC3N"),
+
+        SND_SOC_DAPM_DAC_E("Left DAC", NULL, SND_SOC_NOPM, 0, 0,
+                           pm860x_dac_event,
+                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+        SND_SOC_DAPM_DAC_E("Right DAC", NULL, SND_SOC_NOPM, 0, 0,
+                           pm860x_dac_event,
+                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+
+        SND_SOC_DAPM_MUX("I2S DIN Mux", SND_SOC_NOPM, 0, 0, &i2s_din_mux),
+        SND_SOC_DAPM_MUX("DAC HS1 Mux", SND_SOC_NOPM, 0, 0, &dac_hs1_mux),
+        SND_SOC_DAPM_MUX("DAC HS2 Mux", SND_SOC_NOPM, 0, 0, &dac_hs2_mux),
+        SND_SOC_DAPM_MUX("DAC LO1 Mux", SND_SOC_NOPM, 0, 0, &dac_lo1_mux),
+        SND_SOC_DAPM_MUX("DAC LO2 Mux", SND_SOC_NOPM, 0, 0, &dac_lo2_mux),
+        SND_SOC_DAPM_MUX("DAC SP Mux", SND_SOC_NOPM, 0, 0, &dac_spk_ear_mux),
+        SND_SOC_DAPM_MUX("Headset1 Mux", SND_SOC_NOPM, 0, 0, &hs1_mux),
+        SND_SOC_DAPM_MUX("Headset2 Mux", SND_SOC_NOPM, 0, 0, &hs2_mux),
+        SND_SOC_DAPM_MUX("Lineout1 Mux", SND_SOC_NOPM, 0, 0, &lo1_mux),
+        SND_SOC_DAPM_MUX("Lineout2 Mux", SND_SOC_NOPM, 0, 0, &lo2_mux),
+        SND_SOC_DAPM_MUX("Speaker Earpiece Demux", SND_SOC_NOPM, 0, 0,
+                         &spk_demux),
+
+
+        SND_SOC_DAPM_PGA("Headset1 PGA", PM860X_DAC_EN_1, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Headset2 PGA", PM860X_DAC_EN_1, 1, 0, NULL, 0),
+        SND_SOC_DAPM_OUTPUT("HS1"),
+        SND_SOC_DAPM_OUTPUT("HS2"),
+        SND_SOC_DAPM_PGA("Lineout1 PGA", PM860X_DAC_EN_1, 2, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Lineout2 PGA", PM860X_DAC_EN_1, 3, 0, NULL, 0),
+        SND_SOC_DAPM_OUTPUT("LINEOUT1"),
+        SND_SOC_DAPM_OUTPUT("LINEOUT2"),
+        SND_SOC_DAPM_PGA("Earpiece PGA", PM860X_DAC_EN_1, 4, 0, NULL, 0),
+        SND_SOC_DAPM_OUTPUT("EARP"),
+        SND_SOC_DAPM_OUTPUT("EARN"),
+        SND_SOC_DAPM_PGA("Speaker PGA", PM860X_DAC_EN_1, 5, 0, NULL, 0),
+        SND_SOC_DAPM_OUTPUT("LSP"),
+        SND_SOC_DAPM_OUTPUT("LSN"),
+        SND_SOC_DAPM_REG(snd_soc_dapm_supply, "VCODEC", PM860X_AUDIO_SUPPLIES_2,
+                         0, SUPPLY_MASK, SUPPLY_MASK, 0),
+
+        PM860X_DAPM_OUTPUT("RSYNC", pm860x_rsync_event),
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+        /* supply */
+        {"Left DAC", NULL, "VCODEC"},
+        {"Right DAC", NULL, "VCODEC"},
+        {"Left ADC", NULL, "VCODEC"},
+        {"Right ADC", NULL, "VCODEC"},
+        {"Left ADC", NULL, "Left ADC MOD"},
+        {"Right ADC", NULL, "Right ADC MOD"},
+
+        /* PCM/AIF1 Inputs */
+        {"PCM SDO", NULL, "ADC Left Mux"},
+        {"PCM SDO", NULL, "ADCR EC Mux"},
+
+        /* PCM/AFI2 Outputs */
+        {"Lofi PGA", NULL, "PCM SDI"},
+        {"Lofi PGA", NULL, "Sidetone PGA"},
+        {"Left DAC", NULL, "Lofi PGA"},
+        {"Right DAC", NULL, "Lofi PGA"},
+
+        /* I2S/AIF2 Inputs */
+        {"MIC Mux", "Mic 1", "MIC1P"},
+        {"MIC Mux", "Mic 1", "MIC1N"},
+        {"MIC Mux", "Mic 2", "MIC2P"},
+        {"MIC Mux", "Mic 2", "MIC2N"},
+        {"MIC1 Volume", NULL, "MIC Mux"},
+        {"MIC3 Volume", NULL, "MIC3P"},
+        {"MIC3 Volume", NULL, "MIC3N"},
+        {"Left ADC", NULL, "MIC1 Volume"},
+        {"Right ADC", NULL, "MIC3 Volume"},
+        {"ADC Left Mux", "ADCR", "Right ADC"},
+        {"ADC Left Mux", "ADCL", "Left ADC"},
+        {"ADC Right Mux", "ADCL", "Left ADC"},
+        {"ADC Right Mux", "ADCR", "Right ADC"},
+        {"Left EPA", "Switch", "Left DAC"},
+        {"Right EPA", "Switch", "Right DAC"},
+        {"EC Mux", "Left", "Left DAC"},
+        {"EC Mux", "Right", "Right DAC"},
+        {"EC Mux", "Left + Right", "Left DAC"},
+        {"EC Mux", "Left + Right", "Right DAC"},
+        {"ADCR EC Mux", "ADCR", "ADC Right Mux"},
+        {"ADCR EC Mux", "EC", "EC Mux"},
+        {"I2S Mic Mux", "Ex PA", "Left EPA"},
+        {"I2S Mic Mux", "Ex PA", "Right EPA"},
+        {"I2S Mic Mux", "ADC", "ADC Left Mux"},
+        {"I2S Mic Mux", "ADC", "ADCR EC Mux"},
+        {"I2S DOUT", NULL, "I2S Mic Mux"},
+
+        /* I2S/AIF2 Outputs */
+        {"I2S DIN Mux", "DIN", "I2S DIN"},
+        {"I2S DIN Mux", "DIN1", "I2S DIN1"},
+        {"Left DAC", NULL, "I2S DIN Mux"},
+        {"Right DAC", NULL, "I2S DIN Mux"},
+        {"DAC HS1 Mux", "Left", "Left DAC"},
+        {"DAC HS1 Mux", "Right", "Right DAC"},
+        {"DAC HS2 Mux", "Left", "Left DAC"},
+        {"DAC HS2 Mux", "Right", "Right DAC"},
+        {"DAC LO1 Mux", "Left", "Left DAC"},
+        {"DAC LO1 Mux", "Right", "Right DAC"},
+        {"DAC LO2 Mux", "Left", "Left DAC"},
+        {"DAC LO2 Mux", "Right", "Right DAC"},
+        {"Headset1 Mux", "Digital", "DAC HS1 Mux"},
+        {"Headset2 Mux", "Digital", "DAC HS2 Mux"},
+        {"Lineout1 Mux", "Digital", "DAC LO1 Mux"},
+        {"Lineout2 Mux", "Digital", "DAC LO2 Mux"},
+        {"Headset1 PGA", NULL, "Headset1 Mux"},
+        {"Headset2 PGA", NULL, "Headset2 Mux"},
+        {"Lineout1 PGA", NULL, "Lineout1 Mux"},
+        {"Lineout2 PGA", NULL, "Lineout2 Mux"},
+        {"DAC SP Mux", "Left", "Left DAC"},
+        {"DAC SP Mux", "Right", "Right DAC"},
+        {"Speaker Earpiece Demux", "Speaker", "DAC SP Mux"},
+        {"Speaker PGA", NULL, "Speaker Earpiece Demux"},
+        {"Earpiece PGA", NULL, "Speaker Earpiece Demux"},
+
+        {"RSYNC", NULL, "Headset1 PGA"},
+        {"RSYNC", NULL, "Headset2 PGA"},
+        {"RSYNC", NULL, "Lineout1 PGA"},
+        {"RSYNC", NULL, "Lineout2 PGA"},
+        {"RSYNC", NULL, "Speaker PGA"},
+        {"RSYNC", NULL, "Speaker PGA"},
+        {"RSYNC", NULL, "Earpiece PGA"},
+        {"RSYNC", NULL, "Earpiece PGA"},
+
+        {"HS1", NULL, "RSYNC"},
+        {"HS2", NULL, "RSYNC"},
+        {"LINEOUT1", NULL, "RSYNC"},
+        {"LINEOUT2", NULL, "RSYNC"},
+        {"LSP", NULL, "RSYNC"},
+        {"LSN", NULL, "RSYNC"},
+        {"EARP", NULL, "RSYNC"},
+        {"EARN", NULL, "RSYNC"},
+};
+
+/*
+ * Use MUTE_LEFT & MUTE_RIGHT to implement digital mute.
+ * These bits can also be used to mute.
+ */
+static int pm860x_digital_mute(struct snd_soc_dai *codec_dai, int mute)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        int data = 0, mask = MUTE_LEFT | MUTE_RIGHT;
+
+        if (mute)
+                data = mask;
+        snd_soc_update_bits(codec, PM860X_DAC_OFFSET, mask, data);
+        snd_soc_update_bits(codec, PM860X_EAR_CTRL_2,
+                            RSYNC_CHANGE, RSYNC_CHANGE);
+        return 0;
+}
+
+static int pm860x_pcm_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params,
+                                struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        unsigned char inf = 0, mask = 0;
+
+        /* bit size */
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                inf &= ~PCM_INF2_18WL;
+                break;
+        case SNDRV_PCM_FORMAT_S18_3LE:
+                inf |= PCM_INF2_18WL;
+                break;
+        default:
+                return -EINVAL;
+        }
+        mask |= PCM_INF2_18WL;
+        snd_soc_update_bits(codec, PM860X_PCM_IFACE_2, mask, inf);
+
+        /* sample rate */
+        switch (params_rate(params)) {
+        case 8000:
+                inf = 0;
+                break;
+        case 16000:
+                inf = 3;
+                break;
+        case 32000:
+                inf = 6;
+                break;
+        case 48000:
+                inf = 8;
+                break;
+        default:
+                return -EINVAL;
+        }
+        snd_soc_update_bits(codec, PM860X_PCM_RATE, 0x0f, inf);
+
+        return 0;
+}
+
+static int pm860x_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                                  unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
+        unsigned char inf = 0, mask = 0;
+        int ret = -EINVAL;
+
+        mask |= PCM_INF2_BCLK | PCM_INF2_FS | PCM_INF2_MASTER;
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+        case SND_SOC_DAIFMT_CBM_CFS:
+                if (pm860x->dir == PM860X_CLK_DIR_OUT) {
+                        inf |= PCM_INF2_MASTER;
+                        ret = 0;
+                }
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                if (pm860x->dir == PM860X_CLK_DIR_IN) {
+                        inf &= ~PCM_INF2_MASTER;
+                        ret = 0;
+                }
+                break;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                inf |= PCM_EXACT_I2S;
+                ret = 0;
+                break;
+        }
+        mask |= PCM_MODE_MASK;
+        if (ret)
+                return ret;
+        snd_soc_update_bits(codec, PM860X_PCM_IFACE_2, mask, inf);
+        return 0;
+}
+
+static int pm860x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                                 int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
+
+        if (dir == PM860X_CLK_DIR_OUT)
+                pm860x->dir = PM860X_CLK_DIR_OUT;
+        else {
+                pm860x->dir = PM860X_CLK_DIR_IN;
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int pm860x_i2s_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params,
+                                struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        unsigned char inf;
+
+        /* bit size */
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                inf = 0;
+                break;
+        case SNDRV_PCM_FORMAT_S18_3LE:
+                inf = PCM_INF2_18WL;
+                break;
+        default:
+                return -EINVAL;
+        }
+        snd_soc_update_bits(codec, PM860X_I2S_IFACE_2, PCM_INF2_18WL, inf);
+
+        /* sample rate */
+        switch (params_rate(params)) {
+        case 8000:
+                inf = 0;
+                break;
+        case 11025:
+                inf = 1;
+                break;
+        case 16000:
+                inf = 3;
+                break;
+        case 22050:
+                inf = 4;
+                break;
+        case 32000:
+                inf = 6;
+                break;
+        case 44100:
+                inf = 7;
+                break;
+        case 48000:
+                inf = 8;
+                break;
+        default:
+                return -EINVAL;
+        }
+        snd_soc_update_bits(codec, PM860X_I2S_IFACE_4, 0xf, inf);
+
+        return 0;
+}
+
+static int pm860x_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                                  unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
+        unsigned char inf = 0, mask = 0;
+
+        mask |= PCM_INF2_BCLK | PCM_INF2_FS | PCM_INF2_MASTER;
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                if (pm860x->dir == PM860X_CLK_DIR_OUT)
+                        inf |= PCM_INF2_MASTER;
+                else
+                        return -EINVAL;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                if (pm860x->dir == PM860X_CLK_DIR_IN)
+                        inf &= ~PCM_INF2_MASTER;
+                else
+                        return -EINVAL;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                inf |= PCM_EXACT_I2S;
+                break;
+        default:
+                return -EINVAL;
+        }
+        mask |= PCM_MODE_MASK;
+        snd_soc_update_bits(codec, PM860X_I2S_IFACE_2, mask, inf);
+        return 0;
+}
+
+static int pm860x_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        int data;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+
+        case SND_SOC_BIAS_PREPARE:
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        /* Enable Audio PLL & Audio section */
+                        data = AUDIO_PLL | AUDIO_SECTION_RESET
+                                | AUDIO_SECTION_ON;
+                        pm860x_reg_write(codec->control_data, REG_MISC2, data);
+                }
+                break;
+
+        case SND_SOC_BIAS_OFF:
+                data = AUDIO_PLL | AUDIO_SECTION_RESET | AUDIO_SECTION_ON;
+                pm860x_set_bits(codec->control_data, REG_MISC2, data, 0);
+                break;
+        }
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+static struct snd_soc_dai_ops pm860x_pcm_dai_ops = {
+        .digital_mute   = pm860x_digital_mute,
+        .hw_params      = pm860x_pcm_hw_params,
+        .set_fmt        = pm860x_pcm_set_dai_fmt,
+        .set_sysclk     = pm860x_set_dai_sysclk,
+};
+
+static struct snd_soc_dai_ops pm860x_i2s_dai_ops = {
+        .digital_mute   = pm860x_digital_mute,
+        .hw_params      = pm860x_i2s_hw_params,
+        .set_fmt        = pm860x_i2s_set_dai_fmt,
+        .set_sysclk     = pm860x_set_dai_sysclk,
+};
+
+#define PM860X_RATES    (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |   \
+                         SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
+
+static struct snd_soc_dai_driver pm860x_dai[] = {
+        {
+                /* DAI PCM */
+                .name   = "88pm860x-pcm",
+                .id     = 1,
+                .playback = {
+                        .stream_name    = "PCM Playback",
+                        .channels_min   = 2,
+                        .channels_max   = 2,
+                        .rates          = PM860X_RATES,
+                        .formats        = SNDRV_PCM_FORMAT_S16_LE | \
+                                          SNDRV_PCM_FORMAT_S18_3LE,
+                },
+                .capture = {
+                        .stream_name    = "PCM Capture",
+                        .channels_min   = 2,
+                        .channels_max   = 2,
+                        .rates          = PM860X_RATES,
+                        .formats        = SNDRV_PCM_FORMAT_S16_LE | \
+                                          SNDRV_PCM_FORMAT_S18_3LE,
+                },
+                .ops    = &pm860x_pcm_dai_ops,
+        }, {
+                /* DAI I2S */
+                .name   = "88pm860x-i2s",
+                .id     = 2,
+                .playback = {
+                        .stream_name    = "I2S Playback",
+                        .channels_min   = 2,
+                        .channels_max   = 2,
+                        .rates          = SNDRV_PCM_RATE_8000_48000,
+                        .formats        = SNDRV_PCM_FORMAT_S16_LE | \
+                                          SNDRV_PCM_FORMAT_S18_3LE,
+                },
+                .capture = {
+                        .stream_name    = "I2S Capture",
+                        .channels_min   = 2,
+                        .channels_max   = 2,
+                        .rates          = SNDRV_PCM_RATE_8000_48000,
+                        .formats        = SNDRV_PCM_FORMAT_S16_LE | \
+                                          SNDRV_PCM_FORMAT_S18_3LE,
+                },
+                .ops    = &pm860x_i2s_dai_ops,
+        },
+};
+
+static irqreturn_t pm860x_codec_handler(int irq, void *data)
+{
+        struct pm860x_priv *pm860x = data;
+        int status, shrt, report = 0, mic_report = 0;
+        int mask;
+
+        status = pm860x_reg_read(pm860x->i2c, REG_STATUS_1);
+        shrt = pm860x_reg_read(pm860x->i2c, REG_SHORTS);
+        mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt
+                | pm860x->det.hp_det;
+
+#ifndef CONFIG_SND_SOC_88PM860X_MODULE
+        if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 |
+                      SHORT_LO1 | SHORT_LO2))
+                trace_snd_soc_jack_irq(dev_name(pm860x->codec->dev));
+#endif
+
+        if ((pm860x->det.hp_det & SND_JACK_HEADPHONE)
+                && (status & HEADSET_STATUS))
+                report |= SND_JACK_HEADPHONE;
+
+        if ((pm860x->det.mic_det & SND_JACK_MICROPHONE)
+                && (status & MIC_STATUS))
+                mic_report |= SND_JACK_MICROPHONE;
+
+        if (pm860x->det.hs_shrt && (shrt & (SHORT_HS1 | SHORT_HS2)))
+                report |= pm860x->det.hs_shrt;
+
+        if (pm860x->det.hook_det && (status & HOOK_STATUS))
+                report |= pm860x->det.hook_det;
+
+        if (pm860x->det.lo_shrt && (shrt & (SHORT_LO1 | SHORT_LO2)))
+                report |= pm860x->det.lo_shrt;
+
+        if (report)
+                snd_soc_jack_report(pm860x->det.hp_jack, report, mask);
+        if (mic_report)
+                snd_soc_jack_report(pm860x->det.mic_jack, SND_JACK_MICROPHONE,
+                                    SND_JACK_MICROPHONE);
+
+        dev_dbg(pm860x->codec->dev, "headphone report:0x%x, mask:%x\n",
+                report, mask);
+        dev_dbg(pm860x->codec->dev, "microphone report:0x%x\n", mic_report);
+        return IRQ_HANDLED;
+}
+
+int pm860x_hs_jack_detect(struct snd_soc_codec *codec,
+                          struct snd_soc_jack *jack,
+                          int det, int hook, int hs_shrt, int lo_shrt)
+{
+        struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
+        int data;
+
+        pm860x->det.hp_jack = jack;
+        pm860x->det.hp_det = det;
+        pm860x->det.hook_det = hook;
+        pm860x->det.hs_shrt = hs_shrt;
+        pm860x->det.lo_shrt = lo_shrt;
+
+        if (det & SND_JACK_HEADPHONE)
+                pm860x_set_bits(codec->control_data, REG_HS_DET,
+                                EN_HS_DET, EN_HS_DET);
+        /* headset short detect */
+        if (hs_shrt) {
+                data = CLR_SHORT_HS2 | CLR_SHORT_HS1;
+                pm860x_set_bits(codec->control_data, REG_SHORTS, data, data);
+        }
+        /* Lineout short detect */
+        if (lo_shrt) {
+                data = CLR_SHORT_LO2 | CLR_SHORT_LO1;
+                pm860x_set_bits(codec->control_data, REG_SHORTS, data, data);
+        }
+
+        /* sync status */
+        pm860x_codec_handler(0, pm860x);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(pm860x_hs_jack_detect);
+
+int pm860x_mic_jack_detect(struct snd_soc_codec *codec,
+                           struct snd_soc_jack *jack, int det)
+{
+        struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
+
+        pm860x->det.mic_jack = jack;
+        pm860x->det.mic_det = det;
+
+        if (det & SND_JACK_MICROPHONE)
+                pm860x_set_bits(codec->control_data, REG_MIC_DET,
+                                MICDET_MASK, MICDET_MASK);
+
+        /* sync status */
+        pm860x_codec_handler(0, pm860x);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(pm860x_mic_jack_detect);
+
+static int pm860x_probe(struct snd_soc_codec *codec)
+{
+        struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int i, ret;
+
+        pm860x->codec = codec;
+
+        codec->control_data = pm860x->i2c;
+
+        for (i = 0; i < 4; i++) {
+                ret = request_threaded_irq(pm860x->irq[i], NULL,
+                                           pm860x_codec_handler, IRQF_ONESHOT,
+                                           pm860x->name[i], pm860x);
+                if (ret < 0) {
+                        dev_err(codec->dev, "Failed to request IRQ!\n");
+                        goto out;
+                }
+        }
+
+        pm860x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        ret = pm860x_bulk_read(codec->control_data, REG_CACHE_BASE,
+                               REG_CACHE_SIZE, codec->reg_cache);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to fill register cache: %d\n",
+                        ret);
+                goto out;
+        }
+
+        snd_soc_add_controls(codec, pm860x_snd_controls,
+                             ARRAY_SIZE(pm860x_snd_controls));
+        snd_soc_dapm_new_controls(dapm, pm860x_dapm_widgets,
+                                  ARRAY_SIZE(pm860x_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+        return 0;
+
+out:
+        while (--i >= 0)
+                free_irq(pm860x->irq[i], pm860x);
+        return ret;
+}
+
+static int pm860x_remove(struct snd_soc_codec *codec)
+{
+        struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
+        int i;
+
+        for (i = 3; i >= 0; i--)
+                free_irq(pm860x->irq[i], pm860x);
+        pm860x_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_pm860x = {
+        .probe          = pm860x_probe,
+        .remove         = pm860x_remove,
+        .read           = pm860x_read_reg_cache,
+        .write          = pm860x_write_reg_cache,
+        .reg_cache_size = REG_CACHE_SIZE,
+        .reg_word_size  = sizeof(u8),
+        .set_bias_level = pm860x_set_bias_level,
+};
+
+static int __devinit pm860x_codec_probe(struct platform_device *pdev)
+{
+        struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent);
+        struct pm860x_priv *pm860x;
+        struct resource *res;
+        int i, ret;
+
+        pm860x = kzalloc(sizeof(struct pm860x_priv), GFP_KERNEL);
+        if (pm860x == NULL)
+                return -ENOMEM;
+
+        pm860x->chip = chip;
+        pm860x->i2c = (chip->id == CHIP_PM8607) ? chip->client
+                        : chip->companion;
+        platform_set_drvdata(pdev, pm860x);
+
+        for (i = 0; i < 4; i++) {
+                res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+                if (!res) {
+                        dev_err(&pdev->dev, "Failed to get IRQ resources\n");
+                        goto out;
+                }
+                pm860x->irq[i] = res->start + chip->irq_base;
+                strncpy(pm860x->name[i], res->name, MAX_NAME_LEN);
+        }
+
+        ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pm860x,
+                                     pm860x_dai, ARRAY_SIZE(pm860x_dai));
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to register codec\n");
+                goto out;
+        }
+        return ret;
+
+out:
+        platform_set_drvdata(pdev, NULL);
+        kfree(pm860x);
+        return -EINVAL;
+}
+
+static int __devexit pm860x_codec_remove(struct platform_device *pdev)
+{
+        struct pm860x_priv *pm860x = platform_get_drvdata(pdev);
+
+        snd_soc_unregister_codec(&pdev->dev);
+        platform_set_drvdata(pdev, NULL);
+        kfree(pm860x);
+        return 0;
+}
+
+static struct platform_driver pm860x_codec_driver = {
+        .driver = {
+                .name   = "88pm860x-codec",
+                .owner  = THIS_MODULE,
+        },
+        .probe  = pm860x_codec_probe,
+        .remove = __devexit_p(pm860x_codec_remove),
+};
+
+static __init int pm860x_init(void)
+{
+        return platform_driver_register(&pm860x_codec_driver);
+}
+module_init(pm860x_init);
+
+static __exit void pm860x_exit(void)
+{
+        platform_driver_unregister(&pm860x_codec_driver);
+}
+module_exit(pm860x_exit);
+
+MODULE_DESCRIPTION("ASoC 88PM860x driver");
+MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:88pm860x-codec");
+
diff --git a/sound/soc/codecs/88pm860x-codec.h b/sound/soc/codecs/88pm860x-codec.h
new file mode 100644
index 000000000000..3364ba4a3607
--- /dev/null
+++ b/sound/soc/codecs/88pm860x-codec.h
@@ -0,0 +1,97 @@
+/*
+ * 88pm860x-codec.h -- 88PM860x ALSA SoC Audio Driver
+ *
+ * Copyright 2010 Marvell International Ltd.
+ *      Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __88PM860X_H
+#define __88PM860X_H
+
+/* The offset of these registers are 0xb0 */
+#define PM860X_PCM_IFACE_1              0x00
+#define PM860X_PCM_IFACE_2              0x01
+#define PM860X_PCM_IFACE_3              0x02
+#define PM860X_PCM_RATE                 0x03
+#define PM860X_EC_PATH                  0x04
+#define PM860X_SIDETONE_L_GAIN          0x05
+#define PM860X_SIDETONE_R_GAIN          0x06
+#define PM860X_SIDETONE_SHIFT           0x07
+#define PM860X_ADC_OFFSET_1             0x08
+#define PM860X_ADC_OFFSET_2             0x09
+#define PM860X_DMIC_DELAY               0x0a
+
+#define PM860X_I2S_IFACE_1              0x0b
+#define PM860X_I2S_IFACE_2              0x0c
+#define PM860X_I2S_IFACE_3              0x0d
+#define PM860X_I2S_IFACE_4              0x0e
+#define PM860X_EQUALIZER_N0_1           0x0f
+#define PM860X_EQUALIZER_N0_2           0x10
+#define PM860X_EQUALIZER_N1_1           0x11
+#define PM860X_EQUALIZER_N1_2           0x12
+#define PM860X_EQUALIZER_D1_1           0x13
+#define PM860X_EQUALIZER_D1_2           0x14
+#define PM860X_LOFI_GAIN_LEFT           0x15
+#define PM860X_LOFI_GAIN_RIGHT          0x16
+#define PM860X_HIFIL_GAIN_LEFT          0x17
+#define PM860X_HIFIL_GAIN_RIGHT         0x18
+#define PM860X_HIFIR_GAIN_LEFT          0x19
+#define PM860X_HIFIR_GAIN_RIGHT         0x1a
+#define PM860X_DAC_OFFSET               0x1b
+#define PM860X_OFFSET_LEFT_1            0x1c
+#define PM860X_OFFSET_LEFT_2            0x1d
+#define PM860X_OFFSET_RIGHT_1           0x1e
+#define PM860X_OFFSET_RIGHT_2           0x1f
+#define PM860X_ADC_ANA_1                0x20
+#define PM860X_ADC_ANA_2                0x21
+#define PM860X_ADC_ANA_3                0x22
+#define PM860X_ADC_ANA_4                0x23
+#define PM860X_ANA_TO_ANA               0x24
+#define PM860X_HS1_CTRL                 0x25
+#define PM860X_HS2_CTRL                 0x26
+#define PM860X_LO1_CTRL                 0x27
+#define PM860X_LO2_CTRL                 0x28
+#define PM860X_EAR_CTRL_1               0x29
+#define PM860X_EAR_CTRL_2               0x2a
+#define PM860X_AUDIO_SUPPLIES_1         0x2b
+#define PM860X_AUDIO_SUPPLIES_2         0x2c
+#define PM860X_ADC_EN_1                 0x2d
+#define PM860X_ADC_EN_2                 0x2e
+#define PM860X_DAC_EN_1                 0x2f
+#define PM860X_DAC_EN_2                 0x31
+#define PM860X_AUDIO_CAL_1              0x32
+#define PM860X_AUDIO_CAL_2              0x33
+#define PM860X_AUDIO_CAL_3              0x34
+#define PM860X_AUDIO_CAL_4              0x35
+#define PM860X_AUDIO_CAL_5              0x36
+#define PM860X_ANA_INPUT_SEL_1          0x37
+#define PM860X_ANA_INPUT_SEL_2          0x38
+
+#define PM860X_PCM_IFACE_4              0x39
+#define PM860X_I2S_IFACE_5              0x3a
+
+#define PM860X_SHORTS                   0x3b
+#define PM860X_PLL_ADJ_1                0x3c
+#define PM860X_PLL_ADJ_2                0x3d
+
+/* bits definition */
+#define PM860X_CLK_DIR_IN               0
+#define PM860X_CLK_DIR_OUT              1
+
+#define PM860X_DET_HEADSET              (1 << 0)
+#define PM860X_DET_MIC                  (1 << 1)
+#define PM860X_DET_HOOK                 (1 << 2)
+#define PM860X_SHORT_HEADSET            (1 << 3)
+#define PM860X_SHORT_LINEOUT            (1 << 4)
+#define PM860X_DET_MASK                 0x1F
+
+extern int pm860x_hs_jack_detect(struct snd_soc_codec *, struct snd_soc_jack *,
+                                 int, int, int, int);
+extern int pm860x_mic_jack_detect(struct snd_soc_codec *, struct snd_soc_jack *,
+                                  int);
+
+#endif  /* __88PM860X_H */
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 83f5c67d3c41..98175a096df2 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -10,29 +10,42 @@ config SND_SOC_I2C_AND_SPI
 
 config SND_SOC_ALL_CODECS
         tristate "Build all ASoC CODEC drivers"
+        select SND_SOC_88PM860X if MFD_88PM860X
         select SND_SOC_L3
         select SND_SOC_AC97_CODEC if SND_SOC_AC97_BUS
         select SND_SOC_AD1836 if SPI_MASTER
         select SND_SOC_AD193X if SND_SOC_I2C_AND_SPI
         select SND_SOC_AD1980 if SND_SOC_AC97_BUS
+        select SND_SOC_AD73311
         select SND_SOC_ADS117X
-        select SND_SOC_AD73311 if I2C
         select SND_SOC_AK4104 if SPI_MASTER
         select SND_SOC_AK4535 if I2C
+        select SND_SOC_AK4641 if I2C
         select SND_SOC_AK4642 if I2C
         select SND_SOC_AK4671 if I2C
+        select SND_SOC_ALC5623 if I2C
         select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC
         select SND_SOC_CS42L51 if I2C
         select SND_SOC_CS4270 if I2C
+        select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI
+        select SND_SOC_CX20442
         select SND_SOC_DA7210 if I2C
-        select SND_SOC_JZ4740 if SOC_JZ4740
+        select SND_SOC_DFBMCS320
+        select SND_SOC_JZ4740_CODEC if SOC_JZ4740
+        select SND_SOC_LM4857 if I2C
+        select SND_SOC_MAX98088 if I2C
+        select SND_SOC_MAX98095 if I2C
+        select SND_SOC_MAX9850 if I2C
         select SND_SOC_MAX9877 if I2C
         select SND_SOC_PCM3008
+        select SND_SOC_SGTL5000 if I2C
+        select SND_SOC_SN95031 if INTEL_SCU_IPC
         select SND_SOC_SPDIF
-        select SND_SOC_SSM2602 if I2C
+        select SND_SOC_SSM2602 if SND_SOC_I2C_AND_SPI
         select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
         select SND_SOC_TLV320AIC23 if I2C
         select SND_SOC_TLV320AIC26 if SPI_MASTER
+        select SND_SOC_TVL320AIC32X4 if I2C
         select SND_SOC_TLV320AIC3X if I2C
         select SND_SOC_TPA6130A2 if I2C
         select SND_SOC_TLV320DAC33 if I2C
@@ -40,6 +53,8 @@ config SND_SOC_ALL_CODECS
         select SND_SOC_TWL6040 if TWL4030_CORE
         select SND_SOC_UDA134X
         select SND_SOC_UDA1380 if I2C
+        select SND_SOC_WL1273 if MFD_WL1273_CORE
+        select SND_SOC_WM1250_EV1 if I2C
         select SND_SOC_WM2000 if I2C
         select SND_SOC_WM8350 if MFD_WM8350
         select SND_SOC_WM8400 if MFD_WM8400
@@ -50,24 +65,32 @@ config SND_SOC_ALL_CODECS
         select SND_SOC_WM8727
         select SND_SOC_WM8728 if SND_SOC_I2C_AND_SPI
         select SND_SOC_WM8731 if SND_SOC_I2C_AND_SPI
+        select SND_SOC_WM8737 if SND_SOC_I2C_AND_SPI
         select SND_SOC_WM8741 if SND_SOC_I2C_AND_SPI
         select SND_SOC_WM8750 if SND_SOC_I2C_AND_SPI
         select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI
+        select SND_SOC_WM8770 if SPI_MASTER
         select SND_SOC_WM8776 if SND_SOC_I2C_AND_SPI
+        select SND_SOC_WM8804 if SND_SOC_I2C_AND_SPI
         select SND_SOC_WM8900 if I2C
         select SND_SOC_WM8903 if I2C
         select SND_SOC_WM8904 if I2C
+        select SND_SOC_WM8915 if I2C
         select SND_SOC_WM8940 if I2C
         select SND_SOC_WM8955 if I2C
         select SND_SOC_WM8960 if I2C
         select SND_SOC_WM8961 if I2C
+        select SND_SOC_WM8962 if I2C
         select SND_SOC_WM8971 if I2C
         select SND_SOC_WM8974 if I2C
         select SND_SOC_WM8978 if I2C
+        select SND_SOC_WM8985 if SND_SOC_I2C_AND_SPI
         select SND_SOC_WM8988 if SND_SOC_I2C_AND_SPI
         select SND_SOC_WM8990 if I2C
+        select SND_SOC_WM8991 if I2C
         select SND_SOC_WM8993 if I2C
         select SND_SOC_WM8994 if MFD_WM8994
+        select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI
         select SND_SOC_WM9081 if I2C
         select SND_SOC_WM9090 if I2C
         select SND_SOC_WM9705 if SND_SOC_AC97_BUS
@@ -84,6 +107,9 @@ config SND_SOC_ALL_CODECS
 
           If unsure select "N".
 
+config SND_SOC_88PM860X
+        tristate
+
 config SND_SOC_WM_HUBS
         tristate
         default y if SND_SOC_WM8993=y || SND_SOC_WM8994=y
@@ -114,12 +140,18 @@ config SND_SOC_AK4104
 config SND_SOC_AK4535
         tristate
 
+config SND_SOC_AK4641
+        tristate
+
 config SND_SOC_AK4642
         tristate
 
 config SND_SOC_AK4671
         tristate
 
+config SND_SOC_ALC5623
+       tristate
+
 config SND_SOC_CQ0093VC
         tristate
 
@@ -138,6 +170,9 @@ config SND_SOC_CS4270_VD33_ERRATA
         bool
         depends on SND_SOC_CS4270
 
+config SND_SOC_CS4271
+        tristate
+
 config SND_SOC_CX20442
         tristate
 
@@ -150,9 +185,31 @@ config SND_SOC_L3
 config SND_SOC_DA7210
         tristate
 
+config SND_SOC_DFBMCS320
+        tristate
+
+config SND_SOC_DMIC
+        tristate
+
+config SND_SOC_MAX98088
+       tristate
+
+config SND_SOC_MAX98095
+       tristate
+
+config SND_SOC_MAX9850
+        tristate
+
 config SND_SOC_PCM3008
        tristate
 
+#Freescale sgtl5000 codec
+config SND_SOC_SGTL5000
+        tristate
+
+config SND_SOC_SN95031
+        tristate
+
 config SND_SOC_SPDIF
         tristate
 
@@ -169,6 +226,9 @@ config SND_SOC_TLV320AIC26
         tristate "TI TLV320AIC26 Codec support" if SND_SOC_OF_SIMPLE
         depends on SPI
 
+config SND_SOC_TVL320AIC32X4
+        tristate
+
 config SND_SOC_TLV320AIC3X
         tristate
 
@@ -188,6 +248,12 @@ config SND_SOC_UDA134X
 config SND_SOC_UDA1380
         tristate
 
+config SND_SOC_WL1273
+        tristate
+
+config SND_SOC_WM1250_EV1
+        tristate
+
 config SND_SOC_WM8350
         tristate
 
@@ -215,6 +281,9 @@ config SND_SOC_WM8728
 config SND_SOC_WM8731
         tristate
 
+config SND_SOC_WM8737
+        tristate
+
 config SND_SOC_WM8741
         tristate
 
@@ -224,9 +293,15 @@ config SND_SOC_WM8750
 config SND_SOC_WM8753
         tristate
 
+config SND_SOC_WM8770
+        tristate
+
 config SND_SOC_WM8776
         tristate
 
+config SND_SOC_WM8804
+        tristate
+
 config SND_SOC_WM8900
         tristate
 
@@ -236,6 +311,9 @@ config SND_SOC_WM8903
 config SND_SOC_WM8904
         tristate
 
+config SND_SOC_WM8915
+        tristate
+
 config SND_SOC_WM8940
         tristate
 
@@ -248,6 +326,9 @@ config SND_SOC_WM8960
 config SND_SOC_WM8961
         tristate
 
+config SND_SOC_WM8962
+        tristate
+
 config SND_SOC_WM8971
         tristate
 
@@ -257,18 +338,27 @@ config SND_SOC_WM8974
 config SND_SOC_WM8978
         tristate
 
+config SND_SOC_WM8985
+        tristate
+
 config SND_SOC_WM8988
         tristate
 
 config SND_SOC_WM8990
         tristate
 
+config SND_SOC_WM8991
+        tristate
+
 config SND_SOC_WM8993
         tristate
 
 config SND_SOC_WM8994
         tristate
 
+config SND_SOC_WM8995
+        tristate
+
 config SND_SOC_WM9081
         tristate
 
@@ -282,6 +372,9 @@ config SND_SOC_WM9713
         tristate
 
 # Amp
+config SND_SOC_LM4857
+        tristate
+
 config SND_SOC_MAX9877
         tristate
 
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 53524095759c..fd8558406ef0 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -1,3 +1,4 @@
+snd-soc-88pm860x-objs := 88pm860x-codec.o
 snd-soc-ac97-objs := ac97.o
 snd-soc-ad1836-objs := ad1836.o
 snd-soc-ad193x-objs := ad193x.o
@@ -6,26 +7,39 @@ snd-soc-ad73311-objs := ad73311.o
 snd-soc-ads117x-objs := ads117x.o
 snd-soc-ak4104-objs := ak4104.o
 snd-soc-ak4535-objs := ak4535.o
+snd-soc-ak4641-objs := ak4641.o
 snd-soc-ak4642-objs := ak4642.o
 snd-soc-ak4671-objs := ak4671.o
 snd-soc-cq93vc-objs := cq93vc.o
 snd-soc-cs42l51-objs := cs42l51.o
 snd-soc-cs4270-objs := cs4270.o
+snd-soc-cs4271-objs := cs4271.o
 snd-soc-cx20442-objs := cx20442.o
 snd-soc-da7210-objs := da7210.o
+snd-soc-dfbmcs320-objs := dfbmcs320.o
+snd-soc-dmic-objs := dmic.o
 snd-soc-l3-objs := l3.o
+snd-soc-max98088-objs := max98088.o
+snd-soc-max98095-objs := max98095.o
+snd-soc-max9850-objs := max9850.o
 snd-soc-pcm3008-objs := pcm3008.o
+snd-soc-sgtl5000-objs := sgtl5000.o
+snd-soc-alc5623-objs := alc5623.o
+snd-soc-sn95031-objs := sn95031.o
 snd-soc-spdif-objs := spdif_transciever.o
 snd-soc-ssm2602-objs := ssm2602.o
 snd-soc-stac9766-objs := stac9766.o
 snd-soc-tlv320aic23-objs := tlv320aic23.o
 snd-soc-tlv320aic26-objs := tlv320aic26.o
 snd-soc-tlv320aic3x-objs := tlv320aic3x.o
+snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o
 snd-soc-tlv320dac33-objs := tlv320dac33.o
 snd-soc-twl4030-objs := twl4030.o
 snd-soc-twl6040-objs := twl6040.o
 snd-soc-uda134x-objs := uda134x.o
 snd-soc-uda1380-objs := uda1380.o
+snd-soc-wl1273-objs := wl1273.o
+snd-soc-wm1250-ev1-objs := wm1250-ev1.o
 snd-soc-wm8350-objs := wm8350.o
 snd-soc-wm8400-objs := wm8400.o
 snd-soc-wm8510-objs := wm8510.o
@@ -35,24 +49,32 @@ snd-soc-wm8711-objs := wm8711.o
 snd-soc-wm8727-objs := wm8727.o
 snd-soc-wm8728-objs := wm8728.o
 snd-soc-wm8731-objs := wm8731.o
+snd-soc-wm8737-objs := wm8737.o
 snd-soc-wm8741-objs := wm8741.o
 snd-soc-wm8750-objs := wm8750.o
 snd-soc-wm8753-objs := wm8753.o
+snd-soc-wm8770-objs := wm8770.o
 snd-soc-wm8776-objs := wm8776.o
+snd-soc-wm8804-objs := wm8804.o
 snd-soc-wm8900-objs := wm8900.o
 snd-soc-wm8903-objs := wm8903.o
 snd-soc-wm8904-objs := wm8904.o
+snd-soc-wm8915-objs := wm8915.o
 snd-soc-wm8940-objs := wm8940.o
 snd-soc-wm8955-objs := wm8955.o
 snd-soc-wm8960-objs := wm8960.o
 snd-soc-wm8961-objs := wm8961.o
+snd-soc-wm8962-objs := wm8962.o
 snd-soc-wm8971-objs := wm8971.o
 snd-soc-wm8974-objs := wm8974.o
 snd-soc-wm8978-objs := wm8978.o
+snd-soc-wm8985-objs := wm8985.o
 snd-soc-wm8988-objs := wm8988.o
 snd-soc-wm8990-objs := wm8990.o
+snd-soc-wm8991-objs := wm8991.o
 snd-soc-wm8993-objs := wm8993.o
-snd-soc-wm8994-objs := wm8994.o
+snd-soc-wm8994-objs := wm8994.o wm8994-tables.o wm8958-dsp2.o
+snd-soc-wm8995-objs := wm8995.o
 snd-soc-wm9081-objs := wm9081.o
 snd-soc-wm9705-objs := wm9705.o
 snd-soc-wm9712-objs := wm9712.o
@@ -61,11 +83,13 @@ snd-soc-wm-hubs-objs := wm_hubs.o
 snd-soc-jz4740-codec-objs := jz4740.o
 
 # Amp
+snd-soc-lm4857-objs := lm4857.o
 snd-soc-max9877-objs := max9877.o
 snd-soc-tpa6130a2-objs := tpa6130a2.o
 snd-soc-wm2000-objs := wm2000.o
 snd-soc-wm9090-objs := wm9090.o
 
+obj-$(CONFIG_SND_SOC_88PM860X)  += snd-soc-88pm860x.o
 obj-$(CONFIG_SND_SOC_AC97_CODEC)        += snd-soc-ac97.o
 obj-$(CONFIG_SND_SOC_AD1836)    += snd-soc-ad1836.o
 obj-$(CONFIG_SND_SOC_AD193X)    += snd-soc-ad193x.o
@@ -74,27 +98,40 @@ obj-$(CONFIG_SND_SOC_AD73311) += snd-soc-ad73311.o
 obj-$(CONFIG_SND_SOC_ADS117X)   += snd-soc-ads117x.o
 obj-$(CONFIG_SND_SOC_AK4104)    += snd-soc-ak4104.o
 obj-$(CONFIG_SND_SOC_AK4535)    += snd-soc-ak4535.o
+obj-$(CONFIG_SND_SOC_AK4641)    += snd-soc-ak4641.o
 obj-$(CONFIG_SND_SOC_AK4642)    += snd-soc-ak4642.o
 obj-$(CONFIG_SND_SOC_AK4671)    += snd-soc-ak4671.o
+obj-$(CONFIG_SND_SOC_ALC5623)    += snd-soc-alc5623.o
 obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
 obj-$(CONFIG_SND_SOC_CS42L51)   += snd-soc-cs42l51.o
 obj-$(CONFIG_SND_SOC_CS4270)    += snd-soc-cs4270.o
+obj-$(CONFIG_SND_SOC_CS4271)    += snd-soc-cs4271.o
 obj-$(CONFIG_SND_SOC_CX20442)   += snd-soc-cx20442.o
 obj-$(CONFIG_SND_SOC_DA7210)    += snd-soc-da7210.o
+obj-$(CONFIG_SND_SOC_DFBMCS320) += snd-soc-dfbmcs320.o
+obj-$(CONFIG_SND_SOC_DMIC)      += snd-soc-dmic.o
 obj-$(CONFIG_SND_SOC_L3)        += snd-soc-l3.o
 obj-$(CONFIG_SND_SOC_JZ4740_CODEC)      += snd-soc-jz4740-codec.o
+obj-$(CONFIG_SND_SOC_MAX98088)  += snd-soc-max98088.o
+obj-$(CONFIG_SND_SOC_MAX98095)  += snd-soc-max98095.o
+obj-$(CONFIG_SND_SOC_MAX9850)   += snd-soc-max9850.o
 obj-$(CONFIG_SND_SOC_PCM3008)   += snd-soc-pcm3008.o
+obj-$(CONFIG_SND_SOC_SGTL5000)  += snd-soc-sgtl5000.o
+obj-$(CONFIG_SND_SOC_SN95031)   +=snd-soc-sn95031.o
 obj-$(CONFIG_SND_SOC_SPDIF)     += snd-soc-spdif.o
 obj-$(CONFIG_SND_SOC_SSM2602)   += snd-soc-ssm2602.o
 obj-$(CONFIG_SND_SOC_STAC9766)  += snd-soc-stac9766.o
 obj-$(CONFIG_SND_SOC_TLV320AIC23)       += snd-soc-tlv320aic23.o
 obj-$(CONFIG_SND_SOC_TLV320AIC26)       += snd-soc-tlv320aic26.o
 obj-$(CONFIG_SND_SOC_TLV320AIC3X)       += snd-soc-tlv320aic3x.o
+obj-$(CONFIG_SND_SOC_TVL320AIC32X4)     += snd-soc-tlv320aic32x4.o
 obj-$(CONFIG_SND_SOC_TLV320DAC33)       += snd-soc-tlv320dac33.o
 obj-$(CONFIG_SND_SOC_TWL4030)   += snd-soc-twl4030.o
 obj-$(CONFIG_SND_SOC_TWL6040)   += snd-soc-twl6040.o
 obj-$(CONFIG_SND_SOC_UDA134X)   += snd-soc-uda134x.o
 obj-$(CONFIG_SND_SOC_UDA1380)   += snd-soc-uda1380.o
+obj-$(CONFIG_SND_SOC_WL1273)    += snd-soc-wl1273.o
+obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o
 obj-$(CONFIG_SND_SOC_WM8350)    += snd-soc-wm8350.o
 obj-$(CONFIG_SND_SOC_WM8400)    += snd-soc-wm8400.o
 obj-$(CONFIG_SND_SOC_WM8510)    += snd-soc-wm8510.o
@@ -104,24 +141,32 @@ obj-$(CONFIG_SND_SOC_WM8711)	+= snd-soc-wm8711.o
 obj-$(CONFIG_SND_SOC_WM8727)    += snd-soc-wm8727.o
 obj-$(CONFIG_SND_SOC_WM8728)    += snd-soc-wm8728.o
 obj-$(CONFIG_SND_SOC_WM8731)    += snd-soc-wm8731.o
+obj-$(CONFIG_SND_SOC_WM8737)    += snd-soc-wm8737.o
 obj-$(CONFIG_SND_SOC_WM8741)    += snd-soc-wm8741.o
 obj-$(CONFIG_SND_SOC_WM8750)    += snd-soc-wm8750.o
 obj-$(CONFIG_SND_SOC_WM8753)    += snd-soc-wm8753.o
+obj-$(CONFIG_SND_SOC_WM8770)    += snd-soc-wm8770.o
 obj-$(CONFIG_SND_SOC_WM8776)    += snd-soc-wm8776.o
+obj-$(CONFIG_SND_SOC_WM8804)    += snd-soc-wm8804.o
 obj-$(CONFIG_SND_SOC_WM8900)    += snd-soc-wm8900.o
 obj-$(CONFIG_SND_SOC_WM8903)    += snd-soc-wm8903.o
 obj-$(CONFIG_SND_SOC_WM8904)    += snd-soc-wm8904.o
+obj-$(CONFIG_SND_SOC_WM8915)    += snd-soc-wm8915.o
 obj-$(CONFIG_SND_SOC_WM8940)    += snd-soc-wm8940.o
 obj-$(CONFIG_SND_SOC_WM8955)    += snd-soc-wm8955.o
 obj-$(CONFIG_SND_SOC_WM8960)    += snd-soc-wm8960.o
 obj-$(CONFIG_SND_SOC_WM8961)    += snd-soc-wm8961.o
+obj-$(CONFIG_SND_SOC_WM8962)    += snd-soc-wm8962.o
 obj-$(CONFIG_SND_SOC_WM8971)    += snd-soc-wm8971.o
 obj-$(CONFIG_SND_SOC_WM8974)    += snd-soc-wm8974.o
 obj-$(CONFIG_SND_SOC_WM8978)    += snd-soc-wm8978.o
+obj-$(CONFIG_SND_SOC_WM8985)    += snd-soc-wm8985.o
 obj-$(CONFIG_SND_SOC_WM8988)    += snd-soc-wm8988.o
 obj-$(CONFIG_SND_SOC_WM8990)    += snd-soc-wm8990.o
+obj-$(CONFIG_SND_SOC_WM8991)    += snd-soc-wm8991.o
 obj-$(CONFIG_SND_SOC_WM8993)    += snd-soc-wm8993.o
 obj-$(CONFIG_SND_SOC_WM8994)    += snd-soc-wm8994.o
+obj-$(CONFIG_SND_SOC_WM8995)    += snd-soc-wm8995.o
 obj-$(CONFIG_SND_SOC_WM9081)    += snd-soc-wm9081.o
 obj-$(CONFIG_SND_SOC_WM9705)    += snd-soc-wm9705.o
 obj-$(CONFIG_SND_SOC_WM9712)    += snd-soc-wm9712.o
@@ -129,6 +174,7 @@ obj-$(CONFIG_SND_SOC_WM9713)	+= snd-soc-wm9713.o
 obj-$(CONFIG_SND_SOC_WM_HUBS)   += snd-soc-wm-hubs.o
 
 # Amp
+obj-$(CONFIG_SND_SOC_LM4857)    += snd-soc-lm4857.o
 obj-$(CONFIG_SND_SOC_MAX9877)   += snd-soc-max9877.o
 obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o
 obj-$(CONFIG_SND_SOC_WM2000)    += snd-soc-wm2000.o
diff --git a/sound/soc/codecs/ac97.c b/sound/soc/codecs/ac97.c
index 1f5e57a4bb7a..3c087936aa57 100644
--- a/sound/soc/codecs/ac97.c
+++ b/sound/soc/codecs/ac97.c
@@ -21,17 +21,13 @@
 #include <sound/ac97_codec.h>
 #include <sound/initval.h>
 #include <sound/soc.h>
-#include "ac97.h"
-
-#define AC97_VERSION "0.6"
 
 static int ac97_prepare(struct snd_pcm_substream *substream,
                         struct snd_soc_dai *dai)
 {
         struct snd_pcm_runtime *runtime = substream->runtime;
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
 
         int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
                   AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
@@ -46,8 +42,8 @@ static struct snd_soc_dai_ops ac97_dai_ops = {
         .prepare        = ac97_prepare,
 };
 
-struct snd_soc_dai ac97_dai = {
-        .name = "AC97 HiFi",
+static struct snd_soc_dai_driver ac97_dai = {
+        .name = "ac97-hifi",
         .ac97_control = 1,
         .playback = {
                 .stream_name = "AC97 Playback",
@@ -63,7 +59,6 @@ struct snd_soc_dai ac97_dai = {
                 .formats = SND_SOC_STD_AC97_FMTS,},
         .ops = &ac97_dai_ops,
 };
-EXPORT_SYMBOL_GPL(ac97_dai);
 
 static unsigned int ac97_read(struct snd_soc_codec *codec,
         unsigned int reg)
@@ -78,95 +73,41 @@ static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
         return 0;
 }
 
-static int ac97_soc_probe(struct platform_device *pdev)
+static int ac97_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_card *card = socdev->card;
-        struct snd_soc_codec *codec;
         struct snd_ac97_bus *ac97_bus;
         struct snd_ac97_template ac97_template;
-        int i;
-        int ret = 0;
-
-        printk(KERN_INFO "AC97 SoC Audio Codec %s\n", AC97_VERSION);
-
-        socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (!socdev->card->codec)
-                return -ENOMEM;
-        codec = socdev->card->codec;
-        mutex_init(&codec->mutex);
-
-        codec->name = "AC97";
-        codec->owner = THIS_MODULE;
-        codec->dai = &ac97_dai;
-        codec->num_dai = 1;
-        codec->write = ac97_write;
-        codec->read = ac97_read;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0)
-                goto err;
+        int ret;
 
         /* add codec as bus device for standard ac97 */
-        ret = snd_ac97_bus(codec->card, 0, &soc_ac97_ops, NULL, &ac97_bus);
+        ret = snd_ac97_bus(codec->card->snd_card, 0, &soc_ac97_ops, NULL, &ac97_bus);
         if (ret < 0)
-                goto bus_err;
+                return ret;
 
         memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
         ret = snd_ac97_mixer(ac97_bus, &ac97_template, &codec->ac97);
         if (ret < 0)
-                goto bus_err;
-
-        for (i = 0; i < card->num_links; i++) {
-                if (card->dai_link[i].codec_dai->ac97_control) {
-                        snd_ac97_dev_add_pdata(codec->ac97,
-                                card->dai_link[i].cpu_dai->ac97_pdata);
-                }
-        }
+                return ret;
 
         return 0;
-
-bus_err:
-        snd_soc_free_pcms(socdev);
-
-err:
-        kfree(socdev->card->codec);
-        socdev->card->codec = NULL;
-        return ret;
 }
 
-static int ac97_soc_remove(struct platform_device *pdev)
+static int ac97_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (!codec)
-                return 0;
-
-        snd_soc_free_pcms(socdev);
-        kfree(socdev->card->codec);
-
         return 0;
 }
 
 #ifdef CONFIG_PM
-static int ac97_soc_suspend(struct platform_device *pdev, pm_message_t msg)
+static int ac97_soc_suspend(struct snd_soc_codec *codec, pm_message_t msg)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_ac97_suspend(socdev->card->codec->ac97);
+        snd_ac97_suspend(codec->ac97);
 
         return 0;
 }
 
-static int ac97_soc_resume(struct platform_device *pdev)
+static int ac97_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_ac97_resume(socdev->card->codec->ac97);
+        snd_ac97_resume(codec->ac97);
 
         return 0;
 }
@@ -175,14 +116,50 @@ static int ac97_soc_resume(struct platform_device *pdev)
 #define ac97_soc_resume NULL
 #endif
 
-struct snd_soc_codec_device soc_codec_dev_ac97 = {
+static struct snd_soc_codec_driver soc_codec_dev_ac97 = {
+        .write =        ac97_write,
+        .read =         ac97_read,
         .probe =        ac97_soc_probe,
         .remove =       ac97_soc_remove,
         .suspend =      ac97_soc_suspend,
         .resume =       ac97_soc_resume,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_ac97);
+
+static __devinit int ac97_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_ac97, &ac97_dai, 1);
+}
+
+static int __devexit ac97_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver ac97_codec_driver = {
+        .driver = {
+                .name = "ac97-codec",
+                .owner = THIS_MODULE,
+        },
+
+        .probe = ac97_probe,
+        .remove = __devexit_p(ac97_remove),
+};
+
+static int __init ac97_init(void)
+{
+        return platform_driver_register(&ac97_codec_driver);
+}
+module_init(ac97_init);
+
+static void __exit ac97_exit(void)
+{
+        platform_driver_unregister(&ac97_codec_driver);
+}
+module_exit(ac97_exit);
 
 MODULE_DESCRIPTION("Soc Generic AC97 driver");
 MODULE_AUTHOR("Liam Girdwood");
 MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ac97-codec");
diff --git a/sound/soc/codecs/ac97.h b/sound/soc/codecs/ac97.h
deleted file mode 100644
index 281aa42e2bbb..000000000000
--- a/sound/soc/codecs/ac97.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * linux/sound/codecs/ac97.h -- ALSA SoC Layer
- *
- * Author:              Liam Girdwood
- * Created:             Dec 1st 2005
- * Copyright:   Wolfson Microelectronics. PLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __LINUX_SND_SOC_AC97_H
-#define __LINUX_SND_SOC_AC97_H
-
-extern struct snd_soc_codec_device soc_codec_dev_ac97;
-extern struct snd_soc_dai ac97_dai;
-
-#endif
diff --git a/sound/soc/codecs/ad1836.c b/sound/soc/codecs/ad1836.c
index a01006c8c606..754c496412bd 100644
--- a/sound/soc/codecs/ad1836.c
+++ b/sound/soc/codecs/ad1836.c
@@ -27,21 +27,15 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 #include <sound/tlv.h>
-#include <sound/soc-dapm.h>
 #include <linux/spi/spi.h>
 #include "ad1836.h"
 
 /* codec private data */
 struct ad1836_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[AD1836_NUM_REGS];
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
-static struct snd_soc_codec *ad1836_codec;
-struct snd_soc_codec_device soc_codec_dev_ad1836;
-static int ad1836_register(struct ad1836_priv *ad1836);
-static void ad1836_unregister(struct ad1836_priv *ad1836);
-
 /*
  * AD1836 volume/mute/de-emphasis etc. controls
  */
@@ -146,39 +140,35 @@ static int ad1836_hw_params(struct snd_pcm_substream *substream,
         int word_len = 0;
 
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
 
         /* bit size */
         switch (params_format(params)) {
         case SNDRV_PCM_FORMAT_S16_LE:
-                word_len = 3;
+                word_len = AD1836_WORD_LEN_16;
                 break;
         case SNDRV_PCM_FORMAT_S20_3LE:
-                word_len = 1;
+                word_len = AD1836_WORD_LEN_20;
                 break;
         case SNDRV_PCM_FORMAT_S24_LE:
         case SNDRV_PCM_FORMAT_S32_LE:
-                word_len = 0;
+                word_len = AD1836_WORD_LEN_24;
                 break;
         }
 
-        snd_soc_update_bits(codec, AD1836_DAC_CTRL1,
-                AD1836_DAC_WORD_LEN_MASK, word_len);
+        snd_soc_update_bits(codec, AD1836_DAC_CTRL1, AD1836_DAC_WORD_LEN_MASK,
+                word_len << AD1836_DAC_WORD_LEN_OFFSET);
 
-        snd_soc_update_bits(codec, AD1836_ADC_CTRL2,
-                AD1836_ADC_WORD_LEN_MASK, word_len);
+        snd_soc_update_bits(codec, AD1836_ADC_CTRL2, AD1836_ADC_WORD_LEN_MASK,
+                word_len << AD1836_ADC_WORD_OFFSET);
 
         return 0;
 }
 
 #ifdef CONFIG_PM
-static int ad1836_soc_suspend(struct platform_device *pdev,
+static int ad1836_soc_suspend(struct snd_soc_codec *codec,
                 pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         /* reset clock control mode */
         u16 adc_ctrl2 = snd_soc_read(codec, AD1836_ADC_CTRL2);
         adc_ctrl2 &= ~AD1836_ADC_SERFMT_MASK;
@@ -186,11 +176,8 @@ static int ad1836_soc_suspend(struct platform_device *pdev,
         return snd_soc_write(codec, AD1836_ADC_CTRL2, adc_ctrl2);
 }
 
-static int ad1836_soc_resume(struct platform_device *pdev)
+static int ad1836_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         /* restore clock control mode */
         u16 adc_ctrl2 = snd_soc_read(codec, AD1836_ADC_CTRL2);
         adc_ctrl2 |= AD1836_ADC_AUX;
@@ -202,49 +189,14 @@ static int ad1836_soc_resume(struct platform_device *pdev)
 #define ad1836_soc_resume  NULL
 #endif
 
-static int __devinit ad1836_spi_probe(struct spi_device *spi)
-{
-        struct snd_soc_codec *codec;
-        struct ad1836_priv *ad1836;
-
-        ad1836 = kzalloc(sizeof(struct ad1836_priv), GFP_KERNEL);
-        if (ad1836 == NULL)
-                return -ENOMEM;
-
-        codec = &ad1836->codec;
-        codec->control_data = spi;
-        codec->dev = &spi->dev;
-
-        dev_set_drvdata(&spi->dev, ad1836);
-
-        return ad1836_register(ad1836);
-}
-
-static int __devexit ad1836_spi_remove(struct spi_device *spi)
-{
-        struct ad1836_priv *ad1836 = dev_get_drvdata(&spi->dev);
-
-        ad1836_unregister(ad1836);
-        return 0;
-}
-
-static struct spi_driver ad1836_spi_driver = {
-        .driver = {
-                .name   = "ad1836",
-                .owner  = THIS_MODULE,
-        },
-        .probe          = ad1836_spi_probe,
-        .remove         = __devexit_p(ad1836_spi_remove),
-};
-
 static struct snd_soc_dai_ops ad1836_dai_ops = {
         .hw_params = ad1836_hw_params,
         .set_fmt = ad1836_set_dai_fmt,
 };
 
 /* codec DAI instance */
-struct snd_soc_dai ad1836_dai = {
-        .name = "AD1836",
+static struct snd_soc_dai_driver ad1836_dai = {
+        .name = "ad1836-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -263,40 +215,18 @@ struct snd_soc_dai ad1836_dai = {
         },
         .ops = &ad1836_dai_ops,
 };
-EXPORT_SYMBOL_GPL(ad1836_dai);
 
-static int ad1836_register(struct ad1836_priv *ad1836)
+static int ad1836_probe(struct snd_soc_codec *codec)
 {
-        int ret;
-        struct snd_soc_codec *codec = &ad1836->codec;
-
-        if (ad1836_codec) {
-                dev_err(codec->dev, "Another ad1836 is registered\n");
-                kfree(ad1836);
-                return -EINVAL;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-        snd_soc_codec_set_drvdata(codec, ad1836);
-        codec->reg_cache = ad1836->reg_cache;
-        codec->reg_cache_size = AD1836_NUM_REGS;
-        codec->name = "AD1836";
-        codec->owner = THIS_MODULE;
-        codec->dai = &ad1836_dai;
-        codec->num_dai = 1;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        ad1836_dai.dev = codec->dev;
-        ad1836_codec = codec;
+        struct ad1836_priv *ad1836 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret = 0;
 
+        codec->control_data = ad1836->control_data;
         ret = snd_soc_codec_set_cache_io(codec, 4, 12, SND_SOC_SPI);
         if (ret < 0) {
                 dev_err(codec->dev, "failed to set cache I/O: %d\n",
                                 ret);
-                kfree(ad1836);
                 return ret;
         }
 
@@ -319,81 +249,69 @@ static int ad1836_register(struct ad1836_priv *ad1836)
         snd_soc_write(codec, AD1836_DAC_L3_VOL, 0x3FF);
         snd_soc_write(codec, AD1836_DAC_R3_VOL, 0x3FF);
 
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                kfree(ad1836);
-                return ret;
-        }
-
-        ret = snd_soc_register_dai(&ad1836_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                snd_soc_unregister_codec(codec);
-                kfree(ad1836);
-                return ret;
-        }
+        snd_soc_add_controls(codec, ad1836_snd_controls,
+                             ARRAY_SIZE(ad1836_snd_controls));
+        snd_soc_dapm_new_controls(dapm, ad1836_dapm_widgets,
+                                  ARRAY_SIZE(ad1836_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
 
-        return 0;
+        return ret;
 }
 
-static void ad1836_unregister(struct ad1836_priv *ad1836)
+/* power down chip */
+static int ad1836_remove(struct snd_soc_codec *codec)
 {
-        snd_soc_unregister_dai(&ad1836_dai);
-        snd_soc_unregister_codec(&ad1836->codec);
-        kfree(ad1836);
-        ad1836_codec = NULL;
-}
+        /* reset clock control mode */
+        u16 adc_ctrl2 = snd_soc_read(codec, AD1836_ADC_CTRL2);
+        adc_ctrl2 &= ~AD1836_ADC_SERFMT_MASK;
 
-static int ad1836_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
+        return snd_soc_write(codec, AD1836_ADC_CTRL2, adc_ctrl2);
+}
 
-        if (ad1836_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
+static struct snd_soc_codec_driver soc_codec_dev_ad1836 = {
+        .probe =        ad1836_probe,
+        .remove =       ad1836_remove,
+        .suspend =      ad1836_soc_suspend,
+        .resume =       ad1836_soc_resume,
+        .reg_cache_size = AD1836_NUM_REGS,
+        .reg_word_size = sizeof(u16),
+};
 
-        socdev->card->codec = ad1836_codec;
-        codec = ad1836_codec;
+static int __devinit ad1836_spi_probe(struct spi_device *spi)
+{
+        struct ad1836_priv *ad1836;
+        int ret;
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
+        ad1836 = kzalloc(sizeof(struct ad1836_priv), GFP_KERNEL);
+        if (ad1836 == NULL)
+                return -ENOMEM;
 
-        snd_soc_add_controls(codec, ad1836_snd_controls,
-                             ARRAY_SIZE(ad1836_snd_controls));
-        snd_soc_dapm_new_controls(codec, ad1836_dapm_widgets,
-                                  ARRAY_SIZE(ad1836_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
+        spi_set_drvdata(spi, ad1836);
+        ad1836->control_data = spi;
+        ad1836->control_type = SND_SOC_SPI;
 
-pcm_err:
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_ad1836, &ad1836_dai, 1);
+        if (ret < 0)
+                kfree(ad1836);
         return ret;
 }
 
-/* power down chip */
-static int ad1836_remove(struct platform_device *pdev)
+static int __devexit ad1836_spi_remove(struct spi_device *spi)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_ad1836 = {
-        .probe =        ad1836_probe,
-        .remove =       ad1836_remove,
-        .suspend =      ad1836_soc_suspend,
-        .resume =       ad1836_soc_resume,
+static struct spi_driver ad1836_spi_driver = {
+        .driver = {
+                .name   = "ad1836-codec",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = ad1836_spi_probe,
+        .remove         = __devexit_p(ad1836_spi_remove),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_ad1836);
 
 static int __init ad1836_init(void)
 {
diff --git a/sound/soc/codecs/ad1836.h b/sound/soc/codecs/ad1836.h
index e9d90d3951c5..9d6a3f8f8aaf 100644
--- a/sound/soc/codecs/ad1836.h
+++ b/sound/soc/codecs/ad1836.h
@@ -25,6 +25,7 @@
 #define AD1836_DAC_SERFMT_PCK256       (0x4 << 5)
 #define AD1836_DAC_SERFMT_PCK128       (0x5 << 5)
 #define AD1836_DAC_WORD_LEN_MASK       0x18
+#define AD1836_DAC_WORD_LEN_OFFSET     3
 
 #define AD1836_DAC_CTRL2               1
 #define AD1836_DACL1_MUTE              0
@@ -51,6 +52,7 @@
 #define AD1836_ADCL2_MUTE               2
 #define AD1836_ADCR2_MUTE               3
 #define AD1836_ADC_WORD_LEN_MASK       0x30
+#define AD1836_ADC_WORD_OFFSET         5
 #define AD1836_ADC_SERFMT_MASK         (7 << 6)
 #define AD1836_ADC_SERFMT_PCK256       (0x4 << 6)
 #define AD1836_ADC_SERFMT_PCK128       (0x5 << 6)
@@ -60,6 +62,8 @@
 
 #define AD1836_NUM_REGS                16
 
-extern struct snd_soc_dai ad1836_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ad1836;
+#define AD1836_WORD_LEN_24 0x0
+#define AD1836_WORD_LEN_20 0x1
+#define AD1836_WORD_LEN_16 0x2
+
 #endif
diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c
index 1def75e4862f..2374ca5ffe68 100644
--- a/sound/soc/codecs/ad193x.c
+++ b/sound/soc/codecs/ad193x.c
@@ -19,14 +19,12 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 #include <sound/tlv.h>
-#include <sound/soc-dapm.h>
 #include "ad193x.h"
 
 /* codec private data */
 struct ad193x_priv {
-        unsigned int sysclk;
-        struct snd_soc_codec codec;
-        u8 reg_cache[AD193X_NUM_REGS];
+        enum snd_soc_control_type control_type;
+        int sysclk;
 };
 
 /* ad193x register cache & default register settings */
@@ -34,9 +32,6 @@ static const u8 ad193x_reg[AD193X_NUM_REGS] = {
         0, 0, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0, 0, 0,
 };
 
-static struct snd_soc_codec *ad193x_codec;
-struct snd_soc_codec_device soc_codec_dev_ad193x;
-
 /*
  * AD193X volume/mute/de-emphasis etc. controls
  */
@@ -275,8 +270,7 @@ static int ad193x_hw_params(struct snd_pcm_substream *substream,
         int word_len = 0, reg = 0, master_rate = 0;
 
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct ad193x_priv *ad193x = snd_soc_codec_get_drvdata(codec);
 
         /* bit size */
@@ -323,100 +317,6 @@ static int ad193x_hw_params(struct snd_pcm_substream *substream,
         return 0;
 }
 
-static int ad193x_bus_probe(struct device *dev, void *ctrl_data, int bus_type)
-{
-        struct snd_soc_codec *codec;
-        struct ad193x_priv *ad193x;
-        int ret;
-
-        if (ad193x_codec) {
-                dev_err(dev, "Another ad193x is registered\n");
-                return -EINVAL;
-        }
-
-        ad193x = kzalloc(sizeof(struct ad193x_priv), GFP_KERNEL);
-        if (ad193x == NULL)
-                return -ENOMEM;
-
-        dev_set_drvdata(dev, ad193x);
-
-        codec = &ad193x->codec;
-        mutex_init(&codec->mutex);
-        codec->control_data = ctrl_data;
-        codec->dev = dev;
-        snd_soc_codec_set_drvdata(codec, ad193x);
-        codec->reg_cache = ad193x->reg_cache;
-        codec->reg_cache_size = AD193X_NUM_REGS;
-        codec->name = "AD193X";
-        codec->owner = THIS_MODULE;
-        codec->dai = &ad193x_dai;
-        codec->num_dai = 1;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        ad193x_dai.dev = codec->dev;
-        ad193x_codec = codec;
-
-        memcpy(codec->reg_cache, ad193x_reg, AD193X_NUM_REGS);
-
-        if (bus_type == SND_SOC_I2C)
-                ret = snd_soc_codec_set_cache_io(codec, 8, 8, bus_type);
-        else
-                ret = snd_soc_codec_set_cache_io(codec, 16, 8, bus_type);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to set cache I/O: %d\n",
-                                ret);
-                kfree(ad193x);
-                return ret;
-        }
-
-        /* default setting for ad193x */
-
-        /* unmute dac channels */
-        snd_soc_write(codec, AD193X_DAC_CHNL_MUTE, 0x0);
-        /* de-emphasis: 48kHz, powedown dac */
-        snd_soc_write(codec, AD193X_DAC_CTRL2, 0x1A);
-        /* powerdown dac, dac in tdm mode */
-        snd_soc_write(codec, AD193X_DAC_CTRL0, 0x41);
-        /* high-pass filter enable */
-        snd_soc_write(codec, AD193X_ADC_CTRL0, 0x3);
-        /* sata delay=1, adc aux mode */
-        snd_soc_write(codec, AD193X_ADC_CTRL1, 0x43);
-        /* pll input: mclki/xi */
-        snd_soc_write(codec, AD193X_PLL_CLK_CTRL0, 0x99); /* mclk=24.576Mhz: 0x9D; mclk=12.288Mhz: 0x99 */
-        snd_soc_write(codec, AD193X_PLL_CLK_CTRL1, 0x04);
-        ad193x->sysclk = 12288000;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                kfree(ad193x);
-                return ret;
-        }
-
-        ret = snd_soc_register_dai(&ad193x_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                snd_soc_unregister_codec(codec);
-                kfree(ad193x);
-                return ret;
-        }
-
-        return 0;
-}
-
-static int ad193x_bus_remove(struct device *dev)
-{
-        struct ad193x_priv *ad193x = dev_get_drvdata(dev);
-
-        snd_soc_unregister_dai(&ad193x_dai);
-        snd_soc_unregister_codec(&ad193x->codec);
-        kfree(ad193x);
-        ad193x_codec = NULL;
-
-        return 0;
-}
-
 static struct snd_soc_dai_ops ad193x_dai_ops = {
         .hw_params = ad193x_hw_params,
         .digital_mute = ad193x_mute,
@@ -426,8 +326,8 @@ static struct snd_soc_dai_ops ad193x_dai_ops = {
 };
 
 /* codec DAI instance */
-struct snd_soc_dai ad193x_dai = {
-        .name = "AD193X",
+static struct snd_soc_dai_driver ad193x_dai = {
+        .name = "ad193x-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -446,65 +346,79 @@ struct snd_soc_dai ad193x_dai = {
         },
         .ops = &ad193x_dai_ops,
 };
-EXPORT_SYMBOL_GPL(ad193x_dai);
 
-static int ad193x_probe(struct platform_device *pdev)
+static int ad193x_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
+        struct ad193x_priv *ad193x = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret;
 
-        if (ad193x_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
+        if (ad193x->control_type == SND_SOC_I2C)
+                ret = snd_soc_codec_set_cache_io(codec, 8, 8, ad193x->control_type);
+        else
+                ret = snd_soc_codec_set_cache_io(codec, 16, 8, ad193x->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
-        socdev->card->codec = ad193x_codec;
-        codec = ad193x_codec;
+        /* default setting for ad193x */
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
+        /* unmute dac channels */
+        snd_soc_write(codec, AD193X_DAC_CHNL_MUTE, 0x0);
+        /* de-emphasis: 48kHz, powedown dac */
+        snd_soc_write(codec, AD193X_DAC_CTRL2, 0x1A);
+        /* powerdown dac, dac in tdm mode */
+        snd_soc_write(codec, AD193X_DAC_CTRL0, 0x41);
+        /* high-pass filter enable */
+        snd_soc_write(codec, AD193X_ADC_CTRL0, 0x3);
+        /* sata delay=1, adc aux mode */
+        snd_soc_write(codec, AD193X_ADC_CTRL1, 0x43);
+        /* pll input: mclki/xi */
+        snd_soc_write(codec, AD193X_PLL_CLK_CTRL0, 0x99); /* mclk=24.576Mhz: 0x9D; mclk=12.288Mhz: 0x99 */
+        snd_soc_write(codec, AD193X_PLL_CLK_CTRL1, 0x04);
 
         snd_soc_add_controls(codec, ad193x_snd_controls,
                              ARRAY_SIZE(ad193x_snd_controls));
-        snd_soc_dapm_new_controls(codec, ad193x_dapm_widgets,
+        snd_soc_dapm_new_controls(dapm, ad193x_dapm_widgets,
                                   ARRAY_SIZE(ad193x_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
+        snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
 
-pcm_err:
         return ret;
 }
 
-/* power down chip */
-static int ad193x_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_ad193x = {
+static struct snd_soc_codec_driver soc_codec_dev_ad193x = {
         .probe =        ad193x_probe,
-        .remove =       ad193x_remove,
+        .reg_cache_default = ad193x_reg,
+        .reg_cache_size = AD193X_NUM_REGS,
+        .reg_word_size = sizeof(u16),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_ad193x);
 
 #if defined(CONFIG_SPI_MASTER)
 static int __devinit ad193x_spi_probe(struct spi_device *spi)
 {
-        return ad193x_bus_probe(&spi->dev, spi, SND_SOC_SPI);
+        struct ad193x_priv *ad193x;
+        int ret;
+
+        ad193x = kzalloc(sizeof(struct ad193x_priv), GFP_KERNEL);
+        if (ad193x == NULL)
+                return -ENOMEM;
+
+        spi_set_drvdata(spi, ad193x);
+        ad193x->control_type = SND_SOC_SPI;
+
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_ad193x, &ad193x_dai, 1);
+        if (ret < 0)
+                kfree(ad193x);
+        return ret;
 }
 
 static int __devexit ad193x_spi_remove(struct spi_device *spi)
 {
-        return ad193x_bus_remove(&spi->dev);
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
 }
 
 static struct spi_driver ad193x_spi_driver = {
@@ -528,12 +442,28 @@ MODULE_DEVICE_TABLE(i2c, ad193x_id);
 static int __devinit ad193x_i2c_probe(struct i2c_client *client,
                 const struct i2c_device_id *id)
 {
-        return ad193x_bus_probe(&client->dev, client, SND_SOC_I2C);
+        struct ad193x_priv *ad193x;
+        int ret;
+
+        ad193x = kzalloc(sizeof(struct ad193x_priv), GFP_KERNEL);
+        if (ad193x == NULL)
+                return -ENOMEM;
+
+        i2c_set_clientdata(client, ad193x);
+        ad193x->control_type = SND_SOC_I2C;
+
+        ret =  snd_soc_register_codec(&client->dev,
+                        &soc_codec_dev_ad193x, &ad193x_dai, 1);
+        if (ret < 0)
+                kfree(ad193x);
+        return ret;
 }
 
 static int __devexit ad193x_i2c_remove(struct i2c_client *client)
 {
-        return ad193x_bus_remove(&client->dev);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
 }
 
 static struct i2c_driver ad193x_i2c_driver = {
diff --git a/sound/soc/codecs/ad193x.h b/sound/soc/codecs/ad193x.h
index 654ba64ae04c..9747b5497877 100644
--- a/sound/soc/codecs/ad193x.h
+++ b/sound/soc/codecs/ad193x.h
@@ -80,7 +80,4 @@
 
 #define AD193X_NUM_REGS          17
 
-extern struct snd_soc_dai ad193x_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ad193x;
-
 #endif
diff --git a/sound/soc/codecs/ad1980.c b/sound/soc/codecs/ad1980.c
index 70cfaec3be2c..923b364a3e41 100644
--- a/sound/soc/codecs/ad1980.c
+++ b/sound/soc/codecs/ad1980.c
@@ -29,15 +29,9 @@
 #include <sound/ac97_codec.h>
 #include <sound/initval.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 
 #include "ad1980.h"
 
-static unsigned int ac97_read(struct snd_soc_codec *codec,
-        unsigned int reg);
-static int ac97_write(struct snd_soc_codec *codec,
-        unsigned int reg, unsigned int val);
-
 /*
  * AD1980 register cache
  */
@@ -138,8 +132,8 @@ static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
         return 0;
 }
 
-struct snd_soc_dai ad1980_dai = {
-        .name = "AC97",
+static struct snd_soc_dai_driver ad1980_dai = {
+        .name = "ad1980-hifi",
         .ac97_control = 1,
         .playback = {
                 .stream_name = "Playback",
@@ -185,53 +179,20 @@ err:
         return -EIO;
 }
 
-static int ad1980_soc_probe(struct platform_device *pdev)
+static int ad1980_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
+        int ret;
         u16 vendor_id2;
         u16 ext_status;
 
         printk(KERN_INFO "AD1980 SoC Audio Codec\n");
 
-        socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (socdev->card->codec == NULL)
-                return -ENOMEM;
-        codec = socdev->card->codec;
-        mutex_init(&codec->mutex);
-
-        codec->reg_cache =
-                kzalloc(sizeof(u16) * ARRAY_SIZE(ad1980_reg), GFP_KERNEL);
-        if (codec->reg_cache == NULL) {
-                ret = -ENOMEM;
-                goto cache_err;
-        }
-        memcpy(codec->reg_cache, ad1980_reg, sizeof(u16) * \
-                        ARRAY_SIZE(ad1980_reg));
-        codec->reg_cache_size = sizeof(u16) * ARRAY_SIZE(ad1980_reg);
-        codec->reg_cache_step = 2;
-        codec->name = "AD1980";
-        codec->owner = THIS_MODULE;
-        codec->dai = &ad1980_dai;
-        codec->num_dai = 1;
-        codec->write = ac97_write;
-        codec->read = ac97_read;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
         ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
         if (ret < 0) {
                 printk(KERN_ERR "ad1980: failed to register AC97 codec\n");
-                goto codec_err;
+                return ret;
         }
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0)
-                goto pcm_err;
-
-
         ret = ad1980_reset(codec, 0);
         if (ret < 0) {
                 printk(KERN_ERR "Failed to reset AD1980: AC97 link error\n");
@@ -270,41 +231,60 @@ static int ad1980_soc_probe(struct platform_device *pdev)
         return 0;
 
 reset_err:
-        snd_soc_free_pcms(socdev);
-
-pcm_err:
         snd_soc_free_ac97_codec(codec);
-
-codec_err:
-        kfree(codec->reg_cache);
-
-cache_err:
-        kfree(socdev->card->codec);
-        socdev->card->codec = NULL;
         return ret;
 }
 
-static int ad1980_soc_remove(struct platform_device *pdev)
+static int ad1980_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec == NULL)
-                return 0;
-
-        snd_soc_dapm_free(socdev);
-        snd_soc_free_pcms(socdev);
         snd_soc_free_ac97_codec(codec);
-        kfree(codec->reg_cache);
-        kfree(codec);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_ad1980 = {
+static struct snd_soc_codec_driver soc_codec_dev_ad1980 = {
         .probe =        ad1980_soc_probe,
         .remove =       ad1980_soc_remove,
+        .reg_cache_size = ARRAY_SIZE(ad1980_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = ad1980_reg,
+        .reg_cache_step = 2,
+        .write = ac97_write,
+        .read = ac97_read,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_ad1980);
+
+static __devinit int ad1980_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_ad1980, &ad1980_dai, 1);
+}
+
+static int __devexit ad1980_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver ad1980_codec_driver = {
+        .driver = {
+                        .name = "ad1980",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = ad1980_probe,
+        .remove = __devexit_p(ad1980_remove),
+};
+
+static int __init ad1980_init(void)
+{
+        return platform_driver_register(&ad1980_codec_driver);
+}
+module_init(ad1980_init);
+
+static void __exit ad1980_exit(void)
+{
+        platform_driver_unregister(&ad1980_codec_driver);
+}
+module_exit(ad1980_exit);
 
 MODULE_DESCRIPTION("ASoC ad1980 driver (Obsolete)");
 MODULE_AUTHOR("Roy Huang, Cliff Cai");
diff --git a/sound/soc/codecs/ad1980.h b/sound/soc/codecs/ad1980.h
index 538f37c90806..eb0af44ad3df 100644
--- a/sound/soc/codecs/ad1980.h
+++ b/sound/soc/codecs/ad1980.h
@@ -23,7 +23,4 @@
 #define PR5             0x2000
 #define PR6             0x4000
 
-extern struct snd_soc_dai ad1980_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ad1980;
-
 #endif
diff --git a/sound/soc/codecs/ad73311.c b/sound/soc/codecs/ad73311.c
index 475807bea2c2..8d793e993e9a 100644
--- a/sound/soc/codecs/ad73311.c
+++ b/sound/soc/codecs/ad73311.c
@@ -23,8 +23,8 @@
 
 #include "ad73311.h"
 
-struct snd_soc_dai ad73311_dai = {
-        .name = "AD73311",
+static struct snd_soc_dai_driver ad73311_dai = {
+        .name = "ad73311-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -38,68 +38,40 @@ struct snd_soc_dai ad73311_dai = {
                 .rates = SNDRV_PCM_RATE_8000,
                 .formats = SNDRV_PCM_FMTBIT_S16_LE, },
 };
-EXPORT_SYMBOL_GPL(ad73311_dai);
 
-static int ad73311_soc_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-        mutex_init(&codec->mutex);
-        codec->name = "AD73311";
-        codec->owner = THIS_MODULE;
-        codec->dai = &ad73311_dai;
-        codec->num_dai = 1;
-        socdev->card->codec = codec;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "ad73311: failed to create pcms\n");
-                goto pcm_err;
-        }
-
-        return ret;
+static struct snd_soc_codec_driver soc_codec_dev_ad73311;
 
-pcm_err:
-        kfree(socdev->card->codec);
-        socdev->card->codec = NULL;
-        return ret;
+static int ad73311_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_ad73311, &ad73311_dai, 1);
 }
 
-static int ad73311_soc_remove(struct platform_device *pdev)
+static int __devexit ad73311_remove(struct platform_device *pdev)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec == NULL)
-                return 0;
-        snd_soc_free_pcms(socdev);
-        kfree(codec);
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_ad73311 = {
-        .probe =        ad73311_soc_probe,
-        .remove =       ad73311_soc_remove,
+static struct platform_driver ad73311_codec_driver = {
+        .driver = {
+                        .name = "ad73311",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = ad73311_probe,
+        .remove = __devexit_p(ad73311_remove),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_ad73311);
 
 static int __init ad73311_init(void)
 {
-        return snd_soc_register_dai(&ad73311_dai);
+        return platform_driver_register(&ad73311_codec_driver);
 }
 module_init(ad73311_init);
 
 static void __exit ad73311_exit(void)
 {
-        snd_soc_unregister_dai(&ad73311_dai);
+        platform_driver_unregister(&ad73311_codec_driver);
 }
 module_exit(ad73311_exit);
 
diff --git a/sound/soc/codecs/ad73311.h b/sound/soc/codecs/ad73311.h
index 569573d2d4d7..4b353eefc0bf 100644
--- a/sound/soc/codecs/ad73311.h
+++ b/sound/soc/codecs/ad73311.h
@@ -85,6 +85,4 @@
 #define REGF_INV                (1 << 6)
 #define REGF_ALB                (1 << 7)
 
-extern struct snd_soc_dai ad73311_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ad73311;
 #endif
diff --git a/sound/soc/codecs/ads117x.c b/sound/soc/codecs/ads117x.c
index f8e75edb27b7..8402854ec15e 100644
--- a/sound/soc/codecs/ads117x.c
+++ b/sound/soc/codecs/ads117x.c
@@ -19,16 +19,12 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include "ads117x.h"
-
 #define ADS117X_RATES (SNDRV_PCM_RATE_8000_48000)
-
 #define ADS117X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
 
-struct snd_soc_dai ads117x_dai = {
+static struct snd_soc_dai_driver ads117x_dai = {
 /* ADC */
-        .name = "ADS117X ADC",
-        .id = 1,
+        .name = "ads117x-hifi",
         .capture = {
                 .stream_name = "Capture",
                 .channels_min = 1,
@@ -36,75 +32,29 @@ struct snd_soc_dai ads117x_dai = {
                 .rates = ADS117X_RATES,
                 .formats = ADS117X_FORMATS,},
 };
-EXPORT_SYMBOL_GPL(ads117x_dai);
-
-static int ads117x_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret;
-
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
 
-        socdev->card->codec = codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-        codec->name = "ADS117X";
-        codec->owner = THIS_MODULE;
-        codec->dai = &ads117x_dai;
-        codec->num_dai = 1;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "ads117x: failed to create pcms\n");
-                kfree(codec);
-                return ret;
-        }
-
-        return 0;
-}
-
-static int ads117x_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        snd_soc_free_pcms(socdev);
-        kfree(codec);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_ads117x = {
-        .probe =        ads117x_probe,
-        .remove =       ads117x_remove,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_ads117x);
+static struct snd_soc_codec_driver soc_codec_dev_ads117x;
 
-static __devinit int ads117x_platform_probe(struct platform_device *pdev)
+static __devinit int ads117x_probe(struct platform_device *pdev)
 {
-        ads117x_dai.dev = &pdev->dev;
-        return snd_soc_register_dai(&ads117x_dai);
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_ads117x, &ads117x_dai, 1);
 }
 
-static int __devexit ads117x_platform_remove(struct platform_device *pdev)
+static int __devexit ads117x_remove(struct platform_device *pdev)
 {
-        snd_soc_unregister_dai(&ads117x_dai);
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
 static struct platform_driver ads117x_codec_driver = {
         .driver = {
-                        .name = "ads117x",
+                        .name = "ads117x-codec",
                         .owner = THIS_MODULE,
         },
 
-        .probe = ads117x_platform_probe,
-        .remove = __devexit_p(ads117x_platform_remove),
+        .probe = ads117x_probe,
+        .remove = __devexit_p(ads117x_remove),
 };
 
 static int __init ads117x_init(void)
diff --git a/sound/soc/codecs/ads117x.h b/sound/soc/codecs/ads117x.h
index dbcf50ec9bd1..3ce028614002 100644
--- a/sound/soc/codecs/ads117x.h
+++ b/sound/soc/codecs/ads117x.h
@@ -9,5 +9,5 @@
  *  Free Software Foundation;  either version 2 of the  License, or (at your
  *  option) any later version.
  */
-extern struct snd_soc_dai ads117x_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ads117x;
+extern struct snd_soc_dai_driver ads117x_dai;
+extern struct snd_soc_codec_driver soc_codec_dev_ads117x;
diff --git a/sound/soc/codecs/ak4104.c b/sound/soc/codecs/ak4104.c
index 192aebda3029..cbf0b6d400b8 100644
--- a/sound/soc/codecs/ak4104.c
+++ b/sound/soc/codecs/ak4104.c
@@ -17,8 +17,6 @@
 #include <linux/spi/spi.h>
 #include <sound/asoundef.h>
 
-#include "ak4104.h"
-
 /* AK4104 registers addresses */
 #define AK4104_REG_CONTROL1             0x00
 #define AK4104_REG_RESERVED             0x01
@@ -45,11 +43,11 @@
 #define AK4104_TX_TXE                   (1 << 0)
 #define AK4104_TX_V                     (1 << 1)
 
-#define DRV_NAME "ak4104"
+#define DRV_NAME "ak4104-codec"
 
 struct ak4104_private {
-        struct snd_soc_codec codec;
-        u8 reg_cache[AK4104_NUM_REGS];
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
 static int ak4104_fill_cache(struct snd_soc_codec *codec)
@@ -58,7 +56,7 @@ static int ak4104_fill_cache(struct snd_soc_codec *codec)
         u8 *reg_cache = codec->reg_cache;
         struct spi_device *spi = codec->control_data;
 
-        for (i = 0; i < codec->reg_cache_size; i++) {
+        for (i = 0; i < codec->driver->reg_cache_size; i++) {
                 int ret = spi_w8r8(spi, i | AK4104_READ);
                 if (ret < 0) {
                         dev_err(&spi->dev, "SPI write failure\n");
@@ -76,7 +74,7 @@ static unsigned int ak4104_read_reg_cache(struct snd_soc_codec *codec,
 {
         u8 *reg_cache = codec->reg_cache;
 
-        if (reg >= codec->reg_cache_size)
+        if (reg >= codec->driver->reg_cache_size)
                 return -EINVAL;
 
         return reg_cache[reg];
@@ -88,7 +86,7 @@ static int ak4104_spi_write(struct snd_soc_codec *codec, unsigned int reg,
         u8 *cache = codec->reg_cache;
         struct spi_device *spi = codec->control_data;
 
-        if (reg >= codec->reg_cache_size)
+        if (reg >= codec->driver->reg_cache_size)
                 return -EINVAL;
 
         /* only write to the hardware if value has changed */
@@ -145,8 +143,7 @@ static int ak4104_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         int val = 0;
 
         /* set the IEC958 bits: consumer mode, no copyright bit */
@@ -178,8 +175,8 @@ static struct snd_soc_dai_ops ak4101_dai_ops = {
         .set_fmt = ak4104_set_dai_fmt,
 };
 
-struct snd_soc_dai ak4104_dai = {
-        .name = DRV_NAME,
+static struct snd_soc_dai_driver ak4104_dai = {
+        .name = "ak4104-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -192,45 +189,17 @@ struct snd_soc_dai ak4104_dai = {
         .ops = &ak4101_dai_ops,
 };
 
-static struct snd_soc_codec *ak4104_codec;
-
-static int ak4104_spi_probe(struct spi_device *spi)
+static int ak4104_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec;
-        struct ak4104_private *ak4104;
+        struct ak4104_private *ak4104 = snd_soc_codec_get_drvdata(codec);
         int ret, val;
 
-        spi->bits_per_word = 8;
-        spi->mode = SPI_MODE_0;
-        ret = spi_setup(spi);
-        if (ret < 0)
-                return ret;
-
-        ak4104 = kzalloc(sizeof(struct ak4104_private), GFP_KERNEL);
-        if (!ak4104) {
-                dev_err(&spi->dev, "could not allocate codec\n");
-                return -ENOMEM;
-        }
-
-        codec = &ak4104->codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->dev = &spi->dev;
-        codec->name = DRV_NAME;
-        codec->owner = THIS_MODULE;
-        codec->dai = &ak4104_dai;
-        codec->num_dai = 1;
-        snd_soc_codec_set_drvdata(codec, ak4104);
-        codec->control_data = spi;
-        codec->reg_cache = ak4104->reg_cache;
-        codec->reg_cache_size = AK4104_NUM_REGS;
+        codec->control_data = ak4104->control_data;
 
         /* read all regs and fill the cache */
         ret = ak4104_fill_cache(codec);
         if (ret < 0) {
-                dev_err(&spi->dev, "failed to fill register cache\n");
+                dev_err(codec->dev, "failed to fill register cache\n");
                 return ret;
         }
 
@@ -238,93 +207,81 @@ static int ak4104_spi_probe(struct spi_device *spi)
          * should contain 0x5b. Not a good way to verify the presence of
          * the device, but there is no hardware ID register. */
         if (ak4104_read_reg_cache(codec, AK4104_REG_RESERVED) !=
-                                         AK4104_RESERVED_VAL) {
-                ret = -ENODEV;
-                goto error_free_codec;
-        }
+                                         AK4104_RESERVED_VAL)
+                return -ENODEV;
 
         /* set power-up and non-reset bits */
         val = ak4104_read_reg_cache(codec, AK4104_REG_CONTROL1);
         val |= AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN;
         ret = ak4104_spi_write(codec, AK4104_REG_CONTROL1, val);
         if (ret < 0)
-                goto error_free_codec;
+                return ret;
 
         /* enable transmitter */
         val = ak4104_read_reg_cache(codec, AK4104_REG_TX);
         val |= AK4104_TX_TXE;
         ret = ak4104_spi_write(codec, AK4104_REG_TX, val);
         if (ret < 0)
-                goto error_free_codec;
-
-        ak4104_codec = codec;
-        ret = snd_soc_register_dai(&ak4104_dai);
-        if (ret < 0) {
-                dev_err(&spi->dev, "failed to register DAI\n");
-                goto error_free_codec;
-        }
+                return ret;
 
-        spi_set_drvdata(spi, ak4104);
-        dev_info(&spi->dev, "SPI device initialized\n");
+        dev_info(codec->dev, "SPI device initialized\n");
         return 0;
-
-error_free_codec:
-        kfree(ak4104);
-        ak4104_dai.dev = NULL;
-        return ret;
 }
 
-static int __devexit ak4104_spi_remove(struct spi_device *spi)
+static int ak4104_remove(struct snd_soc_codec *codec)
 {
-        int ret, val;
-        struct ak4104_private *ak4104 = spi_get_drvdata(spi);
+        int val, ret;
 
-        val = ak4104_read_reg_cache(&ak4104->codec, AK4104_REG_CONTROL1);
+        val = ak4104_read_reg_cache(codec, AK4104_REG_CONTROL1);
         if (val < 0)
                 return val;
 
         /* clear power-up and non-reset bits */
         val &= ~(AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN);
-        ret = ak4104_spi_write(&ak4104->codec, AK4104_REG_CONTROL1, val);
-        if (ret < 0)
-                return ret;
+        ret = ak4104_spi_write(codec, AK4104_REG_CONTROL1, val);
 
-        ak4104_codec = NULL;
-        kfree(ak4104);
-        return 0;
+        return ret;
 }
 
-static int ak4104_probe(struct platform_device *pdev)
+static struct snd_soc_codec_driver soc_codec_device_ak4104 = {
+        .probe =        ak4104_probe,
+        .remove =       ak4104_remove,
+        .reg_cache_size = AK4104_NUM_REGS,
+        .reg_word_size = sizeof(u16),
+};
+
+static int ak4104_spi_probe(struct spi_device *spi)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = ak4104_codec;
+        struct ak4104_private *ak4104;
         int ret;
 
-        /* Connect the codec to the socdev.  snd_soc_new_pcms() needs this. */
-        socdev->card->codec = codec;
-
-        /* Register PCMs */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms\n");
+        spi->bits_per_word = 8;
+        spi->mode = SPI_MODE_0;
+        ret = spi_setup(spi);
+        if (ret < 0)
                 return ret;
-        }
 
-        return 0;
+        ak4104 = kzalloc(sizeof(struct ak4104_private), GFP_KERNEL);
+        if (ak4104 == NULL)
+                return -ENOMEM;
+
+        ak4104->control_data = spi;
+        ak4104->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, ak4104);
+
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_device_ak4104, &ak4104_dai, 1);
+        if (ret < 0)
+                kfree(ak4104);
+        return ret;
 }
 
-static int ak4104_remove(struct platform_device *pdev)
+static int __devexit ak4104_spi_remove(struct spi_device *spi)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        snd_soc_free_pcms(socdev);
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
-};
-
-struct snd_soc_codec_device soc_codec_device_ak4104 = {
-        .probe =        ak4104_probe,
-        .remove =       ak4104_remove
-};
-EXPORT_SYMBOL_GPL(soc_codec_device_ak4104);
+}
 
 static struct spi_driver ak4104_spi_driver = {
         .driver  = {
@@ -337,7 +294,6 @@ static struct spi_driver ak4104_spi_driver = {
 
 static int __init ak4104_init(void)
 {
-        pr_info("Asahi Kasei AK4104 ALSA SoC Codec Driver\n");
         return spi_register_driver(&ak4104_spi_driver);
 }
 module_init(ak4104_init);
diff --git a/sound/soc/codecs/ak4104.h b/sound/soc/codecs/ak4104.h
deleted file mode 100644
index eb88fe7e4def..000000000000
--- a/sound/soc/codecs/ak4104.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _AK4104_H
-#define _AK4104_H
-
-extern struct snd_soc_dai ak4104_dai;
-extern struct snd_soc_codec_device soc_codec_device_ak4104;
-
-#endif
diff --git a/sound/soc/codecs/ak4535.c b/sound/soc/codecs/ak4535.c
index d4253675b2d3..e1a214ee757f 100644
--- a/sound/soc/codecs/ak4535.c
+++ b/sound/soc/codecs/ak4535.c
@@ -24,18 +24,17 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 
 #include "ak4535.h"
 
 #define AK4535_VERSION "0.3"
 
-struct snd_soc_codec_device soc_codec_dev_ak4535;
-
 /* codec private data */
 struct ak4535_priv {
         unsigned int sysclk;
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
 /*
@@ -231,7 +230,7 @@ static const struct snd_soc_dapm_widget ak4535_dapm_widgets[] = {
         SND_SOC_DAPM_INPUT("AIN"),
 };
 
-static const struct snd_soc_dapm_route audio_map[] = {
+static const struct snd_soc_dapm_route ak4535_audio_map[] = {
         /*stereo mixer */
         {"Stereo Mixer", "Playback Switch", "DAC"},
         {"Stereo Mixer", "Mic Sidetone Switch", "Mic"},
@@ -288,16 +287,6 @@ static const struct snd_soc_dapm_route audio_map[] = {
         {"Input Mixer", "Aux Capture Switch", "Aux In"},
 };
 
-static int ak4535_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, ak4535_dapm_widgets,
-                                  ARRAY_SIZE(ak4535_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
-
-        return 0;
-}
-
 static int ak4535_set_dai_sysclk(struct snd_soc_dai *codec_dai,
         int clk_id, unsigned int freq, int dir)
 {
@@ -313,8 +302,7 @@ static int ak4535_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct ak4535_priv *ak4535 = snd_soc_codec_get_drvdata(codec);
         u8 mode2 = ak4535_read_reg_cache(codec, AK4535_MODE2) & ~(0x3 << 5);
         int rate = params_rate(params), fs = 256;
@@ -367,9 +355,9 @@ static int ak4535_set_dai_fmt(struct snd_soc_dai *codec_dai,
 static int ak4535_mute(struct snd_soc_dai *dai, int mute)
 {
         struct snd_soc_codec *codec = dai->codec;
-        u16 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC) & 0xffdf;
+        u16 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC);
         if (!mute)
-                ak4535_write(codec, AK4535_DAC, mute_reg);
+                ak4535_write(codec, AK4535_DAC, mute_reg & ~0x20);
         else
                 ak4535_write(codec, AK4535_DAC, mute_reg | 0x20);
         return 0;
@@ -378,14 +366,16 @@ static int ak4535_mute(struct snd_soc_dai *dai, int mute)
 static int ak4535_set_bias_level(struct snd_soc_codec *codec,
         enum snd_soc_bias_level level)
 {
-        u16 i;
+        u16 i, mute_reg;
 
         switch (level) {
         case SND_SOC_BIAS_ON:
-                ak4535_mute(codec->dai, 0);
+                mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC);
+                ak4535_write(codec, AK4535_DAC, mute_reg & ~0x20);
                 break;
         case SND_SOC_BIAS_PREPARE:
-                ak4535_mute(codec->dai, 1);
+                mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC);
+                ak4535_write(codec, AK4535_DAC, mute_reg | 0x20);
                 break;
         case SND_SOC_BIAS_STANDBY:
                 i = ak4535_read_reg_cache(codec, AK4535_PM1);
@@ -398,7 +388,7 @@ static int ak4535_set_bias_level(struct snd_soc_codec *codec,
                 ak4535_write(codec, AK4535_PM1, i & (~0x80));
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -413,8 +403,8 @@ static struct snd_soc_dai_ops ak4535_dai_ops = {
         .set_sysclk     = ak4535_set_dai_sysclk,
 };
 
-struct snd_soc_dai ak4535_dai = {
-        .name = "AK4535",
+static struct snd_soc_dai_driver ak4535_dai = {
+        .name = "ak4535-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -429,95 +419,86 @@ struct snd_soc_dai ak4535_dai = {
                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
         .ops = &ak4535_dai_ops,
 };
-EXPORT_SYMBOL_GPL(ak4535_dai);
 
-static int ak4535_suspend(struct platform_device *pdev, pm_message_t state)
+static int ak4535_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         ak4535_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int ak4535_resume(struct platform_device *pdev)
+static int ak4535_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         ak4535_sync(codec);
         ak4535_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         return 0;
 }
 
-/*
- * initialise the AK4535 driver
- * register the mixer and dsp interfaces with the kernel
- */
-static int ak4535_init(struct snd_soc_device *socdev)
+static int ak4535_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int ret = 0;
+        struct ak4535_priv *ak4535 = snd_soc_codec_get_drvdata(codec);
 
-        codec->name = "AK4535";
-        codec->owner = THIS_MODULE;
-        codec->read = ak4535_read_reg_cache;
-        codec->write = ak4535_write;
-        codec->set_bias_level = ak4535_set_bias_level;
-        codec->dai = &ak4535_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(ak4535_reg);
-        codec->reg_cache = kmemdup(ak4535_reg, sizeof(ak4535_reg), GFP_KERNEL);
-
-        if (codec->reg_cache == NULL)
-                return -ENOMEM;
+        printk(KERN_INFO "AK4535 Audio Codec %s", AK4535_VERSION);
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "ak4535: failed to create pcms\n");
-                goto pcm_err;
-        }
+        codec->control_data = ak4535->control_data;
 
         /* power on device */
         ak4535_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         snd_soc_add_controls(codec, ak4535_snd_controls,
                                 ARRAY_SIZE(ak4535_snd_controls));
-        ak4535_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        kfree(codec->reg_cache);
+        return 0;
+}
 
-        return ret;
+/* power down chip */
+static int ak4535_remove(struct snd_soc_codec *codec)
+{
+        ak4535_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
-static struct snd_soc_device *ak4535_socdev;
+static struct snd_soc_codec_driver soc_codec_dev_ak4535 = {
+        .probe =        ak4535_probe,
+        .remove =       ak4535_remove,
+        .suspend =      ak4535_suspend,
+        .resume =       ak4535_resume,
+        .read = ak4535_read_reg_cache,
+        .write = ak4535_write,
+        .set_bias_level = ak4535_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(ak4535_reg),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = ak4535_reg,
+        .dapm_widgets = ak4535_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(ak4535_dapm_widgets),
+        .dapm_routes = ak4535_audio_map,
+        .num_dapm_routes = ARRAY_SIZE(ak4535_audio_map),
+};
 
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-
-static int ak4535_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+static __devinit int ak4535_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
-        struct snd_soc_device *socdev = ak4535_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct ak4535_priv *ak4535;
         int ret;
 
-        i2c_set_clientdata(i2c, codec);
-        codec->control_data = i2c;
+        ak4535 = kzalloc(sizeof(struct ak4535_priv), GFP_KERNEL);
+        if (ak4535 == NULL)
+                return -ENOMEM;
 
-        ret = ak4535_init(socdev);
-        if (ret < 0)
-                printk(KERN_ERR "failed to initialise AK4535\n");
+        i2c_set_clientdata(i2c, ak4535);
+        ak4535->control_data = i2c;
+        ak4535->control_type = SND_SOC_I2C;
 
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_ak4535, &ak4535_dai, 1);
+        if (ret < 0)
+                kfree(ak4535);
         return ret;
 }
 
-static int ak4535_i2c_remove(struct i2c_client *client)
+static __devexit int ak4535_i2c_remove(struct i2c_client *client)
 {
-        struct snd_soc_codec *codec = i2c_get_clientdata(client);
-        kfree(codec->reg_cache);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -529,138 +510,34 @@ MODULE_DEVICE_TABLE(i2c, ak4535_i2c_id);
 
 static struct i2c_driver ak4535_i2c_driver = {
         .driver = {
-                .name = "AK4535 I2C Codec",
+                .name = "ak4535-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    ak4535_i2c_probe,
-        .remove =   ak4535_i2c_remove,
+        .remove =   __devexit_p(ak4535_i2c_remove),
         .id_table = ak4535_i2c_id,
 };
-
-static int ak4535_add_i2c_device(struct platform_device *pdev,
-                                 const struct ak4535_setup_data *setup)
-{
-        struct i2c_board_info info;
-        struct i2c_adapter *adapter;
-        struct i2c_client *client;
-        int ret;
-
-        ret = i2c_add_driver(&ak4535_i2c_driver);
-        if (ret != 0) {
-                dev_err(&pdev->dev, "can't add i2c driver\n");
-                return ret;
-        }
-
-        memset(&info, 0, sizeof(struct i2c_board_info));
-        info.addr = setup->i2c_address;
-        strlcpy(info.type, "ak4535", I2C_NAME_SIZE);
-
-        adapter = i2c_get_adapter(setup->i2c_bus);
-        if (!adapter) {
-                dev_err(&pdev->dev, "can't get i2c adapter %d\n",
-                        setup->i2c_bus);
-                goto err_driver;
-        }
-
-        client = i2c_new_device(adapter, &info);
-        i2c_put_adapter(adapter);
-        if (!client) {
-                dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
-                        (unsigned int)info.addr);
-                goto err_driver;
-        }
-
-        return 0;
-
-err_driver:
-        i2c_del_driver(&ak4535_i2c_driver);
-        return -ENODEV;
-}
 #endif
 
-static int ak4535_probe(struct platform_device *pdev)
+static int __init ak4535_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct ak4535_setup_data *setup;
-        struct snd_soc_codec *codec;
-        struct ak4535_priv *ak4535;
-        int ret;
-
-        printk(KERN_INFO "AK4535 Audio Codec %s", AK4535_VERSION);
-
-        setup = socdev->codec_data;
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-
-        ak4535 = kzalloc(sizeof(struct ak4535_priv), GFP_KERNEL);
-        if (ak4535 == NULL) {
-                kfree(codec);
-                return -ENOMEM;
-        }
-
-        snd_soc_codec_set_drvdata(codec, ak4535);
-        socdev->card->codec = codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        ak4535_socdev = socdev;
-        ret = -ENODEV;
-
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        if (setup->i2c_address) {
-                codec->hw_write = (hw_write_t)i2c_master_send;
-                ret = ak4535_add_i2c_device(pdev, setup);
-        }
-#endif
-
+        ret = i2c_add_driver(&ak4535_i2c_driver);
         if (ret != 0) {
-                kfree(snd_soc_codec_get_drvdata(codec));
-                kfree(codec);
+                printk(KERN_ERR "Failed to register AK4535 I2C driver: %d\n",
+                       ret);
         }
+#endif
         return ret;
 }
+module_init(ak4535_modinit);
 
-/* power down chip */
-static int ak4535_remove(struct platform_device *pdev)
+static void __exit ak4535_exit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec->control_data)
-                ak4535_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        if (codec->control_data)
-                i2c_unregister_device(codec->control_data);
         i2c_del_driver(&ak4535_i2c_driver);
 #endif
-        kfree(snd_soc_codec_get_drvdata(codec));
-        kfree(codec);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_ak4535 = {
-        .probe =        ak4535_probe,
-        .remove =       ak4535_remove,
-        .suspend =      ak4535_suspend,
-        .resume =       ak4535_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_ak4535);
-
-static int __init ak4535_modinit(void)
-{
-        return snd_soc_register_dai(&ak4535_dai);
-}
-module_init(ak4535_modinit);
-
-static void __exit ak4535_exit(void)
-{
-        snd_soc_unregister_dai(&ak4535_dai);
 }
 module_exit(ak4535_exit);
 
diff --git a/sound/soc/codecs/ak4535.h b/sound/soc/codecs/ak4535.h
index c7a58703ea39..0431e5f634a2 100644
--- a/sound/soc/codecs/ak4535.h
+++ b/sound/soc/codecs/ak4535.h
@@ -36,12 +36,4 @@
 
 #define AK4535_CACHEREGNUM      0x10
 
-struct ak4535_setup_data {
-        int            i2c_bus;
-        unsigned short i2c_address;
-};
-
-extern struct snd_soc_dai ak4535_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ak4535;
-
 #endif
diff --git a/sound/soc/codecs/ak4641.c b/sound/soc/codecs/ak4641.c
new file mode 100644
index 000000000000..ed96f247c2da
--- /dev/null
+++ b/sound/soc/codecs/ak4641.c
@@ -0,0 +1,664 @@
+/*
+ * ak4641.c  --  AK4641 ALSA Soc Audio driver
+ *
+ * Copyright (C) 2008 Harald Welte <laforge@gnufiish.org>
+ * Copyright (C) 2011 Dmitry Artamonow <mad_soft@inbox.ru>
+ *
+ * Based on ak4535.c by Richard Purdie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <sound/ak4641.h>
+
+#include "ak4641.h"
+
+/* codec private data */
+struct ak4641_priv {
+        struct snd_soc_codec *codec;
+        unsigned int sysclk;
+        int deemph;
+        int playback_fs;
+};
+
+/*
+ * ak4641 register cache
+ */
+static const u8 ak4641_reg[AK4641_CACHEREGNUM] = {
+        0x00, 0x80, 0x00, 0x80,
+        0x02, 0x00, 0x11, 0x05,
+        0x00, 0x00, 0x36, 0x10,
+        0x00, 0x00, 0x57, 0x00,
+        0x88, 0x88, 0x08, 0x08
+};
+
+static const int deemph_settings[] = {44100, 0, 48000, 32000};
+
+static int ak4641_set_deemph(struct snd_soc_codec *codec)
+{
+        struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
+        int i, best = 0;
+
+        for (i = 0 ; i < ARRAY_SIZE(deemph_settings); i++) {
+                /* if deemphasis is on, select the nearest available rate */
+                if (ak4641->deemph && deemph_settings[i] != 0 &&
+                    abs(deemph_settings[i] - ak4641->playback_fs) <
+                    abs(deemph_settings[best] - ak4641->playback_fs))
+                        best = i;
+
+                if (!ak4641->deemph && deemph_settings[i] == 0)
+                        best = i;
+        }
+
+        dev_dbg(codec->dev, "Set deemphasis %d\n", best);
+
+        return snd_soc_update_bits(codec, AK4641_DAC, 0x3, best);
+}
+
+static int ak4641_put_deemph(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
+        int deemph = ucontrol->value.enumerated.item[0];
+
+        if (deemph > 1)
+                return -EINVAL;
+
+        ak4641->deemph = deemph;
+
+        return ak4641_set_deemph(codec);
+}
+
+static int ak4641_get_deemph(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = ak4641->deemph;
+        return 0;
+};
+
+static const char *ak4641_mono_out[] = {"(L + R)/2", "Hi-Z"};
+static const char *ak4641_hp_out[] = {"Stereo", "Mono"};
+static const char *ak4641_mic_select[] = {"Internal", "External"};
+static const char *ak4641_mic_or_dac[] = {"Microphone", "Voice DAC"};
+
+
+static const DECLARE_TLV_DB_SCALE(mono_gain_tlv, -1700, 2300, 0);
+static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, 0, 2000, 0);
+static const DECLARE_TLV_DB_SCALE(eq_tlv, -1050, 150, 0);
+static const DECLARE_TLV_DB_SCALE(master_tlv, -12750, 50, 0);
+static const DECLARE_TLV_DB_SCALE(mic_stereo_sidetone_tlv, -2700, 300, 0);
+static const DECLARE_TLV_DB_SCALE(mic_mono_sidetone_tlv, -400, 400, 0);
+static const DECLARE_TLV_DB_SCALE(capture_tlv, -800, 50, 0);
+static const DECLARE_TLV_DB_SCALE(alc_tlv, -800, 50, 0);
+static const DECLARE_TLV_DB_SCALE(aux_in_tlv, -2100, 300, 0);
+
+
+static const struct soc_enum ak4641_mono_out_enum =
+        SOC_ENUM_SINGLE(AK4641_SIG1, 6, 2, ak4641_mono_out);
+static const struct soc_enum ak4641_hp_out_enum =
+        SOC_ENUM_SINGLE(AK4641_MODE2, 2, 2, ak4641_hp_out);
+static const struct soc_enum ak4641_mic_select_enum =
+        SOC_ENUM_SINGLE(AK4641_MIC, 1, 2, ak4641_mic_select);
+static const struct soc_enum ak4641_mic_or_dac_enum =
+        SOC_ENUM_SINGLE(AK4641_BTIF, 4, 2, ak4641_mic_or_dac);
+
+static const struct snd_kcontrol_new ak4641_snd_controls[] = {
+        SOC_ENUM("Mono 1 Output", ak4641_mono_out_enum),
+        SOC_SINGLE_TLV("Mono 1 Gain Volume", AK4641_SIG1, 7, 1, 1,
+                                                        mono_gain_tlv),
+        SOC_ENUM("Headphone Output", ak4641_hp_out_enum),
+        SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
+                                        ak4641_get_deemph, ak4641_put_deemph),
+
+        SOC_SINGLE_TLV("Mic Boost Volume", AK4641_MIC, 0, 1, 0, mic_boost_tlv),
+
+        SOC_SINGLE("ALC Operation Time", AK4641_TIMER, 0, 3, 0),
+        SOC_SINGLE("ALC Recovery Time", AK4641_TIMER, 2, 3, 0),
+        SOC_SINGLE("ALC ZC Time", AK4641_TIMER, 4, 3, 0),
+
+        SOC_SINGLE("ALC 1 Switch", AK4641_ALC1, 5, 1, 0),
+
+        SOC_SINGLE_TLV("ALC Volume", AK4641_ALC2, 0, 71, 0, alc_tlv),
+        SOC_SINGLE("Left Out Enable Switch", AK4641_SIG2, 1, 1, 0),
+        SOC_SINGLE("Right Out Enable Switch", AK4641_SIG2, 0, 1, 0),
+
+        SOC_SINGLE_TLV("Capture Volume", AK4641_PGA, 0, 71, 0, capture_tlv),
+
+        SOC_DOUBLE_R_TLV("Master Playback Volume", AK4641_LATT,
+                                AK4641_RATT, 0, 255, 1, master_tlv),
+
+        SOC_SINGLE_TLV("AUX In Volume", AK4641_VOL, 0, 15, 0, aux_in_tlv),
+
+        SOC_SINGLE("Equalizer Switch", AK4641_DAC, 2, 1, 0),
+        SOC_SINGLE_TLV("EQ1 100 Hz Volume", AK4641_EQLO, 0, 15, 1, eq_tlv),
+        SOC_SINGLE_TLV("EQ2 250 Hz Volume", AK4641_EQLO, 4, 15, 1, eq_tlv),
+        SOC_SINGLE_TLV("EQ3 1 kHz Volume", AK4641_EQMID, 0, 15, 1, eq_tlv),
+        SOC_SINGLE_TLV("EQ4 3.5 kHz Volume", AK4641_EQMID, 4, 15, 1, eq_tlv),
+        SOC_SINGLE_TLV("EQ5 10 kHz Volume", AK4641_EQHI, 0, 15, 1, eq_tlv),
+};
+
+/* Mono 1 Mixer */
+static const struct snd_kcontrol_new ak4641_mono1_mixer_controls[] = {
+        SOC_DAPM_SINGLE_TLV("Mic Mono Sidetone Volume", AK4641_VOL, 7, 1, 0,
+                                                mic_mono_sidetone_tlv),
+        SOC_DAPM_SINGLE("Mic Mono Sidetone Switch", AK4641_SIG1, 4, 1, 0),
+        SOC_DAPM_SINGLE("Mono Playback Switch", AK4641_SIG1, 5, 1, 0),
+};
+
+/* Stereo Mixer */
+static const struct snd_kcontrol_new ak4641_stereo_mixer_controls[] = {
+        SOC_DAPM_SINGLE_TLV("Mic Sidetone Volume", AK4641_VOL, 4, 7, 0,
+                                                mic_stereo_sidetone_tlv),
+        SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4641_SIG2, 4, 1, 0),
+        SOC_DAPM_SINGLE("Playback Switch", AK4641_SIG2, 7, 1, 0),
+        SOC_DAPM_SINGLE("Aux Bypass Switch", AK4641_SIG2, 5, 1, 0),
+};
+
+/* Input Mixer */
+static const struct snd_kcontrol_new ak4641_input_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Mic Capture Switch", AK4641_MIC, 2, 1, 0),
+        SOC_DAPM_SINGLE("Aux Capture Switch", AK4641_MIC, 5, 1, 0),
+};
+
+/* Mic mux */
+static const struct snd_kcontrol_new ak4641_mic_mux_control =
+        SOC_DAPM_ENUM("Mic Select", ak4641_mic_select_enum);
+
+/* Input mux */
+static const struct snd_kcontrol_new ak4641_input_mux_control =
+        SOC_DAPM_ENUM("Input Select", ak4641_mic_or_dac_enum);
+
+/* mono 2 switch */
+static const struct snd_kcontrol_new ak4641_mono2_control =
+        SOC_DAPM_SINGLE("Switch", AK4641_SIG1, 0, 1, 0);
+
+/* ak4641 dapm widgets */
+static const struct snd_soc_dapm_widget ak4641_dapm_widgets[] = {
+        SND_SOC_DAPM_MIXER("Stereo Mixer", SND_SOC_NOPM, 0, 0,
+                &ak4641_stereo_mixer_controls[0],
+                ARRAY_SIZE(ak4641_stereo_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Mono1 Mixer", SND_SOC_NOPM, 0, 0,
+                &ak4641_mono1_mixer_controls[0],
+                ARRAY_SIZE(ak4641_mono1_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0,
+                &ak4641_input_mixer_controls[0],
+                ARRAY_SIZE(ak4641_input_mixer_controls)),
+        SND_SOC_DAPM_MUX("Mic Mux", SND_SOC_NOPM, 0, 0,
+                &ak4641_mic_mux_control),
+        SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
+                &ak4641_input_mux_control),
+        SND_SOC_DAPM_SWITCH("Mono 2 Enable", SND_SOC_NOPM, 0, 0,
+                &ak4641_mono2_control),
+
+        SND_SOC_DAPM_OUTPUT("LOUT"),
+        SND_SOC_DAPM_OUTPUT("ROUT"),
+        SND_SOC_DAPM_OUTPUT("MOUT1"),
+        SND_SOC_DAPM_OUTPUT("MOUT2"),
+        SND_SOC_DAPM_OUTPUT("MICOUT"),
+
+        SND_SOC_DAPM_ADC("ADC", "HiFi Capture", AK4641_PM1, 0, 0),
+        SND_SOC_DAPM_PGA("Mic", AK4641_PM1, 1, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("AUX In", AK4641_PM1, 2, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Mono Out", AK4641_PM1, 3, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Line Out", AK4641_PM1, 4, 0, NULL, 0),
+
+        SND_SOC_DAPM_DAC("DAC", "HiFi Playback", AK4641_PM2, 0, 0),
+        SND_SOC_DAPM_PGA("Mono Out 2", AK4641_PM2, 3, 0, NULL, 0),
+
+        SND_SOC_DAPM_ADC("Voice ADC", "Voice Capture", AK4641_BTIF, 0, 0),
+        SND_SOC_DAPM_ADC("Voice DAC", "Voice Playback", AK4641_BTIF, 1, 0),
+
+        SND_SOC_DAPM_MICBIAS("Mic Int Bias", AK4641_MIC, 3, 0),
+        SND_SOC_DAPM_MICBIAS("Mic Ext Bias", AK4641_MIC, 4, 0),
+
+        SND_SOC_DAPM_INPUT("MICIN"),
+        SND_SOC_DAPM_INPUT("MICEXT"),
+        SND_SOC_DAPM_INPUT("AUX"),
+        SND_SOC_DAPM_INPUT("AIN"),
+};
+
+static const struct snd_soc_dapm_route ak4641_audio_map[] = {
+        /* Stereo Mixer */
+        {"Stereo Mixer", "Playback Switch", "DAC"},
+        {"Stereo Mixer", "Mic Sidetone Switch", "Input Mux"},
+        {"Stereo Mixer", "Aux Bypass Switch", "AUX In"},
+
+        /* Mono 1 Mixer */
+        {"Mono1 Mixer", "Mic Mono Sidetone Switch", "Input Mux"},
+        {"Mono1 Mixer", "Mono Playback Switch", "DAC"},
+
+        /* Mic */
+        {"Mic", NULL, "AIN"},
+        {"Mic Mux", "Internal", "Mic Int Bias"},
+        {"Mic Mux", "External", "Mic Ext Bias"},
+        {"Mic Int Bias", NULL, "MICIN"},
+        {"Mic Ext Bias", NULL, "MICEXT"},
+        {"MICOUT", NULL, "Mic Mux"},
+
+        /* Input Mux */
+        {"Input Mux", "Microphone", "Mic"},
+        {"Input Mux", "Voice DAC", "Voice DAC"},
+
+        /* Line Out */
+        {"LOUT", NULL, "Line Out"},
+        {"ROUT", NULL, "Line Out"},
+        {"Line Out", NULL, "Stereo Mixer"},
+
+        /* Mono 1 Out */
+        {"MOUT1", NULL, "Mono Out"},
+        {"Mono Out", NULL, "Mono1 Mixer"},
+
+        /* Mono 2 Out */
+        {"MOUT2", NULL, "Mono 2 Enable"},
+        {"Mono 2 Enable", "Switch", "Mono Out 2"},
+        {"Mono Out 2", NULL, "Stereo Mixer"},
+
+        {"Voice ADC", NULL, "Mono 2 Enable"},
+
+        /* Aux In */
+        {"AUX In", NULL, "AUX"},
+
+        /* ADC */
+        {"ADC", NULL, "Input Mixer"},
+        {"Input Mixer", "Mic Capture Switch", "Mic"},
+        {"Input Mixer", "Aux Capture Switch", "AUX In"},
+};
+
+static int ak4641_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+        int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
+
+        ak4641->sysclk = freq;
+        return 0;
+}
+
+static int ak4641_i2s_hw_params(struct snd_pcm_substream *substream,
+                                 struct snd_pcm_hw_params *params,
+                                 struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
+        int rate = params_rate(params), fs = 256;
+        u8 mode2;
+
+        if (rate)
+                fs = ak4641->sysclk / rate;
+        else
+                return -EINVAL;
+
+        /* set fs */
+        switch (fs) {
+        case 1024:
+                mode2 = (0x2 << 5);
+                break;
+        case 512:
+                mode2 = (0x1 << 5);
+                break;
+        case 256:
+                mode2 = (0x0 << 5);
+                break;
+        default:
+                dev_err(codec->dev, "Error: unsupported fs=%d\n", fs);
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, AK4641_MODE2, (0x3 << 5), mode2);
+
+        /* Update de-emphasis filter for the new rate */
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                ak4641->playback_fs = rate;
+                ak4641_set_deemph(codec);
+        };
+
+        return 0;
+}
+
+static int ak4641_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                                  unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        u8 btif;
+
+        /* interface format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                btif = (0x3 << 5);
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                btif = (0x2 << 5);
+                break;
+        case SND_SOC_DAIFMT_DSP_A:      /* MSB after FRM */
+                btif = (0x0 << 5);
+                break;
+        case SND_SOC_DAIFMT_DSP_B:      /* MSB during FRM */
+                btif = (0x1 << 5);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return snd_soc_update_bits(codec, AK4641_BTIF, (0x3 << 5), btif);
+}
+
+static int ak4641_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        u8 mode1 = 0;
+
+        /* interface format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                mode1 = 0x02;
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                mode1 = 0x01;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return snd_soc_write(codec, AK4641_MODE1, mode1);
+}
+
+static int ak4641_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+
+        return snd_soc_update_bits(codec, AK4641_DAC, 0x20, mute ? 0x20 : 0);
+}
+
+static int ak4641_set_bias_level(struct snd_soc_codec *codec,
+        enum snd_soc_bias_level level)
+{
+        struct ak4641_platform_data *pdata = codec->dev->platform_data;
+        int ret;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                /* unmute */
+                snd_soc_update_bits(codec, AK4641_DAC, 0x20, 0);
+                break;
+        case SND_SOC_BIAS_PREPARE:
+                /* mute */
+                snd_soc_update_bits(codec, AK4641_DAC, 0x20, 0x20);
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        if (pdata && gpio_is_valid(pdata->gpio_power))
+                                gpio_set_value(pdata->gpio_power, 1);
+                        mdelay(1);
+                        if (pdata && gpio_is_valid(pdata->gpio_npdn))
+                                gpio_set_value(pdata->gpio_npdn, 1);
+                        mdelay(1);
+
+                        ret = snd_soc_cache_sync(codec);
+                        if (ret) {
+                                dev_err(codec->dev,
+                                        "Failed to sync cache: %d\n", ret);
+                                return ret;
+                        }
+                }
+                snd_soc_update_bits(codec, AK4641_PM1, 0x80, 0x80);
+                snd_soc_update_bits(codec, AK4641_PM2, 0x80, 0);
+                break;
+        case SND_SOC_BIAS_OFF:
+                snd_soc_update_bits(codec, AK4641_PM1, 0x80, 0);
+                if (pdata && gpio_is_valid(pdata->gpio_npdn))
+                        gpio_set_value(pdata->gpio_npdn, 0);
+                if (pdata && gpio_is_valid(pdata->gpio_power))
+                        gpio_set_value(pdata->gpio_power, 0);
+                codec->cache_sync = 1;
+                break;
+        }
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#define AK4641_RATES    (SNDRV_PCM_RATE_8000_48000)
+#define AK4641_RATES_BT (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
+                         SNDRV_PCM_RATE_16000)
+#define AK4641_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE)
+
+static struct snd_soc_dai_ops ak4641_i2s_dai_ops = {
+        .hw_params    = ak4641_i2s_hw_params,
+        .set_fmt      = ak4641_i2s_set_dai_fmt,
+        .digital_mute = ak4641_mute,
+        .set_sysclk   = ak4641_set_dai_sysclk,
+};
+
+static struct snd_soc_dai_ops ak4641_pcm_dai_ops = {
+        .hw_params    = NULL, /* rates are controlled by BT chip */
+        .set_fmt      = ak4641_pcm_set_dai_fmt,
+        .digital_mute = ak4641_mute,
+        .set_sysclk   = ak4641_set_dai_sysclk,
+};
+
+struct snd_soc_dai_driver ak4641_dai[] = {
+{
+        .name = "ak4641-hifi",
+        .id = 1,
+        .playback = {
+                .stream_name = "HiFi Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = AK4641_RATES,
+                .formats = AK4641_FORMATS,
+        },
+        .capture = {
+                .stream_name = "HiFi Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = AK4641_RATES,
+                .formats = AK4641_FORMATS,
+        },
+        .ops = &ak4641_i2s_dai_ops,
+        .symmetric_rates = 1,
+},
+{
+        .name = "ak4641-voice",
+        .id = 1,
+        .playback = {
+                .stream_name = "Voice Playback",
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = AK4641_RATES_BT,
+                .formats = AK4641_FORMATS,
+        },
+        .capture = {
+                .stream_name = "Voice Capture",
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = AK4641_RATES_BT,
+                .formats = AK4641_FORMATS,
+        },
+        .ops = &ak4641_pcm_dai_ops,
+        .symmetric_rates = 1,
+},
+};
+
+static int ak4641_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        ak4641_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int ak4641_resume(struct snd_soc_codec *codec)
+{
+        ak4641_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+
+static int ak4641_probe(struct snd_soc_codec *codec)
+{
+        struct ak4641_platform_data *pdata = codec->dev->platform_data;
+        int ret;
+
+
+        if (pdata) {
+                if (gpio_is_valid(pdata->gpio_power)) {
+                        ret = gpio_request_one(pdata->gpio_power,
+                                        GPIOF_OUT_INIT_LOW, "ak4641 power");
+                        if (ret)
+                                goto err_out;
+                }
+                if (gpio_is_valid(pdata->gpio_npdn)) {
+                        ret = gpio_request_one(pdata->gpio_npdn,
+                                        GPIOF_OUT_INIT_LOW, "ak4641 npdn");
+                        if (ret)
+                                goto err_gpio;
+
+                        udelay(1); /* > 150 ns */
+                        gpio_set_value(pdata->gpio_npdn, 1);
+                }
+        }
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                goto err_register;
+        }
+
+        /* power on device */
+        ak4641_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        return 0;
+
+err_register:
+        if (pdata) {
+                if (gpio_is_valid(pdata->gpio_power))
+                        gpio_set_value(pdata->gpio_power, 0);
+                if (gpio_is_valid(pdata->gpio_npdn))
+                        gpio_free(pdata->gpio_npdn);
+        }
+err_gpio:
+        if (pdata && gpio_is_valid(pdata->gpio_power))
+                gpio_free(pdata->gpio_power);
+err_out:
+        return ret;
+}
+
+static int ak4641_remove(struct snd_soc_codec *codec)
+{
+        struct ak4641_platform_data *pdata = codec->dev->platform_data;
+
+        ak4641_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        if (pdata) {
+                if (gpio_is_valid(pdata->gpio_power)) {
+                        gpio_set_value(pdata->gpio_power, 0);
+                        gpio_free(pdata->gpio_power);
+                }
+                if (gpio_is_valid(pdata->gpio_npdn))
+                        gpio_free(pdata->gpio_npdn);
+        }
+        return 0;
+}
+
+
+static struct snd_soc_codec_driver soc_codec_dev_ak4641 = {
+        .probe                  = ak4641_probe,
+        .remove                 = ak4641_remove,
+        .suspend                = ak4641_suspend,
+        .resume                 = ak4641_resume,
+        .controls               = ak4641_snd_controls,
+        .num_controls           = ARRAY_SIZE(ak4641_snd_controls),
+        .dapm_widgets           = ak4641_dapm_widgets,
+        .num_dapm_widgets       = ARRAY_SIZE(ak4641_dapm_widgets),
+        .dapm_routes            = ak4641_audio_map,
+        .num_dapm_routes        = ARRAY_SIZE(ak4641_audio_map),
+        .set_bias_level         = ak4641_set_bias_level,
+        .reg_cache_size         = ARRAY_SIZE(ak4641_reg),
+        .reg_word_size          = sizeof(u8),
+        .reg_cache_default      = ak4641_reg,
+        .reg_cache_step         = 1,
+};
+
+
+static int __devinit ak4641_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct ak4641_priv *ak4641;
+        int ret;
+
+        ak4641 = kzalloc(sizeof(struct ak4641_priv), GFP_KERNEL);
+        if (!ak4641)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, ak4641);
+
+        ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_ak4641,
+                                ak4641_dai, ARRAY_SIZE(ak4641_dai));
+        if (ret < 0)
+                kfree(ak4641);
+
+        return ret;
+}
+
+static int __devexit ak4641_i2c_remove(struct i2c_client *i2c)
+{
+        snd_soc_unregister_codec(&i2c->dev);
+        kfree(i2c_get_clientdata(i2c));
+        return 0;
+}
+
+static const struct i2c_device_id ak4641_i2c_id[] = {
+        { "ak4641", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, ak4641_i2c_id);
+
+static struct i2c_driver ak4641_i2c_driver = {
+        .driver = {
+                .name = "ak4641",
+                .owner = THIS_MODULE,
+        },
+        .probe =    ak4641_i2c_probe,
+        .remove =   __devexit_p(ak4641_i2c_remove),
+        .id_table = ak4641_i2c_id,
+};
+
+static int __init ak4641_modinit(void)
+{
+        int ret;
+
+        ret = i2c_add_driver(&ak4641_i2c_driver);
+        if (ret != 0)
+                pr_err("Failed to register AK4641 I2C driver: %d\n", ret);
+
+        return ret;
+}
+module_init(ak4641_modinit);
+
+static void __exit ak4641_exit(void)
+{
+        i2c_del_driver(&ak4641_i2c_driver);
+}
+module_exit(ak4641_exit);
+
+MODULE_DESCRIPTION("SoC AK4641 driver");
+MODULE_AUTHOR("Harald Welte <laforge@gnufiish.org>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/ak4641.h b/sound/soc/codecs/ak4641.h
new file mode 100644
index 000000000000..4a263248efea
--- /dev/null
+++ b/sound/soc/codecs/ak4641.h
@@ -0,0 +1,47 @@
+/*
+ * ak4641.h  --  AK4641 SoC Audio driver
+ *
+ * Copyright 2008 Harald Welte <laforge@gnufiish.org>
+ *
+ * Based on ak4535.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _AK4641_H
+#define _AK4641_H
+
+/* AK4641 register space */
+
+#define AK4641_PM1              0x00
+#define AK4641_PM2              0x01
+#define AK4641_SIG1             0x02
+#define AK4641_SIG2             0x03
+#define AK4641_MODE1            0x04
+#define AK4641_MODE2            0x05
+#define AK4641_DAC              0x06
+#define AK4641_MIC              0x07
+#define AK4641_TIMER            0x08
+#define AK4641_ALC1             0x09
+#define AK4641_ALC2             0x0a
+#define AK4641_PGA              0x0b
+#define AK4641_LATT             0x0c
+#define AK4641_RATT             0x0d
+#define AK4641_VOL              0x0e
+#define AK4641_STATUS           0x0f
+#define AK4641_EQLO             0x10
+#define AK4641_EQMID            0x11
+#define AK4641_EQHI             0x12
+#define AK4641_BTIF             0x13
+
+#define AK4641_CACHEREGNUM      0x14
+
+
+
+#define AK4641_DAI_HIFI         0
+#define AK4641_DAI_VOICE        1
+
+
+#endif
diff --git a/sound/soc/codecs/ak4642.c b/sound/soc/codecs/ak4642.c
index 3d7dc55305ec..65f46047b1cb 100644
--- a/sound/soc/codecs/ak4642.c
+++ b/sound/soc/codecs/ak4642.c
@@ -26,12 +26,10 @@
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <sound/soc-dapm.h>
+#include <sound/soc.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
-#include "ak4642.h"
-
 #define AK4642_VERSION "0.0.1"
 
 #define PW_MGMT1        0x00
@@ -74,6 +72,12 @@
 
 #define AK4642_CACHEREGNUM      0x25
 
+/* PW_MGMT1*/
+#define PMVCM           (1 << 6) /* VCOM Power Management */
+#define PMMIN           (1 << 5) /* MIN Input Power Management */
+#define PMDAC           (1 << 2) /* DAC Power Management */
+#define PMADL           (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
+
 /* PW_MGMT2 */
 #define HPMTN           (1 << 6)
 #define PMHPL           (1 << 5)
@@ -85,6 +89,23 @@
 #define PMHP_MASK       (PMHPL | PMHPR)
 #define PMHP            PMHP_MASK
 
+/* PW_MGMT3 */
+#define PMADR           (1 << 0) /* MIC L / ADC R Power Management */
+
+/* SG_SL1 */
+#define MINS            (1 << 6) /* Switch from MIN to Speaker */
+#define DACL            (1 << 4) /* Switch from DAC to Stereo or Receiver */
+#define PMMP            (1 << 2) /* MPWR pin Power Management */
+#define MGAIN0          (1 << 0) /* MIC amp gain*/
+
+/* TIMER */
+#define ZTM(param)      ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
+#define WTM(param)      (((param & 0x4) << 4) | ((param & 0x3) << 2))
+
+/* ALC_CTL1 */
+#define ALC             (1 << 5) /* ALC Enable */
+#define LMTH0           (1 << 0) /* ALC Limiter / Recovery Level */
+
 /* MD_CTL1 */
 #define PLL3            (1 << 7)
 #define PLL2            (1 << 6)
@@ -95,6 +116,12 @@
 #define BCKO_MASK       (1 << 3)
 #define BCKO_64         BCKO_MASK
 
+#define DIF_MASK        (3 << 0)
+#define DSP             (0 << 0)
+#define RIGHT_J         (1 << 0)
+#define LEFT_J          (2 << 0)
+#define I2S             (3 << 0)
+
 /* MD_CTL2 */
 #define FS0             (1 << 0)
 #define FS1             (1 << 1)
@@ -102,7 +129,11 @@
 #define FS3             (1 << 5)
 #define FS_MASK         (FS0 | FS1 | FS2 | FS3)
 
-struct snd_soc_codec_device soc_codec_dev_ak4642;
+/* MD_CTL3 */
+#define BST1            (1 << 3)
+
+/* MD_CTL4 */
+#define DACH            (1 << 0)
 
 /*
  * Playback Volume (table 39)
@@ -123,11 +154,11 @@ static const struct snd_kcontrol_new ak4642_snd_controls[] = {
 
 /* codec private data */
 struct ak4642_priv {
-        struct snd_soc_codec codec;
+        unsigned int sysclk;
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
-static struct snd_soc_codec *ak4642_codec;
-
 /*
  * ak4642 register cache
  */
@@ -219,11 +250,12 @@ static int ak4642_dai_startup(struct snd_pcm_substream *substream,
                  * This operation came from example code of
                  * "ASAHI KASEI AK4642" (japanese) manual p97.
                  */
-                ak4642_write(codec, 0x0f, 0x09);
-                ak4642_write(codec, 0x0e, 0x19);
-                ak4642_write(codec, 0x09, 0x91);
-                ak4642_write(codec, 0x0c, 0x91);
-                ak4642_write(codec, 0x00, 0x64);
+                snd_soc_update_bits(codec, MD_CTL4, DACH, DACH);
+                snd_soc_update_bits(codec, MD_CTL3, BST1, BST1);
+                ak4642_write(codec, L_IVC, 0x91); /* volume */
+                ak4642_write(codec, R_IVC, 0x91); /* volume */
+                snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMMIN | PMDAC,
+                                                     PMVCM | PMMIN | PMDAC);
                 snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, PMHP);
                 snd_soc_update_bits(codec, PW_MGMT2, HPMTN,     HPMTN);
         } else {
@@ -240,13 +272,12 @@ static int ak4642_dai_startup(struct snd_pcm_substream *substream,
                  * This operation came from example code of
                  * "ASAHI KASEI AK4642" (japanese) manual p94.
                  */
-                ak4642_write(codec, 0x02, 0x05);
-                ak4642_write(codec, 0x06, 0x3c);
-                ak4642_write(codec, 0x08, 0xe1);
-                ak4642_write(codec, 0x0b, 0x00);
-                ak4642_write(codec, 0x07, 0x21);
-                ak4642_write(codec, 0x00, 0x41);
-                ak4642_write(codec, 0x10, 0x01);
+                ak4642_write(codec, SG_SL1, PMMP | MGAIN0);
+                ak4642_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
+                ak4642_write(codec, ALC_CTL1, ALC | LMTH0);
+                snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMADL,
+                                                     PMVCM | PMADL);
+                snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
         }
 
         return 0;
@@ -262,14 +293,14 @@ static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
                 /* stop headphone output */
                 snd_soc_update_bits(codec, PW_MGMT2, HPMTN,     0);
                 snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, 0);
-                ak4642_write(codec, 0x00, 0x40);
-                ak4642_write(codec, 0x0e, 0x11);
-                ak4642_write(codec, 0x0f, 0x08);
+                snd_soc_update_bits(codec, PW_MGMT1, PMMIN | PMDAC, 0);
+                snd_soc_update_bits(codec, MD_CTL3, BST1, 0);
+                snd_soc_update_bits(codec, MD_CTL4, DACH, 0);
         } else {
                 /* stop stereo input */
-                ak4642_write(codec, 0x00, 0x40);
-                ak4642_write(codec, 0x10, 0x00);
-                ak4642_write(codec, 0x07, 0x01);
+                snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
+                snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
+                snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
         }
 }
 
@@ -326,9 +357,27 @@ static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
         default:
                 return -EINVAL;
         }
-        snd_soc_update_bits(codec, PW_MGMT2, MS, data);
+        snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
         snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
 
+        /* format type */
+        data = 0;
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_LEFT_J:
+                data = LEFT_J;
+                break;
+        case SND_SOC_DAIFMT_I2S:
+                data = I2S;
+                break;
+        /* FIXME
+         * Please add RIGHT_J / DSP support here
+         */
+        default:
+                return -EINVAL;
+                break;
+        }
+        snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
+
         return 0;
 }
 
@@ -393,8 +442,8 @@ static struct snd_soc_dai_ops ak4642_dai_ops = {
         .hw_params      = ak4642_dai_hw_params,
 };
 
-struct snd_soc_dai ak4642_dai = {
-        .name = "AK4642",
+static struct snd_soc_dai_driver ak4642_dai = {
+        .name = "ak4642-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -410,112 +459,65 @@ struct snd_soc_dai ak4642_dai = {
         .ops = &ak4642_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(ak4642_dai);
 
-static int ak4642_resume(struct platform_device *pdev)
+static int ak4642_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         ak4642_sync(codec);
         return 0;
 }
 
-/*
- * initialise the AK4642 driver
- * register the mixer and dsp interfaces with the kernel
- */
-static int ak4642_init(struct ak4642_priv *ak4642)
+
+static int ak4642_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = &ak4642->codec;
-        int ret = 0;
+        struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
 
-        if (ak4642_codec) {
-                dev_err(codec->dev, "Another ak4642 is registered\n");
-                return -EINVAL;
-        }
+        dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, ak4642);
-        codec->name             = "AK4642";
-        codec->owner            = THIS_MODULE;
-        codec->read             = ak4642_read_reg_cache;
-        codec->write            = ak4642_write;
-        codec->dai              = &ak4642_dai;
-        codec->num_dai          = 1;
         codec->hw_write         = (hw_write_t)i2c_master_send;
-        codec->reg_cache_size   = ARRAY_SIZE(ak4642_reg);
-        codec->reg_cache        = kmemdup(ak4642_reg,
-                                          sizeof(ak4642_reg), GFP_KERNEL);
-
-        if (!codec->reg_cache)
-                return -ENOMEM;
+        codec->control_data     = ak4642->control_data;
 
-        ak4642_dai.dev = codec->dev;
-        ak4642_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto reg_cache_err;
-        }
-
-        ret = snd_soc_register_dai(&ak4642_dai);
-        if (ret) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                snd_soc_unregister_codec(codec);
-                goto reg_cache_err;
-        }
-
-        return ret;
-
-reg_cache_err:
-        kfree(codec->reg_cache);
-        codec->reg_cache = NULL;
+        snd_soc_add_controls(codec, ak4642_snd_controls,
+                             ARRAY_SIZE(ak4642_snd_controls));
 
-        return ret;
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
+        .probe                  = ak4642_probe,
+        .resume                 = ak4642_resume,
+        .read                   = ak4642_read_reg_cache,
+        .write                  = ak4642_write,
+        .reg_cache_size         = ARRAY_SIZE(ak4642_reg),
+        .reg_word_size          = sizeof(u8),
+        .reg_cache_default      = ak4642_reg,
+};
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-static int ak4642_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
         struct ak4642_priv *ak4642;
-        struct snd_soc_codec *codec;
         int ret;
 
         ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
         if (!ak4642)
                 return -ENOMEM;
 
-        codec = &ak4642->codec;
-        codec->dev = &i2c->dev;
-
         i2c_set_clientdata(i2c, ak4642);
-        codec->control_data = i2c;
+        ak4642->control_data = i2c;
+        ak4642->control_type = SND_SOC_I2C;
 
-        ret = ak4642_init(ak4642);
-        if (ret < 0) {
-                printk(KERN_ERR "failed to initialise AK4642\n");
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_ak4642, &ak4642_dai, 1);
+        if (ret < 0)
                 kfree(ak4642);
-        }
-
         return ret;
 }
 
-static int ak4642_i2c_remove(struct i2c_client *client)
+static __devexit int ak4642_i2c_remove(struct i2c_client *client)
 {
-        struct ak4642_priv *ak4642 = i2c_get_clientdata(client);
-
-        snd_soc_unregister_dai(&ak4642_dai);
-        snd_soc_unregister_codec(&ak4642->codec);
-        kfree(ak4642->codec.reg_cache);
-        kfree(ak4642);
-        ak4642_codec = NULL;
-
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -528,64 +530,15 @@ MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
 
 static struct i2c_driver ak4642_i2c_driver = {
         .driver = {
-                .name = "AK4642 I2C Codec",
+                .name = "ak4642-codec",
                 .owner = THIS_MODULE,
         },
         .probe          = ak4642_i2c_probe,
-        .remove         = ak4642_i2c_remove,
+        .remove         = __devexit_p(ak4642_i2c_remove),
         .id_table       = ak4642_i2c_id,
 };
-
 #endif
 
-static int ak4642_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        int ret;
-
-        if (!ak4642_codec) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = ak4642_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "ak4642: failed to create pcms\n");
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(ak4642_codec, ak4642_snd_controls,
-                             ARRAY_SIZE(ak4642_snd_controls));
-
-        dev_info(&pdev->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
-        return ret;
-
-pcm_err:
-        return ret;
-
-}
-
-/* power down chip */
-static int ak4642_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_ak4642 = {
-        .probe =        ak4642_probe,
-        .remove =       ak4642_remove,
-        .resume =       ak4642_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_ak4642);
-
 static int __init ak4642_modinit(void)
 {
         int ret = 0;
diff --git a/sound/soc/codecs/ak4642.h b/sound/soc/codecs/ak4642.h
deleted file mode 100644
index e476833d314e..000000000000
--- a/sound/soc/codecs/ak4642.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * ak4642.h  --  AK4642 Soc Audio driver
- *
- * Copyright (C) 2009 Renesas Solutions Corp.
- * Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * Based on ak4535.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _AK4642_H
-#define _AK4642_H
-
-extern struct snd_soc_dai ak4642_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ak4642;
-
-#endif
diff --git a/sound/soc/codecs/ak4671.c b/sound/soc/codecs/ak4671.c
index 87566932a3b1..88b29f8c748b 100644
--- a/sound/soc/codecs/ak4671.c
+++ b/sound/soc/codecs/ak4671.c
@@ -17,18 +17,16 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
 #include "ak4671.h"
 
-static struct snd_soc_codec *ak4671_codec;
 
 /* codec private data */
 struct ak4671_priv {
-        struct snd_soc_codec codec;
-        u8 reg_cache[AK4671_CACHEREGNUM];
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
 /* ak4671 register cache & default register settings */
@@ -354,7 +352,7 @@ static const struct snd_soc_dapm_widget ak4671_dapm_widgets[] = {
         SND_SOC_DAPM_SUPPLY("PMPLL", AK4671_PLL_MODE_SELECT1, 0, 0, NULL, 0),
 };
 
-static const struct snd_soc_dapm_route intercon[] = {
+static const struct snd_soc_dapm_route ak4671_intercon[] = {
         {"DAC Left", "NULL", "PMPLL"},
         {"DAC Right", "NULL", "PMPLL"},
         {"ADC Left", "NULL", "PMPLL"},
@@ -435,16 +433,6 @@ static const struct snd_soc_dapm_route intercon[] = {
         {"ROUT3 Mixer", "RINS4", "RIN4 Mixing Circuit"},
 };
 
-static int ak4671_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, ak4671_dapm_widgets,
-                                  ARRAY_SIZE(ak4671_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
-
-        return 0;
-}
-
 static int ak4671_hw_params(struct snd_pcm_substream *substream,
                 struct snd_pcm_hw_params *params,
                 struct snd_soc_dai *dai)
@@ -602,7 +590,7 @@ static int ak4671_set_bias_level(struct snd_soc_codec *codec,
                 snd_soc_write(codec, AK4671_AD_DA_POWER_MANAGEMENT, 0x00);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -619,8 +607,8 @@ static struct snd_soc_dai_ops ak4671_dai_ops = {
         .set_fmt        = ak4671_set_dai_fmt,
 };
 
-struct snd_soc_dai ak4671_dai = {
-        .name = "AK4671",
+static struct snd_soc_dai_driver ak4671_dai = {
+        .name = "ak4671-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -635,151 +623,72 @@ struct snd_soc_dai ak4671_dai = {
                 .formats = AK4671_FORMATS,},
         .ops = &ak4671_dai_ops,
 };
-EXPORT_SYMBOL_GPL(ak4671_dai);
 
-static int ak4671_probe(struct platform_device *pdev)
+static int ak4671_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (ak4671_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
+        struct ak4671_priv *ak4671 = snd_soc_codec_get_drvdata(codec);
+        int ret;
 
-        socdev->card->codec = ak4671_codec;
-        codec = ak4671_codec;
+        codec->hw_write = (hw_write_t)i2c_master_send;
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, ak4671->control_type);
         if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
         snd_soc_add_controls(codec, ak4671_snd_controls,
                              ARRAY_SIZE(ak4671_snd_controls));
-        ak4671_add_widgets(codec);
 
         ak4671_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return ret;
-
-pcm_err:
-        return ret;
 }
 
-static int ak4671_remove(struct platform_device *pdev)
+static int ak4671_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
+        ak4671_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_ak4671 = {
+static struct snd_soc_codec_driver soc_codec_dev_ak4671 = {
         .probe = ak4671_probe,
         .remove = ak4671_remove,
+        .set_bias_level = ak4671_set_bias_level,
+        .reg_cache_size = AK4671_CACHEREGNUM,
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = ak4671_reg,
+        .dapm_widgets = ak4671_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(ak4671_dapm_widgets),
+        .dapm_routes = ak4671_intercon,
+        .num_dapm_routes = ARRAY_SIZE(ak4671_intercon),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_ak4671);
-
-static int ak4671_register(struct ak4671_priv *ak4671,
-                enum snd_soc_control_type control)
-{
-        int ret;
-        struct snd_soc_codec *codec = &ak4671->codec;
-
-        if (ak4671_codec) {
-                dev_err(codec->dev, "Another AK4671 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec,  ak4671);
-        codec->name = "AK4671";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = ak4671_set_bias_level;
-        codec->dai = &ak4671_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = AK4671_CACHEREGNUM;
-        codec->reg_cache = &ak4671->reg_cache;
-
-        memcpy(codec->reg_cache, ak4671_reg, sizeof(ak4671_reg));
-
-        ret = snd_soc_codec_set_cache_io(codec, 8, 8, control);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
-        }
-
-        ak4671_dai.dev = codec->dev;
-        ak4671_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&ak4671_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
-
-        return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(ak4671);
-        return ret;
-}
-
-static void ak4671_unregister(struct ak4671_priv *ak4671)
-{
-        ak4671_set_bias_level(&ak4671->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&ak4671_dai);
-        snd_soc_unregister_codec(&ak4671->codec);
-        kfree(ak4671);
-        ak4671_codec = NULL;
-}
 
 static int __devinit ak4671_i2c_probe(struct i2c_client *client,
                 const struct i2c_device_id *id)
 {
         struct ak4671_priv *ak4671;
-        struct snd_soc_codec *codec;
+        int ret;
 
         ak4671 = kzalloc(sizeof(struct ak4671_priv), GFP_KERNEL);
         if (ak4671 == NULL)
                 return -ENOMEM;
 
-        codec = &ak4671->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
         i2c_set_clientdata(client, ak4671);
-        codec->control_data = client;
-
-        codec->dev = &client->dev;
+        ak4671->control_data = client;
+        ak4671->control_type = SND_SOC_I2C;
 
-        return ak4671_register(ak4671, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&client->dev,
+                        &soc_codec_dev_ak4671, &ak4671_dai, 1);
+        if (ret < 0)
+                kfree(ak4671);
+        return ret;
 }
 
 static __devexit int ak4671_i2c_remove(struct i2c_client *client)
 {
-        struct ak4671_priv *ak4671 = i2c_get_clientdata(client);
-
-        ak4671_unregister(ak4671);
-
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -791,7 +700,7 @@ MODULE_DEVICE_TABLE(i2c, ak4671_i2c_id);
 
 static struct i2c_driver ak4671_i2c_driver = {
         .driver = {
-                .name = "ak4671",
+                .name = "ak4671-codec",
                 .owner = THIS_MODULE,
         },
         .probe = ak4671_i2c_probe,
diff --git a/sound/soc/codecs/ak4671.h b/sound/soc/codecs/ak4671.h
index e2fad964e88b..61cb7ab7552c 100644
--- a/sound/soc/codecs/ak4671.h
+++ b/sound/soc/codecs/ak4671.h
@@ -150,7 +150,4 @@
 /* AK4671_LOUT2_POWER_MANAGEMENT (0x10) Fields */
 #define AK4671_MUTEN                            0x04
 
-extern struct snd_soc_dai ak4671_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ak4671;
-
 #endif
diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c
new file mode 100644
index 000000000000..eecffb548947
--- /dev/null
+++ b/sound/soc/codecs/alc5623.c
@@ -0,0 +1,1117 @@
+/*
+ * alc5623.c  --  alc562[123] ALSA Soc Audio driver
+ *
+ * Copyright 2008 Realtek Microelectronics
+ * Author: flove <flove@realtek.com> Ethan <eku@marvell.com>
+ *
+ * Copyright 2010 Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ *
+ * Based on WM8753.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/tlv.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/alc5623.h>
+
+#include "alc5623.h"
+
+static int caps_charge = 2000;
+module_param(caps_charge, int, 0);
+MODULE_PARM_DESC(caps_charge, "ALC5623 cap charge time (msecs)");
+
+/* codec private data */
+struct alc5623_priv {
+        enum snd_soc_control_type control_type;
+        void *control_data;
+        struct mutex mutex;
+        u8 id;
+        unsigned int sysclk;
+        u16 reg_cache[ALC5623_VENDOR_ID2+2];
+        unsigned int add_ctrl;
+        unsigned int jack_det_ctrl;
+};
+
+static void alc5623_fill_cache(struct snd_soc_codec *codec)
+{
+        int i, step = codec->driver->reg_cache_step;
+        u16 *cache = codec->reg_cache;
+
+        /* not really efficient ... */
+        for (i = 0 ; i < codec->driver->reg_cache_size ; i += step)
+                cache[i] = codec->hw_read(codec, i);
+}
+
+static inline int alc5623_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, ALC5623_RESET, 0);
+}
+
+static int amp_mixer_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        /* to power-on/off class-d amp generators/speaker */
+        /* need to write to 'index-46h' register :        */
+        /* so write index num (here 0x46) to reg 0x6a     */
+        /* and then 0xffff/0 to reg 0x6c                  */
+        snd_soc_write(w->codec, ALC5623_HID_CTRL_INDEX, 0x46);
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                snd_soc_write(w->codec, ALC5623_HID_CTRL_DATA, 0xFFFF);
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                snd_soc_write(w->codec, ALC5623_HID_CTRL_DATA, 0);
+                break;
+        }
+
+        return 0;
+}
+
+/*
+ * ALC5623 Controls
+ */
+
+static const DECLARE_TLV_DB_SCALE(vol_tlv, -3450, 150, 0);
+static const DECLARE_TLV_DB_SCALE(hp_tlv, -4650, 150, 0);
+static const DECLARE_TLV_DB_SCALE(adc_rec_tlv, -1650, 150, 0);
+static const unsigned int boost_tlv[] = {
+        TLV_DB_RANGE_HEAD(3),
+        0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+        1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
+        2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
+};
+static const DECLARE_TLV_DB_SCALE(dig_tlv, 0, 600, 0);
+
+static const struct snd_kcontrol_new rt5621_vol_snd_controls[] = {
+        SOC_DOUBLE_TLV("Speaker Playback Volume",
+                        ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
+        SOC_DOUBLE("Speaker Playback Switch",
+                        ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
+        SOC_DOUBLE_TLV("Headphone Playback Volume",
+                        ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
+        SOC_DOUBLE("Headphone Playback Switch",
+                        ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5622_vol_snd_controls[] = {
+        SOC_DOUBLE_TLV("Speaker Playback Volume",
+                        ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
+        SOC_DOUBLE("Speaker Playback Switch",
+                        ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
+        SOC_DOUBLE_TLV("Line Playback Volume",
+                        ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
+        SOC_DOUBLE("Line Playback Switch",
+                        ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
+};
+
+static const struct snd_kcontrol_new alc5623_vol_snd_controls[] = {
+        SOC_DOUBLE_TLV("Line Playback Volume",
+                        ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
+        SOC_DOUBLE("Line Playback Switch",
+                        ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
+        SOC_DOUBLE_TLV("Headphone Playback Volume",
+                        ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
+        SOC_DOUBLE("Headphone Playback Switch",
+                        ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
+};
+
+static const struct snd_kcontrol_new alc5623_snd_controls[] = {
+        SOC_DOUBLE_TLV("Auxout Playback Volume",
+                        ALC5623_MONO_AUX_OUT_VOL, 8, 0, 31, 1, hp_tlv),
+        SOC_DOUBLE("Auxout Playback Switch",
+                        ALC5623_MONO_AUX_OUT_VOL, 15, 7, 1, 1),
+        SOC_DOUBLE_TLV("PCM Playback Volume",
+                        ALC5623_STEREO_DAC_VOL, 8, 0, 31, 1, vol_tlv),
+        SOC_DOUBLE_TLV("AuxI Capture Volume",
+                        ALC5623_AUXIN_VOL, 8, 0, 31, 1, vol_tlv),
+        SOC_DOUBLE_TLV("LineIn Capture Volume",
+                        ALC5623_LINE_IN_VOL, 8, 0, 31, 1, vol_tlv),
+        SOC_SINGLE_TLV("Mic1 Capture Volume",
+                        ALC5623_MIC_VOL, 8, 31, 1, vol_tlv),
+        SOC_SINGLE_TLV("Mic2 Capture Volume",
+                        ALC5623_MIC_VOL, 0, 31, 1, vol_tlv),
+        SOC_DOUBLE_TLV("Rec Capture Volume",
+                        ALC5623_ADC_REC_GAIN, 7, 0, 31, 0, adc_rec_tlv),
+        SOC_SINGLE_TLV("Mic 1 Boost Volume",
+                        ALC5623_MIC_CTRL, 10, 2, 0, boost_tlv),
+        SOC_SINGLE_TLV("Mic 2 Boost Volume",
+                        ALC5623_MIC_CTRL, 8, 2, 0, boost_tlv),
+        SOC_SINGLE_TLV("Digital Boost Volume",
+                        ALC5623_ADD_CTRL_REG, 4, 3, 0, dig_tlv),
+};
+
+/*
+ * DAPM Controls
+ */
+static const struct snd_kcontrol_new alc5623_hp_mixer_controls[] = {
+SOC_DAPM_SINGLE("LI2HP Playback Switch", ALC5623_LINE_IN_VOL, 15, 1, 1),
+SOC_DAPM_SINGLE("AUXI2HP Playback Switch", ALC5623_AUXIN_VOL, 15, 1, 1),
+SOC_DAPM_SINGLE("MIC12HP Playback Switch", ALC5623_MIC_ROUTING_CTRL, 15, 1, 1),
+SOC_DAPM_SINGLE("MIC22HP Playback Switch", ALC5623_MIC_ROUTING_CTRL, 7, 1, 1),
+SOC_DAPM_SINGLE("DAC2HP Playback Switch", ALC5623_STEREO_DAC_VOL, 15, 1, 1),
+};
+
+static const struct snd_kcontrol_new alc5623_hpl_mixer_controls[] = {
+SOC_DAPM_SINGLE("ADC2HP_L Playback Switch", ALC5623_ADC_REC_GAIN, 15, 1, 1),
+};
+
+static const struct snd_kcontrol_new alc5623_hpr_mixer_controls[] = {
+SOC_DAPM_SINGLE("ADC2HP_R Playback Switch", ALC5623_ADC_REC_GAIN, 14, 1, 1),
+};
+
+static const struct snd_kcontrol_new alc5623_mono_mixer_controls[] = {
+SOC_DAPM_SINGLE("ADC2MONO_L Playback Switch", ALC5623_ADC_REC_GAIN, 13, 1, 1),
+SOC_DAPM_SINGLE("ADC2MONO_R Playback Switch", ALC5623_ADC_REC_GAIN, 12, 1, 1),
+SOC_DAPM_SINGLE("LI2MONO Playback Switch", ALC5623_LINE_IN_VOL, 13, 1, 1),
+SOC_DAPM_SINGLE("AUXI2MONO Playback Switch", ALC5623_AUXIN_VOL, 13, 1, 1),
+SOC_DAPM_SINGLE("MIC12MONO Playback Switch", ALC5623_MIC_ROUTING_CTRL, 13, 1, 1),
+SOC_DAPM_SINGLE("MIC22MONO Playback Switch", ALC5623_MIC_ROUTING_CTRL, 5, 1, 1),
+SOC_DAPM_SINGLE("DAC2MONO Playback Switch", ALC5623_STEREO_DAC_VOL, 13, 1, 1),
+};
+
+static const struct snd_kcontrol_new alc5623_speaker_mixer_controls[] = {
+SOC_DAPM_SINGLE("LI2SPK Playback Switch", ALC5623_LINE_IN_VOL, 14, 1, 1),
+SOC_DAPM_SINGLE("AUXI2SPK Playback Switch", ALC5623_AUXIN_VOL, 14, 1, 1),
+SOC_DAPM_SINGLE("MIC12SPK Playback Switch", ALC5623_MIC_ROUTING_CTRL, 14, 1, 1),
+SOC_DAPM_SINGLE("MIC22SPK Playback Switch", ALC5623_MIC_ROUTING_CTRL, 6, 1, 1),
+SOC_DAPM_SINGLE("DAC2SPK Playback Switch", ALC5623_STEREO_DAC_VOL, 14, 1, 1),
+};
+
+/* Left Record Mixer */
+static const struct snd_kcontrol_new alc5623_captureL_mixer_controls[] = {
+SOC_DAPM_SINGLE("Mic1 Capture Switch", ALC5623_ADC_REC_MIXER, 14, 1, 1),
+SOC_DAPM_SINGLE("Mic2 Capture Switch", ALC5623_ADC_REC_MIXER, 13, 1, 1),
+SOC_DAPM_SINGLE("LineInL Capture Switch", ALC5623_ADC_REC_MIXER, 12, 1, 1),
+SOC_DAPM_SINGLE("Left AuxI Capture Switch", ALC5623_ADC_REC_MIXER, 11, 1, 1),
+SOC_DAPM_SINGLE("HPMixerL Capture Switch", ALC5623_ADC_REC_MIXER, 10, 1, 1),
+SOC_DAPM_SINGLE("SPKMixer Capture Switch", ALC5623_ADC_REC_MIXER, 9, 1, 1),
+SOC_DAPM_SINGLE("MonoMixer Capture Switch", ALC5623_ADC_REC_MIXER, 8, 1, 1),
+};
+
+/* Right Record Mixer */
+static const struct snd_kcontrol_new alc5623_captureR_mixer_controls[] = {
+SOC_DAPM_SINGLE("Mic1 Capture Switch", ALC5623_ADC_REC_MIXER, 6, 1, 1),
+SOC_DAPM_SINGLE("Mic2 Capture Switch", ALC5623_ADC_REC_MIXER, 5, 1, 1),
+SOC_DAPM_SINGLE("LineInR Capture Switch", ALC5623_ADC_REC_MIXER, 4, 1, 1),
+SOC_DAPM_SINGLE("Right AuxI Capture Switch", ALC5623_ADC_REC_MIXER, 3, 1, 1),
+SOC_DAPM_SINGLE("HPMixerR Capture Switch", ALC5623_ADC_REC_MIXER, 2, 1, 1),
+SOC_DAPM_SINGLE("SPKMixer Capture Switch", ALC5623_ADC_REC_MIXER, 1, 1, 1),
+SOC_DAPM_SINGLE("MonoMixer Capture Switch", ALC5623_ADC_REC_MIXER, 0, 1, 1),
+};
+
+static const char *alc5623_spk_n_sour_sel[] = {
+                "RN/-R", "RP/+R", "LN/-R", "Vmid" };
+static const char *alc5623_hpl_out_input_sel[] = {
+                "Vmid", "HP Left Mix"};
+static const char *alc5623_hpr_out_input_sel[] = {
+                "Vmid", "HP Right Mix"};
+static const char *alc5623_spkout_input_sel[] = {
+                "Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
+static const char *alc5623_aux_out_input_sel[] = {
+                "Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
+
+/* auxout output mux */
+static const struct soc_enum alc5623_aux_out_input_enum =
+SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 6, 4, alc5623_aux_out_input_sel);
+static const struct snd_kcontrol_new alc5623_auxout_mux_controls =
+SOC_DAPM_ENUM("Route", alc5623_aux_out_input_enum);
+
+/* speaker output mux */
+static const struct soc_enum alc5623_spkout_input_enum =
+SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 10, 4, alc5623_spkout_input_sel);
+static const struct snd_kcontrol_new alc5623_spkout_mux_controls =
+SOC_DAPM_ENUM("Route", alc5623_spkout_input_enum);
+
+/* headphone left output mux */
+static const struct soc_enum alc5623_hpl_out_input_enum =
+SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 9, 2, alc5623_hpl_out_input_sel);
+static const struct snd_kcontrol_new alc5623_hpl_out_mux_controls =
+SOC_DAPM_ENUM("Route", alc5623_hpl_out_input_enum);
+
+/* headphone right output mux */
+static const struct soc_enum alc5623_hpr_out_input_enum =
+SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 8, 2, alc5623_hpr_out_input_sel);
+static const struct snd_kcontrol_new alc5623_hpr_out_mux_controls =
+SOC_DAPM_ENUM("Route", alc5623_hpr_out_input_enum);
+
+/* speaker output N select */
+static const struct soc_enum alc5623_spk_n_sour_enum =
+SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 14, 4, alc5623_spk_n_sour_sel);
+static const struct snd_kcontrol_new alc5623_spkoutn_mux_controls =
+SOC_DAPM_ENUM("Route", alc5623_spk_n_sour_enum);
+
+static const struct snd_soc_dapm_widget alc5623_dapm_widgets[] = {
+/* Muxes */
+SND_SOC_DAPM_MUX("AuxOut Mux", SND_SOC_NOPM, 0, 0,
+        &alc5623_auxout_mux_controls),
+SND_SOC_DAPM_MUX("SpeakerOut Mux", SND_SOC_NOPM, 0, 0,
+        &alc5623_spkout_mux_controls),
+SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0,
+        &alc5623_hpl_out_mux_controls),
+SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0,
+        &alc5623_hpr_out_mux_controls),
+SND_SOC_DAPM_MUX("SpeakerOut N Mux", SND_SOC_NOPM, 0, 0,
+        &alc5623_spkoutn_mux_controls),
+
+/* output mixers */
+SND_SOC_DAPM_MIXER("HP Mix", SND_SOC_NOPM, 0, 0,
+        &alc5623_hp_mixer_controls[0],
+        ARRAY_SIZE(alc5623_hp_mixer_controls)),
+SND_SOC_DAPM_MIXER("HPR Mix", ALC5623_PWR_MANAG_ADD2, 4, 0,
+        &alc5623_hpr_mixer_controls[0],
+        ARRAY_SIZE(alc5623_hpr_mixer_controls)),
+SND_SOC_DAPM_MIXER("HPL Mix", ALC5623_PWR_MANAG_ADD2, 5, 0,
+        &alc5623_hpl_mixer_controls[0],
+        ARRAY_SIZE(alc5623_hpl_mixer_controls)),
+SND_SOC_DAPM_MIXER("HPOut Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_MIXER("Mono Mix", ALC5623_PWR_MANAG_ADD2, 2, 0,
+        &alc5623_mono_mixer_controls[0],
+        ARRAY_SIZE(alc5623_mono_mixer_controls)),
+SND_SOC_DAPM_MIXER("Speaker Mix", ALC5623_PWR_MANAG_ADD2, 3, 0,
+        &alc5623_speaker_mixer_controls[0],
+        ARRAY_SIZE(alc5623_speaker_mixer_controls)),
+
+/* input mixers */
+SND_SOC_DAPM_MIXER("Left Capture Mix", ALC5623_PWR_MANAG_ADD2, 1, 0,
+        &alc5623_captureL_mixer_controls[0],
+        ARRAY_SIZE(alc5623_captureL_mixer_controls)),
+SND_SOC_DAPM_MIXER("Right Capture Mix", ALC5623_PWR_MANAG_ADD2, 0, 0,
+        &alc5623_captureR_mixer_controls[0],
+        ARRAY_SIZE(alc5623_captureR_mixer_controls)),
+
+SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
+        ALC5623_PWR_MANAG_ADD2, 9, 0),
+SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
+        ALC5623_PWR_MANAG_ADD2, 8, 0),
+SND_SOC_DAPM_MIXER("I2S Mix", ALC5623_PWR_MANAG_ADD1, 15, 0, NULL, 0),
+SND_SOC_DAPM_MIXER("AuxI Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_MIXER("Line Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
+        ALC5623_PWR_MANAG_ADD2, 7, 0),
+SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
+        ALC5623_PWR_MANAG_ADD2, 6, 0),
+SND_SOC_DAPM_PGA("Left Headphone", ALC5623_PWR_MANAG_ADD3, 10, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Right Headphone", ALC5623_PWR_MANAG_ADD3, 9, 0, NULL, 0),
+SND_SOC_DAPM_PGA("SpeakerOut", ALC5623_PWR_MANAG_ADD3, 12, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Left AuxOut", ALC5623_PWR_MANAG_ADD3, 14, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Right AuxOut", ALC5623_PWR_MANAG_ADD3, 13, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Left LineIn", ALC5623_PWR_MANAG_ADD3, 7, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Right LineIn", ALC5623_PWR_MANAG_ADD3, 6, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Left AuxI", ALC5623_PWR_MANAG_ADD3, 5, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Right AuxI", ALC5623_PWR_MANAG_ADD3, 4, 0, NULL, 0),
+SND_SOC_DAPM_PGA("MIC1 PGA", ALC5623_PWR_MANAG_ADD3, 3, 0, NULL, 0),
+SND_SOC_DAPM_PGA("MIC2 PGA", ALC5623_PWR_MANAG_ADD3, 2, 0, NULL, 0),
+SND_SOC_DAPM_PGA("MIC1 Pre Amp", ALC5623_PWR_MANAG_ADD3, 1, 0, NULL, 0),
+SND_SOC_DAPM_PGA("MIC2 Pre Amp", ALC5623_PWR_MANAG_ADD3, 0, 0, NULL, 0),
+SND_SOC_DAPM_MICBIAS("Mic Bias1", ALC5623_PWR_MANAG_ADD1, 11, 0),
+
+SND_SOC_DAPM_OUTPUT("AUXOUTL"),
+SND_SOC_DAPM_OUTPUT("AUXOUTR"),
+SND_SOC_DAPM_OUTPUT("HPL"),
+SND_SOC_DAPM_OUTPUT("HPR"),
+SND_SOC_DAPM_OUTPUT("SPKOUT"),
+SND_SOC_DAPM_OUTPUT("SPKOUTN"),
+SND_SOC_DAPM_INPUT("LINEINL"),
+SND_SOC_DAPM_INPUT("LINEINR"),
+SND_SOC_DAPM_INPUT("AUXINL"),
+SND_SOC_DAPM_INPUT("AUXINR"),
+SND_SOC_DAPM_INPUT("MIC1"),
+SND_SOC_DAPM_INPUT("MIC2"),
+SND_SOC_DAPM_VMID("Vmid"),
+};
+
+static const char *alc5623_amp_names[] = {"AB Amp", "D Amp"};
+static const struct soc_enum alc5623_amp_enum =
+        SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 13, 2, alc5623_amp_names);
+static const struct snd_kcontrol_new alc5623_amp_mux_controls =
+        SOC_DAPM_ENUM("Route", alc5623_amp_enum);
+
+static const struct snd_soc_dapm_widget alc5623_dapm_amp_widgets[] = {
+SND_SOC_DAPM_PGA_E("D Amp", ALC5623_PWR_MANAG_ADD2, 14, 0, NULL, 0,
+        amp_mixer_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+SND_SOC_DAPM_PGA("AB Amp", ALC5623_PWR_MANAG_ADD2, 15, 0, NULL, 0),
+SND_SOC_DAPM_MUX("AB-D Amp Mux", SND_SOC_NOPM, 0, 0,
+        &alc5623_amp_mux_controls),
+};
+
+static const struct snd_soc_dapm_route intercon[] = {
+        /* virtual mixer - mixes left & right channels */
+        {"I2S Mix", NULL,                               "Left DAC"},
+        {"I2S Mix", NULL,                               "Right DAC"},
+        {"Line Mix", NULL,                              "Right LineIn"},
+        {"Line Mix", NULL,                              "Left LineIn"},
+        {"AuxI Mix", NULL,                              "Left AuxI"},
+        {"AuxI Mix", NULL,                              "Right AuxI"},
+        {"AUXOUTL", NULL,                               "Left AuxOut"},
+        {"AUXOUTR", NULL,                               "Right AuxOut"},
+
+        /* HP mixer */
+        {"HPL Mix", "ADC2HP_L Playback Switch",         "Left Capture Mix"},
+        {"HPL Mix", NULL,                               "HP Mix"},
+        {"HPR Mix", "ADC2HP_R Playback Switch",         "Right Capture Mix"},
+        {"HPR Mix", NULL,                               "HP Mix"},
+        {"HP Mix", "LI2HP Playback Switch",             "Line Mix"},
+        {"HP Mix", "AUXI2HP Playback Switch",           "AuxI Mix"},
+        {"HP Mix", "MIC12HP Playback Switch",           "MIC1 PGA"},
+        {"HP Mix", "MIC22HP Playback Switch",           "MIC2 PGA"},
+        {"HP Mix", "DAC2HP Playback Switch",            "I2S Mix"},
+
+        /* speaker mixer */
+        {"Speaker Mix", "LI2SPK Playback Switch",       "Line Mix"},
+        {"Speaker Mix", "AUXI2SPK Playback Switch",     "AuxI Mix"},
+        {"Speaker Mix", "MIC12SPK Playback Switch",     "MIC1 PGA"},
+        {"Speaker Mix", "MIC22SPK Playback Switch",     "MIC2 PGA"},
+        {"Speaker Mix", "DAC2SPK Playback Switch",      "I2S Mix"},
+
+        /* mono mixer */
+        {"Mono Mix", "ADC2MONO_L Playback Switch",      "Left Capture Mix"},
+        {"Mono Mix", "ADC2MONO_R Playback Switch",      "Right Capture Mix"},
+        {"Mono Mix", "LI2MONO Playback Switch",         "Line Mix"},
+        {"Mono Mix", "AUXI2MONO Playback Switch",       "AuxI Mix"},
+        {"Mono Mix", "MIC12MONO Playback Switch",       "MIC1 PGA"},
+        {"Mono Mix", "MIC22MONO Playback Switch",       "MIC2 PGA"},
+        {"Mono Mix", "DAC2MONO Playback Switch",        "I2S Mix"},
+
+        /* Left record mixer */
+        {"Left Capture Mix", "LineInL Capture Switch",  "LINEINL"},
+        {"Left Capture Mix", "Left AuxI Capture Switch", "AUXINL"},
+        {"Left Capture Mix", "Mic1 Capture Switch",     "MIC1 Pre Amp"},
+        {"Left Capture Mix", "Mic2 Capture Switch",     "MIC2 Pre Amp"},
+        {"Left Capture Mix", "HPMixerL Capture Switch", "HPL Mix"},
+        {"Left Capture Mix", "SPKMixer Capture Switch", "Speaker Mix"},
+        {"Left Capture Mix", "MonoMixer Capture Switch", "Mono Mix"},
+
+        /*Right record mixer */
+        {"Right Capture Mix", "LineInR Capture Switch", "LINEINR"},
+        {"Right Capture Mix", "Right AuxI Capture Switch",      "AUXINR"},
+        {"Right Capture Mix", "Mic1 Capture Switch",    "MIC1 Pre Amp"},
+        {"Right Capture Mix", "Mic2 Capture Switch",    "MIC2 Pre Amp"},
+        {"Right Capture Mix", "HPMixerR Capture Switch", "HPR Mix"},
+        {"Right Capture Mix", "SPKMixer Capture Switch", "Speaker Mix"},
+        {"Right Capture Mix", "MonoMixer Capture Switch", "Mono Mix"},
+
+        /* headphone left mux */
+        {"Left Headphone Mux", "HP Left Mix",           "HPL Mix"},
+        {"Left Headphone Mux", "Vmid",                  "Vmid"},
+
+        /* headphone right mux */
+        {"Right Headphone Mux", "HP Right Mix",         "HPR Mix"},
+        {"Right Headphone Mux", "Vmid",                 "Vmid"},
+
+        /* speaker out mux */
+        {"SpeakerOut Mux", "Vmid",                      "Vmid"},
+        {"SpeakerOut Mux", "HPOut Mix",                 "HPOut Mix"},
+        {"SpeakerOut Mux", "Speaker Mix",               "Speaker Mix"},
+        {"SpeakerOut Mux", "Mono Mix",                  "Mono Mix"},
+
+        /* Mono/Aux Out mux */
+        {"AuxOut Mux", "Vmid",                          "Vmid"},
+        {"AuxOut Mux", "HPOut Mix",                     "HPOut Mix"},
+        {"AuxOut Mux", "Speaker Mix",                   "Speaker Mix"},
+        {"AuxOut Mux", "Mono Mix",                      "Mono Mix"},
+
+        /* output pga */
+        {"HPL", NULL,                                   "Left Headphone"},
+        {"Left Headphone", NULL,                        "Left Headphone Mux"},
+        {"HPR", NULL,                                   "Right Headphone"},
+        {"Right Headphone", NULL,                       "Right Headphone Mux"},
+        {"Left AuxOut", NULL,                           "AuxOut Mux"},
+        {"Right AuxOut", NULL,                          "AuxOut Mux"},
+
+        /* input pga */
+        {"Left LineIn", NULL,                           "LINEINL"},
+        {"Right LineIn", NULL,                          "LINEINR"},
+        {"Left AuxI", NULL,                             "AUXINL"},
+        {"Right AuxI", NULL,                            "AUXINR"},
+        {"MIC1 Pre Amp", NULL,                          "MIC1"},
+        {"MIC2 Pre Amp", NULL,                          "MIC2"},
+        {"MIC1 PGA", NULL,                              "MIC1 Pre Amp"},
+        {"MIC2 PGA", NULL,                              "MIC2 Pre Amp"},
+
+        /* left ADC */
+        {"Left ADC", NULL,                              "Left Capture Mix"},
+
+        /* right ADC */
+        {"Right ADC", NULL,                             "Right Capture Mix"},
+
+        {"SpeakerOut N Mux", "RN/-R",                   "SpeakerOut"},
+        {"SpeakerOut N Mux", "RP/+R",                   "SpeakerOut"},
+        {"SpeakerOut N Mux", "LN/-R",                   "SpeakerOut"},
+        {"SpeakerOut N Mux", "Vmid",                    "Vmid"},
+
+        {"SPKOUT", NULL,                                "SpeakerOut"},
+        {"SPKOUTN", NULL,                               "SpeakerOut N Mux"},
+};
+
+static const struct snd_soc_dapm_route intercon_spk[] = {
+        {"SpeakerOut", NULL,                            "SpeakerOut Mux"},
+};
+
+static const struct snd_soc_dapm_route intercon_amp_spk[] = {
+        {"AB Amp", NULL,                                "SpeakerOut Mux"},
+        {"D Amp", NULL,                                 "SpeakerOut Mux"},
+        {"AB-D Amp Mux", "AB Amp",                      "AB Amp"},
+        {"AB-D Amp Mux", "D Amp",                       "D Amp"},
+        {"SpeakerOut", NULL,                            "AB-D Amp Mux"},
+};
+
+/* PLL divisors */
+struct _pll_div {
+        u32 pll_in;
+        u32 pll_out;
+        u16 regvalue;
+};
+
+/* Note : pll code from original alc5623 driver. Not sure of how good it is */
+/* useful only for master mode */
+static const struct _pll_div codec_master_pll_div[] = {
+
+        {  2048000,  8192000,   0x0ea0},
+        {  3686400,  8192000,   0x4e27},
+        { 12000000,  8192000,   0x456b},
+        { 13000000,  8192000,   0x495f},
+        { 13100000,  8192000,   0x0320},
+        {  2048000,  11289600,  0xf637},
+        {  3686400,  11289600,  0x2f22},
+        { 12000000,  11289600,  0x3e2f},
+        { 13000000,  11289600,  0x4d5b},
+        { 13100000,  11289600,  0x363b},
+        {  2048000,  16384000,  0x1ea0},
+        {  3686400,  16384000,  0x9e27},
+        { 12000000,  16384000,  0x452b},
+        { 13000000,  16384000,  0x542f},
+        { 13100000,  16384000,  0x03a0},
+        {  2048000,  16934400,  0xe625},
+        {  3686400,  16934400,  0x9126},
+        { 12000000,  16934400,  0x4d2c},
+        { 13000000,  16934400,  0x742f},
+        { 13100000,  16934400,  0x3c27},
+        {  2048000,  22579200,  0x2aa0},
+        {  3686400,  22579200,  0x2f20},
+        { 12000000,  22579200,  0x7e2f},
+        { 13000000,  22579200,  0x742f},
+        { 13100000,  22579200,  0x3c27},
+        {  2048000,  24576000,  0x2ea0},
+        {  3686400,  24576000,  0xee27},
+        { 12000000,  24576000,  0x2915},
+        { 13000000,  24576000,  0x772e},
+        { 13100000,  24576000,  0x0d20},
+};
+
+static const struct _pll_div codec_slave_pll_div[] = {
+
+        {  1024000,  16384000,  0x3ea0},
+        {  1411200,  22579200,  0x3ea0},
+        {  1536000,  24576000,  0x3ea0},
+        {  2048000,  16384000,  0x1ea0},
+        {  2822400,  22579200,  0x1ea0},
+        {  3072000,  24576000,  0x1ea0},
+
+};
+
+static int alc5623_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
+                int source, unsigned int freq_in, unsigned int freq_out)
+{
+        int i;
+        struct snd_soc_codec *codec = codec_dai->codec;
+        int gbl_clk = 0, pll_div = 0;
+        u16 reg;
+
+        if (pll_id < ALC5623_PLL_FR_MCLK || pll_id > ALC5623_PLL_FR_BCK)
+                return -ENODEV;
+
+        /* Disable PLL power */
+        snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD2,
+                                ALC5623_PWR_ADD2_PLL,
+                                0);
+
+        /* pll is not used in slave mode */
+        reg = snd_soc_read(codec, ALC5623_DAI_CONTROL);
+        if (reg & ALC5623_DAI_SDP_SLAVE_MODE)
+                return 0;
+
+        if (!freq_in || !freq_out)
+                return 0;
+
+        switch (pll_id) {
+        case ALC5623_PLL_FR_MCLK:
+                for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++) {
+                        if (codec_master_pll_div[i].pll_in == freq_in
+                           && codec_master_pll_div[i].pll_out == freq_out) {
+                                /* PLL source from MCLK */
+                                pll_div  = codec_master_pll_div[i].regvalue;
+                                break;
+                        }
+                }
+                break;
+        case ALC5623_PLL_FR_BCK:
+                for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++) {
+                        if (codec_slave_pll_div[i].pll_in == freq_in
+                           && codec_slave_pll_div[i].pll_out == freq_out) {
+                                /* PLL source from Bitclk */
+                                gbl_clk = ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK;
+                                pll_div = codec_slave_pll_div[i].regvalue;
+                                break;
+                        }
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (!pll_div)
+                return -EINVAL;
+
+        snd_soc_write(codec, ALC5623_GLOBAL_CLK_CTRL_REG, gbl_clk);
+        snd_soc_write(codec, ALC5623_PLL_CTRL, pll_div);
+        snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD2,
+                                ALC5623_PWR_ADD2_PLL,
+                                ALC5623_PWR_ADD2_PLL);
+        gbl_clk |= ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL;
+        snd_soc_write(codec, ALC5623_GLOBAL_CLK_CTRL_REG, gbl_clk);
+
+        return 0;
+}
+
+struct _coeff_div {
+        u16 fs;
+        u16 regvalue;
+};
+
+/* codec hifi mclk (after PLL) clock divider coefficients */
+/* values inspired from column BCLK=32Fs of Appendix A table */
+static const struct _coeff_div coeff_div[] = {
+        {256*8, 0x3a69},
+        {384*8, 0x3c6b},
+        {256*4, 0x2a69},
+        {384*4, 0x2c6b},
+        {256*2, 0x1a69},
+        {384*2, 0x1c6b},
+        {256*1, 0x0a69},
+        {384*1, 0x0c6b},
+};
+
+static int get_coeff(struct snd_soc_codec *codec, int rate)
+{
+        struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
+                if (coeff_div[i].fs * rate == alc5623->sysclk)
+                        return i;
+        }
+        return -EINVAL;
+}
+
+/*
+ * Clock after PLL and dividers
+ */
+static int alc5623_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
+
+        switch (freq) {
+        case  8192000:
+        case 11289600:
+        case 12288000:
+        case 16384000:
+        case 16934400:
+        case 18432000:
+        case 22579200:
+        case 24576000:
+                alc5623->sysclk = freq;
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static int alc5623_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        u16 iface = 0;
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                iface = ALC5623_DAI_SDP_MASTER_MODE;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                iface = ALC5623_DAI_SDP_SLAVE_MODE;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* interface format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                iface |= ALC5623_DAI_I2S_DF_I2S;
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                iface |= ALC5623_DAI_I2S_DF_RIGHT;
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                iface |= ALC5623_DAI_I2S_DF_LEFT;
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+                iface |= ALC5623_DAI_I2S_DF_PCM;
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                iface |= ALC5623_DAI_I2S_DF_PCM | ALC5623_DAI_I2S_PCM_MODE;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* clock inversion */
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_IF:
+                iface |= ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL;
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                iface |= ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL;
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return snd_soc_write(codec, ALC5623_DAI_CONTROL, iface);
+}
+
+static int alc5623_pcm_hw_params(struct snd_pcm_substream *substream,
+                struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
+        int coeff, rate;
+        u16 iface;
+
+        iface = snd_soc_read(codec, ALC5623_DAI_CONTROL);
+        iface &= ~ALC5623_DAI_I2S_DL_MASK;
+
+        /* bit size */
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                iface |= ALC5623_DAI_I2S_DL_16;
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                iface |= ALC5623_DAI_I2S_DL_20;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                iface |= ALC5623_DAI_I2S_DL_24;
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                iface |= ALC5623_DAI_I2S_DL_32;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* set iface & srate */
+        snd_soc_write(codec, ALC5623_DAI_CONTROL, iface);
+        rate = params_rate(params);
+        coeff = get_coeff(codec, rate);
+        if (coeff < 0)
+                return -EINVAL;
+
+        coeff = coeff_div[coeff].regvalue;
+        dev_dbg(codec->dev, "%s: sysclk=%d,rate=%d,coeff=0x%04x\n",
+                __func__, alc5623->sysclk, rate, coeff);
+        snd_soc_write(codec, ALC5623_STEREO_AD_DA_CLK_CTRL, coeff);
+
+        return 0;
+}
+
+static int alc5623_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        u16 hp_mute = ALC5623_MISC_M_DAC_L_INPUT | ALC5623_MISC_M_DAC_R_INPUT;
+        u16 mute_reg = snd_soc_read(codec, ALC5623_MISC_CTRL) & ~hp_mute;
+
+        if (mute)
+                mute_reg |= hp_mute;
+
+        return snd_soc_write(codec, ALC5623_MISC_CTRL, mute_reg);
+}
+
+#define ALC5623_ADD2_POWER_EN (ALC5623_PWR_ADD2_VREF \
+        | ALC5623_PWR_ADD2_DAC_REF_CIR)
+
+#define ALC5623_ADD3_POWER_EN (ALC5623_PWR_ADD3_MAIN_BIAS \
+        | ALC5623_PWR_ADD3_MIC1_BOOST_AD)
+
+#define ALC5623_ADD1_POWER_EN \
+        (ALC5623_PWR_ADD1_SHORT_CURR_DET_EN | ALC5623_PWR_ADD1_SOFTGEN_EN \
+        | ALC5623_PWR_ADD1_DEPOP_BUF_HP | ALC5623_PWR_ADD1_HP_OUT_AMP \
+        | ALC5623_PWR_ADD1_HP_OUT_ENH_AMP)
+
+#define ALC5623_ADD1_POWER_EN_5622 \
+        (ALC5623_PWR_ADD1_SHORT_CURR_DET_EN \
+        | ALC5623_PWR_ADD1_HP_OUT_AMP)
+
+static void enable_power_depop(struct snd_soc_codec *codec)
+{
+        struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
+
+        snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD1,
+                                ALC5623_PWR_ADD1_SOFTGEN_EN,
+                                ALC5623_PWR_ADD1_SOFTGEN_EN);
+
+        snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3, ALC5623_ADD3_POWER_EN);
+
+        snd_soc_update_bits(codec, ALC5623_MISC_CTRL,
+                                ALC5623_MISC_HP_DEPOP_MODE2_EN,
+                                ALC5623_MISC_HP_DEPOP_MODE2_EN);
+
+        msleep(500);
+
+        snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2, ALC5623_ADD2_POWER_EN);
+
+        /* avoid writing '1' into 5622 reserved bits */
+        if (alc5623->id == 0x22)
+                snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1,
+                        ALC5623_ADD1_POWER_EN_5622);
+        else
+                snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1,
+                        ALC5623_ADD1_POWER_EN);
+
+        /* disable HP Depop2 */
+        snd_soc_update_bits(codec, ALC5623_MISC_CTRL,
+                                ALC5623_MISC_HP_DEPOP_MODE2_EN,
+                                0);
+
+}
+
+static int alc5623_set_bias_level(struct snd_soc_codec *codec,
+                                      enum snd_soc_bias_level level)
+{
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                enable_power_depop(codec);
+                break;
+        case SND_SOC_BIAS_PREPARE:
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                /* everything off except vref/vmid, */
+                snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2,
+                                ALC5623_PWR_ADD2_VREF);
+                snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3,
+                                ALC5623_PWR_ADD3_MAIN_BIAS);
+                break;
+        case SND_SOC_BIAS_OFF:
+                /* everything off, dac mute, inactive */
+                snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2, 0);
+                snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3, 0);
+                snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1, 0);
+                break;
+        }
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#define ALC5623_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \
+                        | SNDRV_PCM_FMTBIT_S24_LE \
+                        | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops alc5623_dai_ops = {
+                .hw_params = alc5623_pcm_hw_params,
+                .digital_mute = alc5623_mute,
+                .set_fmt = alc5623_set_dai_fmt,
+                .set_sysclk = alc5623_set_dai_sysclk,
+                .set_pll = alc5623_set_dai_pll,
+};
+
+static struct snd_soc_dai_driver alc5623_dai = {
+        .name = "alc5623-hifi",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rate_min =     8000,
+                .rate_max =     48000,
+                .rates = SNDRV_PCM_RATE_8000_48000,
+                .formats = ALC5623_FORMATS,},
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rate_min =     8000,
+                .rate_max =     48000,
+                .rates = SNDRV_PCM_RATE_8000_48000,
+                .formats = ALC5623_FORMATS,},
+
+        .ops = &alc5623_dai_ops,
+};
+
+static int alc5623_suspend(struct snd_soc_codec *codec, pm_message_t mesg)
+{
+        alc5623_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int alc5623_resume(struct snd_soc_codec *codec)
+{
+        int i, step = codec->driver->reg_cache_step;
+        u16 *cache = codec->reg_cache;
+
+        /* Sync reg_cache with the hardware */
+        for (i = 2 ; i < codec->driver->reg_cache_size ; i += step)
+                snd_soc_write(codec, i, cache[i]);
+
+        alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        /* charge alc5623 caps */
+        if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) {
+                alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+                codec->dapm.bias_level = SND_SOC_BIAS_ON;
+                alc5623_set_bias_level(codec, codec->dapm.bias_level);
+        }
+
+        return 0;
+}
+
+static int alc5623_probe(struct snd_soc_codec *codec)
+{
+        struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret;
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, alc5623->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        alc5623_reset(codec);
+        alc5623_fill_cache(codec);
+
+        /* power on device */
+        alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        if (alc5623->add_ctrl) {
+                snd_soc_write(codec, ALC5623_ADD_CTRL_REG,
+                                alc5623->add_ctrl);
+        }
+
+        if (alc5623->jack_det_ctrl) {
+                snd_soc_write(codec, ALC5623_JACK_DET_CTRL,
+                                alc5623->jack_det_ctrl);
+        }
+
+        switch (alc5623->id) {
+        case 0x21:
+                snd_soc_add_controls(codec, rt5621_vol_snd_controls,
+                        ARRAY_SIZE(rt5621_vol_snd_controls));
+                break;
+        case 0x22:
+                snd_soc_add_controls(codec, rt5622_vol_snd_controls,
+                        ARRAY_SIZE(rt5622_vol_snd_controls));
+                break;
+        case 0x23:
+                snd_soc_add_controls(codec, alc5623_vol_snd_controls,
+                        ARRAY_SIZE(alc5623_vol_snd_controls));
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_add_controls(codec, alc5623_snd_controls,
+                        ARRAY_SIZE(alc5623_snd_controls));
+
+        snd_soc_dapm_new_controls(dapm, alc5623_dapm_widgets,
+                                        ARRAY_SIZE(alc5623_dapm_widgets));
+
+        /* set up audio path interconnects */
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
+
+        switch (alc5623->id) {
+        case 0x21:
+        case 0x22:
+                snd_soc_dapm_new_controls(dapm, alc5623_dapm_amp_widgets,
+                                        ARRAY_SIZE(alc5623_dapm_amp_widgets));
+                snd_soc_dapm_add_routes(dapm, intercon_amp_spk,
+                                        ARRAY_SIZE(intercon_amp_spk));
+                break;
+        case 0x23:
+                snd_soc_dapm_add_routes(dapm, intercon_spk,
+                                        ARRAY_SIZE(intercon_spk));
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return ret;
+}
+
+/* power down chip */
+static int alc5623_remove(struct snd_soc_codec *codec)
+{
+        alc5623_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_device_alc5623 = {
+        .probe = alc5623_probe,
+        .remove = alc5623_remove,
+        .suspend = alc5623_suspend,
+        .resume = alc5623_resume,
+        .set_bias_level = alc5623_set_bias_level,
+        .reg_cache_size = ALC5623_VENDOR_ID2+2,
+        .reg_word_size = sizeof(u16),
+        .reg_cache_step = 2,
+};
+
+/*
+ * ALC5623 2 wire address is determined by A1 pin
+ * state during powerup.
+ *    low  = 0x1a
+ *    high = 0x1b
+ */
+static int alc5623_i2c_probe(struct i2c_client *client,
+                                const struct i2c_device_id *id)
+{
+        struct alc5623_platform_data *pdata;
+        struct alc5623_priv *alc5623;
+        int ret, vid1, vid2;
+
+        vid1 = i2c_smbus_read_word_data(client, ALC5623_VENDOR_ID1);
+        if (vid1 < 0) {
+                dev_err(&client->dev, "failed to read I2C\n");
+                return -EIO;
+        }
+        vid1 = ((vid1 & 0xff) << 8) | (vid1 >> 8);
+
+        vid2 = i2c_smbus_read_byte_data(client, ALC5623_VENDOR_ID2);
+        if (vid2 < 0) {
+                dev_err(&client->dev, "failed to read I2C\n");
+                return -EIO;
+        }
+
+        if ((vid1 != 0x10ec) || (vid2 != id->driver_data)) {
+                dev_err(&client->dev, "unknown or wrong codec\n");
+                dev_err(&client->dev, "Expected %x:%lx, got %x:%x\n",
+                                0x10ec, id->driver_data,
+                                vid1, vid2);
+                return -ENODEV;
+        }
+
+        dev_dbg(&client->dev, "Found codec id : alc56%02x\n", vid2);
+
+        alc5623 = kzalloc(sizeof(struct alc5623_priv), GFP_KERNEL);
+        if (alc5623 == NULL)
+                return -ENOMEM;
+
+        pdata = client->dev.platform_data;
+        if (pdata) {
+                alc5623->add_ctrl = pdata->add_ctrl;
+                alc5623->jack_det_ctrl = pdata->jack_det_ctrl;
+        }
+
+        alc5623->id = vid2;
+        switch (alc5623->id) {
+        case 0x21:
+                alc5623_dai.name = "alc5621-hifi";
+                break;
+        case 0x22:
+                alc5623_dai.name = "alc5622-hifi";
+                break;
+        case 0x23:
+                alc5623_dai.name = "alc5623-hifi";
+                break;
+        default:
+                kfree(alc5623);
+                return -EINVAL;
+        }
+
+        i2c_set_clientdata(client, alc5623);
+        alc5623->control_data = client;
+        alc5623->control_type = SND_SOC_I2C;
+        mutex_init(&alc5623->mutex);
+
+        ret =  snd_soc_register_codec(&client->dev,
+                &soc_codec_device_alc5623, &alc5623_dai, 1);
+        if (ret != 0) {
+                dev_err(&client->dev, "Failed to register codec: %d\n", ret);
+                kfree(alc5623);
+        }
+
+        return ret;
+}
+
+static int alc5623_i2c_remove(struct i2c_client *client)
+{
+        struct alc5623_priv *alc5623 = i2c_get_clientdata(client);
+
+        snd_soc_unregister_codec(&client->dev);
+        kfree(alc5623);
+        return 0;
+}
+
+static const struct i2c_device_id alc5623_i2c_table[] = {
+        {"alc5621", 0x21},
+        {"alc5622", 0x22},
+        {"alc5623", 0x23},
+        {}
+};
+MODULE_DEVICE_TABLE(i2c, alc5623_i2c_table);
+
+/*  i2c codec control layer */
+static struct i2c_driver alc5623_i2c_driver = {
+        .driver = {
+                .name = "alc562x-codec",
+                .owner = THIS_MODULE,
+        },
+        .probe = alc5623_i2c_probe,
+        .remove =  __devexit_p(alc5623_i2c_remove),
+        .id_table = alc5623_i2c_table,
+};
+
+static int __init alc5623_modinit(void)
+{
+        int ret;
+
+        ret = i2c_add_driver(&alc5623_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "%s: can't add i2c driver", __func__);
+                return ret;
+        }
+
+        return ret;
+}
+module_init(alc5623_modinit);
+
+static void __exit alc5623_modexit(void)
+{
+        i2c_del_driver(&alc5623_i2c_driver);
+}
+module_exit(alc5623_modexit);
+
+MODULE_DESCRIPTION("ASoC alc5621/2/3 driver");
+MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/alc5623.h b/sound/soc/codecs/alc5623.h
new file mode 100644
index 000000000000..f3d68260d425
--- /dev/null
+++ b/sound/soc/codecs/alc5623.h
@@ -0,0 +1,161 @@
+/*
+ * alc5623.h  --  alc562[123] ALSA Soc Audio driver
+ *
+ * Copyright 2008 Realtek Microelectronics
+ * Copyright 2010 Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * Author: flove <flove@realtek.com>
+ * Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ALC5623_H
+#define _ALC5623_H
+
+#define ALC5623_RESET                           0x00
+/*                              5621 5622 5623  */
+/* speaker output vol              2    2       */
+/* line output vol                      4    2  */
+/* HP output vol                   4    0    4  */
+#define ALC5623_SPK_OUT_VOL                     0x02
+#define ALC5623_HP_OUT_VOL                      0x04
+#define ALC5623_MONO_AUX_OUT_VOL                0x06
+#define ALC5623_AUXIN_VOL                       0x08
+#define ALC5623_LINE_IN_VOL                     0x0A
+#define ALC5623_STEREO_DAC_VOL                  0x0C
+#define ALC5623_MIC_VOL                         0x0E
+#define ALC5623_MIC_ROUTING_CTRL                0x10
+#define ALC5623_ADC_REC_GAIN                    0x12
+#define ALC5623_ADC_REC_MIXER                   0x14
+#define ALC5623_SOFT_VOL_CTRL_TIME              0x16
+/* ALC5623_OUTPUT_MIXER_CTRL :                  */
+/* same remark as for reg 2 line vs speaker     */
+#define ALC5623_OUTPUT_MIXER_CTRL               0x1C
+#define ALC5623_MIC_CTRL                        0x22
+
+#define ALC5623_DAI_CONTROL                     0x34
+#define ALC5623_DAI_SDP_MASTER_MODE             (0 << 15)
+#define ALC5623_DAI_SDP_SLAVE_MODE              (1 << 15)
+#define ALC5623_DAI_I2S_PCM_MODE                (1 << 14)
+#define ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL      (1 <<  7)
+#define ALC5623_DAI_ADC_DATA_L_R_SWAP           (1 <<  5)
+#define ALC5623_DAI_DAC_DATA_L_R_SWAP           (1 <<  4)
+#define ALC5623_DAI_I2S_DL_MASK                 (3 <<  2)
+#define ALC5623_DAI_I2S_DL_32                   (3 <<  2)
+#define ALC5623_DAI_I2S_DL_24                   (2 <<  2)
+#define ALC5623_DAI_I2S_DL_20                   (1 <<  2)
+#define ALC5623_DAI_I2S_DL_16                   (0 <<  2)
+#define ALC5623_DAI_I2S_DF_PCM                  (3 <<  0)
+#define ALC5623_DAI_I2S_DF_LEFT                 (2 <<  0)
+#define ALC5623_DAI_I2S_DF_RIGHT                (1 <<  0)
+#define ALC5623_DAI_I2S_DF_I2S                  (0 <<  0)
+
+#define ALC5623_STEREO_AD_DA_CLK_CTRL           0x36
+#define ALC5623_COMPANDING_CTRL                 0x38
+
+#define ALC5623_PWR_MANAG_ADD1                  0x3A
+#define ALC5623_PWR_ADD1_MAIN_I2S_EN            (1 << 15)
+#define ALC5623_PWR_ADD1_ZC_DET_PD_EN           (1 << 14)
+#define ALC5623_PWR_ADD1_MIC1_BIAS_EN           (1 << 11)
+#define ALC5623_PWR_ADD1_SHORT_CURR_DET_EN      (1 << 10)
+#define ALC5623_PWR_ADD1_SOFTGEN_EN             (1 <<  8) /* rsvd on 5622 */
+#define ALC5623_PWR_ADD1_DEPOP_BUF_HP           (1 <<  6) /* rsvd on 5622 */
+#define ALC5623_PWR_ADD1_HP_OUT_AMP             (1 <<  5)
+#define ALC5623_PWR_ADD1_HP_OUT_ENH_AMP         (1 <<  4) /* rsvd on 5622 */
+#define ALC5623_PWR_ADD1_DEPOP_BUF_AUX          (1 <<  2)
+#define ALC5623_PWR_ADD1_AUX_OUT_AMP            (1 <<  1)
+#define ALC5623_PWR_ADD1_AUX_OUT_ENH_AMP        (1 <<  0) /* rsvd on 5622 */
+
+#define ALC5623_PWR_MANAG_ADD2                  0x3C
+#define ALC5623_PWR_ADD2_LINEOUT                (1 << 15) /* rt5623 */
+#define ALC5623_PWR_ADD2_CLASS_AB               (1 << 15) /* rt5621 */
+#define ALC5623_PWR_ADD2_CLASS_D                (1 << 14) /* rt5621 */
+#define ALC5623_PWR_ADD2_VREF                   (1 << 13)
+#define ALC5623_PWR_ADD2_PLL                    (1 << 12)
+#define ALC5623_PWR_ADD2_DAC_REF_CIR            (1 << 10)
+#define ALC5623_PWR_ADD2_L_DAC_CLK              (1 <<  9)
+#define ALC5623_PWR_ADD2_R_DAC_CLK              (1 <<  8)
+#define ALC5623_PWR_ADD2_L_ADC_CLK_GAIN         (1 <<  7)
+#define ALC5623_PWR_ADD2_R_ADC_CLK_GAIN         (1 <<  6)
+#define ALC5623_PWR_ADD2_L_HP_MIXER             (1 <<  5)
+#define ALC5623_PWR_ADD2_R_HP_MIXER             (1 <<  4)
+#define ALC5623_PWR_ADD2_SPK_MIXER              (1 <<  3)
+#define ALC5623_PWR_ADD2_MONO_MIXER             (1 <<  2)
+#define ALC5623_PWR_ADD2_L_ADC_REC_MIXER        (1 <<  1)
+#define ALC5623_PWR_ADD2_R_ADC_REC_MIXER        (1 <<  0)
+
+#define ALC5623_PWR_MANAG_ADD3                  0x3E
+#define ALC5623_PWR_ADD3_MAIN_BIAS              (1 << 15)
+#define ALC5623_PWR_ADD3_AUXOUT_L_VOL_AMP       (1 << 14)
+#define ALC5623_PWR_ADD3_AUXOUT_R_VOL_AMP       (1 << 13)
+#define ALC5623_PWR_ADD3_SPK_OUT                (1 << 12)
+#define ALC5623_PWR_ADD3_HP_L_OUT_VOL           (1 << 10)
+#define ALC5623_PWR_ADD3_HP_R_OUT_VOL           (1 <<  9)
+#define ALC5623_PWR_ADD3_LINEIN_L_VOL           (1 <<  7)
+#define ALC5623_PWR_ADD3_LINEIN_R_VOL           (1 <<  6)
+#define ALC5623_PWR_ADD3_AUXIN_L_VOL            (1 <<  5)
+#define ALC5623_PWR_ADD3_AUXIN_R_VOL            (1 <<  4)
+#define ALC5623_PWR_ADD3_MIC1_FUN_CTRL          (1 <<  3)
+#define ALC5623_PWR_ADD3_MIC2_FUN_CTRL          (1 <<  2)
+#define ALC5623_PWR_ADD3_MIC1_BOOST_AD          (1 <<  1)
+#define ALC5623_PWR_ADD3_MIC2_BOOST_AD          (1 <<  0)
+
+#define ALC5623_ADD_CTRL_REG                    0x40
+
+#define ALC5623_GLOBAL_CLK_CTRL_REG             0x42
+#define ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL        (1 << 15)
+#define ALC5623_GBL_CLK_SYS_SOUR_SEL_MCLK       (0 << 15)
+#define ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK     (1 << 14)
+#define ALC5623_GBL_CLK_PLL_SOUR_SEL_MCLK       (0 << 14)
+#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV8      (3 <<  1)
+#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV4      (2 <<  1)
+#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV2      (1 <<  1)
+#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV1      (0 <<  1)
+#define ALC5623_GBL_CLK_PLL_PRE_DIV2            (1 <<  0)
+#define ALC5623_GBL_CLK_PLL_PRE_DIV1            (0 <<  0)
+
+#define ALC5623_PLL_CTRL                        0x44
+#define ALC5623_PLL_CTRL_N_VAL(n)               (((n)&0xff) << 8)
+#define ALC5623_PLL_CTRL_K_VAL(k)               (((k)&0x7)  << 4)
+#define ALC5623_PLL_CTRL_M_VAL(m)               ((m)&0xf)
+
+#define ALC5623_GPIO_OUTPUT_PIN_CTRL            0x4A
+#define ALC5623_GPIO_PIN_CONFIG                 0x4C
+#define ALC5623_GPIO_PIN_POLARITY               0x4E
+#define ALC5623_GPIO_PIN_STICKY                 0x50
+#define ALC5623_GPIO_PIN_WAKEUP                 0x52
+#define ALC5623_GPIO_PIN_STATUS                 0x54
+#define ALC5623_GPIO_PIN_SHARING                0x56
+#define ALC5623_OVER_CURR_STATUS                0x58
+#define ALC5623_JACK_DET_CTRL                   0x5A
+
+#define ALC5623_MISC_CTRL                       0x5E
+#define ALC5623_MISC_DISABLE_FAST_VREG          (1 << 15)
+#define ALC5623_MISC_SPK_CLASS_AB_OC_PD         (1 << 13) /* 5621 */
+#define ALC5623_MISC_SPK_CLASS_AB_OC_DET        (1 << 12) /* 5621 */
+#define ALC5623_MISC_HP_DEPOP_MODE3_EN          (1 << 10)
+#define ALC5623_MISC_HP_DEPOP_MODE2_EN          (1 <<  9)
+#define ALC5623_MISC_HP_DEPOP_MODE1_EN          (1 <<  8)
+#define ALC5623_MISC_AUXOUT_DEPOP_MODE3_EN      (1 <<  6)
+#define ALC5623_MISC_AUXOUT_DEPOP_MODE2_EN      (1 <<  5)
+#define ALC5623_MISC_AUXOUT_DEPOP_MODE1_EN      (1 <<  4)
+#define ALC5623_MISC_M_DAC_L_INPUT              (1 <<  3)
+#define ALC5623_MISC_M_DAC_R_INPUT              (1 <<  2)
+#define ALC5623_MISC_IRQOUT_INV_CTRL            (1 <<  0)
+
+#define ALC5623_PSEDUEO_SPATIAL_CTRL            0x60
+#define ALC5623_EQ_CTRL                         0x62
+#define ALC5623_EQ_MODE_ENABLE                  0x66
+#define ALC5623_AVC_CTRL                        0x68
+#define ALC5623_HID_CTRL_INDEX                  0x6A
+#define ALC5623_HID_CTRL_DATA                   0x6C
+#define ALC5623_VENDOR_ID1                      0x7C
+#define ALC5623_VENDOR_ID2                      0x7E
+
+#define ALC5623_PLL_FR_MCLK                     0
+#define ALC5623_PLL_FR_BCK                      1
+#endif
diff --git a/sound/soc/codecs/cq93vc.c b/sound/soc/codecs/cq93vc.c
index a320fb5a0e26..46dbfd067f79 100644
--- a/sound/soc/codecs/cq93vc.c
+++ b/sound/soc/codecs/cq93vc.c
@@ -30,19 +30,16 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/mfd/davinci_voicecodec.h>
+#include <linux/spi/spi.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dai.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 
 #include <mach/dm365.h>
 
-#include "cq93vc.h"
-
 static inline unsigned int cq93vc_read(struct snd_soc_codec *codec,
                                                 unsigned int reg)
 {
@@ -117,7 +114,7 @@ static int cq93vc_set_bias_level(struct snd_soc_codec *codec,
                              DAVINCI_VC_REG12_POWER_ALL_OFF);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -130,8 +127,8 @@ static struct snd_soc_dai_ops cq93vc_dai_ops = {
         .set_sysclk     = cq93vc_set_dai_sysclk,
 };
 
-struct snd_soc_dai cq93vc_dai = {
-        .name = "CQ93VC",
+static struct snd_soc_dai_driver cq93vc_dai = {
+        .name = "cq93vc-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -146,36 +143,20 @@ struct snd_soc_dai cq93vc_dai = {
                 .formats = CQ93VC_FORMATS,},
         .ops = &cq93vc_dai_ops,
 };
-EXPORT_SYMBOL_GPL(cq93vc_dai);
 
-static int cq93vc_resume(struct platform_device *pdev)
+static int cq93vc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         cq93vc_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
 }
 
-static struct snd_soc_codec *cq93vc_codec;
-
-static int cq93vc_probe(struct platform_device *pdev)
+static int cq93vc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct device *dev = &pdev->dev;
-        struct snd_soc_codec *codec;
-        int ret;
-
-        socdev->card->codec = cq93vc_codec;
-        codec = socdev->card->codec;
-
-        /* Register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(dev, "%s: failed to create pcms\n", pdev->name);
-                return ret;
-        }
+        struct davinci_vc *davinci_vc = codec->dev->platform_data;
+
+        davinci_vc->cq93vc.codec = codec;
+        codec->control_data = davinci_vc;
 
         /* Set controls */
         snd_soc_add_controls(codec, cq93vc_snd_controls,
@@ -187,108 +168,51 @@ static int cq93vc_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int cq93vc_remove(struct platform_device *pdev)
+static int cq93vc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
+        cq93vc_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_cq93vc = {
+static struct snd_soc_codec_driver soc_codec_dev_cq93vc = {
+        .read = cq93vc_read,
+        .write = cq93vc_write,
+        .set_bias_level = cq93vc_set_bias_level,
         .probe = cq93vc_probe,
         .remove = cq93vc_remove,
         .resume = cq93vc_resume,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_cq93vc);
 
-static __init int cq93vc_codec_probe(struct platform_device *pdev)
+static int cq93vc_platform_probe(struct platform_device *pdev)
 {
-        struct davinci_vc *davinci_vc = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret;
-
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL) {
-                dev_dbg(davinci_vc->dev,
-                        "could not allocate memory for codec data\n");
-                return -ENOMEM;
-        }
-
-        davinci_vc->cq93vc.codec = codec;
-
-        cq93vc_dai.dev = &pdev->dev;
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-        codec->dev = &pdev->dev;
-        codec->name = "CQ93VC";
-        codec->owner = THIS_MODULE;
-        codec->read = cq93vc_read;
-        codec->write = cq93vc_write;
-        codec->set_bias_level = cq93vc_set_bias_level;
-        codec->dai = &cq93vc_dai;
-        codec->num_dai = 1;
-        codec->control_data = davinci_vc;
-
-        cq93vc_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret) {
-                dev_err(davinci_vc->dev, "failed to register codec\n");
-                goto fail1;
-        }
-
-        ret = snd_soc_register_dai(&cq93vc_dai);
-        if (ret) {
-                dev_err(davinci_vc->dev, "could register dai\n");
-                goto fail2;
-        }
-        return 0;
-
-fail2:
-        snd_soc_unregister_codec(codec);
-
-fail1:
-        kfree(codec);
-        cq93vc_codec = NULL;
-
-        return ret;
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_cq93vc, &cq93vc_dai, 1);
 }
 
-static int __devexit cq93vc_codec_remove(struct platform_device *pdev)
+static int cq93vc_platform_remove(struct platform_device *pdev)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        snd_soc_unregister_dai(&cq93vc_dai);
-        snd_soc_unregister_codec(&codec);
-
-        kfree(codec);
-        cq93vc_codec = NULL;
-
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
 static struct platform_driver cq93vc_codec_driver = {
         .driver = {
-                   .name = "cq93vc",
-                   .owner = THIS_MODULE,
-                   },
-        .probe = cq93vc_codec_probe,
-        .remove = __devexit_p(cq93vc_codec_remove),
+                        .name = "cq93vc-codec",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = cq93vc_platform_probe,
+        .remove = __devexit_p(cq93vc_platform_remove),
 };
 
-static __init int cq93vc_init(void)
+static int __init cq93vc_init(void)
 {
-        return platform_driver_probe(&cq93vc_codec_driver, cq93vc_codec_probe);
+        return platform_driver_register(&cq93vc_codec_driver);
 }
 module_init(cq93vc_init);
 
-static __exit void cq93vc_exit(void)
+static void __exit cq93vc_exit(void)
 {
         platform_driver_unregister(&cq93vc_codec_driver);
 }
diff --git a/sound/soc/codecs/cq93vc.h b/sound/soc/codecs/cq93vc.h
deleted file mode 100644
index 845b1968ef9c..000000000000
--- a/sound/soc/codecs/cq93vc.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * ALSA SoC CQ0093 Voice Codec Driver for DaVinci platforms
- *
- * Copyright (C) 2010 Texas Instruments, Inc
- *
- * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef _CQ93VC_H
-#define _CQ93VC_H
-
-extern struct snd_soc_dai cq93vc_dai;
-extern struct snd_soc_codec_device soc_codec_dev_cq93vc;
-
-#endif
diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c
index 30d949239def..0206a17d7283 100644
--- a/sound/soc/codecs/cs4270.c
+++ b/sound/soc/codecs/cs4270.c
@@ -31,8 +31,6 @@
 #include <linux/delay.h>
 #include <linux/regulator/consumer.h>
 
-#include "cs4270.h"
-
 /*
  * The codec isn't really big-endian or little-endian, since the I2S
  * interface requires data to be sent serially with the MSbit first.
@@ -108,14 +106,29 @@
 #define CS4270_MUTE_DAC_A       0x01
 #define CS4270_MUTE_DAC_B       0x02
 
+/* Power-on default values for the registers
+ *
+ * This array contains the power-on default values of the registers, with the
+ * exception of the "CHIPID" register (01h).  The lower four bits of that
+ * register contain the hardware revision, so it is treated as volatile.
+ *
+ * Also note that on the CS4270, the first readable register is 1, but ASoC
+ * assumes the first register is 0.  Therfore, the array must have an entry for
+ * register 0, but we use cs4270_reg_is_readable() to tell ASoC that it can't
+ * be read.
+ */
+static const u8 cs4270_default_reg_cache[CS4270_LASTREG + 1] = {
+        0x00, 0x00, 0x00, 0x30, 0x00, 0x60, 0x20, 0x00, 0x00
+};
+
 static const char *supply_names[] = {
         "va", "vd", "vlc"
 };
 
 /* Private data for the CS4270 */
 struct cs4270_private {
-        struct snd_soc_codec codec;
-        u8 reg_cache[CS4270_NUMREGS];
+        enum snd_soc_control_type control_type;
+        void *control_data;
         unsigned int mclk; /* Input frequency of the MCLK pin */
         unsigned int mode; /* The mode (I2S or left-justified) */
         unsigned int slave_mode;
@@ -180,6 +193,20 @@ static struct cs4270_mode_ratios cs4270_mode_ratios[] = {
 /* The number of MCLK/LRCK ratios supported by the CS4270 */
 #define NUM_MCLK_RATIOS         ARRAY_SIZE(cs4270_mode_ratios)
 
+static int cs4270_reg_is_readable(struct snd_soc_codec *codec, unsigned int reg)
+{
+        return (reg >= CS4270_FIRSTREG) && (reg <= CS4270_LASTREG);
+}
+
+static int cs4270_reg_is_volatile(struct snd_soc_codec *codec, unsigned int reg)
+{
+        /* Unreadable registers are considered volatile */
+        if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
+                return 1;
+
+        return reg == CS4270_CHIPID;
+}
+
 /**
  * cs4270_set_dai_sysclk - determine the CS4270 samples rates.
  * @codec_dai: the codec DAI
@@ -212,44 +239,8 @@ static int cs4270_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 {
         struct snd_soc_codec *codec = codec_dai->codec;
         struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
-        unsigned int rates = 0;
-        unsigned int rate_min = -1;
-        unsigned int rate_max = 0;
-        unsigned int i;
 
         cs4270->mclk = freq;
-
-        if (cs4270->mclk) {
-                for (i = 0; i < NUM_MCLK_RATIOS; i++) {
-                        unsigned int rate = freq / cs4270_mode_ratios[i].ratio;
-                        rates |= snd_pcm_rate_to_rate_bit(rate);
-                        if (rate < rate_min)
-                                rate_min = rate;
-                        if (rate > rate_max)
-                                rate_max = rate;
-                }
-                /* FIXME: soc should support a rate list */
-                rates &= ~SNDRV_PCM_RATE_KNOT;
-
-                if (!rates) {
-                        dev_err(codec->dev, "could not find a valid sample rate\n");
-                        return -EINVAL;
-                }
-        } else {
-                /* enable all possible rates */
-                rates = SNDRV_PCM_RATE_8000_192000;
-                rate_min = 8000;
-                rate_max = 192000;
-        }
-
-        codec_dai->playback.rates = rates;
-        codec_dai->playback.rate_min = rate_min;
-        codec_dai->playback.rate_max = rate_max;
-
-        codec_dai->capture.rates = rates;
-        codec_dai->capture.rate_min = rate_min;
-        codec_dai->capture.rate_max = rate_max;
-
         return 0;
 }
 
@@ -301,97 +292,6 @@ static int cs4270_set_dai_fmt(struct snd_soc_dai *codec_dai,
 }
 
 /**
- * cs4270_fill_cache - pre-fill the CS4270 register cache.
- * @codec: the codec for this CS4270
- *
- * This function fills in the CS4270 register cache by reading the register
- * values from the hardware.
- *
- * This CS4270 registers are cached to avoid excessive I2C I/O operations.
- * After the initial read to pre-fill the cache, the CS4270 never updates
- * the register values, so we won't have a cache coherency problem.
- *
- * We use the auto-increment feature of the CS4270 to read all registers in
- * one shot.
- */
-static int cs4270_fill_cache(struct snd_soc_codec *codec)
-{
-        u8 *cache = codec->reg_cache;
-        struct i2c_client *i2c_client = codec->control_data;
-        s32 length;
-
-        length = i2c_smbus_read_i2c_block_data(i2c_client,
-                CS4270_FIRSTREG | CS4270_I2C_INCR, CS4270_NUMREGS, cache);
-
-        if (length != CS4270_NUMREGS) {
-                dev_err(codec->dev, "i2c read failure, addr=0x%x\n",
-                       i2c_client->addr);
-                return -EIO;
-        }
-
-        return 0;
-}
-
-/**
- * cs4270_read_reg_cache - read from the CS4270 register cache.
- * @codec: the codec for this CS4270
- * @reg: the register to read
- *
- * This function returns the value for a given register.  It reads only from
- * the register cache, not the hardware itself.
- *
- * This CS4270 registers are cached to avoid excessive I2C I/O operations.
- * After the initial read to pre-fill the cache, the CS4270 never updates
- * the register values, so we won't have a cache coherency problem.
- */
-static unsigned int cs4270_read_reg_cache(struct snd_soc_codec *codec,
-        unsigned int reg)
-{
-        u8 *cache = codec->reg_cache;
-
-        if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
-                return -EIO;
-
-        return cache[reg - CS4270_FIRSTREG];
-}
-
-/**
- * cs4270_i2c_write - write to a CS4270 register via the I2C bus.
- * @codec: the codec for this CS4270
- * @reg: the register to write
- * @value: the value to write to the register
- *
- * This function writes the given value to the given CS4270 register, and
- * also updates the register cache.
- *
- * Note that we don't use the hw_write function pointer of snd_soc_codec.
- * That's because it's too clunky: the hw_write_t prototype does not match
- * i2c_smbus_write_byte_data(), and it's just another layer of overhead.
- */
-static int cs4270_i2c_write(struct snd_soc_codec *codec, unsigned int reg,
-                            unsigned int value)
-{
-        u8 *cache = codec->reg_cache;
-
-        if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
-                return -EIO;
-
-        /* Only perform an I2C operation if the new value is different */
-        if (cache[reg - CS4270_FIRSTREG] != value) {
-                struct i2c_client *client = codec->control_data;
-                if (i2c_smbus_write_byte_data(client, reg, value)) {
-                        dev_err(codec->dev, "i2c write failed\n");
-                        return -EIO;
-                }
-
-                /* We've written to the hardware, so update the cache */
-                cache[reg - CS4270_FIRSTREG] = value;
-        }
-
-        return 0;
-}
-
-/**
  * cs4270_hw_params - program the CS4270 with the given hardware parameters.
  * @substream: the audio stream
  * @params: the hardware parameters to set
@@ -410,8 +310,7 @@ static int cs4270_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
         int ret;
         unsigned int i;
@@ -549,19 +448,6 @@ static const struct snd_kcontrol_new cs4270_snd_controls[] = {
                 snd_soc_get_volsw, cs4270_soc_put_mute),
 };
 
-/*
- * cs4270_codec - global variable to store codec for the ASoC probe function
- *
- * If struct i2c_driver had a private_data field, we wouldn't need to use
- * cs4270_codec.  This is the only way to pass the codec structure from
- * cs4270_i2c_probe() to cs4270_probe().  Unfortunately, there is no good
- * way to synchronize these two functions.  cs4270_i2c_probe() can be called
- * multiple times before cs4270_probe() is called even once.  So for now, we
- * also only allow cs4270_i2c_probe() to be run once.  That means that we do
- * not support more than one cs4270 device in the system, at least for now.
- */
-static struct snd_soc_codec *cs4270_codec;
-
 static struct snd_soc_dai_ops cs4270_dai_ops = {
         .hw_params      = cs4270_hw_params,
         .set_sysclk     = cs4270_set_dai_sysclk,
@@ -569,25 +455,28 @@ static struct snd_soc_dai_ops cs4270_dai_ops = {
         .digital_mute   = cs4270_dai_mute,
 };
 
-struct snd_soc_dai cs4270_dai = {
-        .name = "cs4270",
+static struct snd_soc_dai_driver cs4270_dai = {
+        .name = "cs4270-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
                 .channels_max = 2,
-                .rates = 0,
+                .rates = SNDRV_PCM_RATE_CONTINUOUS,
+                .rate_min = 4000,
+                .rate_max = 216000,
                 .formats = CS4270_FORMATS,
         },
         .capture = {
                 .stream_name = "Capture",
                 .channels_min = 1,
                 .channels_max = 2,
-                .rates = 0,
+                .rates = SNDRV_PCM_RATE_CONTINUOUS,
+                .rate_min = 4000,
+                .rate_max = 216000,
                 .formats = CS4270_FORMATS,
         },
         .ops = &cs4270_dai_ops,
 };
-EXPORT_SYMBOL_GPL(cs4270_dai);
 
 /**
  * cs4270_probe - ASoC probe function
@@ -596,20 +485,42 @@ EXPORT_SYMBOL_GPL(cs4270_dai);
  * This function is called when ASoC has all the pieces it needs to
  * instantiate a sound driver.
  */
-static int cs4270_probe(struct platform_device *pdev)
+static int cs4270_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = cs4270_codec;
         struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
         int i, ret;
 
-        /* Connect the codec to the socdev.  snd_soc_new_pcms() needs this. */
-        socdev->card->codec = codec;
+        codec->control_data = cs4270->control_data;
 
-        /* Register PCMs */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+        /* Tell ASoC what kind of I/O to use to read the registers.  ASoC will
+         * then do the I2C transactions itself.
+         */
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, cs4270->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret);
+                return ret;
+        }
+
+        /* Disable auto-mute.  This feature appears to be buggy.  In some
+         * situations, auto-mute will not deactivate when it should, so we want
+         * this feature disabled by default.  An application (e.g. alsactl) can
+         * re-enabled it by using the controls.
+         */
+        ret = snd_soc_update_bits(codec, CS4270_MUTE, CS4270_MUTE_AUTO, 0);
+        if (ret < 0) {
+                dev_err(codec->dev, "i2c write failed\n");
+                return ret;
+        }
+
+        /* Disable automatic volume control.  The hardware enables, and it
+         * causes volume change commands to be delayed, sometimes until after
+         * playback has started.  An application (e.g. alsactl) can
+         * re-enabled it by using the controls.
+         */
+        ret = snd_soc_update_bits(codec, CS4270_TRANS,
+                CS4270_TRANS_SOFT | CS4270_TRANS_ZERO, 0);
         if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms\n");
+                dev_err(codec->dev, "i2c write failed\n");
                 return ret;
         }
 
@@ -618,7 +529,7 @@ static int cs4270_probe(struct platform_device *pdev)
                                 ARRAY_SIZE(cs4270_snd_controls));
         if (ret < 0) {
                 dev_err(codec->dev, "failed to add controls\n");
-                goto error_free_pcms;
+                return ret;
         }
 
         /* get the power supply regulators */
@@ -628,7 +539,7 @@ static int cs4270_probe(struct platform_device *pdev)
         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(cs4270->supplies),
                                  cs4270->supplies);
         if (ret < 0)
-                goto error_free_pcms;
+                return ret;
 
         ret = regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies),
                                     cs4270->supplies);
@@ -641,9 +552,6 @@ error_free_regulators:
         regulator_bulk_free(ARRAY_SIZE(cs4270->supplies),
                             cs4270->supplies);
 
-error_free_pcms:
-        snd_soc_free_pcms(socdev);
-
         return ret;
 }
 
@@ -653,19 +561,98 @@ error_free_pcms:
  *
  * This function is the counterpart to cs4270_probe().
  */
-static int cs4270_remove(struct platform_device *pdev)
+static int cs4270_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = cs4270_codec;
         struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
 
-        snd_soc_free_pcms(socdev);
         regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies), cs4270->supplies);
         regulator_bulk_free(ARRAY_SIZE(cs4270->supplies), cs4270->supplies);
 
         return 0;
 };
 
+#ifdef CONFIG_PM
+
+/* This suspend/resume implementation can handle both - a simple standby
+ * where the codec remains powered, and a full suspend, where the voltage
+ * domain the codec is connected to is teared down and/or any other hardware
+ * reset condition is asserted.
+ *
+ * The codec's own power saving features are enabled in the suspend callback,
+ * and all registers are written back to the hardware when resuming.
+ */
+
+static int cs4270_soc_suspend(struct snd_soc_codec *codec, pm_message_t mesg)
+{
+        struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
+        int reg, ret;
+
+        reg = snd_soc_read(codec, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL;
+        if (reg < 0)
+                return reg;
+
+        ret = snd_soc_write(codec, CS4270_PWRCTL, reg);
+        if (ret < 0)
+                return ret;
+
+        regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies),
+                               cs4270->supplies);
+
+        return 0;
+}
+
+static int cs4270_soc_resume(struct snd_soc_codec *codec)
+{
+        struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
+        struct i2c_client *i2c_client = codec->control_data;
+        int reg;
+
+        regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies),
+                              cs4270->supplies);
+
+        /* In case the device was put to hard reset during sleep, we need to
+         * wait 500ns here before any I2C communication. */
+        ndelay(500);
+
+        /* first restore the entire register cache ... */
+        for (reg = CS4270_FIRSTREG; reg <= CS4270_LASTREG; reg++) {
+                u8 val = snd_soc_read(codec, reg);
+
+                if (i2c_smbus_write_byte_data(i2c_client, reg, val)) {
+                        dev_err(codec->dev, "i2c write failed\n");
+                        return -EIO;
+                }
+        }
+
+        /* ... then disable the power-down bits */
+        reg = snd_soc_read(codec, CS4270_PWRCTL);
+        reg &= ~CS4270_PWRCTL_PDN_ALL;
+
+        return snd_soc_write(codec, CS4270_PWRCTL, reg);
+}
+#else
+#define cs4270_soc_suspend      NULL
+#define cs4270_soc_resume       NULL
+#endif /* CONFIG_PM */
+
+/*
+ * ASoC codec device structure
+ *
+ * Assign this variable to the codec_dev field of the machine driver's
+ * snd_soc_device structure.
+ */
+static const struct snd_soc_codec_driver soc_codec_device_cs4270 = {
+        .probe =                cs4270_probe,
+        .remove =               cs4270_remove,
+        .suspend =              cs4270_soc_suspend,
+        .resume =               cs4270_soc_resume,
+        .volatile_register =    cs4270_reg_is_volatile,
+        .readable_register =    cs4270_reg_is_readable,
+        .reg_cache_size =       CS4270_LASTREG + 1,
+        .reg_word_size =        sizeof(u8),
+        .reg_cache_default =    cs4270_default_reg_cache,
+};
+
 /**
  * cs4270_i2c_probe - initialize the I2C interface of the CS4270
  * @i2c_client: the I2C client object
@@ -677,22 +664,9 @@ static int cs4270_remove(struct platform_device *pdev)
 static int cs4270_i2c_probe(struct i2c_client *i2c_client,
         const struct i2c_device_id *id)
 {
-        struct snd_soc_codec *codec;
         struct cs4270_private *cs4270;
-        unsigned int reg;
         int ret;
 
-        /* For now, we only support one cs4270 device in the system.  See the
-         * comment for cs4270_codec.
-         */
-        if (cs4270_codec) {
-                dev_err(&i2c_client->dev, "ignoring CS4270 at addr %X\n",
-                       i2c_client->addr);
-                dev_err(&i2c_client->dev, "only one per board allowed\n");
-                /* Should we return something other than ENODEV here? */
-                return -ENODEV;
-        }
-
         /* Verify that we have a CS4270 */
 
         ret = i2c_smbus_read_byte_data(i2c_client, CS4270_CHIPID);
@@ -712,94 +686,20 @@ static int cs4270_i2c_probe(struct i2c_client *i2c_client,
                 i2c_client->addr);
         dev_info(&i2c_client->dev, "hardware revision %X\n", ret & 0xF);
 
-        /* Allocate enough space for the snd_soc_codec structure
-           and our private data together. */
         cs4270 = kzalloc(sizeof(struct cs4270_private), GFP_KERNEL);
         if (!cs4270) {
                 dev_err(&i2c_client->dev, "could not allocate codec\n");
                 return -ENOMEM;
         }
-        codec = &cs4270->codec;
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->dev = &i2c_client->dev;
-        codec->name = "CS4270";
-        codec->owner = THIS_MODULE;
-        codec->dai = &cs4270_dai;
-        codec->num_dai = 1;
-        snd_soc_codec_set_drvdata(codec, cs4270);
-        codec->control_data = i2c_client;
-        codec->read = cs4270_read_reg_cache;
-        codec->write = cs4270_i2c_write;
-        codec->reg_cache = cs4270->reg_cache;
-        codec->reg_cache_size = CS4270_NUMREGS;
-
-        /* The I2C interface is set up, so pre-fill our register cache */
-
-        ret = cs4270_fill_cache(codec);
-        if (ret < 0) {
-                dev_err(&i2c_client->dev, "failed to fill register cache\n");
-                goto error_free_codec;
-        }
-
-        /* Disable auto-mute.  This feature appears to be buggy.  In some
-         * situations, auto-mute will not deactivate when it should, so we want
-         * this feature disabled by default.  An application (e.g. alsactl) can
-         * re-enabled it by using the controls.
-         */
-
-        reg = cs4270_read_reg_cache(codec, CS4270_MUTE);
-        reg &= ~CS4270_MUTE_AUTO;
-        ret = cs4270_i2c_write(codec, CS4270_MUTE, reg);
-        if (ret < 0) {
-                dev_err(&i2c_client->dev, "i2c write failed\n");
-                return ret;
-        }
-
-        /* Disable automatic volume control.  The hardware enables, and it
-         * causes volume change commands to be delayed, sometimes until after
-         * playback has started.  An application (e.g. alsactl) can
-         * re-enabled it by using the controls.
-         */
-
-        reg = cs4270_read_reg_cache(codec, CS4270_TRANS);
-        reg &= ~(CS4270_TRANS_SOFT | CS4270_TRANS_ZERO);
-        ret = cs4270_i2c_write(codec, CS4270_TRANS, reg);
-        if (ret < 0) {
-                dev_err(&i2c_client->dev, "i2c write failed\n");
-                return ret;
-        }
-
-        /* Initialize the DAI. Normally, we'd prefer to have a kmalloc'd DAI
-         * structure for each CS4270 device, but the machine driver needs to
-         * have a pointer to the DAI structure, so for now it must be a global
-         * variable.
-         */
-        cs4270_dai.dev = &i2c_client->dev;
-
-        /* Register the DAI.  If all the other ASoC driver have already
-         * registered, then this will call our probe function, so
-         * cs4270_codec needs to be ready.
-         */
-        cs4270_codec = codec;
-        ret = snd_soc_register_dai(&cs4270_dai);
-        if (ret < 0) {
-                dev_err(&i2c_client->dev, "failed to register DAIe\n");
-                goto error_free_codec;
-        }
 
         i2c_set_clientdata(i2c_client, cs4270);
+        cs4270->control_data = i2c_client;
+        cs4270->control_type = SND_SOC_I2C;
 
-        return 0;
-
-error_free_codec:
-        kfree(cs4270);
-        cs4270_codec = NULL;
-        cs4270_dai.dev = NULL;
-
+        ret = snd_soc_register_codec(&i2c_client->dev,
+                        &soc_codec_device_cs4270, &cs4270_dai, 1);
+        if (ret < 0)
+                kfree(cs4270);
         return ret;
 }
 
@@ -811,90 +711,20 @@ error_free_codec:
  */
 static int cs4270_i2c_remove(struct i2c_client *i2c_client)
 {
-        struct cs4270_private *cs4270 = i2c_get_clientdata(i2c_client);
-
-        kfree(cs4270);
-        cs4270_codec = NULL;
-        cs4270_dai.dev = NULL;
-
+        snd_soc_unregister_codec(&i2c_client->dev);
+        kfree(i2c_get_clientdata(i2c_client));
         return 0;
 }
 
 /*
  * cs4270_id - I2C device IDs supported by this driver
  */
-static struct i2c_device_id cs4270_id[] = {
+static const struct i2c_device_id cs4270_id[] = {
         {"cs4270", 0},
         {}
 };
 MODULE_DEVICE_TABLE(i2c, cs4270_id);
 
-#ifdef CONFIG_PM
-
-/* This suspend/resume implementation can handle both - a simple standby
- * where the codec remains powered, and a full suspend, where the voltage
- * domain the codec is connected to is teared down and/or any other hardware
- * reset condition is asserted.
- *
- * The codec's own power saving features are enabled in the suspend callback,
- * and all registers are written back to the hardware when resuming.
- */
-
-static int cs4270_soc_suspend(struct platform_device *pdev, pm_message_t mesg)
-{
-        struct snd_soc_codec *codec = cs4270_codec;
-        struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
-        int reg, ret;
-
-        reg = snd_soc_read(codec, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL;
-        if (reg < 0)
-                return reg;
-
-        ret = snd_soc_write(codec, CS4270_PWRCTL, reg);
-        if (ret < 0)
-                return ret;
-
-        regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies),
-                               cs4270->supplies);
-
-        return 0;
-}
-
-static int cs4270_soc_resume(struct platform_device *pdev)
-{
-        struct snd_soc_codec *codec = cs4270_codec;
-        struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
-        struct i2c_client *i2c_client = codec->control_data;
-        int reg;
-
-        regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies),
-                              cs4270->supplies);
-
-        /* In case the device was put to hard reset during sleep, we need to
-         * wait 500ns here before any I2C communication. */
-        ndelay(500);
-
-        /* first restore the entire register cache ... */
-        for (reg = CS4270_FIRSTREG; reg <= CS4270_LASTREG; reg++) {
-                u8 val = snd_soc_read(codec, reg);
-
-                if (i2c_smbus_write_byte_data(i2c_client, reg, val)) {
-                        dev_err(codec->dev, "i2c write failed\n");
-                        return -EIO;
-                }
-        }
-
-        /* ... then disable the power-down bits */
-        reg = snd_soc_read(codec, CS4270_PWRCTL);
-        reg &= ~CS4270_PWRCTL_PDN_ALL;
-
-        return snd_soc_write(codec, CS4270_PWRCTL, reg);
-}
-#else
-#define cs4270_soc_suspend      NULL
-#define cs4270_soc_resume       NULL
-#endif /* CONFIG_PM */
-
 /*
  * cs4270_i2c_driver - I2C device identification
  *
@@ -903,7 +733,7 @@ static int cs4270_soc_resume(struct platform_device *pdev)
  */
 static struct i2c_driver cs4270_i2c_driver = {
         .driver = {
-                .name = "cs4270",
+                .name = "cs4270-codec",
                 .owner = THIS_MODULE,
         },
         .id_table = cs4270_id,
@@ -911,24 +741,8 @@ static struct i2c_driver cs4270_i2c_driver = {
         .remove = cs4270_i2c_remove,
 };
 
-/*
- * ASoC codec device structure
- *
- * Assign this variable to the codec_dev field of the machine driver's
- * snd_soc_device structure.
- */
-struct snd_soc_codec_device soc_codec_device_cs4270 = {
-        .probe =        cs4270_probe,
-        .remove =       cs4270_remove,
-        .suspend =      cs4270_soc_suspend,
-        .resume =       cs4270_soc_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_device_cs4270);
-
 static int __init cs4270_init(void)
 {
-        pr_info("Cirrus Logic CS4270 ALSA SoC Codec Driver\n");
-
         return i2c_add_driver(&cs4270_i2c_driver);
 }
 module_init(cs4270_init);
diff --git a/sound/soc/codecs/cs4270.h b/sound/soc/codecs/cs4270.h
deleted file mode 100644
index adc6cd9667d4..000000000000
--- a/sound/soc/codecs/cs4270.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Cirrus Logic CS4270 ALSA SoC Codec Driver
- *
- * Author: Timur Tabi <timur@freescale.com>
- *
- * Copyright 2007 Freescale Semiconductor, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef _CS4270_H
-#define _CS4270_H
-
-/*
- * The ASoC codec DAI structure for the CS4270.  Assign this structure to
- * the .codec_dai field of your machine driver's snd_soc_dai_link structure.
- */
-extern struct snd_soc_dai cs4270_dai;
-
-/*
- * The ASoC codec device structure for the CS4270.  Assign this structure
- * to the .codec_dev field of your machine driver's snd_soc_device
- * structure.
- */
-extern struct snd_soc_codec_device soc_codec_device_cs4270;
-
-#endif
diff --git a/sound/soc/codecs/cs4271.c b/sound/soc/codecs/cs4271.c
new file mode 100644
index 000000000000..083aab96ca80
--- /dev/null
+++ b/sound/soc/codecs/cs4271.c
@@ -0,0 +1,667 @@
+/*
+ * CS4271 ASoC codec driver
+ *
+ * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * This driver support CS4271 codec being master or slave, working
+ * in control port mode, connected either via SPI or I2C.
+ * The data format accepted is I2S or left-justified.
+ * DAPM support not implemented.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
+#include <sound/cs4271.h>
+
+#define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+                            SNDRV_PCM_FMTBIT_S24_LE | \
+                            SNDRV_PCM_FMTBIT_S32_LE)
+#define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
+
+/*
+ * CS4271 registers
+ * High byte represents SPI chip address (0x10) + write command (0)
+ * Low byte - codec register address
+ */
+#define CS4271_MODE1    0x2001  /* Mode Control 1 */
+#define CS4271_DACCTL   0x2002  /* DAC Control */
+#define CS4271_DACVOL   0x2003  /* DAC Volume & Mixing Control */
+#define CS4271_VOLA     0x2004  /* DAC Channel A Volume Control */
+#define CS4271_VOLB     0x2005  /* DAC Channel B Volume Control */
+#define CS4271_ADCCTL   0x2006  /* ADC Control */
+#define CS4271_MODE2    0x2007  /* Mode Control 2 */
+#define CS4271_CHIPID   0x2008  /* Chip ID */
+
+#define CS4271_FIRSTREG CS4271_MODE1
+#define CS4271_LASTREG  CS4271_MODE2
+#define CS4271_NR_REGS  ((CS4271_LASTREG & 0xFF) + 1)
+
+/* Bit masks for the CS4271 registers */
+#define CS4271_MODE1_MODE_MASK  0xC0
+#define CS4271_MODE1_MODE_1X    0x00
+#define CS4271_MODE1_MODE_2X    0x80
+#define CS4271_MODE1_MODE_4X    0xC0
+
+#define CS4271_MODE1_DIV_MASK   0x30
+#define CS4271_MODE1_DIV_1      0x00
+#define CS4271_MODE1_DIV_15     0x10
+#define CS4271_MODE1_DIV_2      0x20
+#define CS4271_MODE1_DIV_3      0x30
+
+#define CS4271_MODE1_MASTER     0x08
+
+#define CS4271_MODE1_DAC_DIF_MASK       0x07
+#define CS4271_MODE1_DAC_DIF_LJ         0x00
+#define CS4271_MODE1_DAC_DIF_I2S        0x01
+#define CS4271_MODE1_DAC_DIF_RJ16       0x02
+#define CS4271_MODE1_DAC_DIF_RJ24       0x03
+#define CS4271_MODE1_DAC_DIF_RJ20       0x04
+#define CS4271_MODE1_DAC_DIF_RJ18       0x05
+
+#define CS4271_DACCTL_AMUTE     0x80
+#define CS4271_DACCTL_IF_SLOW   0x40
+
+#define CS4271_DACCTL_DEM_MASK  0x30
+#define CS4271_DACCTL_DEM_DIS   0x00
+#define CS4271_DACCTL_DEM_441   0x10
+#define CS4271_DACCTL_DEM_48    0x20
+#define CS4271_DACCTL_DEM_32    0x30
+
+#define CS4271_DACCTL_SVRU      0x08
+#define CS4271_DACCTL_SRD       0x04
+#define CS4271_DACCTL_INVA      0x02
+#define CS4271_DACCTL_INVB      0x01
+
+#define CS4271_DACVOL_BEQUA     0x40
+#define CS4271_DACVOL_SOFT      0x20
+#define CS4271_DACVOL_ZEROC     0x10
+
+#define CS4271_DACVOL_ATAPI_MASK        0x0F
+#define CS4271_DACVOL_ATAPI_M_M         0x00
+#define CS4271_DACVOL_ATAPI_M_BR        0x01
+#define CS4271_DACVOL_ATAPI_M_BL        0x02
+#define CS4271_DACVOL_ATAPI_M_BLR2      0x03
+#define CS4271_DACVOL_ATAPI_AR_M        0x04
+#define CS4271_DACVOL_ATAPI_AR_BR       0x05
+#define CS4271_DACVOL_ATAPI_AR_BL       0x06
+#define CS4271_DACVOL_ATAPI_AR_BLR2     0x07
+#define CS4271_DACVOL_ATAPI_AL_M        0x08
+#define CS4271_DACVOL_ATAPI_AL_BR       0x09
+#define CS4271_DACVOL_ATAPI_AL_BL       0x0A
+#define CS4271_DACVOL_ATAPI_AL_BLR2     0x0B
+#define CS4271_DACVOL_ATAPI_ALR2_M      0x0C
+#define CS4271_DACVOL_ATAPI_ALR2_BR     0x0D
+#define CS4271_DACVOL_ATAPI_ALR2_BL     0x0E
+#define CS4271_DACVOL_ATAPI_ALR2_BLR2   0x0F
+
+#define CS4271_VOLA_MUTE        0x80
+#define CS4271_VOLA_VOL_MASK    0x7F
+#define CS4271_VOLB_MUTE        0x80
+#define CS4271_VOLB_VOL_MASK    0x7F
+
+#define CS4271_ADCCTL_DITHER16  0x20
+
+#define CS4271_ADCCTL_ADC_DIF_MASK      0x10
+#define CS4271_ADCCTL_ADC_DIF_LJ        0x00
+#define CS4271_ADCCTL_ADC_DIF_I2S       0x10
+
+#define CS4271_ADCCTL_MUTEA     0x08
+#define CS4271_ADCCTL_MUTEB     0x04
+#define CS4271_ADCCTL_HPFDA     0x02
+#define CS4271_ADCCTL_HPFDB     0x01
+
+#define CS4271_MODE2_LOOP       0x10
+#define CS4271_MODE2_MUTECAEQUB 0x08
+#define CS4271_MODE2_FREEZE     0x04
+#define CS4271_MODE2_CPEN       0x02
+#define CS4271_MODE2_PDN        0x01
+
+#define CS4271_CHIPID_PART_MASK 0xF0
+#define CS4271_CHIPID_REV_MASK  0x0F
+
+/*
+ * Default CS4271 power-up configuration
+ * Array contains non-existing in hw register at address 0
+ * Array do not include Chip ID, as codec driver does not use
+ * registers read operations at all
+ */
+static const u8 cs4271_dflt_reg[CS4271_NR_REGS] = {
+        0,
+        0,
+        CS4271_DACCTL_AMUTE,
+        CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR,
+        0,
+        0,
+        0,
+        0,
+};
+
+struct cs4271_private {
+        /* SND_SOC_I2C or SND_SOC_SPI */
+        enum snd_soc_control_type       bus_type;
+        void                            *control_data;
+        unsigned int                    mclk;
+        bool                            master;
+        bool                            deemph;
+        /* Current sample rate for de-emphasis control */
+        int                             rate;
+        /* GPIO driving Reset pin, if any */
+        int                             gpio_nreset;
+        /* GPIO that disable serial bus, if any */
+        int                             gpio_disable;
+};
+
+/*
+ * @freq is the desired MCLK rate
+ * MCLK rate should (c) be the sample rate, multiplied by one of the
+ * ratios listed in cs4271_mclk_fs_ratios table
+ */
+static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                                 int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
+
+        cs4271->mclk = freq;
+        return 0;
+}
+
+static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                              unsigned int format)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
+        unsigned int val = 0;
+        int ret;
+
+        switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBS_CFS:
+                cs4271->master = 0;
+                break;
+        case SND_SOC_DAIFMT_CBM_CFM:
+                cs4271->master = 1;
+                val |= CS4271_MODE1_MASTER;
+                break;
+        default:
+                dev_err(codec->dev, "Invalid DAI format\n");
+                return -EINVAL;
+        }
+
+        switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_LEFT_J:
+                val |= CS4271_MODE1_DAC_DIF_LJ;
+                ret = snd_soc_update_bits(codec, CS4271_ADCCTL,
+                        CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
+                if (ret < 0)
+                        return ret;
+                break;
+        case SND_SOC_DAIFMT_I2S:
+                val |= CS4271_MODE1_DAC_DIF_I2S;
+                ret = snd_soc_update_bits(codec, CS4271_ADCCTL,
+                        CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
+                if (ret < 0)
+                        return ret;
+                break;
+        default:
+                dev_err(codec->dev, "Invalid DAI format\n");
+                return -EINVAL;
+        }
+
+        ret = snd_soc_update_bits(codec, CS4271_MODE1,
+                CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
+        if (ret < 0)
+                return ret;
+        return 0;
+}
+
+static int cs4271_deemph[] = {0, 44100, 48000, 32000};
+
+static int cs4271_set_deemph(struct snd_soc_codec *codec)
+{
+        struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
+        int i, ret;
+        int val = CS4271_DACCTL_DEM_DIS;
+
+        if (cs4271->deemph) {
+                /* Find closest de-emphasis freq */
+                val = 1;
+                for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
+                        if (abs(cs4271_deemph[i] - cs4271->rate) <
+                            abs(cs4271_deemph[val] - cs4271->rate))
+                                val = i;
+                val <<= 4;
+        }
+
+        ret = snd_soc_update_bits(codec, CS4271_DACCTL,
+                CS4271_DACCTL_DEM_MASK, val);
+        if (ret < 0)
+                return ret;
+        return 0;
+}
+
+static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = cs4271->deemph;
+        return 0;
+}
+
+static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
+
+        cs4271->deemph = ucontrol->value.enumerated.item[0];
+        return cs4271_set_deemph(codec);
+}
+
+struct cs4271_clk_cfg {
+        bool            master;         /* codec mode */
+        u8              speed_mode;     /* codec speed mode: 1x, 2x, 4x */
+        unsigned short  ratio;          /* MCLK / sample rate */
+        u8              ratio_mask;     /* ratio bit mask for Master mode */
+};
+
+static struct cs4271_clk_cfg cs4271_clk_tab[] = {
+        {1, CS4271_MODE1_MODE_1X, 256,  CS4271_MODE1_DIV_1},
+        {1, CS4271_MODE1_MODE_1X, 384,  CS4271_MODE1_DIV_15},
+        {1, CS4271_MODE1_MODE_1X, 512,  CS4271_MODE1_DIV_2},
+        {1, CS4271_MODE1_MODE_1X, 768,  CS4271_MODE1_DIV_3},
+        {1, CS4271_MODE1_MODE_2X, 128,  CS4271_MODE1_DIV_1},
+        {1, CS4271_MODE1_MODE_2X, 192,  CS4271_MODE1_DIV_15},
+        {1, CS4271_MODE1_MODE_2X, 256,  CS4271_MODE1_DIV_2},
+        {1, CS4271_MODE1_MODE_2X, 384,  CS4271_MODE1_DIV_3},
+        {1, CS4271_MODE1_MODE_4X, 64,   CS4271_MODE1_DIV_1},
+        {1, CS4271_MODE1_MODE_4X, 96,   CS4271_MODE1_DIV_15},
+        {1, CS4271_MODE1_MODE_4X, 128,  CS4271_MODE1_DIV_2},
+        {1, CS4271_MODE1_MODE_4X, 192,  CS4271_MODE1_DIV_3},
+        {0, CS4271_MODE1_MODE_1X, 256,  CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_1X, 384,  CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_1X, 512,  CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_1X, 768,  CS4271_MODE1_DIV_2},
+        {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
+        {0, CS4271_MODE1_MODE_2X, 128,  CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_2X, 192,  CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_2X, 256,  CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_2X, 384,  CS4271_MODE1_DIV_2},
+        {0, CS4271_MODE1_MODE_2X, 512,  CS4271_MODE1_DIV_2},
+        {0, CS4271_MODE1_MODE_4X, 64,   CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_4X, 96,   CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_4X, 128,  CS4271_MODE1_DIV_1},
+        {0, CS4271_MODE1_MODE_4X, 192,  CS4271_MODE1_DIV_2},
+        {0, CS4271_MODE1_MODE_4X, 256,  CS4271_MODE1_DIV_2},
+};
+
+#define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
+
+static int cs4271_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
+        int i, ret;
+        unsigned int ratio, val;
+
+        cs4271->rate = params_rate(params);
+
+        /* Configure DAC */
+        if (cs4271->rate < 50000)
+                val = CS4271_MODE1_MODE_1X;
+        else if (cs4271->rate < 100000)
+                val = CS4271_MODE1_MODE_2X;
+        else
+                val = CS4271_MODE1_MODE_4X;
+
+        ratio = cs4271->mclk / cs4271->rate;
+        for (i = 0; i < CS4171_NR_RATIOS; i++)
+                if ((cs4271_clk_tab[i].master == cs4271->master) &&
+                    (cs4271_clk_tab[i].speed_mode == val) &&
+                    (cs4271_clk_tab[i].ratio == ratio))
+                        break;
+
+        if (i == CS4171_NR_RATIOS) {
+                dev_err(codec->dev, "Invalid sample rate\n");
+                return -EINVAL;
+        }
+
+        val |= cs4271_clk_tab[i].ratio_mask;
+
+        ret = snd_soc_update_bits(codec, CS4271_MODE1,
+                CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
+        if (ret < 0)
+                return ret;
+
+        return cs4271_set_deemph(codec);
+}
+
+static int cs4271_digital_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        int ret;
+        int val_a = 0;
+        int val_b = 0;
+
+        if (mute) {
+                val_a = CS4271_VOLA_MUTE;
+                val_b = CS4271_VOLB_MUTE;
+        }
+
+        ret = snd_soc_update_bits(codec, CS4271_VOLA, CS4271_VOLA_MUTE, val_a);
+        if (ret < 0)
+                return ret;
+        ret = snd_soc_update_bits(codec, CS4271_VOLB, CS4271_VOLB_MUTE, val_b);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
+/* CS4271 controls */
+static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
+
+static const struct snd_kcontrol_new cs4271_snd_controls[] = {
+        SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
+                0, 0x7F, 1, cs4271_dac_tlv),
+        SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
+        SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
+        SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
+        SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
+                cs4271_get_deemph, cs4271_put_deemph),
+        SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
+        SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
+        SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
+        SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
+        SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
+        SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
+        SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
+        SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
+        SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
+        SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
+                7, 1, 1),
+};
+
+static struct snd_soc_dai_ops cs4271_dai_ops = {
+        .hw_params      = cs4271_hw_params,
+        .set_sysclk     = cs4271_set_dai_sysclk,
+        .set_fmt        = cs4271_set_dai_fmt,
+        .digital_mute   = cs4271_digital_mute,
+};
+
+static struct snd_soc_dai_driver cs4271_dai = {
+        .name = "cs4271-hifi",
+        .playback = {
+                .stream_name    = "Playback",
+                .channels_min   = 2,
+                .channels_max   = 2,
+                .rates          = CS4271_PCM_RATES,
+                .formats        = CS4271_PCM_FORMATS,
+        },
+        .capture = {
+                .stream_name    = "Capture",
+                .channels_min   = 2,
+                .channels_max   = 2,
+                .rates          = CS4271_PCM_RATES,
+                .formats        = CS4271_PCM_FORMATS,
+        },
+        .ops = &cs4271_dai_ops,
+        .symmetric_rates = 1,
+};
+
+#ifdef CONFIG_PM
+static int cs4271_soc_suspend(struct snd_soc_codec *codec, pm_message_t mesg)
+{
+        int ret;
+        /* Set power-down bit */
+        ret = snd_soc_update_bits(codec, CS4271_MODE2, 0, CS4271_MODE2_PDN);
+        if (ret < 0)
+                return ret;
+        return 0;
+}
+
+static int cs4271_soc_resume(struct snd_soc_codec *codec)
+{
+        int ret;
+        /* Restore codec state */
+        ret = snd_soc_cache_sync(codec);
+        if (ret < 0)
+                return ret;
+        /* then disable the power-down bit */
+        ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);
+        if (ret < 0)
+                return ret;
+        return 0;
+}
+#else
+#define cs4271_soc_suspend      NULL
+#define cs4271_soc_resume       NULL
+#endif /* CONFIG_PM */
+
+static int cs4271_probe(struct snd_soc_codec *codec)
+{
+        struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
+        struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;
+        int ret;
+        int gpio_nreset = -EINVAL;
+
+        codec->control_data = cs4271->control_data;
+
+        if (cs4271plat && gpio_is_valid(cs4271plat->gpio_nreset))
+                gpio_nreset = cs4271plat->gpio_nreset;
+
+        if (gpio_nreset >= 0)
+                if (gpio_request(gpio_nreset, "CS4271 Reset"))
+                        gpio_nreset = -EINVAL;
+        if (gpio_nreset >= 0) {
+                /* Reset codec */
+                gpio_direction_output(gpio_nreset, 0);
+                udelay(1);
+                gpio_set_value(gpio_nreset, 1);
+                /* Give the codec time to wake up */
+                udelay(1);
+        }
+
+        cs4271->gpio_nreset = gpio_nreset;
+
+        /*
+         * In case of I2C, chip address specified in board data.
+         * So cache IO operations use 8 bit codec register address.
+         * In case of SPI, chip address and register address
+         * passed together as 16 bit value.
+         * Anyway, register address is masked with 0xFF inside
+         * soc-cache code.
+         */
+        if (cs4271->bus_type == SND_SOC_SPI)
+                ret = snd_soc_codec_set_cache_io(codec, 16, 8,
+                        cs4271->bus_type);
+        else
+                ret = snd_soc_codec_set_cache_io(codec, 8, 8,
+                        cs4271->bus_type);
+        if (ret) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        ret = snd_soc_update_bits(codec, CS4271_MODE2, 0,
+                CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
+        if (ret < 0)
+                return ret;
+        ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);
+        if (ret < 0)
+                return ret;
+        /* Power-up sequence requires 85 uS */
+        udelay(85);
+
+        return snd_soc_add_controls(codec, cs4271_snd_controls,
+                ARRAY_SIZE(cs4271_snd_controls));
+}
+
+static int cs4271_remove(struct snd_soc_codec *codec)
+{
+        struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
+        int gpio_nreset;
+
+        gpio_nreset = cs4271->gpio_nreset;
+
+        if (gpio_is_valid(gpio_nreset)) {
+                /* Set codec to the reset state */
+                gpio_set_value(gpio_nreset, 0);
+                gpio_free(gpio_nreset);
+        }
+
+        return 0;
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_cs4271 = {
+        .probe                  = cs4271_probe,
+        .remove                 = cs4271_remove,
+        .suspend                = cs4271_soc_suspend,
+        .resume                 = cs4271_soc_resume,
+        .reg_cache_default      = cs4271_dflt_reg,
+        .reg_cache_size         = ARRAY_SIZE(cs4271_dflt_reg),
+        .reg_word_size          = sizeof(cs4271_dflt_reg[0]),
+        .compress_type          = SND_SOC_FLAT_COMPRESSION,
+};
+
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit cs4271_spi_probe(struct spi_device *spi)
+{
+        struct cs4271_private *cs4271;
+
+        cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL);
+        if (!cs4271)
+                return -ENOMEM;
+
+        spi_set_drvdata(spi, cs4271);
+        cs4271->control_data = spi;
+        cs4271->bus_type = SND_SOC_SPI;
+
+        return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271,
+                &cs4271_dai, 1);
+}
+
+static int __devexit cs4271_spi_remove(struct spi_device *spi)
+{
+        snd_soc_unregister_codec(&spi->dev);
+        return 0;
+}
+
+static struct spi_driver cs4271_spi_driver = {
+        .driver = {
+                .name   = "cs4271",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = cs4271_spi_probe,
+        .remove         = __devexit_p(cs4271_spi_remove),
+};
+#endif /* defined(CONFIG_SPI_MASTER) */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static const struct i2c_device_id cs4271_i2c_id[] = {
+        {"cs4271", 0},
+        {}
+};
+MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id);
+
+static int __devinit cs4271_i2c_probe(struct i2c_client *client,
+                                      const struct i2c_device_id *id)
+{
+        struct cs4271_private *cs4271;
+
+        cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL);
+        if (!cs4271)
+                return -ENOMEM;
+
+        i2c_set_clientdata(client, cs4271);
+        cs4271->control_data = client;
+        cs4271->bus_type = SND_SOC_I2C;
+
+        return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271,
+                &cs4271_dai, 1);
+}
+
+static int __devexit cs4271_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        return 0;
+}
+
+static struct i2c_driver cs4271_i2c_driver = {
+        .driver = {
+                .name   = "cs4271",
+                .owner  = THIS_MODULE,
+        },
+        .id_table       = cs4271_i2c_id,
+        .probe          = cs4271_i2c_probe,
+        .remove         = __devexit_p(cs4271_i2c_remove),
+};
+#endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */
+
+/*
+ * We only register our serial bus driver here without
+ * assignment to particular chip. So if any of the below
+ * fails, there is some problem with I2C or SPI subsystem.
+ * In most cases this module will be compiled with support
+ * of only one serial bus.
+ */
+static int __init cs4271_modinit(void)
+{
+        int ret;
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&cs4271_i2c_driver);
+        if (ret) {
+                pr_err("Failed to register CS4271 I2C driver: %d\n", ret);
+                return ret;
+        }
+#endif
+
+#if defined(CONFIG_SPI_MASTER)
+        ret = spi_register_driver(&cs4271_spi_driver);
+        if (ret) {
+                pr_err("Failed to register CS4271 SPI driver: %d\n", ret);
+                return ret;
+        }
+#endif
+
+        return 0;
+}
+module_init(cs4271_modinit);
+
+static void __exit cs4271_modexit(void)
+{
+#if defined(CONFIG_SPI_MASTER)
+        spi_unregister_driver(&cs4271_spi_driver);
+#endif
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&cs4271_i2c_driver);
+#endif
+}
+module_exit(cs4271_modexit);
+
+MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
+MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c
index dd9b8550c402..8fb7070108dd 100644
--- a/sound/soc/codecs/cs42l51.c
+++ b/sound/soc/codecs/cs42l51.c
@@ -26,7 +26,6 @@
 #include <linux/slab.h>
 #include <sound/core.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 #include <sound/initval.h>
 #include <sound/pcm_params.h>
@@ -42,15 +41,13 @@ enum master_slave_mode {
 };
 
 struct cs42l51_private {
+        enum snd_soc_control_type control_type;
+        void *control_data;
         unsigned int mclk;
         unsigned int audio_mode;        /* The mode (I2S or left-justified) */
         enum master_slave_mode func;
-        struct snd_soc_codec codec;
-        u8 reg_cache[CS42L51_NUMREGS];
 };
 
-static struct snd_soc_codec *cs42l51_codec;
-
 #define CS42L51_FORMATS ( \
                 SNDRV_PCM_FMTBIT_S16_LE  | SNDRV_PCM_FMTBIT_S16_BE  | \
                 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
@@ -75,134 +72,6 @@ static int cs42l51_fill_cache(struct snd_soc_codec *codec)
         return 0;
 }
 
-static int cs42l51_i2c_probe(struct i2c_client *i2c_client,
-        const struct i2c_device_id *id)
-{
-        struct snd_soc_codec *codec;
-        struct cs42l51_private *cs42l51;
-        int ret = 0;
-        int reg;
-
-        if (cs42l51_codec)
-                return -EBUSY;
-
-        /* Verify that we have a CS42L51 */
-        ret = i2c_smbus_read_byte_data(i2c_client, CS42L51_CHIP_REV_ID);
-        if (ret < 0) {
-                dev_err(&i2c_client->dev, "failed to read I2C\n");
-                goto error;
-        }
-
-        if ((ret != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
-            (ret != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
-                dev_err(&i2c_client->dev, "Invalid chip id\n");
-                ret = -ENODEV;
-                goto error;
-        }
-
-        dev_info(&i2c_client->dev, "found device cs42l51 rev %d\n",
-                                ret & 7);
-
-        cs42l51 = kzalloc(sizeof(struct cs42l51_private), GFP_KERNEL);
-        if (!cs42l51) {
-                dev_err(&i2c_client->dev, "could not allocate codec\n");
-                return -ENOMEM;
-        }
-        codec = &cs42l51->codec;
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->dev = &i2c_client->dev;
-        codec->name = "CS42L51";
-        codec->owner = THIS_MODULE;
-        codec->dai = &cs42l51_dai;
-        codec->num_dai = 1;
-        snd_soc_codec_set_drvdata(codec, cs42l51);
-
-        codec->control_data = i2c_client;
-        codec->reg_cache = cs42l51->reg_cache;
-        codec->reg_cache_size = CS42L51_NUMREGS;
-        i2c_set_clientdata(i2c_client, codec);
-
-        ret = cs42l51_fill_cache(codec);
-        if (ret < 0) {
-                dev_err(&i2c_client->dev, "failed to fill register cache\n");
-                goto error_alloc;
-        }
-
-        ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
-        if (ret < 0) {
-                dev_err(&i2c_client->dev, "Failed to set cache I/O: %d\n", ret);
-                goto error_alloc;
-        }
-
-        /*
-         * DAC configuration
-         * - Use signal processor
-         * - auto mute
-         * - vol changes immediate
-         * - no de-emphasize
-         */
-        reg = CS42L51_DAC_CTL_DATA_SEL(1)
-                | CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);
-        ret = snd_soc_write(codec, CS42L51_DAC_CTL, reg);
-        if (ret < 0)
-                goto error_alloc;
-
-        cs42l51_dai.dev = codec->dev;
-        cs42l51_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto error_alloc;
-        }
-
-        ret = snd_soc_register_dai(&cs42l51_dai);
-        if (ret < 0) {
-                dev_err(&i2c_client->dev, "failed to register DAIe\n");
-                goto error_reg;
-        }
-
-        return 0;
-
-error_reg:
-        snd_soc_unregister_codec(codec);
-error_alloc:
-        kfree(cs42l51);
-error:
-        return ret;
-}
-
-static int cs42l51_i2c_remove(struct i2c_client *client)
-{
-        struct cs42l51_private *cs42l51 = i2c_get_clientdata(client);
-        snd_soc_unregister_dai(&cs42l51_dai);
-        snd_soc_unregister_codec(cs42l51_codec);
-        cs42l51_codec = NULL;
-        kfree(cs42l51);
-        return 0;
-}
-
-
-static const struct i2c_device_id cs42l51_id[] = {
-        {"cs42l51", 0},
-        {}
-};
-MODULE_DEVICE_TABLE(i2c, cs42l51_id);
-
-static struct i2c_driver cs42l51_i2c_driver = {
-        .driver = {
-                .name = "CS42L51 I2C",
-                .owner = THIS_MODULE,
-        },
-        .id_table = cs42l51_id,
-        .probe = cs42l51_i2c_probe,
-        .remove = cs42l51_i2c_remove,
-};
-
 static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
                         struct snd_ctl_elem_value *ucontrol)
 {
@@ -484,51 +353,8 @@ static int cs42l51_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 {
         struct snd_soc_codec *codec = codec_dai->codec;
         struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec);
-        struct cs42l51_ratios *ratios = NULL;
-        int nr_ratios = 0;
-        unsigned int rates = 0;
-        unsigned int rate_min = -1;
-        unsigned int rate_max = 0;
-        int i;
 
         cs42l51->mclk = freq;
-
-        switch (cs42l51->func) {
-        case MODE_MASTER:
-                return -EINVAL;
-        case MODE_SLAVE:
-                ratios = slave_ratios;
-                nr_ratios = ARRAY_SIZE(slave_ratios);
-                break;
-        case MODE_SLAVE_AUTO:
-                ratios = slave_auto_ratios;
-                nr_ratios = ARRAY_SIZE(slave_auto_ratios);
-                break;
-        }
-
-        for (i = 0; i < nr_ratios; i++) {
-                unsigned int rate = freq / ratios[i].ratio;
-                rates |= snd_pcm_rate_to_rate_bit(rate);
-                if (rate < rate_min)
-                        rate_min = rate;
-                if (rate > rate_max)
-                        rate_max = rate;
-        }
-        rates &= ~SNDRV_PCM_RATE_KNOT;
-
-        if (!rates) {
-                dev_err(codec->dev, "could not find a valid sample rate\n");
-                return -EINVAL;
-        }
-
-        codec_dai->playback.rates = rates;
-        codec_dai->playback.rate_min = rate_min;
-        codec_dai->playback.rate_max = rate_max;
-
-        codec_dai->capture.rates = rates;
-        codec_dai->capture.rate_min = rate_min;
-        codec_dai->capture.rate_max = rate_max;
-
         return 0;
 }
 
@@ -537,8 +363,7 @@ static int cs42l51_hw_params(struct snd_pcm_substream *substream,
                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec);
         int ret;
         unsigned int i;
@@ -670,8 +495,8 @@ static struct snd_soc_dai_ops cs42l51_dai_ops = {
         .digital_mute   = cs42l51_dai_mute,
 };
 
-struct snd_soc_dai cs42l51_dai = {
-        .name = "CS42L51 HiFi",
+static struct snd_soc_dai_driver cs42l51_dai = {
+        .name = "cs42l51-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -688,56 +513,121 @@ struct snd_soc_dai cs42l51_dai = {
         },
         .ops = &cs42l51_dai_ops,
 };
-EXPORT_SYMBOL_GPL(cs42l51_dai);
-
 
-static int cs42l51_probe(struct platform_device *pdev)
+static int cs42l51_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
+        struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret, reg;
 
-        if (!cs42l51_codec) {
-                dev_err(&pdev->dev, "CS42L51 codec not yet registered\n");
-                return -EINVAL;
-        }
+        codec->control_data = cs42l51->control_data;
 
-        socdev->card->codec = cs42l51_codec;
-        codec = socdev->card->codec;
+        ret = cs42l51_fill_cache(codec);
+        if (ret < 0) {
+                dev_err(codec->dev, "failed to fill register cache\n");
+                return ret;
+        }
 
-        /* Register PCMs */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, cs42l51->control_type);
         if (ret < 0) {
-                dev_err(&pdev->dev, "failed to create PCMs\n");
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
                 return ret;
         }
 
+        /*
+         * DAC configuration
+         * - Use signal processor
+         * - auto mute
+         * - vol changes immediate
+         * - no de-emphasize
+         */
+        reg = CS42L51_DAC_CTL_DATA_SEL(1)
+                | CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);
+        ret = snd_soc_write(codec, CS42L51_DAC_CTL, reg);
+        if (ret < 0)
+                return ret;
+
         snd_soc_add_controls(codec, cs42l51_snd_controls,
                 ARRAY_SIZE(cs42l51_snd_controls));
-        snd_soc_dapm_new_controls(codec, cs42l51_dapm_widgets,
+        snd_soc_dapm_new_controls(dapm, cs42l51_dapm_widgets,
                 ARRAY_SIZE(cs42l51_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, cs42l51_routes,
+        snd_soc_dapm_add_routes(dapm, cs42l51_routes,
                 ARRAY_SIZE(cs42l51_routes));
 
         return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_device_cs42l51 = {
+        .probe =        cs42l51_probe,
+        .reg_cache_size = CS42L51_NUMREGS,
+        .reg_word_size = sizeof(u8),
+};
 
-static int cs42l51_remove(struct platform_device *pdev)
+static int cs42l51_i2c_probe(struct i2c_client *i2c_client,
+        const struct i2c_device_id *id)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+        struct cs42l51_private *cs42l51;
+        int ret;
 
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
+        /* Verify that we have a CS42L51 */
+        ret = i2c_smbus_read_byte_data(i2c_client, CS42L51_CHIP_REV_ID);
+        if (ret < 0) {
+                dev_err(&i2c_client->dev, "failed to read I2C\n");
+                goto error;
+        }
+
+        if ((ret != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
+            (ret != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
+                dev_err(&i2c_client->dev, "Invalid chip id\n");
+                ret = -ENODEV;
+                goto error;
+        }
+
+        dev_info(&i2c_client->dev, "found device cs42l51 rev %d\n",
+                                ret & 7);
+
+        cs42l51 = kzalloc(sizeof(struct cs42l51_private), GFP_KERNEL);
+        if (!cs42l51) {
+                dev_err(&i2c_client->dev, "could not allocate codec\n");
+                return -ENOMEM;
+        }
+
+        i2c_set_clientdata(i2c_client, cs42l51);
+        cs42l51->control_data = i2c_client;
+        cs42l51->control_type = SND_SOC_I2C;
 
+        ret =  snd_soc_register_codec(&i2c_client->dev,
+                        &soc_codec_device_cs42l51, &cs42l51_dai, 1);
+        if (ret < 0)
+                kfree(cs42l51);
+error:
+        return ret;
+}
+
+static int cs42l51_i2c_remove(struct i2c_client *client)
+{
+        struct cs42l51_private *cs42l51 = i2c_get_clientdata(client);
+
+        snd_soc_unregister_codec(&client->dev);
+        kfree(cs42l51);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_device_cs42l51 = {
-        .probe =        cs42l51_probe,
-        .remove =       cs42l51_remove
+static const struct i2c_device_id cs42l51_id[] = {
+        {"cs42l51", 0},
+        {}
+};
+MODULE_DEVICE_TABLE(i2c, cs42l51_id);
+
+static struct i2c_driver cs42l51_i2c_driver = {
+        .driver = {
+                .name = "cs42l51-codec",
+                .owner = THIS_MODULE,
+        },
+        .id_table = cs42l51_id,
+        .probe = cs42l51_i2c_probe,
+        .remove = cs42l51_i2c_remove,
 };
-EXPORT_SYMBOL_GPL(soc_codec_device_cs42l51);
 
 static int __init cs42l51_init(void)
 {
@@ -758,6 +648,6 @@ static void __exit cs42l51_exit(void)
 }
 module_exit(cs42l51_exit);
 
-MODULE_AUTHOR("Arnaud Patard <apatard@mandriva.com>");
+MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
 MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs42l51.h b/sound/soc/codecs/cs42l51.h
index 8f0bd9786ad2..2beeb171db4b 100644
--- a/sound/soc/codecs/cs42l51.h
+++ b/sound/soc/codecs/cs42l51.h
@@ -158,6 +158,4 @@
 #define CS42L51_LASTREG         0x20
 #define CS42L51_NUMREGS         (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
 
-extern struct snd_soc_dai cs42l51_dai;
-extern struct snd_soc_codec_device soc_codec_device_cs42l51;
 #endif
diff --git a/sound/soc/codecs/cx20442.c b/sound/soc/codecs/cx20442.c
index f07a415c753f..d68ea532cc7f 100644
--- a/sound/soc/codecs/cx20442.c
+++ b/sound/soc/codecs/cx20442.c
@@ -18,14 +18,14 @@
 
 #include <sound/core.h>
 #include <sound/initval.h>
-#include <sound/soc-dapm.h>
+#include <sound/soc.h>
 
 #include "cx20442.h"
 
 
 struct cx20442_priv {
-        struct snd_soc_codec codec;
-        u8 reg_cache[1];
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
 #define CX20442_PM              0x0
@@ -86,23 +86,12 @@ static const struct snd_soc_dapm_route cx20442_audio_map[] = {
         {"ADC", NULL, "Input Mixer"},
 };
 
-static int cx20442_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, cx20442_dapm_widgets,
-                                  ARRAY_SIZE(cx20442_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, cx20442_audio_map,
-                                ARRAY_SIZE(cx20442_audio_map));
-
-        return 0;
-}
-
 static unsigned int cx20442_read_reg_cache(struct snd_soc_codec *codec,
                                                         unsigned int reg)
 {
         u8 *reg_cache = codec->reg_cache;
 
-        if (reg >= codec->reg_cache_size)
+        if (reg >= codec->driver->reg_cache_size)
                 return -EINVAL;
 
         return reg_cache[reg];
@@ -164,16 +153,17 @@ static int cx20442_pm_to_v253_vsp(u8 value)
 static int cx20442_write(struct snd_soc_codec *codec, unsigned int reg,
                                                         unsigned int value)
 {
+        struct cx20442_priv *cx20442 = snd_soc_codec_get_drvdata(codec);
         u8 *reg_cache = codec->reg_cache;
         int vls, vsp, old, len;
         char buf[18];
 
-        if (reg >= codec->reg_cache_size)
+        if (reg >= codec->driver->reg_cache_size)
                 return -EINVAL;
 
         /* hw_write and control_data pointers required for talking to the modem
          * are expected to be set by the line discipline initialization code */
-        if (!codec->hw_write || !codec->control_data)
+        if (!codec->hw_write || !cx20442->control_data)
                 return -EIO;
 
         old = reg_cache[reg];
@@ -202,17 +192,13 @@ static int cx20442_write(struct snd_soc_codec *codec, unsigned int reg,
                 return -ENOMEM;
 
         dev_dbg(codec->dev, "%s: %s\n", __func__, buf);
-        if (codec->hw_write(codec->control_data, buf, len) != len)
+        if (codec->hw_write(cx20442->control_data, buf, len) != len)
                 return -EIO;
 
         return 0;
 }
 
 
-/* Moved up here as line discipline referres it during initialization */
-static struct snd_soc_codec *cx20442_codec;
-
-
 /*
  * Line discpline related code
  *
@@ -228,15 +214,15 @@ static const char *v253_init = "ate0m0q0+fclass=8\r";
 /* Line discipline .open() */
 static int v253_open(struct tty_struct *tty)
 {
-        struct snd_soc_codec *codec = cx20442_codec;
         int ret, len = strlen(v253_init);
 
         /* Doesn't make sense without write callback */
         if (!tty->ops->write)
                 return -EINVAL;
 
-        /* Pass the codec structure address for use by other ldisc callbacks */
-        tty->disc_data = codec;
+        /* Won't work if no codec pointer has been passed by a card driver */
+        if (!tty->disc_data)
+                return -ENODEV;
 
         if (tty->ops->write(tty, v253_init, len) != len) {
                 ret = -EIO;
@@ -253,16 +239,19 @@ err:
 static void v253_close(struct tty_struct *tty)
 {
         struct snd_soc_codec *codec = tty->disc_data;
+        struct cx20442_priv *cx20442;
 
         tty->disc_data = NULL;
 
         if (!codec)
                 return;
 
+        cx20442 = snd_soc_codec_get_drvdata(codec);
+
         /* Prevent the codec driver from further accessing the modem */
         codec->hw_write = NULL;
-        codec->control_data = NULL;
-        codec->pop_time = 0;
+        cx20442->control_data = NULL;
+        codec->card->pop_time = 0;
 }
 
 /* Line discipline .hangup() */
@@ -277,17 +266,20 @@ static void v253_receive(struct tty_struct *tty,
                                 const unsigned char *cp, char *fp, int count)
 {
         struct snd_soc_codec *codec = tty->disc_data;
+        struct cx20442_priv *cx20442;
 
         if (!codec)
                 return;
 
-        if (!codec->control_data) {
+        cx20442 = snd_soc_codec_get_drvdata(codec);
+
+        if (!cx20442->control_data) {
                 /* First modem response, complete setup procedure */
 
                 /* Set up codec driver access to modem controls */
-                codec->control_data = tty;
+                cx20442->control_data = tty;
                 codec->hw_write = (hw_write_t)tty->ops->write;
-                codec->pop_time = 1;
+                codec->card->pop_time = 1;
         }
 }
 
@@ -313,8 +305,8 @@ EXPORT_SYMBOL_GPL(v253_ops);
  * Codec DAI
  */
 
-struct snd_soc_dai cx20442_dai = {
-        .name = "CX20442",
+static struct snd_soc_dai_driver cx20442_dai = {
+        .name = "cx20442-voice",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -330,142 +322,68 @@ struct snd_soc_dai cx20442_dai = {
                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
         },
 };
-EXPORT_SYMBOL_GPL(cx20442_dai);
 
-static int cx20442_codec_probe(struct platform_device *pdev)
+static int cx20442_codec_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret;
-
-        if (!cx20442_codec) {
-                dev_err(&pdev->dev, "cx20442 not yet discovered\n");
-                return -ENODEV;
-        }
-        codec = cx20442_codec;
-
-        socdev->card->codec = codec;
+        struct cx20442_priv *cx20442;
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "failed to create pcms\n");
-                goto pcm_err;
-        }
+        cx20442 = kzalloc(sizeof(struct cx20442_priv), GFP_KERNEL);
+        if (cx20442 == NULL)
+                return -ENOMEM;
+        snd_soc_codec_set_drvdata(codec, cx20442);
 
-        cx20442_add_widgets(codec);
+        cx20442->control_data = NULL;
+        codec->hw_write = NULL;
+        codec->card->pop_time = 0;
 
-pcm_err:
-        return ret;
+        return 0;
 }
 
 /* power down chip */
-static int cx20442_codec_remove(struct platform_device *pdev)
+static int cx20442_codec_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+        struct cx20442_priv *cx20442 = snd_soc_codec_get_drvdata(codec);
 
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
+        if (cx20442->control_data) {
+                        struct tty_struct *tty = cx20442->control_data;
+                        tty_hangup(tty);
+        }
 
+        kfree(cx20442);
         return 0;
 }
 
-struct snd_soc_codec_device cx20442_codec_dev = {
+static const u8 cx20442_reg;
+
+static struct snd_soc_codec_driver cx20442_codec_dev = {
         .probe =        cx20442_codec_probe,
         .remove =       cx20442_codec_remove,
+        .reg_cache_default = &cx20442_reg,
+        .reg_cache_size = 1,
+        .reg_word_size = sizeof(u8),
+        .read = cx20442_read_reg_cache,
+        .write = cx20442_write,
+        .dapm_widgets = cx20442_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(cx20442_dapm_widgets),
+        .dapm_routes = cx20442_audio_map,
+        .num_dapm_routes = ARRAY_SIZE(cx20442_audio_map),
 };
-EXPORT_SYMBOL_GPL(cx20442_codec_dev);
-
-static int cx20442_register(struct cx20442_priv *cx20442)
-{
-        struct snd_soc_codec *codec = &cx20442->codec;
-        int ret;
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "CX20442";
-        codec->owner = THIS_MODULE;
-        snd_soc_codec_set_drvdata(codec, cx20442);
-
-        codec->dai = &cx20442_dai;
-        codec->num_dai = 1;
-
-        codec->reg_cache = &cx20442->reg_cache;
-        codec->reg_cache_size = ARRAY_SIZE(cx20442->reg_cache);
-        codec->read = cx20442_read_reg_cache;
-        codec->write = cx20442_write;
-
-        codec->bias_level = SND_SOC_BIAS_OFF;
-
-        cx20442_dai.dev = codec->dev;
-
-        cx20442_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&cx20442_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
-
-        return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        cx20442_codec = NULL;
-        kfree(cx20442);
-        return ret;
-}
-
-static void cx20442_unregister(struct cx20442_priv *cx20442)
-{
-        snd_soc_unregister_dai(&cx20442_dai);
-        snd_soc_unregister_codec(&cx20442->codec);
-
-        cx20442_codec = NULL;
-        kfree(cx20442);
-}
 
 static int cx20442_platform_probe(struct platform_device *pdev)
 {
-        struct cx20442_priv *cx20442;
-        struct snd_soc_codec *codec;
-
-        cx20442 = kzalloc(sizeof(struct cx20442_priv), GFP_KERNEL);
-        if (cx20442 == NULL)
-                return -ENOMEM;
-
-        codec = &cx20442->codec;
-
-        codec->control_data = NULL;
-        codec->hw_write = NULL;
-        codec->pop_time = 0;
-
-        codec->dev = &pdev->dev;
-        platform_set_drvdata(pdev, cx20442);
-
-        return cx20442_register(cx20442);
+        return snd_soc_register_codec(&pdev->dev,
+                        &cx20442_codec_dev, &cx20442_dai, 1);
 }
 
 static int __exit cx20442_platform_remove(struct platform_device *pdev)
 {
-        struct cx20442_priv *cx20442 = platform_get_drvdata(pdev);
-
-        cx20442_unregister(cx20442);
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
 static struct platform_driver cx20442_platform_driver = {
         .driver = {
-                .name = "cx20442",
+                .name = "cx20442-codec",
                 .owner = THIS_MODULE,
                 },
         .probe = cx20442_platform_probe,
@@ -487,4 +405,4 @@ module_exit(cx20442_exit);
 MODULE_DESCRIPTION("ASoC CX20442-11 voice modem codec driver");
 MODULE_AUTHOR("Janusz Krzysztofik");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:cx20442");
+MODULE_ALIAS("platform:cx20442-codec");
diff --git a/sound/soc/codecs/cx20442.h b/sound/soc/codecs/cx20442.h
index 688a5eb62e17..c7a7c79ef0cd 100644
--- a/sound/soc/codecs/cx20442.h
+++ b/sound/soc/codecs/cx20442.h
@@ -13,8 +13,6 @@
 #ifndef _CX20442_CODEC_H
 #define _CX20442_CODEC_H
 
-extern struct snd_soc_dai cx20442_dai;
-extern struct snd_soc_codec_device cx20442_codec_dev;
 extern struct tty_ldisc_ops v253_ops;
 
 #endif
diff --git a/sound/soc/codecs/da7210.c b/sound/soc/codecs/da7210.c
index 3c51d6a57523..92fd9d7a9221 100644
--- a/sound/soc/codecs/da7210.c
+++ b/sound/soc/codecs/da7210.c
@@ -21,12 +21,10 @@
 #include <linux/slab.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
-#include <sound/soc-dapm.h>
+#include <sound/soc.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
-#include "da7210.h"
-
 /* DA7210 register space */
 #define DA7210_STATUS                   0x02
 #define DA7210_STARTUP1                 0x03
@@ -162,11 +160,10 @@ static const struct snd_kcontrol_new da7210_snd_controls[] = {
 
 /* Codec private data */
 struct da7210_priv {
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
-static struct snd_soc_codec *da7210_codec;
-
 /*
  * Register cache
  */
@@ -209,12 +206,12 @@ static int da7210_write(struct snd_soc_codec *codec, u32 reg, u32 value)
         u8 *cache = codec->reg_cache;
         u8 data[2];
 
-        BUG_ON(codec->volatile_register);
+        BUG_ON(codec->driver->volatile_register);
 
         data[0] = reg & 0xff;
         data[1] = value & 0xff;
 
-        if (reg >= codec->reg_cache_size)
+        if (reg >= codec->driver->reg_cache_size)
                 return -EIO;
 
         if (2 != codec->hw_write(codec->control_data, data, 2))
@@ -267,8 +264,7 @@ static int da7210_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u32 dai_cfg1;
         u32 hpf_reg, hpf_mask, hpf_value;
         u32 fs, bypass;
@@ -430,9 +426,8 @@ static struct snd_soc_dai_ops da7210_dai_ops = {
         .set_fmt        = da7210_set_dai_fmt,
 };
 
-struct snd_soc_dai da7210_dai = {
-        .name = "DA7210 IIS",
-        .id = 0,
+static struct snd_soc_dai_driver da7210_dai = {
+        .name = "da7210-hifi",
         /* playback capabilities */
         .playback = {
                 .stream_name = "Playback",
@@ -452,55 +447,15 @@ struct snd_soc_dai da7210_dai = {
         .ops = &da7210_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(da7210_dai);
 
-/*
- * Initialize the DA7210 driver
- * register the mixer and dsp interfaces with the kernel
- */
-static int da7210_init(struct da7210_priv *da7210)
+static int da7210_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = &da7210->codec;
-        int ret = 0;
+        struct da7210_priv *da7210 = snd_soc_codec_get_drvdata(codec);
 
-        if (da7210_codec) {
-                dev_err(codec->dev, "Another da7210 is registered\n");
-                return -EINVAL;
-        }
+        dev_info(codec->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, da7210);
-        codec->name             = "DA7210";
-        codec->owner            = THIS_MODULE;
-        codec->read             = da7210_read;
-        codec->write            = da7210_write;
-        codec->dai              = &da7210_dai;
-        codec->num_dai          = 1;
+        codec->control_data     = da7210->control_data;
         codec->hw_write         = (hw_write_t)i2c_master_send;
-        codec->reg_cache_size   = ARRAY_SIZE(da7210_reg);
-        codec->reg_cache        = kmemdup(da7210_reg,
-                                          sizeof(da7210_reg), GFP_KERNEL);
-
-        if (!codec->reg_cache)
-                return -ENOMEM;
-
-        da7210_dai.dev = codec->dev;
-        da7210_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret) {
-                dev_err(codec->dev, "Failed to register CODEC: %d\n", ret);
-                goto init_err;
-        }
-
-        ret = snd_soc_register_dai(&da7210_dai);
-        if (ret) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto codec_err;
-        }
 
         /* FIXME
          *
@@ -583,54 +538,50 @@ static int da7210_init(struct da7210_priv *da7210)
         /* Activate all enabled subsystem */
         da7210_write(codec, DA7210_STARTUP1, DA7210_SC_MST_EN);
 
-        return ret;
-
-codec_err:
-        snd_soc_unregister_codec(codec);
-init_err:
-        kfree(codec->reg_cache);
-        codec->reg_cache = NULL;
+        snd_soc_add_controls(codec, da7210_snd_controls,
+                             ARRAY_SIZE(da7210_snd_controls));
 
-        return ret;
+        dev_info(codec->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);
 
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_da7210 = {
+        .probe                  = da7210_probe,
+        .read                   = da7210_read,
+        .write                  = da7210_write,
+        .reg_cache_size         = ARRAY_SIZE(da7210_reg),
+        .reg_word_size          = sizeof(u8),
+        .reg_cache_default      = da7210_reg,
+};
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static int __devinit da7210_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct da7210_priv *da7210;
-        struct snd_soc_codec *codec;
         int ret;
 
         da7210 = kzalloc(sizeof(struct da7210_priv), GFP_KERNEL);
         if (!da7210)
                 return -ENOMEM;
 
-        codec = &da7210->codec;
-        codec->dev = &i2c->dev;
-
         i2c_set_clientdata(i2c, da7210);
-        codec->control_data = i2c;
+        da7210->control_data = i2c;
+        da7210->control_type = SND_SOC_I2C;
 
-        ret = da7210_init(da7210);
-        if (ret < 0) {
-                pr_err("Failed to initialise da7210 audio codec\n");
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_da7210, &da7210_dai, 1);
+        if (ret < 0)
                 kfree(da7210);
-        }
 
         return ret;
 }
 
 static int __devexit da7210_i2c_remove(struct i2c_client *client)
 {
-        struct da7210_priv *da7210 = i2c_get_clientdata(client);
-
-        snd_soc_unregister_dai(&da7210_dai);
-        kfree(da7210->codec.reg_cache);
-        kfree(da7210);
-        da7210_codec = NULL;
-
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -643,59 +594,15 @@ MODULE_DEVICE_TABLE(i2c, da7210_i2c_id);
 /* I2C codec control layer */
 static struct i2c_driver da7210_i2c_driver = {
         .driver = {
-                .name = "DA7210 I2C Codec",
+                .name = "da7210-codec",
                 .owner = THIS_MODULE,
         },
-        .probe = da7210_i2c_probe,
-        .remove =  __devexit_p(da7210_i2c_remove),
-        .id_table = da7210_i2c_id,
+        .probe          = da7210_i2c_probe,
+        .remove         = __devexit_p(da7210_i2c_remove),
+        .id_table       = da7210_i2c_id,
 };
 #endif
 
-static int da7210_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret;
-
-        if (!da7210_codec) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = da7210_codec;
-        codec = da7210_codec;
-
-        /* Register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0)
-                goto pcm_err;
-
-        snd_soc_add_controls(da7210_codec, da7210_snd_controls,
-                             ARRAY_SIZE(da7210_snd_controls));
-
-        dev_info(&pdev->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);
-
-pcm_err:
-        return ret;
-}
-
-static int da7210_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_da7210 = {
-        .probe =        da7210_probe,
-        .remove =       da7210_remove,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_da7210);
-
 static int __init da7210_modinit(void)
 {
         int ret = 0;
diff --git a/sound/soc/codecs/da7210.h b/sound/soc/codecs/da7210.h
deleted file mode 100644
index 390d621eb742..000000000000
--- a/sound/soc/codecs/da7210.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * da7210.h  --  audio driver for da7210
- *
- * Copyright (c) 2009 Dialog Semiconductor
- * Written by David Chen <Dajun.chen@diasemi.com>
- *
- * Copyright (C) 2009 Renesas Solutions Corp.
- * Cleanups by Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef _DA7210_H
-#define _DA7210_H
-
-extern struct snd_soc_dai da7210_dai;
-extern struct snd_soc_codec_device soc_codec_dev_da7210;
-
-#endif
-
diff --git a/sound/soc/codecs/dfbmcs320.c b/sound/soc/codecs/dfbmcs320.c
new file mode 100644
index 000000000000..704bbde65737
--- /dev/null
+++ b/sound/soc/codecs/dfbmcs320.c
@@ -0,0 +1,72 @@
+/*
+ * Driver for the DFBM-CS320 bluetooth module
+ * Copyright 2011 Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <sound/soc.h>
+
+static struct snd_soc_dai_driver dfbmcs320_dai = {
+        .name = "dfbmcs320-pcm",
+        .playback = {
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = SNDRV_PCM_RATE_8000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .capture = {
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = SNDRV_PCM_RATE_8000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_dfbmcs320;
+
+static int __devinit dfbmcs320_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_dfbmcs320,
+                        &dfbmcs320_dai, 1);
+}
+
+static int __devexit dfbmcs320_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+
+        return 0;
+}
+
+static struct platform_driver dfmcs320_driver = {
+        .driver = {
+                .name = "dfbmcs320",
+                .owner = THIS_MODULE,
+        },
+        .probe = dfbmcs320_probe,
+        .remove = __devexit_p(dfbmcs320_remove),
+};
+
+static int __init dfbmcs320_init(void)
+{
+        return platform_driver_register(&dfmcs320_driver);
+}
+module_init(dfbmcs320_init);
+
+static void __exit dfbmcs320_exit(void)
+{
+        platform_driver_unregister(&dfmcs320_driver);
+}
+module_exit(dfbmcs320_exit);
+
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("ASoC DFBM-CS320 bluethooth module driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/dmic.c b/sound/soc/codecs/dmic.c
new file mode 100644
index 000000000000..f9a87737ec16
--- /dev/null
+++ b/sound/soc/codecs/dmic.c
@@ -0,0 +1,105 @@
+/*
+ * dmic.c  --  SoC audio for Generic Digital MICs
+ *
+ * Author: Liam Girdwood <lrg@slimlogic.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+static struct snd_soc_dai_driver dmic_dai = {
+        .name = "dmic-hifi",
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 1,
+                .channels_max = 8,
+                .rates = SNDRV_PCM_RATE_CONTINUOUS,
+                .formats = SNDRV_PCM_FMTBIT_S32_LE
+                        | SNDRV_PCM_FMTBIT_S24_LE
+                        | SNDRV_PCM_FMTBIT_S16_LE,
+        },
+};
+
+static const struct snd_soc_dapm_widget dmic_dapm_widgets[] = {
+        SND_SOC_DAPM_AIF_OUT("DMIC AIF", "Capture", 0,
+                             SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_INPUT("DMic"),
+};
+
+static const struct snd_soc_dapm_route intercon[] = {
+        {"DMIC AIF", NULL, "DMic"},
+};
+
+static int dmic_probe(struct snd_soc_codec *codec)
+{
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+        snd_soc_dapm_new_controls(dapm, dmic_dapm_widgets,
+                                  ARRAY_SIZE(dmic_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
+        snd_soc_dapm_new_widgets(dapm);
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_dmic = {
+        .probe  = dmic_probe,
+};
+
+static int __devinit dmic_dev_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_dmic, &dmic_dai, 1);
+}
+
+static int __devexit dmic_dev_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+MODULE_ALIAS("platform:dmic-codec");
+
+static struct platform_driver dmic_driver = {
+        .driver = {
+                .name = "dmic-codec",
+                .owner = THIS_MODULE,
+        },
+        .probe = dmic_dev_probe,
+        .remove = __devexit_p(dmic_dev_remove),
+};
+
+static int __init dmic_init(void)
+{
+        return platform_driver_register(&dmic_driver);
+}
+module_init(dmic_init);
+
+static void __exit dmic_exit(void)
+{
+        platform_driver_unregister(&dmic_driver);
+}
+module_exit(dmic_exit);
+
+MODULE_DESCRIPTION("Generic DMIC driver");
+MODULE_AUTHOR("Liam Girdwood <lrg@slimlogic.co.uk>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/jz4740.c b/sound/soc/codecs/jz4740.c
index 66557de1e4fe..e373f8f06907 100644
--- a/sound/soc/codecs/jz4740.c
+++ b/sound/soc/codecs/jz4740.c
@@ -22,7 +22,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/initval.h>
-#include <sound/soc-dapm.h>
 #include <sound/soc.h>
 
 #define JZ4740_REG_CODEC_1 0x0
@@ -74,29 +73,22 @@ static const uint32_t jz4740_codec_regs[] = {
 struct jz4740_codec {
         void __iomem *base;
         struct resource *mem;
-
-        uint32_t reg_cache[2];
-        struct snd_soc_codec codec;
 };
 
-static inline struct jz4740_codec *codec_to_jz4740(struct snd_soc_codec *codec)
-{
-        return container_of(codec, struct jz4740_codec, codec);
-}
-
 static unsigned int jz4740_codec_read(struct snd_soc_codec *codec,
         unsigned int reg)
 {
-        struct jz4740_codec *jz4740_codec = codec_to_jz4740(codec);
+        struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
         return readl(jz4740_codec->base + (reg << 2));
 }
 
 static int jz4740_codec_write(struct snd_soc_codec *codec, unsigned int reg,
         unsigned int val)
 {
-        struct jz4740_codec *jz4740_codec = codec_to_jz4740(codec);
+        struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
+        u32 *cache = codec->reg_cache;
 
-        jz4740_codec->reg_cache[reg] = val;
+        cache[reg] = val;
         writel(val, jz4740_codec->base + (reg << 2));
 
         return 0;
@@ -172,8 +164,7 @@ static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
 {
         uint32_t val;
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec =rtd->codec;
 
         switch (params_rate(params)) {
         case 8000:
@@ -219,8 +210,8 @@ static struct snd_soc_dai_ops jz4740_codec_dai_ops = {
         .hw_params = jz4740_codec_hw_params,
 };
 
-struct snd_soc_dai jz4740_codec_dai = {
-        .name = "jz4740",
+static struct snd_soc_dai_driver jz4740_codec_dai = {
+        .name = "jz4740-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -238,7 +229,6 @@ struct snd_soc_dai jz4740_codec_dai = {
         .ops = &jz4740_codec_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(jz4740_codec_dai);
 
 static void jz4740_codec_wakeup(struct snd_soc_codec *codec)
 {
@@ -275,7 +265,7 @@ static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
                 break;
         case SND_SOC_BIAS_STANDBY:
                 /* The only way to clear the suspend flag is to reset the codec */
-                if (codec->bias_level == SND_SOC_BIAS_OFF)
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
                         jz4740_codec_wakeup(codec);
 
                 mask = JZ4740_CODEC_1_VREF_DISABLE |
@@ -297,68 +287,37 @@ static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
 
-static struct snd_soc_codec *jz4740_codec_codec;
-
-static int jz4740_codec_dev_probe(struct platform_device *pdev)
+static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
 {
-        int ret;
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = jz4740_codec_codec;
-
-        BUG_ON(!codec);
-
-        socdev->card->codec = codec;
-
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret) {
-                dev_err(&pdev->dev, "Failed to create pcms: %d\n", ret);
-                return ret;
-        }
-
-        snd_soc_add_controls(codec, jz4740_codec_controls,
-                ARRAY_SIZE(jz4740_codec_controls));
-
-        snd_soc_dapm_new_controls(codec, jz4740_codec_dapm_widgets,
-                ARRAY_SIZE(jz4740_codec_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, jz4740_codec_dapm_routes,
-                ARRAY_SIZE(jz4740_codec_dapm_routes));
+        snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
+                        JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
 
-        snd_soc_dapm_new_widgets(codec);
+        jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
 }
 
-static int jz4740_codec_dev_remove(struct platform_device *pdev)
+static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
+        jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
 
-static int jz4740_codec_suspend(struct platform_device *pdev, pm_message_t state)
+static int jz4740_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 }
 
-static int jz4740_codec_resume(struct platform_device *pdev)
+static int jz4740_codec_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 }
 
@@ -367,19 +326,30 @@ static int jz4740_codec_resume(struct platform_device *pdev)
 #define jz4740_codec_resume NULL
 #endif
 
-struct snd_soc_codec_device soc_codec_dev_jz4740_codec = {
+static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
         .probe = jz4740_codec_dev_probe,
         .remove = jz4740_codec_dev_remove,
         .suspend = jz4740_codec_suspend,
         .resume = jz4740_codec_resume,
+        .read = jz4740_codec_read,
+        .write = jz4740_codec_write,
+        .set_bias_level = jz4740_codec_set_bias_level,
+        .reg_cache_default      = jz4740_codec_regs,
+        .reg_word_size = sizeof(u32),
+        .reg_cache_size = 2,
+
+        .controls = jz4740_codec_controls,
+        .num_controls = ARRAY_SIZE(jz4740_codec_controls),
+        .dapm_widgets = jz4740_codec_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
+        .dapm_routes = jz4740_codec_dapm_routes,
+        .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_jz4740_codec);
 
 static int __devinit jz4740_codec_probe(struct platform_device *pdev)
 {
         int ret;
         struct jz4740_codec *jz4740_codec;
-        struct snd_soc_codec *codec;
         struct resource *mem;
 
         jz4740_codec = kzalloc(sizeof(*jz4740_codec), GFP_KERNEL);
@@ -408,55 +378,17 @@ static int __devinit jz4740_codec_probe(struct platform_device *pdev)
         }
         jz4740_codec->mem = mem;
 
-        jz4740_codec_dai.dev = &pdev->dev;
-
-        codec = &jz4740_codec->codec;
-
-        codec->dev              = &pdev->dev;
-        codec->name             = "jz4740";
-        codec->owner            = THIS_MODULE;
-
-        codec->read             = jz4740_codec_read;
-        codec->write            = jz4740_codec_write;
-        codec->set_bias_level   = jz4740_codec_set_bias_level;
-        codec->bias_level       = SND_SOC_BIAS_OFF;
-
-        codec->dai              = &jz4740_codec_dai;
-        codec->num_dai          = 1;
-
-        codec->reg_cache        = jz4740_codec->reg_cache;
-        codec->reg_cache_size   = 2;
-        memcpy(codec->reg_cache, jz4740_codec_regs, sizeof(jz4740_codec_regs));
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        jz4740_codec_codec = codec;
-
-        snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
-                        JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
-
         platform_set_drvdata(pdev, jz4740_codec);
 
-        ret = snd_soc_register_codec(codec);
+        ret = snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
         if (ret) {
                 dev_err(&pdev->dev, "Failed to register codec\n");
                 goto err_iounmap;
         }
 
-        ret = snd_soc_register_dai(&jz4740_codec_dai);
-        if (ret) {
-                dev_err(&pdev->dev, "Failed to register codec dai\n");
-                goto err_unregister_codec;
-        }
-
-        jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-
         return 0;
 
-err_unregister_codec:
-        snd_soc_unregister_codec(codec);
 err_iounmap:
         iounmap(jz4740_codec->base);
 err_release_mem_region:
@@ -472,8 +404,7 @@ static int __devexit jz4740_codec_remove(struct platform_device *pdev)
         struct jz4740_codec *jz4740_codec = platform_get_drvdata(pdev);
         struct resource *mem = jz4740_codec->mem;
 
-        snd_soc_unregister_dai(&jz4740_codec_dai);
-        snd_soc_unregister_codec(&jz4740_codec->codec);
+        snd_soc_unregister_codec(&pdev->dev);
 
         iounmap(jz4740_codec->base);
         release_mem_region(mem->start, resource_size(mem));
diff --git a/sound/soc/codecs/jz4740.h b/sound/soc/codecs/jz4740.h
deleted file mode 100644
index b5a0691be763..000000000000
--- a/sound/soc/codecs/jz4740.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __SND_SOC_CODECS_JZ4740_CODEC_H__
-#define __SND_SOC_CODECS_JZ4740_CODEC_H__
-
-extern struct snd_soc_dai jz4740_codec_dai;
-extern struct snd_soc_codec_device soc_codec_dev_jz4740_codec;
-
-#endif
diff --git a/sound/soc/codecs/lm4857.c b/sound/soc/codecs/lm4857.c
new file mode 100644
index 000000000000..2c2a681da0d7
--- /dev/null
+++ b/sound/soc/codecs/lm4857.c
@@ -0,0 +1,276 @@
+/*
+ * LM4857 AMP driver
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory
+ *         graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ * Copyright 2011 Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+
+#include <sound/core.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+
+struct lm4857 {
+        struct i2c_client *i2c;
+        uint8_t mode;
+};
+
+static const uint8_t lm4857_default_regs[] = {
+        0x00, 0x00, 0x00, 0x00,
+};
+
+/* The register offsets in the cache array */
+#define LM4857_MVOL 0
+#define LM4857_LVOL 1
+#define LM4857_RVOL 2
+#define LM4857_CTRL 3
+
+/* the shifts required to set these bits */
+#define LM4857_3D 5
+#define LM4857_WAKEUP 5
+#define LM4857_EPGAIN 4
+
+static int lm4857_write(struct snd_soc_codec *codec, unsigned int reg,
+                unsigned int value)
+{
+        uint8_t data;
+        int ret;
+
+        ret = snd_soc_cache_write(codec, reg, value);
+        if (ret < 0)
+                return ret;
+
+        data = (reg << 6) | value;
+        ret = i2c_master_send(codec->control_data, &data, 1);
+        if (ret != 1) {
+                dev_err(codec->dev, "Failed to write register: %d\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+
+static unsigned int lm4857_read(struct snd_soc_codec *codec,
+                unsigned int reg)
+{
+        unsigned int val;
+        int ret;
+
+        ret = snd_soc_cache_read(codec, reg, &val);
+        if (ret)
+                return -1;
+
+        return val;
+}
+
+static int lm4857_get_mode(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct lm4857 *lm4857 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = lm4857->mode;
+
+        return 0;
+}
+
+static int lm4857_set_mode(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct lm4857 *lm4857 = snd_soc_codec_get_drvdata(codec);
+        uint8_t value = ucontrol->value.integer.value[0];
+
+        lm4857->mode = value;
+
+        if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
+                snd_soc_update_bits(codec, LM4857_CTRL, 0x0F, value + 6);
+
+        return 1;
+}
+
+static int lm4857_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        struct lm4857 *lm4857 = snd_soc_codec_get_drvdata(codec);
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                snd_soc_update_bits(codec, LM4857_CTRL, 0x0F, lm4857->mode + 6);
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                snd_soc_update_bits(codec, LM4857_CTRL, 0x0F, 0);
+                break;
+        default:
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+
+        return 0;
+}
+
+static const char *lm4857_mode[] = {
+        "Earpiece",
+        "Loudspeaker",
+        "Loudspeaker + Headphone",
+        "Headphone",
+};
+
+static const struct soc_enum lm4857_mode_enum =
+        SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(lm4857_mode), lm4857_mode);
+
+static const struct snd_soc_dapm_widget lm4857_dapm_widgets[] = {
+        SND_SOC_DAPM_INPUT("IN"),
+
+        SND_SOC_DAPM_OUTPUT("LS"),
+        SND_SOC_DAPM_OUTPUT("HP"),
+        SND_SOC_DAPM_OUTPUT("EP"),
+};
+
+static const DECLARE_TLV_DB_SCALE(stereo_tlv, -4050, 150, 0);
+static const DECLARE_TLV_DB_SCALE(mono_tlv, -3450, 150, 0);
+
+static const struct snd_kcontrol_new lm4857_controls[] = {
+        SOC_SINGLE_TLV("Left Playback Volume", LM4857_LVOL, 0, 31, 0,
+                stereo_tlv),
+        SOC_SINGLE_TLV("Right Playback Volume", LM4857_RVOL, 0, 31, 0,
+                stereo_tlv),
+        SOC_SINGLE_TLV("Mono Playback Volume", LM4857_MVOL, 0, 31, 0,
+                mono_tlv),
+        SOC_SINGLE("Spk 3D Playback Switch", LM4857_LVOL, LM4857_3D, 1, 0),
+        SOC_SINGLE("HP 3D Playback Switch", LM4857_RVOL, LM4857_3D, 1, 0),
+        SOC_SINGLE("Fast Wakeup Playback Switch", LM4857_CTRL,
+                LM4857_WAKEUP, 1, 0),
+        SOC_SINGLE("Earpiece 6dB Playback Switch", LM4857_CTRL,
+                LM4857_EPGAIN, 1, 0),
+
+        SOC_ENUM_EXT("Mode", lm4857_mode_enum,
+                lm4857_get_mode, lm4857_set_mode),
+};
+
+/* There is a demux between the input signal and the output signals.
+ * Currently there is no easy way to model it in ASoC and since it does not make
+ * much of a difference in practice simply connect the input direclty to the
+ * outputs. */
+static const struct snd_soc_dapm_route lm4857_routes[] = {
+        {"LS", NULL, "IN"},
+        {"HP", NULL, "IN"},
+        {"EP", NULL, "IN"},
+};
+
+static int lm4857_probe(struct snd_soc_codec *codec)
+{
+        struct lm4857 *lm4857 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret;
+
+        codec->control_data = lm4857->i2c;
+
+        ret = snd_soc_add_controls(codec, lm4857_controls,
+                        ARRAY_SIZE(lm4857_controls));
+        if (ret)
+                return ret;
+
+        ret = snd_soc_dapm_new_controls(dapm, lm4857_dapm_widgets,
+                        ARRAY_SIZE(lm4857_dapm_widgets));
+        if (ret)
+                return ret;
+
+        ret = snd_soc_dapm_add_routes(dapm, lm4857_routes,
+                        ARRAY_SIZE(lm4857_routes));
+        if (ret)
+                return ret;
+
+        snd_soc_dapm_new_widgets(dapm);
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_lm4857 = {
+        .write = lm4857_write,
+        .read = lm4857_read,
+        .probe = lm4857_probe,
+        .reg_cache_size = ARRAY_SIZE(lm4857_default_regs),
+        .reg_word_size = sizeof(uint8_t),
+        .reg_cache_default = lm4857_default_regs,
+        .set_bias_level = lm4857_set_bias_level,
+};
+
+static int __devinit lm4857_i2c_probe(struct i2c_client *i2c,
+        const struct i2c_device_id *id)
+{
+        struct lm4857 *lm4857;
+        int ret;
+
+        lm4857 = kzalloc(sizeof(*lm4857), GFP_KERNEL);
+        if (!lm4857)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, lm4857);
+
+        lm4857->i2c = i2c;
+
+        ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_lm4857, NULL, 0);
+
+        if (ret) {
+                kfree(lm4857);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int __devexit lm4857_i2c_remove(struct i2c_client *i2c)
+{
+        struct lm4857 *lm4857 = i2c_get_clientdata(i2c);
+
+        snd_soc_unregister_codec(&i2c->dev);
+        kfree(lm4857);
+
+        return 0;
+}
+
+static const struct i2c_device_id lm4857_i2c_id[] = {
+        { "lm4857", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, lm4857_i2c_id);
+
+static struct i2c_driver lm4857_i2c_driver = {
+        .driver = {
+                .name = "lm4857",
+                .owner = THIS_MODULE,
+        },
+        .probe = lm4857_i2c_probe,
+        .remove = __devexit_p(lm4857_i2c_remove),
+        .id_table = lm4857_i2c_id,
+};
+
+static int __init lm4857_init(void)
+{
+        return i2c_add_driver(&lm4857_i2c_driver);
+}
+module_init(lm4857_init);
+
+static void __exit lm4857_exit(void)
+{
+        i2c_del_driver(&lm4857_i2c_driver);
+}
+module_exit(lm4857_exit);
+
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("LM4857 amplifier driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c
new file mode 100644
index 000000000000..4173b67c94d1
--- /dev/null
+++ b/sound/soc/codecs/max98088.c
@@ -0,0 +1,2125 @@
+/*
+ * max98088.c -- MAX98088 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Maxim Integrated Products
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <linux/slab.h>
+#include <asm/div64.h>
+#include <sound/max98088.h>
+#include "max98088.h"
+
+enum max98088_type {
+       MAX98088,
+       MAX98089,
+};
+
+struct max98088_cdata {
+       unsigned int rate;
+       unsigned int fmt;
+       int eq_sel;
+};
+
+struct max98088_priv {
+       enum max98088_type devtype;
+       void *control_data;
+       struct max98088_pdata *pdata;
+       unsigned int sysclk;
+       struct max98088_cdata dai[2];
+       int eq_textcnt;
+       const char **eq_texts;
+       struct soc_enum eq_enum;
+       u8 ina_state;
+       u8 inb_state;
+       unsigned int ex_mode;
+       unsigned int digmic;
+       unsigned int mic1pre;
+       unsigned int mic2pre;
+       unsigned int extmic_mode;
+};
+
+static const u8 max98088_reg[M98088_REG_CNT] = {
+       0x00, /* 00 IRQ status */
+       0x00, /* 01 MIC status */
+       0x00, /* 02 jack status */
+       0x00, /* 03 battery voltage */
+       0x00, /* 04 */
+       0x00, /* 05 */
+       0x00, /* 06 */
+       0x00, /* 07 */
+       0x00, /* 08 */
+       0x00, /* 09 */
+       0x00, /* 0A */
+       0x00, /* 0B */
+       0x00, /* 0C */
+       0x00, /* 0D */
+       0x00, /* 0E */
+       0x00, /* 0F interrupt enable */
+
+       0x00, /* 10 master clock */
+       0x00, /* 11 DAI1 clock mode */
+       0x00, /* 12 DAI1 clock control */
+       0x00, /* 13 DAI1 clock control */
+       0x00, /* 14 DAI1 format */
+       0x00, /* 15 DAI1 clock */
+       0x00, /* 16 DAI1 config */
+       0x00, /* 17 DAI1 TDM */
+       0x00, /* 18 DAI1 filters */
+       0x00, /* 19 DAI2 clock mode */
+       0x00, /* 1A DAI2 clock control */
+       0x00, /* 1B DAI2 clock control */
+       0x00, /* 1C DAI2 format */
+       0x00, /* 1D DAI2 clock */
+       0x00, /* 1E DAI2 config */
+       0x00, /* 1F DAI2 TDM */
+
+       0x00, /* 20 DAI2 filters */
+       0x00, /* 21 data config */
+       0x00, /* 22 DAC mixer */
+       0x00, /* 23 left ADC mixer */
+       0x00, /* 24 right ADC mixer */
+       0x00, /* 25 left HP mixer */
+       0x00, /* 26 right HP mixer */
+       0x00, /* 27 HP control */
+       0x00, /* 28 left REC mixer */
+       0x00, /* 29 right REC mixer */
+       0x00, /* 2A REC control */
+       0x00, /* 2B left SPK mixer */
+       0x00, /* 2C right SPK mixer */
+       0x00, /* 2D SPK control */
+       0x00, /* 2E sidetone */
+       0x00, /* 2F DAI1 playback level */
+
+       0x00, /* 30 DAI1 playback level */
+       0x00, /* 31 DAI2 playback level */
+       0x00, /* 32 DAI2 playbakc level */
+       0x00, /* 33 left ADC level */
+       0x00, /* 34 right ADC level */
+       0x00, /* 35 MIC1 level */
+       0x00, /* 36 MIC2 level */
+       0x00, /* 37 INA level */
+       0x00, /* 38 INB level */
+       0x00, /* 39 left HP volume */
+       0x00, /* 3A right HP volume */
+       0x00, /* 3B left REC volume */
+       0x00, /* 3C right REC volume */
+       0x00, /* 3D left SPK volume */
+       0x00, /* 3E right SPK volume */
+       0x00, /* 3F MIC config */
+
+       0x00, /* 40 MIC threshold */
+       0x00, /* 41 excursion limiter filter */
+       0x00, /* 42 excursion limiter threshold */
+       0x00, /* 43 ALC */
+       0x00, /* 44 power limiter threshold */
+       0x00, /* 45 power limiter config */
+       0x00, /* 46 distortion limiter config */
+       0x00, /* 47 audio input */
+       0x00, /* 48 microphone */
+       0x00, /* 49 level control */
+       0x00, /* 4A bypass switches */
+       0x00, /* 4B jack detect */
+       0x00, /* 4C input enable */
+       0x00, /* 4D output enable */
+       0xF0, /* 4E bias control */
+       0x00, /* 4F DAC power */
+
+       0x0F, /* 50 DAC power */
+       0x00, /* 51 system */
+       0x00, /* 52 DAI1 EQ1 */
+       0x00, /* 53 DAI1 EQ1 */
+       0x00, /* 54 DAI1 EQ1 */
+       0x00, /* 55 DAI1 EQ1 */
+       0x00, /* 56 DAI1 EQ1 */
+       0x00, /* 57 DAI1 EQ1 */
+       0x00, /* 58 DAI1 EQ1 */
+       0x00, /* 59 DAI1 EQ1 */
+       0x00, /* 5A DAI1 EQ1 */
+       0x00, /* 5B DAI1 EQ1 */
+       0x00, /* 5C DAI1 EQ2 */
+       0x00, /* 5D DAI1 EQ2 */
+       0x00, /* 5E DAI1 EQ2 */
+       0x00, /* 5F DAI1 EQ2 */
+
+       0x00, /* 60 DAI1 EQ2 */
+       0x00, /* 61 DAI1 EQ2 */
+       0x00, /* 62 DAI1 EQ2 */
+       0x00, /* 63 DAI1 EQ2 */
+       0x00, /* 64 DAI1 EQ2 */
+       0x00, /* 65 DAI1 EQ2 */
+       0x00, /* 66 DAI1 EQ3 */
+       0x00, /* 67 DAI1 EQ3 */
+       0x00, /* 68 DAI1 EQ3 */
+       0x00, /* 69 DAI1 EQ3 */
+       0x00, /* 6A DAI1 EQ3 */
+       0x00, /* 6B DAI1 EQ3 */
+       0x00, /* 6C DAI1 EQ3 */
+       0x00, /* 6D DAI1 EQ3 */
+       0x00, /* 6E DAI1 EQ3 */
+       0x00, /* 6F DAI1 EQ3 */
+
+       0x00, /* 70 DAI1 EQ4 */
+       0x00, /* 71 DAI1 EQ4 */
+       0x00, /* 72 DAI1 EQ4 */
+       0x00, /* 73 DAI1 EQ4 */
+       0x00, /* 74 DAI1 EQ4 */
+       0x00, /* 75 DAI1 EQ4 */
+       0x00, /* 76 DAI1 EQ4 */
+       0x00, /* 77 DAI1 EQ4 */
+       0x00, /* 78 DAI1 EQ4 */
+       0x00, /* 79 DAI1 EQ4 */
+       0x00, /* 7A DAI1 EQ5 */
+       0x00, /* 7B DAI1 EQ5 */
+       0x00, /* 7C DAI1 EQ5 */
+       0x00, /* 7D DAI1 EQ5 */
+       0x00, /* 7E DAI1 EQ5 */
+       0x00, /* 7F DAI1 EQ5 */
+
+       0x00, /* 80 DAI1 EQ5 */
+       0x00, /* 81 DAI1 EQ5 */
+       0x00, /* 82 DAI1 EQ5 */
+       0x00, /* 83 DAI1 EQ5 */
+       0x00, /* 84 DAI2 EQ1 */
+       0x00, /* 85 DAI2 EQ1 */
+       0x00, /* 86 DAI2 EQ1 */
+       0x00, /* 87 DAI2 EQ1 */
+       0x00, /* 88 DAI2 EQ1 */
+       0x00, /* 89 DAI2 EQ1 */
+       0x00, /* 8A DAI2 EQ1 */
+       0x00, /* 8B DAI2 EQ1 */
+       0x00, /* 8C DAI2 EQ1 */
+       0x00, /* 8D DAI2 EQ1 */
+       0x00, /* 8E DAI2 EQ2 */
+       0x00, /* 8F DAI2 EQ2 */
+
+       0x00, /* 90 DAI2 EQ2 */
+       0x00, /* 91 DAI2 EQ2 */
+       0x00, /* 92 DAI2 EQ2 */
+       0x00, /* 93 DAI2 EQ2 */
+       0x00, /* 94 DAI2 EQ2 */
+       0x00, /* 95 DAI2 EQ2 */
+       0x00, /* 96 DAI2 EQ2 */
+       0x00, /* 97 DAI2 EQ2 */
+       0x00, /* 98 DAI2 EQ3 */
+       0x00, /* 99 DAI2 EQ3 */
+       0x00, /* 9A DAI2 EQ3 */
+       0x00, /* 9B DAI2 EQ3 */
+       0x00, /* 9C DAI2 EQ3 */
+       0x00, /* 9D DAI2 EQ3 */
+       0x00, /* 9E DAI2 EQ3 */
+       0x00, /* 9F DAI2 EQ3 */
+
+       0x00, /* A0 DAI2 EQ3 */
+       0x00, /* A1 DAI2 EQ3 */
+       0x00, /* A2 DAI2 EQ4 */
+       0x00, /* A3 DAI2 EQ4 */
+       0x00, /* A4 DAI2 EQ4 */
+       0x00, /* A5 DAI2 EQ4 */
+       0x00, /* A6 DAI2 EQ4 */
+       0x00, /* A7 DAI2 EQ4 */
+       0x00, /* A8 DAI2 EQ4 */
+       0x00, /* A9 DAI2 EQ4 */
+       0x00, /* AA DAI2 EQ4 */
+       0x00, /* AB DAI2 EQ4 */
+       0x00, /* AC DAI2 EQ5 */
+       0x00, /* AD DAI2 EQ5 */
+       0x00, /* AE DAI2 EQ5 */
+       0x00, /* AF DAI2 EQ5 */
+
+       0x00, /* B0 DAI2 EQ5 */
+       0x00, /* B1 DAI2 EQ5 */
+       0x00, /* B2 DAI2 EQ5 */
+       0x00, /* B3 DAI2 EQ5 */
+       0x00, /* B4 DAI2 EQ5 */
+       0x00, /* B5 DAI2 EQ5 */
+       0x00, /* B6 DAI1 biquad */
+       0x00, /* B7 DAI1 biquad */
+       0x00, /* B8 DAI1 biquad */
+       0x00, /* B9 DAI1 biquad */
+       0x00, /* BA DAI1 biquad */
+       0x00, /* BB DAI1 biquad */
+       0x00, /* BC DAI1 biquad */
+       0x00, /* BD DAI1 biquad */
+       0x00, /* BE DAI1 biquad */
+       0x00, /* BF DAI1 biquad */
+
+       0x00, /* C0 DAI2 biquad */
+       0x00, /* C1 DAI2 biquad */
+       0x00, /* C2 DAI2 biquad */
+       0x00, /* C3 DAI2 biquad */
+       0x00, /* C4 DAI2 biquad */
+       0x00, /* C5 DAI2 biquad */
+       0x00, /* C6 DAI2 biquad */
+       0x00, /* C7 DAI2 biquad */
+       0x00, /* C8 DAI2 biquad */
+       0x00, /* C9 DAI2 biquad */
+       0x00, /* CA */
+       0x00, /* CB */
+       0x00, /* CC */
+       0x00, /* CD */
+       0x00, /* CE */
+       0x00, /* CF */
+
+       0x00, /* D0 */
+       0x00, /* D1 */
+       0x00, /* D2 */
+       0x00, /* D3 */
+       0x00, /* D4 */
+       0x00, /* D5 */
+       0x00, /* D6 */
+       0x00, /* D7 */
+       0x00, /* D8 */
+       0x00, /* D9 */
+       0x00, /* DA */
+       0x70, /* DB */
+       0x00, /* DC */
+       0x00, /* DD */
+       0x00, /* DE */
+       0x00, /* DF */
+
+       0x00, /* E0 */
+       0x00, /* E1 */
+       0x00, /* E2 */
+       0x00, /* E3 */
+       0x00, /* E4 */
+       0x00, /* E5 */
+       0x00, /* E6 */
+       0x00, /* E7 */
+       0x00, /* E8 */
+       0x00, /* E9 */
+       0x00, /* EA */
+       0x00, /* EB */
+       0x00, /* EC */
+       0x00, /* ED */
+       0x00, /* EE */
+       0x00, /* EF */
+
+       0x00, /* F0 */
+       0x00, /* F1 */
+       0x00, /* F2 */
+       0x00, /* F3 */
+       0x00, /* F4 */
+       0x00, /* F5 */
+       0x00, /* F6 */
+       0x00, /* F7 */
+       0x00, /* F8 */
+       0x00, /* F9 */
+       0x00, /* FA */
+       0x00, /* FB */
+       0x00, /* FC */
+       0x00, /* FD */
+       0x00, /* FE */
+       0x00, /* FF */
+};
+
+static struct {
+       int readable;
+       int writable;
+       int vol;
+} max98088_access[M98088_REG_CNT] = {
+       { 0xFF, 0xFF, 1 }, /* 00 IRQ status */
+       { 0xFF, 0x00, 1 }, /* 01 MIC status */
+       { 0xFF, 0x00, 1 }, /* 02 jack status */
+       { 0x1F, 0x1F, 1 }, /* 03 battery voltage */
+       { 0xFF, 0xFF, 0 }, /* 04 */
+       { 0xFF, 0xFF, 0 }, /* 05 */
+       { 0xFF, 0xFF, 0 }, /* 06 */
+       { 0xFF, 0xFF, 0 }, /* 07 */
+       { 0xFF, 0xFF, 0 }, /* 08 */
+       { 0xFF, 0xFF, 0 }, /* 09 */
+       { 0xFF, 0xFF, 0 }, /* 0A */
+       { 0xFF, 0xFF, 0 }, /* 0B */
+       { 0xFF, 0xFF, 0 }, /* 0C */
+       { 0xFF, 0xFF, 0 }, /* 0D */
+       { 0xFF, 0xFF, 0 }, /* 0E */
+       { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */
+
+       { 0xFF, 0xFF, 0 }, /* 10 master clock */
+       { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */
+       { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */
+       { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */
+       { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */
+       { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */
+       { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */
+       { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */
+       { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */
+       { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */
+       { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */
+       { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */
+       { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */
+       { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */
+       { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */
+       { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */
+
+       { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */
+       { 0xFF, 0xFF, 0 }, /* 21 data config */
+       { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */
+       { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */
+       { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */
+       { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */
+       { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */
+       { 0xFF, 0xFF, 0 }, /* 27 HP control */
+       { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */
+       { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */
+       { 0xFF, 0xFF, 0 }, /* 2A REC control */
+       { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */
+       { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */
+       { 0xFF, 0xFF, 0 }, /* 2D SPK control */
+       { 0xFF, 0xFF, 0 }, /* 2E sidetone */
+       { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */
+
+       { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */
+       { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */
+       { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */
+       { 0xFF, 0xFF, 0 }, /* 33 left ADC level */
+       { 0xFF, 0xFF, 0 }, /* 34 right ADC level */
+       { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */
+       { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */
+       { 0xFF, 0xFF, 0 }, /* 37 INA level */
+       { 0xFF, 0xFF, 0 }, /* 38 INB level */
+       { 0xFF, 0xFF, 0 }, /* 39 left HP volume */
+       { 0xFF, 0xFF, 0 }, /* 3A right HP volume */
+       { 0xFF, 0xFF, 0 }, /* 3B left REC volume */
+       { 0xFF, 0xFF, 0 }, /* 3C right REC volume */
+       { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */
+       { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */
+       { 0xFF, 0xFF, 0 }, /* 3F MIC config */
+
+       { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */
+       { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */
+       { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */
+       { 0xFF, 0xFF, 0 }, /* 43 ALC */
+       { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */
+       { 0xFF, 0xFF, 0 }, /* 45 power limiter config */
+       { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */
+       { 0xFF, 0xFF, 0 }, /* 47 audio input */
+       { 0xFF, 0xFF, 0 }, /* 48 microphone */
+       { 0xFF, 0xFF, 0 }, /* 49 level control */
+       { 0xFF, 0xFF, 0 }, /* 4A bypass switches */
+       { 0xFF, 0xFF, 0 }, /* 4B jack detect */
+       { 0xFF, 0xFF, 0 }, /* 4C input enable */
+       { 0xFF, 0xFF, 0 }, /* 4D output enable */
+       { 0xFF, 0xFF, 0 }, /* 4E bias control */
+       { 0xFF, 0xFF, 0 }, /* 4F DAC power */
+
+       { 0xFF, 0xFF, 0 }, /* 50 DAC power */
+       { 0xFF, 0xFF, 0 }, /* 51 system */
+       { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */
+
+       { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */
+
+       { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */
+
+       { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */
+       { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */
+
+       { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */
+       { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */
+
+       { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */
+       { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */
+       { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */
+
+       { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */
+       { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */
+       { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */
+
+       { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */
+       { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */
+       { 0x00, 0x00, 0 }, /* CA */
+       { 0x00, 0x00, 0 }, /* CB */
+       { 0x00, 0x00, 0 }, /* CC */
+       { 0x00, 0x00, 0 }, /* CD */
+       { 0x00, 0x00, 0 }, /* CE */
+       { 0x00, 0x00, 0 }, /* CF */
+
+       { 0x00, 0x00, 0 }, /* D0 */
+       { 0x00, 0x00, 0 }, /* D1 */
+       { 0x00, 0x00, 0 }, /* D2 */
+       { 0x00, 0x00, 0 }, /* D3 */
+       { 0x00, 0x00, 0 }, /* D4 */
+       { 0x00, 0x00, 0 }, /* D5 */
+       { 0x00, 0x00, 0 }, /* D6 */
+       { 0x00, 0x00, 0 }, /* D7 */
+       { 0x00, 0x00, 0 }, /* D8 */
+       { 0x00, 0x00, 0 }, /* D9 */
+       { 0x00, 0x00, 0 }, /* DA */
+       { 0x00, 0x00, 0 }, /* DB */
+       { 0x00, 0x00, 0 }, /* DC */
+       { 0x00, 0x00, 0 }, /* DD */
+       { 0x00, 0x00, 0 }, /* DE */
+       { 0x00, 0x00, 0 }, /* DF */
+
+       { 0x00, 0x00, 0 }, /* E0 */
+       { 0x00, 0x00, 0 }, /* E1 */
+       { 0x00, 0x00, 0 }, /* E2 */
+       { 0x00, 0x00, 0 }, /* E3 */
+       { 0x00, 0x00, 0 }, /* E4 */
+       { 0x00, 0x00, 0 }, /* E5 */
+       { 0x00, 0x00, 0 }, /* E6 */
+       { 0x00, 0x00, 0 }, /* E7 */
+       { 0x00, 0x00, 0 }, /* E8 */
+       { 0x00, 0x00, 0 }, /* E9 */
+       { 0x00, 0x00, 0 }, /* EA */
+       { 0x00, 0x00, 0 }, /* EB */
+       { 0x00, 0x00, 0 }, /* EC */
+       { 0x00, 0x00, 0 }, /* ED */
+       { 0x00, 0x00, 0 }, /* EE */
+       { 0x00, 0x00, 0 }, /* EF */
+
+       { 0x00, 0x00, 0 }, /* F0 */
+       { 0x00, 0x00, 0 }, /* F1 */
+       { 0x00, 0x00, 0 }, /* F2 */
+       { 0x00, 0x00, 0 }, /* F3 */
+       { 0x00, 0x00, 0 }, /* F4 */
+       { 0x00, 0x00, 0 }, /* F5 */
+       { 0x00, 0x00, 0 }, /* F6 */
+       { 0x00, 0x00, 0 }, /* F7 */
+       { 0x00, 0x00, 0 }, /* F8 */
+       { 0x00, 0x00, 0 }, /* F9 */
+       { 0x00, 0x00, 0 }, /* FA */
+       { 0x00, 0x00, 0 }, /* FB */
+       { 0x00, 0x00, 0 }, /* FC */
+       { 0x00, 0x00, 0 }, /* FD */
+       { 0x00, 0x00, 0 }, /* FE */
+       { 0xFF, 0x00, 1 }, /* FF */
+};
+
+static int max98088_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
+{
+       return max98088_access[reg].vol;
+}
+
+
+/*
+ * Load equalizer DSP coefficient configurations registers
+ */
+static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai,
+                   unsigned int band, u16 *coefs)
+{
+       unsigned int eq_reg;
+       unsigned int i;
+
+       BUG_ON(band > 4);
+       BUG_ON(dai > 1);
+
+       /* Load the base register address */
+       eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
+
+       /* Add the band address offset, note adjustment for word address */
+       eq_reg += band * (M98088_COEFS_PER_BAND << 1);
+
+       /* Step through the registers and coefs */
+       for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
+               snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i]));
+               snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i]));
+       }
+}
+
+/*
+ * Excursion limiter modes
+ */
+static const char *max98088_exmode_texts[] = {
+       "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
+       "400-600Hz", "400-800Hz",
+};
+
+static const unsigned int max98088_exmode_values[] = {
+       0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
+};
+
+static const struct soc_enum max98088_exmode_enum =
+       SOC_VALUE_ENUM_SINGLE(M98088_REG_41_SPKDHP, 0, 127,
+                             ARRAY_SIZE(max98088_exmode_texts),
+                             max98088_exmode_texts,
+                             max98088_exmode_values);
+
+static const char *max98088_ex_thresh[] = { /* volts PP */
+       "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
+static const struct soc_enum max98088_ex_thresh_enum[] = {
+       SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8,
+               max98088_ex_thresh),
+};
+
+static const char *max98088_fltr_mode[] = {"Voice", "Music" };
+static const struct soc_enum max98088_filter_mode_enum[] = {
+       SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode),
+};
+
+static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
+
+static const struct soc_enum max98088_extmic_enum =
+       SOC_ENUM_SINGLE(M98088_REG_48_CFG_MIC, 0, 3, max98088_extmic_text);
+
+static const struct snd_kcontrol_new max98088_extmic_mux =
+       SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
+
+static const char *max98088_dai1_fltr[] = {
+       "Off", "fc=258/fs=16k", "fc=500/fs=16k",
+       "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
+static const struct soc_enum max98088_dai1_dac_filter_enum[] = {
+       SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr),
+};
+static const struct soc_enum max98088_dai1_adc_filter_enum[] = {
+       SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr),
+};
+
+static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
+                               struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       unsigned int sel = ucontrol->value.integer.value[0];
+
+       max98088->mic1pre = sel;
+       snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
+               (1+sel)<<M98088_MICPRE_SHIFT);
+
+       return 0;
+}
+
+static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
+                               struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+
+       ucontrol->value.integer.value[0] = max98088->mic1pre;
+       return 0;
+}
+
+static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
+                               struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       unsigned int sel = ucontrol->value.integer.value[0];
+
+       max98088->mic2pre = sel;
+       snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
+               (1+sel)<<M98088_MICPRE_SHIFT);
+
+       return 0;
+}
+
+static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
+                               struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+
+       ucontrol->value.integer.value[0] = max98088->mic2pre;
+       return 0;
+}
+
+static const unsigned int max98088_micboost_tlv[] = {
+       TLV_DB_RANGE_HEAD(2),
+       0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
+       2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
+};
+
+static const struct snd_kcontrol_new max98088_snd_controls[] = {
+
+       SOC_DOUBLE_R("Headphone Volume", M98088_REG_39_LVL_HP_L,
+               M98088_REG_3A_LVL_HP_R, 0, 31, 0),
+       SOC_DOUBLE_R("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
+               M98088_REG_3E_LVL_SPK_R, 0, 31, 0),
+       SOC_DOUBLE_R("Receiver Volume", M98088_REG_3B_LVL_REC_L,
+               M98088_REG_3C_LVL_REC_R, 0, 31, 0),
+
+       SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
+               M98088_REG_3A_LVL_HP_R, 7, 1, 1),
+       SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
+               M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
+       SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
+               M98088_REG_3C_LVL_REC_R, 7, 1, 1),
+
+       SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
+       SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
+
+       SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
+                       M98088_REG_35_LVL_MIC1, 5, 2, 0,
+                       max98088_mic1pre_get, max98088_mic1pre_set,
+                       max98088_micboost_tlv),
+       SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
+                       M98088_REG_36_LVL_MIC2, 5, 2, 0,
+                       max98088_mic2pre_get, max98088_mic2pre_set,
+                       max98088_micboost_tlv),
+
+       SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
+       SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
+
+       SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
+       SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
+
+       SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
+       SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
+
+       SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
+       SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
+
+       SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
+       SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
+
+       SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
+       SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
+       SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
+       SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
+               0, 1, 0),
+
+       SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
+       SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
+       SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
+       SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
+
+       SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
+               4, 15, 0),
+       SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
+       SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
+       SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
+
+       SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
+       SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
+};
+
+/* Left speaker mixer switch */
+static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
+       SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
+       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
+       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
+       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
+       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
+       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
+       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
+};
+
+/* Right speaker mixer switch */
+static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
+       SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
+       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
+       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
+       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
+       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
+       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
+       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
+};
+
+/* Left headphone mixer switch */
+static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
+       SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
+       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
+       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
+       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
+       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
+       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
+       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
+};
+
+/* Right headphone mixer switch */
+static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
+       SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
+       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
+       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
+       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
+       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
+       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
+       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
+};
+
+/* Left earpiece/receiver mixer switch */
+static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
+       SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
+       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
+       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
+       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
+       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
+       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
+       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
+};
+
+/* Right earpiece/receiver mixer switch */
+static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
+       SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
+       SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
+       SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
+       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
+       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
+       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
+       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
+       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
+       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
+};
+
+/* Left ADC mixer switch */
+static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
+       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
+       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
+       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
+       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
+       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
+       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
+};
+
+/* Right ADC mixer switch */
+static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
+       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
+       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
+       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
+       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
+       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
+       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
+};
+
+static int max98088_mic_event(struct snd_soc_dapm_widget *w,
+                            struct snd_kcontrol *kcontrol, int event)
+{
+       struct snd_soc_codec *codec = w->codec;
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+
+       switch (event) {
+       case SND_SOC_DAPM_POST_PMU:
+               if (w->reg == M98088_REG_35_LVL_MIC1) {
+                       snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
+                               (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
+               } else {
+                       snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
+                               (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
+               }
+               break;
+       case SND_SOC_DAPM_POST_PMD:
+               snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+/*
+ * The line inputs are 2-channel stereo inputs with the left
+ * and right channels sharing a common PGA power control signal.
+ */
+static int max98088_line_pga(struct snd_soc_dapm_widget *w,
+                            int event, int line, u8 channel)
+{
+       struct snd_soc_codec *codec = w->codec;
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       u8 *state;
+
+       BUG_ON(!((channel == 1) || (channel == 2)));
+
+       switch (line) {
+       case LINE_INA:
+               state = &max98088->ina_state;
+               break;
+       case LINE_INB:
+               state = &max98088->inb_state;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       switch (event) {
+       case SND_SOC_DAPM_POST_PMU:
+               *state |= channel;
+               snd_soc_update_bits(codec, w->reg,
+                       (1 << w->shift), (1 << w->shift));
+               break;
+       case SND_SOC_DAPM_POST_PMD:
+               *state &= ~channel;
+               if (*state == 0) {
+                       snd_soc_update_bits(codec, w->reg,
+                               (1 << w->shift), 0);
+               }
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
+                                  struct snd_kcontrol *k, int event)
+{
+       return max98088_line_pga(w, event, LINE_INA, 1);
+}
+
+static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
+                                  struct snd_kcontrol *k, int event)
+{
+       return max98088_line_pga(w, event, LINE_INA, 2);
+}
+
+static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
+                                  struct snd_kcontrol *k, int event)
+{
+       return max98088_line_pga(w, event, LINE_INB, 1);
+}
+
+static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
+                                  struct snd_kcontrol *k, int event)
+{
+       return max98088_line_pga(w, event, LINE_INB, 2);
+}
+
+static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
+
+       SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
+       SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
+
+       SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
+               M98088_REG_4D_PWR_EN_OUT, 1, 0),
+       SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
+               M98088_REG_4D_PWR_EN_OUT, 0, 0),
+       SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
+               M98088_REG_4D_PWR_EN_OUT, 1, 0),
+       SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
+               M98088_REG_4D_PWR_EN_OUT, 0, 0),
+
+       SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
+               7, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
+               6, 0, NULL, 0),
+
+       SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
+               5, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
+               4, 0, NULL, 0),
+
+       SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
+               3, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
+               2, 0, NULL, 0),
+
+       SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
+               &max98088_extmic_mux),
+
+       SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
+               &max98088_left_hp_mixer_controls[0],
+               ARRAY_SIZE(max98088_left_hp_mixer_controls)),
+
+       SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
+               &max98088_right_hp_mixer_controls[0],
+               ARRAY_SIZE(max98088_right_hp_mixer_controls)),
+
+       SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
+               &max98088_left_speaker_mixer_controls[0],
+               ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
+
+       SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
+               &max98088_right_speaker_mixer_controls[0],
+               ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
+
+       SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
+         &max98088_left_rec_mixer_controls[0],
+               ARRAY_SIZE(max98088_left_rec_mixer_controls)),
+
+       SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
+         &max98088_right_rec_mixer_controls[0],
+               ARRAY_SIZE(max98088_right_rec_mixer_controls)),
+
+       SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
+               &max98088_left_ADC_mixer_controls[0],
+               ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
+
+       SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
+               &max98088_right_ADC_mixer_controls[0],
+               ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
+
+       SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
+               5, 0, NULL, 0, max98088_mic_event,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+       SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
+               5, 0, NULL, 0, max98088_mic_event,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+       SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
+               7, 0, NULL, 0, max98088_pga_ina1_event,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+       SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
+               7, 0, NULL, 0, max98088_pga_ina2_event,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+       SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
+               6, 0, NULL, 0, max98088_pga_inb1_event,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+       SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
+               6, 0, NULL, 0, max98088_pga_inb2_event,
+               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+       SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
+
+       SND_SOC_DAPM_OUTPUT("HPL"),
+       SND_SOC_DAPM_OUTPUT("HPR"),
+       SND_SOC_DAPM_OUTPUT("SPKL"),
+       SND_SOC_DAPM_OUTPUT("SPKR"),
+       SND_SOC_DAPM_OUTPUT("RECL"),
+       SND_SOC_DAPM_OUTPUT("RECR"),
+
+       SND_SOC_DAPM_INPUT("MIC1"),
+       SND_SOC_DAPM_INPUT("MIC2"),
+       SND_SOC_DAPM_INPUT("INA1"),
+       SND_SOC_DAPM_INPUT("INA2"),
+       SND_SOC_DAPM_INPUT("INB1"),
+       SND_SOC_DAPM_INPUT("INB2"),
+};
+
+static const struct snd_soc_dapm_route max98088_audio_map[] = {
+       /* Left headphone output mixer */
+       {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
+       {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
+       {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
+       {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
+       {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
+       {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
+       {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
+       {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
+       {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
+       {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
+
+       /* Right headphone output mixer */
+       {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
+       {"Right HP Mixer", "Left DAC2 Switch", "DACL2"  },
+       {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
+       {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
+       {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
+       {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
+       {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
+       {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
+       {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
+       {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
+
+       /* Left speaker output mixer */
+       {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
+       {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
+       {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
+       {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
+       {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
+       {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
+       {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
+       {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
+       {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
+       {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
+
+       /* Right speaker output mixer */
+       {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
+       {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
+       {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
+       {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
+       {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
+       {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
+       {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
+       {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
+       {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
+       {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
+
+       /* Earpiece/Receiver output mixer */
+       {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
+       {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
+       {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
+       {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
+       {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
+       {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
+       {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
+       {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
+       {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
+       {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
+
+       /* Earpiece/Receiver output mixer */
+       {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
+       {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
+       {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
+       {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
+       {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
+       {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
+       {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
+       {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
+       {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
+       {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
+
+       {"HP Left Out", NULL, "Left HP Mixer"},
+       {"HP Right Out", NULL, "Right HP Mixer"},
+       {"SPK Left Out", NULL, "Left SPK Mixer"},
+       {"SPK Right Out", NULL, "Right SPK Mixer"},
+       {"REC Left Out", NULL, "Left REC Mixer"},
+       {"REC Right Out", NULL, "Right REC Mixer"},
+
+       {"HPL", NULL, "HP Left Out"},
+       {"HPR", NULL, "HP Right Out"},
+       {"SPKL", NULL, "SPK Left Out"},
+       {"SPKR", NULL, "SPK Right Out"},
+       {"RECL", NULL, "REC Left Out"},
+       {"RECR", NULL, "REC Right Out"},
+
+       /* Left ADC input mixer */
+       {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
+       {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
+       {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
+       {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
+       {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
+       {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
+
+       /* Right ADC input mixer */
+       {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
+       {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
+       {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
+       {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
+       {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
+       {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
+
+       /* Inputs */
+       {"ADCL", NULL, "Left ADC Mixer"},
+       {"ADCR", NULL, "Right ADC Mixer"},
+       {"INA1 Input", NULL, "INA1"},
+       {"INA2 Input", NULL, "INA2"},
+       {"INB1 Input", NULL, "INB1"},
+       {"INB2 Input", NULL, "INB2"},
+       {"MIC1 Input", NULL, "MIC1"},
+       {"MIC2 Input", NULL, "MIC2"},
+};
+
+/* codec mclk clock divider coefficients */
+static const struct {
+       u32 rate;
+       u8  sr;
+} rate_table[] = {
+       {8000,  0x10},
+       {11025, 0x20},
+       {16000, 0x30},
+       {22050, 0x40},
+       {24000, 0x50},
+       {32000, 0x60},
+       {44100, 0x70},
+       {48000, 0x80},
+       {88200, 0x90},
+       {96000, 0xA0},
+};
+
+static inline int rate_value(int rate, u8 *value)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
+               if (rate_table[i].rate >= rate) {
+                       *value = rate_table[i].sr;
+                       return 0;
+               }
+       }
+       *value = rate_table[0].sr;
+       return -EINVAL;
+}
+
+static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
+                                  struct snd_pcm_hw_params *params,
+                                  struct snd_soc_dai *dai)
+{
+       struct snd_soc_codec *codec = dai->codec;
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_cdata *cdata;
+       unsigned long long ni;
+       unsigned int rate;
+       u8 regval;
+
+       cdata = &max98088->dai[0];
+
+       rate = params_rate(params);
+
+       switch (params_format(params)) {
+       case SNDRV_PCM_FORMAT_S16_LE:
+               snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
+                       M98088_DAI_WS, 0);
+               break;
+       case SNDRV_PCM_FORMAT_S24_LE:
+               snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
+                       M98088_DAI_WS, M98088_DAI_WS);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
+
+       if (rate_value(rate, &regval))
+               return -EINVAL;
+
+       snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE,
+               M98088_CLKMODE_MASK, regval);
+       cdata->rate = rate;
+
+       /* Configure NI when operating as master */
+       if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT)
+               & M98088_DAI_MAS) {
+               if (max98088->sysclk == 0) {
+                       dev_err(codec->dev, "Invalid system clock frequency\n");
+                       return -EINVAL;
+               }
+               ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
+                               * (unsigned long long int)rate;
+               do_div(ni, (unsigned long long int)max98088->sysclk);
+               snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
+                       (ni >> 8) & 0x7F);
+               snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
+                       ni & 0xFF);
+       }
+
+       /* Update sample rate mode */
+       if (rate < 50000)
+               snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
+                       M98088_DAI_DHF, 0);
+       else
+               snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
+                       M98088_DAI_DHF, M98088_DAI_DHF);
+
+       snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
+               M98088_SHDNRUN);
+
+       return 0;
+}
+
+static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
+                                  struct snd_pcm_hw_params *params,
+                                  struct snd_soc_dai *dai)
+{
+       struct snd_soc_codec *codec = dai->codec;
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_cdata *cdata;
+       unsigned long long ni;
+       unsigned int rate;
+       u8 regval;
+
+       cdata = &max98088->dai[1];
+
+       rate = params_rate(params);
+
+       switch (params_format(params)) {
+       case SNDRV_PCM_FORMAT_S16_LE:
+               snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
+                       M98088_DAI_WS, 0);
+               break;
+       case SNDRV_PCM_FORMAT_S24_LE:
+               snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
+                       M98088_DAI_WS, M98088_DAI_WS);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
+
+       if (rate_value(rate, &regval))
+               return -EINVAL;
+
+       snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE,
+               M98088_CLKMODE_MASK, regval);
+       cdata->rate = rate;
+
+       /* Configure NI when operating as master */
+       if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT)
+               & M98088_DAI_MAS) {
+               if (max98088->sysclk == 0) {
+                       dev_err(codec->dev, "Invalid system clock frequency\n");
+                       return -EINVAL;
+               }
+               ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
+                               * (unsigned long long int)rate;
+               do_div(ni, (unsigned long long int)max98088->sysclk);
+               snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
+                       (ni >> 8) & 0x7F);
+               snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
+                       ni & 0xFF);
+       }
+
+       /* Update sample rate mode */
+       if (rate < 50000)
+               snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
+                       M98088_DAI_DHF, 0);
+       else
+               snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
+                       M98088_DAI_DHF, M98088_DAI_DHF);
+
+       snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
+               M98088_SHDNRUN);
+
+       return 0;
+}
+
+static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
+                                  int clk_id, unsigned int freq, int dir)
+{
+       struct snd_soc_codec *codec = dai->codec;
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+
+       /* Requested clock frequency is already setup */
+       if (freq == max98088->sysclk)
+               return 0;
+
+       max98088->sysclk = freq; /* remember current sysclk */
+
+       /* Setup clocks for slave mode, and using the PLL
+        * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
+        *         0x02 (when master clk is 20MHz to 30MHz)..
+        */
+       if ((freq >= 10000000) && (freq < 20000000)) {
+               snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10);
+       } else if ((freq >= 20000000) && (freq < 30000000)) {
+               snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20);
+       } else {
+               dev_err(codec->dev, "Invalid master clock frequency\n");
+               return -EINVAL;
+       }
+
+       if (snd_soc_read(codec, M98088_REG_51_PWR_SYS)  & M98088_SHDNRUN) {
+               snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
+                       M98088_SHDNRUN, 0);
+               snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
+                       M98088_SHDNRUN, M98088_SHDNRUN);
+       }
+
+       dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
+
+       max98088->sysclk = freq;
+       return 0;
+}
+
+static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
+                                unsigned int fmt)
+{
+       struct snd_soc_codec *codec = codec_dai->codec;
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_cdata *cdata;
+       u8 reg15val;
+       u8 reg14val = 0;
+
+       cdata = &max98088->dai[0];
+
+       if (fmt != cdata->fmt) {
+               cdata->fmt = fmt;
+
+               switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+               case SND_SOC_DAIFMT_CBS_CFS:
+                       /* Slave mode PLL */
+                       snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
+                               0x80);
+                       snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
+                               0x00);
+                       break;
+               case SND_SOC_DAIFMT_CBM_CFM:
+                       /* Set to master mode */
+                       reg14val |= M98088_DAI_MAS;
+                       break;
+               case SND_SOC_DAIFMT_CBS_CFM:
+               case SND_SOC_DAIFMT_CBM_CFS:
+               default:
+                       dev_err(codec->dev, "Clock mode unsupported");
+                       return -EINVAL;
+               }
+
+               switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+               case SND_SOC_DAIFMT_I2S:
+                       reg14val |= M98088_DAI_DLY;
+                       break;
+               case SND_SOC_DAIFMT_LEFT_J:
+                       break;
+               default:
+                       return -EINVAL;
+               }
+
+               switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+               case SND_SOC_DAIFMT_NB_NF:
+                       break;
+               case SND_SOC_DAIFMT_NB_IF:
+                       reg14val |= M98088_DAI_WCI;
+                       break;
+               case SND_SOC_DAIFMT_IB_NF:
+                       reg14val |= M98088_DAI_BCI;
+                       break;
+               case SND_SOC_DAIFMT_IB_IF:
+                       reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
+                       break;
+               default:
+                       return -EINVAL;
+               }
+
+               snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
+                       M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
+                       M98088_DAI_WCI, reg14val);
+
+               reg15val = M98088_DAI_BSEL64;
+               if (max98088->digmic)
+                       reg15val |= M98088_DAI_OSR64;
+               snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val);
+       }
+
+       return 0;
+}
+
+static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
+                                unsigned int fmt)
+{
+       struct snd_soc_codec *codec = codec_dai->codec;
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_cdata *cdata;
+       u8 reg1Cval = 0;
+
+       cdata = &max98088->dai[1];
+
+       if (fmt != cdata->fmt) {
+               cdata->fmt = fmt;
+
+               switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+               case SND_SOC_DAIFMT_CBS_CFS:
+                       /* Slave mode PLL */
+                       snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
+                               0x80);
+                       snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
+                               0x00);
+                       break;
+               case SND_SOC_DAIFMT_CBM_CFM:
+                       /* Set to master mode */
+                       reg1Cval |= M98088_DAI_MAS;
+                       break;
+               case SND_SOC_DAIFMT_CBS_CFM:
+               case SND_SOC_DAIFMT_CBM_CFS:
+               default:
+                       dev_err(codec->dev, "Clock mode unsupported");
+                       return -EINVAL;
+               }
+
+               switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+               case SND_SOC_DAIFMT_I2S:
+                       reg1Cval |= M98088_DAI_DLY;
+                       break;
+               case SND_SOC_DAIFMT_LEFT_J:
+                       break;
+               default:
+                       return -EINVAL;
+               }
+
+               switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+               case SND_SOC_DAIFMT_NB_NF:
+                       break;
+               case SND_SOC_DAIFMT_NB_IF:
+                       reg1Cval |= M98088_DAI_WCI;
+                       break;
+               case SND_SOC_DAIFMT_IB_NF:
+                       reg1Cval |= M98088_DAI_BCI;
+                       break;
+               case SND_SOC_DAIFMT_IB_IF:
+                       reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
+                       break;
+               default:
+                       return -EINVAL;
+               }
+
+               snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
+                       M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
+                       M98088_DAI_WCI, reg1Cval);
+
+               snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK,
+                       M98088_DAI_BSEL64);
+       }
+
+       return 0;
+}
+
+static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute)
+{
+       struct snd_soc_codec *codec = codec_dai->codec;
+       int reg;
+
+       if (mute)
+               reg = M98088_DAI_MUTE;
+       else
+               reg = 0;
+
+       snd_soc_update_bits(codec, M98088_REG_2F_LVL_DAI1_PLAY,
+                           M98088_DAI_MUTE_MASK, reg);
+       return 0;
+}
+
+static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
+{
+       struct snd_soc_codec *codec = codec_dai->codec;
+       int reg;
+
+       if (mute)
+               reg = M98088_DAI_MUTE;
+       else
+               reg = 0;
+
+       snd_soc_update_bits(codec, M98088_REG_31_LVL_DAI2_PLAY,
+                           M98088_DAI_MUTE_MASK, reg);
+       return 0;
+}
+
+static void max98088_sync_cache(struct snd_soc_codec *codec)
+{
+       u16 *reg_cache = codec->reg_cache;
+       int i;
+
+       if (!codec->cache_sync)
+               return;
+
+       codec->cache_only = 0;
+
+       /* write back cached values if they're writeable and
+        * different from the hardware default.
+        */
+       for (i = 1; i < codec->driver->reg_cache_size; i++) {
+               if (!max98088_access[i].writable)
+                       continue;
+
+               if (reg_cache[i] == max98088_reg[i])
+                       continue;
+
+               snd_soc_write(codec, i, reg_cache[i]);
+       }
+
+       codec->cache_sync = 0;
+}
+
+static int max98088_set_bias_level(struct snd_soc_codec *codec,
+                                  enum snd_soc_bias_level level)
+{
+       switch (level) {
+       case SND_SOC_BIAS_ON:
+               break;
+
+       case SND_SOC_BIAS_PREPARE:
+               break;
+
+       case SND_SOC_BIAS_STANDBY:
+               if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
+                       max98088_sync_cache(codec);
+
+               snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
+                               M98088_MBEN, M98088_MBEN);
+               break;
+
+       case SND_SOC_BIAS_OFF:
+               snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
+                               M98088_MBEN, 0);
+               codec->cache_sync = 1;
+               break;
+       }
+       codec->dapm.bias_level = level;
+       return 0;
+}
+
+#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
+#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
+
+static struct snd_soc_dai_ops max98088_dai1_ops = {
+       .set_sysclk = max98088_dai_set_sysclk,
+       .set_fmt = max98088_dai1_set_fmt,
+       .hw_params = max98088_dai1_hw_params,
+       .digital_mute = max98088_dai1_digital_mute,
+};
+
+static struct snd_soc_dai_ops max98088_dai2_ops = {
+       .set_sysclk = max98088_dai_set_sysclk,
+       .set_fmt = max98088_dai2_set_fmt,
+       .hw_params = max98088_dai2_hw_params,
+       .digital_mute = max98088_dai2_digital_mute,
+};
+
+static struct snd_soc_dai_driver max98088_dai[] = {
+{
+       .name = "HiFi",
+       .playback = {
+               .stream_name = "HiFi Playback",
+               .channels_min = 1,
+               .channels_max = 2,
+               .rates = MAX98088_RATES,
+               .formats = MAX98088_FORMATS,
+       },
+       .capture = {
+               .stream_name = "HiFi Capture",
+               .channels_min = 1,
+               .channels_max = 2,
+               .rates = MAX98088_RATES,
+               .formats = MAX98088_FORMATS,
+       },
+        .ops = &max98088_dai1_ops,
+},
+{
+       .name = "Aux",
+       .playback = {
+               .stream_name = "Aux Playback",
+               .channels_min = 1,
+               .channels_max = 2,
+               .rates = MAX98088_RATES,
+               .formats = MAX98088_FORMATS,
+       },
+       .ops = &max98088_dai2_ops,
+}
+};
+
+static int max98088_get_channel(const char *name)
+{
+       if (strcmp(name, "EQ1 Mode") == 0)
+               return 0;
+       if (strcmp(name, "EQ2 Mode") == 0)
+               return 1;
+       return -EINVAL;
+}
+
+static void max98088_setup_eq1(struct snd_soc_codec *codec)
+{
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_pdata *pdata = max98088->pdata;
+       struct max98088_eq_cfg *coef_set;
+       int best, best_val, save, i, sel, fs;
+       struct max98088_cdata *cdata;
+
+       cdata = &max98088->dai[0];
+
+       if (!pdata || !max98088->eq_textcnt)
+               return;
+
+       /* Find the selected configuration with nearest sample rate */
+       fs = cdata->rate;
+       sel = cdata->eq_sel;
+
+       best = 0;
+       best_val = INT_MAX;
+       for (i = 0; i < pdata->eq_cfgcnt; i++) {
+               if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
+                   abs(pdata->eq_cfg[i].rate - fs) < best_val) {
+                       best = i;
+                       best_val = abs(pdata->eq_cfg[i].rate - fs);
+               }
+       }
+
+       dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
+               pdata->eq_cfg[best].name,
+               pdata->eq_cfg[best].rate, fs);
+
+       /* Disable EQ while configuring, and save current on/off state */
+       save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
+       snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
+
+       coef_set = &pdata->eq_cfg[sel];
+
+       m98088_eq_band(codec, 0, 0, coef_set->band1);
+       m98088_eq_band(codec, 0, 1, coef_set->band2);
+       m98088_eq_band(codec, 0, 2, coef_set->band3);
+       m98088_eq_band(codec, 0, 3, coef_set->band4);
+       m98088_eq_band(codec, 0, 4, coef_set->band5);
+
+       /* Restore the original on/off state */
+       snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
+}
+
+static void max98088_setup_eq2(struct snd_soc_codec *codec)
+{
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_pdata *pdata = max98088->pdata;
+       struct max98088_eq_cfg *coef_set;
+       int best, best_val, save, i, sel, fs;
+       struct max98088_cdata *cdata;
+
+       cdata = &max98088->dai[1];
+
+       if (!pdata || !max98088->eq_textcnt)
+               return;
+
+       /* Find the selected configuration with nearest sample rate */
+       fs = cdata->rate;
+
+       sel = cdata->eq_sel;
+       best = 0;
+       best_val = INT_MAX;
+       for (i = 0; i < pdata->eq_cfgcnt; i++) {
+               if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
+                   abs(pdata->eq_cfg[i].rate - fs) < best_val) {
+                       best = i;
+                       best_val = abs(pdata->eq_cfg[i].rate - fs);
+               }
+       }
+
+       dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
+               pdata->eq_cfg[best].name,
+               pdata->eq_cfg[best].rate, fs);
+
+       /* Disable EQ while configuring, and save current on/off state */
+       save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
+       snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
+
+       coef_set = &pdata->eq_cfg[sel];
+
+       m98088_eq_band(codec, 1, 0, coef_set->band1);
+       m98088_eq_band(codec, 1, 1, coef_set->band2);
+       m98088_eq_band(codec, 1, 2, coef_set->band3);
+       m98088_eq_band(codec, 1, 3, coef_set->band4);
+       m98088_eq_band(codec, 1, 4, coef_set->band5);
+
+       /* Restore the original on/off state */
+       snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
+               save);
+}
+
+static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_pdata *pdata = max98088->pdata;
+       int channel = max98088_get_channel(kcontrol->id.name);
+       struct max98088_cdata *cdata;
+       int sel = ucontrol->value.integer.value[0];
+
+       cdata = &max98088->dai[channel];
+
+       if (sel >= pdata->eq_cfgcnt)
+               return -EINVAL;
+
+       cdata->eq_sel = sel;
+
+       switch (channel) {
+       case 0:
+               max98088_setup_eq1(codec);
+               break;
+       case 1:
+               max98088_setup_eq2(codec);
+               break;
+       }
+
+       return 0;
+}
+
+static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       int channel = max98088_get_channel(kcontrol->id.name);
+       struct max98088_cdata *cdata;
+
+       cdata = &max98088->dai[channel];
+       ucontrol->value.enumerated.item[0] = cdata->eq_sel;
+       return 0;
+}
+
+static void max98088_handle_eq_pdata(struct snd_soc_codec *codec)
+{
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_pdata *pdata = max98088->pdata;
+       struct max98088_eq_cfg *cfg;
+       unsigned int cfgcnt;
+       int i, j;
+       const char **t;
+       int ret;
+
+       struct snd_kcontrol_new controls[] = {
+               SOC_ENUM_EXT("EQ1 Mode",
+                       max98088->eq_enum,
+                       max98088_get_eq_enum,
+                       max98088_put_eq_enum),
+               SOC_ENUM_EXT("EQ2 Mode",
+                       max98088->eq_enum,
+                       max98088_get_eq_enum,
+                       max98088_put_eq_enum),
+       };
+
+       cfg = pdata->eq_cfg;
+       cfgcnt = pdata->eq_cfgcnt;
+
+       /* Setup an array of texts for the equalizer enum.
+        * This is based on Mark Brown's equalizer driver code.
+        */
+       max98088->eq_textcnt = 0;
+       max98088->eq_texts = NULL;
+       for (i = 0; i < cfgcnt; i++) {
+               for (j = 0; j < max98088->eq_textcnt; j++) {
+                       if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
+                               break;
+               }
+
+               if (j != max98088->eq_textcnt)
+                       continue;
+
+               /* Expand the array */
+               t = krealloc(max98088->eq_texts,
+                            sizeof(char *) * (max98088->eq_textcnt + 1),
+                            GFP_KERNEL);
+               if (t == NULL)
+                       continue;
+
+               /* Store the new entry */
+               t[max98088->eq_textcnt] = cfg[i].name;
+               max98088->eq_textcnt++;
+               max98088->eq_texts = t;
+       }
+
+       /* Now point the soc_enum to .texts array items */
+       max98088->eq_enum.texts = max98088->eq_texts;
+       max98088->eq_enum.max = max98088->eq_textcnt;
+
+       ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
+       if (ret != 0)
+               dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
+}
+
+static void max98088_handle_pdata(struct snd_soc_codec *codec)
+{
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_pdata *pdata = max98088->pdata;
+       u8 regval = 0;
+
+       if (!pdata) {
+               dev_dbg(codec->dev, "No platform data\n");
+               return;
+       }
+
+       /* Configure mic for analog/digital mic mode */
+       if (pdata->digmic_left_mode)
+               regval |= M98088_DIGMIC_L;
+
+       if (pdata->digmic_right_mode)
+               regval |= M98088_DIGMIC_R;
+
+       max98088->digmic = (regval ? 1 : 0);
+
+       snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval);
+
+       /* Configure receiver output */
+       regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
+       snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL,
+               M98088_REC_LINEMODE_MASK, regval);
+
+       /* Configure equalizers */
+       if (pdata->eq_cfgcnt)
+               max98088_handle_eq_pdata(codec);
+}
+
+#ifdef CONFIG_PM
+static int max98088_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+       max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+       return 0;
+}
+
+static int max98088_resume(struct snd_soc_codec *codec)
+{
+       max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+       return 0;
+}
+#else
+#define max98088_suspend NULL
+#define max98088_resume NULL
+#endif
+
+static int max98088_probe(struct snd_soc_codec *codec)
+{
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+       struct max98088_cdata *cdata;
+       int ret = 0;
+
+       codec->cache_sync = 1;
+
+       ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
+       if (ret != 0) {
+               dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+               return ret;
+       }
+
+       /* initialize private data */
+
+       max98088->sysclk = (unsigned)-1;
+       max98088->eq_textcnt = 0;
+
+       cdata = &max98088->dai[0];
+       cdata->rate = (unsigned)-1;
+       cdata->fmt  = (unsigned)-1;
+       cdata->eq_sel = 0;
+
+       cdata = &max98088->dai[1];
+       cdata->rate = (unsigned)-1;
+       cdata->fmt  = (unsigned)-1;
+       cdata->eq_sel = 0;
+
+       max98088->ina_state = 0;
+       max98088->inb_state = 0;
+       max98088->ex_mode = 0;
+       max98088->digmic = 0;
+       max98088->mic1pre = 0;
+       max98088->mic2pre = 0;
+
+       ret = snd_soc_read(codec, M98088_REG_FF_REV_ID);
+       if (ret < 0) {
+               dev_err(codec->dev, "Failed to read device revision: %d\n",
+                       ret);
+               goto err_access;
+       }
+       dev_info(codec->dev, "revision %c\n", ret + 'A');
+
+       snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV);
+
+       /* initialize registers cache to hardware default */
+       max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+       snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00);
+
+       snd_soc_write(codec, M98088_REG_22_MIX_DAC,
+               M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
+               M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
+
+       snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0);
+       snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F);
+
+       snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG,
+               M98088_S1NORMAL|M98088_SDATA);
+
+       snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG,
+               M98088_S2NORMAL|M98088_SDATA);
+
+       max98088_handle_pdata(codec);
+
+       snd_soc_add_controls(codec, max98088_snd_controls,
+                            ARRAY_SIZE(max98088_snd_controls));
+
+err_access:
+       return ret;
+}
+
+static int max98088_remove(struct snd_soc_codec *codec)
+{
+       struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
+
+       max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
+       kfree(max98088->eq_texts);
+
+       return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
+       .probe   = max98088_probe,
+       .remove  = max98088_remove,
+       .suspend = max98088_suspend,
+       .resume  = max98088_resume,
+       .set_bias_level = max98088_set_bias_level,
+       .reg_cache_size = ARRAY_SIZE(max98088_reg),
+       .reg_word_size = sizeof(u8),
+       .reg_cache_default = max98088_reg,
+       .volatile_register = max98088_volatile_register,
+        .dapm_widgets = max98088_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
+        .dapm_routes = max98088_audio_map,
+        .num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
+};
+
+static int max98088_i2c_probe(struct i2c_client *i2c,
+                            const struct i2c_device_id *id)
+{
+       struct max98088_priv *max98088;
+       int ret;
+
+       max98088 = kzalloc(sizeof(struct max98088_priv), GFP_KERNEL);
+       if (max98088 == NULL)
+               return -ENOMEM;
+
+       max98088->devtype = id->driver_data;
+
+       i2c_set_clientdata(i2c, max98088);
+       max98088->control_data = i2c;
+       max98088->pdata = i2c->dev.platform_data;
+
+       ret = snd_soc_register_codec(&i2c->dev,
+                       &soc_codec_dev_max98088, &max98088_dai[0], 2);
+       if (ret < 0)
+               kfree(max98088);
+       return ret;
+}
+
+static int __devexit max98088_i2c_remove(struct i2c_client *client)
+{
+       snd_soc_unregister_codec(&client->dev);
+       kfree(i2c_get_clientdata(client));
+       return 0;
+}
+
+static const struct i2c_device_id max98088_i2c_id[] = {
+       { "max98088", MAX98088 },
+       { "max98089", MAX98089 },
+       { }
+};
+MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
+
+static struct i2c_driver max98088_i2c_driver = {
+       .driver = {
+               .name = "max98088",
+               .owner = THIS_MODULE,
+       },
+       .probe  = max98088_i2c_probe,
+       .remove = __devexit_p(max98088_i2c_remove),
+       .id_table = max98088_i2c_id,
+};
+
+static int __init max98088_init(void)
+{
+       int ret;
+
+       ret = i2c_add_driver(&max98088_i2c_driver);
+       if (ret)
+               pr_err("Failed to register max98088 I2C driver: %d\n", ret);
+
+       return ret;
+}
+module_init(max98088_init);
+
+static void __exit max98088_exit(void)
+{
+       i2c_del_driver(&max98088_i2c_driver);
+}
+module_exit(max98088_exit);
+
+MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
+MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max98088.h b/sound/soc/codecs/max98088.h
new file mode 100644
index 000000000000..be89a4f4aab8
--- /dev/null
+++ b/sound/soc/codecs/max98088.h
@@ -0,0 +1,206 @@
+/*
+ * max98088.h -- MAX98088 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Maxim Integrated Products
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _MAX98088_H
+#define _MAX98088_H
+
+/*
+ * MAX98088 Registers Definition
+ */
+#define M98088_REG_00_IRQ_STATUS            0x00
+#define M98088_REG_01_MIC_STATUS            0x01
+#define M98088_REG_02_JACK_STAUS            0x02
+#define M98088_REG_03_BATTERY_VOLTAGE       0x03
+#define M98088_REG_0F_IRQ_ENABLE            0x0F
+#define M98088_REG_10_SYS_CLK               0x10
+#define M98088_REG_11_DAI1_CLKMODE          0x11
+#define M98088_REG_12_DAI1_CLKCFG_HI        0x12
+#define M98088_REG_13_DAI1_CLKCFG_LO        0x13
+#define M98088_REG_14_DAI1_FORMAT           0x14
+#define M98088_REG_15_DAI1_CLOCK            0x15
+#define M98088_REG_16_DAI1_IOCFG            0x16
+#define M98088_REG_17_DAI1_TDM              0x17
+#define M98088_REG_18_DAI1_FILTERS          0x18
+#define M98088_REG_19_DAI2_CLKMODE          0x19
+#define M98088_REG_1A_DAI2_CLKCFG_HI        0x1A
+#define M98088_REG_1B_DAI2_CLKCFG_LO        0x1B
+#define M98088_REG_1C_DAI2_FORMAT           0x1C
+#define M98088_REG_1D_DAI2_CLOCK            0x1D
+#define M98088_REG_1E_DAI2_IOCFG            0x1E
+#define M98088_REG_1F_DAI2_TDM              0x1F
+#define M98088_REG_20_DAI2_FILTERS          0x20
+#define M98088_REG_21_SRC                   0x21
+#define M98088_REG_22_MIX_DAC               0x22
+#define M98088_REG_23_MIX_ADC_LEFT          0x23
+#define M98088_REG_24_MIX_ADC_RIGHT         0x24
+#define M98088_REG_25_MIX_HP_LEFT           0x25
+#define M98088_REG_26_MIX_HP_RIGHT          0x26
+#define M98088_REG_27_MIX_HP_CNTL           0x27
+#define M98088_REG_28_MIX_REC_LEFT          0x28
+#define M98088_REG_29_MIX_REC_RIGHT         0x29
+#define M98088_REG_2A_MIC_REC_CNTL          0x2A
+#define M98088_REG_2B_MIX_SPK_LEFT          0x2B
+#define M98088_REG_2C_MIX_SPK_RIGHT         0x2C
+#define M98088_REG_2D_MIX_SPK_CNTL          0x2D
+#define M98088_REG_2E_LVL_SIDETONE          0x2E
+#define M98088_REG_2F_LVL_DAI1_PLAY         0x2F
+#define M98088_REG_30_LVL_DAI1_PLAY_EQ      0x30
+#define M98088_REG_31_LVL_DAI2_PLAY         0x31
+#define M98088_REG_32_LVL_DAI2_PLAY_EQ      0x32
+#define M98088_REG_33_LVL_ADC_L             0x33
+#define M98088_REG_34_LVL_ADC_R             0x34
+#define M98088_REG_35_LVL_MIC1              0x35
+#define M98088_REG_36_LVL_MIC2              0x36
+#define M98088_REG_37_LVL_INA               0x37
+#define M98088_REG_38_LVL_INB               0x38
+#define M98088_REG_39_LVL_HP_L              0x39
+#define M98088_REG_3A_LVL_HP_R              0x3A
+#define M98088_REG_3B_LVL_REC_L             0x3B
+#define M98088_REG_3C_LVL_REC_R             0x3C
+#define M98088_REG_3D_LVL_SPK_L             0x3D
+#define M98088_REG_3E_LVL_SPK_R             0x3E
+#define M98088_REG_3F_MICAGC_CFG            0x3F
+#define M98088_REG_40_MICAGC_THRESH         0x40
+#define M98088_REG_41_SPKDHP                0x41
+#define M98088_REG_42_SPKDHP_THRESH         0x42
+#define M98088_REG_43_SPKALC_COMP           0x43
+#define M98088_REG_44_PWRLMT_CFG            0x44
+#define M98088_REG_45_PWRLMT_TIME           0x45
+#define M98088_REG_46_THDLMT_CFG            0x46
+#define M98088_REG_47_CFG_AUDIO_IN          0x47
+#define M98088_REG_48_CFG_MIC               0x48
+#define M98088_REG_49_CFG_LEVEL             0x49
+#define M98088_REG_4A_CFG_BYPASS            0x4A
+#define M98088_REG_4B_CFG_JACKDET           0x4B
+#define M98088_REG_4C_PWR_EN_IN             0x4C
+#define M98088_REG_4D_PWR_EN_OUT            0x4D
+#define M98088_REG_4E_BIAS_CNTL             0x4E
+#define M98088_REG_4F_DAC_BIAS1             0x4F
+#define M98088_REG_50_DAC_BIAS2             0x50
+#define M98088_REG_51_PWR_SYS               0x51
+#define M98088_REG_52_DAI1_EQ_BASE          0x52
+#define M98088_REG_84_DAI2_EQ_BASE          0x84
+#define M98088_REG_B6_DAI1_BIQUAD_BASE      0xB6
+#define M98088_REG_C0_DAI2_BIQUAD_BASE      0xC0
+#define M98088_REG_FF_REV_ID                0xFF
+
+#define M98088_REG_CNT                      (0xFF+1)
+
+/* MAX98088 Registers Bit Fields */
+
+/* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */
+       #define M98088_CLKMODE_MASK             0xFF
+
+/* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */
+       #define M98088_DAI_MAS                  (1<<7)
+       #define M98088_DAI_WCI                  (1<<6)
+       #define M98088_DAI_BCI                  (1<<5)
+       #define M98088_DAI_DLY                  (1<<4)
+       #define M98088_DAI_TDM                  (1<<2)
+       #define M98088_DAI_FSW                  (1<<1)
+       #define M98088_DAI_WS                   (1<<0)
+
+/* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */
+       #define M98088_DAI_BSEL64               (1<<0)
+       #define M98088_DAI_OSR64                (1<<6)
+
+/* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */
+       #define M98088_S1NORMAL                 (1<<6)
+       #define M98088_S2NORMAL                 (2<<6)
+       #define M98088_SDATA                    (3<<0)
+
+/* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */
+       #define M98088_DAI_DHF                  (1<<3)
+
+/* M98088_REG_22_MIX_DAC */
+       #define M98088_DAI1L_TO_DACL            (1<<7)
+       #define M98088_DAI1R_TO_DACL            (1<<6)
+       #define M98088_DAI2L_TO_DACL            (1<<5)
+       #define M98088_DAI2R_TO_DACL            (1<<4)
+       #define M98088_DAI1L_TO_DACR            (1<<3)
+       #define M98088_DAI1R_TO_DACR            (1<<2)
+       #define M98088_DAI2L_TO_DACR            (1<<1)
+       #define M98088_DAI2R_TO_DACR            (1<<0)
+
+/* M98088_REG_2A_MIC_REC_CNTL */
+       #define M98088_REC_LINEMODE             (1<<7)
+       #define M98088_REC_LINEMODE_MASK        (1<<7)
+
+/* M98088_REG_2D_MIX_SPK_CNTL */
+       #define M98088_MIX_SPKR_GAIN_MASK       (3<<2)
+       #define M98088_MIX_SPKR_GAIN_SHIFT      2
+       #define M98088_MIX_SPKL_GAIN_MASK       (3<<0)
+       #define M98088_MIX_SPKL_GAIN_SHIFT      0
+
+/* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */
+       #define M98088_DAI_MUTE                 (1<<7)
+       #define M98088_DAI_MUTE_MASK            (1<<7)
+       #define M98088_DAI_VOICE_GAIN_MASK      (3<<4)
+       #define M98088_DAI_ATTENUATION_MASK     (0xF<<0)
+       #define M98088_DAI_ATTENUATION_SHIFT    0
+
+/* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */
+       #define M98088_MICPRE_MASK              (3<<5)
+       #define M98088_MICPRE_SHIFT             5
+
+/* M98088_REG_3A_LVL_HP_R */
+       #define M98088_HP_MUTE                  (1<<7)
+
+/* M98088_REG_3C_LVL_REC_R */
+       #define M98088_REC_MUTE                 (1<<7)
+
+/* M98088_REG_3E_LVL_SPK_R */
+       #define M98088_SP_MUTE                  (1<<7)
+
+/* M98088_REG_48_CFG_MIC */
+       #define M98088_EXTMIC_MASK              (3<<0)
+       #define M98088_DIGMIC_L                 (1<<5)
+       #define M98088_DIGMIC_R                 (1<<4)
+
+/* M98088_REG_49_CFG_LEVEL */
+       #define M98088_VSEN                     (1<<6)
+       #define M98088_ZDEN                     (1<<5)
+       #define M98088_EQ2EN                    (1<<1)
+       #define M98088_EQ1EN                    (1<<0)
+
+/* M98088_REG_4C_PWR_EN_IN */
+       #define M98088_INAEN                    (1<<7)
+       #define M98088_INBEN                    (1<<6)
+       #define M98088_MBEN                     (1<<3)
+       #define M98088_ADLEN                    (1<<1)
+       #define M98088_ADREN                    (1<<0)
+
+/* M98088_REG_4D_PWR_EN_OUT */
+       #define M98088_HPLEN                    (1<<7)
+       #define M98088_HPREN                    (1<<6)
+       #define M98088_HPEN                     ((1<<7)|(1<<6))
+       #define M98088_SPLEN                    (1<<5)
+       #define M98088_SPREN                    (1<<4)
+       #define M98088_RECEN                    (1<<3)
+       #define M98088_DALEN                    (1<<1)
+       #define M98088_DAREN                    (1<<0)
+
+/* M98088_REG_51_PWR_SYS */
+       #define M98088_SHDNRUN                  (1<<7)
+       #define M98088_PERFMODE                 (1<<3)
+       #define M98088_HPPLYBACK                (1<<2)
+       #define M98088_PWRSV8K                  (1<<1)
+       #define M98088_PWRSV                    (1<<0)
+
+/* Line inputs */
+#define LINE_INA  0
+#define LINE_INB  1
+
+#define M98088_COEFS_PER_BAND               5
+
+#define M98088_BYTE1(w) ((w >> 8) & 0xff)
+#define M98088_BYTE0(w) (w & 0xff)
+
+#endif
diff --git a/sound/soc/codecs/max98095.c b/sound/soc/codecs/max98095.c
new file mode 100644
index 000000000000..e1d282d477da
--- /dev/null
+++ b/sound/soc/codecs/max98095.c
@@ -0,0 +1,2396 @@
+/*
+ * max98095.c -- MAX98095 ALSA SoC Audio driver
+ *
+ * Copyright 2011 Maxim Integrated Products
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <linux/slab.h>
+#include <asm/div64.h>
+#include <sound/max98095.h>
+#include "max98095.h"
+
+enum max98095_type {
+        MAX98095,
+};
+
+struct max98095_cdata {
+        unsigned int rate;
+        unsigned int fmt;
+        int eq_sel;
+        int bq_sel;
+};
+
+struct max98095_priv {
+        enum max98095_type devtype;
+        void *control_data;
+        struct max98095_pdata *pdata;
+        unsigned int sysclk;
+        struct max98095_cdata dai[3];
+        const char **eq_texts;
+        const char **bq_texts;
+        struct soc_enum eq_enum;
+        struct soc_enum bq_enum;
+        int eq_textcnt;
+        int bq_textcnt;
+        u8 lin_state;
+        unsigned int mic1pre;
+        unsigned int mic2pre;
+};
+
+static const u8 max98095_reg_def[M98095_REG_CNT] = {
+        0x00, /* 00 */
+        0x00, /* 01 */
+        0x00, /* 02 */
+        0x00, /* 03 */
+        0x00, /* 04 */
+        0x00, /* 05 */
+        0x00, /* 06 */
+        0x00, /* 07 */
+        0x00, /* 08 */
+        0x00, /* 09 */
+        0x00, /* 0A */
+        0x00, /* 0B */
+        0x00, /* 0C */
+        0x00, /* 0D */
+        0x00, /* 0E */
+        0x00, /* 0F */
+        0x00, /* 10 */
+        0x00, /* 11 */
+        0x00, /* 12 */
+        0x00, /* 13 */
+        0x00, /* 14 */
+        0x00, /* 15 */
+        0x00, /* 16 */
+        0x00, /* 17 */
+        0x00, /* 18 */
+        0x00, /* 19 */
+        0x00, /* 1A */
+        0x00, /* 1B */
+        0x00, /* 1C */
+        0x00, /* 1D */
+        0x00, /* 1E */
+        0x00, /* 1F */
+        0x00, /* 20 */
+        0x00, /* 21 */
+        0x00, /* 22 */
+        0x00, /* 23 */
+        0x00, /* 24 */
+        0x00, /* 25 */
+        0x00, /* 26 */
+        0x00, /* 27 */
+        0x00, /* 28 */
+        0x00, /* 29 */
+        0x00, /* 2A */
+        0x00, /* 2B */
+        0x00, /* 2C */
+        0x00, /* 2D */
+        0x00, /* 2E */
+        0x00, /* 2F */
+        0x00, /* 30 */
+        0x00, /* 31 */
+        0x00, /* 32 */
+        0x00, /* 33 */
+        0x00, /* 34 */
+        0x00, /* 35 */
+        0x00, /* 36 */
+        0x00, /* 37 */
+        0x00, /* 38 */
+        0x00, /* 39 */
+        0x00, /* 3A */
+        0x00, /* 3B */
+        0x00, /* 3C */
+        0x00, /* 3D */
+        0x00, /* 3E */
+        0x00, /* 3F */
+        0x00, /* 40 */
+        0x00, /* 41 */
+        0x00, /* 42 */
+        0x00, /* 43 */
+        0x00, /* 44 */
+        0x00, /* 45 */
+        0x00, /* 46 */
+        0x00, /* 47 */
+        0x00, /* 48 */
+        0x00, /* 49 */
+        0x00, /* 4A */
+        0x00, /* 4B */
+        0x00, /* 4C */
+        0x00, /* 4D */
+        0x00, /* 4E */
+        0x00, /* 4F */
+        0x00, /* 50 */
+        0x00, /* 51 */
+        0x00, /* 52 */
+        0x00, /* 53 */
+        0x00, /* 54 */
+        0x00, /* 55 */
+        0x00, /* 56 */
+        0x00, /* 57 */
+        0x00, /* 58 */
+        0x00, /* 59 */
+        0x00, /* 5A */
+        0x00, /* 5B */
+        0x00, /* 5C */
+        0x00, /* 5D */
+        0x00, /* 5E */
+        0x00, /* 5F */
+        0x00, /* 60 */
+        0x00, /* 61 */
+        0x00, /* 62 */
+        0x00, /* 63 */
+        0x00, /* 64 */
+        0x00, /* 65 */
+        0x00, /* 66 */
+        0x00, /* 67 */
+        0x00, /* 68 */
+        0x00, /* 69 */
+        0x00, /* 6A */
+        0x00, /* 6B */
+        0x00, /* 6C */
+        0x00, /* 6D */
+        0x00, /* 6E */
+        0x00, /* 6F */
+        0x00, /* 70 */
+        0x00, /* 71 */
+        0x00, /* 72 */
+        0x00, /* 73 */
+        0x00, /* 74 */
+        0x00, /* 75 */
+        0x00, /* 76 */
+        0x00, /* 77 */
+        0x00, /* 78 */
+        0x00, /* 79 */
+        0x00, /* 7A */
+        0x00, /* 7B */
+        0x00, /* 7C */
+        0x00, /* 7D */
+        0x00, /* 7E */
+        0x00, /* 7F */
+        0x00, /* 80 */
+        0x00, /* 81 */
+        0x00, /* 82 */
+        0x00, /* 83 */
+        0x00, /* 84 */
+        0x00, /* 85 */
+        0x00, /* 86 */
+        0x00, /* 87 */
+        0x00, /* 88 */
+        0x00, /* 89 */
+        0x00, /* 8A */
+        0x00, /* 8B */
+        0x00, /* 8C */
+        0x00, /* 8D */
+        0x00, /* 8E */
+        0x00, /* 8F */
+        0x00, /* 90 */
+        0x00, /* 91 */
+        0x30, /* 92 */
+        0xF0, /* 93 */
+        0x00, /* 94 */
+        0x00, /* 95 */
+        0x3F, /* 96 */
+        0x00, /* 97 */
+        0x00, /* 98 */
+        0x00, /* 99 */
+        0x00, /* 9A */
+        0x00, /* 9B */
+        0x00, /* 9C */
+        0x00, /* 9D */
+        0x00, /* 9E */
+        0x00, /* 9F */
+        0x00, /* A0 */
+        0x00, /* A1 */
+        0x00, /* A2 */
+        0x00, /* A3 */
+        0x00, /* A4 */
+        0x00, /* A5 */
+        0x00, /* A6 */
+        0x00, /* A7 */
+        0x00, /* A8 */
+        0x00, /* A9 */
+        0x00, /* AA */
+        0x00, /* AB */
+        0x00, /* AC */
+        0x00, /* AD */
+        0x00, /* AE */
+        0x00, /* AF */
+        0x00, /* B0 */
+        0x00, /* B1 */
+        0x00, /* B2 */
+        0x00, /* B3 */
+        0x00, /* B4 */
+        0x00, /* B5 */
+        0x00, /* B6 */
+        0x00, /* B7 */
+        0x00, /* B8 */
+        0x00, /* B9 */
+        0x00, /* BA */
+        0x00, /* BB */
+        0x00, /* BC */
+        0x00, /* BD */
+        0x00, /* BE */
+        0x00, /* BF */
+        0x00, /* C0 */
+        0x00, /* C1 */
+        0x00, /* C2 */
+        0x00, /* C3 */
+        0x00, /* C4 */
+        0x00, /* C5 */
+        0x00, /* C6 */
+        0x00, /* C7 */
+        0x00, /* C8 */
+        0x00, /* C9 */
+        0x00, /* CA */
+        0x00, /* CB */
+        0x00, /* CC */
+        0x00, /* CD */
+        0x00, /* CE */
+        0x00, /* CF */
+        0x00, /* D0 */
+        0x00, /* D1 */
+        0x00, /* D2 */
+        0x00, /* D3 */
+        0x00, /* D4 */
+        0x00, /* D5 */
+        0x00, /* D6 */
+        0x00, /* D7 */
+        0x00, /* D8 */
+        0x00, /* D9 */
+        0x00, /* DA */
+        0x00, /* DB */
+        0x00, /* DC */
+        0x00, /* DD */
+        0x00, /* DE */
+        0x00, /* DF */
+        0x00, /* E0 */
+        0x00, /* E1 */
+        0x00, /* E2 */
+        0x00, /* E3 */
+        0x00, /* E4 */
+        0x00, /* E5 */
+        0x00, /* E6 */
+        0x00, /* E7 */
+        0x00, /* E8 */
+        0x00, /* E9 */
+        0x00, /* EA */
+        0x00, /* EB */
+        0x00, /* EC */
+        0x00, /* ED */
+        0x00, /* EE */
+        0x00, /* EF */
+        0x00, /* F0 */
+        0x00, /* F1 */
+        0x00, /* F2 */
+        0x00, /* F3 */
+        0x00, /* F4 */
+        0x00, /* F5 */
+        0x00, /* F6 */
+        0x00, /* F7 */
+        0x00, /* F8 */
+        0x00, /* F9 */
+        0x00, /* FA */
+        0x00, /* FB */
+        0x00, /* FC */
+        0x00, /* FD */
+        0x00, /* FE */
+        0x00, /* FF */
+};
+
+static struct {
+        int readable;
+        int writable;
+} max98095_access[M98095_REG_CNT] = {
+        { 0x00, 0x00 }, /* 00 */
+        { 0xFF, 0x00 }, /* 01 */
+        { 0xFF, 0x00 }, /* 02 */
+        { 0xFF, 0x00 }, /* 03 */
+        { 0xFF, 0x00 }, /* 04 */
+        { 0xFF, 0x00 }, /* 05 */
+        { 0xFF, 0x00 }, /* 06 */
+        { 0xFF, 0x00 }, /* 07 */
+        { 0xFF, 0x00 }, /* 08 */
+        { 0xFF, 0x00 }, /* 09 */
+        { 0xFF, 0x00 }, /* 0A */
+        { 0xFF, 0x00 }, /* 0B */
+        { 0xFF, 0x00 }, /* 0C */
+        { 0xFF, 0x00 }, /* 0D */
+        { 0xFF, 0x00 }, /* 0E */
+        { 0xFF, 0x9F }, /* 0F */
+        { 0xFF, 0xFF }, /* 10 */
+        { 0xFF, 0xFF }, /* 11 */
+        { 0xFF, 0xFF }, /* 12 */
+        { 0xFF, 0xFF }, /* 13 */
+        { 0xFF, 0xFF }, /* 14 */
+        { 0xFF, 0xFF }, /* 15 */
+        { 0xFF, 0xFF }, /* 16 */
+        { 0xFF, 0xFF }, /* 17 */
+        { 0xFF, 0xFF }, /* 18 */
+        { 0xFF, 0xFF }, /* 19 */
+        { 0xFF, 0xFF }, /* 1A */
+        { 0xFF, 0xFF }, /* 1B */
+        { 0xFF, 0xFF }, /* 1C */
+        { 0xFF, 0xFF }, /* 1D */
+        { 0xFF, 0x77 }, /* 1E */
+        { 0xFF, 0x77 }, /* 1F */
+        { 0xFF, 0x77 }, /* 20 */
+        { 0xFF, 0x77 }, /* 21 */
+        { 0xFF, 0x77 }, /* 22 */
+        { 0xFF, 0x77 }, /* 23 */
+        { 0xFF, 0xFF }, /* 24 */
+        { 0xFF, 0x7F }, /* 25 */
+        { 0xFF, 0x31 }, /* 26 */
+        { 0xFF, 0xFF }, /* 27 */
+        { 0xFF, 0xFF }, /* 28 */
+        { 0xFF, 0xFF }, /* 29 */
+        { 0xFF, 0xF7 }, /* 2A */
+        { 0xFF, 0x2F }, /* 2B */
+        { 0xFF, 0xEF }, /* 2C */
+        { 0xFF, 0xFF }, /* 2D */
+        { 0xFF, 0xFF }, /* 2E */
+        { 0xFF, 0xFF }, /* 2F */
+        { 0xFF, 0xFF }, /* 30 */
+        { 0xFF, 0xFF }, /* 31 */
+        { 0xFF, 0xFF }, /* 32 */
+        { 0xFF, 0xFF }, /* 33 */
+        { 0xFF, 0xF7 }, /* 34 */
+        { 0xFF, 0x2F }, /* 35 */
+        { 0xFF, 0xCF }, /* 36 */
+        { 0xFF, 0xFF }, /* 37 */
+        { 0xFF, 0xFF }, /* 38 */
+        { 0xFF, 0xFF }, /* 39 */
+        { 0xFF, 0xFF }, /* 3A */
+        { 0xFF, 0xFF }, /* 3B */
+        { 0xFF, 0xFF }, /* 3C */
+        { 0xFF, 0xFF }, /* 3D */
+        { 0xFF, 0xF7 }, /* 3E */
+        { 0xFF, 0x2F }, /* 3F */
+        { 0xFF, 0xCF }, /* 40 */
+        { 0xFF, 0xFF }, /* 41 */
+        { 0xFF, 0x77 }, /* 42 */
+        { 0xFF, 0xFF }, /* 43 */
+        { 0xFF, 0xFF }, /* 44 */
+        { 0xFF, 0xFF }, /* 45 */
+        { 0xFF, 0xFF }, /* 46 */
+        { 0xFF, 0xFF }, /* 47 */
+        { 0xFF, 0xFF }, /* 48 */
+        { 0xFF, 0x0F }, /* 49 */
+        { 0xFF, 0xFF }, /* 4A */
+        { 0xFF, 0xFF }, /* 4B */
+        { 0xFF, 0x3F }, /* 4C */
+        { 0xFF, 0x3F }, /* 4D */
+        { 0xFF, 0x3F }, /* 4E */
+        { 0xFF, 0xFF }, /* 4F */
+        { 0xFF, 0x7F }, /* 50 */
+        { 0xFF, 0x7F }, /* 51 */
+        { 0xFF, 0x0F }, /* 52 */
+        { 0xFF, 0x3F }, /* 53 */
+        { 0xFF, 0x3F }, /* 54 */
+        { 0xFF, 0x3F }, /* 55 */
+        { 0xFF, 0xFF }, /* 56 */
+        { 0xFF, 0xFF }, /* 57 */
+        { 0xFF, 0xBF }, /* 58 */
+        { 0xFF, 0x1F }, /* 59 */
+        { 0xFF, 0xBF }, /* 5A */
+        { 0xFF, 0x1F }, /* 5B */
+        { 0xFF, 0xBF }, /* 5C */
+        { 0xFF, 0x3F }, /* 5D */
+        { 0xFF, 0x3F }, /* 5E */
+        { 0xFF, 0x7F }, /* 5F */
+        { 0xFF, 0x7F }, /* 60 */
+        { 0xFF, 0x47 }, /* 61 */
+        { 0xFF, 0x9F }, /* 62 */
+        { 0xFF, 0x9F }, /* 63 */
+        { 0xFF, 0x9F }, /* 64 */
+        { 0xFF, 0x9F }, /* 65 */
+        { 0xFF, 0x9F }, /* 66 */
+        { 0xFF, 0xBF }, /* 67 */
+        { 0xFF, 0xBF }, /* 68 */
+        { 0xFF, 0xFF }, /* 69 */
+        { 0xFF, 0xFF }, /* 6A */
+        { 0xFF, 0x7F }, /* 6B */
+        { 0xFF, 0xF7 }, /* 6C */
+        { 0xFF, 0xFF }, /* 6D */
+        { 0xFF, 0xFF }, /* 6E */
+        { 0xFF, 0x1F }, /* 6F */
+        { 0xFF, 0xF7 }, /* 70 */
+        { 0xFF, 0xFF }, /* 71 */
+        { 0xFF, 0xFF }, /* 72 */
+        { 0xFF, 0x1F }, /* 73 */
+        { 0xFF, 0xF7 }, /* 74 */
+        { 0xFF, 0xFF }, /* 75 */
+        { 0xFF, 0xFF }, /* 76 */
+        { 0xFF, 0x1F }, /* 77 */
+        { 0xFF, 0xF7 }, /* 78 */
+        { 0xFF, 0xFF }, /* 79 */
+        { 0xFF, 0xFF }, /* 7A */
+        { 0xFF, 0x1F }, /* 7B */
+        { 0xFF, 0xF7 }, /* 7C */
+        { 0xFF, 0xFF }, /* 7D */
+        { 0xFF, 0xFF }, /* 7E */
+        { 0xFF, 0x1F }, /* 7F */
+        { 0xFF, 0xF7 }, /* 80 */
+        { 0xFF, 0xFF }, /* 81 */
+        { 0xFF, 0xFF }, /* 82 */
+        { 0xFF, 0x1F }, /* 83 */
+        { 0xFF, 0x7F }, /* 84 */
+        { 0xFF, 0x0F }, /* 85 */
+        { 0xFF, 0xD8 }, /* 86 */
+        { 0xFF, 0xFF }, /* 87 */
+        { 0xFF, 0xEF }, /* 88 */
+        { 0xFF, 0xFE }, /* 89 */
+        { 0xFF, 0xFE }, /* 8A */
+        { 0xFF, 0xFF }, /* 8B */
+        { 0xFF, 0xFF }, /* 8C */
+        { 0xFF, 0x3F }, /* 8D */
+        { 0xFF, 0xFF }, /* 8E */
+        { 0xFF, 0x3F }, /* 8F */
+        { 0xFF, 0x8F }, /* 90 */
+        { 0xFF, 0xFF }, /* 91 */
+        { 0xFF, 0x3F }, /* 92 */
+        { 0xFF, 0xFF }, /* 93 */
+        { 0xFF, 0xFF }, /* 94 */
+        { 0xFF, 0x0F }, /* 95 */
+        { 0xFF, 0x3F }, /* 96 */
+        { 0xFF, 0x8C }, /* 97 */
+        { 0x00, 0x00 }, /* 98 */
+        { 0x00, 0x00 }, /* 99 */
+        { 0x00, 0x00 }, /* 9A */
+        { 0x00, 0x00 }, /* 9B */
+        { 0x00, 0x00 }, /* 9C */
+        { 0x00, 0x00 }, /* 9D */
+        { 0x00, 0x00 }, /* 9E */
+        { 0x00, 0x00 }, /* 9F */
+        { 0x00, 0x00 }, /* A0 */
+        { 0x00, 0x00 }, /* A1 */
+        { 0x00, 0x00 }, /* A2 */
+        { 0x00, 0x00 }, /* A3 */
+        { 0x00, 0x00 }, /* A4 */
+        { 0x00, 0x00 }, /* A5 */
+        { 0x00, 0x00 }, /* A6 */
+        { 0x00, 0x00 }, /* A7 */
+        { 0x00, 0x00 }, /* A8 */
+        { 0x00, 0x00 }, /* A9 */
+        { 0x00, 0x00 }, /* AA */
+        { 0x00, 0x00 }, /* AB */
+        { 0x00, 0x00 }, /* AC */
+        { 0x00, 0x00 }, /* AD */
+        { 0x00, 0x00 }, /* AE */
+        { 0x00, 0x00 }, /* AF */
+        { 0x00, 0x00 }, /* B0 */
+        { 0x00, 0x00 }, /* B1 */
+        { 0x00, 0x00 }, /* B2 */
+        { 0x00, 0x00 }, /* B3 */
+        { 0x00, 0x00 }, /* B4 */
+        { 0x00, 0x00 }, /* B5 */
+        { 0x00, 0x00 }, /* B6 */
+        { 0x00, 0x00 }, /* B7 */
+        { 0x00, 0x00 }, /* B8 */
+        { 0x00, 0x00 }, /* B9 */
+        { 0x00, 0x00 }, /* BA */
+        { 0x00, 0x00 }, /* BB */
+        { 0x00, 0x00 }, /* BC */
+        { 0x00, 0x00 }, /* BD */
+        { 0x00, 0x00 }, /* BE */
+        { 0x00, 0x00 }, /* BF */
+        { 0x00, 0x00 }, /* C0 */
+        { 0x00, 0x00 }, /* C1 */
+        { 0x00, 0x00 }, /* C2 */
+        { 0x00, 0x00 }, /* C3 */
+        { 0x00, 0x00 }, /* C4 */
+        { 0x00, 0x00 }, /* C5 */
+        { 0x00, 0x00 }, /* C6 */
+        { 0x00, 0x00 }, /* C7 */
+        { 0x00, 0x00 }, /* C8 */
+        { 0x00, 0x00 }, /* C9 */
+        { 0x00, 0x00 }, /* CA */
+        { 0x00, 0x00 }, /* CB */
+        { 0x00, 0x00 }, /* CC */
+        { 0x00, 0x00 }, /* CD */
+        { 0x00, 0x00 }, /* CE */
+        { 0x00, 0x00 }, /* CF */
+        { 0x00, 0x00 }, /* D0 */
+        { 0x00, 0x00 }, /* D1 */
+        { 0x00, 0x00 }, /* D2 */
+        { 0x00, 0x00 }, /* D3 */
+        { 0x00, 0x00 }, /* D4 */
+        { 0x00, 0x00 }, /* D5 */
+        { 0x00, 0x00 }, /* D6 */
+        { 0x00, 0x00 }, /* D7 */
+        { 0x00, 0x00 }, /* D8 */
+        { 0x00, 0x00 }, /* D9 */
+        { 0x00, 0x00 }, /* DA */
+        { 0x00, 0x00 }, /* DB */
+        { 0x00, 0x00 }, /* DC */
+        { 0x00, 0x00 }, /* DD */
+        { 0x00, 0x00 }, /* DE */
+        { 0x00, 0x00 }, /* DF */
+        { 0x00, 0x00 }, /* E0 */
+        { 0x00, 0x00 }, /* E1 */
+        { 0x00, 0x00 }, /* E2 */
+        { 0x00, 0x00 }, /* E3 */
+        { 0x00, 0x00 }, /* E4 */
+        { 0x00, 0x00 }, /* E5 */
+        { 0x00, 0x00 }, /* E6 */
+        { 0x00, 0x00 }, /* E7 */
+        { 0x00, 0x00 }, /* E8 */
+        { 0x00, 0x00 }, /* E9 */
+        { 0x00, 0x00 }, /* EA */
+        { 0x00, 0x00 }, /* EB */
+        { 0x00, 0x00 }, /* EC */
+        { 0x00, 0x00 }, /* ED */
+        { 0x00, 0x00 }, /* EE */
+        { 0x00, 0x00 }, /* EF */
+        { 0x00, 0x00 }, /* F0 */
+        { 0x00, 0x00 }, /* F1 */
+        { 0x00, 0x00 }, /* F2 */
+        { 0x00, 0x00 }, /* F3 */
+        { 0x00, 0x00 }, /* F4 */
+        { 0x00, 0x00 }, /* F5 */
+        { 0x00, 0x00 }, /* F6 */
+        { 0x00, 0x00 }, /* F7 */
+        { 0x00, 0x00 }, /* F8 */
+        { 0x00, 0x00 }, /* F9 */
+        { 0x00, 0x00 }, /* FA */
+        { 0x00, 0x00 }, /* FB */
+        { 0x00, 0x00 }, /* FC */
+        { 0x00, 0x00 }, /* FD */
+        { 0x00, 0x00 }, /* FE */
+        { 0xFF, 0x00 }, /* FF */
+};
+
+static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg)
+{
+        if (reg >= M98095_REG_CNT)
+                return 0;
+        return max98095_access[reg].readable != 0;
+}
+
+static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg)
+{
+        if (reg > M98095_REG_MAX_CACHED)
+                return 1;
+
+        switch (reg) {
+        case M98095_000_HOST_DATA:
+        case M98095_001_HOST_INT_STS:
+        case M98095_002_HOST_RSP_STS:
+        case M98095_003_HOST_CMD_STS:
+        case M98095_004_CODEC_STS:
+        case M98095_005_DAI1_ALC_STS:
+        case M98095_006_DAI2_ALC_STS:
+        case M98095_007_JACK_AUTO_STS:
+        case M98095_008_JACK_MANUAL_STS:
+        case M98095_009_JACK_VBAT_STS:
+        case M98095_00A_ACC_ADC_STS:
+        case M98095_00B_MIC_NG_AGC_STS:
+        case M98095_00C_SPK_L_VOLT_STS:
+        case M98095_00D_SPK_R_VOLT_STS:
+        case M98095_00E_TEMP_SENSOR_STS:
+                return 1;
+        }
+
+        return 0;
+}
+
+/*
+ * Filter coefficients are in a separate register segment
+ * and they share the address space of the normal registers.
+ * The coefficient registers do not need or share the cache.
+ */
+static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg,
+                             unsigned int value)
+{
+        u8 data[2];
+
+        data[0] = reg;
+        data[1] = value;
+        if (codec->hw_write(codec->control_data, data, 2) == 2)
+                return 0;
+        else
+                return -EIO;
+}
+
+/*
+ * Load equalizer DSP coefficient configurations registers
+ */
+static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
+                    unsigned int band, u16 *coefs)
+{
+        unsigned int eq_reg;
+        unsigned int i;
+
+        BUG_ON(band > 4);
+        BUG_ON(dai > 1);
+
+        /* Load the base register address */
+        eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
+
+        /* Add the band address offset, note adjustment for word address */
+        eq_reg += band * (M98095_COEFS_PER_BAND << 1);
+
+        /* Step through the registers and coefs */
+        for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
+                max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
+                max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
+        }
+}
+
+/*
+ * Load biquad filter coefficient configurations registers
+ */
+static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
+                    unsigned int band, u16 *coefs)
+{
+        unsigned int bq_reg;
+        unsigned int i;
+
+        BUG_ON(band > 1);
+        BUG_ON(dai > 1);
+
+        /* Load the base register address */
+        bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
+
+        /* Add the band address offset, note adjustment for word address */
+        bq_reg += band * (M98095_COEFS_PER_BAND << 1);
+
+        /* Step through the registers and coefs */
+        for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
+                max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
+                max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
+        }
+}
+
+static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
+static const struct soc_enum max98095_dai1_filter_mode_enum[] = {
+        SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode),
+};
+static const struct soc_enum max98095_dai2_filter_mode_enum[] = {
+        SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode),
+};
+
+static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
+
+static const struct soc_enum max98095_extmic_enum =
+        SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text);
+
+static const struct snd_kcontrol_new max98095_extmic_mux =
+        SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
+
+static const char * const max98095_linein_text[] = { "INA", "INB" };
+
+static const struct soc_enum max98095_linein_enum =
+        SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text);
+
+static const struct snd_kcontrol_new max98095_linein_mux =
+        SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
+
+static const char * const max98095_line_mode_text[] = {
+        "Stereo", "Differential"};
+
+static const struct soc_enum max98095_linein_mode_enum =
+        SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text);
+
+static const struct soc_enum max98095_lineout_mode_enum =
+        SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text);
+
+static const char * const max98095_dai_fltr[] = {
+        "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
+        "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
+static const struct soc_enum max98095_dai1_dac_filter_enum[] = {
+        SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr),
+};
+static const struct soc_enum max98095_dai2_dac_filter_enum[] = {
+        SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr),
+};
+static const struct soc_enum max98095_dai3_dac_filter_enum[] = {
+        SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr),
+};
+
+static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        unsigned int sel = ucontrol->value.integer.value[0];
+
+        max98095->mic1pre = sel;
+        snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
+                (1+sel)<<M98095_MICPRE_SHIFT);
+
+        return 0;
+}
+
+static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = max98095->mic1pre;
+        return 0;
+}
+
+static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        unsigned int sel = ucontrol->value.integer.value[0];
+
+        max98095->mic2pre = sel;
+        snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
+                (1+sel)<<M98095_MICPRE_SHIFT);
+
+        return 0;
+}
+
+static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = max98095->mic2pre;
+        return 0;
+}
+
+static const unsigned int max98095_micboost_tlv[] = {
+        TLV_DB_RANGE_HEAD(2),
+        0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
+        2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
+};
+
+static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
+static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
+static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
+
+static const unsigned int max98095_hp_tlv[] = {
+        TLV_DB_RANGE_HEAD(5),
+        0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
+        7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
+        15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
+        22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
+        28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
+};
+
+static const unsigned int max98095_spk_tlv[] = {
+        TLV_DB_RANGE_HEAD(4),
+        0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
+        11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
+        19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
+        28, 39, TLV_DB_SCALE_ITEM(650, 50, 0),
+};
+
+static const unsigned int max98095_rcv_lout_tlv[] = {
+        TLV_DB_RANGE_HEAD(5),
+        0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
+        7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
+        15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
+        22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
+        28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
+};
+
+static const unsigned int max98095_lin_tlv[] = {
+        TLV_DB_RANGE_HEAD(3),
+        0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
+        3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
+        4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
+};
+
+static const struct snd_kcontrol_new max98095_snd_controls[] = {
+
+        SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
+                M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
+
+        SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
+                M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
+
+        SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
+                0, 31, 0, max98095_rcv_lout_tlv),
+
+        SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
+                M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
+
+        SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
+                M98095_065_LVL_HP_R, 7, 1, 1),
+
+        SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
+                M98095_068_LVL_SPK_R, 7, 1, 1),
+
+        SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
+
+        SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
+                M98095_063_LVL_LINEOUT2, 7, 1, 1),
+
+        SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
+                max98095_mic_tlv),
+
+        SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
+                max98095_mic_tlv),
+
+        SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
+                        M98095_05F_LVL_MIC1, 5, 2, 0,
+                        max98095_mic1pre_get, max98095_mic1pre_set,
+                        max98095_micboost_tlv),
+        SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
+                        M98095_060_LVL_MIC2, 5, 2, 0,
+                        max98095_mic2pre_get, max98095_mic2pre_set,
+                        max98095_micboost_tlv),
+
+        SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
+                max98095_lin_tlv),
+
+        SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
+                max98095_adc_tlv),
+        SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
+                max98095_adc_tlv),
+
+        SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
+                max98095_adcboost_tlv),
+        SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
+                max98095_adcboost_tlv),
+
+        SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
+        SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
+
+        SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
+        SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
+
+        SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
+        SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
+        SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
+        SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
+        SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
+
+        SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
+        SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
+};
+
+/* Left speaker mixer switch */
+static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
+        SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
+        SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
+        SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
+};
+
+/* Right speaker mixer switch */
+static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
+        SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
+        SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
+        SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
+};
+
+/* Left headphone mixer switch */
+static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
+        SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
+};
+
+/* Right headphone mixer switch */
+static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
+        SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
+};
+
+/* Receiver earpiece mixer switch */
+static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
+        SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
+};
+
+/* Left lineout mixer switch */
+static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
+        SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
+};
+
+/* Right lineout mixer switch */
+static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
+        SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
+};
+
+/* Left ADC mixer switch */
+static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
+};
+
+/* Right ADC mixer switch */
+static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
+        SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
+        SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
+        SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
+        SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
+};
+
+static int max98095_mic_event(struct snd_soc_dapm_widget *w,
+                             struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                if (w->reg == M98095_05F_LVL_MIC1) {
+                        snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
+                                (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
+                } else {
+                        snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
+                                (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
+                }
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+/*
+ * The line inputs are stereo inputs with the left and right
+ * channels sharing a common PGA power control signal.
+ */
+static int max98095_line_pga(struct snd_soc_dapm_widget *w,
+                             int event, u8 channel)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        u8 *state;
+
+        BUG_ON(!((channel == 1) || (channel == 2)));
+
+        state = &max98095->lin_state;
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                *state |= channel;
+                snd_soc_update_bits(codec, w->reg,
+                        (1 << w->shift), (1 << w->shift));
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                *state &= ~channel;
+                if (*state == 0) {
+                        snd_soc_update_bits(codec, w->reg,
+                                (1 << w->shift), 0);
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
+                                   struct snd_kcontrol *k, int event)
+{
+        return max98095_line_pga(w, event, 1);
+}
+
+static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
+                                   struct snd_kcontrol *k, int event)
+{
+        return max98095_line_pga(w, event, 2);
+}
+
+/*
+ * The stereo line out mixer outputs to two stereo line outs.
+ * The 2nd pair has a separate set of enables.
+ */
+static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
+                             struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                snd_soc_update_bits(codec, w->reg,
+                        (1 << (w->shift+2)), (1 << (w->shift+2)));
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                snd_soc_update_bits(codec, w->reg,
+                        (1 << (w->shift+2)), 0);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
+
+        SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
+        SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
+
+        SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
+                M98095_091_PWR_EN_OUT, 0, 0),
+        SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
+                M98095_091_PWR_EN_OUT, 1, 0),
+        SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
+                M98095_091_PWR_EN_OUT, 2, 0),
+        SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
+                M98095_091_PWR_EN_OUT, 2, 0),
+
+        SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
+                6, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
+                7, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
+                4, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
+                5, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
+                3, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
+                0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
+        SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
+                1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
+
+        SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
+                &max98095_extmic_mux),
+
+        SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
+                &max98095_linein_mux),
+
+        SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
+                &max98095_left_hp_mixer_controls[0],
+                ARRAY_SIZE(max98095_left_hp_mixer_controls)),
+
+        SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
+                &max98095_right_hp_mixer_controls[0],
+                ARRAY_SIZE(max98095_right_hp_mixer_controls)),
+
+        SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
+                &max98095_left_speaker_mixer_controls[0],
+                ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
+
+        SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
+                &max98095_right_speaker_mixer_controls[0],
+                ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
+
+        SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
+          &max98095_mono_rcv_mixer_controls[0],
+                ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
+
+        SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
+                &max98095_left_lineout_mixer_controls[0],
+                ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
+
+        SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
+                &max98095_right_lineout_mixer_controls[0],
+                ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
+
+        SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
+                &max98095_left_ADC_mixer_controls[0],
+                ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
+
+        SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
+                &max98095_right_ADC_mixer_controls[0],
+                ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
+
+        SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
+                5, 0, NULL, 0, max98095_mic_event,
+                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+        SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
+                5, 0, NULL, 0, max98095_mic_event,
+                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+        SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
+                7, 0, NULL, 0, max98095_pga_in1_event,
+                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+        SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
+                7, 0, NULL, 0, max98095_pga_in2_event,
+                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+        SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
+        SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
+
+        SND_SOC_DAPM_OUTPUT("HPL"),
+        SND_SOC_DAPM_OUTPUT("HPR"),
+        SND_SOC_DAPM_OUTPUT("SPKL"),
+        SND_SOC_DAPM_OUTPUT("SPKR"),
+        SND_SOC_DAPM_OUTPUT("RCV"),
+        SND_SOC_DAPM_OUTPUT("OUT1"),
+        SND_SOC_DAPM_OUTPUT("OUT2"),
+        SND_SOC_DAPM_OUTPUT("OUT3"),
+        SND_SOC_DAPM_OUTPUT("OUT4"),
+
+        SND_SOC_DAPM_INPUT("MIC1"),
+        SND_SOC_DAPM_INPUT("MIC2"),
+        SND_SOC_DAPM_INPUT("INA1"),
+        SND_SOC_DAPM_INPUT("INA2"),
+        SND_SOC_DAPM_INPUT("INB1"),
+        SND_SOC_DAPM_INPUT("INB2"),
+};
+
+static const struct snd_soc_dapm_route max98095_audio_map[] = {
+        /* Left headphone output mixer */
+        {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
+        {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
+        {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
+        {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
+
+        /* Right headphone output mixer */
+        {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
+        {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
+        {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
+        {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
+
+        /* Left speaker output mixer */
+        {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
+        {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
+        {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
+        {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
+        {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
+        {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
+
+        /* Right speaker output mixer */
+        {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
+        {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
+        {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
+        {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
+        {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
+        {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
+
+        /* Earpiece/Receiver output mixer */
+        {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
+        {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
+        {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
+        {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
+
+        /* Left Lineout output mixer */
+        {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
+        {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
+        {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
+        {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
+
+        /* Right lineout output mixer */
+        {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
+        {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
+        {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
+        {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
+
+        {"HP Left Out", NULL, "Left Headphone Mixer"},
+        {"HP Right Out", NULL, "Right Headphone Mixer"},
+        {"SPK Left Out", NULL, "Left Speaker Mixer"},
+        {"SPK Right Out", NULL, "Right Speaker Mixer"},
+        {"RCV Mono Out", NULL, "Receiver Mixer"},
+        {"LINE Left Out", NULL, "Left Lineout Mixer"},
+        {"LINE Right Out", NULL, "Right Lineout Mixer"},
+
+        {"HPL", NULL, "HP Left Out"},
+        {"HPR", NULL, "HP Right Out"},
+        {"SPKL", NULL, "SPK Left Out"},
+        {"SPKR", NULL, "SPK Right Out"},
+        {"RCV", NULL, "RCV Mono Out"},
+        {"OUT1", NULL, "LINE Left Out"},
+        {"OUT2", NULL, "LINE Right Out"},
+        {"OUT3", NULL, "LINE Left Out"},
+        {"OUT4", NULL, "LINE Right Out"},
+
+        /* Left ADC input mixer */
+        {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
+        {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
+
+        /* Right ADC input mixer */
+        {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
+        {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
+        {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
+        {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
+
+        /* Inputs */
+        {"ADCL", NULL, "Left ADC Mixer"},
+        {"ADCR", NULL, "Right ADC Mixer"},
+
+        {"IN1 Input", NULL, "INA1"},
+        {"IN2 Input", NULL, "INA2"},
+
+        {"MIC1 Input", NULL, "MIC1"},
+        {"MIC2 Input", NULL, "MIC2"},
+};
+
+static int max98095_add_widgets(struct snd_soc_codec *codec)
+{
+        snd_soc_add_controls(codec, max98095_snd_controls,
+                             ARRAY_SIZE(max98095_snd_controls));
+
+        return 0;
+}
+
+/* codec mclk clock divider coefficients */
+static const struct {
+        u32 rate;
+        u8  sr;
+} rate_table[] = {
+        {8000,  0x01},
+        {11025, 0x02},
+        {16000, 0x03},
+        {22050, 0x04},
+        {24000, 0x05},
+        {32000, 0x06},
+        {44100, 0x07},
+        {48000, 0x08},
+        {88200, 0x09},
+        {96000, 0x0A},
+};
+
+static int rate_value(int rate, u8 *value)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
+                if (rate_table[i].rate >= rate) {
+                        *value = rate_table[i].sr;
+                        return 0;
+                }
+        }
+        *value = rate_table[0].sr;
+        return -EINVAL;
+}
+
+static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
+                                   struct snd_pcm_hw_params *params,
+                                   struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_cdata *cdata;
+        unsigned long long ni;
+        unsigned int rate;
+        u8 regval;
+
+        cdata = &max98095->dai[0];
+
+        rate = params_rate(params);
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
+                        M98095_DAI_WS, 0);
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
+                        M98095_DAI_WS, M98095_DAI_WS);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (rate_value(rate, &regval))
+                return -EINVAL;
+
+        snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE,
+                M98095_CLKMODE_MASK, regval);
+        cdata->rate = rate;
+
+        /* Configure NI when operating as master */
+        if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
+                if (max98095->sysclk == 0) {
+                        dev_err(codec->dev, "Invalid system clock frequency\n");
+                        return -EINVAL;
+                }
+                ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
+                                * (unsigned long long int)rate;
+                do_div(ni, (unsigned long long int)max98095->sysclk);
+                snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
+                        (ni >> 8) & 0x7F);
+                snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
+                        ni & 0xFF);
+        }
+
+        /* Update sample rate mode */
+        if (rate < 50000)
+                snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
+                        M98095_DAI_DHF, 0);
+        else
+                snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
+                        M98095_DAI_DHF, M98095_DAI_DHF);
+
+        return 0;
+}
+
+static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
+                                   struct snd_pcm_hw_params *params,
+                                   struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_cdata *cdata;
+        unsigned long long ni;
+        unsigned int rate;
+        u8 regval;
+
+        cdata = &max98095->dai[1];
+
+        rate = params_rate(params);
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
+                        M98095_DAI_WS, 0);
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
+                        M98095_DAI_WS, M98095_DAI_WS);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (rate_value(rate, &regval))
+                return -EINVAL;
+
+        snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE,
+                M98095_CLKMODE_MASK, regval);
+        cdata->rate = rate;
+
+        /* Configure NI when operating as master */
+        if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
+                if (max98095->sysclk == 0) {
+                        dev_err(codec->dev, "Invalid system clock frequency\n");
+                        return -EINVAL;
+                }
+                ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
+                                * (unsigned long long int)rate;
+                do_div(ni, (unsigned long long int)max98095->sysclk);
+                snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
+                        (ni >> 8) & 0x7F);
+                snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
+                        ni & 0xFF);
+        }
+
+        /* Update sample rate mode */
+        if (rate < 50000)
+                snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
+                        M98095_DAI_DHF, 0);
+        else
+                snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
+                        M98095_DAI_DHF, M98095_DAI_DHF);
+
+        return 0;
+}
+
+static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
+                                   struct snd_pcm_hw_params *params,
+                                   struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_cdata *cdata;
+        unsigned long long ni;
+        unsigned int rate;
+        u8 regval;
+
+        cdata = &max98095->dai[2];
+
+        rate = params_rate(params);
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
+                        M98095_DAI_WS, 0);
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
+                        M98095_DAI_WS, M98095_DAI_WS);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (rate_value(rate, &regval))
+                return -EINVAL;
+
+        snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE,
+                M98095_CLKMODE_MASK, regval);
+        cdata->rate = rate;
+
+        /* Configure NI when operating as master */
+        if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
+                if (max98095->sysclk == 0) {
+                        dev_err(codec->dev, "Invalid system clock frequency\n");
+                        return -EINVAL;
+                }
+                ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
+                                * (unsigned long long int)rate;
+                do_div(ni, (unsigned long long int)max98095->sysclk);
+                snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
+                        (ni >> 8) & 0x7F);
+                snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
+                        ni & 0xFF);
+        }
+
+        /* Update sample rate mode */
+        if (rate < 50000)
+                snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
+                        M98095_DAI_DHF, 0);
+        else
+                snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
+                        M98095_DAI_DHF, M98095_DAI_DHF);
+
+        return 0;
+}
+
+static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
+                                   int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+
+        /* Requested clock frequency is already setup */
+        if (freq == max98095->sysclk)
+                return 0;
+
+        max98095->sysclk = freq; /* remember current sysclk */
+
+        /* Setup clocks for slave mode, and using the PLL
+         * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
+         *         0x02 (when master clk is 20MHz to 40MHz)..
+         *         0x03 (when master clk is 40MHz to 60MHz)..
+         */
+        if ((freq >= 10000000) && (freq < 20000000)) {
+                snd_soc_write(codec, M98095_026_SYS_CLK, 0x10);
+        } else if ((freq >= 20000000) && (freq < 40000000)) {
+                snd_soc_write(codec, M98095_026_SYS_CLK, 0x20);
+        } else if ((freq >= 40000000) && (freq < 60000000)) {
+                snd_soc_write(codec, M98095_026_SYS_CLK, 0x30);
+        } else {
+                dev_err(codec->dev, "Invalid master clock frequency\n");
+                return -EINVAL;
+        }
+
+        dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
+
+        max98095->sysclk = freq;
+        return 0;
+}
+
+static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
+                                 unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_cdata *cdata;
+        u8 regval = 0;
+
+        cdata = &max98095->dai[0];
+
+        if (fmt != cdata->fmt) {
+                cdata->fmt = fmt;
+
+                switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+                case SND_SOC_DAIFMT_CBS_CFS:
+                        /* Slave mode PLL */
+                        snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
+                                0x80);
+                        snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
+                                0x00);
+                        break;
+                case SND_SOC_DAIFMT_CBM_CFM:
+                        /* Set to master mode */
+                        regval |= M98095_DAI_MAS;
+                        break;
+                case SND_SOC_DAIFMT_CBS_CFM:
+                case SND_SOC_DAIFMT_CBM_CFS:
+                default:
+                        dev_err(codec->dev, "Clock mode unsupported");
+                        return -EINVAL;
+                }
+
+                switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+                case SND_SOC_DAIFMT_I2S:
+                        regval |= M98095_DAI_DLY;
+                        break;
+                case SND_SOC_DAIFMT_LEFT_J:
+                        break;
+                default:
+                        return -EINVAL;
+                }
+
+                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+                case SND_SOC_DAIFMT_NB_NF:
+                        break;
+                case SND_SOC_DAIFMT_NB_IF:
+                        regval |= M98095_DAI_WCI;
+                        break;
+                case SND_SOC_DAIFMT_IB_NF:
+                        regval |= M98095_DAI_BCI;
+                        break;
+                case SND_SOC_DAIFMT_IB_IF:
+                        regval |= M98095_DAI_BCI|M98095_DAI_WCI;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+
+                snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
+                        M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
+                        M98095_DAI_WCI, regval);
+
+                snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
+        }
+
+        return 0;
+}
+
+static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
+                                 unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_cdata *cdata;
+        u8 regval = 0;
+
+        cdata = &max98095->dai[1];
+
+        if (fmt != cdata->fmt) {
+                cdata->fmt = fmt;
+
+                switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+                case SND_SOC_DAIFMT_CBS_CFS:
+                        /* Slave mode PLL */
+                        snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
+                                0x80);
+                        snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
+                                0x00);
+                        break;
+                case SND_SOC_DAIFMT_CBM_CFM:
+                        /* Set to master mode */
+                        regval |= M98095_DAI_MAS;
+                        break;
+                case SND_SOC_DAIFMT_CBS_CFM:
+                case SND_SOC_DAIFMT_CBM_CFS:
+                default:
+                        dev_err(codec->dev, "Clock mode unsupported");
+                        return -EINVAL;
+                }
+
+                switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+                case SND_SOC_DAIFMT_I2S:
+                        regval |= M98095_DAI_DLY;
+                        break;
+                case SND_SOC_DAIFMT_LEFT_J:
+                        break;
+                default:
+                        return -EINVAL;
+                }
+
+                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+                case SND_SOC_DAIFMT_NB_NF:
+                        break;
+                case SND_SOC_DAIFMT_NB_IF:
+                        regval |= M98095_DAI_WCI;
+                        break;
+                case SND_SOC_DAIFMT_IB_NF:
+                        regval |= M98095_DAI_BCI;
+                        break;
+                case SND_SOC_DAIFMT_IB_IF:
+                        regval |= M98095_DAI_BCI|M98095_DAI_WCI;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+
+                snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
+                        M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
+                        M98095_DAI_WCI, regval);
+
+                snd_soc_write(codec, M98095_035_DAI2_CLOCK,
+                        M98095_DAI_BSEL64);
+        }
+
+        return 0;
+}
+
+static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
+                                 unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_cdata *cdata;
+        u8 regval = 0;
+
+        cdata = &max98095->dai[2];
+
+        if (fmt != cdata->fmt) {
+                cdata->fmt = fmt;
+
+                switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+                case SND_SOC_DAIFMT_CBS_CFS:
+                        /* Slave mode PLL */
+                        snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
+                                0x80);
+                        snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
+                                0x00);
+                        break;
+                case SND_SOC_DAIFMT_CBM_CFM:
+                        /* Set to master mode */
+                        regval |= M98095_DAI_MAS;
+                        break;
+                case SND_SOC_DAIFMT_CBS_CFM:
+                case SND_SOC_DAIFMT_CBM_CFS:
+                default:
+                        dev_err(codec->dev, "Clock mode unsupported");
+                        return -EINVAL;
+                }
+
+                switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+                case SND_SOC_DAIFMT_I2S:
+                        regval |= M98095_DAI_DLY;
+                        break;
+                case SND_SOC_DAIFMT_LEFT_J:
+                        break;
+                default:
+                        return -EINVAL;
+                }
+
+                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+                case SND_SOC_DAIFMT_NB_NF:
+                        break;
+                case SND_SOC_DAIFMT_NB_IF:
+                        regval |= M98095_DAI_WCI;
+                        break;
+                case SND_SOC_DAIFMT_IB_NF:
+                        regval |= M98095_DAI_BCI;
+                        break;
+                case SND_SOC_DAIFMT_IB_IF:
+                        regval |= M98095_DAI_BCI|M98095_DAI_WCI;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+
+                snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
+                        M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
+                        M98095_DAI_WCI, regval);
+
+                snd_soc_write(codec, M98095_03F_DAI3_CLOCK,
+                        M98095_DAI_BSEL64);
+        }
+
+        return 0;
+}
+
+static int max98095_set_bias_level(struct snd_soc_codec *codec,
+                                   enum snd_soc_bias_level level)
+{
+        int ret;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+
+        case SND_SOC_BIAS_PREPARE:
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = snd_soc_cache_sync(codec);
+
+                        if (ret != 0) {
+                                dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
+                                return ret;
+                        }
+                }
+
+                snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
+                                M98095_MBEN, M98095_MBEN);
+                break;
+
+        case SND_SOC_BIAS_OFF:
+                snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
+                                M98095_MBEN, 0);
+                codec->cache_sync = 1;
+                break;
+        }
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
+#define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
+
+static struct snd_soc_dai_ops max98095_dai1_ops = {
+        .set_sysclk = max98095_dai_set_sysclk,
+        .set_fmt = max98095_dai1_set_fmt,
+        .hw_params = max98095_dai1_hw_params,
+};
+
+static struct snd_soc_dai_ops max98095_dai2_ops = {
+        .set_sysclk = max98095_dai_set_sysclk,
+        .set_fmt = max98095_dai2_set_fmt,
+        .hw_params = max98095_dai2_hw_params,
+};
+
+static struct snd_soc_dai_ops max98095_dai3_ops = {
+        .set_sysclk = max98095_dai_set_sysclk,
+        .set_fmt = max98095_dai3_set_fmt,
+        .hw_params = max98095_dai3_hw_params,
+};
+
+static struct snd_soc_dai_driver max98095_dai[] = {
+{
+        .name = "HiFi",
+        .playback = {
+                .stream_name = "HiFi Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = MAX98095_RATES,
+                .formats = MAX98095_FORMATS,
+        },
+        .capture = {
+                .stream_name = "HiFi Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = MAX98095_RATES,
+                .formats = MAX98095_FORMATS,
+        },
+         .ops = &max98095_dai1_ops,
+},
+{
+        .name = "Aux",
+        .playback = {
+                .stream_name = "Aux Playback",
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = MAX98095_RATES,
+                .formats = MAX98095_FORMATS,
+        },
+        .ops = &max98095_dai2_ops,
+},
+{
+        .name = "Voice",
+        .playback = {
+                .stream_name = "Voice Playback",
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = MAX98095_RATES,
+                .formats = MAX98095_FORMATS,
+        },
+        .ops = &max98095_dai3_ops,
+}
+
+};
+
+static int max98095_get_eq_channel(const char *name)
+{
+        if (strcmp(name, "EQ1 Mode") == 0)
+                return 0;
+        if (strcmp(name, "EQ2 Mode") == 0)
+                return 1;
+        return -EINVAL;
+}
+
+static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_pdata *pdata = max98095->pdata;
+        int channel = max98095_get_eq_channel(kcontrol->id.name);
+        struct max98095_cdata *cdata;
+        int sel = ucontrol->value.integer.value[0];
+        struct max98095_eq_cfg *coef_set;
+        int fs, best, best_val, i;
+        int regmask, regsave;
+
+        BUG_ON(channel > 1);
+
+        if (!pdata || !max98095->eq_textcnt)
+                return 0;
+
+        if (sel >= pdata->eq_cfgcnt)
+                return -EINVAL;
+
+        cdata = &max98095->dai[channel];
+        cdata->eq_sel = sel;
+        fs = cdata->rate;
+
+        /* Find the selected configuration with nearest sample rate */
+        best = 0;
+        best_val = INT_MAX;
+        for (i = 0; i < pdata->eq_cfgcnt; i++) {
+                if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
+                        abs(pdata->eq_cfg[i].rate - fs) < best_val) {
+                        best = i;
+                        best_val = abs(pdata->eq_cfg[i].rate - fs);
+                }
+        }
+
+        dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
+                pdata->eq_cfg[best].name,
+                pdata->eq_cfg[best].rate, fs);
+
+        coef_set = &pdata->eq_cfg[best];
+
+        regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
+
+        /* Disable filter while configuring, and save current on/off state */
+        regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
+        snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
+
+        mutex_lock(&codec->mutex);
+        snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
+        m98095_eq_band(codec, channel, 0, coef_set->band1);
+        m98095_eq_band(codec, channel, 1, coef_set->band2);
+        m98095_eq_band(codec, channel, 2, coef_set->band3);
+        m98095_eq_band(codec, channel, 3, coef_set->band4);
+        m98095_eq_band(codec, channel, 4, coef_set->band5);
+        snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
+        mutex_unlock(&codec->mutex);
+
+        /* Restore the original on/off state */
+        snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
+        return 0;
+}
+
+static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        int channel = max98095_get_eq_channel(kcontrol->id.name);
+        struct max98095_cdata *cdata;
+
+        cdata = &max98095->dai[channel];
+        ucontrol->value.enumerated.item[0] = cdata->eq_sel;
+
+        return 0;
+}
+
+static void max98095_handle_eq_pdata(struct snd_soc_codec *codec)
+{
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_pdata *pdata = max98095->pdata;
+        struct max98095_eq_cfg *cfg;
+        unsigned int cfgcnt;
+        int i, j;
+        const char **t;
+        int ret;
+
+        struct snd_kcontrol_new controls[] = {
+                SOC_ENUM_EXT("EQ1 Mode",
+                        max98095->eq_enum,
+                        max98095_get_eq_enum,
+                        max98095_put_eq_enum),
+                SOC_ENUM_EXT("EQ2 Mode",
+                        max98095->eq_enum,
+                        max98095_get_eq_enum,
+                        max98095_put_eq_enum),
+        };
+
+        cfg = pdata->eq_cfg;
+        cfgcnt = pdata->eq_cfgcnt;
+
+        /* Setup an array of texts for the equalizer enum.
+         * This is based on Mark Brown's equalizer driver code.
+         */
+        max98095->eq_textcnt = 0;
+        max98095->eq_texts = NULL;
+        for (i = 0; i < cfgcnt; i++) {
+                for (j = 0; j < max98095->eq_textcnt; j++) {
+                        if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
+                                break;
+                }
+
+                if (j != max98095->eq_textcnt)
+                        continue;
+
+                /* Expand the array */
+                t = krealloc(max98095->eq_texts,
+                             sizeof(char *) * (max98095->eq_textcnt + 1),
+                             GFP_KERNEL);
+                if (t == NULL)
+                        continue;
+
+                /* Store the new entry */
+                t[max98095->eq_textcnt] = cfg[i].name;
+                max98095->eq_textcnt++;
+                max98095->eq_texts = t;
+        }
+
+        /* Now point the soc_enum to .texts array items */
+        max98095->eq_enum.texts = max98095->eq_texts;
+        max98095->eq_enum.max = max98095->eq_textcnt;
+
+        ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
+}
+
+static int max98095_get_bq_channel(const char *name)
+{
+        if (strcmp(name, "Biquad1 Mode") == 0)
+                return 0;
+        if (strcmp(name, "Biquad2 Mode") == 0)
+                return 1;
+        return -EINVAL;
+}
+
+static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_pdata *pdata = max98095->pdata;
+        int channel = max98095_get_bq_channel(kcontrol->id.name);
+        struct max98095_cdata *cdata;
+        int sel = ucontrol->value.integer.value[0];
+        struct max98095_biquad_cfg *coef_set;
+        int fs, best, best_val, i;
+        int regmask, regsave;
+
+        BUG_ON(channel > 1);
+
+        if (!pdata || !max98095->bq_textcnt)
+                return 0;
+
+        if (sel >= pdata->bq_cfgcnt)
+                return -EINVAL;
+
+        cdata = &max98095->dai[channel];
+        cdata->bq_sel = sel;
+        fs = cdata->rate;
+
+        /* Find the selected configuration with nearest sample rate */
+        best = 0;
+        best_val = INT_MAX;
+        for (i = 0; i < pdata->bq_cfgcnt; i++) {
+                if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
+                        abs(pdata->bq_cfg[i].rate - fs) < best_val) {
+                        best = i;
+                        best_val = abs(pdata->bq_cfg[i].rate - fs);
+                }
+        }
+
+        dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
+                pdata->bq_cfg[best].name,
+                pdata->bq_cfg[best].rate, fs);
+
+        coef_set = &pdata->bq_cfg[best];
+
+        regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
+
+        /* Disable filter while configuring, and save current on/off state */
+        regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
+        snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
+
+        mutex_lock(&codec->mutex);
+        snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
+        m98095_biquad_band(codec, channel, 0, coef_set->band1);
+        m98095_biquad_band(codec, channel, 1, coef_set->band2);
+        snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
+        mutex_unlock(&codec->mutex);
+
+        /* Restore the original on/off state */
+        snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
+        return 0;
+}
+
+static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        int channel = max98095_get_bq_channel(kcontrol->id.name);
+        struct max98095_cdata *cdata;
+
+        cdata = &max98095->dai[channel];
+        ucontrol->value.enumerated.item[0] = cdata->bq_sel;
+
+        return 0;
+}
+
+static void max98095_handle_bq_pdata(struct snd_soc_codec *codec)
+{
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_pdata *pdata = max98095->pdata;
+        struct max98095_biquad_cfg *cfg;
+        unsigned int cfgcnt;
+        int i, j;
+        const char **t;
+        int ret;
+
+        struct snd_kcontrol_new controls[] = {
+                SOC_ENUM_EXT("Biquad1 Mode",
+                        max98095->bq_enum,
+                        max98095_get_bq_enum,
+                        max98095_put_bq_enum),
+                SOC_ENUM_EXT("Biquad2 Mode",
+                        max98095->bq_enum,
+                        max98095_get_bq_enum,
+                        max98095_put_bq_enum),
+        };
+
+        cfg = pdata->bq_cfg;
+        cfgcnt = pdata->bq_cfgcnt;
+
+        /* Setup an array of texts for the biquad enum.
+         * This is based on Mark Brown's equalizer driver code.
+         */
+        max98095->bq_textcnt = 0;
+        max98095->bq_texts = NULL;
+        for (i = 0; i < cfgcnt; i++) {
+                for (j = 0; j < max98095->bq_textcnt; j++) {
+                        if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
+                                break;
+                }
+
+                if (j != max98095->bq_textcnt)
+                        continue;
+
+                /* Expand the array */
+                t = krealloc(max98095->bq_texts,
+                             sizeof(char *) * (max98095->bq_textcnt + 1),
+                             GFP_KERNEL);
+                if (t == NULL)
+                        continue;
+
+                /* Store the new entry */
+                t[max98095->bq_textcnt] = cfg[i].name;
+                max98095->bq_textcnt++;
+                max98095->bq_texts = t;
+        }
+
+        /* Now point the soc_enum to .texts array items */
+        max98095->bq_enum.texts = max98095->bq_texts;
+        max98095->bq_enum.max = max98095->bq_textcnt;
+
+        ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret);
+}
+
+static void max98095_handle_pdata(struct snd_soc_codec *codec)
+{
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_pdata *pdata = max98095->pdata;
+        u8 regval = 0;
+
+        if (!pdata) {
+                dev_dbg(codec->dev, "No platform data\n");
+                return;
+        }
+
+        /* Configure mic for analog/digital mic mode */
+        if (pdata->digmic_left_mode)
+                regval |= M98095_DIGMIC_L;
+
+        if (pdata->digmic_right_mode)
+                regval |= M98095_DIGMIC_R;
+
+        snd_soc_write(codec, M98095_087_CFG_MIC, regval);
+
+        /* Configure equalizers */
+        if (pdata->eq_cfgcnt)
+                max98095_handle_eq_pdata(codec);
+
+        /* Configure bi-quad filters */
+        if (pdata->bq_cfgcnt)
+                max98095_handle_bq_pdata(codec);
+}
+
+#ifdef CONFIG_PM
+static int max98095_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        return 0;
+}
+
+static int max98095_resume(struct snd_soc_codec *codec)
+{
+        max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        return 0;
+}
+#else
+#define max98095_suspend NULL
+#define max98095_resume NULL
+#endif
+
+static int max98095_reset(struct snd_soc_codec *codec)
+{
+        int i, ret;
+
+        /* Gracefully reset the DSP core and the codec hardware
+         * in a proper sequence */
+        ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
+                return ret;
+        }
+
+        ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
+                return ret;
+        }
+
+        /* Reset to hardware default for registers, as there is not
+         * a soft reset hardware control register */
+        for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
+                ret = snd_soc_write(codec, i, max98095_reg_def[i]);
+                if (ret < 0) {
+                        dev_err(codec->dev, "Failed to reset: %d\n", ret);
+                        return ret;
+                }
+        }
+
+        return ret;
+}
+
+static int max98095_probe(struct snd_soc_codec *codec)
+{
+        struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
+        struct max98095_cdata *cdata;
+        int ret = 0;
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        /* reset the codec, the DSP core, and disable all interrupts */
+        max98095_reset(codec);
+
+        /* initialize private data */
+
+        max98095->sysclk = (unsigned)-1;
+        max98095->eq_textcnt = 0;
+        max98095->bq_textcnt = 0;
+
+        cdata = &max98095->dai[0];
+        cdata->rate = (unsigned)-1;
+        cdata->fmt  = (unsigned)-1;
+        cdata->eq_sel = 0;
+        cdata->bq_sel = 0;
+
+        cdata = &max98095->dai[1];
+        cdata->rate = (unsigned)-1;
+        cdata->fmt  = (unsigned)-1;
+        cdata->eq_sel = 0;
+        cdata->bq_sel = 0;
+
+        cdata = &max98095->dai[2];
+        cdata->rate = (unsigned)-1;
+        cdata->fmt  = (unsigned)-1;
+        cdata->eq_sel = 0;
+        cdata->bq_sel = 0;
+
+        max98095->lin_state = 0;
+        max98095->mic1pre = 0;
+        max98095->mic2pre = 0;
+
+        ret = snd_soc_read(codec, M98095_0FF_REV_ID);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read device revision: %d\n",
+                        ret);
+                goto err_access;
+        }
+        dev_info(codec->dev, "revision %c\n", ret + 'A');
+
+        snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV);
+
+        /* initialize registers cache to hardware default */
+        max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        snd_soc_write(codec, M98095_048_MIX_DAC_LR,
+                M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
+
+        snd_soc_write(codec, M98095_049_MIX_DAC_M,
+                M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
+
+        snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
+        snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL);
+        snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL);
+
+        snd_soc_write(codec, M98095_02C_DAI1_IOCFG,
+                M98095_S1NORMAL|M98095_SDATA);
+
+        snd_soc_write(codec, M98095_036_DAI2_IOCFG,
+                M98095_S2NORMAL|M98095_SDATA);
+
+        snd_soc_write(codec, M98095_040_DAI3_IOCFG,
+                M98095_S3NORMAL|M98095_SDATA);
+
+        max98095_handle_pdata(codec);
+
+        /* take the codec out of the shut down */
+        snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
+                M98095_SHDNRUN);
+
+        max98095_add_widgets(codec);
+
+err_access:
+        return ret;
+}
+
+static int max98095_remove(struct snd_soc_codec *codec)
+{
+        max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
+        .probe   = max98095_probe,
+        .remove  = max98095_remove,
+        .suspend = max98095_suspend,
+        .resume  = max98095_resume,
+        .set_bias_level = max98095_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(max98095_reg_def),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = max98095_reg_def,
+        .readable_register = max98095_readable,
+        .volatile_register = max98095_volatile,
+        .dapm_widgets     = max98095_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
+        .dapm_routes     = max98095_audio_map,
+        .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
+};
+
+static int max98095_i2c_probe(struct i2c_client *i2c,
+                             const struct i2c_device_id *id)
+{
+        struct max98095_priv *max98095;
+        int ret;
+
+        max98095 = kzalloc(sizeof(struct max98095_priv), GFP_KERNEL);
+        if (max98095 == NULL)
+                return -ENOMEM;
+
+        max98095->devtype = id->driver_data;
+        i2c_set_clientdata(i2c, max98095);
+        max98095->control_data = i2c;
+        max98095->pdata = i2c->dev.platform_data;
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_max98095, &max98095_dai[0], 3);
+        if (ret < 0)
+                kfree(max98095);
+        return ret;
+}
+
+static int __devexit max98095_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+
+        return 0;
+}
+
+static const struct i2c_device_id max98095_i2c_id[] = {
+        { "max98095", MAX98095 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
+
+static struct i2c_driver max98095_i2c_driver = {
+        .driver = {
+                .name = "max98095",
+                .owner = THIS_MODULE,
+        },
+        .probe  = max98095_i2c_probe,
+        .remove = __devexit_p(max98095_i2c_remove),
+        .id_table = max98095_i2c_id,
+};
+
+static int __init max98095_init(void)
+{
+        int ret;
+
+        ret = i2c_add_driver(&max98095_i2c_driver);
+        if (ret)
+                pr_err("Failed to register max98095 I2C driver: %d\n", ret);
+
+        return ret;
+}
+module_init(max98095_init);
+
+static void __exit max98095_exit(void)
+{
+        i2c_del_driver(&max98095_i2c_driver);
+}
+module_exit(max98095_exit);
+
+MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
+MODULE_AUTHOR("Peter Hsiang");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max98095.h b/sound/soc/codecs/max98095.h
new file mode 100644
index 000000000000..891584a0eb03
--- /dev/null
+++ b/sound/soc/codecs/max98095.h
@@ -0,0 +1,299 @@
+/*
+ * max98095.h -- MAX98095 ALSA SoC Audio driver
+ *
+ * Copyright 2011 Maxim Integrated Products
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _MAX98095_H
+#define _MAX98095_H
+
+/*
+ * MAX98095 Registers Definition
+ */
+
+#define M98095_000_HOST_DATA                0x00
+#define M98095_001_HOST_INT_STS             0x01
+#define M98095_002_HOST_RSP_STS             0x02
+#define M98095_003_HOST_CMD_STS             0x03
+#define M98095_004_CODEC_STS                0x04
+#define M98095_005_DAI1_ALC_STS             0x05
+#define M98095_006_DAI2_ALC_STS             0x06
+#define M98095_007_JACK_AUTO_STS            0x07
+#define M98095_008_JACK_MANUAL_STS          0x08
+#define M98095_009_JACK_VBAT_STS            0x09
+#define M98095_00A_ACC_ADC_STS              0x0A
+#define M98095_00B_MIC_NG_AGC_STS           0x0B
+#define M98095_00C_SPK_L_VOLT_STS           0x0C
+#define M98095_00D_SPK_R_VOLT_STS           0x0D
+#define M98095_00E_TEMP_SENSOR_STS          0x0E
+#define M98095_00F_HOST_CFG                 0x0F
+#define M98095_010_HOST_INT_CFG             0x10
+#define M98095_011_HOST_INT_EN              0x11
+#define M98095_012_CODEC_INT_EN             0x12
+#define M98095_013_JACK_INT_EN              0x13
+#define M98095_014_JACK_INT_EN              0x14
+#define M98095_015_DEC                      0x15
+#define M98095_016_RESERVED                 0x16
+#define M98095_017_RESERVED                 0x17
+#define M98095_018_KEYCODE3                 0x18
+#define M98095_019_KEYCODE2                 0x19
+#define M98095_01A_KEYCODE1                 0x1A
+#define M98095_01B_KEYCODE0                 0x1B
+#define M98095_01C_OEMCODE1                 0x1C
+#define M98095_01D_OEMCODE0                 0x1D
+#define M98095_01E_XCFG1                    0x1E
+#define M98095_01F_XCFG2                    0x1F
+#define M98095_020_XCFG3                    0x20
+#define M98095_021_XCFG4                    0x21
+#define M98095_022_XCFG5                    0x22
+#define M98095_023_XCFG6                    0x23
+#define M98095_024_XGPIO                    0x24
+#define M98095_025_XCLKCFG                  0x25
+#define M98095_026_SYS_CLK                  0x26
+#define M98095_027_DAI1_CLKMODE             0x27
+#define M98095_028_DAI1_CLKCFG_HI           0x28
+#define M98095_029_DAI1_CLKCFG_LO           0x29
+#define M98095_02A_DAI1_FORMAT              0x2A
+#define M98095_02B_DAI1_CLOCK               0x2B
+#define M98095_02C_DAI1_IOCFG               0x2C
+#define M98095_02D_DAI1_TDM                 0x2D
+#define M98095_02E_DAI1_FILTERS             0x2E
+#define M98095_02F_DAI1_LVL1                0x2F
+#define M98095_030_DAI1_LVL2                0x30
+#define M98095_031_DAI2_CLKMODE             0x31
+#define M98095_032_DAI2_CLKCFG_HI           0x32
+#define M98095_033_DAI2_CLKCFG_LO           0x33
+#define M98095_034_DAI2_FORMAT              0x34
+#define M98095_035_DAI2_CLOCK               0x35
+#define M98095_036_DAI2_IOCFG               0x36
+#define M98095_037_DAI2_TDM                 0x37
+#define M98095_038_DAI2_FILTERS             0x38
+#define M98095_039_DAI2_LVL1                0x39
+#define M98095_03A_DAI2_LVL2                0x3A
+#define M98095_03B_DAI3_CLKMODE             0x3B
+#define M98095_03C_DAI3_CLKCFG_HI           0x3C
+#define M98095_03D_DAI3_CLKCFG_LO           0x3D
+#define M98095_03E_DAI3_FORMAT              0x3E
+#define M98095_03F_DAI3_CLOCK               0x3F
+#define M98095_040_DAI3_IOCFG               0x40
+#define M98095_041_DAI3_TDM                 0x41
+#define M98095_042_DAI3_FILTERS             0x42
+#define M98095_043_DAI3_LVL1                0x43
+#define M98095_044_DAI3_LVL2                0x44
+#define M98095_045_CFG_DSP                  0x45
+#define M98095_046_DAC_CTRL1                0x46
+#define M98095_047_DAC_CTRL2                0x47
+#define M98095_048_MIX_DAC_LR               0x48
+#define M98095_049_MIX_DAC_M                0x49
+#define M98095_04A_MIX_ADC_LEFT             0x4A
+#define M98095_04B_MIX_ADC_RIGHT            0x4B
+#define M98095_04C_MIX_HP_LEFT              0x4C
+#define M98095_04D_MIX_HP_RIGHT             0x4D
+#define M98095_04E_CFG_HP                   0x4E
+#define M98095_04F_MIX_RCV                  0x4F
+#define M98095_050_MIX_SPK_LEFT             0x50
+#define M98095_051_MIX_SPK_RIGHT            0x51
+#define M98095_052_MIX_SPK_CFG              0x52
+#define M98095_053_MIX_LINEOUT1             0x53
+#define M98095_054_MIX_LINEOUT2             0x54
+#define M98095_055_MIX_LINEOUT_CFG          0x55
+#define M98095_056_LVL_SIDETONE_DAI12       0x56
+#define M98095_057_LVL_SIDETONE_DAI3        0x57
+#define M98095_058_LVL_DAI1_PLAY            0x58
+#define M98095_059_LVL_DAI1_EQ              0x59
+#define M98095_05A_LVL_DAI2_PLAY            0x5A
+#define M98095_05B_LVL_DAI2_EQ              0x5B
+#define M98095_05C_LVL_DAI3_PLAY            0x5C
+#define M98095_05D_LVL_ADC_L                0x5D
+#define M98095_05E_LVL_ADC_R                0x5E
+#define M98095_05F_LVL_MIC1                 0x5F
+#define M98095_060_LVL_MIC2                 0x60
+#define M98095_061_LVL_LINEIN               0x61
+#define M98095_062_LVL_LINEOUT1             0x62
+#define M98095_063_LVL_LINEOUT2             0x63
+#define M98095_064_LVL_HP_L                 0x64
+#define M98095_065_LVL_HP_R                 0x65
+#define M98095_066_LVL_RCV                  0x66
+#define M98095_067_LVL_SPK_L                0x67
+#define M98095_068_LVL_SPK_R                0x68
+#define M98095_069_MICAGC_CFG               0x69
+#define M98095_06A_MICAGC_THRESH            0x6A
+#define M98095_06B_SPK_NOISEGATE            0x6B
+#define M98095_06C_DAI1_ALC1_TIME           0x6C
+#define M98095_06D_DAI1_ALC1_COMP           0x6D
+#define M98095_06E_DAI1_ALC1_EXPN           0x6E
+#define M98095_06F_DAI1_ALC1_GAIN           0x6F
+#define M98095_070_DAI1_ALC2_TIME           0x70
+#define M98095_071_DAI1_ALC2_COMP           0x71
+#define M98095_072_DAI1_ALC2_EXPN           0x72
+#define M98095_073_DAI1_ALC2_GAIN           0x73
+#define M98095_074_DAI1_ALC3_TIME           0x74
+#define M98095_075_DAI1_ALC3_COMP           0x75
+#define M98095_076_DAI1_ALC3_EXPN           0x76
+#define M98095_077_DAI1_ALC3_GAIN           0x77
+#define M98095_078_DAI2_ALC1_TIME           0x78
+#define M98095_079_DAI2_ALC1_COMP           0x79
+#define M98095_07A_DAI2_ALC1_EXPN           0x7A
+#define M98095_07B_DAI2_ALC1_GAIN           0x7B
+#define M98095_07C_DAI2_ALC2_TIME           0x7C
+#define M98095_07D_DAI2_ALC2_COMP           0x7D
+#define M98095_07E_DAI2_ALC2_EXPN           0x7E
+#define M98095_07F_DAI2_ALC2_GAIN           0x7F
+#define M98095_080_DAI2_ALC3_TIME           0x80
+#define M98095_081_DAI2_ALC3_COMP           0x81
+#define M98095_082_DAI2_ALC3_EXPN           0x82
+#define M98095_083_DAI2_ALC3_GAIN           0x83
+#define M98095_084_HP_NOISE_GATE            0x84
+#define M98095_085_AUX_ADC                  0x85
+#define M98095_086_CFG_LINE                 0x86
+#define M98095_087_CFG_MIC                  0x87
+#define M98095_088_CFG_LEVEL                0x88
+#define M98095_089_JACK_DET_AUTO            0x89
+#define M98095_08A_JACK_DET_MANUAL          0x8A
+#define M98095_08B_JACK_KEYSCAN_DBC         0x8B
+#define M98095_08C_JACK_KEYSCAN_DLY         0x8C
+#define M98095_08D_JACK_KEY_THRESH          0x8D
+#define M98095_08E_JACK_DC_SLEW             0x8E
+#define M98095_08F_JACK_TEST_CFG            0x8F
+#define M98095_090_PWR_EN_IN                0x90
+#define M98095_091_PWR_EN_OUT               0x91
+#define M98095_092_PWR_EN_OUT               0x92
+#define M98095_093_BIAS_CTRL                0x93
+#define M98095_094_PWR_DAC_21               0x94
+#define M98095_095_PWR_DAC_03               0x95
+#define M98095_096_PWR_DAC_CK               0x96
+#define M98095_097_PWR_SYS                  0x97
+
+#define M98095_0FF_REV_ID                   0xFF
+
+#define M98095_REG_CNT                      (0xFF+1)
+#define M98095_REG_MAX_CACHED               0X97
+
+/* MAX98095 Registers Bit Fields */
+
+/* M98095_00F_HOST_CFG */
+        #define M98095_SEG                      (1<<0)
+        #define M98095_XTEN                     (1<<1)
+        #define M98095_MDLLEN                   (1<<2)
+
+/* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */
+        #define M98095_CLKMODE_MASK             0xFF
+
+/* M98095_02A_DAI1_FORMAT, M98095_034_DAI2_FORMAT, M98095_03E_DAI3_FORMAT */
+        #define M98095_DAI_MAS                  (1<<7)
+        #define M98095_DAI_WCI                  (1<<6)
+        #define M98095_DAI_BCI                  (1<<5)
+        #define M98095_DAI_DLY                  (1<<4)
+        #define M98095_DAI_TDM                  (1<<2)
+        #define M98095_DAI_FSW                  (1<<1)
+        #define M98095_DAI_WS                   (1<<0)
+
+/* M98095_02B_DAI1_CLOCK, M98095_035_DAI2_CLOCK, M98095_03F_DAI3_CLOCK */
+        #define M98095_DAI_BSEL64               (1<<0)
+        #define M98095_DAI_DOSR_DIV2            (0<<5)
+        #define M98095_DAI_DOSR_DIV4            (1<<5)
+
+/* M98095_02C_DAI1_IOCFG, M98095_036_DAI2_IOCFG, M98095_040_DAI3_IOCFG */
+        #define M98095_S1NORMAL                 (1<<6)
+        #define M98095_S2NORMAL                 (2<<6)
+        #define M98095_S3NORMAL                 (3<<6)
+        #define M98095_SDATA                    (3<<0)
+
+/* M98095_02E_DAI1_FILTERS, M98095_038_DAI2_FILTERS, M98095_042_DAI3_FILTERS */
+        #define M98095_DAI_DHF                  (1<<3)
+
+/* M98095_045_DSP_CFG */
+        #define M98095_DSPNORMAL                (5<<4)
+
+/* M98095_048_MIX_DAC_LR */
+        #define M98095_DAI1L_TO_DACR            (1<<7)
+        #define M98095_DAI1R_TO_DACR            (1<<6)
+        #define M98095_DAI2M_TO_DACR            (1<<5)
+        #define M98095_DAI1L_TO_DACL            (1<<3)
+        #define M98095_DAI1R_TO_DACL            (1<<2)
+        #define M98095_DAI2M_TO_DACL            (1<<1)
+        #define M98095_DAI3M_TO_DACL            (1<<0)
+
+/* M98095_049_MIX_DAC_M */
+        #define M98095_DAI1L_TO_DACM            (1<<3)
+        #define M98095_DAI1R_TO_DACM            (1<<2)
+        #define M98095_DAI2M_TO_DACM            (1<<1)
+        #define M98095_DAI3M_TO_DACM            (1<<0)
+
+/* M98095_04E_MIX_HP_CFG */
+        #define M98095_HPNORMAL                 (3<<4)
+
+/* M98095_05F_LVL_MIC1, M98095_060_LVL_MIC2 */
+        #define M98095_MICPRE_MASK              (3<<5)
+        #define M98095_MICPRE_SHIFT             5
+
+/* M98095_064_LVL_HP_L, M98095_065_LVL_HP_R */
+        #define M98095_HP_MUTE                  (1<<7)
+
+/* M98095_066_LVL_RCV */
+        #define M98095_REC_MUTE                 (1<<7)
+
+/* M98095_067_LVL_SPK_L, M98095_068_LVL_SPK_R */
+        #define M98095_SP_MUTE                  (1<<7)
+
+/* M98095_087_CFG_MIC */
+        #define M98095_MICSEL_MASK              (3<<0)
+        #define M98095_DIGMIC_L                 (1<<2)
+        #define M98095_DIGMIC_R                 (1<<3)
+        #define M98095_DIGMIC2L                 (1<<4)
+        #define M98095_DIGMIC2R                 (1<<5)
+
+/* M98095_088_CFG_LEVEL */
+        #define M98095_VSEN                     (1<<6)
+        #define M98095_ZDEN                     (1<<5)
+        #define M98095_BQ2EN                    (1<<3)
+        #define M98095_BQ1EN                    (1<<2)
+        #define M98095_EQ2EN                    (1<<1)
+        #define M98095_EQ1EN                    (1<<0)
+
+/* M98095_090_PWR_EN_IN */
+        #define M98095_INEN                     (1<<7)
+        #define M98095_MB2EN                    (1<<3)
+        #define M98095_MB1EN                    (1<<2)
+        #define M98095_MBEN                     (3<<2)
+        #define M98095_ADREN                    (1<<1)
+        #define M98095_ADLEN                    (1<<0)
+
+/* M98095_091_PWR_EN_OUT */
+        #define M98095_HPLEN                    (1<<7)
+        #define M98095_HPREN                    (1<<6)
+        #define M98095_SPLEN                    (1<<5)
+        #define M98095_SPREN                    (1<<4)
+        #define M98095_RECEN                    (1<<3)
+        #define M98095_DALEN                    (1<<1)
+        #define M98095_DAREN                    (1<<0)
+
+/* M98095_092_PWR_EN_OUT */
+        #define M98095_SPK_FIXEDSPECTRUM        (0<<4)
+        #define M98095_SPK_SPREADSPECTRUM       (1<<4)
+
+/* M98095_097_PWR_SYS */
+        #define M98095_SHDNRUN                  (1<<7)
+        #define M98095_PERFMODE                 (1<<3)
+        #define M98095_HPPLYBACK                (1<<2)
+        #define M98095_PWRSV8K                  (1<<1)
+        #define M98095_PWRSV                    (1<<0)
+
+#define M98095_COEFS_PER_BAND            5
+
+#define M98095_BYTE1(w) ((w >> 8) & 0xff)
+#define M98095_BYTE0(w) (w & 0xff)
+
+/* Equalizer filter coefficients */
+#define M98095_110_DAI1_EQ_BASE             0x10
+#define M98095_142_DAI2_EQ_BASE             0x42
+
+/* Biquad filter coefficients */
+#define M98095_174_DAI1_BQ_BASE             0x74
+#define M98095_17E_DAI2_BQ_BASE             0x7E
+
+#endif
diff --git a/sound/soc/codecs/max9850.c b/sound/soc/codecs/max9850.c
new file mode 100644
index 000000000000..208d2ee61855
--- /dev/null
+++ b/sound/soc/codecs/max9850.c
@@ -0,0 +1,389 @@
+/*
+ * max9850.c  --  codec driver for max9850
+ *
+ * Copyright (C) 2011 taskit GmbH
+ *
+ * Author: Christian Glindkamp <christian.glindkamp@taskit.de>
+ *
+ * Initial development of this code was funded by
+ * MICRONIC Computer Systeme GmbH, http://www.mcsberlin.de/
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+
+#include "max9850.h"
+
+struct max9850_priv {
+        unsigned int sysclk;
+};
+
+/* max9850 register cache */
+static const u8 max9850_reg[MAX9850_CACHEREGNUM] = {
+        0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* these registers are not used at the moment but provided for the sake of
+ * completeness */
+static int max9850_volatile_register(struct snd_soc_codec *codec,
+                unsigned int reg)
+{
+        switch (reg) {
+        case MAX9850_STATUSA:
+        case MAX9850_STATUSB:
+                return 1;
+        default:
+                return 0;
+        }
+}
+
+static const unsigned int max9850_tlv[] = {
+        TLV_DB_RANGE_HEAD(4),
+        0x18, 0x1f, TLV_DB_SCALE_ITEM(-7450, 400, 0),
+        0x20, 0x33, TLV_DB_SCALE_ITEM(-4150, 200, 0),
+        0x34, 0x37, TLV_DB_SCALE_ITEM(-150, 100, 0),
+        0x38, 0x3f, TLV_DB_SCALE_ITEM(250, 50, 0),
+};
+
+static const struct snd_kcontrol_new max9850_controls[] = {
+SOC_SINGLE_TLV("Headphone Volume", MAX9850_VOLUME, 0, 0x3f, 1, max9850_tlv),
+SOC_SINGLE("Headphone Switch", MAX9850_VOLUME, 7, 1, 1),
+SOC_SINGLE("Mono Switch", MAX9850_GENERAL_PURPOSE, 2, 1, 0),
+};
+
+static const struct snd_kcontrol_new max9850_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Line In Switch", MAX9850_ENABLE, 1, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget max9850_dapm_widgets[] = {
+SND_SOC_DAPM_SUPPLY("Charge Pump 1", MAX9850_ENABLE, 4, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("Charge Pump 2", MAX9850_ENABLE, 5, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("MCLK", MAX9850_ENABLE, 6, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("SHDN", MAX9850_ENABLE, 7, 0, NULL, 0),
+SND_SOC_DAPM_MIXER_NAMED_CTL("Output Mixer", MAX9850_ENABLE, 2, 0,
+                &max9850_mixer_controls[0],
+                ARRAY_SIZE(max9850_mixer_controls)),
+SND_SOC_DAPM_PGA("Headphone Output", MAX9850_ENABLE, 3, 0, NULL, 0),
+SND_SOC_DAPM_DAC("DAC", "HiFi Playback", MAX9850_ENABLE, 0, 0),
+SND_SOC_DAPM_OUTPUT("OUTL"),
+SND_SOC_DAPM_OUTPUT("HPL"),
+SND_SOC_DAPM_OUTPUT("OUTR"),
+SND_SOC_DAPM_OUTPUT("HPR"),
+SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_INPUT("INL"),
+SND_SOC_DAPM_INPUT("INR"),
+};
+
+static const struct snd_soc_dapm_route intercon[] = {
+        /* output mixer */
+        {"Output Mixer", NULL, "DAC"},
+        {"Output Mixer", "Line In Switch", "Line Input"},
+
+        /* outputs */
+        {"Headphone Output", NULL, "Output Mixer"},
+        {"HPL", NULL, "Headphone Output"},
+        {"HPR", NULL, "Headphone Output"},
+        {"OUTL", NULL, "Output Mixer"},
+        {"OUTR", NULL, "Output Mixer"},
+
+        /* inputs */
+        {"Line Input", NULL, "INL"},
+        {"Line Input", NULL, "INR"},
+
+        /* supplies */
+        {"Output Mixer", NULL, "Charge Pump 1"},
+        {"Output Mixer", NULL, "Charge Pump 2"},
+        {"Output Mixer", NULL, "SHDN"},
+        {"DAC", NULL, "MCLK"},
+};
+
+static int max9850_hw_params(struct snd_pcm_substream *substream,
+                             struct snd_pcm_hw_params *params,
+                             struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct max9850_priv *max9850 = snd_soc_codec_get_drvdata(codec);
+        u64 lrclk_div;
+        u8 sf, da;
+
+        if (!max9850->sysclk)
+                return -EINVAL;
+
+        /* lrclk_div = 2^22 * rate / iclk with iclk = mclk / sf */
+        sf = (snd_soc_read(codec, MAX9850_CLOCK) >> 2) + 1;
+        lrclk_div = (1 << 22);
+        lrclk_div *= params_rate(params);
+        lrclk_div *= sf;
+        do_div(lrclk_div, max9850->sysclk);
+
+        snd_soc_write(codec, MAX9850_LRCLK_MSB, (lrclk_div >> 8) & 0x7f);
+        snd_soc_write(codec, MAX9850_LRCLK_LSB, lrclk_div & 0xff);
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                da = 0;
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                da = 0x2;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                da = 0x3;
+                break;
+        default:
+                return -EINVAL;
+        }
+        snd_soc_update_bits(codec, MAX9850_DIGITAL_AUDIO, 0x3, da);
+
+        return 0;
+}
+
+static int max9850_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct max9850_priv *max9850 = snd_soc_codec_get_drvdata(codec);
+
+        /* calculate mclk -> iclk divider */
+        if (freq <= 13000000)
+                snd_soc_write(codec, MAX9850_CLOCK, 0x0);
+        else if (freq <= 26000000)
+                snd_soc_write(codec, MAX9850_CLOCK, 0x4);
+        else if (freq <= 40000000)
+                snd_soc_write(codec, MAX9850_CLOCK, 0x8);
+        else
+                return -EINVAL;
+
+        max9850->sysclk = freq;
+        return 0;
+}
+
+static int max9850_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        u8 da = 0;
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                da |= MAX9850_MASTER;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* interface format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                da |= MAX9850_DLY;
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                da |= MAX9850_RTJ;
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* clock inversion */
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_IF:
+                da |= MAX9850_BCINV | MAX9850_INV;
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                da |= MAX9850_BCINV;
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                da |= MAX9850_INV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* set da */
+        snd_soc_write(codec, MAX9850_DIGITAL_AUDIO, da);
+
+        return 0;
+}
+
+static int max9850_set_bias_level(struct snd_soc_codec *codec,
+                                  enum snd_soc_bias_level level)
+{
+        int ret;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+        case SND_SOC_BIAS_PREPARE:
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = snd_soc_cache_sync(codec);
+                        if (ret) {
+                                dev_err(codec->dev,
+                                        "Failed to sync cache: %d\n", ret);
+                                return ret;
+                        }
+                }
+                break;
+        case SND_SOC_BIAS_OFF:
+                break;
+        }
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#define MAX9850_RATES SNDRV_PCM_RATE_8000_48000
+
+#define MAX9850_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+        SNDRV_PCM_FMTBIT_S24_LE)
+
+static struct snd_soc_dai_ops max9850_dai_ops = {
+        .hw_params      = max9850_hw_params,
+        .set_sysclk     = max9850_set_dai_sysclk,
+        .set_fmt        = max9850_set_dai_fmt,
+};
+
+static struct snd_soc_dai_driver max9850_dai = {
+        .name = "max9850-hifi",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = MAX9850_RATES,
+                .formats = MAX9850_FORMATS
+        },
+        .ops = &max9850_dai_ops,
+};
+
+#ifdef CONFIG_PM
+static int max9850_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        max9850_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        return 0;
+}
+
+static int max9850_resume(struct snd_soc_codec *codec)
+{
+        max9850_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        return 0;
+}
+#else
+#define max9850_suspend NULL
+#define max9850_resume NULL
+#endif
+
+static int max9850_probe(struct snd_soc_codec *codec)
+{
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret;
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        /* enable zero-detect */
+        snd_soc_update_bits(codec, MAX9850_GENERAL_PURPOSE, 1, 1);
+        /* enable slew-rate control */
+        snd_soc_update_bits(codec, MAX9850_VOLUME, 0x40, 0x40);
+        /* set slew-rate 125ms */
+        snd_soc_update_bits(codec, MAX9850_CHARGE_PUMP, 0xff, 0xc0);
+
+        snd_soc_dapm_new_controls(dapm, max9850_dapm_widgets,
+                                  ARRAY_SIZE(max9850_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
+
+        snd_soc_add_controls(codec, max9850_controls,
+                        ARRAY_SIZE(max9850_controls));
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_max9850 = {
+        .probe =        max9850_probe,
+        .suspend =      max9850_suspend,
+        .resume =       max9850_resume,
+        .set_bias_level = max9850_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(max9850_reg),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = max9850_reg,
+        .volatile_register = max9850_volatile_register,
+};
+
+static int __devinit max9850_i2c_probe(struct i2c_client *i2c,
+                const struct i2c_device_id *id)
+{
+        struct max9850_priv *max9850;
+        int ret;
+
+        max9850 = kzalloc(sizeof(struct max9850_priv), GFP_KERNEL);
+        if (max9850 == NULL)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, max9850);
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_max9850, &max9850_dai, 1);
+        if (ret < 0)
+                kfree(max9850);
+        return ret;
+}
+
+static __devexit int max9850_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id max9850_i2c_id[] = {
+        { "max9850", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, max9850_i2c_id);
+
+static struct i2c_driver max9850_i2c_driver = {
+        .driver = {
+                .name = "max9850",
+                .owner = THIS_MODULE,
+        },
+        .probe = max9850_i2c_probe,
+        .remove = __devexit_p(max9850_i2c_remove),
+        .id_table = max9850_i2c_id,
+};
+
+static int __init max9850_init(void)
+{
+        return i2c_add_driver(&max9850_i2c_driver);
+}
+module_init(max9850_init);
+
+static void __exit max9850_exit(void)
+{
+        i2c_del_driver(&max9850_i2c_driver);
+}
+module_exit(max9850_exit);
+
+MODULE_AUTHOR("Christian Glindkamp <christian.glindkamp@taskit.de>");
+MODULE_DESCRIPTION("ASoC MAX9850 codec driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max9850.h b/sound/soc/codecs/max9850.h
new file mode 100644
index 000000000000..72b1ddb04b0d
--- /dev/null
+++ b/sound/soc/codecs/max9850.h
@@ -0,0 +1,38 @@
+/*
+ * max9850.h  --  codec driver for max9850
+ *
+ * Copyright (C) 2011 taskit GmbH
+ * Author: Christian Glindkamp <christian.glindkamp@taskit.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef _MAX9850_H
+#define _MAX9850_H
+
+#define MAX9850_STATUSA                 0x00
+#define MAX9850_STATUSB                 0x01
+#define MAX9850_VOLUME                  0x02
+#define MAX9850_GENERAL_PURPOSE         0x03
+#define MAX9850_INTERRUPT               0x04
+#define MAX9850_ENABLE                  0x05
+#define MAX9850_CLOCK                   0x06
+#define MAX9850_CHARGE_PUMP             0x07
+#define MAX9850_LRCLK_MSB               0x08
+#define MAX9850_LRCLK_LSB               0x09
+#define MAX9850_DIGITAL_AUDIO           0x0a
+
+#define MAX9850_CACHEREGNUM 11
+
+/* MAX9850_DIGITAL_AUDIO */
+#define MAX9850_MASTER                  (1<<7)
+#define MAX9850_INV                     (1<<6)
+#define MAX9850_BCINV                   (1<<5)
+#define MAX9850_DLY                     (1<<3)
+#define MAX9850_RTJ                     (1<<2)
+
+#endif
diff --git a/sound/soc/codecs/pcm3008.c b/sound/soc/codecs/pcm3008.c
index 5a5f187a2657..bd8f26e41602 100644
--- a/sound/soc/codecs/pcm3008.c
+++ b/sound/soc/codecs/pcm3008.c
@@ -32,8 +32,8 @@
 #define PCM3008_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |    \
                        SNDRV_PCM_RATE_48000)
 
-struct snd_soc_dai pcm3008_dai = {
-        .name = "PCM3008 HiFi",
+static struct snd_soc_dai_driver pcm3008_dai = {
+        .name = "pcm3008-hifi",
         .playback = {
                 .stream_name = "PCM3008 Playback",
                 .channels_min = 1,
@@ -49,7 +49,6 @@ struct snd_soc_dai pcm3008_dai = {
                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
         },
 };
-EXPORT_SYMBOL_GPL(pcm3008_dai);
 
 static void pcm3008_gpio_free(struct pcm3008_setup_data *setup)
 {
@@ -59,38 +58,13 @@ static void pcm3008_gpio_free(struct pcm3008_setup_data *setup)
         gpio_free(setup->pdda_pin);
 }
 
-static int pcm3008_soc_probe(struct platform_device *pdev)
+static int pcm3008_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        struct pcm3008_setup_data *setup = socdev->codec_data;
+        struct pcm3008_setup_data *setup = codec->dev->platform_data;
         int ret = 0;
 
         printk(KERN_INFO "PCM3008 SoC Audio Codec %s\n", PCM3008_VERSION);
 
-        socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (!socdev->card->codec)
-                return -ENOMEM;
-
-        codec = socdev->card->codec;
-        mutex_init(&codec->mutex);
-
-        codec->name = "PCM3008";
-        codec->owner = THIS_MODULE;
-        codec->dai = &pcm3008_dai;
-        codec->num_dai = 1;
-        codec->write = NULL;
-        codec->read = NULL;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        /* Register PCMs. */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "pcm3008: failed to create pcms\n");
-                goto pcm_err;
-        }
-
         /* DEM1  DEM0  DE-EMPHASIS_MODE
          * Low   Low   De-emphasis 44.1 kHz ON
          * Low   High  De-emphasis OFF
@@ -130,33 +104,22 @@ static int pcm3008_soc_probe(struct platform_device *pdev)
 
 gpio_err:
         pcm3008_gpio_free(setup);
-pcm_err:
-        kfree(socdev->card->codec);
 
         return ret;
 }
 
-static int pcm3008_soc_remove(struct platform_device *pdev)
+static int pcm3008_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-        struct pcm3008_setup_data *setup = socdev->codec_data;
-
-        if (!codec)
-                return 0;
+        struct pcm3008_setup_data *setup = codec->dev->platform_data;
 
         pcm3008_gpio_free(setup);
-        snd_soc_free_pcms(socdev);
-        kfree(socdev->card->codec);
-
         return 0;
 }
 
 #ifdef CONFIG_PM
-static int pcm3008_soc_suspend(struct platform_device *pdev, pm_message_t msg)
+static int pcm3008_soc_suspend(struct snd_soc_codec *codec, pm_message_t msg)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct pcm3008_setup_data *setup = socdev->codec_data;
+        struct pcm3008_setup_data *setup = codec->dev->platform_data;
 
         gpio_set_value(setup->pdad_pin, 0);
         gpio_set_value(setup->pdda_pin, 0);
@@ -164,10 +127,9 @@ static int pcm3008_soc_suspend(struct platform_device *pdev, pm_message_t msg)
         return 0;
 }
 
-static int pcm3008_soc_resume(struct platform_device *pdev)
+static int pcm3008_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct pcm3008_setup_data *setup = socdev->codec_data;
+        struct pcm3008_setup_data *setup = codec->dev->platform_data;
 
         gpio_set_value(setup->pdad_pin, 1);
         gpio_set_value(setup->pdda_pin, 1);
@@ -179,23 +141,45 @@ static int pcm3008_soc_resume(struct platform_device *pdev)
 #define pcm3008_soc_resume NULL
 #endif
 
-struct snd_soc_codec_device soc_codec_dev_pcm3008 = {
+static struct snd_soc_codec_driver soc_codec_dev_pcm3008 = {
         .probe =        pcm3008_soc_probe,
         .remove =       pcm3008_soc_remove,
         .suspend =      pcm3008_soc_suspend,
         .resume =       pcm3008_soc_resume,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_pcm3008);
 
-static int __init pcm3008_init(void)
+static int __devinit pcm3008_codec_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_pcm3008, &pcm3008_dai, 1);
+}
+
+static int __devexit pcm3008_codec_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+MODULE_ALIAS("platform:pcm3008-codec");
+
+static struct platform_driver pcm3008_codec_driver = {
+        .probe          = pcm3008_codec_probe,
+        .remove         = __devexit_p(pcm3008_codec_remove),
+        .driver         = {
+                .name   = "pcm3008-codec",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init pcm3008_modinit(void)
 {
-        return snd_soc_register_dai(&pcm3008_dai);
+        return platform_driver_register(&pcm3008_codec_driver);
 }
-module_init(pcm3008_init);
+module_init(pcm3008_modinit);
 
 static void __exit pcm3008_exit(void)
 {
-        snd_soc_unregister_dai(&pcm3008_dai);
+        platform_driver_unregister(&pcm3008_codec_driver);
 }
 module_exit(pcm3008_exit);
 
diff --git a/sound/soc/codecs/pcm3008.h b/sound/soc/codecs/pcm3008.h
index d04e87d3c060..7e5489ab4812 100644
--- a/sound/soc/codecs/pcm3008.h
+++ b/sound/soc/codecs/pcm3008.h
@@ -19,7 +19,4 @@ struct pcm3008_setup_data {
         unsigned pdda_pin;
 };
 
-extern struct snd_soc_codec_device soc_codec_dev_pcm3008;
-extern struct snd_soc_dai pcm3008_dai;
-
 #endif
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
new file mode 100644
index 000000000000..ff29380c9ed3
--- /dev/null
+++ b/sound/soc/codecs/sgtl5000.c
@@ -0,0 +1,1527 @@
+/*
+ * sgtl5000.c  --  SGTL5000 ALSA SoC Audio driver
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+#include <sound/core.h>
+#include <sound/tlv.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+
+#include "sgtl5000.h"
+
+#define SGTL5000_DAP_REG_OFFSET 0x0100
+#define SGTL5000_MAX_REG_OFFSET 0x013A
+
+/* default value of sgtl5000 registers except DAP */
+static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] =  {
+        0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */
+        0x0000, /* 0x0002, CHIP_DIG_POWER. */
+        0x0008, /* 0x0004, CHIP_CKL_CTRL */
+        0x0010, /* 0x0006, CHIP_I2S_CTRL */
+        0x0000, /* 0x0008, reserved */
+        0x0008, /* 0x000A, CHIP_SSS_CTRL */
+        0x0000, /* 0x000C, reserved */
+        0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */
+        0x3c3c, /* 0x0010, CHIP_DAC_VOL */
+        0x0000, /* 0x0012, reserved */
+        0x015f, /* 0x0014, CHIP_PAD_STRENGTH */
+        0x0000, /* 0x0016, reserved */
+        0x0000, /* 0x0018, reserved */
+        0x0000, /* 0x001A, reserved */
+        0x0000, /* 0x001E, reserved */
+        0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */
+        0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */
+        0x0111, /* 0x0024, CHIP_ANN_CTRL */
+        0x0000, /* 0x0026, CHIP_LINREG_CTRL */
+        0x0000, /* 0x0028, CHIP_REF_CTRL */
+        0x0000, /* 0x002A, CHIP_MIC_CTRL */
+        0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */
+        0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */
+        0x7060, /* 0x0030, CHIP_ANA_POWER */
+        0x5000, /* 0x0032, CHIP_PLL_CTRL */
+        0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */
+        0x0000, /* 0x0036, CHIP_ANA_STATUS */
+        0x0000, /* 0x0038, reserved */
+        0x0000, /* 0x003A, CHIP_ANA_TEST2 */
+        0x0000, /* 0x003C, CHIP_SHORT_CTRL */
+        0x0000, /* reserved */
+};
+
+/* default value of dap registers */
+static const u16 sgtl5000_dap_regs[] = {
+        0x0000, /* 0x0100, DAP_CONTROL */
+        0x0000, /* 0x0102, DAP_PEQ */
+        0x0040, /* 0x0104, DAP_BASS_ENHANCE */
+        0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */
+        0x0000, /* 0x0108, DAP_AUDIO_EQ */
+        0x0040, /* 0x010A, DAP_SGTL_SURROUND */
+        0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */
+        0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */
+        0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */
+        0x0000, /* 0x0112, reserved */
+        0x0000, /* 0x0114, reserved */
+        0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */
+        0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */
+        0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */
+        0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */
+        0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */
+        0x8000, /* 0x0120, DAP_MAIN_CHAN */
+        0x0000, /* 0x0122, DAP_MIX_CHAN */
+        0x0510, /* 0x0124, DAP_AVC_CTRL */
+        0x1473, /* 0x0126, DAP_AVC_THRESHOLD */
+        0x0028, /* 0x0128, DAP_AVC_ATTACK */
+        0x0050, /* 0x012A, DAP_AVC_DECAY */
+        0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */
+        0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */
+        0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */
+        0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */
+        0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */
+        0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */
+        0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */
+        0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */
+};
+
+/* regulator supplies for sgtl5000, VDDD is an optional external supply */
+enum sgtl5000_regulator_supplies {
+        VDDA,
+        VDDIO,
+        VDDD,
+        SGTL5000_SUPPLY_NUM
+};
+
+/* vddd is optional supply */
+static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
+        "VDDA",
+        "VDDIO",
+        "VDDD"
+};
+
+#define LDO_CONSUMER_NAME       "VDDD_LDO"
+#define LDO_VOLTAGE             1200000
+
+static struct regulator_consumer_supply ldo_consumer[] = {
+        REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
+};
+
+static struct regulator_init_data ldo_init_data = {
+        .constraints = {
+                .min_uV                 = 850000,
+                .max_uV                 = 1600000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &ldo_consumer[0],
+};
+
+/*
+ * sgtl5000 internal ldo regulator,
+ * enabled when VDDD not provided
+ */
+struct ldo_regulator {
+        struct regulator_desc desc;
+        struct regulator_dev *dev;
+        int voltage;
+        void *codec_data;
+        bool enabled;
+};
+
+/* sgtl5000 private structure in codec */
+struct sgtl5000_priv {
+        int sysclk;     /* sysclk rate */
+        int master;     /* i2s master or not */
+        int fmt;        /* i2s data format */
+        struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
+        struct ldo_regulator *ldo;
+};
+
+/*
+ * mic_bias power on/off share the same register bits with
+ * output impedance of mic bias, when power on mic bias, we
+ * need reclaim it to impedance value.
+ * 0x0 = Powered off
+ * 0x1 = 2Kohm
+ * 0x2 = 4Kohm
+ * 0x3 = 8Kohm
+ */
+static int mic_bias_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                /* change mic bias resistor to 4Kohm */
+                snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
+                                SGTL5000_BIAS_R_4k, SGTL5000_BIAS_R_4k);
+                break;
+
+        case SND_SOC_DAPM_PRE_PMD:
+                /*
+                 * SGTL5000_BIAS_R_8k as mask to clean the two bits
+                 * of mic bias and output impedance
+                 */
+                snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
+                                SGTL5000_BIAS_R_8k, 0);
+                break;
+        }
+        return 0;
+}
+
+/*
+ * using codec assist to small pop, hp_powerup or lineout_powerup
+ * should stay setting until vag_powerup is fully ramped down,
+ * vag fully ramped down require 400ms.
+ */
+static int small_pop_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
+                        SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
+                break;
+
+        case SND_SOC_DAPM_PRE_PMD:
+                snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
+                        SGTL5000_VAG_POWERUP, 0);
+                msleep(400);
+                break;
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+/* input sources for ADC */
+static const char *adc_mux_text[] = {
+        "MIC_IN", "LINE_IN"
+};
+
+static const struct soc_enum adc_enum =
+SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
+
+static const struct snd_kcontrol_new adc_mux =
+SOC_DAPM_ENUM("Capture Mux", adc_enum);
+
+/* input sources for DAC */
+static const char *dac_mux_text[] = {
+        "DAC", "LINE_IN"
+};
+
+static const struct soc_enum dac_enum =
+SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
+
+static const struct snd_kcontrol_new dac_mux =
+SOC_DAPM_ENUM("Headphone Mux", dac_enum);
+
+static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
+        SND_SOC_DAPM_INPUT("LINE_IN"),
+        SND_SOC_DAPM_INPUT("MIC_IN"),
+
+        SND_SOC_DAPM_OUTPUT("HP_OUT"),
+        SND_SOC_DAPM_OUTPUT("LINE_OUT"),
+
+        SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
+                                mic_bias_event,
+                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+        SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
+                        small_pop_event,
+                        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+        SND_SOC_DAPM_PGA_E("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0,
+                        small_pop_event,
+                        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+
+        SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
+        SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
+
+        /* aif for i2s input */
+        SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
+                                0, SGTL5000_CHIP_DIG_POWER,
+                                0, 0),
+
+        /* aif for i2s output */
+        SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
+                                0, SGTL5000_CHIP_DIG_POWER,
+                                1, 0),
+
+        SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
+
+        SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
+};
+
+/* routes for sgtl5000 */
+static const struct snd_soc_dapm_route audio_map[] = {
+        {"Capture Mux", "LINE_IN", "LINE_IN"},  /* line_in --> adc_mux */
+        {"Capture Mux", "MIC_IN", "MIC_IN"},    /* mic_in --> adc_mux */
+
+        {"ADC", NULL, "Capture Mux"},           /* adc_mux --> adc */
+        {"AIFOUT", NULL, "ADC"},                /* adc --> i2s_out */
+
+        {"DAC", NULL, "AIFIN"},                 /* i2s-->dac,skip audio mux */
+        {"Headphone Mux", "DAC", "DAC"},        /* dac --> hp_mux */
+        {"LO", NULL, "DAC"},                    /* dac --> line_out */
+
+        {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
+        {"HP", NULL, "Headphone Mux"},          /* hp_mux --> hp */
+
+        {"LINE_OUT", NULL, "LO"},
+        {"HP_OUT", NULL, "HP"},
+};
+
+/* custom function to fetch info of PCM playback volume */
+static int dac_info_volsw(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+        uinfo->count = 2;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 0xfc - 0x3c;
+        return 0;
+}
+
+/*
+ * custom function to get of PCM playback volume
+ *
+ * dac volume register
+ * 15-------------8-7--------------0
+ * | R channel vol | L channel vol |
+ *  -------------------------------
+ *
+ * PCM volume with 0.5017 dB steps from 0 to -90 dB
+ *
+ * register values map to dB
+ * 0x3B and less = Reserved
+ * 0x3C = 0 dB
+ * 0x3D = -0.5 dB
+ * 0xF0 = -90 dB
+ * 0xFC and greater = Muted
+ *
+ * register value map to userspace value
+ *
+ * register value       0x3c(0dB)         0xf0(-90dB)0xfc
+ *                      ------------------------------
+ * userspace value      0xc0                         0
+ */
+static int dac_get_volsw(struct snd_kcontrol *kcontrol,
+                         struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        int reg;
+        int l;
+        int r;
+
+        reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
+
+        /* get left channel volume */
+        l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
+
+        /* get right channel volume */
+        r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
+
+        /* make sure value fall in (0x3c,0xfc) */
+        l = clamp(l, 0x3c, 0xfc);
+        r = clamp(r, 0x3c, 0xfc);
+
+        /* invert it and map to userspace value */
+        l = 0xfc - l;
+        r = 0xfc - r;
+
+        ucontrol->value.integer.value[0] = l;
+        ucontrol->value.integer.value[1] = r;
+
+        return 0;
+}
+
+/*
+ * custom function to put of PCM playback volume
+ *
+ * dac volume register
+ * 15-------------8-7--------------0
+ * | R channel vol | L channel vol |
+ *  -------------------------------
+ *
+ * PCM volume with 0.5017 dB steps from 0 to -90 dB
+ *
+ * register values map to dB
+ * 0x3B and less = Reserved
+ * 0x3C = 0 dB
+ * 0x3D = -0.5 dB
+ * 0xF0 = -90 dB
+ * 0xFC and greater = Muted
+ *
+ * userspace value map to register value
+ *
+ * userspace value      0xc0                         0
+ *                      ------------------------------
+ * register value       0x3c(0dB)       0xf0(-90dB)0xfc
+ */
+static int dac_put_volsw(struct snd_kcontrol *kcontrol,
+                         struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        int reg;
+        int l;
+        int r;
+
+        l = ucontrol->value.integer.value[0];
+        r = ucontrol->value.integer.value[1];
+
+        /* make sure userspace volume fall in (0, 0xfc-0x3c) */
+        l = clamp(l, 0, 0xfc - 0x3c);
+        r = clamp(r, 0, 0xfc - 0x3c);
+
+        /* invert it, get the value can be set to register */
+        l = 0xfc - l;
+        r = 0xfc - r;
+
+        /* shift to get the register value */
+        reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
+                r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
+
+        snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
+
+        return 0;
+}
+
+static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
+
+/* tlv for mic gain, 0db 20db 30db 40db */
+static const unsigned int mic_gain_tlv[] = {
+        TLV_DB_RANGE_HEAD(4),
+        0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+        1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
+};
+
+/* tlv for hp volume, -51.5db to 12.0db, step .5db */
+static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
+
+static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
+        /* SOC_DOUBLE_S8_TLV with invert */
+        {
+                .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+                .name = "PCM Playback Volume",
+                .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
+                        SNDRV_CTL_ELEM_ACCESS_READWRITE,
+                .info = dac_info_volsw,
+                .get = dac_get_volsw,
+                .put = dac_put_volsw,
+        },
+
+        SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
+        SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
+                        SGTL5000_CHIP_ANA_ADC_CTRL,
+                        8, 2, 0, capture_6db_attenuate),
+        SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
+
+        SOC_DOUBLE_TLV("Headphone Playback Volume",
+                        SGTL5000_CHIP_ANA_HP_CTRL,
+                        0, 8,
+                        0x7f, 1,
+                        headphone_volume),
+        SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
+                        5, 1, 0),
+
+        SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
+                        0, 4, 0, mic_gain_tlv),
+};
+
+/* mute the codec used by alsa core */
+static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
+
+        snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
+                        adcdac_ctrl, mute ? adcdac_ctrl : 0);
+
+        return 0;
+}
+
+/* set codec format */
+static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+        u16 i2sctl = 0;
+
+        sgtl5000->master = 0;
+        /*
+         * i2s clock and frame master setting.
+         * ONLY support:
+         *  - clock and frame slave,
+         *  - clock and frame master
+         */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBS_CFS:
+                break;
+        case SND_SOC_DAIFMT_CBM_CFM:
+                i2sctl |= SGTL5000_I2S_MASTER;
+                sgtl5000->master = 1;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* setting i2s data format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_DSP_A:
+                i2sctl |= SGTL5000_I2S_MODE_PCM;
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                i2sctl |= SGTL5000_I2S_MODE_PCM;
+                i2sctl |= SGTL5000_I2S_LRALIGN;
+                break;
+        case SND_SOC_DAIFMT_I2S:
+                i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                i2sctl |= SGTL5000_I2S_MODE_RJ;
+                i2sctl |= SGTL5000_I2S_LRPOL;
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
+                i2sctl |= SGTL5000_I2S_LRALIGN;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
+
+        /* Clock inversion */
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                i2sctl |= SGTL5000_I2S_SCLK_INV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
+
+        return 0;
+}
+
+/* set codec sysclk */
+static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                                   int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+
+        switch (clk_id) {
+        case SGTL5000_SYSCLK:
+                sgtl5000->sysclk = freq;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+/*
+ * set clock according to i2s frame clock,
+ * sgtl5000 provide 2 clock sources.
+ * 1. sys_mclk. sample freq can only configure to
+ *      1/256, 1/384, 1/512 of sys_mclk.
+ * 2. pll. can derive any audio clocks.
+ *
+ * clock setting rules:
+ * 1. in slave mode, only sys_mclk can use.
+ * 2. as constraint by sys_mclk, sample freq should
+ *      set to 32k, 44.1k and above.
+ * 3. using sys_mclk prefer to pll to save power.
+ */
+static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
+{
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+        int clk_ctl = 0;
+        int sys_fs;     /* sample freq */
+
+        /*
+         * sample freq should be divided by frame clock,
+         * if frame clock lower than 44.1khz, sample feq should set to
+         * 32khz or 44.1khz.
+         */
+        switch (frame_rate) {
+        case 8000:
+        case 16000:
+                sys_fs = 32000;
+                break;
+        case 11025:
+        case 22050:
+                sys_fs = 44100;
+                break;
+        default:
+                sys_fs = frame_rate;
+                break;
+        }
+
+        /* set divided factor of frame clock */
+        switch (sys_fs / frame_rate) {
+        case 4:
+                clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
+                break;
+        case 2:
+                clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
+                break;
+        case 1:
+                clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* set the sys_fs according to frame rate */
+        switch (sys_fs) {
+        case 32000:
+                clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
+                break;
+        case 44100:
+                clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
+                break;
+        case 48000:
+                clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
+                break;
+        case 96000:
+                clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
+                break;
+        default:
+                dev_err(codec->dev, "frame rate %d not supported\n",
+                        frame_rate);
+                return -EINVAL;
+        }
+
+        /*
+         * calculate the divider of mclk/sample_freq,
+         * factor of freq =96k can only be 256, since mclk in range (12m,27m)
+         */
+        switch (sgtl5000->sysclk / sys_fs) {
+        case 256:
+                clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
+                        SGTL5000_MCLK_FREQ_SHIFT;
+                break;
+        case 384:
+                clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
+                        SGTL5000_MCLK_FREQ_SHIFT;
+                break;
+        case 512:
+                clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
+                        SGTL5000_MCLK_FREQ_SHIFT;
+                break;
+        default:
+                /* if mclk not satisify the divider, use pll */
+                if (sgtl5000->master) {
+                        clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
+                                SGTL5000_MCLK_FREQ_SHIFT;
+                } else {
+                        dev_err(codec->dev,
+                                "PLL not supported in slave mode\n");
+                        return -EINVAL;
+                }
+        }
+
+        /* if using pll, please check manual 6.4.2 for detail */
+        if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
+                u64 out, t;
+                int div2;
+                int pll_ctl;
+                unsigned int in, int_div, frac_div;
+
+                if (sgtl5000->sysclk > 17000000) {
+                        div2 = 1;
+                        in = sgtl5000->sysclk / 2;
+                } else {
+                        div2 = 0;
+                        in = sgtl5000->sysclk;
+                }
+                if (sys_fs == 44100)
+                        out = 180633600;
+                else
+                        out = 196608000;
+                t = do_div(out, in);
+                int_div = out;
+                t *= 2048;
+                do_div(t, in);
+                frac_div = t;
+                pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
+                    frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
+
+                snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
+                if (div2)
+                        snd_soc_update_bits(codec,
+                                SGTL5000_CHIP_CLK_TOP_CTRL,
+                                SGTL5000_INPUT_FREQ_DIV2,
+                                SGTL5000_INPUT_FREQ_DIV2);
+                else
+                        snd_soc_update_bits(codec,
+                                SGTL5000_CHIP_CLK_TOP_CTRL,
+                                SGTL5000_INPUT_FREQ_DIV2,
+                                0);
+
+                /* power up pll */
+                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+                        SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
+                        SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
+        } else {
+                /* power down pll */
+                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+                        SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
+                        0);
+        }
+
+        /* if using pll, clk_ctrl must be set after pll power up */
+        snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
+
+        return 0;
+}
+
+/*
+ * Set PCM DAI bit size and sample rate.
+ * input: params_rate, params_fmt
+ */
+static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
+                                  struct snd_pcm_hw_params *params,
+                                  struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+        int channels = params_channels(params);
+        int i2s_ctl = 0;
+        int stereo;
+        int ret;
+
+        /* sysclk should already set */
+        if (!sgtl5000->sysclk) {
+                dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
+                return -EFAULT;
+        }
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                stereo = SGTL5000_DAC_STEREO;
+        else
+                stereo = SGTL5000_ADC_STEREO;
+
+        /* set mono to save power */
+        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
+                        channels == 1 ? 0 : stereo);
+
+        /* set codec clock base on lrclk */
+        ret = sgtl5000_set_clock(codec, params_rate(params));
+        if (ret)
+                return ret;
+
+        /* set i2s data format */
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
+                        return -EINVAL;
+                i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
+                i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
+                    SGTL5000_I2S_SCLKFREQ_SHIFT;
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
+                i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
+                    SGTL5000_I2S_SCLKFREQ_SHIFT;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
+                i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
+                    SGTL5000_I2S_SCLKFREQ_SHIFT;
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
+                        return -EINVAL;
+                i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
+                i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
+                    SGTL5000_I2S_SCLKFREQ_SHIFT;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, i2s_ctl, i2s_ctl);
+
+        return 0;
+}
+
+#ifdef CONFIG_REGULATOR
+static int ldo_regulator_is_enabled(struct regulator_dev *dev)
+{
+        struct ldo_regulator *ldo = rdev_get_drvdata(dev);
+
+        return ldo->enabled;
+}
+
+static int ldo_regulator_enable(struct regulator_dev *dev)
+{
+        struct ldo_regulator *ldo = rdev_get_drvdata(dev);
+        struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
+        int reg;
+
+        if (ldo_regulator_is_enabled(dev))
+                return 0;
+
+        /* set regulator value firstly */
+        reg = (1600 - ldo->voltage / 1000) / 50;
+        reg = clamp(reg, 0x0, 0xf);
+
+        /* amend the voltage value, unit: uV */
+        ldo->voltage = (1600 - reg * 50) * 1000;
+
+        /* set voltage to register */
+        snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
+                                (0x1 << 4) - 1, reg);
+
+        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+                                SGTL5000_LINEREG_D_POWERUP,
+                                SGTL5000_LINEREG_D_POWERUP);
+
+        /* when internal ldo enabled, simple digital power can be disabled */
+        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+                                SGTL5000_LINREG_SIMPLE_POWERUP,
+                                0);
+
+        ldo->enabled = 1;
+        return 0;
+}
+
+static int ldo_regulator_disable(struct regulator_dev *dev)
+{
+        struct ldo_regulator *ldo = rdev_get_drvdata(dev);
+        struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
+
+        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+                                SGTL5000_LINEREG_D_POWERUP,
+                                0);
+
+        /* clear voltage info */
+        snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
+                                (0x1 << 4) - 1, 0);
+
+        ldo->enabled = 0;
+
+        return 0;
+}
+
+static int ldo_regulator_get_voltage(struct regulator_dev *dev)
+{
+        struct ldo_regulator *ldo = rdev_get_drvdata(dev);
+
+        return ldo->voltage;
+}
+
+static struct regulator_ops ldo_regulator_ops = {
+        .is_enabled = ldo_regulator_is_enabled,
+        .enable = ldo_regulator_enable,
+        .disable = ldo_regulator_disable,
+        .get_voltage = ldo_regulator_get_voltage,
+};
+
+static int ldo_regulator_register(struct snd_soc_codec *codec,
+                                struct regulator_init_data *init_data,
+                                int voltage)
+{
+        struct ldo_regulator *ldo;
+
+        ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
+
+        if (!ldo) {
+                dev_err(codec->dev, "failed to allocate ldo_regulator\n");
+                return -ENOMEM;
+        }
+
+        ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
+        if (!ldo->desc.name) {
+                kfree(ldo);
+                dev_err(codec->dev, "failed to allocate decs name memory\n");
+                return -ENOMEM;
+        }
+
+        ldo->desc.type  = REGULATOR_VOLTAGE;
+        ldo->desc.owner = THIS_MODULE;
+        ldo->desc.ops   = &ldo_regulator_ops;
+        ldo->desc.n_voltages = 1;
+
+        ldo->codec_data = codec;
+        ldo->voltage = voltage;
+
+        ldo->dev = regulator_register(&ldo->desc, codec->dev,
+                                          init_data, ldo);
+        if (IS_ERR(ldo->dev)) {
+                int ret = PTR_ERR(ldo->dev);
+
+                dev_err(codec->dev, "failed to register regulator\n");
+                kfree(ldo->desc.name);
+                kfree(ldo);
+
+                return ret;
+        }
+
+        return 0;
+}
+
+static int ldo_regulator_remove(struct snd_soc_codec *codec)
+{
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+        struct ldo_regulator *ldo = sgtl5000->ldo;
+
+        if (!ldo)
+                return 0;
+
+        regulator_unregister(ldo->dev);
+        kfree(ldo->desc.name);
+        kfree(ldo);
+
+        return 0;
+}
+#else
+static int ldo_regulator_register(struct snd_soc_codec *codec,
+                                struct regulator_init_data *init_data,
+                                int voltage)
+{
+        return -EINVAL;
+}
+
+static int ldo_regulator_remove(struct snd_soc_codec *codec)
+{
+        return 0;
+}
+#endif
+
+/*
+ * set dac bias
+ * common state changes:
+ * startup:
+ * off --> standby --> prepare --> on
+ * standby --> prepare --> on
+ *
+ * stop:
+ * on --> prepare --> standby
+ */
+static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
+                                   enum snd_soc_bias_level level)
+{
+        int ret;
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+        case SND_SOC_BIAS_PREPARE:
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = regulator_bulk_enable(
+                                                ARRAY_SIZE(sgtl5000->supplies),
+                                                sgtl5000->supplies);
+                        if (ret)
+                                return ret;
+                        udelay(10);
+                }
+
+                break;
+        case SND_SOC_BIAS_OFF:
+                regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
+                                        sgtl5000->supplies);
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+                        SNDRV_PCM_FMTBIT_S20_3LE |\
+                        SNDRV_PCM_FMTBIT_S24_LE |\
+                        SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops sgtl5000_ops = {
+        .hw_params = sgtl5000_pcm_hw_params,
+        .digital_mute = sgtl5000_digital_mute,
+        .set_fmt = sgtl5000_set_dai_fmt,
+        .set_sysclk = sgtl5000_set_dai_sysclk,
+};
+
+static struct snd_soc_dai_driver sgtl5000_dai = {
+        .name = "sgtl5000",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                /*
+                 * only support 8~48K + 96K,
+                 * TODO modify hw_param to support more
+                 */
+                .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
+                .formats = SGTL5000_FORMATS,
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
+                .formats = SGTL5000_FORMATS,
+        },
+        .ops = &sgtl5000_ops,
+        .symmetric_rates = 1,
+};
+
+static int sgtl5000_volatile_register(struct snd_soc_codec *codec,
+                                        unsigned int reg)
+{
+        switch (reg) {
+        case SGTL5000_CHIP_ID:
+        case SGTL5000_CHIP_ADCDAC_CTRL:
+        case SGTL5000_CHIP_ANA_STATUS:
+                return 1;
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_SUSPEND
+static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        return 0;
+}
+
+/*
+ * restore all sgtl5000 registers,
+ * since a big hole between dap and regular registers,
+ * we will restore them respectively.
+ */
+static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
+{
+        u16 *cache = codec->reg_cache;
+        int i;
+        int regular_regs = SGTL5000_CHIP_SHORT_CTRL >> 1;
+
+        /* restore regular registers */
+        for (i = 0; i < regular_regs; i++) {
+                int reg = i << 1;
+
+                /* this regs depends on the others */
+                if (reg == SGTL5000_CHIP_ANA_POWER ||
+                        reg == SGTL5000_CHIP_CLK_CTRL ||
+                        reg == SGTL5000_CHIP_LINREG_CTRL ||
+                        reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
+                        reg == SGTL5000_CHIP_CLK_CTRL)
+                        continue;
+
+                snd_soc_write(codec, reg, cache[i]);
+        }
+
+        /* restore dap registers */
+        for (i = SGTL5000_DAP_REG_OFFSET >> 1;
+                        i < SGTL5000_MAX_REG_OFFSET >> 1; i++) {
+                int reg = i << 1;
+
+                snd_soc_write(codec, reg, cache[i]);
+        }
+
+        /*
+         * restore power and other regs according
+         * to set_power() and set_clock()
+         */
+        snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
+                        cache[SGTL5000_CHIP_LINREG_CTRL >> 1]);
+
+        snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
+                        cache[SGTL5000_CHIP_ANA_POWER >> 1]);
+
+        snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
+                        cache[SGTL5000_CHIP_CLK_CTRL >> 1]);
+
+        snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
+                        cache[SGTL5000_CHIP_REF_CTRL >> 1]);
+
+        snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
+                        cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]);
+        return 0;
+}
+
+static int sgtl5000_resume(struct snd_soc_codec *codec)
+{
+        /* Bring the codec back up to standby to enable regulators */
+        sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        /* Restore registers by cached in memory */
+        sgtl5000_restore_regs(codec);
+        return 0;
+}
+#else
+#define sgtl5000_suspend NULL
+#define sgtl5000_resume  NULL
+#endif  /* CONFIG_SUSPEND */
+
+/*
+ * sgtl5000 has 3 internal power supplies:
+ * 1. VAG, normally set to vdda/2
+ * 2. chargepump, set to different value
+ *      according to voltage of vdda and vddio
+ * 3. line out VAG, normally set to vddio/2
+ *
+ * and should be set according to:
+ * 1. vddd provided by external or not
+ * 2. vdda and vddio voltage value. > 3.1v or not
+ * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
+ */
+static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
+{
+        int vddd;
+        int vdda;
+        int vddio;
+        u16 ana_pwr;
+        u16 lreg_ctrl;
+        int vag;
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+
+        vdda  = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
+        vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
+        vddd  = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
+
+        vdda  = vdda / 1000;
+        vddio = vddio / 1000;
+        vddd  = vddd / 1000;
+
+        if (vdda <= 0 || vddio <= 0 || vddd < 0) {
+                dev_err(codec->dev, "regulator voltage not set correctly\n");
+
+                return -EINVAL;
+        }
+
+        /* according to datasheet, maximum voltage of supplies */
+        if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
+                dev_err(codec->dev,
+                        "exceed max voltage vdda %dmv vddio %dma vddd %dma\n",
+                        vdda, vddio, vddd);
+
+                return -EINVAL;
+        }
+
+        /* reset value */
+        ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
+        ana_pwr |= SGTL5000_DAC_STEREO |
+                        SGTL5000_ADC_STEREO |
+                        SGTL5000_REFTOP_POWERUP;
+        lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
+
+        if (vddio < 3100 && vdda < 3100) {
+                /* enable internal oscillator used for charge pump */
+                snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
+                                        SGTL5000_INT_OSC_EN,
+                                        SGTL5000_INT_OSC_EN);
+                /* Enable VDDC charge pump */
+                ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
+        } else if (vddio >= 3100 && vdda >= 3100) {
+                /*
+                 * if vddio and vddd > 3.1v,
+                 * charge pump should be clean before set ana_pwr
+                 */
+                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+                                SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
+
+                /* VDDC use VDDIO rail */
+                lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
+                lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
+                            SGTL5000_VDDC_MAN_ASSN_SHIFT;
+        }
+
+        snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
+
+        snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
+
+        /* set voltage to register */
+        snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
+                                (0x1 << 4) - 1, 0x8);
+
+        /*
+         * if vddd linear reg has been enabled,
+         * simple digital supply should be clear to get
+         * proper VDDD voltage.
+         */
+        if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
+                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+                                SGTL5000_LINREG_SIMPLE_POWERUP,
+                                0);
+        else
+                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
+                                SGTL5000_LINREG_SIMPLE_POWERUP |
+                                SGTL5000_STARTUP_POWERUP,
+                                0);
+
+        /*
+         * set ADC/DAC VAG to vdda / 2,
+         * should stay in range (0.8v, 1.575v)
+         */
+        vag = vdda / 2;
+        if (vag <= SGTL5000_ANA_GND_BASE)
+                vag = 0;
+        else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
+                 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
+                vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
+        else
+                vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
+
+        snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
+                        vag << SGTL5000_ANA_GND_SHIFT,
+                        vag << SGTL5000_ANA_GND_SHIFT);
+
+        /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
+        vag = vddio / 2;
+        if (vag <= SGTL5000_LINE_OUT_GND_BASE)
+                vag = 0;
+        else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
+                SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
+                vag = SGTL5000_LINE_OUT_GND_MAX;
+        else
+                vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
+                    SGTL5000_LINE_OUT_GND_STP;
+
+        snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
+                        vag << SGTL5000_LINE_OUT_GND_SHIFT |
+                        SGTL5000_LINE_OUT_CURRENT_360u <<
+                                SGTL5000_LINE_OUT_CURRENT_SHIFT,
+                        vag << SGTL5000_LINE_OUT_GND_SHIFT |
+                        SGTL5000_LINE_OUT_CURRENT_360u <<
+                                SGTL5000_LINE_OUT_CURRENT_SHIFT);
+
+        return 0;
+}
+
+static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
+{
+        u16 reg;
+        int ret;
+        int rev;
+        int i;
+        int external_vddd = 0;
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+
+        for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
+                sgtl5000->supplies[i].supply = supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
+                                sgtl5000->supplies);
+        if (!ret)
+                external_vddd = 1;
+        else {
+                /* set internal ldo to 1.2v */
+                int voltage = LDO_VOLTAGE;
+
+                ret = ldo_regulator_register(codec, &ldo_init_data, voltage);
+                if (ret) {
+                        dev_err(codec->dev,
+                        "Failed to register vddd internal supplies: %d\n",
+                                ret);
+                        return ret;
+                }
+
+                sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
+
+                ret = regulator_bulk_get(codec->dev,
+                                ARRAY_SIZE(sgtl5000->supplies),
+                                sgtl5000->supplies);
+
+                if (ret) {
+                        ldo_regulator_remove(codec);
+                        dev_err(codec->dev,
+                                "Failed to request supplies: %d\n", ret);
+
+                        return ret;
+                }
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
+                                        sgtl5000->supplies);
+        if (ret)
+                goto err_regulator_free;
+
+        /* wait for all power rails bring up */
+        udelay(10);
+
+        /* read chip information */
+        reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
+        if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
+            SGTL5000_PARTID_PART_ID) {
+                dev_err(codec->dev,
+                        "Device with ID register %x is not a sgtl5000\n", reg);
+                ret = -ENODEV;
+                goto err_regulator_disable;
+        }
+
+        rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
+        dev_info(codec->dev, "sgtl5000 revision %d\n", rev);
+
+        /*
+         * workaround for revision 0x11 and later,
+         * roll back to use internal LDO
+         */
+        if (external_vddd && rev >= 0x11) {
+                int voltage = LDO_VOLTAGE;
+                /* disable all regulator first */
+                regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
+                                        sgtl5000->supplies);
+                /* free VDDD regulator */
+                regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
+                                        sgtl5000->supplies);
+
+                ret = ldo_regulator_register(codec, &ldo_init_data, voltage);
+                if (ret)
+                        return ret;
+
+                sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
+
+                ret = regulator_bulk_get(codec->dev,
+                                ARRAY_SIZE(sgtl5000->supplies),
+                                sgtl5000->supplies);
+                if (ret) {
+                        ldo_regulator_remove(codec);
+                        dev_err(codec->dev,
+                                "Failed to request supplies: %d\n", ret);
+
+                        return ret;
+                }
+
+                ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
+                                                sgtl5000->supplies);
+                if (ret)
+                        goto err_regulator_free;
+
+                /* wait for all power rails bring up */
+                udelay(10);
+        }
+
+        return 0;
+
+err_regulator_disable:
+        regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
+                                sgtl5000->supplies);
+err_regulator_free:
+        regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
+                                sgtl5000->supplies);
+        if (external_vddd)
+                ldo_regulator_remove(codec);
+        return ret;
+
+}
+
+static int sgtl5000_probe(struct snd_soc_codec *codec)
+{
+        int ret;
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+
+        /* setup i2c data ops */
+        ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        ret = sgtl5000_enable_regulators(codec);
+        if (ret)
+                return ret;
+
+        /* power up sgtl5000 */
+        ret = sgtl5000_set_power_regs(codec);
+        if (ret)
+                goto err;
+
+        /* enable small pop, introduce 400ms delay in turning off */
+        snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
+                                SGTL5000_SMALL_POP,
+                                SGTL5000_SMALL_POP);
+
+        /* disable short cut detector */
+        snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
+
+        /*
+         * set i2s as default input of sound switch
+         * TODO: add sound switch to control and dapm widge.
+         */
+        snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
+                        SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
+        snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
+                        SGTL5000_ADC_EN | SGTL5000_DAC_EN);
+
+        /* enable dac volume ramp by default */
+        snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
+                        SGTL5000_DAC_VOL_RAMP_EN |
+                        SGTL5000_DAC_MUTE_RIGHT |
+                        SGTL5000_DAC_MUTE_LEFT);
+
+        snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
+
+        snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
+                        SGTL5000_HP_ZCD_EN |
+                        SGTL5000_ADC_ZCD_EN);
+
+        snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
+
+        /*
+         * disable DAP
+         * TODO:
+         * Enable DAP in kcontrol and dapm.
+         */
+        snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
+
+        /* leading to standby state */
+        ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        if (ret)
+                goto err;
+
+        snd_soc_add_controls(codec, sgtl5000_snd_controls,
+                             ARRAY_SIZE(sgtl5000_snd_controls));
+
+        snd_soc_dapm_new_controls(&codec->dapm, sgtl5000_dapm_widgets,
+                                  ARRAY_SIZE(sgtl5000_dapm_widgets));
+
+        snd_soc_dapm_add_routes(&codec->dapm, audio_map,
+                                ARRAY_SIZE(audio_map));
+
+        snd_soc_dapm_new_widgets(&codec->dapm);
+
+        return 0;
+
+err:
+        regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
+                                                sgtl5000->supplies);
+        regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
+                                sgtl5000->supplies);
+        ldo_regulator_remove(codec);
+
+        return ret;
+}
+
+static int sgtl5000_remove(struct snd_soc_codec *codec)
+{
+        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+
+        sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
+                                                sgtl5000->supplies);
+        regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
+                                sgtl5000->supplies);
+        ldo_regulator_remove(codec);
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver sgtl5000_driver = {
+        .probe = sgtl5000_probe,
+        .remove = sgtl5000_remove,
+        .suspend = sgtl5000_suspend,
+        .resume = sgtl5000_resume,
+        .set_bias_level = sgtl5000_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(sgtl5000_regs),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_step = 2,
+        .reg_cache_default = sgtl5000_regs,
+        .volatile_register = sgtl5000_volatile_register,
+};
+
+static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
+                                        const struct i2c_device_id *id)
+{
+        struct sgtl5000_priv *sgtl5000;
+        int ret;
+
+        sgtl5000 = kzalloc(sizeof(struct sgtl5000_priv), GFP_KERNEL);
+        if (!sgtl5000)
+                return -ENOMEM;
+
+        /*
+         * copy DAP default values to default value array.
+         * sgtl5000 register space has a big hole, merge it
+         * at init phase makes life easy.
+         * FIXME: should we drop 'const' of sgtl5000_regs?
+         */
+        memcpy((void *)(&sgtl5000_regs[0] + (SGTL5000_DAP_REG_OFFSET >> 1)),
+                        sgtl5000_dap_regs,
+                        SGTL5000_MAX_REG_OFFSET - SGTL5000_DAP_REG_OFFSET);
+
+        i2c_set_clientdata(client, sgtl5000);
+
+        ret = snd_soc_register_codec(&client->dev,
+                        &sgtl5000_driver, &sgtl5000_dai, 1);
+        if (ret) {
+                dev_err(&client->dev, "Failed to register codec: %d\n", ret);
+                kfree(sgtl5000);
+                return ret;
+        }
+
+        return 0;
+}
+
+static __devexit int sgtl5000_i2c_remove(struct i2c_client *client)
+{
+        struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
+
+        snd_soc_unregister_codec(&client->dev);
+
+        kfree(sgtl5000);
+        return 0;
+}
+
+static const struct i2c_device_id sgtl5000_id[] = {
+        {"sgtl5000", 0},
+        {},
+};
+
+MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
+
+static struct i2c_driver sgtl5000_i2c_driver = {
+        .driver = {
+                   .name = "sgtl5000",
+                   .owner = THIS_MODULE,
+                   },
+        .probe = sgtl5000_i2c_probe,
+        .remove = __devexit_p(sgtl5000_i2c_remove),
+        .id_table = sgtl5000_id,
+};
+
+static int __init sgtl5000_modinit(void)
+{
+        return i2c_add_driver(&sgtl5000_i2c_driver);
+}
+module_init(sgtl5000_modinit);
+
+static void __exit sgtl5000_exit(void)
+{
+        i2c_del_driver(&sgtl5000_i2c_driver);
+}
+module_exit(sgtl5000_exit);
+
+MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
+MODULE_AUTHOR("Zeng Zhaoming <zhaoming.zeng@freescale.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h
new file mode 100644
index 000000000000..eec3ab368f39
--- /dev/null
+++ b/sound/soc/codecs/sgtl5000.h
@@ -0,0 +1,400 @@
+/*
+ * sgtl5000.h - SGTL5000 audio codec interface
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _SGTL5000_H
+#define _SGTL5000_H
+
+/*
+ * Register values.
+ */
+#define SGTL5000_CHIP_ID                        0x0000
+#define SGTL5000_CHIP_DIG_POWER                 0x0002
+#define SGTL5000_CHIP_CLK_CTRL                  0x0004
+#define SGTL5000_CHIP_I2S_CTRL                  0x0006
+#define SGTL5000_CHIP_SSS_CTRL                  0x000a
+#define SGTL5000_CHIP_ADCDAC_CTRL               0x000e
+#define SGTL5000_CHIP_DAC_VOL                   0x0010
+#define SGTL5000_CHIP_PAD_STRENGTH              0x0014
+#define SGTL5000_CHIP_ANA_ADC_CTRL              0x0020
+#define SGTL5000_CHIP_ANA_HP_CTRL               0x0022
+#define SGTL5000_CHIP_ANA_CTRL                  0x0024
+#define SGTL5000_CHIP_LINREG_CTRL               0x0026
+#define SGTL5000_CHIP_REF_CTRL                  0x0028
+#define SGTL5000_CHIP_MIC_CTRL                  0x002a
+#define SGTL5000_CHIP_LINE_OUT_CTRL             0x002c
+#define SGTL5000_CHIP_LINE_OUT_VOL              0x002e
+#define SGTL5000_CHIP_ANA_POWER                 0x0030
+#define SGTL5000_CHIP_PLL_CTRL                  0x0032
+#define SGTL5000_CHIP_CLK_TOP_CTRL              0x0034
+#define SGTL5000_CHIP_ANA_STATUS                0x0036
+#define SGTL5000_CHIP_SHORT_CTRL                0x003c
+#define SGTL5000_CHIP_ANA_TEST2                 0x003a
+#define SGTL5000_DAP_CTRL                       0x0100
+#define SGTL5000_DAP_PEQ                        0x0102
+#define SGTL5000_DAP_BASS_ENHANCE               0x0104
+#define SGTL5000_DAP_BASS_ENHANCE_CTRL          0x0106
+#define SGTL5000_DAP_AUDIO_EQ                   0x0108
+#define SGTL5000_DAP_SURROUND                   0x010a
+#define SGTL5000_DAP_FLT_COEF_ACCESS            0x010c
+#define SGTL5000_DAP_COEF_WR_B0_MSB             0x010e
+#define SGTL5000_DAP_COEF_WR_B0_LSB             0x0110
+#define SGTL5000_DAP_EQ_BASS_BAND0              0x0116
+#define SGTL5000_DAP_EQ_BASS_BAND1              0x0118
+#define SGTL5000_DAP_EQ_BASS_BAND2              0x011a
+#define SGTL5000_DAP_EQ_BASS_BAND3              0x011c
+#define SGTL5000_DAP_EQ_BASS_BAND4              0x011e
+#define SGTL5000_DAP_MAIN_CHAN                  0x0120
+#define SGTL5000_DAP_MIX_CHAN                   0x0122
+#define SGTL5000_DAP_AVC_CTRL                   0x0124
+#define SGTL5000_DAP_AVC_THRESHOLD              0x0126
+#define SGTL5000_DAP_AVC_ATTACK                 0x0128
+#define SGTL5000_DAP_AVC_DECAY                  0x012a
+#define SGTL5000_DAP_COEF_WR_B1_MSB             0x012c
+#define SGTL5000_DAP_COEF_WR_B1_LSB             0x012e
+#define SGTL5000_DAP_COEF_WR_B2_MSB             0x0130
+#define SGTL5000_DAP_COEF_WR_B2_LSB             0x0132
+#define SGTL5000_DAP_COEF_WR_A1_MSB             0x0134
+#define SGTL5000_DAP_COEF_WR_A1_LSB             0x0136
+#define SGTL5000_DAP_COEF_WR_A2_MSB             0x0138
+#define SGTL5000_DAP_COEF_WR_A2_LSB             0x013a
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * SGTL5000_CHIP_ID
+ */
+#define SGTL5000_PARTID_MASK                    0xff00
+#define SGTL5000_PARTID_SHIFT                   8
+#define SGTL5000_PARTID_WIDTH                   8
+#define SGTL5000_PARTID_PART_ID                 0xa0
+#define SGTL5000_REVID_MASK                     0x00ff
+#define SGTL5000_REVID_SHIFT                    0
+#define SGTL5000_REVID_WIDTH                    8
+
+/*
+ * SGTL5000_CHIP_DIG_POWER
+ */
+#define SGTL5000_ADC_EN                         0x0040
+#define SGTL5000_DAC_EN                         0x0020
+#define SGTL5000_DAP_POWERUP                    0x0010
+#define SGTL5000_I2S_OUT_POWERUP                0x0002
+#define SGTL5000_I2S_IN_POWERUP                 0x0001
+
+/*
+ * SGTL5000_CHIP_CLK_CTRL
+ */
+#define SGTL5000_RATE_MODE_MASK                 0x0030
+#define SGTL5000_RATE_MODE_SHIFT                4
+#define SGTL5000_RATE_MODE_WIDTH                2
+#define SGTL5000_RATE_MODE_DIV_1                0
+#define SGTL5000_RATE_MODE_DIV_2                1
+#define SGTL5000_RATE_MODE_DIV_4                2
+#define SGTL5000_RATE_MODE_DIV_6                3
+#define SGTL5000_SYS_FS_MASK                    0x000c
+#define SGTL5000_SYS_FS_SHIFT                   2
+#define SGTL5000_SYS_FS_WIDTH                   2
+#define SGTL5000_SYS_FS_32k                     0x0
+#define SGTL5000_SYS_FS_44_1k                   0x1
+#define SGTL5000_SYS_FS_48k                     0x2
+#define SGTL5000_SYS_FS_96k                     0x3
+#define SGTL5000_MCLK_FREQ_MASK                 0x0003
+#define SGTL5000_MCLK_FREQ_SHIFT                0
+#define SGTL5000_MCLK_FREQ_WIDTH                2
+#define SGTL5000_MCLK_FREQ_256FS                0x0
+#define SGTL5000_MCLK_FREQ_384FS                0x1
+#define SGTL5000_MCLK_FREQ_512FS                0x2
+#define SGTL5000_MCLK_FREQ_PLL                  0x3
+
+/*
+ * SGTL5000_CHIP_I2S_CTRL
+ */
+#define SGTL5000_I2S_SCLKFREQ_MASK              0x0100
+#define SGTL5000_I2S_SCLKFREQ_SHIFT             8
+#define SGTL5000_I2S_SCLKFREQ_WIDTH             1
+#define SGTL5000_I2S_SCLKFREQ_64FS              0x0
+#define SGTL5000_I2S_SCLKFREQ_32FS              0x1     /* Not for RJ mode */
+#define SGTL5000_I2S_MASTER                     0x0080
+#define SGTL5000_I2S_SCLK_INV                   0x0040
+#define SGTL5000_I2S_DLEN_MASK                  0x0030
+#define SGTL5000_I2S_DLEN_SHIFT                 4
+#define SGTL5000_I2S_DLEN_WIDTH                 2
+#define SGTL5000_I2S_DLEN_32                    0x0
+#define SGTL5000_I2S_DLEN_24                    0x1
+#define SGTL5000_I2S_DLEN_20                    0x2
+#define SGTL5000_I2S_DLEN_16                    0x3
+#define SGTL5000_I2S_MODE_MASK                  0x000c
+#define SGTL5000_I2S_MODE_SHIFT                 2
+#define SGTL5000_I2S_MODE_WIDTH                 2
+#define SGTL5000_I2S_MODE_I2S_LJ                0x0
+#define SGTL5000_I2S_MODE_RJ                    0x1
+#define SGTL5000_I2S_MODE_PCM                   0x2
+#define SGTL5000_I2S_LRALIGN                    0x0002
+#define SGTL5000_I2S_LRPOL                      0x0001  /* set for which mode */
+
+/*
+ * SGTL5000_CHIP_SSS_CTRL
+ */
+#define SGTL5000_DAP_MIX_LRSWAP                 0x4000
+#define SGTL5000_DAP_LRSWAP                     0x2000
+#define SGTL5000_DAC_LRSWAP                     0x1000
+#define SGTL5000_I2S_OUT_LRSWAP                 0x0400
+#define SGTL5000_DAP_MIX_SEL_MASK               0x0300
+#define SGTL5000_DAP_MIX_SEL_SHIFT              8
+#define SGTL5000_DAP_MIX_SEL_WIDTH              2
+#define SGTL5000_DAP_MIX_SEL_ADC                0x0
+#define SGTL5000_DAP_MIX_SEL_I2S_IN             0x1
+#define SGTL5000_DAP_SEL_MASK                   0x00c0
+#define SGTL5000_DAP_SEL_SHIFT                  6
+#define SGTL5000_DAP_SEL_WIDTH                  2
+#define SGTL5000_DAP_SEL_ADC                    0x0
+#define SGTL5000_DAP_SEL_I2S_IN                 0x1
+#define SGTL5000_DAC_SEL_MASK                   0x0030
+#define SGTL5000_DAC_SEL_SHIFT                  4
+#define SGTL5000_DAC_SEL_WIDTH                  2
+#define SGTL5000_DAC_SEL_ADC                    0x0
+#define SGTL5000_DAC_SEL_I2S_IN                 0x1
+#define SGTL5000_DAC_SEL_DAP                    0x3
+#define SGTL5000_I2S_OUT_SEL_MASK               0x0003
+#define SGTL5000_I2S_OUT_SEL_SHIFT              0
+#define SGTL5000_I2S_OUT_SEL_WIDTH              2
+#define SGTL5000_I2S_OUT_SEL_ADC                0x0
+#define SGTL5000_I2S_OUT_SEL_I2S_IN             0x1
+#define SGTL5000_I2S_OUT_SEL_DAP                0x3
+
+/*
+ * SGTL5000_CHIP_ADCDAC_CTRL
+ */
+#define SGTL5000_VOL_BUSY_DAC_RIGHT             0x2000
+#define SGTL5000_VOL_BUSY_DAC_LEFT              0x1000
+#define SGTL5000_DAC_VOL_RAMP_EN                0x0200
+#define SGTL5000_DAC_VOL_RAMP_EXPO              0x0100
+#define SGTL5000_DAC_MUTE_RIGHT                 0x0008
+#define SGTL5000_DAC_MUTE_LEFT                  0x0004
+#define SGTL5000_ADC_HPF_FREEZE                 0x0002
+#define SGTL5000_ADC_HPF_BYPASS                 0x0001
+
+/*
+ * SGTL5000_CHIP_DAC_VOL
+ */
+#define SGTL5000_DAC_VOL_RIGHT_MASK             0xff00
+#define SGTL5000_DAC_VOL_RIGHT_SHIFT            8
+#define SGTL5000_DAC_VOL_RIGHT_WIDTH            8
+#define SGTL5000_DAC_VOL_LEFT_MASK              0x00ff
+#define SGTL5000_DAC_VOL_LEFT_SHIFT             0
+#define SGTL5000_DAC_VOL_LEFT_WIDTH             8
+
+/*
+ * SGTL5000_CHIP_PAD_STRENGTH
+ */
+#define SGTL5000_PAD_I2S_LRCLK_MASK             0x0300
+#define SGTL5000_PAD_I2S_LRCLK_SHIFT            8
+#define SGTL5000_PAD_I2S_LRCLK_WIDTH            2
+#define SGTL5000_PAD_I2S_SCLK_MASK              0x00c0
+#define SGTL5000_PAD_I2S_SCLK_SHIFT             6
+#define SGTL5000_PAD_I2S_SCLK_WIDTH             2
+#define SGTL5000_PAD_I2S_DOUT_MASK              0x0030
+#define SGTL5000_PAD_I2S_DOUT_SHIFT             4
+#define SGTL5000_PAD_I2S_DOUT_WIDTH             2
+#define SGTL5000_PAD_I2C_SDA_MASK               0x000c
+#define SGTL5000_PAD_I2C_SDA_SHIFT              2
+#define SGTL5000_PAD_I2C_SDA_WIDTH              2
+#define SGTL5000_PAD_I2C_SCL_MASK               0x0003
+#define SGTL5000_PAD_I2C_SCL_SHIFT              0
+#define SGTL5000_PAD_I2C_SCL_WIDTH              2
+
+/*
+ * SGTL5000_CHIP_ANA_ADC_CTRL
+ */
+#define SGTL5000_ADC_VOL_M6DB                   0x0100
+#define SGTL5000_ADC_VOL_RIGHT_MASK             0x00f0
+#define SGTL5000_ADC_VOL_RIGHT_SHIFT            4
+#define SGTL5000_ADC_VOL_RIGHT_WIDTH            4
+#define SGTL5000_ADC_VOL_LEFT_MASK              0x000f
+#define SGTL5000_ADC_VOL_LEFT_SHIFT             0
+#define SGTL5000_ADC_VOL_LEFT_WIDTH             4
+
+/*
+ * SGTL5000_CHIP_ANA_HP_CTRL
+ */
+#define SGTL5000_HP_VOL_RIGHT_MASK              0x7f00
+#define SGTL5000_HP_VOL_RIGHT_SHIFT             8
+#define SGTL5000_HP_VOL_RIGHT_WIDTH             7
+#define SGTL5000_HP_VOL_LEFT_MASK               0x007f
+#define SGTL5000_HP_VOL_LEFT_SHIFT              0
+#define SGTL5000_HP_VOL_LEFT_WIDTH              7
+
+/*
+ * SGTL5000_CHIP_ANA_CTRL
+ */
+#define SGTL5000_LINE_OUT_MUTE                  0x0100
+#define SGTL5000_HP_SEL_MASK                    0x0040
+#define SGTL5000_HP_SEL_SHIFT                   6
+#define SGTL5000_HP_SEL_WIDTH                   1
+#define SGTL5000_HP_SEL_DAC                     0x0
+#define SGTL5000_HP_SEL_LINE_IN                 0x1
+#define SGTL5000_HP_ZCD_EN                      0x0020
+#define SGTL5000_HP_MUTE                        0x0010
+#define SGTL5000_ADC_SEL_MASK                   0x0004
+#define SGTL5000_ADC_SEL_SHIFT                  2
+#define SGTL5000_ADC_SEL_WIDTH                  1
+#define SGTL5000_ADC_SEL_MIC                    0x0
+#define SGTL5000_ADC_SEL_LINE_IN                0x1
+#define SGTL5000_ADC_ZCD_EN                     0x0002
+#define SGTL5000_ADC_MUTE                       0x0001
+
+/*
+ * SGTL5000_CHIP_LINREG_CTRL
+ */
+#define SGTL5000_VDDC_MAN_ASSN_MASK             0x0040
+#define SGTL5000_VDDC_MAN_ASSN_SHIFT            6
+#define SGTL5000_VDDC_MAN_ASSN_WIDTH            1
+#define SGTL5000_VDDC_MAN_ASSN_VDDA             0x0
+#define SGTL5000_VDDC_MAN_ASSN_VDDIO            0x1
+#define SGTL5000_VDDC_ASSN_OVRD                 0x0020
+#define SGTL5000_LINREG_VDDD_MASK               0x000f
+#define SGTL5000_LINREG_VDDD_SHIFT              0
+#define SGTL5000_LINREG_VDDD_WIDTH              4
+
+/*
+ * SGTL5000_CHIP_REF_CTRL
+ */
+#define SGTL5000_ANA_GND_MASK                   0x01f0
+#define SGTL5000_ANA_GND_SHIFT                  4
+#define SGTL5000_ANA_GND_WIDTH                  5
+#define SGTL5000_ANA_GND_BASE                   800     /* mv */
+#define SGTL5000_ANA_GND_STP                    25      /*mv */
+#define SGTL5000_BIAS_CTRL_MASK                 0x000e
+#define SGTL5000_BIAS_CTRL_SHIFT                1
+#define SGTL5000_BIAS_CTRL_WIDTH                3
+#define SGTL5000_SMALL_POP                      0x0001
+
+/*
+ * SGTL5000_CHIP_MIC_CTRL
+ */
+#define SGTL5000_BIAS_R_MASK                    0x0200
+#define SGTL5000_BIAS_R_SHIFT                   8
+#define SGTL5000_BIAS_R_WIDTH                   2
+#define SGTL5000_BIAS_R_off                     0x0
+#define SGTL5000_BIAS_R_2K                      0x1
+#define SGTL5000_BIAS_R_4k                      0x2
+#define SGTL5000_BIAS_R_8k                      0x3
+#define SGTL5000_BIAS_VOLT_MASK                 0x0070
+#define SGTL5000_BIAS_VOLT_SHIFT                4
+#define SGTL5000_BIAS_VOLT_WIDTH                3
+#define SGTL5000_MIC_GAIN_MASK                  0x0003
+#define SGTL5000_MIC_GAIN_SHIFT                 0
+#define SGTL5000_MIC_GAIN_WIDTH                 2
+
+/*
+ * SGTL5000_CHIP_LINE_OUT_CTRL
+ */
+#define SGTL5000_LINE_OUT_CURRENT_MASK          0x0f00
+#define SGTL5000_LINE_OUT_CURRENT_SHIFT         8
+#define SGTL5000_LINE_OUT_CURRENT_WIDTH         4
+#define SGTL5000_LINE_OUT_CURRENT_180u          0x0
+#define SGTL5000_LINE_OUT_CURRENT_270u          0x1
+#define SGTL5000_LINE_OUT_CURRENT_360u          0x3
+#define SGTL5000_LINE_OUT_CURRENT_450u          0x7
+#define SGTL5000_LINE_OUT_CURRENT_540u          0xf
+#define SGTL5000_LINE_OUT_GND_MASK              0x003f
+#define SGTL5000_LINE_OUT_GND_SHIFT             0
+#define SGTL5000_LINE_OUT_GND_WIDTH             6
+#define SGTL5000_LINE_OUT_GND_BASE              800     /* mv */
+#define SGTL5000_LINE_OUT_GND_STP               25
+#define SGTL5000_LINE_OUT_GND_MAX               0x23
+
+/*
+ * SGTL5000_CHIP_LINE_OUT_VOL
+ */
+#define SGTL5000_LINE_OUT_VOL_RIGHT_MASK        0x1f00
+#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT       8
+#define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH       5
+#define SGTL5000_LINE_OUT_VOL_LEFT_MASK         0x001f
+#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT        0
+#define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH        5
+
+/*
+ * SGTL5000_CHIP_ANA_POWER
+ */
+#define SGTL5000_DAC_STEREO                     0x4000
+#define SGTL5000_LINREG_SIMPLE_POWERUP          0x2000
+#define SGTL5000_STARTUP_POWERUP                0x1000
+#define SGTL5000_VDDC_CHRGPMP_POWERUP           0x0800
+#define SGTL5000_PLL_POWERUP                    0x0400
+#define SGTL5000_LINEREG_D_POWERUP              0x0200
+#define SGTL5000_VCOAMP_POWERUP                 0x0100
+#define SGTL5000_VAG_POWERUP                    0x0080
+#define SGTL5000_ADC_STEREO                     0x0040
+#define SGTL5000_REFTOP_POWERUP                 0x0020
+#define SGTL5000_HP_POWERUP                     0x0010
+#define SGTL5000_DAC_POWERUP                    0x0008
+#define SGTL5000_CAPLESS_HP_POWERUP             0x0004
+#define SGTL5000_ADC_POWERUP                    0x0002
+#define SGTL5000_LINE_OUT_POWERUP               0x0001
+
+/*
+ * SGTL5000_CHIP_PLL_CTRL
+ */
+#define SGTL5000_PLL_INT_DIV_MASK               0xf800
+#define SGTL5000_PLL_INT_DIV_SHIFT              11
+#define SGTL5000_PLL_INT_DIV_WIDTH              5
+#define SGTL5000_PLL_FRAC_DIV_MASK              0x0700
+#define SGTL5000_PLL_FRAC_DIV_SHIFT             0
+#define SGTL5000_PLL_FRAC_DIV_WIDTH             11
+
+/*
+ * SGTL5000_CHIP_CLK_TOP_CTRL
+ */
+#define SGTL5000_INT_OSC_EN                     0x0800
+#define SGTL5000_INPUT_FREQ_DIV2                0x0008
+
+/*
+ * SGTL5000_CHIP_ANA_STATUS
+ */
+#define SGTL5000_HP_LRSHORT                     0x0200
+#define SGTL5000_CAPLESS_SHORT                  0x0100
+#define SGTL5000_PLL_LOCKED                     0x0010
+
+/*
+ * SGTL5000_CHIP_SHORT_CTRL
+ */
+#define SGTL5000_LVLADJR_MASK                   0x7000
+#define SGTL5000_LVLADJR_SHIFT                  12
+#define SGTL5000_LVLADJR_WIDTH                  3
+#define SGTL5000_LVLADJL_MASK                   0x0700
+#define SGTL5000_LVLADJL_SHIFT                  8
+#define SGTL5000_LVLADJL_WIDTH                  3
+#define SGTL5000_LVLADJC_MASK                   0x0070
+#define SGTL5000_LVLADJC_SHIFT                  4
+#define SGTL5000_LVLADJC_WIDTH                  3
+#define SGTL5000_LR_SHORT_MOD_MASK              0x000c
+#define SGTL5000_LR_SHORT_MOD_SHIFT             2
+#define SGTL5000_LR_SHORT_MOD_WIDTH             2
+#define SGTL5000_CM_SHORT_MOD_MASK              0x0003
+#define SGTL5000_CM_SHORT_MOD_SHIFT             0
+#define SGTL5000_CM_SHORT_MOD_WIDTH             2
+
+/*
+ *SGTL5000_CHIP_ANA_TEST2
+ */
+#define SGTL5000_MONO_DAC                       0x1000
+
+/*
+ * SGTL5000_DAP_CTRL
+ */
+#define SGTL5000_DAP_MIX_EN                     0x0010
+#define SGTL5000_DAP_EN                         0x0001
+
+#define SGTL5000_SYSCLK                         0x00
+#define SGTL5000_LRCLK                          0x01
+
+#endif
diff --git a/sound/soc/codecs/sn95031.c b/sound/soc/codecs/sn95031.c
new file mode 100644
index 000000000000..84ffdebb8a8b
--- /dev/null
+++ b/sound/soc/codecs/sn95031.c
@@ -0,0 +1,944 @@
+/*
+ *  sn95031.c -  TI sn95031 Codec driver
+ *
+ *  Copyright (C) 2010 Intel Corp
+ *  Author: Vinod Koul <vinod.koul@intel.com>
+ *  Author: Harsha Priya <priya.harsha@intel.com>
+ *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include <asm/intel_scu_ipc.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <sound/jack.h>
+#include "sn95031.h"
+
+#define SN95031_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_44100)
+#define SN95031_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
+
+/* adc helper functions */
+
+/* enables mic bias voltage */
+static void sn95031_enable_mic_bias(struct snd_soc_codec *codec)
+{
+        snd_soc_write(codec, SN95031_VAUD, BIT(2)|BIT(1)|BIT(0));
+        snd_soc_update_bits(codec, SN95031_MICBIAS, BIT(2), BIT(2));
+}
+
+/* Enable/Disable the ADC depending on the argument */
+static void configure_adc(struct snd_soc_codec *sn95031_codec, int val)
+{
+        int value = snd_soc_read(sn95031_codec, SN95031_ADC1CNTL1);
+
+        if (val) {
+                /* Enable and start the ADC */
+                value |= (SN95031_ADC_ENBL | SN95031_ADC_START);
+                value &= (~SN95031_ADC_NO_LOOP);
+        } else {
+                /* Just stop the ADC */
+                value &= (~SN95031_ADC_START);
+        }
+        snd_soc_write(sn95031_codec, SN95031_ADC1CNTL1, value);
+}
+
+/*
+ * finds an empty channel for conversion
+ * If the ADC is not enabled then start using 0th channel
+ * itself. Otherwise find an empty channel by looking for a
+ * channel in which the stopbit is set to 1. returns the index
+ * of the first free channel if succeeds or an error code.
+ *
+ * Context: can sleep
+ *
+ */
+static int find_free_channel(struct snd_soc_codec *sn95031_codec)
+{
+        int ret = 0, i, value;
+
+        /* check whether ADC is enabled */
+        value = snd_soc_read(sn95031_codec, SN95031_ADC1CNTL1);
+
+        if ((value & SN95031_ADC_ENBL) == 0)
+                return 0;
+
+        /* ADC is already enabled; Looking for an empty channel */
+        for (i = 0; i < SN95031_ADC_CHANLS_MAX; i++) {
+                value = snd_soc_read(sn95031_codec,
+                                SN95031_ADC_CHNL_START_ADDR + i);
+                if (value & SN95031_STOPBIT_MASK) {
+                        ret = i;
+                        break;
+                }
+        }
+        return (ret > SN95031_ADC_LOOP_MAX) ? (-EINVAL) : ret;
+}
+
+/* Initialize the ADC for reading micbias values. Can sleep. */
+static int sn95031_initialize_adc(struct snd_soc_codec *sn95031_codec)
+{
+        int base_addr, chnl_addr;
+        int value;
+        static int channel_index;
+
+        /* Index of the first channel in which the stop bit is set */
+        channel_index = find_free_channel(sn95031_codec);
+        if (channel_index < 0) {
+                pr_err("No free ADC channels");
+                return channel_index;
+        }
+
+        base_addr = SN95031_ADC_CHNL_START_ADDR + channel_index;
+
+        if (!(channel_index == 0 || channel_index ==  SN95031_ADC_LOOP_MAX)) {
+                /* Reset stop bit for channels other than 0 and 12 */
+                value = snd_soc_read(sn95031_codec, base_addr);
+                /* Set the stop bit to zero */
+                snd_soc_write(sn95031_codec, base_addr, value & 0xEF);
+                /* Index of the first free channel */
+                base_addr++;
+                channel_index++;
+        }
+
+        /* Since this is the last channel, set the stop bit
+           to 1 by ORing the DIE_SENSOR_CODE with 0x10 */
+        snd_soc_write(sn95031_codec, base_addr,
+                                SN95031_AUDIO_DETECT_CODE | 0x10);
+
+        chnl_addr = SN95031_ADC_DATA_START_ADDR + 2 * channel_index;
+        pr_debug("mid_initialize : %x", chnl_addr);
+        configure_adc(sn95031_codec, 1);
+        return chnl_addr;
+}
+
+
+/* reads the ADC registers and gets the mic bias value in mV. */
+static unsigned int sn95031_get_mic_bias(struct snd_soc_codec *codec)
+{
+        u16 adc_adr = sn95031_initialize_adc(codec);
+        u16 adc_val1, adc_val2;
+        unsigned int mic_bias;
+
+        sn95031_enable_mic_bias(codec);
+
+        /* Enable the sound card for conversion before reading */
+        snd_soc_write(codec, SN95031_ADC1CNTL3, 0x05);
+        /* Re-toggle the RRDATARD bit */
+        snd_soc_write(codec, SN95031_ADC1CNTL3, 0x04);
+
+        /* Read the higher bits of data */
+        msleep(1000);
+        adc_val1 = snd_soc_read(codec, adc_adr);
+        adc_adr++;
+        adc_val2 = snd_soc_read(codec, adc_adr);
+
+        /* Adding lower two bits to the higher bits */
+        mic_bias = (adc_val1 << 2) + (adc_val2 & 3);
+        mic_bias = (mic_bias * SN95031_ADC_ONE_LSB_MULTIPLIER) / 1000;
+        pr_debug("mic bias = %dmV\n", mic_bias);
+        return mic_bias;
+}
+EXPORT_SYMBOL_GPL(sn95031_get_mic_bias);
+/*end - adc helper functions */
+
+static inline unsigned int sn95031_read(struct snd_soc_codec *codec,
+                        unsigned int reg)
+{
+        u8 value = 0;
+        int ret;
+
+        ret = intel_scu_ipc_ioread8(reg, &value);
+        if (ret)
+                pr_err("read of %x failed, err %d\n", reg, ret);
+        return value;
+
+}
+
+static inline int sn95031_write(struct snd_soc_codec *codec,
+                        unsigned int reg, unsigned int value)
+{
+        int ret;
+
+        ret = intel_scu_ipc_iowrite8(reg, value);
+        if (ret)
+                pr_err("write of %x failed, err %d\n", reg, ret);
+        return ret;
+}
+
+static int sn95031_set_vaud_bias(struct snd_soc_codec *codec,
+                enum snd_soc_bias_level level)
+{
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+
+        case SND_SOC_BIAS_PREPARE:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
+                        pr_debug("vaud_bias powering up pll\n");
+                        /* power up the pll */
+                        snd_soc_write(codec, SN95031_AUDPLLCTRL, BIT(5));
+                        /* enable pcm 2 */
+                        snd_soc_update_bits(codec, SN95031_PCM2C2,
+                                        BIT(0), BIT(0));
+                }
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        pr_debug("vaud_bias power up rail\n");
+                        /* power up the rail */
+                        snd_soc_write(codec, SN95031_VAUD,
+                                        BIT(2)|BIT(1)|BIT(0));
+                        msleep(1);
+                } else if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
+                        /* turn off pcm */
+                        pr_debug("vaud_bias power dn pcm\n");
+                        snd_soc_update_bits(codec, SN95031_PCM2C2, BIT(0), 0);
+                        snd_soc_write(codec, SN95031_AUDPLLCTRL, 0);
+                }
+                break;
+
+
+        case SND_SOC_BIAS_OFF:
+                pr_debug("vaud_bias _OFF doing rail shutdown\n");
+                snd_soc_write(codec, SN95031_VAUD, BIT(3));
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+static int sn95031_vhs_event(struct snd_soc_dapm_widget *w,
+                    struct snd_kcontrol *kcontrol, int event)
+{
+        if (SND_SOC_DAPM_EVENT_ON(event)) {
+                pr_debug("VHS SND_SOC_DAPM_EVENT_ON doing rail startup now\n");
+                /* power up the rail */
+                snd_soc_write(w->codec, SN95031_VHSP, 0x3D);
+                snd_soc_write(w->codec, SN95031_VHSN, 0x3F);
+                msleep(1);
+        } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
+                pr_debug("VHS SND_SOC_DAPM_EVENT_OFF doing rail shutdown\n");
+                snd_soc_write(w->codec, SN95031_VHSP, 0xC4);
+                snd_soc_write(w->codec, SN95031_VHSN, 0x04);
+        }
+        return 0;
+}
+
+static int sn95031_vihf_event(struct snd_soc_dapm_widget *w,
+                    struct snd_kcontrol *kcontrol, int event)
+{
+        if (SND_SOC_DAPM_EVENT_ON(event)) {
+                pr_debug("VIHF SND_SOC_DAPM_EVENT_ON doing rail startup now\n");
+                /* power up the rail */
+                snd_soc_write(w->codec, SN95031_VIHF, 0x27);
+                msleep(1);
+        } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
+                pr_debug("VIHF SND_SOC_DAPM_EVENT_OFF doing rail shutdown\n");
+                snd_soc_write(w->codec, SN95031_VIHF, 0x24);
+        }
+        return 0;
+}
+
+static int sn95031_dmic12_event(struct snd_soc_dapm_widget *w,
+                        struct snd_kcontrol *k, int event)
+{
+        unsigned int ldo = 0, clk_dir = 0, data_dir = 0;
+
+        if (SND_SOC_DAPM_EVENT_ON(event)) {
+                ldo = BIT(5)|BIT(4);
+                clk_dir = BIT(0);
+                data_dir = BIT(7);
+        }
+        /* program DMIC LDO, clock and set clock */
+        snd_soc_update_bits(w->codec, SN95031_MICBIAS, BIT(5)|BIT(4), ldo);
+        snd_soc_update_bits(w->codec, SN95031_DMICBUF0123, BIT(0), clk_dir);
+        snd_soc_update_bits(w->codec, SN95031_DMICBUF0123, BIT(7), data_dir);
+        return 0;
+}
+
+static int sn95031_dmic34_event(struct snd_soc_dapm_widget *w,
+                        struct snd_kcontrol *k, int event)
+{
+        unsigned int ldo = 0, clk_dir = 0, data_dir = 0;
+
+        if (SND_SOC_DAPM_EVENT_ON(event)) {
+                ldo = BIT(5)|BIT(4);
+                clk_dir = BIT(2);
+                data_dir = BIT(1);
+        }
+        /* program DMIC LDO, clock and set clock */
+        snd_soc_update_bits(w->codec, SN95031_MICBIAS, BIT(5)|BIT(4), ldo);
+        snd_soc_update_bits(w->codec, SN95031_DMICBUF0123, BIT(2), clk_dir);
+        snd_soc_update_bits(w->codec, SN95031_DMICBUF45, BIT(1), data_dir);
+        return 0;
+}
+
+static int sn95031_dmic56_event(struct snd_soc_dapm_widget *w,
+                        struct snd_kcontrol *k, int event)
+{
+        unsigned int ldo = 0;
+
+        if (SND_SOC_DAPM_EVENT_ON(event))
+                ldo = BIT(7)|BIT(6);
+
+        /* program DMIC LDO */
+        snd_soc_update_bits(w->codec, SN95031_MICBIAS, BIT(7)|BIT(6), ldo);
+        return 0;
+}
+
+/* mux controls */
+static const char *sn95031_mic_texts[] = { "AMIC", "LineIn" };
+
+static const struct soc_enum sn95031_micl_enum =
+        SOC_ENUM_SINGLE(SN95031_ADCCONFIG, 1, 2, sn95031_mic_texts);
+
+static const struct snd_kcontrol_new sn95031_micl_mux_control =
+        SOC_DAPM_ENUM("Route", sn95031_micl_enum);
+
+static const struct soc_enum sn95031_micr_enum =
+        SOC_ENUM_SINGLE(SN95031_ADCCONFIG, 3, 2, sn95031_mic_texts);
+
+static const struct snd_kcontrol_new sn95031_micr_mux_control =
+        SOC_DAPM_ENUM("Route", sn95031_micr_enum);
+
+static const char *sn95031_input_texts[] = {    "DMIC1", "DMIC2", "DMIC3",
+                                                "DMIC4", "DMIC5", "DMIC6",
+                                                "ADC Left", "ADC Right" };
+
+static const struct soc_enum sn95031_input1_enum =
+        SOC_ENUM_SINGLE(SN95031_AUDIOMUX12, 0, 8, sn95031_input_texts);
+
+static const struct snd_kcontrol_new sn95031_input1_mux_control =
+        SOC_DAPM_ENUM("Route", sn95031_input1_enum);
+
+static const struct soc_enum sn95031_input2_enum =
+        SOC_ENUM_SINGLE(SN95031_AUDIOMUX12, 4, 8, sn95031_input_texts);
+
+static const struct snd_kcontrol_new sn95031_input2_mux_control =
+        SOC_DAPM_ENUM("Route", sn95031_input2_enum);
+
+static const struct soc_enum sn95031_input3_enum =
+        SOC_ENUM_SINGLE(SN95031_AUDIOMUX34, 0, 8, sn95031_input_texts);
+
+static const struct snd_kcontrol_new sn95031_input3_mux_control =
+        SOC_DAPM_ENUM("Route", sn95031_input3_enum);
+
+static const struct soc_enum sn95031_input4_enum =
+        SOC_ENUM_SINGLE(SN95031_AUDIOMUX34, 4, 8, sn95031_input_texts);
+
+static const struct snd_kcontrol_new sn95031_input4_mux_control =
+        SOC_DAPM_ENUM("Route", sn95031_input4_enum);
+
+/* capture path controls */
+
+static const char *sn95031_micmode_text[] = {"Single Ended", "Differential"};
+
+/* 0dB to 30dB in 10dB steps */
+static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 10, 0);
+
+static const struct soc_enum sn95031_micmode1_enum =
+        SOC_ENUM_SINGLE(SN95031_MICAMP1, 1, 2, sn95031_micmode_text);
+static const struct soc_enum sn95031_micmode2_enum =
+        SOC_ENUM_SINGLE(SN95031_MICAMP2, 1, 2, sn95031_micmode_text);
+
+static const char *sn95031_dmic_cfg_text[] = {"GPO", "DMIC"};
+
+static const struct soc_enum sn95031_dmic12_cfg_enum =
+        SOC_ENUM_SINGLE(SN95031_DMICMUX, 0, 2, sn95031_dmic_cfg_text);
+static const struct soc_enum sn95031_dmic34_cfg_enum =
+        SOC_ENUM_SINGLE(SN95031_DMICMUX, 1, 2, sn95031_dmic_cfg_text);
+static const struct soc_enum sn95031_dmic56_cfg_enum =
+        SOC_ENUM_SINGLE(SN95031_DMICMUX, 2, 2, sn95031_dmic_cfg_text);
+
+static const struct snd_kcontrol_new sn95031_snd_controls[] = {
+        SOC_ENUM("Mic1Mode Capture Route", sn95031_micmode1_enum),
+        SOC_ENUM("Mic2Mode Capture Route", sn95031_micmode2_enum),
+        SOC_ENUM("DMIC12 Capture Route", sn95031_dmic12_cfg_enum),
+        SOC_ENUM("DMIC34 Capture Route", sn95031_dmic34_cfg_enum),
+        SOC_ENUM("DMIC56 Capture Route", sn95031_dmic56_cfg_enum),
+        SOC_SINGLE_TLV("Mic1 Capture Volume", SN95031_MICAMP1,
+                        2, 4, 0, mic_tlv),
+        SOC_SINGLE_TLV("Mic2 Capture Volume", SN95031_MICAMP2,
+                        2, 4, 0, mic_tlv),
+};
+
+/* DAPM widgets */
+static const struct snd_soc_dapm_widget sn95031_dapm_widgets[] = {
+
+        /* all end points mic, hs etc */
+        SND_SOC_DAPM_OUTPUT("HPOUTL"),
+        SND_SOC_DAPM_OUTPUT("HPOUTR"),
+        SND_SOC_DAPM_OUTPUT("EPOUT"),
+        SND_SOC_DAPM_OUTPUT("IHFOUTL"),
+        SND_SOC_DAPM_OUTPUT("IHFOUTR"),
+        SND_SOC_DAPM_OUTPUT("LINEOUTL"),
+        SND_SOC_DAPM_OUTPUT("LINEOUTR"),
+        SND_SOC_DAPM_OUTPUT("VIB1OUT"),
+        SND_SOC_DAPM_OUTPUT("VIB2OUT"),
+
+        SND_SOC_DAPM_INPUT("AMIC1"), /* headset mic */
+        SND_SOC_DAPM_INPUT("AMIC2"),
+        SND_SOC_DAPM_INPUT("DMIC1"),
+        SND_SOC_DAPM_INPUT("DMIC2"),
+        SND_SOC_DAPM_INPUT("DMIC3"),
+        SND_SOC_DAPM_INPUT("DMIC4"),
+        SND_SOC_DAPM_INPUT("DMIC5"),
+        SND_SOC_DAPM_INPUT("DMIC6"),
+        SND_SOC_DAPM_INPUT("LINEINL"),
+        SND_SOC_DAPM_INPUT("LINEINR"),
+
+        SND_SOC_DAPM_MICBIAS("AMIC1Bias", SN95031_MICBIAS, 2, 0),
+        SND_SOC_DAPM_MICBIAS("AMIC2Bias", SN95031_MICBIAS, 3, 0),
+        SND_SOC_DAPM_MICBIAS("DMIC12Bias", SN95031_DMICMUX, 3, 0),
+        SND_SOC_DAPM_MICBIAS("DMIC34Bias", SN95031_DMICMUX, 4, 0),
+        SND_SOC_DAPM_MICBIAS("DMIC56Bias", SN95031_DMICMUX, 5, 0),
+
+        SND_SOC_DAPM_SUPPLY("DMIC12supply", SN95031_DMICLK, 0, 0,
+                                sn95031_dmic12_event,
+                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+        SND_SOC_DAPM_SUPPLY("DMIC34supply", SN95031_DMICLK, 1, 0,
+                                sn95031_dmic34_event,
+                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+        SND_SOC_DAPM_SUPPLY("DMIC56supply", SN95031_DMICLK, 2, 0,
+                                sn95031_dmic56_event,
+                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+        SND_SOC_DAPM_AIF_OUT("PCM_Out", "Capture", 0,
+                        SND_SOC_NOPM, 0, 0),
+
+        SND_SOC_DAPM_SUPPLY("Headset Rail", SND_SOC_NOPM, 0, 0,
+                        sn95031_vhs_event,
+                        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+        SND_SOC_DAPM_SUPPLY("Speaker Rail", SND_SOC_NOPM, 0, 0,
+                        sn95031_vihf_event,
+                        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+        /* playback path driver enables */
+        SND_SOC_DAPM_PGA("Headset Left Playback",
+                        SN95031_DRIVEREN, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Headset Right Playback",
+                        SN95031_DRIVEREN, 1, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Speaker Left Playback",
+                        SN95031_DRIVEREN, 2, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Speaker Right Playback",
+                        SN95031_DRIVEREN, 3, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Vibra1 Playback",
+                        SN95031_DRIVEREN, 4, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Vibra2 Playback",
+                        SN95031_DRIVEREN, 5, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Earpiece Playback",
+                        SN95031_DRIVEREN, 6, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Lineout Left Playback",
+                        SN95031_LOCTL, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Lineout Right Playback",
+                        SN95031_LOCTL, 4, 0, NULL, 0),
+
+        /* playback path filter enable */
+        SND_SOC_DAPM_PGA("Headset Left Filter",
+                        SN95031_HSEPRXCTRL, 4, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Headset Right Filter",
+                        SN95031_HSEPRXCTRL, 5, 0,  NULL, 0),
+        SND_SOC_DAPM_PGA("Speaker Left Filter",
+                        SN95031_IHFRXCTRL, 0, 0,  NULL, 0),
+        SND_SOC_DAPM_PGA("Speaker Right Filter",
+                        SN95031_IHFRXCTRL, 1, 0,  NULL, 0),
+
+        /* DACs */
+        SND_SOC_DAPM_DAC("HSDAC Left", "Headset",
+                        SN95031_DACCONFIG, 0, 0),
+        SND_SOC_DAPM_DAC("HSDAC Right", "Headset",
+                        SN95031_DACCONFIG, 1, 0),
+        SND_SOC_DAPM_DAC("IHFDAC Left", "Speaker",
+                        SN95031_DACCONFIG, 2, 0),
+        SND_SOC_DAPM_DAC("IHFDAC Right", "Speaker",
+                        SN95031_DACCONFIG, 3, 0),
+        SND_SOC_DAPM_DAC("Vibra1 DAC", "Vibra1",
+                        SN95031_VIB1C5, 1, 0),
+        SND_SOC_DAPM_DAC("Vibra2 DAC", "Vibra2",
+                        SN95031_VIB2C5, 1, 0),
+
+        /* capture widgets */
+        SND_SOC_DAPM_PGA("LineIn Enable Left", SN95031_MICAMP1,
+                                7, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("LineIn Enable Right", SN95031_MICAMP2,
+                                7, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA("MIC1 Enable", SN95031_MICAMP1, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("MIC2 Enable", SN95031_MICAMP2, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("TX1 Enable", SN95031_AUDIOTXEN, 2, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("TX2 Enable", SN95031_AUDIOTXEN, 3, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("TX3 Enable", SN95031_AUDIOTXEN, 4, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("TX4 Enable", SN95031_AUDIOTXEN, 5, 0, NULL, 0),
+
+        /* ADC have null stream as they will be turned ON by TX path */
+        SND_SOC_DAPM_ADC("ADC Left", NULL,
+                        SN95031_ADCCONFIG, 0, 0),
+        SND_SOC_DAPM_ADC("ADC Right", NULL,
+                        SN95031_ADCCONFIG, 2, 0),
+
+        SND_SOC_DAPM_MUX("Mic_InputL Capture Route",
+                        SND_SOC_NOPM, 0, 0, &sn95031_micl_mux_control),
+        SND_SOC_DAPM_MUX("Mic_InputR Capture Route",
+                        SND_SOC_NOPM, 0, 0, &sn95031_micr_mux_control),
+
+        SND_SOC_DAPM_MUX("Txpath1 Capture Route",
+                        SND_SOC_NOPM, 0, 0, &sn95031_input1_mux_control),
+        SND_SOC_DAPM_MUX("Txpath2 Capture Route",
+                        SND_SOC_NOPM, 0, 0, &sn95031_input2_mux_control),
+        SND_SOC_DAPM_MUX("Txpath3 Capture Route",
+                        SND_SOC_NOPM, 0, 0, &sn95031_input3_mux_control),
+        SND_SOC_DAPM_MUX("Txpath4 Capture Route",
+                        SND_SOC_NOPM, 0, 0, &sn95031_input4_mux_control),
+
+};
+
+static const struct snd_soc_dapm_route sn95031_audio_map[] = {
+        /* headset and earpiece map */
+        { "HPOUTL", NULL, "Headset Rail"},
+        { "HPOUTR", NULL, "Headset Rail"},
+        { "HPOUTL", NULL, "Headset Left Playback" },
+        { "HPOUTR", NULL, "Headset Right Playback" },
+        { "EPOUT", NULL, "Earpiece Playback" },
+        { "Headset Left Playback", NULL, "Headset Left Filter"},
+        { "Headset Right Playback", NULL, "Headset Right Filter"},
+        { "Earpiece Playback", NULL, "Headset Left Filter"},
+        { "Headset Left Filter", NULL, "HSDAC Left"},
+        { "Headset Right Filter", NULL, "HSDAC Right"},
+
+        /* speaker map */
+        { "IHFOUTL", NULL, "Speaker Rail"},
+        { "IHFOUTR", NULL, "Speaker Rail"},
+        { "IHFOUTL", "NULL", "Speaker Left Playback"},
+        { "IHFOUTR", "NULL", "Speaker Right Playback"},
+        { "Speaker Left Playback", NULL, "Speaker Left Filter"},
+        { "Speaker Right Playback", NULL, "Speaker Right Filter"},
+        { "Speaker Left Filter", NULL, "IHFDAC Left"},
+        { "Speaker Right Filter", NULL, "IHFDAC Right"},
+
+        /* vibra map */
+        { "VIB1OUT", NULL, "Vibra1 Playback"},
+        { "Vibra1 Playback", NULL, "Vibra1 DAC"},
+
+        { "VIB2OUT", NULL, "Vibra2 Playback"},
+        { "Vibra2 Playback", NULL, "Vibra2 DAC"},
+
+        /* lineout */
+        { "LINEOUTL", NULL, "Lineout Left Playback"},
+        { "LINEOUTR", NULL, "Lineout Right Playback"},
+        { "Lineout Left Playback", NULL, "Headset Left Filter"},
+        { "Lineout Left Playback", NULL, "Speaker Left Filter"},
+        { "Lineout Left Playback", NULL, "Vibra1 DAC"},
+        { "Lineout Right Playback", NULL, "Headset Right Filter"},
+        { "Lineout Right Playback", NULL, "Speaker Right Filter"},
+        { "Lineout Right Playback", NULL, "Vibra2 DAC"},
+
+        /* Headset (AMIC1) mic */
+        { "AMIC1Bias", NULL, "AMIC1"},
+        { "MIC1 Enable", NULL, "AMIC1Bias"},
+        { "Mic_InputL Capture Route", "AMIC", "MIC1 Enable"},
+
+        /* AMIC2 */
+        { "AMIC2Bias", NULL, "AMIC2"},
+        { "MIC2 Enable", NULL, "AMIC2Bias"},
+        { "Mic_InputR Capture Route", "AMIC", "MIC2 Enable"},
+
+
+        /* Linein */
+        { "LineIn Enable Left", NULL, "LINEINL"},
+        { "LineIn Enable Right", NULL, "LINEINR"},
+        { "Mic_InputL Capture Route", "LineIn", "LineIn Enable Left"},
+        { "Mic_InputR Capture Route", "LineIn", "LineIn Enable Right"},
+
+        /* ADC connection */
+        { "ADC Left", NULL, "Mic_InputL Capture Route"},
+        { "ADC Right", NULL, "Mic_InputR Capture Route"},
+
+        /*DMIC connections */
+        { "DMIC1", NULL, "DMIC12supply"},
+        { "DMIC2", NULL, "DMIC12supply"},
+        { "DMIC3", NULL, "DMIC34supply"},
+        { "DMIC4", NULL, "DMIC34supply"},
+        { "DMIC5", NULL, "DMIC56supply"},
+        { "DMIC6", NULL, "DMIC56supply"},
+
+        { "DMIC12Bias", NULL, "DMIC1"},
+        { "DMIC12Bias", NULL, "DMIC2"},
+        { "DMIC34Bias", NULL, "DMIC3"},
+        { "DMIC34Bias", NULL, "DMIC4"},
+        { "DMIC56Bias", NULL, "DMIC5"},
+        { "DMIC56Bias", NULL, "DMIC6"},
+
+        /*TX path inputs*/
+        { "Txpath1 Capture Route", "ADC Left", "ADC Left"},
+        { "Txpath2 Capture Route", "ADC Left", "ADC Left"},
+        { "Txpath3 Capture Route", "ADC Left", "ADC Left"},
+        { "Txpath4 Capture Route", "ADC Left", "ADC Left"},
+        { "Txpath1 Capture Route", "ADC Right", "ADC Right"},
+        { "Txpath2 Capture Route", "ADC Right", "ADC Right"},
+        { "Txpath3 Capture Route", "ADC Right", "ADC Right"},
+        { "Txpath4 Capture Route", "ADC Right", "ADC Right"},
+        { "Txpath1 Capture Route", "DMIC1", "DMIC1"},
+        { "Txpath2 Capture Route", "DMIC1", "DMIC1"},
+        { "Txpath3 Capture Route", "DMIC1", "DMIC1"},
+        { "Txpath4 Capture Route", "DMIC1", "DMIC1"},
+        { "Txpath1 Capture Route", "DMIC2", "DMIC2"},
+        { "Txpath2 Capture Route", "DMIC2", "DMIC2"},
+        { "Txpath3 Capture Route", "DMIC2", "DMIC2"},
+        { "Txpath4 Capture Route", "DMIC2", "DMIC2"},
+        { "Txpath1 Capture Route", "DMIC3", "DMIC3"},
+        { "Txpath2 Capture Route", "DMIC3", "DMIC3"},
+        { "Txpath3 Capture Route", "DMIC3", "DMIC3"},
+        { "Txpath4 Capture Route", "DMIC3", "DMIC3"},
+        { "Txpath1 Capture Route", "DMIC4", "DMIC4"},
+        { "Txpath2 Capture Route", "DMIC4", "DMIC4"},
+        { "Txpath3 Capture Route", "DMIC4", "DMIC4"},
+        { "Txpath4 Capture Route", "DMIC4", "DMIC4"},
+        { "Txpath1 Capture Route", "DMIC5", "DMIC5"},
+        { "Txpath2 Capture Route", "DMIC5", "DMIC5"},
+        { "Txpath3 Capture Route", "DMIC5", "DMIC5"},
+        { "Txpath4 Capture Route", "DMIC5", "DMIC5"},
+        { "Txpath1 Capture Route", "DMIC6", "DMIC6"},
+        { "Txpath2 Capture Route", "DMIC6", "DMIC6"},
+        { "Txpath3 Capture Route", "DMIC6", "DMIC6"},
+        { "Txpath4 Capture Route", "DMIC6", "DMIC6"},
+
+        /* tx path */
+        { "TX1 Enable", NULL, "Txpath1 Capture Route"},
+        { "TX2 Enable", NULL, "Txpath2 Capture Route"},
+        { "TX3 Enable", NULL, "Txpath3 Capture Route"},
+        { "TX4 Enable", NULL, "Txpath4 Capture Route"},
+        { "PCM_Out", NULL, "TX1 Enable"},
+        { "PCM_Out", NULL, "TX2 Enable"},
+        { "PCM_Out", NULL, "TX3 Enable"},
+        { "PCM_Out", NULL, "TX4 Enable"},
+
+};
+
+/* speaker and headset mutes, for audio pops and clicks */
+static int sn95031_pcm_hs_mute(struct snd_soc_dai *dai, int mute)
+{
+        snd_soc_update_bits(dai->codec,
+                        SN95031_HSLVOLCTRL, BIT(7), (!mute << 7));
+        snd_soc_update_bits(dai->codec,
+                        SN95031_HSRVOLCTRL, BIT(7), (!mute << 7));
+        return 0;
+}
+
+static int sn95031_pcm_spkr_mute(struct snd_soc_dai *dai, int mute)
+{
+        snd_soc_update_bits(dai->codec,
+                        SN95031_IHFLVOLCTRL, BIT(7), (!mute << 7));
+        snd_soc_update_bits(dai->codec,
+                        SN95031_IHFRVOLCTRL, BIT(7), (!mute << 7));
+        return 0;
+}
+
+int sn95031_pcm_hw_params(struct snd_pcm_substream *substream,
+                struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+        unsigned int format, rate;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                format = BIT(4)|BIT(5);
+                break;
+
+        case SNDRV_PCM_FORMAT_S24_LE:
+                format = 0;
+                break;
+        default:
+                return -EINVAL;
+        }
+        snd_soc_update_bits(dai->codec, SN95031_PCM2C2,
+                        BIT(4)|BIT(5), format);
+
+        switch (params_rate(params)) {
+        case 48000:
+                pr_debug("RATE_48000\n");
+                rate = 0;
+                break;
+
+        case 44100:
+                pr_debug("RATE_44100\n");
+                rate = BIT(7);
+                break;
+
+        default:
+                pr_err("ERR rate %d\n", params_rate(params));
+                return -EINVAL;
+        }
+        snd_soc_update_bits(dai->codec, SN95031_PCM1C1, BIT(7), rate);
+
+        return 0;
+}
+
+/* Codec DAI section */
+static struct snd_soc_dai_ops sn95031_headset_dai_ops = {
+        .digital_mute   = sn95031_pcm_hs_mute,
+        .hw_params      = sn95031_pcm_hw_params,
+};
+
+static struct snd_soc_dai_ops sn95031_speaker_dai_ops = {
+        .digital_mute   = sn95031_pcm_spkr_mute,
+        .hw_params      = sn95031_pcm_hw_params,
+};
+
+static struct snd_soc_dai_ops sn95031_vib1_dai_ops = {
+        .hw_params      = sn95031_pcm_hw_params,
+};
+
+static struct snd_soc_dai_ops sn95031_vib2_dai_ops = {
+        .hw_params      = sn95031_pcm_hw_params,
+};
+
+struct snd_soc_dai_driver sn95031_dais[] = {
+{
+        .name = "SN95031 Headset",
+        .playback = {
+                .stream_name = "Headset",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SN95031_RATES,
+                .formats = SN95031_FORMATS,
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 1,
+                .channels_max = 5,
+                .rates = SN95031_RATES,
+                .formats = SN95031_FORMATS,
+        },
+        .ops = &sn95031_headset_dai_ops,
+},
+{       .name = "SN95031 Speaker",
+        .playback = {
+                .stream_name = "Speaker",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SN95031_RATES,
+                .formats = SN95031_FORMATS,
+        },
+        .ops = &sn95031_speaker_dai_ops,
+},
+{       .name = "SN95031 Vibra1",
+        .playback = {
+                .stream_name = "Vibra1",
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = SN95031_RATES,
+                .formats = SN95031_FORMATS,
+        },
+        .ops = &sn95031_vib1_dai_ops,
+},
+{       .name = "SN95031 Vibra2",
+        .playback = {
+                .stream_name = "Vibra2",
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = SN95031_RATES,
+                .formats = SN95031_FORMATS,
+        },
+        .ops = &sn95031_vib2_dai_ops,
+},
+};
+
+static inline void sn95031_disable_jack_btn(struct snd_soc_codec *codec)
+{
+        snd_soc_write(codec, SN95031_BTNCTRL2, 0x00);
+}
+
+static inline void sn95031_enable_jack_btn(struct snd_soc_codec *codec)
+{
+        snd_soc_write(codec, SN95031_BTNCTRL1, 0x77);
+        snd_soc_write(codec, SN95031_BTNCTRL2, 0x01);
+}
+
+static int sn95031_get_headset_state(struct snd_soc_jack *mfld_jack)
+{
+        int micbias = sn95031_get_mic_bias(mfld_jack->codec);
+
+        int jack_type = snd_soc_jack_get_type(mfld_jack, micbias);
+
+        pr_debug("jack type detected = %d\n", jack_type);
+        if (jack_type == SND_JACK_HEADSET)
+                sn95031_enable_jack_btn(mfld_jack->codec);
+        return jack_type;
+}
+
+void sn95031_jack_detection(struct mfld_jack_data *jack_data)
+{
+        unsigned int status;
+        unsigned int mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_HEADSET;
+
+        pr_debug("interrupt id read in sram = 0x%x\n", jack_data->intr_id);
+        if (jack_data->intr_id & 0x1) {
+                pr_debug("short_push detected\n");
+                status = SND_JACK_HEADSET | SND_JACK_BTN_0;
+        } else if (jack_data->intr_id & 0x2) {
+                pr_debug("long_push detected\n");
+                status = SND_JACK_HEADSET | SND_JACK_BTN_1;
+        } else if (jack_data->intr_id & 0x4) {
+                pr_debug("headset or headphones inserted\n");
+                status = sn95031_get_headset_state(jack_data->mfld_jack);
+        } else if (jack_data->intr_id & 0x8) {
+                pr_debug("headset or headphones removed\n");
+                status = 0;
+                sn95031_disable_jack_btn(jack_data->mfld_jack->codec);
+        } else {
+                pr_err("unidentified interrupt\n");
+                return;
+        }
+
+        snd_soc_jack_report(jack_data->mfld_jack, status, mask);
+        /*button pressed and released so we send explicit button release */
+        if ((status & SND_JACK_BTN_0) | (status & SND_JACK_BTN_1))
+                snd_soc_jack_report(jack_data->mfld_jack,
+                                SND_JACK_HEADSET, mask);
+}
+EXPORT_SYMBOL_GPL(sn95031_jack_detection);
+
+/* codec registration */
+static int sn95031_codec_probe(struct snd_soc_codec *codec)
+{
+        pr_debug("codec_probe called\n");
+
+        codec->dapm.bias_level = SND_SOC_BIAS_OFF;
+        codec->dapm.idle_bias_off = 1;
+
+        /* PCM interface config
+         * This sets the pcm rx slot conguration to max 6 slots
+         * for max 4 dais (2 stereo and 2 mono)
+         */
+        snd_soc_write(codec, SN95031_PCM2RXSLOT01, 0x10);
+        snd_soc_write(codec, SN95031_PCM2RXSLOT23, 0x32);
+        snd_soc_write(codec, SN95031_PCM2RXSLOT45, 0x54);
+        snd_soc_write(codec, SN95031_PCM2TXSLOT01, 0x10);
+        snd_soc_write(codec, SN95031_PCM2TXSLOT23, 0x32);
+        /* pcm port setting
+         * This sets the pcm port to slave and clock at 19.2Mhz which
+         * can support 6slots, sampling rate set per stream in hw-params
+         */
+        snd_soc_write(codec, SN95031_PCM1C1, 0x00);
+        snd_soc_write(codec, SN95031_PCM2C1, 0x01);
+        snd_soc_write(codec, SN95031_PCM2C2, 0x0A);
+        snd_soc_write(codec, SN95031_HSMIXER, BIT(0)|BIT(4));
+        /* vendor vibra workround, the vibras are muted by
+         * custom register so unmute them
+         */
+        snd_soc_write(codec, SN95031_SSR5, 0x80);
+        snd_soc_write(codec, SN95031_SSR6, 0x80);
+        snd_soc_write(codec, SN95031_VIB1C5, 0x00);
+        snd_soc_write(codec, SN95031_VIB2C5, 0x00);
+        /* configure vibras for pcm port */
+        snd_soc_write(codec, SN95031_VIB1C3, 0x00);
+        snd_soc_write(codec, SN95031_VIB2C3, 0x00);
+
+        /* soft mute ramp time */
+        snd_soc_write(codec, SN95031_SOFTMUTE, 0x3);
+        /* fix the initial volume at 1dB,
+         * default in +9dB,
+         * 1dB give optimal swing on DAC, amps
+         */
+        snd_soc_write(codec, SN95031_HSLVOLCTRL, 0x08);
+        snd_soc_write(codec, SN95031_HSRVOLCTRL, 0x08);
+        snd_soc_write(codec, SN95031_IHFLVOLCTRL, 0x08);
+        snd_soc_write(codec, SN95031_IHFRVOLCTRL, 0x08);
+        /* dac mode and lineout workaround */
+        snd_soc_write(codec, SN95031_SSR2, 0x10);
+        snd_soc_write(codec, SN95031_SSR3, 0x40);
+
+        snd_soc_add_controls(codec, sn95031_snd_controls,
+                             ARRAY_SIZE(sn95031_snd_controls));
+
+        return 0;
+}
+
+static int sn95031_codec_remove(struct snd_soc_codec *codec)
+{
+        pr_debug("codec_remove called\n");
+        sn95031_set_vaud_bias(codec, SND_SOC_BIAS_OFF);
+
+        return 0;
+}
+
+struct snd_soc_codec_driver sn95031_codec = {
+        .probe          = sn95031_codec_probe,
+        .remove         = sn95031_codec_remove,
+        .read           = sn95031_read,
+        .write          = sn95031_write,
+        .set_bias_level = sn95031_set_vaud_bias,
+        .dapm_widgets   = sn95031_dapm_widgets,
+        .num_dapm_widgets       = ARRAY_SIZE(sn95031_dapm_widgets),
+        .dapm_routes    = sn95031_audio_map,
+        .num_dapm_routes        = ARRAY_SIZE(sn95031_audio_map),
+};
+
+static int __devinit sn95031_device_probe(struct platform_device *pdev)
+{
+        pr_debug("codec device probe called for %s\n", dev_name(&pdev->dev));
+        return snd_soc_register_codec(&pdev->dev, &sn95031_codec,
+                        sn95031_dais, ARRAY_SIZE(sn95031_dais));
+}
+
+static int __devexit sn95031_device_remove(struct platform_device *pdev)
+{
+        pr_debug("codec device remove called\n");
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver sn95031_codec_driver = {
+        .driver         = {
+                .name           = "sn95031",
+                .owner          = THIS_MODULE,
+        },
+        .probe          = sn95031_device_probe,
+        .remove         = __devexit_p(sn95031_device_remove),
+};
+
+static int __init sn95031_init(void)
+{
+        pr_debug("driver init called\n");
+        return platform_driver_register(&sn95031_codec_driver);
+}
+module_init(sn95031_init);
+
+static void __exit sn95031_exit(void)
+{
+        pr_debug("driver exit called\n");
+        platform_driver_unregister(&sn95031_codec_driver);
+}
+module_exit(sn95031_exit);
+
+MODULE_DESCRIPTION("ASoC TI SN95031 codec driver");
+MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>");
+MODULE_AUTHOR("Harsha Priya <priya.harsha@intel.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:sn95031");
diff --git a/sound/soc/codecs/sn95031.h b/sound/soc/codecs/sn95031.h
new file mode 100644
index 000000000000..20376d234fb8
--- /dev/null
+++ b/sound/soc/codecs/sn95031.h
@@ -0,0 +1,132 @@
+/*
+ *  sn95031.h - TI sn95031 Codec driver
+ *
+ *  Copyright (C) 2010 Intel Corp
+ *  Author: Vinod Koul <vinod.koul@intel.com>
+ *  Author: Harsha Priya <priya.harsha@intel.com>
+ *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *
+ */
+#ifndef _SN95031_H
+#define _SN95031_H
+
+/*register map*/
+#define SN95031_VAUD                    0xDB
+#define SN95031_VHSP                    0xDC
+#define SN95031_VHSN                    0xDD
+#define SN95031_VIHF                    0xC9
+
+#define SN95031_AUDPLLCTRL              0x240
+#define SN95031_DMICBUF0123             0x241
+#define SN95031_DMICBUF45               0x242
+#define SN95031_DMICGPO                 0x244
+#define SN95031_DMICMUX                 0x245
+#define SN95031_DMICLK                  0x246
+#define SN95031_MICBIAS                 0x247
+#define SN95031_ADCCONFIG               0x248
+#define SN95031_MICAMP1                 0x249
+#define SN95031_MICAMP2                 0x24A
+#define SN95031_NOISEMUX                0x24B
+#define SN95031_AUDIOMUX12              0x24C
+#define SN95031_AUDIOMUX34              0x24D
+#define SN95031_AUDIOSINC               0x24E
+#define SN95031_AUDIOTXEN               0x24F
+#define SN95031_HSEPRXCTRL              0x250
+#define SN95031_IHFRXCTRL               0x251
+#define SN95031_HSMIXER                 0x256
+#define SN95031_DACCONFIG               0x257
+#define SN95031_SOFTMUTE                0x258
+#define SN95031_HSLVOLCTRL              0x259
+#define SN95031_HSRVOLCTRL              0x25A
+#define SN95031_IHFLVOLCTRL             0x25B
+#define SN95031_IHFRVOLCTRL             0x25C
+#define SN95031_DRIVEREN                0x25D
+#define SN95031_LOCTL                   0x25E
+#define SN95031_VIB1C1                  0x25F
+#define SN95031_VIB1C2                  0x260
+#define SN95031_VIB1C3                  0x261
+#define SN95031_VIB1SPIPCM1             0x262
+#define SN95031_VIB1SPIPCM2             0x263
+#define SN95031_VIB1C5                  0x264
+#define SN95031_VIB2C1                  0x265
+#define SN95031_VIB2C2                  0x266
+#define SN95031_VIB2C3                  0x267
+#define SN95031_VIB2SPIPCM1             0x268
+#define SN95031_VIB2SPIPCM2             0x269
+#define SN95031_VIB2C5                  0x26A
+#define SN95031_BTNCTRL1                0x26B
+#define SN95031_BTNCTRL2                0x26C
+#define SN95031_PCM1TXSLOT01            0x26D
+#define SN95031_PCM1TXSLOT23            0x26E
+#define SN95031_PCM1TXSLOT45            0x26F
+#define SN95031_PCM1RXSLOT0_3           0x270
+#define SN95031_PCM1RXSLOT45            0x271
+#define SN95031_PCM2TXSLOT01            0x272
+#define SN95031_PCM2TXSLOT23            0x273
+#define SN95031_PCM2TXSLOT45            0x274
+#define SN95031_PCM2RXSLOT01            0x275
+#define SN95031_PCM2RXSLOT23            0x276
+#define SN95031_PCM2RXSLOT45            0x277
+#define SN95031_PCM1C1                  0x278
+#define SN95031_PCM1C2                  0x279
+#define SN95031_PCM1C3                  0x27A
+#define SN95031_PCM2C1                  0x27B
+#define SN95031_PCM2C2                  0x27C
+/*end codec register defn*/
+
+/*vendor defn these are not part of avp*/
+#define SN95031_SSR2                    0x381
+#define SN95031_SSR3                    0x382
+#define SN95031_SSR5                    0x384
+#define SN95031_SSR6                    0x385
+
+/* ADC registers */
+
+#define SN95031_ADC1CNTL1 0x1C0
+#define SN95031_ADC_ENBL 0x10
+#define SN95031_ADC_START 0x08
+#define SN95031_ADC1CNTL3 0x1C2
+#define SN95031_ADCTHERM_ENBL 0x04
+#define SN95031_ADCRRDATA_ENBL 0x05
+#define SN95031_STOPBIT_MASK 16
+#define SN95031_ADCTHERM_MASK 4
+#define SN95031_ADC_CHANLS_MAX 15 /* Number of ADC channels */
+#define SN95031_ADC_LOOP_MAX (SN95031_ADC_CHANLS_MAX - 1)
+#define SN95031_ADC_NO_LOOP 0x07
+#define SN95031_AUDIO_GPIO_CTRL 0x070
+
+/* ADC channel code values */
+#define SN95031_AUDIO_DETECT_CODE 0x06
+
+/* ADC base addresses */
+#define SN95031_ADC_CHNL_START_ADDR 0x1C5 /* increments by 1 */
+#define SN95031_ADC_DATA_START_ADDR 0x1D4  /* increments by 2 */
+/* multipier to convert to mV */
+#define SN95031_ADC_ONE_LSB_MULTIPLIER 2346
+
+
+struct mfld_jack_data {
+        int intr_id;
+        int micbias_vol;
+        struct snd_soc_jack *mfld_jack;
+};
+
+extern void sn95031_jack_detection(struct mfld_jack_data *jack_data);
+
+#endif
diff --git a/sound/soc/codecs/spdif_transciever.c b/sound/soc/codecs/spdif_transciever.c
index 9119836051a4..6a1a7e705cd7 100644
--- a/sound/soc/codecs/spdif_transciever.c
+++ b/sound/soc/codecs/spdif_transciever.c
@@ -21,57 +21,16 @@
 #include <sound/pcm.h>
 #include <sound/initval.h>
 
-#include "spdif_transciever.h"
-
-MODULE_LICENSE("GPL");
+#define DRV_NAME "spdif-dit"
 
 #define STUB_RATES      SNDRV_PCM_RATE_8000_96000
 #define STUB_FORMATS    SNDRV_PCM_FMTBIT_S16_LE
 
-static struct snd_soc_codec *spdif_dit_codec;
-
-static int spdif_dit_codec_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret;
-
-        if (spdif_dit_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = spdif_dit_codec;
-        codec = spdif_dit_codec;
-
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto err_create_pcms;
-        }
-
-        return 0;
-
-err_create_pcms:
-        return ret;
-}
-
-static int spdif_dit_codec_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-
-        return 0;
-}
 
-struct snd_soc_codec_device soc_codec_dev_spdif_dit = {
-        .probe          = spdif_dit_codec_probe,
-        .remove         = spdif_dit_codec_remove,
-}; EXPORT_SYMBOL_GPL(soc_codec_dev_spdif_dit);
+static struct snd_soc_codec_driver soc_codec_spdif_dit;
 
-struct snd_soc_dai dit_stub_dai = {
-        .name           = "DIT",
+static struct snd_soc_dai_driver dit_stub_dai = {
+        .name           = "dit-hifi",
         .playback       = {
                 .stream_name    = "Playback",
                 .channels_min   = 1,
@@ -80,65 +39,16 @@ struct snd_soc_dai dit_stub_dai = {
                 .formats        = STUB_FORMATS,
         },
 };
-EXPORT_SYMBOL_GPL(dit_stub_dai);
 
 static int spdif_dit_probe(struct platform_device *pdev)
 {
-        struct snd_soc_codec *codec;
-        int ret;
-
-        if (spdif_dit_codec) {
-                dev_err(&pdev->dev, "Another Codec is registered\n");
-                ret = -EINVAL;
-                goto err_reg_codec;
-        }
-
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-
-        codec->dev = &pdev->dev;
-
-        mutex_init(&codec->mutex);
-
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "spdif-dit";
-        codec->owner = THIS_MODULE;
-        codec->dai = &dit_stub_dai;
-        codec->num_dai = 1;
-
-        spdif_dit_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err_reg_codec;
-        }
-
-        dit_stub_dai.dev = &pdev->dev;
-        ret = snd_soc_register_dai(&dit_stub_dai);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to register dai: %d\n", ret);
-                goto err_reg_dai;
-        }
-
-        return 0;
-
-err_reg_dai:
-        snd_soc_unregister_codec(codec);
-err_reg_codec:
-        kfree(spdif_dit_codec);
-        return ret;
+        return snd_soc_register_codec(&pdev->dev, &soc_codec_spdif_dit,
+                        &dit_stub_dai, 1);
 }
 
 static int spdif_dit_remove(struct platform_device *pdev)
 {
-        snd_soc_unregister_dai(&dit_stub_dai);
-        snd_soc_unregister_codec(spdif_dit_codec);
-        kfree(spdif_dit_codec);
-        spdif_dit_codec = NULL;
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
@@ -146,7 +56,7 @@ static struct platform_driver spdif_dit_driver = {
         .probe          = spdif_dit_probe,
         .remove         = spdif_dit_remove,
         .driver         = {
-                .name   = "spdif-dit",
+                .name   = DRV_NAME,
                 .owner  = THIS_MODULE,
         },
 };
@@ -164,3 +74,7 @@ static void __exit dit_exit(void)
 module_init(dit_modinit);
 module_exit(dit_exit);
 
+MODULE_AUTHOR("Steve Chen <schen@mvista.com>");
+MODULE_DESCRIPTION("SPDIF dummy codec driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/codecs/spdif_transciever.h b/sound/soc/codecs/spdif_transciever.h
deleted file mode 100644
index 1e102124f546..000000000000
--- a/sound/soc/codecs/spdif_transciever.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * ALSA SoC DIT/DIR driver header
- *
- * Author:      Steve Chen,  <schen@mvista.com>
- * Copyright:   (C) 2008 MontaVista Software, Inc., <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef CODEC_STUBS_H
-#define CODEC_STUBS_H
-
-extern struct snd_soc_codec_device soc_codec_dev_spdif_dit;
-extern struct snd_soc_dai dit_stub_dai;
-
-#endif /* CODEC_STUBS_H */
diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c
index b47ed4f6ab20..84f4ad568556 100644
--- a/sound/soc/codecs/ssm2602.c
+++ b/sound/soc/codecs/ssm2602.c
@@ -32,26 +32,33 @@
 #include <linux/delay.h>
 #include <linux/pm.h>
 #include <linux/i2c.h>
+#include <linux/spi/spi.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
+#include <sound/tlv.h>
 
 #include "ssm2602.h"
 
 #define SSM2602_VERSION "0.1"
 
-struct snd_soc_codec_device soc_codec_dev_ssm2602;
+enum ssm2602_type {
+        SSM2602,
+        SSM2604,
+};
 
 /* codec private data */
 struct ssm2602_priv {
         unsigned int sysclk;
+        enum snd_soc_control_type control_type;
         struct snd_pcm_substream *master_substream;
         struct snd_pcm_substream *slave_substream;
+
+        enum ssm2602_type type;
 };
 
 /*
@@ -61,60 +68,12 @@ struct ssm2602_priv {
  * There is no point in caching the reset register
  */
 static const u16 ssm2602_reg[SSM2602_CACHEREGNUM] = {
-        0x0017, 0x0017, 0x0079, 0x0079,
-        0x0000, 0x0000, 0x0000, 0x000a,
+        0x0097, 0x0097, 0x0079, 0x0079,
+        0x000a, 0x0008, 0x009f, 0x000a,
         0x0000, 0x0000
 };
 
-/*
- * read ssm2602 register cache
- */
-static inline unsigned int ssm2602_read_reg_cache(struct snd_soc_codec *codec,
-        unsigned int reg)
-{
-        u16 *cache = codec->reg_cache;
-        if (reg == SSM2602_RESET)
-                return 0;
-        if (reg >= SSM2602_CACHEREGNUM)
-                return -1;
-        return cache[reg];
-}
-
-/*
- * write ssm2602 register cache
- */
-static inline void ssm2602_write_reg_cache(struct snd_soc_codec *codec,
-        u16 reg, unsigned int value)
-{
-        u16 *cache = codec->reg_cache;
-        if (reg >= SSM2602_CACHEREGNUM)
-                return;
-        cache[reg] = value;
-}
-
-/*
- * write to the ssm2602 register space
- */
-static int ssm2602_write(struct snd_soc_codec *codec, unsigned int reg,
-        unsigned int value)
-{
-        u8 data[2];
-
-        /* data is
-         *   D15..D9 ssm2602 register offset
-         *   D8...D0 register data
-         */
-        data[0] = (reg << 1) | ((value >> 8) & 0x0001);
-        data[1] = value & 0x00ff;
-
-        ssm2602_write_reg_cache(codec, reg, value);
-        if (codec->hw_write(codec->control_data, data, 2) == 2)
-                return 0;
-        else
-                return -EIO;
-}
-
-#define ssm2602_reset(c)        ssm2602_write(c, SSM2602_RESET, 0)
+#define ssm2602_reset(c)        snd_soc_write(c, SSM2602_RESET, 0)
 
 /*Appending several "None"s just for OSS mixer use*/
 static const char *ssm2602_input_select[] = {
@@ -129,174 +88,187 @@ static const struct soc_enum ssm2602_enum[] = {
         SOC_ENUM_SINGLE(SSM2602_APDIGI, 1, 4, ssm2602_deemph),
 };
 
-static const struct snd_kcontrol_new ssm2602_snd_controls[] = {
+static const unsigned int ssm260x_outmix_tlv[] = {
+        TLV_DB_RANGE_HEAD(2),
+        0, 47, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
+        48, 127, TLV_DB_SCALE_ITEM(-7400, 100, 0),
+};
 
-SOC_DOUBLE_R("Master Playback Volume", SSM2602_LOUT1V, SSM2602_ROUT1V,
-        0, 127, 0),
-SOC_DOUBLE_R("Master Playback ZC Switch", SSM2602_LOUT1V, SSM2602_ROUT1V,
-        7, 1, 0),
+static const DECLARE_TLV_DB_SCALE(ssm260x_inpga_tlv, -3450, 150, 0);
+static const DECLARE_TLV_DB_SCALE(ssm260x_sidetone_tlv, -1500, 300, 0);
 
-SOC_DOUBLE_R("Capture Volume", SSM2602_LINVOL, SSM2602_RINVOL, 0, 31, 0),
+static const struct snd_kcontrol_new ssm260x_snd_controls[] = {
+SOC_DOUBLE_R_TLV("Capture Volume", SSM2602_LINVOL, SSM2602_RINVOL, 0, 45, 0,
+        ssm260x_inpga_tlv),
 SOC_DOUBLE_R("Capture Switch", SSM2602_LINVOL, SSM2602_RINVOL, 7, 1, 1),
 
-SOC_SINGLE("Mic Boost (+20dB)", SSM2602_APANA, 0, 1, 0),
-SOC_SINGLE("Mic Boost2 (+20dB)", SSM2602_APANA, 7, 1, 0),
-SOC_SINGLE("Mic Switch", SSM2602_APANA, 1, 1, 1),
-
-SOC_SINGLE("Sidetone Playback Volume", SSM2602_APANA, 6, 3, 1),
-
 SOC_SINGLE("ADC High Pass Filter Switch", SSM2602_APDIGI, 0, 1, 1),
 SOC_SINGLE("Store DC Offset Switch", SSM2602_APDIGI, 4, 1, 0),
 
-SOC_ENUM("Capture Source", ssm2602_enum[0]),
-
 SOC_ENUM("Playback De-emphasis", ssm2602_enum[1]),
 };
 
+static const struct snd_kcontrol_new ssm2602_snd_controls[] = {
+SOC_DOUBLE_R_TLV("Master Playback Volume", SSM2602_LOUT1V, SSM2602_ROUT1V,
+        0, 127, 0, ssm260x_outmix_tlv),
+SOC_DOUBLE_R("Master Playback ZC Switch", SSM2602_LOUT1V, SSM2602_ROUT1V,
+        7, 1, 0),
+SOC_SINGLE_TLV("Sidetone Playback Volume", SSM2602_APANA, 6, 3, 1,
+        ssm260x_sidetone_tlv),
+
+SOC_SINGLE("Mic Boost (+20dB)", SSM2602_APANA, 0, 1, 0),
+SOC_SINGLE("Mic Boost2 (+20dB)", SSM2602_APANA, 8, 1, 0),
+SOC_SINGLE("Mic Switch", SSM2602_APANA, 1, 1, 1),
+};
+
 /* Output Mixer */
-static const struct snd_kcontrol_new ssm2602_output_mixer_controls[] = {
+static const struct snd_kcontrol_new ssm260x_output_mixer_controls[] = {
 SOC_DAPM_SINGLE("Line Bypass Switch", SSM2602_APANA, 3, 1, 0),
-SOC_DAPM_SINGLE("Mic Sidetone Switch", SSM2602_APANA, 5, 1, 0),
 SOC_DAPM_SINGLE("HiFi Playback Switch", SSM2602_APANA, 4, 1, 0),
+SOC_DAPM_SINGLE("Mic Sidetone Switch", SSM2602_APANA, 5, 1, 0),
 };
 
 /* Input mux */
 static const struct snd_kcontrol_new ssm2602_input_mux_controls =
 SOC_DAPM_ENUM("Input Select", ssm2602_enum[0]);
 
-static const struct snd_soc_dapm_widget ssm2602_dapm_widgets[] = {
-SND_SOC_DAPM_MIXER("Output Mixer", SSM2602_PWR, 4, 1,
-        &ssm2602_output_mixer_controls[0],
-        ARRAY_SIZE(ssm2602_output_mixer_controls)),
+static const struct snd_soc_dapm_widget ssm260x_dapm_widgets[] = {
 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SSM2602_PWR, 3, 1),
+SND_SOC_DAPM_ADC("ADC", "HiFi Capture", SSM2602_PWR, 2, 1),
+SND_SOC_DAPM_PGA("Line Input", SSM2602_PWR, 0, 1, NULL, 0),
+
+SND_SOC_DAPM_SUPPLY("Digital Core Power", SSM2602_ACTIVE, 0, 0, NULL, 0),
+
 SND_SOC_DAPM_OUTPUT("LOUT"),
-SND_SOC_DAPM_OUTPUT("LHPOUT"),
 SND_SOC_DAPM_OUTPUT("ROUT"),
-SND_SOC_DAPM_OUTPUT("RHPOUT"),
-SND_SOC_DAPM_ADC("ADC", "HiFi Capture", SSM2602_PWR, 2, 1),
+SND_SOC_DAPM_INPUT("RLINEIN"),
+SND_SOC_DAPM_INPUT("LLINEIN"),
+};
+
+static const struct snd_soc_dapm_widget ssm2602_dapm_widgets[] = {
+SND_SOC_DAPM_MIXER("Output Mixer", SSM2602_PWR, 4, 1,
+        ssm260x_output_mixer_controls,
+        ARRAY_SIZE(ssm260x_output_mixer_controls)),
+
 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, &ssm2602_input_mux_controls),
-SND_SOC_DAPM_PGA("Line Input", SSM2602_PWR, 0, 1, NULL, 0),
 SND_SOC_DAPM_MICBIAS("Mic Bias", SSM2602_PWR, 1, 1),
+
+SND_SOC_DAPM_OUTPUT("LHPOUT"),
+SND_SOC_DAPM_OUTPUT("RHPOUT"),
 SND_SOC_DAPM_INPUT("MICIN"),
-SND_SOC_DAPM_INPUT("RLINEIN"),
-SND_SOC_DAPM_INPUT("LLINEIN"),
 };
 
-static const struct snd_soc_dapm_route audio_conn[] = {
-        /* output mixer */
+static const struct snd_soc_dapm_widget ssm2604_dapm_widgets[] = {
+SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
+        ssm260x_output_mixer_controls,
+        ARRAY_SIZE(ssm260x_output_mixer_controls) - 1), /* Last element is the mic */
+};
+
+static const struct snd_soc_dapm_route ssm260x_routes[] = {
+        {"DAC", NULL, "Digital Core Power"},
+        {"ADC", NULL, "Digital Core Power"},
+
         {"Output Mixer", "Line Bypass Switch", "Line Input"},
         {"Output Mixer", "HiFi Playback Switch", "DAC"},
+
+        {"ROUT", NULL, "Output Mixer"},
+        {"LOUT", NULL, "Output Mixer"},
+
+        {"Line Input", NULL, "LLINEIN"},
+        {"Line Input", NULL, "RLINEIN"},
+};
+
+static const struct snd_soc_dapm_route ssm2602_routes[] = {
         {"Output Mixer", "Mic Sidetone Switch", "Mic Bias"},
 
-        /* outputs */
         {"RHPOUT", NULL, "Output Mixer"},
-        {"ROUT", NULL, "Output Mixer"},
         {"LHPOUT", NULL, "Output Mixer"},
-        {"LOUT", NULL, "Output Mixer"},
 
-        /* input mux */
         {"Input Mux", "Line", "Line Input"},
         {"Input Mux", "Mic", "Mic Bias"},
         {"ADC", NULL, "Input Mux"},
 
-        /* inputs */
-        {"Line Input", NULL, "LLINEIN"},
-        {"Line Input", NULL, "RLINEIN"},
         {"Mic Bias", NULL, "MICIN"},
 };
 
-static int ssm2602_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, ssm2602_dapm_widgets,
-                                  ARRAY_SIZE(ssm2602_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, audio_conn, ARRAY_SIZE(audio_conn));
-
-        return 0;
-}
+static const struct snd_soc_dapm_route ssm2604_routes[] = {
+        {"ADC", NULL, "Line Input"},
+};
 
-struct _coeff_div {
+struct ssm2602_coeff {
         u32 mclk;
         u32 rate;
-        u16 fs;
-        u8 sr:4;
-        u8 bosr:1;
-        u8 usb:1;
+        u8 srate;
 };
 
-/* codec mclk clock divider coefficients */
-static const struct _coeff_div coeff_div[] = {
+#define SSM2602_COEFF_SRATE(sr, bosr, usb) (((sr) << 2) | ((bosr) << 1) | (usb))
+
+/* codec mclk clock coefficients */
+static const struct ssm2602_coeff ssm2602_coeff_table[] = {
         /* 48k */
-        {12288000, 48000, 256, 0x0, 0x0, 0x0},
-        {18432000, 48000, 384, 0x0, 0x1, 0x0},
-        {12000000, 48000, 250, 0x0, 0x0, 0x1},
+        {12288000, 48000, SSM2602_COEFF_SRATE(0x0, 0x0, 0x0)},
+        {18432000, 48000, SSM2602_COEFF_SRATE(0x0, 0x1, 0x0)},
+        {12000000, 48000, SSM2602_COEFF_SRATE(0x0, 0x0, 0x1)},
 
         /* 32k */
-        {12288000, 32000, 384, 0x6, 0x0, 0x0},
-        {18432000, 32000, 576, 0x6, 0x1, 0x0},
-        {12000000, 32000, 375, 0x6, 0x0, 0x1},
+        {12288000, 32000, SSM2602_COEFF_SRATE(0x6, 0x0, 0x0)},
+        {18432000, 32000, SSM2602_COEFF_SRATE(0x6, 0x1, 0x0)},
+        {12000000, 32000, SSM2602_COEFF_SRATE(0x6, 0x0, 0x1)},
 
         /* 8k */
-        {12288000, 8000, 1536, 0x3, 0x0, 0x0},
-        {18432000, 8000, 2304, 0x3, 0x1, 0x0},
-        {11289600, 8000, 1408, 0xb, 0x0, 0x0},
-        {16934400, 8000, 2112, 0xb, 0x1, 0x0},
-        {12000000, 8000, 1500, 0x3, 0x0, 0x1},
+        {12288000, 8000, SSM2602_COEFF_SRATE(0x3, 0x0, 0x0)},
+        {18432000, 8000, SSM2602_COEFF_SRATE(0x3, 0x1, 0x0)},
+        {11289600, 8000, SSM2602_COEFF_SRATE(0xb, 0x0, 0x0)},
+        {16934400, 8000, SSM2602_COEFF_SRATE(0xb, 0x1, 0x0)},
+        {12000000, 8000, SSM2602_COEFF_SRATE(0x3, 0x0, 0x1)},
 
         /* 96k */
-        {12288000, 96000, 128, 0x7, 0x0, 0x0},
-        {18432000, 96000, 192, 0x7, 0x1, 0x0},
-        {12000000, 96000, 125, 0x7, 0x0, 0x1},
+        {12288000, 96000, SSM2602_COEFF_SRATE(0x7, 0x0, 0x0)},
+        {18432000, 96000, SSM2602_COEFF_SRATE(0x7, 0x1, 0x0)},
+        {12000000, 96000, SSM2602_COEFF_SRATE(0x7, 0x0, 0x1)},
 
         /* 44.1k */
-        {11289600, 44100, 256, 0x8, 0x0, 0x0},
-        {16934400, 44100, 384, 0x8, 0x1, 0x0},
-        {12000000, 44100, 272, 0x8, 0x1, 0x1},
+        {11289600, 44100, SSM2602_COEFF_SRATE(0x8, 0x0, 0x0)},
+        {16934400, 44100, SSM2602_COEFF_SRATE(0x8, 0x1, 0x0)},
+        {12000000, 44100, SSM2602_COEFF_SRATE(0x8, 0x1, 0x1)},
 
         /* 88.2k */
-        {11289600, 88200, 128, 0xf, 0x0, 0x0},
-        {16934400, 88200, 192, 0xf, 0x1, 0x0},
-        {12000000, 88200, 136, 0xf, 0x1, 0x1},
+        {11289600, 88200, SSM2602_COEFF_SRATE(0xf, 0x0, 0x0)},
+        {16934400, 88200, SSM2602_COEFF_SRATE(0xf, 0x1, 0x0)},
+        {12000000, 88200, SSM2602_COEFF_SRATE(0xf, 0x1, 0x1)},
 };
 
-static inline int get_coeff(int mclk, int rate)
+static inline int ssm2602_get_coeff(int mclk, int rate)
 {
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
-                if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
-                        return i;
+        for (i = 0; i < ARRAY_SIZE(ssm2602_coeff_table); i++) {
+                if (ssm2602_coeff_table[i].rate == rate &&
+                        ssm2602_coeff_table[i].mclk == mclk)
+                        return ssm2602_coeff_table[i].srate;
         }
-        return i;
+        return -EINVAL;
 }
 
 static int ssm2602_hw_params(struct snd_pcm_substream *substream,
         struct snd_pcm_hw_params *params,
         struct snd_soc_dai *dai)
 {
-        u16 srate;
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
-        struct i2c_client *i2c = codec->control_data;
-        u16 iface = ssm2602_read_reg_cache(codec, SSM2602_IFACE) & 0xfff3;
-        int i = get_coeff(ssm2602->sysclk, params_rate(params));
+        u16 iface = snd_soc_read(codec, SSM2602_IFACE) & 0xfff3;
+        int srate = ssm2602_get_coeff(ssm2602->sysclk, params_rate(params));
 
         if (substream == ssm2602->slave_substream) {
-                dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
+                dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n");
                 return 0;
         }
 
-        /*no match is found*/
-        if (i == ARRAY_SIZE(coeff_div))
-                return -EINVAL;
-
-        srate = (coeff_div[i].sr << 2) |
-                (coeff_div[i].bosr << 1) | coeff_div[i].usb;
+        if (srate < 0)
+                return srate;
 
-        ssm2602_write(codec, SSM2602_ACTIVE, 0);
-        ssm2602_write(codec, SSM2602_SRATE, srate);
+        snd_soc_write(codec, SSM2602_SRATE, srate);
 
         /* bit size */
         switch (params_format(params)) {
@@ -312,8 +284,7 @@ static int ssm2602_hw_params(struct snd_pcm_substream *substream,
                 iface |= 0x000c;
                 break;
         }
-        ssm2602_write(codec, SSM2602_IFACE, iface);
-        ssm2602_write(codec, SSM2602_ACTIVE, ACTIVE_ACTIVATE_CODEC);
+        snd_soc_write(codec, SSM2602_IFACE, iface);
         return 0;
 }
 
@@ -321,8 +292,7 @@ static int ssm2602_startup(struct snd_pcm_substream *substream,
                            struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
         struct i2c_client *i2c = codec->control_data;
         struct snd_pcm_runtime *master_runtime;
@@ -356,45 +326,29 @@ static int ssm2602_startup(struct snd_pcm_substream *substream,
         return 0;
 }
 
-static int ssm2602_pcm_prepare(struct snd_pcm_substream *substream,
-                               struct snd_soc_dai *dai)
-{
-        struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-        /* set active */
-        ssm2602_write(codec, SSM2602_ACTIVE, ACTIVE_ACTIVATE_CODEC);
-
-        return 0;
-}
-
 static void ssm2602_shutdown(struct snd_pcm_substream *substream,
                              struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
 
-        /* deactivate */
-        if (!codec->active)
-                ssm2602_write(codec, SSM2602_ACTIVE, 0);
-
         if (ssm2602->master_substream == substream)
                 ssm2602->master_substream = ssm2602->slave_substream;
 
         ssm2602->slave_substream = NULL;
 }
 
+
 static int ssm2602_mute(struct snd_soc_dai *dai, int mute)
 {
         struct snd_soc_codec *codec = dai->codec;
-        u16 mute_reg = ssm2602_read_reg_cache(codec, SSM2602_APDIGI) & ~APDIGI_ENABLE_DAC_MUTE;
+        u16 mute_reg = snd_soc_read(codec, SSM2602_APDIGI) & ~APDIGI_ENABLE_DAC_MUTE;
         if (mute)
-                ssm2602_write(codec, SSM2602_APDIGI,
+                snd_soc_write(codec, SSM2602_APDIGI,
                                 mute_reg | APDIGI_ENABLE_DAC_MUTE);
         else
-                ssm2602_write(codec, SSM2602_APDIGI, mute_reg);
+                snd_soc_write(codec, SSM2602_APDIGI, mute_reg);
         return 0;
 }
 
@@ -470,34 +424,33 @@ static int ssm2602_set_dai_fmt(struct snd_soc_dai *codec_dai,
         }
 
         /* set iface */
-        ssm2602_write(codec, SSM2602_IFACE, iface);
+        snd_soc_write(codec, SSM2602_IFACE, iface);
         return 0;
 }
 
 static int ssm2602_set_bias_level(struct snd_soc_codec *codec,
                                  enum snd_soc_bias_level level)
 {
-        u16 reg = ssm2602_read_reg_cache(codec, SSM2602_PWR) & 0xff7f;
+        u16 reg = snd_soc_read(codec, SSM2602_PWR) & 0xff7f;
 
         switch (level) {
         case SND_SOC_BIAS_ON:
                 /* vref/mid, osc on, dac unmute */
-                ssm2602_write(codec, SSM2602_PWR, reg);
+                snd_soc_write(codec, SSM2602_PWR, reg);
                 break;
         case SND_SOC_BIAS_PREPARE:
                 break;
         case SND_SOC_BIAS_STANDBY:
                 /* everything off except vref/vmid, */
-                ssm2602_write(codec, SSM2602_PWR, reg | PWR_CLK_OUT_PDN);
+                snd_soc_write(codec, SSM2602_PWR, reg | PWR_CLK_OUT_PDN);
                 break;
         case SND_SOC_BIAS_OFF:
                 /* everything off, dac mute, inactive */
-                ssm2602_write(codec, SSM2602_ACTIVE, 0);
-                ssm2602_write(codec, SSM2602_PWR, 0xffff);
+                snd_soc_write(codec, SSM2602_PWR, 0xffff);
                 break;
 
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -510,7 +463,6 @@ static int ssm2602_set_bias_level(struct snd_soc_codec *codec,
 
 static struct snd_soc_dai_ops ssm2602_dai_ops = {
         .startup        = ssm2602_startup,
-        .prepare        = ssm2602_pcm_prepare,
         .hw_params      = ssm2602_hw_params,
         .shutdown       = ssm2602_shutdown,
         .digital_mute   = ssm2602_mute,
@@ -518,8 +470,8 @@ static struct snd_soc_dai_ops ssm2602_dai_ops = {
         .set_fmt        = ssm2602_set_dai_fmt,
 };
 
-struct snd_soc_dai ssm2602_dai = {
-        .name = "SSM2602",
+static struct snd_soc_dai_driver ssm2602_dai = {
+        .name = "ssm2602-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -534,93 +486,162 @@ struct snd_soc_dai ssm2602_dai = {
                 .formats = SSM2602_FORMATS,},
         .ops = &ssm2602_dai_ops,
 };
-EXPORT_SYMBOL_GPL(ssm2602_dai);
 
-static int ssm2602_suspend(struct platform_device *pdev, pm_message_t state)
+static int ssm2602_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         ssm2602_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int ssm2602_resume(struct platform_device *pdev)
+static int ssm2602_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int i;
-        u8 data[2];
-        u16 *cache = codec->reg_cache;
-
-        /* Sync reg_cache with the hardware */
-        for (i = 0; i < ARRAY_SIZE(ssm2602_reg); i++) {
-                data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
-                data[1] = cache[i] & 0x00ff;
-                codec->hw_write(codec->control_data, data, 2);
-        }
+        snd_soc_cache_sync(codec);
+
         ssm2602_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
         return 0;
 }
 
-/*
- * initialise the ssm2602 driver
- * register the mixer and dsp interfaces with the kernel
- */
-static int ssm2602_init(struct snd_soc_device *socdev)
+static int ssm2602_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int reg, ret = 0;
-
-        codec->name = "SSM2602";
-        codec->owner = THIS_MODULE;
-        codec->read = ssm2602_read_reg_cache;
-        codec->write = ssm2602_write;
-        codec->set_bias_level = ssm2602_set_bias_level;
-        codec->dai = &ssm2602_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = sizeof(ssm2602_reg);
-        codec->reg_cache = kmemdup(ssm2602_reg, sizeof(ssm2602_reg),
-                                        GFP_KERNEL);
-        if (codec->reg_cache == NULL)
-                return -ENOMEM;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret, reg;
+
+        reg = snd_soc_read(codec, SSM2602_LOUT1V);
+        snd_soc_write(codec, SSM2602_LOUT1V, reg | LOUT1V_LRHP_BOTH);
+        reg = snd_soc_read(codec, SSM2602_ROUT1V);
+        snd_soc_write(codec, SSM2602_ROUT1V, reg | ROUT1V_RLHP_BOTH);
 
-        ssm2602_reset(codec);
+        ret = snd_soc_add_controls(codec, ssm2602_snd_controls,
+                        ARRAY_SIZE(ssm2602_snd_controls));
+        if (ret)
+                return ret;
+
+        ret = snd_soc_dapm_new_controls(dapm, ssm2602_dapm_widgets,
+                        ARRAY_SIZE(ssm2602_dapm_widgets));
+        if (ret)
+                return ret;
+
+        return snd_soc_dapm_add_routes(dapm, ssm2602_routes,
+                        ARRAY_SIZE(ssm2602_routes));
+}
+
+static int ssm2604_probe(struct snd_soc_codec *codec)
+{
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret;
+
+        ret = snd_soc_dapm_new_controls(dapm, ssm2604_dapm_widgets,
+                        ARRAY_SIZE(ssm2604_dapm_widgets));
+        if (ret)
+                return ret;
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+        return snd_soc_dapm_add_routes(dapm, ssm2604_routes,
+                        ARRAY_SIZE(ssm2604_routes));
+}
+
+static int ssm260x_probe(struct snd_soc_codec *codec)
+{
+        struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
+        int ret, reg;
+
+        pr_info("ssm2602 Audio Codec %s", SSM2602_VERSION);
+
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, ssm2602->control_type);
         if (ret < 0) {
-                pr_err("ssm2602: failed to create pcms\n");
-                goto pcm_err;
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
-        /*power on device*/
-        ssm2602_write(codec, SSM2602_ACTIVE, 0);
+
+        ret = ssm2602_reset(codec);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
+                return ret;
+        }
+
         /* set the update bits */
-        reg = ssm2602_read_reg_cache(codec, SSM2602_LINVOL);
-        ssm2602_write(codec, SSM2602_LINVOL, reg | LINVOL_LRIN_BOTH);
-        reg = ssm2602_read_reg_cache(codec, SSM2602_RINVOL);
-        ssm2602_write(codec, SSM2602_RINVOL, reg | RINVOL_RLIN_BOTH);
-        reg = ssm2602_read_reg_cache(codec, SSM2602_LOUT1V);
-        ssm2602_write(codec, SSM2602_LOUT1V, reg | LOUT1V_LRHP_BOTH);
-        reg = ssm2602_read_reg_cache(codec, SSM2602_ROUT1V);
-        ssm2602_write(codec, SSM2602_ROUT1V, reg | ROUT1V_RLHP_BOTH);
+        reg = snd_soc_read(codec, SSM2602_LINVOL);
+        snd_soc_write(codec, SSM2602_LINVOL, reg | LINVOL_LRIN_BOTH);
+        reg = snd_soc_read(codec, SSM2602_RINVOL);
+        snd_soc_write(codec, SSM2602_RINVOL, reg | RINVOL_RLIN_BOTH);
         /*select Line in as default input*/
-        ssm2602_write(codec, SSM2602_APANA, APANA_SELECT_DAC |
+        snd_soc_write(codec, SSM2602_APANA, APANA_SELECT_DAC |
                         APANA_ENABLE_MIC_BOOST);
-        ssm2602_write(codec, SSM2602_PWR, 0);
 
-        snd_soc_add_controls(codec, ssm2602_snd_controls,
-                                ARRAY_SIZE(ssm2602_snd_controls));
-        ssm2602_add_widgets(codec);
+        switch (ssm2602->type) {
+        case SSM2602:
+                ret = ssm2602_probe(codec);
+                break;
+        case SSM2604:
+                ret = ssm2604_probe(codec);
+                break;
+        }
 
         return ret;
+}
 
-pcm_err:
-        kfree(codec->reg_cache);
+/* remove everything here */
+static int ssm2602_remove(struct snd_soc_codec *codec)
+{
+        ssm2602_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_ssm2602 = {
+        .probe =        ssm260x_probe,
+        .remove =       ssm2602_remove,
+        .suspend =      ssm2602_suspend,
+        .resume =       ssm2602_resume,
+        .set_bias_level = ssm2602_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(ssm2602_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = ssm2602_reg,
+
+        .controls = ssm260x_snd_controls,
+        .num_controls = ARRAY_SIZE(ssm260x_snd_controls),
+        .dapm_widgets = ssm260x_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(ssm260x_dapm_widgets),
+        .dapm_routes = ssm260x_routes,
+        .num_dapm_routes = ARRAY_SIZE(ssm260x_routes),
+};
+
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit ssm2602_spi_probe(struct spi_device *spi)
+{
+        struct ssm2602_priv *ssm2602;
+        int ret;
+
+        ssm2602 = kzalloc(sizeof(struct ssm2602_priv), GFP_KERNEL);
+        if (ssm2602 == NULL)
+                return -ENOMEM;
+
+        spi_set_drvdata(spi, ssm2602);
+        ssm2602->control_type = SND_SOC_SPI;
+        ssm2602->type = SSM2602;
+
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_ssm2602, &ssm2602_dai, 1);
+        if (ret < 0)
+                kfree(ssm2602);
         return ret;
 }
 
-static struct snd_soc_device *ssm2602_socdev;
+static int __devexit ssm2602_spi_remove(struct spi_device *spi)
+{
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
+}
+
+static struct spi_driver ssm2602_spi_driver = {
+        .driver = {
+                .name   = "ssm2602",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = ssm2602_spi_probe,
+        .remove         = __devexit_p(ssm2602_spi_remove),
+};
+#endif
 
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 /*
@@ -629,162 +650,87 @@ static struct snd_soc_device *ssm2602_socdev;
  *    low  = 0x1a
  *    high = 0x1b
  */
-static int ssm2602_i2c_probe(struct i2c_client *i2c,
+static int __devinit ssm2602_i2c_probe(struct i2c_client *i2c,
                              const struct i2c_device_id *id)
 {
-        struct snd_soc_device *socdev = ssm2602_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct ssm2602_priv *ssm2602;
         int ret;
 
-        i2c_set_clientdata(i2c, codec);
-        codec->control_data = i2c;
+        ssm2602 = kzalloc(sizeof(struct ssm2602_priv), GFP_KERNEL);
+        if (ssm2602 == NULL)
+                return -ENOMEM;
 
-        ret = ssm2602_init(socdev);
-        if (ret < 0)
-                pr_err("failed to initialise SSM2602\n");
+        i2c_set_clientdata(i2c, ssm2602);
+        ssm2602->control_type = SND_SOC_I2C;
+        ssm2602->type = id->driver_data;
 
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_ssm2602, &ssm2602_dai, 1);
+        if (ret < 0)
+                kfree(ssm2602);
         return ret;
 }
 
-static int ssm2602_i2c_remove(struct i2c_client *client)
+static int __devexit ssm2602_i2c_remove(struct i2c_client *client)
 {
-        struct snd_soc_codec *codec = i2c_get_clientdata(client);
-        kfree(codec->reg_cache);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
 static const struct i2c_device_id ssm2602_i2c_id[] = {
-        { "ssm2602", 0 },
+        { "ssm2602", SSM2602 },
+        { "ssm2603", SSM2602 },
+        { "ssm2604", SSM2604 },
         { }
 };
 MODULE_DEVICE_TABLE(i2c, ssm2602_i2c_id);
+
 /* corgi i2c codec control layer */
 static struct i2c_driver ssm2602_i2c_driver = {
         .driver = {
-                .name = "SSM2602 I2C Codec",
+                .name = "ssm2602",
                 .owner = THIS_MODULE,
         },
         .probe = ssm2602_i2c_probe,
-        .remove = ssm2602_i2c_remove,
+        .remove = __devexit_p(ssm2602_i2c_remove),
         .id_table = ssm2602_i2c_id,
 };
-
-static int ssm2602_add_i2c_device(struct platform_device *pdev,
-                                  const struct ssm2602_setup_data *setup)
-{
-        struct i2c_board_info info;
-        struct i2c_adapter *adapter;
-        struct i2c_client *client;
-        int ret;
-
-        ret = i2c_add_driver(&ssm2602_i2c_driver);
-        if (ret != 0) {
-                dev_err(&pdev->dev, "can't add i2c driver\n");
-                return ret;
-        }
-        memset(&info, 0, sizeof(struct i2c_board_info));
-        info.addr = setup->i2c_address;
-        strlcpy(info.type, "ssm2602", I2C_NAME_SIZE);
-        adapter = i2c_get_adapter(setup->i2c_bus);
-        if (!adapter) {
-                dev_err(&pdev->dev, "can't get i2c adapter %d\n",
-                setup->i2c_bus);
-                goto err_driver;
-        }
-        client = i2c_new_device(adapter, &info);
-        i2c_put_adapter(adapter);
-        if (!client) {
-                dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
-                (unsigned int)info.addr);
-                goto err_driver;
-        }
-        return 0;
-err_driver:
-        i2c_del_driver(&ssm2602_i2c_driver);
-        return -ENODEV;
-}
 #endif
 
-static int ssm2602_probe(struct platform_device *pdev)
+
+static int __init ssm2602_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct ssm2602_setup_data *setup;
-        struct snd_soc_codec *codec;
-        struct ssm2602_priv *ssm2602;
         int ret = 0;
 
-        pr_info("ssm2602 Audio Codec %s", SSM2602_VERSION);
-
-        setup = socdev->codec_data;
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-
-        ssm2602 = kzalloc(sizeof(struct ssm2602_priv), GFP_KERNEL);
-        if (ssm2602 == NULL) {
-                kfree(codec);
-                return -ENOMEM;
-        }
-
-        snd_soc_codec_set_drvdata(codec, ssm2602);
-        socdev->card->codec = codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
+#if defined(CONFIG_SPI_MASTER)
+        ret = spi_register_driver(&ssm2602_spi_driver);
+        if (ret)
+                return ret;
+#endif
 
-        ssm2602_socdev = socdev;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        if (setup->i2c_address) {
-                codec->hw_write = (hw_write_t)i2c_master_send;
-                ret = ssm2602_add_i2c_device(pdev, setup);
-        }
-#else
-        /* other interfaces */
+        ret = i2c_add_driver(&ssm2602_i2c_driver);
+        if (ret)
+                return ret;
 #endif
+
         return ret;
 }
+module_init(ssm2602_modinit);
 
-/* remove everything here */
-static int ssm2602_remove(struct platform_device *pdev)
+static void __exit ssm2602_exit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec->control_data)
-                ssm2602_set_bias_level(codec, SND_SOC_BIAS_OFF);
+#if defined(CONFIG_SPI_MASTER)
+        spi_unregister_driver(&ssm2602_spi_driver);
+#endif
 
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        i2c_unregister_device(codec->control_data);
         i2c_del_driver(&ssm2602_i2c_driver);
 #endif
-        kfree(snd_soc_codec_get_drvdata(codec));
-        kfree(codec);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_ssm2602 = {
-        .probe =        ssm2602_probe,
-        .remove =       ssm2602_remove,
-        .suspend =      ssm2602_suspend,
-        .resume =       ssm2602_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_ssm2602);
-
-static int __init ssm2602_modinit(void)
-{
-        return snd_soc_register_dai(&ssm2602_dai);
-}
-module_init(ssm2602_modinit);
-
-static void __exit ssm2602_exit(void)
-{
-        snd_soc_unregister_dai(&ssm2602_dai);
 }
 module_exit(ssm2602_exit);
 
-MODULE_DESCRIPTION("ASoC ssm2602 driver");
+MODULE_DESCRIPTION("ASoC SSM2602/SSM2603/SSM2604 driver");
 MODULE_AUTHOR("Cliff Cai");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/ssm2602.h b/sound/soc/codecs/ssm2602.h
index f344e6d76e31..b98c69168036 100644
--- a/sound/soc/codecs/ssm2602.h
+++ b/sound/soc/codecs/ssm2602.h
@@ -117,14 +117,5 @@
 #define SSM2602_CACHEREGNUM     10
 
 #define SSM2602_SYSCLK  0
-#define SSM2602_DAI             0
-
-struct ssm2602_setup_data {
-        int i2c_bus;
-        unsigned short i2c_address;
-};
-
-extern struct snd_soc_dai ssm2602_dai;
-extern struct snd_soc_codec_device soc_codec_dev_ssm2602;
 
 #endif
diff --git a/sound/soc/codecs/stac9766.c b/sound/soc/codecs/stac9766.c
index ee86568545c2..78b2b50271e2 100644
--- a/sound/soc/codecs/stac9766.c
+++ b/sound/soc/codecs/stac9766.c
@@ -25,7 +25,6 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 #include <sound/tlv.h>
-#include <sound/soc-of-simple.h>
 
 #include "stac9766.h"
 
@@ -237,7 +236,7 @@ static int stac9766_set_bias_level(struct snd_soc_codec *codec,
                 stac9766_ac97_write(codec, AC97_POWERDOWN, 0xffff);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -257,20 +256,15 @@ static int stac9766_reset(struct snd_soc_codec *codec, int try_warm)
         return 0;
 }
 
-static int stac9766_codec_suspend(struct platform_device *pdev,
+static int stac9766_codec_suspend(struct snd_soc_codec *codec,
                                   pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         stac9766_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int stac9766_codec_resume(struct platform_device *pdev)
+static int stac9766_codec_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         u16 id, reset;
 
         reset = 0;
@@ -300,10 +294,9 @@ static struct snd_soc_dai_ops stac9766_dai_ops_digital = {
         .prepare = ac97_digital_prepare,
 };
 
-struct snd_soc_dai stac9766_dai[] = {
+static struct snd_soc_dai_driver stac9766_dai[] = {
 {
-        .name = "stac9766 analog",
-        .id = 0,
+        .name = "stac9766-hifi-analog",
         .ac97_control = 1,
 
         /* stream cababilities */
@@ -325,8 +318,7 @@ struct snd_soc_dai stac9766_dai[] = {
         .ops = &stac9766_dai_ops_analog,
 },
 {
-        .name = "stac9766 IEC958",
-        .id = 1,
+        .name = "stac9766-hifi-IEC958",
         .ac97_control = 1,
 
         /* stream cababilities */
@@ -342,57 +334,24 @@ struct snd_soc_dai stac9766_dai[] = {
         .ops = &stac9766_dai_ops_digital,
 }
 };
-EXPORT_SYMBOL_GPL(stac9766_dai);
 
-static int stac9766_codec_probe(struct platform_device *pdev)
+static int stac9766_codec_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
         int ret = 0;
 
         printk(KERN_INFO "STAC9766 SoC Audio Codec %s\n", STAC9766_VERSION);
 
-        socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (socdev->card->codec == NULL)
-                return -ENOMEM;
-        codec = socdev->card->codec;
-        mutex_init(&codec->mutex);
-
-        codec->reg_cache = kmemdup(stac9766_reg, sizeof(stac9766_reg),
-                                   GFP_KERNEL);
-        if (codec->reg_cache == NULL) {
-                ret = -ENOMEM;
-                goto cache_err;
-        }
-        codec->reg_cache_size = sizeof(stac9766_reg);
-        codec->reg_cache_step = 2;
-
-        codec->name = "STAC9766";
-        codec->owner = THIS_MODULE;
-        codec->dai = stac9766_dai;
-        codec->num_dai = ARRAY_SIZE(stac9766_dai);
-        codec->write = stac9766_ac97_write;
-        codec->read = stac9766_ac97_read;
-        codec->set_bias_level = stac9766_set_bias_level;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
         ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
         if (ret < 0)
                 goto codec_err;
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0)
-                goto pcm_err;
-
         /* do a cold reset for the controller and then try
          * a warm reset followed by an optional cold reset for codec */
         stac9766_reset(codec, 0);
         ret = stac9766_reset(codec, 1);
         if (ret < 0) {
                 printk(KERN_ERR "Failed to reset STAC9766: AC97 link error\n");
-                goto reset_err;
+                goto codec_err;
         }
 
         stac9766_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -402,40 +361,64 @@ static int stac9766_codec_probe(struct platform_device *pdev)
 
         return 0;
 
-reset_err:
-        snd_soc_free_pcms(socdev);
-pcm_err:
-        snd_soc_free_ac97_codec(codec);
 codec_err:
-        kfree(snd_soc_codec_get_drvdata(codec));
-cache_err:
-        kfree(socdev->card->codec);
-        socdev->card->codec = NULL;
+        snd_soc_free_ac97_codec(codec);
         return ret;
 }
 
-static int stac9766_codec_remove(struct platform_device *pdev)
+static int stac9766_codec_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec == NULL)
-                return 0;
-
-        snd_soc_free_pcms(socdev);
         snd_soc_free_ac97_codec(codec);
-        kfree(codec->reg_cache);
-        kfree(codec);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_stac9766 = {
+static struct snd_soc_codec_driver soc_codec_dev_stac9766 = {
+        .write = stac9766_ac97_write,
+        .read = stac9766_ac97_read,
+        .set_bias_level = stac9766_set_bias_level,
         .probe = stac9766_codec_probe,
         .remove = stac9766_codec_remove,
         .suspend = stac9766_codec_suspend,
         .resume = stac9766_codec_resume,
+        .reg_cache_size = sizeof(stac9766_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_step = 2,
+        .reg_cache_default = stac9766_reg,
+};
+
+static __devinit int stac9766_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_stac9766, stac9766_dai, ARRAY_SIZE(stac9766_dai));
+}
+
+static int __devexit stac9766_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver stac9766_codec_driver = {
+        .driver = {
+                        .name = "stac9766-codec",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = stac9766_probe,
+        .remove = __devexit_p(stac9766_remove),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_stac9766);
+
+static int __init stac9766_init(void)
+{
+        return platform_driver_register(&stac9766_codec_driver);
+}
+module_init(stac9766_init);
+
+static void __exit stac9766_exit(void)
+{
+        platform_driver_unregister(&stac9766_codec_driver);
+}
+module_exit(stac9766_exit);
 
 MODULE_DESCRIPTION("ASoC stac9766 driver");
 MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
diff --git a/sound/soc/codecs/stac9766.h b/sound/soc/codecs/stac9766.h
index 65642eb8393e..c726f907e2c0 100644
--- a/sound/soc/codecs/stac9766.h
+++ b/sound/soc/codecs/stac9766.h
@@ -14,8 +14,4 @@
 #define STAC9766_DAI_AC97_ANALOG                0
 #define STAC9766_DAI_AC97_DIGITAL               1
 
-extern struct snd_soc_dai stac9766_dai[];
-extern struct snd_soc_codec_device soc_codec_dev_stac9766;
-
-
 #endif
diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c
index 0a4b0fef3355..33bb52f3f683 100644
--- a/sound/soc/codecs/tlv320aic23.c
+++ b/sound/soc/codecs/tlv320aic23.c
@@ -30,7 +30,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 #include <sound/initval.h>
 
@@ -213,7 +212,7 @@ static const struct snd_soc_dapm_widget tlv320aic23_dapm_widgets[] = {
         SND_SOC_DAPM_INPUT("MICIN"),
 };
 
-static const struct snd_soc_dapm_route intercon[] = {
+static const struct snd_soc_dapm_route tlv320aic23_intercon[] = {
         /* Output Mixer */
         {"Output Mixer", "Line Bypass Switch", "Line Input"},
         {"Output Mixer", "Playback Switch", "DAC"},
@@ -240,7 +239,8 @@ static const struct snd_soc_dapm_route intercon[] = {
 
 /* AIC23 driver data */
 struct aic23 {
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
+        void *control_data;
         int mclk;
         int requested_adc;
         int requested_dac;
@@ -388,27 +388,15 @@ static int set_sample_rate_control(struct snd_soc_codec *codec, int mclk,
         return 0;
 }
 
-static int tlv320aic23_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, tlv320aic23_dapm_widgets,
-                                  ARRAY_SIZE(tlv320aic23_dapm_widgets));
-
-        /* set up audio path interconnects */
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
-
-        return 0;
-}
-
 static int tlv320aic23_hw_params(struct snd_pcm_substream *substream,
                                  struct snd_pcm_hw_params *params,
                                  struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 iface_reg;
         int ret;
-        struct aic23 *aic23 = container_of(codec, struct aic23, codec);
+        struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec);
         u32 sample_rate_adc = aic23->requested_adc;
         u32 sample_rate_dac = aic23->requested_dac;
         u32 sample_rate = params_rate(params);
@@ -452,8 +440,7 @@ static int tlv320aic23_pcm_prepare(struct snd_pcm_substream *substream,
                                    struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
 
         /* set active */
         tlv320aic23_write(codec, TLV320AIC23_ACTIVE, 0x0001);
@@ -465,9 +452,8 @@ static void tlv320aic23_shutdown(struct snd_pcm_substream *substream,
                                  struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-        struct aic23 *aic23 = container_of(codec, struct aic23, codec);
+        struct snd_soc_codec *codec = rtd->codec;
+        struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec);
 
         /* deactivate */
         if (!codec->active) {
@@ -546,8 +532,7 @@ static int tlv320aic23_set_dai_fmt(struct snd_soc_dai *codec_dai,
 static int tlv320aic23_set_dai_sysclk(struct snd_soc_dai *codec_dai,
                                       int clk_id, unsigned int freq, int dir)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
-        struct aic23 *aic23 = container_of(codec, struct aic23, codec);
+        struct aic23 *aic23 = snd_soc_dai_get_drvdata(codec_dai);
         aic23->mclk = freq;
         return 0;
 }
@@ -577,7 +562,7 @@ static int tlv320aic23_set_bias_level(struct snd_soc_codec *codec,
                 tlv320aic23_write(codec, TLV320AIC23_PWR, 0xffff);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -594,8 +579,8 @@ static struct snd_soc_dai_ops tlv320aic23_dai_ops = {
         .set_sysclk     = tlv320aic23_set_dai_sysclk,
 };
 
-struct snd_soc_dai tlv320aic23_dai = {
-        .name = "tlv320aic23",
+static struct snd_soc_dai_driver tlv320aic23_dai = {
+        .name = "tlv320aic23-hifi",
         .playback = {
                      .stream_name = "Playback",
                      .channels_min = 2,
@@ -610,23 +595,17 @@ struct snd_soc_dai tlv320aic23_dai = {
                     .formats = AIC23_FORMATS,},
         .ops = &tlv320aic23_dai_ops,
 };
-EXPORT_SYMBOL_GPL(tlv320aic23_dai);
 
-static int tlv320aic23_suspend(struct platform_device *pdev,
+static int tlv320aic23_suspend(struct snd_soc_codec *codec,
                                pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         tlv320aic23_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int tlv320aic23_resume(struct platform_device *pdev)
+static int tlv320aic23_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         u16 reg;
 
         /* Sync reg_cache with the hardware */
@@ -639,39 +618,19 @@ static int tlv320aic23_resume(struct platform_device *pdev)
         return 0;
 }
 
-/*
- * initialise the AIC23 driver
- * register the mixer and dsp interfaces with the kernel
- */
-static int tlv320aic23_init(struct snd_soc_device *socdev)
+static int tlv320aic23_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int ret = 0;
-        u16 reg;
+        struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec);
+        int reg;
 
-        codec->name = "tlv320aic23";
-        codec->owner = THIS_MODULE;
-        codec->read = tlv320aic23_read_reg_cache;
-        codec->write = tlv320aic23_write;
-        codec->set_bias_level = tlv320aic23_set_bias_level;
-        codec->dai = &tlv320aic23_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(tlv320aic23_reg);
-        codec->reg_cache =
-            kmemdup(tlv320aic23_reg, sizeof(tlv320aic23_reg), GFP_KERNEL);
-        if (codec->reg_cache == NULL)
-                return -ENOMEM;
+        printk(KERN_INFO "AIC23 Audio Codec %s\n", AIC23_VERSION);
+        codec->control_data = aic23->control_data;
+        codec->hw_write = (hw_write_t)i2c_master_send;
+        codec->hw_read = NULL;
 
         /* Reset codec */
         tlv320aic23_write(codec, TLV320AIC23_RESET, 0);
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "tlv320aic23: failed to create pcms\n");
-                goto pcm_err;
-        }
-
         /* power on device */
         tlv320aic23_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
@@ -705,15 +664,32 @@ static int tlv320aic23_init(struct snd_soc_device *socdev)
 
         snd_soc_add_controls(codec, tlv320aic23_snd_controls,
                                 ARRAY_SIZE(tlv320aic23_snd_controls));
-        tlv320aic23_add_widgets(codec);
 
-        return ret;
+        return 0;
+}
 
-pcm_err:
-        kfree(codec->reg_cache);
-        return ret;
+static int tlv320aic23_remove(struct snd_soc_codec *codec)
+{
+        tlv320aic23_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
-static struct snd_soc_device *tlv320aic23_socdev;
+
+static struct snd_soc_codec_driver soc_codec_dev_tlv320aic23 = {
+        .reg_cache_size = ARRAY_SIZE(tlv320aic23_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = tlv320aic23_reg,
+        .probe = tlv320aic23_probe,
+        .remove = tlv320aic23_remove,
+        .suspend = tlv320aic23_suspend,
+        .resume = tlv320aic23_resume,
+        .read = tlv320aic23_read_reg_cache,
+        .write = tlv320aic23_write,
+        .set_bias_level = tlv320aic23_set_bias_level,
+        .dapm_widgets = tlv320aic23_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(tlv320aic23_dapm_widgets),
+        .dapm_routes = tlv320aic23_intercon,
+        .num_dapm_routes = ARRAY_SIZE(tlv320aic23_intercon),
+};
 
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 /*
@@ -723,31 +699,30 @@ static struct snd_soc_device *tlv320aic23_socdev;
 static int tlv320aic23_codec_probe(struct i2c_client *i2c,
                                    const struct i2c_device_id *i2c_id)
 {
-        struct snd_soc_device *socdev = tlv320aic23_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct aic23 *aic23;
         int ret;
 
         if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
                 return -EINVAL;
 
-        i2c_set_clientdata(i2c, codec);
-        codec->control_data = i2c;
+        aic23 = kzalloc(sizeof(struct aic23), GFP_KERNEL);
+        if (aic23 == NULL)
+                return -ENOMEM;
 
-        ret = tlv320aic23_init(socdev);
-        if (ret < 0) {
-                printk(KERN_ERR "tlv320aic23: failed to initialise AIC23\n");
-                goto err;
-        }
-        return ret;
+        i2c_set_clientdata(i2c, aic23);
+        aic23->control_data = i2c;
+        aic23->control_type = SND_SOC_I2C;
 
-err:
-        kfree(codec);
-        kfree(i2c);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_tlv320aic23, &tlv320aic23_dai, 1);
+        if (ret < 0)
+                kfree(aic23);
         return ret;
 }
 static int __exit tlv320aic23_i2c_remove(struct i2c_client *i2c)
 {
-        put_device(&i2c->dev);
+        snd_soc_unregister_codec(&i2c->dev);
+        kfree(i2c_get_clientdata(i2c));
         return 0;
 }
 
@@ -760,7 +735,7 @@ MODULE_DEVICE_TABLE(i2c, tlv320aic23_id);
 
 static struct i2c_driver tlv320aic23_i2c_driver = {
         .driver = {
-                   .name = "tlv320aic23",
+                   .name = "tlv320aic23-codec",
                    },
         .probe = tlv320aic23_codec_probe,
         .remove = __exit_p(tlv320aic23_i2c_remove),
@@ -769,71 +744,25 @@ static struct i2c_driver tlv320aic23_i2c_driver = {
 
 #endif
 
-static int tlv320aic23_probe(struct platform_device *pdev)
+static int __init tlv320aic23_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        struct aic23 *aic23;
-        int ret = 0;
-
-        printk(KERN_INFO "AIC23 Audio Codec %s\n", AIC23_VERSION);
-
-        aic23 = kzalloc(sizeof(struct aic23), GFP_KERNEL);
-        if (aic23 == NULL)
-                return -ENOMEM;
-        codec = &aic23->codec;
-        socdev->card->codec = codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        tlv320aic23_socdev = socdev;
+        int ret;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        codec->hw_write = (hw_write_t) i2c_master_send;
-        codec->hw_read = NULL;
         ret = i2c_add_driver(&tlv320aic23_i2c_driver);
-        if (ret != 0)
-                printk(KERN_ERR "can't add i2c driver");
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register TLV320AIC23 I2C driver: %d\n",
+                       ret);
+        }
 #endif
         return ret;
 }
+module_init(tlv320aic23_modinit);
 
-static int tlv320aic23_remove(struct platform_device *pdev)
+static void __exit tlv320aic23_exit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-        struct aic23 *aic23 = container_of(codec, struct aic23, codec);
-
-        if (codec->control_data)
-                tlv320aic23_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&tlv320aic23_i2c_driver);
 #endif
-        kfree(codec->reg_cache);
-        kfree(aic23);
-
-        return 0;
-}
-struct snd_soc_codec_device soc_codec_dev_tlv320aic23 = {
-        .probe = tlv320aic23_probe,
-        .remove = tlv320aic23_remove,
-        .suspend = tlv320aic23_suspend,
-        .resume = tlv320aic23_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320aic23);
-
-static int __init tlv320aic23_modinit(void)
-{
-        return snd_soc_register_dai(&tlv320aic23_dai);
-}
-module_init(tlv320aic23_modinit);
-
-static void __exit tlv320aic23_exit(void)
-{
-        snd_soc_unregister_dai(&tlv320aic23_dai);
 }
 module_exit(tlv320aic23_exit);
 
diff --git a/sound/soc/codecs/tlv320aic23.h b/sound/soc/codecs/tlv320aic23.h
index 79d1faf8e570..e804120bd3da 100644
--- a/sound/soc/codecs/tlv320aic23.h
+++ b/sound/soc/codecs/tlv320aic23.h
@@ -116,7 +116,4 @@
 #define TLV320AIC23_SIDETONE_12         0x080
 #define TLV320AIC23_SIDETONE_18         0x0c0
 
-extern struct snd_soc_dai tlv320aic23_dai;
-extern struct snd_soc_codec_device soc_codec_dev_tlv320aic23;
-
 #endif /* _TLV320AIC23_H */
diff --git a/sound/soc/codecs/tlv320aic26.c b/sound/soc/codecs/tlv320aic26.c
index f0e00fd4b435..7859bdcc93db 100644
--- a/sound/soc/codecs/tlv320aic26.c
+++ b/sound/soc/codecs/tlv320aic26.c
@@ -18,8 +18,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
-#include <sound/soc-of-simple.h>
 #include <sound/initval.h>
 
 #include "tlv320aic26.h"
@@ -32,7 +30,6 @@ MODULE_LICENSE("GPL");
 struct aic26 {
         struct spi_device *spi;
         struct snd_soc_codec codec;
-        u16 reg_cache[AIC26_NUM_REGS];  /* shadow registers */
         int master;
         int datfm;
         int mclk;
@@ -130,8 +127,7 @@ static int aic26_hw_params(struct snd_pcm_substream *substream,
                            struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec);
         int fsref, divisor, wlen, pval, jval, dval, qval;
         u16 reg;
@@ -165,10 +161,18 @@ static int aic26_hw_params(struct snd_pcm_substream *substream,
                 dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
         }
 
-        /* Configure PLL */
+        /**
+         * Configure PLL
+         * fsref = (mclk * PLLM) / 2048
+         * where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal)
+         */
         pval = 1;
-        jval = (fsref == 44100) ? 7 : 8;
-        dval = (fsref == 44100) ? 5264 : 1920;
+        /* compute J portion of multiplier */
+        jval = fsref / (aic26->mclk / 2048);
+        /* compute fractional DDDD component of multiplier */
+        dval = fsref - (jval * (aic26->mclk / 2048));
+        dval = (10000 * dval) / (aic26->mclk / 2048);
+        dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval);
         qval = 0;
         reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;
         aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);
@@ -278,8 +282,8 @@ static struct snd_soc_dai_ops aic26_dai_ops = {
         .set_fmt        = aic26_set_fmt,
 };
 
-struct snd_soc_dai aic26_dai = {
-        .name = "tlv320aic26",
+static struct snd_soc_dai_driver aic26_dai = {
+        .name = "tlv320aic26-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -296,7 +300,6 @@ struct snd_soc_dai aic26_dai = {
         },
         .ops = &aic26_dai_ops,
 };
-EXPORT_SYMBOL_GPL(aic26_dai);
 
 /* ---------------------------------------------------------------------
  * ALSA controls
@@ -319,61 +322,6 @@ static const struct snd_kcontrol_new aic26_snd_controls[] = {
 };
 
 /* ---------------------------------------------------------------------
- * SoC CODEC portion of driver: probe and release routines
- */
-static int aic26_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        struct aic26 *aic26;
-        int ret, err;
-
-        dev_info(&pdev->dev, "Probing AIC26 SoC CODEC driver\n");
-        dev_dbg(&pdev->dev, "socdev=%p\n", socdev);
-        dev_dbg(&pdev->dev, "codec_data=%p\n", socdev->codec_data);
-
-        /* Fetch the relevant aic26 private data here (it's already been
-         * stored in the .codec pointer) */
-        aic26 = socdev->codec_data;
-        if (aic26 == NULL) {
-                dev_err(&pdev->dev, "aic26: missing codec pointer\n");
-                return -ENODEV;
-        }
-        codec = &aic26->codec;
-        socdev->card->codec = codec;
-
-        dev_dbg(&pdev->dev, "Registering PCMs, dev=%p, socdev->dev=%p\n",
-                &pdev->dev, socdev->dev);
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "aic26: failed to create pcms\n");
-                return -ENODEV;
-        }
-
-        /* register controls */
-        dev_dbg(&pdev->dev, "Registering controls\n");
-        err = snd_soc_add_controls(codec, aic26_snd_controls,
-                        ARRAY_SIZE(aic26_snd_controls));
-        WARN_ON(err < 0);
-
-        return 0;
-}
-
-static int aic26_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        snd_soc_free_pcms(socdev);
-        return 0;
-}
-
-struct snd_soc_codec_device aic26_soc_codec_dev = {
-        .probe = aic26_probe,
-        .remove = aic26_remove,
-};
-EXPORT_SYMBOL_GPL(aic26_soc_codec_dev);
-
-/* ---------------------------------------------------------------------
  * SPI device portion of driver: sysfs files for debugging
  */
 
@@ -409,13 +357,61 @@ static ssize_t aic26_keyclick_set(struct device *dev,
 static DEVICE_ATTR(keyclick, 0644, aic26_keyclick_show, aic26_keyclick_set);
 
 /* ---------------------------------------------------------------------
+ * SoC CODEC portion of driver: probe and release routines
+ */
+static int aic26_probe(struct snd_soc_codec *codec)
+{
+        int ret, err, i, reg;
+
+        dev_info(codec->dev, "Probing AIC26 SoC CODEC driver\n");
+
+        /* Reset the codec to power on defaults */
+        aic26_reg_write(codec, AIC26_REG_RESET, 0xBB00);
+
+        /* Power up CODEC */
+        aic26_reg_write(codec, AIC26_REG_POWER_CTRL, 0);
+
+        /* Audio Control 3 (master mode, fsref rate) */
+        reg = aic26_reg_read(codec, AIC26_REG_AUDIO_CTRL3);
+        reg &= ~0xf800;
+        reg |= 0x0800; /* set master mode */
+        aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg);
+
+        /* Fill register cache */
+        for (i = 0; i < codec->driver->reg_cache_size; i++)
+                aic26_reg_read(codec, i);
+
+        /* Register the sysfs files for debugging */
+        /* Create SysFS files */
+        ret = device_create_file(codec->dev, &dev_attr_keyclick);
+        if (ret)
+                dev_info(codec->dev, "error creating sysfs files\n");
+
+        /* register controls */
+        dev_dbg(codec->dev, "Registering controls\n");
+        err = snd_soc_add_controls(codec, aic26_snd_controls,
+                        ARRAY_SIZE(aic26_snd_controls));
+        WARN_ON(err < 0);
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver aic26_soc_codec_dev = {
+        .probe = aic26_probe,
+        .read = aic26_reg_read,
+        .write = aic26_reg_write,
+        .reg_cache_size = AIC26_NUM_REGS,
+        .reg_word_size = sizeof(u16),
+};
+
+/* ---------------------------------------------------------------------
  * SPI device portion of driver: probe and release routines and SPI
  *                               driver registration.
  */
 static int aic26_spi_probe(struct spi_device *spi)
 {
         struct aic26 *aic26;
-        int ret, i, reg;
+        int ret;
 
         dev_dbg(&spi->dev, "probing tlv320aic26 spi device\n");
 
@@ -427,59 +423,13 @@ static int aic26_spi_probe(struct spi_device *spi)
         /* Initialize the driver data */
         aic26->spi = spi;
         dev_set_drvdata(&spi->dev, aic26);
-
-        /* Setup what we can in the codec structure so that the register
-         * access functions will work as expected.  More will be filled
-         * out when it is probed by the SoC CODEC part of this driver */
-        snd_soc_codec_set_drvdata(&aic26->codec, aic26);
-        aic26->codec.name = "aic26";
-        aic26->codec.owner = THIS_MODULE;
-        aic26->codec.dai = &aic26_dai;
-        aic26->codec.num_dai = 1;
-        aic26->codec.read = aic26_reg_read;
-        aic26->codec.write = aic26_reg_write;
         aic26->master = 1;
-        mutex_init(&aic26->codec.mutex);
-        INIT_LIST_HEAD(&aic26->codec.dapm_widgets);
-        INIT_LIST_HEAD(&aic26->codec.dapm_paths);
-        aic26->codec.reg_cache_size = AIC26_NUM_REGS;
-        aic26->codec.reg_cache = aic26->reg_cache;
-
-        aic26_dai.dev = &spi->dev;
-        ret = snd_soc_register_dai(&aic26_dai);
-        if (ret != 0) {
-                dev_err(&spi->dev, "Failed to register DAI: %d\n", ret);
-                kfree(aic26);
-                return ret;
-        }
-
-        /* Reset the codec to power on defaults */
-        aic26_reg_write(&aic26->codec, AIC26_REG_RESET, 0xBB00);
-
-        /* Power up CODEC */
-        aic26_reg_write(&aic26->codec, AIC26_REG_POWER_CTRL, 0);
-
-        /* Audio Control 3 (master mode, fsref rate) */
-        reg = aic26_reg_read(&aic26->codec, AIC26_REG_AUDIO_CTRL3);
-        reg &= ~0xf800;
-        reg |= 0x0800; /* set master mode */
-        aic26_reg_write(&aic26->codec, AIC26_REG_AUDIO_CTRL3, reg);
 
-        /* Fill register cache */
-        for (i = 0; i < ARRAY_SIZE(aic26->reg_cache); i++)
-                aic26_reg_read(&aic26->codec, i);
-
-        /* Register the sysfs files for debugging */
-        /* Create SysFS files */
-        ret = device_create_file(&spi->dev, &dev_attr_keyclick);
-        if (ret)
-                dev_info(&spi->dev, "error creating sysfs files\n");
-
-#if defined(CONFIG_SND_SOC_OF_SIMPLE)
-        /* Tell the of_soc helper about this codec */
-        of_snd_soc_register_codec(&aic26_soc_codec_dev, aic26, &aic26_dai,
-                                  spi->dev.archdata.of_node);
-#endif
+        ret = snd_soc_register_codec(&spi->dev,
+                        &aic26_soc_codec_dev, &aic26_dai, 1);
+        if (ret < 0)
+                kfree(aic26);
+        return ret;
 
         dev_dbg(&spi->dev, "SPI device initialized\n");
         return 0;
@@ -487,17 +437,14 @@ static int aic26_spi_probe(struct spi_device *spi)
 
 static int aic26_spi_remove(struct spi_device *spi)
 {
-        struct aic26 *aic26 = dev_get_drvdata(&spi->dev);
-
-        snd_soc_unregister_dai(&aic26_dai);
-        kfree(aic26);
-
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
 }
 
 static struct spi_driver aic26_spi = {
         .driver = {
-                .name = "tlv320aic26",
+                .name = "tlv320aic26-codec",
                 .owner = THIS_MODULE,
         },
         .probe = aic26_spi_probe,
diff --git a/sound/soc/codecs/tlv320aic26.h b/sound/soc/codecs/tlv320aic26.h
index 786ba16c945f..67f19c3bebe6 100644
--- a/sound/soc/codecs/tlv320aic26.h
+++ b/sound/soc/codecs/tlv320aic26.h
@@ -14,14 +14,14 @@
 #define AIC26_PAGE_ADDR(page, offset)   ((page << 6) | offset)
 #define AIC26_NUM_REGS                  AIC26_PAGE_ADDR(3, 0)
 
-/* Page 0: Auxillary data registers */
+/* Page 0: Auxiliary data registers */
 #define AIC26_REG_BAT1                  AIC26_PAGE_ADDR(0, 0x05)
 #define AIC26_REG_BAT2                  AIC26_PAGE_ADDR(0, 0x06)
 #define AIC26_REG_AUX                   AIC26_PAGE_ADDR(0, 0x07)
 #define AIC26_REG_TEMP1                 AIC26_PAGE_ADDR(0, 0x09)
 #define AIC26_REG_TEMP2                 AIC26_PAGE_ADDR(0, 0x0A)
 
-/* Page 1: Auxillary control registers */
+/* Page 1: Auxiliary control registers */
 #define AIC26_REG_AUX_ADC               AIC26_PAGE_ADDR(1, 0x00)
 #define AIC26_REG_STATUS                AIC26_PAGE_ADDR(1, 0x01)
 #define AIC26_REG_REFERENCE             AIC26_PAGE_ADDR(1, 0x03)
@@ -90,7 +90,4 @@ enum aic26_wlen {
         AIC26_WLEN_32   = 3 << 10,
 };
 
-extern struct snd_soc_dai aic26_dai;
-extern struct snd_soc_codec_device aic26_soc_codec_dev;
-
 #endif /* _TLV320AIC16_H_ */
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c
new file mode 100644
index 000000000000..e93b9d1ae1dd
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic32x4.c
@@ -0,0 +1,794 @@
+/*
+ * linux/sound/soc/codecs/tlv320aic32x4.c
+ *
+ * Copyright 2011 Vista Silicon S.L.
+ *
+ * Author: Javier Martin <javier.martin@vista-silicon.com>
+ *
+ * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/cdev.h>
+#include <linux/slab.h>
+
+#include <sound/tlv320aic32x4.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "tlv320aic32x4.h"
+
+struct aic32x4_rate_divs {
+        u32 mclk;
+        u32 rate;
+        u8 p_val;
+        u8 pll_j;
+        u16 pll_d;
+        u16 dosr;
+        u8 ndac;
+        u8 mdac;
+        u8 aosr;
+        u8 nadc;
+        u8 madc;
+        u8 blck_N;
+};
+
+struct aic32x4_priv {
+        u32 sysclk;
+        s32 master;
+        u8 page_no;
+        void *control_data;
+        u32 power_cfg;
+        u32 micpga_routing;
+        bool swapdacs;
+};
+
+/* 0dB min, 1dB steps */
+static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0);
+/* 0dB min, 0.5dB steps */
+static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
+
+static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
+        SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
+                        AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5),
+        SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
+                        AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1),
+        SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
+                        AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1),
+        SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
+                        AIC32X4_HPRGAIN, 6, 0x01, 1),
+        SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
+                        AIC32X4_LORGAIN, 6, 0x01, 1),
+        SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
+                        AIC32X4_RMICPGAVOL, 7, 0x01, 1),
+
+        SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
+        SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
+
+        SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL,
+                        AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5),
+        SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
+                        AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
+
+        SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
+
+        SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
+        SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
+        SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
+                        4, 0x07, 0),
+        SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
+                        0, 0x03, 0),
+        SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
+                        6, 0x03, 0),
+        SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
+                        1, 0x1F, 0),
+        SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
+                        0, 0x7F, 0),
+        SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
+                        3, 0x1F, 0),
+        SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
+                        3, 0x1F, 0),
+        SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
+                        0, 0x1F, 0),
+        SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
+                        0, 0x0F, 0),
+};
+
+static const struct aic32x4_rate_divs aic32x4_divs[] = {
+        /* 8k rate */
+        {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
+        {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
+        {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
+        /* 11.025k rate */
+        {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
+        {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
+        /* 16k rate */
+        {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
+        {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
+        {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
+        /* 22.05k rate */
+        {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
+        {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
+        {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
+        /* 32k rate */
+        {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
+        {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
+        /* 44.1k rate */
+        {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
+        {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
+        {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
+        /* 48k rate */
+        {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
+        {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
+        {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
+};
+
+static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
+        SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
+};
+
+static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
+        SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
+};
+
+static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
+};
+
+static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
+};
+
+static const struct snd_kcontrol_new left_input_mixer_controls[] = {
+        SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
+        SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
+};
+
+static const struct snd_kcontrol_new right_input_mixer_controls[] = {
+        SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
+        SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
+        SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
+        SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
+                           &hpl_output_mixer_controls[0],
+                           ARRAY_SIZE(hpl_output_mixer_controls)),
+        SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
+
+        SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
+                           &lol_output_mixer_controls[0],
+                           ARRAY_SIZE(lol_output_mixer_controls)),
+        SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
+
+        SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
+        SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
+                           &hpr_output_mixer_controls[0],
+                           ARRAY_SIZE(hpr_output_mixer_controls)),
+        SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
+        SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
+                           &lor_output_mixer_controls[0],
+                           ARRAY_SIZE(lor_output_mixer_controls)),
+        SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
+        SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
+                           &left_input_mixer_controls[0],
+                           ARRAY_SIZE(left_input_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
+                           &right_input_mixer_controls[0],
+                           ARRAY_SIZE(right_input_mixer_controls)),
+        SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
+        SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
+        SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
+
+        SND_SOC_DAPM_OUTPUT("HPL"),
+        SND_SOC_DAPM_OUTPUT("HPR"),
+        SND_SOC_DAPM_OUTPUT("LOL"),
+        SND_SOC_DAPM_OUTPUT("LOR"),
+        SND_SOC_DAPM_INPUT("IN1_L"),
+        SND_SOC_DAPM_INPUT("IN1_R"),
+        SND_SOC_DAPM_INPUT("IN2_L"),
+        SND_SOC_DAPM_INPUT("IN2_R"),
+        SND_SOC_DAPM_INPUT("IN3_L"),
+        SND_SOC_DAPM_INPUT("IN3_R"),
+};
+
+static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
+        /* Left Output */
+        {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
+        {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
+
+        {"HPL Power", NULL, "HPL Output Mixer"},
+        {"HPL", NULL, "HPL Power"},
+
+        {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
+
+        {"LOL Power", NULL, "LOL Output Mixer"},
+        {"LOL", NULL, "LOL Power"},
+
+        /* Right Output */
+        {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
+        {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
+
+        {"HPR Power", NULL, "HPR Output Mixer"},
+        {"HPR", NULL, "HPR Power"},
+
+        {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
+
+        {"LOR Power", NULL, "LOR Output Mixer"},
+        {"LOR", NULL, "LOR Power"},
+
+        /* Left input */
+        {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
+        {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
+        {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
+
+        {"Left ADC", NULL, "Left Input Mixer"},
+
+        /* Right Input */
+        {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
+        {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
+        {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
+
+        {"Right ADC", NULL, "Right Input Mixer"},
+};
+
+static inline int aic32x4_change_page(struct snd_soc_codec *codec,
+                                        unsigned int new_page)
+{
+        struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
+        u8 data[2];
+        int ret;
+
+        data[0] = 0x00;
+        data[1] = new_page & 0xff;
+
+        ret = codec->hw_write(codec->control_data, data, 2);
+        if (ret == 2) {
+                aic32x4->page_no = new_page;
+                return 0;
+        } else {
+                return ret;
+        }
+}
+
+static int aic32x4_write(struct snd_soc_codec *codec, unsigned int reg,
+                                unsigned int val)
+{
+        struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
+        unsigned int page = reg / 128;
+        unsigned int fixed_reg = reg % 128;
+        u8 data[2];
+        int ret;
+
+        /* A write to AIC32X4_PSEL is really a non-explicit page change */
+        if (reg == AIC32X4_PSEL)
+                return aic32x4_change_page(codec, val);
+
+        if (aic32x4->page_no != page) {
+                ret = aic32x4_change_page(codec, page);
+                if (ret != 0)
+                        return ret;
+        }
+
+        data[0] = fixed_reg & 0xff;
+        data[1] = val & 0xff;
+
+        if (codec->hw_write(codec->control_data, data, 2) == 2)
+                return 0;
+        else
+                return -EIO;
+}
+
+static unsigned int aic32x4_read(struct snd_soc_codec *codec, unsigned int reg)
+{
+        struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
+        unsigned int page = reg / 128;
+        unsigned int fixed_reg = reg % 128;
+        int ret;
+
+        if (aic32x4->page_no != page) {
+                ret = aic32x4_change_page(codec, page);
+                if (ret != 0)
+                        return ret;
+        }
+        return i2c_smbus_read_byte_data(codec->control_data, fixed_reg & 0xff);
+}
+
+static inline int aic32x4_get_divs(int mclk, int rate)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
+                if ((aic32x4_divs[i].rate == rate)
+                    && (aic32x4_divs[i].mclk == mclk)) {
+                        return i;
+                }
+        }
+        printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
+        return -EINVAL;
+}
+
+static int aic32x4_add_widgets(struct snd_soc_codec *codec)
+{
+        snd_soc_dapm_new_controls(&codec->dapm, aic32x4_dapm_widgets,
+                                  ARRAY_SIZE(aic32x4_dapm_widgets));
+
+        snd_soc_dapm_add_routes(&codec->dapm, aic32x4_dapm_routes,
+                                ARRAY_SIZE(aic32x4_dapm_routes));
+
+        snd_soc_dapm_new_widgets(&codec->dapm);
+        return 0;
+}
+
+static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                                  int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
+
+        switch (freq) {
+        case AIC32X4_FREQ_12000000:
+        case AIC32X4_FREQ_24000000:
+        case AIC32X4_FREQ_25000000:
+                aic32x4->sysclk = freq;
+                return 0;
+        }
+        printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
+        return -EINVAL;
+}
+
+static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
+        u8 iface_reg_1;
+        u8 iface_reg_2;
+        u8 iface_reg_3;
+
+        iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
+        iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
+        iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
+        iface_reg_2 = 0;
+        iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
+        iface_reg_3 = iface_reg_3 & ~(1 << 3);
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                aic32x4->master = 1;
+                iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                aic32x4->master = 0;
+                break;
+        default:
+                printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+                iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
+                iface_reg_3 |= (1 << 3); /* invert bit clock */
+                iface_reg_2 = 0x01; /* add offset 1 */
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
+                iface_reg_3 |= (1 << 3); /* invert bit clock */
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                iface_reg_1 |=
+                        (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                iface_reg_1 |=
+                        (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
+                break;
+        default:
+                printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
+                return -EINVAL;
+        }
+
+        snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
+        snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
+        snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
+        return 0;
+}
+
+static int aic32x4_hw_params(struct snd_pcm_substream *substream,
+                             struct snd_pcm_hw_params *params,
+                             struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
+        u8 data;
+        int i;
+
+        i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
+        if (i < 0) {
+                printk(KERN_ERR "aic32x4: sampling rate not supported\n");
+                return i;
+        }
+
+        /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
+        snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
+        snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
+
+        /* We will fix R value to 1 and will make P & J=K.D as varialble */
+        data = snd_soc_read(codec, AIC32X4_PLLPR);
+        data &= ~(7 << 4);
+        snd_soc_write(codec, AIC32X4_PLLPR,
+                      (data | (aic32x4_divs[i].p_val << 4) | 0x01));
+
+        snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
+
+        snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
+        snd_soc_write(codec, AIC32X4_PLLDLSB,
+                      (aic32x4_divs[i].pll_d & 0xff));
+
+        /* NDAC divider value */
+        data = snd_soc_read(codec, AIC32X4_NDAC);
+        data &= ~(0x7f);
+        snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
+
+        /* MDAC divider value */
+        data = snd_soc_read(codec, AIC32X4_MDAC);
+        data &= ~(0x7f);
+        snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
+
+        /* DOSR MSB & LSB values */
+        snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
+        snd_soc_write(codec, AIC32X4_DOSRLSB,
+                      (aic32x4_divs[i].dosr & 0xff));
+
+        /* NADC divider value */
+        data = snd_soc_read(codec, AIC32X4_NADC);
+        data &= ~(0x7f);
+        snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
+
+        /* MADC divider value */
+        data = snd_soc_read(codec, AIC32X4_MADC);
+        data &= ~(0x7f);
+        snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
+
+        /* AOSR value */
+        snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
+
+        /* BCLK N divider */
+        data = snd_soc_read(codec, AIC32X4_BCLKN);
+        data &= ~(0x7f);
+        snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
+
+        data = snd_soc_read(codec, AIC32X4_IFACE1);
+        data = data & ~(3 << 4);
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
+                break;
+        }
+        snd_soc_write(codec, AIC32X4_IFACE1, data);
+
+        return 0;
+}
+
+static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        u8 dac_reg;
+
+        dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
+        if (mute)
+                snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
+        else
+                snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
+        return 0;
+}
+
+static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
+                                  enum snd_soc_bias_level level)
+{
+        struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
+        u8 value;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                if (aic32x4->master) {
+                        /* Switch on PLL */
+                        value = snd_soc_read(codec, AIC32X4_PLLPR);
+                        snd_soc_write(codec, AIC32X4_PLLPR,
+                                      (value | AIC32X4_PLLEN));
+
+                        /* Switch on NDAC Divider */
+                        value = snd_soc_read(codec, AIC32X4_NDAC);
+                        snd_soc_write(codec, AIC32X4_NDAC,
+                                      value | AIC32X4_NDACEN);
+
+                        /* Switch on MDAC Divider */
+                        value = snd_soc_read(codec, AIC32X4_MDAC);
+                        snd_soc_write(codec, AIC32X4_MDAC,
+                                      value | AIC32X4_MDACEN);
+
+                        /* Switch on NADC Divider */
+                        value = snd_soc_read(codec, AIC32X4_NADC);
+                        snd_soc_write(codec, AIC32X4_NADC,
+                                      value | AIC32X4_MDACEN);
+
+                        /* Switch on MADC Divider */
+                        value = snd_soc_read(codec, AIC32X4_MADC);
+                        snd_soc_write(codec, AIC32X4_MADC,
+                                      value | AIC32X4_MDACEN);
+
+                        /* Switch on BCLK_N Divider */
+                        value = snd_soc_read(codec, AIC32X4_BCLKN);
+                        snd_soc_write(codec, AIC32X4_BCLKN,
+                                      value | AIC32X4_BCLKEN);
+                }
+                break;
+        case SND_SOC_BIAS_PREPARE:
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                if (aic32x4->master) {
+                        /* Switch off PLL */
+                        value = snd_soc_read(codec, AIC32X4_PLLPR);
+                        snd_soc_write(codec, AIC32X4_PLLPR,
+                                      (value & ~AIC32X4_PLLEN));
+
+                        /* Switch off NDAC Divider */
+                        value = snd_soc_read(codec, AIC32X4_NDAC);
+                        snd_soc_write(codec, AIC32X4_NDAC,
+                                      value & ~AIC32X4_NDACEN);
+
+                        /* Switch off MDAC Divider */
+                        value = snd_soc_read(codec, AIC32X4_MDAC);
+                        snd_soc_write(codec, AIC32X4_MDAC,
+                                      value & ~AIC32X4_MDACEN);
+
+                        /* Switch off NADC Divider */
+                        value = snd_soc_read(codec, AIC32X4_NADC);
+                        snd_soc_write(codec, AIC32X4_NADC,
+                                      value & ~AIC32X4_NDACEN);
+
+                        /* Switch off MADC Divider */
+                        value = snd_soc_read(codec, AIC32X4_MADC);
+                        snd_soc_write(codec, AIC32X4_MADC,
+                                      value & ~AIC32X4_MDACEN);
+                        value = snd_soc_read(codec, AIC32X4_BCLKN);
+
+                        /* Switch off BCLK_N Divider */
+                        snd_soc_write(codec, AIC32X4_BCLKN,
+                                      value & ~AIC32X4_BCLKEN);
+                }
+                break;
+        case SND_SOC_BIAS_OFF:
+                break;
+        }
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#define AIC32X4_RATES   SNDRV_PCM_RATE_8000_48000
+#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
+                         | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops aic32x4_ops = {
+        .hw_params = aic32x4_hw_params,
+        .digital_mute = aic32x4_mute,
+        .set_fmt = aic32x4_set_dai_fmt,
+        .set_sysclk = aic32x4_set_dai_sysclk,
+};
+
+static struct snd_soc_dai_driver aic32x4_dai = {
+        .name = "tlv320aic32x4-hifi",
+        .playback = {
+                     .stream_name = "Playback",
+                     .channels_min = 1,
+                     .channels_max = 2,
+                     .rates = AIC32X4_RATES,
+                     .formats = AIC32X4_FORMATS,},
+        .capture = {
+                    .stream_name = "Capture",
+                    .channels_min = 1,
+                    .channels_max = 2,
+                    .rates = AIC32X4_RATES,
+                    .formats = AIC32X4_FORMATS,},
+        .ops = &aic32x4_ops,
+        .symmetric_rates = 1,
+};
+
+static int aic32x4_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int aic32x4_resume(struct snd_soc_codec *codec)
+{
+        aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+
+static int aic32x4_probe(struct snd_soc_codec *codec)
+{
+        struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
+        u32 tmp_reg;
+
+        codec->hw_write = (hw_write_t) i2c_master_send;
+        codec->control_data = aic32x4->control_data;
+
+        snd_soc_write(codec, AIC32X4_RESET, 0x01);
+
+        /* Power platform configuration */
+        if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
+                snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
+                                                      AIC32X4_MICBIAS_2075V);
+        }
+        if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
+                snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
+        }
+        if (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) {
+                snd_soc_write(codec, AIC32X4_LDOCTL, AIC32X4_LDOCTLEN);
+        }
+        tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
+        if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
+                tmp_reg |= AIC32X4_LDOIN_18_36;
+        }
+        if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {
+                tmp_reg |= AIC32X4_LDOIN2HP;
+        }
+        snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
+
+        /* Do DACs need to be swapped? */
+        if (aic32x4->swapdacs) {
+                snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2RCHN | AIC32X4_RDAC2LCHN);
+        } else {
+                snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN);
+        }
+
+        /* Mic PGA routing */
+        if (aic32x4->micpga_routing | AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) {
+                snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
+        }
+        if (aic32x4->micpga_routing | AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) {
+                snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
+        }
+
+        aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        snd_soc_add_controls(codec, aic32x4_snd_controls,
+                             ARRAY_SIZE(aic32x4_snd_controls));
+        aic32x4_add_widgets(codec);
+
+        return 0;
+}
+
+static int aic32x4_remove(struct snd_soc_codec *codec)
+{
+        aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
+        .read = aic32x4_read,
+        .write = aic32x4_write,
+        .probe = aic32x4_probe,
+        .remove = aic32x4_remove,
+        .suspend = aic32x4_suspend,
+        .resume = aic32x4_resume,
+        .set_bias_level = aic32x4_set_bias_level,
+};
+
+static __devinit int aic32x4_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct aic32x4_pdata *pdata = i2c->dev.platform_data;
+        struct aic32x4_priv *aic32x4;
+        int ret;
+
+        aic32x4 = kzalloc(sizeof(struct aic32x4_priv), GFP_KERNEL);
+        if (aic32x4 == NULL)
+                return -ENOMEM;
+
+        aic32x4->control_data = i2c;
+        i2c_set_clientdata(i2c, aic32x4);
+
+        if (pdata) {
+                aic32x4->power_cfg = pdata->power_cfg;
+                aic32x4->swapdacs = pdata->swapdacs;
+                aic32x4->micpga_routing = pdata->micpga_routing;
+        } else {
+                aic32x4->power_cfg = 0;
+                aic32x4->swapdacs = false;
+                aic32x4->micpga_routing = 0;
+        }
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
+        if (ret < 0)
+                kfree(aic32x4);
+        return ret;
+}
+
+static __devexit int aic32x4_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id aic32x4_i2c_id[] = {
+        { "tlv320aic32x4", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
+
+static struct i2c_driver aic32x4_i2c_driver = {
+        .driver = {
+                .name = "tlv320aic32x4",
+                .owner = THIS_MODULE,
+        },
+        .probe =    aic32x4_i2c_probe,
+        .remove =   __devexit_p(aic32x4_i2c_remove),
+        .id_table = aic32x4_i2c_id,
+};
+
+static int __init aic32x4_modinit(void)
+{
+        int ret = 0;
+
+        ret = i2c_add_driver(&aic32x4_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register aic32x4 I2C driver: %d\n",
+                       ret);
+        }
+        return ret;
+}
+module_init(aic32x4_modinit);
+
+static void __exit aic32x4_exit(void)
+{
+        i2c_del_driver(&aic32x4_i2c_driver);
+}
+module_exit(aic32x4_exit);
+
+MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
+MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/tlv320aic32x4.h b/sound/soc/codecs/tlv320aic32x4.h
new file mode 100644
index 000000000000..aae2b2440398
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic32x4.h
@@ -0,0 +1,143 @@
+/*
+ * tlv320aic32x4.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#ifndef _TLV320AIC32X4_H
+#define _TLV320AIC32X4_H
+
+/* tlv320aic32x4 register space (in decimal to match datasheet) */
+
+#define AIC32X4_PAGE1           128
+
+#define AIC32X4_PSEL            0
+#define AIC32X4_RESET           1
+#define AIC32X4_CLKMUX          4
+#define AIC32X4_PLLPR           5
+#define AIC32X4_PLLJ            6
+#define AIC32X4_PLLDMSB         7
+#define AIC32X4_PLLDLSB         8
+#define AIC32X4_NDAC            11
+#define AIC32X4_MDAC            12
+#define AIC32X4_DOSRMSB         13
+#define AIC32X4_DOSRLSB         14
+#define AIC32X4_NADC            18
+#define AIC32X4_MADC            19
+#define AIC32X4_AOSR            20
+#define AIC32X4_CLKMUX2         25
+#define AIC32X4_CLKOUTM         26
+#define AIC32X4_IFACE1          27
+#define AIC32X4_IFACE2          28
+#define AIC32X4_IFACE3          29
+#define AIC32X4_BCLKN           30
+#define AIC32X4_IFACE4          31
+#define AIC32X4_IFACE5          32
+#define AIC32X4_IFACE6          33
+#define AIC32X4_DOUTCTL         53
+#define AIC32X4_DINCTL          54
+#define AIC32X4_DACSPB          60
+#define AIC32X4_ADCSPB          61
+#define AIC32X4_DACSETUP        63
+#define AIC32X4_DACMUTE         64
+#define AIC32X4_LDACVOL         65
+#define AIC32X4_RDACVOL         66
+#define AIC32X4_ADCSETUP        81
+#define AIC32X4_ADCFGA          82
+#define AIC32X4_LADCVOL         83
+#define AIC32X4_RADCVOL         84
+#define AIC32X4_LAGC1           86
+#define AIC32X4_LAGC2           87
+#define AIC32X4_LAGC3           88
+#define AIC32X4_LAGC4           89
+#define AIC32X4_LAGC5           90
+#define AIC32X4_LAGC6           91
+#define AIC32X4_LAGC7           92
+#define AIC32X4_RAGC1           94
+#define AIC32X4_RAGC2           95
+#define AIC32X4_RAGC3           96
+#define AIC32X4_RAGC4           97
+#define AIC32X4_RAGC5           98
+#define AIC32X4_RAGC6           99
+#define AIC32X4_RAGC7           100
+#define AIC32X4_PWRCFG          (AIC32X4_PAGE1 + 1)
+#define AIC32X4_LDOCTL          (AIC32X4_PAGE1 + 2)
+#define AIC32X4_OUTPWRCTL       (AIC32X4_PAGE1 + 9)
+#define AIC32X4_CMMODE          (AIC32X4_PAGE1 + 10)
+#define AIC32X4_HPLROUTE        (AIC32X4_PAGE1 + 12)
+#define AIC32X4_HPRROUTE        (AIC32X4_PAGE1 + 13)
+#define AIC32X4_LOLROUTE        (AIC32X4_PAGE1 + 14)
+#define AIC32X4_LORROUTE        (AIC32X4_PAGE1 + 15)
+#define AIC32X4_HPLGAIN         (AIC32X4_PAGE1 + 16)
+#define AIC32X4_HPRGAIN         (AIC32X4_PAGE1 + 17)
+#define AIC32X4_LOLGAIN         (AIC32X4_PAGE1 + 18)
+#define AIC32X4_LORGAIN         (AIC32X4_PAGE1 + 19)
+#define AIC32X4_HEADSTART       (AIC32X4_PAGE1 + 20)
+#define AIC32X4_MICBIAS         (AIC32X4_PAGE1 + 51)
+#define AIC32X4_LMICPGAPIN      (AIC32X4_PAGE1 + 52)
+#define AIC32X4_LMICPGANIN      (AIC32X4_PAGE1 + 54)
+#define AIC32X4_RMICPGAPIN      (AIC32X4_PAGE1 + 55)
+#define AIC32X4_RMICPGANIN      (AIC32X4_PAGE1 + 57)
+#define AIC32X4_FLOATINGINPUT   (AIC32X4_PAGE1 + 58)
+#define AIC32X4_LMICPGAVOL      (AIC32X4_PAGE1 + 59)
+#define AIC32X4_RMICPGAVOL      (AIC32X4_PAGE1 + 60)
+
+#define AIC32X4_FREQ_12000000 12000000
+#define AIC32X4_FREQ_24000000 24000000
+#define AIC32X4_FREQ_25000000 25000000
+
+#define AIC32X4_WORD_LEN_16BITS         0x00
+#define AIC32X4_WORD_LEN_20BITS         0x01
+#define AIC32X4_WORD_LEN_24BITS         0x02
+#define AIC32X4_WORD_LEN_32BITS         0x03
+
+#define AIC32X4_I2S_MODE                0x00
+#define AIC32X4_DSP_MODE                0x01
+#define AIC32X4_RIGHT_JUSTIFIED_MODE    0x02
+#define AIC32X4_LEFT_JUSTIFIED_MODE     0x03
+
+#define AIC32X4_AVDDWEAKDISABLE         0x08
+#define AIC32X4_LDOCTLEN                0x01
+
+#define AIC32X4_LDOIN_18_36             0x01
+#define AIC32X4_LDOIN2HP                0x02
+
+#define AIC32X4_DACSPBLOCK_MASK         0x1f
+#define AIC32X4_ADCSPBLOCK_MASK         0x1f
+
+#define AIC32X4_PLLJ_SHIFT              6
+#define AIC32X4_DOSRMSB_SHIFT           4
+
+#define AIC32X4_PLLCLKIN                0x03
+
+#define AIC32X4_MICBIAS_LDOIN           0x08
+#define AIC32X4_MICBIAS_2075V           0x60
+
+#define AIC32X4_LMICPGANIN_IN2R_10K     0x10
+#define AIC32X4_RMICPGANIN_IN1L_10K     0x10
+
+#define AIC32X4_LMICPGAVOL_NOGAIN       0x80
+#define AIC32X4_RMICPGAVOL_NOGAIN       0x80
+
+#define AIC32X4_BCLKMASTER              0x08
+#define AIC32X4_WCLKMASTER              0x04
+#define AIC32X4_PLLEN                   (0x01 << 7)
+#define AIC32X4_NDACEN                  (0x01 << 7)
+#define AIC32X4_MDACEN                  (0x01 << 7)
+#define AIC32X4_NADCEN                  (0x01 << 7)
+#define AIC32X4_MADCEN                  (0x01 << 7)
+#define AIC32X4_BCLKEN                  (0x01 << 7)
+#define AIC32X4_DACEN                   (0x03 << 6)
+#define AIC32X4_RDAC2LCHN               (0x02 << 2)
+#define AIC32X4_LDAC2RCHN               (0x02 << 4)
+#define AIC32X4_LDAC2LCHN               (0x01 << 4)
+#define AIC32X4_RDAC2RCHN               (0x01 << 2)
+
+#define AIC32X4_SSTEP2WCLK              0x01
+#define AIC32X4_MUTEON                  0x0C
+#define AIC32X4_DACMOD2BCLK             0x01
+
+#endif                          /* _TLV320AIC32X4_H */
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 71a69908ccf6..789453d44ec5 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -12,11 +12,11 @@
  *
  * Notes:
  *  The AIC3X is a driver for a low power stereo audio
- *  codecs aic31, aic32, aic33.
+ *  codecs aic31, aic32, aic33, aic3007.
  *
  *  It supports full aic33 codec functionality.
- *  The compatibility with aic32, aic31 is as follows:
- *        aic32        |        aic31
+ *  The compatibility with aic32, aic31 and aic3007 is as follows:
+ *    aic32/aic3007    |        aic31
  *  ---------------------------------------
  *   MONO_LOUT -> N/A  |  MONO_LOUT -> N/A
  *                     |  IN1L -> LINE1L
@@ -46,7 +46,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 #include <sound/tlv320aic3x.h>
@@ -61,13 +60,32 @@ static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
         "DRVDD",        /* ADC Analog and Output Driver Voltage */
 };
 
+static LIST_HEAD(reset_list);
+
+struct aic3x_priv;
+
+struct aic3x_disable_nb {
+        struct notifier_block nb;
+        struct aic3x_priv *aic3x;
+};
+
 /* codec private data */
 struct aic3x_priv {
-        struct snd_soc_codec codec;
+        struct snd_soc_codec *codec;
         struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
+        struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
+        enum snd_soc_control_type control_type;
+        struct aic3x_setup_data *setup;
+        void *control_data;
         unsigned int sysclk;
+        struct list_head list;
         int master;
         int gpio_reset;
+        int power;
+#define AIC3X_MODEL_3X 0
+#define AIC3X_MODEL_33 1
+#define AIC3X_MODEL_3007 2
+        u16 model;
 };
 
 /*
@@ -106,62 +124,23 @@ static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
 };
 
 /*
- * read aic3x register cache
+ * read from the aic3x register space. Only use for this function is if
+ * wanting to read volatile bits from those registers that has both read-only
+ * and read/write bits. All other cases should use snd_soc_read.
  */
-static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
-                                                unsigned int reg)
+static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
+                      u8 *value)
 {
         u8 *cache = codec->reg_cache;
-        if (reg >= AIC3X_CACHEREGNUM)
-                return -1;
-        return cache[reg];
-}
 
-/*
- * write aic3x register cache
- */
-static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
-                                         u8 reg, u8 value)
-{
-        u8 *cache = codec->reg_cache;
+        if (codec->cache_only)
+                return -EINVAL;
         if (reg >= AIC3X_CACHEREGNUM)
-                return;
-        cache[reg] = value;
-}
-
-/*
- * write to the aic3x register space
- */
-static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
-                       unsigned int value)
-{
-        u8 data[2];
-
-        /* data is
-         *   D15..D8 aic3x register offset
-         *   D7...D0 register data
-         */
-        data[0] = reg & 0xff;
-        data[1] = value & 0xff;
-
-        aic3x_write_reg_cache(codec, data[0], data[1]);
-        if (codec->hw_write(codec->control_data, data, 2) == 2)
-                return 0;
-        else
-                return -EIO;
-}
-
-/*
- * read from the aic3x register space
- */
-static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
-                      u8 *value)
-{
-        *value = reg & 0xff;
+                return -1;
 
-        value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
+        *value = codec->hw_read(codec, reg);
+        cache[reg] = *value;
 
-        aic3x_write_reg_cache(codec, reg, *value);
         return 0;
 }
 
@@ -178,7 +157,8 @@ static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
                                         struct snd_ctl_elem_value *ucontrol)
 {
-        struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget *widget = wlist->widgets[0];
         struct soc_mixer_control *mc =
                 (struct soc_mixer_control *)kcontrol->private_value;
         unsigned int reg = mc->reg;
@@ -206,7 +186,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
 
         if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
                 /* find dapm widget path assoc with kcontrol */
-                list_for_each_entry(path, &widget->codec->dapm_paths, list) {
+                list_for_each_entry(path, &widget->dapm->card->paths, list) {
                         if (path->kcontrol != kcontrol)
                                 continue;
 
@@ -222,7 +202,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
                 }
 
                 if (found)
-                        snd_soc_dapm_sync(widget->codec);
+                        snd_soc_dapm_sync(widget->dapm);
         }
 
         ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
@@ -286,64 +266,102 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = {
         SOC_DOUBLE_R_TLV("PCM Playback Volume",
                          LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
 
+        /*
+         * Output controls that map to output mixer switches. Note these are
+         * only for swapped L-to-R and R-to-L routes. See below stereo controls
+         * for direct L-to-L and R-to-R routes.
+         */
+        SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
+                       LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
+                       PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
+                       DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
+
+        SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
+                       LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
+                       PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
+                       DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
+
+        SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
+                       LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
+                       PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
+                       DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
+
+        SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
+                       LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
+                       PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
+                       DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
+
+        SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
+                       LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
+                       PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
+                       DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
+
+        SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
+                       LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
+                       PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
+        SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
+                       DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
+
+        /* Stereo output controls for direct L-to-L and R-to-R routes */
+        SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
+                         LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
+                         0, 118, 1, output_stage_tlv),
+        SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
+                         PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
+                         0, 118, 1, output_stage_tlv),
         SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
                          DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
                          0, 118, 1, output_stage_tlv),
-        SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
-        SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
-        SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
-                         DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
-                         0, 118, 1, output_stage_tlv),
-        SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
-                       PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
-        SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
-                       PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
-        SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
-                         LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
+
+        SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
+                         LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
                          0, 118, 1, output_stage_tlv),
-        SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
-                         LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
+        SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
+                         PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
                          0, 118, 1, output_stage_tlv),
-
         SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
                          DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
                          0, 118, 1, output_stage_tlv),
-        SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
-        SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
-                         PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
+
+        SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
+                         LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
                          0, 118, 1, output_stage_tlv),
-        SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
-                         LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
+        SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
+                         PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
                          0, 118, 1, output_stage_tlv),
-
         SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
                          DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
                          0, 118, 1, output_stage_tlv),
-        SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
-                     0x01, 0),
-        SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
-                         PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
+
+        SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
+                         LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
                          0, 118, 1, output_stage_tlv),
-        SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
-                       PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
-        SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
-                       PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
-        SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
-                         LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
+        SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
+                         PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
                          0, 118, 1, output_stage_tlv),
-
         SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
                          DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
                          0, 118, 1, output_stage_tlv),
-        SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
+
+        /* Output pin mute controls */
+        SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
+                     0x01, 0),
+        SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
+        SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
+                     0x01, 0),
+        SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
                      0x01, 0),
-        SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
-                       PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
-        SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
-                       PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
-        SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
-                         LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
-                         0, 118, 1, output_stage_tlv),
 
         /*
          * Note: enable Automatic input Gain Controller with care. It can
@@ -359,6 +377,14 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = {
         SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
 };
 
+/*
+ * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
+ */
+static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
+
+static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
+        SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
+
 /* Left DAC Mux */
 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
@@ -375,22 +401,74 @@ SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
 
-/* Left DAC_L1 Mixer */
-static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
-        SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
+/* Left Line Mixer */
+static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
 };
 
-/* Right DAC_R1 Mixer */
-static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
-        SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
+/* Right Line Mixer */
+static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
+};
+
+/* Mono Mixer */
+static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
+};
+
+/* Left HP Mixer */
+static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
+};
+
+/* Right HP Mixer */
+static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
+};
+
+/* Left HPCOM Mixer */
+static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
+};
+
+/* Right HPCOM Mixer */
+static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
+        SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
+        SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
 };
 
 /* Left PGA Mixer */
@@ -427,54 +505,11 @@ SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
 
-/* Left PGA Bypass Mixer */
-static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
-        SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
-};
-
-/* Right PGA Bypass Mixer */
-static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
-        SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
-};
-
-/* Left Line2 Bypass Mixer */
-static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
-        SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
-};
-
-/* Right Line2 Bypass Mixer */
-static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
-        SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
-        SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
-};
-
 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
         /* Left DAC to Left Outputs */
         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
         SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
                          &aic3x_left_dac_mux_controls),
-        SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
-                           &aic3x_left_dac_mixer_controls[0],
-                           ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
         SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
                          &aic3x_left_hpcom_mux_controls),
         SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
@@ -485,9 +520,6 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
         SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
                          &aic3x_right_dac_mux_controls),
-        SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
-                           &aic3x_right_dac_mixer_controls[0],
-                           ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
         SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
                          &aic3x_right_hpcom_mux_controls),
         SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
@@ -551,25 +583,28 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
         SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
                          MICBIAS_CTRL, 6, 3, 3, 0),
 
-        /* Left PGA to Left Output bypass */
-        SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
-                           &aic3x_left_pga_bp_mixer_controls[0],
-                           ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
-
-        /* Right PGA to Right Output bypass */
-        SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
-                           &aic3x_right_pga_bp_mixer_controls[0],
-                           ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
-
-        /* Left Line2 to Left Output bypass */
-        SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
-                           &aic3x_left_line2_bp_mixer_controls[0],
-                           ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
-
-        /* Right Line2 to Right Output bypass */
-        SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
-                           &aic3x_right_line2_bp_mixer_controls[0],
-                           ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
+        /* Output mixers */
+        SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
+                           &aic3x_left_line_mixer_controls[0],
+                           ARRAY_SIZE(aic3x_left_line_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
+                           &aic3x_right_line_mixer_controls[0],
+                           ARRAY_SIZE(aic3x_right_line_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
+                           &aic3x_mono_mixer_controls[0],
+                           ARRAY_SIZE(aic3x_mono_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
+                           &aic3x_left_hp_mixer_controls[0],
+                           ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
+                           &aic3x_right_hp_mixer_controls[0],
+                           ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
+                           &aic3x_left_hpcom_mixer_controls[0],
+                           ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
+        SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
+                           &aic3x_right_hpcom_mixer_controls[0],
+                           ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
 
         SND_SOC_DAPM_OUTPUT("LLOUT"),
         SND_SOC_DAPM_OUTPUT("RLOUT"),
@@ -585,69 +620,26 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
         SND_SOC_DAPM_INPUT("LINE1R"),
         SND_SOC_DAPM_INPUT("LINE2L"),
         SND_SOC_DAPM_INPUT("LINE2R"),
-};
 
-static const struct snd_soc_dapm_route intercon[] = {
-        /* Left Output */
-        {"Left DAC Mux", "DAC_L1", "Left DAC"},
-        {"Left DAC Mux", "DAC_L2", "Left DAC"},
-        {"Left DAC Mux", "DAC_L3", "Left DAC"},
-
-        {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
-        {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
-        {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
-        {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
-        {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
-        {"Left Line Out", NULL, "Left DAC Mux"},
-        {"Left HP Out", NULL, "Left DAC Mux"},
-
-        {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
-        {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
-        {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
-
-        {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
-        {"Mono Out", NULL, "Left DAC_L1 Mixer"},
-        {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
-        {"Left HP Com", NULL, "Left HPCOM Mux"},
-
-        {"LLOUT", NULL, "Left Line Out"},
-        {"LLOUT", NULL, "Left Line Out"},
-        {"HPLOUT", NULL, "Left HP Out"},
-        {"HPLCOM", NULL, "Left HP Com"},
-
-        /* Right Output */
-        {"Right DAC Mux", "DAC_R1", "Right DAC"},
-        {"Right DAC Mux", "DAC_R2", "Right DAC"},
-        {"Right DAC Mux", "DAC_R3", "Right DAC"},
-
-        {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
-        {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
-        {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
-        {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
-        {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
-        {"Right Line Out", NULL, "Right DAC Mux"},
-        {"Right HP Out", NULL, "Right DAC Mux"},
-
-        {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
-        {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
-        {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
-        {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
-        {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
+        /*
+         * Virtual output pin to detection block inside codec. This can be
+         * used to keep codec bias on if gpio or detection features are needed.
+         * Force pin on or construct a path with an input jack and mic bias
+         * widgets.
+         */
+        SND_SOC_DAPM_OUTPUT("Detection"),
+};
 
-        {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
-        {"Mono Out", NULL, "Right DAC_R1 Mixer"},
-        {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
-        {"Right HP Com", NULL, "Right HPCOM Mux"},
+static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
+        /* Class-D outputs */
+        SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
 
-        {"RLOUT", NULL, "Right Line Out"},
-        {"RLOUT", NULL, "Right Line Out"},
-        {"HPROUT", NULL, "Right HP Out"},
-        {"HPRCOM", NULL, "Right HP Com"},
-
-        /* Mono Output */
-        {"MONO_LOUT", NULL, "Mono Out"},
-        {"MONO_LOUT", NULL, "Mono Out"},
+        SND_SOC_DAPM_OUTPUT("SPOP"),
+        SND_SOC_DAPM_OUTPUT("SPOM"),
+};
 
+static const struct snd_soc_dapm_route intercon[] = {
         /* Left Input */
         {"Left Line1L Mux", "single-ended", "LINE1L"},
         {"Left Line1L Mux", "differential", "LINE1L"},
@@ -680,74 +672,6 @@ static const struct snd_soc_dapm_route intercon[] = {
         {"Right ADC", NULL, "Right PGA Mixer"},
         {"Right ADC", NULL, "GPIO1 dmic modclk"},
 
-        /* Left PGA Bypass */
-        {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
-        {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
-        {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
-        {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
-        {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
-        {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
-        {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
-
-        {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
-        {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
-        {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
-
-        {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
-        {"Mono Out", NULL, "Left PGA Bypass Mixer"},
-        {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
-
-        /* Right PGA Bypass */
-        {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
-        {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
-        {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
-        {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
-        {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
-        {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
-        {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
-
-        {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
-        {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
-        {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
-        {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
-        {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
-
-        {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
-        {"Mono Out", NULL, "Right PGA Bypass Mixer"},
-        {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
-
-        /* Left Line2 Bypass */
-        {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
-        {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
-        {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
-        {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
-        {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
-
-        {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
-        {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
-        {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
-
-        {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
-        {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
-        {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
-
-        /* Right Line2 Bypass */
-        {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
-        {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
-        {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
-        {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
-        {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
-
-        {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
-        {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
-        {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
-        {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
-        {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
-
-        {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
-        {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
-        {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
-
         /*
          * Logical path between digital mic enable and GPIO1 modulator clock
          * output function
@@ -755,15 +679,132 @@ static const struct snd_soc_dapm_route intercon[] = {
         {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
         {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
         {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
+
+        /* Left DAC Output */
+        {"Left DAC Mux", "DAC_L1", "Left DAC"},
+        {"Left DAC Mux", "DAC_L2", "Left DAC"},
+        {"Left DAC Mux", "DAC_L3", "Left DAC"},
+
+        /* Right DAC Output */
+        {"Right DAC Mux", "DAC_R1", "Right DAC"},
+        {"Right DAC Mux", "DAC_R2", "Right DAC"},
+        {"Right DAC Mux", "DAC_R3", "Right DAC"},
+
+        /* Left Line Output */
+        {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
+        {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
+        {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
+        {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
+        {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
+        {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
+
+        {"Left Line Out", NULL, "Left Line Mixer"},
+        {"Left Line Out", NULL, "Left DAC Mux"},
+        {"LLOUT", NULL, "Left Line Out"},
+
+        /* Right Line Output */
+        {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
+        {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
+        {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
+        {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
+        {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
+        {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
+
+        {"Right Line Out", NULL, "Right Line Mixer"},
+        {"Right Line Out", NULL, "Right DAC Mux"},
+        {"RLOUT", NULL, "Right Line Out"},
+
+        /* Mono Output */
+        {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
+        {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
+        {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
+        {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
+        {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
+        {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
+
+        {"Mono Out", NULL, "Mono Mixer"},
+        {"MONO_LOUT", NULL, "Mono Out"},
+
+        /* Left HP Output */
+        {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
+        {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
+        {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
+        {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
+        {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
+        {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
+
+        {"Left HP Out", NULL, "Left HP Mixer"},
+        {"Left HP Out", NULL, "Left DAC Mux"},
+        {"HPLOUT", NULL, "Left HP Out"},
+
+        /* Right HP Output */
+        {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
+        {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
+        {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
+        {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
+        {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
+        {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
+
+        {"Right HP Out", NULL, "Right HP Mixer"},
+        {"Right HP Out", NULL, "Right DAC Mux"},
+        {"HPROUT", NULL, "Right HP Out"},
+
+        /* Left HPCOM Output */
+        {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
+        {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
+        {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
+        {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
+        {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
+        {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
+
+        {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
+        {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
+        {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
+        {"Left HP Com", NULL, "Left HPCOM Mux"},
+        {"HPLCOM", NULL, "Left HP Com"},
+
+        /* Right HPCOM Output */
+        {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
+        {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
+        {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
+        {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
+        {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
+        {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
+
+        {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
+        {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
+        {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
+        {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
+        {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
+        {"Right HP Com", NULL, "Right HPCOM Mux"},
+        {"HPRCOM", NULL, "Right HP Com"},
+};
+
+static const struct snd_soc_dapm_route intercon_3007[] = {
+        /* Class-D outputs */
+        {"Left Class-D Out", NULL, "Left Line Out"},
+        {"Right Class-D Out", NULL, "Left Line Out"},
+        {"SPOP", NULL, "Left Class-D Out"},
+        {"SPOM", NULL, "Right Class-D Out"},
 };
 
 static int aic3x_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
+        struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+        snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
                                   ARRAY_SIZE(aic3x_dapm_widgets));
 
         /* set up audio path interconnects */
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
+
+        if (aic3x->model == AIC3X_MODEL_3007) {
+                snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
+                        ARRAY_SIZE(aic3007_dapm_widgets));
+                snd_soc_dapm_add_routes(dapm, intercon_3007,
+                                        ARRAY_SIZE(intercon_3007));
+        }
 
         return 0;
 }
@@ -773,8 +814,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
                            struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec =rtd->codec;
         struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
         int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
         u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
@@ -783,8 +823,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
         int clk;
 
         /* select data word length */
-        data =
-            aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
+        data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
         switch (params_format(params)) {
         case SNDRV_PCM_FORMAT_S16_LE:
                 break;
@@ -798,7 +837,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
                 data |= (0x03 << 4);
                 break;
         }
-        aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
+        snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
 
         /* Fsref can be 44100 or 48000 */
         fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
@@ -813,17 +852,17 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
 
         if (bypass_pll) {
                 pll_q &= 0xf;
-                aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
-                aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
+                snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
+                snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
                 /* disable PLL if it is bypassed */
-                reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
-                aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
+                reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
+                snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
 
         } else {
-                aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
+                snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
                 /* enable PLL when it is used */
-                reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
-                aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
+                reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
+                snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
         }
 
         /* Route Left DAC to left channel input and
@@ -832,7 +871,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
         data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
         if (params_rate(params) >= 64000)
                 data |= DUAL_RATE_MODE;
-        aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
+        snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
 
         /* codec sample rate select */
         data = (fsref * 20) / params_rate(params);
@@ -841,12 +880,12 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
         data /= 5;
         data -= 2;
         data |= (data << 4);
-        aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
+        snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
 
         if (bypass_pll)
                 return 0;
 
-        /* Use PLL, compute apropriate setup for j, d, r and p, the closest
+        /* Use PLL, compute appropriate setup for j, d, r and p, the closest
          * one wins the game. Try with d==0 first, next with d!=0.
          * Constraints for j are according to the datasheet.
          * The sysclk is divided by 1000 to prevent integer overflows.
@@ -910,13 +949,16 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
         }
 
 found:
-        data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
-        aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
-        aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
-        aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
-        aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
-        aic3x_write(codec, AIC3X_PLL_PROGD_REG,
-                    (pll_d & 0x3F) << PLLD_LSB_SHIFT);
+        data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
+        snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
+                      data | (pll_p << PLLP_SHIFT));
+        snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
+                      pll_r << PLLR_SHIFT);
+        snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
+        snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
+                      (pll_d >> 6) << PLLD_MSB_SHIFT);
+        snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
+                      (pll_d & 0x3F) << PLLD_LSB_SHIFT);
 
         return 0;
 }
@@ -924,15 +966,15 @@ found:
 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
 {
         struct snd_soc_codec *codec = dai->codec;
-        u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
-        u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
+        u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
+        u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
 
         if (mute) {
-                aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
-                aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
+                snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
+                snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
         } else {
-                aic3x_write(codec, LDAC_VOL, ldac_reg);
-                aic3x_write(codec, RDAC_VOL, rdac_reg);
+                snd_soc_write(codec, LDAC_VOL, ldac_reg);
+                snd_soc_write(codec, RDAC_VOL, rdac_reg);
         }
 
         return 0;
@@ -956,8 +998,8 @@ static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
         u8 iface_areg, iface_breg;
         int delay = 0;
 
-        iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
-        iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
+        iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
+        iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
 
         /* set master/slave audio interface */
         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -996,13 +1038,105 @@ static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
         }
 
         /* set iface */
-        aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
-        aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
-        aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
+        snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
+        snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
+        snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
+
+        return 0;
+}
+
+static int aic3x_init_3007(struct snd_soc_codec *codec)
+{
+        u8 tmp1, tmp2, *cache = codec->reg_cache;
+
+        /*
+         * There is no need to cache writes to undocumented page 0xD but
+         * respective page 0 register cache entries must be preserved
+         */
+        tmp1 = cache[0xD];
+        tmp2 = cache[0x8];
+        /* Class-D speaker driver init; datasheet p. 46 */
+        snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
+        snd_soc_write(codec, 0xD, 0x0D);
+        snd_soc_write(codec, 0x8, 0x5C);
+        snd_soc_write(codec, 0x8, 0x5D);
+        snd_soc_write(codec, 0x8, 0x5C);
+        snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
+        cache[0xD] = tmp1;
+        cache[0x8] = tmp2;
+
+        return 0;
+}
+
+static int aic3x_regulator_event(struct notifier_block *nb,
+                                 unsigned long event, void *data)
+{
+        struct aic3x_disable_nb *disable_nb =
+                container_of(nb, struct aic3x_disable_nb, nb);
+        struct aic3x_priv *aic3x = disable_nb->aic3x;
+
+        if (event & REGULATOR_EVENT_DISABLE) {
+                /*
+                 * Put codec to reset and require cache sync as at least one
+                 * of the supplies was disabled
+                 */
+                if (gpio_is_valid(aic3x->gpio_reset))
+                        gpio_set_value(aic3x->gpio_reset, 0);
+                aic3x->codec->cache_sync = 1;
+        }
 
         return 0;
 }
 
+static int aic3x_set_power(struct snd_soc_codec *codec, int power)
+{
+        struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
+        int i, ret;
+        u8 *cache = codec->reg_cache;
+
+        if (power) {
+                ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
+                                            aic3x->supplies);
+                if (ret)
+                        goto out;
+                aic3x->power = 1;
+                /*
+                 * Reset release and cache sync is necessary only if some
+                 * supply was off or if there were cached writes
+                 */
+                if (!codec->cache_sync)
+                        goto out;
+
+                if (gpio_is_valid(aic3x->gpio_reset)) {
+                        udelay(1);
+                        gpio_set_value(aic3x->gpio_reset, 1);
+                }
+
+                /* Sync reg_cache with the hardware */
+                codec->cache_only = 0;
+                for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
+                        snd_soc_write(codec, i, cache[i]);
+                if (aic3x->model == AIC3X_MODEL_3007)
+                        aic3x_init_3007(codec);
+                codec->cache_sync = 0;
+        } else {
+                /*
+                 * Do soft reset to this codec instance in order to clear
+                 * possible VDD leakage currents in case the supply regulators
+                 * remain on
+                 */
+                snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
+                codec->cache_sync = 1;
+                aic3x->power = 0;
+                /* HW writes are needless when bias is off */
+                codec->cache_only = 1;
+                ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
+                                             aic3x->supplies);
+        }
+out:
+        return ret;
+}
+
 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
                                 enum snd_soc_bias_level level)
 {
@@ -1013,25 +1147,31 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec,
         case SND_SOC_BIAS_ON:
                 break;
         case SND_SOC_BIAS_PREPARE:
-                if (aic3x->master) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
+                    aic3x->master) {
                         /* enable pll */
-                        reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
-                        aic3x_write(codec, AIC3X_PLL_PROGA_REG,
-                                    reg | PLL_ENABLE);
+                        reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
+                        snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
+                                      reg | PLL_ENABLE);
                 }
                 break;
         case SND_SOC_BIAS_STANDBY:
-                /* fall through and disable pll */
-        case SND_SOC_BIAS_OFF:
-                if (aic3x->master) {
+                if (!aic3x->power)
+                        aic3x_set_power(codec, 1);
+                if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
+                    aic3x->master) {
                         /* disable pll */
-                        reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
-                        aic3x_write(codec, AIC3X_PLL_PROGA_REG,
-                                    reg & ~PLL_ENABLE);
+                        reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
+                        snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
+                                      reg & ~PLL_ENABLE);
                 }
                 break;
+        case SND_SOC_BIAS_OFF:
+                if (aic3x->power)
+                        aic3x_set_power(codec, 0);
+                break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -1040,15 +1180,15 @@ void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
 {
         u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
         u8 bit = gpio ? 3: 0;
-        u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
-        aic3x_write(codec, reg, val | (!!state << bit));
+        u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
+        snd_soc_write(codec, reg, val | (!!state << bit));
 }
 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
 
 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
 {
         u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
-        u8 val, bit = gpio ? 2: 1;
+        u8 val = 0, bit = gpio ? 2 : 1;
 
         aic3x_read(codec, reg, &val);
         return (val >> bit) & 1;
@@ -1070,13 +1210,13 @@ void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
         if (detect & AIC3X_HEADSET_DETECT_MASK)
                 val |= AIC3X_HEADSET_DETECT_ENABLED;
 
-        aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
+        snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
 }
 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
 
 int aic3x_headset_detected(struct snd_soc_codec *codec)
 {
-        u8 val;
+        u8 val = 0;
         aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
         return (val >> 4) & 1;
 }
@@ -1084,7 +1224,7 @@ EXPORT_SYMBOL_GPL(aic3x_headset_detected);
 
 int aic3x_button_pressed(struct snd_soc_codec *codec)
 {
-        u8 val;
+        u8 val = 0;
         aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
         return (val >> 5) & 1;
 }
@@ -1101,8 +1241,8 @@ static struct snd_soc_dai_ops aic3x_dai_ops = {
         .set_fmt        = aic3x_set_dai_fmt,
 };
 
-struct snd_soc_dai aic3x_dai = {
-        .name = "tlv320aic3x",
+static struct snd_soc_dai_driver aic3x_dai = {
+        .name = "tlv320aic3x-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -1116,34 +1256,18 @@ struct snd_soc_dai aic3x_dai = {
                 .rates = AIC3X_RATES,
                 .formats = AIC3X_FORMATS,},
         .ops = &aic3x_dai_ops,
+        .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(aic3x_dai);
 
-static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
+static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int aic3x_resume(struct platform_device *pdev)
+static int aic3x_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int i;
-        u8 data[2];
-        u8 *cache = codec->reg_cache;
-
-        /* Sync reg_cache with the hardware */
-        for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
-                data[0] = i;
-                data[1] = cache[i];
-                codec->hw_write(codec->control_data, data, 2);
-        }
-
         aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
@@ -1155,152 +1279,221 @@ static int aic3x_resume(struct platform_device *pdev)
  */
 static int aic3x_init(struct snd_soc_codec *codec)
 {
+        struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
         int reg;
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "tlv320aic3x";
-        codec->owner = THIS_MODULE;
-        codec->read = aic3x_read_reg_cache;
-        codec->write = aic3x_write;
-        codec->set_bias_level = aic3x_set_bias_level;
-        codec->dai = &aic3x_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
-        codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
-        if (codec->reg_cache == NULL)
-                return -ENOMEM;
-
-        aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
-        aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
+        snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
+        snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
 
         /* DAC default volume and mute */
-        aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
-        aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
+        snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
+        snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
 
         /* DAC to HP default volume and route to Output mixer */
-        aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
-        aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
-        aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
-        aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
+        snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
+        snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
+        snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
+        snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
         /* DAC to Line Out default volume and route to Output mixer */
-        aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
-        aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
+        snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
+        snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
         /* DAC to Mono Line Out default volume and route to Output mixer */
-        aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
-        aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
+        snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
+        snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
 
         /* unmute all outputs */
-        reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
-        aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
-        reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
-        aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
-        reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
-        aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
-        reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
-        aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
-        reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
-        aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
-        reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
-        aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
-        reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
-        aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
+        reg = snd_soc_read(codec, LLOPM_CTRL);
+        snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
+        reg = snd_soc_read(codec, RLOPM_CTRL);
+        snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
+        reg = snd_soc_read(codec, MONOLOPM_CTRL);
+        snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
+        reg = snd_soc_read(codec, HPLOUT_CTRL);
+        snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
+        reg = snd_soc_read(codec, HPROUT_CTRL);
+        snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
+        reg = snd_soc_read(codec, HPLCOM_CTRL);
+        snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
+        reg = snd_soc_read(codec, HPRCOM_CTRL);
+        snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
 
         /* ADC default volume and unmute */
-        aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
-        aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
+        snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
+        snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
         /* By default route Line1 to ADC PGA mixer */
-        aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
-        aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
+        snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
+        snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
 
         /* PGA to HP Bypass default volume, disconnect from Output Mixer */
-        aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
-        aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
-        aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
-        aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
         /* PGA to Line Out default volume, disconnect from Output Mixer */
-        aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
-        aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
         /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
-        aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
-        aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
 
         /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
-        aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
-        aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
-        aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
-        aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
         /* Line2 Line Out default volume, disconnect from Output Mixer */
-        aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
-        aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
         /* Line2 to Mono Out default volume, disconnect from Output Mixer */
-        aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
-        aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
+        snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
 
-        /* off, with power on */
-        aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        if (aic3x->model == AIC3X_MODEL_3007) {
+                aic3x_init_3007(codec);
+                snd_soc_write(codec, CLASSD_CTRL, 0);
+        }
 
         return 0;
 }
 
-static struct snd_soc_codec *aic3x_codec;
+static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
+{
+        struct aic3x_priv *a;
+
+        list_for_each_entry(a, &reset_list, list) {
+                if (gpio_is_valid(aic3x->gpio_reset) &&
+                    aic3x->gpio_reset == a->gpio_reset)
+                        return true;
+        }
+
+        return false;
+}
 
-static int aic3x_register(struct snd_soc_codec *codec)
+static int aic3x_probe(struct snd_soc_codec *codec)
 {
-        int ret;
+        struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
+        int ret, i;
+
+        INIT_LIST_HEAD(&aic3x->list);
+        codec->control_data = aic3x->control_data;
+        aic3x->codec = codec;
+        codec->dapm.idle_bias_off = 1;
 
-        ret = aic3x_init(codec);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to initialise device\n");
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
                 return ret;
         }
 
-        aic3x_codec = codec;
+        if (gpio_is_valid(aic3x->gpio_reset) &&
+            !aic3x_is_shared_reset(aic3x)) {
+                ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
+                if (ret != 0)
+                        goto err_gpio;
+                gpio_direction_output(aic3x->gpio_reset, 0);
+        }
 
-        ret = snd_soc_register_codec(codec);
-        if (ret) {
-                dev_err(codec->dev, "Failed to register codec\n");
-                return ret;
+        for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
+                aic3x->supplies[i].supply = aic3x_supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
+                                 aic3x->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                goto err_get;
+        }
+        for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
+                aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
+                aic3x->disable_nb[i].aic3x = aic3x;
+                ret = regulator_register_notifier(aic3x->supplies[i].consumer,
+                                                  &aic3x->disable_nb[i].nb);
+                if (ret) {
+                        dev_err(codec->dev,
+                                "Failed to request regulator notifier: %d\n",
+                                 ret);
+                        goto err_notif;
+                }
         }
 
-        ret = snd_soc_register_dai(&aic3x_dai);
-        if (ret) {
-                dev_err(codec->dev, "Failed to register dai\n");
-                snd_soc_unregister_codec(codec);
-                return ret;
+        codec->cache_only = 1;
+        aic3x_init(codec);
+
+        if (aic3x->setup) {
+                /* setup GPIO functions */
+                snd_soc_write(codec, AIC3X_GPIO1_REG,
+                              (aic3x->setup->gpio_func[0] & 0xf) << 4);
+                snd_soc_write(codec, AIC3X_GPIO2_REG,
+                              (aic3x->setup->gpio_func[1] & 0xf) << 4);
         }
 
+        snd_soc_add_controls(codec, aic3x_snd_controls,
+                             ARRAY_SIZE(aic3x_snd_controls));
+        if (aic3x->model == AIC3X_MODEL_3007)
+                snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
+
+        aic3x_add_widgets(codec);
+        list_add(&aic3x->list, &reset_list);
+
         return 0;
+
+err_notif:
+        while (i--)
+                regulator_unregister_notifier(aic3x->supplies[i].consumer,
+                                              &aic3x->disable_nb[i].nb);
+        regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
+err_get:
+        if (gpio_is_valid(aic3x->gpio_reset) &&
+            !aic3x_is_shared_reset(aic3x))
+                gpio_free(aic3x->gpio_reset);
+err_gpio:
+        return ret;
 }
 
-static int aic3x_unregister(struct aic3x_priv *aic3x)
+static int aic3x_remove(struct snd_soc_codec *codec)
 {
-        aic3x_set_bias_level(&aic3x->codec, SND_SOC_BIAS_OFF);
-
-        snd_soc_unregister_dai(&aic3x_dai);
-        snd_soc_unregister_codec(&aic3x->codec);
+        struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
+        int i;
 
-        if (aic3x->gpio_reset >= 0) {
+        aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        list_del(&aic3x->list);
+        if (gpio_is_valid(aic3x->gpio_reset) &&
+            !aic3x_is_shared_reset(aic3x)) {
                 gpio_set_value(aic3x->gpio_reset, 0);
                 gpio_free(aic3x->gpio_reset);
         }
-        regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
+        for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
+                regulator_unregister_notifier(aic3x->supplies[i].consumer,
+                                              &aic3x->disable_nb[i].nb);
         regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
 
-        kfree(aic3x);
-        aic3x_codec = NULL;
-
         return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
+        .set_bias_level = aic3x_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(aic3x_reg),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = aic3x_reg,
+        .probe = aic3x_probe,
+        .remove = aic3x_remove,
+        .suspend = aic3x_suspend,
+        .resume = aic3x_resume,
+};
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 /*
  * AIC3X 2 wire address can be up to 4 devices with device addresses
  * 0x18, 0x19, 0x1A, 0x1B
  */
 
+static const struct i2c_device_id aic3x_i2c_id[] = {
+        [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
+        [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
+        [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
+
 /*
  * If the i2c layer weren't so broken, we could pass this kind of data
  * around
@@ -1308,10 +1501,10 @@ static int aic3x_unregister(struct aic3x_priv *aic3x)
 static int aic3x_i2c_probe(struct i2c_client *i2c,
                            const struct i2c_device_id *id)
 {
-        struct snd_soc_codec *codec;
-        struct aic3x_priv *aic3x;
         struct aic3x_pdata *pdata = i2c->dev.platform_data;
-        int ret, i;
+        struct aic3x_priv *aic3x;
+        int ret;
+        const struct i2c_device_id *tbl;
 
         aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
         if (aic3x == NULL) {
@@ -1319,180 +1512,68 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
                 return -ENOMEM;
         }
 
-        codec = &aic3x->codec;
-        codec->dev = &i2c->dev;
-        snd_soc_codec_set_drvdata(codec, aic3x);
-        codec->control_data = i2c;
-        codec->hw_write = (hw_write_t) i2c_master_send;
+        aic3x->control_data = i2c;
+        aic3x->control_type = SND_SOC_I2C;
 
         i2c_set_clientdata(i2c, aic3x);
-
-        aic3x->gpio_reset = -1;
-        if (pdata && pdata->gpio_reset >= 0) {
-                ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset");
-                if (ret != 0)
-                        goto err_gpio;
+        if (pdata) {
                 aic3x->gpio_reset = pdata->gpio_reset;
-                gpio_direction_output(aic3x->gpio_reset, 0);
-        }
-
-        for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
-                aic3x->supplies[i].supply = aic3x_supply_names[i];
-
-        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
-                                 aic3x->supplies);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
-                goto err_get;
-        }
-
-        ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
-                                    aic3x->supplies);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
-                goto err_enable;
+                aic3x->setup = pdata->setup;
+        } else {
+                aic3x->gpio_reset = -1;
         }
 
-        if (aic3x->gpio_reset >= 0) {
-                udelay(1);
-                gpio_set_value(aic3x->gpio_reset, 1);
+        for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
+                if (!strcmp(tbl->name, id->name))
+                        break;
         }
+        aic3x->model = tbl - aic3x_i2c_id;
 
-        return aic3x_register(codec);
-
-err_enable:
-        regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
-err_get:
-        if (aic3x->gpio_reset >= 0)
-                gpio_free(aic3x->gpio_reset);
-err_gpio:
-        kfree(aic3x);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_aic3x, &aic3x_dai, 1);
+        if (ret < 0)
+                kfree(aic3x);
         return ret;
 }
 
 static int aic3x_i2c_remove(struct i2c_client *client)
 {
-        struct aic3x_priv *aic3x = i2c_get_clientdata(client);
-
-        return aic3x_unregister(aic3x);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
 }
 
-static const struct i2c_device_id aic3x_i2c_id[] = {
-        { "tlv320aic3x", 0 },
-        { "tlv320aic33", 0 },
-        { }
-};
-MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
-
 /* machine i2c codec control layer */
 static struct i2c_driver aic3x_i2c_driver = {
         .driver = {
-                .name = "aic3x I2C Codec",
+                .name = "tlv320aic3x-codec",
                 .owner = THIS_MODULE,
         },
         .probe  = aic3x_i2c_probe,
         .remove = aic3x_i2c_remove,
         .id_table = aic3x_i2c_id,
 };
-
-static inline void aic3x_i2c_init(void)
-{
-        int ret;
-
-        ret = i2c_add_driver(&aic3x_i2c_driver);
-        if (ret)
-                printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
-                       __func__, ret);
-}
-
-static inline void aic3x_i2c_exit(void)
-{
-        i2c_del_driver(&aic3x_i2c_driver);
-}
-#else
-static inline void aic3x_i2c_init(void) { }
-static inline void aic3x_i2c_exit(void) { }
 #endif
 
-static int aic3x_probe(struct platform_device *pdev)
+static int __init aic3x_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct aic3x_setup_data *setup;
-        struct snd_soc_codec *codec;
         int ret = 0;
-
-        codec = aic3x_codec;
-        if (!codec) {
-                dev_err(&pdev->dev, "Codec not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = codec;
-        setup = socdev->codec_data;
-
-        if (setup) {
-                /* setup GPIO functions */
-                aic3x_write(codec, AIC3X_GPIO1_REG,
-                            (setup->gpio_func[0] & 0xf) << 4);
-                aic3x_write(codec, AIC3X_GPIO2_REG,
-                            (setup->gpio_func[1] & 0xf) << 4);
-        }
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "aic3x: failed to create pcms\n");
-                goto pcm_err;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&aic3x_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
+                       ret);
         }
-
-        snd_soc_add_controls(codec, aic3x_snd_controls,
-                             ARRAY_SIZE(aic3x_snd_controls));
-
-        aic3x_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        kfree(codec->reg_cache);
+#endif
         return ret;
 }
-
-static int aic3x_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        /* power down chip */
-        if (codec->control_data)
-                aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        kfree(codec->reg_cache);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_aic3x = {
-        .probe = aic3x_probe,
-        .remove = aic3x_remove,
-        .suspend = aic3x_suspend,
-        .resume = aic3x_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
-
-static int __init aic3x_modinit(void)
-{
-        aic3x_i2c_init();
-
-        return 0;
-}
 module_init(aic3x_modinit);
 
 static void __exit aic3x_exit(void)
 {
-        aic3x_i2c_exit();
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&aic3x_i2c_driver);
+#endif
 }
 module_exit(aic3x_exit);
 
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 9af1c886213c..06a19784b162 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -81,50 +81,63 @@
 /* DAC Digital control registers */
 #define LDAC_VOL                        43
 #define RDAC_VOL                        44
-/* High Power Output control registers */
+/* Left High Power Output control registers */
 #define LINE2L_2_HPLOUT_VOL             45
-#define LINE2R_2_HPROUT_VOL             62
 #define PGAL_2_HPLOUT_VOL               46
-#define PGAL_2_HPROUT_VOL               60
-#define PGAR_2_HPLOUT_VOL               49
-#define PGAR_2_HPROUT_VOL               63
 #define DACL1_2_HPLOUT_VOL              47
-#define DACR1_2_HPROUT_VOL              64
+#define LINE2R_2_HPLOUT_VOL             48
+#define PGAR_2_HPLOUT_VOL               49
+#define DACR1_2_HPLOUT_VOL              50
 #define HPLOUT_CTRL                     51
-#define HPROUT_CTRL                     65
-/* High Power COM control registers */
+/* Left High Power COM control registers */
 #define LINE2L_2_HPLCOM_VOL             52
-#define LINE2R_2_HPRCOM_VOL             69
 #define PGAL_2_HPLCOM_VOL               53
+#define DACL1_2_HPLCOM_VOL              54
+#define LINE2R_2_HPLCOM_VOL             55
 #define PGAR_2_HPLCOM_VOL               56
+#define DACR1_2_HPLCOM_VOL              57
+#define HPLCOM_CTRL                     58
+/* Right High Power Output control registers */
+#define LINE2L_2_HPROUT_VOL             59
+#define PGAL_2_HPROUT_VOL               60
+#define DACL1_2_HPROUT_VOL              61
+#define LINE2R_2_HPROUT_VOL             62
+#define PGAR_2_HPROUT_VOL               63
+#define DACR1_2_HPROUT_VOL              64
+#define HPROUT_CTRL                     65
+/* Right High Power COM control registers */
+#define LINE2L_2_HPRCOM_VOL             66
 #define PGAL_2_HPRCOM_VOL               67
+#define DACL1_2_HPRCOM_VOL              68
+#define LINE2R_2_HPRCOM_VOL             69
 #define PGAR_2_HPRCOM_VOL               70
-#define DACL1_2_HPLCOM_VOL              54
 #define DACR1_2_HPRCOM_VOL              71
-#define HPLCOM_CTRL                     58
 #define HPRCOM_CTRL                     72
 /* Mono Line Output Plus/Minus control registers */
 #define LINE2L_2_MONOLOPM_VOL           73
-#define LINE2R_2_MONOLOPM_VOL           76
 #define PGAL_2_MONOLOPM_VOL             74
-#define PGAR_2_MONOLOPM_VOL             77
 #define DACL1_2_MONOLOPM_VOL            75
+#define LINE2R_2_MONOLOPM_VOL           76
+#define PGAR_2_MONOLOPM_VOL             77
 #define DACR1_2_MONOLOPM_VOL            78
 #define MONOLOPM_CTRL                   79
-/* Line Output Plus/Minus control registers */
+/* Class-D speaker driver on tlv320aic3007 */
+#define CLASSD_CTRL                     73
+/* Left Line Output Plus/Minus control registers */
 #define LINE2L_2_LLOPM_VOL              80
-#define LINE2L_2_RLOPM_VOL              87
-#define LINE2R_2_LLOPM_VOL              83
-#define LINE2R_2_RLOPM_VOL              90
 #define PGAL_2_LLOPM_VOL                81
-#define PGAL_2_RLOPM_VOL                88
-#define PGAR_2_LLOPM_VOL                84
-#define PGAR_2_RLOPM_VOL                91
 #define DACL1_2_LLOPM_VOL               82
-#define DACL1_2_RLOPM_VOL               89
-#define DACR1_2_RLOPM_VOL               92
+#define LINE2R_2_LLOPM_VOL              83
+#define PGAR_2_LLOPM_VOL                84
 #define DACR1_2_LLOPM_VOL               85
 #define LLOPM_CTRL                      86
+/* Right Line Output Plus/Minus control registers */
+#define LINE2L_2_RLOPM_VOL              87
+#define PGAL_2_RLOPM_VOL                88
+#define DACL1_2_RLOPM_VOL               89
+#define LINE2R_2_RLOPM_VOL              90
+#define PGAR_2_RLOPM_VOL                91
+#define DACR1_2_RLOPM_VOL               92
 #define RLOPM_CTRL                      93
 /* GPIO/IRQ registers */
 #define AIC3X_STICKY_IRQ_FLAGS_REG      96
@@ -199,42 +212,6 @@
 /* Default input volume */
 #define DEFAULT_GAIN    0x20
 
-/* GPIO API */
-enum {
-        AIC3X_GPIO1_FUNC_DISABLED               = 0,
-        AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC      = 1,
-        AIC3X_GPIO1_FUNC_CLOCK_MUX              = 2,
-        AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2         = 3,
-        AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4         = 4,
-        AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8         = 5,
-        AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ      = 6,
-        AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ          = 7,
-        AIC3X_GPIO1_FUNC_INPUT                  = 8,
-        AIC3X_GPIO1_FUNC_OUTPUT                 = 9,
-        AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK     = 10,
-        AIC3X_GPIO1_FUNC_AUDIO_WORDCLK          = 11,
-        AIC3X_GPIO1_FUNC_BUTTON_IRQ             = 12,
-        AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ     = 13,
-        AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ   = 14,
-        AIC3X_GPIO1_FUNC_ALL_IRQ                = 16
-};
-
-enum {
-        AIC3X_GPIO2_FUNC_DISABLED               = 0,
-        AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ     = 2,
-        AIC3X_GPIO2_FUNC_INPUT                  = 3,
-        AIC3X_GPIO2_FUNC_OUTPUT                 = 4,
-        AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT      = 5,
-        AIC3X_GPIO2_FUNC_AUDIO_BITCLK           = 8,
-        AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
-        AIC3X_GPIO2_FUNC_ALL_IRQ                = 10,
-        AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
-        AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
-        AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ      = 13,
-        AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ          = 14,
-        AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ       = 15
-};
-
 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
 
@@ -281,11 +258,4 @@ void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
 int aic3x_headset_detected(struct snd_soc_codec *codec);
 int aic3x_button_pressed(struct snd_soc_codec *codec);
 
-struct aic3x_setup_data {
-        unsigned int gpio_func[2];
-};
-
-extern struct snd_soc_dai aic3x_dai;
-extern struct snd_soc_codec_device soc_codec_dev_aic3x;
-
 #endif /* _AIC3X_H */
diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index 8651b01ed223..faa5e9fb1471 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -1,7 +1,7 @@
 /*
  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
  *
- * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  *
  * Copyright:   (C) 2009 Nokia Corporation
  *
@@ -36,21 +36,21 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
 #include <sound/tlv320dac33-plat.h>
 #include "tlv320dac33.h"
 
-#define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
-                                                 * 6144 stereo */
-#define DAC33_BUFFER_SIZE_SAMPLES       6144
-
-#define NSAMPLE_MAX             5700
-
-#define MODE7_LTHR              10
-#define MODE7_UTHR              (DAC33_BUFFER_SIZE_SAMPLES - 10)
+/*
+ * The internal FIFO is 24576 bytes long
+ * It can be configured to hold 16bit or 24bit samples
+ * In 16bit configuration the FIFO can hold 6144 stereo samples
+ * In 24bit configuration the FIFO can hold 4096 stereo samples
+ */
+#define DAC33_FIFO_SIZE_16BIT   6144
+#define DAC33_FIFO_SIZE_24BIT   4096
+#define DAC33_MODE7_MARGIN      10      /* Safety margin for FIFO in Mode7 */
 
 #define BURST_BASEFREQ_HZ       49152000
 
@@ -58,7 +58,7 @@
         (1000000000 / ((rate * 1000) / samples))
 
 #define US_TO_SAMPLES(rate, us) \
-        (rate / (1000000 / us))
+        (rate / (1000000 / (us < 1000000 ? us : 1000000)))
 
 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
         ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
@@ -66,8 +66,6 @@
 static void dac33_calculate_times(struct snd_pcm_substream *substream);
 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
 
-static struct snd_soc_codec *tlv320dac33_codec;
-
 enum dac33_state {
         DAC33_IDLE = 0,
         DAC33_PREFILL,
@@ -93,7 +91,7 @@ struct tlv320dac33_priv {
         struct mutex mutex;
         struct workqueue_struct *dac33_wq;
         struct work_struct work;
-        struct snd_soc_codec codec;
+        struct snd_soc_codec *codec;
         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
         struct snd_pcm_substream *substream;
         int power_gpio;
@@ -102,16 +100,11 @@ struct tlv320dac33_priv {
         unsigned int refclk;
 
         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
-        unsigned int nsample_min;       /* nsample should not be lower than
-                                         * this */
-        unsigned int nsample_max;       /* nsample should not be higher than
-                                         * this */
         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
+        unsigned int fifo_size;         /* Size of the FIFO in samples */
         unsigned int nsample;           /* burst read amount from host */
         int mode1_latency;              /* latency caused by the i2c writes in
                                          * us */
-        int auto_fifo_config;           /* Configure the FIFO based on the
-                                         * period size */
         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
         unsigned int burst_rate;        /* Interface speed in Burst modes */
 
@@ -128,6 +121,8 @@ struct tlv320dac33_priv {
         unsigned int uthr;
 
         enum dac33_state state;
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
@@ -200,7 +195,7 @@ static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
                       u8 *value)
 {
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
-        int val;
+        int val, ret = 0;
 
         *value = reg & 0xff;
 
@@ -210,6 +205,7 @@ static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
                 if (val < 0) {
                         dev_err(codec->dev, "Read failed (%d)\n", val);
                         value[0] = dac33_read_reg_cache(codec, reg);
+                        ret = val;
                 } else {
                         value[0] = val;
                         dac33_write_reg_cache(codec, reg, val);
@@ -218,7 +214,7 @@ static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
                 value[0] = dac33_read_reg_cache(codec, reg);
         }
 
-        return 0;
+        return ret;
 }
 
 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
@@ -302,7 +298,6 @@ static void dac33_init_chip(struct snd_soc_codec *codec)
         if (unlikely(!dac33->chip_power))
                 return;
 
-        /* 44-46: DAC Control Registers */
         /* A : DAC sample rate Fsref/1.5 */
         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
         /* B : DAC src=normal, not muted */
@@ -315,8 +310,6 @@ static void dac33_init_chip(struct snd_soc_codec *codec)
          clock source = internal osc (?) */
         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 
-        dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
-
         /* Restore only selected registers (gains mostly) */
         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
@@ -327,15 +320,28 @@ static void dac33_init_chip(struct snd_soc_codec *codec)
                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
+
+        dac33_write(codec, DAC33_OUT_AMP_CTRL,
+                    dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
+
+        dac33_write(codec, DAC33_LDAC_PWR_CTRL,
+                    dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL));
+        dac33_write(codec, DAC33_RDAC_PWR_CTRL,
+                    dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL));
 }
 
-static inline void dac33_read_id(struct snd_soc_codec *codec)
+static inline int dac33_read_id(struct snd_soc_codec *codec)
 {
+        int i, ret = 0;
         u8 reg;
 
-        dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
-        dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
-        dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
+        for (i = 0; i < 3; i++) {
+                ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
+                if (ret < 0)
+                        break;
+        }
+
+        return ret;
 }
 
 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
@@ -351,6 +357,21 @@ static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
         dac33_write(codec, DAC33_PWR_CTRL, reg);
 }
 
+static inline void dac33_disable_digital(struct snd_soc_codec *codec)
+{
+        u8 reg;
+
+        /* Stop the DAI clock */
+        reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
+        reg &= ~DAC33_BCLKON;
+        dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
+
+        /* Power down the Oscillator, and DACs */
+        reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
+        reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
+        dac33_write(codec, DAC33_PWR_CTRL, reg);
+}
+
 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 {
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
@@ -399,7 +420,7 @@ exit:
         return ret;
 }
 
-static int playback_event(struct snd_soc_dapm_widget *w,
+static int dac33_playback_event(struct snd_soc_dapm_widget *w,
                 struct snd_kcontrol *kcontrol, int event)
 {
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
@@ -411,77 +432,13 @@ static int playback_event(struct snd_soc_dapm_widget *w,
                         dac33_prepare_chip(dac33->substream);
                 }
                 break;
+        case SND_SOC_DAPM_POST_PMD:
+                dac33_disable_digital(w->codec);
+                break;
         }
         return 0;
 }
 
-static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
-                         struct snd_ctl_elem_value *ucontrol)
-{
-        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-        struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
-
-        ucontrol->value.integer.value[0] = dac33->nsample;
-
-        return 0;
-}
-
-static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
-                         struct snd_ctl_elem_value *ucontrol)
-{
-        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-        struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
-        int ret = 0;
-
-        if (dac33->nsample == ucontrol->value.integer.value[0])
-                return 0;
-
-        if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
-            ucontrol->value.integer.value[0] > dac33->nsample_max) {
-                ret = -EINVAL;
-        } else {
-                dac33->nsample = ucontrol->value.integer.value[0];
-                /* Re calculate the burst time */
-                dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
-                                                      dac33->nsample);
-        }
-
-        return ret;
-}
-
-static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
-                         struct snd_ctl_elem_value *ucontrol)
-{
-        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-        struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
-
-        ucontrol->value.integer.value[0] = dac33->uthr;
-
-        return 0;
-}
-
-static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
-                         struct snd_ctl_elem_value *ucontrol)
-{
-        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-        struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
-        int ret = 0;
-
-        if (dac33->substream)
-                return -EBUSY;
-
-        if (dac33->uthr == ucontrol->value.integer.value[0])
-                return 0;
-
-        if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
-            ucontrol->value.integer.value[0] > MODE7_UTHR)
-                ret = -EINVAL;
-        else
-                dac33->uthr = ucontrol->value.integer.value[0];
-
-        return ret;
-}
-
 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
                          struct snd_ctl_elem_value *ucontrol)
 {
@@ -524,6 +481,22 @@ static const struct soc_enum dac33_fifo_mode_enum =
         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
                             dac33_fifo_mode_texts);
 
+/* L/R Line Output Gain */
+static const char *lr_lineout_gain_texts[] = {
+        "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
+        "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
+};
+
+static const struct soc_enum l_lineout_gain_enum =
+        SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
+                        ARRAY_SIZE(lr_lineout_gain_texts),
+                        lr_lineout_gain_texts);
+
+static const struct soc_enum r_lineout_gain_enum =
+        SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
+                        ARRAY_SIZE(lr_lineout_gain_texts),
+                        lr_lineout_gain_texts);
+
 /*
  * DACL/R digital volume control:
  * from 0 dB to -63.5 in 0.5 dB steps
@@ -541,6 +514,8 @@ static const struct snd_kcontrol_new dac33_snd_controls[] = {
                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
         SOC_DOUBLE_R("Line to Line Out Volume",
                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
+        SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
+        SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
 };
 
 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
@@ -548,13 +523,6 @@ static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 };
 
-static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
-        SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
-                dac33_get_nsample, dac33_set_nsample),
-        SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
-                 dac33_get_uthr, dac33_set_uthr),
-};
-
 /* Analog bypass */
 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
@@ -562,6 +530,25 @@ static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 
+/* LOP L/R invert selection */
+static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
+
+static const struct soc_enum dac33_left_lom_enum =
+        SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3,
+                        ARRAY_SIZE(dac33_lr_lom_texts),
+                        dac33_lr_lom_texts);
+
+static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
+SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
+
+static const struct soc_enum dac33_right_lom_enum =
+        SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2,
+                        ARRAY_SIZE(dac33_lr_lom_texts),
+                        dac33_lr_lom_texts);
+
+static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
+SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
+
 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
@@ -569,8 +556,8 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
         SND_SOC_DAPM_INPUT("LINEL"),
         SND_SOC_DAPM_INPUT("LINER"),
 
-        SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
-        SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
+        SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
 
         /* Analog bypass */
         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
@@ -578,12 +565,33 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
                                 &dac33_dapm_abypassr_control),
 
-        SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
+        SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
+                &dac33_dapm_left_lom_control),
+        SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
+                &dac33_dapm_right_lom_control),
+        /*
+         * For DAPM path, when only the anlog bypass path is enabled, and the
+         * LOP inverted from the corresponding DAC side.
+         * This is needed, so we can attach the DAC power supply in this case.
+         */
+        SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
-        SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
+        SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 
-        SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
+        SND_SOC_DAPM_SUPPLY("Left DAC Power",
+                            DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("Right DAC Power",
+                            DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
+
+        SND_SOC_DAPM_SUPPLY("Codec Power",
+                            DAC33_PWR_CTRL, 4, 0, NULL, 0),
+
+        SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
+        SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
 };
 
 static const struct snd_soc_dapm_route audio_map[] = {
@@ -591,24 +599,42 @@ static const struct snd_soc_dapm_route audio_map[] = {
         {"Analog Left Bypass", "Switch", "LINEL"},
         {"Analog Right Bypass", "Switch", "LINER"},
 
-        {"Output Left Amp Power", NULL, "DACL"},
-        {"Output Right Amp Power", NULL, "DACR"},
+        {"Output Left Amplifier", NULL, "DACL"},
+        {"Output Right Amplifier", NULL, "DACR"},
+
+        {"Left Bypass PGA", NULL, "Analog Left Bypass"},
+        {"Right Bypass PGA", NULL, "Analog Right Bypass"},
+
+        {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
+        {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
+        {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
+        {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
 
-        {"Output Left Amp Power", NULL, "Analog Left Bypass"},
-        {"Output Right Amp Power", NULL, "Analog Right Bypass"},
+        {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
+        {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
+
+        {"DACL", NULL, "Left DAC Power"},
+        {"DACR", NULL, "Right DAC Power"},
+
+        {"Left Bypass PGA", NULL, "Left DAC Power"},
+        {"Right Bypass PGA", NULL, "Right DAC Power"},
 
         /* output */
-        {"LEFT_LO", NULL, "Output Left Amp Power"},
-        {"RIGHT_LO", NULL, "Output Right Amp Power"},
+        {"LEFT_LO", NULL, "Output Left Amplifier"},
+        {"RIGHT_LO", NULL, "Output Right Amplifier"},
+
+        {"LEFT_LO", NULL, "Codec Power"},
+        {"RIGHT_LO", NULL, "Codec Power"},
 };
 
 static int dac33_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
-                                  ARRAY_SIZE(dac33_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
+        snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
+                                  ARRAY_SIZE(dac33_dapm_widgets));
         /* set up audio path interconnects */
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -620,12 +646,11 @@ static int dac33_set_bias_level(struct snd_soc_codec *codec,
 
         switch (level) {
         case SND_SOC_BIAS_ON:
-                dac33_soft_power(codec, 1);
                 break;
         case SND_SOC_BIAS_PREPARE:
                 break;
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Coming from OFF, switch on the codec */
                         ret = dac33_hard_power(codec, 1);
                         if (ret != 0)
@@ -636,23 +661,23 @@ static int dac33_set_bias_level(struct snd_soc_codec *codec,
                 break;
         case SND_SOC_BIAS_OFF:
                 /* Do not power off, when the codec is already off */
-                if (codec->bias_level == SND_SOC_BIAS_OFF)
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
                         return 0;
                 ret = dac33_hard_power(codec, 0);
                 if (ret != 0)
                         return ret;
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
 
 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 {
-        struct snd_soc_codec *codec;
-
-        codec = &dac33->codec;
+        struct snd_soc_codec *codec = dac33->codec;
+        unsigned int delay;
+        unsigned long flags;
 
         switch (dac33->fifo_mode) {
         case DAC33_FIFO_MODE1:
@@ -660,28 +685,29 @@ static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
                         DAC33_THRREG(dac33->nsample));
 
                 /* Take the timestamps */
-                spin_lock_irq(&dac33->lock);
+                spin_lock_irqsave(&dac33->lock, flags);
                 dac33->t_stamp2 = ktime_to_us(ktime_get());
                 dac33->t_stamp1 = dac33->t_stamp2;
-                spin_unlock_irq(&dac33->lock);
+                spin_unlock_irqrestore(&dac33->lock, flags);
 
                 dac33_write16(codec, DAC33_PREFILL_MSB,
                                 DAC33_THRREG(dac33->alarm_threshold));
                 /* Enable Alarm Threshold IRQ with a delay */
-                udelay(SAMPLES_TO_US(dac33->burst_rate,
-                                     dac33->alarm_threshold));
+                delay = SAMPLES_TO_US(dac33->burst_rate,
+                                     dac33->alarm_threshold) + 1000;
+                usleep_range(delay, delay + 500);
                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
                 break;
         case DAC33_FIFO_MODE7:
                 /* Take the timestamp */
-                spin_lock_irq(&dac33->lock);
+                spin_lock_irqsave(&dac33->lock, flags);
                 dac33->t_stamp1 = ktime_to_us(ktime_get());
                 /* Move back the timestamp with drain time */
                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
-                spin_unlock_irq(&dac33->lock);
+                spin_unlock_irqrestore(&dac33->lock, flags);
 
                 dac33_write16(codec, DAC33_PREFILL_MSB,
-                                DAC33_THRREG(MODE7_LTHR));
+                                DAC33_THRREG(DAC33_MODE7_MARGIN));
 
                 /* Enable Upper Threshold IRQ */
                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
@@ -695,16 +721,15 @@ static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 
 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 {
-        struct snd_soc_codec *codec;
-
-        codec = &dac33->codec;
+        struct snd_soc_codec *codec = dac33->codec;
+        unsigned long flags;
 
         switch (dac33->fifo_mode) {
         case DAC33_FIFO_MODE1:
                 /* Take the timestamp */
-                spin_lock_irq(&dac33->lock);
+                spin_lock_irqsave(&dac33->lock, flags);
                 dac33->t_stamp2 = ktime_to_us(ktime_get());
-                spin_unlock_irq(&dac33->lock);
+                spin_unlock_irqrestore(&dac33->lock, flags);
 
                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
                                 DAC33_THRREG(dac33->nsample));
@@ -726,7 +751,7 @@ static void dac33_work(struct work_struct *work)
         u8 reg;
 
         dac33 = container_of(work, struct tlv320dac33_priv, work);
-        codec = &dac33->codec;
+        codec = dac33->codec;
 
         mutex_lock(&dac33->mutex);
         switch (dac33->state) {
@@ -757,10 +782,11 @@ static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 {
         struct snd_soc_codec *codec = dev;
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
+        unsigned long flags;
 
-        spin_lock(&dac33->lock);
+        spin_lock_irqsave(&dac33->lock, flags);
         dac33->t_stamp1 = ktime_to_us(ktime_get());
-        spin_unlock(&dac33->lock);
+        spin_unlock_irqrestore(&dac33->lock, flags);
 
         /* Do not schedule the workqueue in Mode7 */
         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
@@ -771,11 +797,11 @@ static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 
 static void dac33_oscwait(struct snd_soc_codec *codec)
 {
-        int timeout = 20;
+        int timeout = 60;
         u8 reg;
 
         do {
-                msleep(1);
+                usleep_range(1000, 2000);
                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
@@ -787,13 +813,14 @@ static int dac33_startup(struct snd_pcm_substream *substream,
                            struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 
         /* Stream started, save the substream pointer */
         dac33->substream = substream;
 
+        snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
+
         return 0;
 }
 
@@ -801,24 +828,21 @@ static void dac33_shutdown(struct snd_pcm_substream *substream,
                              struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 
         dac33->substream = NULL;
-
-        /* Reset the nSample restrictions */
-        dac33->nsample_min = 0;
-        dac33->nsample_max = NSAMPLE_MAX;
 }
 
+#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
+        (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
 static int dac33_hw_params(struct snd_pcm_substream *substream,
                            struct snd_pcm_hw_params *params,
                            struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 
         /* Check parameters for validity */
         switch (params_rate(params)) {
@@ -833,6 +857,12 @@ static int dac33_hw_params(struct snd_pcm_substream *substream,
 
         switch (params_format(params)) {
         case SNDRV_PCM_FORMAT_S16_LE:
+                dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
+                dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
+                dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
                 break;
         default:
                 dev_err(codec->dev, "unsupported format %d\n",
@@ -856,8 +886,7 @@ static int dac33_hw_params(struct snd_pcm_substream *substream,
 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
         u8 aictrl_a, aictrl_b, fifoctrl_a;
@@ -888,6 +917,9 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
                 fifoctrl_a |= DAC33_WIDTH;
                 break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
+                break;
         default:
                 dev_err(codec->dev, "unsupported format %d\n",
                         substream->runtime->format);
@@ -914,8 +946,8 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
         /* Write registers 0x08 and 0x09 (MSB, LSB) */
         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 
-        /* calib time: 128 is a nice number ;) */
-        dac33_write(codec, DAC33_CALIB_TIME, 128);
+        /* OSC calibration time */
+        dac33_write(codec, DAC33_CALIB_TIME, 96);
 
         /* adjustment treshold & step */
         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
@@ -998,7 +1030,7 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
                 /*
                  * For FIFO bypass mode:
                  * Enable the FIFO bypass (Disable the FIFO use)
-                 * Set the BCLK as continous
+                 * Set the BCLK as continuous
                  */
                 fifoctrl_a |= DAC33_FBYPAS;
                 aictrl_b |= DAC33_BCLKON;
@@ -1022,7 +1054,10 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
                                                         dac33->burst_bclkdiv);
         else
-                dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
+                if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
+                        dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
+                else
+                        dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
 
         switch (dac33->fifo_mode) {
         case DAC33_FIFO_MODE1:
@@ -1035,7 +1070,8 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
                  * at the bottom, and also at the top of the FIFO
                  */
                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
-                dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
+                dac33_write16(codec, DAC33_LTHR_MSB,
+                              DAC33_THRREG(DAC33_MODE7_MARGIN));
                 break;
         default:
                 break;
@@ -1049,8 +1085,7 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 static void dac33_calculate_times(struct snd_pcm_substream *substream)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
         unsigned int period_size = substream->runtime->period_size;
         unsigned int rate = substream->runtime->rate;
@@ -1065,38 +1100,21 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream)
                 /* Number of samples under i2c latency */
                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
                                                 dac33->mode1_latency);
-                if (dac33->auto_fifo_config) {
-                        if (period_size <= dac33->alarm_threshold)
-                                /*
-                                 * Configure nSamaple to number of periods,
-                                 * which covers the latency requironment.
-                                 */
-                                dac33->nsample = period_size *
-                                       ((dac33->alarm_threshold / period_size) +
-                                       (dac33->alarm_threshold % period_size ?
-                                       1 : 0));
-                        else
-                                dac33->nsample = period_size;
-                } else {
-                        /* nSample time shall not be shorter than i2c latency */
-                        dac33->nsample_min = dac33->alarm_threshold;
+                nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
+
+                if (period_size <= dac33->alarm_threshold)
                         /*
-                         * nSample should not be bigger than alsa buffer minus
-                         * size of one period to avoid overruns
+                         * Configure nSamaple to number of periods,
+                         * which covers the latency requironment.
                          */
-                        dac33->nsample_max = substream->runtime->buffer_size -
-                                                period_size;
-                        nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
-                                        dac33->alarm_threshold;
-                        if (dac33->nsample_max > nsample_limit)
-                                dac33->nsample_max = nsample_limit;
-
-                        /* Correct the nSample if it is outside of the ranges */
-                        if (dac33->nsample < dac33->nsample_min)
-                                dac33->nsample = dac33->nsample_min;
-                        if (dac33->nsample > dac33->nsample_max)
-                                dac33->nsample = dac33->nsample_max;
-                }
+                        dac33->nsample = period_size *
+                                ((dac33->alarm_threshold / period_size) +
+                                (dac33->alarm_threshold % period_size ?
+                                1 : 0));
+                else if (period_size > nsample_limit)
+                        dac33->nsample = nsample_limit;
+                else
+                        dac33->nsample = period_size;
 
                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
                                                       dac33->nsample);
@@ -1104,19 +1122,16 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream)
                 dac33->t_stamp2 = 0;
                 break;
         case DAC33_FIFO_MODE7:
-                if (dac33->auto_fifo_config) {
-                        dac33->uthr = UTHR_FROM_PERIOD_SIZE(
-                                        period_size,
-                                        rate,
-                                        dac33->burst_rate) + 9;
-                        if (dac33->uthr > MODE7_UTHR)
-                                dac33->uthr = MODE7_UTHR;
-                        if (dac33->uthr < (MODE7_LTHR + 10))
-                                dac33->uthr = (MODE7_LTHR + 10);
-                }
+                dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
+                                                    dac33->burst_rate) + 9;
+                if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
+                        dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
+                if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
+                        dac33->uthr = (DAC33_MODE7_MARGIN + 10);
+
                 dac33->mode7_us_to_lthr =
                                 SAMPLES_TO_US(substream->runtime->rate,
-                                        dac33->uthr - MODE7_LTHR + 1);
+                                        dac33->uthr - DAC33_MODE7_MARGIN + 1);
                 dac33->t_stamp1 = 0;
                 break;
         default:
@@ -1129,8 +1144,7 @@ static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
                              struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
         int ret = 0;
 
@@ -1163,22 +1177,22 @@ static snd_pcm_sframes_t dac33_dai_delay(
                         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
         unsigned long long t0, t1, t_now;
         unsigned int time_delta, uthr;
         int samples_out, samples_in, samples;
         snd_pcm_sframes_t delay = 0;
+        unsigned long flags;
 
         switch (dac33->fifo_mode) {
         case DAC33_FIFO_BYPASS:
                 break;
         case DAC33_FIFO_MODE1:
-                spin_lock(&dac33->lock);
+                spin_lock_irqsave(&dac33->lock, flags);
                 t0 = dac33->t_stamp1;
                 t1 = dac33->t_stamp2;
-                spin_unlock(&dac33->lock);
+                spin_unlock_irqrestore(&dac33->lock, flags);
                 t_now = ktime_to_us(ktime_get());
 
                 /* We have not started to fill the FIFO yet, delay is 0 */
@@ -1236,17 +1250,17 @@ static snd_pcm_sframes_t dac33_dai_delay(
                         samples += (samples_in - samples_out);
 
                         if (likely(samples > 0))
-                                delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
-                                        DAC33_BUFFER_SIZE_SAMPLES : samples;
+                                delay = samples > dac33->fifo_size ?
+                                        dac33->fifo_size : samples;
                         else
                                 delay = 0;
                 }
                 break;
         case DAC33_FIFO_MODE7:
-                spin_lock(&dac33->lock);
+                spin_lock_irqsave(&dac33->lock, flags);
                 t0 = dac33->t_stamp1;
                 uthr = dac33->uthr;
-                spin_unlock(&dac33->lock);
+                spin_unlock_irqrestore(&dac33->lock, flags);
                 t_now = ktime_to_us(ktime_get());
 
                 /* We have not started to fill the FIFO yet, delay is 0 */
@@ -1289,7 +1303,7 @@ static snd_pcm_sframes_t dac33_dai_delay(
                         samples_in = US_TO_SAMPLES(
                                         dac33->burst_rate,
                                         time_delta);
-                        delay = MODE7_LTHR + samples_in - samples_out;
+                        delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
 
                         if (unlikely(delay > uthr))
                                 delay = uthr;
@@ -1389,91 +1403,110 @@ static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
         return 0;
 }
 
-static int dac33_soc_probe(struct platform_device *pdev)
+static int dac33_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        struct tlv320dac33_priv *dac33;
+        struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
         int ret = 0;
 
-        BUG_ON(!tlv320dac33_codec);
+        codec->control_data = dac33->control_data;
+        codec->hw_write = (hw_write_t) i2c_master_send;
+        codec->dapm.idle_bias_off = 1;
+        dac33->codec = codec;
 
-        codec = tlv320dac33_codec;
-        socdev->card->codec = codec;
-        dac33 = snd_soc_codec_get_drvdata(codec);
+        /* Read the tlv320dac33 ID registers */
+        ret = dac33_hard_power(codec, 1);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
+                goto err_power;
+        }
+        ret = dac33_read_id(codec);
+        dac33_hard_power(codec, 0);
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
         if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms\n");
-                goto pcm_err;
+                dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
+                ret = -ENODEV;
+                goto err_power;
+        }
+
+        /* Check if the IRQ number is valid and request it */
+        if (dac33->irq >= 0) {
+                ret = request_irq(dac33->irq, dac33_interrupt_handler,
+                                  IRQF_TRIGGER_RISING | IRQF_DISABLED,
+                                  codec->name, codec);
+                if (ret < 0) {
+                        dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
+                                                dac33->irq, ret);
+                        dac33->irq = -1;
+                }
+                if (dac33->irq != -1) {
+                        /* Setup work queue */
+                        dac33->dac33_wq =
+                                create_singlethread_workqueue("tlv320dac33");
+                        if (dac33->dac33_wq == NULL) {
+                                free_irq(dac33->irq, codec);
+                                return -ENOMEM;
+                        }
+
+                        INIT_WORK(&dac33->work, dac33_work);
+                }
         }
 
         snd_soc_add_controls(codec, dac33_snd_controls,
                              ARRAY_SIZE(dac33_snd_controls));
         /* Only add the FIFO controls, if we have valid IRQ number */
-        if (dac33->irq >= 0) {
+        if (dac33->irq >= 0)
                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
                                      ARRAY_SIZE(dac33_mode_snd_controls));
-                /* FIFO usage controls only, if autoio config is not selected */
-                if (!dac33->auto_fifo_config)
-                        snd_soc_add_controls(codec, dac33_fifo_snd_controls,
-                                        ARRAY_SIZE(dac33_fifo_snd_controls));
-        }
 
         dac33_add_widgets(codec);
 
-        return 0;
-
-pcm_err:
-        dac33_hard_power(codec, 0);
+err_power:
         return ret;
 }
 
-static int dac33_soc_remove(struct platform_device *pdev)
+static int dac33_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 
         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
+        if (dac33->irq >= 0) {
+                free_irq(dac33->irq, dac33->codec);
+                destroy_workqueue(dac33->dac33_wq);
+        }
         return 0;
 }
 
-static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
+static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int dac33_soc_resume(struct platform_device *pdev)
+static int dac33_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
+static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
+        .read = dac33_read_reg_cache,
+        .write = dac33_write_locked,
+        .set_bias_level = dac33_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(dac33_reg),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = dac33_reg,
         .probe = dac33_soc_probe,
         .remove = dac33_soc_remove,
         .suspend = dac33_soc_suspend,
         .resume = dac33_soc_resume,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
 
 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
                          SNDRV_PCM_RATE_48000)
-#define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
+#define DAC33_FORMATS   (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
 
 static struct snd_soc_dai_ops dac33_dai_ops = {
         .startup        = dac33_startup,
@@ -1485,8 +1518,8 @@ static struct snd_soc_dai_ops dac33_dai_ops = {
         .set_fmt        = dac33_set_dai_fmt,
 };
 
-struct snd_soc_dai dac33_dai = {
-        .name = "tlv320dac33",
+static struct snd_soc_dai_driver dac33_dai = {
+        .name = "tlv320dac33-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -1495,14 +1528,12 @@ struct snd_soc_dai dac33_dai = {
                 .formats = DAC33_FORMATS,},
         .ops = &dac33_dai_ops,
 };
-EXPORT_SYMBOL_GPL(dac33_dai);
 
 static int __devinit dac33_i2c_probe(struct i2c_client *client,
                                      const struct i2c_device_id *id)
 {
         struct tlv320dac33_platform_data *pdata;
         struct tlv320dac33_priv *dac33;
-        struct snd_soc_codec *codec;
         int ret, i;
 
         if (client->dev.platform_data == NULL) {
@@ -1515,171 +1546,75 @@ static int __devinit dac33_i2c_probe(struct i2c_client *client,
         if (dac33 == NULL)
                 return -ENOMEM;
 
-        codec = &dac33->codec;
-        snd_soc_codec_set_drvdata(codec, dac33);
-        codec->control_data = client;
-
-        mutex_init(&codec->mutex);
+        dac33->control_data = client;
         mutex_init(&dac33->mutex);
         spin_lock_init(&dac33->lock);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "tlv320dac33";
-        codec->owner = THIS_MODULE;
-        codec->read = dac33_read_reg_cache;
-        codec->write = dac33_write_locked;
-        codec->hw_write = (hw_write_t) i2c_master_send;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = dac33_set_bias_level;
-        codec->idle_bias_off = 1;
-        codec->dai = &dac33_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
-        codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
-                                   GFP_KERNEL);
-        if (codec->reg_cache == NULL) {
-                ret = -ENOMEM;
-                goto error_reg;
-        }
 
         i2c_set_clientdata(client, dac33);
 
         dac33->power_gpio = pdata->power_gpio;
         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
-        /* Pre calculate the burst rate */
-        dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
         dac33->keep_bclk = pdata->keep_bclk;
-        dac33->auto_fifo_config = pdata->auto_fifo_config;
         dac33->mode1_latency = pdata->mode1_latency;
         if (!dac33->mode1_latency)
                 dac33->mode1_latency = 10000; /* 10ms */
         dac33->irq = client->irq;
-        dac33->nsample = NSAMPLE_MAX;
-        dac33->nsample_max = NSAMPLE_MAX;
-        dac33->uthr = MODE7_UTHR;
         /* Disable FIFO use by default */
         dac33->fifo_mode = DAC33_FIFO_BYPASS;
 
-        tlv320dac33_codec = codec;
-
-        codec->dev = &client->dev;
-        dac33_dai.dev = codec->dev;
-
         /* Check if the reset GPIO number is valid and request it */
         if (dac33->power_gpio >= 0) {
                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
                 if (ret < 0) {
-                        dev_err(codec->dev,
+                        dev_err(&client->dev,
                                 "Failed to request reset GPIO (%d)\n",
                                 dac33->power_gpio);
-                        snd_soc_unregister_dai(&dac33_dai);
-                        snd_soc_unregister_codec(codec);
-                        goto error_gpio;
+                        goto err_gpio;
                 }
                 gpio_direction_output(dac33->power_gpio, 0);
         }
 
-        /* Check if the IRQ number is valid and request it */
-        if (dac33->irq >= 0) {
-                ret = request_irq(dac33->irq, dac33_interrupt_handler,
-                                  IRQF_TRIGGER_RISING | IRQF_DISABLED,
-                                  codec->name, codec);
-                if (ret < 0) {
-                        dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
-                                                dac33->irq, ret);
-                        dac33->irq = -1;
-                }
-                if (dac33->irq != -1) {
-                        /* Setup work queue */
-                        dac33->dac33_wq =
-                                create_singlethread_workqueue("tlv320dac33");
-                        if (dac33->dac33_wq == NULL) {
-                                free_irq(dac33->irq, &dac33->codec);
-                                ret = -ENOMEM;
-                                goto error_wq;
-                        }
-
-                        INIT_WORK(&dac33->work, dac33_work);
-                }
-        }
-
         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
                 dac33->supplies[i].supply = dac33_supply_names[i];
 
-        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
+        ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
                                  dac33->supplies);
 
         if (ret != 0) {
-                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
                 goto err_get;
         }
 
-        /* Read the tlv320dac33 ID registers */
-        ret = dac33_hard_power(codec, 1);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
-                goto error_codec;
-        }
-        dac33_read_id(codec);
-        dac33_hard_power(codec, 0);
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto error_codec;
-        }
-
-        ret = snd_soc_register_dai(&dac33_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                snd_soc_unregister_codec(codec);
-                goto error_codec;
-        }
+        ret = snd_soc_register_codec(&client->dev,
+                        &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
+        if (ret < 0)
+                goto err_register;
 
         return ret;
-
-error_codec:
+err_register:
         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
 err_get:
-        if (dac33->irq >= 0) {
-                free_irq(dac33->irq, &dac33->codec);
-                destroy_workqueue(dac33->dac33_wq);
-        }
-error_wq:
         if (dac33->power_gpio >= 0)
                 gpio_free(dac33->power_gpio);
-error_gpio:
-        kfree(codec->reg_cache);
-error_reg:
-        tlv320dac33_codec = NULL;
+err_gpio:
         kfree(dac33);
-
         return ret;
 }
 
 static int __devexit dac33_i2c_remove(struct i2c_client *client)
 {
-        struct tlv320dac33_priv *dac33;
-
-        dac33 = i2c_get_clientdata(client);
+        struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
 
         if (unlikely(dac33->chip_power))
-                dac33_hard_power(&dac33->codec, 0);
+                dac33_hard_power(dac33->codec, 0);
 
         if (dac33->power_gpio >= 0)
                 gpio_free(dac33->power_gpio);
-        if (dac33->irq >= 0)
-                free_irq(dac33->irq, &dac33->codec);
 
         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
 
-        destroy_workqueue(dac33->dac33_wq);
-        snd_soc_unregister_dai(&dac33_dai);
-        snd_soc_unregister_codec(&dac33->codec);
-        kfree(dac33->codec.reg_cache);
+        snd_soc_unregister_codec(&client->dev);
         kfree(dac33);
-        tlv320dac33_codec = NULL;
 
         return 0;
 }
@@ -1691,10 +1626,11 @@ static const struct i2c_device_id tlv320dac33_i2c_id[] = {
         },
         { },
 };
+MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
 
 static struct i2c_driver tlv320dac33_i2c_driver = {
         .driver = {
-                .name = "tlv320dac33",
+                .name = "tlv320dac33-codec",
                 .owner = THIS_MODULE,
         },
         .probe          = dac33_i2c_probe,
@@ -1722,5 +1658,5 @@ module_exit(dac33_module_exit);
 
 
 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
-MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
+MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/tlv320dac33.h b/sound/soc/codecs/tlv320dac33.h
index eb8ae07f0bd2..ed69670747bf 100644
--- a/sound/soc/codecs/tlv320dac33.h
+++ b/sound/soc/codecs/tlv320dac33.h
@@ -1,7 +1,7 @@
 /*
  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
  *
- * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  *
  * Copyright:   (C) 2009 Nokia Corporation
  *
@@ -261,7 +261,4 @@
 #define TLV320DAC33_MCLK                0
 #define TLV320DAC33_SLEEPCLK            1
 
-extern struct snd_soc_dai dac33_dai;
-extern struct snd_soc_codec_device soc_codec_dev_tlv320dac33;
-
 #endif /* __TLV320DAC33_H */
diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c
index 99b70e5978a2..239e0c461068 100644
--- a/sound/soc/codecs/tpa6130a2.c
+++ b/sound/soc/codecs/tpa6130a2.c
@@ -3,7 +3,7 @@
  *
  * Copyright (C) Nokia Corporation
  *
- * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -29,7 +29,6 @@
 #include <linux/slab.h>
 #include <sound/tpa6130a2-plat.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 
 #include "tpa6130a2.h"
@@ -42,7 +41,7 @@ struct tpa6130a2_data {
         unsigned char regs[TPA6130A2_CACHEREGNUM];
         struct regulator *supply;
         int power_gpio;
-        unsigned char power_state;
+        u8 power_state:1;
         enum tpa_model id;
 };
 
@@ -78,8 +77,10 @@ static int tpa6130a2_i2c_write(int reg, u8 value)
 
         if (data->power_state) {
                 val = i2c_smbus_write_byte_data(tpa6130a2_client, reg, value);
-                if (val < 0)
+                if (val < 0) {
                         dev_err(&tpa6130a2_client->dev, "Write failed\n");
+                        return val;
+                }
         }
 
         /* Either powered on or off, we save the context */
@@ -98,47 +99,58 @@ static u8 tpa6130a2_read(int reg)
         return data->regs[reg];
 }
 
-static void tpa6130a2_initialize(void)
+static int tpa6130a2_initialize(void)
 {
         struct tpa6130a2_data *data;
-        int i;
+        int i, ret = 0;
 
         BUG_ON(tpa6130a2_client == NULL);
         data = i2c_get_clientdata(tpa6130a2_client);
 
-        for (i = 1; i < TPA6130A2_REG_VERSION; i++)
-                tpa6130a2_i2c_write(i, data->regs[i]);
+        for (i = 1; i < TPA6130A2_REG_VERSION; i++) {
+                ret = tpa6130a2_i2c_write(i, data->regs[i]);
+                if (ret < 0)
+                        break;
+        }
+
+        return ret;
 }
 
-static int tpa6130a2_power(int power)
+static int tpa6130a2_power(u8 power)
 {
         struct  tpa6130a2_data *data;
         u8      val;
-        int     ret;
+        int     ret = 0;
 
         BUG_ON(tpa6130a2_client == NULL);
         data = i2c_get_clientdata(tpa6130a2_client);
 
         mutex_lock(&data->mutex);
-        if (power) {
-                /* Power on */
-                if (data->power_gpio >= 0)
-                        gpio_set_value(data->power_gpio, 1);
+        if (power == data->power_state)
+                goto exit;
 
+        if (power) {
                 ret = regulator_enable(data->supply);
                 if (ret != 0) {
                         dev_err(&tpa6130a2_client->dev,
                                 "Failed to enable supply: %d\n", ret);
                         goto exit;
                 }
+                /* Power on */
+                if (data->power_gpio >= 0)
+                        gpio_set_value(data->power_gpio, 1);
 
                 data->power_state = 1;
-                tpa6130a2_initialize();
-
-                /* Clear SWS */
-                val = tpa6130a2_read(TPA6130A2_REG_CONTROL);
-                val &= ~TPA6130A2_SWS;
-                tpa6130a2_i2c_write(TPA6130A2_REG_CONTROL, val);
+                ret = tpa6130a2_initialize();
+                if (ret < 0) {
+                        dev_err(&tpa6130a2_client->dev,
+                                "Failed to initialize chip\n");
+                        if (data->power_gpio >= 0)
+                                gpio_set_value(data->power_gpio, 0);
+                        regulator_disable(data->supply);
+                        data->power_state = 0;
+                        goto exit;
+                }
         } else {
                 /* set SWS */
                 val = tpa6130a2_read(TPA6130A2_REG_CONTROL);
@@ -284,6 +296,7 @@ static void tpa6130a2_channel_enable(u8 channel, int enable)
                 /* Enable amplifier */
                 val = tpa6130a2_read(TPA6130A2_REG_CONTROL);
                 val |= channel;
+                val &= ~TPA6130A2_SWS;
                 tpa6130a2_i2c_write(TPA6130A2_REG_CONTROL, val);
 
                 /* Unmute channel */
@@ -304,84 +317,33 @@ static void tpa6130a2_channel_enable(u8 channel, int enable)
         }
 }
 
-static int tpa6130a2_left_event(struct snd_soc_dapm_widget *w,
-                struct snd_kcontrol *kcontrol, int event)
-{
-        switch (event) {
-        case SND_SOC_DAPM_POST_PMU:
-                tpa6130a2_channel_enable(TPA6130A2_HP_EN_L, 1);
-                break;
-        case SND_SOC_DAPM_POST_PMD:
-                tpa6130a2_channel_enable(TPA6130A2_HP_EN_L, 0);
-                break;
-        }
-        return 0;
-}
-
-static int tpa6130a2_right_event(struct snd_soc_dapm_widget *w,
-                struct snd_kcontrol *kcontrol, int event)
-{
-        switch (event) {
-        case SND_SOC_DAPM_POST_PMU:
-                tpa6130a2_channel_enable(TPA6130A2_HP_EN_R, 1);
-                break;
-        case SND_SOC_DAPM_POST_PMD:
-                tpa6130a2_channel_enable(TPA6130A2_HP_EN_R, 0);
-                break;
-        }
-        return 0;
-}
-
-static int tpa6130a2_supply_event(struct snd_soc_dapm_widget *w,
-                struct snd_kcontrol *kcontrol, int event)
+int tpa6130a2_stereo_enable(struct snd_soc_codec *codec, int enable)
 {
         int ret = 0;
-
-        switch (event) {
-        case SND_SOC_DAPM_POST_PMU:
+        if (enable) {
                 ret = tpa6130a2_power(1);
-                break;
-        case SND_SOC_DAPM_POST_PMD:
+                if (ret < 0)
+                        return ret;
+                tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L,
+                                         1);
+        } else {
+                tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L,
+                                         0);
                 ret = tpa6130a2_power(0);
-                break;
         }
+
         return ret;
 }
-
-static const struct snd_soc_dapm_widget tpa6130a2_dapm_widgets[] = {
-        SND_SOC_DAPM_PGA_E("TPA6130A2 Left", SND_SOC_NOPM,
-                        0, 0, NULL, 0, tpa6130a2_left_event,
-                        SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
-        SND_SOC_DAPM_PGA_E("TPA6130A2 Right", SND_SOC_NOPM,
-                        0, 0, NULL, 0, tpa6130a2_right_event,
-                        SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
-        SND_SOC_DAPM_SUPPLY("TPA6130A2 Enable", SND_SOC_NOPM,
-                        0, 0, tpa6130a2_supply_event,
-                        SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
-        /* Outputs */
-        SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Left"),
-        SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Right"),
-};
-
-static const struct snd_soc_dapm_route audio_map[] = {
-        {"TPA6130A2 Headphone Left", NULL, "TPA6130A2 Left"},
-        {"TPA6130A2 Headphone Right", NULL, "TPA6130A2 Right"},
-
-        {"TPA6130A2 Headphone Left", NULL, "TPA6130A2 Enable"},
-        {"TPA6130A2 Headphone Right", NULL, "TPA6130A2 Enable"},
-};
+EXPORT_SYMBOL_GPL(tpa6130a2_stereo_enable);
 
 int tpa6130a2_add_controls(struct snd_soc_codec *codec)
 {
         struct  tpa6130a2_data *data;
 
-        BUG_ON(tpa6130a2_client == NULL);
-        data = i2c_get_clientdata(tpa6130a2_client);
-
-        snd_soc_dapm_new_controls(codec, tpa6130a2_dapm_widgets,
-                                ARRAY_SIZE(tpa6130a2_dapm_widgets));
+        if (tpa6130a2_client == NULL)
+                return -ENODEV;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        data = i2c_get_clientdata(tpa6130a2_client);
 
         if (data->id == TPA6140A2)
                 return snd_soc_add_controls(codec, tpa6140a2_controls,
@@ -389,7 +351,6 @@ int tpa6130a2_add_controls(struct snd_soc_codec *codec)
         else
                 return snd_soc_add_controls(codec, tpa6130a2_controls,
                                                 ARRAY_SIZE(tpa6130a2_controls));
-
 }
 EXPORT_SYMBOL_GPL(tpa6130a2_add_controls);
 
@@ -534,7 +495,7 @@ static void __exit tpa6130a2_exit(void)
         i2c_del_driver(&tpa6130a2_i2c_driver);
 }
 
-MODULE_AUTHOR("Peter Ujfalusi");
+MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
 MODULE_DESCRIPTION("TPA6130A2 Headphone amplifier driver");
 MODULE_LICENSE("GPL");
 
diff --git a/sound/soc/codecs/tpa6130a2.h b/sound/soc/codecs/tpa6130a2.h
index 57e867fd86d1..417444020ba6 100644
--- a/sound/soc/codecs/tpa6130a2.h
+++ b/sound/soc/codecs/tpa6130a2.h
@@ -3,7 +3,7 @@
  *
  * Copyright (C) Nokia Corporation
  *
- * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -57,5 +57,6 @@
 #define TPA6130A2_VERSION_MASK          (0x0f)
 
 extern int tpa6130a2_add_controls(struct snd_soc_codec *codec);
+extern int tpa6130a2_stereo_enable(struct snd_soc_codec *codec, int enable);
 
 #endif /* __TPA6130A2_H__ */
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 7b618bbff884..bec788b12613 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -32,11 +32,19 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
-#include "twl4030.h"
+/* Register descriptions are here */
+#include <linux/mfd/twl4030-codec.h>
+
+/* Shadow register used by the audio driver */
+#define TWL4030_REG_SW_SHADOW           0x4A
+#define TWL4030_CACHEREGNUM     (TWL4030_REG_SW_SHADOW + 1)
+
+/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
+#define TWL4030_HFL_EN                  0x01
+#define TWL4030_HFR_EN                  0x02
 
 /*
  * twl4030 register cache & default register settings
@@ -224,6 +232,16 @@ static int twl4030_write(struct snd_soc_codec *codec,
         return 0;
 }
 
+static inline void twl4030_wait_ms(int time)
+{
+        if (time < 60) {
+                time *= 1000;
+                usleep_range(time, time + 500);
+        } else {
+                msleep(time);
+        }
+}
+
 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
 {
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
@@ -262,7 +280,7 @@ static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
                                  i, val, twl4030_reg[i]);
                 }
         }
-        dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
+        dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
                  difference, difference ? "Not OK" : "OK");
 }
 
@@ -277,21 +295,19 @@ static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
 
 }
 
-static void twl4030_init_chip(struct platform_device *pdev)
+static void twl4030_init_chip(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct twl4030_setup_data *setup = socdev->codec_data;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct twl4030_codec_audio_data *pdata = dev_get_platdata(codec->dev);
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
         u8 reg, byte;
         int i = 0;
 
         /* Check defaults, if instructed before anything else */
-        if (setup && setup->check_defaults)
+        if (pdata && pdata->check_defaults)
                 twl4030_check_defaults(codec);
 
         /* Reset registers, if no setup data or if instructed to do so */
-        if (!setup || (setup && setup->reset_registers))
+        if (!pdata || (pdata && pdata->reset_registers))
                 twl4030_reset_registers(codec);
 
         /* Refresh APLL_CTL register from HW */
@@ -312,20 +328,14 @@ static void twl4030_init_chip(struct platform_device *pdev)
         twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
 
         /* Machine dependent setup */
-        if (!setup)
+        if (!pdata)
                 return;
 
-        twl4030->digimic_delay = setup->digimic_delay;
-
-        /* Configuration for headset ramp delay from setup data */
-        if (setup->sysclk != twl4030->sysclk)
-                dev_warn(codec->dev,
-                                "Mismatch in APLL mclk: %u (configured: %u)\n",
-                                setup->sysclk, twl4030->sysclk);
+        twl4030->digimic_delay = pdata->digimic_delay;
 
         reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
         reg &= ~TWL4030_RAMP_DELAY;
-        reg |= (setup->ramp_delay_value << 2);
+        reg |= (pdata->ramp_delay_value << 2);
         twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
 
         /* initiate offset cancellation */
@@ -333,14 +343,18 @@ static void twl4030_init_chip(struct platform_device *pdev)
 
         reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
         reg &= ~TWL4030_OFFSET_CNCL_SEL;
-        reg |= setup->offset_cncl_path;
+        reg |= pdata->offset_cncl_path;
         twl4030_write(codec, TWL4030_REG_ANAMICL,
                 reg | TWL4030_CNCL_OFFSET_START);
 
-        /* wait for offset cancellation to complete */
+        /*
+         * Wait for offset cancellation to complete.
+         * Since this takes a while, do not slam the i2c.
+         * Start polling the status after ~20ms.
+         */
+        msleep(20);
         do {
-                /* this takes a little while, so don't slam i2c */
-                udelay(2000);
+                usleep_range(1000, 2000);
                 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
                                     TWL4030_REG_ANAMICL);
         } while ((i++ < 100) &&
@@ -718,23 +732,24 @@ static int aif_event(struct snd_soc_dapm_widget *w,
 
 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 {
-        struct snd_soc_device *socdev = codec->socdev;
-        struct twl4030_setup_data *setup = socdev->codec_data;
-
+        struct twl4030_codec_audio_data *pdata = codec->dev->platform_data;
         unsigned char hs_gain, hs_pop;
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
         /* Base values for ramp delay calculation: 2^19 - 2^26 */
         unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
                                     8388608, 16777216, 33554432, 67108864};
+        unsigned int delay;
 
         hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
         hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
+        delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
+                twl4030->sysclk) + 1;
 
         /* Enable external mute control, this dramatically reduces
          * the pop-noise */
-        if (setup && setup->hs_extmute) {
-                if (setup->set_hs_extmute) {
-                        setup->set_hs_extmute(1);
+        if (pdata && pdata->hs_extmute) {
+                if (pdata->set_hs_extmute) {
+                        pdata->set_hs_extmute(1);
                 } else {
                         hs_pop |= TWL4030_EXTMUTE;
                         twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
@@ -752,16 +767,14 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
                 hs_pop |= TWL4030_RAMP_EN;
                 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
                 /* Wait ramp delay time + 1, so the VMID can settle */
-                mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
-                        twl4030->sysclk) + 1);
+                twl4030_wait_ms(delay);
         } else {
                 /* Headset ramp-down _not_ according to
                  * the TRM, but in a way that it is working */
                 hs_pop &= ~TWL4030_RAMP_EN;
                 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
                 /* Wait ramp delay time + 1, so the VMID can settle */
-                mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
-                        twl4030->sysclk) + 1);
+                twl4030_wait_ms(delay);
                 /* Bypass the reg_cache to mute the headset */
                 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
                                         hs_gain & (~0x0f),
@@ -772,9 +785,9 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
         }
 
         /* Disable external mute */
-        if (setup && setup->hs_extmute) {
-                if (setup->set_hs_extmute) {
-                        setup->set_hs_extmute(0);
+        if (pdata && pdata->hs_extmute) {
+                if (pdata->set_hs_extmute) {
+                        pdata->set_hs_extmute(0);
                 } else {
                         hs_pop &= ~TWL4030_EXTMUTE;
                         twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
@@ -836,7 +849,7 @@ static int digimic_event(struct snd_soc_dapm_widget *w,
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
 
         if (twl4030->digimic_delay)
-                mdelay(twl4030->digimic_delay);
+                twl4030_wait_ms(twl4030->digimic_delay);
         return 0;
 }
 
@@ -1622,10 +1635,11 @@ static const struct snd_soc_dapm_route intercon[] = {
 
 static int twl4030_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
-                                 ARRAY_SIZE(twl4030_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+        snd_soc_dapm_new_controls(dapm, twl4030_dapm_widgets,
+                                 ARRAY_SIZE(twl4030_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
 
         return 0;
 }
@@ -1639,14 +1653,14 @@ static int twl4030_set_bias_level(struct snd_soc_codec *codec,
         case SND_SOC_BIAS_PREPARE:
                 break;
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF)
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
                         twl4030_codec_enable(codec, 1);
                 break;
         case SND_SOC_BIAS_OFF:
                 twl4030_codec_enable(codec, 0);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -1707,10 +1721,10 @@ static int twl4030_startup(struct snd_pcm_substream *substream,
                            struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
 
+        snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
         if (twl4030->master_substream) {
                 twl4030->slave_substream = substream;
                 /* The DAI has one configuration for playback and capture, so
@@ -1738,8 +1752,7 @@ static void twl4030_shutdown(struct snd_pcm_substream *substream,
                              struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
 
         if (twl4030->master_substream == substream)
@@ -1764,8 +1777,7 @@ static int twl4030_hw_params(struct snd_pcm_substream *substream,
                            struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
         u8 mode, old_mode, format, old_format;
 
@@ -1837,7 +1849,7 @@ static int twl4030_hw_params(struct snd_pcm_substream *substream,
         case SNDRV_PCM_FORMAT_S16_LE:
                 format |= TWL4030_DATA_WIDTH_16S_16W;
                 break;
-        case SNDRV_PCM_FORMAT_S24_LE:
+        case SNDRV_PCM_FORMAT_S32_LE:
                 format |= TWL4030_DATA_WIDTH_32S_24W;
                 break;
         default:
@@ -1999,13 +2011,12 @@ static int twl4030_voice_startup(struct snd_pcm_substream *substream,
                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
         u8 mode;
 
         /* If the system master clock is not 26MHz, the voice PCM interface is
-         * not avilable.
+         * not available.
          */
         if (twl4030->sysclk != 26000) {
                 dev_err(codec->dev, "The board is configured for %u Hz, while"
@@ -2015,7 +2026,7 @@ static int twl4030_voice_startup(struct snd_pcm_substream *substream,
         }
 
         /* If the codec mode is not option2, the voice PCM interface is not
-         * avilable.
+         * available.
          */
         mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
                 & TWL4030_OPT_MODE;
@@ -2033,8 +2044,7 @@ static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
                                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
 
         /* Enable voice digital filters */
         twl4030_voice_enable(codec, substream->stream, 0);
@@ -2044,8 +2054,7 @@ static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
         u8 old_mode, mode;
 
@@ -2173,9 +2182,9 @@ static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
 }
 
 #define TWL4030_RATES    (SNDRV_PCM_RATE_8000_48000)
-#define TWL4030_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
+#define TWL4030_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
 
-static struct snd_soc_dai_ops twl4030_dai_ops = {
+static struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
         .startup        = twl4030_startup,
         .shutdown       = twl4030_shutdown,
         .hw_params      = twl4030_hw_params,
@@ -2193,9 +2202,9 @@ static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
         .set_tristate   = twl4030_voice_set_tristate,
 };
 
-struct snd_soc_dai twl4030_dai[] = {
+static struct snd_soc_dai_driver twl4030_dai[] = {
 {
-        .name = "twl4030",
+        .name = "twl4030-hifi",
         .playback = {
                 .stream_name = "HiFi Playback",
                 .channels_min = 2,
@@ -2208,10 +2217,10 @@ struct snd_soc_dai twl4030_dai[] = {
                 .channels_max = 4,
                 .rates = TWL4030_RATES,
                 .formats = TWL4030_FORMATS,},
-        .ops = &twl4030_dai_ops,
+        .ops = &twl4030_dai_hifi_ops,
 },
 {
-        .name = "twl4030 Voice",
+        .name = "twl4030-voice",
         .playback = {
                 .stream_name = "Voice Playback",
                 .channels_min = 1,
@@ -2227,164 +2236,91 @@ struct snd_soc_dai twl4030_dai[] = {
         .ops = &twl4030_dai_voice_ops,
 },
 };
-EXPORT_SYMBOL_GPL(twl4030_dai);
 
-static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
+static int twl4030_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
         return 0;
 }
 
-static int twl4030_soc_resume(struct platform_device *pdev)
+static int twl4030_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         return 0;
 }
 
-static struct snd_soc_codec *twl4030_codec;
-
-static int twl4030_soc_probe(struct platform_device *pdev)
+static int twl4030_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret;
-
-        BUG_ON(!twl4030_codec);
-
-        codec = twl4030_codec;
-        socdev->card->codec = codec;
-
-        twl4030_init_chip(pdev);
+        struct twl4030_priv *twl4030;
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "failed to create pcms\n");
-                return ret;
+        twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
+        if (twl4030 == NULL) {
+                printk("Can not allocate memroy\n");
+                return -ENOMEM;
         }
+        snd_soc_codec_set_drvdata(codec, twl4030);
+        /* Set the defaults, and power up the codec */
+        twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
+        codec->dapm.idle_bias_off = 1;
+
+        twl4030_init_chip(codec);
 
         snd_soc_add_controls(codec, twl4030_snd_controls,
                                 ARRAY_SIZE(twl4030_snd_controls));
         twl4030_add_widgets(codec);
-
         return 0;
 }
 
-static int twl4030_soc_remove(struct platform_device *pdev)
+static int twl4030_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
 
         /* Reset registers to their chip default before leaving */
         twl4030_reset_registers(codec);
         twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
+        kfree(twl4030);
         return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
+        .probe = twl4030_soc_probe,
+        .remove = twl4030_soc_remove,
+        .suspend = twl4030_soc_suspend,
+        .resume = twl4030_soc_resume,
+        .read = twl4030_read_reg_cache,
+        .write = twl4030_write,
+        .set_bias_level = twl4030_set_bias_level,
+        .reg_cache_size = sizeof(twl4030_reg),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = twl4030_reg,
+};
+
 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
 {
         struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
-        struct snd_soc_codec *codec;
-        struct twl4030_priv *twl4030;
-        int ret;
 
         if (!pdata) {
                 dev_err(&pdev->dev, "platform_data is missing\n");
                 return -EINVAL;
         }
 
-        twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
-        if (twl4030 == NULL) {
-                dev_err(&pdev->dev, "Can not allocate memroy\n");
-                return -ENOMEM;
-        }
-
-        codec = &twl4030->codec;
-        snd_soc_codec_set_drvdata(codec, twl4030);
-        codec->dev = &pdev->dev;
-        twl4030_dai[0].dev = &pdev->dev;
-        twl4030_dai[1].dev = &pdev->dev;
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "twl4030";
-        codec->owner = THIS_MODULE;
-        codec->read = twl4030_read_reg_cache;
-        codec->write = twl4030_write;
-        codec->set_bias_level = twl4030_set_bias_level;
-        codec->idle_bias_off = 1;
-        codec->dai = twl4030_dai;
-        codec->num_dai = ARRAY_SIZE(twl4030_dai);
-        codec->reg_cache_size = sizeof(twl4030_reg);
-        codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
-                                        GFP_KERNEL);
-        if (codec->reg_cache == NULL) {
-                ret = -ENOMEM;
-                goto error_cache;
-        }
-
-        platform_set_drvdata(pdev, twl4030);
-        twl4030_codec = codec;
-
-        /* Set the defaults, and power up the codec */
-        twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto error_codec;
-        }
-
-        ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
-                snd_soc_unregister_codec(codec);
-                goto error_codec;
-        }
-
-        return 0;
-
-error_codec:
-        twl4030_codec_enable(codec, 0);
-        kfree(codec->reg_cache);
-error_cache:
-        kfree(twl4030);
-        return ret;
+        return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
+                        twl4030_dai, ARRAY_SIZE(twl4030_dai));
 }
 
 static int __devexit twl4030_codec_remove(struct platform_device *pdev)
 {
-        struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
-
-        snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
-        snd_soc_unregister_codec(&twl4030->codec);
-        kfree(twl4030->codec.reg_cache);
-        kfree(twl4030);
-
-        twl4030_codec = NULL;
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
-MODULE_ALIAS("platform:twl4030_codec_audio");
+MODULE_ALIAS("platform:twl4030-codec");
 
 static struct platform_driver twl4030_codec_driver = {
         .probe          = twl4030_codec_probe,
         .remove         = __devexit_p(twl4030_codec_remove),
         .driver         = {
-                .name   = "twl4030_codec_audio",
+                .name   = "twl4030-codec",
                 .owner  = THIS_MODULE,
         },
 };
@@ -2401,14 +2337,6 @@ static void __exit twl4030_exit(void)
 }
 module_exit(twl4030_exit);
 
-struct snd_soc_codec_device soc_codec_dev_twl4030 = {
-        .probe = twl4030_soc_probe,
-        .remove = twl4030_soc_remove,
-        .suspend = twl4030_soc_suspend,
-        .resume = twl4030_soc_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
-
 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
 MODULE_AUTHOR("Steve Sakoman");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h
deleted file mode 100644
index 6c57430f6e24..000000000000
--- a/sound/soc/codecs/twl4030.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * ALSA SoC TWL4030 codec driver
- *
- * Author: Steve Sakoman <steve@sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#ifndef __TWL4030_AUDIO_H__
-#define __TWL4030_AUDIO_H__
-
-/* Register descriptions are here */
-#include <linux/mfd/twl4030-codec.h>
-
-/* Shadow register used by the audio driver */
-#define TWL4030_REG_SW_SHADOW           0x4A
-#define TWL4030_CACHEREGNUM     (TWL4030_REG_SW_SHADOW + 1)
-
-/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
-#define TWL4030_HFL_EN                  0x01
-#define TWL4030_HFR_EN                  0x02
-
-#define TWL4030_DAI_HIFI                0
-#define TWL4030_DAI_VOICE               1
-
-extern struct snd_soc_dai twl4030_dai[2];
-extern struct snd_soc_codec_device soc_codec_dev_twl4030;
-
-struct twl4030_setup_data {
-        unsigned int ramp_delay_value;
-        unsigned int digimic_delay; /* in ms */
-        unsigned int sysclk;
-        unsigned int offset_cncl_path;
-        unsigned int check_defaults:1;
-        unsigned int reset_registers:1;
-        unsigned int hs_extmute:1;
-        void (*set_hs_extmute)(int mute);
-};
-
-#endif  /* End of __TWL4030_AUDIO_H__ */
-
-
diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index 64a807f1a8a1..4c336636d4f5 100644
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -34,18 +34,49 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
 #include "twl6040.h"
 
-#define TWL6040_RATES    (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
-#define TWL6040_FORMATS  (SNDRV_PCM_FMTBIT_S32_LE)
+#define TWL6040_RATES           SNDRV_PCM_RATE_8000_96000
+#define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
+
+#define TWL6040_OUTHS_0dB 0x00
+#define TWL6040_OUTHS_M30dB 0x0F
+#define TWL6040_OUTHF_0dB 0x03
+#define TWL6040_OUTHF_M52dB 0x1D
+
+#define TWL6040_RAMP_NONE       0
+#define TWL6040_RAMP_UP         1
+#define TWL6040_RAMP_DOWN       2
+
+#define TWL6040_HSL_VOL_MASK    0x0F
+#define TWL6040_HSL_VOL_SHIFT   0
+#define TWL6040_HSR_VOL_MASK    0xF0
+#define TWL6040_HSR_VOL_SHIFT   4
+#define TWL6040_HF_VOL_MASK     0x1F
+#define TWL6040_HF_VOL_SHIFT    0
+
+struct twl6040_output {
+        u16 active;
+        u16 left_vol;
+        u16 right_vol;
+        u16 left_step;
+        u16 right_step;
+        unsigned int step_delay;
+        u16 ramp;
+        u16 mute;
+        struct completion ramp_done;
+};
+
+struct twl6040_jack_data {
+        struct snd_soc_jack *jack;
+        int report;
+};
 
 /* codec private data */
 struct twl6040_data {
-        struct snd_soc_codec codec;
         int audpwron;
         int naudint;
         int codec_powered;
@@ -54,6 +85,17 @@ struct twl6040_data {
         unsigned int sysclk;
         struct snd_pcm_hw_constraint_list *sysclk_constraints;
         struct completion ready;
+        struct twl6040_jack_data hs_jack;
+        struct snd_soc_codec *codec;
+        struct workqueue_struct *workqueue;
+        struct delayed_work delayed_work;
+        struct mutex mutex;
+        struct twl6040_output headset;
+        struct twl6040_output handsfree;
+        struct workqueue_struct *hf_workqueue;
+        struct workqueue_struct *hs_workqueue;
+        struct delayed_work hs_delayed_work;
+        struct delayed_work hf_delayed_work;
 };
 
 /*
@@ -202,7 +244,7 @@ static int twl6040_read_reg_volatile(struct snd_soc_codec *codec,
         if (reg >= TWL6040_CACHEREGNUM)
                 return -EIO;
 
-        twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg);
+        twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &value, reg);
         twl6040_write_reg_cache(codec, reg, value);
 
         return value;
@@ -218,7 +260,7 @@ static int twl6040_write(struct snd_soc_codec *codec,
                 return -EIO;
 
         twl6040_write_reg_cache(codec, reg, value);
-        return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
+        return twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, value, reg);
 }
 
 static void twl6040_init_vio_regs(struct snd_soc_codec *codec)
@@ -255,6 +297,305 @@ static void twl6040_init_vdd_regs(struct snd_soc_codec *codec)
         }
 }
 
+/*
+ * Ramp HS PGA volume to minimise pops at stream startup and shutdown.
+ */
+static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec,
+                        unsigned int left_step, unsigned int right_step)
+{
+
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+        struct twl6040_output *headset = &priv->headset;
+        int left_complete = 0, right_complete = 0;
+        u8 reg, val;
+
+        /* left channel */
+        left_step = (left_step > 0xF) ? 0xF : left_step;
+        reg = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN);
+        val = (~reg & TWL6040_HSL_VOL_MASK);
+
+        if (headset->ramp == TWL6040_RAMP_UP) {
+                /* ramp step up */
+                if (val < headset->left_vol) {
+                        val += left_step;
+                        reg &= ~TWL6040_HSL_VOL_MASK;
+                        twl6040_write(codec, TWL6040_REG_HSGAIN,
+                                        (reg | (~val & TWL6040_HSL_VOL_MASK)));
+                } else {
+                        left_complete = 1;
+                }
+        } else if (headset->ramp == TWL6040_RAMP_DOWN) {
+                /* ramp step down */
+                if (val > 0x0) {
+                        val -= left_step;
+                        reg &= ~TWL6040_HSL_VOL_MASK;
+                        twl6040_write(codec, TWL6040_REG_HSGAIN, reg |
+                                                (~val & TWL6040_HSL_VOL_MASK));
+                } else {
+                        left_complete = 1;
+                }
+        }
+
+        /* right channel */
+        right_step = (right_step > 0xF) ? 0xF : right_step;
+        reg = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN);
+        val = (~reg & TWL6040_HSR_VOL_MASK) >> TWL6040_HSR_VOL_SHIFT;
+
+        if (headset->ramp == TWL6040_RAMP_UP) {
+                /* ramp step up */
+                if (val < headset->right_vol) {
+                        val += right_step;
+                        reg &= ~TWL6040_HSR_VOL_MASK;
+                        twl6040_write(codec, TWL6040_REG_HSGAIN,
+                                (reg | (~val << TWL6040_HSR_VOL_SHIFT)));
+                } else {
+                        right_complete = 1;
+                }
+        } else if (headset->ramp == TWL6040_RAMP_DOWN) {
+                /* ramp step down */
+                if (val > 0x0) {
+                        val -= right_step;
+                        reg &= ~TWL6040_HSR_VOL_MASK;
+                        twl6040_write(codec, TWL6040_REG_HSGAIN,
+                                         reg | (~val << TWL6040_HSR_VOL_SHIFT));
+                } else {
+                        right_complete = 1;
+                }
+        }
+
+        return left_complete & right_complete;
+}
+
+/*
+ * Ramp HF PGA volume to minimise pops at stream startup and shutdown.
+ */
+static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec,
+                        unsigned int left_step, unsigned int right_step)
+{
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+        struct twl6040_output *handsfree = &priv->handsfree;
+        int left_complete = 0, right_complete = 0;
+        u16 reg, val;
+
+        /* left channel */
+        left_step = (left_step > 0x1D) ? 0x1D : left_step;
+        reg = twl6040_read_reg_cache(codec, TWL6040_REG_HFLGAIN);
+        reg = 0x1D - reg;
+        val = (reg & TWL6040_HF_VOL_MASK);
+        if (handsfree->ramp == TWL6040_RAMP_UP) {
+                /* ramp step up */
+                if (val < handsfree->left_vol) {
+                        val += left_step;
+                        reg &= ~TWL6040_HF_VOL_MASK;
+                        twl6040_write(codec, TWL6040_REG_HFLGAIN,
+                                                reg | (0x1D - val));
+                } else {
+                        left_complete = 1;
+                }
+        } else if (handsfree->ramp == TWL6040_RAMP_DOWN) {
+                /* ramp step down */
+                if (val > 0) {
+                        val -= left_step;
+                        reg &= ~TWL6040_HF_VOL_MASK;
+                        twl6040_write(codec, TWL6040_REG_HFLGAIN,
+                                                reg | (0x1D - val));
+                } else {
+                        left_complete = 1;
+                }
+        }
+
+        /* right channel */
+        right_step = (right_step > 0x1D) ? 0x1D : right_step;
+        reg = twl6040_read_reg_cache(codec, TWL6040_REG_HFRGAIN);
+        reg = 0x1D - reg;
+        val = (reg & TWL6040_HF_VOL_MASK);
+        if (handsfree->ramp == TWL6040_RAMP_UP) {
+                /* ramp step up */
+                if (val < handsfree->right_vol) {
+                        val += right_step;
+                        reg &= ~TWL6040_HF_VOL_MASK;
+                        twl6040_write(codec, TWL6040_REG_HFRGAIN,
+                                                reg | (0x1D - val));
+                } else {
+                        right_complete = 1;
+                }
+        } else if (handsfree->ramp == TWL6040_RAMP_DOWN) {
+                /* ramp step down */
+                if (val > 0) {
+                        val -= right_step;
+                        reg &= ~TWL6040_HF_VOL_MASK;
+                        twl6040_write(codec, TWL6040_REG_HFRGAIN,
+                                                reg | (0x1D - val));
+                }
+        }
+
+        return left_complete & right_complete;
+}
+
+/*
+ * This work ramps both output PGAs at stream start/stop time to
+ * minimise pop associated with DAPM power switching.
+ */
+static void twl6040_pga_hs_work(struct work_struct *work)
+{
+        struct twl6040_data *priv =
+                container_of(work, struct twl6040_data, hs_delayed_work.work);
+        struct snd_soc_codec *codec = priv->codec;
+        struct twl6040_output *headset = &priv->headset;
+        unsigned int delay = headset->step_delay;
+        int i, headset_complete;
+
+        /* do we need to ramp at all ? */
+        if (headset->ramp == TWL6040_RAMP_NONE)
+                return;
+
+        /* HS PGA volumes have 4 bits of resolution to ramp */
+        for (i = 0; i <= 16; i++) {
+                headset_complete = 1;
+                if (headset->ramp != TWL6040_RAMP_NONE)
+                        headset_complete = twl6040_hs_ramp_step(codec,
+                                                        headset->left_step,
+                                                        headset->right_step);
+
+                /* ramp finished ? */
+                if (headset_complete)
+                        break;
+
+                /*
+                 * TODO: tune: delay is longer over 0dB
+                 * as increases are larger.
+                 */
+                if (i >= 8)
+                        schedule_timeout_interruptible(msecs_to_jiffies(delay +
+                                                        (delay >> 1)));
+                else
+                        schedule_timeout_interruptible(msecs_to_jiffies(delay));
+        }
+
+        if (headset->ramp == TWL6040_RAMP_DOWN) {
+                headset->active = 0;
+                complete(&headset->ramp_done);
+        } else {
+                headset->active = 1;
+        }
+        headset->ramp = TWL6040_RAMP_NONE;
+}
+
+static void twl6040_pga_hf_work(struct work_struct *work)
+{
+        struct twl6040_data *priv =
+                container_of(work, struct twl6040_data, hf_delayed_work.work);
+        struct snd_soc_codec *codec = priv->codec;
+        struct twl6040_output *handsfree = &priv->handsfree;
+        unsigned int delay = handsfree->step_delay;
+        int i, handsfree_complete;
+
+        /* do we need to ramp at all ? */
+        if (handsfree->ramp == TWL6040_RAMP_NONE)
+                return;
+
+        /* HF PGA volumes have 5 bits of resolution to ramp */
+        for (i = 0; i <= 32; i++) {
+                handsfree_complete = 1;
+                if (handsfree->ramp != TWL6040_RAMP_NONE)
+                        handsfree_complete = twl6040_hf_ramp_step(codec,
+                                                        handsfree->left_step,
+                                                        handsfree->right_step);
+
+                /* ramp finished ? */
+                if (handsfree_complete)
+                        break;
+
+                /*
+                 * TODO: tune: delay is longer over 0dB
+                 * as increases are larger.
+                 */
+                if (i >= 16)
+                        schedule_timeout_interruptible(msecs_to_jiffies(delay +
+                                                       (delay >> 1)));
+                else
+                        schedule_timeout_interruptible(msecs_to_jiffies(delay));
+        }
+
+
+        if (handsfree->ramp == TWL6040_RAMP_DOWN) {
+                handsfree->active = 0;
+                complete(&handsfree->ramp_done);
+        } else
+                handsfree->active = 1;
+        handsfree->ramp = TWL6040_RAMP_NONE;
+}
+
+static int pga_event(struct snd_soc_dapm_widget *w,
+                        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+        struct twl6040_output *out;
+        struct delayed_work *work;
+        struct workqueue_struct *queue;
+
+        switch (w->shift) {
+        case 2:
+        case 3:
+                out = &priv->headset;
+                work = &priv->hs_delayed_work;
+                queue = priv->hs_workqueue;
+                out->step_delay = 5;    /* 5 ms between volume ramp steps */
+                break;
+        case 4:
+                out = &priv->handsfree;
+                work = &priv->hf_delayed_work;
+                queue = priv->hf_workqueue;
+                out->step_delay = 5;    /* 5 ms between volume ramp steps */
+                if (SND_SOC_DAPM_EVENT_ON(event))
+                        priv->non_lp++;
+                else
+                        priv->non_lp--;
+                break;
+        default:
+                return -1;
+        }
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                if (out->active)
+                        break;
+
+                /* don't use volume ramp for power-up */
+                out->left_step = out->left_vol;
+                out->right_step = out->right_vol;
+
+                if (!delayed_work_pending(work)) {
+                        out->ramp = TWL6040_RAMP_UP;
+                        queue_delayed_work(queue, work,
+                                        msecs_to_jiffies(1));
+                }
+                break;
+
+        case SND_SOC_DAPM_PRE_PMD:
+                if (!out->active)
+                        break;
+
+                if (!delayed_work_pending(work)) {
+                        /* use volume ramp for power-down */
+                        out->left_step = 1;
+                        out->right_step = 1;
+                        out->ramp = TWL6040_RAMP_DOWN;
+                        INIT_COMPLETION(out->ramp_done);
+
+                        queue_delayed_work(queue, work,
+                                        msecs_to_jiffies(1));
+
+                        wait_for_completion_timeout(&out->ramp_done,
+                                        msecs_to_jiffies(2000));
+                }
+                break;
+        }
+
+        return 0;
+}
+
 /* twl6040 codec manual power-up sequence */
 static void twl6040_power_up(struct snd_soc_codec *codec)
 {
@@ -383,6 +724,47 @@ static int twl6040_power_mode_event(struct snd_soc_dapm_widget *w,
         return 0;
 }
 
+static void twl6040_hs_jack_report(struct snd_soc_codec *codec,
+                                   struct snd_soc_jack *jack, int report)
+{
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+        int status;
+
+        mutex_lock(&priv->mutex);
+
+        /* Sync status */
+        status = twl6040_read_reg_volatile(codec, TWL6040_REG_STATUS);
+        if (status & TWL6040_PLUGCOMP)
+                snd_soc_jack_report(jack, report, report);
+        else
+                snd_soc_jack_report(jack, 0, report);
+
+        mutex_unlock(&priv->mutex);
+}
+
+void twl6040_hs_jack_detect(struct snd_soc_codec *codec,
+                                struct snd_soc_jack *jack, int report)
+{
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
+        struct twl6040_jack_data *hs_jack = &priv->hs_jack;
+
+        hs_jack->jack = jack;
+        hs_jack->report = report;
+
+        twl6040_hs_jack_report(codec, hs_jack->jack, hs_jack->report);
+}
+EXPORT_SYMBOL_GPL(twl6040_hs_jack_detect);
+
+static void twl6040_accessory_work(struct work_struct *work)
+{
+        struct twl6040_data *priv = container_of(work,
+                                        struct twl6040_data, delayed_work.work);
+        struct snd_soc_codec *codec = priv->codec;
+        struct twl6040_jack_data *hs_jack = &priv->hs_jack;
+
+        twl6040_hs_jack_report(codec, hs_jack->jack, hs_jack->report);
+}
+
 /* audio interrupt handler */
 static irqreturn_t twl6040_naudint_handler(int irq, void *data)
 {
@@ -390,33 +772,180 @@ static irqreturn_t twl6040_naudint_handler(int irq, void *data)
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
         u8 intid;
 
-        twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID);
+        twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID);
 
-        switch (intid) {
-        case TWL6040_THINT:
+        if (intid & TWL6040_THINT)
                 dev_alert(codec->dev, "die temp over-limit detection\n");
+
+        if ((intid & TWL6040_PLUGINT) || (intid & TWL6040_UNPLUGINT))
+                queue_delayed_work(priv->workqueue, &priv->delayed_work,
+                                                        msecs_to_jiffies(200));
+
+        if (intid & TWL6040_HOOKINT)
+                dev_info(codec->dev, "hook detection\n");
+
+        if (intid & TWL6040_HFINT)
+                dev_alert(codec->dev, "hf drivers over current detection\n");
+
+        if (intid & TWL6040_VIBINT)
+                dev_alert(codec->dev, "vib drivers over current detection\n");
+
+        if (intid & TWL6040_READYINT)
+                complete(&priv->ready);
+
+        return IRQ_HANDLED;
+}
+
+static int twl6040_put_volsw(struct snd_kcontrol *kcontrol,
+                                  struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
+        struct twl6040_output *out = NULL;
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        int ret;
+        unsigned int reg = mc->reg;
+
+        /* For HS and HF we shadow the values and only actually write
+         * them out when active in order to ensure the amplifier comes on
+         * as quietly as possible. */
+        switch (reg) {
+        case TWL6040_REG_HSGAIN:
+                out = &twl6040_priv->headset;
                 break;
-        case TWL6040_PLUGINT:
-        case TWL6040_UNPLUGINT:
-        case TWL6040_HOOKINT:
+        default:
                 break;
-        case TWL6040_HFINT:
-                dev_alert(codec->dev, "hf drivers over current detection\n");
+        }
+
+        if (out) {
+                out->left_vol = ucontrol->value.integer.value[0];
+                out->right_vol = ucontrol->value.integer.value[1];
+                if (!out->active)
+                        return 1;
+        }
+
+        ret = snd_soc_put_volsw(kcontrol, ucontrol);
+        if (ret < 0)
+                return ret;
+
+        return 1;
+}
+
+static int twl6040_get_volsw(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
+        struct twl6040_output *out = &twl6040_priv->headset;
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        unsigned int reg = mc->reg;
+
+        switch (reg) {
+        case TWL6040_REG_HSGAIN:
+                out = &twl6040_priv->headset;
+                ucontrol->value.integer.value[0] = out->left_vol;
+                ucontrol->value.integer.value[1] = out->right_vol;
+                return 0;
+
+        default:
                 break;
-        case TWL6040_VIBINT:
-                dev_alert(codec->dev, "vib drivers over current detection\n");
+        }
+
+        return snd_soc_get_volsw(kcontrol, ucontrol);
+}
+
+static int twl6040_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
+                                  struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
+        struct twl6040_output *out = NULL;
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        int ret;
+        unsigned int reg = mc->reg;
+
+        /* For HS and HF we shadow the values and only actually write
+         * them out when active in order to ensure the amplifier comes on
+         * as quietly as possible. */
+        switch (reg) {
+        case TWL6040_REG_HFLGAIN:
+        case TWL6040_REG_HFRGAIN:
+                out = &twl6040_priv->handsfree;
                 break;
-        case TWL6040_READYINT:
-                complete(&priv->ready);
+        default:
                 break;
+        }
+
+        if (out) {
+                out->left_vol = ucontrol->value.integer.value[0];
+                out->right_vol = ucontrol->value.integer.value[1];
+                if (!out->active)
+                        return 1;
+        }
+
+        ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
+        if (ret < 0)
+                return ret;
+
+        return 1;
+}
+
+static int twl6040_get_volsw_2r(struct snd_kcontrol *kcontrol,
+                                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
+        struct twl6040_output *out = &twl6040_priv->handsfree;
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        unsigned int reg = mc->reg;
+
+        /* If these are cached registers use the cache */
+        switch (reg) {
+        case TWL6040_REG_HFLGAIN:
+        case TWL6040_REG_HFRGAIN:
+                out = &twl6040_priv->handsfree;
+                ucontrol->value.integer.value[0] = out->left_vol;
+                ucontrol->value.integer.value[1] = out->right_vol;
+                return 0;
+
         default:
-                dev_err(codec->dev, "unknown audio interrupt %d\n", intid);
                 break;
         }
 
-        return IRQ_HANDLED;
+        return snd_soc_get_volsw_2r(kcontrol, ucontrol);
 }
 
+/* double control with volume update */
+#define SOC_TWL6040_DOUBLE_TLV(xname, xreg, shift_left, shift_right, xmax,\
+                                                        xinvert, tlv_array)\
+{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
+        .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+                 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+        .tlv.p = (tlv_array), \
+        .info = snd_soc_info_volsw, .get = twl6040_get_volsw, \
+        .put = twl6040_put_volsw, \
+        .private_value = (unsigned long)&(struct soc_mixer_control) \
+                {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
+                 .max = xmax, .platform_max = xmax, .invert = xinvert} }
+
+/* double control with volume update */
+#define SOC_TWL6040_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax,\
+                                xinvert, tlv_array)\
+{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
+        .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
+                SNDRV_CTL_ELEM_ACCESS_READWRITE | \
+                SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
+        .tlv.p = (tlv_array), \
+        .info = snd_soc_info_volsw_2r, \
+        .get = twl6040_get_volsw_2r, .put = twl6040_put_volsw_2r_vu, \
+        .private_value = (unsigned long)&(struct soc_mixer_control) \
+                {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
+                 .rshift = xshift, .max = xmax, .invert = xinvert}, }
+
 /*
  * MICATT volume control:
  * from -6 to 0 dB in 6 dB steps
@@ -425,9 +954,15 @@ static DECLARE_TLV_DB_SCALE(mic_preamp_tlv, -600, 600, 0);
 
 /*
  * MICGAIN volume control:
- * from 6 to 30 dB in 6 dB steps
+ * from -6 to 30 dB in 6 dB steps
+ */
+static DECLARE_TLV_DB_SCALE(mic_amp_tlv, -600, 600, 0);
+
+/*
+ * AFMGAIN volume control:
+ * from -18 to 24 dB in 6 dB steps
  */
-static DECLARE_TLV_DB_SCALE(mic_amp_tlv, 600, 600, 0);
+static DECLARE_TLV_DB_SCALE(afm_amp_tlv, -1800, 600, 0);
 
 /*
  * HSGAIN volume control:
@@ -456,8 +991,30 @@ static const char *twl6040_amicr_texts[] =
         {"Headset Mic", "Sub Mic", "Aux/FM Right", "Off"};
 
 static const struct soc_enum twl6040_enum[] = {
-        SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 3, twl6040_amicl_texts),
-        SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 3, twl6040_amicr_texts),
+        SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 4, twl6040_amicl_texts),
+        SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 4, twl6040_amicr_texts),
+};
+
+static const char *twl6040_hs_texts[] = {
+        "Off", "HS DAC", "Line-In amp"
+};
+
+static const struct soc_enum twl6040_hs_enum[] = {
+        SOC_ENUM_SINGLE(TWL6040_REG_HSLCTL, 5, ARRAY_SIZE(twl6040_hs_texts),
+                        twl6040_hs_texts),
+        SOC_ENUM_SINGLE(TWL6040_REG_HSRCTL, 5, ARRAY_SIZE(twl6040_hs_texts),
+                        twl6040_hs_texts),
+};
+
+static const char *twl6040_hf_texts[] = {
+        "Off", "HF DAC", "Line-In amp"
+};
+
+static const struct soc_enum twl6040_hf_enum[] = {
+        SOC_ENUM_SINGLE(TWL6040_REG_HFLCTL, 2, ARRAY_SIZE(twl6040_hf_texts),
+                        twl6040_hf_texts),
+        SOC_ENUM_SINGLE(TWL6040_REG_HFRCTL, 2, ARRAY_SIZE(twl6040_hf_texts),
+                        twl6040_hf_texts),
 };
 
 static const struct snd_kcontrol_new amicl_control =
@@ -467,18 +1024,18 @@ static const struct snd_kcontrol_new amicr_control =
         SOC_DAPM_ENUM("Route", twl6040_enum[1]);
 
 /* Headset DAC playback switches */
-static const struct snd_kcontrol_new hsdacl_switch_controls =
-        SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSLCTL, 5, 1, 0);
+static const struct snd_kcontrol_new hsl_mux_controls =
+        SOC_DAPM_ENUM("Route", twl6040_hs_enum[0]);
 
-static const struct snd_kcontrol_new hsdacr_switch_controls =
-        SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSRCTL, 5, 1, 0);
+static const struct snd_kcontrol_new hsr_mux_controls =
+        SOC_DAPM_ENUM("Route", twl6040_hs_enum[1]);
 
 /* Handsfree DAC playback switches */
-static const struct snd_kcontrol_new hfdacl_switch_controls =
-        SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFLCTL, 2, 1, 0);
+static const struct snd_kcontrol_new hfl_mux_controls =
+        SOC_DAPM_ENUM("Route", twl6040_hf_enum[0]);
 
-static const struct snd_kcontrol_new hfdacr_switch_controls =
-        SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFRCTL, 2, 1, 0);
+static const struct snd_kcontrol_new hfr_mux_controls =
+        SOC_DAPM_ENUM("Route", twl6040_hf_enum[1]);
 
 static const struct snd_kcontrol_new ep_driver_switch_controls =
         SOC_DAPM_SINGLE("Switch", TWL6040_REG_EARCTL, 0, 1, 0);
@@ -490,10 +1047,14 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = {
         SOC_DOUBLE_TLV("Capture Volume",
                 TWL6040_REG_MICGAIN, 0, 3, 4, 0, mic_amp_tlv),
 
+        /* AFM gains */
+        SOC_DOUBLE_TLV("Aux FM Volume",
+                TWL6040_REG_LINEGAIN, 0, 3, 7, 0, afm_amp_tlv),
+
         /* Playback gains */
-        SOC_DOUBLE_TLV("Headset Playback Volume",
+        SOC_TWL6040_DOUBLE_TLV("Headset Playback Volume",
                 TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv),
-        SOC_DOUBLE_R_TLV("Handsfree Playback Volume",
+        SOC_TWL6040_DOUBLE_R_TLV("Handsfree Playback Volume",
                 TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv),
         SOC_SINGLE_TLV("Earphone Playback Volume",
                 TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv),
@@ -526,6 +1087,12 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = {
         SND_SOC_DAPM_PGA("MicAmpR",
                         TWL6040_REG_MICRCTL, 0, 0, NULL, 0),
 
+        /* Auxiliary FM PGAs */
+        SND_SOC_DAPM_PGA("AFMAmpL",
+                        TWL6040_REG_MICLCTL, 1, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("AFMAmpR",
+                        TWL6040_REG_MICRCTL, 1, 0, NULL, 0),
+
         /* ADCs */
         SND_SOC_DAPM_ADC("ADC Left", "Left Front Capture",
                         TWL6040_REG_MICLCTL, 2, 0),
@@ -560,29 +1127,33 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = {
                         twl6040_power_mode_event,
                         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 
-        /* Analog playback switches */
-        SND_SOC_DAPM_SWITCH("HSDAC Left Playback",
-                        SND_SOC_NOPM, 0, 0, &hsdacl_switch_controls),
-        SND_SOC_DAPM_SWITCH("HSDAC Right Playback",
-                        SND_SOC_NOPM, 0, 0, &hsdacr_switch_controls),
-        SND_SOC_DAPM_SWITCH("HFDAC Left Playback",
-                        SND_SOC_NOPM, 0, 0, &hfdacl_switch_controls),
-        SND_SOC_DAPM_SWITCH("HFDAC Right Playback",
-                        SND_SOC_NOPM, 0, 0, &hfdacr_switch_controls),
+        SND_SOC_DAPM_MUX("HF Left Playback",
+                        SND_SOC_NOPM, 0, 0, &hfl_mux_controls),
+        SND_SOC_DAPM_MUX("HF Right Playback",
+                        SND_SOC_NOPM, 0, 0, &hfr_mux_controls),
+        /* Analog playback Muxes */
+        SND_SOC_DAPM_MUX("HS Left Playback",
+                        SND_SOC_NOPM, 0, 0, &hsl_mux_controls),
+        SND_SOC_DAPM_MUX("HS Right Playback",
+                        SND_SOC_NOPM, 0, 0, &hsr_mux_controls),
 
         /* Analog playback drivers */
-        SND_SOC_DAPM_PGA_E("Handsfree Left Driver",
+        SND_SOC_DAPM_OUT_DRV_E("Handsfree Left Driver",
                         TWL6040_REG_HFLCTL, 4, 0, NULL, 0,
-                        twl6040_power_mode_event,
-                        SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
-        SND_SOC_DAPM_PGA_E("Handsfree Right Driver",
+                        pga_event,
+                        SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+        SND_SOC_DAPM_OUT_DRV_E("Handsfree Right Driver",
                         TWL6040_REG_HFRCTL, 4, 0, NULL, 0,
-                        twl6040_power_mode_event,
-                        SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
-        SND_SOC_DAPM_PGA("Headset Left Driver",
-                        TWL6040_REG_HSLCTL, 2, 0, NULL, 0),
-        SND_SOC_DAPM_PGA("Headset Right Driver",
-                        TWL6040_REG_HSRCTL, 2, 0, NULL, 0),
+                        pga_event,
+                        SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+        SND_SOC_DAPM_OUT_DRV_E("Headset Left Driver",
+                        TWL6040_REG_HSLCTL, 2, 0, NULL, 0,
+                        pga_event,
+                        SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+        SND_SOC_DAPM_OUT_DRV_E("Headset Right Driver",
+                        TWL6040_REG_HSRCTL, 2, 0, NULL, 0,
+                        pga_event,
+                        SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
         SND_SOC_DAPM_SWITCH_E("Earphone Driver",
                         SND_SOC_NOPM, 0, 0, &ep_driver_switch_controls,
                         twl6040_power_mode_event,
@@ -612,12 +1183,18 @@ static const struct snd_soc_dapm_route intercon[] = {
         {"ADC Left", NULL, "MicAmpL"},
         {"ADC Right", NULL, "MicAmpR"},
 
-        /* Headset playback path */
-        {"HSDAC Left Playback", "Switch", "HSDAC Left"},
-        {"HSDAC Right Playback", "Switch", "HSDAC Right"},
+        /* AFM path */
+        {"AFMAmpL", "NULL", "AFML"},
+        {"AFMAmpR", "NULL", "AFMR"},
+
+        {"HS Left Playback", "HS DAC", "HSDAC Left"},
+        {"HS Left Playback", "Line-In amp", "AFMAmpL"},
+
+        {"HS Right Playback", "HS DAC", "HSDAC Right"},
+        {"HS Right Playback", "Line-In amp", "AFMAmpR"},
 
-        {"Headset Left Driver", NULL, "HSDAC Left Playback"},
-        {"Headset Right Driver", NULL, "HSDAC Right Playback"},
+        {"Headset Left Driver", "NULL", "HS Left Playback"},
+        {"Headset Right Driver", "NULL", "HS Right Playback"},
 
         {"HSOL", NULL, "Headset Left Driver"},
         {"HSOR", NULL, "Headset Right Driver"},
@@ -626,12 +1203,14 @@ static const struct snd_soc_dapm_route intercon[] = {
         {"Earphone Driver", "Switch", "HSDAC Left"},
         {"EP", NULL, "Earphone Driver"},
 
-        /* Handsfree playback path */
-        {"HFDAC Left Playback", "Switch", "HFDAC Left"},
-        {"HFDAC Right Playback", "Switch", "HFDAC Right"},
+        {"HF Left Playback", "HF DAC", "HFDAC Left"},
+        {"HF Left Playback", "Line-In amp", "AFMAmpL"},
 
-        {"HFDAC Left PGA", NULL, "HFDAC Left Playback"},
-        {"HFDAC Right PGA", NULL, "HFDAC Right Playback"},
+        {"HF Right Playback", "HF DAC", "HFDAC Right"},
+        {"HF Right Playback", "Line-In amp", "AFMAmpR"},
+
+        {"HFDAC Left PGA", NULL, "HF Left Playback"},
+        {"HFDAC Right PGA", NULL, "HF Right Playback"},
 
         {"Handsfree Left Driver", "Switch", "HFDAC Left PGA"},
         {"Handsfree Right Driver", "Switch", "HFDAC Right PGA"},
@@ -642,12 +1221,12 @@ static const struct snd_soc_dapm_route intercon[] = {
 
 static int twl6040_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, twl6040_dapm_widgets,
-                                 ARRAY_SIZE(twl6040_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_new_widgets(codec);
+        snd_soc_dapm_new_controls(dapm, twl6040_dapm_widgets,
+                                 ARRAY_SIZE(twl6040_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
+        snd_soc_dapm_new_widgets(dapm);
 
         return 0;
 }
@@ -660,10 +1239,10 @@ static int twl6040_power_up_completion(struct snd_soc_codec *codec,
         u8 intid;
 
         time_left = wait_for_completion_timeout(&priv->ready,
-                                msecs_to_jiffies(48));
+                                msecs_to_jiffies(144));
 
         if (!time_left) {
-                twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid,
+                twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid,
                                                         TWL6040_REG_INTID);
                 if (!(intid & TWL6040_READYINT)) {
                         dev_err(codec->dev, "timeout waiting for READYINT\n");
@@ -714,6 +1293,15 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec,
 
                 /* initialize vdd/vss registers with reg_cache */
                 twl6040_init_vdd_regs(codec);
+
+                /* Set external boost GPO */
+                twl6040_write(codec, TWL6040_REG_GPOCTL, 0x02);
+
+                /* Set initial minimal gain values */
+                twl6040_write(codec, TWL6040_REG_HSGAIN, 0xFF);
+                twl6040_write(codec, TWL6040_REG_EARCTL, 0x1E);
+                twl6040_write(codec, TWL6040_REG_HFLGAIN, 0x1D);
+                twl6040_write(codec, TWL6040_REG_HFRGAIN, 0x1D);
                 break;
         case SND_SOC_BIAS_OFF:
                 if (!priv->codec_powered)
@@ -740,7 +1328,7 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -770,27 +1358,9 @@ static int twl6040_startup(struct snd_pcm_substream *substream,
                         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
 
-        if (!priv->sysclk) {
-                dev_err(codec->dev,
-                        "no mclk configured, call set_sysclk() on init\n");
-                return -EINVAL;
-        }
-
-        /*
-         * capture is not supported at 17.64 MHz,
-         * it's reserved for headset low-power playback scenario
-         */
-        if ((priv->sysclk == 17640000) && substream->stream) {
-                dev_err(codec->dev,
-                        "capture mode is not supported at %dHz\n",
-                        priv->sysclk);
-                return -EINVAL;
-        }
-
         snd_pcm_hw_constraint_list(substream->runtime, 0,
                                 SNDRV_PCM_HW_PARAM_RATE,
                                 priv->sysclk_constraints);
@@ -803,8 +1373,7 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
                         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
         u8 lppllctl;
         int rate;
@@ -817,10 +1386,17 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
 
         rate = params_rate(params);
         switch (rate) {
+        case 11250:
+        case 22500:
+        case 44100:
         case 88200:
                 lppllctl |= TWL6040_LPLLFIN;
                 priv->sysclk = 17640000;
                 break;
+        case 8000:
+        case 16000:
+        case 32000:
+        case 48000:
         case 96000:
                 lppllctl &= ~TWL6040_LPLLFIN;
                 priv->sysclk = 19200000;
@@ -835,32 +1411,37 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
         return 0;
 }
 
-static int twl6040_trigger(struct snd_pcm_substream *substream,
-                        int cmd, struct snd_soc_dai *dai)
+static int twl6040_prepare(struct snd_pcm_substream *substream,
+                        struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
 
-        switch (cmd) {
-        case SNDRV_PCM_TRIGGER_START:
-        case SNDRV_PCM_TRIGGER_RESUME:
-                /*
-                 * low-power playback mode is restricted
-                 * for headset path only
-                 */
-                if ((priv->sysclk == 17640000) && priv->non_lp) {
+        if (!priv->sysclk) {
+                dev_err(codec->dev,
+                        "no mclk configured, call set_sysclk() on init\n");
+                return -EINVAL;
+        }
+
+        /*
+         * capture is not supported at 17.64 MHz,
+         * it's reserved for headset low-power playback scenario
+         */
+        if ((priv->sysclk == 17640000) &&
+                        substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+                dev_err(codec->dev,
+                        "capture mode is not supported at %dHz\n",
+                        priv->sysclk);
+                return -EINVAL;
+        }
+
+        if ((priv->sysclk == 17640000) && priv->non_lp) {
                         dev_err(codec->dev,
                                 "some enabled paths aren't supported at %dHz\n",
                                 priv->sysclk);
                         return -EPERM;
-                }
-                break;
-        default:
-                break;
         }
-
         return 0;
 }
 
@@ -974,12 +1555,12 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 static struct snd_soc_dai_ops twl6040_dai_ops = {
         .startup        = twl6040_startup,
         .hw_params      = twl6040_hw_params,
-        .trigger        = twl6040_trigger,
+        .prepare        = twl6040_prepare,
         .set_sysclk     = twl6040_set_dai_sysclk,
 };
 
-struct snd_soc_dai twl6040_dai = {
-        .name = "twl6040",
+static struct snd_soc_dai_driver twl6040_dai = {
+        .name = "twl6040-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -996,25 +1577,19 @@ struct snd_soc_dai twl6040_dai = {
         },
         .ops = &twl6040_dai_ops,
 };
-EXPORT_SYMBOL_GPL(twl6040_dai);
 
 #ifdef CONFIG_PM
-static int twl6040_suspend(struct platform_device *pdev, pm_message_t state)
+static int twl6040_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int twl6040_resume(struct platform_device *pdev)
+static int twl6040_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        twl6040_set_bias_level(codec, codec->dapm.suspend_bias_level);
 
         return 0;
 }
@@ -1023,111 +1598,49 @@ static int twl6040_resume(struct platform_device *pdev)
 #define twl6040_resume NULL
 #endif
 
-static struct snd_soc_codec *twl6040_codec;
-
-static int twl6040_probe(struct platform_device *pdev)
+static int twl6040_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        BUG_ON(!twl6040_codec);
-
-        codec = twl6040_codec;
-        socdev->card->codec = codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "failed to create pcms\n");
-                return ret;
-        }
-
-        snd_soc_add_controls(codec, twl6040_snd_controls,
-                                ARRAY_SIZE(twl6040_snd_controls));
-        twl6040_add_widgets(codec);
-
-        if (ret < 0) {
-                dev_err(&pdev->dev, "failed to register card\n");
-                goto card_err;
-        }
-
-        return ret;
-
-card_err:
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-        return ret;
-}
-
-static int twl6040_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-        kfree(codec);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_twl6040 = {
-        .probe = twl6040_probe,
-        .remove = twl6040_remove,
-        .suspend = twl6040_suspend,
-        .resume = twl6040_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_twl6040);
-
-static int __devinit twl6040_codec_probe(struct platform_device *pdev)
-{
-        struct twl4030_codec_data *twl_codec = pdev->dev.platform_data;
-        struct snd_soc_codec *codec;
+        struct twl4030_codec_data *twl_codec = codec->dev->platform_data;
         struct twl6040_data *priv;
         int audpwron, naudint;
         int ret = 0;
+        u8 icrev, intmr = TWL6040_ALLINT_MSK;
 
         priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL);
         if (priv == NULL)
                 return -ENOMEM;
+        snd_soc_codec_set_drvdata(codec, priv);
 
-        if (twl_codec) {
+        priv->codec = codec;
+
+        twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &icrev, TWL6040_REG_ASICREV);
+
+        if (twl_codec && (icrev > 0))
                 audpwron = twl_codec->audpwron_gpio;
-                naudint = twl_codec->naudint_irq;
-        } else {
+        else
                 audpwron = -EINVAL;
+
+        if (twl_codec)
+                naudint = twl_codec->naudint_irq;
+        else
                 naudint = 0;
-        }
 
         priv->audpwron = audpwron;
         priv->naudint = naudint;
+        priv->workqueue = create_singlethread_workqueue("twl6040-codec");
 
-        codec = &priv->codec;
-        codec->dev = &pdev->dev;
-        twl6040_dai.dev = &pdev->dev;
-
-        codec->name = "twl6040";
-        codec->owner = THIS_MODULE;
-        codec->read = twl6040_read_reg_cache;
-        codec->write = twl6040_write;
-        codec->set_bias_level = twl6040_set_bias_level;
-        snd_soc_codec_set_drvdata(codec, priv);
-        codec->dai = &twl6040_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(twl6040_reg);
-        codec->reg_cache = kmemdup(twl6040_reg, sizeof(twl6040_reg),
-                                        GFP_KERNEL);
-        if (codec->reg_cache == NULL) {
+        if (!priv->workqueue) {
                 ret = -ENOMEM;
-                goto cache_err;
+                goto work_err;
         }
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
+        INIT_DELAYED_WORK(&priv->delayed_work, twl6040_accessory_work);
+
+        mutex_init(&priv->mutex);
+
         init_completion(&priv->ready);
+        init_completion(&priv->headset.ramp_done);
+        init_completion(&priv->handsfree.ramp_done);
 
         if (gpio_is_valid(audpwron)) {
                 ret = gpio_request(audpwron, "audpwron");
@@ -1139,7 +1652,14 @@ static int __devinit twl6040_codec_probe(struct platform_device *pdev)
                         goto gpio2_err;
 
                 priv->codec_powered = 0;
+
+                /* enable only codec ready interrupt */
+                intmr &= ~(TWL6040_READYMSK | TWL6040_PLUGMSK);
+
+                /* reset interrupt status to allow correct power up sequence */
+                twl6040_read_reg_volatile(codec, TWL6040_REG_INTID);
         }
+        twl6040_write(codec, TWL6040_REG_INTMR, intmr);
 
         if (naudint) {
                 /* audio interrupt */
@@ -1149,43 +1669,40 @@ static int __devinit twl6040_codec_probe(struct platform_device *pdev)
                                 "twl6040_codec", codec);
                 if (ret)
                         goto gpio2_err;
-        } else {
-                if (gpio_is_valid(audpwron)) {
-                        /* enable only codec ready interrupt */
-                        twl6040_write_reg_cache(codec, TWL6040_REG_INTMR,
-                                        ~TWL6040_READYMSK & TWL6040_ALLINT_MSK);
-                } else {
-                        /* no interrupts at all */
-                        twl6040_write_reg_cache(codec, TWL6040_REG_INTMR,
-                                                TWL6040_ALLINT_MSK);
-                }
         }
 
         /* init vio registers */
         twl6040_init_vio_regs(codec);
 
-        /* power on device */
-        ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-        if (ret)
+        priv->hf_workqueue = create_singlethread_workqueue("twl6040-hf");
+        if (priv->hf_workqueue == NULL) {
+                ret = -ENOMEM;
                 goto irq_err;
+        }
+        priv->hs_workqueue = create_singlethread_workqueue("twl6040-hs");
+        if (priv->hs_workqueue == NULL) {
+                ret = -ENOMEM;
+                goto wq_err;
+        }
 
-        ret = snd_soc_register_codec(codec);
-        if (ret)
-                goto reg_err;
-
-        twl6040_codec = codec;
+        INIT_DELAYED_WORK(&priv->hs_delayed_work, twl6040_pga_hs_work);
+        INIT_DELAYED_WORK(&priv->hf_delayed_work, twl6040_pga_hf_work);
 
-        ret = snd_soc_register_dai(&twl6040_dai);
+        /* power on device */
+        ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         if (ret)
-                goto dai_err;
+                goto bias_err;
+
+        snd_soc_add_controls(codec, twl6040_snd_controls,
+                                ARRAY_SIZE(twl6040_snd_controls));
+        twl6040_add_widgets(codec);
 
         return 0;
 
-dai_err:
-        snd_soc_unregister_codec(codec);
-        twl6040_codec = NULL;
-reg_err:
-        twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
+bias_err:
+        destroy_workqueue(priv->hs_workqueue);
+wq_err:
+        destroy_workqueue(priv->hf_workqueue);
 irq_err:
         if (naudint)
                 free_irq(naudint, codec);
@@ -1193,36 +1710,62 @@ gpio2_err:
         if (gpio_is_valid(audpwron))
                 gpio_free(audpwron);
 gpio1_err:
-        kfree(codec->reg_cache);
-cache_err:
+        destroy_workqueue(priv->workqueue);
+work_err:
         kfree(priv);
         return ret;
 }
 
-static int __devexit twl6040_codec_remove(struct platform_device *pdev)
+static int twl6040_remove(struct snd_soc_codec *codec)
 {
-        struct twl6040_data *priv = snd_soc_codec_get_drvdata(twl6040_codec);
+        struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
         int audpwron = priv->audpwron;
         int naudint = priv->naudint;
 
+        twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
         if (gpio_is_valid(audpwron))
                 gpio_free(audpwron);
 
         if (naudint)
-                free_irq(naudint, twl6040_codec);
+                free_irq(naudint, codec);
+
+        destroy_workqueue(priv->workqueue);
+        destroy_workqueue(priv->hf_workqueue);
+        destroy_workqueue(priv->hs_workqueue);
+        kfree(priv);
+
+        return 0;
+}
 
-        snd_soc_unregister_dai(&twl6040_dai);
-        snd_soc_unregister_codec(twl6040_codec);
+static struct snd_soc_codec_driver soc_codec_dev_twl6040 = {
+        .probe = twl6040_probe,
+        .remove = twl6040_remove,
+        .suspend = twl6040_suspend,
+        .resume = twl6040_resume,
+        .read = twl6040_read_reg_cache,
+        .write = twl6040_write,
+        .set_bias_level = twl6040_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(twl6040_reg),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = twl6040_reg,
+};
 
-        kfree(twl6040_codec);
-        twl6040_codec = NULL;
+static int __devinit twl6040_codec_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_twl6040, &twl6040_dai, 1);
+}
 
+static int __devexit twl6040_codec_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
 static struct platform_driver twl6040_codec_driver = {
         .driver = {
-                .name = "twl6040_codec",
+                .name = "twl6040-codec",
                 .owner = THIS_MODULE,
         },
         .probe = twl6040_codec_probe,
diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h
index c472070a1da2..23aeed0963e6 100644
--- a/sound/soc/codecs/twl6040.h
+++ b/sound/soc/codecs/twl6040.h
@@ -79,6 +79,7 @@
 
 /* INTMR (0x04) fields */
 
+#define TWL6040_PLUGMSK                 0x02
 #define TWL6040_READYMSK                0x40
 #define TWL6040_ALLINT_MSK              0x7B
 
@@ -135,7 +136,11 @@
 #define TWL6040_HPPLL_ID                1
 #define TWL6040_LPPLL_ID                2
 
-extern struct snd_soc_dai twl6040_dai;
-extern struct snd_soc_codec_device soc_codec_dev_twl6040;
+/* STATUS (0x2E) fields */
+
+#define TWL6040_PLUGCOMP                0x02
+
+void twl6040_hs_jack_detect(struct snd_soc_codec *codec,
+                            struct snd_soc_jack *jack, int report);
 
 #endif /* End of __TWL6040_H__ */
diff --git a/sound/soc/codecs/uda134x.c b/sound/soc/codecs/uda134x.c
index f3b4c1d6a82d..a7b8f301bad3 100644
--- a/sound/soc/codecs/uda134x.c
+++ b/sound/soc/codecs/uda134x.c
@@ -19,7 +19,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 
 #include <sound/uda134x.h>
@@ -161,8 +160,7 @@ static int uda134x_startup(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec =rtd->codec;
         struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
         struct snd_pcm_runtime *master_runtime;
 
@@ -194,8 +192,7 @@ static void uda134x_shutdown(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
 
         if (uda134x->master_substream == substream)
@@ -209,8 +206,7 @@ static int uda134x_hw_params(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
         u8 hw_params;
 
@@ -364,7 +360,7 @@ static int uda134x_set_bias_level(struct snd_soc_codec *codec,
                         pd->power(1);
                         /* Sync reg_cache with the hardware */
                         for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
-                                codec->write(codec, i, *cache++);
+                                codec->driver->write(codec, i, *cache++);
                 }
                 break;
         case SND_SOC_BIAS_STANDBY:
@@ -392,7 +388,7 @@ static int uda134x_set_bias_level(struct snd_soc_codec *codec,
                         pd->power(0);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -465,8 +461,8 @@ static struct snd_soc_dai_ops uda134x_dai_ops = {
         .set_fmt        = uda134x_set_dai_fmt,
 };
 
-struct snd_soc_dai uda134x_dai = {
-        .name = "UDA134X",
+static struct snd_soc_dai_driver uda134x_dai = {
+        .name = "uda134x-hifi",
         /* playback capabilities */
         .playback = {
                 .stream_name = "Playback",
@@ -486,27 +482,22 @@ struct snd_soc_dai uda134x_dai = {
         /* pcm operations */
         .ops = &uda134x_dai_ops,
 };
-EXPORT_SYMBOL(uda134x_dai);
 
-
-static int uda134x_soc_probe(struct platform_device *pdev)
+static int uda134x_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
         struct uda134x_priv *uda134x;
-        void *codec_setup_data = socdev->codec_data;
-        int ret = -ENOMEM;
-        struct uda134x_platform_data *pd;
+        struct uda134x_platform_data *pd = codec->card->dev->platform_data;
+
+        int ret;
 
         printk(KERN_INFO "UDA134X SoC Audio Codec\n");
 
-        if (!codec_setup_data) {
+        if (!pd) {
                 printk(KERN_ERR "UDA134X SoC codec: "
                        "missing L3 bitbang function\n");
                 return -ENODEV;
         }
 
-        pd = codec_setup_data;
         switch (pd->model) {
         case UDA134X_UDA1340:
         case UDA134X_UDA1341:
@@ -520,58 +511,22 @@ static int uda134x_soc_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
-        socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (socdev->card->codec == NULL)
-                return ret;
-
-        codec = socdev->card->codec;
-
         uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
         if (uda134x == NULL)
-                goto priv_err;
+                return -ENOMEM;
         snd_soc_codec_set_drvdata(codec, uda134x);
 
-        codec->reg_cache = kmemdup(uda134x_reg, sizeof(uda134x_reg),
-                                   GFP_KERNEL);
-        if (codec->reg_cache == NULL)
-                goto reg_err;
-
-        mutex_init(&codec->mutex);
-
-        codec->reg_cache_size = sizeof(uda134x_reg);
-        codec->reg_cache_step = 1;
-
-        codec->name = "UDA134X";
-        codec->owner = THIS_MODULE;
-        codec->dai = &uda134x_dai;
-        codec->num_dai = 1;
-        codec->read = uda134x_read_reg_cache;
-        codec->write = uda134x_write;
-
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->control_data = codec_setup_data;
+        codec->control_data = pd;
 
         if (pd->power)
                 pd->power(1);
 
         uda134x_reset(codec);
 
-        if (pd->is_powered_on_standby) {
-                codec->set_bias_level = NULL;
+        if (pd->is_powered_on_standby)
                 uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
-        } else {
-                codec->set_bias_level = uda134x_set_bias_level;
+        else
                 uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-        }
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "UDA134X: failed to register pcms\n");
-                goto pcm_err;
-        }
 
         switch (pd->model) {
         case UDA134X_UDA1340:
@@ -590,61 +545,42 @@ static int uda134x_soc_probe(struct platform_device *pdev)
         default:
                 printk(KERN_ERR "%s unknown codec type: %d",
                         __func__, pd->model);
-        return -EINVAL;
+                kfree(uda134x);
+                return -EINVAL;
         }
 
         if (ret < 0) {
                 printk(KERN_ERR "UDA134X: failed to register controls\n");
-                goto pcm_err;
+                kfree(uda134x);
+                return ret;
         }
 
         return 0;
-
-pcm_err:
-        kfree(codec->reg_cache);
-reg_err:
-        kfree(snd_soc_codec_get_drvdata(codec));
-priv_err:
-        kfree(codec);
-        return ret;
 }
 
 /* power down chip */
-static int uda134x_soc_remove(struct platform_device *pdev)
+static int uda134x_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
 
         uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        kfree(snd_soc_codec_get_drvdata(codec));
-        kfree(codec->reg_cache);
-        kfree(codec);
-
+        kfree(uda134x);
         return 0;
 }
 
 #if defined(CONFIG_PM)
-static int uda134x_soc_suspend(struct platform_device *pdev,
+static int uda134x_soc_suspend(struct snd_soc_codec *codec,
                                                 pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int uda134x_soc_resume(struct platform_device *pdev)
+static int uda134x_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
         uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
         return 0;
@@ -654,25 +590,52 @@ static int uda134x_soc_resume(struct platform_device *pdev)
 #define uda134x_soc_resume NULL
 #endif /* CONFIG_PM */
 
-struct snd_soc_codec_device soc_codec_dev_uda134x = {
+static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
         .probe =        uda134x_soc_probe,
         .remove =       uda134x_soc_remove,
         .suspend =      uda134x_soc_suspend,
         .resume =       uda134x_soc_resume,
+        .reg_cache_size = sizeof(uda134x_reg),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = uda134x_reg,
+        .reg_cache_step = 1,
+        .read = uda134x_read_reg_cache,
+        .write = uda134x_write,
+        .set_bias_level = uda134x_set_bias_level,
+};
+
+static int __devinit uda134x_codec_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_uda134x, &uda134x_dai, 1);
+}
+
+static int __devexit uda134x_codec_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver uda134x_codec_driver = {
+        .driver = {
+                .name = "uda134x-codec",
+                .owner = THIS_MODULE,
+        },
+        .probe = uda134x_codec_probe,
+        .remove = __devexit_p(uda134x_codec_remove),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_uda134x);
 
-static int __init uda134x_init(void)
+static int __init uda134x_codec_init(void)
 {
-        return snd_soc_register_dai(&uda134x_dai);
+        return platform_driver_register(&uda134x_codec_driver);
 }
-module_init(uda134x_init);
+module_init(uda134x_codec_init);
 
-static void __exit uda134x_exit(void)
+static void __exit uda134x_codec_exit(void)
 {
-        snd_soc_unregister_dai(&uda134x_dai);
+        platform_driver_unregister(&uda134x_codec_driver);
 }
-module_exit(uda134x_exit);
+module_exit(uda134x_codec_exit);
 
 MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
 MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
diff --git a/sound/soc/codecs/uda134x.h b/sound/soc/codecs/uda134x.h
index 205f03b3eaf8..9faae06972b3 100644
--- a/sound/soc/codecs/uda134x.h
+++ b/sound/soc/codecs/uda134x.h
@@ -31,7 +31,4 @@
 #define STATUS0_DAIFMT_MASK (~(7<<1))
 #define STATUS0_SYSCLK_MASK (~(3<<4))
 
-extern struct snd_soc_dai uda134x_dai;
-extern struct snd_soc_codec_device soc_codec_dev_uda134x;
-
 #endif
diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c
index 2f925a27dcde..c5ca8cfea60f 100644
--- a/sound/soc/codecs/uda1380.c
+++ b/sound/soc/codecs/uda1380.c
@@ -27,20 +27,17 @@
 #include <sound/control.h>
 #include <sound/initval.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 #include <sound/uda1380.h>
 
 #include "uda1380.h"
 
-static struct snd_soc_codec *uda1380_codec;
-
 /* codec private data */
 struct uda1380_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[UDA1380_CACHEREGNUM];
+        struct snd_soc_codec *codec;
         unsigned int dac_clk;
         struct work_struct work;
+        void *control_data;
 };
 
 /*
@@ -131,10 +128,51 @@ static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
                 return -EIO;
 }
 
-#define uda1380_reset(c)        uda1380_write(c, UDA1380_RESET, 0)
+static void uda1380_sync_cache(struct snd_soc_codec *codec)
+{
+        int reg;
+        u8 data[3];
+        u16 *cache = codec->reg_cache;
+
+        /* Sync reg_cache with the hardware */
+        for (reg = 0; reg < UDA1380_MVOL; reg++) {
+                data[0] = reg;
+                data[1] = (cache[reg] & 0xff00) >> 8;
+                data[2] = cache[reg] & 0x00ff;
+                if (codec->hw_write(codec->control_data, data, 3) != 3)
+                        dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
+                                __func__, reg);
+        }
+}
+
+static int uda1380_reset(struct snd_soc_codec *codec)
+{
+        struct uda1380_platform_data *pdata = codec->dev->platform_data;
+
+        if (gpio_is_valid(pdata->gpio_reset)) {
+                gpio_set_value(pdata->gpio_reset, 1);
+                mdelay(1);
+                gpio_set_value(pdata->gpio_reset, 0);
+        } else {
+                u8 data[3];
+
+                data[0] = UDA1380_RESET;
+                data[1] = 0;
+                data[2] = 0;
+
+                if (codec->hw_write(codec->control_data, data, 3) != 3) {
+                        dev_err(codec->dev, "%s: failed\n", __func__);
+                        return -EIO;
+                }
+        }
+
+        return 0;
+}
 
 static void uda1380_flush_work(struct work_struct *work)
 {
+        struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
+        struct snd_soc_codec *uda1380_codec = uda1380->codec;
         int bit, reg;
 
         for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
@@ -145,6 +183,7 @@ static void uda1380_flush_work(struct work_struct *work)
                                 uda1380_read_reg_cache(uda1380_codec, reg));
                 clear_bit(bit, &uda1380_cache_dirty);
         }
+
 }
 
 /* declarations of ALSA reg_elem_REAL controls */
@@ -373,10 +412,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int uda1380_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets,
-                                  ARRAY_SIZE(uda1380_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, uda1380_dapm_widgets,
+                                  ARRAY_SIZE(uda1380_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -474,8 +514,7 @@ static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
         int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
 
@@ -501,8 +540,7 @@ static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
                                  struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
 
         /* set WSPLL power and divider if running from this clock */
@@ -540,8 +578,7 @@ static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
                                  struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
 
         /* shut down WSPLL power if running from this clock */
@@ -562,20 +599,43 @@ static int uda1380_set_bias_level(struct snd_soc_codec *codec,
         enum snd_soc_bias_level level)
 {
         int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
+        int reg;
+        struct uda1380_platform_data *pdata = codec->dev->platform_data;
+
+        if (codec->dapm.bias_level == level)
+                return 0;
 
         switch (level) {
         case SND_SOC_BIAS_ON:
         case SND_SOC_BIAS_PREPARE:
+                /* ADC, DAC on */
                 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
                 break;
         case SND_SOC_BIAS_STANDBY:
-                uda1380_write(codec, UDA1380_PM, R02_PON_BIAS);
-                break;
-        case SND_SOC_BIAS_OFF:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        if (gpio_is_valid(pdata->gpio_power)) {
+                                gpio_set_value(pdata->gpio_power, 1);
+                                mdelay(1);
+                                uda1380_reset(codec);
+                        }
+
+                        uda1380_sync_cache(codec);
+                }
                 uda1380_write(codec, UDA1380_PM, 0x0);
                 break;
+        case SND_SOC_BIAS_OFF:
+                if (!gpio_is_valid(pdata->gpio_power))
+                        break;
+
+                gpio_set_value(pdata->gpio_power, 0);
+
+                /* Mark mixer regs cache dirty to sync them with
+                 * codec regs on power on.
+                 */
+                for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
+                        set_bit(reg - 0x10, &uda1380_cache_dirty);
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -604,9 +664,9 @@ static struct snd_soc_dai_ops uda1380_dai_ops_capture = {
         .set_fmt        = uda1380_set_dai_fmt_capture,
 };
 
-struct snd_soc_dai uda1380_dai[] = {
+static struct snd_soc_dai_driver uda1380_dai[] = {
 {
-        .name = "UDA1380",
+        .name = "uda1380-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -622,7 +682,7 @@ struct snd_soc_dai uda1380_dai[] = {
         .ops = &uda1380_dai_ops,
 },
 { /* playback only - dual interface */
-        .name = "UDA1380",
+        .name = "uda1380-hifi-playback",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -633,7 +693,7 @@ struct snd_soc_dai uda1380_dai[] = {
         .ops = &uda1380_dai_ops_playback,
 },
 { /* capture only - dual interface*/
-        .name = "UDA1380",
+        .name = "uda1380-hifi-capture",
         .capture = {
                 .stream_name = "Capture",
                 .channels_min = 1,
@@ -644,67 +704,69 @@ struct snd_soc_dai uda1380_dai[] = {
         .ops = &uda1380_dai_ops_capture,
 },
 };
-EXPORT_SYMBOL_GPL(uda1380_dai);
 
-static int uda1380_suspend(struct platform_device *pdev, pm_message_t state)
+static int uda1380_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int uda1380_resume(struct platform_device *pdev)
+static int uda1380_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int i;
-        u8 data[2];
-        u16 *cache = codec->reg_cache;
-
-        /* Sync reg_cache with the hardware */
-        for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) {
-                data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
-                data[1] = cache[i] & 0x00ff;
-                codec->hw_write(codec->control_data, data, 2);
-        }
         uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         return 0;
 }
 
-static int uda1380_probe(struct platform_device *pdev)
+static int uda1380_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        struct uda1380_platform_data *pdata;
-        int ret = 0;
+        struct uda1380_platform_data *pdata =codec->dev->platform_data;
+        struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
+        int ret;
 
-        if (uda1380_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
+        uda1380->codec = codec;
+
+        codec->hw_write = (hw_write_t)i2c_master_send;
+        codec->control_data = uda1380->control_data;
 
-        socdev->card->codec = uda1380_codec;
-        codec = uda1380_codec;
-        pdata = codec->dev->platform_data;
+        if (!pdata)
+                return -EINVAL;
+
+        if (gpio_is_valid(pdata->gpio_reset)) {
+                ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
+                if (ret)
+                        goto err_out;
+                ret = gpio_direction_output(pdata->gpio_reset, 0);
+                if (ret)
+                        goto err_gpio_reset_conf;
+        }
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
+        if (gpio_is_valid(pdata->gpio_power)) {
+                ret = gpio_request(pdata->gpio_power, "uda1380 power");
+                if (ret)
+                        goto err_gpio;
+                ret = gpio_direction_output(pdata->gpio_power, 0);
+                if (ret)
+                        goto err_gpio_power_conf;
+        } else {
+                ret = uda1380_reset(codec);
+                if (ret) {
+                        dev_err(codec->dev, "Failed to issue reset\n");
+                        goto err_reset;
+                }
         }
 
+        INIT_WORK(&uda1380->work, uda1380_flush_work);
+
         /* power on device */
         uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         /* set clock input */
         switch (pdata->dac_clk) {
         case UDA1380_DAC_CLK_SYSCLK:
-                uda1380_write(codec, UDA1380_CLK, 0);
+                uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
                 break;
         case UDA1380_DAC_CLK_WSPLL:
-                uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK);
+                uda1380_write_reg_cache(codec, UDA1380_CLK,
+                        R00_DAC_CLK);
                 break;
         }
 
@@ -712,167 +774,73 @@ static int uda1380_probe(struct platform_device *pdev)
                                 ARRAY_SIZE(uda1380_snd_controls));
         uda1380_add_widgets(codec);
 
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-/* power down chip */
-static int uda1380_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec->control_data)
-                uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_uda1380 = {
-        .probe =        uda1380_probe,
-        .remove =       uda1380_remove,
-        .suspend =      uda1380_suspend,
-        .resume =       uda1380_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_uda1380);
-
-static int uda1380_register(struct uda1380_priv *uda1380)
-{
-        int ret, i;
-        struct snd_soc_codec *codec = &uda1380->codec;
-        struct uda1380_platform_data *pdata = codec->dev->platform_data;
-
-        if (uda1380_codec) {
-                dev_err(codec->dev, "Another UDA1380 is registered\n");
-                return -EINVAL;
-        }
-
-        if (!pdata || !pdata->gpio_power || !pdata->gpio_reset)
-                return -EINVAL;
-
-        ret = gpio_request(pdata->gpio_power, "uda1380 power");
-        if (ret)
-                goto err_out;
-        ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
-        if (ret)
-                goto err_gpio;
-
-        gpio_direction_output(pdata->gpio_power, 1);
-
-        /* we may need to have the clock running here - pH5 */
-        gpio_direction_output(pdata->gpio_reset, 1);
-        udelay(5);
-        gpio_set_value(pdata->gpio_reset, 0);
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, uda1380);
-        codec->name = "UDA1380";
-        codec->owner = THIS_MODULE;
-        codec->read = uda1380_read_reg_cache;
-        codec->write = uda1380_write;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = uda1380_set_bias_level;
-        codec->dai = uda1380_dai;
-        codec->num_dai = ARRAY_SIZE(uda1380_dai);
-        codec->reg_cache_size = ARRAY_SIZE(uda1380_reg);
-        codec->reg_cache = &uda1380->reg_cache;
-        codec->reg_cache_step = 1;
-
-        memcpy(codec->reg_cache, uda1380_reg, sizeof(uda1380_reg));
-
-        ret = uda1380_reset(codec);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to issue reset\n");
-                goto err_reset;
-        }
-
-        INIT_WORK(&uda1380->work, uda1380_flush_work);
-
-        for (i = 0; i < ARRAY_SIZE(uda1380_dai); i++)
-                uda1380_dai[i].dev = codec->dev;
-
-        uda1380_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err_reset;
-        }
-
-        ret = snd_soc_register_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
-                goto err_dai;
-        }
-
         return 0;
 
-err_dai:
-        snd_soc_unregister_codec(codec);
 err_reset:
-        gpio_set_value(pdata->gpio_power, 0);
-        gpio_free(pdata->gpio_reset);
+err_gpio_power_conf:
+        if (gpio_is_valid(pdata->gpio_power))
+                gpio_free(pdata->gpio_power);
+
+err_gpio_reset_conf:
 err_gpio:
-        gpio_free(pdata->gpio_power);
+        if (gpio_is_valid(pdata->gpio_reset))
+                gpio_free(pdata->gpio_reset);
 err_out:
         return ret;
 }
 
-static void uda1380_unregister(struct uda1380_priv *uda1380)
+/* power down chip */
+static int uda1380_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = &uda1380->codec;
-        struct uda1380_platform_data *pdata = codec->dev->platform_data;
+        struct uda1380_platform_data *pdata =codec->dev->platform_data;
 
-        snd_soc_unregister_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
-        snd_soc_unregister_codec(&uda1380->codec);
+        uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
-        gpio_set_value(pdata->gpio_power, 0);
         gpio_free(pdata->gpio_reset);
         gpio_free(pdata->gpio_power);
 
-        kfree(uda1380);
-        uda1380_codec = NULL;
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
+        .probe =        uda1380_probe,
+        .remove =       uda1380_remove,
+        .suspend =      uda1380_suspend,
+        .resume =       uda1380_resume,
+        .read =         uda1380_read_reg_cache,
+        .write =        uda1380_write,
+        .set_bias_level = uda1380_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(uda1380_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = uda1380_reg,
+        .reg_cache_step = 1,
+};
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct uda1380_priv *uda1380;
-        struct snd_soc_codec *codec;
         int ret;
 
         uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
         if (uda1380 == NULL)
                 return -ENOMEM;
 
-        codec = &uda1380->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
         i2c_set_clientdata(i2c, uda1380);
-        codec->control_data = i2c;
+        uda1380->control_data = i2c;
 
-        codec->dev = &i2c->dev;
-
-        ret = uda1380_register(uda1380);
-        if (ret != 0)
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
+        if (ret < 0)
                 kfree(uda1380);
-
         return ret;
 }
 
 static int __devexit uda1380_i2c_remove(struct i2c_client *i2c)
 {
-        struct uda1380_priv *uda1380 = i2c_get_clientdata(i2c);
-        uda1380_unregister(uda1380);
+        snd_soc_unregister_codec(&i2c->dev);
+        kfree(i2c_get_clientdata(i2c));
         return 0;
 }
 
@@ -884,7 +852,7 @@ MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
 
 static struct i2c_driver uda1380_i2c_driver = {
         .driver = {
-                .name =  "UDA1380 I2C Codec",
+                .name =  "uda1380-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    uda1380_i2c_probe,
diff --git a/sound/soc/codecs/uda1380.h b/sound/soc/codecs/uda1380.h
index 9cefa8a54770..942e3927c72b 100644
--- a/sound/soc/codecs/uda1380.h
+++ b/sound/soc/codecs/uda1380.h
@@ -76,7 +76,4 @@
 #define UDA1380_DAI_PLAYBACK    1 /* playback DAI */
 #define UDA1380_DAI_CAPTURE     2 /* capture DAI */
 
-extern struct snd_soc_dai uda1380_dai[3];
-extern struct snd_soc_codec_device soc_codec_dev_uda1380;
-
 #endif /* _UDA1380_H */
diff --git a/sound/soc/codecs/wl1273.c b/sound/soc/codecs/wl1273.c
new file mode 100644
index 000000000000..5836201834d9
--- /dev/null
+++ b/sound/soc/codecs/wl1273.c
@@ -0,0 +1,527 @@
+/*
+ * ALSA SoC WL1273 codec driver
+ *
+ * Author:      Matti Aaltonen, <matti.j.aaltonen@nokia.com>
+ *
+ * Copyright:   (C) 2010, 2011 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/mfd/wl1273-core.h>
+#include <linux/slab.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+
+#include "wl1273.h"
+
+enum wl1273_mode { WL1273_MODE_BT, WL1273_MODE_FM_RX, WL1273_MODE_FM_TX };
+
+/* codec private data */
+struct wl1273_priv {
+        enum wl1273_mode mode;
+        struct wl1273_core *core;
+        unsigned int channels;
+};
+
+static int snd_wl1273_fm_set_i2s_mode(struct wl1273_core *core,
+                                      int rate, int width)
+{
+        struct device *dev = &core->client->dev;
+        int r = 0;
+        u16 mode;
+
+        dev_dbg(dev, "rate: %d\n", rate);
+        dev_dbg(dev, "width: %d\n", width);
+
+        mutex_lock(&core->lock);
+
+        mode = core->i2s_mode & ~WL1273_IS2_WIDTH & ~WL1273_IS2_RATE;
+
+        switch (rate) {
+        case 48000:
+                mode |= WL1273_IS2_RATE_48K;
+                break;
+        case 44100:
+                mode |= WL1273_IS2_RATE_44_1K;
+                break;
+        case 32000:
+                mode |= WL1273_IS2_RATE_32K;
+                break;
+        case 22050:
+                mode |= WL1273_IS2_RATE_22_05K;
+                break;
+        case 16000:
+                mode |= WL1273_IS2_RATE_16K;
+                break;
+        case 12000:
+                mode |= WL1273_IS2_RATE_12K;
+                break;
+        case 11025:
+                mode |= WL1273_IS2_RATE_11_025;
+                break;
+        case 8000:
+                mode |= WL1273_IS2_RATE_8K;
+                break;
+        default:
+                dev_err(dev, "Sampling rate: %d not supported\n", rate);
+                r = -EINVAL;
+                goto out;
+        }
+
+        switch (width) {
+        case 16:
+                mode |= WL1273_IS2_WIDTH_32;
+                break;
+        case 20:
+                mode |= WL1273_IS2_WIDTH_40;
+                break;
+        case 24:
+                mode |= WL1273_IS2_WIDTH_48;
+                break;
+        case 25:
+                mode |= WL1273_IS2_WIDTH_50;
+                break;
+        case 30:
+                mode |= WL1273_IS2_WIDTH_60;
+                break;
+        case 32:
+                mode |= WL1273_IS2_WIDTH_64;
+                break;
+        case 40:
+                mode |= WL1273_IS2_WIDTH_80;
+                break;
+        case 48:
+                mode |= WL1273_IS2_WIDTH_96;
+                break;
+        case 64:
+                mode |= WL1273_IS2_WIDTH_128;
+                break;
+        default:
+                dev_err(dev, "Data width: %d not supported\n", width);
+                r = -EINVAL;
+                goto out;
+        }
+
+        dev_dbg(dev, "WL1273_I2S_DEF_MODE: 0x%04x\n",  WL1273_I2S_DEF_MODE);
+        dev_dbg(dev, "core->i2s_mode: 0x%04x\n", core->i2s_mode);
+        dev_dbg(dev, "mode: 0x%04x\n", mode);
+
+        if (core->i2s_mode != mode) {
+                r = core->write(core, WL1273_I2S_MODE_CONFIG_SET, mode);
+                if (r)
+                        goto out;
+
+                core->i2s_mode = mode;
+                r = core->write(core, WL1273_AUDIO_ENABLE,
+                                WL1273_AUDIO_ENABLE_I2S);
+                if (r)
+                        goto out;
+        }
+out:
+        mutex_unlock(&core->lock);
+
+        return r;
+}
+
+static int snd_wl1273_fm_set_channel_number(struct wl1273_core *core,
+                                            int channel_number)
+{
+        struct device *dev = &core->client->dev;
+        int r = 0;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        mutex_lock(&core->lock);
+
+        if (core->channel_number == channel_number)
+                goto out;
+
+        if (channel_number == 1 && core->mode == WL1273_MODE_RX)
+                r = core->write(core, WL1273_MOST_MODE_SET, WL1273_RX_MONO);
+        else if (channel_number == 1 && core->mode == WL1273_MODE_TX)
+                r = core->write(core, WL1273_MONO_SET, WL1273_TX_MONO);
+        else if (channel_number == 2 && core->mode == WL1273_MODE_RX)
+                r = core->write(core, WL1273_MOST_MODE_SET, WL1273_RX_STEREO);
+        else if (channel_number == 2 && core->mode == WL1273_MODE_TX)
+                r = core->write(core, WL1273_MONO_SET, WL1273_TX_STEREO);
+        else
+                r = -EINVAL;
+out:
+        mutex_unlock(&core->lock);
+
+        return r;
+}
+
+static int snd_wl1273_get_audio_route(struct snd_kcontrol *kcontrol,
+                                      struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = wl1273->mode;
+
+        return 0;
+}
+
+/*
+ * TODO: Implement the audio routing in the driver. Now this control
+ * only indicates the setting that has been done elsewhere (in the user
+ * space).
+ */
+static const char * const wl1273_audio_route[] = { "Bt", "FmRx", "FmTx" };
+
+static int snd_wl1273_set_audio_route(struct snd_kcontrol *kcontrol,
+                                      struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
+
+        if (wl1273->mode == ucontrol->value.integer.value[0])
+                return 0;
+
+        /* Do not allow changes while stream is running */
+        if (codec->active)
+                return -EPERM;
+
+        if (ucontrol->value.integer.value[0] < 0 ||
+            ucontrol->value.integer.value[0] >=  ARRAY_SIZE(wl1273_audio_route))
+                return -EINVAL;
+
+        wl1273->mode = ucontrol->value.integer.value[0];
+
+        return 1;
+}
+
+static const struct soc_enum wl1273_enum =
+        SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wl1273_audio_route), wl1273_audio_route);
+
+static int snd_wl1273_fm_audio_get(struct snd_kcontrol *kcontrol,
+                                   struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
+
+        dev_dbg(codec->dev, "%s: enter.\n", __func__);
+
+        ucontrol->value.integer.value[0] = wl1273->core->audio_mode;
+
+        return 0;
+}
+
+static int snd_wl1273_fm_audio_put(struct snd_kcontrol *kcontrol,
+                                   struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
+        int val, r = 0;
+
+        dev_dbg(codec->dev, "%s: enter.\n", __func__);
+
+        val = ucontrol->value.integer.value[0];
+        if (wl1273->core->audio_mode == val)
+                return 0;
+
+        r = wl1273->core->set_audio(wl1273->core, val);
+        if (r < 0)
+                return r;
+
+        return 1;
+}
+
+static const char * const wl1273_audio_strings[] = { "Digital", "Analog" };
+
+static const struct soc_enum wl1273_audio_enum =
+        SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wl1273_audio_strings),
+                            wl1273_audio_strings);
+
+static int snd_wl1273_fm_volume_get(struct snd_kcontrol *kcontrol,
+                                    struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
+
+        dev_dbg(codec->dev, "%s: enter.\n", __func__);
+
+        ucontrol->value.integer.value[0] = wl1273->core->volume;
+
+        return 0;
+}
+
+static int snd_wl1273_fm_volume_put(struct snd_kcontrol *kcontrol,
+                                    struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
+        int r;
+
+        dev_dbg(codec->dev, "%s: enter.\n", __func__);
+
+        r = wl1273->core->set_volume(wl1273->core,
+                                     ucontrol->value.integer.value[0]);
+        if (r)
+                return r;
+
+        return 1;
+}
+
+static const struct snd_kcontrol_new wl1273_controls[] = {
+        SOC_ENUM_EXT("Codec Mode", wl1273_enum,
+                     snd_wl1273_get_audio_route, snd_wl1273_set_audio_route),
+        SOC_ENUM_EXT("Audio Switch", wl1273_audio_enum,
+                     snd_wl1273_fm_audio_get,  snd_wl1273_fm_audio_put),
+        SOC_SINGLE_EXT("Volume", 0, 0, WL1273_MAX_VOLUME, 0,
+                       snd_wl1273_fm_volume_get, snd_wl1273_fm_volume_put),
+};
+
+static int wl1273_startup(struct snd_pcm_substream *substream,
+                          struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
+
+        switch (wl1273->mode) {
+        case WL1273_MODE_BT:
+                snd_pcm_hw_constraint_minmax(substream->runtime,
+                                             SNDRV_PCM_HW_PARAM_RATE,
+                                             8000, 8000);
+                snd_pcm_hw_constraint_minmax(substream->runtime,
+                                             SNDRV_PCM_HW_PARAM_CHANNELS, 1, 1);
+                break;
+        case WL1273_MODE_FM_RX:
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                        pr_err("Cannot play in RX mode.\n");
+                        return -EINVAL;
+                }
+                break;
+        case WL1273_MODE_FM_TX:
+                if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+                        pr_err("Cannot capture in TX mode.\n");
+                        return -EINVAL;
+                }
+                break;
+        default:
+                return -EINVAL;
+                break;
+        }
+
+        return 0;
+}
+
+static int wl1273_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(rtd->codec);
+        struct wl1273_core *core = wl1273->core;
+        unsigned int rate, width, r;
+
+        if (params_format(params) != SNDRV_PCM_FORMAT_S16_LE) {
+                pr_err("Only SNDRV_PCM_FORMAT_S16_LE supported.\n");
+                return -EINVAL;
+        }
+
+        rate = params_rate(params);
+        width =  hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
+
+        if (wl1273->mode == WL1273_MODE_BT) {
+                if (rate != 8000) {
+                        pr_err("Rate %d not supported.\n", params_rate(params));
+                        return -EINVAL;
+                }
+
+                if (params_channels(params) != 1) {
+                        pr_err("Only mono supported.\n");
+                        return -EINVAL;
+                }
+
+                return 0;
+        }
+
+        if (wl1273->mode == WL1273_MODE_FM_TX &&
+            substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+                pr_err("Only playback supported with TX.\n");
+                return -EINVAL;
+        }
+
+        if (wl1273->mode == WL1273_MODE_FM_RX  &&
+            substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                pr_err("Only capture supported with RX.\n");
+                return -EINVAL;
+        }
+
+        if (wl1273->mode != WL1273_MODE_FM_RX  &&
+            wl1273->mode != WL1273_MODE_FM_TX) {
+                pr_err("Unexpected mode: %d.\n", wl1273->mode);
+                return -EINVAL;
+        }
+
+        r = snd_wl1273_fm_set_i2s_mode(core, rate, width);
+        if (r)
+                return r;
+
+        wl1273->channels = params_channels(params);
+        r = snd_wl1273_fm_set_channel_number(core, wl1273->channels);
+        if (r)
+                return r;
+
+        return 0;
+}
+
+static struct snd_soc_dai_ops wl1273_dai_ops = {
+        .startup        = wl1273_startup,
+        .hw_params      = wl1273_hw_params,
+};
+
+static struct snd_soc_dai_driver wl1273_dai = {
+        .name = "wl1273-fm",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_48000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE},
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_48000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE},
+        .ops = &wl1273_dai_ops,
+};
+
+/* Audio interface format for the soc_card driver */
+int wl1273_get_format(struct snd_soc_codec *codec, unsigned int *fmt)
+{
+        struct wl1273_priv *wl1273;
+
+        if (codec == NULL || fmt == NULL)
+                return -EINVAL;
+
+        wl1273 = snd_soc_codec_get_drvdata(codec);
+
+        switch (wl1273->mode) {
+        case WL1273_MODE_FM_RX:
+        case WL1273_MODE_FM_TX:
+                *fmt =  SND_SOC_DAIFMT_I2S |
+                        SND_SOC_DAIFMT_NB_NF |
+                        SND_SOC_DAIFMT_CBM_CFM;
+
+                break;
+        case WL1273_MODE_BT:
+                *fmt =  SND_SOC_DAIFMT_DSP_A |
+                        SND_SOC_DAIFMT_IB_NF |
+                        SND_SOC_DAIFMT_CBM_CFM;
+
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(wl1273_get_format);
+
+static int wl1273_probe(struct snd_soc_codec *codec)
+{
+        struct wl1273_core **core = codec->dev->platform_data;
+        struct wl1273_priv *wl1273;
+        int r;
+
+        dev_dbg(codec->dev, "%s.\n", __func__);
+
+        if (!core) {
+                dev_err(codec->dev, "Platform data is missing.\n");
+                return -EINVAL;
+        }
+
+        wl1273 = kzalloc(sizeof(struct wl1273_priv), GFP_KERNEL);
+        if (wl1273 == NULL) {
+                dev_err(codec->dev, "Cannot allocate memory.\n");
+                return -ENOMEM;
+        }
+
+        wl1273->mode = WL1273_MODE_BT;
+        wl1273->core = *core;
+
+        snd_soc_codec_set_drvdata(codec, wl1273);
+        mutex_init(&codec->mutex);
+
+        r = snd_soc_add_controls(codec, wl1273_controls,
+                                 ARRAY_SIZE(wl1273_controls));
+        if (r)
+                kfree(wl1273);
+
+        return r;
+}
+
+static int wl1273_remove(struct snd_soc_codec *codec)
+{
+        struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
+
+        dev_dbg(codec->dev, "%s\n", __func__);
+        kfree(wl1273);
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_wl1273 = {
+        .probe = wl1273_probe,
+        .remove = wl1273_remove,
+};
+
+static int __devinit wl1273_platform_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wl1273,
+                                      &wl1273_dai, 1);
+}
+
+static int __devexit wl1273_platform_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+MODULE_ALIAS("platform:wl1273-codec");
+
+static struct platform_driver wl1273_platform_driver = {
+        .driver         = {
+                .name   = "wl1273-codec",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = wl1273_platform_probe,
+        .remove         = __devexit_p(wl1273_platform_remove),
+};
+
+static int __init wl1273_init(void)
+{
+        return platform_driver_register(&wl1273_platform_driver);
+}
+module_init(wl1273_init);
+
+static void __exit wl1273_exit(void)
+{
+        platform_driver_unregister(&wl1273_platform_driver);
+}
+module_exit(wl1273_exit);
+
+MODULE_AUTHOR("Matti Aaltonen <matti.j.aaltonen@nokia.com>");
+MODULE_DESCRIPTION("ASoC WL1273 codec driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wl1273.h b/sound/soc/codecs/wl1273.h
new file mode 100644
index 000000000000..43ec7e668c51
--- /dev/null
+++ b/sound/soc/codecs/wl1273.h
@@ -0,0 +1,30 @@
+/*
+ * sound/soc/codec/wl1273.h
+ *
+ * ALSA SoC WL1273 codec driver
+ *
+ * Copyright (C) Nokia Corporation
+ * Author: Matti Aaltonen <matti.j.aaltonen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __WL1273_CODEC_H__
+#define __WL1273_CODEC_H__
+
+int wl1273_get_format(struct snd_soc_codec *codec, unsigned int *fmt);
+
+#endif  /* End of __WL1273_CODEC_H__ */
diff --git a/sound/soc/codecs/wm1250-ev1.c b/sound/soc/codecs/wm1250-ev1.c
new file mode 100644
index 000000000000..bcc208967917
--- /dev/null
+++ b/sound/soc/codecs/wm1250-ev1.c
@@ -0,0 +1,108 @@
+/*
+ * Driver for the 1250-EV1 audio I/O module
+ *
+ * Copyright 2011 Wolfson Microelectronics plc
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+static const struct snd_soc_dapm_widget wm1250_ev1_dapm_widgets[] = {
+SND_SOC_DAPM_ADC("ADC", "wm1250-ev1 Capture", SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_DAC("DAC", "wm1250-ev1 Playback", SND_SOC_NOPM, 0, 0),
+
+SND_SOC_DAPM_INPUT("WM1250 Input"),
+SND_SOC_DAPM_OUTPUT("WM1250 Output"),
+};
+
+static const struct snd_soc_dapm_route wm1250_ev1_dapm_routes[] = {
+        { "ADC", NULL, "WM1250 Input" },
+        { "WM1250 Output", NULL, "DAC" },
+};
+
+static struct snd_soc_dai_driver wm1250_ev1_dai = {
+        .name = "wm1250-ev1",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = SNDRV_PCM_RATE_8000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 1,
+                .channels_max = 1,
+                .rates = SNDRV_PCM_RATE_8000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_wm1250_ev1 = {
+        .dapm_widgets = wm1250_ev1_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm1250_ev1_dapm_widgets),
+        .dapm_routes = wm1250_ev1_dapm_routes,
+        .num_dapm_routes = ARRAY_SIZE(wm1250_ev1_dapm_routes),
+};
+
+static int __devinit wm1250_ev1_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_wm1250_ev1,
+                                      &wm1250_ev1_dai, 1);
+}
+
+static int __devexit wm1250_ev1_remove(struct i2c_client *i2c)
+{
+        snd_soc_unregister_codec(&i2c->dev);
+
+        return 0;
+}
+
+static const struct i2c_device_id wm1250_ev1_i2c_id[] = {
+        { "wm1250-ev1", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm1250_ev1_i2c_id);
+
+static struct i2c_driver wm1250_ev1_i2c_driver = {
+        .driver = {
+                .name = "wm1250-ev1",
+                .owner = THIS_MODULE,
+        },
+        .probe =    wm1250_ev1_probe,
+        .remove =   __devexit_p(wm1250_ev1_remove),
+        .id_table = wm1250_ev1_i2c_id,
+};
+
+static int __init wm1250_ev1_modinit(void)
+{
+        int ret = 0;
+
+        ret = i2c_add_driver(&wm1250_ev1_i2c_driver);
+        if (ret != 0)
+                pr_err("Failed to register WM1250-EV1 I2C driver: %d\n", ret);
+
+        return ret;
+}
+module_init(wm1250_ev1_modinit);
+
+static void __exit wm1250_ev1_exit(void)
+{
+        i2c_del_driver(&wm1250_ev1_i2c_driver);
+}
+module_exit(wm1250_ev1_exit);
+
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_DESCRIPTION("WM1250-EV1 audio I/O module driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm2000.c b/sound/soc/codecs/wm2000.c
index 4bcd168794e1..a3b9cbb20ee9 100644
--- a/sound/soc/codecs/wm2000.c
+++ b/sound/soc/codecs/wm2000.c
@@ -36,7 +36,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
@@ -705,6 +704,7 @@ static const struct snd_soc_dapm_route audio_map[] = {
 /* Called from the machine driver */
 int wm2000_add_controls(struct snd_soc_codec *codec)
 {
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
         int ret;
 
         if (!wm2000_i2c) {
@@ -712,12 +712,12 @@ int wm2000_add_controls(struct snd_soc_codec *codec)
                 return -ENODEV;
         }
 
-        ret = snd_soc_dapm_new_controls(codec, wm2000_dapm_widgets,
+        ret = snd_soc_dapm_new_controls(dapm, wm2000_dapm_widgets,
                                         ARRAY_SIZE(wm2000_dapm_widgets));
         if (ret < 0)
                 return ret;
 
-        ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
         if (ret < 0)
                 return ret;
 
@@ -836,24 +836,25 @@ static void wm2000_i2c_shutdown(struct i2c_client *i2c)
 }
 
 #ifdef CONFIG_PM
-static int wm2000_i2c_suspend(struct i2c_client *i2c, pm_message_t mesg)
+static int wm2000_i2c_suspend(struct device *dev)
 {
+        struct i2c_client *i2c = to_i2c_client(dev);
         struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
 
         return wm2000_anc_transition(wm2000, ANC_OFF);
 }
 
-static int wm2000_i2c_resume(struct i2c_client *i2c)
+static int wm2000_i2c_resume(struct device *dev)
 {
+        struct i2c_client *i2c = to_i2c_client(dev);
         struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
 
         return wm2000_anc_set_mode(wm2000);
 }
-#else
-#define wm2000_i2c_suspend NULL
-#define wm2000_i2c_resume NULL
 #endif
 
+static SIMPLE_DEV_PM_OPS(wm2000_pm, wm2000_i2c_suspend, wm2000_i2c_resume);
+
 static const struct i2c_device_id wm2000_i2c_id[] = {
         { "wm2000", 0 },
         { }
@@ -864,11 +865,10 @@ static struct i2c_driver wm2000_i2c_driver = {
         .driver = {
                 .name = "wm2000",
                 .owner = THIS_MODULE,
+                .pm = &wm2000_pm,
         },
         .probe = wm2000_i2c_probe,
         .remove = __devexit_p(wm2000_i2c_remove),
-        .suspend = wm2000_i2c_suspend,
-        .resume = wm2000_i2c_resume,
         .shutdown = wm2000_i2c_shutdown,
         .id_table = wm2000_i2c_id,
 };
diff --git a/sound/soc/codecs/wm2000.h b/sound/soc/codecs/wm2000.h
index c18e261c3c7f..0b6f056f73cc 100644
--- a/sound/soc/codecs/wm2000.h
+++ b/sound/soc/codecs/wm2000.h
@@ -16,9 +16,6 @@ struct wm2000_setup_data {
 
 extern int wm2000_add_controls(struct snd_soc_codec *codec);
 
-extern struct snd_soc_dai wm2000_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm2000;
-
 #define WM2000_REG_SYS_START        0x8000
 #define WM2000_REG_SPEECH_CLARITY   0x8fef
 #define WM2000_REG_SYS_WATCHDOG     0x8ff6
diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index 0221ca79b3ae..6d6dc9efe914 100644
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -24,9 +24,9 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
+#include <trace/events/asoc.h>
 
 #include "wm8350.h"
 
@@ -54,6 +54,7 @@ struct wm8350_output {
 
 struct wm8350_jack_data {
         struct snd_soc_jack *jack;
+        struct delayed_work work;
         int report;
         int short_report;
 };
@@ -230,8 +231,9 @@ static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
  */
 static void wm8350_pga_work(struct work_struct *work)
 {
-        struct snd_soc_codec *codec =
-            container_of(work, struct snd_soc_codec, delayed_work.work);
+        struct snd_soc_dapm_context *dapm =
+            container_of(work, struct snd_soc_dapm_context, delayed_work.work);
+        struct snd_soc_codec *codec = dapm->codec;
         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
         struct wm8350_output *out1 = &wm8350_data->out1,
             *out2 = &wm8350_data->out2;
@@ -302,8 +304,8 @@ static int pga_event(struct snd_soc_dapm_widget *w,
                 out->ramp = WM8350_RAMP_UP;
                 out->active = 1;
 
-                if (!delayed_work_pending(&codec->delayed_work))
-                        schedule_delayed_work(&codec->delayed_work,
+                if (!delayed_work_pending(&codec->dapm.delayed_work))
+                        schedule_delayed_work(&codec->dapm.delayed_work,
                                               msecs_to_jiffies(1));
                 break;
 
@@ -311,8 +313,8 @@ static int pga_event(struct snd_soc_dapm_widget *w,
                 out->ramp = WM8350_RAMP_DOWN;
                 out->active = 0;
 
-                if (!delayed_work_pending(&codec->delayed_work))
-                        schedule_delayed_work(&codec->delayed_work,
+                if (!delayed_work_pending(&codec->dapm.delayed_work))
+                        schedule_delayed_work(&codec->dapm.delayed_work,
                                               msecs_to_jiffies(1));
                 break;
         }
@@ -786,9 +788,10 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8350_add_widgets(struct snd_soc_codec *codec)
 {
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
         int ret;
 
-        ret = snd_soc_dapm_new_controls(codec,
+        ret = snd_soc_dapm_new_controls(dapm,
                                         wm8350_dapm_widgets,
                                         ARRAY_SIZE(wm8350_dapm_widgets));
         if (ret != 0) {
@@ -797,7 +800,7 @@ static int wm8350_add_widgets(struct snd_soc_codec *codec)
         }
 
         /* set up audio paths */
-        ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
         if (ret != 0) {
                 dev_err(codec->dev, "DAPM route register failed\n");
                 return ret;
@@ -831,7 +834,7 @@ static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
         }
 
         /* MCLK direction */
-        if (dir == WM8350_MCLK_DIR_OUT)
+        if (dir == SND_SOC_CLOCK_OUT)
                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
                                 WM8350_MCLK_DIR);
         else
@@ -1184,7 +1187,7 @@ static int wm8350_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
                                                     priv->supplies);
                         if (ret != 0)
@@ -1317,68 +1320,86 @@ static int wm8350_set_bias_level(struct snd_soc_codec *codec,
                                        priv->supplies);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
-static int wm8350_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8350_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8350_resume(struct platform_device *pdev)
+static int wm8350_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
 }
 
-static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
+static void wm8350_hp_work(struct wm8350_data *priv,
+                           struct wm8350_jack_data *jack,
+                           u16 mask)
 {
-        struct wm8350_data *priv = data;
         struct wm8350 *wm8350 = priv->codec.control_data;
         u16 reg;
         int report;
-        int mask;
+
+        reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
+        if (reg & mask)
+                report = jack->report;
+        else
+                report = 0;
+
+        snd_soc_jack_report(jack->jack, report, jack->report);
+
+}
+
+static void wm8350_hpl_work(struct work_struct *work)
+{
+        struct wm8350_data *priv =
+            container_of(work, struct wm8350_data, hpl.work.work);
+
+        wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
+}
+
+static void wm8350_hpr_work(struct work_struct *work)
+{
+        struct wm8350_data *priv =
+            container_of(work, struct wm8350_data, hpr.work.work);
+        
+        wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
+}
+
+static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
+{
+        struct wm8350_data *priv = data;
+        struct wm8350 *wm8350 = priv->codec.control_data;
         struct wm8350_jack_data *jack = NULL;
 
         switch (irq - wm8350->irq_base) {
         case WM8350_IRQ_CODEC_JCK_DET_L:
+#ifndef CONFIG_SND_SOC_WM8350_MODULE
+                trace_snd_soc_jack_irq("WM8350 HPL");
+#endif
                 jack = &priv->hpl;
-                mask = WM8350_JACK_L_LVL;
                 break;
 
         case WM8350_IRQ_CODEC_JCK_DET_R:
+#ifndef CONFIG_SND_SOC_WM8350_MODULE
+                trace_snd_soc_jack_irq("WM8350 HPR");
+#endif
                 jack = &priv->hpr;
-                mask = WM8350_JACK_R_LVL;
                 break;
 
         default:
                 BUG();
         }
 
-        if (!jack->jack) {
-                dev_warn(wm8350->dev, "Jack interrupt called with no jack\n");
-                return IRQ_NONE;
-        }
-
-        /* Debounce */
-        msleep(200);
-
-        reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
-        if (reg & mask)
-                report = jack->report;
-        else
-                report = 0;
+        if (device_may_wakeup(wm8350->dev))
+                pm_wakeup_event(wm8350->dev, 250);
 
-        snd_soc_jack_report(jack->jack, report, jack->report);
+        schedule_delayed_work(&jack->work, 200);
 
         return IRQ_HANDLED;
 }
@@ -1442,6 +1463,10 @@ static irqreturn_t wm8350_mic_handler(int irq, void *data)
         u16 reg;
         int report = 0;
 
+#ifndef CONFIG_SND_SOC_WM8350_MODULE
+        trace_snd_soc_jack_irq("WM8350 mic");
+#endif
+
         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
         if (reg & WM8350_JACK_MICSCD_LVL)
                 report |= priv->mic.short_report;
@@ -1489,24 +1514,76 @@ int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
 }
 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
 
-static struct snd_soc_codec *wm8350_codec;
+#define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
+
+#define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+                        SNDRV_PCM_FMTBIT_S20_3LE |\
+                        SNDRV_PCM_FMTBIT_S24_LE)
+
+static struct snd_soc_dai_ops wm8350_dai_ops = {
+         .hw_params     = wm8350_pcm_hw_params,
+         .digital_mute  = wm8350_mute,
+         .trigger       = wm8350_pcm_trigger,
+         .set_fmt       = wm8350_set_dai_fmt,
+         .set_sysclk    = wm8350_set_dai_sysclk,
+         .set_pll       = wm8350_set_fll,
+         .set_clkdiv    = wm8350_set_clkdiv,
+};
+
+static struct snd_soc_dai_driver wm8350_dai = {
+        .name = "wm8350-hifi",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = WM8350_RATES,
+                .formats = WM8350_FORMATS,
+        },
+        .capture = {
+                 .stream_name = "Capture",
+                 .channels_min = 1,
+                 .channels_max = 2,
+                 .rates = WM8350_RATES,
+                 .formats = WM8350_FORMATS,
+         },
+        .ops = &wm8350_dai_ops,
+};
 
-static int wm8350_probe(struct platform_device *pdev)
+static  int wm8350_codec_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        struct wm8350 *wm8350;
+        struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
         struct wm8350_data *priv;
-        int ret;
         struct wm8350_output *out1;
         struct wm8350_output *out2;
+        int ret, i;
+
+        if (wm8350->codec.platform_data == NULL) {
+                dev_err(codec->dev, "No audio platform data supplied\n");
+                return -EINVAL;
+        }
+
+        priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL);
+        if (priv == NULL)
+                return -ENOMEM;
+        snd_soc_codec_set_drvdata(codec, priv);
 
-        BUG_ON(!wm8350_codec);
+        for (i = 0; i < ARRAY_SIZE(supply_names); i++)
+                priv->supplies[i].supply = supply_names[i];
 
-        socdev->card->codec = wm8350_codec;
-        codec = socdev->card->codec;
-        wm8350 = codec->control_data;
-        priv = snd_soc_codec_get_drvdata(codec);
+        ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
+                                 priv->supplies);
+        if (ret != 0)
+                goto err_priv;
+
+        wm8350->codec.codec = codec;
+        codec->control_data = wm8350;
+
+        /* Put the codec into reset if it wasn't already */
+        wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
+
+        INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
+        INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
+        INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
 
         /* Enable the codec */
         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
@@ -1542,6 +1619,13 @@ static int wm8350_probe(struct platform_device *pdev)
         wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
                         WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
 
+        /* Make sure AIF tristating is disabled by default */
+        wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
+
+        /* Make sure we've got a sane companding setup too */
+        wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
+                          WM8350_DAC_COMP | WM8350_LOOPBACK);
+
         /* Make sure jack detect is disabled to start off with */
         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
                           WM8350_JDL_ENA | WM8350_JDR_ENA);
@@ -1557,11 +1641,6 @@ static int wm8350_probe(struct platform_device *pdev)
         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
                             wm8350_mic_handler, 0, "Microphone detect", priv);
 
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "failed to create pcms\n");
-                return ret;
-        }
 
         snd_soc_add_controls(codec, wm8350_snd_controls,
                                 ARRAY_SIZE(wm8350_snd_controls));
@@ -1570,15 +1649,16 @@ static int wm8350_probe(struct platform_device *pdev)
         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
+
+err_priv:
+        kfree(priv);
+        return ret;
 }
 
-static int wm8350_remove(struct platform_device *pdev)
+static int  wm8350_codec_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-        struct wm8350 *wm8350 = codec->control_data;
         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
-        int ret;
+        struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
 
         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
                           WM8350_JDL_ENA | WM8350_JDR_ENA);
@@ -1593,148 +1673,41 @@ static int wm8350_remove(struct platform_device *pdev)
         priv->hpr.jack = NULL;
         priv->mic.jack = NULL;
 
-        /* cancel any work waiting to be queued. */
-        ret = cancel_delayed_work(&codec->delayed_work);
+        cancel_delayed_work_sync(&priv->hpl.work);
+        cancel_delayed_work_sync(&priv->hpr.work);
 
         /* if there was any work waiting then we run it now and
          * wait for its completion */
-        if (ret) {
-                schedule_delayed_work(&codec->delayed_work, 0);
-                flush_scheduled_work();
-        }
+        flush_delayed_work_sync(&codec->dapm.delayed_work);
 
         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
 
+        regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
+        kfree(priv);
         return 0;
 }
 
-#define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
-
-#define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-                        SNDRV_PCM_FMTBIT_S20_3LE |\
-                        SNDRV_PCM_FMTBIT_S24_LE)
-
-static struct snd_soc_dai_ops wm8350_dai_ops = {
-         .hw_params     = wm8350_pcm_hw_params,
-         .digital_mute  = wm8350_mute,
-         .trigger       = wm8350_pcm_trigger,
-         .set_fmt       = wm8350_set_dai_fmt,
-         .set_sysclk    = wm8350_set_dai_sysclk,
-         .set_pll       = wm8350_set_fll,
-         .set_clkdiv    = wm8350_set_clkdiv,
-};
-
-struct snd_soc_dai wm8350_dai = {
-        .name = "WM8350",
-        .playback = {
-                .stream_name = "Playback",
-                .channels_min = 1,
-                .channels_max = 2,
-                .rates = WM8350_RATES,
-                .formats = WM8350_FORMATS,
-        },
-        .capture = {
-                 .stream_name = "Capture",
-                 .channels_min = 1,
-                 .channels_max = 2,
-                 .rates = WM8350_RATES,
-                 .formats = WM8350_FORMATS,
-         },
-        .ops = &wm8350_dai_ops,
-};
-EXPORT_SYMBOL_GPL(wm8350_dai);
-
-struct snd_soc_codec_device soc_codec_dev_wm8350 = {
-        .probe =        wm8350_probe,
-        .remove =       wm8350_remove,
+static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
+        .probe =        wm8350_codec_probe,
+        .remove =       wm8350_codec_remove,
         .suspend =      wm8350_suspend,
         .resume =       wm8350_resume,
+        .read = wm8350_codec_read,
+        .write = wm8350_codec_write,
+        .set_bias_level = wm8350_set_bias_level,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8350);
 
-static __devinit int wm8350_codec_probe(struct platform_device *pdev)
+static int __devinit wm8350_probe(struct platform_device *pdev)
 {
-        struct wm8350 *wm8350 = platform_get_drvdata(pdev);
-        struct wm8350_data *priv;
-        struct snd_soc_codec *codec;
-        int ret, i;
-
-        if (wm8350->codec.platform_data == NULL) {
-                dev_err(&pdev->dev, "No audio platform data supplied\n");
-                return -EINVAL;
-        }
-
-        priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL);
-        if (priv == NULL)
-                return -ENOMEM;
-
-        for (i = 0; i < ARRAY_SIZE(supply_names); i++)
-                priv->supplies[i].supply = supply_names[i];
-
-        ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
-                                 priv->supplies);
-        if (ret != 0)
-                goto err_priv;
-
-        codec = &priv->codec;
-        wm8350->codec.codec = codec;
-
-        wm8350_dai.dev = &pdev->dev;
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-        codec->dev = &pdev->dev;
-        codec->name = "WM8350";
-        codec->owner = THIS_MODULE;
-        codec->read = wm8350_codec_read;
-        codec->write = wm8350_codec_write;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8350_set_bias_level;
-        codec->dai = &wm8350_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8350_MAX_REGISTER;
-        snd_soc_codec_set_drvdata(codec, priv);
-        codec->control_data = wm8350;
-
-        /* Put the codec into reset if it wasn't already */
-        wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
-
-        INIT_DELAYED_WORK(&codec->delayed_work, wm8350_pga_work);
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0)
-                goto err_supply;
-
-        wm8350_codec = codec;
-
-        ret = snd_soc_register_dai(&wm8350_dai);
-        if (ret != 0)
-                goto err_codec;
-        return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err_supply:
-        regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
-err_priv:
-        kfree(priv);
-        wm8350_codec = NULL;
-        return ret;
+        return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
+                        &wm8350_dai, 1);
 }
 
-static int __devexit wm8350_codec_remove(struct platform_device *pdev)
+static int __devexit wm8350_remove(struct platform_device *pdev)
 {
-        struct wm8350 *wm8350 = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = wm8350->codec.codec;
-        struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
-
-        snd_soc_unregister_dai(&wm8350_dai);
-        snd_soc_unregister_codec(codec);
-        regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
-        kfree(priv);
-        wm8350_codec = NULL;
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
@@ -1743,8 +1716,8 @@ static struct platform_driver wm8350_codec_driver = {
                    .name = "wm8350-codec",
                    .owner = THIS_MODULE,
                    },
-        .probe = wm8350_codec_probe,
-        .remove = __devexit_p(wm8350_codec_remove),
+        .probe = wm8350_probe,
+        .remove = __devexit_p(wm8350_remove),
 };
 
 static __init int wm8350_init(void)
diff --git a/sound/soc/codecs/wm8350.h b/sound/soc/codecs/wm8350.h
index 9ed0467c71db..74108eb82938 100644
--- a/sound/soc/codecs/wm8350.h
+++ b/sound/soc/codecs/wm8350.h
@@ -15,9 +15,6 @@
 #include <sound/soc.h>
 #include <linux/mfd/wm8350/audio.h>
 
-extern struct snd_soc_dai wm8350_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8350;
-
 enum wm8350_jack {
         WM8350_JDL = 1,
         WM8350_JDR = 2,
diff --git a/sound/soc/codecs/wm8400.c b/sound/soc/codecs/wm8400.c
index 8f294066b0ed..fbee556cbf35 100644
--- a/sound/soc/codecs/wm8400.c
+++ b/sound/soc/codecs/wm8400.c
@@ -22,11 +22,11 @@
 #include <linux/regulator/consumer.h>
 #include <linux/mfd/wm8400-audio.h>
 #include <linux/mfd/wm8400-private.h>
+#include <linux/mfd/core.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
@@ -65,7 +65,7 @@ static struct regulator_bulk_data power[] = {
 
 /* codec private data */
 struct wm8400_priv {
-        struct snd_soc_codec codec;
+        struct snd_soc_codec *codec;
         struct wm8400 *wm8400;
         u16 fake_register;
         unsigned int sysclk;
@@ -911,10 +911,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8400_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8400_dapm_widgets,
-                                  ARRAY_SIZE(wm8400_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, wm8400_dapm_widgets,
+                                  ARRAY_SIZE(wm8400_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -1163,8 +1164,7 @@ static int wm8400_hw_params(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1);
 
         audio1 &= ~WM8400_AIF_WL_MASK;
@@ -1220,7 +1220,7 @@ static int wm8400_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         ret = regulator_bulk_enable(ARRAY_SIZE(power),
                                                     &power[0]);
                         if (ret != 0) {
@@ -1307,7 +1307,7 @@ static int wm8400_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -1332,10 +1332,9 @@ static struct snd_soc_dai_ops wm8400_dai_ops = {
  * 1. ADC/DAC on Primary Interface
  * 2. ADC on Primary Interface/DAC on secondary
  */
-struct snd_soc_dai wm8400_dai = {
+static struct snd_soc_dai_driver wm8400_dai = {
 /* ADC/DAC on primary */
-        .name = "WM8400 ADC/DAC Primary",
-        .id = 1,
+        .name = "wm8400-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -1352,147 +1351,53 @@ struct snd_soc_dai wm8400_dai = {
         },
         .ops = &wm8400_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8400_dai);
 
-static int wm8400_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8400_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm8400_resume(struct platform_device *pdev)
+static int wm8400_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
 }
 
-static struct snd_soc_codec *wm8400_codec;
-
-static int wm8400_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret;
-
-        if (!wm8400_codec) {
-                dev_err(&pdev->dev, "wm8400 not yet discovered\n");
-                return -ENODEV;
-        }
-        codec = wm8400_codec;
-
-        socdev->card->codec = codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "failed to create pcms\n");
-                goto pcm_err;
-        }
-
-        wm8400_add_controls(codec);
-        wm8400_add_widgets(codec);
-
-pcm_err:
-        return ret;
-}
-
-/* power down chip */
-static int wm8400_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8400 = {
-        .probe =        wm8400_probe,
-        .remove =       wm8400_remove,
-        .suspend =      wm8400_suspend,
-        .resume =       wm8400_resume,
-};
-
 static void wm8400_probe_deferred(struct work_struct *work)
 {
         struct wm8400_priv *priv = container_of(work, struct wm8400_priv,
                                                 work);
-        struct snd_soc_codec *codec = &priv->codec;
-        int ret;
+        struct snd_soc_codec *codec = priv->codec;
 
         /* charge output caps */
         wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-
-        /* We're done, tell the subsystem. */
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(priv->wm8400->dev,
-                        "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&wm8400_dai);
-        if (ret != 0) {
-                dev_err(priv->wm8400->dev,
-                        "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
-
-        return;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF);
 }
 
-static int wm8400_codec_probe(struct platform_device *dev)
+static int wm8400_codec_probe(struct snd_soc_codec *codec)
 {
+        struct wm8400 *wm8400 = dev_get_platdata(codec->dev);
         struct wm8400_priv *priv;
         int ret;
         u16 reg;
-        struct snd_soc_codec *codec;
 
         priv = kzalloc(sizeof(struct wm8400_priv), GFP_KERNEL);
         if (priv == NULL)
                 return -ENOMEM;
 
-        codec = &priv->codec;
         snd_soc_codec_set_drvdata(codec, priv);
-        codec->control_data = dev_get_drvdata(&dev->dev);
-        priv->wm8400 = dev_get_drvdata(&dev->dev);
+        codec->control_data = priv->wm8400 = wm8400;
+        priv->codec = codec;
 
-        ret = regulator_bulk_get(priv->wm8400->dev,
+        ret = regulator_bulk_get(wm8400->dev,
                                  ARRAY_SIZE(power), &power[0]);
         if (ret != 0) {
-                dev_err(&dev->dev, "Failed to get regulators: %d\n", ret);
+                dev_err(codec->dev, "Failed to get regulators: %d\n", ret);
                 goto err;
         }
 
-        codec->dev = &dev->dev;
-        wm8400_dai.dev = &dev->dev;
-
-        codec->name = "WM8400";
-        codec->owner = THIS_MODULE;
-        codec->read = wm8400_read;
-        codec->write = wm8400_write;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8400_set_bias_level;
-        codec->dai = &wm8400_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8400_REGISTER_COUNT;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
         INIT_WORK(&priv->work, wm8400_probe_deferred);
 
         wm8400_codec_reset(codec);
@@ -1511,65 +1416,78 @@ static int wm8400_codec_probe(struct platform_device *dev)
         wm8400_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
         wm8400_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
 
-        wm8400_codec = codec;
-
         if (!schedule_work(&priv->work)) {
                 ret = -EINVAL;
                 goto err_regulator;
         }
-
+        wm8400_add_controls(codec);
+        wm8400_add_widgets(codec);
         return 0;
 
 err_regulator:
-        wm8400_codec = NULL;
         regulator_bulk_free(ARRAY_SIZE(power), power);
 err:
         kfree(priv);
         return ret;
 }
 
-static int __exit wm8400_codec_remove(struct platform_device *dev)
+static int  wm8400_codec_remove(struct snd_soc_codec *codec)
 {
-        struct wm8400_priv *priv = snd_soc_codec_get_drvdata(wm8400_codec);
+        struct wm8400_priv *priv = snd_soc_codec_get_drvdata(codec);
         u16 reg;
 
-        snd_soc_unregister_dai(&wm8400_dai);
-        snd_soc_unregister_codec(wm8400_codec);
-
-        reg = wm8400_read(wm8400_codec, WM8400_POWER_MANAGEMENT_1);
-        wm8400_write(wm8400_codec, WM8400_POWER_MANAGEMENT_1,
+        reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1);
+        wm8400_write(codec, WM8400_POWER_MANAGEMENT_1,
                      reg & (~WM8400_CODEC_ENA));
 
         regulator_bulk_free(ARRAY_SIZE(power), power);
         kfree(priv);
 
-        wm8400_codec = NULL;
+        return 0;
+}
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
+        .probe =        wm8400_codec_probe,
+        .remove =       wm8400_codec_remove,
+        .suspend =      wm8400_suspend,
+        .resume =       wm8400_resume,
+        .read = wm8400_read,
+        .write = wm8400_write,
+        .set_bias_level = wm8400_set_bias_level,
+};
+
+static int __devinit wm8400_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400,
+                        &wm8400_dai, 1);
+}
+
+static int __devexit wm8400_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
 static struct platform_driver wm8400_codec_driver = {
         .driver = {
-                .name = "wm8400-codec",
-                .owner = THIS_MODULE,
-        },
-        .probe = wm8400_codec_probe,
-        .remove = __exit_p(wm8400_codec_remove),
+                   .name = "wm8400-codec",
+                   .owner = THIS_MODULE,
+                   },
+        .probe = wm8400_probe,
+        .remove = __devexit_p(wm8400_remove),
 };
 
-static int __init wm8400_codec_init(void)
+static __init int wm8400_init(void)
 {
         return platform_driver_register(&wm8400_codec_driver);
 }
-module_init(wm8400_codec_init);
+module_init(wm8400_init);
 
-static void __exit wm8400_codec_exit(void)
+static __exit void wm8400_exit(void)
 {
         platform_driver_unregister(&wm8400_codec_driver);
 }
-module_exit(wm8400_codec_exit);
-
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8400);
+module_exit(wm8400_exit);
 
 MODULE_DESCRIPTION("ASoC WM8400 driver");
 MODULE_AUTHOR("Mark Brown");
diff --git a/sound/soc/codecs/wm8400.h b/sound/soc/codecs/wm8400.h
index 79c5934d4776..521adb193870 100644
--- a/sound/soc/codecs/wm8400.h
+++ b/sound/soc/codecs/wm8400.h
@@ -56,7 +56,4 @@
 #define WM8400_BCLK_DIV_44                      (0xE << 1)
 #define WM8400_BCLK_DIV_48                      (0xF << 1)
 
-extern struct snd_soc_dai wm8400_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8400;
-
 #endif
diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c
index 0f7bcb61071a..db0dced74843 100644
--- a/sound/soc/codecs/wm8510.c
+++ b/sound/soc/codecs/wm8510.c
@@ -24,15 +24,10 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 
 #include "wm8510.h"
 
-#define WM8510_VERSION "0.6"
-
-struct snd_soc_codec_device soc_codec_dev_wm8510;
-
 /*
  * wm8510 register cache
  * We can't read the WM8510 register space when we are
@@ -61,6 +56,11 @@ static const u16 wm8510_reg[WM8510_CACHEREGNUM] = {
 
 #define wm8510_reset(c) snd_soc_write(c, WM8510_RESET, 0)
 
+/* codec private data */
+struct wm8510_priv {
+        enum snd_soc_control_type control_type;
+};
+
 static const char *wm8510_companding[] = { "Off", "NC", "u-law", "A-law" };
 static const char *wm8510_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
 static const char *wm8510_alc[] = { "ALC", "Limiter" };
@@ -215,10 +215,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8510_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8510_dapm_widgets,
-                                  ARRAY_SIZE(wm8510_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, wm8510_dapm_widgets,
+                                  ARRAY_SIZE(wm8510_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -403,8 +404,7 @@ static int wm8510_pcm_hw_params(struct snd_pcm_substream *substream,
                                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 iface = snd_soc_read(codec, WM8510_IFACE) & 0x19f;
         u16 adn = snd_soc_read(codec, WM8510_ADD) & 0x1f1;
 
@@ -478,7 +478,7 @@ static int wm8510_set_bias_level(struct snd_soc_codec *codec,
         case SND_SOC_BIAS_STANDBY:
                 power1 |= WM8510_POWER1_BIASEN | WM8510_POWER1_BUFIOEN;
 
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Initial cap charge at VMID 5k */
                         snd_soc_write(codec, WM8510_POWER1, power1 | 0x3);
                         mdelay(100);
@@ -495,7 +495,7 @@ static int wm8510_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -514,8 +514,8 @@ static struct snd_soc_dai_ops wm8510_dai_ops = {
         .set_pll        = wm8510_set_dai_pll,
 };
 
-struct snd_soc_dai wm8510_dai = {
-        .name = "WM8510 HiFi",
+static struct snd_soc_dai_driver wm8510_dai = {
+        .name = "wm8510-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -531,21 +531,15 @@ struct snd_soc_dai wm8510_dai = {
         .ops = &wm8510_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8510_dai);
 
-static int wm8510_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8510_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8510_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8510_resume(struct platform_device *pdev)
+static int wm8510_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -561,256 +555,158 @@ static int wm8510_resume(struct platform_device *pdev)
         return 0;
 }
 
-/*
- * initialise the WM8510 driver
- * register the mixer and dsp interfaces with the kernel
- */
-static int wm8510_init(struct snd_soc_device *socdev,
-                       enum snd_soc_control_type control)
+static int wm8510_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int ret = 0;
-
-        codec->name = "WM8510";
-        codec->owner = THIS_MODULE;
-        codec->set_bias_level = wm8510_set_bias_level;
-        codec->dai = &wm8510_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(wm8510_reg);
-        codec->reg_cache = kmemdup(wm8510_reg, sizeof(wm8510_reg), GFP_KERNEL);
-
-        if (codec->reg_cache == NULL)
-                return -ENOMEM;
+        struct wm8510_priv *wm8510 = snd_soc_codec_get_drvdata(codec);
+        int ret;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9,  wm8510->control_type);
         if (ret < 0) {
-                printk(KERN_ERR "wm8510: failed to set cache I/O: %d\n",
-                       ret);
-                goto err;
+                printk(KERN_ERR "wm8510: failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
         wm8510_reset(codec);
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "wm8510: failed to create pcms\n");
-                goto err;
-        }
-
         /* power on device */
-        codec->bias_level = SND_SOC_BIAS_OFF;
         wm8510_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         snd_soc_add_controls(codec, wm8510_snd_controls,
                                 ARRAY_SIZE(wm8510_snd_controls));
         wm8510_add_widgets(codec);
 
         return ret;
-
-err:
-        kfree(codec->reg_cache);
-        return ret;
 }
 
-static struct snd_soc_device *wm8510_socdev;
+/* power down chip */
+static int wm8510_remove(struct snd_soc_codec *codec)
+{
+        struct wm8510_priv *wm8510 = snd_soc_codec_get_drvdata(codec);
 
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        wm8510_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        kfree(wm8510);
+        return 0;
+}
 
-/*
- * WM8510 2 wire address is 0x1a
- */
+static struct snd_soc_codec_driver soc_codec_dev_wm8510 = {
+        .probe =        wm8510_probe,
+        .remove =       wm8510_remove,
+        .suspend =      wm8510_suspend,
+        .resume =       wm8510_resume,
+        .set_bias_level = wm8510_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8510_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default =wm8510_reg,
+};
 
-static int wm8510_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8510_spi_probe(struct spi_device *spi)
 {
-        struct snd_soc_device *socdev = wm8510_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct wm8510_priv *wm8510;
         int ret;
 
-        i2c_set_clientdata(i2c, codec);
-        codec->control_data = i2c;
+        wm8510 = kzalloc(sizeof(struct wm8510_priv), GFP_KERNEL);
+        if (wm8510 == NULL)
+                return -ENOMEM;
+
+        wm8510->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8510);
 
-        ret = wm8510_init(socdev, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8510, &wm8510_dai, 1);
         if (ret < 0)
-                pr_err("failed to initialise WM8510\n");
-
+                kfree(wm8510);
         return ret;
 }
 
-static int wm8510_i2c_remove(struct i2c_client *client)
+static int __devexit wm8510_spi_remove(struct spi_device *spi)
 {
-        struct snd_soc_codec *codec = i2c_get_clientdata(client);
-        kfree(codec->reg_cache);
+        snd_soc_unregister_codec(&spi->dev);
         return 0;
 }
 
-static const struct i2c_device_id wm8510_i2c_id[] = {
-        { "wm8510", 0 },
-        { }
-};
-MODULE_DEVICE_TABLE(i2c, wm8510_i2c_id);
-
-static struct i2c_driver wm8510_i2c_driver = {
+static struct spi_driver wm8510_spi_driver = {
         .driver = {
-                .name = "WM8510 I2C Codec",
-                .owner = THIS_MODULE,
+                .name   = "wm8510",
+                .owner  = THIS_MODULE,
         },
-        .probe =    wm8510_i2c_probe,
-        .remove =   wm8510_i2c_remove,
-        .id_table = wm8510_i2c_id,
+        .probe          = wm8510_spi_probe,
+        .remove         = __devexit_p(wm8510_spi_remove),
 };
+#endif /* CONFIG_SPI_MASTER */
 
-static int wm8510_add_i2c_device(struct platform_device *pdev,
-                                 const struct wm8510_setup_data *setup)
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8510_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
-        struct i2c_board_info info;
-        struct i2c_adapter *adapter;
-        struct i2c_client *client;
+        struct wm8510_priv *wm8510;
         int ret;
 
-        ret = i2c_add_driver(&wm8510_i2c_driver);
-        if (ret != 0) {
-                dev_err(&pdev->dev, "can't add i2c driver\n");
-                return ret;
-        }
-
-        memset(&info, 0, sizeof(struct i2c_board_info));
-        info.addr = setup->i2c_address;
-        strlcpy(info.type, "wm8510", I2C_NAME_SIZE);
-
-        adapter = i2c_get_adapter(setup->i2c_bus);
-        if (!adapter) {
-                dev_err(&pdev->dev, "can't get i2c adapter %d\n",
-                        setup->i2c_bus);
-                goto err_driver;
-        }
-
-        client = i2c_new_device(adapter, &info);
-        i2c_put_adapter(adapter);
-        if (!client) {
-                dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
-                        (unsigned int)info.addr);
-                goto err_driver;
-        }
-
-        return 0;
-
-err_driver:
-        i2c_del_driver(&wm8510_i2c_driver);
-        return -ENODEV;
-}
-#endif
-
-#if defined(CONFIG_SPI_MASTER)
-static int __devinit wm8510_spi_probe(struct spi_device *spi)
-{
-        struct snd_soc_device *socdev = wm8510_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int ret;
+        wm8510 = kzalloc(sizeof(struct wm8510_priv), GFP_KERNEL);
+        if (wm8510 == NULL)
+                return -ENOMEM;
 
-        codec->control_data = spi;
+        i2c_set_clientdata(i2c, wm8510);
+        wm8510->control_type = SND_SOC_I2C;
 
-        ret = wm8510_init(socdev, SND_SOC_SPI);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8510, &wm8510_dai, 1);
         if (ret < 0)
-                dev_err(&spi->dev, "failed to initialise WM8510\n");
-
+                kfree(wm8510);
         return ret;
 }
 
-static int __devexit wm8510_spi_remove(struct spi_device *spi)
+static __devexit int wm8510_i2c_remove(struct i2c_client *client)
 {
+        snd_soc_unregister_codec(&client->dev);
         return 0;
 }
 
-static struct spi_driver wm8510_spi_driver = {
+static const struct i2c_device_id wm8510_i2c_id[] = {
+        { "wm8510", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8510_i2c_id);
+
+static struct i2c_driver wm8510_i2c_driver = {
         .driver = {
-                .name   = "wm8510",
-                .bus    = &spi_bus_type,
-                .owner  = THIS_MODULE,
+                .name = "wm8510-codec",
+                .owner = THIS_MODULE,
         },
-        .probe          = wm8510_spi_probe,
-        .remove         = __devexit_p(wm8510_spi_remove),
+        .probe =    wm8510_i2c_probe,
+        .remove =   __devexit_p(wm8510_i2c_remove),
+        .id_table = wm8510_i2c_id,
 };
-#endif /* CONFIG_SPI_MASTER */
+#endif
 
-static int wm8510_probe(struct platform_device *pdev)
+static int __init wm8510_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct wm8510_setup_data *setup;
-        struct snd_soc_codec *codec;
         int ret = 0;
-
-        pr_info("WM8510 Audio Codec %s", WM8510_VERSION);
-
-        setup = socdev->codec_data;
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-
-        socdev->card->codec = codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        wm8510_socdev = socdev;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        if (setup->i2c_address) {
-                ret = wm8510_add_i2c_device(pdev, setup);
+        ret = i2c_add_driver(&wm8510_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8510 I2C driver: %d\n",
+                       ret);
         }
 #endif
 #if defined(CONFIG_SPI_MASTER)
-        if (setup->spi) {
-                ret = spi_register_driver(&wm8510_spi_driver);
-                if (ret != 0)
-                        printk(KERN_ERR "can't add spi driver");
+        ret = spi_register_driver(&wm8510_spi_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8510 SPI driver: %d\n",
+                       ret);
         }
 #endif
-
-        if (ret != 0)
-                kfree(codec);
         return ret;
 }
+module_init(wm8510_modinit);
 
-/* power down chip */
-static int wm8510_remove(struct platform_device *pdev)
+static void __exit wm8510_exit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec->control_data)
-                wm8510_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        i2c_unregister_device(codec->control_data);
         i2c_del_driver(&wm8510_i2c_driver);
 #endif
 #if defined(CONFIG_SPI_MASTER)
         spi_unregister_driver(&wm8510_spi_driver);
 #endif
-        kfree(codec);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8510 = {
-        .probe =        wm8510_probe,
-        .remove =       wm8510_remove,
-        .suspend =      wm8510_suspend,
-        .resume =       wm8510_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8510);
-
-static int __init wm8510_modinit(void)
-{
-        return snd_soc_register_dai(&wm8510_dai);
-}
-module_init(wm8510_modinit);
-
-static void __exit wm8510_exit(void)
-{
-        snd_soc_unregister_dai(&wm8510_dai);
 }
 module_exit(wm8510_exit);
 
diff --git a/sound/soc/codecs/wm8510.h b/sound/soc/codecs/wm8510.h
index bdefcf5c69ff..b3e26ed9f2d0 100644
--- a/sound/soc/codecs/wm8510.h
+++ b/sound/soc/codecs/wm8510.h
@@ -99,7 +99,4 @@ struct wm8510_setup_data {
         unsigned short i2c_address;
 };
 
-extern struct snd_soc_dai wm8510_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8510;
-
 #endif
diff --git a/sound/soc/codecs/wm8523.c b/sound/soc/codecs/wm8523.c
index 0ad039b4adf5..4fd4d8dca0fc 100644
--- a/sound/soc/codecs/wm8523.c
+++ b/sound/soc/codecs/wm8523.c
@@ -24,15 +24,11 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
 #include "wm8523.h"
 
-static struct snd_soc_codec *wm8523_codec;
-struct snd_soc_codec_device soc_codec_dev_wm8523;
-
 #define WM8523_NUM_SUPPLIES 2
 static const char *wm8523_supply_names[WM8523_NUM_SUPPLIES] = {
         "AVDD",
@@ -43,8 +39,7 @@ static const char *wm8523_supply_names[WM8523_NUM_SUPPLIES] = {
 
 /* codec private data */
 struct wm8523_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM8523_REGISTER_COUNT];
+        enum snd_soc_control_type control_type;
         struct regulator_bulk_data supplies[WM8523_NUM_SUPPLIES];
         unsigned int sysclk;
         unsigned int rate_constraint_list[WM8523_NUM_RATES];
@@ -63,7 +58,7 @@ static const u16 wm8523_reg[WM8523_REGISTER_COUNT] = {
         0x0000,     /* R8 - ZERO_DETECT */
 };
 
-static int wm8523_volatile_register(unsigned int reg)
+static int wm8523_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
 {
         switch (reg) {
         case WM8523_DEVICE_ID:
@@ -113,10 +108,11 @@ static const struct snd_soc_dapm_route intercon[] = {
 
 static int wm8523_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8523_dapm_widgets,
-                                  ARRAY_SIZE(wm8523_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+        snd_soc_dapm_new_controls(dapm, wm8523_dapm_widgets,
+                                  ARRAY_SIZE(wm8523_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
 
         return 0;
 }
@@ -149,7 +145,6 @@ static int wm8523_startup(struct snd_pcm_substream *substream,
                 return -EINVAL;
         }
 
-        return 0;
         snd_pcm_hw_constraint_list(substream->runtime, 0,
                                    SNDRV_PCM_HW_PARAM_RATE,
                                    &wm8523->rate_constraint);
@@ -162,8 +157,7 @@ static int wm8523_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec);
         int i;
         u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1);
@@ -319,6 +313,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
                                  enum snd_soc_bias_level level)
 {
         struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec);
+        u16 *reg_cache = codec->reg_cache;
         int ret, i;
 
         switch (level) {
@@ -332,7 +327,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
                                                     wm8523->supplies);
                         if (ret != 0) {
@@ -349,7 +344,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
                         /* Sync back default/cached values */
                         for (i = WM8523_AIF_CTRL1;
                              i < WM8523_MAX_REGISTER; i++)
-                                snd_soc_write(codec, i, wm8523->reg_cache[i]);
+                                snd_soc_write(codec, i, reg_cache[i]);
 
 
                         msleep(100);
@@ -371,7 +366,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
                                        wm8523->supplies);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -387,8 +382,8 @@ static struct snd_soc_dai_ops wm8523_dai_ops = {
         .set_fmt        = wm8523_set_dai_fmt,
 };
 
-struct snd_soc_dai wm8523_dai = {
-        .name = "WM8523",
+static struct snd_soc_dai_driver wm8523_dai = {
+        .name = "wm8523-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,  /* Mono modes not yet supported */
@@ -398,25 +393,17 @@ struct snd_soc_dai wm8523_dai = {
         },
         .ops = &wm8523_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8523_dai);
 
 #ifdef CONFIG_PM
-static int wm8523_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8523_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8523_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8523_resume(struct platform_device *pdev)
+static int wm8523_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8523_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-
         return 0;
 }
 #else
@@ -424,93 +411,20 @@ static int wm8523_resume(struct platform_device *pdev)
 #define wm8523_resume NULL
 #endif
 
-static int wm8523_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8523_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8523_codec;
-        codec = wm8523_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8523_snd_controls,
-                             ARRAY_SIZE(wm8523_snd_controls));
-        wm8523_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-static int wm8523_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8523 = {
-        .probe =        wm8523_probe,
-        .remove =       wm8523_remove,
-        .suspend =      wm8523_suspend,
-        .resume =       wm8523_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8523);
-
-static int wm8523_register(struct wm8523_priv *wm8523,
-                           enum snd_soc_control_type control)
+static int wm8523_probe(struct snd_soc_codec *codec)
 {
-        int ret;
-        struct snd_soc_codec *codec = &wm8523->codec;
-        int i;
-
-        if (wm8523_codec) {
-                dev_err(codec->dev, "Another WM8523 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8523);
-        codec->name = "WM8523";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8523_set_bias_level;
-        codec->dai = &wm8523_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8523_REGISTER_COUNT;
-        codec->reg_cache = &wm8523->reg_cache;
-        codec->volatile_register = wm8523_volatile_register;
+        struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec);
+        int ret, i;
 
+        codec->hw_write = (hw_write_t)i2c_master_send;
         wm8523->rate_constraint.list = &wm8523->rate_constraint_list[0];
         wm8523->rate_constraint.count =
                 ARRAY_SIZE(wm8523->rate_constraint_list);
 
-        memcpy(codec->reg_cache, wm8523_reg, sizeof(wm8523_reg));
-
-        ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8523->control_type);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++)
@@ -520,7 +434,7 @@ static int wm8523_register(struct wm8523_priv *wm8523,
                                  wm8523->supplies);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
@@ -555,80 +469,77 @@ static int wm8523_register(struct wm8523_priv *wm8523,
                 goto err_enable;
         }
 
-        wm8523_dai.dev = codec->dev;
-
         /* Change some default settings - latch VU and enable ZC */
-        wm8523->reg_cache[WM8523_DAC_GAINR] |= WM8523_DACR_VU;
-        wm8523->reg_cache[WM8523_DAC_CTRL3] |= WM8523_ZC;
+        snd_soc_update_bits(codec, WM8523_DAC_GAINR,
+                            WM8523_DACR_VU, WM8523_DACR_VU);
+        snd_soc_update_bits(codec, WM8523_DAC_CTRL3, WM8523_ZC, WM8523_ZC);
 
         wm8523_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         /* Bias level configuration will have done an extra enable */
         regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
 
-        wm8523_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err_enable;
-        }
-
-        ret = snd_soc_register_dai(&wm8523_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+        snd_soc_add_controls(codec, wm8523_snd_controls,
+                             ARRAY_SIZE(wm8523_snd_controls));
+        wm8523_add_widgets(codec);
 
         return 0;
 
-err_codec:
-        snd_soc_unregister_codec(codec);
 err_enable:
         regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
 err_get:
         regulator_bulk_free(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
-err:
-        kfree(wm8523);
+
         return ret;
 }
 
-static void wm8523_unregister(struct wm8523_priv *wm8523)
+static int wm8523_remove(struct snd_soc_codec *codec)
 {
-        wm8523_set_bias_level(&wm8523->codec, SND_SOC_BIAS_OFF);
+        struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec);
+
+        wm8523_set_bias_level(codec, SND_SOC_BIAS_OFF);
         regulator_bulk_free(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
-        snd_soc_unregister_dai(&wm8523_dai);
-        snd_soc_unregister_codec(&wm8523->codec);
-        kfree(wm8523);
-        wm8523_codec = NULL;
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8523 = {
+        .probe =        wm8523_probe,
+        .remove =       wm8523_remove,
+        .suspend =      wm8523_suspend,
+        .resume =       wm8523_resume,
+        .set_bias_level = wm8523_set_bias_level,
+        .reg_cache_size = WM8523_REGISTER_COUNT,
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8523_reg,
+        .volatile_register = wm8523_volatile_register,
+};
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int wm8523_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm8523_priv *wm8523;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8523 = kzalloc(sizeof(struct wm8523_priv), GFP_KERNEL);
         if (wm8523 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8523->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
         i2c_set_clientdata(i2c, wm8523);
-        codec->control_data = i2c;
+        wm8523->control_type = SND_SOC_I2C;
 
-        codec->dev = &i2c->dev;
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8523, &wm8523_dai, 1);
+        if (ret < 0)
+                kfree(wm8523);
+        return ret;
 
-        return wm8523_register(wm8523, SND_SOC_I2C);
 }
 
 static __devexit int wm8523_i2c_remove(struct i2c_client *client)
 {
-        struct wm8523_priv *wm8523 = i2c_get_clientdata(client);
-        wm8523_unregister(wm8523);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -640,7 +551,7 @@ MODULE_DEVICE_TABLE(i2c, wm8523_i2c_id);
 
 static struct i2c_driver wm8523_i2c_driver = {
         .driver = {
-                .name = "WM8523",
+                .name = "wm8523-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8523_i2c_probe,
diff --git a/sound/soc/codecs/wm8523.h b/sound/soc/codecs/wm8523.h
index 1aa9ce3e1357..4d5b1eb8f2fc 100644
--- a/sound/soc/codecs/wm8523.h
+++ b/sound/soc/codecs/wm8523.h
@@ -154,7 +154,4 @@
 #define WM8523_ZD_COUNT_SHIFT                        0  /* ZD_COUNT - [1:0] */
 #define WM8523_ZD_COUNT_WIDTH                        2  /* ZD_COUNT - [1:0] */
 
-extern struct snd_soc_dai wm8523_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8523;
-
 #endif
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index 72deeabef4fe..4bbc0a79f01e 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -31,7 +31,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 #include <sound/initval.h>
 #include <asm/div64.h>
@@ -94,6 +93,8 @@
 
 #define WM8580_MAX_REGISTER                  0x35
 
+#define WM8580_DACOSR 0x40
+
 /* PLLB4 (register 7h) */
 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
@@ -112,19 +113,7 @@
 
 /* AIF control 1 (registers 9h-bh) */
 #define WM8580_AIF_RATE_MASK       0x7
-#define WM8580_AIF_RATE_128        0x0
-#define WM8580_AIF_RATE_192        0x1
-#define WM8580_AIF_RATE_256        0x2
-#define WM8580_AIF_RATE_384        0x3
-#define WM8580_AIF_RATE_512        0x4
-#define WM8580_AIF_RATE_768        0x5
-#define WM8580_AIF_RATE_1152       0x6
-
 #define WM8580_AIF_BCLKSEL_MASK   0x18
-#define WM8580_AIF_BCLKSEL_64     0x00
-#define WM8580_AIF_BCLKSEL_128    0x08
-#define WM8580_AIF_BCLKSEL_256    0x10
-#define WM8580_AIF_BCLKSEL_SYSCLK 0x18
 
 #define WM8580_AIF_MS             0x20
 
@@ -171,7 +160,7 @@
 static const u16 wm8580_reg[] = {
         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
-        0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
+        0x0010, 0x0002, 0x0002, 0x00c2, /*R11*/
         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
@@ -199,11 +188,11 @@ static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 
 /* codec private data */
 struct wm8580_priv {
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
-        u16 reg_cache[WM8580_MAX_REGISTER + 1];
         struct pll_state a;
         struct pll_state b;
+        int sysclk[2];
 };
 
 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
@@ -273,8 +262,8 @@ SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
 
-SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
-SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
+SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
+SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 };
 
 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
@@ -311,10 +300,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
-                                  ARRAY_SIZE(wm8580_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, wm8580_dapm_widgets,
+                                  ARRAY_SIZE(wm8580_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -476,6 +466,10 @@ static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
         return 0;
 }
 
+static const int wm8580_sysclk_ratios[] = {
+        128, 192, 256, 384, 512, 768, 1152,
+};
+
 /*
  * Set PCM DAI bit size and sample rate.
  */
@@ -484,29 +478,68 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
                                  struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-        u16 paifb = snd_soc_read(codec, WM8580_PAIF3 + dai->id);
+        struct snd_soc_codec *codec = rtd->codec;
+        struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
+        u16 paifa = 0;
+        u16 paifb = 0;
+        int i, ratio, osr;
 
-        paifb &= ~WM8580_AIF_LENGTH_MASK;
         /* bit size */
         switch (params_format(params)) {
         case SNDRV_PCM_FORMAT_S16_LE:
+                paifa |= 0x8;
                 break;
         case SNDRV_PCM_FORMAT_S20_3LE:
+                paifa |= 0x0;
                 paifb |= WM8580_AIF_LENGTH_20;
                 break;
         case SNDRV_PCM_FORMAT_S24_LE:
+                paifa |= 0x0;
                 paifb |= WM8580_AIF_LENGTH_24;
                 break;
         case SNDRV_PCM_FORMAT_S32_LE:
-                paifb |= WM8580_AIF_LENGTH_24;
+                paifa |= 0x0;
+                paifb |= WM8580_AIF_LENGTH_32;
                 break;
         default:
                 return -EINVAL;
         }
 
-        snd_soc_write(codec, WM8580_PAIF3 + dai->id, paifb);
+        /* Look up the SYSCLK ratio; accept only exact matches */
+        ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
+        for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
+                if (ratio == wm8580_sysclk_ratios[i])
+                        break;
+        if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
+                dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
+                        wm8580->sysclk[dai->driver->id], params_rate(params));
+                return -EINVAL;
+        }
+        paifa |= i;
+        dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
+                wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                switch (ratio) {
+                case 128:
+                case 192:
+                        osr = WM8580_DACOSR;
+                        dev_dbg(codec->dev, "Selecting 64x OSR\n");
+                        break;
+                default:
+                        osr = 0;
+                        dev_dbg(codec->dev, "Selecting 128x OSR\n");
+                        break;
+                }
+
+                snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
+        }
+
+        snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
+                            WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
+                            paifa);
+        snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
+                            WM8580_AIF_LENGTH_MASK, paifb);
         return 0;
 }
 
@@ -518,8 +551,8 @@ static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
         unsigned int aifb;
         int can_invert_lrclk;
 
-        aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
-        aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->id);
+        aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
+        aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
 
         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 
@@ -585,8 +618,8 @@ static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
                 return -EINVAL;
         }
 
-        snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
-        snd_soc_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
+        snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
+        snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
 
         return 0;
 }
@@ -624,28 +657,6 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
                 snd_soc_write(codec, WM8580_PLLB4, reg);
                 break;
 
-        case WM8580_DAC_CLKSEL:
-                reg = snd_soc_read(codec, WM8580_CLKSEL);
-                reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
-
-                switch (div) {
-                case WM8580_CLKSRC_MCLK:
-                        break;
-
-                case WM8580_CLKSRC_PLLA:
-                        reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
-                        break;
-
-                case WM8580_CLKSRC_PLLB:
-                        reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
-                        break;
-
-                default:
-                        return -EINVAL;
-                }
-                snd_soc_write(codec, WM8580_CLKSEL, reg);
-                break;
-
         case WM8580_CLKOUTSRC:
                 reg = snd_soc_read(codec, WM8580_PLLB4);
                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
@@ -679,6 +690,55 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
         return 0;
 }
 
+static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+                             unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
+        int sel, sel_mask, sel_shift;
+
+        switch (dai->driver->id) {
+        case WM8580_DAI_PAIFRX:
+                sel_mask = 0x3;
+                sel_shift = 0;
+                break;
+
+        case WM8580_DAI_PAIFTX:
+                sel_mask = 0xc;
+                sel_shift = 2;
+                break;
+
+        default:
+                BUG_ON("Unknown DAI driver ID\n");
+                return -EINVAL;
+        }
+
+        switch (clk_id) {
+        case WM8580_CLKSRC_ADCMCLK:
+                if (dai->driver->id != WM8580_DAI_PAIFTX)
+                        return -EINVAL;
+                sel = 0 << sel_shift;
+                break;
+        case WM8580_CLKSRC_PLLA:
+                sel = 1 << sel_shift;
+                break;
+        case WM8580_CLKSRC_PLLB:
+                sel = 2 << sel_shift;
+                break;
+        case WM8580_CLKSRC_MCLK:
+                sel = 3 << sel_shift;
+                break;
+        default:
+                dev_err(codec->dev, "Unknown clock %d\n", clk_id);
+                return -EINVAL;
+        }
+
+        /* We really should validate PLL settings but not yet */
+        wm8580->sysclk[dai->driver->id] = freq;
+
+        return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
+}
+
 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 {
         struct snd_soc_codec *codec = codec_dai->codec;
@@ -706,13 +766,13 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Power up and get individual control of the DACs */
                         reg = snd_soc_read(codec, WM8580_PWRDN1);
                         reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
                         snd_soc_write(codec, WM8580_PWRDN1, reg);
 
-                        /* Make VMID high impedence */
+                        /* Make VMID high impedance */
                         reg = snd_soc_read(codec,  WM8580_ADC_CONTROL1);
                         reg &= ~0x100;
                         snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
@@ -724,7 +784,7 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec,
                 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -732,6 +792,7 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec,
                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 
 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
+        .set_sysclk     = wm8580_set_sysclk,
         .hw_params      = wm8580_paif_hw_params,
         .set_fmt        = wm8580_set_paif_dai_fmt,
         .set_clkdiv     = wm8580_set_dai_clkdiv,
@@ -740,16 +801,17 @@ static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 };
 
 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
+        .set_sysclk     = wm8580_set_sysclk,
         .hw_params      = wm8580_paif_hw_params,
         .set_fmt        = wm8580_set_paif_dai_fmt,
         .set_clkdiv     = wm8580_set_dai_clkdiv,
         .set_pll        = wm8580_set_dai_pll,
 };
 
-struct snd_soc_dai wm8580_dai[] = {
+static struct snd_soc_dai_driver wm8580_dai[] = {
         {
-                .name = "WM8580 PAIFRX",
-                .id = 0,
+                .name = "wm8580-hifi-playback",
+                .id     = WM8580_DAI_PAIFRX,
                 .playback = {
                         .stream_name = "Playback",
                         .channels_min = 1,
@@ -760,8 +822,8 @@ struct snd_soc_dai wm8580_dai[] = {
                 .ops = &wm8580_dai_ops_playback,
         },
         {
-                .name = "WM8580 PAIFTX",
-                .id = 1,
+                .name = "wm8580-hifi-capture",
+                .id     =       WM8580_DAI_PAIFTX,
                 .capture = {
                         .stream_name = "Capture",
                         .channels_min = 2,
@@ -772,90 +834,16 @@ struct snd_soc_dai wm8580_dai[] = {
                 .ops = &wm8580_dai_ops_capture,
         },
 };
-EXPORT_SYMBOL_GPL(wm8580_dai);
-
-static struct snd_soc_codec *wm8580_codec;
-
-static int wm8580_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8580_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8580_codec;
-        codec = wm8580_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8580_snd_controls,
-                             ARRAY_SIZE(wm8580_snd_controls));
-        wm8580_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-/* power down chip */
-static int wm8580_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8580 = {
-        .probe =        wm8580_probe,
-        .remove =       wm8580_remove,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
 
-static int wm8580_register(struct wm8580_priv *wm8580,
-                           enum snd_soc_control_type control)
+static int wm8580_probe(struct snd_soc_codec *codec)
 {
-        int ret, i;
-        struct snd_soc_codec *codec = &wm8580->codec;
-
-        if (wm8580_codec) {
-                dev_err(codec->dev, "Another WM8580 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8580);
-        codec->name = "WM8580";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8580_set_bias_level;
-        codec->dai = wm8580_dai;
-        codec->num_dai = ARRAY_SIZE(wm8580_dai);
-        codec->reg_cache_size = ARRAY_SIZE(wm8580->reg_cache);
-        codec->reg_cache = &wm8580->reg_cache;
-
-        memcpy(codec->reg_cache, wm8580_reg, sizeof(wm8580_reg));
+        struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
+        int ret = 0,i;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
@@ -865,7 +853,7 @@ static int wm8580_register(struct wm8580_priv *wm8580,
                                  wm8580->supplies);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
@@ -882,74 +870,68 @@ static int wm8580_register(struct wm8580_priv *wm8580,
                 goto err_regulator_enable;
         }
 
-        for (i = 0; i < ARRAY_SIZE(wm8580_dai); i++)
-                wm8580_dai[i].dev = codec->dev;
-
         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
-        wm8580_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err_regulator_enable;
-        }
-
-        ret = snd_soc_register_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+        snd_soc_add_controls(codec, wm8580_snd_controls,
+                             ARRAY_SIZE(wm8580_snd_controls));
+        wm8580_add_widgets(codec);
 
         return 0;
 
-err_codec:
-        snd_soc_unregister_codec(codec);
 err_regulator_enable:
         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 err_regulator_get:
         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
-err:
-        kfree(wm8580);
         return ret;
 }
 
-static void wm8580_unregister(struct wm8580_priv *wm8580)
+/* power down chip */
+static int wm8580_remove(struct snd_soc_codec *codec)
 {
-        wm8580_set_bias_level(&wm8580->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
-        snd_soc_unregister_codec(&wm8580->codec);
+        struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
+
+        wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
-        kfree(wm8580);
-        wm8580_codec = NULL;
+
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
+        .probe =        wm8580_probe,
+        .remove =       wm8580_remove,
+        .set_bias_level = wm8580_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8580_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8580_reg,
+};
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static int wm8580_i2c_probe(struct i2c_client *i2c,
                             const struct i2c_device_id *id)
 {
         struct wm8580_priv *wm8580;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
         if (wm8580 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8580->codec;
-
         i2c_set_clientdata(i2c, wm8580);
-        codec->control_data = i2c;
+        wm8580->control_type = SND_SOC_I2C;
 
-        codec->dev = &i2c->dev;
-
-        return wm8580_register(wm8580, SND_SOC_I2C);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
+        if (ret < 0)
+                kfree(wm8580);
+        return ret;
 }
 
 static int wm8580_i2c_remove(struct i2c_client *client)
 {
-        struct wm8580_priv *wm8580 = i2c_get_clientdata(client);
-        wm8580_unregister(wm8580);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -961,7 +943,7 @@ MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 
 static struct i2c_driver wm8580_i2c_driver = {
         .driver = {
-                .name = "wm8580",
+                .name = "wm8580-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8580_i2c_probe,
@@ -972,7 +954,7 @@ static struct i2c_driver wm8580_i2c_driver = {
 
 static int __init wm8580_modinit(void)
 {
-        int ret;
+        int ret = 0;
 
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8580_i2c_driver);
@@ -981,7 +963,7 @@ static int __init wm8580_modinit(void)
         }
 #endif
 
-        return 0;
+        return ret;
 }
 module_init(wm8580_modinit);
 
diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h
index 0dfb5ddde6a2..1d34656d0dcb 100644
--- a/sound/soc/codecs/wm8580.h
+++ b/sound/soc/codecs/wm8580.h
@@ -19,20 +19,17 @@
 #define WM8580_PLLB  2
 
 #define WM8580_MCLK       1
-#define WM8580_DAC_CLKSEL 2
-#define WM8580_CLKOUTSRC  3
+#define WM8580_CLKOUTSRC  2
 
-#define WM8580_CLKSRC_MCLK 1
-#define WM8580_CLKSRC_PLLA 2
-#define WM8580_CLKSRC_PLLB 3
-#define WM8580_CLKSRC_OSC  4
-#define WM8580_CLKSRC_NONE 5
+#define WM8580_CLKSRC_MCLK    1
+#define WM8580_CLKSRC_PLLA    2
+#define WM8580_CLKSRC_PLLB    3
+#define WM8580_CLKSRC_OSC     4
+#define WM8580_CLKSRC_NONE    5
+#define WM8580_CLKSRC_ADCMCLK 6
 
 #define WM8580_DAI_PAIFRX 0
 #define WM8580_DAI_PAIFTX 1
 
-extern struct snd_soc_dai wm8580_dai[];
-extern struct snd_soc_codec_device soc_codec_dev_wm8580;
-
 #endif
 
diff --git a/sound/soc/codecs/wm8711.c b/sound/soc/codecs/wm8711.c
index e2dba07f0260..a537e4af6ae7 100644
--- a/sound/soc/codecs/wm8711.c
+++ b/sound/soc/codecs/wm8711.c
@@ -25,18 +25,14 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 #include <sound/initval.h>
 
 #include "wm8711.h"
 
-static struct snd_soc_codec *wm8711_codec;
-
 /* codec private data */
 struct wm8711_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM8711_CACHEREGNUM];
+        enum snd_soc_control_type bus_type;
         unsigned int sysclk;
 };
 
@@ -81,7 +77,7 @@ SND_SOC_DAPM_OUTPUT("ROUT"),
 SND_SOC_DAPM_OUTPUT("RHPOUT"),
 };
 
-static const struct snd_soc_dapm_route intercon[] = {
+static const struct snd_soc_dapm_route wm8711_intercon[] = {
         /* output mixer */
         {"Output Mixer", "Line Bypass Switch", "Line Input"},
         {"Output Mixer", "HiFi Playback Switch", "DAC"},
@@ -93,16 +89,6 @@ static const struct snd_soc_dapm_route intercon[] = {
         {"LOUT", NULL, "Output Mixer"},
 };
 
-static int wm8711_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, wm8711_dapm_widgets,
-                                  ARRAY_SIZE(wm8711_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
-
-        return 0;
-}
-
 struct _coeff_div {
         u32 mclk;
         u32 rate;
@@ -163,7 +149,7 @@ static int wm8711_hw_params(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
 {
         struct snd_soc_codec *codec = dai->codec;
-        struct wm8711_priv *wm8711 = snd_soc_codec_get_drvdata(codec);
+        struct wm8711_priv *wm8711 =  snd_soc_codec_get_drvdata(codec);
         u16 iface = snd_soc_read(codec, WM8711_IFACE) & 0xfffc;
         int i = get_coeff(wm8711->sysclk, params_rate(params));
         u16 srate = (coeff_div[i].sr << 2) |
@@ -227,7 +213,7 @@ static int wm8711_set_dai_sysclk(struct snd_soc_dai *codec_dai,
                 int clk_id, unsigned int freq, int dir)
 {
         struct snd_soc_codec *codec = codec_dai->codec;
-        struct wm8711_priv *wm8711 = snd_soc_codec_get_drvdata(codec);
+        struct wm8711_priv *wm8711 =  snd_soc_codec_get_drvdata(codec);
 
         switch (freq) {
         case 11289600:
@@ -320,7 +306,7 @@ static int wm8711_set_bias_level(struct snd_soc_codec *codec,
                 snd_soc_write(codec, WM8711_PWR, 0xffff);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -338,8 +324,8 @@ static struct snd_soc_dai_ops wm8711_ops = {
         .set_fmt = wm8711_set_dai_fmt,
 };
 
-struct snd_soc_dai wm8711_dai = {
-        .name = "WM8711",
+static struct snd_soc_dai_driver wm8711_dai = {
+        .name = "wm8711-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -349,22 +335,16 @@ struct snd_soc_dai wm8711_dai = {
         },
         .ops = &wm8711_ops,
 };
-EXPORT_SYMBOL_GPL(wm8711_dai);
 
-static int wm8711_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8711_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         snd_soc_write(codec, WM8711_ACTIVE, 0x0);
         wm8711_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8711_resume(struct platform_device *pdev)
+static int wm8711_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -380,99 +360,23 @@ static int wm8711_resume(struct platform_device *pdev)
         return 0;
 }
 
-static int wm8711_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8711_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8711_codec;
-        codec = wm8711_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8711_snd_controls,
-                             ARRAY_SIZE(wm8711_snd_controls));
-        wm8711_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-/* power down chip */
-static int wm8711_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8711 = {
-        .probe =        wm8711_probe,
-        .remove =       wm8711_remove,
-        .suspend =      wm8711_suspend,
-        .resume =       wm8711_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8711);
-
-static int wm8711_register(struct wm8711_priv *wm8711,
-                           enum snd_soc_control_type control)
+static int wm8711_probe(struct snd_soc_codec *codec)
 {
-        int ret;
-        struct snd_soc_codec *codec = &wm8711->codec;
-        u16 reg;
-
-        if (wm8711_codec) {
-                dev_err(codec->dev, "Another WM8711 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8711);
-        codec->name = "WM8711";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8711_set_bias_level;
-        codec->dai = &wm8711_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8711_CACHEREGNUM;
-        codec->reg_cache = &wm8711->reg_cache;
-
-        memcpy(codec->reg_cache, wm8711_reg, sizeof(wm8711_reg));
+        struct wm8711_priv *wm8711 = snd_soc_codec_get_drvdata(codec);
+        int ret, reg;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8711->bus_type);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = wm8711_reset(codec);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to issue reset\n");
-                goto err;
+                return ret;
         }
 
-        wm8711_dai.dev = codec->dev;
-
         wm8711_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         /* Latch the update bits */
@@ -481,70 +385,65 @@ static int wm8711_register(struct wm8711_priv *wm8711,
         reg = snd_soc_read(codec, WM8711_ROUT1V);
         snd_soc_write(codec, WM8711_ROUT1V, reg | 0x0100);
 
-        wm8711_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&wm8711_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
-
-        return 0;
+        snd_soc_add_controls(codec, wm8711_snd_controls,
+                             ARRAY_SIZE(wm8711_snd_controls));
 
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8711);
         return ret;
+
 }
 
-static void wm8711_unregister(struct wm8711_priv *wm8711)
+/* power down chip */
+static int wm8711_remove(struct snd_soc_codec *codec)
 {
-        wm8711_set_bias_level(&wm8711->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm8711_dai);
-        snd_soc_unregister_codec(&wm8711->codec);
-        kfree(wm8711);
-        wm8711_codec = NULL;
+        wm8711_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8711 = {
+        .probe =        wm8711_probe,
+        .remove =       wm8711_remove,
+        .suspend =      wm8711_suspend,
+        .resume =       wm8711_resume,
+        .set_bias_level = wm8711_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8711_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8711_reg,
+        .dapm_widgets = wm8711_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm8711_dapm_widgets),
+        .dapm_routes = wm8711_intercon,
+        .num_dapm_routes = ARRAY_SIZE(wm8711_intercon),
+};
+
 #if defined(CONFIG_SPI_MASTER)
 static int __devinit wm8711_spi_probe(struct spi_device *spi)
 {
-        struct snd_soc_codec *codec;
         struct wm8711_priv *wm8711;
+        int ret;
 
         wm8711 = kzalloc(sizeof(struct wm8711_priv), GFP_KERNEL);
         if (wm8711 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8711->codec;
-        codec->control_data = spi;
-        codec->dev = &spi->dev;
+        spi_set_drvdata(spi, wm8711);
+        wm8711->bus_type = SND_SOC_SPI;
 
-        dev_set_drvdata(&spi->dev, wm8711);
-
-        return wm8711_register(wm8711, SND_SOC_SPI);
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8711, &wm8711_dai, 1);
+        if (ret < 0)
+                kfree(wm8711);
+        return ret;
 }
 
 static int __devexit wm8711_spi_remove(struct spi_device *spi)
 {
-        struct wm8711_priv *wm8711 = dev_get_drvdata(&spi->dev);
-
-        wm8711_unregister(wm8711);
-
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
 }
 
 static struct spi_driver wm8711_spi_driver = {
         .driver = {
-                .name   = "wm8711",
-                .bus    = &spi_bus_type,
+                .name   = "wm8711-codec",
                 .owner  = THIS_MODULE,
         },
         .probe          = wm8711_spi_probe,
@@ -553,31 +452,30 @@ static struct spi_driver wm8711_spi_driver = {
 #endif /* CONFIG_SPI_MASTER */
 
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-static __devinit int wm8711_i2c_probe(struct i2c_client *i2c,
+static __devinit int wm8711_i2c_probe(struct i2c_client *client,
                                       const struct i2c_device_id *id)
 {
         struct wm8711_priv *wm8711;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8711 = kzalloc(sizeof(struct wm8711_priv), GFP_KERNEL);
         if (wm8711 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8711->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
-        i2c_set_clientdata(i2c, wm8711);
-        codec->control_data = i2c;
+        i2c_set_clientdata(client, wm8711);
+        wm8711->bus_type = SND_SOC_I2C;
 
-        codec->dev = &i2c->dev;
-
-        return wm8711_register(wm8711, SND_SOC_I2C);
+        ret =  snd_soc_register_codec(&client->dev,
+                        &soc_codec_dev_wm8711, &wm8711_dai, 1);
+        if (ret < 0)
+                kfree(wm8711);
+        return ret;
 }
 
 static __devexit int wm8711_i2c_remove(struct i2c_client *client)
 {
-        struct wm8711_priv *wm8711 = i2c_get_clientdata(client);
-        wm8711_unregister(wm8711);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -589,7 +487,7 @@ MODULE_DEVICE_TABLE(i2c, wm8711_i2c_id);
 
 static struct i2c_driver wm8711_i2c_driver = {
         .driver = {
-                .name = "WM8711 I2C Codec",
+                .name = "wm8711-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8711_i2c_probe,
diff --git a/sound/soc/codecs/wm8711.h b/sound/soc/codecs/wm8711.h
index 381e84a43816..a61db985499f 100644
--- a/sound/soc/codecs/wm8711.h
+++ b/sound/soc/codecs/wm8711.h
@@ -36,7 +36,4 @@ struct wm8711_setup_data {
         unsigned short i2c_address;
 };
 
-extern struct snd_soc_dai wm8711_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8711;
-
 #endif
diff --git a/sound/soc/codecs/wm8727.c b/sound/soc/codecs/wm8727.c
index 9d1df2628136..748808285119 100644
--- a/sound/soc/codecs/wm8727.c
+++ b/sound/soc/codecs/wm8727.c
@@ -23,7 +23,6 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include "wm8727.h"
 /*
  * Note this is a simple chip with no configuration interface, sample rate is
  * determined automatically by examining the Master clock and Bit clock ratios
@@ -33,8 +32,8 @@
                         SNDRV_PCM_RATE_192000)
 
 
-struct snd_soc_dai wm8727_dai = {
-        .name = "WM8727",
+static struct snd_soc_dai_driver wm8727_dai = {
+        .name = "wm8727-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -43,103 +42,18 @@ struct snd_soc_dai wm8727_dai = {
                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
                 },
 };
-EXPORT_SYMBOL_GPL(wm8727_dai);
 
-static struct snd_soc_codec *wm8727_codec;
+static struct snd_soc_codec_driver soc_codec_dev_wm8727;
 
-static int wm8727_soc_probe(struct platform_device *pdev)
+static __devinit int wm8727_probe(struct platform_device *pdev)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        int ret = 0;
-
-        BUG_ON(!wm8727_codec);
-
-        socdev->card->codec = wm8727_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "wm8727: failed to create pcms\n");
-                goto pcm_err;
-        }
-
-        return ret;
-
-pcm_err:
-        kfree(socdev->card->codec);
-        socdev->card->codec = NULL;
-        return ret;
-}
-
-static int wm8727_soc_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8727 = {
-        .probe =        wm8727_soc_probe,
-        .remove =       wm8727_soc_remove,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8727);
-
-
-static __devinit int wm8727_platform_probe(struct platform_device *pdev)
-{
-        struct snd_soc_codec *codec;
-        int ret;
-
-        if (wm8727_codec) {
-                dev_err(&pdev->dev, "Another WM8727 is registered\n");
-                return -EBUSY;
-        }
-
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-        wm8727_codec = codec;
-
-        platform_set_drvdata(pdev, codec);
-
-        mutex_init(&codec->mutex);
-        codec->dev = &pdev->dev;
-        codec->name = "WM8727";
-        codec->owner = THIS_MODULE;
-        codec->dai = &wm8727_dai;
-        codec->num_dai = 1;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        wm8727_dai.dev = &pdev->dev;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(&pdev->dev, "Failed to register CODEC: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&wm8727_dai);
-        if (ret != 0) {
-                dev_err(&pdev->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
-
-        return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(codec);
-        return ret;
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_wm8727, &wm8727_dai, 1);
 }
 
-static int __devexit wm8727_platform_remove(struct platform_device *pdev)
+static int __devexit wm8727_remove(struct platform_device *pdev)
 {
-        snd_soc_unregister_dai(&wm8727_dai);
-        snd_soc_unregister_codec(platform_get_drvdata(pdev));
+        snd_soc_unregister_codec(&pdev->dev);
         return 0;
 }
 
@@ -149,8 +63,8 @@ static struct platform_driver wm8727_codec_driver = {
                         .owner = THIS_MODULE,
         },
 
-        .probe = wm8727_platform_probe,
-        .remove = __devexit_p(wm8727_platform_remove),
+        .probe = wm8727_probe,
+        .remove = __devexit_p(wm8727_remove),
 };
 
 static int __init wm8727_init(void)
diff --git a/sound/soc/codecs/wm8727.h b/sound/soc/codecs/wm8727.h
deleted file mode 100644
index ee19aa71bcdc..000000000000
--- a/sound/soc/codecs/wm8727.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * wm8727.h
- *
- *  Created on: 15-Oct-2009
- *      Author: neil.jones@imgtec.com
- *
- * Copyright (C) 2009 Imagination Technologies Ltd.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-
-#ifndef WM8727_H_
-#define WM8727_H_
-
-extern struct snd_soc_dai wm8727_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8727;
-
-#endif /* WM8727_H_ */
diff --git a/sound/soc/codecs/wm8728.c b/sound/soc/codecs/wm8728.c
index 34be2d2b69ef..86d4718d3a76 100644
--- a/sound/soc/codecs/wm8728.c
+++ b/sound/soc/codecs/wm8728.c
@@ -23,14 +23,11 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
 #include "wm8728.h"
 
-struct snd_soc_codec_device soc_codec_dev_wm8728;
-
 /*
  * We can't read the WM8728 register space so we cache them instead.
  * Note that the defaults here aren't the physical defaults, we latch
@@ -44,6 +41,11 @@ static const u16 wm8728_reg_defaults[] = {
         0x100,
 };
 
+/* codec private data */
+struct wm8728_priv {
+        enum snd_soc_control_type control_type;
+};
+
 static const DECLARE_TLV_DB_SCALE(wm8728_tlv, -12750, 50, 1);
 
 static const struct snd_kcontrol_new wm8728_snd_controls[] = {
@@ -63,21 +65,11 @@ SND_SOC_DAPM_OUTPUT("VOUTL"),
 SND_SOC_DAPM_OUTPUT("VOUTR"),
 };
 
-static const struct snd_soc_dapm_route intercon[] = {
+static const struct snd_soc_dapm_route wm8728_intercon[] = {
         {"VOUTL", NULL, "DAC"},
         {"VOUTR", NULL, "DAC"},
 };
 
-static int wm8728_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, wm8728_dapm_widgets,
-                                  ARRAY_SIZE(wm8728_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
-
-        return 0;
-}
-
 static int wm8728_mute(struct snd_soc_dai *dai, int mute)
 {
         struct snd_soc_codec *codec = dai->codec;
@@ -96,8 +88,7 @@ static int wm8728_hw_params(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 dac = snd_soc_read(codec, WM8728_DACCTL);
 
         dac &= ~0x18;
@@ -178,7 +169,7 @@ static int wm8728_set_bias_level(struct snd_soc_codec *codec,
         case SND_SOC_BIAS_ON:
         case SND_SOC_BIAS_PREPARE:
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Power everything up... */
                         reg = snd_soc_read(codec, WM8728_DACCTL);
                         snd_soc_write(codec, WM8728_DACCTL, reg & ~0x4);
@@ -195,7 +186,7 @@ static int wm8728_set_bias_level(struct snd_soc_codec *codec,
                 snd_soc_write(codec, WM8728_DACCTL, reg | 0x4);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -210,8 +201,8 @@ static struct snd_soc_dai_ops wm8728_dai_ops = {
         .set_fmt        = wm8728_set_dai_fmt,
 };
 
-struct snd_soc_dai wm8728_dai = {
-        .name = "WM8728",
+static struct snd_soc_dai_driver wm8728_dai = {
+        .name = "wm8728-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -221,63 +212,31 @@ struct snd_soc_dai wm8728_dai = {
         },
         .ops = &wm8728_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8728_dai);
 
-static int wm8728_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8728_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8728_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm8728_resume(struct platform_device *pdev)
+static int wm8728_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8728_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
 }
 
-/*
- * initialise the WM8728 driver
- * register the mixer and dsp interfaces with the kernel
- */
-static int wm8728_init(struct snd_soc_device *socdev,
-                       enum snd_soc_control_type control)
+static int wm8728_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int ret = 0;
-
-        codec->name = "WM8728";
-        codec->owner = THIS_MODULE;
-        codec->set_bias_level = wm8728_set_bias_level;
-        codec->dai = &wm8728_dai;
-        codec->num_dai = 1;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->reg_cache_size = ARRAY_SIZE(wm8728_reg_defaults);
-        codec->reg_cache = kmemdup(wm8728_reg_defaults,
-                                   sizeof(wm8728_reg_defaults),
-                                   GFP_KERNEL);
-        if (codec->reg_cache == NULL)
-                return -ENOMEM;
+        struct wm8728_priv *wm8728 = snd_soc_codec_get_drvdata(codec);
+        int ret;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8728->control_type);
         if (ret < 0) {
                 printk(KERN_ERR "wm8728: failed to configure cache I/O: %d\n",
                        ret);
-                goto err;
-        }
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "wm8728: failed to create pcms\n");
-                goto err;
+                return ret;
         }
 
         /* power on device */
@@ -285,218 +244,142 @@ static int wm8728_init(struct snd_soc_device *socdev,
 
         snd_soc_add_controls(codec, wm8728_snd_controls,
                                 ARRAY_SIZE(wm8728_snd_controls));
-        wm8728_add_widgets(codec);
-
-        return ret;
 
-err:
-        kfree(codec->reg_cache);
         return ret;
 }
 
-static struct snd_soc_device *wm8728_socdev;
-
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static int wm8728_remove(struct snd_soc_codec *codec)
+{
+        wm8728_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
 
-/*
- * WM8728 2 wire address is determined by GPIO5
- * state during powerup.
- *    low  = 0x1a
- *    high = 0x1b
- */
+static struct snd_soc_codec_driver soc_codec_dev_wm8728 = {
+        .probe =        wm8728_probe,
+        .remove =       wm8728_remove,
+        .suspend =      wm8728_suspend,
+        .resume =       wm8728_resume,
+        .set_bias_level = wm8728_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8728_reg_defaults),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8728_reg_defaults,
+        .dapm_widgets = wm8728_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm8728_dapm_widgets),
+        .dapm_routes = wm8728_intercon,
+        .num_dapm_routes = ARRAY_SIZE(wm8728_intercon),
+};
 
-static int wm8728_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8728_spi_probe(struct spi_device *spi)
 {
-        struct snd_soc_device *socdev = wm8728_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct wm8728_priv *wm8728;
         int ret;
 
-        i2c_set_clientdata(i2c, codec);
-        codec->control_data = i2c;
+        wm8728 = kzalloc(sizeof(struct wm8728_priv), GFP_KERNEL);
+        if (wm8728 == NULL)
+                return -ENOMEM;
+
+        wm8728->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8728);
 
-        ret = wm8728_init(socdev, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8728, &wm8728_dai, 1);
         if (ret < 0)
-                pr_err("failed to initialise WM8728\n");
-
+                kfree(wm8728);
         return ret;
 }
 
-static int wm8728_i2c_remove(struct i2c_client *client)
+static int __devexit wm8728_spi_remove(struct spi_device *spi)
 {
-        struct snd_soc_codec *codec = i2c_get_clientdata(client);
-        kfree(codec->reg_cache);
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
 }
 
-static const struct i2c_device_id wm8728_i2c_id[] = {
-        { "wm8728", 0 },
-        { }
-};
-MODULE_DEVICE_TABLE(i2c, wm8728_i2c_id);
-
-static struct i2c_driver wm8728_i2c_driver = {
+static struct spi_driver wm8728_spi_driver = {
         .driver = {
-                .name = "WM8728 I2C Codec",
-                .owner = THIS_MODULE,
+                .name   = "wm8728-codec",
+                .owner  = THIS_MODULE,
         },
-        .probe =    wm8728_i2c_probe,
-        .remove =   wm8728_i2c_remove,
-        .id_table = wm8728_i2c_id,
+        .probe          = wm8728_spi_probe,
+        .remove         = __devexit_p(wm8728_spi_remove),
 };
+#endif /* CONFIG_SPI_MASTER */
 
-static int wm8728_add_i2c_device(struct platform_device *pdev,
-                                 const struct wm8728_setup_data *setup)
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8728_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
-        struct i2c_board_info info;
-        struct i2c_adapter *adapter;
-        struct i2c_client *client;
+        struct wm8728_priv *wm8728;
         int ret;
 
-        ret = i2c_add_driver(&wm8728_i2c_driver);
-        if (ret != 0) {
-                dev_err(&pdev->dev, "can't add i2c driver\n");
-                return ret;
-        }
-
-        memset(&info, 0, sizeof(struct i2c_board_info));
-        info.addr = setup->i2c_address;
-        strlcpy(info.type, "wm8728", I2C_NAME_SIZE);
-
-        adapter = i2c_get_adapter(setup->i2c_bus);
-        if (!adapter) {
-                dev_err(&pdev->dev, "can't get i2c adapter %d\n",
-                        setup->i2c_bus);
-                goto err_driver;
-        }
-
-        client = i2c_new_device(adapter, &info);
-        i2c_put_adapter(adapter);
-        if (!client) {
-                dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
-                        (unsigned int)info.addr);
-                goto err_driver;
-        }
-
-        return 0;
-
-err_driver:
-        i2c_del_driver(&wm8728_i2c_driver);
-        return -ENODEV;
-}
-#endif
-
-#if defined(CONFIG_SPI_MASTER)
-static int __devinit wm8728_spi_probe(struct spi_device *spi)
-{
-        struct snd_soc_device *socdev = wm8728_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int ret;
+        wm8728 = kzalloc(sizeof(struct wm8728_priv), GFP_KERNEL);
+        if (wm8728 == NULL)
+                return -ENOMEM;
 
-        codec->control_data = spi;
+        i2c_set_clientdata(i2c, wm8728);
+        wm8728->control_type = SND_SOC_I2C;
 
-        ret = wm8728_init(socdev, SND_SOC_SPI);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8728, &wm8728_dai, 1);
         if (ret < 0)
-                dev_err(&spi->dev, "failed to initialise WM8728\n");
-
+                kfree(wm8728);
         return ret;
 }
 
-static int __devexit wm8728_spi_remove(struct spi_device *spi)
+static __devexit int wm8728_i2c_remove(struct i2c_client *client)
 {
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
-static struct spi_driver wm8728_spi_driver = {
+static const struct i2c_device_id wm8728_i2c_id[] = {
+        { "wm8728", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8728_i2c_id);
+
+static struct i2c_driver wm8728_i2c_driver = {
         .driver = {
-                .name   = "wm8728",
-                .bus    = &spi_bus_type,
-                .owner  = THIS_MODULE,
+                .name = "wm8728-codec",
+                .owner = THIS_MODULE,
         },
-        .probe          = wm8728_spi_probe,
-        .remove         = __devexit_p(wm8728_spi_remove),
+        .probe =    wm8728_i2c_probe,
+        .remove =   __devexit_p(wm8728_i2c_remove),
+        .id_table = wm8728_i2c_id,
 };
-#endif /* CONFIG_SPI_MASTER */
+#endif
 
-static int wm8728_probe(struct platform_device *pdev)
+static int __init wm8728_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct wm8728_setup_data *setup;
-        struct snd_soc_codec *codec;
         int ret = 0;
-
-        setup = socdev->codec_data;
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-
-        socdev->card->codec = codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        wm8728_socdev = socdev;
-        ret = -ENODEV;
-
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        if (setup->i2c_address) {
-                ret = wm8728_add_i2c_device(pdev, setup);
+        ret = i2c_add_driver(&wm8728_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8728 I2C driver: %d\n",
+                       ret);
         }
 #endif
 #if defined(CONFIG_SPI_MASTER)
-        if (setup->spi) {
-                ret = spi_register_driver(&wm8728_spi_driver);
-                if (ret != 0)
-                        printk(KERN_ERR "can't add spi driver");
+        ret = spi_register_driver(&wm8728_spi_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8728 SPI driver: %d\n",
+                       ret);
         }
 #endif
-
-        if (ret != 0)
-                kfree(codec);
-
         return ret;
 }
+module_init(wm8728_modinit);
 
-/* power down chip */
-static int wm8728_remove(struct platform_device *pdev)
+static void __exit wm8728_exit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec->control_data)
-                wm8728_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        i2c_unregister_device(codec->control_data);
         i2c_del_driver(&wm8728_i2c_driver);
 #endif
 #if defined(CONFIG_SPI_MASTER)
         spi_unregister_driver(&wm8728_spi_driver);
 #endif
-        kfree(codec);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8728 = {
-        .probe =        wm8728_probe,
-        .remove =       wm8728_remove,
-        .suspend =      wm8728_suspend,
-        .resume =       wm8728_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8728);
-
-static int __init wm8728_modinit(void)
-{
-        return snd_soc_register_dai(&wm8728_dai);
-}
-module_init(wm8728_modinit);
-
-static void __exit wm8728_exit(void)
-{
-        snd_soc_unregister_dai(&wm8728_dai);
 }
 module_exit(wm8728_exit);
 
diff --git a/sound/soc/codecs/wm8728.h b/sound/soc/codecs/wm8728.h
index d269c132474b..8aea362ffd47 100644
--- a/sound/soc/codecs/wm8728.h
+++ b/sound/soc/codecs/wm8728.h
@@ -18,13 +18,4 @@
 #define WM8728_DACCTL    0x02
 #define WM8728_IFCTL     0x03
 
-struct wm8728_setup_data {
-        int            spi;
-        int            i2c_bus;
-        unsigned short i2c_address;
-};
-
-extern struct snd_soc_dai wm8728_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8728;
-
 #endif
diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
index 0ab9b6355297..76b4361e9b80 100644
--- a/sound/soc/codecs/wm8731.c
+++ b/sound/soc/codecs/wm8731.c
@@ -26,15 +26,11 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
 #include "wm8731.h"
 
-static struct snd_soc_codec *wm8731_codec;
-struct snd_soc_codec_device soc_codec_dev_wm8731;
-
 #define WM8731_NUM_SUPPLIES 4
 static const char *wm8731_supply_names[WM8731_NUM_SUPPLIES] = {
         "AVDD",
@@ -45,10 +41,12 @@ static const char *wm8731_supply_names[WM8731_NUM_SUPPLIES] = {
 
 /* codec private data */
 struct wm8731_priv {
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
         struct regulator_bulk_data supplies[WM8731_NUM_SUPPLIES];
-        u16 reg_cache[WM8731_CACHEREGNUM];
         unsigned int sysclk;
+        int sysclk_type;
+        int playback_fs;
+        bool deemph;
 };
 
 
@@ -67,16 +65,79 @@ static const u16 wm8731_reg[WM8731_CACHEREGNUM] = {
 #define wm8731_reset(c) snd_soc_write(c, WM8731_RESET, 0)
 
 static const char *wm8731_input_select[] = {"Line In", "Mic"};
-static const char *wm8731_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
 
-static const struct soc_enum wm8731_enum[] = {
-        SOC_ENUM_SINGLE(WM8731_APANA, 2, 2, wm8731_input_select),
-        SOC_ENUM_SINGLE(WM8731_APDIGI, 1, 4, wm8731_deemph),
-};
+static const struct soc_enum wm8731_insel_enum =
+        SOC_ENUM_SINGLE(WM8731_APANA, 2, 2, wm8731_input_select);
+
+static int wm8731_deemph[] = { 0, 32000, 44100, 48000 };
+
+static int wm8731_set_deemph(struct snd_soc_codec *codec)
+{
+        struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
+        int val, i, best;
+
+        /* If we're using deemphasis select the nearest available sample
+         * rate.
+         */
+        if (wm8731->deemph) {
+                best = 1;
+                for (i = 2; i < ARRAY_SIZE(wm8731_deemph); i++) {
+                        if (abs(wm8731_deemph[i] - wm8731->playback_fs) <
+                            abs(wm8731_deemph[best] - wm8731->playback_fs))
+                                best = i;
+                }
+
+                val = best << 1;
+        } else {
+                best = 0;
+                val = 0;
+        }
+
+        dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
+                best, wm8731_deemph[best]);
+
+        return snd_soc_update_bits(codec, WM8731_APDIGI, 0x6, val);
+}
+
+static int wm8731_get_deemph(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = wm8731->deemph;
+
+        return 0;
+}
+
+static int wm8731_put_deemph(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
+        int deemph = ucontrol->value.enumerated.item[0];
+        int ret = 0;
+
+        if (deemph > 1)
+                return -EINVAL;
+
+        mutex_lock(&codec->mutex);
+        if (wm8731->deemph != deemph) {
+                wm8731->deemph = deemph;
+
+                wm8731_set_deemph(codec);
+
+                ret = 1;
+        }
+        mutex_unlock(&codec->mutex);
+
+        return ret;
+}
 
 static const DECLARE_TLV_DB_SCALE(in_tlv, -3450, 150, 0);
 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -1500, 300, 0);
 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
+static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 2000, 0);
 
 static const struct snd_kcontrol_new wm8731_snd_controls[] = {
 
@@ -89,7 +150,7 @@ SOC_DOUBLE_R_TLV("Capture Volume", WM8731_LINVOL, WM8731_RINVOL, 0, 31, 0,
                  in_tlv),
 SOC_DOUBLE_R("Line Capture Switch", WM8731_LINVOL, WM8731_RINVOL, 7, 1, 1),
 
-SOC_SINGLE("Mic Boost (+20dB)", WM8731_APANA, 0, 1, 0),
+SOC_SINGLE_TLV("Mic Boost Volume", WM8731_APANA, 0, 1, 0, mic_tlv),
 SOC_SINGLE("Mic Capture Switch", WM8731_APANA, 1, 1, 1),
 
 SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1,
@@ -98,7 +159,8 @@ SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1,
 SOC_SINGLE("ADC High Pass Filter Switch", WM8731_APDIGI, 0, 1, 1),
 SOC_SINGLE("Store DC Offset Switch", WM8731_APDIGI, 4, 1, 0),
 
-SOC_ENUM("Playback De-emphasis", wm8731_enum[1]),
+SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
+                    wm8731_get_deemph, wm8731_put_deemph),
 };
 
 /* Output Mixer */
@@ -110,9 +172,11 @@ SOC_DAPM_SINGLE("HiFi Playback Switch", WM8731_APANA, 4, 1, 0),
 
 /* Input mux */
 static const struct snd_kcontrol_new wm8731_input_mux_controls =
-SOC_DAPM_ENUM("Input Select", wm8731_enum[0]);
+SOC_DAPM_ENUM("Input Select", wm8731_insel_enum);
 
 static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = {
+SND_SOC_DAPM_SUPPLY("ACTIVE",WM8731_ACTIVE, 0, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("OSC", WM8731_PWR, 5, 1, NULL, 0),
 SND_SOC_DAPM_MIXER("Output Mixer", WM8731_PWR, 4, 1,
         &wm8731_output_mixer_controls[0],
         ARRAY_SIZE(wm8731_output_mixer_controls)),
@@ -130,7 +194,20 @@ SND_SOC_DAPM_INPUT("RLINEIN"),
 SND_SOC_DAPM_INPUT("LLINEIN"),
 };
 
-static const struct snd_soc_dapm_route intercon[] = {
+static int wm8731_check_osc(struct snd_soc_dapm_widget *source,
+                            struct snd_soc_dapm_widget *sink)
+{
+        struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(source->codec);
+
+        return wm8731->sysclk_type == WM8731_SYSCLK_XTAL;
+}
+
+static const struct snd_soc_dapm_route wm8731_intercon[] = {
+        {"DAC", NULL, "OSC", wm8731_check_osc},
+        {"ADC", NULL, "OSC", wm8731_check_osc},
+        {"DAC", NULL, "ACTIVE"},
+        {"ADC", NULL, "ACTIVE"},
+
         /* output mixer */
         {"Output Mixer", "Line Bypass Switch", "Line Input"},
         {"Output Mixer", "HiFi Playback Switch", "DAC"},
@@ -153,16 +230,6 @@ static const struct snd_soc_dapm_route intercon[] = {
         {"Mic Bias", NULL, "MICIN"},
 };
 
-static int wm8731_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, wm8731_dapm_widgets,
-                                  ARRAY_SIZE(wm8731_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
-
-        return 0;
-}
-
 struct _coeff_div {
         u32 mclk;
         u32 rate;
@@ -222,15 +289,15 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream,
                             struct snd_pcm_hw_params *params,
                             struct snd_soc_dai *dai)
 {
-        struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = dai->codec;
         struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
         u16 iface = snd_soc_read(codec, WM8731_IFACE) & 0xfff3;
         int i = get_coeff(wm8731->sysclk, params_rate(params));
         u16 srate = (coeff_div[i].sr << 2) |
                 (coeff_div[i].bosr << 1) | coeff_div[i].usb;
 
+        wm8731->playback_fs = params_rate(params);
+
         snd_soc_write(codec, WM8731_SRATE, srate);
 
         /* bit size */
@@ -245,37 +312,12 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream,
                 break;
         }
 
-        snd_soc_write(codec, WM8731_IFACE, iface);
-        return 0;
-}
-
-static int wm8731_pcm_prepare(struct snd_pcm_substream *substream,
-                              struct snd_soc_dai *dai)
-{
-        struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        /* set active */
-        snd_soc_write(codec, WM8731_ACTIVE, 0x0001);
+        wm8731_set_deemph(codec);
 
+        snd_soc_write(codec, WM8731_IFACE, iface);
         return 0;
 }
 
-static void wm8731_shutdown(struct snd_pcm_substream *substream,
-                            struct snd_soc_dai *dai)
-{
-        struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        /* deactivate */
-        if (!codec->active) {
-                udelay(50);
-                snd_soc_write(codec, WM8731_ACTIVE, 0x0);
-        }
-}
-
 static int wm8731_mute(struct snd_soc_dai *dai, int mute)
 {
         struct snd_soc_codec *codec = dai->codec;
@@ -294,6 +336,15 @@ static int wm8731_set_dai_sysclk(struct snd_soc_dai *codec_dai,
         struct snd_soc_codec *codec = codec_dai->codec;
         struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
 
+        switch (clk_id) {
+        case WM8731_SYSCLK_XTAL:
+        case WM8731_SYSCLK_MCLK:
+                wm8731->sysclk_type = clk_id;
+                break;
+        default:
+                return -EINVAL;
+        }
+
         switch (freq) {
         case 11289600:
         case 12000000:
@@ -301,9 +352,14 @@ static int wm8731_set_dai_sysclk(struct snd_soc_dai *codec_dai,
         case 16934400:
         case 18432000:
                 wm8731->sysclk = freq;
-                return 0;
+                break;
+        default:
+                return -EINVAL;
         }
-        return -EINVAL;
+
+        snd_soc_dapm_sync(&codec->dapm);
+
+        return 0;
 }
 
 
@@ -381,7 +437,7 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
         case SND_SOC_BIAS_PREPARE:
                 break;
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8731->supplies),
                                                     wm8731->supplies);
                         if (ret != 0)
@@ -404,13 +460,12 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
                 snd_soc_write(codec, WM8731_PWR, reg | 0x0040);
                 break;
         case SND_SOC_BIAS_OFF:
-                snd_soc_write(codec, WM8731_ACTIVE, 0x0);
                 snd_soc_write(codec, WM8731_PWR, 0xffff);
                 regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies),
                                        wm8731->supplies);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -420,16 +475,14 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
         SNDRV_PCM_FMTBIT_S24_LE)
 
 static struct snd_soc_dai_ops wm8731_dai_ops = {
-        .prepare        = wm8731_pcm_prepare,
         .hw_params      = wm8731_hw_params,
-        .shutdown       = wm8731_shutdown,
         .digital_mute   = wm8731_mute,
         .set_sysclk     = wm8731_set_dai_sysclk,
         .set_fmt        = wm8731_set_dai_fmt,
 };
 
-struct snd_soc_dai wm8731_dai = {
-        .name = "WM8731",
+static struct snd_soc_dai_driver wm8731_dai = {
+        .name = "wm8731-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -445,24 +498,17 @@ struct snd_soc_dai wm8731_dai = {
         .ops = &wm8731_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8731_dai);
 
 #ifdef CONFIG_PM
-static int wm8731_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8731_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8731_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm8731_resume(struct platform_device *pdev)
+static int wm8731_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
@@ -472,88 +518,15 @@ static int wm8731_resume(struct platform_device *pdev)
 #define wm8731_resume NULL
 #endif
 
-static int wm8731_probe(struct platform_device *pdev)
+static int wm8731_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8731_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8731_codec;
-        codec = wm8731_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8731_snd_controls,
-                             ARRAY_SIZE(wm8731_snd_controls));
-        wm8731_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-/* power down chip */
-static int wm8731_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8731 = {
-        .probe =        wm8731_probe,
-        .remove =       wm8731_remove,
-        .suspend =      wm8731_suspend,
-        .resume =       wm8731_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8731);
-
-static int wm8731_register(struct wm8731_priv *wm8731,
-                           enum snd_soc_control_type control)
-{
-        int ret, i;
-        struct snd_soc_codec *codec = &wm8731->codec;
-
-        if (wm8731_codec) {
-                dev_err(codec->dev, "Another WM8731 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8731);
-        codec->name = "WM8731";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8731_set_bias_level;
-        codec->dai = &wm8731_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8731_CACHEREGNUM;
-        codec->reg_cache = &wm8731->reg_cache;
-
-        memcpy(codec->reg_cache, wm8731_reg, sizeof(wm8731_reg));
+        struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
+        int ret = 0, i;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8731->control_type);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         for (i = 0; i < ARRAY_SIZE(wm8731->supplies); i++)
@@ -563,7 +536,7 @@ static int wm8731_register(struct wm8731_priv *wm8731,
                                  wm8731->supplies);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = regulator_bulk_enable(ARRAY_SIZE(wm8731->supplies),
@@ -579,8 +552,6 @@ static int wm8731_register(struct wm8731_priv *wm8731,
                 goto err_regulator_enable;
         }
 
-        wm8731_dai.dev = codec->dev;
-
         wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         /* Latch the update bits */
@@ -590,81 +561,82 @@ static int wm8731_register(struct wm8731_priv *wm8731,
         snd_soc_update_bits(codec, WM8731_RINVOL, 0x100, 0);
 
         /* Disable bypass path by default */
-        snd_soc_update_bits(codec, WM8731_APANA, 0x4, 0);
+        snd_soc_update_bits(codec, WM8731_APANA, 0x8, 0);
 
-        wm8731_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err_regulator_enable;
-        }
-
-        ret = snd_soc_register_dai(&wm8731_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                snd_soc_unregister_codec(codec);
-                goto err_codec;
-        }
+        snd_soc_add_controls(codec, wm8731_snd_controls,
+                             ARRAY_SIZE(wm8731_snd_controls));
 
         /* Regulators will have been enabled by bias management */
         regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
 
         return 0;
 
-err_codec:
-        snd_soc_unregister_codec(codec);
 err_regulator_enable:
         regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
 err_regulator_get:
         regulator_bulk_free(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
-err:
-        kfree(wm8731);
+
         return ret;
 }
 
-static void wm8731_unregister(struct wm8731_priv *wm8731)
+/* power down chip */
+static int wm8731_remove(struct snd_soc_codec *codec)
 {
-        wm8731_set_bias_level(&wm8731->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm8731_dai);
-        snd_soc_unregister_codec(&wm8731->codec);
+        struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
+
+        wm8731_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
         regulator_bulk_free(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
-        kfree(wm8731);
-        wm8731_codec = NULL;
+
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8731 = {
+        .probe =        wm8731_probe,
+        .remove =       wm8731_remove,
+        .suspend =      wm8731_suspend,
+        .resume =       wm8731_resume,
+        .set_bias_level = wm8731_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8731_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8731_reg,
+        .dapm_widgets = wm8731_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm8731_dapm_widgets),
+        .dapm_routes = wm8731_intercon,
+        .num_dapm_routes = ARRAY_SIZE(wm8731_intercon),
+};
+
 #if defined(CONFIG_SPI_MASTER)
 static int __devinit wm8731_spi_probe(struct spi_device *spi)
 {
-        struct snd_soc_codec *codec;
         struct wm8731_priv *wm8731;
+        int ret;
 
         wm8731 = kzalloc(sizeof(struct wm8731_priv), GFP_KERNEL);
         if (wm8731 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8731->codec;
-        codec->control_data = spi;
-        codec->dev = &spi->dev;
+        wm8731->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8731);
 
-        dev_set_drvdata(&spi->dev, wm8731);
-
-        return wm8731_register(wm8731, SND_SOC_SPI);
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8731, &wm8731_dai, 1);
+        if (ret < 0)
+                kfree(wm8731);
+        return ret;
 }
 
 static int __devexit wm8731_spi_remove(struct spi_device *spi)
 {
-        struct wm8731_priv *wm8731 = dev_get_drvdata(&spi->dev);
-
-        wm8731_unregister(wm8731);
-
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
 }
 
 static struct spi_driver wm8731_spi_driver = {
         .driver = {
                 .name   = "wm8731",
-                .bus    = &spi_bus_type,
                 .owner  = THIS_MODULE,
         },
         .probe          = wm8731_spi_probe,
@@ -677,26 +649,26 @@ static __devinit int wm8731_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm8731_priv *wm8731;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8731 = kzalloc(sizeof(struct wm8731_priv), GFP_KERNEL);
         if (wm8731 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8731->codec;
-
         i2c_set_clientdata(i2c, wm8731);
-        codec->control_data = i2c;
+        wm8731->control_type = SND_SOC_I2C;
 
-        codec->dev = &i2c->dev;
-
-        return wm8731_register(wm8731, SND_SOC_I2C);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8731, &wm8731_dai, 1);
+        if (ret < 0)
+                kfree(wm8731);
+        return ret;
 }
 
 static __devexit int wm8731_i2c_remove(struct i2c_client *client)
 {
-        struct wm8731_priv *wm8731 = i2c_get_clientdata(client);
-        wm8731_unregister(wm8731);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -719,7 +691,7 @@ static struct i2c_driver wm8731_i2c_driver = {
 
 static int __init wm8731_modinit(void)
 {
-        int ret;
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8731_i2c_driver);
         if (ret != 0) {
@@ -734,7 +706,7 @@ static int __init wm8731_modinit(void)
                        ret);
         }
 #endif
-        return 0;
+        return ret;
 }
 module_init(wm8731_modinit);
 
diff --git a/sound/soc/codecs/wm8731.h b/sound/soc/codecs/wm8731.h
index cd7b806e8ad0..e9c0c76ab73b 100644
--- a/sound/soc/codecs/wm8731.h
+++ b/sound/soc/codecs/wm8731.h
@@ -31,10 +31,9 @@
 
 #define WM8731_CACHEREGNUM      10
 
-#define WM8731_SYSCLK   0
-#define WM8731_DAI              0
+#define WM8731_SYSCLK_XTAL 1
+#define WM8731_SYSCLK_MCLK 2
 
-extern struct snd_soc_dai wm8731_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8731;
+#define WM8731_DAI              0
 
 #endif
diff --git a/sound/soc/codecs/wm8737.c b/sound/soc/codecs/wm8737.c
new file mode 100644
index 000000000000..30c67d06a904
--- /dev/null
+++ b/sound/soc/codecs/wm8737.c
@@ -0,0 +1,754 @@
+/*
+ * wm8737.c  --  WM8737 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "wm8737.h"
+
+#define WM8737_NUM_SUPPLIES 4
+static const char *wm8737_supply_names[WM8737_NUM_SUPPLIES] = {
+        "DCVDD",
+        "DBVDD",
+        "AVDD",
+        "MVDD",
+};
+
+/* codec private data */
+struct wm8737_priv {
+        enum snd_soc_control_type control_type;
+        struct regulator_bulk_data supplies[WM8737_NUM_SUPPLIES];
+        unsigned int mclk;
+};
+
+static const u16 wm8737_reg[WM8737_REGISTER_COUNT] = {
+        0x00C3,     /* R0  - Left PGA volume */
+        0x00C3,     /* R1  - Right PGA volume */
+        0x0007,     /* R2  - AUDIO path L */
+        0x0007,     /* R3  - AUDIO path R */
+        0x0000,     /* R4  - 3D Enhance */
+        0x0000,     /* R5  - ADC Control */
+        0x0000,     /* R6  - Power Management */
+        0x000A,     /* R7  - Audio Format */
+        0x0000,     /* R8  - Clocking */
+        0x000F,     /* R9  - MIC Preamp Control */
+        0x0003,     /* R10 - Misc Bias Control */
+        0x0000,     /* R11 - Noise Gate */
+        0x007C,     /* R12 - ALC1 */
+        0x0000,     /* R13 - ALC2 */
+        0x0032,     /* R14 - ALC3 */
+};
+
+static int wm8737_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, WM8737_RESET, 0);
+}
+
+static const unsigned int micboost_tlv[] = {
+        TLV_DB_RANGE_HEAD(4),
+        0, 0, TLV_DB_SCALE_ITEM(1300, 0, 0),
+        1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
+        2, 2, TLV_DB_SCALE_ITEM(2800, 0, 0),
+        3, 3, TLV_DB_SCALE_ITEM(3300, 0, 0),
+};
+static const DECLARE_TLV_DB_SCALE(pga_tlv, -9750, 50, 1);
+static const DECLARE_TLV_DB_SCALE(adc_tlv, -600, 600, 0);
+static const DECLARE_TLV_DB_SCALE(ng_tlv, -7800, 600, 0);
+static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -1200, 600, 0);
+static const DECLARE_TLV_DB_SCALE(alc_target_tlv, -1800, 100, 0);
+
+static const char *micbias_enum_text[] = {
+        "25%",
+        "50%",
+        "75%",
+        "100%",
+};
+
+static const struct soc_enum micbias_enum =
+        SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 0, 4, micbias_enum_text);
+
+static const char *low_cutoff_text[] = {
+        "Low", "High"
+};
+
+static const struct soc_enum low_3d =
+        SOC_ENUM_SINGLE(WM8737_3D_ENHANCE, 6, 2, low_cutoff_text);
+
+static const char *high_cutoff_text[] = {
+        "High", "Low"
+};
+
+static const struct soc_enum high_3d =
+        SOC_ENUM_SINGLE(WM8737_3D_ENHANCE, 5, 2, high_cutoff_text);
+
+static const char *alc_fn_text[] = {
+        "Disabled", "Right", "Left", "Stereo"
+};
+
+static const struct soc_enum alc_fn =
+        SOC_ENUM_SINGLE(WM8737_ALC1, 7, 4, alc_fn_text);
+
+static const char *alc_hold_text[] = {
+        "0", "2.67ms", "5.33ms", "10.66ms", "21.32ms", "42.64ms", "85.28ms",
+        "170.56ms", "341.12ms", "682.24ms", "1.364s", "2.728s", "5.458s",
+        "10.916s", "21.832s", "43.691s"
+};
+
+static const struct soc_enum alc_hold =
+        SOC_ENUM_SINGLE(WM8737_ALC2, 0, 16, alc_hold_text);
+
+static const char *alc_atk_text[] = {
+        "8.4ms", "16.8ms", "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms",
+        "1.075s", "2.15s", "4.3s", "8.6s"
+};
+
+static const struct soc_enum alc_atk =
+        SOC_ENUM_SINGLE(WM8737_ALC3, 0, 11, alc_atk_text);
+
+static const char *alc_dcy_text[] = {
+        "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms", "1.075s", "2.15s",
+        "4.3s", "8.6s", "17.2s", "34.41s"
+};
+
+static const struct soc_enum alc_dcy =
+        SOC_ENUM_SINGLE(WM8737_ALC3, 4, 11, alc_dcy_text);
+
+static const struct snd_kcontrol_new wm8737_snd_controls[] = {
+SOC_DOUBLE_R_TLV("Mic Boost Volume", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
+                 6, 3, 0, micboost_tlv),
+SOC_DOUBLE_R("Mic Boost Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
+             4, 1, 0),
+SOC_DOUBLE("Mic ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
+           3, 1, 0),
+
+SOC_DOUBLE_R_TLV("Capture Volume", WM8737_LEFT_PGA_VOLUME,
+                 WM8737_RIGHT_PGA_VOLUME, 0, 255, 0, pga_tlv),
+SOC_DOUBLE("Capture ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
+           2, 1, 0),
+
+SOC_DOUBLE("INPUT1 DC Bias Switch", WM8737_MISC_BIAS_CONTROL, 0, 1, 1, 0),
+
+SOC_ENUM("Mic PGA Bias", micbias_enum),
+SOC_SINGLE("ADC Low Power Switch", WM8737_ADC_CONTROL, 2, 1, 0),
+SOC_SINGLE("High Pass Filter Switch", WM8737_ADC_CONTROL, 0, 1, 1),
+SOC_DOUBLE("Polarity Invert Switch", WM8737_ADC_CONTROL, 5, 6, 1, 0),
+
+SOC_SINGLE("3D Switch", WM8737_3D_ENHANCE, 0, 1, 0),
+SOC_SINGLE("3D Depth", WM8737_3D_ENHANCE, 1, 15, 0),
+SOC_ENUM("3D Low Cut-off", low_3d),
+SOC_ENUM("3D High Cut-off", low_3d),
+SOC_SINGLE_TLV("3D ADC Volume", WM8737_3D_ENHANCE, 7, 1, 1, adc_tlv),
+
+SOC_SINGLE("Noise Gate Switch", WM8737_NOISE_GATE, 0, 1, 0),
+SOC_SINGLE_TLV("Noise Gate Threshold Volume", WM8737_NOISE_GATE, 2, 7, 0,
+               ng_tlv),
+
+SOC_ENUM("ALC", alc_fn),
+SOC_SINGLE_TLV("ALC Max Gain Volume", WM8737_ALC1, 4, 7, 0, alc_max_tlv),
+SOC_SINGLE_TLV("ALC Target Volume", WM8737_ALC1, 0, 15, 0, alc_target_tlv),
+SOC_ENUM("ALC Hold Time", alc_hold),
+SOC_SINGLE("ALC ZC Switch", WM8737_ALC2, 4, 1, 0),
+SOC_ENUM("ALC Attack Time", alc_atk),
+SOC_ENUM("ALC Decay Time", alc_dcy),
+};
+
+static const char *linsel_text[] = {
+        "LINPUT1", "LINPUT2", "LINPUT3", "LINPUT1 DC",
+};
+
+static const struct soc_enum linsel_enum =
+        SOC_ENUM_SINGLE(WM8737_AUDIO_PATH_L, 7, 4, linsel_text);
+
+static const struct snd_kcontrol_new linsel_mux =
+        SOC_DAPM_ENUM("LINSEL", linsel_enum);
+
+
+static const char *rinsel_text[] = {
+        "RINPUT1", "RINPUT2", "RINPUT3", "RINPUT1 DC",
+};
+
+static const struct soc_enum rinsel_enum =
+        SOC_ENUM_SINGLE(WM8737_AUDIO_PATH_R, 7, 4, rinsel_text);
+
+static const struct snd_kcontrol_new rinsel_mux =
+        SOC_DAPM_ENUM("RINSEL", rinsel_enum);
+
+static const char *bypass_text[] = {
+        "Direct", "Preamp"
+};
+
+static const struct soc_enum lbypass_enum =
+        SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 2, 2, bypass_text);
+
+static const struct snd_kcontrol_new lbypass_mux =
+        SOC_DAPM_ENUM("Left Bypass", lbypass_enum);
+
+
+static const struct soc_enum rbypass_enum =
+        SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 3, 2, bypass_text);
+
+static const struct snd_kcontrol_new rbypass_mux =
+        SOC_DAPM_ENUM("Left Bypass", rbypass_enum);
+
+static const struct snd_soc_dapm_widget wm8737_dapm_widgets[] = {
+SND_SOC_DAPM_INPUT("LINPUT1"),
+SND_SOC_DAPM_INPUT("LINPUT2"),
+SND_SOC_DAPM_INPUT("LINPUT3"),
+SND_SOC_DAPM_INPUT("RINPUT1"),
+SND_SOC_DAPM_INPUT("RINPUT2"),
+SND_SOC_DAPM_INPUT("RINPUT3"),
+SND_SOC_DAPM_INPUT("LACIN"),
+SND_SOC_DAPM_INPUT("RACIN"),
+
+SND_SOC_DAPM_MUX("LINSEL", SND_SOC_NOPM, 0, 0, &linsel_mux),
+SND_SOC_DAPM_MUX("RINSEL", SND_SOC_NOPM, 0, 0, &rinsel_mux),
+
+SND_SOC_DAPM_MUX("Left Preamp Mux", SND_SOC_NOPM, 0, 0, &lbypass_mux),
+SND_SOC_DAPM_MUX("Right Preamp Mux", SND_SOC_NOPM, 0, 0, &rbypass_mux),
+
+SND_SOC_DAPM_PGA("PGAL", WM8737_POWER_MANAGEMENT, 5, 0, NULL, 0),
+SND_SOC_DAPM_PGA("PGAR", WM8737_POWER_MANAGEMENT, 4, 0, NULL, 0),
+
+SND_SOC_DAPM_DAC("ADCL", NULL, WM8737_POWER_MANAGEMENT, 3, 0),
+SND_SOC_DAPM_DAC("ADCR", NULL, WM8737_POWER_MANAGEMENT, 2, 0),
+
+SND_SOC_DAPM_AIF_OUT("AIF", "Capture", 0, WM8737_POWER_MANAGEMENT, 6, 0),
+};
+
+static const struct snd_soc_dapm_route intercon[] = {
+        { "LINSEL", "LINPUT1", "LINPUT1" },
+        { "LINSEL", "LINPUT2", "LINPUT2" },
+        { "LINSEL", "LINPUT3", "LINPUT3" },
+        { "LINSEL", "LINPUT1 DC", "LINPUT1" },
+
+        { "RINSEL", "RINPUT1", "RINPUT1" },
+        { "RINSEL", "RINPUT2", "RINPUT2" },
+        { "RINSEL", "RINPUT3", "RINPUT3" },
+        { "RINSEL", "RINPUT1 DC", "RINPUT1" },
+
+        { "Left Preamp Mux", "Preamp", "LINSEL" },
+        { "Left Preamp Mux", "Direct", "LACIN" },
+
+        { "Right Preamp Mux", "Preamp", "RINSEL" },
+        { "Right Preamp Mux", "Direct", "RACIN" },
+
+        { "PGAL", NULL, "Left Preamp Mux" },
+        { "PGAR", NULL, "Right Preamp Mux" },
+
+        { "ADCL", NULL, "PGAL" },
+        { "ADCR", NULL, "PGAR" },
+
+        { "AIF", NULL, "ADCL" },
+        { "AIF", NULL, "ADCR" },
+};
+
+static int wm8737_add_widgets(struct snd_soc_codec *codec)
+{
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+        snd_soc_dapm_new_controls(dapm, wm8737_dapm_widgets,
+                                  ARRAY_SIZE(wm8737_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
+
+        return 0;
+}
+
+/* codec mclk clock divider coefficients */
+static const struct {
+        u32 mclk;
+        u32 rate;
+        u8 usb;
+        u8 sr;
+} coeff_div[] = {
+        { 12288000,  8000, 0,  0x4 },
+        { 12288000, 12000, 0,  0x8 },
+        { 12288000, 16000, 0,  0xa },
+        { 12288000, 24000, 0, 0x1c },
+        { 12288000, 32000, 0,  0xc },
+        { 12288000, 48000, 0,    0 },
+        { 12288000, 96000, 0,  0xe },
+
+        { 11289600,  8000, 0, 0x14 },
+        { 11289600, 11025, 0, 0x18 },
+        { 11289600, 22050, 0, 0x1a },
+        { 11289600, 44100, 0, 0x10 },
+        { 11289600, 88200, 0, 0x1e },
+
+        { 18432000,  8000, 0,  0x5 },
+        { 18432000, 12000, 0,  0x9 },
+        { 18432000, 16000, 0,  0xb },
+        { 18432000, 24000, 0, 0x1b },
+        { 18432000, 32000, 0,  0xd },
+        { 18432000, 48000, 0,  0x1 },
+        { 18432000, 96000, 0, 0x1f },
+
+        { 16934400,  8000, 0, 0x15 },
+        { 16934400, 11025, 0, 0x19 },
+        { 16934400, 22050, 0, 0x1b },
+        { 16934400, 44100, 0, 0x11 },
+        { 16934400, 88200, 0, 0x1f },
+
+        { 12000000,  8000, 1,  0x4 },
+        { 12000000, 11025, 1, 0x19 },
+        { 12000000, 12000, 1,  0x8 },
+        { 12000000, 16000, 1,  0xa },
+        { 12000000, 22050, 1, 0x1b },
+        { 12000000, 24000, 1, 0x1c },
+        { 12000000, 32000, 1,  0xc },
+        { 12000000, 44100, 1, 0x11 },
+        { 12000000, 48000, 1,  0x0 },
+        { 12000000, 88200, 1, 0x1f },
+        { 12000000, 96000, 1,  0xe },
+};
+
+static int wm8737_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
+        int i;
+        u16 clocking = 0;
+        u16 af = 0;
+
+        for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
+                if (coeff_div[i].rate != params_rate(params))
+                        continue;
+
+                if (coeff_div[i].mclk == wm8737->mclk)
+                        break;
+
+                if (coeff_div[i].mclk == wm8737->mclk * 2) {
+                        clocking |= WM8737_CLKDIV2;
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(coeff_div)) {
+                dev_err(codec->dev, "%dHz MCLK can't support %dHz\n",
+                        wm8737->mclk, params_rate(params));
+                return -EINVAL;
+        }
+
+        clocking |= coeff_div[i].usb | (coeff_div[i].sr << WM8737_SR_SHIFT);
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                af |= 0x8;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                af |= 0x10;
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                af |= 0x18;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8737_AUDIO_FORMAT, WM8737_WL_MASK, af);
+        snd_soc_update_bits(codec, WM8737_CLOCKING,
+                            WM8737_USB_MODE | WM8737_CLKDIV2 | WM8737_SR_MASK,
+                            clocking);
+
+        return 0;
+}
+
+static int wm8737_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                                 int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
+                if (freq == coeff_div[i].mclk ||
+                    freq == coeff_div[i].mclk * 2) {
+                        wm8737->mclk = freq;
+                        return 0;
+                }
+        }
+
+        dev_err(codec->dev, "MCLK rate %dHz not supported\n", freq);
+
+        return -EINVAL;
+}
+
+
+static int wm8737_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        u16 af = 0;
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                af |= WM8737_MS;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                af |= 0x2;
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                af |= 0x1;
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+                af |= 0x3;
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                af |= 0x13;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                af |= WM8737_LRP;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8737_AUDIO_FORMAT,
+                            WM8737_FORMAT_MASK | WM8737_LRP | WM8737_MS, af);
+
+        return 0;
+}
+
+static int wm8737_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+
+        case SND_SOC_BIAS_PREPARE:
+                /* VMID at 2*75k */
+                snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
+                                    WM8737_VMIDSEL_MASK, 0);
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
+                                                    wm8737->supplies);
+                        if (ret != 0) {
+                                dev_err(codec->dev,
+                                        "Failed to enable supplies: %d\n",
+                                        ret);
+                                return ret;
+                        }
+
+                        snd_soc_cache_sync(codec);
+
+                        /* Fast VMID ramp at 2*2.5k */
+                        snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
+                                            WM8737_VMIDSEL_MASK, 0x4);
+
+                        /* Bring VMID up */
+                        snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT,
+                                            WM8737_VMID_MASK |
+                                            WM8737_VREF_MASK,
+                                            WM8737_VMID_MASK |
+                                            WM8737_VREF_MASK);
+
+                        msleep(500);
+                }
+
+                /* VMID at 2*300k */
+                snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
+                                    WM8737_VMIDSEL_MASK, 2);
+
+                break;
+
+        case SND_SOC_BIAS_OFF:
+                snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT,
+                                    WM8737_VMID_MASK | WM8737_VREF_MASK, 0);
+
+                regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies),
+                                       wm8737->supplies);
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#define WM8737_RATES SNDRV_PCM_RATE_8000_96000
+
+#define WM8737_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops wm8737_dai_ops = {
+        .hw_params      = wm8737_hw_params,
+        .set_sysclk     = wm8737_set_dai_sysclk,
+        .set_fmt        = wm8737_set_dai_fmt,
+};
+
+static struct snd_soc_dai_driver wm8737_dai = {
+        .name = "wm8737",
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 2,  /* Mono modes not yet supported */
+                .channels_max = 2,
+                .rates = WM8737_RATES,
+                .formats = WM8737_FORMATS,
+        },
+        .ops = &wm8737_dai_ops,
+};
+
+#ifdef CONFIG_PM
+static int wm8737_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        wm8737_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int wm8737_resume(struct snd_soc_codec *codec)
+{
+        wm8737_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+#else
+#define wm8737_suspend NULL
+#define wm8737_resume NULL
+#endif
+
+static int wm8737_probe(struct snd_soc_codec *codec)
+{
+        struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
+        int ret, i;
+
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8737->control_type);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)
+                wm8737->supplies[i].supply = wm8737_supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8737->supplies),
+                                 wm8737->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                return ret;
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
+                                    wm8737->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                goto err_get;
+        }
+
+        ret = wm8737_reset(codec);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to issue reset\n");
+                goto err_enable;
+        }
+
+        snd_soc_update_bits(codec, WM8737_LEFT_PGA_VOLUME, WM8737_LVU,
+                            WM8737_LVU);
+        snd_soc_update_bits(codec, WM8737_RIGHT_PGA_VOLUME, WM8737_RVU,
+                            WM8737_RVU);
+
+        wm8737_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        /* Bias level configuration will have done an extra enable */
+        regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
+
+        snd_soc_add_controls(codec, wm8737_snd_controls,
+                             ARRAY_SIZE(wm8737_snd_controls));
+        wm8737_add_widgets(codec);
+
+        return 0;
+
+err_enable:
+        regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
+err_get:
+        regulator_bulk_free(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
+
+        return ret;
+}
+
+static int wm8737_remove(struct snd_soc_codec *codec)
+{
+        struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
+
+        wm8737_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        regulator_bulk_free(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8737 = {
+        .probe          = wm8737_probe,
+        .remove         = wm8737_remove,
+        .suspend        = wm8737_suspend,
+        .resume         = wm8737_resume,
+        .set_bias_level = wm8737_set_bias_level,
+
+        .reg_cache_size = WM8737_REGISTER_COUNT - 1, /* Skip reset */
+        .reg_word_size  = sizeof(u16),
+        .reg_cache_default = wm8737_reg,
+};
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8737_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8737_priv *wm8737;
+        int ret;
+
+        wm8737 = kzalloc(sizeof(struct wm8737_priv), GFP_KERNEL);
+        if (wm8737 == NULL)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, wm8737);
+        wm8737->control_type = SND_SOC_I2C;
+
+        ret =  snd_soc_register_codec(&i2c->dev,
+                                      &soc_codec_dev_wm8737, &wm8737_dai, 1);
+        if (ret < 0)
+                kfree(wm8737);
+        return ret;
+
+}
+
+static __devexit int wm8737_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id wm8737_i2c_id[] = {
+        { "wm8737", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8737_i2c_id);
+
+static struct i2c_driver wm8737_i2c_driver = {
+        .driver = {
+                .name = "wm8737",
+                .owner = THIS_MODULE,
+        },
+        .probe =    wm8737_i2c_probe,
+        .remove =   __devexit_p(wm8737_i2c_remove),
+        .id_table = wm8737_i2c_id,
+};
+#endif
+
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8737_spi_probe(struct spi_device *spi)
+{
+        struct wm8737_priv *wm8737;
+        int ret;
+
+        wm8737 = kzalloc(sizeof(struct wm8737_priv), GFP_KERNEL);
+        if (wm8737 == NULL)
+                return -ENOMEM;
+
+        wm8737->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8737);
+
+        ret = snd_soc_register_codec(&spi->dev,
+                                     &soc_codec_dev_wm8737, &wm8737_dai, 1);
+        if (ret < 0)
+                kfree(wm8737);
+        return ret;
+}
+
+static int __devexit wm8737_spi_remove(struct spi_device *spi)
+{
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
+}
+
+static struct spi_driver wm8737_spi_driver = {
+        .driver = {
+                .name   = "wm8737",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = wm8737_spi_probe,
+        .remove         = __devexit_p(wm8737_spi_remove),
+};
+#endif /* CONFIG_SPI_MASTER */
+
+static int __init wm8737_modinit(void)
+{
+        int ret;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8737_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8737 I2C driver: %d\n",
+                       ret);
+        }
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        ret = spi_register_driver(&wm8737_spi_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8737 SPI driver: %d\n",
+                       ret);
+        }
+#endif
+        return 0;
+}
+module_init(wm8737_modinit);
+
+static void __exit wm8737_exit(void)
+{
+#if defined(CONFIG_SPI_MASTER)
+        spi_unregister_driver(&wm8737_spi_driver);
+#endif
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&wm8737_i2c_driver);
+#endif
+}
+module_exit(wm8737_exit);
+
+MODULE_DESCRIPTION("ASoC WM8737 driver");
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8737.h b/sound/soc/codecs/wm8737.h
new file mode 100644
index 000000000000..23d14c8ff6e7
--- /dev/null
+++ b/sound/soc/codecs/wm8737.h
@@ -0,0 +1,322 @@
+#ifndef _WM8737_H
+#define _WM8737_H
+
+/*
+ * wm8737.c  --  WM8523 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Register values.
+ */
+#define WM8737_LEFT_PGA_VOLUME                  0x00
+#define WM8737_RIGHT_PGA_VOLUME                 0x01
+#define WM8737_AUDIO_PATH_L                     0x02
+#define WM8737_AUDIO_PATH_R                     0x03
+#define WM8737_3D_ENHANCE                       0x04
+#define WM8737_ADC_CONTROL                      0x05
+#define WM8737_POWER_MANAGEMENT                 0x06
+#define WM8737_AUDIO_FORMAT                     0x07
+#define WM8737_CLOCKING                         0x08
+#define WM8737_MIC_PREAMP_CONTROL               0x09
+#define WM8737_MISC_BIAS_CONTROL                0x0A
+#define WM8737_NOISE_GATE                       0x0B
+#define WM8737_ALC1                             0x0C
+#define WM8737_ALC2                             0x0D
+#define WM8737_ALC3                             0x0E
+#define WM8737_RESET                            0x0F
+
+#define WM8737_REGISTER_COUNT                   16
+#define WM8737_MAX_REGISTER                     0x0F
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Left PGA volume
+ */
+#define WM8737_LVU                              0x0100  /* LVU */
+#define WM8737_LVU_MASK                         0x0100  /* LVU */
+#define WM8737_LVU_SHIFT                             8  /* LVU */
+#define WM8737_LVU_WIDTH                             1  /* LVU */
+#define WM8737_LINVOL_MASK                      0x00FF  /* LINVOL - [7:0] */
+#define WM8737_LINVOL_SHIFT                          0  /* LINVOL - [7:0] */
+#define WM8737_LINVOL_WIDTH                          8  /* LINVOL - [7:0] */
+
+/*
+ * R1 (0x01) - Right PGA volume
+ */
+#define WM8737_RVU                              0x0100  /* RVU */
+#define WM8737_RVU_MASK                         0x0100  /* RVU */
+#define WM8737_RVU_SHIFT                             8  /* RVU */
+#define WM8737_RVU_WIDTH                             1  /* RVU */
+#define WM8737_RINVOL_MASK                      0x00FF  /* RINVOL - [7:0] */
+#define WM8737_RINVOL_SHIFT                          0  /* RINVOL - [7:0] */
+#define WM8737_RINVOL_WIDTH                          8  /* RINVOL - [7:0] */
+
+/*
+ * R2 (0x02) - AUDIO path L
+ */
+#define WM8737_LINSEL_MASK                      0x0180  /* LINSEL - [8:7] */
+#define WM8737_LINSEL_SHIFT                          7  /* LINSEL - [8:7] */
+#define WM8737_LINSEL_WIDTH                          2  /* LINSEL - [8:7] */
+#define WM8737_LMICBOOST_MASK                   0x0060  /* LMICBOOST - [6:5] */
+#define WM8737_LMICBOOST_SHIFT                       5  /* LMICBOOST - [6:5] */
+#define WM8737_LMICBOOST_WIDTH                       2  /* LMICBOOST - [6:5] */
+#define WM8737_LMBE                             0x0010  /* LMBE */
+#define WM8737_LMBE_MASK                        0x0010  /* LMBE */
+#define WM8737_LMBE_SHIFT                            4  /* LMBE */
+#define WM8737_LMBE_WIDTH                            1  /* LMBE */
+#define WM8737_LMZC                             0x0008  /* LMZC */
+#define WM8737_LMZC_MASK                        0x0008  /* LMZC */
+#define WM8737_LMZC_SHIFT                            3  /* LMZC */
+#define WM8737_LMZC_WIDTH                            1  /* LMZC */
+#define WM8737_LPZC                             0x0004  /* LPZC */
+#define WM8737_LPZC_MASK                        0x0004  /* LPZC */
+#define WM8737_LPZC_SHIFT                            2  /* LPZC */
+#define WM8737_LPZC_WIDTH                            1  /* LPZC */
+#define WM8737_LZCTO_MASK                       0x0003  /* LZCTO - [1:0] */
+#define WM8737_LZCTO_SHIFT                           0  /* LZCTO - [1:0] */
+#define WM8737_LZCTO_WIDTH                           2  /* LZCTO - [1:0] */
+
+/*
+ * R3 (0x03) - AUDIO path R
+ */
+#define WM8737_RINSEL_MASK                      0x0180  /* RINSEL - [8:7] */
+#define WM8737_RINSEL_SHIFT                          7  /* RINSEL - [8:7] */
+#define WM8737_RINSEL_WIDTH                          2  /* RINSEL - [8:7] */
+#define WM8737_RMICBOOST_MASK                   0x0060  /* RMICBOOST - [6:5] */
+#define WM8737_RMICBOOST_SHIFT                       5  /* RMICBOOST - [6:5] */
+#define WM8737_RMICBOOST_WIDTH                       2  /* RMICBOOST - [6:5] */
+#define WM8737_RMBE                             0x0010  /* RMBE */
+#define WM8737_RMBE_MASK                        0x0010  /* RMBE */
+#define WM8737_RMBE_SHIFT                            4  /* RMBE */
+#define WM8737_RMBE_WIDTH                            1  /* RMBE */
+#define WM8737_RMZC                             0x0008  /* RMZC */
+#define WM8737_RMZC_MASK                        0x0008  /* RMZC */
+#define WM8737_RMZC_SHIFT                            3  /* RMZC */
+#define WM8737_RMZC_WIDTH                            1  /* RMZC */
+#define WM8737_RPZC                             0x0004  /* RPZC */
+#define WM8737_RPZC_MASK                        0x0004  /* RPZC */
+#define WM8737_RPZC_SHIFT                            2  /* RPZC */
+#define WM8737_RPZC_WIDTH                            1  /* RPZC */
+#define WM8737_RZCTO_MASK                       0x0003  /* RZCTO - [1:0] */
+#define WM8737_RZCTO_SHIFT                           0  /* RZCTO - [1:0] */
+#define WM8737_RZCTO_WIDTH                           2  /* RZCTO - [1:0] */
+
+/*
+ * R4 (0x04) - 3D Enhance
+ */
+#define WM8737_DIV2                             0x0080  /* DIV2 */
+#define WM8737_DIV2_MASK                        0x0080  /* DIV2 */
+#define WM8737_DIV2_SHIFT                            7  /* DIV2 */
+#define WM8737_DIV2_WIDTH                            1  /* DIV2 */
+#define WM8737_3DLC                             0x0040  /* 3DLC */
+#define WM8737_3DLC_MASK                        0x0040  /* 3DLC */
+#define WM8737_3DLC_SHIFT                            6  /* 3DLC */
+#define WM8737_3DLC_WIDTH                            1  /* 3DLC */
+#define WM8737_3DUC                             0x0020  /* 3DUC */
+#define WM8737_3DUC_MASK                        0x0020  /* 3DUC */
+#define WM8737_3DUC_SHIFT                            5  /* 3DUC */
+#define WM8737_3DUC_WIDTH                            1  /* 3DUC */
+#define WM8737_3DDEPTH_MASK                     0x001E  /* 3DDEPTH - [4:1] */
+#define WM8737_3DDEPTH_SHIFT                         1  /* 3DDEPTH - [4:1] */
+#define WM8737_3DDEPTH_WIDTH                         4  /* 3DDEPTH - [4:1] */
+#define WM8737_3DE                              0x0001  /* 3DE */
+#define WM8737_3DE_MASK                         0x0001  /* 3DE */
+#define WM8737_3DE_SHIFT                             0  /* 3DE */
+#define WM8737_3DE_WIDTH                             1  /* 3DE */
+
+/*
+ * R5 (0x05) - ADC Control
+ */
+#define WM8737_MONOMIX_MASK                     0x0180  /* MONOMIX - [8:7] */
+#define WM8737_MONOMIX_SHIFT                         7  /* MONOMIX - [8:7] */
+#define WM8737_MONOMIX_WIDTH                         2  /* MONOMIX - [8:7] */
+#define WM8737_POLARITY_MASK                    0x0060  /* POLARITY - [6:5] */
+#define WM8737_POLARITY_SHIFT                        5  /* POLARITY - [6:5] */
+#define WM8737_POLARITY_WIDTH                        2  /* POLARITY - [6:5] */
+#define WM8737_HPOR                             0x0010  /* HPOR */
+#define WM8737_HPOR_MASK                        0x0010  /* HPOR */
+#define WM8737_HPOR_SHIFT                            4  /* HPOR */
+#define WM8737_HPOR_WIDTH                            1  /* HPOR */
+#define WM8737_LP                               0x0004  /* LP */
+#define WM8737_LP_MASK                          0x0004  /* LP */
+#define WM8737_LP_SHIFT                              2  /* LP */
+#define WM8737_LP_WIDTH                              1  /* LP */
+#define WM8737_MONOUT                           0x0002  /* MONOUT */
+#define WM8737_MONOUT_MASK                      0x0002  /* MONOUT */
+#define WM8737_MONOUT_SHIFT                          1  /* MONOUT */
+#define WM8737_MONOUT_WIDTH                          1  /* MONOUT */
+#define WM8737_ADCHPD                           0x0001  /* ADCHPD */
+#define WM8737_ADCHPD_MASK                      0x0001  /* ADCHPD */
+#define WM8737_ADCHPD_SHIFT                          0  /* ADCHPD */
+#define WM8737_ADCHPD_WIDTH                          1  /* ADCHPD */
+
+/*
+ * R6 (0x06) - Power Management
+ */
+#define WM8737_VMID                             0x0100  /* VMID */
+#define WM8737_VMID_MASK                        0x0100  /* VMID */
+#define WM8737_VMID_SHIFT                            8  /* VMID */
+#define WM8737_VMID_WIDTH                            1  /* VMID */
+#define WM8737_VREF                             0x0080  /* VREF */
+#define WM8737_VREF_MASK                        0x0080  /* VREF */
+#define WM8737_VREF_SHIFT                            7  /* VREF */
+#define WM8737_VREF_WIDTH                            1  /* VREF */
+#define WM8737_AI                               0x0040  /* AI */
+#define WM8737_AI_MASK                          0x0040  /* AI */
+#define WM8737_AI_SHIFT                              6  /* AI */
+#define WM8737_AI_WIDTH                              1  /* AI */
+#define WM8737_PGL                              0x0020  /* PGL */
+#define WM8737_PGL_MASK                         0x0020  /* PGL */
+#define WM8737_PGL_SHIFT                             5  /* PGL */
+#define WM8737_PGL_WIDTH                             1  /* PGL */
+#define WM8737_PGR                              0x0010  /* PGR */
+#define WM8737_PGR_MASK                         0x0010  /* PGR */
+#define WM8737_PGR_SHIFT                             4  /* PGR */
+#define WM8737_PGR_WIDTH                             1  /* PGR */
+#define WM8737_ADL                              0x0008  /* ADL */
+#define WM8737_ADL_MASK                         0x0008  /* ADL */
+#define WM8737_ADL_SHIFT                             3  /* ADL */
+#define WM8737_ADL_WIDTH                             1  /* ADL */
+#define WM8737_ADR                              0x0004  /* ADR */
+#define WM8737_ADR_MASK                         0x0004  /* ADR */
+#define WM8737_ADR_SHIFT                             2  /* ADR */
+#define WM8737_ADR_WIDTH                             1  /* ADR */
+#define WM8737_MICBIAS_MASK                     0x0003  /* MICBIAS - [1:0] */
+#define WM8737_MICBIAS_SHIFT                         0  /* MICBIAS - [1:0] */
+#define WM8737_MICBIAS_WIDTH                         2  /* MICBIAS - [1:0] */
+
+/*
+ * R7 (0x07) - Audio Format
+ */
+#define WM8737_SDODIS                           0x0080  /* SDODIS */
+#define WM8737_SDODIS_MASK                      0x0080  /* SDODIS */
+#define WM8737_SDODIS_SHIFT                          7  /* SDODIS */
+#define WM8737_SDODIS_WIDTH                          1  /* SDODIS */
+#define WM8737_MS                               0x0040  /* MS */
+#define WM8737_MS_MASK                          0x0040  /* MS */
+#define WM8737_MS_SHIFT                              6  /* MS */
+#define WM8737_MS_WIDTH                              1  /* MS */
+#define WM8737_LRP                              0x0010  /* LRP */
+#define WM8737_LRP_MASK                         0x0010  /* LRP */
+#define WM8737_LRP_SHIFT                             4  /* LRP */
+#define WM8737_LRP_WIDTH                             1  /* LRP */
+#define WM8737_WL_MASK                          0x000C  /* WL - [3:2] */
+#define WM8737_WL_SHIFT                              2  /* WL - [3:2] */
+#define WM8737_WL_WIDTH                              2  /* WL - [3:2] */
+#define WM8737_FORMAT_MASK                      0x0003  /* FORMAT - [1:0] */
+#define WM8737_FORMAT_SHIFT                          0  /* FORMAT - [1:0] */
+#define WM8737_FORMAT_WIDTH                          2  /* FORMAT - [1:0] */
+
+/*
+ * R8 (0x08) - Clocking
+ */
+#define WM8737_AUTODETECT                       0x0080  /* AUTODETECT */
+#define WM8737_AUTODETECT_MASK                  0x0080  /* AUTODETECT */
+#define WM8737_AUTODETECT_SHIFT                      7  /* AUTODETECT */
+#define WM8737_AUTODETECT_WIDTH                      1  /* AUTODETECT */
+#define WM8737_CLKDIV2                          0x0040  /* CLKDIV2 */
+#define WM8737_CLKDIV2_MASK                     0x0040  /* CLKDIV2 */
+#define WM8737_CLKDIV2_SHIFT                         6  /* CLKDIV2 */
+#define WM8737_CLKDIV2_WIDTH                         1  /* CLKDIV2 */
+#define WM8737_SR_MASK                          0x003E  /* SR - [5:1] */
+#define WM8737_SR_SHIFT                              1  /* SR - [5:1] */
+#define WM8737_SR_WIDTH                              5  /* SR - [5:1] */
+#define WM8737_USB_MODE                         0x0001  /* USB MODE */
+#define WM8737_USB_MODE_MASK                    0x0001  /* USB MODE */
+#define WM8737_USB_MODE_SHIFT                        0  /* USB MODE */
+#define WM8737_USB_MODE_WIDTH                        1  /* USB MODE */
+
+/*
+ * R9 (0x09) - MIC Preamp Control
+ */
+#define WM8737_RBYPEN                           0x0008  /* RBYPEN */
+#define WM8737_RBYPEN_MASK                      0x0008  /* RBYPEN */
+#define WM8737_RBYPEN_SHIFT                          3  /* RBYPEN */
+#define WM8737_RBYPEN_WIDTH                          1  /* RBYPEN */
+#define WM8737_LBYPEN                           0x0004  /* LBYPEN */
+#define WM8737_LBYPEN_MASK                      0x0004  /* LBYPEN */
+#define WM8737_LBYPEN_SHIFT                          2  /* LBYPEN */
+#define WM8737_LBYPEN_WIDTH                          1  /* LBYPEN */
+#define WM8737_MBCTRL_MASK                      0x0003  /* MBCTRL - [1:0] */
+#define WM8737_MBCTRL_SHIFT                          0  /* MBCTRL - [1:0] */
+#define WM8737_MBCTRL_WIDTH                          2  /* MBCTRL - [1:0] */
+
+/*
+ * R10 (0x0A) - Misc Bias Control
+ */
+#define WM8737_VMIDSEL_MASK                     0x000C  /* VMIDSEL - [3:2] */
+#define WM8737_VMIDSEL_SHIFT                         2  /* VMIDSEL - [3:2] */
+#define WM8737_VMIDSEL_WIDTH                         2  /* VMIDSEL - [3:2] */
+#define WM8737_LINPUT1_DC_BIAS_ENABLE           0x0002  /* LINPUT1 DC BIAS ENABLE */
+#define WM8737_LINPUT1_DC_BIAS_ENABLE_MASK      0x0002  /* LINPUT1 DC BIAS ENABLE */
+#define WM8737_LINPUT1_DC_BIAS_ENABLE_SHIFT          1  /* LINPUT1 DC BIAS ENABLE */
+#define WM8737_LINPUT1_DC_BIAS_ENABLE_WIDTH          1  /* LINPUT1 DC BIAS ENABLE */
+#define WM8737_RINPUT1_DC_BIAS_ENABLE           0x0001  /* RINPUT1 DC BIAS ENABLE */
+#define WM8737_RINPUT1_DC_BIAS_ENABLE_MASK      0x0001  /* RINPUT1 DC BIAS ENABLE */
+#define WM8737_RINPUT1_DC_BIAS_ENABLE_SHIFT          0  /* RINPUT1 DC BIAS ENABLE */
+#define WM8737_RINPUT1_DC_BIAS_ENABLE_WIDTH          1  /* RINPUT1 DC BIAS ENABLE */
+
+/*
+ * R11 (0x0B) - Noise Gate
+ */
+#define WM8737_NGTH_MASK                        0x001C  /* NGTH - [4:2] */
+#define WM8737_NGTH_SHIFT                            2  /* NGTH - [4:2] */
+#define WM8737_NGTH_WIDTH                            3  /* NGTH - [4:2] */
+#define WM8737_NGAT                             0x0001  /* NGAT */
+#define WM8737_NGAT_MASK                        0x0001  /* NGAT */
+#define WM8737_NGAT_SHIFT                            0  /* NGAT */
+#define WM8737_NGAT_WIDTH                            1  /* NGAT */
+
+/*
+ * R12 (0x0C) - ALC1
+ */
+#define WM8737_ALCSEL_MASK                      0x0180  /* ALCSEL - [8:7] */
+#define WM8737_ALCSEL_SHIFT                          7  /* ALCSEL - [8:7] */
+#define WM8737_ALCSEL_WIDTH                          2  /* ALCSEL - [8:7] */
+#define WM8737_MAX_GAIN_MASK                    0x0070  /* MAX GAIN - [6:4] */
+#define WM8737_MAX_GAIN_SHIFT                        4  /* MAX GAIN - [6:4] */
+#define WM8737_MAX_GAIN_WIDTH                        3  /* MAX GAIN - [6:4] */
+#define WM8737_ALCL_MASK                        0x000F  /* ALCL - [3:0] */
+#define WM8737_ALCL_SHIFT                            0  /* ALCL - [3:0] */
+#define WM8737_ALCL_WIDTH                            4  /* ALCL - [3:0] */
+
+/*
+ * R13 (0x0D) - ALC2
+ */
+#define WM8737_ALCZCE                           0x0010  /* ALCZCE */
+#define WM8737_ALCZCE_MASK                      0x0010  /* ALCZCE */
+#define WM8737_ALCZCE_SHIFT                          4  /* ALCZCE */
+#define WM8737_ALCZCE_WIDTH                          1  /* ALCZCE */
+#define WM8737_HLD_MASK                         0x000F  /* HLD - [3:0] */
+#define WM8737_HLD_SHIFT                             0  /* HLD - [3:0] */
+#define WM8737_HLD_WIDTH                             4  /* HLD - [3:0] */
+
+/*
+ * R14 (0x0E) - ALC3
+ */
+#define WM8737_DCY_MASK                         0x00F0  /* DCY - [7:4] */
+#define WM8737_DCY_SHIFT                             4  /* DCY - [7:4] */
+#define WM8737_DCY_WIDTH                             4  /* DCY - [7:4] */
+#define WM8737_ATK_MASK                         0x000F  /* ATK - [3:0] */
+#define WM8737_ATK_SHIFT                             0  /* ATK - [3:0] */
+#define WM8737_ATK_WIDTH                             4  /* ATK - [3:0] */
+
+/*
+ * R15 (0x0F) - Reset
+ */
+#define WM8737_RESET_MASK                       0x01FF  /* RESET - [8:0] */
+#define WM8737_RESET_SHIFT                           0  /* RESET - [8:0] */
+#define WM8737_RESET_WIDTH                           9  /* RESET - [8:0] */
+
+#endif
diff --git a/sound/soc/codecs/wm8741.c b/sound/soc/codecs/wm8741.c
index b9ea8904ad4b..25af901fe813 100644
--- a/sound/soc/codecs/wm8741.c
+++ b/sound/soc/codecs/wm8741.c
@@ -24,31 +24,25 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
 #include "wm8741.h"
 
-static struct snd_soc_codec *wm8741_codec;
-struct snd_soc_codec_device soc_codec_dev_wm8741;
-
 #define WM8741_NUM_SUPPLIES 2
 static const char *wm8741_supply_names[WM8741_NUM_SUPPLIES] = {
         "AVDD",
         "DVDD",
 };
 
-#define WM8741_NUM_RATES 4
+#define WM8741_NUM_RATES 6
 
 /* codec private data */
 struct wm8741_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM8741_REGISTER_COUNT];
+        enum snd_soc_control_type control_type;
         struct regulator_bulk_data supplies[WM8741_NUM_SUPPLIES];
         unsigned int sysclk;
-        unsigned int rate_constraint_list[WM8741_NUM_RATES];
-        struct snd_pcm_hw_constraint_list rate_constraint;
+        struct snd_pcm_hw_constraint_list *sysclk_constraints;
 };
 
 static const u16 wm8741_reg_defaults[WM8741_REGISTER_COUNT] = {
@@ -99,10 +93,11 @@ static const struct snd_soc_dapm_route intercon[] = {
 
 static int wm8741_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8741_dapm_widgets,
-                                  ARRAY_SIZE(wm8741_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+        snd_soc_dapm_new_controls(dapm, wm8741_dapm_widgets,
+                                  ARRAY_SIZE(wm8741_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
 
         return 0;
 }
@@ -111,10 +106,84 @@ static struct {
         int value;
         int ratio;
 } lrclk_ratios[WM8741_NUM_RATES] = {
-        { 1, 256 },
-        { 2, 384 },
-        { 3, 512 },
-        { 4, 768 },
+        { 1, 128 },
+        { 2, 192 },
+        { 3, 256 },
+        { 4, 384 },
+        { 5, 512 },
+        { 6, 768 },
+};
+
+static unsigned int rates_11289[] = {
+        44100, 88235,
+};
+
+static struct snd_pcm_hw_constraint_list constraints_11289 = {
+        .count  = ARRAY_SIZE(rates_11289),
+        .list   = rates_11289,
+};
+
+static unsigned int rates_12288[] = {
+        32000, 48000, 96000,
+};
+
+static struct snd_pcm_hw_constraint_list constraints_12288 = {
+        .count  = ARRAY_SIZE(rates_12288),
+        .list   = rates_12288,
+};
+
+static unsigned int rates_16384[] = {
+        32000,
+};
+
+static struct snd_pcm_hw_constraint_list constraints_16384 = {
+        .count  = ARRAY_SIZE(rates_16384),
+        .list   = rates_16384,
+};
+
+static unsigned int rates_16934[] = {
+        44100, 88235,
+};
+
+static struct snd_pcm_hw_constraint_list constraints_16934 = {
+        .count  = ARRAY_SIZE(rates_16934),
+        .list   = rates_16934,
+};
+
+static unsigned int rates_18432[] = {
+        48000, 96000,
+};
+
+static struct snd_pcm_hw_constraint_list constraints_18432 = {
+        .count  = ARRAY_SIZE(rates_18432),
+        .list   = rates_18432,
+};
+
+static unsigned int rates_22579[] = {
+        44100, 88235, 1764000
+};
+
+static struct snd_pcm_hw_constraint_list constraints_22579 = {
+        .count  = ARRAY_SIZE(rates_22579),
+        .list   = rates_22579,
+};
+
+static unsigned int rates_24576[] = {
+        32000, 48000, 96000, 192000
+};
+
+static struct snd_pcm_hw_constraint_list constraints_24576 = {
+        .count  = ARRAY_SIZE(rates_24576),
+        .list   = rates_24576,
+};
+
+static unsigned int rates_36864[] = {
+        48000, 96000, 19200
+};
+
+static struct snd_pcm_hw_constraint_list constraints_36864 = {
+        .count  = ARRAY_SIZE(rates_36864),
+        .list   = rates_36864,
 };
 
 
@@ -135,7 +204,7 @@ static int wm8741_startup(struct snd_pcm_substream *substream,
 
         snd_pcm_hw_constraint_list(substream->runtime, 0,
                                    SNDRV_PCM_HW_PARAM_RATE,
-                                   &wm8741->rate_constraint);
+                                   wm8741->sysclk_constraints);
 
         return 0;
 }
@@ -145,8 +214,7 @@ static int wm8741_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);
         u16 iface = snd_soc_read(codec, WM8741_FORMAT_CONTROL) & 0x1FC;
         int i;
@@ -196,47 +264,52 @@ static int wm8741_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 {
         struct snd_soc_codec *codec = codec_dai->codec;
         struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);
-        unsigned int val;
-        int i;
 
         dev_dbg(codec->dev, "wm8741_set_dai_sysclk info: freq=%dHz\n", freq);
 
-        wm8741->sysclk = freq;
-
-        wm8741->rate_constraint.count = 0;
-
-        for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
-                dev_dbg(codec->dev, "index = %d, ratio = %d, freq = %d",
-                                i, lrclk_ratios[i].ratio, freq);
-
-                val = freq / lrclk_ratios[i].ratio;
-                /* Check that it's a standard rate since core can't
-                 * cope with others and having the odd rates confuses
-                 * constraint matching.
-                 */
-                switch (val) {
-                case 32000:
-                case 44100:
-                case 48000:
-                case 64000:
-                case 88200:
-                case 96000:
-                        dev_dbg(codec->dev, "Supported sample rate: %dHz\n",
-                                val);
-                        wm8741->rate_constraint_list[i] = val;
-                        wm8741->rate_constraint.count++;
-                        break;
-                default:
-                        dev_dbg(codec->dev, "Skipping sample rate: %dHz\n",
-                                val);
-                }
+        switch (freq) {
+        case 11289600:
+                wm8741->sysclk_constraints = &constraints_11289;
+                wm8741->sysclk = freq;
+                return 0;
+
+        case 12288000:
+                wm8741->sysclk_constraints = &constraints_12288;
+                wm8741->sysclk = freq;
+                return 0;
+
+        case 16384000:
+                wm8741->sysclk_constraints = &constraints_16384;
+                wm8741->sysclk = freq;
+                return 0;
+
+        case 16934400:
+                wm8741->sysclk_constraints = &constraints_16934;
+                wm8741->sysclk = freq;
+                return 0;
+
+        case 18432000:
+                wm8741->sysclk_constraints = &constraints_18432;
+                wm8741->sysclk = freq;
+                return 0;
+
+        case 22579200:
+        case 33868800:
+                wm8741->sysclk_constraints = &constraints_22579;
+                wm8741->sysclk = freq;
+                return 0;
+
+        case 24576000:
+                wm8741->sysclk_constraints = &constraints_24576;
+                wm8741->sysclk = freq;
+                return 0;
+
+        case 36864000:
+                wm8741->sysclk_constraints = &constraints_36864;
+                wm8741->sysclk = freq;
+                return 0;
         }
-
-        /* Need at least one supported rate... */
-        if (wm8741->rate_constraint.count == 0)
-                return -EINVAL;
-
-        return 0;
+        return -EINVAL;
 }
 
 static int wm8741_set_dai_fmt(struct snd_soc_dai *codec_dai,
@@ -314,8 +387,8 @@ static struct snd_soc_dai_ops wm8741_dai_ops = {
         .set_fmt        = wm8741_set_dai_fmt,
 };
 
-struct snd_soc_dai wm8741_dai = {
-        .name = "WM8741",
+static struct snd_soc_dai_driver wm8741_dai = {
+        .name = "wm8741",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,  /* Mono modes not yet supported */
@@ -325,13 +398,10 @@ struct snd_soc_dai wm8741_dai = {
         },
         .ops = &wm8741_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8741_dai);
 
 #ifdef CONFIG_PM
-static int wm8741_resume(struct platform_device *pdev)
+static int wm8741_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         u16 *cache = codec->reg_cache;
         int i;
 
@@ -348,189 +418,103 @@ static int wm8741_resume(struct platform_device *pdev)
 #define wm8741_resume NULL
 #endif
 
-static int wm8741_probe(struct platform_device *pdev)
+static int wm8741_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
+        struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);
         int ret = 0;
 
-        if (wm8741_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8741->control_type);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
-        socdev->card->codec = wm8741_codec;
-        codec = wm8741_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+        ret = wm8741_reset(codec);
         if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
+                dev_err(codec->dev, "Failed to issue reset\n");
+                return ret;
         }
 
+        /* Change some default settings - latch VU */
+        snd_soc_update_bits(codec, WM8741_DACLLSB_ATTENUATION,
+                            WM8741_UPDATELL, WM8741_UPDATELL);
+        snd_soc_update_bits(codec, WM8741_DACLMSB_ATTENUATION,
+                            WM8741_UPDATELM, WM8741_UPDATELM);
+        snd_soc_update_bits(codec, WM8741_DACRLSB_ATTENUATION,
+                            WM8741_UPDATERL, WM8741_UPDATERL);
+        snd_soc_update_bits(codec, WM8741_DACRLSB_ATTENUATION,
+                            WM8741_UPDATERM, WM8741_UPDATERM);
+
         snd_soc_add_controls(codec, wm8741_snd_controls,
                              ARRAY_SIZE(wm8741_snd_controls));
         wm8741_add_widgets(codec);
 
+        dev_dbg(codec->dev, "Successful registration\n");
         return ret;
-
-pcm_err:
-        return ret;
-}
-
-static int wm8741_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_wm8741 = {
+static struct snd_soc_codec_driver soc_codec_dev_wm8741 = {
         .probe =        wm8741_probe,
-        .remove =       wm8741_remove,
         .resume =       wm8741_resume,
+        .reg_cache_size = ARRAY_SIZE(wm8741_reg_defaults),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8741_reg_defaults,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8741);
 
-static int wm8741_register(struct wm8741_priv *wm8741,
-                           enum snd_soc_control_type control)
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static int wm8741_i2c_probe(struct i2c_client *i2c,
+                            const struct i2c_device_id *id)
 {
-        int ret;
-        struct snd_soc_codec *codec = &wm8741->codec;
-        int i;
-
-        if (wm8741_codec) {
-                dev_err(codec->dev, "Another WM8741 is registered\n");
-                return -EINVAL;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8741);
-        codec->name = "WM8741";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = NULL;
-        codec->dai = &wm8741_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8741_REGISTER_COUNT;
-        codec->reg_cache = &wm8741->reg_cache;
-
-        wm8741->rate_constraint.list = &wm8741->rate_constraint_list[0];
-        wm8741->rate_constraint.count =
-                ARRAY_SIZE(wm8741->rate_constraint_list);
-
-        memcpy(codec->reg_cache, wm8741_reg_defaults,
-                sizeof(wm8741->reg_cache));
+        struct wm8741_priv *wm8741;
+        int ret, i;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
-        }
+        wm8741 = kzalloc(sizeof(struct wm8741_priv), GFP_KERNEL);
+        if (wm8741 == NULL)
+                return -ENOMEM;
 
         for (i = 0; i < ARRAY_SIZE(wm8741->supplies); i++)
                 wm8741->supplies[i].supply = wm8741_supply_names[i];
 
-        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8741->supplies),
+        ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8741->supplies),
                                  wm8741->supplies);
         if (ret != 0) {
-                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
                 goto err;
         }
 
         ret = regulator_bulk_enable(ARRAY_SIZE(wm8741->supplies),
                                     wm8741->supplies);
         if (ret != 0) {
-                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
                 goto err_get;
         }
 
-        ret = wm8741_reset(codec);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to issue reset\n");
-                goto err_enable;
-        }
-
-        wm8741_dai.dev = codec->dev;
-
-        /* Change some default settings - latch VU */
-        wm8741->reg_cache[WM8741_DACLLSB_ATTENUATION] |= WM8741_UPDATELL;
-        wm8741->reg_cache[WM8741_DACLMSB_ATTENUATION] |= WM8741_UPDATELM;
-        wm8741->reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERL;
-        wm8741->reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERM;
-
-        wm8741_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                return ret;
-        }
-
-        ret = snd_soc_register_dai(&wm8741_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                snd_soc_unregister_codec(codec);
-                return ret;
-        }
+        i2c_set_clientdata(i2c, wm8741);
+        wm8741->control_type = SND_SOC_I2C;
 
-        dev_dbg(codec->dev, "Successful registration\n");
-        return 0;
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8741, &wm8741_dai, 1);
+        if (ret < 0)
+                goto err_enable;
+        return ret;
 
 err_enable:
         regulator_bulk_disable(ARRAY_SIZE(wm8741->supplies), wm8741->supplies);
 
 err_get:
         regulator_bulk_free(ARRAY_SIZE(wm8741->supplies), wm8741->supplies);
-
 err:
         kfree(wm8741);
         return ret;
 }
 
-static void wm8741_unregister(struct wm8741_priv *wm8741)
-{
-        regulator_bulk_free(ARRAY_SIZE(wm8741->supplies), wm8741->supplies);
-
-        snd_soc_unregister_dai(&wm8741_dai);
-        snd_soc_unregister_codec(&wm8741->codec);
-        kfree(wm8741);
-        wm8741_codec = NULL;
-}
-
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-static __devinit int wm8741_i2c_probe(struct i2c_client *i2c,
-                                      const struct i2c_device_id *id)
-{
-        struct wm8741_priv *wm8741;
-        struct snd_soc_codec *codec;
-
-        wm8741 = kzalloc(sizeof(struct wm8741_priv), GFP_KERNEL);
-        if (wm8741 == NULL)
-                return -ENOMEM;
-
-        codec = &wm8741->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
-        i2c_set_clientdata(i2c, wm8741);
-        codec->control_data = i2c;
-
-        codec->dev = &i2c->dev;
-
-        return wm8741_register(wm8741, SND_SOC_I2C);
-}
-
-static __devexit int wm8741_i2c_remove(struct i2c_client *client)
+static int wm8741_i2c_remove(struct i2c_client *client)
 {
         struct wm8741_priv *wm8741 = i2c_get_clientdata(client);
-        wm8741_unregister(wm8741);
+
+        snd_soc_unregister_codec(&client->dev);
+        regulator_bulk_free(ARRAY_SIZE(wm8741->supplies), wm8741->supplies);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -540,29 +524,28 @@ static const struct i2c_device_id wm8741_i2c_id[] = {
 };
 MODULE_DEVICE_TABLE(i2c, wm8741_i2c_id);
 
-
 static struct i2c_driver wm8741_i2c_driver = {
         .driver = {
-                .name = "WM8741",
+                .name = "wm8741-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8741_i2c_probe,
-        .remove =   __devexit_p(wm8741_i2c_remove),
+        .remove =   wm8741_i2c_remove,
         .id_table = wm8741_i2c_id,
 };
 #endif
 
 static int __init wm8741_modinit(void)
 {
-        int ret;
+        int ret = 0;
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8741_i2c_driver);
-        if (ret != 0) {
-                printk(KERN_ERR "Failed to register WM8741 I2C driver: %d\n",
-                       ret);
-        }
+        if (ret != 0)
+                pr_err("Failed to register WM8741 I2C driver: %d\n", ret);
 #endif
-        return 0;
+
+        return ret;
 }
 module_init(wm8741_modinit);
 
diff --git a/sound/soc/codecs/wm8741.h b/sound/soc/codecs/wm8741.h
index fdef6ecd1f6f..56c1b1d4a681 100644
--- a/sound/soc/codecs/wm8741.h
+++ b/sound/soc/codecs/wm8741.h
@@ -208,7 +208,4 @@
 
 #define  WM8741_SYSCLK 0
 
-extern struct snd_soc_dai wm8741_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8741;
-
 #endif
diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c
index e2c05e3e323a..38f38fddd190 100644
--- a/sound/soc/codecs/wm8750.c
+++ b/sound/soc/codecs/wm8750.c
@@ -25,7 +25,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 
 #include "wm8750.h"
@@ -52,8 +51,7 @@ static const u16 wm8750_reg[] = {
 /* codec private data */
 struct wm8750_priv {
         unsigned int sysclk;
-        struct snd_soc_codec codec;
-        u16 reg_cache[ARRAY_SIZE(wm8750_reg)];
+        enum snd_soc_control_type control_type;
 };
 
 #define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0)
@@ -399,10 +397,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8750_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8750_dapm_widgets,
-                                  ARRAY_SIZE(wm8750_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, wm8750_dapm_widgets,
+                                  ARRAY_SIZE(wm8750_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -560,8 +559,7 @@ static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
                                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8750_priv *wm8750 = snd_soc_codec_get_drvdata(codec);
         u16 iface = snd_soc_read(codec, WM8750_IFACE) & 0x1f3;
         u16 srate = snd_soc_read(codec, WM8750_SRATE) & 0x1c0;
@@ -616,7 +614,7 @@ static int wm8750_set_bias_level(struct snd_soc_codec *codec,
         case SND_SOC_BIAS_PREPARE:
                 break;
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Set VMID to 5k */
                         snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x01c1);
 
@@ -631,7 +629,7 @@ static int wm8750_set_bias_level(struct snd_soc_codec *codec,
                 snd_soc_write(codec, WM8750_PWR1, 0x0001);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -649,8 +647,8 @@ static struct snd_soc_dai_ops wm8750_dai_ops = {
         .set_sysclk     = wm8750_set_dai_sysclk,
 };
 
-struct snd_soc_dai wm8750_dai = {
-        .name = "WM8750",
+static struct snd_soc_dai_driver wm8750_dai = {
+        .name = "wm8750-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -665,21 +663,15 @@ struct snd_soc_dai wm8750_dai = {
                 .formats = WM8750_FORMATS,},
         .ops = &wm8750_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8750_dai);
 
-static int wm8750_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8750_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8750_resume(struct platform_device *pdev)
+static int wm8750_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -698,100 +690,21 @@ static int wm8750_resume(struct platform_device *pdev)
         return 0;
 }
 
-static struct snd_soc_codec *wm8750_codec;
-
-static int wm8750_probe(struct platform_device *pdev)
+static int wm8750_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (!wm8750_codec) {
-                dev_err(&pdev->dev, "WM8750 codec not yet registered\n");
-                return -EINVAL;
-        }
-
-        socdev->card->codec = wm8750_codec;
-        codec = wm8750_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "wm8750: failed to create pcms\n");
-                goto err;
-        }
-
-        snd_soc_add_controls(codec, wm8750_snd_controls,
-                                ARRAY_SIZE(wm8750_snd_controls));
-        wm8750_add_widgets(codec);
-
-        return 0;
-
-err:
-        return ret;
-}
-
-/* power down chip */
-static int wm8750_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8750 = {
-        .probe          = wm8750_probe,
-        .remove         = wm8750_remove,
-        .suspend        = wm8750_suspend,
-        .resume         = wm8750_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8750);
-
-/*
- * initialise the WM8750 driver
- * register the mixer and dsp interfaces with the kernel
- */
-static int wm8750_register(struct wm8750_priv *wm8750,
-                        enum snd_soc_control_type control)
-{
-        struct snd_soc_codec *codec = &wm8750->codec;
-        int reg, ret = 0;
-
-        if (wm8750_codec) {
-                dev_err(codec->dev, "Multiple WM8750 devices not supported\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "WM8750";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_STANDBY;
-        codec->set_bias_level = wm8750_set_bias_level;
-        codec->dai = &wm8750_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(wm8750->reg_cache) + 1;
-        codec->reg_cache = &wm8750->reg_cache;
-        snd_soc_codec_set_drvdata(codec, wm8750);
-
-        memcpy(codec->reg_cache, wm8750_reg, sizeof(wm8750->reg_cache));
+        struct wm8750_priv *wm8750 = snd_soc_codec_get_drvdata(codec);
+        int reg, ret;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8750->control_type);
         if (ret < 0) {
                 printk(KERN_ERR "wm8750: failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = wm8750_reset(codec);
         if (ret < 0) {
                 printk(KERN_ERR "wm8750: failed to reset: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         /* charge output caps */
@@ -815,150 +728,130 @@ static int wm8750_register(struct wm8750_priv *wm8750,
         reg = snd_soc_read(codec, WM8750_RINVOL);
         snd_soc_write(codec, WM8750_RINVOL, reg | 0x0100);
 
-        wm8750_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dais(&wm8750_dai, 1);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
-                goto err_codec;
-        }
-
-        return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8750);
+        snd_soc_add_controls(codec, wm8750_snd_controls,
+                                ARRAY_SIZE(wm8750_snd_controls));
+        wm8750_add_widgets(codec);
         return ret;
 }
 
-static void wm8750_unregister(struct wm8750_priv *wm8750)
+static int wm8750_remove(struct snd_soc_codec *codec)
 {
-        wm8750_set_bias_level(&wm8750->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dais(&wm8750_dai, 1);
-        snd_soc_unregister_codec(&wm8750->codec);
-        kfree(wm8750);
-        wm8750_codec = NULL;
+        wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-
-/*
- * WM8750 2 wire address is determined by GPIO5
- * state during powerup.
- *    low  = 0x1a
- *    high = 0x1b
- */
+static struct snd_soc_codec_driver soc_codec_dev_wm8750 = {
+        .probe =        wm8750_probe,
+        .remove =       wm8750_remove,
+        .suspend =      wm8750_suspend,
+        .resume =       wm8750_resume,
+        .set_bias_level = wm8750_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8750_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8750_reg,
+};
 
-static int wm8750_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8750_spi_probe(struct spi_device *spi)
 {
-        struct snd_soc_codec *codec;
         struct wm8750_priv *wm8750;
+        int ret;
 
         wm8750 = kzalloc(sizeof(struct wm8750_priv), GFP_KERNEL);
         if (wm8750 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8750->codec;
-        codec->control_data = i2c;
-        i2c_set_clientdata(i2c, wm8750);
-
-        codec->dev = &i2c->dev;
+        wm8750->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8750);
 
-        return wm8750_register(wm8750, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8750, &wm8750_dai, 1);
+        if (ret < 0)
+                kfree(wm8750);
+        return ret;
 }
 
-static int wm8750_i2c_remove(struct i2c_client *client)
+static int __devexit wm8750_spi_remove(struct spi_device *spi)
 {
-        struct wm8750_priv *wm8750 = i2c_get_clientdata(client);
-        wm8750_unregister(wm8750);
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
 }
 
-static const struct i2c_device_id wm8750_i2c_id[] = {
-        { "wm8750", 0 },
-        { "wm8987", 0 }, /* WM8987 is register compatible with WM8750 */
-        { }
-};
-MODULE_DEVICE_TABLE(i2c, wm8750_i2c_id);
-
-static struct i2c_driver wm8750_i2c_driver = {
+static struct spi_driver wm8750_spi_driver = {
         .driver = {
-                .name = "WM8750 I2C Codec",
-                .owner = THIS_MODULE,
+                .name   = "wm8750-codec",
+                .owner  = THIS_MODULE,
         },
-        .probe =    wm8750_i2c_probe,
-        .remove =   wm8750_i2c_remove,
-        .id_table = wm8750_i2c_id,
+        .probe          = wm8750_spi_probe,
+        .remove         = __devexit_p(wm8750_spi_remove),
 };
-#endif
+#endif /* CONFIG_SPI_MASTER */
 
-#if defined(CONFIG_SPI_MASTER)
-static int __devinit wm8750_spi_probe(struct spi_device *spi)
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8750_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
-        struct snd_soc_codec *codec;
         struct wm8750_priv *wm8750;
+        int ret;
 
         wm8750 = kzalloc(sizeof(struct wm8750_priv), GFP_KERNEL);
         if (wm8750 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8750->codec;
-        codec->control_data = spi;
-        codec->dev = &spi->dev;
-
-        dev_set_drvdata(&spi->dev, wm8750);
+        i2c_set_clientdata(i2c, wm8750);
+        wm8750->control_type = SND_SOC_I2C;
 
-        return wm8750_register(wm8750, SND_SOC_SPI);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8750, &wm8750_dai, 1);
+        if (ret < 0)
+                kfree(wm8750);
+        return ret;
 }
 
-static int __devexit wm8750_spi_remove(struct spi_device *spi)
+static __devexit int wm8750_i2c_remove(struct i2c_client *client)
 {
-        struct wm8750_priv *wm8750 = dev_get_drvdata(&spi->dev);
-        wm8750_unregister(wm8750);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
-static const struct spi_device_id wm8750_spi_id[] = {
+static const struct i2c_device_id wm8750_i2c_id[] = {
         { "wm8750", 0 },
         { "wm8987", 0 },
         { }
 };
-MODULE_DEVICE_TABLE(spi, wm8750_spi_id);
+MODULE_DEVICE_TABLE(i2c, wm8750_i2c_id);
 
-static struct spi_driver wm8750_spi_driver = {
+static struct i2c_driver wm8750_i2c_driver = {
         .driver = {
-                .name   = "WM8750 SPI Codec",
-                .bus    = &spi_bus_type,
-                .owner  = THIS_MODULE,
+                .name = "wm8750-codec",
+                .owner = THIS_MODULE,
         },
-        .probe          = wm8750_spi_probe,
-        .remove         = __devexit_p(wm8750_spi_remove),
-        .id_table       = wm8750_spi_id,
+        .probe =    wm8750_i2c_probe,
+        .remove =   __devexit_p(wm8750_i2c_remove),
+        .id_table = wm8750_i2c_id,
 };
 #endif
 
 static int __init wm8750_modinit(void)
 {
-        int ret;
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8750_i2c_driver);
-        if (ret != 0)
-                pr_err("Failed to register WM8750 I2C driver: %d\n", ret);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8750 I2C driver: %d\n",
+                       ret);
+        }
 #endif
 #if defined(CONFIG_SPI_MASTER)
         ret = spi_register_driver(&wm8750_spi_driver);
-        if (ret != 0)
-                pr_err("Failed to register WM8750 SPI driver: %d\n", ret);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8750 SPI driver: %d\n",
+                       ret);
+        }
 #endif
-        return 0;
+        return ret;
 }
 module_init(wm8750_modinit);
 
diff --git a/sound/soc/codecs/wm8750.h b/sound/soc/codecs/wm8750.h
index 1dc100e19cfe..121427c047fb 100644
--- a/sound/soc/codecs/wm8750.h
+++ b/sound/soc/codecs/wm8750.h
@@ -57,13 +57,4 @@
 
 #define WM8750_SYSCLK   0
 
-struct wm8750_setup_data {
-        int spi;
-        int i2c_bus;
-        unsigned short i2c_address;
-};
-
-extern struct snd_soc_dai wm8750_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8750;
-
 #endif
diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c
index b59f349c5218..ffa2ffe5ec11 100644
--- a/sound/soc/codecs/wm8753.c
+++ b/sound/soc/codecs/wm8753.c
@@ -45,7 +45,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 #include <asm/div64.h>
@@ -56,8 +55,10 @@ static int caps_charge = 2000;
 module_param(caps_charge, int, 0);
 MODULE_PARM_DESC(caps_charge, "WM8753 cap charge time (msecs)");
 
-static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
-        unsigned int mode);
+static int wm8753_hifi_write_dai_fmt(struct snd_soc_codec *codec,
+                unsigned int fmt);
+static int wm8753_voice_write_dai_fmt(struct snd_soc_codec *codec,
+                unsigned int fmt);
 
 /*
  * wm8753 register cache
@@ -65,79 +66,37 @@ static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
  * are using 2 wire for device control, so we cache them instead.
  */
 static const u16 wm8753_reg[] = {
-        0x0008, 0x0000, 0x000a, 0x000a,
-        0x0033, 0x0000, 0x0007, 0x00ff,
-        0x00ff, 0x000f, 0x000f, 0x007b,
-        0x0000, 0x0032, 0x0000, 0x00c3,
-        0x00c3, 0x00c0, 0x0000, 0x0000,
+        0x0000, 0x0008, 0x0000, 0x000a,
+        0x000a, 0x0033, 0x0000, 0x0007,
+        0x00ff, 0x00ff, 0x000f, 0x000f,
+        0x007b, 0x0000, 0x0032, 0x0000,
+        0x00c3, 0x00c3, 0x00c0, 0x0000,
         0x0000, 0x0000, 0x0000, 0x0000,
         0x0000, 0x0000, 0x0000, 0x0000,
-        0x0000, 0x0000, 0x0000, 0x0055,
-        0x0005, 0x0050, 0x0055, 0x0050,
-        0x0055, 0x0050, 0x0055, 0x0079,
-        0x0079, 0x0079, 0x0079, 0x0079,
         0x0000, 0x0000, 0x0000, 0x0000,
-        0x0097, 0x0097, 0x0000, 0x0004,
-        0x0000, 0x0083, 0x0024, 0x01ba,
-        0x0000, 0x0083, 0x0024, 0x01ba,
-        0x0000, 0x0000, 0x0000
+        0x0055, 0x0005, 0x0050, 0x0055,
+        0x0050, 0x0055, 0x0050, 0x0055,
+        0x0079, 0x0079, 0x0079, 0x0079,
+        0x0079, 0x0000, 0x0000, 0x0000,
+        0x0000, 0x0097, 0x0097, 0x0000,
+        0x0004, 0x0000, 0x0083, 0x0024,
+        0x01ba, 0x0000, 0x0083, 0x0024,
+        0x01ba, 0x0000, 0x0000, 0x0000
 };
 
 /* codec private data */
 struct wm8753_priv {
+        enum snd_soc_control_type control_type;
         unsigned int sysclk;
         unsigned int pcmclk;
-        struct snd_soc_codec codec;
-        u16 reg_cache[ARRAY_SIZE(wm8753_reg)];
-};
-
-/*
- * read wm8753 register cache
- */
-static inline unsigned int wm8753_read_reg_cache(struct snd_soc_codec *codec,
-        unsigned int reg)
-{
-        u16 *cache = codec->reg_cache;
-        if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1))
-                return -1;
-        return cache[reg - 1];
-}
-
-/*
- * write wm8753 register cache
- */
-static inline void wm8753_write_reg_cache(struct snd_soc_codec *codec,
-        unsigned int reg, unsigned int value)
-{
-        u16 *cache = codec->reg_cache;
-        if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1))
-                return;
-        cache[reg - 1] = value;
-}
-
-/*
- * write to the WM8753 register space
- */
-static int wm8753_write(struct snd_soc_codec *codec, unsigned int reg,
-        unsigned int value)
-{
-        u8 data[2];
 
-        /* data is
-         *   D15..D9 WM8753 register offset
-         *   D8...D0 register data
-         */
-        data[0] = (reg << 1) | ((value >> 8) & 0x0001);
-        data[1] = value & 0x00ff;
+        unsigned int voice_fmt;
+        unsigned int hifi_fmt;
 
-        wm8753_write_reg_cache(codec, reg, value);
-        if (codec->hw_write(codec->control_data, data, 2) == 2)
-                return 0;
-        else
-                return -EIO;
-}
+        int dai_func;
+};
 
-#define wm8753_reset(c) wm8753_write(c, WM8753_RESET, 0)
+#define wm8753_reset(c) snd_soc_write(c, WM8753_RESET, 0)
 
 /*
  * WM8753 Controls
@@ -217,9 +176,9 @@ static int wm8753_get_dai(struct snd_kcontrol *kcontrol,
         struct snd_ctl_elem_value *ucontrol)
 {
         struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
-        int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL);
+        struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
 
-        ucontrol->value.integer.value[0] = (mode & 0xc) >> 2;
+        ucontrol->value.integer.value[0] = wm8753->dai_func;
         return 0;
 }
 
@@ -227,16 +186,26 @@ static int wm8753_set_dai(struct snd_kcontrol *kcontrol,
         struct snd_ctl_elem_value *ucontrol)
 {
         struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
-        int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL);
+        struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
+        u16 ioctl;
 
-        if (((mode & 0xc) >> 2) == ucontrol->value.integer.value[0])
-                return 0;
+        if (codec->active)
+                return -EBUSY;
+
+        ioctl = snd_soc_read(codec, WM8753_IOCTL);
+
+        wm8753->dai_func = ucontrol->value.integer.value[0];
+
+        if (((ioctl >> 2) & 0x3) == wm8753->dai_func)
+                return 1;
 
-        mode &= 0xfff3;
-        mode |= (ucontrol->value.integer.value[0] << 2);
+        ioctl = (ioctl & 0x1f3) | (wm8753->dai_func << 2);
+        snd_soc_write(codec, WM8753_IOCTL, ioctl);
+
+
+        wm8753_hifi_write_dai_fmt(codec, wm8753->hifi_fmt);
+        wm8753_voice_write_dai_fmt(codec, wm8753->voice_fmt);
 
-        wm8753_write(codec, WM8753_IOCTL, mode);
-        wm8753_set_dai_mode(codec, ucontrol->value.integer.value[0]);
         return 1;
 }
 
@@ -669,10 +638,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8753_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8753_dapm_widgets,
-                                  ARRAY_SIZE(wm8753_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, wm8753_dapm_widgets,
+                                  ARRAY_SIZE(wm8753_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -737,17 +707,17 @@ static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
         if (pll_id == WM8753_PLL1) {
                 offset = 0;
                 enable = 0x10;
-                reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xffef;
+                reg = snd_soc_read(codec, WM8753_CLOCK) & 0xffef;
         } else {
                 offset = 4;
                 enable = 0x8;
-                reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfff7;
+                reg = snd_soc_read(codec, WM8753_CLOCK) & 0xfff7;
         }
 
         if (!freq_in || !freq_out) {
                 /* disable PLL  */
-                wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0026);
-                wm8753_write(codec, WM8753_CLOCK, reg);
+                snd_soc_write(codec, WM8753_PLL1CTL1 + offset, 0x0026);
+                snd_soc_write(codec, WM8753_CLOCK, reg);
                 return 0;
         } else {
                 u16 value = 0;
@@ -758,20 +728,20 @@ static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
                 /* set up N and K PLL divisor ratios */
                 /* bits 8:5 = PLL_N, bits 3:0 = PLL_K[21:18] */
                 value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18);
-                wm8753_write(codec, WM8753_PLL1CTL2 + offset, value);
+                snd_soc_write(codec, WM8753_PLL1CTL2 + offset, value);
 
                 /* bits 8:0 = PLL_K[17:9] */
                 value = (pll_div.k & 0x03fe00) >> 9;
-                wm8753_write(codec, WM8753_PLL1CTL3 + offset, value);
+                snd_soc_write(codec, WM8753_PLL1CTL3 + offset, value);
 
                 /* bits 8:0 = PLL_K[8:0] */
                 value = pll_div.k & 0x0001ff;
-                wm8753_write(codec, WM8753_PLL1CTL4 + offset, value);
+                snd_soc_write(codec, WM8753_PLL1CTL4 + offset, value);
 
                 /* set PLL as input and enable */
-                wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 |
+                snd_soc_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 |
                         (pll_div.div2 << 3));
-                wm8753_write(codec, WM8753_CLOCK, reg | enable);
+                snd_soc_write(codec, WM8753_CLOCK, reg | enable);
         }
         return 0;
 }
@@ -874,11 +844,10 @@ static int wm8753_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 /*
  * Set's ADC and Voice DAC format.
  */
-static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_dai *codec_dai,
+static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_codec *codec,
                 unsigned int fmt)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
-        u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01ec;
+        u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01ec;
 
         /* interface format */
         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -900,7 +869,7 @@ static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_dai *codec_dai,
                 return -EINVAL;
         }
 
-        wm8753_write(codec, WM8753_PCM, voice);
+        snd_soc_write(codec, WM8753_PCM, voice);
         return 0;
 }
 
@@ -912,11 +881,10 @@ static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
                                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
-        u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01f3;
-        u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x017f;
+        u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01f3;
+        u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x017f;
 
         /* bit size */
         switch (params_format(params)) {
@@ -936,23 +904,22 @@ static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
         /* sample rate */
         if (params_rate(params) * 384 == wm8753->pcmclk)
                 srate |= 0x80;
-        wm8753_write(codec, WM8753_SRATE1, srate);
+        snd_soc_write(codec, WM8753_SRATE1, srate);
 
-        wm8753_write(codec, WM8753_PCM, voice);
+        snd_soc_write(codec, WM8753_PCM, voice);
         return 0;
 }
 
 /*
  * Set's PCM dai fmt and BCLK.
  */
-static int wm8753_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
+static int wm8753_pcm_set_dai_fmt(struct snd_soc_codec *codec,
                 unsigned int fmt)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
         u16 voice, ioctl;
 
-        voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x011f;
-        ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x015d;
+        voice = snd_soc_read(codec, WM8753_PCM) & 0x011f;
+        ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x015d;
 
         /* set master/slave audio interface */
         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1006,8 +973,8 @@ static int wm8753_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
                 return -EINVAL;
         }
 
-        wm8753_write(codec, WM8753_PCM, voice);
-        wm8753_write(codec, WM8753_IOCTL, ioctl);
+        snd_soc_write(codec, WM8753_PCM, voice);
+        snd_soc_write(codec, WM8753_IOCTL, ioctl);
         return 0;
 }
 
@@ -1019,16 +986,16 @@ static int wm8753_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 
         switch (div_id) {
         case WM8753_PCMDIV:
-                reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0x003f;
-                wm8753_write(codec, WM8753_CLOCK, reg | div);
+                reg = snd_soc_read(codec, WM8753_CLOCK) & 0x003f;
+                snd_soc_write(codec, WM8753_CLOCK, reg | div);
                 break;
         case WM8753_BCLKDIV:
-                reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x01c7;
-                wm8753_write(codec, WM8753_SRATE2, reg | div);
+                reg = snd_soc_read(codec, WM8753_SRATE2) & 0x01c7;
+                snd_soc_write(codec, WM8753_SRATE2, reg | div);
                 break;
         case WM8753_VXCLKDIV:
-                reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x003f;
-                wm8753_write(codec, WM8753_SRATE2, reg | div);
+                reg = snd_soc_read(codec, WM8753_SRATE2) & 0x003f;
+                snd_soc_write(codec, WM8753_SRATE2, reg | div);
                 break;
         default:
                 return -EINVAL;
@@ -1039,11 +1006,10 @@ static int wm8753_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 /*
  * Set's HiFi DAC format.
  */
-static int wm8753_hdac_set_dai_fmt(struct snd_soc_dai *codec_dai,
+static int wm8753_hdac_set_dai_fmt(struct snd_soc_codec *codec,
                 unsigned int fmt)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
-        u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01e0;
+        u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01e0;
 
         /* interface format */
         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -1065,21 +1031,20 @@ static int wm8753_hdac_set_dai_fmt(struct snd_soc_dai *codec_dai,
                 return -EINVAL;
         }
 
-        wm8753_write(codec, WM8753_HIFI, hifi);
+        snd_soc_write(codec, WM8753_HIFI, hifi);
         return 0;
 }
 
 /*
  * Set's I2S DAI format.
  */
-static int wm8753_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
+static int wm8753_i2s_set_dai_fmt(struct snd_soc_codec *codec,
                 unsigned int fmt)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
         u16 ioctl, hifi;
 
-        hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x011f;
-        ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x00ae;
+        hifi = snd_soc_read(codec, WM8753_HIFI) & 0x011f;
+        ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x00ae;
 
         /* set master/slave audio interface */
         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1133,8 +1098,8 @@ static int wm8753_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
                 return -EINVAL;
         }
 
-        wm8753_write(codec, WM8753_HIFI, hifi);
-        wm8753_write(codec, WM8753_IOCTL, ioctl);
+        snd_soc_write(codec, WM8753_HIFI, hifi);
+        snd_soc_write(codec, WM8753_IOCTL, ioctl);
         return 0;
 }
 
@@ -1146,11 +1111,10 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
                                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
-        u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x01c0;
-        u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01f3;
+        u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x01c0;
+        u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01f3;
         int coeff;
 
         /* is digital filter coefficient valid ? */
@@ -1159,7 +1123,7 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
                 printk(KERN_ERR "wm8753 invalid MCLK or rate\n");
                 return coeff;
         }
-        wm8753_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) |
+        snd_soc_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) |
                 coeff_div[coeff].usb);
 
         /* bit size */
@@ -1177,81 +1141,137 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
                 break;
         }
 
-        wm8753_write(codec, WM8753_HIFI, hifi);
+        snd_soc_write(codec, WM8753_HIFI, hifi);
         return 0;
 }
 
-static int wm8753_mode1v_set_dai_fmt(struct snd_soc_dai *codec_dai,
+static int wm8753_mode1v_set_dai_fmt(struct snd_soc_codec *codec,
                 unsigned int fmt)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
         u16 clock;
 
         /* set clk source as pcmclk */
-        clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
-        wm8753_write(codec, WM8753_CLOCK, clock);
+        clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
+        snd_soc_write(codec, WM8753_CLOCK, clock);
 
-        if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
-                return -EINVAL;
-        return wm8753_pcm_set_dai_fmt(codec_dai, fmt);
+        return wm8753_vdac_adc_set_dai_fmt(codec, fmt);
 }
 
-static int wm8753_mode1h_set_dai_fmt(struct snd_soc_dai *codec_dai,
+static int wm8753_mode1h_set_dai_fmt(struct snd_soc_codec *codec,
                 unsigned int fmt)
 {
-        if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0)
-                return -EINVAL;
-        return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
+        return wm8753_hdac_set_dai_fmt(codec, fmt);
 }
 
-static int wm8753_mode2_set_dai_fmt(struct snd_soc_dai *codec_dai,
+static int wm8753_mode2_set_dai_fmt(struct snd_soc_codec *codec,
                 unsigned int fmt)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
         u16 clock;
 
         /* set clk source as pcmclk */
-        clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
-        wm8753_write(codec, WM8753_CLOCK, clock);
+        clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
+        snd_soc_write(codec, WM8753_CLOCK, clock);
 
-        if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
-                return -EINVAL;
-        return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
+        return wm8753_vdac_adc_set_dai_fmt(codec, fmt);
 }
 
-static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_dai *codec_dai,
+static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_codec *codec,
                 unsigned int fmt)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
         u16 clock;
 
         /* set clk source as mclk */
-        clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
-        wm8753_write(codec, WM8753_CLOCK, clock | 0x4);
+        clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
+        snd_soc_write(codec, WM8753_CLOCK, clock | 0x4);
 
-        if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0)
-                return -EINVAL;
-        if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
+        if (wm8753_hdac_set_dai_fmt(codec, fmt) < 0)
                 return -EINVAL;
-        return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
+        return wm8753_vdac_adc_set_dai_fmt(codec, fmt);
+}
+
+static int wm8753_hifi_write_dai_fmt(struct snd_soc_codec *codec,
+                unsigned int fmt)
+{
+        struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
+        int ret = 0;
+
+        switch (wm8753->dai_func) {
+        case 0:
+                ret = wm8753_mode1h_set_dai_fmt(codec, fmt);
+                break;
+        case 1:
+                ret = wm8753_mode2_set_dai_fmt(codec, fmt);
+                break;
+        case 2:
+        case 3:
+                ret = wm8753_mode3_4_set_dai_fmt(codec, fmt);
+                break;
+        default:
+                 break;
+        }
+        if (ret)
+                return ret;
+
+        return wm8753_i2s_set_dai_fmt(codec, fmt);
 }
 
+static int wm8753_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
+
+        wm8753->hifi_fmt = fmt;
+
+        return wm8753_hifi_write_dai_fmt(codec, fmt);
+};
+
+static int wm8753_voice_write_dai_fmt(struct snd_soc_codec *codec,
+                unsigned int fmt)
+{
+        struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
+        int ret = 0;
+
+        if (wm8753->dai_func != 0)
+                return 0;
+
+        ret = wm8753_mode1v_set_dai_fmt(codec, fmt);
+        if (ret)
+                return ret;
+        ret = wm8753_pcm_set_dai_fmt(codec, fmt);
+        if (ret)
+                return ret;
+
+        return 0;
+};
+
+static int wm8753_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
+
+        wm8753->voice_fmt = fmt;
+
+        return wm8753_voice_write_dai_fmt(codec, fmt);
+};
+
 static int wm8753_mute(struct snd_soc_dai *dai, int mute)
 {
         struct snd_soc_codec *codec = dai->codec;
-        u16 mute_reg = wm8753_read_reg_cache(codec, WM8753_DAC) & 0xfff7;
+        u16 mute_reg = snd_soc_read(codec, WM8753_DAC) & 0xfff7;
+        struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
 
         /* the digital mute covers the HiFi and Voice DAC's on the WM8753.
          * make sure we check if they are not both active when we mute */
-        if (mute && dai->id == 1) {
-                if (!wm8753_dai[WM8753_DAI_VOICE].playback.active ||
-                        !wm8753_dai[WM8753_DAI_HIFI].playback.active)
-                        wm8753_write(codec, WM8753_DAC, mute_reg | 0x8);
+        if (mute && wm8753->dai_func == 1) {
+                if (!codec->active)
+                        snd_soc_write(codec, WM8753_DAC, mute_reg | 0x8);
         } else {
                 if (mute)
-                        wm8753_write(codec, WM8753_DAC, mute_reg | 0x8);
+                        snd_soc_write(codec, WM8753_DAC, mute_reg | 0x8);
                 else
-                        wm8753_write(codec, WM8753_DAC, mute_reg);
+                        snd_soc_write(codec, WM8753_DAC, mute_reg);
         }
 
         return 0;
@@ -1260,26 +1280,26 @@ static int wm8753_mute(struct snd_soc_dai *dai, int mute)
 static int wm8753_set_bias_level(struct snd_soc_codec *codec,
                                  enum snd_soc_bias_level level)
 {
-        u16 pwr_reg = wm8753_read_reg_cache(codec, WM8753_PWR1) & 0xfe3e;
+        u16 pwr_reg = snd_soc_read(codec, WM8753_PWR1) & 0xfe3e;
 
         switch (level) {
         case SND_SOC_BIAS_ON:
                 /* set vmid to 50k and unmute dac */
-                wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x00c0);
+                snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x00c0);
                 break;
         case SND_SOC_BIAS_PREPARE:
                 /* set vmid to 5k for quick power up */
-                wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x01c1);
+                snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x01c1);
                 break;
         case SND_SOC_BIAS_STANDBY:
                 /* mute dac and set vmid to 500k, enable VREF */
-                wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x0141);
+                snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x0141);
                 break;
         case SND_SOC_BIAS_OFF:
-                wm8753_write(codec, WM8753_PWR1, 0x0001);
+                snd_soc_write(codec, WM8753_PWR1, 0x0001);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -1292,7 +1312,7 @@ static int wm8753_set_bias_level(struct snd_soc_codec *codec,
         SNDRV_PCM_FMTBIT_S24_LE)
 
 /*
- * The WM8753 supports upto 4 different and mutually exclusive DAI
+ * The WM8753 supports up to 4 different and mutually exclusive DAI
  * configurations. This gives 2 PCM's available for use, hifi and voice.
  * NOTE: The Voice PCM cannot play or capture audio to the CPU as it's DAI
  * is connected between the wm8753 and a BT codec or GSM modem.
@@ -1302,452 +1322,237 @@ static int wm8753_set_bias_level(struct snd_soc_codec *codec,
  * 3. Voice disabled - HIFI over HIFI
  * 4. Voice disabled - HIFI over HIFI, uses voice DAI LRC for capture
  */
-static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode1 = {
+static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode = {
         .hw_params      = wm8753_i2s_hw_params,
         .digital_mute   = wm8753_mute,
-        .set_fmt        = wm8753_mode1h_set_dai_fmt,
-        .set_clkdiv     = wm8753_set_dai_clkdiv,
-        .set_pll        = wm8753_set_dai_pll,
-        .set_sysclk     = wm8753_set_dai_sysclk,
-};
-
-static struct snd_soc_dai_ops wm8753_dai_ops_voice_mode1 = {
-        .hw_params      = wm8753_pcm_hw_params,
-        .digital_mute   = wm8753_mute,
-        .set_fmt        = wm8753_mode1v_set_dai_fmt,
+        .set_fmt        = wm8753_hifi_set_dai_fmt,
         .set_clkdiv     = wm8753_set_dai_clkdiv,
         .set_pll        = wm8753_set_dai_pll,
         .set_sysclk     = wm8753_set_dai_sysclk,
 };
 
-static struct snd_soc_dai_ops wm8753_dai_ops_voice_mode2 = {
+static struct snd_soc_dai_ops wm8753_dai_ops_voice_mode = {
         .hw_params      = wm8753_pcm_hw_params,
         .digital_mute   = wm8753_mute,
-        .set_fmt        = wm8753_mode2_set_dai_fmt,
+        .set_fmt        = wm8753_voice_set_dai_fmt,
         .set_clkdiv     = wm8753_set_dai_clkdiv,
         .set_pll        = wm8753_set_dai_pll,
         .set_sysclk     = wm8753_set_dai_sysclk,
 };
 
-static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode3 = {
-        .hw_params      = wm8753_i2s_hw_params,
-        .digital_mute   = wm8753_mute,
-        .set_fmt        = wm8753_mode3_4_set_dai_fmt,
-        .set_clkdiv     = wm8753_set_dai_clkdiv,
-        .set_pll        = wm8753_set_dai_pll,
-        .set_sysclk     = wm8753_set_dai_sysclk,
-};
-
-static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode4 = {
-        .hw_params      = wm8753_i2s_hw_params,
-        .digital_mute   = wm8753_mute,
-        .set_fmt        = wm8753_mode3_4_set_dai_fmt,
-        .set_clkdiv     = wm8753_set_dai_clkdiv,
-        .set_pll        = wm8753_set_dai_pll,
-        .set_sysclk     = wm8753_set_dai_sysclk,
-};
-
-static const struct snd_soc_dai wm8753_all_dai[] = {
+static struct snd_soc_dai_driver wm8753_dai[] = {
 /* DAI HiFi mode 1 */
-{       .name = "WM8753 HiFi",
-        .id = 1,
+{       .name = "wm8753-hifi",
         .playback = {
                 .stream_name = "HiFi Playback",
                 .channels_min = 1,
                 .channels_max = 2,
                 .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS},
+                .formats = WM8753_FORMATS
+        },
         .capture = { /* dummy for fast DAI switching */
                 .stream_name = "Capture",
                 .channels_min = 1,
                 .channels_max = 2,
                 .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS},
-        .ops = &wm8753_dai_ops_hifi_mode1,
+                .formats = WM8753_FORMATS
+        },
+        .ops = &wm8753_dai_ops_hifi_mode,
 },
 /* DAI Voice mode 1 */
-{       .name = "WM8753 Voice",
-        .id = 1,
+{       .name = "wm8753-voice",
         .playback = {
                 .stream_name = "Voice Playback",
                 .channels_min = 1,
                 .channels_max = 1,
                 .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS,},
-        .capture = {
-                .stream_name = "Capture",
-                .channels_min = 1,
-                .channels_max = 2,
-                .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS,},
-        .ops = &wm8753_dai_ops_voice_mode1,
-},
-/* DAI HiFi mode 2 - dummy */
-{       .name = "WM8753 HiFi",
-        .id = 2,
-},
-/* DAI Voice mode 2 */
-{       .name = "WM8753 Voice",
-        .id = 2,
-        .playback = {
-                .stream_name = "Voice Playback",
-                .channels_min = 1,
-                .channels_max = 1,
-                .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS,},
-        .capture = {
-                .stream_name = "Capture",
-                .channels_min = 1,
-                .channels_max = 2,
-                .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS,},
-        .ops = &wm8753_dai_ops_voice_mode2,
-},
-/* DAI HiFi mode 3 */
-{       .name = "WM8753 HiFi",
-        .id = 3,
-        .playback = {
-                .stream_name = "HiFi Playback",
-                .channels_min = 1,
-                .channels_max = 2,
-                .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS,},
-        .capture = {
-                .stream_name = "Capture",
-                .channels_min = 1,
-                .channels_max = 2,
-                .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS,},
-        .ops = &wm8753_dai_ops_hifi_mode3,
-},
-/* DAI Voice mode 3 - dummy */
-{       .name = "WM8753 Voice",
-        .id = 3,
-},
-/* DAI HiFi mode 4 */
-{       .name = "WM8753 HiFi",
-        .id = 4,
-        .playback = {
-                .stream_name = "HiFi Playback",
-                .channels_min = 1,
-                .channels_max = 2,
-                .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS,},
+                .formats = WM8753_FORMATS,
+        },
         .capture = {
                 .stream_name = "Capture",
                 .channels_min = 1,
                 .channels_max = 2,
                 .rates = WM8753_RATES,
-                .formats = WM8753_FORMATS,},
-        .ops = &wm8753_dai_ops_hifi_mode4,
-},
-/* DAI Voice mode 4 - dummy */
-{       .name = "WM8753 Voice",
-        .id = 4,
-},
-};
-
-struct snd_soc_dai wm8753_dai[] = {
-        {
-                .name = "WM8753 DAI 0",
-        },
-        {
-                .name = "WM8753 DAI 1",
+                .formats = WM8753_FORMATS,
         },
+        .ops = &wm8753_dai_ops_voice_mode,
+},
 };
-EXPORT_SYMBOL_GPL(wm8753_dai);
-
-static void wm8753_set_dai_mode(struct snd_soc_codec *codec, unsigned int mode)
-{
-        if (mode < 4) {
-                int playback_active, capture_active, codec_active, pop_wait;
-                void *private_data;
-                struct list_head list;
-
-                playback_active = wm8753_dai[0].playback.active;
-                capture_active = wm8753_dai[0].capture.active;
-                codec_active = wm8753_dai[0].active;
-                private_data = wm8753_dai[0].private_data;
-                pop_wait = wm8753_dai[0].pop_wait;
-                list = wm8753_dai[0].list;
-                wm8753_dai[0] = wm8753_all_dai[mode << 1];
-                wm8753_dai[0].playback.active = playback_active;
-                wm8753_dai[0].capture.active = capture_active;
-                wm8753_dai[0].active = codec_active;
-                wm8753_dai[0].private_data = private_data;
-                wm8753_dai[0].pop_wait = pop_wait;
-                wm8753_dai[0].list = list;
-
-                playback_active = wm8753_dai[1].playback.active;
-                capture_active = wm8753_dai[1].capture.active;
-                codec_active = wm8753_dai[1].active;
-                private_data = wm8753_dai[1].private_data;
-                pop_wait = wm8753_dai[1].pop_wait;
-                list = wm8753_dai[1].list;
-                wm8753_dai[1] = wm8753_all_dai[(mode << 1) + 1];
-                wm8753_dai[1].playback.active = playback_active;
-                wm8753_dai[1].capture.active = capture_active;
-                wm8753_dai[1].active = codec_active;
-                wm8753_dai[1].private_data = private_data;
-                wm8753_dai[1].pop_wait = pop_wait;
-                wm8753_dai[1].list = list;
-        }
-        wm8753_dai[0].codec = codec;
-        wm8753_dai[1].codec = codec;
-}
 
 static void wm8753_work(struct work_struct *work)
 {
-        struct snd_soc_codec *codec =
-                container_of(work, struct snd_soc_codec, delayed_work.work);
-        wm8753_set_bias_level(codec, codec->bias_level);
+        struct snd_soc_dapm_context *dapm =
+                container_of(work, struct snd_soc_dapm_context,
+                             delayed_work.work);
+        struct snd_soc_codec *codec = dapm->codec;
+        wm8753_set_bias_level(codec, dapm->bias_level);
 }
 
-static int wm8753_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8753_resume(struct platform_device *pdev)
+static int wm8753_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
+        u16 *reg_cache = codec->reg_cache;
         int i;
-        u8 data[2];
-        u16 *cache = codec->reg_cache;
 
         /* Sync reg_cache with the hardware */
-        for (i = 0; i < ARRAY_SIZE(wm8753_reg); i++) {
-                if (i + 1 == WM8753_RESET)
+        for (i = 1; i < ARRAY_SIZE(wm8753_reg); i++) {
+                if (i == WM8753_RESET)
                         continue;
 
                 /* No point in writing hardware default values back */
-                if (cache[i] == wm8753_reg[i])
+                if (reg_cache[i] == wm8753_reg[i])
                         continue;
 
-                data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
-                data[1] = cache[i] & 0x00ff;
-                codec->hw_write(codec->control_data, data, 2);
+                snd_soc_write(codec, i, reg_cache[i]);
         }
 
         wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         /* charge wm8753 caps */
-        if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
+        if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) {
                 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
-                codec->bias_level = SND_SOC_BIAS_ON;
-                schedule_delayed_work(&codec->delayed_work,
+                codec->dapm.bias_level = SND_SOC_BIAS_ON;
+                schedule_delayed_work(&codec->dapm.delayed_work,
                         msecs_to_jiffies(caps_charge));
         }
 
         return 0;
 }
 
-static struct snd_soc_codec *wm8753_codec;
-
-static int wm8753_probe(struct platform_device *pdev)
+static int wm8753_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (!wm8753_codec) {
-                dev_err(&pdev->dev, "WM8753 codec not yet registered\n");
-                return -EINVAL;
-        }
+        struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
+        int ret;
 
-        socdev->card->codec = wm8753_codec;
-        codec = wm8753_codec;
+        INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8753_work);
 
-        wm8753_set_dai_mode(codec, 0);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8753->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+        ret = wm8753_reset(codec);
         if (ret < 0) {
-                printk(KERN_ERR "wm8753: failed to create pcms\n");
-                goto pcm_err;
+                dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
+                return ret;
         }
 
+        wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        wm8753->dai_func = 0;
+
+        /* charge output caps */
+        wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
+        schedule_delayed_work(&codec->dapm.delayed_work,
+                              msecs_to_jiffies(caps_charge));
+
+        /* set the update bits */
+        snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_LOUT1V, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_ROUT1V, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_LOUT2V, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_ROUT2V, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_LINVOL, 0x0100, 0x0100);
+        snd_soc_update_bits(codec, WM8753_RINVOL, 0x0100, 0x0100);
+
         snd_soc_add_controls(codec, wm8753_snd_controls,
                              ARRAY_SIZE(wm8753_snd_controls));
         wm8753_add_widgets(codec);
 
         return 0;
-
-pcm_err:
-        return ret;
-}
-
-/*
- * This function forces any delayed work to be queued and run.
- */
-static int run_delayed_work(struct delayed_work *dwork)
-{
-        int ret;
-
-        /* cancel any work waiting to be queued. */
-        ret = cancel_delayed_work(dwork);
-
-        /* if there was any work waiting then we run it now and
-         * wait for it's completion */
-        if (ret) {
-                schedule_delayed_work(dwork, 0);
-                flush_scheduled_work();
-        }
-        return ret;
 }
 
 /* power down chip */
-static int wm8753_remove(struct platform_device *pdev)
+static int wm8753_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
+        flush_delayed_work_sync(&codec->dapm.delayed_work);
+        wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_wm8753 = {
-        .probe =        wm8753_probe,
-        .remove =       wm8753_remove,
-        .suspend =      wm8753_suspend,
+static struct snd_soc_codec_driver soc_codec_dev_wm8753 = {
+        .probe =        wm8753_probe,
+        .remove =       wm8753_remove,
+        .suspend =      wm8753_suspend,
         .resume =       wm8753_resume,
+        .set_bias_level = wm8753_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8753_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8753_reg,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8753);
 
-static int wm8753_register(struct wm8753_priv *wm8753)
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8753_spi_probe(struct spi_device *spi)
 {
-        int ret, i;
-        struct snd_soc_codec *codec = &wm8753->codec;
-        u16 reg;
-
-        if (wm8753_codec) {
-                dev_err(codec->dev, "Multiple WM8753 devices not supported\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "WM8753";
-        codec->owner = THIS_MODULE;
-        codec->read = wm8753_read_reg_cache;
-        codec->write = wm8753_write;
-        codec->bias_level = SND_SOC_BIAS_STANDBY;
-        codec->set_bias_level = wm8753_set_bias_level;
-        codec->dai = wm8753_dai;
-        codec->num_dai = 2;
-        codec->reg_cache_size = ARRAY_SIZE(wm8753->reg_cache) + 1;
-        codec->reg_cache = &wm8753->reg_cache;
-        snd_soc_codec_set_drvdata(codec, wm8753);
-
-        memcpy(codec->reg_cache, wm8753_reg, sizeof(wm8753->reg_cache));
-        INIT_DELAYED_WORK(&codec->delayed_work, wm8753_work);
-
-        ret = wm8753_reset(codec);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to issue reset\n");
-                goto err;
-        }
-
-        /* charge output caps */
-        wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
-        schedule_delayed_work(&codec->delayed_work,
-                              msecs_to_jiffies(caps_charge));
-
-        /* set the update bits */
-        reg = wm8753_read_reg_cache(codec, WM8753_LDAC);
-        wm8753_write(codec, WM8753_LDAC, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_RDAC);
-        wm8753_write(codec, WM8753_RDAC, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_LADC);
-        wm8753_write(codec, WM8753_LADC, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_RADC);
-        wm8753_write(codec, WM8753_RADC, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_LOUT1V);
-        wm8753_write(codec, WM8753_LOUT1V, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_ROUT1V);
-        wm8753_write(codec, WM8753_ROUT1V, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_LOUT2V);
-        wm8753_write(codec, WM8753_LOUT2V, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_ROUT2V);
-        wm8753_write(codec, WM8753_ROUT2V, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_LINVOL);
-        wm8753_write(codec, WM8753_LINVOL, reg | 0x0100);
-        reg = wm8753_read_reg_cache(codec, WM8753_RINVOL);
-        wm8753_write(codec, WM8753_RINVOL, reg | 0x0100);
-
-        wm8753_codec = codec;
-
-        for (i = 0; i < ARRAY_SIZE(wm8753_dai); i++)
-                wm8753_dai[i].dev = codec->dev;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
+        struct wm8753_priv *wm8753;
+        int ret;
 
-        ret = snd_soc_register_dais(&wm8753_dai[0], ARRAY_SIZE(wm8753_dai));
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
-                goto err_codec;
-        }
+        wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
+        if (wm8753 == NULL)
+                return -ENOMEM;
 
-        return 0;
+        wm8753->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8753);
 
-err_codec:
-        run_delayed_work(&codec->delayed_work);
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8753);
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8753, wm8753_dai, ARRAY_SIZE(wm8753_dai));
+        if (ret < 0)
+                kfree(wm8753);
         return ret;
 }
 
-static void wm8753_unregister(struct wm8753_priv *wm8753)
+static int __devexit wm8753_spi_remove(struct spi_device *spi)
 {
-        wm8753_set_bias_level(&wm8753->codec, SND_SOC_BIAS_OFF);
-        run_delayed_work(&wm8753->codec.delayed_work);
-        snd_soc_unregister_dais(&wm8753_dai[0], ARRAY_SIZE(wm8753_dai));
-        snd_soc_unregister_codec(&wm8753->codec);
-        kfree(wm8753);
-        wm8753_codec = NULL;
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
 }
 
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static struct spi_driver wm8753_spi_driver = {
+        .driver = {
+                .name   = "wm8753-codec",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = wm8753_spi_probe,
+        .remove         = __devexit_p(wm8753_spi_remove),
+};
+#endif /* CONFIG_SPI_MASTER */
 
-static int wm8753_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8753_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
-        struct snd_soc_codec *codec;
         struct wm8753_priv *wm8753;
+        int ret;
 
         wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
         if (wm8753 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8753->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-        codec->control_data = i2c;
-        i2c_set_clientdata(i2c, wm8753);
-
-        codec->dev = &i2c->dev;
+        i2c_set_clientdata(i2c, wm8753);
+        wm8753->control_type = SND_SOC_I2C;
 
-        return wm8753_register(wm8753);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8753, wm8753_dai, ARRAY_SIZE(wm8753_dai));
+        if (ret < 0)
+                kfree(wm8753);
+        return ret;
 }
 
-static int wm8753_i2c_remove(struct i2c_client *client)
+static __devexit int wm8753_i2c_remove(struct i2c_client *client)
 {
-        struct wm8753_priv *wm8753 = i2c_get_clientdata(client);
-        wm8753_unregister(wm8753);
-        return 0;
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
 }
 
 static const struct i2c_device_id wm8753_i2c_id[] = {
@@ -1758,91 +1563,33 @@ MODULE_DEVICE_TABLE(i2c, wm8753_i2c_id);
 
 static struct i2c_driver wm8753_i2c_driver = {
         .driver = {
-                .name = "wm8753",
+                .name = "wm8753-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8753_i2c_probe,
-        .remove =   wm8753_i2c_remove,
+        .remove =   __devexit_p(wm8753_i2c_remove),
         .id_table = wm8753_i2c_id,
 };
 #endif
 
-#if defined(CONFIG_SPI_MASTER)
-static int wm8753_spi_write(struct spi_device *spi, const char *data, int len)
-{
-        struct spi_transfer t;
-        struct spi_message m;
-        u8 msg[2];
-
-        if (len <= 0)
-                return 0;
-
-        msg[0] = data[0];
-        msg[1] = data[1];
-
-        spi_message_init(&m);
-        memset(&t, 0, (sizeof t));
-
-        t.tx_buf = &msg[0];
-        t.len = len;
-
-        spi_message_add_tail(&t, &m);
-        spi_sync(spi, &m);
-
-        return len;
-}
-
-static int __devinit wm8753_spi_probe(struct spi_device *spi)
-{
-        struct snd_soc_codec *codec;
-        struct wm8753_priv *wm8753;
-
-        wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
-        if (wm8753 == NULL)
-                return -ENOMEM;
-
-        codec = &wm8753->codec;
-        codec->control_data = spi;
-        codec->hw_write = (hw_write_t)wm8753_spi_write;
-        codec->dev = &spi->dev;
-
-        dev_set_drvdata(&spi->dev, wm8753);
-
-        return wm8753_register(wm8753);
-}
-
-static int __devexit wm8753_spi_remove(struct spi_device *spi)
-{
-        struct wm8753_priv *wm8753 = dev_get_drvdata(&spi->dev);
-        wm8753_unregister(wm8753);
-        return 0;
-}
-
-static struct spi_driver wm8753_spi_driver = {
-        .driver = {
-                .name   = "wm8753",
-                .bus    = &spi_bus_type,
-                .owner  = THIS_MODULE,
-        },
-        .probe          = wm8753_spi_probe,
-        .remove         = __devexit_p(wm8753_spi_remove),
-};
-#endif
-
 static int __init wm8753_modinit(void)
 {
-        int ret;
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8753_i2c_driver);
-        if (ret != 0)
-                pr_err("Failed to register WM8753 I2C driver: %d\n", ret);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8753 I2C driver: %d\n",
+                       ret);
+        }
 #endif
 #if defined(CONFIG_SPI_MASTER)
         ret = spi_register_driver(&wm8753_spi_driver);
-        if (ret != 0)
-                pr_err("Failed to register WM8753 SPI driver: %d\n", ret);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8753 SPI driver: %d\n",
+                       ret);
+        }
 #endif
-        return 0;
+        return ret;
 }
 module_init(wm8753_modinit);
 
diff --git a/sound/soc/codecs/wm8753.h b/sound/soc/codecs/wm8753.h
index 57b2ba244040..94edac144bcb 100644
--- a/sound/soc/codecs/wm8753.h
+++ b/sound/soc/codecs/wm8753.h
@@ -115,7 +115,4 @@
 #define WM8753_DAI_HIFI         0
 #define WM8753_DAI_VOICE                1
 
-extern struct snd_soc_dai wm8753_dai[2];
-extern struct snd_soc_codec_device soc_codec_dev_wm8753;
-
 #endif
diff --git a/sound/soc/codecs/wm8770.c b/sound/soc/codecs/wm8770.c
new file mode 100644
index 000000000000..19b92baa9e8c
--- /dev/null
+++ b/sound/soc/codecs/wm8770.c
@@ -0,0 +1,749 @@
+/*
+ * wm8770.c  --  WM8770 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "wm8770.h"
+
+#define WM8770_NUM_SUPPLIES 3
+static const char *wm8770_supply_names[WM8770_NUM_SUPPLIES] = {
+        "AVDD1",
+        "AVDD2",
+        "DVDD"
+};
+
+static const u16 wm8770_reg_defs[WM8770_CACHEREGNUM] = {
+        0x7f, 0x7f, 0x7f, 0x7f,
+        0x7f, 0x7f, 0x7f, 0x7f,
+        0x7f, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0, 0x90, 0,
+        0, 0x22, 0x22, 0x3e,
+        0xc, 0xc, 0x100, 0x189,
+        0x189, 0x8770
+};
+
+struct wm8770_priv {
+        enum snd_soc_control_type control_type;
+        struct regulator_bulk_data supplies[WM8770_NUM_SUPPLIES];
+        struct notifier_block disable_nb[WM8770_NUM_SUPPLIES];
+        struct snd_soc_codec *codec;
+        int sysclk;
+};
+
+static int vout12supply_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event);
+static int vout34supply_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event);
+
+/*
+ * We can't use the same notifier block for more than one supply and
+ * there's no way I can see to get from a callback to the caller
+ * except container_of().
+ */
+#define WM8770_REGULATOR_EVENT(n) \
+static int wm8770_regulator_event_##n(struct notifier_block *nb, \
+                                      unsigned long event, void *data)    \
+{ \
+        struct wm8770_priv *wm8770 = container_of(nb, struct wm8770_priv, \
+                                     disable_nb[n]); \
+        if (event & REGULATOR_EVENT_DISABLE) { \
+                wm8770->codec->cache_sync = 1; \
+        } \
+        return 0; \
+}
+
+WM8770_REGULATOR_EVENT(0)
+WM8770_REGULATOR_EVENT(1)
+WM8770_REGULATOR_EVENT(2)
+
+static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
+static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -12750, 50, 1);
+static const DECLARE_TLV_DB_SCALE(dac_alg_tlv, -12700, 100, 1);
+
+static const char *dac_phase_text[][2] = {
+        { "DAC1 Normal", "DAC1 Inverted" },
+        { "DAC2 Normal", "DAC2 Inverted" },
+        { "DAC3 Normal", "DAC3 Inverted" },
+        { "DAC4 Normal", "DAC4 Inverted" },
+};
+
+static const struct soc_enum dac_phase[] = {
+        SOC_ENUM_DOUBLE(WM8770_DACPHASE, 0, 1, 2, dac_phase_text[0]),
+        SOC_ENUM_DOUBLE(WM8770_DACPHASE, 2, 3, 2, dac_phase_text[1]),
+        SOC_ENUM_DOUBLE(WM8770_DACPHASE, 4, 5, 2, dac_phase_text[2]),
+        SOC_ENUM_DOUBLE(WM8770_DACPHASE, 6, 7, 2, dac_phase_text[3]),
+};
+
+static const struct snd_kcontrol_new wm8770_snd_controls[] = {
+        /* global DAC playback controls */
+        SOC_SINGLE_TLV("DAC Playback Volume", WM8770_MSDIGVOL, 0, 255, 0,
+                dac_dig_tlv),
+        SOC_SINGLE("DAC Playback Switch", WM8770_DACMUTE, 4, 1, 1),
+        SOC_SINGLE("DAC Playback ZC Switch", WM8770_DACCTRL1, 0, 1, 0),
+
+        /* global VOUT playback controls */
+        SOC_SINGLE_TLV("VOUT Playback Volume", WM8770_MSALGVOL, 0, 127, 0,
+                dac_alg_tlv),
+        SOC_SINGLE("VOUT Playback ZC Switch", WM8770_MSALGVOL, 7, 1, 0),
+
+        /* VOUT1/2/3/4 specific controls */
+        SOC_DOUBLE_R_TLV("VOUT1 Playback Volume", WM8770_VOUT1LVOL,
+                WM8770_VOUT1RVOL, 0, 127, 0, dac_alg_tlv),
+        SOC_DOUBLE_R("VOUT1 Playback ZC Switch", WM8770_VOUT1LVOL,
+                WM8770_VOUT1RVOL, 7, 1, 0),
+        SOC_DOUBLE_R_TLV("VOUT2 Playback Volume", WM8770_VOUT2LVOL,
+                WM8770_VOUT2RVOL, 0, 127, 0, dac_alg_tlv),
+        SOC_DOUBLE_R("VOUT2 Playback ZC Switch", WM8770_VOUT2LVOL,
+                WM8770_VOUT2RVOL, 7, 1, 0),
+        SOC_DOUBLE_R_TLV("VOUT3 Playback Volume", WM8770_VOUT3LVOL,
+                WM8770_VOUT3RVOL, 0, 127, 0, dac_alg_tlv),
+        SOC_DOUBLE_R("VOUT3 Playback ZC Switch", WM8770_VOUT3LVOL,
+                WM8770_VOUT3RVOL, 7, 1, 0),
+        SOC_DOUBLE_R_TLV("VOUT4 Playback Volume", WM8770_VOUT4LVOL,
+                WM8770_VOUT4RVOL, 0, 127, 0, dac_alg_tlv),
+        SOC_DOUBLE_R("VOUT4 Playback ZC Switch", WM8770_VOUT4LVOL,
+                WM8770_VOUT4RVOL, 7, 1, 0),
+
+        /* DAC1/2/3/4 specific controls */
+        SOC_DOUBLE_R_TLV("DAC1 Playback Volume", WM8770_DAC1LVOL,
+                WM8770_DAC1RVOL, 0, 255, 0, dac_dig_tlv),
+        SOC_SINGLE("DAC1 Deemphasis Switch", WM8770_DACCTRL2, 0, 1, 0),
+        SOC_ENUM("DAC1 Phase", dac_phase[0]),
+        SOC_DOUBLE_R_TLV("DAC2 Playback Volume", WM8770_DAC2LVOL,
+                WM8770_DAC2RVOL, 0, 255, 0, dac_dig_tlv),
+        SOC_SINGLE("DAC2 Deemphasis Switch", WM8770_DACCTRL2, 1, 1, 0),
+        SOC_ENUM("DAC2 Phase", dac_phase[1]),
+        SOC_DOUBLE_R_TLV("DAC3 Playback Volume", WM8770_DAC3LVOL,
+                WM8770_DAC3RVOL, 0, 255, 0, dac_dig_tlv),
+        SOC_SINGLE("DAC3 Deemphasis Switch", WM8770_DACCTRL2, 2, 1, 0),
+        SOC_ENUM("DAC3 Phase", dac_phase[2]),
+        SOC_DOUBLE_R_TLV("DAC4 Playback Volume", WM8770_DAC4LVOL,
+                WM8770_DAC4RVOL, 0, 255, 0, dac_dig_tlv),
+        SOC_SINGLE("DAC4 Deemphasis Switch", WM8770_DACCTRL2, 3, 1, 0),
+        SOC_ENUM("DAC4 Phase", dac_phase[3]),
+
+        /* ADC specific controls */
+        SOC_DOUBLE_R_TLV("Capture Volume", WM8770_ADCLCTRL, WM8770_ADCRCTRL,
+                0, 31, 0, adc_tlv),
+        SOC_DOUBLE_R("Capture Switch", WM8770_ADCLCTRL, WM8770_ADCRCTRL,
+                5, 1, 1),
+
+        /* other controls */
+        SOC_SINGLE("ADC 128x Oversampling Switch", WM8770_MSTRCTRL, 3, 1, 0),
+        SOC_SINGLE("ADC Highpass Filter Switch", WM8770_IFACECTRL, 8, 1, 1)
+};
+
+static const char *ain_text[] = {
+        "AIN1", "AIN2", "AIN3", "AIN4",
+        "AIN5", "AIN6", "AIN7", "AIN8"
+};
+
+static const struct soc_enum ain_enum =
+        SOC_ENUM_DOUBLE(WM8770_ADCMUX, 0, 4, 8, ain_text);
+
+static const struct snd_kcontrol_new ain_mux =
+        SOC_DAPM_ENUM("Capture Mux", ain_enum);
+
+static const struct snd_kcontrol_new vout1_mix_controls[] = {
+        SOC_DAPM_SINGLE("DAC1 Switch", WM8770_OUTMUX1, 0, 1, 0),
+        SOC_DAPM_SINGLE("AUX1 Switch", WM8770_OUTMUX1, 1, 1, 0),
+        SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX1, 2, 1, 0)
+};
+
+static const struct snd_kcontrol_new vout2_mix_controls[] = {
+        SOC_DAPM_SINGLE("DAC2 Switch", WM8770_OUTMUX1, 3, 1, 0),
+        SOC_DAPM_SINGLE("AUX2 Switch", WM8770_OUTMUX1, 4, 1, 0),
+        SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX1, 5, 1, 0)
+};
+
+static const struct snd_kcontrol_new vout3_mix_controls[] = {
+        SOC_DAPM_SINGLE("DAC3 Switch", WM8770_OUTMUX2, 0, 1, 0),
+        SOC_DAPM_SINGLE("AUX3 Switch", WM8770_OUTMUX2, 1, 1, 0),
+        SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX2, 2, 1, 0)
+};
+
+static const struct snd_kcontrol_new vout4_mix_controls[] = {
+        SOC_DAPM_SINGLE("DAC4 Switch", WM8770_OUTMUX2, 3, 1, 0),
+        SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX2, 4, 1, 0)
+};
+
+static const struct snd_soc_dapm_widget wm8770_dapm_widgets[] = {
+        SND_SOC_DAPM_INPUT("AUX1"),
+        SND_SOC_DAPM_INPUT("AUX2"),
+        SND_SOC_DAPM_INPUT("AUX3"),
+
+        SND_SOC_DAPM_INPUT("AIN1"),
+        SND_SOC_DAPM_INPUT("AIN2"),
+        SND_SOC_DAPM_INPUT("AIN3"),
+        SND_SOC_DAPM_INPUT("AIN4"),
+        SND_SOC_DAPM_INPUT("AIN5"),
+        SND_SOC_DAPM_INPUT("AIN6"),
+        SND_SOC_DAPM_INPUT("AIN7"),
+        SND_SOC_DAPM_INPUT("AIN8"),
+
+        SND_SOC_DAPM_MUX("Capture Mux", WM8770_ADCMUX, 8, 1, &ain_mux),
+
+        SND_SOC_DAPM_ADC("ADC", "Capture", WM8770_PWDNCTRL, 1, 1),
+
+        SND_SOC_DAPM_DAC("DAC1", "Playback", WM8770_PWDNCTRL, 2, 1),
+        SND_SOC_DAPM_DAC("DAC2", "Playback", WM8770_PWDNCTRL, 3, 1),
+        SND_SOC_DAPM_DAC("DAC3", "Playback", WM8770_PWDNCTRL, 4, 1),
+        SND_SOC_DAPM_DAC("DAC4", "Playback", WM8770_PWDNCTRL, 5, 1),
+
+        SND_SOC_DAPM_SUPPLY("VOUT12 Supply", SND_SOC_NOPM, 0, 0,
+                vout12supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+        SND_SOC_DAPM_SUPPLY("VOUT34 Supply", SND_SOC_NOPM, 0, 0,
+                vout34supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+        SND_SOC_DAPM_MIXER("VOUT1 Mixer", SND_SOC_NOPM, 0, 0,
+                vout1_mix_controls, ARRAY_SIZE(vout1_mix_controls)),
+        SND_SOC_DAPM_MIXER("VOUT2 Mixer", SND_SOC_NOPM, 0, 0,
+                vout2_mix_controls, ARRAY_SIZE(vout2_mix_controls)),
+        SND_SOC_DAPM_MIXER("VOUT3 Mixer", SND_SOC_NOPM, 0, 0,
+                vout3_mix_controls, ARRAY_SIZE(vout3_mix_controls)),
+        SND_SOC_DAPM_MIXER("VOUT4 Mixer", SND_SOC_NOPM, 0, 0,
+                vout4_mix_controls, ARRAY_SIZE(vout4_mix_controls)),
+
+        SND_SOC_DAPM_OUTPUT("VOUT1"),
+        SND_SOC_DAPM_OUTPUT("VOUT2"),
+        SND_SOC_DAPM_OUTPUT("VOUT3"),
+        SND_SOC_DAPM_OUTPUT("VOUT4")
+};
+
+static const struct snd_soc_dapm_route wm8770_intercon[] = {
+        { "Capture Mux", "AIN1", "AIN1" },
+        { "Capture Mux", "AIN2", "AIN2" },
+        { "Capture Mux", "AIN3", "AIN3" },
+        { "Capture Mux", "AIN4", "AIN4" },
+        { "Capture Mux", "AIN5", "AIN5" },
+        { "Capture Mux", "AIN6", "AIN6" },
+        { "Capture Mux", "AIN7", "AIN7" },
+        { "Capture Mux", "AIN8", "AIN8" },
+
+        { "ADC", NULL, "Capture Mux" },
+
+        { "VOUT1 Mixer", NULL, "VOUT12 Supply" },
+        { "VOUT1 Mixer", "DAC1 Switch", "DAC1" },
+        { "VOUT1 Mixer", "AUX1 Switch", "AUX1" },
+        { "VOUT1 Mixer", "Bypass Switch", "Capture Mux" },
+
+        { "VOUT2 Mixer", NULL, "VOUT12 Supply" },
+        { "VOUT2 Mixer", "DAC2 Switch", "DAC2" },
+        { "VOUT2 Mixer", "AUX2 Switch", "AUX2" },
+        { "VOUT2 Mixer", "Bypass Switch", "Capture Mux" },
+
+        { "VOUT3 Mixer", NULL, "VOUT34 Supply" },
+        { "VOUT3 Mixer", "DAC3 Switch", "DAC3" },
+        { "VOUT3 Mixer", "AUX3 Switch", "AUX3" },
+        { "VOUT3 Mixer", "Bypass Switch", "Capture Mux" },
+
+        { "VOUT4 Mixer", NULL, "VOUT34 Supply" },
+        { "VOUT4 Mixer", "DAC4 Switch", "DAC4" },
+        { "VOUT4 Mixer", "Bypass Switch", "Capture Mux" },
+
+        { "VOUT1", NULL, "VOUT1 Mixer" },
+        { "VOUT2", NULL, "VOUT2 Mixer" },
+        { "VOUT3", NULL, "VOUT3 Mixer" },
+        { "VOUT4", NULL, "VOUT4 Mixer" }
+};
+
+static int vout12supply_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec;
+
+        codec = w->codec;
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                snd_soc_update_bits(codec, WM8770_OUTMUX1, 0x180, 0);
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                snd_soc_update_bits(codec, WM8770_OUTMUX1, 0x180, 0x180);
+                break;
+        }
+
+        return 0;
+}
+
+static int vout34supply_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec;
+
+        codec = w->codec;
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                snd_soc_update_bits(codec, WM8770_OUTMUX2, 0x180, 0);
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                snd_soc_update_bits(codec, WM8770_OUTMUX2, 0x180, 0x180);
+                break;
+        }
+
+        return 0;
+}
+
+static int wm8770_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, WM8770_RESET, 0);
+}
+
+static int wm8770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec;
+        int iface, master;
+
+        codec = dai->codec;
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                master = 0x100;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                master = 0;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        iface = 0;
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                iface |= 0x2;
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                iface |= 0x1;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_IF:
+                iface |= 0xc;
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                iface |= 0x8;
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                iface |= 0x4;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8770_IFACECTRL, 0xf, iface);
+        snd_soc_update_bits(codec, WM8770_MSTRCTRL, 0x100, master);
+
+        return 0;
+}
+
+static const int mclk_ratios[] = {
+        128,
+        192,
+        256,
+        384,
+        512,
+        768
+};
+
+static int wm8770_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec;
+        struct wm8770_priv *wm8770;
+        int i;
+        int iface;
+        int shift;
+        int ratio;
+
+        codec = dai->codec;
+        wm8770 = snd_soc_codec_get_drvdata(codec);
+
+        iface = 0;
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                iface |= 0x10;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                iface |= 0x20;
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                iface |= 0x30;
+                break;
+        }
+
+        switch (substream->stream) {
+        case SNDRV_PCM_STREAM_PLAYBACK:
+                i = 0;
+                shift = 4;
+                break;
+        case SNDRV_PCM_STREAM_CAPTURE:
+                i = 2;
+                shift = 0;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Only need to set MCLK/LRCLK ratio if we're master */
+        if (snd_soc_read(codec, WM8770_MSTRCTRL) & 0x100) {
+                for (; i < ARRAY_SIZE(mclk_ratios); ++i) {
+                        ratio = wm8770->sysclk / params_rate(params);
+                        if (ratio == mclk_ratios[i])
+                                break;
+                }
+
+                if (i == ARRAY_SIZE(mclk_ratios)) {
+                        dev_err(codec->dev,
+                                "Unable to configure MCLK ratio %d/%d\n",
+                                wm8770->sysclk, params_rate(params));
+                        return -EINVAL;
+                }
+
+                dev_dbg(codec->dev, "MCLK is %dfs\n", mclk_ratios[i]);
+
+                snd_soc_update_bits(codec, WM8770_MSTRCTRL, 0x7 << shift,
+                                    i << shift);
+        }
+
+        snd_soc_update_bits(codec, WM8770_IFACECTRL, 0x30, iface);
+
+        return 0;
+}
+
+static int wm8770_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec;
+
+        codec = dai->codec;
+        return snd_soc_update_bits(codec, WM8770_DACMUTE, 0x10,
+                                   !!mute << 4);
+}
+
+static int wm8770_set_sysclk(struct snd_soc_dai *dai,
+                             int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec;
+        struct wm8770_priv *wm8770;
+
+        codec = dai->codec;
+        wm8770 = snd_soc_codec_get_drvdata(codec);
+        wm8770->sysclk = freq;
+        return 0;
+}
+
+static void wm8770_sync_cache(struct snd_soc_codec *codec)
+{
+        int i;
+        u16 *cache;
+
+        if (!codec->cache_sync)
+                return;
+
+        codec->cache_only = 0;
+        cache = codec->reg_cache;
+        for (i = 0; i < codec->driver->reg_cache_size; i++) {
+                if (i == WM8770_RESET || cache[i] == wm8770_reg_defs[i])
+                        continue;
+                snd_soc_write(codec, i, cache[i]);
+        }
+        codec->cache_sync = 0;
+}
+
+static int wm8770_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        int ret;
+        struct wm8770_priv *wm8770;
+
+        wm8770 = snd_soc_codec_get_drvdata(codec);
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+        case SND_SOC_BIAS_PREPARE:
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = regulator_bulk_enable(ARRAY_SIZE(wm8770->supplies),
+                                                    wm8770->supplies);
+                        if (ret) {
+                                dev_err(codec->dev,
+                                        "Failed to enable supplies: %d\n",
+                                        ret);
+                                return ret;
+                        }
+                        wm8770_sync_cache(codec);
+                        /* global powerup */
+                        snd_soc_write(codec, WM8770_PWDNCTRL, 0);
+                }
+                break;
+        case SND_SOC_BIAS_OFF:
+                /* global powerdown */
+                snd_soc_write(codec, WM8770_PWDNCTRL, 1);
+                regulator_bulk_disable(ARRAY_SIZE(wm8770->supplies),
+                                       wm8770->supplies);
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#define WM8770_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops wm8770_dai_ops = {
+        .digital_mute = wm8770_mute,
+        .hw_params = wm8770_hw_params,
+        .set_fmt = wm8770_set_fmt,
+        .set_sysclk = wm8770_set_sysclk,
+};
+
+static struct snd_soc_dai_driver wm8770_dai = {
+        .name = "wm8770-hifi",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_192000,
+                .formats = WM8770_FORMATS
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_96000,
+                .formats = WM8770_FORMATS
+        },
+        .ops = &wm8770_dai_ops,
+        .symmetric_rates = 1
+};
+
+#ifdef CONFIG_PM
+static int wm8770_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        wm8770_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int wm8770_resume(struct snd_soc_codec *codec)
+{
+        wm8770_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+#else
+#define wm8770_suspend NULL
+#define wm8770_resume NULL
+#endif
+
+static int wm8770_probe(struct snd_soc_codec *codec)
+{
+        struct wm8770_priv *wm8770;
+        int ret;
+        int i;
+
+        wm8770 = snd_soc_codec_get_drvdata(codec);
+        wm8770->codec = codec;
+
+        codec->dapm.idle_bias_off = 1;
+
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8770->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(wm8770->supplies); i++)
+                wm8770->supplies[i].supply = wm8770_supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8770->supplies),
+                                 wm8770->supplies);
+        if (ret) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                return ret;
+        }
+
+        wm8770->disable_nb[0].notifier_call = wm8770_regulator_event_0;
+        wm8770->disable_nb[1].notifier_call = wm8770_regulator_event_1;
+        wm8770->disable_nb[2].notifier_call = wm8770_regulator_event_2;
+
+        /* This should really be moved into the regulator core */
+        for (i = 0; i < ARRAY_SIZE(wm8770->supplies); i++) {
+                ret = regulator_register_notifier(wm8770->supplies[i].consumer,
+                                                  &wm8770->disable_nb[i]);
+                if (ret) {
+                        dev_err(codec->dev,
+                                "Failed to register regulator notifier: %d\n",
+                                ret);
+                }
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(wm8770->supplies),
+                                    wm8770->supplies);
+        if (ret) {
+                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                goto err_reg_get;
+        }
+
+        ret = wm8770_reset(codec);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
+                goto err_reg_enable;
+        }
+
+        wm8770_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        /* latch the volume update bits */
+        snd_soc_update_bits(codec, WM8770_MSDIGVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_MSALGVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_VOUT1RVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_VOUT2RVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_VOUT3RVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_VOUT4RVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_DAC1RVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_DAC2RVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_DAC3RVOL, 0x100, 0x100);
+        snd_soc_update_bits(codec, WM8770_DAC4RVOL, 0x100, 0x100);
+
+        /* mute all DACs */
+        snd_soc_update_bits(codec, WM8770_DACMUTE, 0x10, 0x10);
+
+        snd_soc_add_controls(codec, wm8770_snd_controls,
+                             ARRAY_SIZE(wm8770_snd_controls));
+        snd_soc_dapm_new_controls(&codec->dapm, wm8770_dapm_widgets,
+                                  ARRAY_SIZE(wm8770_dapm_widgets));
+        snd_soc_dapm_add_routes(&codec->dapm, wm8770_intercon,
+                                ARRAY_SIZE(wm8770_intercon));
+        return 0;
+
+err_reg_enable:
+        regulator_bulk_disable(ARRAY_SIZE(wm8770->supplies), wm8770->supplies);
+err_reg_get:
+        regulator_bulk_free(ARRAY_SIZE(wm8770->supplies), wm8770->supplies);
+        return ret;
+}
+
+static int wm8770_remove(struct snd_soc_codec *codec)
+{
+        struct wm8770_priv *wm8770;
+        int i;
+
+        wm8770 = snd_soc_codec_get_drvdata(codec);
+        wm8770_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        for (i = 0; i < ARRAY_SIZE(wm8770->supplies); ++i)
+                regulator_unregister_notifier(wm8770->supplies[i].consumer,
+                                              &wm8770->disable_nb[i]);
+        regulator_bulk_free(ARRAY_SIZE(wm8770->supplies), wm8770->supplies);
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8770 = {
+        .probe = wm8770_probe,
+        .remove = wm8770_remove,
+        .suspend = wm8770_suspend,
+        .resume = wm8770_resume,
+        .set_bias_level = wm8770_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8770_reg_defs),
+        .reg_word_size = sizeof (u16),
+        .reg_cache_default = wm8770_reg_defs
+};
+
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8770_spi_probe(struct spi_device *spi)
+{
+        struct wm8770_priv *wm8770;
+        int ret;
+
+        wm8770 = kzalloc(sizeof(struct wm8770_priv), GFP_KERNEL);
+        if (!wm8770)
+                return -ENOMEM;
+
+        wm8770->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8770);
+
+        ret = snd_soc_register_codec(&spi->dev,
+                                     &soc_codec_dev_wm8770, &wm8770_dai, 1);
+        if (ret < 0)
+                kfree(wm8770);
+        return ret;
+}
+
+static int __devexit wm8770_spi_remove(struct spi_device *spi)
+{
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
+}
+
+static struct spi_driver wm8770_spi_driver = {
+        .driver = {
+                .name = "wm8770",
+                .owner = THIS_MODULE,
+        },
+        .probe = wm8770_spi_probe,
+        .remove = __devexit_p(wm8770_spi_remove)
+};
+#endif
+
+static int __init wm8770_modinit(void)
+{
+        int ret = 0;
+
+#if defined(CONFIG_SPI_MASTER)
+        ret = spi_register_driver(&wm8770_spi_driver);
+        if (ret) {
+                printk(KERN_ERR "Failed to register wm8770 SPI driver: %d\n",
+                       ret);
+        }
+#endif
+        return ret;
+}
+module_init(wm8770_modinit);
+
+static void __exit wm8770_exit(void)
+{
+#if defined(CONFIG_SPI_MASTER)
+        spi_unregister_driver(&wm8770_spi_driver);
+#endif
+}
+module_exit(wm8770_exit);
+
+MODULE_DESCRIPTION("ASoC WM8770 driver");
+MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8770.h b/sound/soc/codecs/wm8770.h
new file mode 100644
index 000000000000..5f1b3bda6cc8
--- /dev/null
+++ b/sound/soc/codecs/wm8770.h
@@ -0,0 +1,51 @@
+/*
+ * wm8770.h  --  WM8770 ASoC driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8770_H
+#define _WM8770_H
+
+/* Registers */
+#define WM8770_VOUT1LVOL                0
+#define WM8770_VOUT1RVOL                0x1
+#define WM8770_VOUT2LVOL                0x2
+#define WM8770_VOUT2RVOL                0x3
+#define WM8770_VOUT3LVOL                0x4
+#define WM8770_VOUT3RVOL                0x5
+#define WM8770_VOUT4LVOL                0x6
+#define WM8770_VOUT4RVOL                0x7
+#define WM8770_MSALGVOL                 0x8
+#define WM8770_DAC1LVOL                 0x9
+#define WM8770_DAC1RVOL                 0xa
+#define WM8770_DAC2LVOL                 0xb
+#define WM8770_DAC2RVOL                 0xc
+#define WM8770_DAC3LVOL                 0xd
+#define WM8770_DAC3RVOL                 0xe
+#define WM8770_DAC4LVOL                 0xf
+#define WM8770_DAC4RVOL                 0x10
+#define WM8770_MSDIGVOL                 0x11
+#define WM8770_DACPHASE                 0x12
+#define WM8770_DACCTRL1                 0x13
+#define WM8770_DACMUTE                  0x14
+#define WM8770_DACCTRL2                 0x15
+#define WM8770_IFACECTRL                0x16
+#define WM8770_MSTRCTRL                 0x17
+#define WM8770_PWDNCTRL                 0x18
+#define WM8770_ADCLCTRL                 0x19
+#define WM8770_ADCRCTRL                 0x1a
+#define WM8770_ADCMUX                   0x1b
+#define WM8770_OUTMUX1                  0x1c
+#define WM8770_OUTMUX2                  0x1d
+#define WM8770_RESET                    0x31
+
+#define WM8770_CACHEREGNUM 0x20
+
+#endif
diff --git a/sound/soc/codecs/wm8776.c b/sound/soc/codecs/wm8776.c
index f8154e661524..8e7953b1b790 100644
--- a/sound/soc/codecs/wm8776.c
+++ b/sound/soc/codecs/wm8776.c
@@ -25,26 +25,17 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
 #include "wm8776.h"
 
-static struct snd_soc_codec *wm8776_codec;
-struct snd_soc_codec_device soc_codec_dev_wm8776;
-
 /* codec private data */
 struct wm8776_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM8776_CACHEREGNUM];
+        enum snd_soc_control_type control_type;
         int sysclk[2];
 };
 
-#ifdef CONFIG_SPI_MASTER
-static int wm8776_spi_write(struct spi_device *spi, const char *data, int len);
-#endif
-
 static const u16 wm8776_reg[WM8776_CACHEREGNUM] = {
         0x79, 0x79, 0x79, 0xff, 0xff,  /* 4 */
         0xff, 0x00, 0x90, 0x00, 0x00,  /* 9 */
@@ -144,7 +135,7 @@ static int wm8776_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
         struct snd_soc_codec *codec = dai->codec;
         int reg, iface, master;
 
-        switch (dai->id) {
+        switch (dai->driver->id) {
         case WM8776_DAI_DAC:
                 reg = WM8776_DACIFCTRL;
                 master = 0x80;
@@ -226,7 +217,7 @@ static int wm8776_hw_params(struct snd_pcm_substream *substream,
 
         iface = 0;
 
-        switch (dai->id) {
+        switch (dai->driver->id) {
         case WM8776_DAI_DAC:
                 iface_reg = WM8776_DACIFCTRL;
                 master = 0x80;
@@ -260,7 +251,7 @@ static int wm8776_hw_params(struct snd_pcm_substream *substream,
         /* Only need to set MCLK/LRCLK ratio if we're master */
         if (snd_soc_read(codec, WM8776_MSTRCTRL) & master) {
                 for (i = 0; i < ARRAY_SIZE(mclk_ratios); i++) {
-                        if (wm8776->sysclk[dai->id] / params_rate(params)
+                        if (wm8776->sysclk[dai->driver->id] / params_rate(params)
                             == mclk_ratios[i])
                                 break;
                 }
@@ -268,7 +259,7 @@ static int wm8776_hw_params(struct snd_pcm_substream *substream,
                 if (i == ARRAY_SIZE(mclk_ratios)) {
                         dev_err(codec->dev,
                                 "Unable to configure MCLK ratio %d/%d\n",
-                                wm8776->sysclk[dai->id], params_rate(params));
+                                wm8776->sysclk[dai->driver->id], params_rate(params));
                         return -EINVAL;
                 }
 
@@ -298,9 +289,9 @@ static int wm8776_set_sysclk(struct snd_soc_dai *dai,
         struct snd_soc_codec *codec = dai->codec;
         struct wm8776_priv *wm8776 = snd_soc_codec_get_drvdata(codec);
 
-        BUG_ON(dai->id >= ARRAY_SIZE(wm8776->sysclk));
+        BUG_ON(dai->driver->id >= ARRAY_SIZE(wm8776->sysclk));
 
-        wm8776->sysclk[dai->id] = freq;
+        wm8776->sysclk[dai->driver->id] = freq;
 
         return 0;
 }
@@ -314,7 +305,7 @@ static int wm8776_set_bias_level(struct snd_soc_codec *codec,
         case SND_SOC_BIAS_PREPARE:
                 break;
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Disable the global powerdown; DAPM does the rest */
                         snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 0);
                 }
@@ -325,7 +316,7 @@ static int wm8776_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -350,10 +341,10 @@ static struct snd_soc_dai_ops wm8776_adc_ops = {
         .set_sysclk     = wm8776_set_sysclk,
 };
 
-struct snd_soc_dai wm8776_dai[] = {
+static struct snd_soc_dai_driver wm8776_dai[] = {
         {
-                .name = "WM8776 Playback",
-                .id = WM8776_DAI_DAC,
+                .name = "wm8776-hifi-playback",
+                .id     = WM8776_DAI_DAC,
                 .playback = {
                         .stream_name = "Playback",
                         .channels_min = 2,
@@ -364,8 +355,8 @@ struct snd_soc_dai wm8776_dai[] = {
                 .ops = &wm8776_dac_ops,
         },
         {
-                .name = "WM8776 Capture",
-                .id = WM8776_DAI_ADC,
+                .name = "wm8776-hifi-capture",
+                .id     = WM8776_DAI_ADC,
                 .capture = {
                         .stream_name = "Capture",
                         .channels_min = 2,
@@ -376,23 +367,17 @@ struct snd_soc_dai wm8776_dai[] = {
                 .ops = &wm8776_adc_ops,
         },
 };
-EXPORT_SYMBOL_GPL(wm8776_dai);
 
 #ifdef CONFIG_PM
-static int wm8776_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8776_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8776_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm8776_resume(struct platform_device *pdev)
+static int wm8776_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -415,99 +400,22 @@ static int wm8776_resume(struct platform_device *pdev)
 #define wm8776_resume NULL
 #endif
 
-static int wm8776_probe(struct platform_device *pdev)
+static int wm8776_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
+        struct wm8776_priv *wm8776 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
         int ret = 0;
 
-        if (wm8776_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8776_codec;
-        codec = wm8776_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8776_snd_controls,
-                             ARRAY_SIZE(wm8776_snd_controls));
-        snd_soc_dapm_new_controls(codec, wm8776_dapm_widgets,
-                                  ARRAY_SIZE(wm8776_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-/* power down chip */
-static int wm8776_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8776 = {
-        .probe =        wm8776_probe,
-        .remove =       wm8776_remove,
-        .suspend =      wm8776_suspend,
-        .resume =       wm8776_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8776);
-
-static int wm8776_register(struct wm8776_priv *wm8776,
-                           enum snd_soc_control_type control)
-{
-        int ret, i;
-        struct snd_soc_codec *codec = &wm8776->codec;
-
-        if (wm8776_codec) {
-                dev_err(codec->dev, "Another WM8776 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8776);
-        codec->name = "WM8776";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8776_set_bias_level;
-        codec->dai = wm8776_dai;
-        codec->num_dai = ARRAY_SIZE(wm8776_dai);
-        codec->reg_cache_size = WM8776_CACHEREGNUM;
-        codec->reg_cache = &wm8776->reg_cache;
-
-        memcpy(codec->reg_cache, wm8776_reg, sizeof(wm8776_reg));
-
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8776->control_type);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
-        for (i = 0; i < ARRAY_SIZE(wm8776_dai); i++)
-                wm8776_dai[i].dev = codec->dev;
-
         ret = wm8776_reset(codec);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         wm8776_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -517,95 +425,63 @@ static int wm8776_register(struct wm8776_priv *wm8776,
         snd_soc_update_bits(codec, WM8776_HPRVOL, 0x100, 0x100);
         snd_soc_update_bits(codec, WM8776_DACRVOL, 0x100, 0x100);
 
-        wm8776_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dais(wm8776_dai, ARRAY_SIZE(wm8776_dai));
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
-                goto err_codec;
-        }
-
-        return 0;
+        snd_soc_add_controls(codec, wm8776_snd_controls,
+                             ARRAY_SIZE(wm8776_snd_controls));
+        snd_soc_dapm_new_controls(dapm, wm8776_dapm_widgets,
+                                  ARRAY_SIZE(wm8776_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
 
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8776);
         return ret;
 }
 
-static void wm8776_unregister(struct wm8776_priv *wm8776)
+/* power down chip */
+static int wm8776_remove(struct snd_soc_codec *codec)
 {
-        wm8776_set_bias_level(&wm8776->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dais(wm8776_dai, ARRAY_SIZE(wm8776_dai));
-        snd_soc_unregister_codec(&wm8776->codec);
-        kfree(wm8776);
-        wm8776_codec = NULL;
+        wm8776_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
-#if defined(CONFIG_SPI_MASTER)
-static int wm8776_spi_write(struct spi_device *spi, const char *data, int len)
-{
-        struct spi_transfer t;
-        struct spi_message m;
-        u8 msg[2];
-
-        if (len <= 0)
-                return 0;
-
-        msg[0] = data[0];
-        msg[1] = data[1];
-
-        spi_message_init(&m);
-        memset(&t, 0, (sizeof t));
-
-        t.tx_buf = &msg[0];
-        t.len = len;
-
-        spi_message_add_tail(&t, &m);
-        spi_sync(spi, &m);
-
-        return len;
-}
+static struct snd_soc_codec_driver soc_codec_dev_wm8776 = {
+        .probe =        wm8776_probe,
+        .remove =       wm8776_remove,
+        .suspend =      wm8776_suspend,
+        .resume =       wm8776_resume,
+        .set_bias_level = wm8776_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8776_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8776_reg,
+};
 
+#if defined(CONFIG_SPI_MASTER)
 static int __devinit wm8776_spi_probe(struct spi_device *spi)
 {
-        struct snd_soc_codec *codec;
         struct wm8776_priv *wm8776;
+        int ret;
 
         wm8776 = kzalloc(sizeof(struct wm8776_priv), GFP_KERNEL);
         if (wm8776 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8776->codec;
-        codec->control_data = spi;
-        codec->hw_write = (hw_write_t)wm8776_spi_write;
-        codec->dev = &spi->dev;
+        wm8776->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8776);
 
-        dev_set_drvdata(&spi->dev, wm8776);
-
-        return wm8776_register(wm8776, SND_SOC_SPI);
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8776, wm8776_dai, ARRAY_SIZE(wm8776_dai));
+        if (ret < 0)
+                kfree(wm8776);
+        return ret;
 }
 
 static int __devexit wm8776_spi_remove(struct spi_device *spi)
 {
-        struct wm8776_priv *wm8776 = dev_get_drvdata(&spi->dev);
-
-        wm8776_unregister(wm8776);
-
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
 }
 
 static struct spi_driver wm8776_spi_driver = {
         .driver = {
-                .name   = "wm8776",
-                .bus    = &spi_bus_type,
+                .name   = "wm8776-codec",
                 .owner  = THIS_MODULE,
         },
         .probe          = wm8776_spi_probe,
@@ -618,27 +494,26 @@ static __devinit int wm8776_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm8776_priv *wm8776;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8776 = kzalloc(sizeof(struct wm8776_priv), GFP_KERNEL);
         if (wm8776 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8776->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
         i2c_set_clientdata(i2c, wm8776);
-        codec->control_data = i2c;
-
-        codec->dev = &i2c->dev;
+        wm8776->control_type = SND_SOC_I2C;
 
-        return wm8776_register(wm8776, SND_SOC_I2C);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8776, wm8776_dai, ARRAY_SIZE(wm8776_dai));
+        if (ret < 0)
+                kfree(wm8776);
+        return ret;
 }
 
 static __devexit int wm8776_i2c_remove(struct i2c_client *client)
 {
-        struct wm8776_priv *wm8776 = i2c_get_clientdata(client);
-        wm8776_unregister(wm8776);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -650,7 +525,7 @@ MODULE_DEVICE_TABLE(i2c, wm8776_i2c_id);
 
 static struct i2c_driver wm8776_i2c_driver = {
         .driver = {
-                .name = "wm8776",
+                .name = "wm8776-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8776_i2c_probe,
@@ -661,22 +536,22 @@ static struct i2c_driver wm8776_i2c_driver = {
 
 static int __init wm8776_modinit(void)
 {
-        int ret;
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8776_i2c_driver);
         if (ret != 0) {
-                printk(KERN_ERR "Failed to register WM8776 I2C driver: %d\n",
+                printk(KERN_ERR "Failed to register wm8776 I2C driver: %d\n",
                        ret);
         }
 #endif
 #if defined(CONFIG_SPI_MASTER)
         ret = spi_register_driver(&wm8776_spi_driver);
         if (ret != 0) {
-                printk(KERN_ERR "Failed to register WM8776 SPI driver: %d\n",
+                printk(KERN_ERR "Failed to register wm8776 SPI driver: %d\n",
                        ret);
         }
 #endif
-        return 0;
+        return ret;
 }
 module_init(wm8776_modinit);
 
diff --git a/sound/soc/codecs/wm8776.h b/sound/soc/codecs/wm8776.h
index 6606d25d2d83..4cf1c8e0bfc9 100644
--- a/sound/soc/codecs/wm8776.h
+++ b/sound/soc/codecs/wm8776.h
@@ -45,7 +45,4 @@
 #define WM8776_DAI_DAC 0
 #define WM8776_DAI_ADC 1
 
-extern struct snd_soc_dai wm8776_dai[];
-extern struct snd_soc_codec_device soc_codec_dev_wm8776;
-
 #endif
diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c
new file mode 100644
index 000000000000..9a5e67c5a6bd
--- /dev/null
+++ b/sound/soc/codecs/wm8804.c
@@ -0,0 +1,837 @@
+/*
+ * wm8804.c  --  WM8804 S/PDIF transceiver driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "wm8804.h"
+
+#define WM8804_NUM_SUPPLIES 2
+static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
+        "PVDD",
+        "DVDD"
+};
+
+static const u8 wm8804_reg_defs[] = {
+        0x05,     /* R0  - RST/DEVID1 */
+        0x88,     /* R1  - DEVID2 */
+        0x04,     /* R2  - DEVREV */
+        0x21,     /* R3  - PLL1 */
+        0xFD,     /* R4  - PLL2 */
+        0x36,     /* R5  - PLL3 */
+        0x07,     /* R6  - PLL4 */
+        0x16,     /* R7  - PLL5 */
+        0x18,     /* R8  - PLL6 */
+        0xFF,     /* R9  - SPDMODE */
+        0x00,     /* R10 - INTMASK */
+        0x00,     /* R11 - INTSTAT */
+        0x00,     /* R12 - SPDSTAT */
+        0x00,     /* R13 - RXCHAN1 */
+        0x00,     /* R14 - RXCHAN2 */
+        0x00,     /* R15 - RXCHAN3 */
+        0x00,     /* R16 - RXCHAN4 */
+        0x00,     /* R17 - RXCHAN5 */
+        0x00,     /* R18 - SPDTX1 */
+        0x00,     /* R19 - SPDTX2 */
+        0x00,     /* R20 - SPDTX3 */
+        0x71,     /* R21 - SPDTX4 */
+        0x0B,     /* R22 - SPDTX5 */
+        0x70,     /* R23 - GPO0 */
+        0x57,     /* R24 - GPO1 */
+        0x00,     /* R25 */
+        0x42,     /* R26 - GPO2 */
+        0x06,     /* R27 - AIFTX */
+        0x06,     /* R28 - AIFRX */
+        0x80,     /* R29 - SPDRX1 */
+        0x07,     /* R30 - PWRDN */
+};
+
+struct wm8804_priv {
+        enum snd_soc_control_type control_type;
+        struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
+        struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
+        struct snd_soc_codec *codec;
+};
+
+static int txsrc_get(struct snd_kcontrol *kcontrol,
+                     struct snd_ctl_elem_value *ucontrol);
+
+static int txsrc_put(struct snd_kcontrol *kcontrol,
+                     struct snd_ctl_elem_value *ucontrol);
+
+/*
+ * We can't use the same notifier block for more than one supply and
+ * there's no way I can see to get from a callback to the caller
+ * except container_of().
+ */
+#define WM8804_REGULATOR_EVENT(n) \
+static int wm8804_regulator_event_##n(struct notifier_block *nb, \
+                                      unsigned long event, void *data)    \
+{ \
+        struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
+                                                  disable_nb[n]); \
+        if (event & REGULATOR_EVENT_DISABLE) { \
+                wm8804->codec->cache_sync = 1; \
+        } \
+        return 0; \
+}
+
+WM8804_REGULATOR_EVENT(0)
+WM8804_REGULATOR_EVENT(1)
+
+static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
+static const SOC_ENUM_SINGLE_EXT_DECL(txsrc, txsrc_text);
+
+static const struct snd_kcontrol_new wm8804_snd_controls[] = {
+        SOC_ENUM_EXT("Input Source", txsrc, txsrc_get, txsrc_put),
+        SOC_SINGLE("TX Playback Switch", WM8804_PWRDN, 2, 1, 1),
+        SOC_SINGLE("AIF Playback Switch", WM8804_PWRDN, 4, 1, 1)
+};
+
+static int txsrc_get(struct snd_kcontrol *kcontrol,
+                     struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec;
+        unsigned int src;
+
+        codec = snd_kcontrol_chip(kcontrol);
+        src = snd_soc_read(codec, WM8804_SPDTX4);
+        if (src & 0x40)
+                ucontrol->value.integer.value[0] = 1;
+        else
+                ucontrol->value.integer.value[0] = 0;
+
+        return 0;
+}
+
+static int txsrc_put(struct snd_kcontrol *kcontrol,
+                     struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec;
+        unsigned int src, txpwr;
+
+        codec = snd_kcontrol_chip(kcontrol);
+
+        if (ucontrol->value.integer.value[0] != 0
+                        && ucontrol->value.integer.value[0] != 1)
+                return -EINVAL;
+
+        src = snd_soc_read(codec, WM8804_SPDTX4);
+        switch ((src & 0x40) >> 6) {
+        case 0:
+                if (!ucontrol->value.integer.value[0])
+                        return 0;
+                break;
+        case 1:
+                if (ucontrol->value.integer.value[1])
+                        return 0;
+                break;
+        }
+
+        /* save the current power state of the transmitter */
+        txpwr = snd_soc_read(codec, WM8804_PWRDN) & 0x4;
+        /* power down the transmitter */
+        snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x4);
+        /* set the tx source */
+        snd_soc_update_bits(codec, WM8804_SPDTX4, 0x40,
+                            ucontrol->value.integer.value[0] << 6);
+
+        if (ucontrol->value.integer.value[0]) {
+                /* power down the receiver */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0x2);
+                /* power up the AIF */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0);
+        } else {
+                /* don't power down the AIF -- may be used as an output */
+                /* power up the receiver */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0);
+        }
+
+        /* restore the transmitter's configuration */
+        snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, txpwr);
+
+        return 0;
+}
+
+static int wm8804_volatile(struct snd_soc_codec *codec, unsigned int reg)
+{
+        switch (reg) {
+        case WM8804_RST_DEVID1:
+        case WM8804_DEVID2:
+        case WM8804_DEVREV:
+        case WM8804_INTSTAT:
+        case WM8804_SPDSTAT:
+        case WM8804_RXCHAN1:
+        case WM8804_RXCHAN2:
+        case WM8804_RXCHAN3:
+        case WM8804_RXCHAN4:
+        case WM8804_RXCHAN5:
+                return 1;
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+static int wm8804_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, WM8804_RST_DEVID1, 0x0);
+}
+
+static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec;
+        u16 format, master, bcp, lrp;
+
+        codec = dai->codec;
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                format = 0x2;
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                format = 0x0;
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                format = 0x1;
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+        case SND_SOC_DAIFMT_DSP_B:
+                format = 0x3;
+                break;
+        default:
+                dev_err(dai->dev, "Unknown dai format\n");
+                return -EINVAL;
+        }
+
+        /* set data format */
+        snd_soc_update_bits(codec, WM8804_AIFTX, 0x3, format);
+        snd_soc_update_bits(codec, WM8804_AIFRX, 0x3, format);
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                master = 1;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                master = 0;
+                break;
+        default:
+                dev_err(dai->dev, "Unknown master/slave configuration\n");
+                return -EINVAL;
+        }
+
+        /* set master/slave mode */
+        snd_soc_update_bits(codec, WM8804_AIFRX, 0x40, master << 6);
+
+        bcp = lrp = 0;
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_IF:
+                bcp = lrp = 1;
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                bcp = 1;
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                lrp = 1;
+                break;
+        default:
+                dev_err(dai->dev, "Unknown polarity configuration\n");
+                return -EINVAL;
+        }
+
+        /* set frame inversion */
+        snd_soc_update_bits(codec, WM8804_AIFTX, 0x10 | 0x20,
+                            (bcp << 4) | (lrp << 5));
+        snd_soc_update_bits(codec, WM8804_AIFRX, 0x10 | 0x20,
+                            (bcp << 4) | (lrp << 5));
+        return 0;
+}
+
+static int wm8804_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec;
+        u16 blen;
+
+        codec = dai->codec;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                blen = 0x0;
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                blen = 0x1;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                blen = 0x2;
+                break;
+        default:
+                dev_err(dai->dev, "Unsupported word length: %u\n",
+                        params_format(params));
+                return -EINVAL;
+        }
+
+        /* set word length */
+        snd_soc_update_bits(codec, WM8804_AIFTX, 0xc, blen << 2);
+        snd_soc_update_bits(codec, WM8804_AIFRX, 0xc, blen << 2);
+
+        return 0;
+}
+
+struct pll_div {
+        u32 prescale:1;
+        u32 mclkdiv:1;
+        u32 freqmode:2;
+        u32 n:4;
+        u32 k:22;
+};
+
+/* PLL rate to output rate divisions */
+static struct {
+        unsigned int div;
+        unsigned int freqmode;
+        unsigned int mclkdiv;
+} post_table[] = {
+        {  2,  0, 0 },
+        {  4,  0, 1 },
+        {  4,  1, 0 },
+        {  8,  1, 1 },
+        {  8,  2, 0 },
+        { 16,  2, 1 },
+        { 12,  3, 0 },
+        { 24,  3, 1 }
+};
+
+#define FIXED_PLL_SIZE ((1ULL << 22) * 10)
+static int pll_factors(struct pll_div *pll_div, unsigned int target,
+                       unsigned int source)
+{
+        u64 Kpart;
+        unsigned long int K, Ndiv, Nmod, tmp;
+        int i;
+
+        /*
+         * Scale the output frequency up; the PLL should run in the
+         * region of 90-100MHz.
+         */
+        for (i = 0; i < ARRAY_SIZE(post_table); i++) {
+                tmp = target * post_table[i].div;
+                if (tmp >= 90000000 && tmp <= 100000000) {
+                        pll_div->freqmode = post_table[i].freqmode;
+                        pll_div->mclkdiv = post_table[i].mclkdiv;
+                        target *= post_table[i].div;
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(post_table)) {
+                pr_err("%s: Unable to scale output frequency: %uHz\n",
+                       __func__, target);
+                return -EINVAL;
+        }
+
+        pll_div->prescale = 0;
+        Ndiv = target / source;
+        if (Ndiv < 5) {
+                source >>= 1;
+                pll_div->prescale = 1;
+                Ndiv = target / source;
+        }
+
+        if (Ndiv < 5 || Ndiv > 13) {
+                pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
+                       __func__, Ndiv);
+                return -EINVAL;
+        }
+        pll_div->n = Ndiv;
+
+        Nmod = target % source;
+        Kpart = FIXED_PLL_SIZE * (u64)Nmod;
+
+        do_div(Kpart, source);
+
+        K = Kpart & 0xffffffff;
+        if ((K % 10) >= 5)
+                K += 5;
+        K /= 10;
+        pll_div->k = K;
+
+        return 0;
+}
+
+static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
+                          int source, unsigned int freq_in,
+                          unsigned int freq_out)
+{
+        struct snd_soc_codec *codec;
+
+        codec = dai->codec;
+        if (!freq_in || !freq_out) {
+                /* disable the PLL */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
+                return 0;
+        } else {
+                int ret;
+                struct pll_div pll_div;
+
+                ret = pll_factors(&pll_div, freq_out, freq_in);
+                if (ret)
+                        return ret;
+
+                /* power down the PLL before reprogramming it */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
+
+                if (!freq_in || !freq_out)
+                        return 0;
+
+                /* set PLLN and PRESCALE */
+                snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
+                                    pll_div.n | (pll_div.prescale << 4));
+                /* set mclkdiv and freqmode */
+                snd_soc_update_bits(codec, WM8804_PLL5, 0x3 | 0x8,
+                                    pll_div.freqmode | (pll_div.mclkdiv << 3));
+                /* set PLLK */
+                snd_soc_write(codec, WM8804_PLL1, pll_div.k & 0xff);
+                snd_soc_write(codec, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
+                snd_soc_write(codec, WM8804_PLL3, pll_div.k >> 16);
+
+                /* power up the PLL */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0);
+        }
+
+        return 0;
+}
+
+static int wm8804_set_sysclk(struct snd_soc_dai *dai,
+                             int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec;
+
+        codec = dai->codec;
+
+        switch (clk_id) {
+        case WM8804_TX_CLKSRC_MCLK:
+                if ((freq >= 10000000 && freq <= 14400000)
+                                || (freq >= 16280000 && freq <= 27000000))
+                        snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0x80);
+                else {
+                        dev_err(dai->dev, "OSCCLOCK is not within the "
+                                "recommended range: %uHz\n", freq);
+                        return -EINVAL;
+                }
+                break;
+        case WM8804_TX_CLKSRC_PLL:
+                snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0);
+                break;
+        case WM8804_CLKOUT_SRC_CLK1:
+                snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0);
+                break;
+        case WM8804_CLKOUT_SRC_OSCCLK:
+                snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0x8);
+                break;
+        default:
+                dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
+                             int div_id, int div)
+{
+        struct snd_soc_codec *codec;
+
+        codec = dai->codec;
+        switch (div_id) {
+        case WM8804_CLKOUT_DIV:
+                snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
+                                    (div & 0x3) << 4);
+                break;
+        default:
+                dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static void wm8804_sync_cache(struct snd_soc_codec *codec)
+{
+        short i;
+        u8 *cache;
+
+        if (!codec->cache_sync)
+                return;
+
+        codec->cache_only = 0;
+        cache = codec->reg_cache;
+        for (i = 0; i < codec->driver->reg_cache_size; i++) {
+                if (i == WM8804_RST_DEVID1 || cache[i] == wm8804_reg_defs[i])
+                        continue;
+                snd_soc_write(codec, i, cache[i]);
+        }
+        codec->cache_sync = 0;
+}
+
+static int wm8804_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        int ret;
+        struct wm8804_priv *wm8804;
+
+        wm8804 = snd_soc_codec_get_drvdata(codec);
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+        case SND_SOC_BIAS_PREPARE:
+                /* power up the OSC and the PLL */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
+                                                    wm8804->supplies);
+                        if (ret) {
+                                dev_err(codec->dev,
+                                        "Failed to enable supplies: %d\n",
+                                        ret);
+                                return ret;
+                        }
+                        wm8804_sync_cache(codec);
+                }
+                /* power down the OSC and the PLL */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
+                break;
+        case SND_SOC_BIAS_OFF:
+                /* power down the OSC and the PLL */
+                snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
+                regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
+                                       wm8804->supplies);
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int wm8804_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int wm8804_resume(struct snd_soc_codec *codec)
+{
+        wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+#else
+#define wm8804_suspend NULL
+#define wm8804_resume NULL
+#endif
+
+static int wm8804_remove(struct snd_soc_codec *codec)
+{
+        struct wm8804_priv *wm8804;
+        int i;
+
+        wm8804 = snd_soc_codec_get_drvdata(codec);
+        wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i)
+                regulator_unregister_notifier(wm8804->supplies[i].consumer,
+                                              &wm8804->disable_nb[i]);
+        regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
+        return 0;
+}
+
+static int wm8804_probe(struct snd_soc_codec *codec)
+{
+        struct wm8804_priv *wm8804;
+        int i, id1, id2, ret;
+
+        wm8804 = snd_soc_codec_get_drvdata(codec);
+        wm8804->codec = codec;
+
+        codec->dapm.idle_bias_off = 1;
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, wm8804->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
+                return ret;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
+                wm8804->supplies[i].supply = wm8804_supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies),
+                                 wm8804->supplies);
+        if (ret) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                return ret;
+        }
+
+        wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
+        wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
+
+        /* This should really be moved into the regulator core */
+        for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
+                ret = regulator_register_notifier(wm8804->supplies[i].consumer,
+                                                  &wm8804->disable_nb[i]);
+                if (ret != 0) {
+                        dev_err(codec->dev,
+                                "Failed to register regulator notifier: %d\n",
+                                ret);
+                }
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
+                                    wm8804->supplies);
+        if (ret) {
+                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                goto err_reg_get;
+        }
+
+        id1 = snd_soc_read(codec, WM8804_RST_DEVID1);
+        if (id1 < 0) {
+                dev_err(codec->dev, "Failed to read device ID: %d\n", id1);
+                ret = id1;
+                goto err_reg_enable;
+        }
+
+        id2 = snd_soc_read(codec, WM8804_DEVID2);
+        if (id2 < 0) {
+                dev_err(codec->dev, "Failed to read device ID: %d\n", id2);
+                ret = id2;
+                goto err_reg_enable;
+        }
+
+        id2 = (id2 << 8) | id1;
+
+        if (id2 != ((wm8804_reg_defs[WM8804_DEVID2] << 8)
+                        | wm8804_reg_defs[WM8804_RST_DEVID1])) {
+                dev_err(codec->dev, "Invalid device ID: %#x\n", id2);
+                ret = -EINVAL;
+                goto err_reg_enable;
+        }
+
+        ret = snd_soc_read(codec, WM8804_DEVREV);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read device revision: %d\n",
+                        ret);
+                goto err_reg_enable;
+        }
+        dev_info(codec->dev, "revision %c\n", ret + 'A');
+
+        ret = wm8804_reset(codec);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
+                goto err_reg_enable;
+        }
+
+        wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        snd_soc_add_controls(codec, wm8804_snd_controls,
+                             ARRAY_SIZE(wm8804_snd_controls));
+        return 0;
+
+err_reg_enable:
+        regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
+err_reg_get:
+        regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
+        return ret;
+}
+
+static struct snd_soc_dai_ops wm8804_dai_ops = {
+        .hw_params = wm8804_hw_params,
+        .set_fmt = wm8804_set_fmt,
+        .set_sysclk = wm8804_set_sysclk,
+        .set_clkdiv = wm8804_set_clkdiv,
+        .set_pll = wm8804_set_pll
+};
+
+#define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+                        SNDRV_PCM_FMTBIT_S24_LE)
+
+#define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
+                      SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
+                      SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
+                      SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
+
+static struct snd_soc_dai_driver wm8804_dai = {
+        .name = "wm8804-spdif",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = WM8804_RATES,
+                .formats = WM8804_FORMATS,
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = WM8804_RATES,
+                .formats = WM8804_FORMATS,
+        },
+        .ops = &wm8804_dai_ops,
+        .symmetric_rates = 1
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
+        .probe = wm8804_probe,
+        .remove = wm8804_remove,
+        .suspend = wm8804_suspend,
+        .resume = wm8804_resume,
+        .set_bias_level = wm8804_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8804_reg_defs),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = wm8804_reg_defs,
+        .volatile_register = wm8804_volatile
+};
+
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8804_spi_probe(struct spi_device *spi)
+{
+        struct wm8804_priv *wm8804;
+        int ret;
+
+        wm8804 = kzalloc(sizeof *wm8804, GFP_KERNEL);
+        if (!wm8804)
+                return -ENOMEM;
+
+        wm8804->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8804);
+
+        ret = snd_soc_register_codec(&spi->dev,
+                                     &soc_codec_dev_wm8804, &wm8804_dai, 1);
+        if (ret < 0)
+                kfree(wm8804);
+        return ret;
+}
+
+static int __devexit wm8804_spi_remove(struct spi_device *spi)
+{
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
+}
+
+static struct spi_driver wm8804_spi_driver = {
+        .driver = {
+                .name = "wm8804",
+                .owner = THIS_MODULE,
+        },
+        .probe = wm8804_spi_probe,
+        .remove = __devexit_p(wm8804_spi_remove)
+};
+#endif
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8804_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8804_priv *wm8804;
+        int ret;
+
+        wm8804 = kzalloc(sizeof *wm8804, GFP_KERNEL);
+        if (!wm8804)
+                return -ENOMEM;
+
+        wm8804->control_type = SND_SOC_I2C;
+        i2c_set_clientdata(i2c, wm8804);
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                                     &soc_codec_dev_wm8804, &wm8804_dai, 1);
+        if (ret < 0)
+                kfree(wm8804);
+        return ret;
+}
+
+static __devexit int wm8804_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id wm8804_i2c_id[] = {
+        { "wm8804", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8804_i2c_id);
+
+static struct i2c_driver wm8804_i2c_driver = {
+        .driver = {
+                .name = "wm8804",
+                .owner = THIS_MODULE,
+        },
+        .probe = wm8804_i2c_probe,
+        .remove = __devexit_p(wm8804_i2c_remove),
+        .id_table = wm8804_i2c_id
+};
+#endif
+
+static int __init wm8804_modinit(void)
+{
+        int ret = 0;
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8804_i2c_driver);
+        if (ret) {
+                printk(KERN_ERR "Failed to register wm8804 I2C driver: %d\n",
+                       ret);
+        }
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        ret = spi_register_driver(&wm8804_spi_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8804 SPI driver: %d\n",
+                       ret);
+        }
+#endif
+        return ret;
+}
+module_init(wm8804_modinit);
+
+static void __exit wm8804_exit(void)
+{
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&wm8804_i2c_driver);
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        spi_unregister_driver(&wm8804_spi_driver);
+#endif
+}
+module_exit(wm8804_exit);
+
+MODULE_DESCRIPTION("ASoC WM8804 driver");
+MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8804.h b/sound/soc/codecs/wm8804.h
new file mode 100644
index 000000000000..8ec14f5573cb
--- /dev/null
+++ b/sound/soc/codecs/wm8804.h
@@ -0,0 +1,61 @@
+/*
+ * wm8804.h  --  WM8804 S/PDIF transceiver driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8804_H
+#define _WM8804_H
+
+/*
+ * Register values.
+ */
+#define WM8804_RST_DEVID1                       0x00
+#define WM8804_DEVID2                           0x01
+#define WM8804_DEVREV                           0x02
+#define WM8804_PLL1                             0x03
+#define WM8804_PLL2                             0x04
+#define WM8804_PLL3                             0x05
+#define WM8804_PLL4                             0x06
+#define WM8804_PLL5                             0x07
+#define WM8804_PLL6                             0x08
+#define WM8804_SPDMODE                          0x09
+#define WM8804_INTMASK                          0x0A
+#define WM8804_INTSTAT                          0x0B
+#define WM8804_SPDSTAT                          0x0C
+#define WM8804_RXCHAN1                          0x0D
+#define WM8804_RXCHAN2                          0x0E
+#define WM8804_RXCHAN3                          0x0F
+#define WM8804_RXCHAN4                          0x10
+#define WM8804_RXCHAN5                          0x11
+#define WM8804_SPDTX1                           0x12
+#define WM8804_SPDTX2                           0x13
+#define WM8804_SPDTX3                           0x14
+#define WM8804_SPDTX4                           0x15
+#define WM8804_SPDTX5                           0x16
+#define WM8804_GPO0                             0x17
+#define WM8804_GPO1                             0x18
+#define WM8804_GPO2                             0x1A
+#define WM8804_AIFTX                            0x1B
+#define WM8804_AIFRX                            0x1C
+#define WM8804_SPDRX1                           0x1D
+#define WM8804_PWRDN                            0x1E
+
+#define WM8804_REGISTER_COUNT                   30
+#define WM8804_MAX_REGISTER                     0x1E
+
+#define WM8804_TX_CLKSRC_MCLK                   1
+#define WM8804_TX_CLKSRC_PLL                    2
+
+#define WM8804_CLKOUT_SRC_CLK1                  3
+#define WM8804_CLKOUT_SRC_OSCCLK                4
+
+#define WM8804_CLKOUT_DIV                       1
+
+#endif  /* _WM8804_H */
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index 5da17a704e5a..449ea09a193d 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -23,13 +23,13 @@
 #include <linux/delay.h>
 #include <linux/pm.h>
 #include <linux/i2c.h>
+#include <linux/spi/spi.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
@@ -137,12 +137,8 @@
 
 #define WM8900_LRC_MASK 0xfc00
 
-struct snd_soc_codec_device soc_codec_dev_wm8900;
-
 struct wm8900_priv {
-        struct snd_soc_codec codec;
-
-        u16 reg_cache[WM8900_MAXREG];
+        enum snd_soc_control_type control_type;
 
         u32 fll_in; /* FLL input frequency */
         u32 fll_out; /* FLL output frequency */
@@ -184,11 +180,10 @@ static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
         /* Remaining registers all zero */
 };
 
-static int wm8900_volatile_register(unsigned int reg)
+static int wm8900_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
 {
         switch (reg) {
         case WM8900_REG_ID:
-        case WM8900_REG_POWER1:
                 return 1;
         default:
                 return 0;
@@ -614,10 +609,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8900_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
-                                  ARRAY_SIZE(wm8900_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, wm8900_dapm_widgets,
+                                  ARRAY_SIZE(wm8900_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -627,8 +623,7 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 reg;
 
         reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
@@ -1015,8 +1010,8 @@ static struct snd_soc_dai_ops wm8900_dai_ops = {
         .digital_mute   = wm8900_digital_mute,
 };
 
-struct snd_soc_dai wm8900_dai = {
-        .name = "WM8900 HiFi",
+static struct snd_soc_dai_driver wm8900_dai = {
+        .name = "wm8900-hifi",
         .playback = {
                 .stream_name = "HiFi Playback",
                 .channels_min = 1,
@@ -1033,7 +1028,6 @@ struct snd_soc_dai wm8900_dai = {
          },
         .ops = &wm8900_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8900_dai);
 
 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
                                  enum snd_soc_bias_level level)
@@ -1056,7 +1050,7 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
 
         case SND_SOC_BIAS_STANDBY:
                 /* Charge capacitors if initial power up */
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* STARTUP_BIAS_ENA on */
                         snd_soc_write(codec, WM8900_REG_POWER1,
                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA);
@@ -1124,14 +1118,12 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
                              WM8900_REG_POWER2_SYSCLK_ENA);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
-static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8900_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
         int fll_out = wm8900->fll_out;
         int fll_in  = wm8900->fll_in;
@@ -1140,7 +1132,7 @@ static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
         /* Stop the FLL in an orderly fashion */
         ret = wm8900_set_fll(codec, 0, 0, 0);
         if (ret != 0) {
-                dev_err(&pdev->dev, "Failed to stop FLL\n");
+                dev_err(codec->dev, "Failed to stop FLL\n");
                 return ret;
         }
 
@@ -1152,10 +1144,8 @@ static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
         return 0;
 }
 
-static int wm8900_resume(struct platform_device *pdev)
+static int wm8900_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
         u16 *cache;
         int i, ret;
@@ -1176,7 +1166,7 @@ static int wm8900_resume(struct platform_device *pdev)
 
                 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
                 if (ret != 0) {
-                        dev_err(&pdev->dev, "Failed to restart FLL\n");
+                        dev_err(codec->dev, "Failed to restart FLL\n");
                         return ret;
                 }
         }
@@ -1186,61 +1176,28 @@ static int wm8900_resume(struct platform_device *pdev)
                         snd_soc_write(codec, i, cache[i]);
                 kfree(cache);
         } else
-                dev_err(&pdev->dev, "Unable to allocate register cache\n");
+                dev_err(codec->dev, "Unable to allocate register cache\n");
 
         return 0;
 }
 
-static struct snd_soc_codec *wm8900_codec;
-
-static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
-                                      const struct i2c_device_id *id)
+static int wm8900_probe(struct snd_soc_codec *codec)
 {
-        struct wm8900_priv *wm8900;
-        struct snd_soc_codec *codec;
-        unsigned int reg;
-        int ret;
-
-        wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
-        if (wm8900 == NULL)
-                return -ENOMEM;
+        struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
+        int ret = 0, reg;
 
-        codec = &wm8900->codec;
-        snd_soc_codec_set_drvdata(codec, wm8900);
-        codec->reg_cache = &wm8900->reg_cache[0];
-        codec->reg_cache_size = WM8900_MAXREG;
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "WM8900";
-        codec->owner = THIS_MODULE;
-        codec->dai = &wm8900_dai;
-        codec->num_dai = 1;
-        codec->control_data = i2c;
-        codec->set_bias_level = wm8900_set_bias_level;
-        codec->volatile_register = wm8900_volatile_register;
-        codec->dev = &i2c->dev;
-
-        ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type);
         if (ret != 0) {
-                dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
         reg = snd_soc_read(codec, WM8900_REG_ID);
         if (reg != 0x8900) {
-                dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg);
-                ret = -ENODEV;
-                goto err;
+                dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
+                return -ENODEV;
         }
 
-        /* Read back from the chip */
-        reg = snd_soc_read(codec, WM8900_REG_POWER1);
-        reg = (reg >> 12) & 0xf;
-        dev_info(&i2c->dev, "WM8900 revision %d\n", reg);
-
         wm8900_reset(codec);
 
         /* Turn the chip on */
@@ -1271,43 +1228,94 @@ static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
         /* Set the DAC and mixer output bias */
         snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
 
-        wm8900_dai.dev = &i2c->dev;
+        snd_soc_add_controls(codec, wm8900_snd_controls,
+                                ARRAY_SIZE(wm8900_snd_controls));
+        wm8900_add_widgets(codec);
+
+        return 0;
+}
 
-        wm8900_codec = codec;
+/* power down chip */
+static int wm8900_remove(struct snd_soc_codec *codec)
+{
+        wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
 
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
+static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
+        .probe =        wm8900_probe,
+        .remove =       wm8900_remove,
+        .suspend =      wm8900_suspend,
+        .resume =       wm8900_resume,
+        .set_bias_level = wm8900_set_bias_level,
+        .volatile_register = wm8900_volatile_register,
+        .reg_cache_size = ARRAY_SIZE(wm8900_reg_defaults),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8900_reg_defaults,
+};
 
-        ret = snd_soc_register_dai(&wm8900_dai);
-        if (ret != 0) {
-                dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8900_spi_probe(struct spi_device *spi)
+{
+        struct wm8900_priv *wm8900;
+        int ret;
 
-        return ret;
+        wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
+        if (wm8900 == NULL)
+                return -ENOMEM;
+
+        wm8900->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8900);
 
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8900);
-        wm8900_codec = NULL;
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8900, &wm8900_dai, 1);
+        if (ret < 0)
+                kfree(wm8900);
         return ret;
 }
 
-static __devexit int wm8900_i2c_remove(struct i2c_client *client)
+static int __devexit wm8900_spi_remove(struct spi_device *spi)
 {
-        snd_soc_unregister_dai(&wm8900_dai);
-        snd_soc_unregister_codec(wm8900_codec);
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
+}
 
-        wm8900_set_bias_level(wm8900_codec, SND_SOC_BIAS_OFF);
+static struct spi_driver wm8900_spi_driver = {
+        .driver = {
+                .name   = "wm8900-codec",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = wm8900_spi_probe,
+        .remove         = __devexit_p(wm8900_spi_remove),
+};
+#endif /* CONFIG_SPI_MASTER */
 
-        wm8900_dai.dev = NULL;
-        kfree(snd_soc_codec_get_drvdata(wm8900_codec));
-        wm8900_codec = NULL;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8900_priv *wm8900;
+        int ret;
 
+        wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
+        if (wm8900 == NULL)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, wm8900);
+        wm8900->control_type = SND_SOC_I2C;
+
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8900, &wm8900_dai, 1);
+        if (ret < 0)
+                kfree(wm8900);
+        return ret;
+}
+
+static __devexit int wm8900_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -1319,71 +1327,44 @@ MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
 
 static struct i2c_driver wm8900_i2c_driver = {
         .driver = {
-                .name = "WM8900",
+                .name = "wm8900-codec",
                 .owner = THIS_MODULE,
         },
-        .probe = wm8900_i2c_probe,
-        .remove = __devexit_p(wm8900_i2c_remove),
+        .probe =    wm8900_i2c_probe,
+        .remove =   __devexit_p(wm8900_i2c_remove),
         .id_table = wm8900_i2c_id,
 };
+#endif
 
-static int wm8900_probe(struct platform_device *pdev)
+static int __init wm8900_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
         int ret = 0;
-
-        if (!wm8900_codec) {
-                dev_err(&pdev->dev, "I2C client not yet instantiated\n");
-                return -ENODEV;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8900_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
+                       ret);
         }
-
-        codec = wm8900_codec;
-        socdev->card->codec = codec;
-
-        /* Register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "Failed to register new PCMs\n");
-                goto pcm_err;
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        ret = spi_register_driver(&wm8900_spi_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
+                       ret);
         }
-
-        snd_soc_add_controls(codec, wm8900_snd_controls,
-                                ARRAY_SIZE(wm8900_snd_controls));
-        wm8900_add_widgets(codec);
-
-pcm_err:
+#endif
         return ret;
 }
-
-/* power down chip */
-static int wm8900_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8900 = {
-        .probe =        wm8900_probe,
-        .remove =       wm8900_remove,
-        .suspend =      wm8900_suspend,
-        .resume =       wm8900_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900);
-
-static int __init wm8900_modinit(void)
-{
-        return i2c_add_driver(&wm8900_i2c_driver);
-}
 module_init(wm8900_modinit);
 
 static void __exit wm8900_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm8900_i2c_driver);
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        spi_unregister_driver(&wm8900_spi_driver);
+#endif
 }
 module_exit(wm8900_exit);
 
diff --git a/sound/soc/codecs/wm8900.h b/sound/soc/codecs/wm8900.h
index fd15007d10c7..583f257e799b 100644
--- a/sound/soc/codecs/wm8900.h
+++ b/sound/soc/codecs/wm8900.h
@@ -52,7 +52,4 @@
 #define WM8900_DAC_CLKDIV_5_5 0x14
 #define WM8900_DAC_CLKDIV_6   0x18
 
-extern struct snd_soc_dai wm8900_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8900;
-
 #endif
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index bf08282d5ee5..43e3d760766f 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -2,6 +2,7 @@
  * wm8903.c  --  WM8903 ALSA SoC Audio driver
  *
  * Copyright 2008 Wolfson Microelectronics
+ * Copyright 2011 NVIDIA, Inc.
  *
  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  *
@@ -19,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/completion.h>
 #include <linux/delay.h>
+#include <linux/gpio.h>
 #include <linux/pm.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
@@ -29,9 +31,9 @@
 #include <sound/pcm_params.h>
 #include <sound/tlv.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/wm8903.h>
+#include <trace/events/asoc.h>
 
 #include "wm8903.h"
 
@@ -213,17 +215,19 @@ static u16 wm8903_reg_defaults[] = {
 };
 
 struct wm8903_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
+        struct snd_soc_codec *codec;
 
         int sysclk;
+        int irq;
 
-        /* Reference counts */
-        int class_w_users;
-        int playback_active;
-        int capture_active;
+        int fs;
+        int deemph;
 
-        struct completion wseq;
+        int dcs_pending;
+        int dcs_cache[4];
+
+        /* Reference count */
+        int class_w_users;
 
         struct snd_soc_jack *mic_jack;
         int mic_det;
@@ -231,17 +235,22 @@ struct wm8903_priv {
         int mic_last_report;
         int mic_delay;
 
-        struct snd_pcm_substream *master_substream;
-        struct snd_pcm_substream *slave_substream;
+#ifdef CONFIG_GPIOLIB
+        struct gpio_chip gpio_chip;
+#endif
 };
 
-static int wm8903_volatile_register(unsigned int reg)
+static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
 {
         switch (reg) {
         case WM8903_SW_RESET_AND_ID:
         case WM8903_REVISION_NUMBER:
         case WM8903_INTERRUPT_STATUS_1:
         case WM8903_WRITE_SEQUENCER_4:
+        case WM8903_DC_SERVO_READBACK_1:
+        case WM8903_DC_SERVO_READBACK_2:
+        case WM8903_DC_SERVO_READBACK_3:
+        case WM8903_DC_SERVO_READBACK_4:
                 return 1;
 
         default:
@@ -249,51 +258,6 @@ static int wm8903_volatile_register(unsigned int reg)
         }
 }
 
-static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
-{
-        u16 reg[5];
-        struct i2c_client *i2c = codec->control_data;
-        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
-
-        BUG_ON(start > 48);
-
-        /* Enable the sequencer if it's not already on */
-        reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
-        snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
-                      reg[0] | WM8903_WSEQ_ENA);
-
-        dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
-
-        snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
-                     start | WM8903_WSEQ_START);
-
-        /* Wait for it to complete.  If we have the interrupt wired up then
-         * that will break us out of the poll early.
-         */
-        do {
-                wait_for_completion_timeout(&wm8903->wseq,
-                                            msecs_to_jiffies(10));
-
-                reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
-        } while (reg[4] & WM8903_WSEQ_BUSY);
-
-        dev_dbg(&i2c->dev, "Sequence complete\n");
-
-        /* Disable the sequencer again if we enabled it */
-        snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
-
-        return 0;
-}
-
-static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
-{
-        int i;
-
-        /* There really ought to be something better we can do here :/ */
-        for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
-                cache[i] = codec->hw_read(codec, i);
-}
-
 static void wm8903_reset(struct snd_soc_codec *codec)
 {
         snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
@@ -301,11 +265,6 @@ static void wm8903_reset(struct snd_soc_codec *codec)
                sizeof(wm8903_reg_defaults));
 }
 
-#define WM8903_OUTPUT_SHORT 0x8
-#define WM8903_OUTPUT_OUT   0x4
-#define WM8903_OUTPUT_INT   0x2
-#define WM8903_OUTPUT_IN    0x1
-
 static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
                            struct snd_kcontrol *kcontrol, int event)
 {
@@ -315,97 +274,101 @@ static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
         return 0;
 }
 
-/*
- * Event for headphone and line out amplifier power changes.  Special
- * power up/down sequences are required in order to maximise pop/click
- * performance.
- */
-static int wm8903_output_event(struct snd_soc_dapm_widget *w,
-                               struct snd_kcontrol *kcontrol, int event)
+static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
+                            struct snd_kcontrol *kcontrol, int event)
 {
         struct snd_soc_codec *codec = w->codec;
-        u16 val;
-        u16 reg;
-        u16 dcs_reg;
-        u16 dcs_bit;
-        int shift;
-
-        switch (w->reg) {
-        case WM8903_POWER_MANAGEMENT_2:
-                reg = WM8903_ANALOGUE_HP_0;
-                dcs_bit = 0 + w->shift;
-                break;
-        case WM8903_POWER_MANAGEMENT_3:
-                reg = WM8903_ANALOGUE_LINEOUT_0;
-                dcs_bit = 2 + w->shift;
-                break;
-        default:
-                BUG();
-                return -EINVAL;  /* Spurious warning from some compilers */
-        }
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
 
-        switch (w->shift) {
-        case 0:
-                shift = 0;
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                wm8903->dcs_pending |= 1 << w->shift;
                 break;
-        case 1:
-                shift = 4;
+        case SND_SOC_DAPM_PRE_PMD:
+                snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
+                                    1 << w->shift, 0);
                 break;
-        default:
-                BUG();
-                return -EINVAL;  /* Spurious warning from some compilers */
         }
 
-        if (event & SND_SOC_DAPM_PRE_PMU) {
-                val = snd_soc_read(codec, reg);
+        return 0;
+}
+
+#define WM8903_DCS_MODE_WRITE_STOP 0
+#define WM8903_DCS_MODE_START_STOP 2
 
-                /* Short the output */
-                val &= ~(WM8903_OUTPUT_SHORT << shift);
-                snd_soc_write(codec, reg, val);
-        }
+static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
+                                enum snd_soc_dapm_type event, int subseq)
+{
+        struct snd_soc_codec *codec = container_of(dapm,
+                                                   struct snd_soc_codec, dapm);
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
+        int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
+        int i, val;
 
-        if (event & SND_SOC_DAPM_POST_PMU) {
-                val = snd_soc_read(codec, reg);
+        /* Complete any pending DC servo starts */
+        if (wm8903->dcs_pending) {
+                dev_dbg(codec->dev, "Starting DC servo for %x\n",
+                        wm8903->dcs_pending);
 
-                val |= (WM8903_OUTPUT_IN << shift);
-                snd_soc_write(codec, reg, val);
+                /* If we've no cached values then we need to do startup */
+                for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
+                        if (!(wm8903->dcs_pending & (1 << i)))
+                                continue;
 
-                val |= (WM8903_OUTPUT_INT << shift);
-                snd_soc_write(codec, reg, val);
+                        if (wm8903->dcs_cache[i]) {
+                                dev_dbg(codec->dev,
+                                        "Restore DC servo %d value %x\n",
+                                        3 - i, wm8903->dcs_cache[i]);
+
+                                snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
+                                              wm8903->dcs_cache[i] & 0xff);
+                        } else {
+                                dev_dbg(codec->dev,
+                                        "Calibrate DC servo %d\n", 3 - i);
+                                dcs_mode = WM8903_DCS_MODE_START_STOP;
+                        }
+                }
 
-                /* Turn on the output ENA_OUTP */
-                val |= (WM8903_OUTPUT_OUT << shift);
-                snd_soc_write(codec, reg, val);
+                /* Don't trust the cache for analogue */
+                if (wm8903->class_w_users)
+                        dcs_mode = WM8903_DCS_MODE_START_STOP;
 
-                /* Enable the DC servo */
-                dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
-                dcs_reg |= dcs_bit;
-                snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
+                snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
+                                    WM8903_DCS_MODE_MASK, dcs_mode);
 
-                /* Remove the short */
-                val |= (WM8903_OUTPUT_SHORT << shift);
-                snd_soc_write(codec, reg, val);
-        }
+                snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
+                                    WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
 
-        if (event & SND_SOC_DAPM_PRE_PMD) {
-                val = snd_soc_read(codec, reg);
+                switch (dcs_mode) {
+                case WM8903_DCS_MODE_WRITE_STOP:
+                        break;
 
-                /* Short the output */
-                val &= ~(WM8903_OUTPUT_SHORT << shift);
-                snd_soc_write(codec, reg, val);
+                case WM8903_DCS_MODE_START_STOP:
+                        msleep(270);
 
-                /* Disable the DC servo */
-                dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
-                dcs_reg &= ~dcs_bit;
-                snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
+                        /* Cache the measured offsets for digital */
+                        if (wm8903->class_w_users)
+                                break;
 
-                /* Then disable the intermediate and output stages */
-                val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
-                          WM8903_OUTPUT_IN) << shift);
-                snd_soc_write(codec, reg, val);
-        }
+                        for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
+                                if (!(wm8903->dcs_pending & (1 << i)))
+                                        continue;
 
-        return 0;
+                                val = snd_soc_read(codec,
+                                                   WM8903_DC_SERVO_READBACK_1 + i);
+                                dev_dbg(codec->dev, "DC servo %d: %x\n",
+                                        3 - i, val);
+                                wm8903->dcs_cache[i] = val;
+                        }
+                        break;
+
+                default:
+                        pr_warn("DCS mode %d delay not set\n", dcs_mode);
+                        break;
+                }
+
+                wm8903->dcs_pending = 0;
+        }
 }
 
 /*
@@ -419,10 +382,10 @@ static int wm8903_output_event(struct snd_soc_dapm_widget *w,
 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
                               struct snd_ctl_elem_value *ucontrol)
 {
-        struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget *widget = wlist->widgets[0];
         struct snd_soc_codec *codec = widget->codec;
         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
-        struct i2c_client *i2c = codec->control_data;
         u16 reg;
         int ret;
 
@@ -431,7 +394,7 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
         /* Turn it off if we're about to enable bypass */
         if (ucontrol->value.integer.value[0]) {
                 if (wm8903->class_w_users == 0) {
-                        dev_dbg(&i2c->dev, "Disabling Class W\n");
+                        dev_dbg(codec->dev, "Disabling Class W\n");
                         snd_soc_write(codec, WM8903_CLASS_W_0, reg &
                                      ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
                 }
@@ -444,14 +407,14 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
         /* If we've just disabled the last bypass path turn Class W on */
         if (!ucontrol->value.integer.value[0]) {
                 if (wm8903->class_w_users == 1) {
-                        dev_dbg(&i2c->dev, "Enabling Class W\n");
+                        dev_dbg(codec->dev, "Enabling Class W\n");
                         snd_soc_write(codec, WM8903_CLASS_W_0, reg |
                                      WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
                 }
                 wm8903->class_w_users--;
         }
 
-        dev_dbg(&i2c->dev, "Bypass use count now %d\n",
+        dev_dbg(codec->dev, "Bypass use count now %d\n",
                 wm8903->class_w_users);
 
         return ret;
@@ -464,6 +427,72 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
 
 
+static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
+
+static int wm8903_set_deemph(struct snd_soc_codec *codec)
+{
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
+        int val, i, best;
+
+        /* If we're using deemphasis select the nearest available sample
+         * rate.
+         */
+        if (wm8903->deemph) {
+                best = 1;
+                for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
+                        if (abs(wm8903_deemph[i] - wm8903->fs) <
+                            abs(wm8903_deemph[best] - wm8903->fs))
+                                best = i;
+                }
+
+                val = best << WM8903_DEEMPH_SHIFT;
+        } else {
+                best = 0;
+                val = 0;
+        }
+
+        dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
+                best, wm8903_deemph[best]);
+
+        return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
+                                   WM8903_DEEMPH_MASK, val);
+}
+
+static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = wm8903->deemph;
+
+        return 0;
+}
+
+static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
+        int deemph = ucontrol->value.enumerated.item[0];
+        int ret = 0;
+
+        if (deemph > 1)
+                return -EINVAL;
+
+        mutex_lock(&codec->mutex);
+        if (wm8903->deemph != deemph) {
+                wm8903->deemph = deemph;
+
+                wm8903_set_deemph(codec);
+
+                ret = 1;
+        }
+        mutex_unlock(&codec->mutex);
+
+        return ret;
+}
+
 /* ALSA can only do steps of .01dB */
 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 
@@ -476,6 +505,23 @@ static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
 
+static const char *hpf_mode_text[] = {
+        "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
+};
+
+static const struct soc_enum hpf_mode =
+        SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
+
+static const char *osr_text[] = {
+        "Low power", "High performance"
+};
+
+static const struct soc_enum adc_osr =
+        SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
+
+static const struct soc_enum dac_osr =
+        SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
+
 static const char *drc_slope_text[] = {
         "1", "1/2", "1/4", "1/8", "1/16", "0"
 };
@@ -538,13 +584,6 @@ static const char *mute_mode_text[] = {
 static const struct soc_enum mute_mode =
         SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
 
-static const char *dac_deemphasis_text[] = {
-        "Disabled", "32kHz", "44.1kHz", "48kHz"
-};
-
-static const struct soc_enum dac_deemphasis =
-        SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
-
 static const char *companding_text[] = {
         "ulaw", "alaw"
 };
@@ -596,6 +635,29 @@ static const struct soc_enum lsidetone_enum =
 static const struct soc_enum rsidetone_enum =
         SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
 
+static const char *adcinput_text[] = {
+        "ADC", "DMIC"
+};
+
+static const struct soc_enum adcinput_enum =
+        SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text);
+
+static const char *aif_text[] = {
+        "Left", "Right"
+};
+
+static const struct soc_enum lcapture_enum =
+        SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
+
+static const struct soc_enum rcapture_enum =
+        SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
+
+static const struct soc_enum lplay_enum =
+        SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
+
+static const struct soc_enum rplay_enum =
+        SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
+
 static const struct snd_kcontrol_new wm8903_snd_controls[] = {
 
 /* Input PGAs - No TLV since the scale depends on PGA mode */
@@ -614,6 +676,9 @@ SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
            6, 1, 0),
 
 /* ADCs */
+SOC_ENUM("ADC OSR", adc_osr),
+SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
+SOC_ENUM("HPF Mode", hpf_mode),
 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
@@ -635,7 +700,7 @@ SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
 
 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
-                 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
+                 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
 SOC_ENUM("ADC Companding Mode", adc_companding),
 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
 
@@ -643,14 +708,16 @@ SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
                12, 0, digital_sidetone_tlv),
 
 /* DAC */
+SOC_ENUM("DAC OSR", dac_osr),
 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
                  WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
 SOC_ENUM("DAC Soft Mute Rate", soft_mute),
 SOC_ENUM("DAC Mute Mode", mute_mode),
 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
-SOC_ENUM("DAC De-emphasis", dac_deemphasis),
 SOC_ENUM("DAC Companding Mode", dac_companding),
 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
+SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
+                    wm8903_get_deemph, wm8903_put_deemph),
 
 /* Headphones */
 SOC_DOUBLE_R("Headphone Switch",
@@ -708,6 +775,21 @@ static const struct snd_kcontrol_new lsidetone_mux =
 static const struct snd_kcontrol_new rsidetone_mux =
         SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
 
+static const struct snd_kcontrol_new adcinput_mux =
+        SOC_DAPM_ENUM("ADC Input", adcinput_enum);
+
+static const struct snd_kcontrol_new lcapture_mux =
+        SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
+
+static const struct snd_kcontrol_new rcapture_mux =
+        SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
+
+static const struct snd_kcontrol_new lplay_mux =
+        SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
+
+static const struct snd_kcontrol_new rplay_mux =
+        SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
+
 static const struct snd_kcontrol_new left_output_mixer[] = {
 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
@@ -746,6 +828,7 @@ SND_SOC_DAPM_INPUT("IN2L"),
 SND_SOC_DAPM_INPUT("IN2R"),
 SND_SOC_DAPM_INPUT("IN3L"),
 SND_SOC_DAPM_INPUT("IN3R"),
+SND_SOC_DAPM_INPUT("DMICDAT"),
 
 SND_SOC_DAPM_OUTPUT("HPOUTL"),
 SND_SOC_DAPM_OUTPUT("HPOUTR"),
@@ -771,14 +854,29 @@ SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
 
-SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
-SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
+SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
+SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
+
+SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
+SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
+
+SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
+SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
+
+SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
 
 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
 
-SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
-SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
+SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
+
+SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
+SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
+
+SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
+SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
 
 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
                    left_output_mixer, ARRAY_SIZE(left_output_mixer)),
@@ -790,23 +888,51 @@ SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
 
-SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
-                   1, 0, NULL, 0, wm8903_output_event,
-                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
-                   SND_SOC_DAPM_PRE_PMD),
-SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
-                   0, 0, NULL, 0, wm8903_output_event,
-                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
-                   SND_SOC_DAPM_PRE_PMD),
-
-SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
-                   NULL, 0, wm8903_output_event,
-                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
-                   SND_SOC_DAPM_PRE_PMD),
-SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
-                   NULL, 0, wm8903_output_event,
-                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
-                   SND_SOC_DAPM_PRE_PMD),
+SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
+                   1, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
+                   0, 0, NULL, 0),
+
+SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
+                   NULL, 0),
+SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
+                   NULL, 0),
+
+SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
+
+SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
+                   NULL, 0),
+SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
+                   NULL, 0),
+SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
+                   NULL, 0),
+SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
+                   NULL, 0),
+SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
+                   NULL, 0),
+SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
+                   NULL, 0),
+SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
+                   NULL, 0),
+SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
+                   NULL, 0),
+
+SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
+                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
+                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
+                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
+                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 
 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
                  NULL, 0),
@@ -816,9 +942,17 @@ SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
                     wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
 };
 
-static const struct snd_soc_dapm_route intercon[] = {
+static const struct snd_soc_dapm_route wm8903_intercon[] = {
+
+        { "CLK_DSP", NULL, "CLK_SYS" },
+        { "Mic Bias", NULL, "CLK_SYS" },
+        { "HPL_DCS", NULL, "CLK_SYS" },
+        { "HPR_DCS", NULL, "CLK_SYS" },
+        { "LINEOUTL_DCS", NULL, "CLK_SYS" },
+        { "LINEOUTR_DCS", NULL, "CLK_SYS" },
 
         { "Left Input Mux", "IN1L", "IN1L" },
         { "Left Input Mux", "IN2L", "IN2L" },
@@ -860,18 +994,41 @@ static const struct snd_soc_dapm_route intercon[] = {
         { "Left Input PGA", NULL, "Left Input Mode Mux" },
         { "Right Input PGA", NULL, "Right Input Mode Mux" },
 
-        { "ADCL", NULL, "Left Input PGA" },
+        { "Left ADC Input", "ADC", "Left Input PGA" },
+        { "Left ADC Input", "DMIC", "DMICDAT" },
+        { "Right ADC Input", "ADC", "Right Input PGA" },
+        { "Right ADC Input", "DMIC", "DMICDAT" },
+
+        { "Left Capture Mux", "Left", "ADCL" },
+        { "Left Capture Mux", "Right", "ADCR" },
+
+        { "Right Capture Mux", "Left", "ADCL" },
+        { "Right Capture Mux", "Right", "ADCR" },
+
+        { "AIFTXL", NULL, "Left Capture Mux" },
+        { "AIFTXR", NULL, "Right Capture Mux" },
+
+        { "ADCL", NULL, "Left ADC Input" },
         { "ADCL", NULL, "CLK_DSP" },
-        { "ADCR", NULL, "Right Input PGA" },
+        { "ADCR", NULL, "Right ADC Input" },
         { "ADCR", NULL, "CLK_DSP" },
 
+        { "Left Playback Mux", "Left", "AIFRXL" },
+        { "Left Playback Mux", "Right", "AIFRXR" },
+
+        { "Right Playback Mux", "Left", "AIFRXL" },
+        { "Right Playback Mux", "Right", "AIFRXR" },
+
         { "DACL Sidetone", "Left", "ADCL" },
         { "DACL Sidetone", "Right", "ADCR" },
         { "DACR Sidetone", "Left", "ADCL" },
         { "DACR Sidetone", "Right", "ADCR" },
 
+        { "DACL", NULL, "Left Playback Mux" },
         { "DACL", NULL, "DACL Sidetone" },
         { "DACL", NULL, "CLK_DSP" },
+
+        { "DACR", NULL, "Right Playback Mux" },
         { "DACR", NULL, "DACR Sidetone" },
         { "DACR", NULL, "CLK_DSP" },
 
@@ -904,11 +1061,39 @@ static const struct snd_soc_dapm_route intercon[] = {
         { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
         { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
 
-        { "HPOUTL", NULL, "Left Headphone Output PGA" },
-        { "HPOUTR", NULL, "Right Headphone Output PGA" },
-
-        { "LINEOUTL", NULL, "Left Line Output PGA" },
-        { "LINEOUTR", NULL, "Right Line Output PGA" },
+        { "HPL_ENA", NULL, "Left Headphone Output PGA" },
+        { "HPR_ENA", NULL, "Right Headphone Output PGA" },
+        { "HPL_ENA_DLY", NULL, "HPL_ENA" },
+        { "HPR_ENA_DLY", NULL, "HPR_ENA" },
+        { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
+        { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
+        { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
+        { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
+
+        { "HPL_DCS", NULL, "DCS Master" },
+        { "HPR_DCS", NULL, "DCS Master" },
+        { "LINEOUTL_DCS", NULL, "DCS Master" },
+        { "LINEOUTR_DCS", NULL, "DCS Master" },
+
+        { "HPL_DCS", NULL, "HPL_ENA_DLY" },
+        { "HPR_DCS", NULL, "HPR_ENA_DLY" },
+        { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
+        { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
+
+        { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
+        { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
+        { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
+        { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
+
+        { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
+        { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
+        { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
+        { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
+
+        { "HPOUTL", NULL, "HPL_RMV_SHORT" },
+        { "HPOUTR", NULL, "HPR_RMV_SHORT" },
+        { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
+        { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
 
         { "LOP", NULL, "Left Speaker PGA" },
         { "LON", NULL, "Left Speaker PGA" },
@@ -922,78 +1107,116 @@ static const struct snd_soc_dapm_route intercon[] = {
         { "Right Line Output PGA", NULL, "Charge Pump" },
 };
 
-static int wm8903_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
-                                  ARRAY_SIZE(wm8903_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
-
-        return 0;
-}
-
 static int wm8903_set_bias_level(struct snd_soc_codec *codec,
                                  enum snd_soc_bias_level level)
 {
-        struct i2c_client *i2c = codec->control_data;
-        u16 reg, reg2;
-
         switch (level) {
         case SND_SOC_BIAS_ON:
+                break;
+
         case SND_SOC_BIAS_PREPARE:
-                reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
-                reg &= ~(WM8903_VMID_RES_MASK);
-                reg |= WM8903_VMID_RES_50K;
-                snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
+                snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
+                                    WM8903_VMID_RES_MASK,
+                                    WM8903_VMID_RES_50K);
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
-                        snd_soc_write(codec, WM8903_CLOCK_RATES_2,
-                                     WM8903_CLK_SYS_ENA);
-
-                        /* Change DC servo dither level in startup sequence */
-                        snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
-                        snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
-                        snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
-
-                        wm8903_run_sequence(codec, 0);
-                        wm8903_sync_reg_cache(codec, codec->reg_cache);
-
-                        /* Enable low impedence charge pump output */
-                        reg = snd_soc_read(codec,
-                                          WM8903_CONTROL_INTERFACE_TEST_1);
-                        snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
-                                     reg | WM8903_TEST_KEY);
-                        reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
-                        snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
-                                     reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
-                        snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
-                                     reg);
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
+                                            WM8903_POBCTRL | WM8903_ISEL_MASK |
+                                            WM8903_STARTUP_BIAS_ENA |
+                                            WM8903_BIAS_ENA,
+                                            WM8903_POBCTRL |
+                                            (2 << WM8903_ISEL_SHIFT) |
+                                            WM8903_STARTUP_BIAS_ENA);
+
+                        snd_soc_update_bits(codec,
+                                            WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
+                                            WM8903_SPK_DISCHARGE,
+                                            WM8903_SPK_DISCHARGE);
+
+                        msleep(33);
+
+                        snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
+                                            WM8903_SPKL_ENA | WM8903_SPKR_ENA,
+                                            WM8903_SPKL_ENA | WM8903_SPKR_ENA);
+
+                        snd_soc_update_bits(codec,
+                                            WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
+                                            WM8903_SPK_DISCHARGE, 0);
+
+                        snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
+                                            WM8903_VMID_TIE_ENA |
+                                            WM8903_BUFIO_ENA |
+                                            WM8903_VMID_IO_ENA |
+                                            WM8903_VMID_SOFT_MASK |
+                                            WM8903_VMID_RES_MASK |
+                                            WM8903_VMID_BUF_ENA,
+                                            WM8903_VMID_TIE_ENA |
+                                            WM8903_BUFIO_ENA |
+                                            WM8903_VMID_IO_ENA |
+                                            (2 << WM8903_VMID_SOFT_SHIFT) |
+                                            WM8903_VMID_RES_250K |
+                                            WM8903_VMID_BUF_ENA);
+
+                        msleep(129);
+
+                        snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
+                                            WM8903_SPKL_ENA | WM8903_SPKR_ENA,
+                                            0);
+
+                        snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
+                                            WM8903_VMID_SOFT_MASK, 0);
+
+                        snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
+                                            WM8903_VMID_RES_MASK,
+                                            WM8903_VMID_RES_50K);
+
+                        snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
+                                            WM8903_BIAS_ENA | WM8903_POBCTRL,
+                                            WM8903_BIAS_ENA);
 
                         /* By default no bypass paths are enabled so
                          * enable Class W support.
                          */
-                        dev_dbg(&i2c->dev, "Enabling Class W\n");
-                        snd_soc_write(codec, WM8903_CLASS_W_0, reg |
-                                     WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
+                        dev_dbg(codec->dev, "Enabling Class W\n");
+                        snd_soc_update_bits(codec, WM8903_CLASS_W_0,
+                                            WM8903_CP_DYN_FREQ |
+                                            WM8903_CP_DYN_V,
+                                            WM8903_CP_DYN_FREQ |
+                                            WM8903_CP_DYN_V);
                 }
 
-                reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
-                reg &= ~(WM8903_VMID_RES_MASK);
-                reg |= WM8903_VMID_RES_250K;
-                snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
+                snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
+                                    WM8903_VMID_RES_MASK,
+                                    WM8903_VMID_RES_250K);
                 break;
 
         case SND_SOC_BIAS_OFF:
-                wm8903_run_sequence(codec, 32);
-                reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
-                reg &= ~WM8903_CLK_SYS_ENA;
-                snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
+                snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
+                                    WM8903_BIAS_ENA, 0);
+
+                snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
+                                    WM8903_VMID_SOFT_MASK,
+                                    2 << WM8903_VMID_SOFT_SHIFT);
+
+                snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
+                                    WM8903_VMID_BUF_ENA, 0);
+
+                msleep(290);
+
+                snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
+                                    WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
+                                    WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
+                                    WM8903_VMID_SOFT_MASK |
+                                    WM8903_VMID_BUF_ENA, 0);
+
+                snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
+                                    WM8903_STARTUP_BIAS_ENA, 0);
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -1224,70 +1447,13 @@ static struct {
         { 0,      0 },
 };
 
-static int wm8903_startup(struct snd_pcm_substream *substream,
-                          struct snd_soc_dai *dai)
-{
-        struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
-        struct i2c_client *i2c = codec->control_data;
-        struct snd_pcm_runtime *master_runtime;
-
-        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-                wm8903->playback_active++;
-        else
-                wm8903->capture_active++;
-
-        /* The DAI has shared clocks so if we already have a playback or
-         * capture going then constrain this substream to match it.
-         */
-        if (wm8903->master_substream) {
-                master_runtime = wm8903->master_substream->runtime;
-
-                dev_dbg(&i2c->dev, "Constraining to %d bits\n",
-                        master_runtime->sample_bits);
-
-                snd_pcm_hw_constraint_minmax(substream->runtime,
-                                             SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
-                                             master_runtime->sample_bits,
-                                             master_runtime->sample_bits);
-
-                wm8903->slave_substream = substream;
-        } else
-                wm8903->master_substream = substream;
-
-        return 0;
-}
-
-static void wm8903_shutdown(struct snd_pcm_substream *substream,
-                            struct snd_soc_dai *dai)
-{
-        struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
-        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
-
-        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-                wm8903->playback_active--;
-        else
-                wm8903->capture_active--;
-
-        if (wm8903->master_substream == substream)
-                wm8903->master_substream = wm8903->slave_substream;
-
-        wm8903->slave_substream = NULL;
-}
-
 static int wm8903_hw_params(struct snd_pcm_substream *substream,
                             struct snd_pcm_hw_params *params,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec =rtd->codec;
         struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
-        struct i2c_client *i2c = codec->control_data;
         int fs = params_rate(params);
         int bclk;
         int bclk_div;
@@ -1305,11 +1471,6 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
         u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
         u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
 
-        if (substream == wm8903->slave_substream) {
-                dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
-                return 0;
-        }
-
         /* Enable sloping stopband filter for low sample rates */
         if (fs <= 24000)
                 dac_digital1 |= WM8903_DAC_SB_FILT;
@@ -1327,20 +1488,7 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
                 }
         }
 
-        /* Constraints should stop us hitting this but let's make sure */
-        if (wm8903->capture_active)
-                switch (sample_rates[dsp_config].rate) {
-                case 88200:
-                case 96000:
-                        dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
-                                fs);
-                        return -EINVAL;
-
-                default:
-                        break;
-                }
-
-        dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
+        dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
         clock1 &= ~WM8903_SAMPLE_RATE_MASK;
         clock1 |= sample_rates[dsp_config].value;
 
@@ -1366,7 +1514,7 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
                 return -EINVAL;
         }
 
-        dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
+        dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
                 wm8903->sysclk, fs);
 
         /* We may not have an MCLK which allows us to generate exactly
@@ -1401,12 +1549,12 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
         clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
         clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
 
-        dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
+        dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
                 clk_sys_ratios[clk_config].rate,
                 clk_sys_ratios[clk_config].mode,
                 clk_sys_ratios[clk_config].div);
 
-        dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
+        dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
 
         /* We may not get quite the right frequency if using
          * approximate clocks so look for the closest match that is
@@ -1428,13 +1576,16 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
         aif2 &= ~WM8903_BCLK_DIV_MASK;
         aif3 &= ~WM8903_LRCLK_RATE_MASK;
 
-        dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
+        dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
                 bclk_divs[bclk_div].ratio / 10, bclk,
                 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
 
         aif2 |= bclk_divs[bclk_div].div;
         aif3 |= bclk / fs;
 
+        wm8903->fs = params_rate(params);
+        wm8903_set_deemph(codec);
+
         snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
         snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
         snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
@@ -1486,7 +1637,7 @@ int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
                             WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
                             irq_mask);
 
-        if (det && shrt) {
+        if (det || shrt) {
                 /* Enable mic detection, this may not have been set through
                  * platform data (eg, if the defaults are OK). */
                 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
@@ -1504,8 +1655,8 @@ EXPORT_SYMBOL_GPL(wm8903_mic_detect);
 
 static irqreturn_t wm8903_irq(int irq, void *data)
 {
-        struct wm8903_priv *wm8903 = data;
-        struct snd_soc_codec *codec = &wm8903->codec;
+        struct snd_soc_codec *codec = data;
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
         int mic_report;
         int int_pol;
         int int_val = 0;
@@ -1514,8 +1665,7 @@ static irqreturn_t wm8903_irq(int irq, void *data)
         int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
 
         if (int_val & WM8903_WSEQ_BUSY_EINT) {
-                dev_dbg(codec->dev, "Write sequencer done\n");
-                complete(&wm8903->wseq);
+                dev_warn(codec->dev, "Write sequencer done\n");
         }
 
         /*
@@ -1528,6 +1678,11 @@ static irqreturn_t wm8903_irq(int irq, void *data)
         mic_report = wm8903->mic_last_report;
         int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
 
+#ifndef CONFIG_SND_SOC_WM8903_MODULE
+        if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
+                trace_snd_soc_jack_irq(dev_name(codec->dev));
+#endif
+
         if (int_val & WM8903_MICSHRT_EINT) {
                 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
 
@@ -1578,16 +1733,14 @@ static irqreturn_t wm8903_irq(int irq, void *data)
                         SNDRV_PCM_FMTBIT_S24_LE)
 
 static struct snd_soc_dai_ops wm8903_dai_ops = {
-        .startup        = wm8903_startup,
-        .shutdown       = wm8903_shutdown,
         .hw_params      = wm8903_hw_params,
         .digital_mute   = wm8903_digital_mute,
         .set_fmt        = wm8903_set_dai_fmt,
         .set_sysclk     = wm8903_set_dai_sysclk,
 };
 
-struct snd_soc_dai wm8903_dai = {
-        .name = "WM8903",
+static struct snd_soc_dai_driver wm8903_dai = {
+        .name = "wm8903-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -1605,23 +1758,16 @@ struct snd_soc_dai wm8903_dai = {
         .ops = &wm8903_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8903_dai);
 
-static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm8903_resume(struct platform_device *pdev)
+static int wm8903_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-        struct i2c_client *i2c = codec->control_data;
         int i;
         u16 *reg_cache = codec->reg_cache;
         u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
@@ -1637,77 +1783,177 @@ static int wm8903_resume(struct platform_device *pdev)
                                 snd_soc_write(codec, i, tmp_cache[i]);
                 kfree(tmp_cache);
         } else {
-                dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
+                dev_err(codec->dev, "Failed to allocate temporary cache\n");
         }
 
         return 0;
 }
 
-static struct snd_soc_codec *wm8903_codec;
+#ifdef CONFIG_GPIOLIB
+static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
+{
+        return container_of(chip, struct wm8903_priv, gpio_chip);
+}
 
-static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
-                                      const struct i2c_device_id *id)
+static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
 {
-        struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
-        struct wm8903_priv *wm8903;
-        struct snd_soc_codec *codec;
-        int ret, i;
-        int trigger, irq_pol;
-        u16 val;
+        if (offset >= WM8903_NUM_GPIO)
+                return -EINVAL;
 
-        wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
-        if (wm8903 == NULL)
-                return -ENOMEM;
+        return 0;
+}
 
-        codec = &wm8903->codec;
+static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+        struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
+        struct snd_soc_codec *codec = wm8903->codec;
+        unsigned int mask, val;
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
+        mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
+        val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
+                WM8903_GP1_DIR;
 
-        codec->dev = &i2c->dev;
-        codec->name = "WM8903";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8903_set_bias_level;
-        codec->dai = &wm8903_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
-        codec->reg_cache = &wm8903->reg_cache[0];
-        snd_soc_codec_set_drvdata(codec, wm8903);
-        codec->volatile_register = wm8903_volatile_register;
-        init_completion(&wm8903->wseq);
+        return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
+                                   mask, val);
+}
+
+static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
+        struct snd_soc_codec *codec = wm8903->codec;
+        int reg;
 
-        i2c_set_clientdata(i2c, codec);
-        codec->control_data = i2c;
+        reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
+
+        return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
+}
+
+static int wm8903_gpio_direction_out(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
+        struct snd_soc_codec *codec = wm8903->codec;
+        unsigned int mask, val;
+
+        mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
+        val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
+                (value << WM8903_GP2_LVL_SHIFT);
+
+        return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
+                                   mask, val);
+}
+
+static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
+        struct snd_soc_codec *codec = wm8903->codec;
+
+        snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
+                            WM8903_GP1_LVL_MASK,
+                            !!value << WM8903_GP1_LVL_SHIFT);
+}
+
+static struct gpio_chip wm8903_template_chip = {
+        .label                  = "wm8903",
+        .owner                  = THIS_MODULE,
+        .request                = wm8903_gpio_request,
+        .direction_input        = wm8903_gpio_direction_in,
+        .get                    = wm8903_gpio_get,
+        .direction_output       = wm8903_gpio_direction_out,
+        .set                    = wm8903_gpio_set,
+        .can_sleep              = 1,
+};
+
+static void wm8903_init_gpio(struct snd_soc_codec *codec)
+{
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
+        struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
+        int ret;
+
+        wm8903->gpio_chip = wm8903_template_chip;
+        wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
+        wm8903->gpio_chip.dev = codec->dev;
+
+        if (pdata && pdata->gpio_base)
+                wm8903->gpio_chip.base = pdata->gpio_base;
+        else
+                wm8903->gpio_chip.base = -1;
+
+        ret = gpiochip_add(&wm8903->gpio_chip);
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
+}
+
+static void wm8903_free_gpio(struct snd_soc_codec *codec)
+{
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        ret = gpiochip_remove(&wm8903->gpio_chip);
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
+}
+#else
+static void wm8903_init_gpio(struct snd_soc_codec *codec)
+{
+}
+
+static void wm8903_free_gpio(struct snd_soc_codec *codec)
+{
+}
+#endif
+
+static int wm8903_probe(struct snd_soc_codec *codec)
+{
+        struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
+        struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
+        int ret, i;
+        int trigger, irq_pol;
+        u16 val;
+
+        wm8903->codec = codec;
 
         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
         if (ret != 0) {
-                dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
         val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
         if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
-                dev_err(&i2c->dev,
+                dev_err(codec->dev,
                         "Device with ID register %x is not a WM8903\n", val);
                 return -ENODEV;
         }
 
         val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
-        dev_info(&i2c->dev, "WM8903 revision %d\n",
-                 val & WM8903_CHIP_REV_MASK);
+        dev_info(codec->dev, "WM8903 revision %c\n",
+                 (val & WM8903_CHIP_REV_MASK) + 'A');
 
         wm8903_reset(codec);
 
         /* Set up GPIOs and microphone detection */
         if (pdata) {
+                bool mic_gpio = false;
+
                 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
-                        if (!pdata->gpio_cfg[i])
+                        if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
                                 continue;
 
                         snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
                                       pdata->gpio_cfg[i] & 0xffff);
+
+                        val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
+                                >> WM8903_GP1_FN_SHIFT;
+
+                        switch (val) {
+                        case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
+                        case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
+                                mic_gpio = true;
+                                break;
+                        default:
+                                break;
+                        }
                 }
 
                 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
@@ -1718,10 +1964,18 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
                         snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
                                             WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
 
+                /* If microphone detection is enabled by pdata but
+                 * detected via IRQ then interrupts can be lost before
+                 * the machine driver has set up microphone detection
+                 * IRQs as the IRQs are clear on read.  The detection
+                 * will be enabled when the machine driver configures.
+                 */
+                WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
+
                 wm8903->mic_delay = pdata->micdet_delay;
         }
         
-        if (i2c->irq) {
+        if (wm8903->irq) {
                 if (pdata && pdata->irq_active_low) {
                         trigger = IRQF_TRIGGER_LOW;
                         irq_pol = WM8903_IRQ_POL;
@@ -1733,13 +1987,13 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
                 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
                                     WM8903_IRQ_POL, irq_pol);
                 
-                ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
+                ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
                                            trigger | IRQF_ONESHOT,
-                                           "wm8903", wm8903);
+                                           "wm8903", codec);
                 if (ret != 0) {
-                        dev_err(&i2c->dev, "Failed to request IRQ: %d\n",
+                        dev_err(codec->dev, "Failed to request IRQ: %d\n",
                                 ret);
-                        goto err;
+                        return ret;
                 }
 
                 /* Enable write sequencer interrupts */
@@ -1777,137 +2031,107 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
         snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
 
         /* Enable DAC soft mute by default */
-        val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
-        val |= WM8903_DAC_MUTEMODE;
-        snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
+        snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
+                            WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
+                            WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
 
-        wm8903_dai.dev = &i2c->dev;
-        wm8903_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
-                goto err_irq;
-        }
-
-        ret = snd_soc_register_dai(&wm8903_dai);
-        if (ret != 0) {
-                dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+        snd_soc_add_controls(codec, wm8903_snd_controls,
+                                ARRAY_SIZE(wm8903_snd_controls));
 
-        return ret;
+        wm8903_init_gpio(codec);
 
-err_codec:
-        snd_soc_unregister_codec(codec);
-err_irq:
-        if (i2c->irq)
-                free_irq(i2c->irq, wm8903);
-err:
-        wm8903_codec = NULL;
-        kfree(wm8903);
         return ret;
 }
 
-static __devexit int wm8903_i2c_remove(struct i2c_client *client)
+/* power down chip */
+static int wm8903_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = i2c_get_clientdata(client);
-        struct wm8903_priv *priv = snd_soc_codec_get_drvdata(codec);
+        wm8903_free_gpio(codec);
+        wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
 
-        snd_soc_unregister_dai(&wm8903_dai);
-        snd_soc_unregister_codec(codec);
+static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
+        .probe =        wm8903_probe,
+        .remove =       wm8903_remove,
+        .suspend =      wm8903_suspend,
+        .resume =       wm8903_resume,
+        .set_bias_level = wm8903_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8903_reg_defaults,
+        .volatile_register = wm8903_volatile_register,
+        .seq_notifier = wm8903_seq_notifier,
+        .dapm_widgets = wm8903_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
+        .dapm_routes = wm8903_intercon,
+        .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
+};
 
-        wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8903_priv *wm8903;
+        int ret;
 
-        if (client->irq)
-                free_irq(client->irq, priv);
+        wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
+        if (wm8903 == NULL)
+                return -ENOMEM;
 
-        kfree(priv);
+        i2c_set_clientdata(i2c, wm8903);
+        wm8903->irq = i2c->irq;
 
-        wm8903_codec = NULL;
-        wm8903_dai.dev = NULL;
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8903, &wm8903_dai, 1);
+        if (ret < 0)
+                kfree(wm8903);
+        return ret;
+}
 
+static __devexit int wm8903_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
-/* i2c codec control layer */
 static const struct i2c_device_id wm8903_i2c_id[] = {
-       { "wm8903", 0 },
-       { }
+        { "wm8903", 0 },
+        { }
 };
 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
 
 static struct i2c_driver wm8903_i2c_driver = {
         .driver = {
-                .name = "WM8903",
+                .name = "wm8903",
                 .owner = THIS_MODULE,
         },
-        .probe    = wm8903_i2c_probe,
-        .remove   = __devexit_p(wm8903_i2c_remove),
+        .probe =    wm8903_i2c_probe,
+        .remove =   __devexit_p(wm8903_i2c_remove),
         .id_table = wm8903_i2c_id,
 };
+#endif
 
-static int wm8903_probe(struct platform_device *pdev)
+static int __init wm8903_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
         int ret = 0;
-
-        if (!wm8903_codec) {
-                dev_err(&pdev->dev, "I2C device not yet probed\n");
-                goto err;
-        }
-
-        socdev->card->codec = wm8903_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "failed to create pcms\n");
-                goto err;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8903_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
+                       ret);
         }
-
-        snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
-                                ARRAY_SIZE(wm8903_snd_controls));
-        wm8903_add_widgets(socdev->card->codec);
-
-        return ret;
-
-err:
+#endif
         return ret;
 }
-
-/* power down chip */
-static int wm8903_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec->control_data)
-                wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8903 = {
-        .probe =        wm8903_probe,
-        .remove =       wm8903_remove,
-        .suspend =      wm8903_suspend,
-        .resume =       wm8903_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
-
-static int __init wm8903_modinit(void)
-{
-        return i2c_add_driver(&wm8903_i2c_driver);
-}
 module_init(wm8903_modinit);
 
 static void __exit wm8903_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm8903_i2c_driver);
+#endif
 }
 module_exit(wm8903_exit);
 
diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h
index ce384a2ad820..db949311c0f2 100644
--- a/sound/soc/codecs/wm8903.h
+++ b/sound/soc/codecs/wm8903.h
@@ -15,17 +15,10 @@
 
 #include <linux/i2c.h>
 
-extern struct snd_soc_dai wm8903_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8903;
-
 extern int wm8903_mic_detect(struct snd_soc_codec *codec,
                              struct snd_soc_jack *jack,
                              int det, int shrt);
 
-#define WM8903_MCLK_DIV_2 1
-#define WM8903_CLK_SYS    2
-#define WM8903_BCLK       3
-#define WM8903_LRCLK      4
 
 /*
  * Register values.
@@ -82,6 +75,14 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
 #define WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0    0x41
 #define WM8903_DC_SERVO_0                       0x43
 #define WM8903_DC_SERVO_2                       0x45
+#define WM8903_DC_SERVO_4                       0x47
+#define WM8903_DC_SERVO_5                       0x48
+#define WM8903_DC_SERVO_6                       0x49
+#define WM8903_DC_SERVO_7                       0x4A
+#define WM8903_DC_SERVO_READBACK_1              0x51
+#define WM8903_DC_SERVO_READBACK_2              0x52
+#define WM8903_DC_SERVO_READBACK_3              0x53
+#define WM8903_DC_SERVO_READBACK_4              0x54
 #define WM8903_ANALOGUE_HP_0                    0x5A
 #define WM8903_ANALOGUE_LINEOUT_0               0x5E
 #define WM8903_CHARGE_PUMP_0                    0x62
@@ -101,8 +102,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
 #define WM8903_INTERRUPT_STATUS_1_MASK          0x7A
 #define WM8903_INTERRUPT_POLARITY_1             0x7B
 #define WM8903_INTERRUPT_CONTROL                0x7E
-#define WM8903_CONTROL_INTERFACE_TEST_1         0x81
-#define WM8903_CHARGE_PUMP_TEST_1               0x95
 #define WM8903_CLOCK_RATE_TEST_4                0xA4
 #define WM8903_ANALOGUE_OUTPUT_BIAS_0           0xAC
 
@@ -174,7 +173,7 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
 
 #define WM8903_VMID_RES_50K                          2
 #define WM8903_VMID_RES_250K                         3
-#define WM8903_VMID_RES_5K                           4
+#define WM8903_VMID_RES_5K                           6
 
 /*
  * R8 (0x08) - Analogue DAC 0
@@ -1209,25 +1208,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
 #define WM8903_IRQ_POL_WIDTH                         1  /* IRQ_POL */
 
 /*
- * R129 (0x81) - Control Interface Test 1
- */
-#define WM8903_USER_KEY                         0x0002  /* USER_KEY */
-#define WM8903_USER_KEY_MASK                    0x0002  /* USER_KEY */
-#define WM8903_USER_KEY_SHIFT                        1  /* USER_KEY */
-#define WM8903_USER_KEY_WIDTH                        1  /* USER_KEY */
-#define WM8903_TEST_KEY                         0x0001  /* TEST_KEY */
-#define WM8903_TEST_KEY_MASK                    0x0001  /* TEST_KEY */
-#define WM8903_TEST_KEY_SHIFT                        0  /* TEST_KEY */
-#define WM8903_TEST_KEY_WIDTH                        1  /* TEST_KEY */
-
-/*
- * R149 (0x95) - Charge Pump Test 1
- */
-#define WM8903_CP_SW_KELVIN_MODE_MASK           0x0006  /* CP_SW_KELVIN_MODE - [2:1] */
-#define WM8903_CP_SW_KELVIN_MODE_SHIFT               1  /* CP_SW_KELVIN_MODE - [2:1] */
-#define WM8903_CP_SW_KELVIN_MODE_WIDTH               2  /* CP_SW_KELVIN_MODE - [2:1] */
-
-/*
  * R164 (0xA4) - Clock Rate Test 4
  */
 #define WM8903_ADC_DIG_MIC                      0x0200  /* ADC_DIG_MIC */
diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
index f7dcabf6283c..9b3bba4df5b3 100644
--- a/sound/soc/codecs/wm8904.c
+++ b/sound/soc/codecs/wm8904.c
@@ -24,16 +24,12 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 #include <sound/wm8904.h>
 
 #include "wm8904.h"
 
-static struct snd_soc_codec *wm8904_codec;
-struct snd_soc_codec_device soc_codec_dev_wm8904;
-
 enum wm8904_type {
         WM8904,
         WM8912,
@@ -52,10 +48,9 @@ static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
 
 /* codec private data */
 struct wm8904_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM8904_MAX_REGISTER + 1];
 
         enum wm8904_type devtype;
+        void *control_data;
 
         struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
 
@@ -601,7 +596,7 @@ static struct {
         { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */
 };
 
-static int wm8904_volatile_register(unsigned int reg)
+static int wm8904_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
 {
         return wm8904_access[reg].vol;
 }
@@ -689,7 +684,7 @@ static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
                                struct snd_ctl_elem_value *ucontrol)
 {
         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);  
+        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
         struct wm8904_pdata *pdata = wm8904->pdata;
         int value = ucontrol->value.integer.value[0];
 
@@ -760,7 +755,7 @@ static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
                                          struct snd_ctl_elem_value *ucontrol)
 {
         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);  
+        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
         struct wm8904_pdata *pdata = wm8904->pdata;
         int value = ucontrol->value.integer.value[0];
 
@@ -820,7 +815,8 @@ static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 
-        return wm8904->deemph;
+        ucontrol->value.enumerated.item[0] = wm8904->deemph;
+        return 0;
 }
 
 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
@@ -1430,10 +1426,11 @@ static const struct snd_soc_dapm_route wm8912_intercon[] = {
 static int wm8904_add_widgets(struct snd_soc_codec *codec)
 {
         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets,
+        snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
                                   ARRAY_SIZE(wm8904_core_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, core_intercon,
+        snd_soc_dapm_add_routes(dapm, core_intercon,
                                 ARRAY_SIZE(core_intercon));
 
         switch (wm8904->devtype) {
@@ -1445,20 +1442,20 @@ static int wm8904_add_widgets(struct snd_soc_codec *codec)
                 snd_soc_add_controls(codec, wm8904_snd_controls,
                                      ARRAY_SIZE(wm8904_snd_controls));
 
-                snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets,
+                snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
                                           ARRAY_SIZE(wm8904_adc_dapm_widgets));
-                snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets,
+                snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
                                           ARRAY_SIZE(wm8904_dac_dapm_widgets));
-                snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets,
+                snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
                                           ARRAY_SIZE(wm8904_dapm_widgets));
 
-                snd_soc_dapm_add_routes(codec, core_intercon,
+                snd_soc_dapm_add_routes(dapm, core_intercon,
                                         ARRAY_SIZE(core_intercon));
-                snd_soc_dapm_add_routes(codec, adc_intercon,
+                snd_soc_dapm_add_routes(dapm, adc_intercon,
                                         ARRAY_SIZE(adc_intercon));
-                snd_soc_dapm_add_routes(codec, dac_intercon,
+                snd_soc_dapm_add_routes(dapm, dac_intercon,
                                         ARRAY_SIZE(dac_intercon));
-                snd_soc_dapm_add_routes(codec, wm8904_intercon,
+                snd_soc_dapm_add_routes(dapm, wm8904_intercon,
                                         ARRAY_SIZE(wm8904_intercon));
                 break;
 
@@ -1466,17 +1463,17 @@ static int wm8904_add_widgets(struct snd_soc_codec *codec)
                 snd_soc_add_controls(codec, wm8904_dac_snd_controls,
                                      ARRAY_SIZE(wm8904_dac_snd_controls));
 
-                snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets,
+                snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
                                           ARRAY_SIZE(wm8904_dac_dapm_widgets));
 
-                snd_soc_dapm_add_routes(codec, dac_intercon,
+                snd_soc_dapm_add_routes(dapm, dac_intercon,
                                         ARRAY_SIZE(dac_intercon));
-                snd_soc_dapm_add_routes(codec, wm8912_intercon,
+                snd_soc_dapm_add_routes(dapm, wm8912_intercon,
                                         ARRAY_SIZE(wm8912_intercon));
                 break;
         }
 
-        snd_soc_dapm_new_widgets(codec);
+        snd_soc_dapm_new_widgets(dapm);
         return 0;
 }
 
@@ -1592,7 +1589,7 @@ static int wm8904_hw_params(struct snd_pcm_substream *substream,
                        - wm8904->fs);
         for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
                 cur_val = abs((wm8904->sysclk_rate /
-                               clk_sys_rates[i].ratio) - wm8904->fs);;
+                               clk_sys_rates[i].ratio) - wm8904->fs);
                 if (cur_val < best_val) {
                         best = i;
                         best_val = cur_val;
@@ -1898,7 +1895,7 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
 
         pr_debug("Fvco=%dHz\n", target);
 
-        /* Find an appropraite FLL_FRATIO and factor it out of the target */
+        /* Find an appropriate FLL_FRATIO and factor it out of the target */
         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
@@ -2095,7 +2092,7 @@ static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 
 static void wm8904_sync_cache(struct snd_soc_codec *codec)
 {
-        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
+        u16 *reg_cache = codec->reg_cache;
         int i;
 
         if (!codec->cache_sync)
@@ -2106,14 +2103,14 @@ static void wm8904_sync_cache(struct snd_soc_codec *codec)
         /* Sync back cached values if they're different from the
          * hardware default.
          */
-        for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) {
+        for (i = 1; i < codec->driver->reg_cache_size; i++) {
                 if (!wm8904_access[i].writable)
                         continue;
 
-                if (wm8904->reg_cache[i] == wm8904_reg[i])
+                if (reg_cache[i] == wm8904_reg[i])
                         continue;
 
-                snd_soc_write(codec, i, wm8904->reg_cache[i]);
+                snd_soc_write(codec, i, reg_cache[i]);
         }
 
         codec->cache_sync = 0;
@@ -2141,7 +2138,7 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
                                                     wm8904->supplies);
                         if (ret != 0) {
@@ -2200,7 +2197,7 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec,
                                        wm8904->supplies);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -2218,8 +2215,8 @@ static struct snd_soc_dai_ops wm8904_dai_ops = {
         .digital_mute = wm8904_digital_mute,
 };
 
-struct snd_soc_dai wm8904_dai = {
-        .name = "WM8904",
+static struct snd_soc_dai_driver wm8904_dai = {
+        .name = "wm8904-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -2237,24 +2234,17 @@ struct snd_soc_dai wm8904_dai = {
         .ops = &wm8904_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8904_dai);
 
 #ifdef CONFIG_PM
-static int wm8904_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8904_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm8904_resume(struct platform_device *pdev)
+static int wm8904_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
@@ -2264,9 +2254,9 @@ static int wm8904_resume(struct platform_device *pdev)
 #define wm8904_resume NULL
 #endif
 
-static void wm8904_handle_retune_mobile_pdata(struct wm8904_priv *wm8904)
+static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = &wm8904->codec;
+        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
         struct wm8904_pdata *pdata = wm8904->pdata;
         struct snd_kcontrol_new control =
                 SOC_ENUM_EXT("EQ Mode",
@@ -2315,20 +2305,20 @@ static void wm8904_handle_retune_mobile_pdata(struct wm8904_priv *wm8904)
         wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts;
         wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
 
-        ret = snd_soc_add_controls(&wm8904->codec, &control, 1);
+        ret = snd_soc_add_controls(codec, &control, 1);
         if (ret != 0)
-                dev_err(wm8904->codec.dev,
+                dev_err(codec->dev,
                         "Failed to add ReTune Mobile control: %d\n", ret);
 }
 
-static void wm8904_handle_pdata(struct wm8904_priv *wm8904)
+static void wm8904_handle_pdata(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = &wm8904->codec;
+        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
         struct wm8904_pdata *pdata = wm8904->pdata;
         int ret, i;
 
         if (!pdata) {
-                snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls,
+                snd_soc_add_controls(codec, wm8904_eq_controls,
                                      ARRAY_SIZE(wm8904_eq_controls));
                 return;
         }
@@ -2344,7 +2334,7 @@ static void wm8904_handle_pdata(struct wm8904_priv *wm8904)
                 wm8904->drc_texts = kmalloc(sizeof(char *)
                                             * pdata->num_drc_cfgs, GFP_KERNEL);
                 if (!wm8904->drc_texts) {
-                        dev_err(wm8904->codec.dev,
+                        dev_err(codec->dev,
                                 "Failed to allocate %d DRC config texts\n",
                                 pdata->num_drc_cfgs);
                         return;
@@ -2356,9 +2346,9 @@ static void wm8904_handle_pdata(struct wm8904_priv *wm8904)
                 wm8904->drc_enum.max = pdata->num_drc_cfgs;
                 wm8904->drc_enum.texts = wm8904->drc_texts;
 
-                ret = snd_soc_add_controls(&wm8904->codec, &control, 1);
+                ret = snd_soc_add_controls(codec, &control, 1);
                 if (ret != 0)
-                        dev_err(wm8904->codec.dev,
+                        dev_err(codec->dev,
                                 "Failed to add DRC mode control: %d\n", ret);
 
                 wm8904_set_drc(codec);
@@ -2368,91 +2358,22 @@ static void wm8904_handle_pdata(struct wm8904_priv *wm8904)
                 pdata->num_retune_mobile_cfgs);
 
         if (pdata->num_retune_mobile_cfgs)
-                wm8904_handle_retune_mobile_pdata(wm8904);
+                wm8904_handle_retune_mobile_pdata(codec);
         else
-                snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls,
+                snd_soc_add_controls(codec, wm8904_eq_controls,
                                      ARRAY_SIZE(wm8904_eq_controls));
 }
 
-static int wm8904_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8904_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8904_codec;
-        codec = wm8904_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        wm8904_handle_pdata(snd_soc_codec_get_drvdata(codec));
-
-        wm8904_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-static int wm8904_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8904 = {
-        .probe =        wm8904_probe,
-        .remove =       wm8904_remove,
-        .suspend =      wm8904_suspend,
-        .resume =       wm8904_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904);
 
-static int wm8904_register(struct wm8904_priv *wm8904,
-                           enum snd_soc_control_type control)
+static int wm8904_probe(struct snd_soc_codec *codec)
 {
+        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
         struct wm8904_pdata *pdata = wm8904->pdata;
-        int ret;
-        struct snd_soc_codec *codec = &wm8904->codec;
-        int i;
-
-        if (wm8904_codec) {
-                dev_err(codec->dev, "Another WM8904 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
+        u16 *reg_cache = codec->reg_cache;
+        int ret, i;
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8904);
-        codec->name = "WM8904";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8904_set_bias_level;
-        codec->dai = &wm8904_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8904_MAX_REGISTER;
-        codec->reg_cache = &wm8904->reg_cache;
-        codec->volatile_register = wm8904_volatile_register;
         codec->cache_sync = 1;
-        codec->idle_bias_off = 1;
+        codec->dapm.idle_bias_off = 1;
 
         switch (wm8904->devtype) {
         case WM8904:
@@ -2463,16 +2384,13 @@ static int wm8904_register(struct wm8904_priv *wm8904,
         default:
                 dev_err(codec->dev, "Unknown device type %d\n",
                         wm8904->devtype);
-                ret = -EINVAL;
-                goto err;
+                return -EINVAL;
         }
 
-        memcpy(codec->reg_cache, wm8904_reg, sizeof(wm8904_reg));
-
-        ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
@@ -2482,7 +2400,7 @@ static int wm8904_register(struct wm8904_priv *wm8904,
                                  wm8904->supplies);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
@@ -2517,22 +2435,29 @@ static int wm8904_register(struct wm8904_priv *wm8904,
                 goto err_enable;
         }
 
-        wm8904_dai.dev = codec->dev;
-
         /* Change some default settings - latch VU and enable ZC */
-        wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU;
-        wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU;
-        wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU;
-        wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU;
-        wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU |
-                WM8904_HPOUTLZC;
-        wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU |
-                WM8904_HPOUTRZC;
-        wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU |
-                WM8904_LINEOUTLZC;
-        wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU |
-                WM8904_LINEOUTRZC;
-        wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
+        snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_LEFT,
+                            WM8904_ADC_VU, WM8904_ADC_VU);
+        snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
+                            WM8904_ADC_VU, WM8904_ADC_VU);
+        snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_LEFT,
+                            WM8904_DAC_VU, WM8904_DAC_VU);
+        snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
+                            WM8904_DAC_VU, WM8904_DAC_VU);
+        snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_LEFT,
+                            WM8904_HPOUT_VU | WM8904_HPOUTLZC,
+                            WM8904_HPOUT_VU | WM8904_HPOUTLZC);
+        snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_RIGHT,
+                            WM8904_HPOUT_VU | WM8904_HPOUTRZC,
+                            WM8904_HPOUT_VU | WM8904_HPOUTRZC);
+        snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_LEFT,
+                            WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
+                            WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
+        snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_RIGHT,
+                            WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
+                            WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
+        snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0,
+                            WM8904_SR_MODE, 0);
 
         /* Apply configuration from the platform data. */
         if (wm8904->pdata) {
@@ -2540,95 +2465,95 @@ static int wm8904_register(struct wm8904_priv *wm8904,
                         if (!pdata->gpio_cfg[i])
                                 continue;
 
-                        wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i]
+                        reg_cache[WM8904_GPIO_CONTROL_1 + i]
                                 = pdata->gpio_cfg[i] & 0xffff;
                 }
 
                 /* Zero is the default value for these anyway */
                 for (i = 0; i < WM8904_MIC_REGS; i++)
-                        wm8904->reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i]
+                        reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i]
                                 = pdata->mic_cfg[i];
         }
 
         /* Set Class W by default - this will be managed by the Class
          * G widget at runtime where bypass paths are available.
          */
-        wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR;
+        snd_soc_update_bits(codec, WM8904_CLASS_W_0,
+                            WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
 
         /* Use normal bias source */
-        wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL;
+        snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
+                            WM8904_POBCTRL, 0);
 
         wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         /* Bias level configuration will have done an extra enable */
         regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
 
-        wm8904_codec = codec;
+        wm8904_handle_pdata(codec);
 
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err_enable;
-        }
-
-        ret = snd_soc_register_dai(&wm8904_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+        wm8904_add_widgets(codec);
 
         return 0;
 
-err_codec:
-        snd_soc_unregister_codec(codec);
 err_enable:
         regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
 err_get:
         regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
-err:
-        kfree(wm8904);
         return ret;
 }
 
-static void wm8904_unregister(struct wm8904_priv *wm8904)
+static int wm8904_remove(struct snd_soc_codec *codec)
 {
-        wm8904_set_bias_level(&wm8904->codec, SND_SOC_BIAS_OFF);
+        struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
+
+        wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
         regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
-        snd_soc_unregister_dai(&wm8904_dai);
-        snd_soc_unregister_codec(&wm8904->codec);
-        kfree(wm8904);
-        wm8904_codec = NULL;
+        kfree(wm8904->retune_mobile_texts);
+        kfree(wm8904->drc_texts);
+
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
+        .probe =        wm8904_probe,
+        .remove =       wm8904_remove,
+        .suspend =      wm8904_suspend,
+        .resume =       wm8904_resume,
+        .set_bias_level = wm8904_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8904_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8904_reg,
+        .volatile_register = wm8904_volatile_register,
+};
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int wm8904_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm8904_priv *wm8904;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL);
         if (wm8904 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8904->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
         wm8904->devtype = id->driver_data;
-
         i2c_set_clientdata(i2c, wm8904);
-        codec->control_data = i2c;
+        wm8904->control_data = i2c;
         wm8904->pdata = i2c->dev.platform_data;
 
-        codec->dev = &i2c->dev;
-
-        return wm8904_register(wm8904, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8904, &wm8904_dai, 1);
+        if (ret < 0)
+                kfree(wm8904);
+        return ret;
 }
 
 static __devexit int wm8904_i2c_remove(struct i2c_client *client)
 {
-        struct wm8904_priv *wm8904 = i2c_get_clientdata(client);
-        wm8904_unregister(wm8904);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -2641,7 +2566,7 @@ MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
 
 static struct i2c_driver wm8904_i2c_driver = {
         .driver = {
-                .name = "WM8904",
+                .name = "wm8904-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8904_i2c_probe,
@@ -2652,15 +2577,15 @@ static struct i2c_driver wm8904_i2c_driver = {
 
 static int __init wm8904_modinit(void)
 {
-        int ret;
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8904_i2c_driver);
         if (ret != 0) {
-                printk(KERN_ERR "Failed to register WM8904 I2C driver: %d\n",
+                printk(KERN_ERR "Failed to register wm8904 I2C driver: %d\n",
                        ret);
         }
 #endif
-        return 0;
+        return ret;
 }
 module_init(wm8904_modinit);
 
diff --git a/sound/soc/codecs/wm8904.h b/sound/soc/codecs/wm8904.h
index abe5059b3004..9e8c84188ba7 100644
--- a/sound/soc/codecs/wm8904.h
+++ b/sound/soc/codecs/wm8904.h
@@ -21,9 +21,6 @@
 #define WM8904_FLL_LRCLK         3
 #define WM8904_FLL_FREE_RUNNING  4
 
-extern struct snd_soc_dai wm8904_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8904;
-
 /*
  * Register values.
  */
diff --git a/sound/soc/codecs/wm8915.c b/sound/soc/codecs/wm8915.c
new file mode 100644
index 000000000000..e2ab4fac2819
--- /dev/null
+++ b/sound/soc/codecs/wm8915.c
@@ -0,0 +1,2931 @@
+/*
+ * wm8915.c - WM8915 audio codec interface
+ *
+ * Copyright 2011 Wolfson Microelectronics PLC.
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/gcd.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <sound/core.h>
+#include <sound/jack.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <trace/events/asoc.h>
+
+#include <sound/wm8915.h>
+#include "wm8915.h"
+
+#define WM8915_AIFS 2
+
+#define HPOUT1L 1
+#define HPOUT1R 2
+#define HPOUT2L 4
+#define HPOUT2R 8
+
+#define WM8915_NUM_SUPPLIES 6
+static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = {
+        "DCVDD",
+        "DBVDD",
+        "AVDD1",
+        "AVDD2",
+        "CPVDD",
+        "MICVDD",
+};
+
+struct wm8915_priv {
+        struct snd_soc_codec *codec;
+
+        int ldo1ena;
+
+        int sysclk;
+
+        int fll_src;
+        int fll_fref;
+        int fll_fout;
+
+        struct completion fll_lock;
+
+        u16 dcs_pending;
+        struct completion dcs_done;
+
+        u16 hpout_ena;
+        u16 hpout_pending;
+
+        struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES];
+        struct notifier_block disable_nb[WM8915_NUM_SUPPLIES];
+
+        struct wm8915_pdata pdata;
+
+        int rx_rate[WM8915_AIFS];
+
+        /* Platform dependant ReTune mobile configuration */
+        int num_retune_mobile_texts;
+        const char **retune_mobile_texts;
+        int retune_mobile_cfg[2];
+        struct soc_enum retune_mobile_enum;
+
+        struct snd_soc_jack *jack;
+        bool detecting;
+        bool jack_mic;
+        wm8915_polarity_fn polarity_cb;
+
+#ifdef CONFIG_GPIOLIB
+        struct gpio_chip gpio_chip;
+#endif
+};
+
+/* We can't use the same notifier block for more than one supply and
+ * there's no way I can see to get from a callback to the caller
+ * except container_of().
+ */
+#define WM8915_REGULATOR_EVENT(n) \
+static int wm8915_regulator_event_##n(struct notifier_block *nb, \
+                                    unsigned long event, void *data)    \
+{ \
+        struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \
+                                                  disable_nb[n]); \
+        if (event & REGULATOR_EVENT_DISABLE) { \
+                wm8915->codec->cache_sync = 1; \
+        } \
+        return 0; \
+}
+
+WM8915_REGULATOR_EVENT(0)
+WM8915_REGULATOR_EVENT(1)
+WM8915_REGULATOR_EVENT(2)
+WM8915_REGULATOR_EVENT(3)
+WM8915_REGULATOR_EVENT(4)
+WM8915_REGULATOR_EVENT(5)
+
+static const u16 wm8915_reg[WM8915_MAX_REGISTER] = {
+        [WM8915_SOFTWARE_RESET] = 0x8915,
+        [WM8915_POWER_MANAGEMENT_7] = 0x10,
+        [WM8915_DAC1_HPOUT1_VOLUME] = 0x88,
+        [WM8915_DAC2_HPOUT2_VOLUME] = 0x88,
+        [WM8915_DAC1_LEFT_VOLUME] = 0x2c0,
+        [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0,
+        [WM8915_DAC2_LEFT_VOLUME] = 0x2c0,
+        [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0,
+        [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80,
+        [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80,
+        [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80,
+        [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80,
+        [WM8915_MICBIAS_1] = 0x39,
+        [WM8915_MICBIAS_2] = 0x39,
+        [WM8915_LDO_1] = 0x3,
+        [WM8915_LDO_2] = 0x13,
+        [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4,
+        [WM8915_HEADPHONE_DETECT_1] = 0x20,
+        [WM8915_MIC_DETECT_1] = 0x7600,
+        [WM8915_MIC_DETECT_2] = 0xbf,
+        [WM8915_CHARGE_PUMP_1] = 0x1f25,
+        [WM8915_CHARGE_PUMP_2] = 0xab19,
+        [WM8915_DC_SERVO_5] = 0x2a2a,
+        [WM8915_CONTROL_INTERFACE_1] = 0x8004,
+        [WM8915_CLOCKING_1] = 0x10,
+        [WM8915_AIF_RATE] = 0x83,
+        [WM8915_FLL_CONTROL_4] = 0x5dc0,
+        [WM8915_FLL_CONTROL_5] = 0xc84,
+        [WM8915_FLL_EFS_2] = 0x2,
+        [WM8915_AIF1_TX_LRCLK_1] = 0x80,
+        [WM8915_AIF1_TX_LRCLK_2] = 0x8,
+        [WM8915_AIF1_RX_LRCLK_1] = 0x80,
+        [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
+        [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818,
+        [WM8915_AIF1TX_TEST] = 0x7,
+        [WM8915_AIF2_TX_LRCLK_1] = 0x80,
+        [WM8915_AIF2_TX_LRCLK_2] = 0x8,
+        [WM8915_AIF2_RX_LRCLK_1] = 0x80,
+        [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
+        [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818,
+        [WM8915_AIF2TX_TEST] = 0x1,
+        [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0,
+        [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0,
+        [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0,
+        [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0,
+        [WM8915_DSP1_TX_FILTERS] = 0x2000,
+        [WM8915_DSP1_RX_FILTERS_1] = 0x200,
+        [WM8915_DSP1_RX_FILTERS_2] = 0x10,
+        [WM8915_DSP1_DRC_1] = 0x98,
+        [WM8915_DSP1_DRC_2] = 0x845,
+        [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318,
+        [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300,
+        [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca,
+        [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400,
+        [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
+        [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
+        [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145,
+        [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75,
+        [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
+        [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
+        [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373,
+        [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54,
+        [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558,
+        [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e,
+        [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829,
+        [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
+        [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
+        [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564,
+        [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559,
+        [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
+        [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0,
+        [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0,
+        [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0,
+        [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0,
+        [WM8915_DSP2_TX_FILTERS] = 0x2000,
+        [WM8915_DSP2_RX_FILTERS_1] = 0x200,
+        [WM8915_DSP2_RX_FILTERS_2] = 0x10,
+        [WM8915_DSP2_DRC_1] = 0x98,
+        [WM8915_DSP2_DRC_2] = 0x845,
+        [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318,
+        [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300,
+        [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca,
+        [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400,
+        [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
+        [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
+        [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145,
+        [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75,
+        [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
+        [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
+        [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373,
+        [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54,
+        [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558,
+        [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e,
+        [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829,
+        [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
+        [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
+        [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564,
+        [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559,
+        [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
+        [WM8915_OVERSAMPLING] = 0xd,
+        [WM8915_SIDETONE] = 0x1040,
+        [WM8915_GPIO_1] = 0xa101,
+        [WM8915_GPIO_2] = 0xa101,
+        [WM8915_GPIO_3] = 0xa101,
+        [WM8915_GPIO_4] = 0xa101,
+        [WM8915_GPIO_5] = 0xa101,
+        [WM8915_PULL_CONTROL_2] = 0x140,
+        [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f,
+        [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
+        [WM8915_RIGHT_PDM_SPEAKER] = 0x1,
+        [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
+        [WM8915_PDM_SPEAKER_VOLUME] = 0x66,
+        [WM8915_WRITE_SEQUENCER_0] = 0x1,
+        [WM8915_WRITE_SEQUENCER_1] = 0x1,
+        [WM8915_WRITE_SEQUENCER_3] = 0x6,
+        [WM8915_WRITE_SEQUENCER_4] = 0x40,
+        [WM8915_WRITE_SEQUENCER_5] = 0x1,
+        [WM8915_WRITE_SEQUENCER_6] = 0xf,
+        [WM8915_WRITE_SEQUENCER_7] = 0x6,
+        [WM8915_WRITE_SEQUENCER_8] = 0x1,
+        [WM8915_WRITE_SEQUENCER_9] = 0x3,
+        [WM8915_WRITE_SEQUENCER_10] = 0x104,
+        [WM8915_WRITE_SEQUENCER_12] = 0x60,
+        [WM8915_WRITE_SEQUENCER_13] = 0x11,
+        [WM8915_WRITE_SEQUENCER_14] = 0x401,
+        [WM8915_WRITE_SEQUENCER_16] = 0x50,
+        [WM8915_WRITE_SEQUENCER_17] = 0x3,
+        [WM8915_WRITE_SEQUENCER_18] = 0x100,
+        [WM8915_WRITE_SEQUENCER_20] = 0x51,
+        [WM8915_WRITE_SEQUENCER_21] = 0x3,
+        [WM8915_WRITE_SEQUENCER_22] = 0x104,
+        [WM8915_WRITE_SEQUENCER_23] = 0xa,
+        [WM8915_WRITE_SEQUENCER_24] = 0x60,
+        [WM8915_WRITE_SEQUENCER_25] = 0x3b,
+        [WM8915_WRITE_SEQUENCER_26] = 0x502,
+        [WM8915_WRITE_SEQUENCER_27] = 0x100,
+        [WM8915_WRITE_SEQUENCER_28] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_32] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_36] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_40] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_44] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_48] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_52] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_56] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_60] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_64] = 0x1,
+        [WM8915_WRITE_SEQUENCER_65] = 0x1,
+        [WM8915_WRITE_SEQUENCER_67] = 0x6,
+        [WM8915_WRITE_SEQUENCER_68] = 0x40,
+        [WM8915_WRITE_SEQUENCER_69] = 0x1,
+        [WM8915_WRITE_SEQUENCER_70] = 0xf,
+        [WM8915_WRITE_SEQUENCER_71] = 0x6,
+        [WM8915_WRITE_SEQUENCER_72] = 0x1,
+        [WM8915_WRITE_SEQUENCER_73] = 0x3,
+        [WM8915_WRITE_SEQUENCER_74] = 0x104,
+        [WM8915_WRITE_SEQUENCER_76] = 0x60,
+        [WM8915_WRITE_SEQUENCER_77] = 0x11,
+        [WM8915_WRITE_SEQUENCER_78] = 0x401,
+        [WM8915_WRITE_SEQUENCER_80] = 0x50,
+        [WM8915_WRITE_SEQUENCER_81] = 0x3,
+        [WM8915_WRITE_SEQUENCER_82] = 0x100,
+        [WM8915_WRITE_SEQUENCER_84] = 0x60,
+        [WM8915_WRITE_SEQUENCER_85] = 0x3b,
+        [WM8915_WRITE_SEQUENCER_86] = 0x502,
+        [WM8915_WRITE_SEQUENCER_87] = 0x100,
+        [WM8915_WRITE_SEQUENCER_88] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_92] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_96] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_100] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_104] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_108] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_112] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_116] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_120] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_124] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_128] = 0x1,
+        [WM8915_WRITE_SEQUENCER_129] = 0x1,
+        [WM8915_WRITE_SEQUENCER_131] = 0x6,
+        [WM8915_WRITE_SEQUENCER_132] = 0x40,
+        [WM8915_WRITE_SEQUENCER_133] = 0x1,
+        [WM8915_WRITE_SEQUENCER_134] = 0xf,
+        [WM8915_WRITE_SEQUENCER_135] = 0x6,
+        [WM8915_WRITE_SEQUENCER_136] = 0x1,
+        [WM8915_WRITE_SEQUENCER_137] = 0x3,
+        [WM8915_WRITE_SEQUENCER_138] = 0x106,
+        [WM8915_WRITE_SEQUENCER_140] = 0x61,
+        [WM8915_WRITE_SEQUENCER_141] = 0x11,
+        [WM8915_WRITE_SEQUENCER_142] = 0x401,
+        [WM8915_WRITE_SEQUENCER_144] = 0x50,
+        [WM8915_WRITE_SEQUENCER_145] = 0x3,
+        [WM8915_WRITE_SEQUENCER_146] = 0x102,
+        [WM8915_WRITE_SEQUENCER_148] = 0x51,
+        [WM8915_WRITE_SEQUENCER_149] = 0x3,
+        [WM8915_WRITE_SEQUENCER_150] = 0x106,
+        [WM8915_WRITE_SEQUENCER_151] = 0xa,
+        [WM8915_WRITE_SEQUENCER_152] = 0x61,
+        [WM8915_WRITE_SEQUENCER_153] = 0x3b,
+        [WM8915_WRITE_SEQUENCER_154] = 0x502,
+        [WM8915_WRITE_SEQUENCER_155] = 0x100,
+        [WM8915_WRITE_SEQUENCER_156] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_160] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_164] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_168] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_172] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_176] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_180] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_184] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_188] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_192] = 0x1,
+        [WM8915_WRITE_SEQUENCER_193] = 0x1,
+        [WM8915_WRITE_SEQUENCER_195] = 0x6,
+        [WM8915_WRITE_SEQUENCER_196] = 0x40,
+        [WM8915_WRITE_SEQUENCER_197] = 0x1,
+        [WM8915_WRITE_SEQUENCER_198] = 0xf,
+        [WM8915_WRITE_SEQUENCER_199] = 0x6,
+        [WM8915_WRITE_SEQUENCER_200] = 0x1,
+        [WM8915_WRITE_SEQUENCER_201] = 0x3,
+        [WM8915_WRITE_SEQUENCER_202] = 0x106,
+        [WM8915_WRITE_SEQUENCER_204] = 0x61,
+        [WM8915_WRITE_SEQUENCER_205] = 0x11,
+        [WM8915_WRITE_SEQUENCER_206] = 0x401,
+        [WM8915_WRITE_SEQUENCER_208] = 0x50,
+        [WM8915_WRITE_SEQUENCER_209] = 0x3,
+        [WM8915_WRITE_SEQUENCER_210] = 0x102,
+        [WM8915_WRITE_SEQUENCER_212] = 0x61,
+        [WM8915_WRITE_SEQUENCER_213] = 0x3b,
+        [WM8915_WRITE_SEQUENCER_214] = 0x502,
+        [WM8915_WRITE_SEQUENCER_215] = 0x100,
+        [WM8915_WRITE_SEQUENCER_216] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_220] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_224] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_228] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_232] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_236] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_240] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_244] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_248] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_252] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_256] = 0x60,
+        [WM8915_WRITE_SEQUENCER_258] = 0x601,
+        [WM8915_WRITE_SEQUENCER_260] = 0x50,
+        [WM8915_WRITE_SEQUENCER_262] = 0x100,
+        [WM8915_WRITE_SEQUENCER_264] = 0x1,
+        [WM8915_WRITE_SEQUENCER_266] = 0x104,
+        [WM8915_WRITE_SEQUENCER_267] = 0x100,
+        [WM8915_WRITE_SEQUENCER_268] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_272] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_276] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_280] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_284] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_288] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_292] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_296] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_300] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_304] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_308] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_312] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_316] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_320] = 0x61,
+        [WM8915_WRITE_SEQUENCER_322] = 0x601,
+        [WM8915_WRITE_SEQUENCER_324] = 0x50,
+        [WM8915_WRITE_SEQUENCER_326] = 0x102,
+        [WM8915_WRITE_SEQUENCER_328] = 0x1,
+        [WM8915_WRITE_SEQUENCER_330] = 0x106,
+        [WM8915_WRITE_SEQUENCER_331] = 0x100,
+        [WM8915_WRITE_SEQUENCER_332] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_336] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_340] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_344] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_348] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_352] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_356] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_360] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_364] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_368] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_372] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_376] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_380] = 0x2fff,
+        [WM8915_WRITE_SEQUENCER_384] = 0x60,
+        [WM8915_WRITE_SEQUENCER_386] = 0x601,
+        [WM8915_WRITE_SEQUENCER_388] = 0x61,
+        [WM8915_WRITE_SEQUENCER_390] = 0x601,
+        [WM8915_WRITE_SEQUENCER_392] = 0x50,
+        [WM8915_WRITE_SEQUENCER_394] = 0x300,
+        [WM8915_WRITE_SEQUENCER_396] = 0x1,
+        [WM8915_WRITE_SEQUENCER_398] = 0x304,
+        [WM8915_WRITE_SEQUENCER_400] = 0x40,
+        [WM8915_WRITE_SEQUENCER_402] = 0xf,
+        [WM8915_WRITE_SEQUENCER_404] = 0x1,
+        [WM8915_WRITE_SEQUENCER_407] = 0x100,
+};
+
+static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
+static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
+static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
+static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
+static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
+static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
+static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
+
+static const char *sidetone_hpf_text[] = {
+        "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
+};
+
+static const struct soc_enum sidetone_hpf =
+        SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text);
+
+static const char *hpf_mode_text[] = {
+        "HiFi", "Custom", "Voice"
+};
+
+static const struct soc_enum dsp1tx_hpf_mode =
+        SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
+
+static const struct soc_enum dsp2tx_hpf_mode =
+        SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
+
+static const char *hpf_cutoff_text[] = {
+        "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
+};
+
+static const struct soc_enum dsp1tx_hpf_cutoff =
+        SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
+
+static const struct soc_enum dsp2tx_hpf_cutoff =
+        SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
+
+static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        struct wm8915_pdata *pdata = &wm8915->pdata;
+        int base, best, best_val, save, i, cfg, iface;
+
+        if (!wm8915->num_retune_mobile_texts)
+                return;
+
+        switch (block) {
+        case 0:
+                base = WM8915_DSP1_RX_EQ_GAINS_1;
+                if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
+                    WM8915_DSP1RX_SRC)
+                        iface = 1;
+                else
+                        iface = 0;
+                break;
+        case 1:
+                base = WM8915_DSP1_RX_EQ_GAINS_2;
+                if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
+                    WM8915_DSP2RX_SRC)
+                        iface = 1;
+                else
+                        iface = 0;
+                break;
+        default:
+                return;
+        }
+
+        /* Find the version of the currently selected configuration
+         * with the nearest sample rate. */
+        cfg = wm8915->retune_mobile_cfg[block];
+        best = 0;
+        best_val = INT_MAX;
+        for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
+                if (strcmp(pdata->retune_mobile_cfgs[i].name,
+                           wm8915->retune_mobile_texts[cfg]) == 0 &&
+                    abs(pdata->retune_mobile_cfgs[i].rate
+                        - wm8915->rx_rate[iface]) < best_val) {
+                        best = i;
+                        best_val = abs(pdata->retune_mobile_cfgs[i].rate
+                                       - wm8915->rx_rate[iface]);
+                }
+        }
+
+        dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
+                block,
+                pdata->retune_mobile_cfgs[best].name,
+                pdata->retune_mobile_cfgs[best].rate,
+                wm8915->rx_rate[iface]);
+
+        /* The EQ will be disabled while reconfiguring it, remember the
+         * current configuration. 
+         */
+        save = snd_soc_read(codec, base);
+        save &= WM8915_DSP1RX_EQ_ENA;
+
+        for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
+                snd_soc_update_bits(codec, base + i, 0xffff,
+                                    pdata->retune_mobile_cfgs[best].regs[i]);
+
+        snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save);
+}
+
+/* Icky as hell but saves code duplication */
+static int wm8915_get_retune_mobile_block(const char *name)
+{
+        if (strcmp(name, "DSP1 EQ Mode") == 0)
+                return 0;
+        if (strcmp(name, "DSP2 EQ Mode") == 0)
+                return 1;
+        return -EINVAL;
+}
+
+static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
+                                         struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        struct wm8915_pdata *pdata = &wm8915->pdata;
+        int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
+        int value = ucontrol->value.integer.value[0];
+
+        if (block < 0)
+                return block;
+
+        if (value >= pdata->num_retune_mobile_cfgs)
+                return -EINVAL;
+
+        wm8915->retune_mobile_cfg[block] = value;
+
+        wm8915_set_retune_mobile(codec, block);
+
+        return 0;
+}
+
+static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
+                                         struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
+
+        ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block];
+
+        return 0;
+}
+
+static const struct snd_kcontrol_new wm8915_snd_controls[] = {
+SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME,
+                 WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
+SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME,
+             WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
+
+SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES,
+               0, 5, 24, 0, sidetone_tlv),
+SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES,
+               0, 5, 24, 0, sidetone_tlv),
+SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0),
+SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
+SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0),
+
+SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME,
+                 WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
+SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME,
+                 WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
+
+SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS,
+           13, 1, 0),
+SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0),
+SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
+SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
+
+SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS,
+           13, 1, 0),
+SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0),
+SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
+SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
+
+SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME,
+                 WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
+SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1),
+
+SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME,
+                 WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
+SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1),
+
+SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME,
+                 WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
+SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME,
+             WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1),
+
+SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME,
+                 WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
+SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME,
+             WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1),
+
+SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0),
+SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0),
+SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0),
+SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0),
+
+SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0),
+SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0),
+
+SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4,
+               8, 0, out_digital_tlv),
+SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4,
+               8, 0, out_digital_tlv),
+
+SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME,
+                 WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
+SOC_DOUBLE_R("Output 1 ZC Switch",  WM8915_OUTPUT1_LEFT_VOLUME,
+             WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
+
+SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME,
+                 WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
+SOC_DOUBLE_R("Output 2 ZC Switch",  WM8915_OUTPUT2_LEFT_VOLUME,
+             WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
+
+SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
+               spk_tlv),
+SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER,
+             WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1),
+SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER,
+             WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0),
+
+SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
+SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8915_eq_controls[] = {
+SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
+               eq_tlv),
+SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
+               eq_tlv),
+SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
+               eq_tlv),
+SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
+               eq_tlv),
+SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
+               eq_tlv),
+
+SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
+               eq_tlv),
+SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
+               eq_tlv),
+SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
+               eq_tlv),
+SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
+               eq_tlv),
+SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
+               eq_tlv),
+};
+
+static int cp_event(struct snd_soc_dapm_widget *w,
+                    struct snd_kcontrol *kcontrol, int event)
+{
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                msleep(5);
+                break;
+        default:
+                BUG();
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int rmv_short_event(struct snd_soc_dapm_widget *w,
+                           struct snd_kcontrol *kcontrol, int event)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
+
+        /* Record which outputs we enabled */
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMD:
+                wm8915->hpout_pending &= ~w->shift;
+                break;
+        case SND_SOC_DAPM_PRE_PMU:
+                wm8915->hpout_pending |= w->shift;
+                break;
+        default:
+                BUG();
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
+{
+        struct i2c_client *i2c = to_i2c_client(codec->dev);
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int i, ret;
+        unsigned long timeout = 200;
+
+        snd_soc_write(codec, WM8915_DC_SERVO_2, mask);
+
+        /* Use the interrupt if possible */
+        do {
+                if (i2c->irq) {
+                        timeout = wait_for_completion_timeout(&wm8915->dcs_done,
+                                                              msecs_to_jiffies(200));
+                        if (timeout == 0)
+                                dev_err(codec->dev, "DC servo timed out\n");
+
+                } else {
+                        msleep(1);
+                        if (--i) {
+                                timeout = 0;
+                                break;
+                        }
+                }
+
+                ret = snd_soc_read(codec, WM8915_DC_SERVO_2);
+                dev_dbg(codec->dev, "DC servo state: %x\n", ret);
+        } while (ret & mask);
+
+        if (timeout == 0)
+                dev_err(codec->dev, "DC servo timed out for %x\n", mask);
+        else
+                dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
+}
+
+static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm,
+                                enum snd_soc_dapm_type event, int subseq)
+{
+        struct snd_soc_codec *codec = container_of(dapm,
+                                                   struct snd_soc_codec, dapm);
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        u16 val, mask;
+
+        /* Complete any pending DC servo starts */
+        if (wm8915->dcs_pending) {
+                dev_dbg(codec->dev, "Starting DC servo for %x\n",
+                        wm8915->dcs_pending);
+
+                /* Trigger a startup sequence */
+                wait_for_dc_servo(codec, wm8915->dcs_pending
+                                         << WM8915_DCS_TRIG_STARTUP_0_SHIFT);
+
+                wm8915->dcs_pending = 0;
+        }
+
+        if (wm8915->hpout_pending != wm8915->hpout_ena) {
+                dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
+                        wm8915->hpout_ena, wm8915->hpout_pending);
+
+                val = 0;
+                mask = 0;
+                if (wm8915->hpout_pending & HPOUT1L) {
+                        val |= WM8915_HPOUT1L_RMV_SHORT;
+                        mask |= WM8915_HPOUT1L_RMV_SHORT;
+                } else {
+                        mask |= WM8915_HPOUT1L_RMV_SHORT |
+                                WM8915_HPOUT1L_OUTP |
+                                WM8915_HPOUT1L_DLY;
+                }
+
+                if (wm8915->hpout_pending & HPOUT1R) {
+                        val |= WM8915_HPOUT1R_RMV_SHORT;
+                        mask |= WM8915_HPOUT1R_RMV_SHORT;
+                } else {
+                        mask |= WM8915_HPOUT1R_RMV_SHORT |
+                                WM8915_HPOUT1R_OUTP |
+                                WM8915_HPOUT1R_DLY;
+                }
+
+                snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val);
+
+                val = 0;
+                mask = 0;
+                if (wm8915->hpout_pending & HPOUT2L) {
+                        val |= WM8915_HPOUT2L_RMV_SHORT;
+                        mask |= WM8915_HPOUT2L_RMV_SHORT;
+                } else {
+                        mask |= WM8915_HPOUT2L_RMV_SHORT |
+                                WM8915_HPOUT2L_OUTP |
+                                WM8915_HPOUT2L_DLY;
+                }
+
+                if (wm8915->hpout_pending & HPOUT2R) {
+                        val |= WM8915_HPOUT2R_RMV_SHORT;
+                        mask |= WM8915_HPOUT2R_RMV_SHORT;
+                } else {
+                        mask |= WM8915_HPOUT2R_RMV_SHORT |
+                                WM8915_HPOUT2R_OUTP |
+                                WM8915_HPOUT2R_DLY;
+                }
+
+                snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val);
+
+                wm8915->hpout_ena = wm8915->hpout_pending;
+        }
+}
+
+static int dcs_start(struct snd_soc_dapm_widget *w,
+                     struct snd_kcontrol *kcontrol, int event)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                wm8915->dcs_pending |= 1 << w->shift;
+                break;
+        default:
+                BUG();
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static const char *sidetone_text[] = {
+        "IN1", "IN2",
+};
+
+static const struct soc_enum left_sidetone_enum =
+        SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text);
+
+static const struct snd_kcontrol_new left_sidetone =
+        SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
+
+static const struct soc_enum right_sidetone_enum =
+        SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text);
+
+static const struct snd_kcontrol_new right_sidetone =
+        SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
+
+static const char *spk_text[] = {
+        "DAC1L", "DAC1R", "DAC2L", "DAC2R"
+};
+
+static const struct soc_enum spkl_enum =
+        SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text);
+
+static const struct snd_kcontrol_new spkl_mux =
+        SOC_DAPM_ENUM("SPKL", spkl_enum);
+
+static const struct soc_enum spkr_enum =
+        SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
+
+static const struct snd_kcontrol_new spkr_mux =
+        SOC_DAPM_ENUM("SPKR", spkr_enum);
+
+static const char *dsp1rx_text[] = {
+        "AIF1", "AIF2"
+};
+
+static const struct soc_enum dsp1rx_enum =
+        SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
+
+static const struct snd_kcontrol_new dsp1rx =
+        SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
+
+static const char *dsp2rx_text[] = {
+         "AIF2", "AIF1"
+};
+
+static const struct soc_enum dsp2rx_enum =
+        SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
+
+static const struct snd_kcontrol_new dsp2rx =
+        SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
+
+static const char *aif2tx_text[] = {
+        "DSP2", "DSP1", "AIF1"
+};
+
+static const struct soc_enum aif2tx_enum =
+        SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
+
+static const struct snd_kcontrol_new aif2tx =
+        SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
+
+static const char *inmux_text[] = {
+        "ADC", "DMIC1", "DMIC2"
+};
+
+static const struct soc_enum in1_enum =
+        SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text);
+
+static const struct snd_kcontrol_new in1_mux =
+        SOC_DAPM_ENUM("IN1 Mux", in1_enum);
+
+static const struct soc_enum in2_enum =
+        SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text);
+
+static const struct snd_kcontrol_new in2_mux =
+        SOC_DAPM_ENUM("IN2 Mux", in2_enum);
+
+static const struct snd_kcontrol_new dac2r_mix[] = {
+SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
+                5, 1, 0),
+SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
+                4, 1, 0),
+SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
+SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dac2l_mix[] = {
+SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
+                5, 1, 0),
+SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
+                4, 1, 0),
+SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
+SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dac1r_mix[] = {
+SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
+                5, 1, 0),
+SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
+                4, 1, 0),
+SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
+SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dac1l_mix[] = {
+SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
+                5, 1, 0),
+SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
+                4, 1, 0),
+SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
+SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dsp1txl[] = {
+SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
+                1, 1, 0),
+SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dsp1txr[] = {
+SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
+                1, 1, 0),
+SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dsp2txl[] = {
+SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
+                1, 1, 0),
+SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dsp2txr[] = {
+SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
+                1, 1, 0),
+SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+
+static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = {
+SND_SOC_DAPM_INPUT("IN1LN"),
+SND_SOC_DAPM_INPUT("IN1LP"),
+SND_SOC_DAPM_INPUT("IN1RN"),
+SND_SOC_DAPM_INPUT("IN1RP"),
+
+SND_SOC_DAPM_INPUT("IN2LN"),
+SND_SOC_DAPM_INPUT("IN2LP"),
+SND_SOC_DAPM_INPUT("IN2RN"),
+SND_SOC_DAPM_INPUT("IN2RP"),
+
+SND_SOC_DAPM_INPUT("DMIC1DAT"),
+SND_SOC_DAPM_INPUT("DMIC2DAT"),
+
+SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event,
+                      SND_SOC_DAPM_POST_PMU),
+
+SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
+SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0),
+SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0),
+
+SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
+SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
+
+SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
+SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
+SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
+SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
+
+SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0),
+SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0),
+SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0),
+SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0),
+
+SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
+
+SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0),
+SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0),
+SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0),
+SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0),
+
+SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0),
+SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0),
+
+SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
+SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
+
+SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0),
+SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0),
+SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0),
+SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0),
+
+SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0,
+                   dsp2txl, ARRAY_SIZE(dsp2txl)),
+SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0,
+                   dsp2txr, ARRAY_SIZE(dsp2txr)),
+SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0,
+                   dsp1txl, ARRAY_SIZE(dsp1txl)),
+SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0,
+                   dsp1txr, ARRAY_SIZE(dsp1txr)),
+
+SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
+                   dac2l_mix, ARRAY_SIZE(dac2l_mix)),
+SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
+                   dac2r_mix, ARRAY_SIZE(dac2r_mix)),
+SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
+                   dac1l_mix, ARRAY_SIZE(dac1l_mix)),
+SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
+                   dac1r_mix, ARRAY_SIZE(dac1r_mix)),
+
+SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0),
+SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0),
+SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0),
+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0),
+
+SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
+                    WM8915_POWER_MANAGEMENT_4, 9, 0),
+SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
+                    WM8915_POWER_MANAGEMENT_4, 8, 0),
+
+SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
+                    WM8915_POWER_MANAGEMENT_6, 9, 0),
+SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
+                    WM8915_POWER_MANAGEMENT_6, 8, 0),
+
+SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
+                    WM8915_POWER_MANAGEMENT_4, 5, 0),
+SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
+                    WM8915_POWER_MANAGEMENT_4, 4, 0),
+SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
+                    WM8915_POWER_MANAGEMENT_4, 3, 0),
+SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
+                    WM8915_POWER_MANAGEMENT_4, 2, 0),
+SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
+                    WM8915_POWER_MANAGEMENT_4, 1, 0),
+SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
+                    WM8915_POWER_MANAGEMENT_4, 0, 0),
+
+SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
+                     WM8915_POWER_MANAGEMENT_6, 5, 0),
+SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
+                     WM8915_POWER_MANAGEMENT_6, 4, 0),
+SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
+                     WM8915_POWER_MANAGEMENT_6, 3, 0),
+SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
+                     WM8915_POWER_MANAGEMENT_6, 2, 0),
+SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
+                     WM8915_POWER_MANAGEMENT_6, 1, 0),
+SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
+                     WM8915_POWER_MANAGEMENT_6, 0, 0),
+
+/* We route as stereo pairs so define some dummy widgets to squash
+ * things down for now.  RXA = 0,1, RXB = 2,3 and so on */
+SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
+SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
+SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
+
+SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
+SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
+SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
+SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
+
+SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start,
+                   SND_SOC_DAPM_POST_PMU),
+SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
+                   rmv_short_event,
+                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+
+SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start,
+                   SND_SOC_DAPM_POST_PMU),
+SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
+                   rmv_short_event,
+                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+
+SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start,
+                   SND_SOC_DAPM_POST_PMU),
+SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
+                   rmv_short_event,
+                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+
+SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start,
+                   SND_SOC_DAPM_POST_PMU),
+SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0),
+SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
+                   rmv_short_event,
+                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+
+SND_SOC_DAPM_OUTPUT("HPOUT1L"),
+SND_SOC_DAPM_OUTPUT("HPOUT1R"),
+SND_SOC_DAPM_OUTPUT("HPOUT2L"),
+SND_SOC_DAPM_OUTPUT("HPOUT2R"),
+SND_SOC_DAPM_OUTPUT("SPKDAT"),
+};
+
+static const struct snd_soc_dapm_route wm8915_dapm_routes[] = {
+        { "AIFCLK", NULL, "SYSCLK" },
+        { "SYSDSPCLK", NULL, "SYSCLK" },
+        { "Charge Pump", NULL, "SYSCLK" },
+
+        { "MICB1", NULL, "LDO2" },
+        { "MICB2", NULL, "LDO2" },
+
+        { "IN1L PGA", NULL, "IN2LN" },
+        { "IN1L PGA", NULL, "IN2LP" },
+        { "IN1L PGA", NULL, "IN1LN" },
+        { "IN1L PGA", NULL, "IN1LP" },
+
+        { "IN1R PGA", NULL, "IN2RN" },
+        { "IN1R PGA", NULL, "IN2RP" },
+        { "IN1R PGA", NULL, "IN1RN" },
+        { "IN1R PGA", NULL, "IN1RP" },
+
+        { "ADCL", NULL, "IN1L PGA" },
+
+        { "ADCR", NULL, "IN1R PGA" },
+
+        { "DMIC1L", NULL, "DMIC1DAT" },
+        { "DMIC1R", NULL, "DMIC1DAT" },
+        { "DMIC2L", NULL, "DMIC2DAT" },
+        { "DMIC2R", NULL, "DMIC2DAT" },
+
+        { "DMIC2L", NULL, "DMIC2" },
+        { "DMIC2R", NULL, "DMIC2" },
+        { "DMIC1L", NULL, "DMIC1" },
+        { "DMIC1R", NULL, "DMIC1" },
+
+        { "IN1L Mux", "ADC", "ADCL" },
+        { "IN1L Mux", "DMIC1", "DMIC1L" },
+        { "IN1L Mux", "DMIC2", "DMIC2L" },
+
+        { "IN1R Mux", "ADC", "ADCR" },
+        { "IN1R Mux", "DMIC1", "DMIC1R" },
+        { "IN1R Mux", "DMIC2", "DMIC2R" },
+
+        { "IN2L Mux", "ADC", "ADCL" },
+        { "IN2L Mux", "DMIC1", "DMIC1L" },
+        { "IN2L Mux", "DMIC2", "DMIC2L" },
+
+        { "IN2R Mux", "ADC", "ADCR" },
+        { "IN2R Mux", "DMIC1", "DMIC1R" },
+        { "IN2R Mux", "DMIC2", "DMIC2R" },
+
+        { "Left Sidetone", "IN1", "IN1L Mux" },
+        { "Left Sidetone", "IN2", "IN2L Mux" },
+
+        { "Right Sidetone", "IN1", "IN1R Mux" },
+        { "Right Sidetone", "IN2", "IN2R Mux" },
+
+        { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
+        { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
+
+        { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
+        { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
+
+        { "AIF1TX0", NULL, "DSP1TXL" },
+        { "AIF1TX1", NULL, "DSP1TXR" },
+        { "AIF1TX2", NULL, "DSP2TXL" },
+        { "AIF1TX3", NULL, "DSP2TXR" },
+        { "AIF1TX4", NULL, "AIF2RX0" },
+        { "AIF1TX5", NULL, "AIF2RX1" },
+
+        { "AIF1RX0", NULL, "AIFCLK" },
+        { "AIF1RX1", NULL, "AIFCLK" },
+        { "AIF1RX2", NULL, "AIFCLK" },
+        { "AIF1RX3", NULL, "AIFCLK" },
+        { "AIF1RX4", NULL, "AIFCLK" },
+        { "AIF1RX5", NULL, "AIFCLK" },
+
+        { "AIF2RX0", NULL, "AIFCLK" },
+        { "AIF2RX1", NULL, "AIFCLK" },
+
+        { "DSP1RXL", NULL, "SYSDSPCLK" },
+        { "DSP1RXR", NULL, "SYSDSPCLK" },
+        { "DSP2RXL", NULL, "SYSDSPCLK" },
+        { "DSP2RXR", NULL, "SYSDSPCLK" },
+        { "DSP1TXL", NULL, "SYSDSPCLK" },
+        { "DSP1TXR", NULL, "SYSDSPCLK" },
+        { "DSP2TXL", NULL, "SYSDSPCLK" },
+        { "DSP2TXR", NULL, "SYSDSPCLK" },
+
+        { "AIF1RXA", NULL, "AIF1RX0" },
+        { "AIF1RXA", NULL, "AIF1RX1" },
+        { "AIF1RXB", NULL, "AIF1RX2" },
+        { "AIF1RXB", NULL, "AIF1RX3" },
+        { "AIF1RXC", NULL, "AIF1RX4" },
+        { "AIF1RXC", NULL, "AIF1RX5" },
+
+        { "AIF2RX", NULL, "AIF2RX0" },
+        { "AIF2RX", NULL, "AIF2RX1" },
+
+        { "AIF2TX", "DSP2", "DSP2TX" },
+        { "AIF2TX", "DSP1", "DSP1RX" },
+        { "AIF2TX", "AIF1", "AIF1RXC" },
+
+        { "DSP1RXL", NULL, "DSP1RX" },
+        { "DSP1RXR", NULL, "DSP1RX" },
+        { "DSP2RXL", NULL, "DSP2RX" },
+        { "DSP2RXR", NULL, "DSP2RX" },
+
+        { "DSP2TX", NULL, "DSP2TXL" },
+        { "DSP2TX", NULL, "DSP2TXR" },
+
+        { "DSP1RX", "AIF1", "AIF1RXA" },
+        { "DSP1RX", "AIF2", "AIF2RX" },
+
+        { "DSP2RX", "AIF1", "AIF1RXB" },
+        { "DSP2RX", "AIF2", "AIF2RX" },
+
+        { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
+        { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
+        { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
+        { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
+
+        { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
+        { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
+        { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
+        { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
+
+        { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
+        { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
+        { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
+        { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
+
+        { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
+        { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
+        { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
+        { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
+
+        { "DAC1L", NULL, "DAC1L Mixer" },
+        { "DAC1R", NULL, "DAC1R Mixer" },
+        { "DAC2L", NULL, "DAC2L Mixer" },
+        { "DAC2R", NULL, "DAC2R Mixer" },
+
+        { "HPOUT2L PGA", NULL, "Charge Pump" },
+        { "HPOUT2L PGA", NULL, "DAC2L" },
+        { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
+        { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
+        { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
+        { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
+
+        { "HPOUT2R PGA", NULL, "Charge Pump" },
+        { "HPOUT2R PGA", NULL, "DAC2R" },
+        { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
+        { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
+        { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
+        { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
+
+        { "HPOUT1L PGA", NULL, "Charge Pump" },
+        { "HPOUT1L PGA", NULL, "DAC1L" },
+        { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
+        { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
+        { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
+        { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
+
+        { "HPOUT1R PGA", NULL, "Charge Pump" },
+        { "HPOUT1R PGA", NULL, "DAC1R" },
+        { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
+        { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
+        { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
+        { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
+
+        { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
+        { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
+        { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
+        { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
+
+        { "SPKL", "DAC1L", "DAC1L" },
+        { "SPKL", "DAC1R", "DAC1R" },
+        { "SPKL", "DAC2L", "DAC2L" },
+        { "SPKL", "DAC2R", "DAC2R" },
+
+        { "SPKR", "DAC1L", "DAC1L" },
+        { "SPKR", "DAC1R", "DAC1R" },
+        { "SPKR", "DAC2L", "DAC2L" },
+        { "SPKR", "DAC2R", "DAC2R" },
+
+        { "SPKL PGA", NULL, "SPKL" },
+        { "SPKR PGA", NULL, "SPKR" },
+
+        { "SPKDAT", NULL, "SPKL PGA" },
+        { "SPKDAT", NULL, "SPKR PGA" },
+};
+
+static int wm8915_readable_register(struct snd_soc_codec *codec,
+                                    unsigned int reg)
+{
+        /* Due to the sparseness of the register map the compiler
+         * output from an explicit switch statement ends up being much
+         * more efficient than a table.
+         */
+        switch (reg) {
+        case WM8915_SOFTWARE_RESET:
+        case WM8915_POWER_MANAGEMENT_1:
+        case WM8915_POWER_MANAGEMENT_2:
+        case WM8915_POWER_MANAGEMENT_3:
+        case WM8915_POWER_MANAGEMENT_4:
+        case WM8915_POWER_MANAGEMENT_5:
+        case WM8915_POWER_MANAGEMENT_6:
+        case WM8915_POWER_MANAGEMENT_7:
+        case WM8915_POWER_MANAGEMENT_8:
+        case WM8915_LEFT_LINE_INPUT_VOLUME:
+        case WM8915_RIGHT_LINE_INPUT_VOLUME:
+        case WM8915_LINE_INPUT_CONTROL:
+        case WM8915_DAC1_HPOUT1_VOLUME:
+        case WM8915_DAC2_HPOUT2_VOLUME:
+        case WM8915_DAC1_LEFT_VOLUME:
+        case WM8915_DAC1_RIGHT_VOLUME:
+        case WM8915_DAC2_LEFT_VOLUME:
+        case WM8915_DAC2_RIGHT_VOLUME:
+        case WM8915_OUTPUT1_LEFT_VOLUME:
+        case WM8915_OUTPUT1_RIGHT_VOLUME:
+        case WM8915_OUTPUT2_LEFT_VOLUME:
+        case WM8915_OUTPUT2_RIGHT_VOLUME:
+        case WM8915_MICBIAS_1:
+        case WM8915_MICBIAS_2:
+        case WM8915_LDO_1:
+        case WM8915_LDO_2:
+        case WM8915_ACCESSORY_DETECT_MODE_1:
+        case WM8915_ACCESSORY_DETECT_MODE_2:
+        case WM8915_HEADPHONE_DETECT_1:
+        case WM8915_HEADPHONE_DETECT_2:
+        case WM8915_MIC_DETECT_1:
+        case WM8915_MIC_DETECT_2:
+        case WM8915_MIC_DETECT_3:
+        case WM8915_CHARGE_PUMP_1:
+        case WM8915_CHARGE_PUMP_2:
+        case WM8915_DC_SERVO_1:
+        case WM8915_DC_SERVO_2:
+        case WM8915_DC_SERVO_3:
+        case WM8915_DC_SERVO_5:
+        case WM8915_DC_SERVO_6:
+        case WM8915_DC_SERVO_7:
+        case WM8915_DC_SERVO_READBACK_0:
+        case WM8915_ANALOGUE_HP_1:
+        case WM8915_ANALOGUE_HP_2:
+        case WM8915_CHIP_REVISION:
+        case WM8915_CONTROL_INTERFACE_1:
+        case WM8915_WRITE_SEQUENCER_CTRL_1:
+        case WM8915_WRITE_SEQUENCER_CTRL_2:
+        case WM8915_AIF_CLOCKING_1:
+        case WM8915_AIF_CLOCKING_2:
+        case WM8915_CLOCKING_1:
+        case WM8915_CLOCKING_2:
+        case WM8915_AIF_RATE:
+        case WM8915_FLL_CONTROL_1:
+        case WM8915_FLL_CONTROL_2:
+        case WM8915_FLL_CONTROL_3:
+        case WM8915_FLL_CONTROL_4:
+        case WM8915_FLL_CONTROL_5:
+        case WM8915_FLL_CONTROL_6:
+        case WM8915_FLL_EFS_1:
+        case WM8915_FLL_EFS_2:
+        case WM8915_AIF1_CONTROL:
+        case WM8915_AIF1_BCLK:
+        case WM8915_AIF1_TX_LRCLK_1:
+        case WM8915_AIF1_TX_LRCLK_2:
+        case WM8915_AIF1_RX_LRCLK_1:
+        case WM8915_AIF1_RX_LRCLK_2:
+        case WM8915_AIF1TX_DATA_CONFIGURATION_1:
+        case WM8915_AIF1TX_DATA_CONFIGURATION_2:
+        case WM8915_AIF1RX_DATA_CONFIGURATION:
+        case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION:
+        case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION:
+        case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION:
+        case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION:
+        case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION:
+        case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION:
+        case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION:
+        case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION:
+        case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION:
+        case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION:
+        case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION:
+        case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION:
+        case WM8915_AIF1RX_MONO_CONFIGURATION:
+        case WM8915_AIF1TX_TEST:
+        case WM8915_AIF2_CONTROL:
+        case WM8915_AIF2_BCLK:
+        case WM8915_AIF2_TX_LRCLK_1:
+        case WM8915_AIF2_TX_LRCLK_2:
+        case WM8915_AIF2_RX_LRCLK_1:
+        case WM8915_AIF2_RX_LRCLK_2:
+        case WM8915_AIF2TX_DATA_CONFIGURATION_1:
+        case WM8915_AIF2TX_DATA_CONFIGURATION_2:
+        case WM8915_AIF2RX_DATA_CONFIGURATION:
+        case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION:
+        case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION:
+        case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION:
+        case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION:
+        case WM8915_AIF2RX_MONO_CONFIGURATION:
+        case WM8915_AIF2TX_TEST:
+        case WM8915_DSP1_TX_LEFT_VOLUME:
+        case WM8915_DSP1_TX_RIGHT_VOLUME:
+        case WM8915_DSP1_RX_LEFT_VOLUME:
+        case WM8915_DSP1_RX_RIGHT_VOLUME:
+        case WM8915_DSP1_TX_FILTERS:
+        case WM8915_DSP1_RX_FILTERS_1:
+        case WM8915_DSP1_RX_FILTERS_2:
+        case WM8915_DSP1_DRC_1:
+        case WM8915_DSP1_DRC_2:
+        case WM8915_DSP1_DRC_3:
+        case WM8915_DSP1_DRC_4:
+        case WM8915_DSP1_DRC_5:
+        case WM8915_DSP1_RX_EQ_GAINS_1:
+        case WM8915_DSP1_RX_EQ_GAINS_2:
+        case WM8915_DSP1_RX_EQ_BAND_1_A:
+        case WM8915_DSP1_RX_EQ_BAND_1_B:
+        case WM8915_DSP1_RX_EQ_BAND_1_PG:
+        case WM8915_DSP1_RX_EQ_BAND_2_A:
+        case WM8915_DSP1_RX_EQ_BAND_2_B:
+        case WM8915_DSP1_RX_EQ_BAND_2_C:
+        case WM8915_DSP1_RX_EQ_BAND_2_PG:
+        case WM8915_DSP1_RX_EQ_BAND_3_A:
+        case WM8915_DSP1_RX_EQ_BAND_3_B:
+        case WM8915_DSP1_RX_EQ_BAND_3_C:
+        case WM8915_DSP1_RX_EQ_BAND_3_PG:
+        case WM8915_DSP1_RX_EQ_BAND_4_A:
+        case WM8915_DSP1_RX_EQ_BAND_4_B:
+        case WM8915_DSP1_RX_EQ_BAND_4_C:
+        case WM8915_DSP1_RX_EQ_BAND_4_PG:
+        case WM8915_DSP1_RX_EQ_BAND_5_A:
+        case WM8915_DSP1_RX_EQ_BAND_5_B:
+        case WM8915_DSP1_RX_EQ_BAND_5_PG:
+        case WM8915_DSP2_TX_LEFT_VOLUME:
+        case WM8915_DSP2_TX_RIGHT_VOLUME:
+        case WM8915_DSP2_RX_LEFT_VOLUME:
+        case WM8915_DSP2_RX_RIGHT_VOLUME:
+        case WM8915_DSP2_TX_FILTERS:
+        case WM8915_DSP2_RX_FILTERS_1:
+        case WM8915_DSP2_RX_FILTERS_2:
+        case WM8915_DSP2_DRC_1:
+        case WM8915_DSP2_DRC_2:
+        case WM8915_DSP2_DRC_3:
+        case WM8915_DSP2_DRC_4:
+        case WM8915_DSP2_DRC_5:
+        case WM8915_DSP2_RX_EQ_GAINS_1:
+        case WM8915_DSP2_RX_EQ_GAINS_2:
+        case WM8915_DSP2_RX_EQ_BAND_1_A:
+        case WM8915_DSP2_RX_EQ_BAND_1_B:
+        case WM8915_DSP2_RX_EQ_BAND_1_PG:
+        case WM8915_DSP2_RX_EQ_BAND_2_A:
+        case WM8915_DSP2_RX_EQ_BAND_2_B:
+        case WM8915_DSP2_RX_EQ_BAND_2_C:
+        case WM8915_DSP2_RX_EQ_BAND_2_PG:
+        case WM8915_DSP2_RX_EQ_BAND_3_A:
+        case WM8915_DSP2_RX_EQ_BAND_3_B:
+        case WM8915_DSP2_RX_EQ_BAND_3_C:
+        case WM8915_DSP2_RX_EQ_BAND_3_PG:
+        case WM8915_DSP2_RX_EQ_BAND_4_A:
+        case WM8915_DSP2_RX_EQ_BAND_4_B:
+        case WM8915_DSP2_RX_EQ_BAND_4_C:
+        case WM8915_DSP2_RX_EQ_BAND_4_PG:
+        case WM8915_DSP2_RX_EQ_BAND_5_A:
+        case WM8915_DSP2_RX_EQ_BAND_5_B:
+        case WM8915_DSP2_RX_EQ_BAND_5_PG:
+        case WM8915_DAC1_MIXER_VOLUMES:
+        case WM8915_DAC1_LEFT_MIXER_ROUTING:
+        case WM8915_DAC1_RIGHT_MIXER_ROUTING:
+        case WM8915_DAC2_MIXER_VOLUMES:
+        case WM8915_DAC2_LEFT_MIXER_ROUTING:
+        case WM8915_DAC2_RIGHT_MIXER_ROUTING:
+        case WM8915_DSP1_TX_LEFT_MIXER_ROUTING:
+        case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING:
+        case WM8915_DSP2_TX_LEFT_MIXER_ROUTING:
+        case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING:
+        case WM8915_DSP_TX_MIXER_SELECT:
+        case WM8915_DAC_SOFTMUTE:
+        case WM8915_OVERSAMPLING:
+        case WM8915_SIDETONE:
+        case WM8915_GPIO_1:
+        case WM8915_GPIO_2:
+        case WM8915_GPIO_3:
+        case WM8915_GPIO_4:
+        case WM8915_GPIO_5:
+        case WM8915_PULL_CONTROL_1:
+        case WM8915_PULL_CONTROL_2:
+        case WM8915_INTERRUPT_STATUS_1:
+        case WM8915_INTERRUPT_STATUS_2:
+        case WM8915_INTERRUPT_RAW_STATUS_2:
+        case WM8915_INTERRUPT_STATUS_1_MASK:
+        case WM8915_INTERRUPT_STATUS_2_MASK:
+        case WM8915_INTERRUPT_CONTROL:
+        case WM8915_LEFT_PDM_SPEAKER:
+        case WM8915_RIGHT_PDM_SPEAKER:
+        case WM8915_PDM_SPEAKER_MUTE_SEQUENCE:
+        case WM8915_PDM_SPEAKER_VOLUME:
+                return 1;
+        default:
+                return 0;
+        }
+}
+
+static int wm8915_volatile_register(struct snd_soc_codec *codec,
+                                    unsigned int reg)
+{
+        switch (reg) {
+        case WM8915_SOFTWARE_RESET:
+        case WM8915_CHIP_REVISION:
+        case WM8915_LDO_1:
+        case WM8915_LDO_2:
+        case WM8915_INTERRUPT_STATUS_1:
+        case WM8915_INTERRUPT_STATUS_2:
+        case WM8915_INTERRUPT_RAW_STATUS_2:
+        case WM8915_DC_SERVO_READBACK_0:
+        case WM8915_DC_SERVO_2:
+        case WM8915_DC_SERVO_6:
+        case WM8915_DC_SERVO_7:
+        case WM8915_FLL_CONTROL_6:
+        case WM8915_MIC_DETECT_3:
+        case WM8915_HEADPHONE_DETECT_1:
+        case WM8915_HEADPHONE_DETECT_2:
+                return 1;
+        default:
+                return 0;
+        }
+}
+
+static int wm8915_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915);
+}
+
+static int wm8915_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+
+        case SND_SOC_BIAS_PREPARE:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
+                        snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
+                                            WM8915_BG_ENA, WM8915_BG_ENA);
+                        msleep(2);
+                }
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
+                                                    wm8915->supplies);
+                        if (ret != 0) {
+                                dev_err(codec->dev,
+                                        "Failed to enable supplies: %d\n",
+                                        ret);
+                                return ret;
+                        }
+
+                        if (wm8915->pdata.ldo_ena >= 0) {
+                                gpio_set_value_cansleep(wm8915->pdata.ldo_ena,
+                                                        1);
+                                msleep(5);
+                        }
+
+                        codec->cache_only = false;
+                        snd_soc_cache_sync(codec);
+                }
+
+                snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
+                                    WM8915_BG_ENA, 0);
+                break;
+
+        case SND_SOC_BIAS_OFF:
+                codec->cache_only = true;
+                if (wm8915->pdata.ldo_ena >= 0)
+                        gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
+                regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies),
+                                       wm8915->supplies);
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+
+        return 0;
+}
+
+static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        int aifctrl = 0;
+        int bclk = 0;
+        int lrclk_tx = 0;
+        int lrclk_rx = 0;
+        int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
+
+        switch (dai->id) {
+        case 0:
+                aifctrl_reg = WM8915_AIF1_CONTROL;
+                bclk_reg = WM8915_AIF1_BCLK;
+                lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2;
+                lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2;
+                break;
+        case 1:
+                aifctrl_reg = WM8915_AIF2_CONTROL;
+                bclk_reg = WM8915_AIF2_BCLK;
+                lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2;
+                lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2;
+                break;
+        default:
+                BUG();
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                bclk |= WM8915_AIF1_BCLK_INV;
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
+                lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
+                break;
+        case SND_SOC_DAIFMT_IB_IF:
+                bclk |= WM8915_AIF1_BCLK_INV;
+                lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
+                lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
+                break;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBS_CFS:
+                break;
+        case SND_SOC_DAIFMT_CBS_CFM:
+                lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
+                lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
+                break;
+        case SND_SOC_DAIFMT_CBM_CFS:
+                bclk |= WM8915_AIF1_BCLK_MSTR;
+                break;
+        case SND_SOC_DAIFMT_CBM_CFM:
+                bclk |= WM8915_AIF1_BCLK_MSTR;
+                lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
+                lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_DSP_A:
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                aifctrl |= 1;
+                break;
+        case SND_SOC_DAIFMT_I2S:
+                aifctrl |= 2;
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                aifctrl |= 3;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl);
+        snd_soc_update_bits(codec, bclk_reg,
+                            WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR,
+                            bclk);
+        snd_soc_update_bits(codec, lrclk_tx_reg,
+                            WM8915_AIF1TX_LRCLK_INV |
+                            WM8915_AIF1TX_LRCLK_MSTR,
+                            lrclk_tx);
+        snd_soc_update_bits(codec, lrclk_rx_reg,
+                            WM8915_AIF1RX_LRCLK_INV |
+                            WM8915_AIF1RX_LRCLK_MSTR,
+                            lrclk_rx);
+
+        return 0;
+}
+
+static const int bclk_divs[] = {
+        1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
+};
+
+static const int dsp_divs[] = {
+        48000, 32000, 16000, 8000
+};
+
+static int wm8915_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int bits, i, bclk_rate, best, cur_val;
+        int aifdata = 0;
+        int bclk = 0;
+        int lrclk = 0;
+        int dsp = 0;
+        int aifdata_reg, bclk_reg, lrclk_reg, dsp_shift;
+
+        if (!wm8915->sysclk) {
+                dev_err(codec->dev, "SYSCLK not configured\n");
+                return -EINVAL;
+        }
+
+        switch (dai->id) {
+        case 0:
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
+                    (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) {
+                        aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION;
+                        lrclk_reg = WM8915_AIF1_RX_LRCLK_1;
+                } else {
+                        aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1;
+                        lrclk_reg = WM8915_AIF1_TX_LRCLK_1;
+                }
+                bclk_reg = WM8915_AIF1_BCLK;
+                dsp_shift = 0;
+                break;
+        case 1:
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
+                    (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) {
+                        aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION;
+                        lrclk_reg = WM8915_AIF2_RX_LRCLK_1;
+                } else {
+                        aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1;
+                        lrclk_reg = WM8915_AIF2_TX_LRCLK_1;
+                }
+                bclk_reg = WM8915_AIF2_BCLK;
+                dsp_shift = WM8915_DSP2_DIV_SHIFT;
+                break;
+        default:
+                BUG();
+                return -EINVAL;
+        }
+
+        bclk_rate = snd_soc_params_to_bclk(params);
+        if (bclk_rate < 0) {
+                dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
+                return bclk_rate;
+        }
+
+        /* Needs looking at for TDM */
+        bits = snd_pcm_format_width(params_format(params));
+        if (bits < 0)
+                return bits;
+        aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits;
+
+        for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
+                if (dsp_divs[i] == params_rate(params))
+                        break;
+        }
+        if (i == ARRAY_SIZE(dsp_divs)) {
+                dev_err(codec->dev, "Unsupported sample rate %dHz\n",
+                        params_rate(params));
+                return -EINVAL;
+        }
+        dsp |= i << dsp_shift;
+
+        /* Pick a divisor for BCLK as close as we can get to ideal */
+        best = 0;
+        for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
+                cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate;
+                if (cur_val < 0) /* BCLK table is sorted */
+                        break;
+                best = i;
+        }
+        bclk_rate = wm8915->sysclk / bclk_divs[best];
+        dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
+                bclk_divs[best], bclk_rate);
+        bclk |= best;
+
+        lrclk = bclk_rate / params_rate(params);
+        dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
+                lrclk, bclk_rate / lrclk);
+
+        snd_soc_update_bits(codec, aifdata_reg,
+                            WM8915_AIF1TX_WL_MASK |
+                            WM8915_AIF1TX_SLOT_LEN_MASK,
+                            aifdata);
+        snd_soc_update_bits(codec, bclk_reg, WM8915_AIF1_BCLK_DIV_MASK, bclk);
+        snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK,
+                            lrclk);
+        snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2,
+                            WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp);
+
+        wm8915->rx_rate[dai->id] = params_rate(params);
+
+        return 0;
+}
+
+static int wm8915_set_sysclk(struct snd_soc_dai *dai,
+                int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int lfclk = 0;
+        int ratediv = 0;
+        int src;
+        int old;
+
+        /* Disable SYSCLK while we reconfigure */
+        old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1) & WM8915_SYSCLK_ENA;
+        snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
+                            WM8915_SYSCLK_ENA, 0);
+
+        switch (clk_id) {
+        case WM8915_SYSCLK_MCLK1:
+                wm8915->sysclk = freq;
+                src = 0;
+                break;
+        case WM8915_SYSCLK_MCLK2:
+                wm8915->sysclk = freq;
+                src = 1;
+                break;
+        case WM8915_SYSCLK_FLL:
+                wm8915->sysclk = freq;
+                src = 2;
+                break;
+        default:
+                dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
+                return -EINVAL;
+        }
+
+        switch (wm8915->sysclk) {
+        case 6144000:
+                snd_soc_update_bits(codec, WM8915_AIF_RATE,
+                                    WM8915_SYSCLK_RATE, 0);
+                break;
+        case 24576000:
+                ratediv = WM8915_SYSCLK_DIV;
+        case 12288000:
+                snd_soc_update_bits(codec, WM8915_AIF_RATE,
+                                    WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE);
+                break;
+        case 32000:
+        case 32768:
+                lfclk = WM8915_LFCLK_ENA;
+                break;
+        default:
+                dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
+                         wm8915->sysclk);
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
+                            WM8915_SYSCLK_SRC_MASK | WM8915_SYSCLK_DIV_MASK,
+                            src << WM8915_SYSCLK_SRC_SHIFT | ratediv);
+        snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk);
+        snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
+                            WM8915_SYSCLK_ENA, old);
+
+        return 0;
+}
+
+struct _fll_div {
+        u16 fll_fratio;
+        u16 fll_outdiv;
+        u16 fll_refclk_div;
+        u16 fll_loop_gain;
+        u16 fll_ref_freq;
+        u16 n;
+        u16 theta;
+        u16 lambda;
+};
+
+static struct {
+        unsigned int min;
+        unsigned int max;
+        u16 fll_fratio;
+        int ratio;
+} fll_fratios[] = {
+        {       0,    64000, 4, 16 },
+        {   64000,   128000, 3,  8 },
+        {  128000,   256000, 2,  4 },
+        {  256000,  1000000, 1,  2 },
+        { 1000000, 13500000, 0,  1 },
+};
+
+static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
+                       unsigned int Fout)
+{
+        unsigned int target;
+        unsigned int div;
+        unsigned int fratio, gcd_fll;
+        int i;
+
+        /* Fref must be <=13.5MHz */
+        div = 1;
+        fll_div->fll_refclk_div = 0;
+        while ((Fref / div) > 13500000) {
+                div *= 2;
+                fll_div->fll_refclk_div++;
+
+                if (div > 8) {
+                        pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
+                               Fref);
+                        return -EINVAL;
+                }
+        }
+
+        pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
+
+        /* Apply the division for our remaining calculations */
+        Fref /= div;
+
+        if (Fref >= 3000000)
+                fll_div->fll_loop_gain = 5;
+        else
+                fll_div->fll_loop_gain = 0;
+
+        if (Fref >= 48000)
+                fll_div->fll_ref_freq = 0;
+        else
+                fll_div->fll_ref_freq = 1;
+
+        /* Fvco should be 90-100MHz; don't check the upper bound */
+        div = 2;
+        while (Fout * div < 90000000) {
+                div++;
+                if (div > 64) {
+                        pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
+                               Fout);
+                        return -EINVAL;
+                }
+        }
+        target = Fout * div;
+        fll_div->fll_outdiv = div - 1;
+
+        pr_debug("FLL Fvco=%dHz\n", target);
+
+        /* Find an appropraite FLL_FRATIO and factor it out of the target */
+        for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
+                if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
+                        fll_div->fll_fratio = fll_fratios[i].fll_fratio;
+                        fratio = fll_fratios[i].ratio;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(fll_fratios)) {
+                pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
+                return -EINVAL;
+        }
+
+        fll_div->n = target / (fratio * Fref);
+
+        if (target % Fref == 0) {
+                fll_div->theta = 0;
+                fll_div->lambda = 0;
+        } else {
+                gcd_fll = gcd(target, fratio * Fref);
+
+                fll_div->theta = (target - (fll_div->n * fratio * Fref))
+                        / gcd_fll;
+                fll_div->lambda = (fratio * Fref) / gcd_fll;
+        }
+
+        pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
+                 fll_div->n, fll_div->theta, fll_div->lambda);
+        pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
+                 fll_div->fll_fratio, fll_div->fll_outdiv,
+                 fll_div->fll_refclk_div);
+
+        return 0;
+}
+
+static int wm8915_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
+                          unsigned int Fref, unsigned int Fout)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        struct _fll_div fll_div;
+        unsigned long timeout;
+        int ret, reg;
+
+        /* Any change? */
+        if (source == wm8915->fll_src && Fref == wm8915->fll_fref &&
+            Fout == wm8915->fll_fout)
+                return 0;
+
+        if (Fout == 0) {
+                dev_dbg(codec->dev, "FLL disabled\n");
+
+                wm8915->fll_fref = 0;
+                wm8915->fll_fout = 0;
+
+                snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
+                                    WM8915_FLL_ENA, 0);
+
+                return 0;
+        }
+
+        ret = fll_factors(&fll_div, Fref, Fout);
+        if (ret != 0)
+                return ret;
+
+        switch (source) {
+        case WM8915_FLL_MCLK1:
+                reg = 0;
+                break;
+        case WM8915_FLL_MCLK2:
+                reg = 1;
+                break;
+        case WM8915_FLL_DACLRCLK1:
+                reg = 2;
+                break;
+        case WM8915_FLL_BCLK1:
+                reg = 3;
+                break;
+        default:
+                dev_err(codec->dev, "Unknown FLL source %d\n", ret);
+                return -EINVAL;
+        }
+
+        reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT;
+        reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT;
+
+        snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5,
+                            WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ |
+                            WM8915_FLL_REFCLK_SRC_MASK, reg);
+
+        reg = 0;
+        if (fll_div.theta || fll_div.lambda)
+                reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT);
+        else
+                reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT;
+        snd_soc_write(codec, WM8915_FLL_EFS_2, reg);
+
+        snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2,
+                            WM8915_FLL_OUTDIV_MASK |
+                            WM8915_FLL_FRATIO_MASK,
+                            (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) |
+                            (fll_div.fll_fratio));
+
+        snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta);
+
+        snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4,
+                            WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK,
+                            (fll_div.n << WM8915_FLL_N_SHIFT) |
+                            fll_div.fll_loop_gain);
+
+        snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda);
+
+        snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
+                            WM8915_FLL_ENA, WM8915_FLL_ENA);
+
+        /* The FLL supports live reconfiguration - kick that in case we were
+         * already enabled.
+         */
+        snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK);
+
+        /* Wait for the FLL to lock, using the interrupt if possible */
+        if (Fref > 1000000)
+                timeout = usecs_to_jiffies(300);
+        else
+                timeout = msecs_to_jiffies(2);
+
+        wait_for_completion_timeout(&wm8915->fll_lock, timeout);
+
+        dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
+
+        wm8915->fll_fref = Fref;
+        wm8915->fll_fout = Fout;
+        wm8915->fll_src = source;
+
+        return 0;
+}
+
+#ifdef CONFIG_GPIOLIB
+static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip)
+{
+        return container_of(chip, struct wm8915_priv, gpio_chip);
+}
+
+static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
+        struct snd_soc_codec *codec = wm8915->codec;
+
+        snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
+                            WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT);
+}
+
+static int wm8915_gpio_direction_out(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
+        struct snd_soc_codec *codec = wm8915->codec;
+        int val;
+
+        val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT);
+
+        return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
+                                   WM8915_GP1_FN_MASK | WM8915_GP1_DIR |
+                                   WM8915_GP1_LVL, val);
+}
+
+static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
+        struct snd_soc_codec *codec = wm8915->codec;
+        int ret;
+
+        ret = snd_soc_read(codec, WM8915_GPIO_1 + offset);
+        if (ret < 0)
+                return ret;
+
+        return (ret & WM8915_GP1_LVL) != 0;
+}
+
+static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+        struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
+        struct snd_soc_codec *codec = wm8915->codec;
+
+        return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
+                                   WM8915_GP1_FN_MASK | WM8915_GP1_DIR,
+                                   (1 << WM8915_GP1_FN_SHIFT) |
+                                   (1 << WM8915_GP1_DIR_SHIFT));
+}
+
+static struct gpio_chip wm8915_template_chip = {
+        .label                  = "wm8915",
+        .owner                  = THIS_MODULE,
+        .direction_output       = wm8915_gpio_direction_out,
+        .set                    = wm8915_gpio_set,
+        .direction_input        = wm8915_gpio_direction_in,
+        .get                    = wm8915_gpio_get,
+        .can_sleep              = 1,
+};
+
+static void wm8915_init_gpio(struct snd_soc_codec *codec)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        wm8915->gpio_chip = wm8915_template_chip;
+        wm8915->gpio_chip.ngpio = 5;
+        wm8915->gpio_chip.dev = codec->dev;
+
+        if (wm8915->pdata.gpio_base)
+                wm8915->gpio_chip.base = wm8915->pdata.gpio_base;
+        else
+                wm8915->gpio_chip.base = -1;
+
+        ret = gpiochip_add(&wm8915->gpio_chip);
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
+}
+
+static void wm8915_free_gpio(struct snd_soc_codec *codec)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        ret = gpiochip_remove(&wm8915->gpio_chip);
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
+}
+#else
+static void wm8915_init_gpio(struct snd_soc_codec *codec)
+{
+}
+
+static void wm8915_free_gpio(struct snd_soc_codec *codec)
+{
+}
+#endif
+
+/**
+ * wm8915_detect - Enable default WM8915 jack detection
+ *
+ * The WM8915 has advanced accessory detection support for headsets.
+ * This function provides a default implementation which integrates
+ * the majority of this functionality with minimal user configuration.
+ *
+ * This will detect headset, headphone and short circuit button and
+ * will also detect inverted microphone ground connections and update
+ * the polarity of the connections.
+ */
+int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
+                  wm8915_polarity_fn polarity_cb)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+
+        wm8915->jack = jack;
+        wm8915->detecting = true;
+        wm8915->polarity_cb = polarity_cb;
+
+        if (wm8915->polarity_cb)
+                wm8915->polarity_cb(codec, 0);
+
+        /* Clear discarge to avoid noise during detection */
+        snd_soc_update_bits(codec, WM8915_MICBIAS_1,
+                            WM8915_MICB1_DISCH, 0);
+        snd_soc_update_bits(codec, WM8915_MICBIAS_2,
+                            WM8915_MICB2_DISCH, 0);
+
+        /* LDO2 powers the microphones, SYSCLK clocks detection */
+        snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
+        snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
+
+        /* We start off just enabling microphone detection - even a
+         * plain headphone will trigger detection.
+         */
+        snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
+                            WM8915_MICD_ENA, WM8915_MICD_ENA);
+
+        /* Slowest detection rate, gives debounce for initial detection */
+        snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
+                            WM8915_MICD_RATE_MASK,
+                            WM8915_MICD_RATE_MASK);
+
+        /* Enable interrupts and we're off */
+        snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK,
+                            WM8915_IM_MICD_EINT, 0);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(wm8915_detect);
+
+static void wm8915_micd(struct snd_soc_codec *codec)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int val, reg;
+
+        val = snd_soc_read(codec, WM8915_MIC_DETECT_3);
+
+        dev_dbg(codec->dev, "Microphone event: %x\n", val);
+
+        if (!(val & WM8915_MICD_VALID)) {
+                dev_warn(codec->dev, "Microphone detection state invalid\n");
+                return;
+        }
+
+        /* No accessory, reset everything and report removal */
+        if (!(val & WM8915_MICD_STS)) {
+                dev_dbg(codec->dev, "Jack removal detected\n");
+                wm8915->jack_mic = false;
+                wm8915->detecting = true;
+                snd_soc_jack_report(wm8915->jack, 0,
+                                    SND_JACK_HEADSET | SND_JACK_BTN_0);
+                snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
+                                    WM8915_MICD_RATE_MASK,
+                                    WM8915_MICD_RATE_MASK);
+                return;
+        }
+
+        /* If the measurement is very high we've got a microphone but
+         * do a little debounce to account for mechanical issues.
+         */
+        if (val & 0x400) {
+                dev_dbg(codec->dev, "Microphone detected\n");
+                snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET,
+                                    SND_JACK_HEADSET | SND_JACK_BTN_0);
+                wm8915->jack_mic = true;
+                wm8915->detecting = false;
+        }
+
+        /* If we detected a lower impedence during initial startup
+         * then we probably have the wrong polarity, flip it.  Don't
+         * do this for the lowest impedences to speed up detection of
+         * plain headphones.
+         */
+        if (wm8915->detecting && (val & 0x3f0)) {
+                reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2);
+                reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
+                        WM8915_MICD_BIAS_SRC;
+                snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
+                                    WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
+                                    WM8915_MICD_BIAS_SRC, reg);
+
+                if (wm8915->polarity_cb)
+                        wm8915->polarity_cb(codec,
+                                            (reg & WM8915_MICD_SRC) != 0);
+
+                dev_dbg(codec->dev, "Set microphone polarity to %d\n",
+                        (reg & WM8915_MICD_SRC) != 0);
+
+                return;
+        }
+
+        /* Don't distinguish between buttons, just report any low
+         * impedence as BTN_0.
+         */
+        if (val & 0x3fc) {
+                if (wm8915->jack_mic) {
+                        dev_dbg(codec->dev, "Mic button detected\n");
+                        snd_soc_jack_report(wm8915->jack,
+                                            SND_JACK_HEADSET | SND_JACK_BTN_0,
+                                            SND_JACK_HEADSET | SND_JACK_BTN_0);
+                } else {
+                        dev_dbg(codec->dev, "Headphone detected\n");
+                        snd_soc_jack_report(wm8915->jack,
+                                            SND_JACK_HEADPHONE,
+                                            SND_JACK_HEADSET |
+                                            SND_JACK_BTN_0);
+                        wm8915->detecting = false;
+                }
+        }
+
+        /* Increase poll rate to give better responsiveness for buttons */
+        if (!wm8915->detecting)
+                snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
+                                    WM8915_MICD_RATE_MASK,
+                                    5 << WM8915_MICD_RATE_SHIFT);
+}
+
+static irqreturn_t wm8915_irq(int irq, void *data)
+{
+        struct snd_soc_codec *codec = data;
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        int irq_val;
+
+        irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2);
+        if (irq_val < 0) {
+                dev_err(codec->dev, "Failed to read IRQ status: %d\n",
+                        irq_val);
+                return IRQ_NONE;
+        }
+        irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK);
+
+        if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) {
+                dev_dbg(codec->dev, "DC servo IRQ\n");
+                complete(&wm8915->dcs_done);
+        }
+
+        if (irq_val & WM8915_FIFOS_ERR_EINT)
+                dev_err(codec->dev, "Digital core FIFO error\n");
+
+        if (irq_val & WM8915_FLL_LOCK_EINT) {
+                dev_dbg(codec->dev, "FLL locked\n");
+                complete(&wm8915->fll_lock);
+        }
+
+        if (irq_val & WM8915_MICD_EINT)
+                wm8915_micd(codec);
+
+        if (irq_val) {
+                snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val);
+
+                return IRQ_HANDLED;
+        } else {
+                return IRQ_NONE;
+        }
+}
+
+static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        struct wm8915_pdata *pdata = &wm8915->pdata;
+
+        struct snd_kcontrol_new controls[] = {
+                SOC_ENUM_EXT("DSP1 EQ Mode",
+                             wm8915->retune_mobile_enum,
+                             wm8915_get_retune_mobile_enum,
+                             wm8915_put_retune_mobile_enum),
+                SOC_ENUM_EXT("DSP2 EQ Mode",
+                             wm8915->retune_mobile_enum,
+                             wm8915_get_retune_mobile_enum,
+                             wm8915_put_retune_mobile_enum),
+        };
+        int ret, i, j;
+        const char **t;
+
+        /* We need an array of texts for the enum API but the number
+         * of texts is likely to be less than the number of
+         * configurations due to the sample rate dependency of the
+         * configurations. */
+        wm8915->num_retune_mobile_texts = 0;
+        wm8915->retune_mobile_texts = NULL;
+        for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
+                for (j = 0; j < wm8915->num_retune_mobile_texts; j++) {
+                        if (strcmp(pdata->retune_mobile_cfgs[i].name,
+                                   wm8915->retune_mobile_texts[j]) == 0)
+                                break;
+                }
+
+                if (j != wm8915->num_retune_mobile_texts)
+                        continue;
+
+                /* Expand the array... */
+                t = krealloc(wm8915->retune_mobile_texts,
+                             sizeof(char *) * 
+                             (wm8915->num_retune_mobile_texts + 1),
+                             GFP_KERNEL);
+                if (t == NULL)
+                        continue;
+
+                /* ...store the new entry... */
+                t[wm8915->num_retune_mobile_texts] = 
+                        pdata->retune_mobile_cfgs[i].name;
+
+                /* ...and remember the new version. */
+                wm8915->num_retune_mobile_texts++;
+                wm8915->retune_mobile_texts = t;
+        }
+
+        dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
+                wm8915->num_retune_mobile_texts);
+
+        wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts;
+        wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts;
+
+        ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
+        if (ret != 0)
+                dev_err(codec->dev,
+                        "Failed to add ReTune Mobile controls: %d\n", ret);
+}
+
+static int wm8915_probe(struct snd_soc_codec *codec)
+{
+        int ret;
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        struct i2c_client *i2c = to_i2c_client(codec->dev);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int i, irq_flags;
+
+        wm8915->codec = codec;
+
+        init_completion(&wm8915->dcs_done);
+        init_completion(&wm8915->fll_lock);
+
+        dapm->idle_bias_off = true;
+        dapm->bias_level = SND_SOC_BIAS_OFF;
+
+        ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                goto err;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
+                wm8915->supplies[i].supply = wm8915_supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies),
+                                 wm8915->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                goto err;
+        }
+
+        wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0;
+        wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1;
+        wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2;
+        wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3;
+        wm8915->disable_nb[4].notifier_call = wm8915_regulator_event_4;
+        wm8915->disable_nb[5].notifier_call = wm8915_regulator_event_5;
+
+        /* This should really be moved into the regulator core */
+        for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) {
+                ret = regulator_register_notifier(wm8915->supplies[i].consumer,
+                                                  &wm8915->disable_nb[i]);
+                if (ret != 0) {
+                        dev_err(codec->dev,
+                                "Failed to register regulator notifier: %d\n",
+                                ret);
+                }
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
+                                    wm8915->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                goto err_get;
+        }
+
+        if (wm8915->pdata.ldo_ena >= 0) {
+                gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1);
+                msleep(5);
+        }
+
+        ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
+                goto err_enable;
+        }
+        if (ret != 0x8915) {
+                dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret);
+                ret = -EINVAL;
+                goto err_enable;
+        }
+
+        ret = snd_soc_read(codec, WM8915_CHIP_REVISION);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read device revision: %d\n",
+                        ret);
+                goto err_enable;
+        }
+        
+        dev_info(codec->dev, "revision %c\n",
+                 (ret & WM8915_CHIP_REV_MASK) + 'A');
+
+        if (wm8915->pdata.ldo_ena >= 0) {
+                gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
+        } else {
+                ret = wm8915_reset(codec);
+                if (ret < 0) {
+                        dev_err(codec->dev, "Failed to issue reset\n");
+                        goto err_enable;
+                }
+        }
+
+        codec->cache_only = true;
+
+        /* Apply platform data settings */
+        snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL,
+                            WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK,
+                            wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT |
+                            wm8915->pdata.inr_mode);
+
+        for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) {
+                if (!wm8915->pdata.gpio_default[i])
+                        continue;
+
+                snd_soc_write(codec, WM8915_GPIO_1 + i,
+                              wm8915->pdata.gpio_default[i] & 0xffff);
+        }
+
+        if (wm8915->pdata.spkmute_seq)
+                snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE,
+                                    WM8915_SPK_MUTE_ENDIAN |
+                                    WM8915_SPK_MUTE_SEQ1_MASK,
+                                    wm8915->pdata.spkmute_seq);
+
+        snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
+                            WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC |
+                            WM8915_MICD_SRC, wm8915->pdata.micdet_def);
+
+        /* Latch volume update bits */
+        snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME,
+                            WM8915_IN1_VU, WM8915_IN1_VU);
+        snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME,
+                            WM8915_IN1_VU, WM8915_IN1_VU);
+
+        snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME,
+                            WM8915_DAC1_VU, WM8915_DAC1_VU);
+        snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME,
+                            WM8915_DAC1_VU, WM8915_DAC1_VU);
+        snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME,
+                            WM8915_DAC2_VU, WM8915_DAC2_VU);
+        snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME,
+                            WM8915_DAC2_VU, WM8915_DAC2_VU);
+
+        snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME,
+                            WM8915_DAC1_VU, WM8915_DAC1_VU);
+        snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME,
+                            WM8915_DAC1_VU, WM8915_DAC1_VU);
+        snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME,
+                            WM8915_DAC2_VU, WM8915_DAC2_VU);
+        snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME,
+                            WM8915_DAC2_VU, WM8915_DAC2_VU);
+
+        snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME,
+                            WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
+        snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME,
+                            WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
+        snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME,
+                            WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
+        snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME,
+                            WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
+
+        snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME,
+                            WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
+        snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME,
+                            WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
+        snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME,
+                            WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
+        snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME,
+                            WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
+
+        /* No support currently for the underclocked TDM modes and
+         * pick a default TDM layout with each channel pair working with
+         * slots 0 and 1. */
+        snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION,
+                            WM8915_AIF1RX_CHAN0_SLOTS_MASK |
+                            WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
+        snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION,
+                            WM8915_AIF1RX_CHAN1_SLOTS_MASK |
+                            WM8915_AIF1RX_CHAN1_START_SLOT_MASK,
+                            1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
+        snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION,
+                            WM8915_AIF1RX_CHAN2_SLOTS_MASK |
+                            WM8915_AIF1RX_CHAN2_START_SLOT_MASK,
+                            1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
+        snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION,
+                            WM8915_AIF1RX_CHAN3_SLOTS_MASK |
+                            WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
+        snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION,
+                            WM8915_AIF1RX_CHAN4_SLOTS_MASK |
+                            WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
+        snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION,
+                            WM8915_AIF1RX_CHAN5_SLOTS_MASK |
+                            WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
+
+        snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION,
+                            WM8915_AIF2RX_CHAN0_SLOTS_MASK |
+                            WM8915_AIF2RX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
+        snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION,
+                            WM8915_AIF2RX_CHAN1_SLOTS_MASK |
+                            WM8915_AIF2RX_CHAN1_START_SLOT_MASK,
+                            1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
+
+        snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION,
+                            WM8915_AIF1TX_CHAN0_SLOTS_MASK |
+                            WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
+        snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
+                            WM8915_AIF1TX_CHAN1_SLOTS_MASK |
+                            WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
+        snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION,
+                            WM8915_AIF1TX_CHAN2_SLOTS_MASK |
+                            WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
+        snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION,
+                            WM8915_AIF1TX_CHAN3_SLOTS_MASK |
+                            WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
+        snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION,
+                            WM8915_AIF1TX_CHAN4_SLOTS_MASK |
+                            WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
+        snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION,
+                            WM8915_AIF1TX_CHAN5_SLOTS_MASK |
+                            WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
+
+        snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION,
+                            WM8915_AIF2TX_CHAN0_SLOTS_MASK |
+                            WM8915_AIF2TX_CHAN0_START_SLOT_MASK,
+                            1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
+        snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
+                            WM8915_AIF2TX_CHAN1_SLOTS_MASK |
+                            WM8915_AIF2TX_CHAN1_START_SLOT_MASK,
+                            1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
+
+        if (wm8915->pdata.num_retune_mobile_cfgs)
+                wm8915_retune_mobile_pdata(codec);
+        else
+                snd_soc_add_controls(codec, wm8915_eq_controls,
+                                     ARRAY_SIZE(wm8915_eq_controls));
+
+        /* If the TX LRCLK pins are not in LRCLK mode configure the
+         * AIFs to source their clocks from the RX LRCLKs.
+         */
+        if ((snd_soc_read(codec, WM8915_GPIO_1)))
+                snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2,
+                                    WM8915_AIF1TX_LRCLK_MODE,
+                                    WM8915_AIF1TX_LRCLK_MODE);
+
+        if ((snd_soc_read(codec, WM8915_GPIO_2)))
+                snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2,
+                                    WM8915_AIF2TX_LRCLK_MODE,
+                                    WM8915_AIF2TX_LRCLK_MODE);
+
+        regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
+
+        wm8915_init_gpio(codec);
+
+        if (i2c->irq) {
+                if (wm8915->pdata.irq_flags)
+                        irq_flags = wm8915->pdata.irq_flags;
+                else
+                        irq_flags = IRQF_TRIGGER_LOW;
+
+                irq_flags |= IRQF_ONESHOT;
+
+                ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq,
+                                           irq_flags, "wm8915", codec);
+                if (ret == 0) {
+                        /* Unmask the interrupt */
+                        snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
+                                            WM8915_IM_IRQ, 0);
+
+                        /* Enable error reporting and DC servo status */
+                        snd_soc_update_bits(codec,
+                                            WM8915_INTERRUPT_STATUS_2_MASK,
+                                            WM8915_IM_DCS_DONE_23_EINT |
+                                            WM8915_IM_DCS_DONE_01_EINT |
+                                            WM8915_IM_FLL_LOCK_EINT |
+                                            WM8915_IM_FIFOS_ERR_EINT,
+                                            0);
+                } else {
+                        dev_err(codec->dev, "Failed to request IRQ: %d\n",
+                                ret);
+                }
+        }
+
+        return 0;
+
+err_enable:
+        if (wm8915->pdata.ldo_ena >= 0)
+                gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
+
+        regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
+err_get:
+        regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
+err:
+        return ret;
+}
+
+static int wm8915_remove(struct snd_soc_codec *codec)
+{
+        struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
+        struct i2c_client *i2c = to_i2c_client(codec->dev);
+        int i;
+
+        snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
+                            WM8915_IM_IRQ, WM8915_IM_IRQ);
+
+        if (i2c->irq)
+                free_irq(i2c->irq, codec);
+
+        wm8915_free_gpio(codec);
+
+        for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
+                regulator_unregister_notifier(wm8915->supplies[i].consumer,
+                                              &wm8915->disable_nb[i]);
+        regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8915 = {
+        .probe =        wm8915_probe,
+        .remove =       wm8915_remove,
+        .set_bias_level = wm8915_set_bias_level,
+        .seq_notifier = wm8915_seq_notifier,
+        .reg_cache_size = WM8915_MAX_REGISTER + 1,
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8915_reg,
+        .volatile_register = wm8915_volatile_register,
+        .readable_register = wm8915_readable_register,
+        .compress_type = SND_SOC_RBTREE_COMPRESSION,
+        .controls = wm8915_snd_controls,
+        .num_controls = ARRAY_SIZE(wm8915_snd_controls),
+        .dapm_widgets = wm8915_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets),
+        .dapm_routes = wm8915_dapm_routes,
+        .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes),
+        .set_pll = wm8915_set_fll,
+};
+
+#define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+                      SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
+#define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
+                        SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
+                        SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops wm8915_dai_ops = {
+        .set_fmt = wm8915_set_fmt,
+        .hw_params = wm8915_hw_params,
+        .set_sysclk = wm8915_set_sysclk,
+};
+
+static struct snd_soc_dai_driver wm8915_dai[] = {
+        {
+                .name = "wm8915-aif1",
+                .playback = {
+                        .stream_name = "AIF1 Playback",
+                        .channels_min = 1,
+                        .channels_max = 6,
+                        .rates = WM8915_RATES,
+                        .formats = WM8915_FORMATS,
+                },
+                .capture = {
+                         .stream_name = "AIF1 Capture",
+                         .channels_min = 1,
+                         .channels_max = 6,
+                         .rates = WM8915_RATES,
+                         .formats = WM8915_FORMATS,
+                 },
+                .ops = &wm8915_dai_ops,
+        },
+        {
+                .name = "wm8915-aif2",
+                .playback = {
+                        .stream_name = "AIF2 Playback",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = WM8915_RATES,
+                        .formats = WM8915_FORMATS,
+                },
+                .capture = {
+                         .stream_name = "AIF2 Capture",
+                         .channels_min = 1,
+                         .channels_max = 2,
+                         .rates = WM8915_RATES,
+                         .formats = WM8915_FORMATS,
+                 },
+                .ops = &wm8915_dai_ops,
+        },
+};
+
+static __devinit int wm8915_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8915_priv *wm8915;
+        int ret;
+
+        wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL);
+        if (wm8915 == NULL)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, wm8915);
+
+        if (dev_get_platdata(&i2c->dev))
+                memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev),
+                       sizeof(wm8915->pdata));
+
+        if (wm8915->pdata.ldo_ena > 0) {
+                ret = gpio_request_one(wm8915->pdata.ldo_ena,
+                                       GPIOF_OUT_INIT_LOW, "WM8915 ENA");
+                if (ret < 0) {
+                        dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
+                                wm8915->pdata.ldo_ena, ret);
+                        goto err;
+                }
+        }
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                                     &soc_codec_dev_wm8915, wm8915_dai,
+                                     ARRAY_SIZE(wm8915_dai));
+        if (ret < 0)
+                goto err_gpio;
+
+        return ret;
+
+err_gpio:
+        if (wm8915->pdata.ldo_ena > 0)
+                gpio_free(wm8915->pdata.ldo_ena);
+err:
+        kfree(wm8915);
+
+        return ret;
+}
+
+static __devexit int wm8915_i2c_remove(struct i2c_client *client)
+{
+        struct wm8915_priv *wm8915 = i2c_get_clientdata(client);
+
+        snd_soc_unregister_codec(&client->dev);
+        if (wm8915->pdata.ldo_ena > 0)
+                gpio_free(wm8915->pdata.ldo_ena);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id wm8915_i2c_id[] = {
+        { "wm8915", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id);
+
+static struct i2c_driver wm8915_i2c_driver = {
+        .driver = {
+                .name = "wm8915",
+                .owner = THIS_MODULE,
+        },
+        .probe =    wm8915_i2c_probe,
+        .remove =   __devexit_p(wm8915_i2c_remove),
+        .id_table = wm8915_i2c_id,
+};
+
+static int __init wm8915_modinit(void)
+{
+        int ret;
+
+        ret = i2c_add_driver(&wm8915_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n",
+                       ret);
+        }
+
+        return ret;
+}
+module_init(wm8915_modinit);
+
+static void __exit wm8915_exit(void)
+{
+        i2c_del_driver(&wm8915_i2c_driver);
+}
+module_exit(wm8915_exit);
+
+MODULE_DESCRIPTION("ASoC WM8915 driver");
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8915.h b/sound/soc/codecs/wm8915.h
new file mode 100644
index 000000000000..200ffd7bf953
--- /dev/null
+++ b/sound/soc/codecs/wm8915.h
@@ -0,0 +1,3717 @@
+/*
+ * wm8915.h - WM8915 audio codec interface
+ *
+ * Copyright 2011 Wolfson Microelectronics PLC.
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef _WM8915_H
+#define _WM8915_H
+
+#define WM8915_SYSCLK_MCLK1 1
+#define WM8915_SYSCLK_MCLK2 2
+#define WM8915_SYSCLK_FLL   3
+
+#define WM8915_FLL_MCLK1      1
+#define WM8915_FLL_MCLK2      2
+#define WM8915_FLL_DACLRCLK1  3
+#define WM8915_FLL_BCLK1      4
+
+typedef void (*wm8915_polarity_fn)(struct snd_soc_codec *codec, int polarity);
+
+int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
+                  wm8915_polarity_fn polarity_cb);
+
+/*
+ * Register values.
+ */
+#define WM8915_SOFTWARE_RESET                   0x00
+#define WM8915_POWER_MANAGEMENT_1               0x01
+#define WM8915_POWER_MANAGEMENT_2               0x02
+#define WM8915_POWER_MANAGEMENT_3               0x03
+#define WM8915_POWER_MANAGEMENT_4               0x04
+#define WM8915_POWER_MANAGEMENT_5               0x05
+#define WM8915_POWER_MANAGEMENT_6               0x06
+#define WM8915_POWER_MANAGEMENT_7               0x07
+#define WM8915_POWER_MANAGEMENT_8               0x08
+#define WM8915_LEFT_LINE_INPUT_VOLUME           0x10
+#define WM8915_RIGHT_LINE_INPUT_VOLUME          0x11
+#define WM8915_LINE_INPUT_CONTROL               0x12
+#define WM8915_DAC1_HPOUT1_VOLUME               0x15
+#define WM8915_DAC2_HPOUT2_VOLUME               0x16
+#define WM8915_DAC1_LEFT_VOLUME                 0x18
+#define WM8915_DAC1_RIGHT_VOLUME                0x19
+#define WM8915_DAC2_LEFT_VOLUME                 0x1A
+#define WM8915_DAC2_RIGHT_VOLUME                0x1B
+#define WM8915_OUTPUT1_LEFT_VOLUME              0x1C
+#define WM8915_OUTPUT1_RIGHT_VOLUME             0x1D
+#define WM8915_OUTPUT2_LEFT_VOLUME              0x1E
+#define WM8915_OUTPUT2_RIGHT_VOLUME             0x1F
+#define WM8915_MICBIAS_1                        0x20
+#define WM8915_MICBIAS_2                        0x21
+#define WM8915_LDO_1                            0x28
+#define WM8915_LDO_2                            0x29
+#define WM8915_ACCESSORY_DETECT_MODE_1          0x30
+#define WM8915_ACCESSORY_DETECT_MODE_2          0x31
+#define WM8915_HEADPHONE_DETECT_1               0x34
+#define WM8915_HEADPHONE_DETECT_2               0x35
+#define WM8915_MIC_DETECT_1                     0x38
+#define WM8915_MIC_DETECT_2                     0x39
+#define WM8915_MIC_DETECT_3                     0x3A
+#define WM8915_CHARGE_PUMP_1                    0x40
+#define WM8915_CHARGE_PUMP_2                    0x41
+#define WM8915_DC_SERVO_1                       0x50
+#define WM8915_DC_SERVO_2                       0x51
+#define WM8915_DC_SERVO_3                       0x52
+#define WM8915_DC_SERVO_5                       0x54
+#define WM8915_DC_SERVO_6                       0x55
+#define WM8915_DC_SERVO_7                       0x56
+#define WM8915_DC_SERVO_READBACK_0              0x57
+#define WM8915_ANALOGUE_HP_1                    0x60
+#define WM8915_ANALOGUE_HP_2                    0x61
+#define WM8915_CHIP_REVISION                    0x100
+#define WM8915_CONTROL_INTERFACE_1              0x101
+#define WM8915_WRITE_SEQUENCER_CTRL_1           0x110
+#define WM8915_WRITE_SEQUENCER_CTRL_2           0x111
+#define WM8915_AIF_CLOCKING_1                   0x200
+#define WM8915_AIF_CLOCKING_2                   0x201
+#define WM8915_CLOCKING_1                       0x208
+#define WM8915_CLOCKING_2                       0x209
+#define WM8915_AIF_RATE                         0x210
+#define WM8915_FLL_CONTROL_1                    0x220
+#define WM8915_FLL_CONTROL_2                    0x221
+#define WM8915_FLL_CONTROL_3                    0x222
+#define WM8915_FLL_CONTROL_4                    0x223
+#define WM8915_FLL_CONTROL_5                    0x224
+#define WM8915_FLL_CONTROL_6                    0x225
+#define WM8915_FLL_EFS_1                        0x226
+#define WM8915_FLL_EFS_2                        0x227
+#define WM8915_AIF1_CONTROL                     0x300
+#define WM8915_AIF1_BCLK                        0x301
+#define WM8915_AIF1_TX_LRCLK_1                  0x302
+#define WM8915_AIF1_TX_LRCLK_2                  0x303
+#define WM8915_AIF1_RX_LRCLK_1                  0x304
+#define WM8915_AIF1_RX_LRCLK_2                  0x305
+#define WM8915_AIF1TX_DATA_CONFIGURATION_1      0x306
+#define WM8915_AIF1TX_DATA_CONFIGURATION_2      0x307
+#define WM8915_AIF1RX_DATA_CONFIGURATION        0x308
+#define WM8915_AIF1TX_CHANNEL_0_CONFIGURATION   0x309
+#define WM8915_AIF1TX_CHANNEL_1_CONFIGURATION   0x30A
+#define WM8915_AIF1TX_CHANNEL_2_CONFIGURATION   0x30B
+#define WM8915_AIF1TX_CHANNEL_3_CONFIGURATION   0x30C
+#define WM8915_AIF1TX_CHANNEL_4_CONFIGURATION   0x30D
+#define WM8915_AIF1TX_CHANNEL_5_CONFIGURATION   0x30E
+#define WM8915_AIF1RX_CHANNEL_0_CONFIGURATION   0x30F
+#define WM8915_AIF1RX_CHANNEL_1_CONFIGURATION   0x310
+#define WM8915_AIF1RX_CHANNEL_2_CONFIGURATION   0x311
+#define WM8915_AIF1RX_CHANNEL_3_CONFIGURATION   0x312
+#define WM8915_AIF1RX_CHANNEL_4_CONFIGURATION   0x313
+#define WM8915_AIF1RX_CHANNEL_5_CONFIGURATION   0x314
+#define WM8915_AIF1RX_MONO_CONFIGURATION        0x315
+#define WM8915_AIF1TX_TEST                      0x31A
+#define WM8915_AIF2_CONTROL                     0x320
+#define WM8915_AIF2_BCLK                        0x321
+#define WM8915_AIF2_TX_LRCLK_1                  0x322
+#define WM8915_AIF2_TX_LRCLK_2                  0x323
+#define WM8915_AIF2_RX_LRCLK_1                  0x324
+#define WM8915_AIF2_RX_LRCLK_2                  0x325
+#define WM8915_AIF2TX_DATA_CONFIGURATION_1      0x326
+#define WM8915_AIF2TX_DATA_CONFIGURATION_2      0x327
+#define WM8915_AIF2RX_DATA_CONFIGURATION        0x328
+#define WM8915_AIF2TX_CHANNEL_0_CONFIGURATION   0x329
+#define WM8915_AIF2TX_CHANNEL_1_CONFIGURATION   0x32A
+#define WM8915_AIF2RX_CHANNEL_0_CONFIGURATION   0x32B
+#define WM8915_AIF2RX_CHANNEL_1_CONFIGURATION   0x32C
+#define WM8915_AIF2RX_MONO_CONFIGURATION        0x32D
+#define WM8915_AIF2TX_TEST                      0x32F
+#define WM8915_DSP1_TX_LEFT_VOLUME              0x400
+#define WM8915_DSP1_TX_RIGHT_VOLUME             0x401
+#define WM8915_DSP1_RX_LEFT_VOLUME              0x402
+#define WM8915_DSP1_RX_RIGHT_VOLUME             0x403
+#define WM8915_DSP1_TX_FILTERS                  0x410
+#define WM8915_DSP1_RX_FILTERS_1                0x420
+#define WM8915_DSP1_RX_FILTERS_2                0x421
+#define WM8915_DSP1_DRC_1                       0x440
+#define WM8915_DSP1_DRC_2                       0x441
+#define WM8915_DSP1_DRC_3                       0x442
+#define WM8915_DSP1_DRC_4                       0x443
+#define WM8915_DSP1_DRC_5                       0x444
+#define WM8915_DSP1_RX_EQ_GAINS_1               0x480
+#define WM8915_DSP1_RX_EQ_GAINS_2               0x481
+#define WM8915_DSP1_RX_EQ_BAND_1_A              0x482
+#define WM8915_DSP1_RX_EQ_BAND_1_B              0x483
+#define WM8915_DSP1_RX_EQ_BAND_1_PG             0x484
+#define WM8915_DSP1_RX_EQ_BAND_2_A              0x485
+#define WM8915_DSP1_RX_EQ_BAND_2_B              0x486
+#define WM8915_DSP1_RX_EQ_BAND_2_C              0x487
+#define WM8915_DSP1_RX_EQ_BAND_2_PG             0x488
+#define WM8915_DSP1_RX_EQ_BAND_3_A              0x489
+#define WM8915_DSP1_RX_EQ_BAND_3_B              0x48A
+#define WM8915_DSP1_RX_EQ_BAND_3_C              0x48B
+#define WM8915_DSP1_RX_EQ_BAND_3_PG             0x48C
+#define WM8915_DSP1_RX_EQ_BAND_4_A              0x48D
+#define WM8915_DSP1_RX_EQ_BAND_4_B              0x48E
+#define WM8915_DSP1_RX_EQ_BAND_4_C              0x48F
+#define WM8915_DSP1_RX_EQ_BAND_4_PG             0x490
+#define WM8915_DSP1_RX_EQ_BAND_5_A              0x491
+#define WM8915_DSP1_RX_EQ_BAND_5_B              0x492
+#define WM8915_DSP1_RX_EQ_BAND_5_PG             0x493
+#define WM8915_DSP2_TX_LEFT_VOLUME              0x500
+#define WM8915_DSP2_TX_RIGHT_VOLUME             0x501
+#define WM8915_DSP2_RX_LEFT_VOLUME              0x502
+#define WM8915_DSP2_RX_RIGHT_VOLUME             0x503
+#define WM8915_DSP2_TX_FILTERS                  0x510
+#define WM8915_DSP2_RX_FILTERS_1                0x520
+#define WM8915_DSP2_RX_FILTERS_2                0x521
+#define WM8915_DSP2_DRC_1                       0x540
+#define WM8915_DSP2_DRC_2                       0x541
+#define WM8915_DSP2_DRC_3                       0x542
+#define WM8915_DSP2_DRC_4                       0x543
+#define WM8915_DSP2_DRC_5                       0x544
+#define WM8915_DSP2_RX_EQ_GAINS_1               0x580
+#define WM8915_DSP2_RX_EQ_GAINS_2               0x581
+#define WM8915_DSP2_RX_EQ_BAND_1_A              0x582
+#define WM8915_DSP2_RX_EQ_BAND_1_B              0x583
+#define WM8915_DSP2_RX_EQ_BAND_1_PG             0x584
+#define WM8915_DSP2_RX_EQ_BAND_2_A              0x585
+#define WM8915_DSP2_RX_EQ_BAND_2_B              0x586
+#define WM8915_DSP2_RX_EQ_BAND_2_C              0x587
+#define WM8915_DSP2_RX_EQ_BAND_2_PG             0x588
+#define WM8915_DSP2_RX_EQ_BAND_3_A              0x589
+#define WM8915_DSP2_RX_EQ_BAND_3_B              0x58A
+#define WM8915_DSP2_RX_EQ_BAND_3_C              0x58B
+#define WM8915_DSP2_RX_EQ_BAND_3_PG             0x58C
+#define WM8915_DSP2_RX_EQ_BAND_4_A              0x58D
+#define WM8915_DSP2_RX_EQ_BAND_4_B              0x58E
+#define WM8915_DSP2_RX_EQ_BAND_4_C              0x58F
+#define WM8915_DSP2_RX_EQ_BAND_4_PG             0x590
+#define WM8915_DSP2_RX_EQ_BAND_5_A              0x591
+#define WM8915_DSP2_RX_EQ_BAND_5_B              0x592
+#define WM8915_DSP2_RX_EQ_BAND_5_PG             0x593
+#define WM8915_DAC1_MIXER_VOLUMES               0x600
+#define WM8915_DAC1_LEFT_MIXER_ROUTING          0x601
+#define WM8915_DAC1_RIGHT_MIXER_ROUTING         0x602
+#define WM8915_DAC2_MIXER_VOLUMES               0x603
+#define WM8915_DAC2_LEFT_MIXER_ROUTING          0x604
+#define WM8915_DAC2_RIGHT_MIXER_ROUTING         0x605
+#define WM8915_DSP1_TX_LEFT_MIXER_ROUTING       0x606
+#define WM8915_DSP1_TX_RIGHT_MIXER_ROUTING      0x607
+#define WM8915_DSP2_TX_LEFT_MIXER_ROUTING       0x608
+#define WM8915_DSP2_TX_RIGHT_MIXER_ROUTING      0x609
+#define WM8915_DSP_TX_MIXER_SELECT              0x60A
+#define WM8915_DAC_SOFTMUTE                     0x610
+#define WM8915_OVERSAMPLING                     0x620
+#define WM8915_SIDETONE                         0x621
+#define WM8915_GPIO_1                           0x700
+#define WM8915_GPIO_2                           0x701
+#define WM8915_GPIO_3                           0x702
+#define WM8915_GPIO_4                           0x703
+#define WM8915_GPIO_5                           0x704
+#define WM8915_PULL_CONTROL_1                   0x720
+#define WM8915_PULL_CONTROL_2                   0x721
+#define WM8915_INTERRUPT_STATUS_1               0x730
+#define WM8915_INTERRUPT_STATUS_2               0x731
+#define WM8915_INTERRUPT_RAW_STATUS_2           0x732
+#define WM8915_INTERRUPT_STATUS_1_MASK          0x738
+#define WM8915_INTERRUPT_STATUS_2_MASK          0x739
+#define WM8915_INTERRUPT_CONTROL                0x740
+#define WM8915_LEFT_PDM_SPEAKER                 0x800
+#define WM8915_RIGHT_PDM_SPEAKER                0x801
+#define WM8915_PDM_SPEAKER_MUTE_SEQUENCE        0x802
+#define WM8915_PDM_SPEAKER_VOLUME               0x803
+#define WM8915_WRITE_SEQUENCER_0                0x3000
+#define WM8915_WRITE_SEQUENCER_1                0x3001
+#define WM8915_WRITE_SEQUENCER_2                0x3002
+#define WM8915_WRITE_SEQUENCER_3                0x3003
+#define WM8915_WRITE_SEQUENCER_4                0x3004
+#define WM8915_WRITE_SEQUENCER_5                0x3005
+#define WM8915_WRITE_SEQUENCER_6                0x3006
+#define WM8915_WRITE_SEQUENCER_7                0x3007
+#define WM8915_WRITE_SEQUENCER_8                0x3008
+#define WM8915_WRITE_SEQUENCER_9                0x3009
+#define WM8915_WRITE_SEQUENCER_10               0x300A
+#define WM8915_WRITE_SEQUENCER_11               0x300B
+#define WM8915_WRITE_SEQUENCER_12               0x300C
+#define WM8915_WRITE_SEQUENCER_13               0x300D
+#define WM8915_WRITE_SEQUENCER_14               0x300E
+#define WM8915_WRITE_SEQUENCER_15               0x300F
+#define WM8915_WRITE_SEQUENCER_16               0x3010
+#define WM8915_WRITE_SEQUENCER_17               0x3011
+#define WM8915_WRITE_SEQUENCER_18               0x3012
+#define WM8915_WRITE_SEQUENCER_19               0x3013
+#define WM8915_WRITE_SEQUENCER_20               0x3014
+#define WM8915_WRITE_SEQUENCER_21               0x3015
+#define WM8915_WRITE_SEQUENCER_22               0x3016
+#define WM8915_WRITE_SEQUENCER_23               0x3017
+#define WM8915_WRITE_SEQUENCER_24               0x3018
+#define WM8915_WRITE_SEQUENCER_25               0x3019
+#define WM8915_WRITE_SEQUENCER_26               0x301A
+#define WM8915_WRITE_SEQUENCER_27               0x301B
+#define WM8915_WRITE_SEQUENCER_28               0x301C
+#define WM8915_WRITE_SEQUENCER_29               0x301D
+#define WM8915_WRITE_SEQUENCER_30               0x301E
+#define WM8915_WRITE_SEQUENCER_31               0x301F
+#define WM8915_WRITE_SEQUENCER_32               0x3020
+#define WM8915_WRITE_SEQUENCER_33               0x3021
+#define WM8915_WRITE_SEQUENCER_34               0x3022
+#define WM8915_WRITE_SEQUENCER_35               0x3023
+#define WM8915_WRITE_SEQUENCER_36               0x3024
+#define WM8915_WRITE_SEQUENCER_37               0x3025
+#define WM8915_WRITE_SEQUENCER_38               0x3026
+#define WM8915_WRITE_SEQUENCER_39               0x3027
+#define WM8915_WRITE_SEQUENCER_40               0x3028
+#define WM8915_WRITE_SEQUENCER_41               0x3029
+#define WM8915_WRITE_SEQUENCER_42               0x302A
+#define WM8915_WRITE_SEQUENCER_43               0x302B
+#define WM8915_WRITE_SEQUENCER_44               0x302C
+#define WM8915_WRITE_SEQUENCER_45               0x302D
+#define WM8915_WRITE_SEQUENCER_46               0x302E
+#define WM8915_WRITE_SEQUENCER_47               0x302F
+#define WM8915_WRITE_SEQUENCER_48               0x3030
+#define WM8915_WRITE_SEQUENCER_49               0x3031
+#define WM8915_WRITE_SEQUENCER_50               0x3032
+#define WM8915_WRITE_SEQUENCER_51               0x3033
+#define WM8915_WRITE_SEQUENCER_52               0x3034
+#define WM8915_WRITE_SEQUENCER_53               0x3035
+#define WM8915_WRITE_SEQUENCER_54               0x3036
+#define WM8915_WRITE_SEQUENCER_55               0x3037
+#define WM8915_WRITE_SEQUENCER_56               0x3038
+#define WM8915_WRITE_SEQUENCER_57               0x3039
+#define WM8915_WRITE_SEQUENCER_58               0x303A
+#define WM8915_WRITE_SEQUENCER_59               0x303B
+#define WM8915_WRITE_SEQUENCER_60               0x303C
+#define WM8915_WRITE_SEQUENCER_61               0x303D
+#define WM8915_WRITE_SEQUENCER_62               0x303E
+#define WM8915_WRITE_SEQUENCER_63               0x303F
+#define WM8915_WRITE_SEQUENCER_64               0x3040
+#define WM8915_WRITE_SEQUENCER_65               0x3041
+#define WM8915_WRITE_SEQUENCER_66               0x3042
+#define WM8915_WRITE_SEQUENCER_67               0x3043
+#define WM8915_WRITE_SEQUENCER_68               0x3044
+#define WM8915_WRITE_SEQUENCER_69               0x3045
+#define WM8915_WRITE_SEQUENCER_70               0x3046
+#define WM8915_WRITE_SEQUENCER_71               0x3047
+#define WM8915_WRITE_SEQUENCER_72               0x3048
+#define WM8915_WRITE_SEQUENCER_73               0x3049
+#define WM8915_WRITE_SEQUENCER_74               0x304A
+#define WM8915_WRITE_SEQUENCER_75               0x304B
+#define WM8915_WRITE_SEQUENCER_76               0x304C
+#define WM8915_WRITE_SEQUENCER_77               0x304D
+#define WM8915_WRITE_SEQUENCER_78               0x304E
+#define WM8915_WRITE_SEQUENCER_79               0x304F
+#define WM8915_WRITE_SEQUENCER_80               0x3050
+#define WM8915_WRITE_SEQUENCER_81               0x3051
+#define WM8915_WRITE_SEQUENCER_82               0x3052
+#define WM8915_WRITE_SEQUENCER_83               0x3053
+#define WM8915_WRITE_SEQUENCER_84               0x3054
+#define WM8915_WRITE_SEQUENCER_85               0x3055
+#define WM8915_WRITE_SEQUENCER_86               0x3056
+#define WM8915_WRITE_SEQUENCER_87               0x3057
+#define WM8915_WRITE_SEQUENCER_88               0x3058
+#define WM8915_WRITE_SEQUENCER_89               0x3059
+#define WM8915_WRITE_SEQUENCER_90               0x305A
+#define WM8915_WRITE_SEQUENCER_91               0x305B
+#define WM8915_WRITE_SEQUENCER_92               0x305C
+#define WM8915_WRITE_SEQUENCER_93               0x305D
+#define WM8915_WRITE_SEQUENCER_94               0x305E
+#define WM8915_WRITE_SEQUENCER_95               0x305F
+#define WM8915_WRITE_SEQUENCER_96               0x3060
+#define WM8915_WRITE_SEQUENCER_97               0x3061
+#define WM8915_WRITE_SEQUENCER_98               0x3062
+#define WM8915_WRITE_SEQUENCER_99               0x3063
+#define WM8915_WRITE_SEQUENCER_100              0x3064
+#define WM8915_WRITE_SEQUENCER_101              0x3065
+#define WM8915_WRITE_SEQUENCER_102              0x3066
+#define WM8915_WRITE_SEQUENCER_103              0x3067
+#define WM8915_WRITE_SEQUENCER_104              0x3068
+#define WM8915_WRITE_SEQUENCER_105              0x3069
+#define WM8915_WRITE_SEQUENCER_106              0x306A
+#define WM8915_WRITE_SEQUENCER_107              0x306B
+#define WM8915_WRITE_SEQUENCER_108              0x306C
+#define WM8915_WRITE_SEQUENCER_109              0x306D
+#define WM8915_WRITE_SEQUENCER_110              0x306E
+#define WM8915_WRITE_SEQUENCER_111              0x306F
+#define WM8915_WRITE_SEQUENCER_112              0x3070
+#define WM8915_WRITE_SEQUENCER_113              0x3071
+#define WM8915_WRITE_SEQUENCER_114              0x3072
+#define WM8915_WRITE_SEQUENCER_115              0x3073
+#define WM8915_WRITE_SEQUENCER_116              0x3074
+#define WM8915_WRITE_SEQUENCER_117              0x3075
+#define WM8915_WRITE_SEQUENCER_118              0x3076
+#define WM8915_WRITE_SEQUENCER_119              0x3077
+#define WM8915_WRITE_SEQUENCER_120              0x3078
+#define WM8915_WRITE_SEQUENCER_121              0x3079
+#define WM8915_WRITE_SEQUENCER_122              0x307A
+#define WM8915_WRITE_SEQUENCER_123              0x307B
+#define WM8915_WRITE_SEQUENCER_124              0x307C
+#define WM8915_WRITE_SEQUENCER_125              0x307D
+#define WM8915_WRITE_SEQUENCER_126              0x307E
+#define WM8915_WRITE_SEQUENCER_127              0x307F
+#define WM8915_WRITE_SEQUENCER_128              0x3080
+#define WM8915_WRITE_SEQUENCER_129              0x3081
+#define WM8915_WRITE_SEQUENCER_130              0x3082
+#define WM8915_WRITE_SEQUENCER_131              0x3083
+#define WM8915_WRITE_SEQUENCER_132              0x3084
+#define WM8915_WRITE_SEQUENCER_133              0x3085
+#define WM8915_WRITE_SEQUENCER_134              0x3086
+#define WM8915_WRITE_SEQUENCER_135              0x3087
+#define WM8915_WRITE_SEQUENCER_136              0x3088
+#define WM8915_WRITE_SEQUENCER_137              0x3089
+#define WM8915_WRITE_SEQUENCER_138              0x308A
+#define WM8915_WRITE_SEQUENCER_139              0x308B
+#define WM8915_WRITE_SEQUENCER_140              0x308C
+#define WM8915_WRITE_SEQUENCER_141              0x308D
+#define WM8915_WRITE_SEQUENCER_142              0x308E
+#define WM8915_WRITE_SEQUENCER_143              0x308F
+#define WM8915_WRITE_SEQUENCER_144              0x3090
+#define WM8915_WRITE_SEQUENCER_145              0x3091
+#define WM8915_WRITE_SEQUENCER_146              0x3092
+#define WM8915_WRITE_SEQUENCER_147              0x3093
+#define WM8915_WRITE_SEQUENCER_148              0x3094
+#define WM8915_WRITE_SEQUENCER_149              0x3095
+#define WM8915_WRITE_SEQUENCER_150              0x3096
+#define WM8915_WRITE_SEQUENCER_151              0x3097
+#define WM8915_WRITE_SEQUENCER_152              0x3098
+#define WM8915_WRITE_SEQUENCER_153              0x3099
+#define WM8915_WRITE_SEQUENCER_154              0x309A
+#define WM8915_WRITE_SEQUENCER_155              0x309B
+#define WM8915_WRITE_SEQUENCER_156              0x309C
+#define WM8915_WRITE_SEQUENCER_157              0x309D
+#define WM8915_WRITE_SEQUENCER_158              0x309E
+#define WM8915_WRITE_SEQUENCER_159              0x309F
+#define WM8915_WRITE_SEQUENCER_160              0x30A0
+#define WM8915_WRITE_SEQUENCER_161              0x30A1
+#define WM8915_WRITE_SEQUENCER_162              0x30A2
+#define WM8915_WRITE_SEQUENCER_163              0x30A3
+#define WM8915_WRITE_SEQUENCER_164              0x30A4
+#define WM8915_WRITE_SEQUENCER_165              0x30A5
+#define WM8915_WRITE_SEQUENCER_166              0x30A6
+#define WM8915_WRITE_SEQUENCER_167              0x30A7
+#define WM8915_WRITE_SEQUENCER_168              0x30A8
+#define WM8915_WRITE_SEQUENCER_169              0x30A9
+#define WM8915_WRITE_SEQUENCER_170              0x30AA
+#define WM8915_WRITE_SEQUENCER_171              0x30AB
+#define WM8915_WRITE_SEQUENCER_172              0x30AC
+#define WM8915_WRITE_SEQUENCER_173              0x30AD
+#define WM8915_WRITE_SEQUENCER_174              0x30AE
+#define WM8915_WRITE_SEQUENCER_175              0x30AF
+#define WM8915_WRITE_SEQUENCER_176              0x30B0
+#define WM8915_WRITE_SEQUENCER_177              0x30B1
+#define WM8915_WRITE_SEQUENCER_178              0x30B2
+#define WM8915_WRITE_SEQUENCER_179              0x30B3
+#define WM8915_WRITE_SEQUENCER_180              0x30B4
+#define WM8915_WRITE_SEQUENCER_181              0x30B5
+#define WM8915_WRITE_SEQUENCER_182              0x30B6
+#define WM8915_WRITE_SEQUENCER_183              0x30B7
+#define WM8915_WRITE_SEQUENCER_184              0x30B8
+#define WM8915_WRITE_SEQUENCER_185              0x30B9
+#define WM8915_WRITE_SEQUENCER_186              0x30BA
+#define WM8915_WRITE_SEQUENCER_187              0x30BB
+#define WM8915_WRITE_SEQUENCER_188              0x30BC
+#define WM8915_WRITE_SEQUENCER_189              0x30BD
+#define WM8915_WRITE_SEQUENCER_190              0x30BE
+#define WM8915_WRITE_SEQUENCER_191              0x30BF
+#define WM8915_WRITE_SEQUENCER_192              0x30C0
+#define WM8915_WRITE_SEQUENCER_193              0x30C1
+#define WM8915_WRITE_SEQUENCER_194              0x30C2
+#define WM8915_WRITE_SEQUENCER_195              0x30C3
+#define WM8915_WRITE_SEQUENCER_196              0x30C4
+#define WM8915_WRITE_SEQUENCER_197              0x30C5
+#define WM8915_WRITE_SEQUENCER_198              0x30C6
+#define WM8915_WRITE_SEQUENCER_199              0x30C7
+#define WM8915_WRITE_SEQUENCER_200              0x30C8
+#define WM8915_WRITE_SEQUENCER_201              0x30C9
+#define WM8915_WRITE_SEQUENCER_202              0x30CA
+#define WM8915_WRITE_SEQUENCER_203              0x30CB
+#define WM8915_WRITE_SEQUENCER_204              0x30CC
+#define WM8915_WRITE_SEQUENCER_205              0x30CD
+#define WM8915_WRITE_SEQUENCER_206              0x30CE
+#define WM8915_WRITE_SEQUENCER_207              0x30CF
+#define WM8915_WRITE_SEQUENCER_208              0x30D0
+#define WM8915_WRITE_SEQUENCER_209              0x30D1
+#define WM8915_WRITE_SEQUENCER_210              0x30D2
+#define WM8915_WRITE_SEQUENCER_211              0x30D3
+#define WM8915_WRITE_SEQUENCER_212              0x30D4
+#define WM8915_WRITE_SEQUENCER_213              0x30D5
+#define WM8915_WRITE_SEQUENCER_214              0x30D6
+#define WM8915_WRITE_SEQUENCER_215              0x30D7
+#define WM8915_WRITE_SEQUENCER_216              0x30D8
+#define WM8915_WRITE_SEQUENCER_217              0x30D9
+#define WM8915_WRITE_SEQUENCER_218              0x30DA
+#define WM8915_WRITE_SEQUENCER_219              0x30DB
+#define WM8915_WRITE_SEQUENCER_220              0x30DC
+#define WM8915_WRITE_SEQUENCER_221              0x30DD
+#define WM8915_WRITE_SEQUENCER_222              0x30DE
+#define WM8915_WRITE_SEQUENCER_223              0x30DF
+#define WM8915_WRITE_SEQUENCER_224              0x30E0
+#define WM8915_WRITE_SEQUENCER_225              0x30E1
+#define WM8915_WRITE_SEQUENCER_226              0x30E2
+#define WM8915_WRITE_SEQUENCER_227              0x30E3
+#define WM8915_WRITE_SEQUENCER_228              0x30E4
+#define WM8915_WRITE_SEQUENCER_229              0x30E5
+#define WM8915_WRITE_SEQUENCER_230              0x30E6
+#define WM8915_WRITE_SEQUENCER_231              0x30E7
+#define WM8915_WRITE_SEQUENCER_232              0x30E8
+#define WM8915_WRITE_SEQUENCER_233              0x30E9
+#define WM8915_WRITE_SEQUENCER_234              0x30EA
+#define WM8915_WRITE_SEQUENCER_235              0x30EB
+#define WM8915_WRITE_SEQUENCER_236              0x30EC
+#define WM8915_WRITE_SEQUENCER_237              0x30ED
+#define WM8915_WRITE_SEQUENCER_238              0x30EE
+#define WM8915_WRITE_SEQUENCER_239              0x30EF
+#define WM8915_WRITE_SEQUENCER_240              0x30F0
+#define WM8915_WRITE_SEQUENCER_241              0x30F1
+#define WM8915_WRITE_SEQUENCER_242              0x30F2
+#define WM8915_WRITE_SEQUENCER_243              0x30F3
+#define WM8915_WRITE_SEQUENCER_244              0x30F4
+#define WM8915_WRITE_SEQUENCER_245              0x30F5
+#define WM8915_WRITE_SEQUENCER_246              0x30F6
+#define WM8915_WRITE_SEQUENCER_247              0x30F7
+#define WM8915_WRITE_SEQUENCER_248              0x30F8
+#define WM8915_WRITE_SEQUENCER_249              0x30F9
+#define WM8915_WRITE_SEQUENCER_250              0x30FA
+#define WM8915_WRITE_SEQUENCER_251              0x30FB
+#define WM8915_WRITE_SEQUENCER_252              0x30FC
+#define WM8915_WRITE_SEQUENCER_253              0x30FD
+#define WM8915_WRITE_SEQUENCER_254              0x30FE
+#define WM8915_WRITE_SEQUENCER_255              0x30FF
+#define WM8915_WRITE_SEQUENCER_256              0x3100
+#define WM8915_WRITE_SEQUENCER_257              0x3101
+#define WM8915_WRITE_SEQUENCER_258              0x3102
+#define WM8915_WRITE_SEQUENCER_259              0x3103
+#define WM8915_WRITE_SEQUENCER_260              0x3104
+#define WM8915_WRITE_SEQUENCER_261              0x3105
+#define WM8915_WRITE_SEQUENCER_262              0x3106
+#define WM8915_WRITE_SEQUENCER_263              0x3107
+#define WM8915_WRITE_SEQUENCER_264              0x3108
+#define WM8915_WRITE_SEQUENCER_265              0x3109
+#define WM8915_WRITE_SEQUENCER_266              0x310A
+#define WM8915_WRITE_SEQUENCER_267              0x310B
+#define WM8915_WRITE_SEQUENCER_268              0x310C
+#define WM8915_WRITE_SEQUENCER_269              0x310D
+#define WM8915_WRITE_SEQUENCER_270              0x310E
+#define WM8915_WRITE_SEQUENCER_271              0x310F
+#define WM8915_WRITE_SEQUENCER_272              0x3110
+#define WM8915_WRITE_SEQUENCER_273              0x3111
+#define WM8915_WRITE_SEQUENCER_274              0x3112
+#define WM8915_WRITE_SEQUENCER_275              0x3113
+#define WM8915_WRITE_SEQUENCER_276              0x3114
+#define WM8915_WRITE_SEQUENCER_277              0x3115
+#define WM8915_WRITE_SEQUENCER_278              0x3116
+#define WM8915_WRITE_SEQUENCER_279              0x3117
+#define WM8915_WRITE_SEQUENCER_280              0x3118
+#define WM8915_WRITE_SEQUENCER_281              0x3119
+#define WM8915_WRITE_SEQUENCER_282              0x311A
+#define WM8915_WRITE_SEQUENCER_283              0x311B
+#define WM8915_WRITE_SEQUENCER_284              0x311C
+#define WM8915_WRITE_SEQUENCER_285              0x311D
+#define WM8915_WRITE_SEQUENCER_286              0x311E
+#define WM8915_WRITE_SEQUENCER_287              0x311F
+#define WM8915_WRITE_SEQUENCER_288              0x3120
+#define WM8915_WRITE_SEQUENCER_289              0x3121
+#define WM8915_WRITE_SEQUENCER_290              0x3122
+#define WM8915_WRITE_SEQUENCER_291              0x3123
+#define WM8915_WRITE_SEQUENCER_292              0x3124
+#define WM8915_WRITE_SEQUENCER_293              0x3125
+#define WM8915_WRITE_SEQUENCER_294              0x3126
+#define WM8915_WRITE_SEQUENCER_295              0x3127
+#define WM8915_WRITE_SEQUENCER_296              0x3128
+#define WM8915_WRITE_SEQUENCER_297              0x3129
+#define WM8915_WRITE_SEQUENCER_298              0x312A
+#define WM8915_WRITE_SEQUENCER_299              0x312B
+#define WM8915_WRITE_SEQUENCER_300              0x312C
+#define WM8915_WRITE_SEQUENCER_301              0x312D
+#define WM8915_WRITE_SEQUENCER_302              0x312E
+#define WM8915_WRITE_SEQUENCER_303              0x312F
+#define WM8915_WRITE_SEQUENCER_304              0x3130
+#define WM8915_WRITE_SEQUENCER_305              0x3131
+#define WM8915_WRITE_SEQUENCER_306              0x3132
+#define WM8915_WRITE_SEQUENCER_307              0x3133
+#define WM8915_WRITE_SEQUENCER_308              0x3134
+#define WM8915_WRITE_SEQUENCER_309              0x3135
+#define WM8915_WRITE_SEQUENCER_310              0x3136
+#define WM8915_WRITE_SEQUENCER_311              0x3137
+#define WM8915_WRITE_SEQUENCER_312              0x3138
+#define WM8915_WRITE_SEQUENCER_313              0x3139
+#define WM8915_WRITE_SEQUENCER_314              0x313A
+#define WM8915_WRITE_SEQUENCER_315              0x313B
+#define WM8915_WRITE_SEQUENCER_316              0x313C
+#define WM8915_WRITE_SEQUENCER_317              0x313D
+#define WM8915_WRITE_SEQUENCER_318              0x313E
+#define WM8915_WRITE_SEQUENCER_319              0x313F
+#define WM8915_WRITE_SEQUENCER_320              0x3140
+#define WM8915_WRITE_SEQUENCER_321              0x3141
+#define WM8915_WRITE_SEQUENCER_322              0x3142
+#define WM8915_WRITE_SEQUENCER_323              0x3143
+#define WM8915_WRITE_SEQUENCER_324              0x3144
+#define WM8915_WRITE_SEQUENCER_325              0x3145
+#define WM8915_WRITE_SEQUENCER_326              0x3146
+#define WM8915_WRITE_SEQUENCER_327              0x3147
+#define WM8915_WRITE_SEQUENCER_328              0x3148
+#define WM8915_WRITE_SEQUENCER_329              0x3149
+#define WM8915_WRITE_SEQUENCER_330              0x314A
+#define WM8915_WRITE_SEQUENCER_331              0x314B
+#define WM8915_WRITE_SEQUENCER_332              0x314C
+#define WM8915_WRITE_SEQUENCER_333              0x314D
+#define WM8915_WRITE_SEQUENCER_334              0x314E
+#define WM8915_WRITE_SEQUENCER_335              0x314F
+#define WM8915_WRITE_SEQUENCER_336              0x3150
+#define WM8915_WRITE_SEQUENCER_337              0x3151
+#define WM8915_WRITE_SEQUENCER_338              0x3152
+#define WM8915_WRITE_SEQUENCER_339              0x3153
+#define WM8915_WRITE_SEQUENCER_340              0x3154
+#define WM8915_WRITE_SEQUENCER_341              0x3155
+#define WM8915_WRITE_SEQUENCER_342              0x3156
+#define WM8915_WRITE_SEQUENCER_343              0x3157
+#define WM8915_WRITE_SEQUENCER_344              0x3158
+#define WM8915_WRITE_SEQUENCER_345              0x3159
+#define WM8915_WRITE_SEQUENCER_346              0x315A
+#define WM8915_WRITE_SEQUENCER_347              0x315B
+#define WM8915_WRITE_SEQUENCER_348              0x315C
+#define WM8915_WRITE_SEQUENCER_349              0x315D
+#define WM8915_WRITE_SEQUENCER_350              0x315E
+#define WM8915_WRITE_SEQUENCER_351              0x315F
+#define WM8915_WRITE_SEQUENCER_352              0x3160
+#define WM8915_WRITE_SEQUENCER_353              0x3161
+#define WM8915_WRITE_SEQUENCER_354              0x3162
+#define WM8915_WRITE_SEQUENCER_355              0x3163
+#define WM8915_WRITE_SEQUENCER_356              0x3164
+#define WM8915_WRITE_SEQUENCER_357              0x3165
+#define WM8915_WRITE_SEQUENCER_358              0x3166
+#define WM8915_WRITE_SEQUENCER_359              0x3167
+#define WM8915_WRITE_SEQUENCER_360              0x3168
+#define WM8915_WRITE_SEQUENCER_361              0x3169
+#define WM8915_WRITE_SEQUENCER_362              0x316A
+#define WM8915_WRITE_SEQUENCER_363              0x316B
+#define WM8915_WRITE_SEQUENCER_364              0x316C
+#define WM8915_WRITE_SEQUENCER_365              0x316D
+#define WM8915_WRITE_SEQUENCER_366              0x316E
+#define WM8915_WRITE_SEQUENCER_367              0x316F
+#define WM8915_WRITE_SEQUENCER_368              0x3170
+#define WM8915_WRITE_SEQUENCER_369              0x3171
+#define WM8915_WRITE_SEQUENCER_370              0x3172
+#define WM8915_WRITE_SEQUENCER_371              0x3173
+#define WM8915_WRITE_SEQUENCER_372              0x3174
+#define WM8915_WRITE_SEQUENCER_373              0x3175
+#define WM8915_WRITE_SEQUENCER_374              0x3176
+#define WM8915_WRITE_SEQUENCER_375              0x3177
+#define WM8915_WRITE_SEQUENCER_376              0x3178
+#define WM8915_WRITE_SEQUENCER_377              0x3179
+#define WM8915_WRITE_SEQUENCER_378              0x317A
+#define WM8915_WRITE_SEQUENCER_379              0x317B
+#define WM8915_WRITE_SEQUENCER_380              0x317C
+#define WM8915_WRITE_SEQUENCER_381              0x317D
+#define WM8915_WRITE_SEQUENCER_382              0x317E
+#define WM8915_WRITE_SEQUENCER_383              0x317F
+#define WM8915_WRITE_SEQUENCER_384              0x3180
+#define WM8915_WRITE_SEQUENCER_385              0x3181
+#define WM8915_WRITE_SEQUENCER_386              0x3182
+#define WM8915_WRITE_SEQUENCER_387              0x3183
+#define WM8915_WRITE_SEQUENCER_388              0x3184
+#define WM8915_WRITE_SEQUENCER_389              0x3185
+#define WM8915_WRITE_SEQUENCER_390              0x3186
+#define WM8915_WRITE_SEQUENCER_391              0x3187
+#define WM8915_WRITE_SEQUENCER_392              0x3188
+#define WM8915_WRITE_SEQUENCER_393              0x3189
+#define WM8915_WRITE_SEQUENCER_394              0x318A
+#define WM8915_WRITE_SEQUENCER_395              0x318B
+#define WM8915_WRITE_SEQUENCER_396              0x318C
+#define WM8915_WRITE_SEQUENCER_397              0x318D
+#define WM8915_WRITE_SEQUENCER_398              0x318E
+#define WM8915_WRITE_SEQUENCER_399              0x318F
+#define WM8915_WRITE_SEQUENCER_400              0x3190
+#define WM8915_WRITE_SEQUENCER_401              0x3191
+#define WM8915_WRITE_SEQUENCER_402              0x3192
+#define WM8915_WRITE_SEQUENCER_403              0x3193
+#define WM8915_WRITE_SEQUENCER_404              0x3194
+#define WM8915_WRITE_SEQUENCER_405              0x3195
+#define WM8915_WRITE_SEQUENCER_406              0x3196
+#define WM8915_WRITE_SEQUENCER_407              0x3197
+#define WM8915_WRITE_SEQUENCER_408              0x3198
+#define WM8915_WRITE_SEQUENCER_409              0x3199
+#define WM8915_WRITE_SEQUENCER_410              0x319A
+#define WM8915_WRITE_SEQUENCER_411              0x319B
+#define WM8915_WRITE_SEQUENCER_412              0x319C
+#define WM8915_WRITE_SEQUENCER_413              0x319D
+#define WM8915_WRITE_SEQUENCER_414              0x319E
+#define WM8915_WRITE_SEQUENCER_415              0x319F
+#define WM8915_WRITE_SEQUENCER_416              0x31A0
+#define WM8915_WRITE_SEQUENCER_417              0x31A1
+#define WM8915_WRITE_SEQUENCER_418              0x31A2
+#define WM8915_WRITE_SEQUENCER_419              0x31A3
+#define WM8915_WRITE_SEQUENCER_420              0x31A4
+#define WM8915_WRITE_SEQUENCER_421              0x31A5
+#define WM8915_WRITE_SEQUENCER_422              0x31A6
+#define WM8915_WRITE_SEQUENCER_423              0x31A7
+#define WM8915_WRITE_SEQUENCER_424              0x31A8
+#define WM8915_WRITE_SEQUENCER_425              0x31A9
+#define WM8915_WRITE_SEQUENCER_426              0x31AA
+#define WM8915_WRITE_SEQUENCER_427              0x31AB
+#define WM8915_WRITE_SEQUENCER_428              0x31AC
+#define WM8915_WRITE_SEQUENCER_429              0x31AD
+#define WM8915_WRITE_SEQUENCER_430              0x31AE
+#define WM8915_WRITE_SEQUENCER_431              0x31AF
+#define WM8915_WRITE_SEQUENCER_432              0x31B0
+#define WM8915_WRITE_SEQUENCER_433              0x31B1
+#define WM8915_WRITE_SEQUENCER_434              0x31B2
+#define WM8915_WRITE_SEQUENCER_435              0x31B3
+#define WM8915_WRITE_SEQUENCER_436              0x31B4
+#define WM8915_WRITE_SEQUENCER_437              0x31B5
+#define WM8915_WRITE_SEQUENCER_438              0x31B6
+#define WM8915_WRITE_SEQUENCER_439              0x31B7
+#define WM8915_WRITE_SEQUENCER_440              0x31B8
+#define WM8915_WRITE_SEQUENCER_441              0x31B9
+#define WM8915_WRITE_SEQUENCER_442              0x31BA
+#define WM8915_WRITE_SEQUENCER_443              0x31BB
+#define WM8915_WRITE_SEQUENCER_444              0x31BC
+#define WM8915_WRITE_SEQUENCER_445              0x31BD
+#define WM8915_WRITE_SEQUENCER_446              0x31BE
+#define WM8915_WRITE_SEQUENCER_447              0x31BF
+#define WM8915_WRITE_SEQUENCER_448              0x31C0
+#define WM8915_WRITE_SEQUENCER_449              0x31C1
+#define WM8915_WRITE_SEQUENCER_450              0x31C2
+#define WM8915_WRITE_SEQUENCER_451              0x31C3
+#define WM8915_WRITE_SEQUENCER_452              0x31C4
+#define WM8915_WRITE_SEQUENCER_453              0x31C5
+#define WM8915_WRITE_SEQUENCER_454              0x31C6
+#define WM8915_WRITE_SEQUENCER_455              0x31C7
+#define WM8915_WRITE_SEQUENCER_456              0x31C8
+#define WM8915_WRITE_SEQUENCER_457              0x31C9
+#define WM8915_WRITE_SEQUENCER_458              0x31CA
+#define WM8915_WRITE_SEQUENCER_459              0x31CB
+#define WM8915_WRITE_SEQUENCER_460              0x31CC
+#define WM8915_WRITE_SEQUENCER_461              0x31CD
+#define WM8915_WRITE_SEQUENCER_462              0x31CE
+#define WM8915_WRITE_SEQUENCER_463              0x31CF
+#define WM8915_WRITE_SEQUENCER_464              0x31D0
+#define WM8915_WRITE_SEQUENCER_465              0x31D1
+#define WM8915_WRITE_SEQUENCER_466              0x31D2
+#define WM8915_WRITE_SEQUENCER_467              0x31D3
+#define WM8915_WRITE_SEQUENCER_468              0x31D4
+#define WM8915_WRITE_SEQUENCER_469              0x31D5
+#define WM8915_WRITE_SEQUENCER_470              0x31D6
+#define WM8915_WRITE_SEQUENCER_471              0x31D7
+#define WM8915_WRITE_SEQUENCER_472              0x31D8
+#define WM8915_WRITE_SEQUENCER_473              0x31D9
+#define WM8915_WRITE_SEQUENCER_474              0x31DA
+#define WM8915_WRITE_SEQUENCER_475              0x31DB
+#define WM8915_WRITE_SEQUENCER_476              0x31DC
+#define WM8915_WRITE_SEQUENCER_477              0x31DD
+#define WM8915_WRITE_SEQUENCER_478              0x31DE
+#define WM8915_WRITE_SEQUENCER_479              0x31DF
+#define WM8915_WRITE_SEQUENCER_480              0x31E0
+#define WM8915_WRITE_SEQUENCER_481              0x31E1
+#define WM8915_WRITE_SEQUENCER_482              0x31E2
+#define WM8915_WRITE_SEQUENCER_483              0x31E3
+#define WM8915_WRITE_SEQUENCER_484              0x31E4
+#define WM8915_WRITE_SEQUENCER_485              0x31E5
+#define WM8915_WRITE_SEQUENCER_486              0x31E6
+#define WM8915_WRITE_SEQUENCER_487              0x31E7
+#define WM8915_WRITE_SEQUENCER_488              0x31E8
+#define WM8915_WRITE_SEQUENCER_489              0x31E9
+#define WM8915_WRITE_SEQUENCER_490              0x31EA
+#define WM8915_WRITE_SEQUENCER_491              0x31EB
+#define WM8915_WRITE_SEQUENCER_492              0x31EC
+#define WM8915_WRITE_SEQUENCER_493              0x31ED
+#define WM8915_WRITE_SEQUENCER_494              0x31EE
+#define WM8915_WRITE_SEQUENCER_495              0x31EF
+#define WM8915_WRITE_SEQUENCER_496              0x31F0
+#define WM8915_WRITE_SEQUENCER_497              0x31F1
+#define WM8915_WRITE_SEQUENCER_498              0x31F2
+#define WM8915_WRITE_SEQUENCER_499              0x31F3
+#define WM8915_WRITE_SEQUENCER_500              0x31F4
+#define WM8915_WRITE_SEQUENCER_501              0x31F5
+#define WM8915_WRITE_SEQUENCER_502              0x31F6
+#define WM8915_WRITE_SEQUENCER_503              0x31F7
+#define WM8915_WRITE_SEQUENCER_504              0x31F8
+#define WM8915_WRITE_SEQUENCER_505              0x31F9
+#define WM8915_WRITE_SEQUENCER_506              0x31FA
+#define WM8915_WRITE_SEQUENCER_507              0x31FB
+#define WM8915_WRITE_SEQUENCER_508              0x31FC
+#define WM8915_WRITE_SEQUENCER_509              0x31FD
+#define WM8915_WRITE_SEQUENCER_510              0x31FE
+#define WM8915_WRITE_SEQUENCER_511              0x31FF
+
+#define WM8915_REGISTER_COUNT                   706
+#define WM8915_MAX_REGISTER                     0x31FF
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Software Reset
+ */
+#define WM8915_SW_RESET_MASK                    0xFFFF  /* SW_RESET - [15:0] */
+#define WM8915_SW_RESET_SHIFT                        0  /* SW_RESET - [15:0] */
+#define WM8915_SW_RESET_WIDTH                       16  /* SW_RESET - [15:0] */
+
+/*
+ * R1 (0x01) - Power Management (1)
+ */
+#define WM8915_MICB2_ENA                        0x0200  /* MICB2_ENA */
+#define WM8915_MICB2_ENA_MASK                   0x0200  /* MICB2_ENA */
+#define WM8915_MICB2_ENA_SHIFT                       9  /* MICB2_ENA */
+#define WM8915_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
+#define WM8915_MICB1_ENA                        0x0100  /* MICB1_ENA */
+#define WM8915_MICB1_ENA_MASK                   0x0100  /* MICB1_ENA */
+#define WM8915_MICB1_ENA_SHIFT                       8  /* MICB1_ENA */
+#define WM8915_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
+#define WM8915_HPOUT2L_ENA                      0x0080  /* HPOUT2L_ENA */
+#define WM8915_HPOUT2L_ENA_MASK                 0x0080  /* HPOUT2L_ENA */
+#define WM8915_HPOUT2L_ENA_SHIFT                     7  /* HPOUT2L_ENA */
+#define WM8915_HPOUT2L_ENA_WIDTH                     1  /* HPOUT2L_ENA */
+#define WM8915_HPOUT2R_ENA                      0x0040  /* HPOUT2R_ENA */
+#define WM8915_HPOUT2R_ENA_MASK                 0x0040  /* HPOUT2R_ENA */
+#define WM8915_HPOUT2R_ENA_SHIFT                     6  /* HPOUT2R_ENA */
+#define WM8915_HPOUT2R_ENA_WIDTH                     1  /* HPOUT2R_ENA */
+#define WM8915_HPOUT1L_ENA                      0x0020  /* HPOUT1L_ENA */
+#define WM8915_HPOUT1L_ENA_MASK                 0x0020  /* HPOUT1L_ENA */
+#define WM8915_HPOUT1L_ENA_SHIFT                     5  /* HPOUT1L_ENA */
+#define WM8915_HPOUT1L_ENA_WIDTH                     1  /* HPOUT1L_ENA */
+#define WM8915_HPOUT1R_ENA                      0x0010  /* HPOUT1R_ENA */
+#define WM8915_HPOUT1R_ENA_MASK                 0x0010  /* HPOUT1R_ENA */
+#define WM8915_HPOUT1R_ENA_SHIFT                     4  /* HPOUT1R_ENA */
+#define WM8915_HPOUT1R_ENA_WIDTH                     1  /* HPOUT1R_ENA */
+#define WM8915_BG_ENA                           0x0001  /* BG_ENA */
+#define WM8915_BG_ENA_MASK                      0x0001  /* BG_ENA */
+#define WM8915_BG_ENA_SHIFT                          0  /* BG_ENA */
+#define WM8915_BG_ENA_WIDTH                          1  /* BG_ENA */
+
+/*
+ * R2 (0x02) - Power Management (2)
+ */
+#define WM8915_OPCLK_ENA                        0x0800  /* OPCLK_ENA */
+#define WM8915_OPCLK_ENA_MASK                   0x0800  /* OPCLK_ENA */
+#define WM8915_OPCLK_ENA_SHIFT                      11  /* OPCLK_ENA */
+#define WM8915_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
+#define WM8915_INL_ENA                          0x0020  /* INL_ENA */
+#define WM8915_INL_ENA_MASK                     0x0020  /* INL_ENA */
+#define WM8915_INL_ENA_SHIFT                         5  /* INL_ENA */
+#define WM8915_INL_ENA_WIDTH                         1  /* INL_ENA */
+#define WM8915_INR_ENA                          0x0010  /* INR_ENA */
+#define WM8915_INR_ENA_MASK                     0x0010  /* INR_ENA */
+#define WM8915_INR_ENA_SHIFT                         4  /* INR_ENA */
+#define WM8915_INR_ENA_WIDTH                         1  /* INR_ENA */
+#define WM8915_LDO2_ENA                         0x0002  /* LDO2_ENA */
+#define WM8915_LDO2_ENA_MASK                    0x0002  /* LDO2_ENA */
+#define WM8915_LDO2_ENA_SHIFT                        1  /* LDO2_ENA */
+#define WM8915_LDO2_ENA_WIDTH                        1  /* LDO2_ENA */
+
+/*
+ * R3 (0x03) - Power Management (3)
+ */
+#define WM8915_DSP2RXL_ENA                      0x0800  /* DSP2RXL_ENA */
+#define WM8915_DSP2RXL_ENA_MASK                 0x0800  /* DSP2RXL_ENA */
+#define WM8915_DSP2RXL_ENA_SHIFT                    11  /* DSP2RXL_ENA */
+#define WM8915_DSP2RXL_ENA_WIDTH                     1  /* DSP2RXL_ENA */
+#define WM8915_DSP2RXR_ENA                      0x0400  /* DSP2RXR_ENA */
+#define WM8915_DSP2RXR_ENA_MASK                 0x0400  /* DSP2RXR_ENA */
+#define WM8915_DSP2RXR_ENA_SHIFT                    10  /* DSP2RXR_ENA */
+#define WM8915_DSP2RXR_ENA_WIDTH                     1  /* DSP2RXR_ENA */
+#define WM8915_DSP1RXL_ENA                      0x0200  /* DSP1RXL_ENA */
+#define WM8915_DSP1RXL_ENA_MASK                 0x0200  /* DSP1RXL_ENA */
+#define WM8915_DSP1RXL_ENA_SHIFT                     9  /* DSP1RXL_ENA */
+#define WM8915_DSP1RXL_ENA_WIDTH                     1  /* DSP1RXL_ENA */
+#define WM8915_DSP1RXR_ENA                      0x0100  /* DSP1RXR_ENA */
+#define WM8915_DSP1RXR_ENA_MASK                 0x0100  /* DSP1RXR_ENA */
+#define WM8915_DSP1RXR_ENA_SHIFT                     8  /* DSP1RXR_ENA */
+#define WM8915_DSP1RXR_ENA_WIDTH                     1  /* DSP1RXR_ENA */
+#define WM8915_DMIC2L_ENA                       0x0020  /* DMIC2L_ENA */
+#define WM8915_DMIC2L_ENA_MASK                  0x0020  /* DMIC2L_ENA */
+#define WM8915_DMIC2L_ENA_SHIFT                      5  /* DMIC2L_ENA */
+#define WM8915_DMIC2L_ENA_WIDTH                      1  /* DMIC2L_ENA */
+#define WM8915_DMIC2R_ENA                       0x0010  /* DMIC2R_ENA */
+#define WM8915_DMIC2R_ENA_MASK                  0x0010  /* DMIC2R_ENA */
+#define WM8915_DMIC2R_ENA_SHIFT                      4  /* DMIC2R_ENA */
+#define WM8915_DMIC2R_ENA_WIDTH                      1  /* DMIC2R_ENA */
+#define WM8915_DMIC1L_ENA                       0x0008  /* DMIC1L_ENA */
+#define WM8915_DMIC1L_ENA_MASK                  0x0008  /* DMIC1L_ENA */
+#define WM8915_DMIC1L_ENA_SHIFT                      3  /* DMIC1L_ENA */
+#define WM8915_DMIC1L_ENA_WIDTH                      1  /* DMIC1L_ENA */
+#define WM8915_DMIC1R_ENA                       0x0004  /* DMIC1R_ENA */
+#define WM8915_DMIC1R_ENA_MASK                  0x0004  /* DMIC1R_ENA */
+#define WM8915_DMIC1R_ENA_SHIFT                      2  /* DMIC1R_ENA */
+#define WM8915_DMIC1R_ENA_WIDTH                      1  /* DMIC1R_ENA */
+#define WM8915_ADCL_ENA                         0x0002  /* ADCL_ENA */
+#define WM8915_ADCL_ENA_MASK                    0x0002  /* ADCL_ENA */
+#define WM8915_ADCL_ENA_SHIFT                        1  /* ADCL_ENA */
+#define WM8915_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
+#define WM8915_ADCR_ENA                         0x0001  /* ADCR_ENA */
+#define WM8915_ADCR_ENA_MASK                    0x0001  /* ADCR_ENA */
+#define WM8915_ADCR_ENA_SHIFT                        0  /* ADCR_ENA */
+#define WM8915_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
+
+/*
+ * R4 (0x04) - Power Management (4)
+ */
+#define WM8915_AIF2RX_CHAN1_ENA                 0x0200  /* AIF2RX_CHAN1_ENA */
+#define WM8915_AIF2RX_CHAN1_ENA_MASK            0x0200  /* AIF2RX_CHAN1_ENA */
+#define WM8915_AIF2RX_CHAN1_ENA_SHIFT                9  /* AIF2RX_CHAN1_ENA */
+#define WM8915_AIF2RX_CHAN1_ENA_WIDTH                1  /* AIF2RX_CHAN1_ENA */
+#define WM8915_AIF2RX_CHAN0_ENA                 0x0100  /* AIF2RX_CHAN0_ENA */
+#define WM8915_AIF2RX_CHAN0_ENA_MASK            0x0100  /* AIF2RX_CHAN0_ENA */
+#define WM8915_AIF2RX_CHAN0_ENA_SHIFT                8  /* AIF2RX_CHAN0_ENA */
+#define WM8915_AIF2RX_CHAN0_ENA_WIDTH                1  /* AIF2RX_CHAN0_ENA */
+#define WM8915_AIF1RX_CHAN5_ENA                 0x0020  /* AIF1RX_CHAN5_ENA */
+#define WM8915_AIF1RX_CHAN5_ENA_MASK            0x0020  /* AIF1RX_CHAN5_ENA */
+#define WM8915_AIF1RX_CHAN5_ENA_SHIFT                5  /* AIF1RX_CHAN5_ENA */
+#define WM8915_AIF1RX_CHAN5_ENA_WIDTH                1  /* AIF1RX_CHAN5_ENA */
+#define WM8915_AIF1RX_CHAN4_ENA                 0x0010  /* AIF1RX_CHAN4_ENA */
+#define WM8915_AIF1RX_CHAN4_ENA_MASK            0x0010  /* AIF1RX_CHAN4_ENA */
+#define WM8915_AIF1RX_CHAN4_ENA_SHIFT                4  /* AIF1RX_CHAN4_ENA */
+#define WM8915_AIF1RX_CHAN4_ENA_WIDTH                1  /* AIF1RX_CHAN4_ENA */
+#define WM8915_AIF1RX_CHAN3_ENA                 0x0008  /* AIF1RX_CHAN3_ENA */
+#define WM8915_AIF1RX_CHAN3_ENA_MASK            0x0008  /* AIF1RX_CHAN3_ENA */
+#define WM8915_AIF1RX_CHAN3_ENA_SHIFT                3  /* AIF1RX_CHAN3_ENA */
+#define WM8915_AIF1RX_CHAN3_ENA_WIDTH                1  /* AIF1RX_CHAN3_ENA */
+#define WM8915_AIF1RX_CHAN2_ENA                 0x0004  /* AIF1RX_CHAN2_ENA */
+#define WM8915_AIF1RX_CHAN2_ENA_MASK            0x0004  /* AIF1RX_CHAN2_ENA */
+#define WM8915_AIF1RX_CHAN2_ENA_SHIFT                2  /* AIF1RX_CHAN2_ENA */
+#define WM8915_AIF1RX_CHAN2_ENA_WIDTH                1  /* AIF1RX_CHAN2_ENA */
+#define WM8915_AIF1RX_CHAN1_ENA                 0x0002  /* AIF1RX_CHAN1_ENA */
+#define WM8915_AIF1RX_CHAN1_ENA_MASK            0x0002  /* AIF1RX_CHAN1_ENA */
+#define WM8915_AIF1RX_CHAN1_ENA_SHIFT                1  /* AIF1RX_CHAN1_ENA */
+#define WM8915_AIF1RX_CHAN1_ENA_WIDTH                1  /* AIF1RX_CHAN1_ENA */
+#define WM8915_AIF1RX_CHAN0_ENA                 0x0001  /* AIF1RX_CHAN0_ENA */
+#define WM8915_AIF1RX_CHAN0_ENA_MASK            0x0001  /* AIF1RX_CHAN0_ENA */
+#define WM8915_AIF1RX_CHAN0_ENA_SHIFT                0  /* AIF1RX_CHAN0_ENA */
+#define WM8915_AIF1RX_CHAN0_ENA_WIDTH                1  /* AIF1RX_CHAN0_ENA */
+
+/*
+ * R5 (0x05) - Power Management (5)
+ */
+#define WM8915_DSP2TXL_ENA                      0x0800  /* DSP2TXL_ENA */
+#define WM8915_DSP2TXL_ENA_MASK                 0x0800  /* DSP2TXL_ENA */
+#define WM8915_DSP2TXL_ENA_SHIFT                    11  /* DSP2TXL_ENA */
+#define WM8915_DSP2TXL_ENA_WIDTH                     1  /* DSP2TXL_ENA */
+#define WM8915_DSP2TXR_ENA                      0x0400  /* DSP2TXR_ENA */
+#define WM8915_DSP2TXR_ENA_MASK                 0x0400  /* DSP2TXR_ENA */
+#define WM8915_DSP2TXR_ENA_SHIFT                    10  /* DSP2TXR_ENA */
+#define WM8915_DSP2TXR_ENA_WIDTH                     1  /* DSP2TXR_ENA */
+#define WM8915_DSP1TXL_ENA                      0x0200  /* DSP1TXL_ENA */
+#define WM8915_DSP1TXL_ENA_MASK                 0x0200  /* DSP1TXL_ENA */
+#define WM8915_DSP1TXL_ENA_SHIFT                     9  /* DSP1TXL_ENA */
+#define WM8915_DSP1TXL_ENA_WIDTH                     1  /* DSP1TXL_ENA */
+#define WM8915_DSP1TXR_ENA                      0x0100  /* DSP1TXR_ENA */
+#define WM8915_DSP1TXR_ENA_MASK                 0x0100  /* DSP1TXR_ENA */
+#define WM8915_DSP1TXR_ENA_SHIFT                     8  /* DSP1TXR_ENA */
+#define WM8915_DSP1TXR_ENA_WIDTH                     1  /* DSP1TXR_ENA */
+#define WM8915_DAC2L_ENA                        0x0008  /* DAC2L_ENA */
+#define WM8915_DAC2L_ENA_MASK                   0x0008  /* DAC2L_ENA */
+#define WM8915_DAC2L_ENA_SHIFT                       3  /* DAC2L_ENA */
+#define WM8915_DAC2L_ENA_WIDTH                       1  /* DAC2L_ENA */
+#define WM8915_DAC2R_ENA                        0x0004  /* DAC2R_ENA */
+#define WM8915_DAC2R_ENA_MASK                   0x0004  /* DAC2R_ENA */
+#define WM8915_DAC2R_ENA_SHIFT                       2  /* DAC2R_ENA */
+#define WM8915_DAC2R_ENA_WIDTH                       1  /* DAC2R_ENA */
+#define WM8915_DAC1L_ENA                        0x0002  /* DAC1L_ENA */
+#define WM8915_DAC1L_ENA_MASK                   0x0002  /* DAC1L_ENA */
+#define WM8915_DAC1L_ENA_SHIFT                       1  /* DAC1L_ENA */
+#define WM8915_DAC1L_ENA_WIDTH                       1  /* DAC1L_ENA */
+#define WM8915_DAC1R_ENA                        0x0001  /* DAC1R_ENA */
+#define WM8915_DAC1R_ENA_MASK                   0x0001  /* DAC1R_ENA */
+#define WM8915_DAC1R_ENA_SHIFT                       0  /* DAC1R_ENA */
+#define WM8915_DAC1R_ENA_WIDTH                       1  /* DAC1R_ENA */
+
+/*
+ * R6 (0x06) - Power Management (6)
+ */
+#define WM8915_AIF2TX_CHAN1_ENA                 0x0200  /* AIF2TX_CHAN1_ENA */
+#define WM8915_AIF2TX_CHAN1_ENA_MASK            0x0200  /* AIF2TX_CHAN1_ENA */
+#define WM8915_AIF2TX_CHAN1_ENA_SHIFT                9  /* AIF2TX_CHAN1_ENA */
+#define WM8915_AIF2TX_CHAN1_ENA_WIDTH                1  /* AIF2TX_CHAN1_ENA */
+#define WM8915_AIF2TX_CHAN0_ENA                 0x0100  /* AIF2TX_CHAN0_ENA */
+#define WM8915_AIF2TX_CHAN0_ENA_MASK            0x0100  /* AIF2TX_CHAN0_ENA */
+#define WM8915_AIF2TX_CHAN0_ENA_SHIFT                8  /* AIF2TX_CHAN0_ENA */
+#define WM8915_AIF2TX_CHAN0_ENA_WIDTH                1  /* AIF2TX_CHAN0_ENA */
+#define WM8915_AIF1TX_CHAN5_ENA                 0x0020  /* AIF1TX_CHAN5_ENA */
+#define WM8915_AIF1TX_CHAN5_ENA_MASK            0x0020  /* AIF1TX_CHAN5_ENA */
+#define WM8915_AIF1TX_CHAN5_ENA_SHIFT                5  /* AIF1TX_CHAN5_ENA */
+#define WM8915_AIF1TX_CHAN5_ENA_WIDTH                1  /* AIF1TX_CHAN5_ENA */
+#define WM8915_AIF1TX_CHAN4_ENA                 0x0010  /* AIF1TX_CHAN4_ENA */
+#define WM8915_AIF1TX_CHAN4_ENA_MASK            0x0010  /* AIF1TX_CHAN4_ENA */
+#define WM8915_AIF1TX_CHAN4_ENA_SHIFT                4  /* AIF1TX_CHAN4_ENA */
+#define WM8915_AIF1TX_CHAN4_ENA_WIDTH                1  /* AIF1TX_CHAN4_ENA */
+#define WM8915_AIF1TX_CHAN3_ENA                 0x0008  /* AIF1TX_CHAN3_ENA */
+#define WM8915_AIF1TX_CHAN3_ENA_MASK            0x0008  /* AIF1TX_CHAN3_ENA */
+#define WM8915_AIF1TX_CHAN3_ENA_SHIFT                3  /* AIF1TX_CHAN3_ENA */
+#define WM8915_AIF1TX_CHAN3_ENA_WIDTH                1  /* AIF1TX_CHAN3_ENA */
+#define WM8915_AIF1TX_CHAN2_ENA                 0x0004  /* AIF1TX_CHAN2_ENA */
+#define WM8915_AIF1TX_CHAN2_ENA_MASK            0x0004  /* AIF1TX_CHAN2_ENA */
+#define WM8915_AIF1TX_CHAN2_ENA_SHIFT                2  /* AIF1TX_CHAN2_ENA */
+#define WM8915_AIF1TX_CHAN2_ENA_WIDTH                1  /* AIF1TX_CHAN2_ENA */
+#define WM8915_AIF1TX_CHAN1_ENA                 0x0002  /* AIF1TX_CHAN1_ENA */
+#define WM8915_AIF1TX_CHAN1_ENA_MASK            0x0002  /* AIF1TX_CHAN1_ENA */
+#define WM8915_AIF1TX_CHAN1_ENA_SHIFT                1  /* AIF1TX_CHAN1_ENA */
+#define WM8915_AIF1TX_CHAN1_ENA_WIDTH                1  /* AIF1TX_CHAN1_ENA */
+#define WM8915_AIF1TX_CHAN0_ENA                 0x0001  /* AIF1TX_CHAN0_ENA */
+#define WM8915_AIF1TX_CHAN0_ENA_MASK            0x0001  /* AIF1TX_CHAN0_ENA */
+#define WM8915_AIF1TX_CHAN0_ENA_SHIFT                0  /* AIF1TX_CHAN0_ENA */
+#define WM8915_AIF1TX_CHAN0_ENA_WIDTH                1  /* AIF1TX_CHAN0_ENA */
+
+/*
+ * R7 (0x07) - Power Management (7)
+ */
+#define WM8915_DMIC2_FN                         0x0200  /* DMIC2_FN */
+#define WM8915_DMIC2_FN_MASK                    0x0200  /* DMIC2_FN */
+#define WM8915_DMIC2_FN_SHIFT                        9  /* DMIC2_FN */
+#define WM8915_DMIC2_FN_WIDTH                        1  /* DMIC2_FN */
+#define WM8915_DMIC1_FN                         0x0100  /* DMIC1_FN */
+#define WM8915_DMIC1_FN_MASK                    0x0100  /* DMIC1_FN */
+#define WM8915_DMIC1_FN_SHIFT                        8  /* DMIC1_FN */
+#define WM8915_DMIC1_FN_WIDTH                        1  /* DMIC1_FN */
+#define WM8915_ADC_DMIC_DSP2R_ENA               0x0080  /* ADC_DMIC_DSP2R_ENA */
+#define WM8915_ADC_DMIC_DSP2R_ENA_MASK          0x0080  /* ADC_DMIC_DSP2R_ENA */
+#define WM8915_ADC_DMIC_DSP2R_ENA_SHIFT              7  /* ADC_DMIC_DSP2R_ENA */
+#define WM8915_ADC_DMIC_DSP2R_ENA_WIDTH              1  /* ADC_DMIC_DSP2R_ENA */
+#define WM8915_ADC_DMIC_DSP2L_ENA               0x0040  /* ADC_DMIC_DSP2L_ENA */
+#define WM8915_ADC_DMIC_DSP2L_ENA_MASK          0x0040  /* ADC_DMIC_DSP2L_ENA */
+#define WM8915_ADC_DMIC_DSP2L_ENA_SHIFT              6  /* ADC_DMIC_DSP2L_ENA */
+#define WM8915_ADC_DMIC_DSP2L_ENA_WIDTH              1  /* ADC_DMIC_DSP2L_ENA */
+#define WM8915_ADC_DMIC_SRC2_MASK               0x0030  /* ADC_DMIC_SRC2 - [5:4] */
+#define WM8915_ADC_DMIC_SRC2_SHIFT                   4  /* ADC_DMIC_SRC2 - [5:4] */
+#define WM8915_ADC_DMIC_SRC2_WIDTH                   2  /* ADC_DMIC_SRC2 - [5:4] */
+#define WM8915_ADC_DMIC_DSP1R_ENA               0x0008  /* ADC_DMIC_DSP1R_ENA */
+#define WM8915_ADC_DMIC_DSP1R_ENA_MASK          0x0008  /* ADC_DMIC_DSP1R_ENA */
+#define WM8915_ADC_DMIC_DSP1R_ENA_SHIFT              3  /* ADC_DMIC_DSP1R_ENA */
+#define WM8915_ADC_DMIC_DSP1R_ENA_WIDTH              1  /* ADC_DMIC_DSP1R_ENA */
+#define WM8915_ADC_DMIC_DSP1L_ENA               0x0004  /* ADC_DMIC_DSP1L_ENA */
+#define WM8915_ADC_DMIC_DSP1L_ENA_MASK          0x0004  /* ADC_DMIC_DSP1L_ENA */
+#define WM8915_ADC_DMIC_DSP1L_ENA_SHIFT              2  /* ADC_DMIC_DSP1L_ENA */
+#define WM8915_ADC_DMIC_DSP1L_ENA_WIDTH              1  /* ADC_DMIC_DSP1L_ENA */
+#define WM8915_ADC_DMIC_SRC1_MASK               0x0003  /* ADC_DMIC_SRC1 - [1:0] */
+#define WM8915_ADC_DMIC_SRC1_SHIFT                   0  /* ADC_DMIC_SRC1 - [1:0] */
+#define WM8915_ADC_DMIC_SRC1_WIDTH                   2  /* ADC_DMIC_SRC1 - [1:0] */
+
+/*
+ * R8 (0x08) - Power Management (8)
+ */
+#define WM8915_AIF2TX_SRC_MASK                  0x00C0  /* AIF2TX_SRC - [7:6] */
+#define WM8915_AIF2TX_SRC_SHIFT                      6  /* AIF2TX_SRC - [7:6] */
+#define WM8915_AIF2TX_SRC_WIDTH                      2  /* AIF2TX_SRC - [7:6] */
+#define WM8915_DSP2RX_SRC                       0x0010  /* DSP2RX_SRC */
+#define WM8915_DSP2RX_SRC_MASK                  0x0010  /* DSP2RX_SRC */
+#define WM8915_DSP2RX_SRC_SHIFT                      4  /* DSP2RX_SRC */
+#define WM8915_DSP2RX_SRC_WIDTH                      1  /* DSP2RX_SRC */
+#define WM8915_DSP1RX_SRC                       0x0001  /* DSP1RX_SRC */
+#define WM8915_DSP1RX_SRC_MASK                  0x0001  /* DSP1RX_SRC */
+#define WM8915_DSP1RX_SRC_SHIFT                      0  /* DSP1RX_SRC */
+#define WM8915_DSP1RX_SRC_WIDTH                      1  /* DSP1RX_SRC */
+
+/*
+ * R16 (0x10) - Left Line Input Volume
+ */
+#define WM8915_IN1_VU                           0x0080  /* IN1_VU */
+#define WM8915_IN1_VU_MASK                      0x0080  /* IN1_VU */
+#define WM8915_IN1_VU_SHIFT                          7  /* IN1_VU */
+#define WM8915_IN1_VU_WIDTH                          1  /* IN1_VU */
+#define WM8915_IN1L_ZC                          0x0020  /* IN1L_ZC */
+#define WM8915_IN1L_ZC_MASK                     0x0020  /* IN1L_ZC */
+#define WM8915_IN1L_ZC_SHIFT                         5  /* IN1L_ZC */
+#define WM8915_IN1L_ZC_WIDTH                         1  /* IN1L_ZC */
+#define WM8915_IN1L_VOL_MASK                    0x001F  /* IN1L_VOL - [4:0] */
+#define WM8915_IN1L_VOL_SHIFT                        0  /* IN1L_VOL - [4:0] */
+#define WM8915_IN1L_VOL_WIDTH                        5  /* IN1L_VOL - [4:0] */
+
+/*
+ * R17 (0x11) - Right Line Input Volume
+ */
+#define WM8915_IN1_VU                           0x0080  /* IN1_VU */
+#define WM8915_IN1_VU_MASK                      0x0080  /* IN1_VU */
+#define WM8915_IN1_VU_SHIFT                          7  /* IN1_VU */
+#define WM8915_IN1_VU_WIDTH                          1  /* IN1_VU */
+#define WM8915_IN1R_ZC                          0x0020  /* IN1R_ZC */
+#define WM8915_IN1R_ZC_MASK                     0x0020  /* IN1R_ZC */
+#define WM8915_IN1R_ZC_SHIFT                         5  /* IN1R_ZC */
+#define WM8915_IN1R_ZC_WIDTH                         1  /* IN1R_ZC */
+#define WM8915_IN1R_VOL_MASK                    0x001F  /* IN1R_VOL - [4:0] */
+#define WM8915_IN1R_VOL_SHIFT                        0  /* IN1R_VOL - [4:0] */
+#define WM8915_IN1R_VOL_WIDTH                        5  /* IN1R_VOL - [4:0] */
+
+/*
+ * R18 (0x12) - Line Input Control
+ */
+#define WM8915_INL_MODE_MASK                    0x000C  /* INL_MODE - [3:2] */
+#define WM8915_INL_MODE_SHIFT                        2  /* INL_MODE - [3:2] */
+#define WM8915_INL_MODE_WIDTH                        2  /* INL_MODE - [3:2] */
+#define WM8915_INR_MODE_MASK                    0x0003  /* INR_MODE - [1:0] */
+#define WM8915_INR_MODE_SHIFT                        0  /* INR_MODE - [1:0] */
+#define WM8915_INR_MODE_WIDTH                        2  /* INR_MODE - [1:0] */
+
+/*
+ * R21 (0x15) - DAC1 HPOUT1 Volume
+ */
+#define WM8915_DAC1R_HPOUT1R_VOL_MASK           0x00F0  /* DAC1R_HPOUT1R_VOL - [7:4] */
+#define WM8915_DAC1R_HPOUT1R_VOL_SHIFT               4  /* DAC1R_HPOUT1R_VOL - [7:4] */
+#define WM8915_DAC1R_HPOUT1R_VOL_WIDTH               4  /* DAC1R_HPOUT1R_VOL - [7:4] */
+#define WM8915_DAC1L_HPOUT1L_VOL_MASK           0x000F  /* DAC1L_HPOUT1L_VOL - [3:0] */
+#define WM8915_DAC1L_HPOUT1L_VOL_SHIFT               0  /* DAC1L_HPOUT1L_VOL - [3:0] */
+#define WM8915_DAC1L_HPOUT1L_VOL_WIDTH               4  /* DAC1L_HPOUT1L_VOL - [3:0] */
+
+/*
+ * R22 (0x16) - DAC2 HPOUT2 Volume
+ */
+#define WM8915_DAC2R_HPOUT2R_VOL_MASK           0x00F0  /* DAC2R_HPOUT2R_VOL - [7:4] */
+#define WM8915_DAC2R_HPOUT2R_VOL_SHIFT               4  /* DAC2R_HPOUT2R_VOL - [7:4] */
+#define WM8915_DAC2R_HPOUT2R_VOL_WIDTH               4  /* DAC2R_HPOUT2R_VOL - [7:4] */
+#define WM8915_DAC2L_HPOUT2L_VOL_MASK           0x000F  /* DAC2L_HPOUT2L_VOL - [3:0] */
+#define WM8915_DAC2L_HPOUT2L_VOL_SHIFT               0  /* DAC2L_HPOUT2L_VOL - [3:0] */
+#define WM8915_DAC2L_HPOUT2L_VOL_WIDTH               4  /* DAC2L_HPOUT2L_VOL - [3:0] */
+
+/*
+ * R24 (0x18) - DAC1 Left Volume
+ */
+#define WM8915_DAC1L_MUTE                       0x0200  /* DAC1L_MUTE */
+#define WM8915_DAC1L_MUTE_MASK                  0x0200  /* DAC1L_MUTE */
+#define WM8915_DAC1L_MUTE_SHIFT                      9  /* DAC1L_MUTE */
+#define WM8915_DAC1L_MUTE_WIDTH                      1  /* DAC1L_MUTE */
+#define WM8915_DAC1_VU                          0x0100  /* DAC1_VU */
+#define WM8915_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
+#define WM8915_DAC1_VU_SHIFT                         8  /* DAC1_VU */
+#define WM8915_DAC1_VU_WIDTH                         1  /* DAC1_VU */
+#define WM8915_DAC1L_VOL_MASK                   0x00FF  /* DAC1L_VOL - [7:0] */
+#define WM8915_DAC1L_VOL_SHIFT                       0  /* DAC1L_VOL - [7:0] */
+#define WM8915_DAC1L_VOL_WIDTH                       8  /* DAC1L_VOL - [7:0] */
+
+/*
+ * R25 (0x19) - DAC1 Right Volume
+ */
+#define WM8915_DAC1R_MUTE                       0x0200  /* DAC1R_MUTE */
+#define WM8915_DAC1R_MUTE_MASK                  0x0200  /* DAC1R_MUTE */
+#define WM8915_DAC1R_MUTE_SHIFT                      9  /* DAC1R_MUTE */
+#define WM8915_DAC1R_MUTE_WIDTH                      1  /* DAC1R_MUTE */
+#define WM8915_DAC1_VU                          0x0100  /* DAC1_VU */
+#define WM8915_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
+#define WM8915_DAC1_VU_SHIFT                         8  /* DAC1_VU */
+#define WM8915_DAC1_VU_WIDTH                         1  /* DAC1_VU */
+#define WM8915_DAC1R_VOL_MASK                   0x00FF  /* DAC1R_VOL - [7:0] */
+#define WM8915_DAC1R_VOL_SHIFT                       0  /* DAC1R_VOL - [7:0] */
+#define WM8915_DAC1R_VOL_WIDTH                       8  /* DAC1R_VOL - [7:0] */
+
+/*
+ * R26 (0x1A) - DAC2 Left Volume
+ */
+#define WM8915_DAC2L_MUTE                       0x0200  /* DAC2L_MUTE */
+#define WM8915_DAC2L_MUTE_MASK                  0x0200  /* DAC2L_MUTE */
+#define WM8915_DAC2L_MUTE_SHIFT                      9  /* DAC2L_MUTE */
+#define WM8915_DAC2L_MUTE_WIDTH                      1  /* DAC2L_MUTE */
+#define WM8915_DAC2_VU                          0x0100  /* DAC2_VU */
+#define WM8915_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
+#define WM8915_DAC2_VU_SHIFT                         8  /* DAC2_VU */
+#define WM8915_DAC2_VU_WIDTH                         1  /* DAC2_VU */
+#define WM8915_DAC2L_VOL_MASK                   0x00FF  /* DAC2L_VOL - [7:0] */
+#define WM8915_DAC2L_VOL_SHIFT                       0  /* DAC2L_VOL - [7:0] */
+#define WM8915_DAC2L_VOL_WIDTH                       8  /* DAC2L_VOL - [7:0] */
+
+/*
+ * R27 (0x1B) - DAC2 Right Volume
+ */
+#define WM8915_DAC2R_MUTE                       0x0200  /* DAC2R_MUTE */
+#define WM8915_DAC2R_MUTE_MASK                  0x0200  /* DAC2R_MUTE */
+#define WM8915_DAC2R_MUTE_SHIFT                      9  /* DAC2R_MUTE */
+#define WM8915_DAC2R_MUTE_WIDTH                      1  /* DAC2R_MUTE */
+#define WM8915_DAC2_VU                          0x0100  /* DAC2_VU */
+#define WM8915_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
+#define WM8915_DAC2_VU_SHIFT                         8  /* DAC2_VU */
+#define WM8915_DAC2_VU_WIDTH                         1  /* DAC2_VU */
+#define WM8915_DAC2R_VOL_MASK                   0x00FF  /* DAC2R_VOL - [7:0] */
+#define WM8915_DAC2R_VOL_SHIFT                       0  /* DAC2R_VOL - [7:0] */
+#define WM8915_DAC2R_VOL_WIDTH                       8  /* DAC2R_VOL - [7:0] */
+
+/*
+ * R28 (0x1C) - Output1 Left Volume
+ */
+#define WM8915_DAC1_VU                          0x0100  /* DAC1_VU */
+#define WM8915_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
+#define WM8915_DAC1_VU_SHIFT                         8  /* DAC1_VU */
+#define WM8915_DAC1_VU_WIDTH                         1  /* DAC1_VU */
+#define WM8915_HPOUT1L_ZC                       0x0080  /* HPOUT1L_ZC */
+#define WM8915_HPOUT1L_ZC_MASK                  0x0080  /* HPOUT1L_ZC */
+#define WM8915_HPOUT1L_ZC_SHIFT                      7  /* HPOUT1L_ZC */
+#define WM8915_HPOUT1L_ZC_WIDTH                      1  /* HPOUT1L_ZC */
+#define WM8915_HPOUT1L_VOL_MASK                 0x000F  /* HPOUT1L_VOL - [3:0] */
+#define WM8915_HPOUT1L_VOL_SHIFT                     0  /* HPOUT1L_VOL - [3:0] */
+#define WM8915_HPOUT1L_VOL_WIDTH                     4  /* HPOUT1L_VOL - [3:0] */
+
+/*
+ * R29 (0x1D) - Output1 Right Volume
+ */
+#define WM8915_DAC1_VU                          0x0100  /* DAC1_VU */
+#define WM8915_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
+#define WM8915_DAC1_VU_SHIFT                         8  /* DAC1_VU */
+#define WM8915_DAC1_VU_WIDTH                         1  /* DAC1_VU */
+#define WM8915_HPOUT1R_ZC                       0x0080  /* HPOUT1R_ZC */
+#define WM8915_HPOUT1R_ZC_MASK                  0x0080  /* HPOUT1R_ZC */
+#define WM8915_HPOUT1R_ZC_SHIFT                      7  /* HPOUT1R_ZC */
+#define WM8915_HPOUT1R_ZC_WIDTH                      1  /* HPOUT1R_ZC */
+#define WM8915_HPOUT1R_VOL_MASK                 0x000F  /* HPOUT1R_VOL - [3:0] */
+#define WM8915_HPOUT1R_VOL_SHIFT                     0  /* HPOUT1R_VOL - [3:0] */
+#define WM8915_HPOUT1R_VOL_WIDTH                     4  /* HPOUT1R_VOL - [3:0] */
+
+/*
+ * R30 (0x1E) - Output2 Left Volume
+ */
+#define WM8915_DAC2_VU                          0x0100  /* DAC2_VU */
+#define WM8915_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
+#define WM8915_DAC2_VU_SHIFT                         8  /* DAC2_VU */
+#define WM8915_DAC2_VU_WIDTH                         1  /* DAC2_VU */
+#define WM8915_HPOUT2L_ZC                       0x0080  /* HPOUT2L_ZC */
+#define WM8915_HPOUT2L_ZC_MASK                  0x0080  /* HPOUT2L_ZC */
+#define WM8915_HPOUT2L_ZC_SHIFT                      7  /* HPOUT2L_ZC */
+#define WM8915_HPOUT2L_ZC_WIDTH                      1  /* HPOUT2L_ZC */
+#define WM8915_HPOUT2L_VOL_MASK                 0x000F  /* HPOUT2L_VOL - [3:0] */
+#define WM8915_HPOUT2L_VOL_SHIFT                     0  /* HPOUT2L_VOL - [3:0] */
+#define WM8915_HPOUT2L_VOL_WIDTH                     4  /* HPOUT2L_VOL - [3:0] */
+
+/*
+ * R31 (0x1F) - Output2 Right Volume
+ */
+#define WM8915_DAC2_VU                          0x0100  /* DAC2_VU */
+#define WM8915_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
+#define WM8915_DAC2_VU_SHIFT                         8  /* DAC2_VU */
+#define WM8915_DAC2_VU_WIDTH                         1  /* DAC2_VU */
+#define WM8915_HPOUT2R_ZC                       0x0080  /* HPOUT2R_ZC */
+#define WM8915_HPOUT2R_ZC_MASK                  0x0080  /* HPOUT2R_ZC */
+#define WM8915_HPOUT2R_ZC_SHIFT                      7  /* HPOUT2R_ZC */
+#define WM8915_HPOUT2R_ZC_WIDTH                      1  /* HPOUT2R_ZC */
+#define WM8915_HPOUT2R_VOL_MASK                 0x000F  /* HPOUT2R_VOL - [3:0] */
+#define WM8915_HPOUT2R_VOL_SHIFT                     0  /* HPOUT2R_VOL - [3:0] */
+#define WM8915_HPOUT2R_VOL_WIDTH                     4  /* HPOUT2R_VOL - [3:0] */
+
+/*
+ * R32 (0x20) - MICBIAS (1)
+ */
+#define WM8915_MICB1_RATE                       0x0020  /* MICB1_RATE */
+#define WM8915_MICB1_RATE_MASK                  0x0020  /* MICB1_RATE */
+#define WM8915_MICB1_RATE_SHIFT                      5  /* MICB1_RATE */
+#define WM8915_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
+#define WM8915_MICB1_MODE                       0x0010  /* MICB1_MODE */
+#define WM8915_MICB1_MODE_MASK                  0x0010  /* MICB1_MODE */
+#define WM8915_MICB1_MODE_SHIFT                      4  /* MICB1_MODE */
+#define WM8915_MICB1_MODE_WIDTH                      1  /* MICB1_MODE */
+#define WM8915_MICB1_LVL_MASK                   0x000E  /* MICB1_LVL - [3:1] */
+#define WM8915_MICB1_LVL_SHIFT                       1  /* MICB1_LVL - [3:1] */
+#define WM8915_MICB1_LVL_WIDTH                       3  /* MICB1_LVL - [3:1] */
+#define WM8915_MICB1_DISCH                      0x0001  /* MICB1_DISCH */
+#define WM8915_MICB1_DISCH_MASK                 0x0001  /* MICB1_DISCH */
+#define WM8915_MICB1_DISCH_SHIFT                     0  /* MICB1_DISCH */
+#define WM8915_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
+
+/*
+ * R33 (0x21) - MICBIAS (2)
+ */
+#define WM8915_MICB2_RATE                       0x0020  /* MICB2_RATE */
+#define WM8915_MICB2_RATE_MASK                  0x0020  /* MICB2_RATE */
+#define WM8915_MICB2_RATE_SHIFT                      5  /* MICB2_RATE */
+#define WM8915_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
+#define WM8915_MICB2_MODE                       0x0010  /* MICB2_MODE */
+#define WM8915_MICB2_MODE_MASK                  0x0010  /* MICB2_MODE */
+#define WM8915_MICB2_MODE_SHIFT                      4  /* MICB2_MODE */
+#define WM8915_MICB2_MODE_WIDTH                      1  /* MICB2_MODE */
+#define WM8915_MICB2_LVL_MASK                   0x000E  /* MICB2_LVL - [3:1] */
+#define WM8915_MICB2_LVL_SHIFT                       1  /* MICB2_LVL - [3:1] */
+#define WM8915_MICB2_LVL_WIDTH                       3  /* MICB2_LVL - [3:1] */
+#define WM8915_MICB2_DISCH                      0x0001  /* MICB2_DISCH */
+#define WM8915_MICB2_DISCH_MASK                 0x0001  /* MICB2_DISCH */
+#define WM8915_MICB2_DISCH_SHIFT                     0  /* MICB2_DISCH */
+#define WM8915_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
+
+/*
+ * R40 (0x28) - LDO 1
+ */
+#define WM8915_LDO1_MODE                        0x0020  /* LDO1_MODE */
+#define WM8915_LDO1_MODE_MASK                   0x0020  /* LDO1_MODE */
+#define WM8915_LDO1_MODE_SHIFT                       5  /* LDO1_MODE */
+#define WM8915_LDO1_MODE_WIDTH                       1  /* LDO1_MODE */
+#define WM8915_LDO1_VSEL_MASK                   0x0006  /* LDO1_VSEL - [2:1] */
+#define WM8915_LDO1_VSEL_SHIFT                       1  /* LDO1_VSEL - [2:1] */
+#define WM8915_LDO1_VSEL_WIDTH                       2  /* LDO1_VSEL - [2:1] */
+#define WM8915_LDO1_DISCH                       0x0001  /* LDO1_DISCH */
+#define WM8915_LDO1_DISCH_MASK                  0x0001  /* LDO1_DISCH */
+#define WM8915_LDO1_DISCH_SHIFT                      0  /* LDO1_DISCH */
+#define WM8915_LDO1_DISCH_WIDTH                      1  /* LDO1_DISCH */
+
+/*
+ * R41 (0x29) - LDO 2
+ */
+#define WM8915_LDO2_MODE                        0x0020  /* LDO2_MODE */
+#define WM8915_LDO2_MODE_MASK                   0x0020  /* LDO2_MODE */
+#define WM8915_LDO2_MODE_SHIFT                       5  /* LDO2_MODE */
+#define WM8915_LDO2_MODE_WIDTH                       1  /* LDO2_MODE */
+#define WM8915_LDO2_VSEL_MASK                   0x001E  /* LDO2_VSEL - [4:1] */
+#define WM8915_LDO2_VSEL_SHIFT                       1  /* LDO2_VSEL - [4:1] */
+#define WM8915_LDO2_VSEL_WIDTH                       4  /* LDO2_VSEL - [4:1] */
+#define WM8915_LDO2_DISCH                       0x0001  /* LDO2_DISCH */
+#define WM8915_LDO2_DISCH_MASK                  0x0001  /* LDO2_DISCH */
+#define WM8915_LDO2_DISCH_SHIFT                      0  /* LDO2_DISCH */
+#define WM8915_LDO2_DISCH_WIDTH                      1  /* LDO2_DISCH */
+
+/*
+ * R48 (0x30) - Accessory Detect Mode 1
+ */
+#define WM8915_JD_MODE_MASK                     0x0003  /* JD_MODE - [1:0] */
+#define WM8915_JD_MODE_SHIFT                         0  /* JD_MODE - [1:0] */
+#define WM8915_JD_MODE_WIDTH                         2  /* JD_MODE - [1:0] */
+
+/*
+ * R49 (0x31) - Accessory Detect Mode 2
+ */
+#define WM8915_HPOUT1FB_SRC                     0x0004  /* HPOUT1FB_SRC */
+#define WM8915_HPOUT1FB_SRC_MASK                0x0004  /* HPOUT1FB_SRC */
+#define WM8915_HPOUT1FB_SRC_SHIFT                    2  /* HPOUT1FB_SRC */
+#define WM8915_HPOUT1FB_SRC_WIDTH                    1  /* HPOUT1FB_SRC */
+#define WM8915_MICD_SRC                         0x0002  /* MICD_SRC */
+#define WM8915_MICD_SRC_MASK                    0x0002  /* MICD_SRC */
+#define WM8915_MICD_SRC_SHIFT                        1  /* MICD_SRC */
+#define WM8915_MICD_SRC_WIDTH                        1  /* MICD_SRC */
+#define WM8915_MICD_BIAS_SRC                    0x0001  /* MICD_BIAS_SRC */
+#define WM8915_MICD_BIAS_SRC_MASK               0x0001  /* MICD_BIAS_SRC */
+#define WM8915_MICD_BIAS_SRC_SHIFT                   0  /* MICD_BIAS_SRC */
+#define WM8915_MICD_BIAS_SRC_WIDTH                   1  /* MICD_BIAS_SRC */
+
+/*
+ * R52 (0x34) - Headphone Detect 1
+ */
+#define WM8915_HP_HOLDTIME_MASK                 0x00E0  /* HP_HOLDTIME - [7:5] */
+#define WM8915_HP_HOLDTIME_SHIFT                     5  /* HP_HOLDTIME - [7:5] */
+#define WM8915_HP_HOLDTIME_WIDTH                     3  /* HP_HOLDTIME - [7:5] */
+#define WM8915_HP_CLK_DIV_MASK                  0x0018  /* HP_CLK_DIV - [4:3] */
+#define WM8915_HP_CLK_DIV_SHIFT                      3  /* HP_CLK_DIV - [4:3] */
+#define WM8915_HP_CLK_DIV_WIDTH                      2  /* HP_CLK_DIV - [4:3] */
+#define WM8915_HP_STEP_SIZE                     0x0002  /* HP_STEP_SIZE */
+#define WM8915_HP_STEP_SIZE_MASK                0x0002  /* HP_STEP_SIZE */
+#define WM8915_HP_STEP_SIZE_SHIFT                    1  /* HP_STEP_SIZE */
+#define WM8915_HP_STEP_SIZE_WIDTH                    1  /* HP_STEP_SIZE */
+#define WM8915_HP_POLL                          0x0001  /* HP_POLL */
+#define WM8915_HP_POLL_MASK                     0x0001  /* HP_POLL */
+#define WM8915_HP_POLL_SHIFT                         0  /* HP_POLL */
+#define WM8915_HP_POLL_WIDTH                         1  /* HP_POLL */
+
+/*
+ * R53 (0x35) - Headphone Detect 2
+ */
+#define WM8915_HP_DONE                          0x0080  /* HP_DONE */
+#define WM8915_HP_DONE_MASK                     0x0080  /* HP_DONE */
+#define WM8915_HP_DONE_SHIFT                         7  /* HP_DONE */
+#define WM8915_HP_DONE_WIDTH                         1  /* HP_DONE */
+#define WM8915_HP_LVL_MASK                      0x007F  /* HP_LVL - [6:0] */
+#define WM8915_HP_LVL_SHIFT                          0  /* HP_LVL - [6:0] */
+#define WM8915_HP_LVL_WIDTH                          7  /* HP_LVL - [6:0] */
+
+/*
+ * R56 (0x38) - Mic Detect 1
+ */
+#define WM8915_MICD_BIAS_STARTTIME_MASK         0xF000  /* MICD_BIAS_STARTTIME - [15:12] */
+#define WM8915_MICD_BIAS_STARTTIME_SHIFT            12  /* MICD_BIAS_STARTTIME - [15:12] */
+#define WM8915_MICD_BIAS_STARTTIME_WIDTH             4  /* MICD_BIAS_STARTTIME - [15:12] */
+#define WM8915_MICD_RATE_MASK                   0x0F00  /* MICD_RATE - [11:8] */
+#define WM8915_MICD_RATE_SHIFT                       8  /* MICD_RATE - [11:8] */
+#define WM8915_MICD_RATE_WIDTH                       4  /* MICD_RATE - [11:8] */
+#define WM8915_MICD_DBTIME                      0x0002  /* MICD_DBTIME */
+#define WM8915_MICD_DBTIME_MASK                 0x0002  /* MICD_DBTIME */
+#define WM8915_MICD_DBTIME_SHIFT                     1  /* MICD_DBTIME */
+#define WM8915_MICD_DBTIME_WIDTH                     1  /* MICD_DBTIME */
+#define WM8915_MICD_ENA                         0x0001  /* MICD_ENA */
+#define WM8915_MICD_ENA_MASK                    0x0001  /* MICD_ENA */
+#define WM8915_MICD_ENA_SHIFT                        0  /* MICD_ENA */
+#define WM8915_MICD_ENA_WIDTH                        1  /* MICD_ENA */
+
+/*
+ * R57 (0x39) - Mic Detect 2
+ */
+#define WM8915_MICD_LVL_SEL_MASK                0x00FF  /* MICD_LVL_SEL - [7:0] */
+#define WM8915_MICD_LVL_SEL_SHIFT                    0  /* MICD_LVL_SEL - [7:0] */
+#define WM8915_MICD_LVL_SEL_WIDTH                    8  /* MICD_LVL_SEL - [7:0] */
+
+/*
+ * R58 (0x3A) - Mic Detect 3
+ */
+#define WM8915_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
+#define WM8915_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
+#define WM8915_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
+#define WM8915_MICD_VALID                       0x0002  /* MICD_VALID */
+#define WM8915_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
+#define WM8915_MICD_VALID_SHIFT                      1  /* MICD_VALID */
+#define WM8915_MICD_VALID_WIDTH                      1  /* MICD_VALID */
+#define WM8915_MICD_STS                         0x0001  /* MICD_STS */
+#define WM8915_MICD_STS_MASK                    0x0001  /* MICD_STS */
+#define WM8915_MICD_STS_SHIFT                        0  /* MICD_STS */
+#define WM8915_MICD_STS_WIDTH                        1  /* MICD_STS */
+
+/*
+ * R64 (0x40) - Charge Pump (1)
+ */
+#define WM8915_CP_ENA                           0x8000  /* CP_ENA */
+#define WM8915_CP_ENA_MASK                      0x8000  /* CP_ENA */
+#define WM8915_CP_ENA_SHIFT                         15  /* CP_ENA */
+#define WM8915_CP_ENA_WIDTH                          1  /* CP_ENA */
+
+/*
+ * R65 (0x41) - Charge Pump (2)
+ */
+#define WM8915_CP_DISCH                         0x8000  /* CP_DISCH */
+#define WM8915_CP_DISCH_MASK                    0x8000  /* CP_DISCH */
+#define WM8915_CP_DISCH_SHIFT                       15  /* CP_DISCH */
+#define WM8915_CP_DISCH_WIDTH                        1  /* CP_DISCH */
+
+/*
+ * R80 (0x50) - DC Servo (1)
+ */
+#define WM8915_DCS_ENA_CHAN_3                   0x0008  /* DCS_ENA_CHAN_3 */
+#define WM8915_DCS_ENA_CHAN_3_MASK              0x0008  /* DCS_ENA_CHAN_3 */
+#define WM8915_DCS_ENA_CHAN_3_SHIFT                  3  /* DCS_ENA_CHAN_3 */
+#define WM8915_DCS_ENA_CHAN_3_WIDTH                  1  /* DCS_ENA_CHAN_3 */
+#define WM8915_DCS_ENA_CHAN_2                   0x0004  /* DCS_ENA_CHAN_2 */
+#define WM8915_DCS_ENA_CHAN_2_MASK              0x0004  /* DCS_ENA_CHAN_2 */
+#define WM8915_DCS_ENA_CHAN_2_SHIFT                  2  /* DCS_ENA_CHAN_2 */
+#define WM8915_DCS_ENA_CHAN_2_WIDTH                  1  /* DCS_ENA_CHAN_2 */
+#define WM8915_DCS_ENA_CHAN_1                   0x0002  /* DCS_ENA_CHAN_1 */
+#define WM8915_DCS_ENA_CHAN_1_MASK              0x0002  /* DCS_ENA_CHAN_1 */
+#define WM8915_DCS_ENA_CHAN_1_SHIFT                  1  /* DCS_ENA_CHAN_1 */
+#define WM8915_DCS_ENA_CHAN_1_WIDTH                  1  /* DCS_ENA_CHAN_1 */
+#define WM8915_DCS_ENA_CHAN_0                   0x0001  /* DCS_ENA_CHAN_0 */
+#define WM8915_DCS_ENA_CHAN_0_MASK              0x0001  /* DCS_ENA_CHAN_0 */
+#define WM8915_DCS_ENA_CHAN_0_SHIFT                  0  /* DCS_ENA_CHAN_0 */
+#define WM8915_DCS_ENA_CHAN_0_WIDTH                  1  /* DCS_ENA_CHAN_0 */
+
+/*
+ * R81 (0x51) - DC Servo (2)
+ */
+#define WM8915_DCS_TRIG_SINGLE_3                0x8000  /* DCS_TRIG_SINGLE_3 */
+#define WM8915_DCS_TRIG_SINGLE_3_MASK           0x8000  /* DCS_TRIG_SINGLE_3 */
+#define WM8915_DCS_TRIG_SINGLE_3_SHIFT              15  /* DCS_TRIG_SINGLE_3 */
+#define WM8915_DCS_TRIG_SINGLE_3_WIDTH               1  /* DCS_TRIG_SINGLE_3 */
+#define WM8915_DCS_TRIG_SINGLE_2                0x4000  /* DCS_TRIG_SINGLE_2 */
+#define WM8915_DCS_TRIG_SINGLE_2_MASK           0x4000  /* DCS_TRIG_SINGLE_2 */
+#define WM8915_DCS_TRIG_SINGLE_2_SHIFT              14  /* DCS_TRIG_SINGLE_2 */
+#define WM8915_DCS_TRIG_SINGLE_2_WIDTH               1  /* DCS_TRIG_SINGLE_2 */
+#define WM8915_DCS_TRIG_SINGLE_1                0x2000  /* DCS_TRIG_SINGLE_1 */
+#define WM8915_DCS_TRIG_SINGLE_1_MASK           0x2000  /* DCS_TRIG_SINGLE_1 */
+#define WM8915_DCS_TRIG_SINGLE_1_SHIFT              13  /* DCS_TRIG_SINGLE_1 */
+#define WM8915_DCS_TRIG_SINGLE_1_WIDTH               1  /* DCS_TRIG_SINGLE_1 */
+#define WM8915_DCS_TRIG_SINGLE_0                0x1000  /* DCS_TRIG_SINGLE_0 */
+#define WM8915_DCS_TRIG_SINGLE_0_MASK           0x1000  /* DCS_TRIG_SINGLE_0 */
+#define WM8915_DCS_TRIG_SINGLE_0_SHIFT              12  /* DCS_TRIG_SINGLE_0 */
+#define WM8915_DCS_TRIG_SINGLE_0_WIDTH               1  /* DCS_TRIG_SINGLE_0 */
+#define WM8915_DCS_TRIG_SERIES_3                0x0800  /* DCS_TRIG_SERIES_3 */
+#define WM8915_DCS_TRIG_SERIES_3_MASK           0x0800  /* DCS_TRIG_SERIES_3 */
+#define WM8915_DCS_TRIG_SERIES_3_SHIFT              11  /* DCS_TRIG_SERIES_3 */
+#define WM8915_DCS_TRIG_SERIES_3_WIDTH               1  /* DCS_TRIG_SERIES_3 */
+#define WM8915_DCS_TRIG_SERIES_2                0x0400  /* DCS_TRIG_SERIES_2 */
+#define WM8915_DCS_TRIG_SERIES_2_MASK           0x0400  /* DCS_TRIG_SERIES_2 */
+#define WM8915_DCS_TRIG_SERIES_2_SHIFT              10  /* DCS_TRIG_SERIES_2 */
+#define WM8915_DCS_TRIG_SERIES_2_WIDTH               1  /* DCS_TRIG_SERIES_2 */
+#define WM8915_DCS_TRIG_SERIES_1                0x0200  /* DCS_TRIG_SERIES_1 */
+#define WM8915_DCS_TRIG_SERIES_1_MASK           0x0200  /* DCS_TRIG_SERIES_1 */
+#define WM8915_DCS_TRIG_SERIES_1_SHIFT               9  /* DCS_TRIG_SERIES_1 */
+#define WM8915_DCS_TRIG_SERIES_1_WIDTH               1  /* DCS_TRIG_SERIES_1 */
+#define WM8915_DCS_TRIG_SERIES_0                0x0100  /* DCS_TRIG_SERIES_0 */
+#define WM8915_DCS_TRIG_SERIES_0_MASK           0x0100  /* DCS_TRIG_SERIES_0 */
+#define WM8915_DCS_TRIG_SERIES_0_SHIFT               8  /* DCS_TRIG_SERIES_0 */
+#define WM8915_DCS_TRIG_SERIES_0_WIDTH               1  /* DCS_TRIG_SERIES_0 */
+#define WM8915_DCS_TRIG_STARTUP_3               0x0080  /* DCS_TRIG_STARTUP_3 */
+#define WM8915_DCS_TRIG_STARTUP_3_MASK          0x0080  /* DCS_TRIG_STARTUP_3 */
+#define WM8915_DCS_TRIG_STARTUP_3_SHIFT              7  /* DCS_TRIG_STARTUP_3 */
+#define WM8915_DCS_TRIG_STARTUP_3_WIDTH              1  /* DCS_TRIG_STARTUP_3 */
+#define WM8915_DCS_TRIG_STARTUP_2               0x0040  /* DCS_TRIG_STARTUP_2 */
+#define WM8915_DCS_TRIG_STARTUP_2_MASK          0x0040  /* DCS_TRIG_STARTUP_2 */
+#define WM8915_DCS_TRIG_STARTUP_2_SHIFT              6  /* DCS_TRIG_STARTUP_2 */
+#define WM8915_DCS_TRIG_STARTUP_2_WIDTH              1  /* DCS_TRIG_STARTUP_2 */
+#define WM8915_DCS_TRIG_STARTUP_1               0x0020  /* DCS_TRIG_STARTUP_1 */
+#define WM8915_DCS_TRIG_STARTUP_1_MASK          0x0020  /* DCS_TRIG_STARTUP_1 */
+#define WM8915_DCS_TRIG_STARTUP_1_SHIFT              5  /* DCS_TRIG_STARTUP_1 */
+#define WM8915_DCS_TRIG_STARTUP_1_WIDTH              1  /* DCS_TRIG_STARTUP_1 */
+#define WM8915_DCS_TRIG_STARTUP_0               0x0010  /* DCS_TRIG_STARTUP_0 */
+#define WM8915_DCS_TRIG_STARTUP_0_MASK          0x0010  /* DCS_TRIG_STARTUP_0 */
+#define WM8915_DCS_TRIG_STARTUP_0_SHIFT              4  /* DCS_TRIG_STARTUP_0 */
+#define WM8915_DCS_TRIG_STARTUP_0_WIDTH              1  /* DCS_TRIG_STARTUP_0 */
+#define WM8915_DCS_TRIG_DAC_WR_3                0x0008  /* DCS_TRIG_DAC_WR_3 */
+#define WM8915_DCS_TRIG_DAC_WR_3_MASK           0x0008  /* DCS_TRIG_DAC_WR_3 */
+#define WM8915_DCS_TRIG_DAC_WR_3_SHIFT               3  /* DCS_TRIG_DAC_WR_3 */
+#define WM8915_DCS_TRIG_DAC_WR_3_WIDTH               1  /* DCS_TRIG_DAC_WR_3 */
+#define WM8915_DCS_TRIG_DAC_WR_2                0x0004  /* DCS_TRIG_DAC_WR_2 */
+#define WM8915_DCS_TRIG_DAC_WR_2_MASK           0x0004  /* DCS_TRIG_DAC_WR_2 */
+#define WM8915_DCS_TRIG_DAC_WR_2_SHIFT               2  /* DCS_TRIG_DAC_WR_2 */
+#define WM8915_DCS_TRIG_DAC_WR_2_WIDTH               1  /* DCS_TRIG_DAC_WR_2 */
+#define WM8915_DCS_TRIG_DAC_WR_1                0x0002  /* DCS_TRIG_DAC_WR_1 */
+#define WM8915_DCS_TRIG_DAC_WR_1_MASK           0x0002  /* DCS_TRIG_DAC_WR_1 */
+#define WM8915_DCS_TRIG_DAC_WR_1_SHIFT               1  /* DCS_TRIG_DAC_WR_1 */
+#define WM8915_DCS_TRIG_DAC_WR_1_WIDTH               1  /* DCS_TRIG_DAC_WR_1 */
+#define WM8915_DCS_TRIG_DAC_WR_0                0x0001  /* DCS_TRIG_DAC_WR_0 */
+#define WM8915_DCS_TRIG_DAC_WR_0_MASK           0x0001  /* DCS_TRIG_DAC_WR_0 */
+#define WM8915_DCS_TRIG_DAC_WR_0_SHIFT               0  /* DCS_TRIG_DAC_WR_0 */
+#define WM8915_DCS_TRIG_DAC_WR_0_WIDTH               1  /* DCS_TRIG_DAC_WR_0 */
+
+/*
+ * R82 (0x52) - DC Servo (3)
+ */
+#define WM8915_DCS_TIMER_PERIOD_23_MASK         0x0F00  /* DCS_TIMER_PERIOD_23 - [11:8] */
+#define WM8915_DCS_TIMER_PERIOD_23_SHIFT             8  /* DCS_TIMER_PERIOD_23 - [11:8] */
+#define WM8915_DCS_TIMER_PERIOD_23_WIDTH             4  /* DCS_TIMER_PERIOD_23 - [11:8] */
+#define WM8915_DCS_TIMER_PERIOD_01_MASK         0x000F  /* DCS_TIMER_PERIOD_01 - [3:0] */
+#define WM8915_DCS_TIMER_PERIOD_01_SHIFT             0  /* DCS_TIMER_PERIOD_01 - [3:0] */
+#define WM8915_DCS_TIMER_PERIOD_01_WIDTH             4  /* DCS_TIMER_PERIOD_01 - [3:0] */
+
+/*
+ * R84 (0x54) - DC Servo (5)
+ */
+#define WM8915_DCS_SERIES_NO_23_MASK            0x7F00  /* DCS_SERIES_NO_23 - [14:8] */
+#define WM8915_DCS_SERIES_NO_23_SHIFT                8  /* DCS_SERIES_NO_23 - [14:8] */
+#define WM8915_DCS_SERIES_NO_23_WIDTH                7  /* DCS_SERIES_NO_23 - [14:8] */
+#define WM8915_DCS_SERIES_NO_01_MASK            0x007F  /* DCS_SERIES_NO_01 - [6:0] */
+#define WM8915_DCS_SERIES_NO_01_SHIFT                0  /* DCS_SERIES_NO_01 - [6:0] */
+#define WM8915_DCS_SERIES_NO_01_WIDTH                7  /* DCS_SERIES_NO_01 - [6:0] */
+
+/*
+ * R85 (0x55) - DC Servo (6)
+ */
+#define WM8915_DCS_DAC_WR_VAL_3_MASK            0xFF00  /* DCS_DAC_WR_VAL_3 - [15:8] */
+#define WM8915_DCS_DAC_WR_VAL_3_SHIFT                8  /* DCS_DAC_WR_VAL_3 - [15:8] */
+#define WM8915_DCS_DAC_WR_VAL_3_WIDTH                8  /* DCS_DAC_WR_VAL_3 - [15:8] */
+#define WM8915_DCS_DAC_WR_VAL_2_MASK            0x00FF  /* DCS_DAC_WR_VAL_2 - [7:0] */
+#define WM8915_DCS_DAC_WR_VAL_2_SHIFT                0  /* DCS_DAC_WR_VAL_2 - [7:0] */
+#define WM8915_DCS_DAC_WR_VAL_2_WIDTH                8  /* DCS_DAC_WR_VAL_2 - [7:0] */
+
+/*
+ * R86 (0x56) - DC Servo (7)
+ */
+#define WM8915_DCS_DAC_WR_VAL_1_MASK            0xFF00  /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8915_DCS_DAC_WR_VAL_1_SHIFT                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8915_DCS_DAC_WR_VAL_1_WIDTH                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8915_DCS_DAC_WR_VAL_0_MASK            0x00FF  /* DCS_DAC_WR_VAL_0 - [7:0] */
+#define WM8915_DCS_DAC_WR_VAL_0_SHIFT                0  /* DCS_DAC_WR_VAL_0 - [7:0] */
+#define WM8915_DCS_DAC_WR_VAL_0_WIDTH                8  /* DCS_DAC_WR_VAL_0 - [7:0] */
+
+/*
+ * R87 (0x57) - DC Servo Readback 0
+ */
+#define WM8915_DCS_CAL_COMPLETE_MASK            0x0F00  /* DCS_CAL_COMPLETE - [11:8] */
+#define WM8915_DCS_CAL_COMPLETE_SHIFT                8  /* DCS_CAL_COMPLETE - [11:8] */
+#define WM8915_DCS_CAL_COMPLETE_WIDTH                4  /* DCS_CAL_COMPLETE - [11:8] */
+#define WM8915_DCS_DAC_WR_COMPLETE_MASK         0x00F0  /* DCS_DAC_WR_COMPLETE - [7:4] */
+#define WM8915_DCS_DAC_WR_COMPLETE_SHIFT             4  /* DCS_DAC_WR_COMPLETE - [7:4] */
+#define WM8915_DCS_DAC_WR_COMPLETE_WIDTH             4  /* DCS_DAC_WR_COMPLETE - [7:4] */
+#define WM8915_DCS_STARTUP_COMPLETE_MASK        0x000F  /* DCS_STARTUP_COMPLETE - [3:0] */
+#define WM8915_DCS_STARTUP_COMPLETE_SHIFT            0  /* DCS_STARTUP_COMPLETE - [3:0] */
+#define WM8915_DCS_STARTUP_COMPLETE_WIDTH            4  /* DCS_STARTUP_COMPLETE - [3:0] */
+
+/*
+ * R96 (0x60) - Analogue HP (1)
+ */
+#define WM8915_HPOUT1L_RMV_SHORT                0x0080  /* HPOUT1L_RMV_SHORT */
+#define WM8915_HPOUT1L_RMV_SHORT_MASK           0x0080  /* HPOUT1L_RMV_SHORT */
+#define WM8915_HPOUT1L_RMV_SHORT_SHIFT               7  /* HPOUT1L_RMV_SHORT */
+#define WM8915_HPOUT1L_RMV_SHORT_WIDTH               1  /* HPOUT1L_RMV_SHORT */
+#define WM8915_HPOUT1L_OUTP                     0x0040  /* HPOUT1L_OUTP */
+#define WM8915_HPOUT1L_OUTP_MASK                0x0040  /* HPOUT1L_OUTP */
+#define WM8915_HPOUT1L_OUTP_SHIFT                    6  /* HPOUT1L_OUTP */
+#define WM8915_HPOUT1L_OUTP_WIDTH                    1  /* HPOUT1L_OUTP */
+#define WM8915_HPOUT1L_DLY                      0x0020  /* HPOUT1L_DLY */
+#define WM8915_HPOUT1L_DLY_MASK                 0x0020  /* HPOUT1L_DLY */
+#define WM8915_HPOUT1L_DLY_SHIFT                     5  /* HPOUT1L_DLY */
+#define WM8915_HPOUT1L_DLY_WIDTH                     1  /* HPOUT1L_DLY */
+#define WM8915_HPOUT1R_RMV_SHORT                0x0008  /* HPOUT1R_RMV_SHORT */
+#define WM8915_HPOUT1R_RMV_SHORT_MASK           0x0008  /* HPOUT1R_RMV_SHORT */
+#define WM8915_HPOUT1R_RMV_SHORT_SHIFT               3  /* HPOUT1R_RMV_SHORT */
+#define WM8915_HPOUT1R_RMV_SHORT_WIDTH               1  /* HPOUT1R_RMV_SHORT */
+#define WM8915_HPOUT1R_OUTP                     0x0004  /* HPOUT1R_OUTP */
+#define WM8915_HPOUT1R_OUTP_MASK                0x0004  /* HPOUT1R_OUTP */
+#define WM8915_HPOUT1R_OUTP_SHIFT                    2  /* HPOUT1R_OUTP */
+#define WM8915_HPOUT1R_OUTP_WIDTH                    1  /* HPOUT1R_OUTP */
+#define WM8915_HPOUT1R_DLY                      0x0002  /* HPOUT1R_DLY */
+#define WM8915_HPOUT1R_DLY_MASK                 0x0002  /* HPOUT1R_DLY */
+#define WM8915_HPOUT1R_DLY_SHIFT                     1  /* HPOUT1R_DLY */
+#define WM8915_HPOUT1R_DLY_WIDTH                     1  /* HPOUT1R_DLY */
+
+/*
+ * R97 (0x61) - Analogue HP (2)
+ */
+#define WM8915_HPOUT2L_RMV_SHORT                0x0080  /* HPOUT2L_RMV_SHORT */
+#define WM8915_HPOUT2L_RMV_SHORT_MASK           0x0080  /* HPOUT2L_RMV_SHORT */
+#define WM8915_HPOUT2L_RMV_SHORT_SHIFT               7  /* HPOUT2L_RMV_SHORT */
+#define WM8915_HPOUT2L_RMV_SHORT_WIDTH               1  /* HPOUT2L_RMV_SHORT */
+#define WM8915_HPOUT2L_OUTP                     0x0040  /* HPOUT2L_OUTP */
+#define WM8915_HPOUT2L_OUTP_MASK                0x0040  /* HPOUT2L_OUTP */
+#define WM8915_HPOUT2L_OUTP_SHIFT                    6  /* HPOUT2L_OUTP */
+#define WM8915_HPOUT2L_OUTP_WIDTH                    1  /* HPOUT2L_OUTP */
+#define WM8915_HPOUT2L_DLY                      0x0020  /* HPOUT2L_DLY */
+#define WM8915_HPOUT2L_DLY_MASK                 0x0020  /* HPOUT2L_DLY */
+#define WM8915_HPOUT2L_DLY_SHIFT                     5  /* HPOUT2L_DLY */
+#define WM8915_HPOUT2L_DLY_WIDTH                     1  /* HPOUT2L_DLY */
+#define WM8915_HPOUT2R_RMV_SHORT                0x0008  /* HPOUT2R_RMV_SHORT */
+#define WM8915_HPOUT2R_RMV_SHORT_MASK           0x0008  /* HPOUT2R_RMV_SHORT */
+#define WM8915_HPOUT2R_RMV_SHORT_SHIFT               3  /* HPOUT2R_RMV_SHORT */
+#define WM8915_HPOUT2R_RMV_SHORT_WIDTH               1  /* HPOUT2R_RMV_SHORT */
+#define WM8915_HPOUT2R_OUTP                     0x0004  /* HPOUT2R_OUTP */
+#define WM8915_HPOUT2R_OUTP_MASK                0x0004  /* HPOUT2R_OUTP */
+#define WM8915_HPOUT2R_OUTP_SHIFT                    2  /* HPOUT2R_OUTP */
+#define WM8915_HPOUT2R_OUTP_WIDTH                    1  /* HPOUT2R_OUTP */
+#define WM8915_HPOUT2R_DLY                      0x0002  /* HPOUT2R_DLY */
+#define WM8915_HPOUT2R_DLY_MASK                 0x0002  /* HPOUT2R_DLY */
+#define WM8915_HPOUT2R_DLY_SHIFT                     1  /* HPOUT2R_DLY */
+#define WM8915_HPOUT2R_DLY_WIDTH                     1  /* HPOUT2R_DLY */
+
+/*
+ * R256 (0x100) - Chip Revision
+ */
+#define WM8915_CHIP_REV_MASK                    0x000F  /* CHIP_REV - [3:0] */
+#define WM8915_CHIP_REV_SHIFT                        0  /* CHIP_REV - [3:0] */
+#define WM8915_CHIP_REV_WIDTH                        4  /* CHIP_REV - [3:0] */
+
+/*
+ * R257 (0x101) - Control Interface (1)
+ */
+#define WM8915_AUTO_INC                         0x0004  /* AUTO_INC */
+#define WM8915_AUTO_INC_MASK                    0x0004  /* AUTO_INC */
+#define WM8915_AUTO_INC_SHIFT                        2  /* AUTO_INC */
+#define WM8915_AUTO_INC_WIDTH                        1  /* AUTO_INC */
+
+/*
+ * R272 (0x110) - Write Sequencer Ctrl (1)
+ */
+#define WM8915_WSEQ_ENA                         0x8000  /* WSEQ_ENA */
+#define WM8915_WSEQ_ENA_MASK                    0x8000  /* WSEQ_ENA */
+#define WM8915_WSEQ_ENA_SHIFT                       15  /* WSEQ_ENA */
+#define WM8915_WSEQ_ENA_WIDTH                        1  /* WSEQ_ENA */
+#define WM8915_WSEQ_ABORT                       0x0200  /* WSEQ_ABORT */
+#define WM8915_WSEQ_ABORT_MASK                  0x0200  /* WSEQ_ABORT */
+#define WM8915_WSEQ_ABORT_SHIFT                      9  /* WSEQ_ABORT */
+#define WM8915_WSEQ_ABORT_WIDTH                      1  /* WSEQ_ABORT */
+#define WM8915_WSEQ_START                       0x0100  /* WSEQ_START */
+#define WM8915_WSEQ_START_MASK                  0x0100  /* WSEQ_START */
+#define WM8915_WSEQ_START_SHIFT                      8  /* WSEQ_START */
+#define WM8915_WSEQ_START_WIDTH                      1  /* WSEQ_START */
+#define WM8915_WSEQ_START_INDEX_MASK            0x007F  /* WSEQ_START_INDEX - [6:0] */
+#define WM8915_WSEQ_START_INDEX_SHIFT                0  /* WSEQ_START_INDEX - [6:0] */
+#define WM8915_WSEQ_START_INDEX_WIDTH                7  /* WSEQ_START_INDEX - [6:0] */
+
+/*
+ * R273 (0x111) - Write Sequencer Ctrl (2)
+ */
+#define WM8915_WSEQ_BUSY                        0x0100  /* WSEQ_BUSY */
+#define WM8915_WSEQ_BUSY_MASK                   0x0100  /* WSEQ_BUSY */
+#define WM8915_WSEQ_BUSY_SHIFT                       8  /* WSEQ_BUSY */
+#define WM8915_WSEQ_BUSY_WIDTH                       1  /* WSEQ_BUSY */
+#define WM8915_WSEQ_CURRENT_INDEX_MASK          0x007F  /* WSEQ_CURRENT_INDEX - [6:0] */
+#define WM8915_WSEQ_CURRENT_INDEX_SHIFT              0  /* WSEQ_CURRENT_INDEX - [6:0] */
+#define WM8915_WSEQ_CURRENT_INDEX_WIDTH              7  /* WSEQ_CURRENT_INDEX - [6:0] */
+
+/*
+ * R512 (0x200) - AIF Clocking (1)
+ */
+#define WM8915_SYSCLK_SRC_MASK                  0x0018  /* SYSCLK_SRC - [4:3] */
+#define WM8915_SYSCLK_SRC_SHIFT                      3  /* SYSCLK_SRC - [4:3] */
+#define WM8915_SYSCLK_SRC_WIDTH                      2  /* SYSCLK_SRC - [4:3] */
+#define WM8915_SYSCLK_INV                       0x0004  /* SYSCLK_INV */
+#define WM8915_SYSCLK_INV_MASK                  0x0004  /* SYSCLK_INV */
+#define WM8915_SYSCLK_INV_SHIFT                      2  /* SYSCLK_INV */
+#define WM8915_SYSCLK_INV_WIDTH                      1  /* SYSCLK_INV */
+#define WM8915_SYSCLK_DIV                       0x0002  /* SYSCLK_DIV */
+#define WM8915_SYSCLK_DIV_MASK                  0x0002  /* SYSCLK_DIV */
+#define WM8915_SYSCLK_DIV_SHIFT                      1  /* SYSCLK_DIV */
+#define WM8915_SYSCLK_DIV_WIDTH                      1  /* SYSCLK_DIV */
+#define WM8915_SYSCLK_ENA                       0x0001  /* SYSCLK_ENA */
+#define WM8915_SYSCLK_ENA_MASK                  0x0001  /* SYSCLK_ENA */
+#define WM8915_SYSCLK_ENA_SHIFT                      0  /* SYSCLK_ENA */
+#define WM8915_SYSCLK_ENA_WIDTH                      1  /* SYSCLK_ENA */
+
+/*
+ * R513 (0x201) - AIF Clocking (2)
+ */
+#define WM8915_DSP2_DIV_MASK                    0x0018  /* DSP2_DIV - [4:3] */
+#define WM8915_DSP2_DIV_SHIFT                        3  /* DSP2_DIV - [4:3] */
+#define WM8915_DSP2_DIV_WIDTH                        2  /* DSP2_DIV - [4:3] */
+#define WM8915_DSP1_DIV_MASK                    0x0003  /* DSP1_DIV - [1:0] */
+#define WM8915_DSP1_DIV_SHIFT                        0  /* DSP1_DIV - [1:0] */
+#define WM8915_DSP1_DIV_WIDTH                        2  /* DSP1_DIV - [1:0] */
+
+/*
+ * R520 (0x208) - Clocking (1)
+ */
+#define WM8915_LFCLK_ENA                        0x0020  /* LFCLK_ENA */
+#define WM8915_LFCLK_ENA_MASK                   0x0020  /* LFCLK_ENA */
+#define WM8915_LFCLK_ENA_SHIFT                       5  /* LFCLK_ENA */
+#define WM8915_LFCLK_ENA_WIDTH                       1  /* LFCLK_ENA */
+#define WM8915_TOCLK_ENA                        0x0010  /* TOCLK_ENA */
+#define WM8915_TOCLK_ENA_MASK                   0x0010  /* TOCLK_ENA */
+#define WM8915_TOCLK_ENA_SHIFT                       4  /* TOCLK_ENA */
+#define WM8915_TOCLK_ENA_WIDTH                       1  /* TOCLK_ENA */
+#define WM8915_AIFCLK_ENA                       0x0004  /* AIFCLK_ENA */
+#define WM8915_AIFCLK_ENA_MASK                  0x0004  /* AIFCLK_ENA */
+#define WM8915_AIFCLK_ENA_SHIFT                      2  /* AIFCLK_ENA */
+#define WM8915_AIFCLK_ENA_WIDTH                      1  /* AIFCLK_ENA */
+#define WM8915_SYSDSPCLK_ENA                    0x0002  /* SYSDSPCLK_ENA */
+#define WM8915_SYSDSPCLK_ENA_MASK               0x0002  /* SYSDSPCLK_ENA */
+#define WM8915_SYSDSPCLK_ENA_SHIFT                   1  /* SYSDSPCLK_ENA */
+#define WM8915_SYSDSPCLK_ENA_WIDTH                   1  /* SYSDSPCLK_ENA */
+
+/*
+ * R521 (0x209) - Clocking (2)
+ */
+#define WM8915_TOCLK_DIV_MASK                   0x0700  /* TOCLK_DIV - [10:8] */
+#define WM8915_TOCLK_DIV_SHIFT                       8  /* TOCLK_DIV - [10:8] */
+#define WM8915_TOCLK_DIV_WIDTH                       3  /* TOCLK_DIV - [10:8] */
+#define WM8915_DBCLK_DIV_MASK                   0x00F0  /* DBCLK_DIV - [7:4] */
+#define WM8915_DBCLK_DIV_SHIFT                       4  /* DBCLK_DIV - [7:4] */
+#define WM8915_DBCLK_DIV_WIDTH                       4  /* DBCLK_DIV - [7:4] */
+#define WM8915_OPCLK_DIV_MASK                   0x0007  /* OPCLK_DIV - [2:0] */
+#define WM8915_OPCLK_DIV_SHIFT                       0  /* OPCLK_DIV - [2:0] */
+#define WM8915_OPCLK_DIV_WIDTH                       3  /* OPCLK_DIV - [2:0] */
+
+/*
+ * R528 (0x210) - AIF Rate
+ */
+#define WM8915_SYSCLK_RATE                      0x0001  /* SYSCLK_RATE */
+#define WM8915_SYSCLK_RATE_MASK                 0x0001  /* SYSCLK_RATE */
+#define WM8915_SYSCLK_RATE_SHIFT                     0  /* SYSCLK_RATE */
+#define WM8915_SYSCLK_RATE_WIDTH                     1  /* SYSCLK_RATE */
+
+/*
+ * R544 (0x220) - FLL Control (1)
+ */
+#define WM8915_FLL_OSC_ENA                      0x0002  /* FLL_OSC_ENA */
+#define WM8915_FLL_OSC_ENA_MASK                 0x0002  /* FLL_OSC_ENA */
+#define WM8915_FLL_OSC_ENA_SHIFT                     1  /* FLL_OSC_ENA */
+#define WM8915_FLL_OSC_ENA_WIDTH                     1  /* FLL_OSC_ENA */
+#define WM8915_FLL_ENA                          0x0001  /* FLL_ENA */
+#define WM8915_FLL_ENA_MASK                     0x0001  /* FLL_ENA */
+#define WM8915_FLL_ENA_SHIFT                         0  /* FLL_ENA */
+#define WM8915_FLL_ENA_WIDTH                         1  /* FLL_ENA */
+
+/*
+ * R545 (0x221) - FLL Control (2)
+ */
+#define WM8915_FLL_OUTDIV_MASK                  0x3F00  /* FLL_OUTDIV - [13:8] */
+#define WM8915_FLL_OUTDIV_SHIFT                      8  /* FLL_OUTDIV - [13:8] */
+#define WM8915_FLL_OUTDIV_WIDTH                      6  /* FLL_OUTDIV - [13:8] */
+#define WM8915_FLL_FRATIO_MASK                  0x0007  /* FLL_FRATIO - [2:0] */
+#define WM8915_FLL_FRATIO_SHIFT                      0  /* FLL_FRATIO - [2:0] */
+#define WM8915_FLL_FRATIO_WIDTH                      3  /* FLL_FRATIO - [2:0] */
+
+/*
+ * R546 (0x222) - FLL Control (3)
+ */
+#define WM8915_FLL_THETA_MASK                   0xFFFF  /* FLL_THETA - [15:0] */
+#define WM8915_FLL_THETA_SHIFT                       0  /* FLL_THETA - [15:0] */
+#define WM8915_FLL_THETA_WIDTH                      16  /* FLL_THETA - [15:0] */
+
+/*
+ * R547 (0x223) - FLL Control (4)
+ */
+#define WM8915_FLL_N_MASK                       0x7FE0  /* FLL_N - [14:5] */
+#define WM8915_FLL_N_SHIFT                           5  /* FLL_N - [14:5] */
+#define WM8915_FLL_N_WIDTH                          10  /* FLL_N - [14:5] */
+#define WM8915_FLL_LOOP_GAIN_MASK               0x000F  /* FLL_LOOP_GAIN - [3:0] */
+#define WM8915_FLL_LOOP_GAIN_SHIFT                   0  /* FLL_LOOP_GAIN - [3:0] */
+#define WM8915_FLL_LOOP_GAIN_WIDTH                   4  /* FLL_LOOP_GAIN - [3:0] */
+
+/*
+ * R548 (0x224) - FLL Control (5)
+ */
+#define WM8915_FLL_FRC_NCO_VAL_MASK             0x1F80  /* FLL_FRC_NCO_VAL - [12:7] */
+#define WM8915_FLL_FRC_NCO_VAL_SHIFT                 7  /* FLL_FRC_NCO_VAL - [12:7] */
+#define WM8915_FLL_FRC_NCO_VAL_WIDTH                 6  /* FLL_FRC_NCO_VAL - [12:7] */
+#define WM8915_FLL_FRC_NCO                      0x0040  /* FLL_FRC_NCO */
+#define WM8915_FLL_FRC_NCO_MASK                 0x0040  /* FLL_FRC_NCO */
+#define WM8915_FLL_FRC_NCO_SHIFT                     6  /* FLL_FRC_NCO */
+#define WM8915_FLL_FRC_NCO_WIDTH                     1  /* FLL_FRC_NCO */
+#define WM8915_FLL_REFCLK_DIV_MASK              0x0018  /* FLL_REFCLK_DIV - [4:3] */
+#define WM8915_FLL_REFCLK_DIV_SHIFT                  3  /* FLL_REFCLK_DIV - [4:3] */
+#define WM8915_FLL_REFCLK_DIV_WIDTH                  2  /* FLL_REFCLK_DIV - [4:3] */
+#define WM8915_FLL_REF_FREQ                     0x0004  /* FLL_REF_FREQ */
+#define WM8915_FLL_REF_FREQ_MASK                0x0004  /* FLL_REF_FREQ */
+#define WM8915_FLL_REF_FREQ_SHIFT                    2  /* FLL_REF_FREQ */
+#define WM8915_FLL_REF_FREQ_WIDTH                    1  /* FLL_REF_FREQ */
+#define WM8915_FLL_REFCLK_SRC_MASK              0x0003  /* FLL_REFCLK_SRC - [1:0] */
+#define WM8915_FLL_REFCLK_SRC_SHIFT                  0  /* FLL_REFCLK_SRC - [1:0] */
+#define WM8915_FLL_REFCLK_SRC_WIDTH                  2  /* FLL_REFCLK_SRC - [1:0] */
+
+/*
+ * R549 (0x225) - FLL Control (6)
+ */
+#define WM8915_FLL_REFCLK_SRC_STS_MASK          0x000C  /* FLL_REFCLK_SRC_STS - [3:2] */
+#define WM8915_FLL_REFCLK_SRC_STS_SHIFT              2  /* FLL_REFCLK_SRC_STS - [3:2] */
+#define WM8915_FLL_REFCLK_SRC_STS_WIDTH              2  /* FLL_REFCLK_SRC_STS - [3:2] */
+#define WM8915_FLL_SWITCH_CLK                   0x0001  /* FLL_SWITCH_CLK */
+#define WM8915_FLL_SWITCH_CLK_MASK              0x0001  /* FLL_SWITCH_CLK */
+#define WM8915_FLL_SWITCH_CLK_SHIFT                  0  /* FLL_SWITCH_CLK */
+#define WM8915_FLL_SWITCH_CLK_WIDTH                  1  /* FLL_SWITCH_CLK */
+
+/*
+ * R550 (0x226) - FLL EFS 1
+ */
+#define WM8915_FLL_LAMBDA_MASK                  0xFFFF  /* FLL_LAMBDA - [15:0] */
+#define WM8915_FLL_LAMBDA_SHIFT                      0  /* FLL_LAMBDA - [15:0] */
+#define WM8915_FLL_LAMBDA_WIDTH                     16  /* FLL_LAMBDA - [15:0] */
+
+/*
+ * R551 (0x227) - FLL EFS 2
+ */
+#define WM8915_FLL_LFSR_SEL_MASK                0x0006  /* FLL_LFSR_SEL - [2:1] */
+#define WM8915_FLL_LFSR_SEL_SHIFT                    1  /* FLL_LFSR_SEL - [2:1] */
+#define WM8915_FLL_LFSR_SEL_WIDTH                    2  /* FLL_LFSR_SEL - [2:1] */
+#define WM8915_FLL_EFS_ENA                      0x0001  /* FLL_EFS_ENA */
+#define WM8915_FLL_EFS_ENA_MASK                 0x0001  /* FLL_EFS_ENA */
+#define WM8915_FLL_EFS_ENA_SHIFT                     0  /* FLL_EFS_ENA */
+#define WM8915_FLL_EFS_ENA_WIDTH                     1  /* FLL_EFS_ENA */
+
+/*
+ * R768 (0x300) - AIF1 Control
+ */
+#define WM8915_AIF1_TRI                         0x0004  /* AIF1_TRI */
+#define WM8915_AIF1_TRI_MASK                    0x0004  /* AIF1_TRI */
+#define WM8915_AIF1_TRI_SHIFT                        2  /* AIF1_TRI */
+#define WM8915_AIF1_TRI_WIDTH                        1  /* AIF1_TRI */
+#define WM8915_AIF1_FMT_MASK                    0x0003  /* AIF1_FMT - [1:0] */
+#define WM8915_AIF1_FMT_SHIFT                        0  /* AIF1_FMT - [1:0] */
+#define WM8915_AIF1_FMT_WIDTH                        2  /* AIF1_FMT - [1:0] */
+
+/*
+ * R769 (0x301) - AIF1 BCLK
+ */
+#define WM8915_AIF1_BCLK_INV                    0x0400  /* AIF1_BCLK_INV */
+#define WM8915_AIF1_BCLK_INV_MASK               0x0400  /* AIF1_BCLK_INV */
+#define WM8915_AIF1_BCLK_INV_SHIFT                  10  /* AIF1_BCLK_INV */
+#define WM8915_AIF1_BCLK_INV_WIDTH                   1  /* AIF1_BCLK_INV */
+#define WM8915_AIF1_BCLK_FRC                    0x0200  /* AIF1_BCLK_FRC */
+#define WM8915_AIF1_BCLK_FRC_MASK               0x0200  /* AIF1_BCLK_FRC */
+#define WM8915_AIF1_BCLK_FRC_SHIFT                   9  /* AIF1_BCLK_FRC */
+#define WM8915_AIF1_BCLK_FRC_WIDTH                   1  /* AIF1_BCLK_FRC */
+#define WM8915_AIF1_BCLK_MSTR                   0x0100  /* AIF1_BCLK_MSTR */
+#define WM8915_AIF1_BCLK_MSTR_MASK              0x0100  /* AIF1_BCLK_MSTR */
+#define WM8915_AIF1_BCLK_MSTR_SHIFT                  8  /* AIF1_BCLK_MSTR */
+#define WM8915_AIF1_BCLK_MSTR_WIDTH                  1  /* AIF1_BCLK_MSTR */
+#define WM8915_AIF1_BCLK_DIV_MASK               0x000F  /* AIF1_BCLK_DIV - [3:0] */
+#define WM8915_AIF1_BCLK_DIV_SHIFT                   0  /* AIF1_BCLK_DIV - [3:0] */
+#define WM8915_AIF1_BCLK_DIV_WIDTH                   4  /* AIF1_BCLK_DIV - [3:0] */
+
+/*
+ * R770 (0x302) - AIF1 TX LRCLK(1)
+ */
+#define WM8915_AIF1TX_RATE_MASK                 0x07FF  /* AIF1TX_RATE - [10:0] */
+#define WM8915_AIF1TX_RATE_SHIFT                     0  /* AIF1TX_RATE - [10:0] */
+#define WM8915_AIF1TX_RATE_WIDTH                    11  /* AIF1TX_RATE - [10:0] */
+
+/*
+ * R771 (0x303) - AIF1 TX LRCLK(2)
+ */
+#define WM8915_AIF1TX_LRCLK_MODE                0x0008  /* AIF1TX_LRCLK_MODE */
+#define WM8915_AIF1TX_LRCLK_MODE_MASK           0x0008  /* AIF1TX_LRCLK_MODE */
+#define WM8915_AIF1TX_LRCLK_MODE_SHIFT               3  /* AIF1TX_LRCLK_MODE */
+#define WM8915_AIF1TX_LRCLK_MODE_WIDTH               1  /* AIF1TX_LRCLK_MODE */
+#define WM8915_AIF1TX_LRCLK_INV                 0x0004  /* AIF1TX_LRCLK_INV */
+#define WM8915_AIF1TX_LRCLK_INV_MASK            0x0004  /* AIF1TX_LRCLK_INV */
+#define WM8915_AIF1TX_LRCLK_INV_SHIFT                2  /* AIF1TX_LRCLK_INV */
+#define WM8915_AIF1TX_LRCLK_INV_WIDTH                1  /* AIF1TX_LRCLK_INV */
+#define WM8915_AIF1TX_LRCLK_FRC                 0x0002  /* AIF1TX_LRCLK_FRC */
+#define WM8915_AIF1TX_LRCLK_FRC_MASK            0x0002  /* AIF1TX_LRCLK_FRC */
+#define WM8915_AIF1TX_LRCLK_FRC_SHIFT                1  /* AIF1TX_LRCLK_FRC */
+#define WM8915_AIF1TX_LRCLK_FRC_WIDTH                1  /* AIF1TX_LRCLK_FRC */
+#define WM8915_AIF1TX_LRCLK_MSTR                0x0001  /* AIF1TX_LRCLK_MSTR */
+#define WM8915_AIF1TX_LRCLK_MSTR_MASK           0x0001  /* AIF1TX_LRCLK_MSTR */
+#define WM8915_AIF1TX_LRCLK_MSTR_SHIFT               0  /* AIF1TX_LRCLK_MSTR */
+#define WM8915_AIF1TX_LRCLK_MSTR_WIDTH               1  /* AIF1TX_LRCLK_MSTR */
+
+/*
+ * R772 (0x304) - AIF1 RX LRCLK(1)
+ */
+#define WM8915_AIF1RX_RATE_MASK                 0x07FF  /* AIF1RX_RATE - [10:0] */
+#define WM8915_AIF1RX_RATE_SHIFT                     0  /* AIF1RX_RATE - [10:0] */
+#define WM8915_AIF1RX_RATE_WIDTH                    11  /* AIF1RX_RATE - [10:0] */
+
+/*
+ * R773 (0x305) - AIF1 RX LRCLK(2)
+ */
+#define WM8915_AIF1RX_LRCLK_INV                 0x0004  /* AIF1RX_LRCLK_INV */
+#define WM8915_AIF1RX_LRCLK_INV_MASK            0x0004  /* AIF1RX_LRCLK_INV */
+#define WM8915_AIF1RX_LRCLK_INV_SHIFT                2  /* AIF1RX_LRCLK_INV */
+#define WM8915_AIF1RX_LRCLK_INV_WIDTH                1  /* AIF1RX_LRCLK_INV */
+#define WM8915_AIF1RX_LRCLK_FRC                 0x0002  /* AIF1RX_LRCLK_FRC */
+#define WM8915_AIF1RX_LRCLK_FRC_MASK            0x0002  /* AIF1RX_LRCLK_FRC */
+#define WM8915_AIF1RX_LRCLK_FRC_SHIFT                1  /* AIF1RX_LRCLK_FRC */
+#define WM8915_AIF1RX_LRCLK_FRC_WIDTH                1  /* AIF1RX_LRCLK_FRC */
+#define WM8915_AIF1RX_LRCLK_MSTR                0x0001  /* AIF1RX_LRCLK_MSTR */
+#define WM8915_AIF1RX_LRCLK_MSTR_MASK           0x0001  /* AIF1RX_LRCLK_MSTR */
+#define WM8915_AIF1RX_LRCLK_MSTR_SHIFT               0  /* AIF1RX_LRCLK_MSTR */
+#define WM8915_AIF1RX_LRCLK_MSTR_WIDTH               1  /* AIF1RX_LRCLK_MSTR */
+
+/*
+ * R774 (0x306) - AIF1TX Data Configuration (1)
+ */
+#define WM8915_AIF1TX_WL_MASK                   0xFF00  /* AIF1TX_WL - [15:8] */
+#define WM8915_AIF1TX_WL_SHIFT                       8  /* AIF1TX_WL - [15:8] */
+#define WM8915_AIF1TX_WL_WIDTH                       8  /* AIF1TX_WL - [15:8] */
+#define WM8915_AIF1TX_SLOT_LEN_MASK             0x00FF  /* AIF1TX_SLOT_LEN - [7:0] */
+#define WM8915_AIF1TX_SLOT_LEN_SHIFT                 0  /* AIF1TX_SLOT_LEN - [7:0] */
+#define WM8915_AIF1TX_SLOT_LEN_WIDTH                 8  /* AIF1TX_SLOT_LEN - [7:0] */
+
+/*
+ * R775 (0x307) - AIF1TX Data Configuration (2)
+ */
+#define WM8915_AIF1TX_DAT_TRI                   0x0001  /* AIF1TX_DAT_TRI */
+#define WM8915_AIF1TX_DAT_TRI_MASK              0x0001  /* AIF1TX_DAT_TRI */
+#define WM8915_AIF1TX_DAT_TRI_SHIFT                  0  /* AIF1TX_DAT_TRI */
+#define WM8915_AIF1TX_DAT_TRI_WIDTH                  1  /* AIF1TX_DAT_TRI */
+
+/*
+ * R776 (0x308) - AIF1RX Data Configuration
+ */
+#define WM8915_AIF1RX_WL_MASK                   0xFF00  /* AIF1RX_WL - [15:8] */
+#define WM8915_AIF1RX_WL_SHIFT                       8  /* AIF1RX_WL - [15:8] */
+#define WM8915_AIF1RX_WL_WIDTH                       8  /* AIF1RX_WL - [15:8] */
+#define WM8915_AIF1RX_SLOT_LEN_MASK             0x00FF  /* AIF1RX_SLOT_LEN - [7:0] */
+#define WM8915_AIF1RX_SLOT_LEN_SHIFT                 0  /* AIF1RX_SLOT_LEN - [7:0] */
+#define WM8915_AIF1RX_SLOT_LEN_WIDTH                 8  /* AIF1RX_SLOT_LEN - [7:0] */
+
+/*
+ * R777 (0x309) - AIF1TX Channel 0 Configuration
+ */
+#define WM8915_AIF1TX_CHAN0_DAT_INV             0x8000  /* AIF1TX_CHAN0_DAT_INV */
+#define WM8915_AIF1TX_CHAN0_DAT_INV_MASK        0x8000  /* AIF1TX_CHAN0_DAT_INV */
+#define WM8915_AIF1TX_CHAN0_DAT_INV_SHIFT           15  /* AIF1TX_CHAN0_DAT_INV */
+#define WM8915_AIF1TX_CHAN0_DAT_INV_WIDTH            1  /* AIF1TX_CHAN0_DAT_INV */
+#define WM8915_AIF1TX_CHAN0_SPACING_MASK        0x7E00  /* AIF1TX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN0_SPACING_SHIFT            9  /* AIF1TX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN0_SPACING_WIDTH            6  /* AIF1TX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN0_SLOTS_MASK          0x01C0  /* AIF1TX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN0_SLOTS_SHIFT              6  /* AIF1TX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN0_SLOTS_WIDTH              3  /* AIF1TX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN0_START_SLOT_MASK     0x003F  /* AIF1TX_CHAN0_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN0_START_SLOT_SHIFT         0  /* AIF1TX_CHAN0_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN0_START_SLOT_WIDTH         6  /* AIF1TX_CHAN0_START_SLOT - [5:0] */
+
+/*
+ * R778 (0x30A) - AIF1TX Channel 1 Configuration
+ */
+#define WM8915_AIF1TX_CHAN1_DAT_INV             0x8000  /* AIF1TX_CHAN1_DAT_INV */
+#define WM8915_AIF1TX_CHAN1_DAT_INV_MASK        0x8000  /* AIF1TX_CHAN1_DAT_INV */
+#define WM8915_AIF1TX_CHAN1_DAT_INV_SHIFT           15  /* AIF1TX_CHAN1_DAT_INV */
+#define WM8915_AIF1TX_CHAN1_DAT_INV_WIDTH            1  /* AIF1TX_CHAN1_DAT_INV */
+#define WM8915_AIF1TX_CHAN1_SPACING_MASK        0x7E00  /* AIF1TX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN1_SPACING_SHIFT            9  /* AIF1TX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN1_SPACING_WIDTH            6  /* AIF1TX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN1_SLOTS_MASK          0x01C0  /* AIF1TX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN1_SLOTS_SHIFT              6  /* AIF1TX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN1_SLOTS_WIDTH              3  /* AIF1TX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN1_START_SLOT_MASK     0x003F  /* AIF1TX_CHAN1_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN1_START_SLOT_SHIFT         0  /* AIF1TX_CHAN1_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN1_START_SLOT_WIDTH         6  /* AIF1TX_CHAN1_START_SLOT - [5:0] */
+
+/*
+ * R779 (0x30B) - AIF1TX Channel 2 Configuration
+ */
+#define WM8915_AIF1TX_CHAN2_DAT_INV             0x8000  /* AIF1TX_CHAN2_DAT_INV */
+#define WM8915_AIF1TX_CHAN2_DAT_INV_MASK        0x8000  /* AIF1TX_CHAN2_DAT_INV */
+#define WM8915_AIF1TX_CHAN2_DAT_INV_SHIFT           15  /* AIF1TX_CHAN2_DAT_INV */
+#define WM8915_AIF1TX_CHAN2_DAT_INV_WIDTH            1  /* AIF1TX_CHAN2_DAT_INV */
+#define WM8915_AIF1TX_CHAN2_SPACING_MASK        0x7E00  /* AIF1TX_CHAN2_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN2_SPACING_SHIFT            9  /* AIF1TX_CHAN2_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN2_SPACING_WIDTH            6  /* AIF1TX_CHAN2_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN2_SLOTS_MASK          0x01C0  /* AIF1TX_CHAN2_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN2_SLOTS_SHIFT              6  /* AIF1TX_CHAN2_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN2_SLOTS_WIDTH              3  /* AIF1TX_CHAN2_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN2_START_SLOT_MASK     0x003F  /* AIF1TX_CHAN2_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN2_START_SLOT_SHIFT         0  /* AIF1TX_CHAN2_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN2_START_SLOT_WIDTH         6  /* AIF1TX_CHAN2_START_SLOT - [5:0] */
+
+/*
+ * R780 (0x30C) - AIF1TX Channel 3 Configuration
+ */
+#define WM8915_AIF1TX_CHAN3_DAT_INV             0x8000  /* AIF1TX_CHAN3_DAT_INV */
+#define WM8915_AIF1TX_CHAN3_DAT_INV_MASK        0x8000  /* AIF1TX_CHAN3_DAT_INV */
+#define WM8915_AIF1TX_CHAN3_DAT_INV_SHIFT           15  /* AIF1TX_CHAN3_DAT_INV */
+#define WM8915_AIF1TX_CHAN3_DAT_INV_WIDTH            1  /* AIF1TX_CHAN3_DAT_INV */
+#define WM8915_AIF1TX_CHAN3_SPACING_MASK        0x7E00  /* AIF1TX_CHAN3_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN3_SPACING_SHIFT            9  /* AIF1TX_CHAN3_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN3_SPACING_WIDTH            6  /* AIF1TX_CHAN3_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN3_SLOTS_MASK          0x01C0  /* AIF1TX_CHAN3_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN3_SLOTS_SHIFT              6  /* AIF1TX_CHAN3_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN3_SLOTS_WIDTH              3  /* AIF1TX_CHAN3_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN3_START_SLOT_MASK     0x003F  /* AIF1TX_CHAN3_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN3_START_SLOT_SHIFT         0  /* AIF1TX_CHAN3_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN3_START_SLOT_WIDTH         6  /* AIF1TX_CHAN3_START_SLOT - [5:0] */
+
+/*
+ * R781 (0x30D) - AIF1TX Channel 4 Configuration
+ */
+#define WM8915_AIF1TX_CHAN4_DAT_INV             0x8000  /* AIF1TX_CHAN4_DAT_INV */
+#define WM8915_AIF1TX_CHAN4_DAT_INV_MASK        0x8000  /* AIF1TX_CHAN4_DAT_INV */
+#define WM8915_AIF1TX_CHAN4_DAT_INV_SHIFT           15  /* AIF1TX_CHAN4_DAT_INV */
+#define WM8915_AIF1TX_CHAN4_DAT_INV_WIDTH            1  /* AIF1TX_CHAN4_DAT_INV */
+#define WM8915_AIF1TX_CHAN4_SPACING_MASK        0x7E00  /* AIF1TX_CHAN4_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN4_SPACING_SHIFT            9  /* AIF1TX_CHAN4_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN4_SPACING_WIDTH            6  /* AIF1TX_CHAN4_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN4_SLOTS_MASK          0x01C0  /* AIF1TX_CHAN4_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN4_SLOTS_SHIFT              6  /* AIF1TX_CHAN4_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN4_SLOTS_WIDTH              3  /* AIF1TX_CHAN4_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN4_START_SLOT_MASK     0x003F  /* AIF1TX_CHAN4_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN4_START_SLOT_SHIFT         0  /* AIF1TX_CHAN4_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN4_START_SLOT_WIDTH         6  /* AIF1TX_CHAN4_START_SLOT - [5:0] */
+
+/*
+ * R782 (0x30E) - AIF1TX Channel 5 Configuration
+ */
+#define WM8915_AIF1TX_CHAN5_DAT_INV             0x8000  /* AIF1TX_CHAN5_DAT_INV */
+#define WM8915_AIF1TX_CHAN5_DAT_INV_MASK        0x8000  /* AIF1TX_CHAN5_DAT_INV */
+#define WM8915_AIF1TX_CHAN5_DAT_INV_SHIFT           15  /* AIF1TX_CHAN5_DAT_INV */
+#define WM8915_AIF1TX_CHAN5_DAT_INV_WIDTH            1  /* AIF1TX_CHAN5_DAT_INV */
+#define WM8915_AIF1TX_CHAN5_SPACING_MASK        0x7E00  /* AIF1TX_CHAN5_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN5_SPACING_SHIFT            9  /* AIF1TX_CHAN5_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN5_SPACING_WIDTH            6  /* AIF1TX_CHAN5_SPACING - [14:9] */
+#define WM8915_AIF1TX_CHAN5_SLOTS_MASK          0x01C0  /* AIF1TX_CHAN5_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN5_SLOTS_SHIFT              6  /* AIF1TX_CHAN5_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN5_SLOTS_WIDTH              3  /* AIF1TX_CHAN5_SLOTS - [8:6] */
+#define WM8915_AIF1TX_CHAN5_START_SLOT_MASK     0x003F  /* AIF1TX_CHAN5_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN5_START_SLOT_SHIFT         0  /* AIF1TX_CHAN5_START_SLOT - [5:0] */
+#define WM8915_AIF1TX_CHAN5_START_SLOT_WIDTH         6  /* AIF1TX_CHAN5_START_SLOT - [5:0] */
+
+/*
+ * R783 (0x30F) - AIF1RX Channel 0 Configuration
+ */
+#define WM8915_AIF1RX_CHAN0_DAT_INV             0x8000  /* AIF1RX_CHAN0_DAT_INV */
+#define WM8915_AIF1RX_CHAN0_DAT_INV_MASK        0x8000  /* AIF1RX_CHAN0_DAT_INV */
+#define WM8915_AIF1RX_CHAN0_DAT_INV_SHIFT           15  /* AIF1RX_CHAN0_DAT_INV */
+#define WM8915_AIF1RX_CHAN0_DAT_INV_WIDTH            1  /* AIF1RX_CHAN0_DAT_INV */
+#define WM8915_AIF1RX_CHAN0_SPACING_MASK        0x7E00  /* AIF1RX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN0_SPACING_SHIFT            9  /* AIF1RX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN0_SPACING_WIDTH            6  /* AIF1RX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN0_SLOTS_MASK          0x01C0  /* AIF1RX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN0_SLOTS_SHIFT              6  /* AIF1RX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN0_SLOTS_WIDTH              3  /* AIF1RX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN0_START_SLOT_MASK     0x003F  /* AIF1RX_CHAN0_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN0_START_SLOT_SHIFT         0  /* AIF1RX_CHAN0_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN0_START_SLOT_WIDTH         6  /* AIF1RX_CHAN0_START_SLOT - [5:0] */
+
+/*
+ * R784 (0x310) - AIF1RX Channel 1 Configuration
+ */
+#define WM8915_AIF1RX_CHAN1_DAT_INV             0x8000  /* AIF1RX_CHAN1_DAT_INV */
+#define WM8915_AIF1RX_CHAN1_DAT_INV_MASK        0x8000  /* AIF1RX_CHAN1_DAT_INV */
+#define WM8915_AIF1RX_CHAN1_DAT_INV_SHIFT           15  /* AIF1RX_CHAN1_DAT_INV */
+#define WM8915_AIF1RX_CHAN1_DAT_INV_WIDTH            1  /* AIF1RX_CHAN1_DAT_INV */
+#define WM8915_AIF1RX_CHAN1_SPACING_MASK        0x7E00  /* AIF1RX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN1_SPACING_SHIFT            9  /* AIF1RX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN1_SPACING_WIDTH            6  /* AIF1RX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN1_SLOTS_MASK          0x01C0  /* AIF1RX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN1_SLOTS_SHIFT              6  /* AIF1RX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN1_SLOTS_WIDTH              3  /* AIF1RX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN1_START_SLOT_MASK     0x003F  /* AIF1RX_CHAN1_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN1_START_SLOT_SHIFT         0  /* AIF1RX_CHAN1_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN1_START_SLOT_WIDTH         6  /* AIF1RX_CHAN1_START_SLOT - [5:0] */
+
+/*
+ * R785 (0x311) - AIF1RX Channel 2 Configuration
+ */
+#define WM8915_AIF1RX_CHAN2_DAT_INV             0x8000  /* AIF1RX_CHAN2_DAT_INV */
+#define WM8915_AIF1RX_CHAN2_DAT_INV_MASK        0x8000  /* AIF1RX_CHAN2_DAT_INV */
+#define WM8915_AIF1RX_CHAN2_DAT_INV_SHIFT           15  /* AIF1RX_CHAN2_DAT_INV */
+#define WM8915_AIF1RX_CHAN2_DAT_INV_WIDTH            1  /* AIF1RX_CHAN2_DAT_INV */
+#define WM8915_AIF1RX_CHAN2_SPACING_MASK        0x7E00  /* AIF1RX_CHAN2_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN2_SPACING_SHIFT            9  /* AIF1RX_CHAN2_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN2_SPACING_WIDTH            6  /* AIF1RX_CHAN2_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN2_SLOTS_MASK          0x01C0  /* AIF1RX_CHAN2_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN2_SLOTS_SHIFT              6  /* AIF1RX_CHAN2_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN2_SLOTS_WIDTH              3  /* AIF1RX_CHAN2_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN2_START_SLOT_MASK     0x003F  /* AIF1RX_CHAN2_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN2_START_SLOT_SHIFT         0  /* AIF1RX_CHAN2_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN2_START_SLOT_WIDTH         6  /* AIF1RX_CHAN2_START_SLOT - [5:0] */
+
+/*
+ * R786 (0x312) - AIF1RX Channel 3 Configuration
+ */
+#define WM8915_AIF1RX_CHAN3_DAT_INV             0x8000  /* AIF1RX_CHAN3_DAT_INV */
+#define WM8915_AIF1RX_CHAN3_DAT_INV_MASK        0x8000  /* AIF1RX_CHAN3_DAT_INV */
+#define WM8915_AIF1RX_CHAN3_DAT_INV_SHIFT           15  /* AIF1RX_CHAN3_DAT_INV */
+#define WM8915_AIF1RX_CHAN3_DAT_INV_WIDTH            1  /* AIF1RX_CHAN3_DAT_INV */
+#define WM8915_AIF1RX_CHAN3_SPACING_MASK        0x7E00  /* AIF1RX_CHAN3_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN3_SPACING_SHIFT            9  /* AIF1RX_CHAN3_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN3_SPACING_WIDTH            6  /* AIF1RX_CHAN3_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN3_SLOTS_MASK          0x01C0  /* AIF1RX_CHAN3_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN3_SLOTS_SHIFT              6  /* AIF1RX_CHAN3_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN3_SLOTS_WIDTH              3  /* AIF1RX_CHAN3_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN3_START_SLOT_MASK     0x003F  /* AIF1RX_CHAN3_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN3_START_SLOT_SHIFT         0  /* AIF1RX_CHAN3_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN3_START_SLOT_WIDTH         6  /* AIF1RX_CHAN3_START_SLOT - [5:0] */
+
+/*
+ * R787 (0x313) - AIF1RX Channel 4 Configuration
+ */
+#define WM8915_AIF1RX_CHAN4_DAT_INV             0x8000  /* AIF1RX_CHAN4_DAT_INV */
+#define WM8915_AIF1RX_CHAN4_DAT_INV_MASK        0x8000  /* AIF1RX_CHAN4_DAT_INV */
+#define WM8915_AIF1RX_CHAN4_DAT_INV_SHIFT           15  /* AIF1RX_CHAN4_DAT_INV */
+#define WM8915_AIF1RX_CHAN4_DAT_INV_WIDTH            1  /* AIF1RX_CHAN4_DAT_INV */
+#define WM8915_AIF1RX_CHAN4_SPACING_MASK        0x7E00  /* AIF1RX_CHAN4_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN4_SPACING_SHIFT            9  /* AIF1RX_CHAN4_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN4_SPACING_WIDTH            6  /* AIF1RX_CHAN4_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN4_SLOTS_MASK          0x01C0  /* AIF1RX_CHAN4_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN4_SLOTS_SHIFT              6  /* AIF1RX_CHAN4_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN4_SLOTS_WIDTH              3  /* AIF1RX_CHAN4_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN4_START_SLOT_MASK     0x003F  /* AIF1RX_CHAN4_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN4_START_SLOT_SHIFT         0  /* AIF1RX_CHAN4_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN4_START_SLOT_WIDTH         6  /* AIF1RX_CHAN4_START_SLOT - [5:0] */
+
+/*
+ * R788 (0x314) - AIF1RX Channel 5 Configuration
+ */
+#define WM8915_AIF1RX_CHAN5_DAT_INV             0x8000  /* AIF1RX_CHAN5_DAT_INV */
+#define WM8915_AIF1RX_CHAN5_DAT_INV_MASK        0x8000  /* AIF1RX_CHAN5_DAT_INV */
+#define WM8915_AIF1RX_CHAN5_DAT_INV_SHIFT           15  /* AIF1RX_CHAN5_DAT_INV */
+#define WM8915_AIF1RX_CHAN5_DAT_INV_WIDTH            1  /* AIF1RX_CHAN5_DAT_INV */
+#define WM8915_AIF1RX_CHAN5_SPACING_MASK        0x7E00  /* AIF1RX_CHAN5_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN5_SPACING_SHIFT            9  /* AIF1RX_CHAN5_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN5_SPACING_WIDTH            6  /* AIF1RX_CHAN5_SPACING - [14:9] */
+#define WM8915_AIF1RX_CHAN5_SLOTS_MASK          0x01C0  /* AIF1RX_CHAN5_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN5_SLOTS_SHIFT              6  /* AIF1RX_CHAN5_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN5_SLOTS_WIDTH              3  /* AIF1RX_CHAN5_SLOTS - [8:6] */
+#define WM8915_AIF1RX_CHAN5_START_SLOT_MASK     0x003F  /* AIF1RX_CHAN5_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN5_START_SLOT_SHIFT         0  /* AIF1RX_CHAN5_START_SLOT - [5:0] */
+#define WM8915_AIF1RX_CHAN5_START_SLOT_WIDTH         6  /* AIF1RX_CHAN5_START_SLOT - [5:0] */
+
+/*
+ * R789 (0x315) - AIF1RX Mono Configuration
+ */
+#define WM8915_AIF1RX_CHAN4_MONO_MODE           0x0004  /* AIF1RX_CHAN4_MONO_MODE */
+#define WM8915_AIF1RX_CHAN4_MONO_MODE_MASK      0x0004  /* AIF1RX_CHAN4_MONO_MODE */
+#define WM8915_AIF1RX_CHAN4_MONO_MODE_SHIFT          2  /* AIF1RX_CHAN4_MONO_MODE */
+#define WM8915_AIF1RX_CHAN4_MONO_MODE_WIDTH          1  /* AIF1RX_CHAN4_MONO_MODE */
+#define WM8915_AIF1RX_CHAN2_MONO_MODE           0x0002  /* AIF1RX_CHAN2_MONO_MODE */
+#define WM8915_AIF1RX_CHAN2_MONO_MODE_MASK      0x0002  /* AIF1RX_CHAN2_MONO_MODE */
+#define WM8915_AIF1RX_CHAN2_MONO_MODE_SHIFT          1  /* AIF1RX_CHAN2_MONO_MODE */
+#define WM8915_AIF1RX_CHAN2_MONO_MODE_WIDTH          1  /* AIF1RX_CHAN2_MONO_MODE */
+#define WM8915_AIF1RX_CHAN0_MONO_MODE           0x0001  /* AIF1RX_CHAN0_MONO_MODE */
+#define WM8915_AIF1RX_CHAN0_MONO_MODE_MASK      0x0001  /* AIF1RX_CHAN0_MONO_MODE */
+#define WM8915_AIF1RX_CHAN0_MONO_MODE_SHIFT          0  /* AIF1RX_CHAN0_MONO_MODE */
+#define WM8915_AIF1RX_CHAN0_MONO_MODE_WIDTH          1  /* AIF1RX_CHAN0_MONO_MODE */
+
+/*
+ * R794 (0x31A) - AIF1TX Test
+ */
+#define WM8915_AIF1TX45_DITHER_ENA              0x0004  /* AIF1TX45_DITHER_ENA */
+#define WM8915_AIF1TX45_DITHER_ENA_MASK         0x0004  /* AIF1TX45_DITHER_ENA */
+#define WM8915_AIF1TX45_DITHER_ENA_SHIFT             2  /* AIF1TX45_DITHER_ENA */
+#define WM8915_AIF1TX45_DITHER_ENA_WIDTH             1  /* AIF1TX45_DITHER_ENA */
+#define WM8915_AIF1TX23_DITHER_ENA              0x0002  /* AIF1TX23_DITHER_ENA */
+#define WM8915_AIF1TX23_DITHER_ENA_MASK         0x0002  /* AIF1TX23_DITHER_ENA */
+#define WM8915_AIF1TX23_DITHER_ENA_SHIFT             1  /* AIF1TX23_DITHER_ENA */
+#define WM8915_AIF1TX23_DITHER_ENA_WIDTH             1  /* AIF1TX23_DITHER_ENA */
+#define WM8915_AIF1TX01_DITHER_ENA              0x0001  /* AIF1TX01_DITHER_ENA */
+#define WM8915_AIF1TX01_DITHER_ENA_MASK         0x0001  /* AIF1TX01_DITHER_ENA */
+#define WM8915_AIF1TX01_DITHER_ENA_SHIFT             0  /* AIF1TX01_DITHER_ENA */
+#define WM8915_AIF1TX01_DITHER_ENA_WIDTH             1  /* AIF1TX01_DITHER_ENA */
+
+/*
+ * R800 (0x320) - AIF2 Control
+ */
+#define WM8915_AIF2_TRI                         0x0004  /* AIF2_TRI */
+#define WM8915_AIF2_TRI_MASK                    0x0004  /* AIF2_TRI */
+#define WM8915_AIF2_TRI_SHIFT                        2  /* AIF2_TRI */
+#define WM8915_AIF2_TRI_WIDTH                        1  /* AIF2_TRI */
+#define WM8915_AIF2_FMT_MASK                    0x0003  /* AIF2_FMT - [1:0] */
+#define WM8915_AIF2_FMT_SHIFT                        0  /* AIF2_FMT - [1:0] */
+#define WM8915_AIF2_FMT_WIDTH                        2  /* AIF2_FMT - [1:0] */
+
+/*
+ * R801 (0x321) - AIF2 BCLK
+ */
+#define WM8915_AIF2_BCLK_INV                    0x0400  /* AIF2_BCLK_INV */
+#define WM8915_AIF2_BCLK_INV_MASK               0x0400  /* AIF2_BCLK_INV */
+#define WM8915_AIF2_BCLK_INV_SHIFT                  10  /* AIF2_BCLK_INV */
+#define WM8915_AIF2_BCLK_INV_WIDTH                   1  /* AIF2_BCLK_INV */
+#define WM8915_AIF2_BCLK_FRC                    0x0200  /* AIF2_BCLK_FRC */
+#define WM8915_AIF2_BCLK_FRC_MASK               0x0200  /* AIF2_BCLK_FRC */
+#define WM8915_AIF2_BCLK_FRC_SHIFT                   9  /* AIF2_BCLK_FRC */
+#define WM8915_AIF2_BCLK_FRC_WIDTH                   1  /* AIF2_BCLK_FRC */
+#define WM8915_AIF2_BCLK_MSTR                   0x0100  /* AIF2_BCLK_MSTR */
+#define WM8915_AIF2_BCLK_MSTR_MASK              0x0100  /* AIF2_BCLK_MSTR */
+#define WM8915_AIF2_BCLK_MSTR_SHIFT                  8  /* AIF2_BCLK_MSTR */
+#define WM8915_AIF2_BCLK_MSTR_WIDTH                  1  /* AIF2_BCLK_MSTR */
+#define WM8915_AIF2_BCLK_DIV_MASK               0x000F  /* AIF2_BCLK_DIV - [3:0] */
+#define WM8915_AIF2_BCLK_DIV_SHIFT                   0  /* AIF2_BCLK_DIV - [3:0] */
+#define WM8915_AIF2_BCLK_DIV_WIDTH                   4  /* AIF2_BCLK_DIV - [3:0] */
+
+/*
+ * R802 (0x322) - AIF2 TX LRCLK(1)
+ */
+#define WM8915_AIF2TX_RATE_MASK                 0x07FF  /* AIF2TX_RATE - [10:0] */
+#define WM8915_AIF2TX_RATE_SHIFT                     0  /* AIF2TX_RATE - [10:0] */
+#define WM8915_AIF2TX_RATE_WIDTH                    11  /* AIF2TX_RATE - [10:0] */
+
+/*
+ * R803 (0x323) - AIF2 TX LRCLK(2)
+ */
+#define WM8915_AIF2TX_LRCLK_MODE                0x0008  /* AIF2TX_LRCLK_MODE */
+#define WM8915_AIF2TX_LRCLK_MODE_MASK           0x0008  /* AIF2TX_LRCLK_MODE */
+#define WM8915_AIF2TX_LRCLK_MODE_SHIFT               3  /* AIF2TX_LRCLK_MODE */
+#define WM8915_AIF2TX_LRCLK_MODE_WIDTH               1  /* AIF2TX_LRCLK_MODE */
+#define WM8915_AIF2TX_LRCLK_INV                 0x0004  /* AIF2TX_LRCLK_INV */
+#define WM8915_AIF2TX_LRCLK_INV_MASK            0x0004  /* AIF2TX_LRCLK_INV */
+#define WM8915_AIF2TX_LRCLK_INV_SHIFT                2  /* AIF2TX_LRCLK_INV */
+#define WM8915_AIF2TX_LRCLK_INV_WIDTH                1  /* AIF2TX_LRCLK_INV */
+#define WM8915_AIF2TX_LRCLK_FRC                 0x0002  /* AIF2TX_LRCLK_FRC */
+#define WM8915_AIF2TX_LRCLK_FRC_MASK            0x0002  /* AIF2TX_LRCLK_FRC */
+#define WM8915_AIF2TX_LRCLK_FRC_SHIFT                1  /* AIF2TX_LRCLK_FRC */
+#define WM8915_AIF2TX_LRCLK_FRC_WIDTH                1  /* AIF2TX_LRCLK_FRC */
+#define WM8915_AIF2TX_LRCLK_MSTR                0x0001  /* AIF2TX_LRCLK_MSTR */
+#define WM8915_AIF2TX_LRCLK_MSTR_MASK           0x0001  /* AIF2TX_LRCLK_MSTR */
+#define WM8915_AIF2TX_LRCLK_MSTR_SHIFT               0  /* AIF2TX_LRCLK_MSTR */
+#define WM8915_AIF2TX_LRCLK_MSTR_WIDTH               1  /* AIF2TX_LRCLK_MSTR */
+
+/*
+ * R804 (0x324) - AIF2 RX LRCLK(1)
+ */
+#define WM8915_AIF2RX_RATE_MASK                 0x07FF  /* AIF2RX_RATE - [10:0] */
+#define WM8915_AIF2RX_RATE_SHIFT                     0  /* AIF2RX_RATE - [10:0] */
+#define WM8915_AIF2RX_RATE_WIDTH                    11  /* AIF2RX_RATE - [10:0] */
+
+/*
+ * R805 (0x325) - AIF2 RX LRCLK(2)
+ */
+#define WM8915_AIF2RX_LRCLK_INV                 0x0004  /* AIF2RX_LRCLK_INV */
+#define WM8915_AIF2RX_LRCLK_INV_MASK            0x0004  /* AIF2RX_LRCLK_INV */
+#define WM8915_AIF2RX_LRCLK_INV_SHIFT                2  /* AIF2RX_LRCLK_INV */
+#define WM8915_AIF2RX_LRCLK_INV_WIDTH                1  /* AIF2RX_LRCLK_INV */
+#define WM8915_AIF2RX_LRCLK_FRC                 0x0002  /* AIF2RX_LRCLK_FRC */
+#define WM8915_AIF2RX_LRCLK_FRC_MASK            0x0002  /* AIF2RX_LRCLK_FRC */
+#define WM8915_AIF2RX_LRCLK_FRC_SHIFT                1  /* AIF2RX_LRCLK_FRC */
+#define WM8915_AIF2RX_LRCLK_FRC_WIDTH                1  /* AIF2RX_LRCLK_FRC */
+#define WM8915_AIF2RX_LRCLK_MSTR                0x0001  /* AIF2RX_LRCLK_MSTR */
+#define WM8915_AIF2RX_LRCLK_MSTR_MASK           0x0001  /* AIF2RX_LRCLK_MSTR */
+#define WM8915_AIF2RX_LRCLK_MSTR_SHIFT               0  /* AIF2RX_LRCLK_MSTR */
+#define WM8915_AIF2RX_LRCLK_MSTR_WIDTH               1  /* AIF2RX_LRCLK_MSTR */
+
+/*
+ * R806 (0x326) - AIF2TX Data Configuration (1)
+ */
+#define WM8915_AIF2TX_WL_MASK                   0xFF00  /* AIF2TX_WL - [15:8] */
+#define WM8915_AIF2TX_WL_SHIFT                       8  /* AIF2TX_WL - [15:8] */
+#define WM8915_AIF2TX_WL_WIDTH                       8  /* AIF2TX_WL - [15:8] */
+#define WM8915_AIF2TX_SLOT_LEN_MASK             0x00FF  /* AIF2TX_SLOT_LEN - [7:0] */
+#define WM8915_AIF2TX_SLOT_LEN_SHIFT                 0  /* AIF2TX_SLOT_LEN - [7:0] */
+#define WM8915_AIF2TX_SLOT_LEN_WIDTH                 8  /* AIF2TX_SLOT_LEN - [7:0] */
+
+/*
+ * R807 (0x327) - AIF2TX Data Configuration (2)
+ */
+#define WM8915_AIF2TX_DAT_TRI                   0x0001  /* AIF2TX_DAT_TRI */
+#define WM8915_AIF2TX_DAT_TRI_MASK              0x0001  /* AIF2TX_DAT_TRI */
+#define WM8915_AIF2TX_DAT_TRI_SHIFT                  0  /* AIF2TX_DAT_TRI */
+#define WM8915_AIF2TX_DAT_TRI_WIDTH                  1  /* AIF2TX_DAT_TRI */
+
+/*
+ * R808 (0x328) - AIF2RX Data Configuration
+ */
+#define WM8915_AIF2RX_WL_MASK                   0xFF00  /* AIF2RX_WL - [15:8] */
+#define WM8915_AIF2RX_WL_SHIFT                       8  /* AIF2RX_WL - [15:8] */
+#define WM8915_AIF2RX_WL_WIDTH                       8  /* AIF2RX_WL - [15:8] */
+#define WM8915_AIF2RX_SLOT_LEN_MASK             0x00FF  /* AIF2RX_SLOT_LEN - [7:0] */
+#define WM8915_AIF2RX_SLOT_LEN_SHIFT                 0  /* AIF2RX_SLOT_LEN - [7:0] */
+#define WM8915_AIF2RX_SLOT_LEN_WIDTH                 8  /* AIF2RX_SLOT_LEN - [7:0] */
+
+/*
+ * R809 (0x329) - AIF2TX Channel 0 Configuration
+ */
+#define WM8915_AIF2TX_CHAN0_DAT_INV             0x8000  /* AIF2TX_CHAN0_DAT_INV */
+#define WM8915_AIF2TX_CHAN0_DAT_INV_MASK        0x8000  /* AIF2TX_CHAN0_DAT_INV */
+#define WM8915_AIF2TX_CHAN0_DAT_INV_SHIFT           15  /* AIF2TX_CHAN0_DAT_INV */
+#define WM8915_AIF2TX_CHAN0_DAT_INV_WIDTH            1  /* AIF2TX_CHAN0_DAT_INV */
+#define WM8915_AIF2TX_CHAN0_SPACING_MASK        0x7E00  /* AIF2TX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF2TX_CHAN0_SPACING_SHIFT            9  /* AIF2TX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF2TX_CHAN0_SPACING_WIDTH            6  /* AIF2TX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF2TX_CHAN0_SLOTS_MASK          0x01C0  /* AIF2TX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF2TX_CHAN0_SLOTS_SHIFT              6  /* AIF2TX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF2TX_CHAN0_SLOTS_WIDTH              3  /* AIF2TX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF2TX_CHAN0_START_SLOT_MASK     0x003F  /* AIF2TX_CHAN0_START_SLOT - [5:0] */
+#define WM8915_AIF2TX_CHAN0_START_SLOT_SHIFT         0  /* AIF2TX_CHAN0_START_SLOT - [5:0] */
+#define WM8915_AIF2TX_CHAN0_START_SLOT_WIDTH         6  /* AIF2TX_CHAN0_START_SLOT - [5:0] */
+
+/*
+ * R810 (0x32A) - AIF2TX Channel 1 Configuration
+ */
+#define WM8915_AIF2TX_CHAN1_DAT_INV             0x8000  /* AIF2TX_CHAN1_DAT_INV */
+#define WM8915_AIF2TX_CHAN1_DAT_INV_MASK        0x8000  /* AIF2TX_CHAN1_DAT_INV */
+#define WM8915_AIF2TX_CHAN1_DAT_INV_SHIFT           15  /* AIF2TX_CHAN1_DAT_INV */
+#define WM8915_AIF2TX_CHAN1_DAT_INV_WIDTH            1  /* AIF2TX_CHAN1_DAT_INV */
+#define WM8915_AIF2TX_CHAN1_SPACING_MASK        0x7E00  /* AIF2TX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF2TX_CHAN1_SPACING_SHIFT            9  /* AIF2TX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF2TX_CHAN1_SPACING_WIDTH            6  /* AIF2TX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF2TX_CHAN1_SLOTS_MASK          0x01C0  /* AIF2TX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF2TX_CHAN1_SLOTS_SHIFT              6  /* AIF2TX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF2TX_CHAN1_SLOTS_WIDTH              3  /* AIF2TX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF2TX_CHAN1_START_SLOT_MASK     0x003F  /* AIF2TX_CHAN1_START_SLOT - [5:0] */
+#define WM8915_AIF2TX_CHAN1_START_SLOT_SHIFT         0  /* AIF2TX_CHAN1_START_SLOT - [5:0] */
+#define WM8915_AIF2TX_CHAN1_START_SLOT_WIDTH         6  /* AIF2TX_CHAN1_START_SLOT - [5:0] */
+
+/*
+ * R811 (0x32B) - AIF2RX Channel 0 Configuration
+ */
+#define WM8915_AIF2RX_CHAN0_DAT_INV             0x8000  /* AIF2RX_CHAN0_DAT_INV */
+#define WM8915_AIF2RX_CHAN0_DAT_INV_MASK        0x8000  /* AIF2RX_CHAN0_DAT_INV */
+#define WM8915_AIF2RX_CHAN0_DAT_INV_SHIFT           15  /* AIF2RX_CHAN0_DAT_INV */
+#define WM8915_AIF2RX_CHAN0_DAT_INV_WIDTH            1  /* AIF2RX_CHAN0_DAT_INV */
+#define WM8915_AIF2RX_CHAN0_SPACING_MASK        0x7E00  /* AIF2RX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF2RX_CHAN0_SPACING_SHIFT            9  /* AIF2RX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF2RX_CHAN0_SPACING_WIDTH            6  /* AIF2RX_CHAN0_SPACING - [14:9] */
+#define WM8915_AIF2RX_CHAN0_SLOTS_MASK          0x01C0  /* AIF2RX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF2RX_CHAN0_SLOTS_SHIFT              6  /* AIF2RX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF2RX_CHAN0_SLOTS_WIDTH              3  /* AIF2RX_CHAN0_SLOTS - [8:6] */
+#define WM8915_AIF2RX_CHAN0_START_SLOT_MASK     0x003F  /* AIF2RX_CHAN0_START_SLOT - [5:0] */
+#define WM8915_AIF2RX_CHAN0_START_SLOT_SHIFT         0  /* AIF2RX_CHAN0_START_SLOT - [5:0] */
+#define WM8915_AIF2RX_CHAN0_START_SLOT_WIDTH         6  /* AIF2RX_CHAN0_START_SLOT - [5:0] */
+
+/*
+ * R812 (0x32C) - AIF2RX Channel 1 Configuration
+ */
+#define WM8915_AIF2RX_CHAN1_DAT_INV             0x8000  /* AIF2RX_CHAN1_DAT_INV */
+#define WM8915_AIF2RX_CHAN1_DAT_INV_MASK        0x8000  /* AIF2RX_CHAN1_DAT_INV */
+#define WM8915_AIF2RX_CHAN1_DAT_INV_SHIFT           15  /* AIF2RX_CHAN1_DAT_INV */
+#define WM8915_AIF2RX_CHAN1_DAT_INV_WIDTH            1  /* AIF2RX_CHAN1_DAT_INV */
+#define WM8915_AIF2RX_CHAN1_SPACING_MASK        0x7E00  /* AIF2RX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF2RX_CHAN1_SPACING_SHIFT            9  /* AIF2RX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF2RX_CHAN1_SPACING_WIDTH            6  /* AIF2RX_CHAN1_SPACING - [14:9] */
+#define WM8915_AIF2RX_CHAN1_SLOTS_MASK          0x01C0  /* AIF2RX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF2RX_CHAN1_SLOTS_SHIFT              6  /* AIF2RX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF2RX_CHAN1_SLOTS_WIDTH              3  /* AIF2RX_CHAN1_SLOTS - [8:6] */
+#define WM8915_AIF2RX_CHAN1_START_SLOT_MASK     0x003F  /* AIF2RX_CHAN1_START_SLOT - [5:0] */
+#define WM8915_AIF2RX_CHAN1_START_SLOT_SHIFT         0  /* AIF2RX_CHAN1_START_SLOT - [5:0] */
+#define WM8915_AIF2RX_CHAN1_START_SLOT_WIDTH         6  /* AIF2RX_CHAN1_START_SLOT - [5:0] */
+
+/*
+ * R813 (0x32D) - AIF2RX Mono Configuration
+ */
+#define WM8915_AIF2RX_CHAN0_MONO_MODE           0x0001  /* AIF2RX_CHAN0_MONO_MODE */
+#define WM8915_AIF2RX_CHAN0_MONO_MODE_MASK      0x0001  /* AIF2RX_CHAN0_MONO_MODE */
+#define WM8915_AIF2RX_CHAN0_MONO_MODE_SHIFT          0  /* AIF2RX_CHAN0_MONO_MODE */
+#define WM8915_AIF2RX_CHAN0_MONO_MODE_WIDTH          1  /* AIF2RX_CHAN0_MONO_MODE */
+
+/*
+ * R815 (0x32F) - AIF2TX Test
+ */
+#define WM8915_AIF2TX_DITHER_ENA                0x0001  /* AIF2TX_DITHER_ENA */
+#define WM8915_AIF2TX_DITHER_ENA_MASK           0x0001  /* AIF2TX_DITHER_ENA */
+#define WM8915_AIF2TX_DITHER_ENA_SHIFT               0  /* AIF2TX_DITHER_ENA */
+#define WM8915_AIF2TX_DITHER_ENA_WIDTH               1  /* AIF2TX_DITHER_ENA */
+
+/*
+ * R1024 (0x400) - DSP1 TX Left Volume
+ */
+#define WM8915_DSP1TX_VU                        0x0100  /* DSP1TX_VU */
+#define WM8915_DSP1TX_VU_MASK                   0x0100  /* DSP1TX_VU */
+#define WM8915_DSP1TX_VU_SHIFT                       8  /* DSP1TX_VU */
+#define WM8915_DSP1TX_VU_WIDTH                       1  /* DSP1TX_VU */
+#define WM8915_DSP1TXL_VOL_MASK                 0x00FF  /* DSP1TXL_VOL - [7:0] */
+#define WM8915_DSP1TXL_VOL_SHIFT                     0  /* DSP1TXL_VOL - [7:0] */
+#define WM8915_DSP1TXL_VOL_WIDTH                     8  /* DSP1TXL_VOL - [7:0] */
+
+/*
+ * R1025 (0x401) - DSP1 TX Right Volume
+ */
+#define WM8915_DSP1TX_VU                        0x0100  /* DSP1TX_VU */
+#define WM8915_DSP1TX_VU_MASK                   0x0100  /* DSP1TX_VU */
+#define WM8915_DSP1TX_VU_SHIFT                       8  /* DSP1TX_VU */
+#define WM8915_DSP1TX_VU_WIDTH                       1  /* DSP1TX_VU */
+#define WM8915_DSP1TXR_VOL_MASK                 0x00FF  /* DSP1TXR_VOL - [7:0] */
+#define WM8915_DSP1TXR_VOL_SHIFT                     0  /* DSP1TXR_VOL - [7:0] */
+#define WM8915_DSP1TXR_VOL_WIDTH                     8  /* DSP1TXR_VOL - [7:0] */
+
+/*
+ * R1026 (0x402) - DSP1 RX Left Volume
+ */
+#define WM8915_DSP1RX_VU                        0x0100  /* DSP1RX_VU */
+#define WM8915_DSP1RX_VU_MASK                   0x0100  /* DSP1RX_VU */
+#define WM8915_DSP1RX_VU_SHIFT                       8  /* DSP1RX_VU */
+#define WM8915_DSP1RX_VU_WIDTH                       1  /* DSP1RX_VU */
+#define WM8915_DSP1RXL_VOL_MASK                 0x00FF  /* DSP1RXL_VOL - [7:0] */
+#define WM8915_DSP1RXL_VOL_SHIFT                     0  /* DSP1RXL_VOL - [7:0] */
+#define WM8915_DSP1RXL_VOL_WIDTH                     8  /* DSP1RXL_VOL - [7:0] */
+
+/*
+ * R1027 (0x403) - DSP1 RX Right Volume
+ */
+#define WM8915_DSP1RX_VU                        0x0100  /* DSP1RX_VU */
+#define WM8915_DSP1RX_VU_MASK                   0x0100  /* DSP1RX_VU */
+#define WM8915_DSP1RX_VU_SHIFT                       8  /* DSP1RX_VU */
+#define WM8915_DSP1RX_VU_WIDTH                       1  /* DSP1RX_VU */
+#define WM8915_DSP1RXR_VOL_MASK                 0x00FF  /* DSP1RXR_VOL - [7:0] */
+#define WM8915_DSP1RXR_VOL_SHIFT                     0  /* DSP1RXR_VOL - [7:0] */
+#define WM8915_DSP1RXR_VOL_WIDTH                     8  /* DSP1RXR_VOL - [7:0] */
+
+/*
+ * R1040 (0x410) - DSP1 TX Filters
+ */
+#define WM8915_DSP1TX_NF                        0x2000  /* DSP1TX_NF */
+#define WM8915_DSP1TX_NF_MASK                   0x2000  /* DSP1TX_NF */
+#define WM8915_DSP1TX_NF_SHIFT                      13  /* DSP1TX_NF */
+#define WM8915_DSP1TX_NF_WIDTH                       1  /* DSP1TX_NF */
+#define WM8915_DSP1TXL_HPF                      0x1000  /* DSP1TXL_HPF */
+#define WM8915_DSP1TXL_HPF_MASK                 0x1000  /* DSP1TXL_HPF */
+#define WM8915_DSP1TXL_HPF_SHIFT                    12  /* DSP1TXL_HPF */
+#define WM8915_DSP1TXL_HPF_WIDTH                     1  /* DSP1TXL_HPF */
+#define WM8915_DSP1TXR_HPF                      0x0800  /* DSP1TXR_HPF */
+#define WM8915_DSP1TXR_HPF_MASK                 0x0800  /* DSP1TXR_HPF */
+#define WM8915_DSP1TXR_HPF_SHIFT                    11  /* DSP1TXR_HPF */
+#define WM8915_DSP1TXR_HPF_WIDTH                     1  /* DSP1TXR_HPF */
+#define WM8915_DSP1TX_HPF_MODE_MASK             0x0018  /* DSP1TX_HPF_MODE - [4:3] */
+#define WM8915_DSP1TX_HPF_MODE_SHIFT                 3  /* DSP1TX_HPF_MODE - [4:3] */
+#define WM8915_DSP1TX_HPF_MODE_WIDTH                 2  /* DSP1TX_HPF_MODE - [4:3] */
+#define WM8915_DSP1TX_HPF_CUT_MASK              0x0007  /* DSP1TX_HPF_CUT - [2:0] */
+#define WM8915_DSP1TX_HPF_CUT_SHIFT                  0  /* DSP1TX_HPF_CUT - [2:0] */
+#define WM8915_DSP1TX_HPF_CUT_WIDTH                  3  /* DSP1TX_HPF_CUT - [2:0] */
+
+/*
+ * R1056 (0x420) - DSP1 RX Filters (1)
+ */
+#define WM8915_DSP1RX_MUTE                      0x0200  /* DSP1RX_MUTE */
+#define WM8915_DSP1RX_MUTE_MASK                 0x0200  /* DSP1RX_MUTE */
+#define WM8915_DSP1RX_MUTE_SHIFT                     9  /* DSP1RX_MUTE */
+#define WM8915_DSP1RX_MUTE_WIDTH                     1  /* DSP1RX_MUTE */
+#define WM8915_DSP1RX_MONO                      0x0080  /* DSP1RX_MONO */
+#define WM8915_DSP1RX_MONO_MASK                 0x0080  /* DSP1RX_MONO */
+#define WM8915_DSP1RX_MONO_SHIFT                     7  /* DSP1RX_MONO */
+#define WM8915_DSP1RX_MONO_WIDTH                     1  /* DSP1RX_MONO */
+#define WM8915_DSP1RX_MUTERATE                  0x0020  /* DSP1RX_MUTERATE */
+#define WM8915_DSP1RX_MUTERATE_MASK             0x0020  /* DSP1RX_MUTERATE */
+#define WM8915_DSP1RX_MUTERATE_SHIFT                 5  /* DSP1RX_MUTERATE */
+#define WM8915_DSP1RX_MUTERATE_WIDTH                 1  /* DSP1RX_MUTERATE */
+#define WM8915_DSP1RX_UNMUTE_RAMP               0x0010  /* DSP1RX_UNMUTE_RAMP */
+#define WM8915_DSP1RX_UNMUTE_RAMP_MASK          0x0010  /* DSP1RX_UNMUTE_RAMP */
+#define WM8915_DSP1RX_UNMUTE_RAMP_SHIFT              4  /* DSP1RX_UNMUTE_RAMP */
+#define WM8915_DSP1RX_UNMUTE_RAMP_WIDTH              1  /* DSP1RX_UNMUTE_RAMP */
+
+/*
+ * R1057 (0x421) - DSP1 RX Filters (2)
+ */
+#define WM8915_DSP1RX_3D_GAIN_MASK              0x3E00  /* DSP1RX_3D_GAIN - [13:9] */
+#define WM8915_DSP1RX_3D_GAIN_SHIFT                  9  /* DSP1RX_3D_GAIN - [13:9] */
+#define WM8915_DSP1RX_3D_GAIN_WIDTH                  5  /* DSP1RX_3D_GAIN - [13:9] */
+#define WM8915_DSP1RX_3D_ENA                    0x0100  /* DSP1RX_3D_ENA */
+#define WM8915_DSP1RX_3D_ENA_MASK               0x0100  /* DSP1RX_3D_ENA */
+#define WM8915_DSP1RX_3D_ENA_SHIFT                   8  /* DSP1RX_3D_ENA */
+#define WM8915_DSP1RX_3D_ENA_WIDTH                   1  /* DSP1RX_3D_ENA */
+
+/*
+ * R1088 (0x440) - DSP1 DRC (1)
+ */
+#define WM8915_DSP1DRC_SIG_DET_RMS_MASK         0xF800  /* DSP1DRC_SIG_DET_RMS - [15:11] */
+#define WM8915_DSP1DRC_SIG_DET_RMS_SHIFT            11  /* DSP1DRC_SIG_DET_RMS - [15:11] */
+#define WM8915_DSP1DRC_SIG_DET_RMS_WIDTH             5  /* DSP1DRC_SIG_DET_RMS - [15:11] */
+#define WM8915_DSP1DRC_SIG_DET_PK_MASK          0x0600  /* DSP1DRC_SIG_DET_PK - [10:9] */
+#define WM8915_DSP1DRC_SIG_DET_PK_SHIFT              9  /* DSP1DRC_SIG_DET_PK - [10:9] */
+#define WM8915_DSP1DRC_SIG_DET_PK_WIDTH              2  /* DSP1DRC_SIG_DET_PK - [10:9] */
+#define WM8915_DSP1DRC_NG_ENA                   0x0100  /* DSP1DRC_NG_ENA */
+#define WM8915_DSP1DRC_NG_ENA_MASK              0x0100  /* DSP1DRC_NG_ENA */
+#define WM8915_DSP1DRC_NG_ENA_SHIFT                  8  /* DSP1DRC_NG_ENA */
+#define WM8915_DSP1DRC_NG_ENA_WIDTH                  1  /* DSP1DRC_NG_ENA */
+#define WM8915_DSP1DRC_SIG_DET_MODE             0x0080  /* DSP1DRC_SIG_DET_MODE */
+#define WM8915_DSP1DRC_SIG_DET_MODE_MASK        0x0080  /* DSP1DRC_SIG_DET_MODE */
+#define WM8915_DSP1DRC_SIG_DET_MODE_SHIFT            7  /* DSP1DRC_SIG_DET_MODE */
+#define WM8915_DSP1DRC_SIG_DET_MODE_WIDTH            1  /* DSP1DRC_SIG_DET_MODE */
+#define WM8915_DSP1DRC_SIG_DET                  0x0040  /* DSP1DRC_SIG_DET */
+#define WM8915_DSP1DRC_SIG_DET_MASK             0x0040  /* DSP1DRC_SIG_DET */
+#define WM8915_DSP1DRC_SIG_DET_SHIFT                 6  /* DSP1DRC_SIG_DET */
+#define WM8915_DSP1DRC_SIG_DET_WIDTH                 1  /* DSP1DRC_SIG_DET */
+#define WM8915_DSP1DRC_KNEE2_OP_ENA             0x0020  /* DSP1DRC_KNEE2_OP_ENA */
+#define WM8915_DSP1DRC_KNEE2_OP_ENA_MASK        0x0020  /* DSP1DRC_KNEE2_OP_ENA */
+#define WM8915_DSP1DRC_KNEE2_OP_ENA_SHIFT            5  /* DSP1DRC_KNEE2_OP_ENA */
+#define WM8915_DSP1DRC_KNEE2_OP_ENA_WIDTH            1  /* DSP1DRC_KNEE2_OP_ENA */
+#define WM8915_DSP1DRC_QR                       0x0010  /* DSP1DRC_QR */
+#define WM8915_DSP1DRC_QR_MASK                  0x0010  /* DSP1DRC_QR */
+#define WM8915_DSP1DRC_QR_SHIFT                      4  /* DSP1DRC_QR */
+#define WM8915_DSP1DRC_QR_WIDTH                      1  /* DSP1DRC_QR */
+#define WM8915_DSP1DRC_ANTICLIP                 0x0008  /* DSP1DRC_ANTICLIP */
+#define WM8915_DSP1DRC_ANTICLIP_MASK            0x0008  /* DSP1DRC_ANTICLIP */
+#define WM8915_DSP1DRC_ANTICLIP_SHIFT                3  /* DSP1DRC_ANTICLIP */
+#define WM8915_DSP1DRC_ANTICLIP_WIDTH                1  /* DSP1DRC_ANTICLIP */
+#define WM8915_DSP1RX_DRC_ENA                   0x0004  /* DSP1RX_DRC_ENA */
+#define WM8915_DSP1RX_DRC_ENA_MASK              0x0004  /* DSP1RX_DRC_ENA */
+#define WM8915_DSP1RX_DRC_ENA_SHIFT                  2  /* DSP1RX_DRC_ENA */
+#define WM8915_DSP1RX_DRC_ENA_WIDTH                  1  /* DSP1RX_DRC_ENA */
+#define WM8915_DSP1TXL_DRC_ENA                  0x0002  /* DSP1TXL_DRC_ENA */
+#define WM8915_DSP1TXL_DRC_ENA_MASK             0x0002  /* DSP1TXL_DRC_ENA */
+#define WM8915_DSP1TXL_DRC_ENA_SHIFT                 1  /* DSP1TXL_DRC_ENA */
+#define WM8915_DSP1TXL_DRC_ENA_WIDTH                 1  /* DSP1TXL_DRC_ENA */
+#define WM8915_DSP1TXR_DRC_ENA                  0x0001  /* DSP1TXR_DRC_ENA */
+#define WM8915_DSP1TXR_DRC_ENA_MASK             0x0001  /* DSP1TXR_DRC_ENA */
+#define WM8915_DSP1TXR_DRC_ENA_SHIFT                 0  /* DSP1TXR_DRC_ENA */
+#define WM8915_DSP1TXR_DRC_ENA_WIDTH                 1  /* DSP1TXR_DRC_ENA */
+
+/*
+ * R1089 (0x441) - DSP1 DRC (2)
+ */
+#define WM8915_DSP1DRC_ATK_MASK                 0x1E00  /* DSP1DRC_ATK - [12:9] */
+#define WM8915_DSP1DRC_ATK_SHIFT                     9  /* DSP1DRC_ATK - [12:9] */
+#define WM8915_DSP1DRC_ATK_WIDTH                     4  /* DSP1DRC_ATK - [12:9] */
+#define WM8915_DSP1DRC_DCY_MASK                 0x01E0  /* DSP1DRC_DCY - [8:5] */
+#define WM8915_DSP1DRC_DCY_SHIFT                     5  /* DSP1DRC_DCY - [8:5] */
+#define WM8915_DSP1DRC_DCY_WIDTH                     4  /* DSP1DRC_DCY - [8:5] */
+#define WM8915_DSP1DRC_MINGAIN_MASK             0x001C  /* DSP1DRC_MINGAIN - [4:2] */
+#define WM8915_DSP1DRC_MINGAIN_SHIFT                 2  /* DSP1DRC_MINGAIN - [4:2] */
+#define WM8915_DSP1DRC_MINGAIN_WIDTH                 3  /* DSP1DRC_MINGAIN - [4:2] */
+#define WM8915_DSP1DRC_MAXGAIN_MASK             0x0003  /* DSP1DRC_MAXGAIN - [1:0] */
+#define WM8915_DSP1DRC_MAXGAIN_SHIFT                 0  /* DSP1DRC_MAXGAIN - [1:0] */
+#define WM8915_DSP1DRC_MAXGAIN_WIDTH                 2  /* DSP1DRC_MAXGAIN - [1:0] */
+
+/*
+ * R1090 (0x442) - DSP1 DRC (3)
+ */
+#define WM8915_DSP1DRC_NG_MINGAIN_MASK          0xF000  /* DSP1DRC_NG_MINGAIN - [15:12] */
+#define WM8915_DSP1DRC_NG_MINGAIN_SHIFT             12  /* DSP1DRC_NG_MINGAIN - [15:12] */
+#define WM8915_DSP1DRC_NG_MINGAIN_WIDTH              4  /* DSP1DRC_NG_MINGAIN - [15:12] */
+#define WM8915_DSP1DRC_NG_EXP_MASK              0x0C00  /* DSP1DRC_NG_EXP - [11:10] */
+#define WM8915_DSP1DRC_NG_EXP_SHIFT                 10  /* DSP1DRC_NG_EXP - [11:10] */
+#define WM8915_DSP1DRC_NG_EXP_WIDTH                  2  /* DSP1DRC_NG_EXP - [11:10] */
+#define WM8915_DSP1DRC_QR_THR_MASK              0x0300  /* DSP1DRC_QR_THR - [9:8] */
+#define WM8915_DSP1DRC_QR_THR_SHIFT                  8  /* DSP1DRC_QR_THR - [9:8] */
+#define WM8915_DSP1DRC_QR_THR_WIDTH                  2  /* DSP1DRC_QR_THR - [9:8] */
+#define WM8915_DSP1DRC_QR_DCY_MASK              0x00C0  /* DSP1DRC_QR_DCY - [7:6] */
+#define WM8915_DSP1DRC_QR_DCY_SHIFT                  6  /* DSP1DRC_QR_DCY - [7:6] */
+#define WM8915_DSP1DRC_QR_DCY_WIDTH                  2  /* DSP1DRC_QR_DCY - [7:6] */
+#define WM8915_DSP1DRC_HI_COMP_MASK             0x0038  /* DSP1DRC_HI_COMP - [5:3] */
+#define WM8915_DSP1DRC_HI_COMP_SHIFT                 3  /* DSP1DRC_HI_COMP - [5:3] */
+#define WM8915_DSP1DRC_HI_COMP_WIDTH                 3  /* DSP1DRC_HI_COMP - [5:3] */
+#define WM8915_DSP1DRC_LO_COMP_MASK             0x0007  /* DSP1DRC_LO_COMP - [2:0] */
+#define WM8915_DSP1DRC_LO_COMP_SHIFT                 0  /* DSP1DRC_LO_COMP - [2:0] */
+#define WM8915_DSP1DRC_LO_COMP_WIDTH                 3  /* DSP1DRC_LO_COMP - [2:0] */
+
+/*
+ * R1091 (0x443) - DSP1 DRC (4)
+ */
+#define WM8915_DSP1DRC_KNEE_IP_MASK             0x07E0  /* DSP1DRC_KNEE_IP - [10:5] */
+#define WM8915_DSP1DRC_KNEE_IP_SHIFT                 5  /* DSP1DRC_KNEE_IP - [10:5] */
+#define WM8915_DSP1DRC_KNEE_IP_WIDTH                 6  /* DSP1DRC_KNEE_IP - [10:5] */
+#define WM8915_DSP1DRC_KNEE_OP_MASK             0x001F  /* DSP1DRC_KNEE_OP - [4:0] */
+#define WM8915_DSP1DRC_KNEE_OP_SHIFT                 0  /* DSP1DRC_KNEE_OP - [4:0] */
+#define WM8915_DSP1DRC_KNEE_OP_WIDTH                 5  /* DSP1DRC_KNEE_OP - [4:0] */
+
+/*
+ * R1092 (0x444) - DSP1 DRC (5)
+ */
+#define WM8915_DSP1DRC_KNEE2_IP_MASK            0x03E0  /* DSP1DRC_KNEE2_IP - [9:5] */
+#define WM8915_DSP1DRC_KNEE2_IP_SHIFT                5  /* DSP1DRC_KNEE2_IP - [9:5] */
+#define WM8915_DSP1DRC_KNEE2_IP_WIDTH                5  /* DSP1DRC_KNEE2_IP - [9:5] */
+#define WM8915_DSP1DRC_KNEE2_OP_MASK            0x001F  /* DSP1DRC_KNEE2_OP - [4:0] */
+#define WM8915_DSP1DRC_KNEE2_OP_SHIFT                0  /* DSP1DRC_KNEE2_OP - [4:0] */
+#define WM8915_DSP1DRC_KNEE2_OP_WIDTH                5  /* DSP1DRC_KNEE2_OP - [4:0] */
+
+/*
+ * R1152 (0x480) - DSP1 RX EQ Gains (1)
+ */
+#define WM8915_DSP1RX_EQ_B1_GAIN_MASK           0xF800  /* DSP1RX_EQ_B1_GAIN - [15:11] */
+#define WM8915_DSP1RX_EQ_B1_GAIN_SHIFT              11  /* DSP1RX_EQ_B1_GAIN - [15:11] */
+#define WM8915_DSP1RX_EQ_B1_GAIN_WIDTH               5  /* DSP1RX_EQ_B1_GAIN - [15:11] */
+#define WM8915_DSP1RX_EQ_B2_GAIN_MASK           0x07C0  /* DSP1RX_EQ_B2_GAIN - [10:6] */
+#define WM8915_DSP1RX_EQ_B2_GAIN_SHIFT               6  /* DSP1RX_EQ_B2_GAIN - [10:6] */
+#define WM8915_DSP1RX_EQ_B2_GAIN_WIDTH               5  /* DSP1RX_EQ_B2_GAIN - [10:6] */
+#define WM8915_DSP1RX_EQ_B3_GAIN_MASK           0x003E  /* DSP1RX_EQ_B3_GAIN - [5:1] */
+#define WM8915_DSP1RX_EQ_B3_GAIN_SHIFT               1  /* DSP1RX_EQ_B3_GAIN - [5:1] */
+#define WM8915_DSP1RX_EQ_B3_GAIN_WIDTH               5  /* DSP1RX_EQ_B3_GAIN - [5:1] */
+#define WM8915_DSP1RX_EQ_ENA                    0x0001  /* DSP1RX_EQ_ENA */
+#define WM8915_DSP1RX_EQ_ENA_MASK               0x0001  /* DSP1RX_EQ_ENA */
+#define WM8915_DSP1RX_EQ_ENA_SHIFT                   0  /* DSP1RX_EQ_ENA */
+#define WM8915_DSP1RX_EQ_ENA_WIDTH                   1  /* DSP1RX_EQ_ENA */
+
+/*
+ * R1153 (0x481) - DSP1 RX EQ Gains (2)
+ */
+#define WM8915_DSP1RX_EQ_B4_GAIN_MASK           0xF800  /* DSP1RX_EQ_B4_GAIN - [15:11] */
+#define WM8915_DSP1RX_EQ_B4_GAIN_SHIFT              11  /* DSP1RX_EQ_B4_GAIN - [15:11] */
+#define WM8915_DSP1RX_EQ_B4_GAIN_WIDTH               5  /* DSP1RX_EQ_B4_GAIN - [15:11] */
+#define WM8915_DSP1RX_EQ_B5_GAIN_MASK           0x07C0  /* DSP1RX_EQ_B5_GAIN - [10:6] */
+#define WM8915_DSP1RX_EQ_B5_GAIN_SHIFT               6  /* DSP1RX_EQ_B5_GAIN - [10:6] */
+#define WM8915_DSP1RX_EQ_B5_GAIN_WIDTH               5  /* DSP1RX_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1154 (0x482) - DSP1 RX EQ Band 1 A
+ */
+#define WM8915_DSP1RX_EQ_B1_A_MASK              0xFFFF  /* DSP1RX_EQ_B1_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B1_A_SHIFT                  0  /* DSP1RX_EQ_B1_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B1_A_WIDTH                 16  /* DSP1RX_EQ_B1_A - [15:0] */
+
+/*
+ * R1155 (0x483) - DSP1 RX EQ Band 1 B
+ */
+#define WM8915_DSP1RX_EQ_B1_B_MASK              0xFFFF  /* DSP1RX_EQ_B1_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B1_B_SHIFT                  0  /* DSP1RX_EQ_B1_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B1_B_WIDTH                 16  /* DSP1RX_EQ_B1_B - [15:0] */
+
+/*
+ * R1156 (0x484) - DSP1 RX EQ Band 1 PG
+ */
+#define WM8915_DSP1RX_EQ_B1_PG_MASK             0xFFFF  /* DSP1RX_EQ_B1_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B1_PG_SHIFT                 0  /* DSP1RX_EQ_B1_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B1_PG_WIDTH                16  /* DSP1RX_EQ_B1_PG - [15:0] */
+
+/*
+ * R1157 (0x485) - DSP1 RX EQ Band 2 A
+ */
+#define WM8915_DSP1RX_EQ_B2_A_MASK              0xFFFF  /* DSP1RX_EQ_B2_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B2_A_SHIFT                  0  /* DSP1RX_EQ_B2_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B2_A_WIDTH                 16  /* DSP1RX_EQ_B2_A - [15:0] */
+
+/*
+ * R1158 (0x486) - DSP1 RX EQ Band 2 B
+ */
+#define WM8915_DSP1RX_EQ_B2_B_MASK              0xFFFF  /* DSP1RX_EQ_B2_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B2_B_SHIFT                  0  /* DSP1RX_EQ_B2_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B2_B_WIDTH                 16  /* DSP1RX_EQ_B2_B - [15:0] */
+
+/*
+ * R1159 (0x487) - DSP1 RX EQ Band 2 C
+ */
+#define WM8915_DSP1RX_EQ_B2_C_MASK              0xFFFF  /* DSP1RX_EQ_B2_C - [15:0] */
+#define WM8915_DSP1RX_EQ_B2_C_SHIFT                  0  /* DSP1RX_EQ_B2_C - [15:0] */
+#define WM8915_DSP1RX_EQ_B2_C_WIDTH                 16  /* DSP1RX_EQ_B2_C - [15:0] */
+
+/*
+ * R1160 (0x488) - DSP1 RX EQ Band 2 PG
+ */
+#define WM8915_DSP1RX_EQ_B2_PG_MASK             0xFFFF  /* DSP1RX_EQ_B2_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B2_PG_SHIFT                 0  /* DSP1RX_EQ_B2_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B2_PG_WIDTH                16  /* DSP1RX_EQ_B2_PG - [15:0] */
+
+/*
+ * R1161 (0x489) - DSP1 RX EQ Band 3 A
+ */
+#define WM8915_DSP1RX_EQ_B3_A_MASK              0xFFFF  /* DSP1RX_EQ_B3_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B3_A_SHIFT                  0  /* DSP1RX_EQ_B3_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B3_A_WIDTH                 16  /* DSP1RX_EQ_B3_A - [15:0] */
+
+/*
+ * R1162 (0x48A) - DSP1 RX EQ Band 3 B
+ */
+#define WM8915_DSP1RX_EQ_B3_B_MASK              0xFFFF  /* DSP1RX_EQ_B3_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B3_B_SHIFT                  0  /* DSP1RX_EQ_B3_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B3_B_WIDTH                 16  /* DSP1RX_EQ_B3_B - [15:0] */
+
+/*
+ * R1163 (0x48B) - DSP1 RX EQ Band 3 C
+ */
+#define WM8915_DSP1RX_EQ_B3_C_MASK              0xFFFF  /* DSP1RX_EQ_B3_C - [15:0] */
+#define WM8915_DSP1RX_EQ_B3_C_SHIFT                  0  /* DSP1RX_EQ_B3_C - [15:0] */
+#define WM8915_DSP1RX_EQ_B3_C_WIDTH                 16  /* DSP1RX_EQ_B3_C - [15:0] */
+
+/*
+ * R1164 (0x48C) - DSP1 RX EQ Band 3 PG
+ */
+#define WM8915_DSP1RX_EQ_B3_PG_MASK             0xFFFF  /* DSP1RX_EQ_B3_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B3_PG_SHIFT                 0  /* DSP1RX_EQ_B3_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B3_PG_WIDTH                16  /* DSP1RX_EQ_B3_PG - [15:0] */
+
+/*
+ * R1165 (0x48D) - DSP1 RX EQ Band 4 A
+ */
+#define WM8915_DSP1RX_EQ_B4_A_MASK              0xFFFF  /* DSP1RX_EQ_B4_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B4_A_SHIFT                  0  /* DSP1RX_EQ_B4_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B4_A_WIDTH                 16  /* DSP1RX_EQ_B4_A - [15:0] */
+
+/*
+ * R1166 (0x48E) - DSP1 RX EQ Band 4 B
+ */
+#define WM8915_DSP1RX_EQ_B4_B_MASK              0xFFFF  /* DSP1RX_EQ_B4_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B4_B_SHIFT                  0  /* DSP1RX_EQ_B4_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B4_B_WIDTH                 16  /* DSP1RX_EQ_B4_B - [15:0] */
+
+/*
+ * R1167 (0x48F) - DSP1 RX EQ Band 4 C
+ */
+#define WM8915_DSP1RX_EQ_B4_C_MASK              0xFFFF  /* DSP1RX_EQ_B4_C - [15:0] */
+#define WM8915_DSP1RX_EQ_B4_C_SHIFT                  0  /* DSP1RX_EQ_B4_C - [15:0] */
+#define WM8915_DSP1RX_EQ_B4_C_WIDTH                 16  /* DSP1RX_EQ_B4_C - [15:0] */
+
+/*
+ * R1168 (0x490) - DSP1 RX EQ Band 4 PG
+ */
+#define WM8915_DSP1RX_EQ_B4_PG_MASK             0xFFFF  /* DSP1RX_EQ_B4_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B4_PG_SHIFT                 0  /* DSP1RX_EQ_B4_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B4_PG_WIDTH                16  /* DSP1RX_EQ_B4_PG - [15:0] */
+
+/*
+ * R1169 (0x491) - DSP1 RX EQ Band 5 A
+ */
+#define WM8915_DSP1RX_EQ_B5_A_MASK              0xFFFF  /* DSP1RX_EQ_B5_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B5_A_SHIFT                  0  /* DSP1RX_EQ_B5_A - [15:0] */
+#define WM8915_DSP1RX_EQ_B5_A_WIDTH                 16  /* DSP1RX_EQ_B5_A - [15:0] */
+
+/*
+ * R1170 (0x492) - DSP1 RX EQ Band 5 B
+ */
+#define WM8915_DSP1RX_EQ_B5_B_MASK              0xFFFF  /* DSP1RX_EQ_B5_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B5_B_SHIFT                  0  /* DSP1RX_EQ_B5_B - [15:0] */
+#define WM8915_DSP1RX_EQ_B5_B_WIDTH                 16  /* DSP1RX_EQ_B5_B - [15:0] */
+
+/*
+ * R1171 (0x493) - DSP1 RX EQ Band 5 PG
+ */
+#define WM8915_DSP1RX_EQ_B5_PG_MASK             0xFFFF  /* DSP1RX_EQ_B5_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B5_PG_SHIFT                 0  /* DSP1RX_EQ_B5_PG - [15:0] */
+#define WM8915_DSP1RX_EQ_B5_PG_WIDTH                16  /* DSP1RX_EQ_B5_PG - [15:0] */
+
+/*
+ * R1280 (0x500) - DSP2 TX Left Volume
+ */
+#define WM8915_DSP2TX_VU                        0x0100  /* DSP2TX_VU */
+#define WM8915_DSP2TX_VU_MASK                   0x0100  /* DSP2TX_VU */
+#define WM8915_DSP2TX_VU_SHIFT                       8  /* DSP2TX_VU */
+#define WM8915_DSP2TX_VU_WIDTH                       1  /* DSP2TX_VU */
+#define WM8915_DSP2TXL_VOL_MASK                 0x00FF  /* DSP2TXL_VOL - [7:0] */
+#define WM8915_DSP2TXL_VOL_SHIFT                     0  /* DSP2TXL_VOL - [7:0] */
+#define WM8915_DSP2TXL_VOL_WIDTH                     8  /* DSP2TXL_VOL - [7:0] */
+
+/*
+ * R1281 (0x501) - DSP2 TX Right Volume
+ */
+#define WM8915_DSP2TX_VU                        0x0100  /* DSP2TX_VU */
+#define WM8915_DSP2TX_VU_MASK                   0x0100  /* DSP2TX_VU */
+#define WM8915_DSP2TX_VU_SHIFT                       8  /* DSP2TX_VU */
+#define WM8915_DSP2TX_VU_WIDTH                       1  /* DSP2TX_VU */
+#define WM8915_DSP2TXR_VOL_MASK                 0x00FF  /* DSP2TXR_VOL - [7:0] */
+#define WM8915_DSP2TXR_VOL_SHIFT                     0  /* DSP2TXR_VOL - [7:0] */
+#define WM8915_DSP2TXR_VOL_WIDTH                     8  /* DSP2TXR_VOL - [7:0] */
+
+/*
+ * R1282 (0x502) - DSP2 RX Left Volume
+ */
+#define WM8915_DSP2RX_VU                        0x0100  /* DSP2RX_VU */
+#define WM8915_DSP2RX_VU_MASK                   0x0100  /* DSP2RX_VU */
+#define WM8915_DSP2RX_VU_SHIFT                       8  /* DSP2RX_VU */
+#define WM8915_DSP2RX_VU_WIDTH                       1  /* DSP2RX_VU */
+#define WM8915_DSP2RXL_VOL_MASK                 0x00FF  /* DSP2RXL_VOL - [7:0] */
+#define WM8915_DSP2RXL_VOL_SHIFT                     0  /* DSP2RXL_VOL - [7:0] */
+#define WM8915_DSP2RXL_VOL_WIDTH                     8  /* DSP2RXL_VOL - [7:0] */
+
+/*
+ * R1283 (0x503) - DSP2 RX Right Volume
+ */
+#define WM8915_DSP2RX_VU                        0x0100  /* DSP2RX_VU */
+#define WM8915_DSP2RX_VU_MASK                   0x0100  /* DSP2RX_VU */
+#define WM8915_DSP2RX_VU_SHIFT                       8  /* DSP2RX_VU */
+#define WM8915_DSP2RX_VU_WIDTH                       1  /* DSP2RX_VU */
+#define WM8915_DSP2RXR_VOL_MASK                 0x00FF  /* DSP2RXR_VOL - [7:0] */
+#define WM8915_DSP2RXR_VOL_SHIFT                     0  /* DSP2RXR_VOL - [7:0] */
+#define WM8915_DSP2RXR_VOL_WIDTH                     8  /* DSP2RXR_VOL - [7:0] */
+
+/*
+ * R1296 (0x510) - DSP2 TX Filters
+ */
+#define WM8915_DSP2TX_NF                        0x2000  /* DSP2TX_NF */
+#define WM8915_DSP2TX_NF_MASK                   0x2000  /* DSP2TX_NF */
+#define WM8915_DSP2TX_NF_SHIFT                      13  /* DSP2TX_NF */
+#define WM8915_DSP2TX_NF_WIDTH                       1  /* DSP2TX_NF */
+#define WM8915_DSP2TXL_HPF                      0x1000  /* DSP2TXL_HPF */
+#define WM8915_DSP2TXL_HPF_MASK                 0x1000  /* DSP2TXL_HPF */
+#define WM8915_DSP2TXL_HPF_SHIFT                    12  /* DSP2TXL_HPF */
+#define WM8915_DSP2TXL_HPF_WIDTH                     1  /* DSP2TXL_HPF */
+#define WM8915_DSP2TXR_HPF                      0x0800  /* DSP2TXR_HPF */
+#define WM8915_DSP2TXR_HPF_MASK                 0x0800  /* DSP2TXR_HPF */
+#define WM8915_DSP2TXR_HPF_SHIFT                    11  /* DSP2TXR_HPF */
+#define WM8915_DSP2TXR_HPF_WIDTH                     1  /* DSP2TXR_HPF */
+#define WM8915_DSP2TX_HPF_MODE_MASK             0x0018  /* DSP2TX_HPF_MODE - [4:3] */
+#define WM8915_DSP2TX_HPF_MODE_SHIFT                 3  /* DSP2TX_HPF_MODE - [4:3] */
+#define WM8915_DSP2TX_HPF_MODE_WIDTH                 2  /* DSP2TX_HPF_MODE - [4:3] */
+#define WM8915_DSP2TX_HPF_CUT_MASK              0x0007  /* DSP2TX_HPF_CUT - [2:0] */
+#define WM8915_DSP2TX_HPF_CUT_SHIFT                  0  /* DSP2TX_HPF_CUT - [2:0] */
+#define WM8915_DSP2TX_HPF_CUT_WIDTH                  3  /* DSP2TX_HPF_CUT - [2:0] */
+
+/*
+ * R1312 (0x520) - DSP2 RX Filters (1)
+ */
+#define WM8915_DSP2RX_MUTE                      0x0200  /* DSP2RX_MUTE */
+#define WM8915_DSP2RX_MUTE_MASK                 0x0200  /* DSP2RX_MUTE */
+#define WM8915_DSP2RX_MUTE_SHIFT                     9  /* DSP2RX_MUTE */
+#define WM8915_DSP2RX_MUTE_WIDTH                     1  /* DSP2RX_MUTE */
+#define WM8915_DSP2RX_MONO                      0x0080  /* DSP2RX_MONO */
+#define WM8915_DSP2RX_MONO_MASK                 0x0080  /* DSP2RX_MONO */
+#define WM8915_DSP2RX_MONO_SHIFT                     7  /* DSP2RX_MONO */
+#define WM8915_DSP2RX_MONO_WIDTH                     1  /* DSP2RX_MONO */
+#define WM8915_DSP2RX_MUTERATE                  0x0020  /* DSP2RX_MUTERATE */
+#define WM8915_DSP2RX_MUTERATE_MASK             0x0020  /* DSP2RX_MUTERATE */
+#define WM8915_DSP2RX_MUTERATE_SHIFT                 5  /* DSP2RX_MUTERATE */
+#define WM8915_DSP2RX_MUTERATE_WIDTH                 1  /* DSP2RX_MUTERATE */
+#define WM8915_DSP2RX_UNMUTE_RAMP               0x0010  /* DSP2RX_UNMUTE_RAMP */
+#define WM8915_DSP2RX_UNMUTE_RAMP_MASK          0x0010  /* DSP2RX_UNMUTE_RAMP */
+#define WM8915_DSP2RX_UNMUTE_RAMP_SHIFT              4  /* DSP2RX_UNMUTE_RAMP */
+#define WM8915_DSP2RX_UNMUTE_RAMP_WIDTH              1  /* DSP2RX_UNMUTE_RAMP */
+
+/*
+ * R1313 (0x521) - DSP2 RX Filters (2)
+ */
+#define WM8915_DSP2RX_3D_GAIN_MASK              0x3E00  /* DSP2RX_3D_GAIN - [13:9] */
+#define WM8915_DSP2RX_3D_GAIN_SHIFT                  9  /* DSP2RX_3D_GAIN - [13:9] */
+#define WM8915_DSP2RX_3D_GAIN_WIDTH                  5  /* DSP2RX_3D_GAIN - [13:9] */
+#define WM8915_DSP2RX_3D_ENA                    0x0100  /* DSP2RX_3D_ENA */
+#define WM8915_DSP2RX_3D_ENA_MASK               0x0100  /* DSP2RX_3D_ENA */
+#define WM8915_DSP2RX_3D_ENA_SHIFT                   8  /* DSP2RX_3D_ENA */
+#define WM8915_DSP2RX_3D_ENA_WIDTH                   1  /* DSP2RX_3D_ENA */
+
+/*
+ * R1344 (0x540) - DSP2 DRC (1)
+ */
+#define WM8915_DSP2DRC_SIG_DET_RMS_MASK         0xF800  /* DSP2DRC_SIG_DET_RMS - [15:11] */
+#define WM8915_DSP2DRC_SIG_DET_RMS_SHIFT            11  /* DSP2DRC_SIG_DET_RMS - [15:11] */
+#define WM8915_DSP2DRC_SIG_DET_RMS_WIDTH             5  /* DSP2DRC_SIG_DET_RMS - [15:11] */
+#define WM8915_DSP2DRC_SIG_DET_PK_MASK          0x0600  /* DSP2DRC_SIG_DET_PK - [10:9] */
+#define WM8915_DSP2DRC_SIG_DET_PK_SHIFT              9  /* DSP2DRC_SIG_DET_PK - [10:9] */
+#define WM8915_DSP2DRC_SIG_DET_PK_WIDTH              2  /* DSP2DRC_SIG_DET_PK - [10:9] */
+#define WM8915_DSP2DRC_NG_ENA                   0x0100  /* DSP2DRC_NG_ENA */
+#define WM8915_DSP2DRC_NG_ENA_MASK              0x0100  /* DSP2DRC_NG_ENA */
+#define WM8915_DSP2DRC_NG_ENA_SHIFT                  8  /* DSP2DRC_NG_ENA */
+#define WM8915_DSP2DRC_NG_ENA_WIDTH                  1  /* DSP2DRC_NG_ENA */
+#define WM8915_DSP2DRC_SIG_DET_MODE             0x0080  /* DSP2DRC_SIG_DET_MODE */
+#define WM8915_DSP2DRC_SIG_DET_MODE_MASK        0x0080  /* DSP2DRC_SIG_DET_MODE */
+#define WM8915_DSP2DRC_SIG_DET_MODE_SHIFT            7  /* DSP2DRC_SIG_DET_MODE */
+#define WM8915_DSP2DRC_SIG_DET_MODE_WIDTH            1  /* DSP2DRC_SIG_DET_MODE */
+#define WM8915_DSP2DRC_SIG_DET                  0x0040  /* DSP2DRC_SIG_DET */
+#define WM8915_DSP2DRC_SIG_DET_MASK             0x0040  /* DSP2DRC_SIG_DET */
+#define WM8915_DSP2DRC_SIG_DET_SHIFT                 6  /* DSP2DRC_SIG_DET */
+#define WM8915_DSP2DRC_SIG_DET_WIDTH                 1  /* DSP2DRC_SIG_DET */
+#define WM8915_DSP2DRC_KNEE2_OP_ENA             0x0020  /* DSP2DRC_KNEE2_OP_ENA */
+#define WM8915_DSP2DRC_KNEE2_OP_ENA_MASK        0x0020  /* DSP2DRC_KNEE2_OP_ENA */
+#define WM8915_DSP2DRC_KNEE2_OP_ENA_SHIFT            5  /* DSP2DRC_KNEE2_OP_ENA */
+#define WM8915_DSP2DRC_KNEE2_OP_ENA_WIDTH            1  /* DSP2DRC_KNEE2_OP_ENA */
+#define WM8915_DSP2DRC_QR                       0x0010  /* DSP2DRC_QR */
+#define WM8915_DSP2DRC_QR_MASK                  0x0010  /* DSP2DRC_QR */
+#define WM8915_DSP2DRC_QR_SHIFT                      4  /* DSP2DRC_QR */
+#define WM8915_DSP2DRC_QR_WIDTH                      1  /* DSP2DRC_QR */
+#define WM8915_DSP2DRC_ANTICLIP                 0x0008  /* DSP2DRC_ANTICLIP */
+#define WM8915_DSP2DRC_ANTICLIP_MASK            0x0008  /* DSP2DRC_ANTICLIP */
+#define WM8915_DSP2DRC_ANTICLIP_SHIFT                3  /* DSP2DRC_ANTICLIP */
+#define WM8915_DSP2DRC_ANTICLIP_WIDTH                1  /* DSP2DRC_ANTICLIP */
+#define WM8915_DSP2RX_DRC_ENA                   0x0004  /* DSP2RX_DRC_ENA */
+#define WM8915_DSP2RX_DRC_ENA_MASK              0x0004  /* DSP2RX_DRC_ENA */
+#define WM8915_DSP2RX_DRC_ENA_SHIFT                  2  /* DSP2RX_DRC_ENA */
+#define WM8915_DSP2RX_DRC_ENA_WIDTH                  1  /* DSP2RX_DRC_ENA */
+#define WM8915_DSP2TXL_DRC_ENA                  0x0002  /* DSP2TXL_DRC_ENA */
+#define WM8915_DSP2TXL_DRC_ENA_MASK             0x0002  /* DSP2TXL_DRC_ENA */
+#define WM8915_DSP2TXL_DRC_ENA_SHIFT                 1  /* DSP2TXL_DRC_ENA */
+#define WM8915_DSP2TXL_DRC_ENA_WIDTH                 1  /* DSP2TXL_DRC_ENA */
+#define WM8915_DSP2TXR_DRC_ENA                  0x0001  /* DSP2TXR_DRC_ENA */
+#define WM8915_DSP2TXR_DRC_ENA_MASK             0x0001  /* DSP2TXR_DRC_ENA */
+#define WM8915_DSP2TXR_DRC_ENA_SHIFT                 0  /* DSP2TXR_DRC_ENA */
+#define WM8915_DSP2TXR_DRC_ENA_WIDTH                 1  /* DSP2TXR_DRC_ENA */
+
+/*
+ * R1345 (0x541) - DSP2 DRC (2)
+ */
+#define WM8915_DSP2DRC_ATK_MASK                 0x1E00  /* DSP2DRC_ATK - [12:9] */
+#define WM8915_DSP2DRC_ATK_SHIFT                     9  /* DSP2DRC_ATK - [12:9] */
+#define WM8915_DSP2DRC_ATK_WIDTH                     4  /* DSP2DRC_ATK - [12:9] */
+#define WM8915_DSP2DRC_DCY_MASK                 0x01E0  /* DSP2DRC_DCY - [8:5] */
+#define WM8915_DSP2DRC_DCY_SHIFT                     5  /* DSP2DRC_DCY - [8:5] */
+#define WM8915_DSP2DRC_DCY_WIDTH                     4  /* DSP2DRC_DCY - [8:5] */
+#define WM8915_DSP2DRC_MINGAIN_MASK             0x001C  /* DSP2DRC_MINGAIN - [4:2] */
+#define WM8915_DSP2DRC_MINGAIN_SHIFT                 2  /* DSP2DRC_MINGAIN - [4:2] */
+#define WM8915_DSP2DRC_MINGAIN_WIDTH                 3  /* DSP2DRC_MINGAIN - [4:2] */
+#define WM8915_DSP2DRC_MAXGAIN_MASK             0x0003  /* DSP2DRC_MAXGAIN - [1:0] */
+#define WM8915_DSP2DRC_MAXGAIN_SHIFT                 0  /* DSP2DRC_MAXGAIN - [1:0] */
+#define WM8915_DSP2DRC_MAXGAIN_WIDTH                 2  /* DSP2DRC_MAXGAIN - [1:0] */
+
+/*
+ * R1346 (0x542) - DSP2 DRC (3)
+ */
+#define WM8915_DSP2DRC_NG_MINGAIN_MASK          0xF000  /* DSP2DRC_NG_MINGAIN - [15:12] */
+#define WM8915_DSP2DRC_NG_MINGAIN_SHIFT             12  /* DSP2DRC_NG_MINGAIN - [15:12] */
+#define WM8915_DSP2DRC_NG_MINGAIN_WIDTH              4  /* DSP2DRC_NG_MINGAIN - [15:12] */
+#define WM8915_DSP2DRC_NG_EXP_MASK              0x0C00  /* DSP2DRC_NG_EXP - [11:10] */
+#define WM8915_DSP2DRC_NG_EXP_SHIFT                 10  /* DSP2DRC_NG_EXP - [11:10] */
+#define WM8915_DSP2DRC_NG_EXP_WIDTH                  2  /* DSP2DRC_NG_EXP - [11:10] */
+#define WM8915_DSP2DRC_QR_THR_MASK              0x0300  /* DSP2DRC_QR_THR - [9:8] */
+#define WM8915_DSP2DRC_QR_THR_SHIFT                  8  /* DSP2DRC_QR_THR - [9:8] */
+#define WM8915_DSP2DRC_QR_THR_WIDTH                  2  /* DSP2DRC_QR_THR - [9:8] */
+#define WM8915_DSP2DRC_QR_DCY_MASK              0x00C0  /* DSP2DRC_QR_DCY - [7:6] */
+#define WM8915_DSP2DRC_QR_DCY_SHIFT                  6  /* DSP2DRC_QR_DCY - [7:6] */
+#define WM8915_DSP2DRC_QR_DCY_WIDTH                  2  /* DSP2DRC_QR_DCY - [7:6] */
+#define WM8915_DSP2DRC_HI_COMP_MASK             0x0038  /* DSP2DRC_HI_COMP - [5:3] */
+#define WM8915_DSP2DRC_HI_COMP_SHIFT                 3  /* DSP2DRC_HI_COMP - [5:3] */
+#define WM8915_DSP2DRC_HI_COMP_WIDTH                 3  /* DSP2DRC_HI_COMP - [5:3] */
+#define WM8915_DSP2DRC_LO_COMP_MASK             0x0007  /* DSP2DRC_LO_COMP - [2:0] */
+#define WM8915_DSP2DRC_LO_COMP_SHIFT                 0  /* DSP2DRC_LO_COMP - [2:0] */
+#define WM8915_DSP2DRC_LO_COMP_WIDTH                 3  /* DSP2DRC_LO_COMP - [2:0] */
+
+/*
+ * R1347 (0x543) - DSP2 DRC (4)
+ */
+#define WM8915_DSP2DRC_KNEE_IP_MASK             0x07E0  /* DSP2DRC_KNEE_IP - [10:5] */
+#define WM8915_DSP2DRC_KNEE_IP_SHIFT                 5  /* DSP2DRC_KNEE_IP - [10:5] */
+#define WM8915_DSP2DRC_KNEE_IP_WIDTH                 6  /* DSP2DRC_KNEE_IP - [10:5] */
+#define WM8915_DSP2DRC_KNEE_OP_MASK             0x001F  /* DSP2DRC_KNEE_OP - [4:0] */
+#define WM8915_DSP2DRC_KNEE_OP_SHIFT                 0  /* DSP2DRC_KNEE_OP - [4:0] */
+#define WM8915_DSP2DRC_KNEE_OP_WIDTH                 5  /* DSP2DRC_KNEE_OP - [4:0] */
+
+/*
+ * R1348 (0x544) - DSP2 DRC (5)
+ */
+#define WM8915_DSP2DRC_KNEE2_IP_MASK            0x03E0  /* DSP2DRC_KNEE2_IP - [9:5] */
+#define WM8915_DSP2DRC_KNEE2_IP_SHIFT                5  /* DSP2DRC_KNEE2_IP - [9:5] */
+#define WM8915_DSP2DRC_KNEE2_IP_WIDTH                5  /* DSP2DRC_KNEE2_IP - [9:5] */
+#define WM8915_DSP2DRC_KNEE2_OP_MASK            0x001F  /* DSP2DRC_KNEE2_OP - [4:0] */
+#define WM8915_DSP2DRC_KNEE2_OP_SHIFT                0  /* DSP2DRC_KNEE2_OP - [4:0] */
+#define WM8915_DSP2DRC_KNEE2_OP_WIDTH                5  /* DSP2DRC_KNEE2_OP - [4:0] */
+
+/*
+ * R1408 (0x580) - DSP2 RX EQ Gains (1)
+ */
+#define WM8915_DSP2RX_EQ_B1_GAIN_MASK           0xF800  /* DSP2RX_EQ_B1_GAIN - [15:11] */
+#define WM8915_DSP2RX_EQ_B1_GAIN_SHIFT              11  /* DSP2RX_EQ_B1_GAIN - [15:11] */
+#define WM8915_DSP2RX_EQ_B1_GAIN_WIDTH               5  /* DSP2RX_EQ_B1_GAIN - [15:11] */
+#define WM8915_DSP2RX_EQ_B2_GAIN_MASK           0x07C0  /* DSP2RX_EQ_B2_GAIN - [10:6] */
+#define WM8915_DSP2RX_EQ_B2_GAIN_SHIFT               6  /* DSP2RX_EQ_B2_GAIN - [10:6] */
+#define WM8915_DSP2RX_EQ_B2_GAIN_WIDTH               5  /* DSP2RX_EQ_B2_GAIN - [10:6] */
+#define WM8915_DSP2RX_EQ_B3_GAIN_MASK           0x003E  /* DSP2RX_EQ_B3_GAIN - [5:1] */
+#define WM8915_DSP2RX_EQ_B3_GAIN_SHIFT               1  /* DSP2RX_EQ_B3_GAIN - [5:1] */
+#define WM8915_DSP2RX_EQ_B3_GAIN_WIDTH               5  /* DSP2RX_EQ_B3_GAIN - [5:1] */
+#define WM8915_DSP2RX_EQ_ENA                    0x0001  /* DSP2RX_EQ_ENA */
+#define WM8915_DSP2RX_EQ_ENA_MASK               0x0001  /* DSP2RX_EQ_ENA */
+#define WM8915_DSP2RX_EQ_ENA_SHIFT                   0  /* DSP2RX_EQ_ENA */
+#define WM8915_DSP2RX_EQ_ENA_WIDTH                   1  /* DSP2RX_EQ_ENA */
+
+/*
+ * R1409 (0x581) - DSP2 RX EQ Gains (2)
+ */
+#define WM8915_DSP2RX_EQ_B4_GAIN_MASK           0xF800  /* DSP2RX_EQ_B4_GAIN - [15:11] */
+#define WM8915_DSP2RX_EQ_B4_GAIN_SHIFT              11  /* DSP2RX_EQ_B4_GAIN - [15:11] */
+#define WM8915_DSP2RX_EQ_B4_GAIN_WIDTH               5  /* DSP2RX_EQ_B4_GAIN - [15:11] */
+#define WM8915_DSP2RX_EQ_B5_GAIN_MASK           0x07C0  /* DSP2RX_EQ_B5_GAIN - [10:6] */
+#define WM8915_DSP2RX_EQ_B5_GAIN_SHIFT               6  /* DSP2RX_EQ_B5_GAIN - [10:6] */
+#define WM8915_DSP2RX_EQ_B5_GAIN_WIDTH               5  /* DSP2RX_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1410 (0x582) - DSP2 RX EQ Band 1 A
+ */
+#define WM8915_DSP2RX_EQ_B1_A_MASK              0xFFFF  /* DSP2RX_EQ_B1_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B1_A_SHIFT                  0  /* DSP2RX_EQ_B1_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B1_A_WIDTH                 16  /* DSP2RX_EQ_B1_A - [15:0] */
+
+/*
+ * R1411 (0x583) - DSP2 RX EQ Band 1 B
+ */
+#define WM8915_DSP2RX_EQ_B1_B_MASK              0xFFFF  /* DSP2RX_EQ_B1_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B1_B_SHIFT                  0  /* DSP2RX_EQ_B1_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B1_B_WIDTH                 16  /* DSP2RX_EQ_B1_B - [15:0] */
+
+/*
+ * R1412 (0x584) - DSP2 RX EQ Band 1 PG
+ */
+#define WM8915_DSP2RX_EQ_B1_PG_MASK             0xFFFF  /* DSP2RX_EQ_B1_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B1_PG_SHIFT                 0  /* DSP2RX_EQ_B1_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B1_PG_WIDTH                16  /* DSP2RX_EQ_B1_PG - [15:0] */
+
+/*
+ * R1413 (0x585) - DSP2 RX EQ Band 2 A
+ */
+#define WM8915_DSP2RX_EQ_B2_A_MASK              0xFFFF  /* DSP2RX_EQ_B2_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B2_A_SHIFT                  0  /* DSP2RX_EQ_B2_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B2_A_WIDTH                 16  /* DSP2RX_EQ_B2_A - [15:0] */
+
+/*
+ * R1414 (0x586) - DSP2 RX EQ Band 2 B
+ */
+#define WM8915_DSP2RX_EQ_B2_B_MASK              0xFFFF  /* DSP2RX_EQ_B2_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B2_B_SHIFT                  0  /* DSP2RX_EQ_B2_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B2_B_WIDTH                 16  /* DSP2RX_EQ_B2_B - [15:0] */
+
+/*
+ * R1415 (0x587) - DSP2 RX EQ Band 2 C
+ */
+#define WM8915_DSP2RX_EQ_B2_C_MASK              0xFFFF  /* DSP2RX_EQ_B2_C - [15:0] */
+#define WM8915_DSP2RX_EQ_B2_C_SHIFT                  0  /* DSP2RX_EQ_B2_C - [15:0] */
+#define WM8915_DSP2RX_EQ_B2_C_WIDTH                 16  /* DSP2RX_EQ_B2_C - [15:0] */
+
+/*
+ * R1416 (0x588) - DSP2 RX EQ Band 2 PG
+ */
+#define WM8915_DSP2RX_EQ_B2_PG_MASK             0xFFFF  /* DSP2RX_EQ_B2_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B2_PG_SHIFT                 0  /* DSP2RX_EQ_B2_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B2_PG_WIDTH                16  /* DSP2RX_EQ_B2_PG - [15:0] */
+
+/*
+ * R1417 (0x589) - DSP2 RX EQ Band 3 A
+ */
+#define WM8915_DSP2RX_EQ_B3_A_MASK              0xFFFF  /* DSP2RX_EQ_B3_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B3_A_SHIFT                  0  /* DSP2RX_EQ_B3_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B3_A_WIDTH                 16  /* DSP2RX_EQ_B3_A - [15:0] */
+
+/*
+ * R1418 (0x58A) - DSP2 RX EQ Band 3 B
+ */
+#define WM8915_DSP2RX_EQ_B3_B_MASK              0xFFFF  /* DSP2RX_EQ_B3_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B3_B_SHIFT                  0  /* DSP2RX_EQ_B3_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B3_B_WIDTH                 16  /* DSP2RX_EQ_B3_B - [15:0] */
+
+/*
+ * R1419 (0x58B) - DSP2 RX EQ Band 3 C
+ */
+#define WM8915_DSP2RX_EQ_B3_C_MASK              0xFFFF  /* DSP2RX_EQ_B3_C - [15:0] */
+#define WM8915_DSP2RX_EQ_B3_C_SHIFT                  0  /* DSP2RX_EQ_B3_C - [15:0] */
+#define WM8915_DSP2RX_EQ_B3_C_WIDTH                 16  /* DSP2RX_EQ_B3_C - [15:0] */
+
+/*
+ * R1420 (0x58C) - DSP2 RX EQ Band 3 PG
+ */
+#define WM8915_DSP2RX_EQ_B3_PG_MASK             0xFFFF  /* DSP2RX_EQ_B3_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B3_PG_SHIFT                 0  /* DSP2RX_EQ_B3_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B3_PG_WIDTH                16  /* DSP2RX_EQ_B3_PG - [15:0] */
+
+/*
+ * R1421 (0x58D) - DSP2 RX EQ Band 4 A
+ */
+#define WM8915_DSP2RX_EQ_B4_A_MASK              0xFFFF  /* DSP2RX_EQ_B4_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B4_A_SHIFT                  0  /* DSP2RX_EQ_B4_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B4_A_WIDTH                 16  /* DSP2RX_EQ_B4_A - [15:0] */
+
+/*
+ * R1422 (0x58E) - DSP2 RX EQ Band 4 B
+ */
+#define WM8915_DSP2RX_EQ_B4_B_MASK              0xFFFF  /* DSP2RX_EQ_B4_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B4_B_SHIFT                  0  /* DSP2RX_EQ_B4_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B4_B_WIDTH                 16  /* DSP2RX_EQ_B4_B - [15:0] */
+
+/*
+ * R1423 (0x58F) - DSP2 RX EQ Band 4 C
+ */
+#define WM8915_DSP2RX_EQ_B4_C_MASK              0xFFFF  /* DSP2RX_EQ_B4_C - [15:0] */
+#define WM8915_DSP2RX_EQ_B4_C_SHIFT                  0  /* DSP2RX_EQ_B4_C - [15:0] */
+#define WM8915_DSP2RX_EQ_B4_C_WIDTH                 16  /* DSP2RX_EQ_B4_C - [15:0] */
+
+/*
+ * R1424 (0x590) - DSP2 RX EQ Band 4 PG
+ */
+#define WM8915_DSP2RX_EQ_B4_PG_MASK             0xFFFF  /* DSP2RX_EQ_B4_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B4_PG_SHIFT                 0  /* DSP2RX_EQ_B4_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B4_PG_WIDTH                16  /* DSP2RX_EQ_B4_PG - [15:0] */
+
+/*
+ * R1425 (0x591) - DSP2 RX EQ Band 5 A
+ */
+#define WM8915_DSP2RX_EQ_B5_A_MASK              0xFFFF  /* DSP2RX_EQ_B5_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B5_A_SHIFT                  0  /* DSP2RX_EQ_B5_A - [15:0] */
+#define WM8915_DSP2RX_EQ_B5_A_WIDTH                 16  /* DSP2RX_EQ_B5_A - [15:0] */
+
+/*
+ * R1426 (0x592) - DSP2 RX EQ Band 5 B
+ */
+#define WM8915_DSP2RX_EQ_B5_B_MASK              0xFFFF  /* DSP2RX_EQ_B5_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B5_B_SHIFT                  0  /* DSP2RX_EQ_B5_B - [15:0] */
+#define WM8915_DSP2RX_EQ_B5_B_WIDTH                 16  /* DSP2RX_EQ_B5_B - [15:0] */
+
+/*
+ * R1427 (0x593) - DSP2 RX EQ Band 5 PG
+ */
+#define WM8915_DSP2RX_EQ_B5_PG_MASK             0xFFFF  /* DSP2RX_EQ_B5_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B5_PG_SHIFT                 0  /* DSP2RX_EQ_B5_PG - [15:0] */
+#define WM8915_DSP2RX_EQ_B5_PG_WIDTH                16  /* DSP2RX_EQ_B5_PG - [15:0] */
+
+/*
+ * R1536 (0x600) - DAC1 Mixer Volumes
+ */
+#define WM8915_ADCR_DAC1_VOL_MASK               0x03E0  /* ADCR_DAC1_VOL - [9:5] */
+#define WM8915_ADCR_DAC1_VOL_SHIFT                   5  /* ADCR_DAC1_VOL - [9:5] */
+#define WM8915_ADCR_DAC1_VOL_WIDTH                   5  /* ADCR_DAC1_VOL - [9:5] */
+#define WM8915_ADCL_DAC1_VOL_MASK               0x001F  /* ADCL_DAC1_VOL - [4:0] */
+#define WM8915_ADCL_DAC1_VOL_SHIFT                   0  /* ADCL_DAC1_VOL - [4:0] */
+#define WM8915_ADCL_DAC1_VOL_WIDTH                   5  /* ADCL_DAC1_VOL - [4:0] */
+
+/*
+ * R1537 (0x601) - DAC1 Left Mixer Routing
+ */
+#define WM8915_ADCR_TO_DAC1L                    0x0020  /* ADCR_TO_DAC1L */
+#define WM8915_ADCR_TO_DAC1L_MASK               0x0020  /* ADCR_TO_DAC1L */
+#define WM8915_ADCR_TO_DAC1L_SHIFT                   5  /* ADCR_TO_DAC1L */
+#define WM8915_ADCR_TO_DAC1L_WIDTH                   1  /* ADCR_TO_DAC1L */
+#define WM8915_ADCL_TO_DAC1L                    0x0010  /* ADCL_TO_DAC1L */
+#define WM8915_ADCL_TO_DAC1L_MASK               0x0010  /* ADCL_TO_DAC1L */
+#define WM8915_ADCL_TO_DAC1L_SHIFT                   4  /* ADCL_TO_DAC1L */
+#define WM8915_ADCL_TO_DAC1L_WIDTH                   1  /* ADCL_TO_DAC1L */
+#define WM8915_DSP2RXL_TO_DAC1L                 0x0002  /* DSP2RXL_TO_DAC1L */
+#define WM8915_DSP2RXL_TO_DAC1L_MASK            0x0002  /* DSP2RXL_TO_DAC1L */
+#define WM8915_DSP2RXL_TO_DAC1L_SHIFT                1  /* DSP2RXL_TO_DAC1L */
+#define WM8915_DSP2RXL_TO_DAC1L_WIDTH                1  /* DSP2RXL_TO_DAC1L */
+#define WM8915_DSP1RXL_TO_DAC1L                 0x0001  /* DSP1RXL_TO_DAC1L */
+#define WM8915_DSP1RXL_TO_DAC1L_MASK            0x0001  /* DSP1RXL_TO_DAC1L */
+#define WM8915_DSP1RXL_TO_DAC1L_SHIFT                0  /* DSP1RXL_TO_DAC1L */
+#define WM8915_DSP1RXL_TO_DAC1L_WIDTH                1  /* DSP1RXL_TO_DAC1L */
+
+/*
+ * R1538 (0x602) - DAC1 Right Mixer Routing
+ */
+#define WM8915_ADCR_TO_DAC1R                    0x0020  /* ADCR_TO_DAC1R */
+#define WM8915_ADCR_TO_DAC1R_MASK               0x0020  /* ADCR_TO_DAC1R */
+#define WM8915_ADCR_TO_DAC1R_SHIFT                   5  /* ADCR_TO_DAC1R */
+#define WM8915_ADCR_TO_DAC1R_WIDTH                   1  /* ADCR_TO_DAC1R */
+#define WM8915_ADCL_TO_DAC1R                    0x0010  /* ADCL_TO_DAC1R */
+#define WM8915_ADCL_TO_DAC1R_MASK               0x0010  /* ADCL_TO_DAC1R */
+#define WM8915_ADCL_TO_DAC1R_SHIFT                   4  /* ADCL_TO_DAC1R */
+#define WM8915_ADCL_TO_DAC1R_WIDTH                   1  /* ADCL_TO_DAC1R */
+#define WM8915_DSP2RXR_TO_DAC1R                 0x0002  /* DSP2RXR_TO_DAC1R */
+#define WM8915_DSP2RXR_TO_DAC1R_MASK            0x0002  /* DSP2RXR_TO_DAC1R */
+#define WM8915_DSP2RXR_TO_DAC1R_SHIFT                1  /* DSP2RXR_TO_DAC1R */
+#define WM8915_DSP2RXR_TO_DAC1R_WIDTH                1  /* DSP2RXR_TO_DAC1R */
+#define WM8915_DSP1RXR_TO_DAC1R                 0x0001  /* DSP1RXR_TO_DAC1R */
+#define WM8915_DSP1RXR_TO_DAC1R_MASK            0x0001  /* DSP1RXR_TO_DAC1R */
+#define WM8915_DSP1RXR_TO_DAC1R_SHIFT                0  /* DSP1RXR_TO_DAC1R */
+#define WM8915_DSP1RXR_TO_DAC1R_WIDTH                1  /* DSP1RXR_TO_DAC1R */
+
+/*
+ * R1539 (0x603) - DAC2 Mixer Volumes
+ */
+#define WM8915_ADCR_DAC2_VOL_MASK               0x03E0  /* ADCR_DAC2_VOL - [9:5] */
+#define WM8915_ADCR_DAC2_VOL_SHIFT                   5  /* ADCR_DAC2_VOL - [9:5] */
+#define WM8915_ADCR_DAC2_VOL_WIDTH                   5  /* ADCR_DAC2_VOL - [9:5] */
+#define WM8915_ADCL_DAC2_VOL_MASK               0x001F  /* ADCL_DAC2_VOL - [4:0] */
+#define WM8915_ADCL_DAC2_VOL_SHIFT                   0  /* ADCL_DAC2_VOL - [4:0] */
+#define WM8915_ADCL_DAC2_VOL_WIDTH                   5  /* ADCL_DAC2_VOL - [4:0] */
+
+/*
+ * R1540 (0x604) - DAC2 Left Mixer Routing
+ */
+#define WM8915_ADCR_TO_DAC2L                    0x0020  /* ADCR_TO_DAC2L */
+#define WM8915_ADCR_TO_DAC2L_MASK               0x0020  /* ADCR_TO_DAC2L */
+#define WM8915_ADCR_TO_DAC2L_SHIFT                   5  /* ADCR_TO_DAC2L */
+#define WM8915_ADCR_TO_DAC2L_WIDTH                   1  /* ADCR_TO_DAC2L */
+#define WM8915_ADCL_TO_DAC2L                    0x0010  /* ADCL_TO_DAC2L */
+#define WM8915_ADCL_TO_DAC2L_MASK               0x0010  /* ADCL_TO_DAC2L */
+#define WM8915_ADCL_TO_DAC2L_SHIFT                   4  /* ADCL_TO_DAC2L */
+#define WM8915_ADCL_TO_DAC2L_WIDTH                   1  /* ADCL_TO_DAC2L */
+#define WM8915_DSP2RXL_TO_DAC2L                 0x0002  /* DSP2RXL_TO_DAC2L */
+#define WM8915_DSP2RXL_TO_DAC2L_MASK            0x0002  /* DSP2RXL_TO_DAC2L */
+#define WM8915_DSP2RXL_TO_DAC2L_SHIFT                1  /* DSP2RXL_TO_DAC2L */
+#define WM8915_DSP2RXL_TO_DAC2L_WIDTH                1  /* DSP2RXL_TO_DAC2L */
+#define WM8915_DSP1RXL_TO_DAC2L                 0x0001  /* DSP1RXL_TO_DAC2L */
+#define WM8915_DSP1RXL_TO_DAC2L_MASK            0x0001  /* DSP1RXL_TO_DAC2L */
+#define WM8915_DSP1RXL_TO_DAC2L_SHIFT                0  /* DSP1RXL_TO_DAC2L */
+#define WM8915_DSP1RXL_TO_DAC2L_WIDTH                1  /* DSP1RXL_TO_DAC2L */
+
+/*
+ * R1541 (0x605) - DAC2 Right Mixer Routing
+ */
+#define WM8915_ADCR_TO_DAC2R                    0x0020  /* ADCR_TO_DAC2R */
+#define WM8915_ADCR_TO_DAC2R_MASK               0x0020  /* ADCR_TO_DAC2R */
+#define WM8915_ADCR_TO_DAC2R_SHIFT                   5  /* ADCR_TO_DAC2R */
+#define WM8915_ADCR_TO_DAC2R_WIDTH                   1  /* ADCR_TO_DAC2R */
+#define WM8915_ADCL_TO_DAC2R                    0x0010  /* ADCL_TO_DAC2R */
+#define WM8915_ADCL_TO_DAC2R_MASK               0x0010  /* ADCL_TO_DAC2R */
+#define WM8915_ADCL_TO_DAC2R_SHIFT                   4  /* ADCL_TO_DAC2R */
+#define WM8915_ADCL_TO_DAC2R_WIDTH                   1  /* ADCL_TO_DAC2R */
+#define WM8915_DSP2RXR_TO_DAC2R                 0x0002  /* DSP2RXR_TO_DAC2R */
+#define WM8915_DSP2RXR_TO_DAC2R_MASK            0x0002  /* DSP2RXR_TO_DAC2R */
+#define WM8915_DSP2RXR_TO_DAC2R_SHIFT                1  /* DSP2RXR_TO_DAC2R */
+#define WM8915_DSP2RXR_TO_DAC2R_WIDTH                1  /* DSP2RXR_TO_DAC2R */
+#define WM8915_DSP1RXR_TO_DAC2R                 0x0001  /* DSP1RXR_TO_DAC2R */
+#define WM8915_DSP1RXR_TO_DAC2R_MASK            0x0001  /* DSP1RXR_TO_DAC2R */
+#define WM8915_DSP1RXR_TO_DAC2R_SHIFT                0  /* DSP1RXR_TO_DAC2R */
+#define WM8915_DSP1RXR_TO_DAC2R_WIDTH                1  /* DSP1RXR_TO_DAC2R */
+
+/*
+ * R1542 (0x606) - DSP1 TX Left Mixer Routing
+ */
+#define WM8915_ADC1L_TO_DSP1TXL                 0x0002  /* ADC1L_TO_DSP1TXL */
+#define WM8915_ADC1L_TO_DSP1TXL_MASK            0x0002  /* ADC1L_TO_DSP1TXL */
+#define WM8915_ADC1L_TO_DSP1TXL_SHIFT                1  /* ADC1L_TO_DSP1TXL */
+#define WM8915_ADC1L_TO_DSP1TXL_WIDTH                1  /* ADC1L_TO_DSP1TXL */
+#define WM8915_DACL_TO_DSP1TXL                  0x0001  /* DACL_TO_DSP1TXL */
+#define WM8915_DACL_TO_DSP1TXL_MASK             0x0001  /* DACL_TO_DSP1TXL */
+#define WM8915_DACL_TO_DSP1TXL_SHIFT                 0  /* DACL_TO_DSP1TXL */
+#define WM8915_DACL_TO_DSP1TXL_WIDTH                 1  /* DACL_TO_DSP1TXL */
+
+/*
+ * R1543 (0x607) - DSP1 TX Right Mixer Routing
+ */
+#define WM8915_ADC1R_TO_DSP1TXR                 0x0002  /* ADC1R_TO_DSP1TXR */
+#define WM8915_ADC1R_TO_DSP1TXR_MASK            0x0002  /* ADC1R_TO_DSP1TXR */
+#define WM8915_ADC1R_TO_DSP1TXR_SHIFT                1  /* ADC1R_TO_DSP1TXR */
+#define WM8915_ADC1R_TO_DSP1TXR_WIDTH                1  /* ADC1R_TO_DSP1TXR */
+#define WM8915_DACR_TO_DSP1TXR                  0x0001  /* DACR_TO_DSP1TXR */
+#define WM8915_DACR_TO_DSP1TXR_MASK             0x0001  /* DACR_TO_DSP1TXR */
+#define WM8915_DACR_TO_DSP1TXR_SHIFT                 0  /* DACR_TO_DSP1TXR */
+#define WM8915_DACR_TO_DSP1TXR_WIDTH                 1  /* DACR_TO_DSP1TXR */
+
+/*
+ * R1544 (0x608) - DSP2 TX Left Mixer Routing
+ */
+#define WM8915_ADC2L_TO_DSP2TXL                 0x0002  /* ADC2L_TO_DSP2TXL */
+#define WM8915_ADC2L_TO_DSP2TXL_MASK            0x0002  /* ADC2L_TO_DSP2TXL */
+#define WM8915_ADC2L_TO_DSP2TXL_SHIFT                1  /* ADC2L_TO_DSP2TXL */
+#define WM8915_ADC2L_TO_DSP2TXL_WIDTH                1  /* ADC2L_TO_DSP2TXL */
+#define WM8915_DACL_TO_DSP2TXL                  0x0001  /* DACL_TO_DSP2TXL */
+#define WM8915_DACL_TO_DSP2TXL_MASK             0x0001  /* DACL_TO_DSP2TXL */
+#define WM8915_DACL_TO_DSP2TXL_SHIFT                 0  /* DACL_TO_DSP2TXL */
+#define WM8915_DACL_TO_DSP2TXL_WIDTH                 1  /* DACL_TO_DSP2TXL */
+
+/*
+ * R1545 (0x609) - DSP2 TX Right Mixer Routing
+ */
+#define WM8915_ADC2R_TO_DSP2TXR                 0x0002  /* ADC2R_TO_DSP2TXR */
+#define WM8915_ADC2R_TO_DSP2TXR_MASK            0x0002  /* ADC2R_TO_DSP2TXR */
+#define WM8915_ADC2R_TO_DSP2TXR_SHIFT                1  /* ADC2R_TO_DSP2TXR */
+#define WM8915_ADC2R_TO_DSP2TXR_WIDTH                1  /* ADC2R_TO_DSP2TXR */
+#define WM8915_DACR_TO_DSP2TXR                  0x0001  /* DACR_TO_DSP2TXR */
+#define WM8915_DACR_TO_DSP2TXR_MASK             0x0001  /* DACR_TO_DSP2TXR */
+#define WM8915_DACR_TO_DSP2TXR_SHIFT                 0  /* DACR_TO_DSP2TXR */
+#define WM8915_DACR_TO_DSP2TXR_WIDTH                 1  /* DACR_TO_DSP2TXR */
+
+/*
+ * R1546 (0x60A) - DSP TX Mixer Select
+ */
+#define WM8915_DAC_TO_DSPTX_SRC                 0x0001  /* DAC_TO_DSPTX_SRC */
+#define WM8915_DAC_TO_DSPTX_SRC_MASK            0x0001  /* DAC_TO_DSPTX_SRC */
+#define WM8915_DAC_TO_DSPTX_SRC_SHIFT                0  /* DAC_TO_DSPTX_SRC */
+#define WM8915_DAC_TO_DSPTX_SRC_WIDTH                1  /* DAC_TO_DSPTX_SRC */
+
+/*
+ * R1552 (0x610) - DAC Softmute
+ */
+#define WM8915_DAC_SOFTMUTEMODE                 0x0002  /* DAC_SOFTMUTEMODE */
+#define WM8915_DAC_SOFTMUTEMODE_MASK            0x0002  /* DAC_SOFTMUTEMODE */
+#define WM8915_DAC_SOFTMUTEMODE_SHIFT                1  /* DAC_SOFTMUTEMODE */
+#define WM8915_DAC_SOFTMUTEMODE_WIDTH                1  /* DAC_SOFTMUTEMODE */
+#define WM8915_DAC_MUTERATE                     0x0001  /* DAC_MUTERATE */
+#define WM8915_DAC_MUTERATE_MASK                0x0001  /* DAC_MUTERATE */
+#define WM8915_DAC_MUTERATE_SHIFT                    0  /* DAC_MUTERATE */
+#define WM8915_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
+
+/*
+ * R1568 (0x620) - Oversampling
+ */
+#define WM8915_SPK_OSR128                       0x0008  /* SPK_OSR128 */
+#define WM8915_SPK_OSR128_MASK                  0x0008  /* SPK_OSR128 */
+#define WM8915_SPK_OSR128_SHIFT                      3  /* SPK_OSR128 */
+#define WM8915_SPK_OSR128_WIDTH                      1  /* SPK_OSR128 */
+#define WM8915_DMIC_OSR64                       0x0004  /* DMIC_OSR64 */
+#define WM8915_DMIC_OSR64_MASK                  0x0004  /* DMIC_OSR64 */
+#define WM8915_DMIC_OSR64_SHIFT                      2  /* DMIC_OSR64 */
+#define WM8915_DMIC_OSR64_WIDTH                      1  /* DMIC_OSR64 */
+#define WM8915_ADC_OSR128                       0x0002  /* ADC_OSR128 */
+#define WM8915_ADC_OSR128_MASK                  0x0002  /* ADC_OSR128 */
+#define WM8915_ADC_OSR128_SHIFT                      1  /* ADC_OSR128 */
+#define WM8915_ADC_OSR128_WIDTH                      1  /* ADC_OSR128 */
+#define WM8915_DAC_OSR128                       0x0001  /* DAC_OSR128 */
+#define WM8915_DAC_OSR128_MASK                  0x0001  /* DAC_OSR128 */
+#define WM8915_DAC_OSR128_SHIFT                      0  /* DAC_OSR128 */
+#define WM8915_DAC_OSR128_WIDTH                      1  /* DAC_OSR128 */
+
+/*
+ * R1569 (0x621) - Sidetone
+ */
+#define WM8915_ST_LPF                           0x1000  /* ST_LPF */
+#define WM8915_ST_LPF_MASK                      0x1000  /* ST_LPF */
+#define WM8915_ST_LPF_SHIFT                         12  /* ST_LPF */
+#define WM8915_ST_LPF_WIDTH                          1  /* ST_LPF */
+#define WM8915_ST_HPF_CUT_MASK                  0x0380  /* ST_HPF_CUT - [9:7] */
+#define WM8915_ST_HPF_CUT_SHIFT                      7  /* ST_HPF_CUT - [9:7] */
+#define WM8915_ST_HPF_CUT_WIDTH                      3  /* ST_HPF_CUT - [9:7] */
+#define WM8915_ST_HPF                           0x0040  /* ST_HPF */
+#define WM8915_ST_HPF_MASK                      0x0040  /* ST_HPF */
+#define WM8915_ST_HPF_SHIFT                          6  /* ST_HPF */
+#define WM8915_ST_HPF_WIDTH                          1  /* ST_HPF */
+#define WM8915_STR_SEL                          0x0002  /* STR_SEL */
+#define WM8915_STR_SEL_MASK                     0x0002  /* STR_SEL */
+#define WM8915_STR_SEL_SHIFT                         1  /* STR_SEL */
+#define WM8915_STR_SEL_WIDTH                         1  /* STR_SEL */
+#define WM8915_STL_SEL                          0x0001  /* STL_SEL */
+#define WM8915_STL_SEL_MASK                     0x0001  /* STL_SEL */
+#define WM8915_STL_SEL_SHIFT                         0  /* STL_SEL */
+#define WM8915_STL_SEL_WIDTH                         1  /* STL_SEL */
+
+/*
+ * R1792 (0x700) - GPIO 1
+ */
+#define WM8915_GP1_DIR                          0x8000  /* GP1_DIR */
+#define WM8915_GP1_DIR_MASK                     0x8000  /* GP1_DIR */
+#define WM8915_GP1_DIR_SHIFT                        15  /* GP1_DIR */
+#define WM8915_GP1_DIR_WIDTH                         1  /* GP1_DIR */
+#define WM8915_GP1_PU                           0x4000  /* GP1_PU */
+#define WM8915_GP1_PU_MASK                      0x4000  /* GP1_PU */
+#define WM8915_GP1_PU_SHIFT                         14  /* GP1_PU */
+#define WM8915_GP1_PU_WIDTH                          1  /* GP1_PU */
+#define WM8915_GP1_PD                           0x2000  /* GP1_PD */
+#define WM8915_GP1_PD_MASK                      0x2000  /* GP1_PD */
+#define WM8915_GP1_PD_SHIFT                         13  /* GP1_PD */
+#define WM8915_GP1_PD_WIDTH                          1  /* GP1_PD */
+#define WM8915_GP1_POL                          0x0400  /* GP1_POL */
+#define WM8915_GP1_POL_MASK                     0x0400  /* GP1_POL */
+#define WM8915_GP1_POL_SHIFT                        10  /* GP1_POL */
+#define WM8915_GP1_POL_WIDTH                         1  /* GP1_POL */
+#define WM8915_GP1_OP_CFG                       0x0200  /* GP1_OP_CFG */
+#define WM8915_GP1_OP_CFG_MASK                  0x0200  /* GP1_OP_CFG */
+#define WM8915_GP1_OP_CFG_SHIFT                      9  /* GP1_OP_CFG */
+#define WM8915_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
+#define WM8915_GP1_DB                           0x0100  /* GP1_DB */
+#define WM8915_GP1_DB_MASK                      0x0100  /* GP1_DB */
+#define WM8915_GP1_DB_SHIFT                          8  /* GP1_DB */
+#define WM8915_GP1_DB_WIDTH                          1  /* GP1_DB */
+#define WM8915_GP1_LVL                          0x0040  /* GP1_LVL */
+#define WM8915_GP1_LVL_MASK                     0x0040  /* GP1_LVL */
+#define WM8915_GP1_LVL_SHIFT                         6  /* GP1_LVL */
+#define WM8915_GP1_LVL_WIDTH                         1  /* GP1_LVL */
+#define WM8915_GP1_FN_MASK                      0x000F  /* GP1_FN - [3:0] */
+#define WM8915_GP1_FN_SHIFT                          0  /* GP1_FN - [3:0] */
+#define WM8915_GP1_FN_WIDTH                          4  /* GP1_FN - [3:0] */
+
+/*
+ * R1793 (0x701) - GPIO 2
+ */
+#define WM8915_GP2_DIR                          0x8000  /* GP2_DIR */
+#define WM8915_GP2_DIR_MASK                     0x8000  /* GP2_DIR */
+#define WM8915_GP2_DIR_SHIFT                        15  /* GP2_DIR */
+#define WM8915_GP2_DIR_WIDTH                         1  /* GP2_DIR */
+#define WM8915_GP2_PU                           0x4000  /* GP2_PU */
+#define WM8915_GP2_PU_MASK                      0x4000  /* GP2_PU */
+#define WM8915_GP2_PU_SHIFT                         14  /* GP2_PU */
+#define WM8915_GP2_PU_WIDTH                          1  /* GP2_PU */
+#define WM8915_GP2_PD                           0x2000  /* GP2_PD */
+#define WM8915_GP2_PD_MASK                      0x2000  /* GP2_PD */
+#define WM8915_GP2_PD_SHIFT                         13  /* GP2_PD */
+#define WM8915_GP2_PD_WIDTH                          1  /* GP2_PD */
+#define WM8915_GP2_POL                          0x0400  /* GP2_POL */
+#define WM8915_GP2_POL_MASK                     0x0400  /* GP2_POL */
+#define WM8915_GP2_POL_SHIFT                        10  /* GP2_POL */
+#define WM8915_GP2_POL_WIDTH                         1  /* GP2_POL */
+#define WM8915_GP2_OP_CFG                       0x0200  /* GP2_OP_CFG */
+#define WM8915_GP2_OP_CFG_MASK                  0x0200  /* GP2_OP_CFG */
+#define WM8915_GP2_OP_CFG_SHIFT                      9  /* GP2_OP_CFG */
+#define WM8915_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
+#define WM8915_GP2_DB                           0x0100  /* GP2_DB */
+#define WM8915_GP2_DB_MASK                      0x0100  /* GP2_DB */
+#define WM8915_GP2_DB_SHIFT                          8  /* GP2_DB */
+#define WM8915_GP2_DB_WIDTH                          1  /* GP2_DB */
+#define WM8915_GP2_LVL                          0x0040  /* GP2_LVL */
+#define WM8915_GP2_LVL_MASK                     0x0040  /* GP2_LVL */
+#define WM8915_GP2_LVL_SHIFT                         6  /* GP2_LVL */
+#define WM8915_GP2_LVL_WIDTH                         1  /* GP2_LVL */
+#define WM8915_GP2_FN_MASK                      0x000F  /* GP2_FN - [3:0] */
+#define WM8915_GP2_FN_SHIFT                          0  /* GP2_FN - [3:0] */
+#define WM8915_GP2_FN_WIDTH                          4  /* GP2_FN - [3:0] */
+
+/*
+ * R1794 (0x702) - GPIO 3
+ */
+#define WM8915_GP3_DIR                          0x8000  /* GP3_DIR */
+#define WM8915_GP3_DIR_MASK                     0x8000  /* GP3_DIR */
+#define WM8915_GP3_DIR_SHIFT                        15  /* GP3_DIR */
+#define WM8915_GP3_DIR_WIDTH                         1  /* GP3_DIR */
+#define WM8915_GP3_PU                           0x4000  /* GP3_PU */
+#define WM8915_GP3_PU_MASK                      0x4000  /* GP3_PU */
+#define WM8915_GP3_PU_SHIFT                         14  /* GP3_PU */
+#define WM8915_GP3_PU_WIDTH                          1  /* GP3_PU */
+#define WM8915_GP3_PD                           0x2000  /* GP3_PD */
+#define WM8915_GP3_PD_MASK                      0x2000  /* GP3_PD */
+#define WM8915_GP3_PD_SHIFT                         13  /* GP3_PD */
+#define WM8915_GP3_PD_WIDTH                          1  /* GP3_PD */
+#define WM8915_GP3_POL                          0x0400  /* GP3_POL */
+#define WM8915_GP3_POL_MASK                     0x0400  /* GP3_POL */
+#define WM8915_GP3_POL_SHIFT                        10  /* GP3_POL */
+#define WM8915_GP3_POL_WIDTH                         1  /* GP3_POL */
+#define WM8915_GP3_OP_CFG                       0x0200  /* GP3_OP_CFG */
+#define WM8915_GP3_OP_CFG_MASK                  0x0200  /* GP3_OP_CFG */
+#define WM8915_GP3_OP_CFG_SHIFT                      9  /* GP3_OP_CFG */
+#define WM8915_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
+#define WM8915_GP3_DB                           0x0100  /* GP3_DB */
+#define WM8915_GP3_DB_MASK                      0x0100  /* GP3_DB */
+#define WM8915_GP3_DB_SHIFT                          8  /* GP3_DB */
+#define WM8915_GP3_DB_WIDTH                          1  /* GP3_DB */
+#define WM8915_GP3_LVL                          0x0040  /* GP3_LVL */
+#define WM8915_GP3_LVL_MASK                     0x0040  /* GP3_LVL */
+#define WM8915_GP3_LVL_SHIFT                         6  /* GP3_LVL */
+#define WM8915_GP3_LVL_WIDTH                         1  /* GP3_LVL */
+#define WM8915_GP3_FN_MASK                      0x000F  /* GP3_FN - [3:0] */
+#define WM8915_GP3_FN_SHIFT                          0  /* GP3_FN - [3:0] */
+#define WM8915_GP3_FN_WIDTH                          4  /* GP3_FN - [3:0] */
+
+/*
+ * R1795 (0x703) - GPIO 4
+ */
+#define WM8915_GP4_DIR                          0x8000  /* GP4_DIR */
+#define WM8915_GP4_DIR_MASK                     0x8000  /* GP4_DIR */
+#define WM8915_GP4_DIR_SHIFT                        15  /* GP4_DIR */
+#define WM8915_GP4_DIR_WIDTH                         1  /* GP4_DIR */
+#define WM8915_GP4_PU                           0x4000  /* GP4_PU */
+#define WM8915_GP4_PU_MASK                      0x4000  /* GP4_PU */
+#define WM8915_GP4_PU_SHIFT                         14  /* GP4_PU */
+#define WM8915_GP4_PU_WIDTH                          1  /* GP4_PU */
+#define WM8915_GP4_PD                           0x2000  /* GP4_PD */
+#define WM8915_GP4_PD_MASK                      0x2000  /* GP4_PD */
+#define WM8915_GP4_PD_SHIFT                         13  /* GP4_PD */
+#define WM8915_GP4_PD_WIDTH                          1  /* GP4_PD */
+#define WM8915_GP4_POL                          0x0400  /* GP4_POL */
+#define WM8915_GP4_POL_MASK                     0x0400  /* GP4_POL */
+#define WM8915_GP4_POL_SHIFT                        10  /* GP4_POL */
+#define WM8915_GP4_POL_WIDTH                         1  /* GP4_POL */
+#define WM8915_GP4_OP_CFG                       0x0200  /* GP4_OP_CFG */
+#define WM8915_GP4_OP_CFG_MASK                  0x0200  /* GP4_OP_CFG */
+#define WM8915_GP4_OP_CFG_SHIFT                      9  /* GP4_OP_CFG */
+#define WM8915_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
+#define WM8915_GP4_DB                           0x0100  /* GP4_DB */
+#define WM8915_GP4_DB_MASK                      0x0100  /* GP4_DB */
+#define WM8915_GP4_DB_SHIFT                          8  /* GP4_DB */
+#define WM8915_GP4_DB_WIDTH                          1  /* GP4_DB */
+#define WM8915_GP4_LVL                          0x0040  /* GP4_LVL */
+#define WM8915_GP4_LVL_MASK                     0x0040  /* GP4_LVL */
+#define WM8915_GP4_LVL_SHIFT                         6  /* GP4_LVL */
+#define WM8915_GP4_LVL_WIDTH                         1  /* GP4_LVL */
+#define WM8915_GP4_FN_MASK                      0x000F  /* GP4_FN - [3:0] */
+#define WM8915_GP4_FN_SHIFT                          0  /* GP4_FN - [3:0] */
+#define WM8915_GP4_FN_WIDTH                          4  /* GP4_FN - [3:0] */
+
+/*
+ * R1796 (0x704) - GPIO 5
+ */
+#define WM8915_GP5_DIR                          0x8000  /* GP5_DIR */
+#define WM8915_GP5_DIR_MASK                     0x8000  /* GP5_DIR */
+#define WM8915_GP5_DIR_SHIFT                        15  /* GP5_DIR */
+#define WM8915_GP5_DIR_WIDTH                         1  /* GP5_DIR */
+#define WM8915_GP5_PU                           0x4000  /* GP5_PU */
+#define WM8915_GP5_PU_MASK                      0x4000  /* GP5_PU */
+#define WM8915_GP5_PU_SHIFT                         14  /* GP5_PU */
+#define WM8915_GP5_PU_WIDTH                          1  /* GP5_PU */
+#define WM8915_GP5_PD                           0x2000  /* GP5_PD */
+#define WM8915_GP5_PD_MASK                      0x2000  /* GP5_PD */
+#define WM8915_GP5_PD_SHIFT                         13  /* GP5_PD */
+#define WM8915_GP5_PD_WIDTH                          1  /* GP5_PD */
+#define WM8915_GP5_POL                          0x0400  /* GP5_POL */
+#define WM8915_GP5_POL_MASK                     0x0400  /* GP5_POL */
+#define WM8915_GP5_POL_SHIFT                        10  /* GP5_POL */
+#define WM8915_GP5_POL_WIDTH                         1  /* GP5_POL */
+#define WM8915_GP5_OP_CFG                       0x0200  /* GP5_OP_CFG */
+#define WM8915_GP5_OP_CFG_MASK                  0x0200  /* GP5_OP_CFG */
+#define WM8915_GP5_OP_CFG_SHIFT                      9  /* GP5_OP_CFG */
+#define WM8915_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
+#define WM8915_GP5_DB                           0x0100  /* GP5_DB */
+#define WM8915_GP5_DB_MASK                      0x0100  /* GP5_DB */
+#define WM8915_GP5_DB_SHIFT                          8  /* GP5_DB */
+#define WM8915_GP5_DB_WIDTH                          1  /* GP5_DB */
+#define WM8915_GP5_LVL                          0x0040  /* GP5_LVL */
+#define WM8915_GP5_LVL_MASK                     0x0040  /* GP5_LVL */
+#define WM8915_GP5_LVL_SHIFT                         6  /* GP5_LVL */
+#define WM8915_GP5_LVL_WIDTH                         1  /* GP5_LVL */
+#define WM8915_GP5_FN_MASK                      0x000F  /* GP5_FN - [3:0] */
+#define WM8915_GP5_FN_SHIFT                          0  /* GP5_FN - [3:0] */
+#define WM8915_GP5_FN_WIDTH                          4  /* GP5_FN - [3:0] */
+
+/*
+ * R1824 (0x720) - Pull Control (1)
+ */
+#define WM8915_DMICDAT2_PD                      0x1000  /* DMICDAT2_PD */
+#define WM8915_DMICDAT2_PD_MASK                 0x1000  /* DMICDAT2_PD */
+#define WM8915_DMICDAT2_PD_SHIFT                    12  /* DMICDAT2_PD */
+#define WM8915_DMICDAT2_PD_WIDTH                     1  /* DMICDAT2_PD */
+#define WM8915_DMICDAT1_PD                      0x0400  /* DMICDAT1_PD */
+#define WM8915_DMICDAT1_PD_MASK                 0x0400  /* DMICDAT1_PD */
+#define WM8915_DMICDAT1_PD_SHIFT                    10  /* DMICDAT1_PD */
+#define WM8915_DMICDAT1_PD_WIDTH                     1  /* DMICDAT1_PD */
+#define WM8915_MCLK2_PU                         0x0200  /* MCLK2_PU */
+#define WM8915_MCLK2_PU_MASK                    0x0200  /* MCLK2_PU */
+#define WM8915_MCLK2_PU_SHIFT                        9  /* MCLK2_PU */
+#define WM8915_MCLK2_PU_WIDTH                        1  /* MCLK2_PU */
+#define WM8915_MCLK2_PD                         0x0100  /* MCLK2_PD */
+#define WM8915_MCLK2_PD_MASK                    0x0100  /* MCLK2_PD */
+#define WM8915_MCLK2_PD_SHIFT                        8  /* MCLK2_PD */
+#define WM8915_MCLK2_PD_WIDTH                        1  /* MCLK2_PD */
+#define WM8915_MCLK1_PU                         0x0080  /* MCLK1_PU */
+#define WM8915_MCLK1_PU_MASK                    0x0080  /* MCLK1_PU */
+#define WM8915_MCLK1_PU_SHIFT                        7  /* MCLK1_PU */
+#define WM8915_MCLK1_PU_WIDTH                        1  /* MCLK1_PU */
+#define WM8915_MCLK1_PD                         0x0040  /* MCLK1_PD */
+#define WM8915_MCLK1_PD_MASK                    0x0040  /* MCLK1_PD */
+#define WM8915_MCLK1_PD_SHIFT                        6  /* MCLK1_PD */
+#define WM8915_MCLK1_PD_WIDTH                        1  /* MCLK1_PD */
+#define WM8915_DACDAT1_PU                       0x0020  /* DACDAT1_PU */
+#define WM8915_DACDAT1_PU_MASK                  0x0020  /* DACDAT1_PU */
+#define WM8915_DACDAT1_PU_SHIFT                      5  /* DACDAT1_PU */
+#define WM8915_DACDAT1_PU_WIDTH                      1  /* DACDAT1_PU */
+#define WM8915_DACDAT1_PD                       0x0010  /* DACDAT1_PD */
+#define WM8915_DACDAT1_PD_MASK                  0x0010  /* DACDAT1_PD */
+#define WM8915_DACDAT1_PD_SHIFT                      4  /* DACDAT1_PD */
+#define WM8915_DACDAT1_PD_WIDTH                      1  /* DACDAT1_PD */
+#define WM8915_DACLRCLK1_PU                     0x0008  /* DACLRCLK1_PU */
+#define WM8915_DACLRCLK1_PU_MASK                0x0008  /* DACLRCLK1_PU */
+#define WM8915_DACLRCLK1_PU_SHIFT                    3  /* DACLRCLK1_PU */
+#define WM8915_DACLRCLK1_PU_WIDTH                    1  /* DACLRCLK1_PU */
+#define WM8915_DACLRCLK1_PD                     0x0004  /* DACLRCLK1_PD */
+#define WM8915_DACLRCLK1_PD_MASK                0x0004  /* DACLRCLK1_PD */
+#define WM8915_DACLRCLK1_PD_SHIFT                    2  /* DACLRCLK1_PD */
+#define WM8915_DACLRCLK1_PD_WIDTH                    1  /* DACLRCLK1_PD */
+#define WM8915_BCLK1_PU                         0x0002  /* BCLK1_PU */
+#define WM8915_BCLK1_PU_MASK                    0x0002  /* BCLK1_PU */
+#define WM8915_BCLK1_PU_SHIFT                        1  /* BCLK1_PU */
+#define WM8915_BCLK1_PU_WIDTH                        1  /* BCLK1_PU */
+#define WM8915_BCLK1_PD                         0x0001  /* BCLK1_PD */
+#define WM8915_BCLK1_PD_MASK                    0x0001  /* BCLK1_PD */
+#define WM8915_BCLK1_PD_SHIFT                        0  /* BCLK1_PD */
+#define WM8915_BCLK1_PD_WIDTH                        1  /* BCLK1_PD */
+
+/*
+ * R1825 (0x721) - Pull Control (2)
+ */
+#define WM8915_LDO1ENA_PD                       0x0100  /* LDO1ENA_PD */
+#define WM8915_LDO1ENA_PD_MASK                  0x0100  /* LDO1ENA_PD */
+#define WM8915_LDO1ENA_PD_SHIFT                      8  /* LDO1ENA_PD */
+#define WM8915_LDO1ENA_PD_WIDTH                      1  /* LDO1ENA_PD */
+#define WM8915_ADDR_PD                          0x0040  /* ADDR_PD */
+#define WM8915_ADDR_PD_MASK                     0x0040  /* ADDR_PD */
+#define WM8915_ADDR_PD_SHIFT                         6  /* ADDR_PD */
+#define WM8915_ADDR_PD_WIDTH                         1  /* ADDR_PD */
+#define WM8915_DACDAT2_PU                       0x0020  /* DACDAT2_PU */
+#define WM8915_DACDAT2_PU_MASK                  0x0020  /* DACDAT2_PU */
+#define WM8915_DACDAT2_PU_SHIFT                      5  /* DACDAT2_PU */
+#define WM8915_DACDAT2_PU_WIDTH                      1  /* DACDAT2_PU */
+#define WM8915_DACDAT2_PD                       0x0010  /* DACDAT2_PD */
+#define WM8915_DACDAT2_PD_MASK                  0x0010  /* DACDAT2_PD */
+#define WM8915_DACDAT2_PD_SHIFT                      4  /* DACDAT2_PD */
+#define WM8915_DACDAT2_PD_WIDTH                      1  /* DACDAT2_PD */
+#define WM8915_DACLRCLK2_PU                     0x0008  /* DACLRCLK2_PU */
+#define WM8915_DACLRCLK2_PU_MASK                0x0008  /* DACLRCLK2_PU */
+#define WM8915_DACLRCLK2_PU_SHIFT                    3  /* DACLRCLK2_PU */
+#define WM8915_DACLRCLK2_PU_WIDTH                    1  /* DACLRCLK2_PU */
+#define WM8915_DACLRCLK2_PD                     0x0004  /* DACLRCLK2_PD */
+#define WM8915_DACLRCLK2_PD_MASK                0x0004  /* DACLRCLK2_PD */
+#define WM8915_DACLRCLK2_PD_SHIFT                    2  /* DACLRCLK2_PD */
+#define WM8915_DACLRCLK2_PD_WIDTH                    1  /* DACLRCLK2_PD */
+#define WM8915_BCLK2_PU                         0x0002  /* BCLK2_PU */
+#define WM8915_BCLK2_PU_MASK                    0x0002  /* BCLK2_PU */
+#define WM8915_BCLK2_PU_SHIFT                        1  /* BCLK2_PU */
+#define WM8915_BCLK2_PU_WIDTH                        1  /* BCLK2_PU */
+#define WM8915_BCLK2_PD                         0x0001  /* BCLK2_PD */
+#define WM8915_BCLK2_PD_MASK                    0x0001  /* BCLK2_PD */
+#define WM8915_BCLK2_PD_SHIFT                        0  /* BCLK2_PD */
+#define WM8915_BCLK2_PD_WIDTH                        1  /* BCLK2_PD */
+
+/*
+ * R1840 (0x730) - Interrupt Status 1
+ */
+#define WM8915_GP5_EINT                         0x0010  /* GP5_EINT */
+#define WM8915_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
+#define WM8915_GP5_EINT_SHIFT                        4  /* GP5_EINT */
+#define WM8915_GP5_EINT_WIDTH                        1  /* GP5_EINT */
+#define WM8915_GP4_EINT                         0x0008  /* GP4_EINT */
+#define WM8915_GP4_EINT_MASK                    0x0008  /* GP4_EINT */
+#define WM8915_GP4_EINT_SHIFT                        3  /* GP4_EINT */
+#define WM8915_GP4_EINT_WIDTH                        1  /* GP4_EINT */
+#define WM8915_GP3_EINT                         0x0004  /* GP3_EINT */
+#define WM8915_GP3_EINT_MASK                    0x0004  /* GP3_EINT */
+#define WM8915_GP3_EINT_SHIFT                        2  /* GP3_EINT */
+#define WM8915_GP3_EINT_WIDTH                        1  /* GP3_EINT */
+#define WM8915_GP2_EINT                         0x0002  /* GP2_EINT */
+#define WM8915_GP2_EINT_MASK                    0x0002  /* GP2_EINT */
+#define WM8915_GP2_EINT_SHIFT                        1  /* GP2_EINT */
+#define WM8915_GP2_EINT_WIDTH                        1  /* GP2_EINT */
+#define WM8915_GP1_EINT                         0x0001  /* GP1_EINT */
+#define WM8915_GP1_EINT_MASK                    0x0001  /* GP1_EINT */
+#define WM8915_GP1_EINT_SHIFT                        0  /* GP1_EINT */
+#define WM8915_GP1_EINT_WIDTH                        1  /* GP1_EINT */
+
+/*
+ * R1841 (0x731) - Interrupt Status 2
+ */
+#define WM8915_DCS_DONE_23_EINT                 0x1000  /* DCS_DONE_23_EINT */
+#define WM8915_DCS_DONE_23_EINT_MASK            0x1000  /* DCS_DONE_23_EINT */
+#define WM8915_DCS_DONE_23_EINT_SHIFT               12  /* DCS_DONE_23_EINT */
+#define WM8915_DCS_DONE_23_EINT_WIDTH                1  /* DCS_DONE_23_EINT */
+#define WM8915_DCS_DONE_01_EINT                 0x0800  /* DCS_DONE_01_EINT */
+#define WM8915_DCS_DONE_01_EINT_MASK            0x0800  /* DCS_DONE_01_EINT */
+#define WM8915_DCS_DONE_01_EINT_SHIFT               11  /* DCS_DONE_01_EINT */
+#define WM8915_DCS_DONE_01_EINT_WIDTH                1  /* DCS_DONE_01_EINT */
+#define WM8915_WSEQ_DONE_EINT                   0x0400  /* WSEQ_DONE_EINT */
+#define WM8915_WSEQ_DONE_EINT_MASK              0x0400  /* WSEQ_DONE_EINT */
+#define WM8915_WSEQ_DONE_EINT_SHIFT                 10  /* WSEQ_DONE_EINT */
+#define WM8915_WSEQ_DONE_EINT_WIDTH                  1  /* WSEQ_DONE_EINT */
+#define WM8915_FIFOS_ERR_EINT                   0x0200  /* FIFOS_ERR_EINT */
+#define WM8915_FIFOS_ERR_EINT_MASK              0x0200  /* FIFOS_ERR_EINT */
+#define WM8915_FIFOS_ERR_EINT_SHIFT                  9  /* FIFOS_ERR_EINT */
+#define WM8915_FIFOS_ERR_EINT_WIDTH                  1  /* FIFOS_ERR_EINT */
+#define WM8915_DSP2DRC_SIG_DET_EINT             0x0080  /* DSP2DRC_SIG_DET_EINT */
+#define WM8915_DSP2DRC_SIG_DET_EINT_MASK        0x0080  /* DSP2DRC_SIG_DET_EINT */
+#define WM8915_DSP2DRC_SIG_DET_EINT_SHIFT            7  /* DSP2DRC_SIG_DET_EINT */
+#define WM8915_DSP2DRC_SIG_DET_EINT_WIDTH            1  /* DSP2DRC_SIG_DET_EINT */
+#define WM8915_DSP1DRC_SIG_DET_EINT             0x0040  /* DSP1DRC_SIG_DET_EINT */
+#define WM8915_DSP1DRC_SIG_DET_EINT_MASK        0x0040  /* DSP1DRC_SIG_DET_EINT */
+#define WM8915_DSP1DRC_SIG_DET_EINT_SHIFT            6  /* DSP1DRC_SIG_DET_EINT */
+#define WM8915_DSP1DRC_SIG_DET_EINT_WIDTH            1  /* DSP1DRC_SIG_DET_EINT */
+#define WM8915_FLL_SW_CLK_DONE_EINT             0x0008  /* FLL_SW_CLK_DONE_EINT */
+#define WM8915_FLL_SW_CLK_DONE_EINT_MASK        0x0008  /* FLL_SW_CLK_DONE_EINT */
+#define WM8915_FLL_SW_CLK_DONE_EINT_SHIFT            3  /* FLL_SW_CLK_DONE_EINT */
+#define WM8915_FLL_SW_CLK_DONE_EINT_WIDTH            1  /* FLL_SW_CLK_DONE_EINT */
+#define WM8915_FLL_LOCK_EINT                    0x0004  /* FLL_LOCK_EINT */
+#define WM8915_FLL_LOCK_EINT_MASK               0x0004  /* FLL_LOCK_EINT */
+#define WM8915_FLL_LOCK_EINT_SHIFT                   2  /* FLL_LOCK_EINT */
+#define WM8915_FLL_LOCK_EINT_WIDTH                   1  /* FLL_LOCK_EINT */
+#define WM8915_HP_DONE_EINT                     0x0002  /* HP_DONE_EINT */
+#define WM8915_HP_DONE_EINT_MASK                0x0002  /* HP_DONE_EINT */
+#define WM8915_HP_DONE_EINT_SHIFT                    1  /* HP_DONE_EINT */
+#define WM8915_HP_DONE_EINT_WIDTH                    1  /* HP_DONE_EINT */
+#define WM8915_MICD_EINT                        0x0001  /* MICD_EINT */
+#define WM8915_MICD_EINT_MASK                   0x0001  /* MICD_EINT */
+#define WM8915_MICD_EINT_SHIFT                       0  /* MICD_EINT */
+#define WM8915_MICD_EINT_WIDTH                       1  /* MICD_EINT */
+
+/*
+ * R1842 (0x732) - Interrupt Raw Status 2
+ */
+#define WM8915_DCS_DONE_23_STS                  0x1000  /* DCS_DONE_23_STS */
+#define WM8915_DCS_DONE_23_STS_MASK             0x1000  /* DCS_DONE_23_STS */
+#define WM8915_DCS_DONE_23_STS_SHIFT                12  /* DCS_DONE_23_STS */
+#define WM8915_DCS_DONE_23_STS_WIDTH                 1  /* DCS_DONE_23_STS */
+#define WM8915_DCS_DONE_01_STS                  0x0800  /* DCS_DONE_01_STS */
+#define WM8915_DCS_DONE_01_STS_MASK             0x0800  /* DCS_DONE_01_STS */
+#define WM8915_DCS_DONE_01_STS_SHIFT                11  /* DCS_DONE_01_STS */
+#define WM8915_DCS_DONE_01_STS_WIDTH                 1  /* DCS_DONE_01_STS */
+#define WM8915_WSEQ_DONE_STS                    0x0400  /* WSEQ_DONE_STS */
+#define WM8915_WSEQ_DONE_STS_MASK               0x0400  /* WSEQ_DONE_STS */
+#define WM8915_WSEQ_DONE_STS_SHIFT                  10  /* WSEQ_DONE_STS */
+#define WM8915_WSEQ_DONE_STS_WIDTH                   1  /* WSEQ_DONE_STS */
+#define WM8915_FIFOS_ERR_STS                    0x0200  /* FIFOS_ERR_STS */
+#define WM8915_FIFOS_ERR_STS_MASK               0x0200  /* FIFOS_ERR_STS */
+#define WM8915_FIFOS_ERR_STS_SHIFT                   9  /* FIFOS_ERR_STS */
+#define WM8915_FIFOS_ERR_STS_WIDTH                   1  /* FIFOS_ERR_STS */
+#define WM8915_DSP2DRC_SIG_DET_STS              0x0080  /* DSP2DRC_SIG_DET_STS */
+#define WM8915_DSP2DRC_SIG_DET_STS_MASK         0x0080  /* DSP2DRC_SIG_DET_STS */
+#define WM8915_DSP2DRC_SIG_DET_STS_SHIFT             7  /* DSP2DRC_SIG_DET_STS */
+#define WM8915_DSP2DRC_SIG_DET_STS_WIDTH             1  /* DSP2DRC_SIG_DET_STS */
+#define WM8915_DSP1DRC_SIG_DET_STS              0x0040  /* DSP1DRC_SIG_DET_STS */
+#define WM8915_DSP1DRC_SIG_DET_STS_MASK         0x0040  /* DSP1DRC_SIG_DET_STS */
+#define WM8915_DSP1DRC_SIG_DET_STS_SHIFT             6  /* DSP1DRC_SIG_DET_STS */
+#define WM8915_DSP1DRC_SIG_DET_STS_WIDTH             1  /* DSP1DRC_SIG_DET_STS */
+#define WM8915_FLL_LOCK_STS                     0x0004  /* FLL_LOCK_STS */
+#define WM8915_FLL_LOCK_STS_MASK                0x0004  /* FLL_LOCK_STS */
+#define WM8915_FLL_LOCK_STS_SHIFT                    2  /* FLL_LOCK_STS */
+#define WM8915_FLL_LOCK_STS_WIDTH                    1  /* FLL_LOCK_STS */
+
+/*
+ * R1848 (0x738) - Interrupt Status 1 Mask
+ */
+#define WM8915_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
+#define WM8915_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
+#define WM8915_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
+#define WM8915_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
+#define WM8915_IM_GP4_EINT                      0x0008  /* IM_GP4_EINT */
+#define WM8915_IM_GP4_EINT_MASK                 0x0008  /* IM_GP4_EINT */
+#define WM8915_IM_GP4_EINT_SHIFT                     3  /* IM_GP4_EINT */
+#define WM8915_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
+#define WM8915_IM_GP3_EINT                      0x0004  /* IM_GP3_EINT */
+#define WM8915_IM_GP3_EINT_MASK                 0x0004  /* IM_GP3_EINT */
+#define WM8915_IM_GP3_EINT_SHIFT                     2  /* IM_GP3_EINT */
+#define WM8915_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
+#define WM8915_IM_GP2_EINT                      0x0002  /* IM_GP2_EINT */
+#define WM8915_IM_GP2_EINT_MASK                 0x0002  /* IM_GP2_EINT */
+#define WM8915_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
+#define WM8915_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
+#define WM8915_IM_GP1_EINT                      0x0001  /* IM_GP1_EINT */
+#define WM8915_IM_GP1_EINT_MASK                 0x0001  /* IM_GP1_EINT */
+#define WM8915_IM_GP1_EINT_SHIFT                     0  /* IM_GP1_EINT */
+#define WM8915_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
+
+/*
+ * R1849 (0x739) - Interrupt Status 2 Mask
+ */
+#define WM8915_IM_DCS_DONE_23_EINT              0x1000  /* IM_DCS_DONE_23_EINT */
+#define WM8915_IM_DCS_DONE_23_EINT_MASK         0x1000  /* IM_DCS_DONE_23_EINT */
+#define WM8915_IM_DCS_DONE_23_EINT_SHIFT            12  /* IM_DCS_DONE_23_EINT */
+#define WM8915_IM_DCS_DONE_23_EINT_WIDTH             1  /* IM_DCS_DONE_23_EINT */
+#define WM8915_IM_DCS_DONE_01_EINT              0x0800  /* IM_DCS_DONE_01_EINT */
+#define WM8915_IM_DCS_DONE_01_EINT_MASK         0x0800  /* IM_DCS_DONE_01_EINT */
+#define WM8915_IM_DCS_DONE_01_EINT_SHIFT            11  /* IM_DCS_DONE_01_EINT */
+#define WM8915_IM_DCS_DONE_01_EINT_WIDTH             1  /* IM_DCS_DONE_01_EINT */
+#define WM8915_IM_WSEQ_DONE_EINT                0x0400  /* IM_WSEQ_DONE_EINT */
+#define WM8915_IM_WSEQ_DONE_EINT_MASK           0x0400  /* IM_WSEQ_DONE_EINT */
+#define WM8915_IM_WSEQ_DONE_EINT_SHIFT              10  /* IM_WSEQ_DONE_EINT */
+#define WM8915_IM_WSEQ_DONE_EINT_WIDTH               1  /* IM_WSEQ_DONE_EINT */
+#define WM8915_IM_FIFOS_ERR_EINT                0x0200  /* IM_FIFOS_ERR_EINT */
+#define WM8915_IM_FIFOS_ERR_EINT_MASK           0x0200  /* IM_FIFOS_ERR_EINT */
+#define WM8915_IM_FIFOS_ERR_EINT_SHIFT               9  /* IM_FIFOS_ERR_EINT */
+#define WM8915_IM_FIFOS_ERR_EINT_WIDTH               1  /* IM_FIFOS_ERR_EINT */
+#define WM8915_IM_DSP2DRC_SIG_DET_EINT          0x0080  /* IM_DSP2DRC_SIG_DET_EINT */
+#define WM8915_IM_DSP2DRC_SIG_DET_EINT_MASK     0x0080  /* IM_DSP2DRC_SIG_DET_EINT */
+#define WM8915_IM_DSP2DRC_SIG_DET_EINT_SHIFT         7  /* IM_DSP2DRC_SIG_DET_EINT */
+#define WM8915_IM_DSP2DRC_SIG_DET_EINT_WIDTH         1  /* IM_DSP2DRC_SIG_DET_EINT */
+#define WM8915_IM_DSP1DRC_SIG_DET_EINT          0x0040  /* IM_DSP1DRC_SIG_DET_EINT */
+#define WM8915_IM_DSP1DRC_SIG_DET_EINT_MASK     0x0040  /* IM_DSP1DRC_SIG_DET_EINT */
+#define WM8915_IM_DSP1DRC_SIG_DET_EINT_SHIFT         6  /* IM_DSP1DRC_SIG_DET_EINT */
+#define WM8915_IM_DSP1DRC_SIG_DET_EINT_WIDTH         1  /* IM_DSP1DRC_SIG_DET_EINT */
+#define WM8915_IM_FLL_SW_CLK_DONE_EINT          0x0008  /* IM_FLL_SW_CLK_DONE_EINT */
+#define WM8915_IM_FLL_SW_CLK_DONE_EINT_MASK     0x0008  /* IM_FLL_SW_CLK_DONE_EINT */
+#define WM8915_IM_FLL_SW_CLK_DONE_EINT_SHIFT         3  /* IM_FLL_SW_CLK_DONE_EINT */
+#define WM8915_IM_FLL_SW_CLK_DONE_EINT_WIDTH         1  /* IM_FLL_SW_CLK_DONE_EINT */
+#define WM8915_IM_FLL_LOCK_EINT                 0x0004  /* IM_FLL_LOCK_EINT */
+#define WM8915_IM_FLL_LOCK_EINT_MASK            0x0004  /* IM_FLL_LOCK_EINT */
+#define WM8915_IM_FLL_LOCK_EINT_SHIFT                2  /* IM_FLL_LOCK_EINT */
+#define WM8915_IM_FLL_LOCK_EINT_WIDTH                1  /* IM_FLL_LOCK_EINT */
+#define WM8915_IM_HP_DONE_EINT                  0x0002  /* IM_HP_DONE_EINT */
+#define WM8915_IM_HP_DONE_EINT_MASK             0x0002  /* IM_HP_DONE_EINT */
+#define WM8915_IM_HP_DONE_EINT_SHIFT                 1  /* IM_HP_DONE_EINT */
+#define WM8915_IM_HP_DONE_EINT_WIDTH                 1  /* IM_HP_DONE_EINT */
+#define WM8915_IM_MICD_EINT                     0x0001  /* IM_MICD_EINT */
+#define WM8915_IM_MICD_EINT_MASK                0x0001  /* IM_MICD_EINT */
+#define WM8915_IM_MICD_EINT_SHIFT                    0  /* IM_MICD_EINT */
+#define WM8915_IM_MICD_EINT_WIDTH                    1  /* IM_MICD_EINT */
+
+/*
+ * R1856 (0x740) - Interrupt Control
+ */
+#define WM8915_IM_IRQ                           0x0001  /* IM_IRQ */
+#define WM8915_IM_IRQ_MASK                      0x0001  /* IM_IRQ */
+#define WM8915_IM_IRQ_SHIFT                          0  /* IM_IRQ */
+#define WM8915_IM_IRQ_WIDTH                          1  /* IM_IRQ */
+
+/*
+ * R2048 (0x800) - Left PDM Speaker
+ */
+#define WM8915_SPKL_ENA                         0x0010  /* SPKL_ENA */
+#define WM8915_SPKL_ENA_MASK                    0x0010  /* SPKL_ENA */
+#define WM8915_SPKL_ENA_SHIFT                        4  /* SPKL_ENA */
+#define WM8915_SPKL_ENA_WIDTH                        1  /* SPKL_ENA */
+#define WM8915_SPKL_MUTE                        0x0008  /* SPKL_MUTE */
+#define WM8915_SPKL_MUTE_MASK                   0x0008  /* SPKL_MUTE */
+#define WM8915_SPKL_MUTE_SHIFT                       3  /* SPKL_MUTE */
+#define WM8915_SPKL_MUTE_WIDTH                       1  /* SPKL_MUTE */
+#define WM8915_SPKL_MUTE_ZC                     0x0004  /* SPKL_MUTE_ZC */
+#define WM8915_SPKL_MUTE_ZC_MASK                0x0004  /* SPKL_MUTE_ZC */
+#define WM8915_SPKL_MUTE_ZC_SHIFT                    2  /* SPKL_MUTE_ZC */
+#define WM8915_SPKL_MUTE_ZC_WIDTH                    1  /* SPKL_MUTE_ZC */
+#define WM8915_SPKL_SRC_MASK                    0x0003  /* SPKL_SRC - [1:0] */
+#define WM8915_SPKL_SRC_SHIFT                        0  /* SPKL_SRC - [1:0] */
+#define WM8915_SPKL_SRC_WIDTH                        2  /* SPKL_SRC - [1:0] */
+
+/*
+ * R2049 (0x801) - Right PDM Speaker
+ */
+#define WM8915_SPKR_ENA                         0x0010  /* SPKR_ENA */
+#define WM8915_SPKR_ENA_MASK                    0x0010  /* SPKR_ENA */
+#define WM8915_SPKR_ENA_SHIFT                        4  /* SPKR_ENA */
+#define WM8915_SPKR_ENA_WIDTH                        1  /* SPKR_ENA */
+#define WM8915_SPKR_MUTE                        0x0008  /* SPKR_MUTE */
+#define WM8915_SPKR_MUTE_MASK                   0x0008  /* SPKR_MUTE */
+#define WM8915_SPKR_MUTE_SHIFT                       3  /* SPKR_MUTE */
+#define WM8915_SPKR_MUTE_WIDTH                       1  /* SPKR_MUTE */
+#define WM8915_SPKR_MUTE_ZC                     0x0004  /* SPKR_MUTE_ZC */
+#define WM8915_SPKR_MUTE_ZC_MASK                0x0004  /* SPKR_MUTE_ZC */
+#define WM8915_SPKR_MUTE_ZC_SHIFT                    2  /* SPKR_MUTE_ZC */
+#define WM8915_SPKR_MUTE_ZC_WIDTH                    1  /* SPKR_MUTE_ZC */
+#define WM8915_SPKR_SRC_MASK                    0x0003  /* SPKR_SRC - [1:0] */
+#define WM8915_SPKR_SRC_SHIFT                        0  /* SPKR_SRC - [1:0] */
+#define WM8915_SPKR_SRC_WIDTH                        2  /* SPKR_SRC - [1:0] */
+
+/*
+ * R2050 (0x802) - PDM Speaker Mute Sequence
+ */
+#define WM8915_SPK_MUTE_ENDIAN                  0x0100  /* SPK_MUTE_ENDIAN */
+#define WM8915_SPK_MUTE_ENDIAN_MASK             0x0100  /* SPK_MUTE_ENDIAN */
+#define WM8915_SPK_MUTE_ENDIAN_SHIFT                 8  /* SPK_MUTE_ENDIAN */
+#define WM8915_SPK_MUTE_ENDIAN_WIDTH                 1  /* SPK_MUTE_ENDIAN */
+#define WM8915_SPK_MUTE_SEQ1_MASK               0x00FF  /* SPK_MUTE_SEQ1 - [7:0] */
+#define WM8915_SPK_MUTE_SEQ1_SHIFT                   0  /* SPK_MUTE_SEQ1 - [7:0] */
+#define WM8915_SPK_MUTE_SEQ1_WIDTH                   8  /* SPK_MUTE_SEQ1 - [7:0] */
+
+/*
+ * R2051 (0x803) - PDM Speaker Volume
+ */
+#define WM8915_SPKR_VOL_MASK                    0x00F0  /* SPKR_VOL - [7:4] */
+#define WM8915_SPKR_VOL_SHIFT                        4  /* SPKR_VOL - [7:4] */
+#define WM8915_SPKR_VOL_WIDTH                        4  /* SPKR_VOL - [7:4] */
+#define WM8915_SPKL_VOL_MASK                    0x000F  /* SPKL_VOL - [3:0] */
+#define WM8915_SPKL_VOL_SHIFT                        0  /* SPKL_VOL - [3:0] */
+#define WM8915_SPKL_VOL_WIDTH                        4  /* SPKL_VOL - [3:0] */
+
+#endif
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index f0c11138e610..25580e3ee7c4 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -35,7 +35,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
@@ -43,8 +42,8 @@
 
 struct wm8940_priv {
         unsigned int sysclk;
-        u16 reg_cache[WM8940_CACHEREGNUM];
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
+        void *control_data;
 };
 
 static u16 wm8940_reg_defaults[] = {
@@ -290,13 +289,14 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8940_add_widgets(struct snd_soc_codec *codec)
 {
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
         int ret;
 
-        ret = snd_soc_dapm_new_controls(codec, wm8940_dapm_widgets,
+        ret = snd_soc_dapm_new_controls(dapm, wm8940_dapm_widgets,
                                         ARRAY_SIZE(wm8940_dapm_widgets));
         if (ret)
                 goto error_ret;
-        ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
         if (ret)
                 goto error_ret;
 
@@ -365,8 +365,7 @@ static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
                                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFD9F;
         u16 addcntrl = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFF1;
         u16 companding =  snd_soc_read(codec,
@@ -636,8 +635,8 @@ static struct snd_soc_dai_ops wm8940_dai_ops = {
         .set_pll = wm8940_set_dai_pll,
 };
 
-struct snd_soc_dai wm8940_dai = {
-        .name = "WM8940",
+static struct snd_soc_dai_driver wm8940_dai = {
+        .name = "wm8940-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -655,20 +654,14 @@ struct snd_soc_dai wm8940_dai = {
         .ops = &wm8940_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8940_dai);
 
-static int wm8940_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8940_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         return wm8940_set_bias_level(codec, SND_SOC_BIAS_OFF);
 }
 
-static int wm8940_resume(struct platform_device *pdev)
+static int wm8940_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         int ret;
         u8 data[3];
@@ -697,108 +690,26 @@ error_ret:
         return ret;
 }
 
-static struct snd_soc_codec *wm8940_codec;
-
-static int wm8940_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-
-        int ret = 0;
-
-        if (wm8940_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8940_codec;
-        codec = wm8940_codec;
-
-        mutex_init(&codec->mutex);
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        ret = snd_soc_add_controls(codec, wm8940_snd_controls,
-                             ARRAY_SIZE(wm8940_snd_controls));
-        if (ret)
-                goto error_free_pcms;
-        ret = wm8940_add_widgets(codec);
-        if (ret)
-                goto error_free_pcms;
-
-        return ret;
-
-error_free_pcms:
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-pcm_err:
-        return ret;
-}
-
-static int wm8940_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8940 = {
-        .probe = wm8940_probe,
-        .remove = wm8940_remove,
-        .suspend = wm8940_suspend,
-        .resume = wm8940_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8940);
-
-static int wm8940_register(struct wm8940_priv *wm8940,
-                           enum snd_soc_control_type control)
+static int wm8940_probe(struct snd_soc_codec *codec)
 {
-        struct wm8940_setup_data *pdata = wm8940->codec.dev->platform_data;
-        struct snd_soc_codec *codec = &wm8940->codec;
+        struct wm8940_priv *wm8940 = snd_soc_codec_get_drvdata(codec);
+        struct wm8940_setup_data *pdata = codec->dev->platform_data;
         int ret;
         u16 reg;
-        if (wm8940_codec) {
-                dev_err(codec->dev, "Another WM8940 is registered\n");
-                return -EINVAL;
-        }
-
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8940);
-        codec->name = "WM8940";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8940_set_bias_level;
-        codec->dai = &wm8940_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(wm8940_reg_defaults);
-        codec->reg_cache = &wm8940->reg_cache;
 
-        ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
+        codec->control_data = wm8940->control_data;
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8940->control_type);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
                 return ret;
         }
 
-        memcpy(codec->reg_cache, wm8940_reg_defaults,
-               sizeof(wm8940_reg_defaults));
-
         ret = wm8940_reset(codec);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to issue reset\n");
                 return ret;
         }
 
-        wm8940_dai.dev = codec->dev;
-
         wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         ret = snd_soc_write(codec, WM8940_POWER1, 0x180);
@@ -814,64 +725,60 @@ static int wm8940_register(struct wm8940_priv *wm8940,
                         return ret;
         }
 
-
-        wm8940_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
+        ret = snd_soc_add_controls(codec, wm8940_snd_controls,
+                             ARRAY_SIZE(wm8940_snd_controls));
+        if (ret)
                 return ret;
-        }
-
-        ret = snd_soc_register_dai(&wm8940_dai);
-        if (ret) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                snd_soc_unregister_codec(codec);
+        ret = wm8940_add_widgets(codec);
+        if (ret)
                 return ret;
-        }
 
-        return 0;
+        return ret;
 }
 
-static void wm8940_unregister(struct wm8940_priv *wm8940)
+static int wm8940_remove(struct snd_soc_codec *codec)
 {
-        wm8940_set_bias_level(&wm8940->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm8940_dai);
-        snd_soc_unregister_codec(&wm8940->codec);
-        kfree(wm8940);
-        wm8940_codec = NULL;
+        wm8940_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
-static int wm8940_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+static struct snd_soc_codec_driver soc_codec_dev_wm8940 = {
+        .probe =        wm8940_probe,
+        .remove =       wm8940_remove,
+        .suspend =      wm8940_suspend,
+        .resume =       wm8940_resume,
+        .set_bias_level = wm8940_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8940_reg_defaults),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8940_reg_defaults,
+};
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8940_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
-        int ret;
         struct wm8940_priv *wm8940;
-        struct snd_soc_codec *codec;
+        int ret;
 
-        wm8940 = kzalloc(sizeof *wm8940, GFP_KERNEL);
+        wm8940 = kzalloc(sizeof(struct wm8940_priv), GFP_KERNEL);
         if (wm8940 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8940->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
         i2c_set_clientdata(i2c, wm8940);
-        codec->control_data = i2c;
-        codec->dev = &i2c->dev;
+        wm8940->control_data = i2c;
+        wm8940->control_type = SND_SOC_I2C;
 
-        ret = wm8940_register(wm8940, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8940, &wm8940_dai, 1);
         if (ret < 0)
                 kfree(wm8940);
-
         return ret;
 }
 
-static int __devexit wm8940_i2c_remove(struct i2c_client *client)
+static __devexit int wm8940_i2c_remove(struct i2c_client *client)
 {
-        struct wm8940_priv *wm8940 = i2c_get_clientdata(client);
-
-        wm8940_unregister(wm8940);
-
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -883,29 +790,34 @@ MODULE_DEVICE_TABLE(i2c, wm8940_i2c_id);
 
 static struct i2c_driver wm8940_i2c_driver = {
         .driver = {
-                .name = "WM8940 I2C Codec",
+                .name = "wm8940-codec",
                 .owner = THIS_MODULE,
         },
-        .probe = wm8940_i2c_probe,
-        .remove = __devexit_p(wm8940_i2c_remove),
+        .probe =    wm8940_i2c_probe,
+        .remove =   __devexit_p(wm8940_i2c_remove),
         .id_table = wm8940_i2c_id,
 };
+#endif
 
 static int __init wm8940_modinit(void)
 {
-        int ret;
-
+        int ret = 0;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8940_i2c_driver);
-        if (ret)
-                printk(KERN_ERR "Failed to register WM8940 I2C driver: %d\n",
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8940 I2C driver: %d\n",
                        ret);
+        }
+#endif
         return ret;
 }
 module_init(wm8940_modinit);
 
 static void __exit wm8940_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm8940_i2c_driver);
+#endif
 }
 module_exit(wm8940_exit);
 
diff --git a/sound/soc/codecs/wm8940.h b/sound/soc/codecs/wm8940.h
index 8410eed3ef84..907fe192e9e0 100644
--- a/sound/soc/codecs/wm8940.h
+++ b/sound/soc/codecs/wm8940.h
@@ -15,8 +15,6 @@ struct wm8940_setup_data {
 #define WM8940_VROI_30K 1
         unsigned int vroi:1;
 };
-extern struct snd_soc_dai wm8940_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8940;
 
 /* WM8940 register space */
 #define WM8940_SOFTRESET        0x00
diff --git a/sound/soc/codecs/wm8955.c b/sound/soc/codecs/wm8955.c
index 5f025593d84d..3c7198779c31 100644
--- a/sound/soc/codecs/wm8955.c
+++ b/sound/soc/codecs/wm8955.c
@@ -23,16 +23,12 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 #include <sound/wm8955.h>
 
 #include "wm8955.h"
 
-static struct snd_soc_codec *wm8955_codec;
-struct snd_soc_codec_device soc_codec_dev_wm8955;
-
 #define WM8955_NUM_SUPPLIES 4
 static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
         "DCVDD",
@@ -43,8 +39,7 @@ static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
 
 /* codec private data */
 struct wm8955_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM8955_MAX_REGISTER + 1];
+        enum snd_soc_control_type control_type;
 
         unsigned int mclk_rate;
 
@@ -52,8 +47,6 @@ struct wm8955_priv {
         int fs;
 
         struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
-
-        struct wm8955_pdata *pdata;
 };
 
 static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
@@ -183,7 +176,7 @@ static int wm8995_pll_factors(struct device *dev,
         return 0;
 }
 
-/* Lookup table specifiying SRATE (table 25 in datasheet); some of the
+/* Lookup table specifying SRATE (table 25 in datasheet); some of the
  * output frequencies have been rounded to the standard frequencies
  * they are intended to match where the error is slight. */
 static struct {
@@ -384,7 +377,8 @@ static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
         struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
 
-        return wm8955->deemph;
+        ucontrol->value.enumerated.item[0] = wm8955->deemph;
+        return 0;
 }
 
 static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
@@ -581,13 +575,14 @@ static const struct snd_soc_dapm_route wm8955_intercon[] = {
 
 static int wm8955_add_widgets(struct snd_soc_codec *codec)
 {
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
         snd_soc_add_controls(codec, wm8955_snd_controls,
                              ARRAY_SIZE(wm8955_snd_controls));
 
-        snd_soc_dapm_new_controls(codec, wm8955_dapm_widgets,
+        snd_soc_dapm_new_controls(dapm, wm8955_dapm_widgets,
                                   ARRAY_SIZE(wm8955_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, wm8955_intercon,
+        snd_soc_dapm_add_routes(dapm, wm8955_intercon,
                                 ARRAY_SIZE(wm8955_intercon));
 
         return 0;
@@ -771,6 +766,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
                                  enum snd_soc_bias_level level)
 {
         struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
+        u16 *reg_cache = codec->reg_cache;
         int ret, i;
 
         switch (level) {
@@ -790,7 +786,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
                                                     wm8955->supplies);
                         if (ret != 0) {
@@ -803,14 +799,14 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
                         /* Sync back cached values if they're
                          * different from the hardware default.
                          */
-                        for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) {
+                        for (i = 0; i < codec->driver->reg_cache_size; i++) {
                                 if (i == WM8955_RESET)
                                         continue;
 
-                                if (wm8955->reg_cache[i] == wm8955_reg[i])
+                                if (reg_cache[i] == wm8955_reg[i])
                                         continue;
 
-                                snd_soc_write(codec, i, wm8955->reg_cache[i]);
+                                snd_soc_write(codec, i, reg_cache[i]);
                         }
 
                         /* Enable VREF and VMID */
@@ -854,7 +850,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
                                        wm8955->supplies);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -870,8 +866,8 @@ static struct snd_soc_dai_ops wm8955_dai_ops = {
         .digital_mute = wm8955_digital_mute,
 };
 
-struct snd_soc_dai wm8955_dai = {
-        .name = "WM8955",
+static struct snd_soc_dai_driver wm8955_dai = {
+        .name = "wm8955-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
@@ -881,24 +877,17 @@ struct snd_soc_dai wm8955_dai = {
         },
         .ops = &wm8955_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8955_dai);
 
 #ifdef CONFIG_PM
-static int wm8955_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8955_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm8955_resume(struct platform_device *pdev)
+static int wm8955_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
@@ -908,86 +897,17 @@ static int wm8955_resume(struct platform_device *pdev)
 #define wm8955_resume NULL
 #endif
 
-static int wm8955_probe(struct platform_device *pdev)
+static int wm8955_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8955_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8955_codec;
-        codec = wm8955_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        wm8955_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-static int wm8955_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8955 = {
-        .probe =        wm8955_probe,
-        .remove =       wm8955_remove,
-        .suspend =      wm8955_suspend,
-        .resume =       wm8955_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8955);
-
-static int wm8955_register(struct wm8955_priv *wm8955,
-                           enum snd_soc_control_type control)
-{
-        int ret;
-        struct snd_soc_codec *codec = &wm8955->codec;
-        int i;
-
-        if (wm8955_codec) {
-                dev_err(codec->dev, "Another WM8955 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8955);
-        codec->name = "WM8955";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8955_set_bias_level;
-        codec->dai = &wm8955_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8955_MAX_REGISTER;
-        codec->reg_cache = &wm8955->reg_cache;
-
-        memcpy(codec->reg_cache, wm8955_reg, sizeof(wm8955_reg));
+        struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
+        struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
+        u16 *reg_cache = codec->reg_cache;
+        int ret, i;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
@@ -997,7 +917,7 @@ static int wm8955_register(struct wm8955_priv *wm8955,
                                  wm8955->supplies);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
@@ -1013,28 +933,37 @@ static int wm8955_register(struct wm8955_priv *wm8955,
                 goto err_enable;
         }
 
-        wm8955_dai.dev = codec->dev;
-
         /* Change some default settings - latch VU and enable ZC */
-        wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
-        wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
-        wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
-        wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
-        wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
-        wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
-        wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
+        snd_soc_update_bits(codec, WM8955_LEFT_DAC_VOLUME,
+                            WM8955_LDVU, WM8955_LDVU);
+        snd_soc_update_bits(codec, WM8955_RIGHT_DAC_VOLUME,
+                            WM8955_RDVU, WM8955_RDVU);
+        snd_soc_update_bits(codec, WM8955_LOUT1_VOLUME,
+                            WM8955_LO1VU | WM8955_LO1ZC,
+                            WM8955_LO1VU | WM8955_LO1ZC);
+        snd_soc_update_bits(codec, WM8955_ROUT1_VOLUME,
+                            WM8955_RO1VU | WM8955_RO1ZC,
+                            WM8955_RO1VU | WM8955_RO1ZC);
+        snd_soc_update_bits(codec, WM8955_LOUT2_VOLUME,
+                            WM8955_LO2VU | WM8955_LO2ZC,
+                            WM8955_LO2VU | WM8955_LO2ZC);
+        snd_soc_update_bits(codec, WM8955_ROUT2_VOLUME,
+                            WM8955_RO2VU | WM8955_RO2ZC,
+                            WM8955_RO2VU | WM8955_RO2ZC);
+        snd_soc_update_bits(codec, WM8955_MONOOUT_VOLUME,
+                            WM8955_MOZC, WM8955_MOZC);
 
         /* Also enable adaptive bass boost by default */
-        wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
+        snd_soc_update_bits(codec, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
 
         /* Set platform data values */
-        if (wm8955->pdata) {
-                if (wm8955->pdata->out2_speaker)
-                        wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2]
+        if (pdata) {
+                if (pdata->out2_speaker)
+                        reg_cache[WM8955_ADDITIONAL_CONTROL_2]
                                 |= WM8955_ROUT2INV;
 
-                if (wm8955->pdata->monoin_diff)
-                        wm8955->reg_cache[WM8955_MONO_OUT_MIX_1]
+                if (pdata->monoin_diff)
+                        reg_cache[WM8955_MONO_OUT_MIX_1]
                                 |= WM8955_DMEN;
         }
 
@@ -1043,70 +972,61 @@ static int wm8955_register(struct wm8955_priv *wm8955,
         /* Bias level configuration will have done an extra enable */
         regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
 
-        wm8955_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err_enable;
-        }
-
-        ret = snd_soc_register_dai(&wm8955_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
-
+        wm8955_add_widgets(codec);
         return 0;
 
-err_codec:
-        snd_soc_unregister_codec(codec);
 err_enable:
         regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
 err_get:
         regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
-err:
-        kfree(wm8955);
         return ret;
 }
 
-static void wm8955_unregister(struct wm8955_priv *wm8955)
+static int wm8955_remove(struct snd_soc_codec *codec)
 {
-        wm8955_set_bias_level(&wm8955->codec, SND_SOC_BIAS_OFF);
+        struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
+
+        wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
         regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
-        snd_soc_unregister_dai(&wm8955_dai);
-        snd_soc_unregister_codec(&wm8955->codec);
-        kfree(wm8955);
-        wm8955_codec = NULL;
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
+        .probe =        wm8955_probe,
+        .remove =       wm8955_remove,
+        .suspend =      wm8955_suspend,
+        .resume =       wm8955_resume,
+        .set_bias_level = wm8955_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8955_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8955_reg,
+};
+
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm8955_priv *wm8955;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL);
         if (wm8955 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8955->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
         i2c_set_clientdata(i2c, wm8955);
-        codec->control_data = i2c;
-        wm8955->pdata = i2c->dev.platform_data;
-
-        codec->dev = &i2c->dev;
+        wm8955->control_type = SND_SOC_I2C;
 
-        return wm8955_register(wm8955, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8955, &wm8955_dai, 1);
+        if (ret < 0)
+                kfree(wm8955);
+        return ret;
 }
 
 static __devexit int wm8955_i2c_remove(struct i2c_client *client)
 {
-        struct wm8955_priv *wm8955 = i2c_get_clientdata(client);
-        wm8955_unregister(wm8955);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -1118,7 +1038,7 @@ MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
 
 static struct i2c_driver wm8955_i2c_driver = {
         .driver = {
-                .name = "wm8955",
+                .name = "wm8955-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8955_i2c_probe,
@@ -1129,7 +1049,7 @@ static struct i2c_driver wm8955_i2c_driver = {
 
 static int __init wm8955_modinit(void)
 {
-        int ret;
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8955_i2c_driver);
         if (ret != 0) {
@@ -1137,7 +1057,7 @@ static int __init wm8955_modinit(void)
                        ret);
         }
 #endif
-        return 0;
+        return ret;
 }
 module_init(wm8955_modinit);
 
diff --git a/sound/soc/codecs/wm8955.h b/sound/soc/codecs/wm8955.h
index ae349c8531f6..d13fd5c5fa63 100644
--- a/sound/soc/codecs/wm8955.h
+++ b/sound/soc/codecs/wm8955.h
@@ -15,9 +15,6 @@
 
 #define WM8955_CLK_MCLK 1
 
-extern struct snd_soc_dai wm8955_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8955;
-
 /*
  * Register values.
  */
diff --git a/sound/soc/codecs/wm8958-dsp2.c b/sound/soc/codecs/wm8958-dsp2.c
new file mode 100644
index 000000000000..0293763debe5
--- /dev/null
+++ b/sound/soc/codecs/wm8958-dsp2.c
@@ -0,0 +1,1051 @@
+/*
+ * wm8958-dsp2.c  --  WM8958 DSP2 support
+ *
+ * Copyright 2011 Wolfson Microelectronics plc
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <trace/events/asoc.h>
+
+#include <linux/mfd/wm8994/core.h>
+#include <linux/mfd/wm8994/registers.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/wm8994/gpio.h>
+
+#include "wm8994.h"
+
+#define WM_FW_BLOCK_INFO 0xff
+#define WM_FW_BLOCK_PM   0x00
+#define WM_FW_BLOCK_X    0x01
+#define WM_FW_BLOCK_Y    0x02
+#define WM_FW_BLOCK_Z    0x03
+#define WM_FW_BLOCK_I    0x06
+#define WM_FW_BLOCK_A    0x08
+#define WM_FW_BLOCK_C    0x0c
+
+static int wm8958_dsp2_fw(struct snd_soc_codec *codec, const char *name,
+                          const struct firmware *fw, bool check)
+{
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        u64 data64;
+        u32 data32;
+        const u8 *data;
+        char *str;
+        size_t block_len, len;
+        int ret = 0;
+
+        /* Suppress unneeded downloads */
+        if (wm8994->cur_fw == fw)
+                return 0;
+
+        if (fw->size < 32) {
+                dev_err(codec->dev, "%s: firmware too short\n", name);
+                goto err;
+        }
+
+        if (memcmp(fw->data, "WMFW", 4) != 0) {
+                dev_err(codec->dev, "%s: firmware has bad file magic %08x\n",
+                        name, data32);
+                goto err;
+        }
+
+        memcpy(&data32, fw->data + 4, sizeof(data32));
+        len = be32_to_cpu(data32);
+
+        memcpy(&data32, fw->data + 8, sizeof(data32));
+        data32 = be32_to_cpu(data32);
+        if ((data32 >> 24) & 0xff) {
+                dev_err(codec->dev, "%s: unsupported firmware version %d\n",
+                        name, (data32 >> 24) & 0xff);
+                goto err;
+        }
+        if ((data32 & 0xffff) != 8958) {
+                dev_err(codec->dev, "%s: unsupported target device %d\n",
+                        name, data32 & 0xffff);
+                goto err;
+        }
+        if (((data32 >> 16) & 0xff) != 0xc) {
+                dev_err(codec->dev, "%s: unsupported target core %d\n",
+                        name, (data32 >> 16) & 0xff);
+                goto err;
+        }
+
+        if (check) {
+                memcpy(&data64, fw->data + 24, sizeof(u64));
+                dev_info(codec->dev, "%s timestamp %llx\n",
+                         name, be64_to_cpu(data64));
+        } else {
+                snd_soc_write(codec, 0x102, 0x2);
+                snd_soc_write(codec, 0x900, 0x2);
+        }
+
+        data = fw->data + len;
+        len = fw->size - len;
+        while (len) {
+                if (len < 12) {
+                        dev_err(codec->dev, "%s short data block of %zd\n",
+                                name, len);
+                        goto err;
+                }
+
+                memcpy(&data32, data + 4, sizeof(data32));
+                block_len = be32_to_cpu(data32);
+                if (block_len + 8 > len) {
+                        dev_err(codec->dev, "%zd byte block longer than file\n",
+                                block_len);
+                        goto err;
+                }
+                if (block_len == 0) {
+                        dev_err(codec->dev, "Zero length block\n");
+                        goto err;
+                }
+
+                memcpy(&data32, data, sizeof(data32));
+                data32 = be32_to_cpu(data32);
+
+                switch ((data32 >> 24) & 0xff) {
+                case WM_FW_BLOCK_INFO:
+                        /* Informational text */
+                        if (!check)
+                                break;
+
+                        str = kzalloc(block_len + 1, GFP_KERNEL);
+                        if (str) {
+                                memcpy(str, data + 8, block_len);
+                                dev_info(codec->dev, "%s: %s\n", name, str);
+                                kfree(str);
+                        } else {
+                                dev_err(codec->dev, "Out of memory\n");
+                        }
+                        break;
+                case WM_FW_BLOCK_PM:
+                case WM_FW_BLOCK_X:
+                case WM_FW_BLOCK_Y:
+                case WM_FW_BLOCK_Z:
+                case WM_FW_BLOCK_I:
+                case WM_FW_BLOCK_A:
+                case WM_FW_BLOCK_C:
+                        dev_dbg(codec->dev, "%s: %zd bytes of %x@%x\n", name,
+                                block_len, (data32 >> 24) & 0xff,
+                                data32 & 0xffffff);
+
+                        if (check)
+                                break;
+
+                        data32 &= 0xffffff;
+
+                        wm8994_bulk_write(codec->control_data,
+                                          data32 & 0xffffff,
+                                          block_len / 2,
+                                          (void *)(data + 8));
+
+                        break;
+                default:
+                        dev_warn(codec->dev, "%s: unknown block type %d\n",
+                                 name, (data32 >> 24) & 0xff);
+                        break;
+                }
+
+                /* Round up to the next 32 bit word */
+                block_len += block_len % 4;
+
+                data += block_len + 8;
+                len -= block_len + 8;
+        }
+
+        if (!check) {
+                dev_dbg(codec->dev, "%s: download done\n", name);
+                wm8994->cur_fw = fw;
+        } else {
+                dev_info(codec->dev, "%s: got firmware\n", name);
+        }
+
+        goto ok;
+
+err:
+        ret = -EINVAL;
+ok:
+        if (!check) {
+                snd_soc_write(codec, 0x900, 0x0);
+                snd_soc_write(codec, 0x102, 0x0);
+        }
+
+        return ret;
+}
+
+static void wm8958_dsp_start_mbc(struct snd_soc_codec *codec, int path)
+{
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994_pdata *pdata = wm8994->pdata;
+        int i;
+
+        /* If the DSP is already running then noop */
+        if (snd_soc_read(codec, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
+                return;
+
+        /* If we have MBC firmware download it */
+        if (wm8994->mbc)
+                wm8958_dsp2_fw(codec, "MBC", wm8994->mbc, false);
+
+        snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
+                            WM8958_DSP2_ENA, WM8958_DSP2_ENA);
+
+        /* If we've got user supplied MBC settings use them */
+        if (pdata && pdata->num_mbc_cfgs) {
+                struct wm8958_mbc_cfg *cfg
+                        = &pdata->mbc_cfgs[wm8994->mbc_cfg];
+
+                for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
+                        snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
+                                      cfg->coeff_regs[i]);
+
+                for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
+                        snd_soc_write(codec,
+                                      i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
+                                      cfg->cutoff_regs[i]);
+        }
+
+        /* Run the DSP */
+        snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
+                      WM8958_DSP2_RUNR);
+
+        /* And we're off! */
+        snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
+                            WM8958_MBC_ENA |
+                            WM8958_MBC_SEL_MASK,
+                            path << WM8958_MBC_SEL_SHIFT |
+                            WM8958_MBC_ENA);
+}
+
+static void wm8958_dsp_start_vss(struct snd_soc_codec *codec, int path)
+{
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994_pdata *pdata = wm8994->pdata;
+        int i, ena;
+
+        if (wm8994->mbc_vss)
+                wm8958_dsp2_fw(codec, "MBC+VSS", wm8994->mbc_vss, false);
+
+        snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
+                            WM8958_DSP2_ENA, WM8958_DSP2_ENA);
+
+        /* If we've got user supplied settings use them */
+        if (pdata && pdata->num_mbc_cfgs) {
+                struct wm8958_mbc_cfg *cfg
+                        = &pdata->mbc_cfgs[wm8994->mbc_cfg];
+
+                for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
+                        snd_soc_write(codec, i + 0x2800,
+                                      cfg->combined_regs[i]);
+        }
+
+        if (pdata && pdata->num_vss_cfgs) {
+                struct wm8958_vss_cfg *cfg
+                        = &pdata->vss_cfgs[wm8994->vss_cfg];
+
+                for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
+                        snd_soc_write(codec, i + 0x2600, cfg->regs[i]);
+        }
+
+        if (pdata && pdata->num_vss_hpf_cfgs) {
+                struct wm8958_vss_hpf_cfg *cfg
+                        = &pdata->vss_hpf_cfgs[wm8994->vss_hpf_cfg];
+
+                for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
+                        snd_soc_write(codec, i + 0x2400, cfg->regs[i]);
+        }
+
+        /* Run the DSP */
+        snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
+                      WM8958_DSP2_RUNR);
+
+        /* Enable the algorithms we've selected */
+        ena = 0;
+        if (wm8994->mbc_ena[path])
+                ena |= 0x8;
+        if (wm8994->hpf2_ena[path])
+                ena |= 0x4;
+        if (wm8994->hpf1_ena[path])
+                ena |= 0x2;
+        if (wm8994->vss_ena[path])
+                ena |= 0x1;
+
+        snd_soc_write(codec, 0x2201, ena);
+
+        /* Switch the DSP into the data path */
+        snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
+                            WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
+                            path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
+}
+
+static void wm8958_dsp_start_enh_eq(struct snd_soc_codec *codec, int path)
+{
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994_pdata *pdata = wm8994->pdata;
+        int i;
+
+        wm8958_dsp2_fw(codec, "ENH_EQ", wm8994->enh_eq, false);
+
+        snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
+                            WM8958_DSP2_ENA, WM8958_DSP2_ENA);
+
+        /* If we've got user supplied settings use them */
+        if (pdata && pdata->num_enh_eq_cfgs) {
+                struct wm8958_enh_eq_cfg *cfg
+                        = &pdata->enh_eq_cfgs[wm8994->enh_eq_cfg];
+
+                for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
+                        snd_soc_write(codec, i + 0x2200,
+                                      cfg->regs[i]);
+        }
+
+        /* Run the DSP */
+        snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
+                      WM8958_DSP2_RUNR);
+
+        /* Switch the DSP into the data path */
+        snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
+                            WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
+                            path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
+}
+
+static void wm8958_dsp_apply(struct snd_soc_codec *codec, int path, int start)
+{
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
+        int ena, reg, aif;
+
+        switch (path) {
+        case 0:
+                pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
+                aif = 0;
+                break;
+        case 1:
+                pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
+                aif = 0;
+                break;
+        case 2:
+                pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
+                aif = 1;
+                break;
+        default:
+                BUG();
+                return;
+        }
+
+        /* Do we have both an active AIF and an active algorithm? */
+        ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
+                wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
+                wm8994->enh_eq_ena[path];
+        if (!pwr_reg)
+                ena = 0;
+
+        reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
+
+        dev_dbg(codec->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
+                path, wm8994->dsp_active, start, pwr_reg, reg);
+
+        if (start && ena) {
+                /* If the DSP is already running then noop */
+                if (reg & WM8958_DSP2_ENA)
+                        return;
+
+                /* If either AIFnCLK is not yet enabled postpone */
+                if (!(snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
+                      & WM8994_AIF1CLK_ENA_MASK) &&
+                    !(snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
+                      & WM8994_AIF2CLK_ENA_MASK))
+                        return;
+
+                /* Switch the clock over to the appropriate AIF */
+                snd_soc_update_bits(codec, WM8994_CLOCKING_1,
+                                    WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
+                                    aif << WM8958_DSP2CLK_SRC_SHIFT |
+                                    WM8958_DSP2CLK_ENA);
+
+                if (wm8994->enh_eq_ena[path])
+                        wm8958_dsp_start_enh_eq(codec, path);
+                else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
+                    wm8994->hpf2_ena[path])
+                        wm8958_dsp_start_vss(codec, path);
+                else if (wm8994->mbc_ena[path])
+                        wm8958_dsp_start_mbc(codec, path);
+
+                wm8994->dsp_active = path;
+
+                dev_dbg(codec->dev, "DSP running in path %d\n", path);
+        }
+
+        if (!start && wm8994->dsp_active == path) {
+                /* If the DSP is already stopped then noop */
+                if (!(reg & WM8958_DSP2_ENA))
+                        return;
+
+                snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
+                                    WM8958_MBC_ENA, 0); 
+                snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
+                              WM8958_DSP2_STOP);
+                snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
+                                    WM8958_DSP2_ENA, 0);
+                snd_soc_update_bits(codec, WM8994_CLOCKING_1,
+                                    WM8958_DSP2CLK_ENA, 0);
+
+                wm8994->dsp_active = -1;
+
+                dev_dbg(codec->dev, "DSP stopped\n");
+        }
+}
+
+int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
+                  struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        int i;
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+        case SND_SOC_DAPM_PRE_PMU:
+                for (i = 0; i < 3; i++)
+                        wm8958_dsp_apply(codec, i, 1);
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+        case SND_SOC_DAPM_PRE_PMD:
+                for (i = 0; i < 3; i++)
+                        wm8958_dsp_apply(codec, i, 0);
+                break;
+        }
+
+        return 0;
+}
+
+/* Check if DSP2 is in use on another AIF */
+static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
+                if (i == aif)
+                        continue;
+                if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
+                    wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
+                        return 1;
+        }
+
+        return 0;
+}
+
+static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
+                               struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994_pdata *pdata = wm8994->pdata;
+        int value = ucontrol->value.integer.value[0];
+        int reg;
+
+        /* Don't allow on the fly reconfiguration */
+        reg = snd_soc_read(codec, WM8994_CLOCKING_1);
+        if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
+                return -EBUSY;
+
+        if (value >= pdata->num_mbc_cfgs)
+                return -EINVAL;
+
+        wm8994->mbc_cfg = value;
+
+        return 0;
+}
+
+static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
+                               struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
+
+        return 0;
+}
+
+static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
+                           struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+        uinfo->count = 1;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 1;
+        return 0;
+}
+
+static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_value *ucontrol)
+{
+        int mbc = kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
+
+        return 0;
+}
+
+static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_value *ucontrol)
+{
+        int mbc = kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
+                return 0;
+
+        if (ucontrol->value.integer.value[0] > 1)
+                return -EINVAL;
+
+        if (wm8958_dsp2_busy(wm8994, mbc)) {
+                dev_dbg(codec->dev, "DSP2 active on %d already\n", mbc);
+                return -EBUSY;
+        }
+
+        if (wm8994->enh_eq_ena[mbc])
+                return -EBUSY;
+
+        wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
+
+        wm8958_dsp_apply(codec, mbc, wm8994->mbc_ena[mbc]);
+
+        return 0;
+}
+
+#define WM8958_MBC_SWITCH(xname, xval) {\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+        .info = wm8958_mbc_info, \
+        .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
+        .private_value = xval }
+
+static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
+                               struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994_pdata *pdata = wm8994->pdata;
+        int value = ucontrol->value.integer.value[0];
+        int reg;
+
+        /* Don't allow on the fly reconfiguration */
+        reg = snd_soc_read(codec, WM8994_CLOCKING_1);
+        if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
+                return -EBUSY;
+
+        if (value >= pdata->num_vss_cfgs)
+                return -EINVAL;
+
+        wm8994->vss_cfg = value;
+
+        return 0;
+}
+
+static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
+                               struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
+
+        return 0;
+}
+
+static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
+                                   struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994_pdata *pdata = wm8994->pdata;
+        int value = ucontrol->value.integer.value[0];
+        int reg;
+
+        /* Don't allow on the fly reconfiguration */
+        reg = snd_soc_read(codec, WM8994_CLOCKING_1);
+        if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
+                return -EBUSY;
+
+        if (value >= pdata->num_vss_hpf_cfgs)
+                return -EINVAL;
+
+        wm8994->vss_hpf_cfg = value;
+
+        return 0;
+}
+
+static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
+                                   struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
+
+        return 0;
+}
+
+static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
+                           struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+        uinfo->count = 1;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 1;
+        return 0;
+}
+
+static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_value *ucontrol)
+{
+        int vss = kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
+
+        return 0;
+}
+
+static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_value *ucontrol)
+{
+        int vss = kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
+                return 0;
+
+        if (ucontrol->value.integer.value[0] > 1)
+                return -EINVAL;
+
+        if (!wm8994->mbc_vss)
+                return -ENODEV;
+
+        if (wm8958_dsp2_busy(wm8994, vss)) {
+                dev_dbg(codec->dev, "DSP2 active on %d already\n", vss);
+                return -EBUSY;
+        }
+
+        if (wm8994->enh_eq_ena[vss])
+                return -EBUSY;
+
+        wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
+
+        wm8958_dsp_apply(codec, vss, wm8994->vss_ena[vss]);
+
+        return 0;
+}
+
+
+#define WM8958_VSS_SWITCH(xname, xval) {\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+        .info = wm8958_vss_info, \
+        .get = wm8958_vss_get, .put = wm8958_vss_put, \
+        .private_value = xval }
+
+static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
+                           struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+        uinfo->count = 1;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 1;
+        return 0;
+}
+
+static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_value *ucontrol)
+{
+        int hpf = kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        if (hpf < 3)
+                ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
+        else
+                ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
+
+        return 0;
+}
+
+static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_value *ucontrol)
+{
+        int hpf = kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        if (hpf < 3) {
+                if (wm8994->hpf1_ena[hpf % 3] ==
+                    ucontrol->value.integer.value[0])
+                        return 0;
+        } else {
+                if (wm8994->hpf2_ena[hpf % 3] ==
+                    ucontrol->value.integer.value[0])
+                        return 0;
+        }
+
+        if (ucontrol->value.integer.value[0] > 1)
+                return -EINVAL;
+
+        if (!wm8994->mbc_vss)
+                return -ENODEV;
+
+        if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
+                dev_dbg(codec->dev, "DSP2 active on %d already\n", hpf);
+                return -EBUSY;
+        }
+
+        if (wm8994->enh_eq_ena[hpf % 3])
+                return -EBUSY;
+
+        if (hpf < 3)
+                wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
+        else
+                wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
+
+        wm8958_dsp_apply(codec, hpf % 3, ucontrol->value.integer.value[0]);
+
+        return 0;
+}
+
+#define WM8958_HPF_SWITCH(xname, xval) {\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+        .info = wm8958_hpf_info, \
+        .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
+        .private_value = xval }
+
+static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
+                                  struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994_pdata *pdata = wm8994->pdata;
+        int value = ucontrol->value.integer.value[0];
+        int reg;
+
+        /* Don't allow on the fly reconfiguration */
+        reg = snd_soc_read(codec, WM8994_CLOCKING_1);
+        if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
+                return -EBUSY;
+
+        if (value >= pdata->num_enh_eq_cfgs)
+                return -EINVAL;
+
+        wm8994->enh_eq_cfg = value;
+
+        return 0;
+}
+
+static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
+                                  struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
+
+        return 0;
+}
+
+static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
+                           struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+        uinfo->count = 1;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 1;
+        return 0;
+}
+
+static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_value *ucontrol)
+{
+        int eq = kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
+
+        return 0;
+}
+
+static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
+                          struct snd_ctl_elem_value *ucontrol)
+{
+        int eq = kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
+                return 0;
+
+        if (ucontrol->value.integer.value[0] > 1)
+                return -EINVAL;
+
+        if (!wm8994->enh_eq)
+                return -ENODEV;
+
+        if (wm8958_dsp2_busy(wm8994, eq)) {
+                dev_dbg(codec->dev, "DSP2 active on %d already\n", eq);
+                return -EBUSY;
+        }
+
+        if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
+            wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
+                return -EBUSY;
+
+        wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
+
+        wm8958_dsp_apply(codec, eq, ucontrol->value.integer.value[0]);
+
+        return 0;
+}
+
+#define WM8958_ENH_EQ_SWITCH(xname, xval) {\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+        .info = wm8958_enh_eq_info, \
+        .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
+        .private_value = xval }
+
+static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
+WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
+WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
+WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
+};
+
+static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
+WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
+WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
+WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
+WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
+WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
+WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
+WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
+WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
+WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
+};
+
+static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
+WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
+WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
+WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
+};
+
+static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
+{
+        struct snd_soc_codec *codec = context;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        if (fw && (wm8958_dsp2_fw(codec, "ENH_EQ", fw, true) == 0)) {
+                mutex_lock(&codec->mutex);
+                wm8994->enh_eq = fw;
+                mutex_unlock(&codec->mutex);
+        }
+}
+
+static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
+{
+        struct snd_soc_codec *codec = context;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        if (fw && (wm8958_dsp2_fw(codec, "MBC+VSS", fw, true) == 0)) {
+                mutex_lock(&codec->mutex);
+                wm8994->mbc_vss = fw;
+                mutex_unlock(&codec->mutex);
+        }
+
+        /* We can't have more than one request outstanding at once so
+         * we daisy chain.
+         */
+        request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
+                                "wm8958_enh_eq.wfw", codec->dev, GFP_KERNEL,
+                                codec, wm8958_enh_eq_loaded);
+}
+
+static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
+{
+        struct snd_soc_codec *codec = context;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        if (wm8958_dsp2_fw(codec, "MBC", fw, true) != 0)
+                return;
+
+        mutex_lock(&codec->mutex);
+        wm8994->mbc = fw;
+        mutex_unlock(&codec->mutex);
+
+        /* We can't have more than one request outstanding at once so
+         * we daisy chain.
+         */
+        request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
+                                "wm8958_mbc_vss.wfw", codec->dev, GFP_KERNEL,
+                                codec, wm8958_mbc_vss_loaded);
+}
+
+void wm8958_dsp2_init(struct snd_soc_codec *codec)
+{
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994_pdata *pdata = wm8994->pdata;
+        int ret, i;
+
+        wm8994->dsp_active = -1;
+
+        snd_soc_add_controls(codec, wm8958_mbc_snd_controls,
+                             ARRAY_SIZE(wm8958_mbc_snd_controls));
+        snd_soc_add_controls(codec, wm8958_vss_snd_controls,
+                             ARRAY_SIZE(wm8958_vss_snd_controls));
+        snd_soc_add_controls(codec, wm8958_enh_eq_snd_controls,
+                             ARRAY_SIZE(wm8958_enh_eq_snd_controls));
+
+
+        /* We don't *require* firmware and don't want to delay boot */
+        request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
+                                "wm8958_mbc.wfw", codec->dev, GFP_KERNEL,
+                                codec, wm8958_mbc_loaded);
+
+        if (!pdata)
+                return;
+
+        if (pdata->num_mbc_cfgs) {
+                struct snd_kcontrol_new control[] = {
+                        SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
+                                     wm8958_get_mbc_enum, wm8958_put_mbc_enum),
+                };
+
+                /* We need an array of texts for the enum API */
+                wm8994->mbc_texts = kmalloc(sizeof(char *)
+                                            * pdata->num_mbc_cfgs, GFP_KERNEL);
+                if (!wm8994->mbc_texts) {
+                        dev_err(wm8994->codec->dev,
+                                "Failed to allocate %d MBC config texts\n",
+                                pdata->num_mbc_cfgs);
+                        return;
+                }
+
+                for (i = 0; i < pdata->num_mbc_cfgs; i++)
+                        wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
+
+                wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
+                wm8994->mbc_enum.texts = wm8994->mbc_texts;
+
+                ret = snd_soc_add_controls(wm8994->codec, control, 1);
+                if (ret != 0)
+                        dev_err(wm8994->codec->dev,
+                                "Failed to add MBC mode controls: %d\n", ret);
+        }
+
+        if (pdata->num_vss_cfgs) {
+                struct snd_kcontrol_new control[] = {
+                        SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
+                                     wm8958_get_vss_enum, wm8958_put_vss_enum),
+                };
+
+                /* We need an array of texts for the enum API */
+                wm8994->vss_texts = kmalloc(sizeof(char *)
+                                            * pdata->num_vss_cfgs, GFP_KERNEL);
+                if (!wm8994->vss_texts) {
+                        dev_err(wm8994->codec->dev,
+                                "Failed to allocate %d VSS config texts\n",
+                                pdata->num_vss_cfgs);
+                        return;
+                }
+
+                for (i = 0; i < pdata->num_vss_cfgs; i++)
+                        wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
+
+                wm8994->vss_enum.max = pdata->num_vss_cfgs;
+                wm8994->vss_enum.texts = wm8994->vss_texts;
+
+                ret = snd_soc_add_controls(wm8994->codec, control, 1);
+                if (ret != 0)
+                        dev_err(wm8994->codec->dev,
+                                "Failed to add VSS mode controls: %d\n", ret);
+        }
+
+        if (pdata->num_vss_hpf_cfgs) {
+                struct snd_kcontrol_new control[] = {
+                        SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
+                                     wm8958_get_vss_hpf_enum,
+                                     wm8958_put_vss_hpf_enum),
+                };
+
+                /* We need an array of texts for the enum API */
+                wm8994->vss_hpf_texts = kmalloc(sizeof(char *)
+                                                * pdata->num_vss_hpf_cfgs, GFP_KERNEL);
+                if (!wm8994->vss_hpf_texts) {
+                        dev_err(wm8994->codec->dev,
+                                "Failed to allocate %d VSS HPF config texts\n",
+                                pdata->num_vss_hpf_cfgs);
+                        return;
+                }
+
+                for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
+                        wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
+
+                wm8994->vss_hpf_enum.max = pdata->num_vss_hpf_cfgs;
+                wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
+
+                ret = snd_soc_add_controls(wm8994->codec, control, 1);
+                if (ret != 0)
+                        dev_err(wm8994->codec->dev,
+                                "Failed to add VSS HPFmode controls: %d\n",
+                                ret);
+        }
+
+        if (pdata->num_enh_eq_cfgs) {
+                struct snd_kcontrol_new control[] = {
+                        SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
+                                     wm8958_get_enh_eq_enum,
+                                     wm8958_put_enh_eq_enum),
+                };
+
+                /* We need an array of texts for the enum API */
+                wm8994->enh_eq_texts = kmalloc(sizeof(char *)
+                                                * pdata->num_enh_eq_cfgs, GFP_KERNEL);
+                if (!wm8994->enh_eq_texts) {
+                        dev_err(wm8994->codec->dev,
+                                "Failed to allocate %d enhanced EQ config texts\n",
+                                pdata->num_enh_eq_cfgs);
+                        return;
+                }
+
+                for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
+                        wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
+
+                wm8994->enh_eq_enum.max = pdata->num_enh_eq_cfgs;
+                wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
+
+                ret = snd_soc_add_controls(wm8994->codec, control, 1);
+                if (ret != 0)
+                        dev_err(wm8994->codec->dev,
+                                "Failed to add enhanced EQ controls: %d\n",
+                                ret);
+        }
+}
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
index 3c6ee61f6c95..4393394b7bc1 100644
--- a/sound/soc/codecs/wm8960.c
+++ b/sound/soc/codecs/wm8960.c
@@ -20,7 +20,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 #include <sound/wm8960.h>
@@ -29,8 +28,6 @@
 
 #define AUDIO_NAME "wm8960"
 
-struct snd_soc_codec_device soc_codec_dev_wm8960;
-
 /* R25 - Power 1 */
 #define WM8960_VMID_MASK 0x180
 #define WM8960_VREF      0x40
@@ -74,8 +71,10 @@ static const u16 wm8960_reg[WM8960_CACHEREGNUM] = {
 };
 
 struct wm8960_priv {
-        u16 reg_cache[WM8960_CACHEREGNUM];
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
+        void *control_data;
+        int (*set_bias_level)(struct snd_soc_codec *,
+                              enum snd_soc_bias_level level);
         struct snd_soc_dapm_widget *lout1;
         struct snd_soc_dapm_widget *rout1;
         struct snd_soc_dapm_widget *out3;
@@ -137,7 +136,8 @@ static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
         struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
 
-        return wm8960->deemph;
+        ucontrol->value.enumerated.item[0] = wm8960->deemph;
+        return 0;
 }
 
 static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
@@ -387,27 +387,28 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec)
 {
         struct wm8960_data *pdata = codec->dev->platform_data;
         struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
         struct snd_soc_dapm_widget *w;
 
-        snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets,
+        snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
                                   ARRAY_SIZE(wm8960_dapm_widgets));
 
-        snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
+        snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
 
         /* In capless mode OUT3 is used to provide VMID for the
          * headphone outputs, otherwise it is used as a mono mixer.
          */
         if (pdata && pdata->capless) {
-                snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets_capless,
+                snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
                                           ARRAY_SIZE(wm8960_dapm_widgets_capless));
 
-                snd_soc_dapm_add_routes(codec, audio_paths_capless,
+                snd_soc_dapm_add_routes(dapm, audio_paths_capless,
                                         ARRAY_SIZE(audio_paths_capless));
         } else {
-                snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets_out3,
+                snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
                                           ARRAY_SIZE(wm8960_dapm_widgets_out3));
 
-                snd_soc_dapm_add_routes(codec, audio_paths_out3,
+                snd_soc_dapm_add_routes(dapm, audio_paths_out3,
                                         ARRAY_SIZE(audio_paths_out3));
         }
 
@@ -416,7 +417,9 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec)
          * list each time to find the desired power state do so now
          * and save the result.
          */
-        list_for_each_entry(w, &codec->dapm_widgets, list) {
+        list_for_each_entry(w, &codec->card->widgets, list) {
+                if (w->dapm != &codec->dapm)
+                        continue;
                 if (strcmp(w->name, "LOUT1 PGA") == 0)
                         wm8960->lout1 = w;
                 if (strcmp(w->name, "ROUT1 PGA") == 0)
@@ -507,8 +510,7 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
         u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
         int i;
@@ -572,7 +574,7 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Enable anti-pop features */
                         snd_soc_write(codec, WM8960_APOP1,
                                       WM8960_POBCTRL | WM8960_SOFT_ST |
@@ -610,7 +612,7 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -626,7 +628,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_PREPARE:
-                switch (codec->bias_level) {
+                switch (codec->dapm.bias_level) {
                 case SND_SOC_BIAS_STANDBY:
                         /* Enable anti pop mode */
                         snd_soc_update_bits(codec, WM8960_APOP1,
@@ -681,7 +683,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                switch (codec->bias_level) {
+                switch (codec->dapm.bias_level) {
                 case SND_SOC_BIAS_PREPARE:
                         /* Disable HP discharge */
                         snd_soc_update_bits(codec, WM8960_APOP2,
@@ -705,7 +707,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -849,6 +851,14 @@ static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
         return 0;
 }
 
+static int wm8960_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+
+        return wm8960->set_bias_level(codec, level);
+}
+
 #define WM8960_RATES SNDRV_PCM_RATE_8000_48000
 
 #define WM8960_FORMATS \
@@ -863,8 +873,8 @@ static struct snd_soc_dai_ops wm8960_dai_ops = {
         .set_pll = wm8960_set_dai_pll,
 };
 
-struct snd_soc_dai wm8960_dai = {
-        .name = "WM8960",
+static struct snd_soc_dai_driver wm8960_dai = {
+        .name = "wm8960-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -880,21 +890,18 @@ struct snd_soc_dai wm8960_dai = {
         .ops = &wm8960_dai_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8960_dai);
 
-static int wm8960_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8960_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
 
-        codec->set_bias_level(codec, SND_SOC_BIAS_OFF);
+        wm8960->set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8960_resume(struct platform_device *pdev)
+static int wm8960_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -906,78 +913,19 @@ static int wm8960_resume(struct platform_device *pdev)
                 codec->hw_write(codec->control_data, data, 2);
         }
 
-        codec->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-
+        wm8960->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         return 0;
 }
 
-static struct snd_soc_codec *wm8960_codec;
-
-static int wm8960_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8960_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8960_codec;
-        codec = wm8960_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8960_snd_controls,
-                             ARRAY_SIZE(wm8960_snd_controls));
-        wm8960_add_widgets(codec);
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-/* power down chip */
-static int wm8960_remove(struct platform_device *pdev)
+static int wm8960_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8960 = {
-        .probe =        wm8960_probe,
-        .remove =       wm8960_remove,
-        .suspend =      wm8960_suspend,
-        .resume =       wm8960_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8960);
-
-static int wm8960_register(struct wm8960_priv *wm8960,
-                           enum snd_soc_control_type control)
-{
-        struct wm8960_data *pdata = wm8960->codec.dev->platform_data;
-        struct snd_soc_codec *codec = &wm8960->codec;
+        struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+        struct wm8960_data *pdata = dev_get_platdata(codec->dev);
         int ret;
         u16 reg;
 
-        if (wm8960_codec) {
-                dev_err(codec->dev, "Another WM8960 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        codec->set_bias_level = wm8960_set_bias_level_out3;
+        wm8960->set_bias_level = wm8960_set_bias_level_out3;
+        codec->control_data = wm8960->control_data;
 
         if (!pdata) {
                 dev_warn(codec->dev, "No platform data supplied\n");
@@ -988,39 +936,22 @@ static int wm8960_register(struct wm8960_priv *wm8960,
                 }
 
                 if (pdata->capless)
-                        codec->set_bias_level = wm8960_set_bias_level_capless;
+                        wm8960->set_bias_level = wm8960_set_bias_level_capless;
         }
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8960);
-        codec->name = "WM8960";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->dai = &wm8960_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8960_CACHEREGNUM;
-        codec->reg_cache = &wm8960->reg_cache;
-
-        memcpy(codec->reg_cache, wm8960_reg, sizeof(wm8960_reg));
-
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8960->control_type);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = wm8960_reset(codec);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to issue reset\n");
-                goto err;
+                return ret;
         }
 
-        wm8960_dai.dev = codec->dev;
-
-        codec->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        wm8960->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         /* Latch the update bits */
         reg = snd_soc_read(codec, WM8960_LINVOL);
@@ -1044,62 +975,59 @@ static int wm8960_register(struct wm8960_priv *wm8960,
         reg = snd_soc_read(codec, WM8960_ROUT2);
         snd_soc_write(codec, WM8960_ROUT2, reg | 0x100);
 
-        wm8960_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&wm8960_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+        snd_soc_add_controls(codec, wm8960_snd_controls,
+                                     ARRAY_SIZE(wm8960_snd_controls));
+        wm8960_add_widgets(codec);
 
         return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8960);
-        return ret;
 }
 
-static void wm8960_unregister(struct wm8960_priv *wm8960)
+/* power down chip */
+static int wm8960_remove(struct snd_soc_codec *codec)
 {
-        wm8960->codec.set_bias_level(&wm8960->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm8960_dai);
-        snd_soc_unregister_codec(&wm8960->codec);
-        kfree(wm8960);
-        wm8960_codec = NULL;
+        struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+
+        wm8960->set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8960 = {
+        .probe =        wm8960_probe,
+        .remove =       wm8960_remove,
+        .suspend =      wm8960_suspend,
+        .resume =       wm8960_resume,
+        .set_bias_level = wm8960_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8960_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8960_reg,
+};
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int wm8960_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm8960_priv *wm8960;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8960 = kzalloc(sizeof(struct wm8960_priv), GFP_KERNEL);
         if (wm8960 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8960->codec;
-
         i2c_set_clientdata(i2c, wm8960);
-        codec->control_data = i2c;
-
-        codec->dev = &i2c->dev;
+        wm8960->control_type = SND_SOC_I2C;
+        wm8960->control_data = i2c;
 
-        return wm8960_register(wm8960, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8960, &wm8960_dai, 1);
+        if (ret < 0)
+                kfree(wm8960);
+        return ret;
 }
 
 static __devexit int wm8960_i2c_remove(struct i2c_client *client)
 {
-        struct wm8960_priv *wm8960 = i2c_get_clientdata(client);
-        wm8960_unregister(wm8960);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -1111,35 +1039,37 @@ MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
 
 static struct i2c_driver wm8960_i2c_driver = {
         .driver = {
-                .name = "wm8960",
+                .name = "wm8960-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8960_i2c_probe,
         .remove =   __devexit_p(wm8960_i2c_remove),
         .id_table = wm8960_i2c_id,
 };
+#endif
 
 static int __init wm8960_modinit(void)
 {
-        int ret;
-
+        int ret = 0;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8960_i2c_driver);
         if (ret != 0) {
                 printk(KERN_ERR "Failed to register WM8960 I2C driver: %d\n",
                        ret);
         }
-
+#endif
         return ret;
 }
 module_init(wm8960_modinit);
 
 static void __exit wm8960_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm8960_i2c_driver);
+#endif
 }
 module_exit(wm8960_exit);
 
-
 MODULE_DESCRIPTION("ASoC WM8960 driver");
 MODULE_AUTHOR("Liam Girdwood");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8960.h b/sound/soc/codecs/wm8960.h
index a5ef65481b86..2d8163d7004b 100644
--- a/sound/soc/codecs/wm8960.h
+++ b/sound/soc/codecs/wm8960.h
@@ -110,7 +110,4 @@
 #define WM8960_OPCLK_DIV_5_5            (4 << 0)
 #define WM8960_OPCLK_DIV_6              (5 << 0)
 
-extern struct snd_soc_dai wm8960_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8960;
-
 #endif
diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c
index 2549d3a297ab..cdee8103d09b 100644
--- a/sound/soc/codecs/wm8961.c
+++ b/sound/soc/codecs/wm8961.c
@@ -23,7 +23,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
@@ -288,12 +287,11 @@ static u16 wm8961_reg_defaults[] = {
 };
 
 struct wm8961_priv {
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
         int sysclk;
-        u16 reg_cache[WM8961_MAX_REGISTER];
 };
 
-static int wm8961_volatile_register(unsigned int reg)
+static int wm8961_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
 {
         switch (reg) {
         case WM8961_SOFTWARE_RESET:
@@ -711,7 +709,7 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream,
         if (fs <= 24000)
                 reg |= WM8961_DACSLOPE;
         else
-                reg &= WM8961_DACSLOPE;
+                reg &= ~WM8961_DACSLOPE;
         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
 
         return 0;
@@ -736,7 +734,7 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
                 freq /= 2;
         } else {
                 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
-                reg &= WM8961_MCLKDIV;
+                reg &= ~WM8961_MCLKDIV;
         }
 
         snd_soc_write(codec, WM8961_CLOCKING1, reg);
@@ -882,7 +880,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_PREPARE:
-                if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
                         /* Enable bias generation */
                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
                         reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
@@ -897,7 +895,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_PREPARE) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
                         /* VREF off */
                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
                         reg &= ~WM8961_VREF;
@@ -919,7 +917,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -940,8 +938,8 @@ static struct snd_soc_dai_ops wm8961_dai_ops = {
         .set_clkdiv = wm8961_set_clkdiv,
 };
 
-struct snd_soc_dai wm8961_dai = {
-        .name = "WM8961",
+static struct snd_soc_dai_driver wm8961_dai = {
+        .name = "wm8961-hifi",
         .playback = {
                 .stream_name = "HiFi Playback",
                 .channels_min = 1,
@@ -956,140 +954,23 @@ struct snd_soc_dai wm8961_dai = {
                 .formats = WM8961_FORMATS,},
         .ops = &wm8961_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8961_dai);
 
-
-static struct snd_soc_codec *wm8961_codec;
-
-static int wm8961_probe(struct platform_device *pdev)
+static int wm8961_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
         int ret = 0;
-
-        if (wm8961_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8961_codec;
-        codec = wm8961_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8961_snd_controls,
-                                ARRAY_SIZE(wm8961_snd_controls));
-        snd_soc_dapm_new_controls(codec, wm8961_dapm_widgets,
-                                  ARRAY_SIZE(wm8961_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-static int wm8961_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-#ifdef CONFIG_PM
-static int wm8961_suspend(struct platform_device *pdev, pm_message_t state)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
-
-        return 0;
-}
-
-static int wm8961_resume(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-        u16 *reg_cache = codec->reg_cache;
-        int i;
-
-        for (i = 0; i < codec->reg_cache_size; i++) {
-                if (reg_cache[i] == wm8961_reg_defaults[i])
-                        continue;
-
-                if (i == WM8961_SOFTWARE_RESET)
-                        continue;
-
-                snd_soc_write(codec, i, reg_cache[i]);
-        }
-
-        wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-
-        return 0;
-}
-#else
-#define wm8961_suspend NULL
-#define wm8961_resume NULL
-#endif
-
-struct snd_soc_codec_device soc_codec_dev_wm8961 = {
-        .probe =        wm8961_probe,
-        .remove =       wm8961_remove,
-        .suspend =      wm8961_suspend,
-        .resume =       wm8961_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8961);
-
-static int wm8961_register(struct wm8961_priv *wm8961)
-{
-        struct snd_soc_codec *codec = &wm8961->codec;
-        int ret;
         u16 reg;
 
-        if (wm8961_codec) {
-                dev_err(codec->dev, "Another WM8961 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8961);
-        codec->name = "WM8961";
-        codec->owner = THIS_MODULE;
-        codec->dai = &wm8961_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(wm8961->reg_cache);
-        codec->reg_cache = &wm8961->reg_cache;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8961_set_bias_level;
-        codec->volatile_register = wm8961_volatile_register;
-
-        memcpy(codec->reg_cache, wm8961_reg_defaults,
-               sizeof(wm8961_reg_defaults));
-
         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
         if (ret != 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
         if (reg != 0x1801) {
                 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
-                ret = -EINVAL;
-                goto err;
+                return -EINVAL;
         }
 
         /* This isn't volatile - readback doesn't correspond to write */
@@ -1102,7 +983,7 @@ static int wm8961_register(struct wm8961_priv *wm8961)
         ret = wm8961_reset(codec);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to issue reset\n");
-                goto err;
+                return ret;
         }
 
         /* Enable class W */
@@ -1140,64 +1021,89 @@ static int wm8961_register(struct wm8961_priv *wm8961)
 
         wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
-        wm8961_dai.dev = codec->dev;
+        snd_soc_add_controls(codec, wm8961_snd_controls,
+                                ARRAY_SIZE(wm8961_snd_controls));
+        snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets,
+                                  ARRAY_SIZE(wm8961_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
 
-        wm8961_codec = codec;
+        return 0;
+}
 
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
+static int wm8961_remove(struct snd_soc_codec *codec)
+{
+        wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
 
-        ret = snd_soc_register_dai(&wm8961_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+#ifdef CONFIG_PM
+static int wm8961_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8961);
-        return ret;
 }
 
-static void wm8961_unregister(struct wm8961_priv *wm8961)
+static int wm8961_resume(struct snd_soc_codec *codec)
 {
-        wm8961_set_bias_level(&wm8961->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm8961_dai);
-        snd_soc_unregister_codec(&wm8961->codec);
-        kfree(wm8961);
-        wm8961_codec = NULL;
+        u16 *reg_cache = codec->reg_cache;
+        int i;
+
+        for (i = 0; i < codec->driver->reg_cache_size; i++) {
+                if (reg_cache[i] == wm8961_reg_defaults[i])
+                        continue;
+
+                if (i == WM8961_SOFTWARE_RESET)
+                        continue;
+
+                snd_soc_write(codec, i, reg_cache[i]);
+        }
+
+        wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        return 0;
 }
+#else
+#define wm8961_suspend NULL
+#define wm8961_resume NULL
+#endif
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
+        .probe =        wm8961_probe,
+        .remove =       wm8961_remove,
+        .suspend =      wm8961_suspend,
+        .resume =       wm8961_resume,
+        .set_bias_level = wm8961_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8961_reg_defaults),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8961_reg_defaults,
+        .volatile_register = wm8961_volatile_register,
+};
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm8961_priv *wm8961;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8961 = kzalloc(sizeof(struct wm8961_priv), GFP_KERNEL);
         if (wm8961 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8961->codec;
-
         i2c_set_clientdata(i2c, wm8961);
-        codec->control_data = i2c;
 
-        codec->dev = &i2c->dev;
-
-        return wm8961_register(wm8961);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8961, &wm8961_dai, 1);
+        if (ret < 0)
+                kfree(wm8961);
+        return ret;
 }
 
 static __devexit int wm8961_i2c_remove(struct i2c_client *client)
 {
-        struct wm8961_priv *wm8961 = i2c_get_clientdata(client);
-        wm8961_unregister(wm8961);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -1209,35 +1115,37 @@ MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
 
 static struct i2c_driver wm8961_i2c_driver = {
         .driver = {
-                .name = "wm8961",
+                .name = "wm8961-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8961_i2c_probe,
         .remove =   __devexit_p(wm8961_i2c_remove),
         .id_table = wm8961_i2c_id,
 };
+#endif
 
 static int __init wm8961_modinit(void)
 {
-        int ret;
-
+        int ret = 0;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8961_i2c_driver);
         if (ret != 0) {
-                printk(KERN_ERR "Failed to register WM8961 I2C driver: %d\n",
+                printk(KERN_ERR "Failed to register wm8961 I2C driver: %d\n",
                        ret);
         }
-
+#endif
         return ret;
 }
 module_init(wm8961_modinit);
 
 static void __exit wm8961_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm8961_i2c_driver);
+#endif
 }
 module_exit(wm8961_exit);
 
-
 MODULE_DESCRIPTION("ASoC WM8961 driver");
 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8961.h b/sound/soc/codecs/wm8961.h
index 5513bfd720d6..1d736e5701c8 100644
--- a/sound/soc/codecs/wm8961.h
+++ b/sound/soc/codecs/wm8961.h
@@ -11,9 +11,6 @@
 
 #include <sound/soc.h>
 
-extern struct snd_soc_codec_device soc_codec_dev_wm8961;
-extern struct snd_soc_dai wm8961_dai;
-
 #define WM8961_BCLK  1
 #define WM8961_LRCLK 2
 
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
new file mode 100644
index 000000000000..5e05eed96c38
--- /dev/null
+++ b/sound/soc/codecs/wm8962.c
@@ -0,0 +1,4045 @@
+/*
+ * wm8962.c  --  WM8962 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/gcd.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <sound/core.h>
+#include <sound/jack.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <sound/wm8962.h>
+#include <trace/events/asoc.h>
+
+#include "wm8962.h"
+
+#define WM8962_NUM_SUPPLIES 8
+static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
+        "DCVDD",
+        "DBVDD",
+        "AVDD",
+        "CPVDD",
+        "MICVDD",
+        "PLLVDD",
+        "SPKVDD1",
+        "SPKVDD2",
+};
+
+/* codec private data */
+struct wm8962_priv {
+        struct snd_soc_codec *codec;
+
+        int sysclk;
+        int sysclk_rate;
+
+        int bclk;  /* Desired BCLK */
+        int lrclk;
+
+        struct completion fll_lock;
+        int fll_src;
+        int fll_fref;
+        int fll_fout;
+
+        struct delayed_work mic_work;
+        struct snd_soc_jack *jack;
+
+        struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
+        struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
+
+#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
+        struct input_dev *beep;
+        struct work_struct beep_work;
+        int beep_rate;
+#endif
+
+#ifdef CONFIG_GPIOLIB
+        struct gpio_chip gpio_chip;
+#endif
+};
+
+/* We can't use the same notifier block for more than one supply and
+ * there's no way I can see to get from a callback to the caller
+ * except container_of().
+ */
+#define WM8962_REGULATOR_EVENT(n) \
+static int wm8962_regulator_event_##n(struct notifier_block *nb, \
+                                    unsigned long event, void *data)    \
+{ \
+        struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
+                                                  disable_nb[n]); \
+        if (event & REGULATOR_EVENT_DISABLE) { \
+                wm8962->codec->cache_sync = 1; \
+        } \
+        return 0; \
+}
+
+WM8962_REGULATOR_EVENT(0)
+WM8962_REGULATOR_EVENT(1)
+WM8962_REGULATOR_EVENT(2)
+WM8962_REGULATOR_EVENT(3)
+WM8962_REGULATOR_EVENT(4)
+WM8962_REGULATOR_EVENT(5)
+WM8962_REGULATOR_EVENT(6)
+WM8962_REGULATOR_EVENT(7)
+
+static const u16 wm8962_reg[WM8962_MAX_REGISTER + 1] = {
+        [0] = 0x009F,     /* R0     - Left Input volume */
+        [1] = 0x049F,     /* R1     - Right Input volume */
+        [2] = 0x0000,     /* R2     - HPOUTL volume */
+        [3] = 0x0000,     /* R3     - HPOUTR volume */
+        [4] = 0x0020,     /* R4     - Clocking1 */
+        [5] = 0x0018,     /* R5     - ADC & DAC Control 1 */
+        [6] = 0x2008,     /* R6     - ADC & DAC Control 2 */
+        [7] = 0x000A,     /* R7     - Audio Interface 0 */
+        [8] = 0x01E4,     /* R8     - Clocking2 */
+        [9] = 0x0300,     /* R9     - Audio Interface 1 */
+        [10] = 0x00C0,    /* R10    - Left DAC volume */
+        [11] = 0x00C0,    /* R11    - Right DAC volume */
+
+        [14] = 0x0040,     /* R14    - Audio Interface 2 */
+        [15] = 0x6243,     /* R15    - Software Reset */
+
+        [17] = 0x007B,     /* R17    - ALC1 */
+        [18] = 0x0000,     /* R18    - ALC2 */
+        [19] = 0x1C32,     /* R19    - ALC3 */
+        [20] = 0x3200,     /* R20    - Noise Gate */
+        [21] = 0x00C0,     /* R21    - Left ADC volume */
+        [22] = 0x00C0,     /* R22    - Right ADC volume */
+        [23] = 0x0160,     /* R23    - Additional control(1) */
+        [24] = 0x0000,     /* R24    - Additional control(2) */
+        [25] = 0x0000,     /* R25    - Pwr Mgmt (1) */
+        [26] = 0x0000,     /* R26    - Pwr Mgmt (2) */
+        [27] = 0x0010,     /* R27    - Additional Control (3) */
+        [28] = 0x0000,     /* R28    - Anti-pop */
+
+        [30] = 0x005E,     /* R30    - Clocking 3 */
+        [31] = 0x0000,     /* R31    - Input mixer control (1) */
+        [32] = 0x0145,     /* R32    - Left input mixer volume */
+        [33] = 0x0145,     /* R33    - Right input mixer volume */
+        [34] = 0x0009,     /* R34    - Input mixer control (2) */
+        [35] = 0x0003,     /* R35    - Input bias control */
+        [37] = 0x0008,     /* R37    - Left input PGA control */
+        [38] = 0x0008,     /* R38    - Right input PGA control */
+
+        [40] = 0x0000,     /* R40    - SPKOUTL volume */
+        [41] = 0x0000,     /* R41    - SPKOUTR volume */
+
+        [47] = 0x0000,     /* R47    - Thermal Shutdown Status */
+        [48] = 0x8027,     /* R48    - Additional Control (4) */
+        [49] = 0x0010,     /* R49    - Class D Control 1 */
+
+        [51] = 0x0003,     /* R51    - Class D Control 2 */
+
+        [56] = 0x0506,     /* R56    - Clocking 4 */
+        [57] = 0x0000,     /* R57    - DAC DSP Mixing (1) */
+        [58] = 0x0000,     /* R58    - DAC DSP Mixing (2) */
+
+        [60] = 0x0300,     /* R60    - DC Servo 0 */
+        [61] = 0x0300,     /* R61    - DC Servo 1 */
+
+        [64] = 0x0810,     /* R64    - DC Servo 4 */
+
+        [66] = 0x0000,     /* R66    - DC Servo 6 */
+
+        [68] = 0x001B,     /* R68    - Analogue PGA Bias */
+        [69] = 0x0000,     /* R69    - Analogue HP 0 */
+
+        [71] = 0x01FB,     /* R71    - Analogue HP 2 */
+        [72] = 0x0000,     /* R72    - Charge Pump 1 */
+
+        [82] = 0x0004,     /* R82    - Charge Pump B */
+
+        [87] = 0x0000,     /* R87    - Write Sequencer Control 1 */
+
+        [90] = 0x0000,     /* R90    - Write Sequencer Control 2 */
+
+        [93] = 0x0000,     /* R93    - Write Sequencer Control 3 */
+        [94] = 0x0000,     /* R94    - Control Interface */
+
+        [99] = 0x0000,     /* R99    - Mixer Enables */
+        [100] = 0x0000,     /* R100   - Headphone Mixer (1) */
+        [101] = 0x0000,     /* R101   - Headphone Mixer (2) */
+        [102] = 0x013F,     /* R102   - Headphone Mixer (3) */
+        [103] = 0x013F,     /* R103   - Headphone Mixer (4) */
+
+        [105] = 0x0000,     /* R105   - Speaker Mixer (1) */
+        [106] = 0x0000,     /* R106   - Speaker Mixer (2) */
+        [107] = 0x013F,     /* R107   - Speaker Mixer (3) */
+        [108] = 0x013F,     /* R108   - Speaker Mixer (4) */
+        [109] = 0x0003,     /* R109   - Speaker Mixer (5) */
+        [110] = 0x0002,     /* R110   - Beep Generator (1) */
+
+        [115] = 0x0006,     /* R115   - Oscillator Trim (3) */
+        [116] = 0x0026,     /* R116   - Oscillator Trim (4) */
+
+        [119] = 0x0000,     /* R119   - Oscillator Trim (7) */
+
+        [124] = 0x0011,     /* R124   - Analogue Clocking1 */
+        [125] = 0x004B,     /* R125   - Analogue Clocking2 */
+        [126] = 0x000D,     /* R126   - Analogue Clocking3 */
+        [127] = 0x0000,     /* R127   - PLL Software Reset */
+
+        [129] = 0x0000,     /* R129   - PLL2 */
+
+        [131] = 0x0000,     /* R131   - PLL 4 */
+
+        [136] = 0x0067,     /* R136   - PLL 9 */
+        [137] = 0x001C,     /* R137   - PLL 10 */
+        [138] = 0x0071,     /* R138   - PLL 11 */
+        [139] = 0x00C7,     /* R139   - PLL 12 */
+        [140] = 0x0067,     /* R140   - PLL 13 */
+        [141] = 0x0048,     /* R141   - PLL 14 */
+        [142] = 0x0022,     /* R142   - PLL 15 */
+        [143] = 0x0097,     /* R143   - PLL 16 */
+
+        [155] = 0x000C,     /* R155   - FLL Control (1) */
+        [156] = 0x0039,     /* R156   - FLL Control (2) */
+        [157] = 0x0180,     /* R157   - FLL Control (3) */
+
+        [159] = 0x0032,     /* R159   - FLL Control (5) */
+        [160] = 0x0018,     /* R160   - FLL Control (6) */
+        [161] = 0x007D,     /* R161   - FLL Control (7) */
+        [162] = 0x0008,     /* R162   - FLL Control (8) */
+
+        [252] = 0x0005,     /* R252   - General test 1 */
+
+        [256] = 0x0000,     /* R256   - DF1 */
+        [257] = 0x0000,     /* R257   - DF2 */
+        [258] = 0x0000,     /* R258   - DF3 */
+        [259] = 0x0000,     /* R259   - DF4 */
+        [260] = 0x0000,     /* R260   - DF5 */
+        [261] = 0x0000,     /* R261   - DF6 */
+        [262] = 0x0000,     /* R262   - DF7 */
+
+        [264] = 0x0000,     /* R264   - LHPF1 */
+        [265] = 0x0000,     /* R265   - LHPF2 */
+
+        [268] = 0x0000,     /* R268   - THREED1 */
+        [269] = 0x0000,     /* R269   - THREED2 */
+        [270] = 0x0000,     /* R270   - THREED3 */
+        [271] = 0x0000,     /* R271   - THREED4 */
+
+        [276] = 0x000C,     /* R276   - DRC 1 */
+        [277] = 0x0925,     /* R277   - DRC 2 */
+        [278] = 0x0000,     /* R278   - DRC 3 */
+        [279] = 0x0000,     /* R279   - DRC 4 */
+        [280] = 0x0000,     /* R280   - DRC 5 */
+
+        [285] = 0x0000,     /* R285   - Tloopback */
+
+        [335] = 0x0004,     /* R335   - EQ1 */
+        [336] = 0x6318,     /* R336   - EQ2 */
+        [337] = 0x6300,     /* R337   - EQ3 */
+        [338] = 0x0FCA,     /* R338   - EQ4 */
+        [339] = 0x0400,     /* R339   - EQ5 */
+        [340] = 0x00D8,     /* R340   - EQ6 */
+        [341] = 0x1EB5,     /* R341   - EQ7 */
+        [342] = 0xF145,     /* R342   - EQ8 */
+        [343] = 0x0B75,     /* R343   - EQ9 */
+        [344] = 0x01C5,     /* R344   - EQ10 */
+        [345] = 0x1C58,     /* R345   - EQ11 */
+        [346] = 0xF373,     /* R346   - EQ12 */
+        [347] = 0x0A54,     /* R347   - EQ13 */
+        [348] = 0x0558,     /* R348   - EQ14 */
+        [349] = 0x168E,     /* R349   - EQ15 */
+        [350] = 0xF829,     /* R350   - EQ16 */
+        [351] = 0x07AD,     /* R351   - EQ17 */
+        [352] = 0x1103,     /* R352   - EQ18 */
+        [353] = 0x0564,     /* R353   - EQ19 */
+        [354] = 0x0559,     /* R354   - EQ20 */
+        [355] = 0x4000,     /* R355   - EQ21 */
+        [356] = 0x6318,     /* R356   - EQ22 */
+        [357] = 0x6300,     /* R357   - EQ23 */
+        [358] = 0x0FCA,     /* R358   - EQ24 */
+        [359] = 0x0400,     /* R359   - EQ25 */
+        [360] = 0x00D8,     /* R360   - EQ26 */
+        [361] = 0x1EB5,     /* R361   - EQ27 */
+        [362] = 0xF145,     /* R362   - EQ28 */
+        [363] = 0x0B75,     /* R363   - EQ29 */
+        [364] = 0x01C5,     /* R364   - EQ30 */
+        [365] = 0x1C58,     /* R365   - EQ31 */
+        [366] = 0xF373,     /* R366   - EQ32 */
+        [367] = 0x0A54,     /* R367   - EQ33 */
+        [368] = 0x0558,     /* R368   - EQ34 */
+        [369] = 0x168E,     /* R369   - EQ35 */
+        [370] = 0xF829,     /* R370   - EQ36 */
+        [371] = 0x07AD,     /* R371   - EQ37 */
+        [372] = 0x1103,     /* R372   - EQ38 */
+        [373] = 0x0564,     /* R373   - EQ39 */
+        [374] = 0x0559,     /* R374   - EQ40 */
+        [375] = 0x4000,     /* R375   - EQ41 */
+
+        [513] = 0x0000,     /* R513   - GPIO 2 */
+        [514] = 0x0000,     /* R514   - GPIO 3 */
+
+        [516] = 0x8100,     /* R516   - GPIO 5 */
+        [517] = 0x8100,     /* R517   - GPIO 6 */
+
+        [560] = 0x0000,     /* R560   - Interrupt Status 1 */
+        [561] = 0x0000,     /* R561   - Interrupt Status 2 */
+
+        [568] = 0x0030,     /* R568   - Interrupt Status 1 Mask */
+        [569] = 0xFFED,     /* R569   - Interrupt Status 2 Mask */
+
+        [576] = 0x0000,     /* R576   - Interrupt Control */
+
+        [584] = 0x002D,     /* R584   - IRQ Debounce */
+
+        [586] = 0x0000,     /* R586   -  MICINT Source Pol */
+
+        [768] = 0x1C00,     /* R768   - DSP2 Power Management */
+
+        [1037] = 0x0000,     /* R1037  - DSP2_ExecControl */
+
+        [8192] = 0x0000,     /* R8192  - DSP2 Instruction RAM 0 */
+
+        [9216] = 0x0030,     /* R9216  - DSP2 Address RAM 2 */
+        [9217] = 0x0000,     /* R9217  - DSP2 Address RAM 1 */
+        [9218] = 0x0000,     /* R9218  - DSP2 Address RAM 0 */
+
+        [12288] = 0x0000,     /* R12288 - DSP2 Data1 RAM 1 */
+        [12289] = 0x0000,     /* R12289 - DSP2 Data1 RAM 0 */
+
+        [13312] = 0x0000,     /* R13312 - DSP2 Data2 RAM 1 */
+        [13313] = 0x0000,     /* R13313 - DSP2 Data2 RAM 0 */
+
+        [14336] = 0x0000,     /* R14336 - DSP2 Data3 RAM 1 */
+        [14337] = 0x0000,     /* R14337 - DSP2 Data3 RAM 0 */
+
+        [15360] = 0x000A,     /* R15360 - DSP2 Coeff RAM 0 */
+
+        [16384] = 0x0000,     /* R16384 - RETUNEADC_SHARED_COEFF_1 */
+        [16385] = 0x0000,     /* R16385 - RETUNEADC_SHARED_COEFF_0 */
+        [16386] = 0x0000,     /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
+        [16387] = 0x0000,     /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
+        [16388] = 0x0000,     /* R16388 - SOUNDSTAGE_ENABLES_1 */
+        [16389] = 0x0000,     /* R16389 - SOUNDSTAGE_ENABLES_0 */
+
+        [16896] = 0x0002,     /* R16896 - HDBASS_AI_1 */
+        [16897] = 0xBD12,     /* R16897 - HDBASS_AI_0 */
+        [16898] = 0x007C,     /* R16898 - HDBASS_AR_1 */
+        [16899] = 0x586C,     /* R16899 - HDBASS_AR_0 */
+        [16900] = 0x0053,     /* R16900 - HDBASS_B_1 */
+        [16901] = 0x8121,     /* R16901 - HDBASS_B_0 */
+        [16902] = 0x003F,     /* R16902 - HDBASS_K_1 */
+        [16903] = 0x8BD8,     /* R16903 - HDBASS_K_0 */
+        [16904] = 0x0032,     /* R16904 - HDBASS_N1_1 */
+        [16905] = 0xF52D,     /* R16905 - HDBASS_N1_0 */
+        [16906] = 0x0065,     /* R16906 - HDBASS_N2_1 */
+        [16907] = 0xAC8C,     /* R16907 - HDBASS_N2_0 */
+        [16908] = 0x006B,     /* R16908 - HDBASS_N3_1 */
+        [16909] = 0xE087,     /* R16909 - HDBASS_N3_0 */
+        [16910] = 0x0072,     /* R16910 - HDBASS_N4_1 */
+        [16911] = 0x1483,     /* R16911 - HDBASS_N4_0 */
+        [16912] = 0x0072,     /* R16912 - HDBASS_N5_1 */
+        [16913] = 0x1483,     /* R16913 - HDBASS_N5_0 */
+        [16914] = 0x0043,     /* R16914 - HDBASS_X1_1 */
+        [16915] = 0x3525,     /* R16915 - HDBASS_X1_0 */
+        [16916] = 0x0006,     /* R16916 - HDBASS_X2_1 */
+        [16917] = 0x6A4A,     /* R16917 - HDBASS_X2_0 */
+        [16918] = 0x0043,     /* R16918 - HDBASS_X3_1 */
+        [16919] = 0x6079,     /* R16919 - HDBASS_X3_0 */
+        [16920] = 0x0008,     /* R16920 - HDBASS_ATK_1 */
+        [16921] = 0x0000,     /* R16921 - HDBASS_ATK_0 */
+        [16922] = 0x0001,     /* R16922 - HDBASS_DCY_1 */
+        [16923] = 0x0000,     /* R16923 - HDBASS_DCY_0 */
+        [16924] = 0x0059,     /* R16924 - HDBASS_PG_1 */
+        [16925] = 0x999A,     /* R16925 - HDBASS_PG_0 */
+
+        [17048] = 0x0083,     /* R17408 - HPF_C_1 */
+        [17049] = 0x98AD,     /* R17409 - HPF_C_0 */
+
+        [17920] = 0x007F,     /* R17920 - ADCL_RETUNE_C1_1 */
+        [17921] = 0xFFFF,     /* R17921 - ADCL_RETUNE_C1_0 */
+        [17922] = 0x0000,     /* R17922 - ADCL_RETUNE_C2_1 */
+        [17923] = 0x0000,     /* R17923 - ADCL_RETUNE_C2_0 */
+        [17924] = 0x0000,     /* R17924 - ADCL_RETUNE_C3_1 */
+        [17925] = 0x0000,     /* R17925 - ADCL_RETUNE_C3_0 */
+        [17926] = 0x0000,     /* R17926 - ADCL_RETUNE_C4_1 */
+        [17927] = 0x0000,     /* R17927 - ADCL_RETUNE_C4_0 */
+        [17928] = 0x0000,     /* R17928 - ADCL_RETUNE_C5_1 */
+        [17929] = 0x0000,     /* R17929 - ADCL_RETUNE_C5_0 */
+        [17930] = 0x0000,     /* R17930 - ADCL_RETUNE_C6_1 */
+        [17931] = 0x0000,     /* R17931 - ADCL_RETUNE_C6_0 */
+        [17932] = 0x0000,     /* R17932 - ADCL_RETUNE_C7_1 */
+        [17933] = 0x0000,     /* R17933 - ADCL_RETUNE_C7_0 */
+        [17934] = 0x0000,     /* R17934 - ADCL_RETUNE_C8_1 */
+        [17935] = 0x0000,     /* R17935 - ADCL_RETUNE_C8_0 */
+        [17936] = 0x0000,     /* R17936 - ADCL_RETUNE_C9_1 */
+        [17937] = 0x0000,     /* R17937 - ADCL_RETUNE_C9_0 */
+        [17938] = 0x0000,     /* R17938 - ADCL_RETUNE_C10_1 */
+        [17939] = 0x0000,     /* R17939 - ADCL_RETUNE_C10_0 */
+        [17940] = 0x0000,     /* R17940 - ADCL_RETUNE_C11_1 */
+        [17941] = 0x0000,     /* R17941 - ADCL_RETUNE_C11_0 */
+        [17942] = 0x0000,     /* R17942 - ADCL_RETUNE_C12_1 */
+        [17943] = 0x0000,     /* R17943 - ADCL_RETUNE_C12_0 */
+        [17944] = 0x0000,     /* R17944 - ADCL_RETUNE_C13_1 */
+        [17945] = 0x0000,     /* R17945 - ADCL_RETUNE_C13_0 */
+        [17946] = 0x0000,     /* R17946 - ADCL_RETUNE_C14_1 */
+        [17947] = 0x0000,     /* R17947 - ADCL_RETUNE_C14_0 */
+        [17948] = 0x0000,     /* R17948 - ADCL_RETUNE_C15_1 */
+        [17949] = 0x0000,     /* R17949 - ADCL_RETUNE_C15_0 */
+        [17950] = 0x0000,     /* R17950 - ADCL_RETUNE_C16_1 */
+        [17951] = 0x0000,     /* R17951 - ADCL_RETUNE_C16_0 */
+        [17952] = 0x0000,     /* R17952 - ADCL_RETUNE_C17_1 */
+        [17953] = 0x0000,     /* R17953 - ADCL_RETUNE_C17_0 */
+        [17954] = 0x0000,     /* R17954 - ADCL_RETUNE_C18_1 */
+        [17955] = 0x0000,     /* R17955 - ADCL_RETUNE_C18_0 */
+        [17956] = 0x0000,     /* R17956 - ADCL_RETUNE_C19_1 */
+        [17957] = 0x0000,     /* R17957 - ADCL_RETUNE_C19_0 */
+        [17958] = 0x0000,     /* R17958 - ADCL_RETUNE_C20_1 */
+        [17959] = 0x0000,     /* R17959 - ADCL_RETUNE_C20_0 */
+        [17960] = 0x0000,     /* R17960 - ADCL_RETUNE_C21_1 */
+        [17961] = 0x0000,     /* R17961 - ADCL_RETUNE_C21_0 */
+        [17962] = 0x0000,     /* R17962 - ADCL_RETUNE_C22_1 */
+        [17963] = 0x0000,     /* R17963 - ADCL_RETUNE_C22_0 */
+        [17964] = 0x0000,     /* R17964 - ADCL_RETUNE_C23_1 */
+        [17965] = 0x0000,     /* R17965 - ADCL_RETUNE_C23_0 */
+        [17966] = 0x0000,     /* R17966 - ADCL_RETUNE_C24_1 */
+        [17967] = 0x0000,     /* R17967 - ADCL_RETUNE_C24_0 */
+        [17968] = 0x0000,     /* R17968 - ADCL_RETUNE_C25_1 */
+        [17969] = 0x0000,     /* R17969 - ADCL_RETUNE_C25_0 */
+        [17970] = 0x0000,     /* R17970 - ADCL_RETUNE_C26_1 */
+        [17971] = 0x0000,     /* R17971 - ADCL_RETUNE_C26_0 */
+        [17972] = 0x0000,     /* R17972 - ADCL_RETUNE_C27_1 */
+        [17973] = 0x0000,     /* R17973 - ADCL_RETUNE_C27_0 */
+        [17974] = 0x0000,     /* R17974 - ADCL_RETUNE_C28_1 */
+        [17975] = 0x0000,     /* R17975 - ADCL_RETUNE_C28_0 */
+        [17976] = 0x0000,     /* R17976 - ADCL_RETUNE_C29_1 */
+        [17977] = 0x0000,     /* R17977 - ADCL_RETUNE_C29_0 */
+        [17978] = 0x0000,     /* R17978 - ADCL_RETUNE_C30_1 */
+        [17979] = 0x0000,     /* R17979 - ADCL_RETUNE_C30_0 */
+        [17980] = 0x0000,     /* R17980 - ADCL_RETUNE_C31_1 */
+        [17981] = 0x0000,     /* R17981 - ADCL_RETUNE_C31_0 */
+        [17982] = 0x0000,     /* R17982 - ADCL_RETUNE_C32_1 */
+        [17983] = 0x0000,     /* R17983 - ADCL_RETUNE_C32_0 */
+
+        [18432] = 0x0020,     /* R18432 - RETUNEADC_PG2_1 */
+        [18433] = 0x0000,     /* R18433 - RETUNEADC_PG2_0 */
+        [18434] = 0x0040,     /* R18434 - RETUNEADC_PG_1 */
+        [18435] = 0x0000,     /* R18435 - RETUNEADC_PG_0 */
+
+        [18944] = 0x007F,     /* R18944 - ADCR_RETUNE_C1_1 */
+        [18945] = 0xFFFF,     /* R18945 - ADCR_RETUNE_C1_0 */
+        [18946] = 0x0000,     /* R18946 - ADCR_RETUNE_C2_1 */
+        [18947] = 0x0000,     /* R18947 - ADCR_RETUNE_C2_0 */
+        [18948] = 0x0000,     /* R18948 - ADCR_RETUNE_C3_1 */
+        [18949] = 0x0000,     /* R18949 - ADCR_RETUNE_C3_0 */
+        [18950] = 0x0000,     /* R18950 - ADCR_RETUNE_C4_1 */
+        [18951] = 0x0000,     /* R18951 - ADCR_RETUNE_C4_0 */
+        [18952] = 0x0000,     /* R18952 - ADCR_RETUNE_C5_1 */
+        [18953] = 0x0000,     /* R18953 - ADCR_RETUNE_C5_0 */
+        [18954] = 0x0000,     /* R18954 - ADCR_RETUNE_C6_1 */
+        [18955] = 0x0000,     /* R18955 - ADCR_RETUNE_C6_0 */
+        [18956] = 0x0000,     /* R18956 - ADCR_RETUNE_C7_1 */
+        [18957] = 0x0000,     /* R18957 - ADCR_RETUNE_C7_0 */
+        [18958] = 0x0000,     /* R18958 - ADCR_RETUNE_C8_1 */
+        [18959] = 0x0000,     /* R18959 - ADCR_RETUNE_C8_0 */
+        [18960] = 0x0000,     /* R18960 - ADCR_RETUNE_C9_1 */
+        [18961] = 0x0000,     /* R18961 - ADCR_RETUNE_C9_0 */
+        [18962] = 0x0000,     /* R18962 - ADCR_RETUNE_C10_1 */
+        [18963] = 0x0000,     /* R18963 - ADCR_RETUNE_C10_0 */
+        [18964] = 0x0000,     /* R18964 - ADCR_RETUNE_C11_1 */
+        [18965] = 0x0000,     /* R18965 - ADCR_RETUNE_C11_0 */
+        [18966] = 0x0000,     /* R18966 - ADCR_RETUNE_C12_1 */
+        [18967] = 0x0000,     /* R18967 - ADCR_RETUNE_C12_0 */
+        [18968] = 0x0000,     /* R18968 - ADCR_RETUNE_C13_1 */
+        [18969] = 0x0000,     /* R18969 - ADCR_RETUNE_C13_0 */
+        [18970] = 0x0000,     /* R18970 - ADCR_RETUNE_C14_1 */
+        [18971] = 0x0000,     /* R18971 - ADCR_RETUNE_C14_0 */
+        [18972] = 0x0000,     /* R18972 - ADCR_RETUNE_C15_1 */
+        [18973] = 0x0000,     /* R18973 - ADCR_RETUNE_C15_0 */
+        [18974] = 0x0000,     /* R18974 - ADCR_RETUNE_C16_1 */
+        [18975] = 0x0000,     /* R18975 - ADCR_RETUNE_C16_0 */
+        [18976] = 0x0000,     /* R18976 - ADCR_RETUNE_C17_1 */
+        [18977] = 0x0000,     /* R18977 - ADCR_RETUNE_C17_0 */
+        [18978] = 0x0000,     /* R18978 - ADCR_RETUNE_C18_1 */
+        [18979] = 0x0000,     /* R18979 - ADCR_RETUNE_C18_0 */
+        [18980] = 0x0000,     /* R18980 - ADCR_RETUNE_C19_1 */
+        [18981] = 0x0000,     /* R18981 - ADCR_RETUNE_C19_0 */
+        [18982] = 0x0000,     /* R18982 - ADCR_RETUNE_C20_1 */
+        [18983] = 0x0000,     /* R18983 - ADCR_RETUNE_C20_0 */
+        [18984] = 0x0000,     /* R18984 - ADCR_RETUNE_C21_1 */
+        [18985] = 0x0000,     /* R18985 - ADCR_RETUNE_C21_0 */
+        [18986] = 0x0000,     /* R18986 - ADCR_RETUNE_C22_1 */
+        [18987] = 0x0000,     /* R18987 - ADCR_RETUNE_C22_0 */
+        [18988] = 0x0000,     /* R18988 - ADCR_RETUNE_C23_1 */
+        [18989] = 0x0000,     /* R18989 - ADCR_RETUNE_C23_0 */
+        [18990] = 0x0000,     /* R18990 - ADCR_RETUNE_C24_1 */
+        [18991] = 0x0000,     /* R18991 - ADCR_RETUNE_C24_0 */
+        [18992] = 0x0000,     /* R18992 - ADCR_RETUNE_C25_1 */
+        [18993] = 0x0000,     /* R18993 - ADCR_RETUNE_C25_0 */
+        [18994] = 0x0000,     /* R18994 - ADCR_RETUNE_C26_1 */
+        [18995] = 0x0000,     /* R18995 - ADCR_RETUNE_C26_0 */
+        [18996] = 0x0000,     /* R18996 - ADCR_RETUNE_C27_1 */
+        [18997] = 0x0000,     /* R18997 - ADCR_RETUNE_C27_0 */
+        [18998] = 0x0000,     /* R18998 - ADCR_RETUNE_C28_1 */
+        [18999] = 0x0000,     /* R18999 - ADCR_RETUNE_C28_0 */
+        [19000] = 0x0000,     /* R19000 - ADCR_RETUNE_C29_1 */
+        [19001] = 0x0000,     /* R19001 - ADCR_RETUNE_C29_0 */
+        [19002] = 0x0000,     /* R19002 - ADCR_RETUNE_C30_1 */
+        [19003] = 0x0000,     /* R19003 - ADCR_RETUNE_C30_0 */
+        [19004] = 0x0000,     /* R19004 - ADCR_RETUNE_C31_1 */
+        [19005] = 0x0000,     /* R19005 - ADCR_RETUNE_C31_0 */
+        [19006] = 0x0000,     /* R19006 - ADCR_RETUNE_C32_1 */
+        [19007] = 0x0000,     /* R19007 - ADCR_RETUNE_C32_0 */
+
+        [19456] = 0x007F,     /* R19456 - DACL_RETUNE_C1_1 */
+        [19457] = 0xFFFF,     /* R19457 - DACL_RETUNE_C1_0 */
+        [19458] = 0x0000,     /* R19458 - DACL_RETUNE_C2_1 */
+        [19459] = 0x0000,     /* R19459 - DACL_RETUNE_C2_0 */
+        [19460] = 0x0000,     /* R19460 - DACL_RETUNE_C3_1 */
+        [19461] = 0x0000,     /* R19461 - DACL_RETUNE_C3_0 */
+        [19462] = 0x0000,     /* R19462 - DACL_RETUNE_C4_1 */
+        [19463] = 0x0000,     /* R19463 - DACL_RETUNE_C4_0 */
+        [19464] = 0x0000,     /* R19464 - DACL_RETUNE_C5_1 */
+        [19465] = 0x0000,     /* R19465 - DACL_RETUNE_C5_0 */
+        [19466] = 0x0000,     /* R19466 - DACL_RETUNE_C6_1 */
+        [19467] = 0x0000,     /* R19467 - DACL_RETUNE_C6_0 */
+        [19468] = 0x0000,     /* R19468 - DACL_RETUNE_C7_1 */
+        [19469] = 0x0000,     /* R19469 - DACL_RETUNE_C7_0 */
+        [19470] = 0x0000,     /* R19470 - DACL_RETUNE_C8_1 */
+        [19471] = 0x0000,     /* R19471 - DACL_RETUNE_C8_0 */
+        [19472] = 0x0000,     /* R19472 - DACL_RETUNE_C9_1 */
+        [19473] = 0x0000,     /* R19473 - DACL_RETUNE_C9_0 */
+        [19474] = 0x0000,     /* R19474 - DACL_RETUNE_C10_1 */
+        [19475] = 0x0000,     /* R19475 - DACL_RETUNE_C10_0 */
+        [19476] = 0x0000,     /* R19476 - DACL_RETUNE_C11_1 */
+        [19477] = 0x0000,     /* R19477 - DACL_RETUNE_C11_0 */
+        [19478] = 0x0000,     /* R19478 - DACL_RETUNE_C12_1 */
+        [19479] = 0x0000,     /* R19479 - DACL_RETUNE_C12_0 */
+        [19480] = 0x0000,     /* R19480 - DACL_RETUNE_C13_1 */
+        [19481] = 0x0000,     /* R19481 - DACL_RETUNE_C13_0 */
+        [19482] = 0x0000,     /* R19482 - DACL_RETUNE_C14_1 */
+        [19483] = 0x0000,     /* R19483 - DACL_RETUNE_C14_0 */
+        [19484] = 0x0000,     /* R19484 - DACL_RETUNE_C15_1 */
+        [19485] = 0x0000,     /* R19485 - DACL_RETUNE_C15_0 */
+        [19486] = 0x0000,     /* R19486 - DACL_RETUNE_C16_1 */
+        [19487] = 0x0000,     /* R19487 - DACL_RETUNE_C16_0 */
+        [19488] = 0x0000,     /* R19488 - DACL_RETUNE_C17_1 */
+        [19489] = 0x0000,     /* R19489 - DACL_RETUNE_C17_0 */
+        [19490] = 0x0000,     /* R19490 - DACL_RETUNE_C18_1 */
+        [19491] = 0x0000,     /* R19491 - DACL_RETUNE_C18_0 */
+        [19492] = 0x0000,     /* R19492 - DACL_RETUNE_C19_1 */
+        [19493] = 0x0000,     /* R19493 - DACL_RETUNE_C19_0 */
+        [19494] = 0x0000,     /* R19494 - DACL_RETUNE_C20_1 */
+        [19495] = 0x0000,     /* R19495 - DACL_RETUNE_C20_0 */
+        [19496] = 0x0000,     /* R19496 - DACL_RETUNE_C21_1 */
+        [19497] = 0x0000,     /* R19497 - DACL_RETUNE_C21_0 */
+        [19498] = 0x0000,     /* R19498 - DACL_RETUNE_C22_1 */
+        [19499] = 0x0000,     /* R19499 - DACL_RETUNE_C22_0 */
+        [19500] = 0x0000,     /* R19500 - DACL_RETUNE_C23_1 */
+        [19501] = 0x0000,     /* R19501 - DACL_RETUNE_C23_0 */
+        [19502] = 0x0000,     /* R19502 - DACL_RETUNE_C24_1 */
+        [19503] = 0x0000,     /* R19503 - DACL_RETUNE_C24_0 */
+        [19504] = 0x0000,     /* R19504 - DACL_RETUNE_C25_1 */
+        [19505] = 0x0000,     /* R19505 - DACL_RETUNE_C25_0 */
+        [19506] = 0x0000,     /* R19506 - DACL_RETUNE_C26_1 */
+        [19507] = 0x0000,     /* R19507 - DACL_RETUNE_C26_0 */
+        [19508] = 0x0000,     /* R19508 - DACL_RETUNE_C27_1 */
+        [19509] = 0x0000,     /* R19509 - DACL_RETUNE_C27_0 */
+        [19510] = 0x0000,     /* R19510 - DACL_RETUNE_C28_1 */
+        [19511] = 0x0000,     /* R19511 - DACL_RETUNE_C28_0 */
+        [19512] = 0x0000,     /* R19512 - DACL_RETUNE_C29_1 */
+        [19513] = 0x0000,     /* R19513 - DACL_RETUNE_C29_0 */
+        [19514] = 0x0000,     /* R19514 - DACL_RETUNE_C30_1 */
+        [19515] = 0x0000,     /* R19515 - DACL_RETUNE_C30_0 */
+        [19516] = 0x0000,     /* R19516 - DACL_RETUNE_C31_1 */
+        [19517] = 0x0000,     /* R19517 - DACL_RETUNE_C31_0 */
+        [19518] = 0x0000,     /* R19518 - DACL_RETUNE_C32_1 */
+        [19519] = 0x0000,     /* R19519 - DACL_RETUNE_C32_0 */
+
+        [19968] = 0x0020,     /* R19968 - RETUNEDAC_PG2_1 */
+        [19969] = 0x0000,     /* R19969 - RETUNEDAC_PG2_0 */
+        [19970] = 0x0040,     /* R19970 - RETUNEDAC_PG_1 */
+        [19971] = 0x0000,     /* R19971 - RETUNEDAC_PG_0 */
+
+        [20480] = 0x007F,     /* R20480 - DACR_RETUNE_C1_1 */
+        [20481] = 0xFFFF,     /* R20481 - DACR_RETUNE_C1_0 */
+        [20482] = 0x0000,     /* R20482 - DACR_RETUNE_C2_1 */
+        [20483] = 0x0000,     /* R20483 - DACR_RETUNE_C2_0 */
+        [20484] = 0x0000,     /* R20484 - DACR_RETUNE_C3_1 */
+        [20485] = 0x0000,     /* R20485 - DACR_RETUNE_C3_0 */
+        [20486] = 0x0000,     /* R20486 - DACR_RETUNE_C4_1 */
+        [20487] = 0x0000,     /* R20487 - DACR_RETUNE_C4_0 */
+        [20488] = 0x0000,     /* R20488 - DACR_RETUNE_C5_1 */
+        [20489] = 0x0000,     /* R20489 - DACR_RETUNE_C5_0 */
+        [20490] = 0x0000,     /* R20490 - DACR_RETUNE_C6_1 */
+        [20491] = 0x0000,     /* R20491 - DACR_RETUNE_C6_0 */
+        [20492] = 0x0000,     /* R20492 - DACR_RETUNE_C7_1 */
+        [20493] = 0x0000,     /* R20493 - DACR_RETUNE_C7_0 */
+        [20494] = 0x0000,     /* R20494 - DACR_RETUNE_C8_1 */
+        [20495] = 0x0000,     /* R20495 - DACR_RETUNE_C8_0 */
+        [20496] = 0x0000,     /* R20496 - DACR_RETUNE_C9_1 */
+        [20497] = 0x0000,     /* R20497 - DACR_RETUNE_C9_0 */
+        [20498] = 0x0000,     /* R20498 - DACR_RETUNE_C10_1 */
+        [20499] = 0x0000,     /* R20499 - DACR_RETUNE_C10_0 */
+        [20500] = 0x0000,     /* R20500 - DACR_RETUNE_C11_1 */
+        [20501] = 0x0000,     /* R20501 - DACR_RETUNE_C11_0 */
+        [20502] = 0x0000,     /* R20502 - DACR_RETUNE_C12_1 */
+        [20503] = 0x0000,     /* R20503 - DACR_RETUNE_C12_0 */
+        [20504] = 0x0000,     /* R20504 - DACR_RETUNE_C13_1 */
+        [20505] = 0x0000,     /* R20505 - DACR_RETUNE_C13_0 */
+        [20506] = 0x0000,     /* R20506 - DACR_RETUNE_C14_1 */
+        [20507] = 0x0000,     /* R20507 - DACR_RETUNE_C14_0 */
+        [20508] = 0x0000,     /* R20508 - DACR_RETUNE_C15_1 */
+        [20509] = 0x0000,     /* R20509 - DACR_RETUNE_C15_0 */
+        [20510] = 0x0000,     /* R20510 - DACR_RETUNE_C16_1 */
+        [20511] = 0x0000,     /* R20511 - DACR_RETUNE_C16_0 */
+        [20512] = 0x0000,     /* R20512 - DACR_RETUNE_C17_1 */
+        [20513] = 0x0000,     /* R20513 - DACR_RETUNE_C17_0 */
+        [20514] = 0x0000,     /* R20514 - DACR_RETUNE_C18_1 */
+        [20515] = 0x0000,     /* R20515 - DACR_RETUNE_C18_0 */
+        [20516] = 0x0000,     /* R20516 - DACR_RETUNE_C19_1 */
+        [20517] = 0x0000,     /* R20517 - DACR_RETUNE_C19_0 */
+        [20518] = 0x0000,     /* R20518 - DACR_RETUNE_C20_1 */
+        [20519] = 0x0000,     /* R20519 - DACR_RETUNE_C20_0 */
+        [20520] = 0x0000,     /* R20520 - DACR_RETUNE_C21_1 */
+        [20521] = 0x0000,     /* R20521 - DACR_RETUNE_C21_0 */
+        [20522] = 0x0000,     /* R20522 - DACR_RETUNE_C22_1 */
+        [20523] = 0x0000,     /* R20523 - DACR_RETUNE_C22_0 */
+        [20524] = 0x0000,     /* R20524 - DACR_RETUNE_C23_1 */
+        [20525] = 0x0000,     /* R20525 - DACR_RETUNE_C23_0 */
+        [20526] = 0x0000,     /* R20526 - DACR_RETUNE_C24_1 */
+        [20527] = 0x0000,     /* R20527 - DACR_RETUNE_C24_0 */
+        [20528] = 0x0000,     /* R20528 - DACR_RETUNE_C25_1 */
+        [20529] = 0x0000,     /* R20529 - DACR_RETUNE_C25_0 */
+        [20530] = 0x0000,     /* R20530 - DACR_RETUNE_C26_1 */
+        [20531] = 0x0000,     /* R20531 - DACR_RETUNE_C26_0 */
+        [20532] = 0x0000,     /* R20532 - DACR_RETUNE_C27_1 */
+        [20533] = 0x0000,     /* R20533 - DACR_RETUNE_C27_0 */
+        [20534] = 0x0000,     /* R20534 - DACR_RETUNE_C28_1 */
+        [20535] = 0x0000,     /* R20535 - DACR_RETUNE_C28_0 */
+        [20536] = 0x0000,     /* R20536 - DACR_RETUNE_C29_1 */
+        [20537] = 0x0000,     /* R20537 - DACR_RETUNE_C29_0 */
+        [20538] = 0x0000,     /* R20538 - DACR_RETUNE_C30_1 */
+        [20539] = 0x0000,     /* R20539 - DACR_RETUNE_C30_0 */
+        [20540] = 0x0000,     /* R20540 - DACR_RETUNE_C31_1 */
+        [20541] = 0x0000,     /* R20541 - DACR_RETUNE_C31_0 */
+        [20542] = 0x0000,     /* R20542 - DACR_RETUNE_C32_1 */
+        [20543] = 0x0000,     /* R20543 - DACR_RETUNE_C32_0 */
+
+        [20992] = 0x008C,     /* R20992 - VSS_XHD2_1 */
+        [20993] = 0x0200,     /* R20993 - VSS_XHD2_0 */
+        [20994] = 0x0035,     /* R20994 - VSS_XHD3_1 */
+        [20995] = 0x0700,     /* R20995 - VSS_XHD3_0 */
+        [20996] = 0x003A,     /* R20996 - VSS_XHN1_1 */
+        [20997] = 0x4100,     /* R20997 - VSS_XHN1_0 */
+        [20998] = 0x008B,     /* R20998 - VSS_XHN2_1 */
+        [20999] = 0x7D00,     /* R20999 - VSS_XHN2_0 */
+        [21000] = 0x003A,     /* R21000 - VSS_XHN3_1 */
+        [21001] = 0x4100,     /* R21001 - VSS_XHN3_0 */
+        [21002] = 0x008C,     /* R21002 - VSS_XLA_1 */
+        [21003] = 0xFEE8,     /* R21003 - VSS_XLA_0 */
+        [21004] = 0x0078,     /* R21004 - VSS_XLB_1 */
+        [21005] = 0x0000,     /* R21005 - VSS_XLB_0 */
+        [21006] = 0x003F,     /* R21006 - VSS_XLG_1 */
+        [21007] = 0xB260,     /* R21007 - VSS_XLG_0 */
+        [21008] = 0x002D,     /* R21008 - VSS_PG2_1 */
+        [21009] = 0x1818,     /* R21009 - VSS_PG2_0 */
+        [21010] = 0x0020,     /* R21010 - VSS_PG_1 */
+        [21011] = 0x0000,     /* R21011 - VSS_PG_0 */
+        [21012] = 0x00F1,     /* R21012 - VSS_XTD1_1 */
+        [21013] = 0x8340,     /* R21013 - VSS_XTD1_0 */
+        [21014] = 0x00FB,     /* R21014 - VSS_XTD2_1 */
+        [21015] = 0x8300,     /* R21015 - VSS_XTD2_0 */
+        [21016] = 0x00EE,     /* R21016 - VSS_XTD3_1 */
+        [21017] = 0xAEC0,     /* R21017 - VSS_XTD3_0 */
+        [21018] = 0x00FB,     /* R21018 - VSS_XTD4_1 */
+        [21019] = 0xAC40,     /* R21019 - VSS_XTD4_0 */
+        [21020] = 0x00F1,     /* R21020 - VSS_XTD5_1 */
+        [21021] = 0x7F80,     /* R21021 - VSS_XTD5_0 */
+        [21022] = 0x00F4,     /* R21022 - VSS_XTD6_1 */
+        [21023] = 0x3B40,     /* R21023 - VSS_XTD6_0 */
+        [21024] = 0x00F5,     /* R21024 - VSS_XTD7_1 */
+        [21025] = 0xFB00,     /* R21025 - VSS_XTD7_0 */
+        [21026] = 0x00EA,     /* R21026 - VSS_XTD8_1 */
+        [21027] = 0x10C0,     /* R21027 - VSS_XTD8_0 */
+        [21028] = 0x00FC,     /* R21028 - VSS_XTD9_1 */
+        [21029] = 0xC580,     /* R21029 - VSS_XTD9_0 */
+        [21030] = 0x00E2,     /* R21030 - VSS_XTD10_1 */
+        [21031] = 0x75C0,     /* R21031 - VSS_XTD10_0 */
+        [21032] = 0x0004,     /* R21032 - VSS_XTD11_1 */
+        [21033] = 0xB480,     /* R21033 - VSS_XTD11_0 */
+        [21034] = 0x00D4,     /* R21034 - VSS_XTD12_1 */
+        [21035] = 0xF980,     /* R21035 - VSS_XTD12_0 */
+        [21036] = 0x0004,     /* R21036 - VSS_XTD13_1 */
+        [21037] = 0x9140,     /* R21037 - VSS_XTD13_0 */
+        [21038] = 0x00D8,     /* R21038 - VSS_XTD14_1 */
+        [21039] = 0xA480,     /* R21039 - VSS_XTD14_0 */
+        [21040] = 0x0002,     /* R21040 - VSS_XTD15_1 */
+        [21041] = 0x3DC0,     /* R21041 - VSS_XTD15_0 */
+        [21042] = 0x00CF,     /* R21042 - VSS_XTD16_1 */
+        [21043] = 0x7A80,     /* R21043 - VSS_XTD16_0 */
+        [21044] = 0x00DC,     /* R21044 - VSS_XTD17_1 */
+        [21045] = 0x0600,     /* R21045 - VSS_XTD17_0 */
+        [21046] = 0x00F2,     /* R21046 - VSS_XTD18_1 */
+        [21047] = 0xDAC0,     /* R21047 - VSS_XTD18_0 */
+        [21048] = 0x00BA,     /* R21048 - VSS_XTD19_1 */
+        [21049] = 0xF340,     /* R21049 - VSS_XTD19_0 */
+        [21050] = 0x000A,     /* R21050 - VSS_XTD20_1 */
+        [21051] = 0x7940,     /* R21051 - VSS_XTD20_0 */
+        [21052] = 0x001C,     /* R21052 - VSS_XTD21_1 */
+        [21053] = 0x0680,     /* R21053 - VSS_XTD21_0 */
+        [21054] = 0x00FD,     /* R21054 - VSS_XTD22_1 */
+        [21055] = 0x2D00,     /* R21055 - VSS_XTD22_0 */
+        [21056] = 0x001C,     /* R21056 - VSS_XTD23_1 */
+        [21057] = 0xE840,     /* R21057 - VSS_XTD23_0 */
+        [21058] = 0x000D,     /* R21058 - VSS_XTD24_1 */
+        [21059] = 0xDC40,     /* R21059 - VSS_XTD24_0 */
+        [21060] = 0x00FC,     /* R21060 - VSS_XTD25_1 */
+        [21061] = 0x9D00,     /* R21061 - VSS_XTD25_0 */
+        [21062] = 0x0009,     /* R21062 - VSS_XTD26_1 */
+        [21063] = 0x5580,     /* R21063 - VSS_XTD26_0 */
+        [21064] = 0x00FE,     /* R21064 - VSS_XTD27_1 */
+        [21065] = 0x7E80,     /* R21065 - VSS_XTD27_0 */
+        [21066] = 0x000E,     /* R21066 - VSS_XTD28_1 */
+        [21067] = 0xAB40,     /* R21067 - VSS_XTD28_0 */
+        [21068] = 0x00F9,     /* R21068 - VSS_XTD29_1 */
+        [21069] = 0x9880,     /* R21069 - VSS_XTD29_0 */
+        [21070] = 0x0009,     /* R21070 - VSS_XTD30_1 */
+        [21071] = 0x87C0,     /* R21071 - VSS_XTD30_0 */
+        [21072] = 0x00FD,     /* R21072 - VSS_XTD31_1 */
+        [21073] = 0x2C40,     /* R21073 - VSS_XTD31_0 */
+        [21074] = 0x0009,     /* R21074 - VSS_XTD32_1 */
+        [21075] = 0x4800,     /* R21075 - VSS_XTD32_0 */
+        [21076] = 0x0003,     /* R21076 - VSS_XTS1_1 */
+        [21077] = 0x5F40,     /* R21077 - VSS_XTS1_0 */
+        [21078] = 0x0000,     /* R21078 - VSS_XTS2_1 */
+        [21079] = 0x8700,     /* R21079 - VSS_XTS2_0 */
+        [21080] = 0x00FA,     /* R21080 - VSS_XTS3_1 */
+        [21081] = 0xE4C0,     /* R21081 - VSS_XTS3_0 */
+        [21082] = 0x0000,     /* R21082 - VSS_XTS4_1 */
+        [21083] = 0x0B40,     /* R21083 - VSS_XTS4_0 */
+        [21084] = 0x0004,     /* R21084 - VSS_XTS5_1 */
+        [21085] = 0xE180,     /* R21085 - VSS_XTS5_0 */
+        [21086] = 0x0001,     /* R21086 - VSS_XTS6_1 */
+        [21087] = 0x1F40,     /* R21087 - VSS_XTS6_0 */
+        [21088] = 0x00F8,     /* R21088 - VSS_XTS7_1 */
+        [21089] = 0xB000,     /* R21089 - VSS_XTS7_0 */
+        [21090] = 0x00FB,     /* R21090 - VSS_XTS8_1 */
+        [21091] = 0xCBC0,     /* R21091 - VSS_XTS8_0 */
+        [21092] = 0x0004,     /* R21092 - VSS_XTS9_1 */
+        [21093] = 0xF380,     /* R21093 - VSS_XTS9_0 */
+        [21094] = 0x0007,     /* R21094 - VSS_XTS10_1 */
+        [21095] = 0xDF40,     /* R21095 - VSS_XTS10_0 */
+        [21096] = 0x00FF,     /* R21096 - VSS_XTS11_1 */
+        [21097] = 0x0700,     /* R21097 - VSS_XTS11_0 */
+        [21098] = 0x00EF,     /* R21098 - VSS_XTS12_1 */
+        [21099] = 0xD700,     /* R21099 - VSS_XTS12_0 */
+        [21100] = 0x00FB,     /* R21100 - VSS_XTS13_1 */
+        [21101] = 0xAF40,     /* R21101 - VSS_XTS13_0 */
+        [21102] = 0x0010,     /* R21102 - VSS_XTS14_1 */
+        [21103] = 0x8A80,     /* R21103 - VSS_XTS14_0 */
+        [21104] = 0x0011,     /* R21104 - VSS_XTS15_1 */
+        [21105] = 0x07C0,     /* R21105 - VSS_XTS15_0 */
+        [21106] = 0x00E0,     /* R21106 - VSS_XTS16_1 */
+        [21107] = 0x0800,     /* R21107 - VSS_XTS16_0 */
+        [21108] = 0x00D2,     /* R21108 - VSS_XTS17_1 */
+        [21109] = 0x7600,     /* R21109 - VSS_XTS17_0 */
+        [21110] = 0x0020,     /* R21110 - VSS_XTS18_1 */
+        [21111] = 0xCF40,     /* R21111 - VSS_XTS18_0 */
+        [21112] = 0x0030,     /* R21112 - VSS_XTS19_1 */
+        [21113] = 0x2340,     /* R21113 - VSS_XTS19_0 */
+        [21114] = 0x00FD,     /* R21114 - VSS_XTS20_1 */
+        [21115] = 0x69C0,     /* R21115 - VSS_XTS20_0 */
+        [21116] = 0x0028,     /* R21116 - VSS_XTS21_1 */
+        [21117] = 0x3500,     /* R21117 - VSS_XTS21_0 */
+        [21118] = 0x0006,     /* R21118 - VSS_XTS22_1 */
+        [21119] = 0x3300,     /* R21119 - VSS_XTS22_0 */
+        [21120] = 0x00D9,     /* R21120 - VSS_XTS23_1 */
+        [21121] = 0xF6C0,     /* R21121 - VSS_XTS23_0 */
+        [21122] = 0x00F3,     /* R21122 - VSS_XTS24_1 */
+        [21123] = 0x3340,     /* R21123 - VSS_XTS24_0 */
+        [21124] = 0x000F,     /* R21124 - VSS_XTS25_1 */
+        [21125] = 0x4200,     /* R21125 - VSS_XTS25_0 */
+        [21126] = 0x0004,     /* R21126 - VSS_XTS26_1 */
+        [21127] = 0x0C80,     /* R21127 - VSS_XTS26_0 */
+        [21128] = 0x00FB,     /* R21128 - VSS_XTS27_1 */
+        [21129] = 0x3F80,     /* R21129 - VSS_XTS27_0 */
+        [21130] = 0x00F7,     /* R21130 - VSS_XTS28_1 */
+        [21131] = 0x57C0,     /* R21131 - VSS_XTS28_0 */
+        [21132] = 0x0003,     /* R21132 - VSS_XTS29_1 */
+        [21133] = 0x5400,     /* R21133 - VSS_XTS29_0 */
+        [21134] = 0x0000,     /* R21134 - VSS_XTS30_1 */
+        [21135] = 0xC6C0,     /* R21135 - VSS_XTS30_0 */
+        [21136] = 0x0003,     /* R21136 - VSS_XTS31_1 */
+        [21137] = 0x12C0,     /* R21137 - VSS_XTS31_0 */
+        [21138] = 0x00FD,     /* R21138 - VSS_XTS32_1 */
+        [21139] = 0x8580,     /* R21139 - VSS_XTS32_0 */
+};
+
+static const struct wm8962_reg_access {
+        u16 read;
+        u16 write;
+        u16 vol;
+} wm8962_reg_access[WM8962_MAX_REGISTER + 1] = {
+        [0] = { 0x00FF, 0x01FF, 0x0000 }, /* R0     - Left Input volume */
+        [1] = { 0xFEFF, 0x01FF, 0xFFFF }, /* R1     - Right Input volume */
+        [2] = { 0x00FF, 0x01FF, 0x0000 }, /* R2     - HPOUTL volume */
+        [3] = { 0x00FF, 0x01FF, 0x0000 }, /* R3     - HPOUTR volume */
+        [4] = { 0x07FE, 0x07FE, 0xFFFF }, /* R4     - Clocking1 */
+        [5] = { 0x007F, 0x007F, 0x0000 }, /* R5     - ADC & DAC Control 1 */
+        [6] = { 0x37ED, 0x37ED, 0x0000 }, /* R6     - ADC & DAC Control 2 */
+        [7] = { 0x1FFF, 0x1FFF, 0x0000 }, /* R7     - Audio Interface 0 */
+        [8] = { 0x0FEF, 0x0FEF, 0xFFFF }, /* R8     - Clocking2 */
+        [9] = { 0x0B9F, 0x039F, 0x0000 }, /* R9     - Audio Interface 1 */
+        [10] = { 0x00FF, 0x01FF, 0x0000 }, /* R10    - Left DAC volume */
+        [11] = { 0x00FF, 0x01FF, 0x0000 }, /* R11    - Right DAC volume */
+        [14] = { 0x07FF, 0x07FF, 0x0000 }, /* R14    - Audio Interface 2 */
+        [15] = { 0xFFFF, 0xFFFF, 0xFFFF }, /* R15    - Software Reset */
+        [17] = { 0x07FF, 0x07FF, 0x0000 }, /* R17    - ALC1 */
+        [18] = { 0xF8FF, 0x00FF, 0xFFFF }, /* R18    - ALC2 */
+        [19] = { 0x1DFF, 0x1DFF, 0x0000 }, /* R19    - ALC3 */
+        [20] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20    - Noise Gate */
+        [21] = { 0x00FF, 0x01FF, 0x0000 }, /* R21    - Left ADC volume */
+        [22] = { 0x00FF, 0x01FF, 0x0000 }, /* R22    - Right ADC volume */
+        [23] = { 0x0161, 0x0161, 0x0000 }, /* R23    - Additional control(1) */
+        [24] = { 0x0008, 0x0008, 0x0000 }, /* R24    - Additional control(2) */
+        [25] = { 0x07FE, 0x07FE, 0x0000 }, /* R25    - Pwr Mgmt (1) */
+        [26] = { 0x01FB, 0x01FB, 0x0000 }, /* R26    - Pwr Mgmt (2) */
+        [27] = { 0x0017, 0x0017, 0x0000 }, /* R27    - Additional Control (3) */
+        [28] = { 0x001C, 0x001C, 0x0000 }, /* R28    - Anti-pop */
+
+        [30] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R30    - Clocking 3 */
+        [31] = { 0x000F, 0x000F, 0x0000 }, /* R31    - Input mixer control (1) */
+        [32] = { 0x01FF, 0x01FF, 0x0000 }, /* R32    - Left input mixer volume */
+        [33] = { 0x01FF, 0x01FF, 0x0000 }, /* R33    - Right input mixer volume */
+        [34] = { 0x003F, 0x003F, 0x0000 }, /* R34    - Input mixer control (2) */
+        [35] = { 0x003F, 0x003F, 0x0000 }, /* R35    - Input bias control */
+        [37] = { 0x001F, 0x001F, 0x0000 }, /* R37    - Left input PGA control */
+        [38] = { 0x001F, 0x001F, 0x0000 }, /* R38    - Right input PGA control */
+        [40] = { 0x00FF, 0x01FF, 0x0000 }, /* R40    - SPKOUTL volume */
+        [41] = { 0x00FF, 0x01FF, 0x0000 }, /* R41    - SPKOUTR volume */
+
+        [47] = { 0x000F, 0x0000, 0x0000 }, /* R47    - Thermal Shutdown Status */
+        [48] = { 0x7EC7, 0x7E07, 0xFFFF }, /* R48    - Additional Control (4) */
+        [49] = { 0x00D3, 0x00D7, 0xFFFF }, /* R49    - Class D Control 1 */
+        [51] = { 0x0047, 0x0047, 0x0000 }, /* R51    - Class D Control 2 */
+        [56] = { 0x001E, 0x001E, 0x0000 }, /* R56    - Clocking 4 */
+        [57] = { 0x02FC, 0x02FC, 0x0000 }, /* R57    - DAC DSP Mixing (1) */
+        [58] = { 0x00FC, 0x00FC, 0x0000 }, /* R58    - DAC DSP Mixing (2) */
+        [60] = { 0x00CC, 0x00CC, 0x0000 }, /* R60    - DC Servo 0 */
+        [61] = { 0x00DD, 0x00DD, 0x0000 }, /* R61    - DC Servo 1 */
+        [64] = { 0x3F80, 0x3F80, 0x0000 }, /* R64    - DC Servo 4 */
+        [66] = { 0x0780, 0x0000, 0xFFFF }, /* R66    - DC Servo 6 */
+        [68] = { 0x0007, 0x0007, 0x0000 }, /* R68    - Analogue PGA Bias */
+        [69] = { 0x00FF, 0x00FF, 0x0000 }, /* R69    - Analogue HP 0 */
+        [71] = { 0x01FF, 0x01FF, 0x0000 }, /* R71    - Analogue HP 2 */
+        [72] = { 0x0001, 0x0001, 0x0000 }, /* R72    - Charge Pump 1 */
+        [82] = { 0x0001, 0x0001, 0x0000 }, /* R82    - Charge Pump B */
+        [87] = { 0x00A0, 0x00A0, 0x0000 }, /* R87    - Write Sequencer Control 1 */
+        [90] = { 0x007F, 0x01FF, 0x0000 }, /* R90    - Write Sequencer Control 2 */
+        [93] = { 0x03F9, 0x0000, 0x0000 }, /* R93    - Write Sequencer Control 3 */
+        [94] = { 0x0070, 0x0070, 0x0000 }, /* R94    - Control Interface */
+        [99] = { 0x000F, 0x000F, 0x0000 }, /* R99    - Mixer Enables */
+        [100] = { 0x00BF, 0x00BF, 0x0000 }, /* R100   - Headphone Mixer (1) */
+        [101] = { 0x00BF, 0x00BF, 0x0000 }, /* R101   - Headphone Mixer (2) */
+        [102] = { 0x01FF, 0x01FF, 0x0000 }, /* R102   - Headphone Mixer (3) */
+        [103] = { 0x01FF, 0x01FF, 0x0000 }, /* R103   - Headphone Mixer (4) */
+        [105] = { 0x00BF, 0x00BF, 0x0000 }, /* R105   - Speaker Mixer (1) */
+        [106] = { 0x00BF, 0x00BF, 0x0000 }, /* R106   - Speaker Mixer (2) */
+        [107] = { 0x01FF, 0x01FF, 0x0000 }, /* R107   - Speaker Mixer (3) */
+        [108] = { 0x01FF, 0x01FF, 0x0000 }, /* R108   - Speaker Mixer (4) */
+        [109] = { 0x00F0, 0x00F0, 0x0000 }, /* R109   - Speaker Mixer (5) */
+        [110] = { 0x00F7, 0x00F7, 0x0000 }, /* R110   - Beep Generator (1) */
+        [115] = { 0x001F, 0x001F, 0x0000 }, /* R115   - Oscillator Trim (3) */
+        [116] = { 0x001F, 0x001F, 0x0000 }, /* R116   - Oscillator Trim (4) */
+        [119] = { 0x00FF, 0x00FF, 0x0000 }, /* R119   - Oscillator Trim (7) */
+        [124] = { 0x0079, 0x0079, 0x0000 }, /* R124   - Analogue Clocking1 */
+        [125] = { 0x00DF, 0x00DF, 0x0000 }, /* R125   - Analogue Clocking2 */
+        [126] = { 0x000D, 0x000D, 0x0000 }, /* R126   - Analogue Clocking3 */
+        [127] = { 0x0000, 0xFFFF, 0x0000 }, /* R127   - PLL Software Reset */
+        [129] = { 0x00B0, 0x00B0, 0x0000 }, /* R129   - PLL2 */
+        [131] = { 0x0003, 0x0003, 0x0000 }, /* R131   - PLL 4 */
+        [136] = { 0x005F, 0x005F, 0x0000 }, /* R136   - PLL 9 */
+        [137] = { 0x00FF, 0x00FF, 0x0000 }, /* R137   - PLL 10 */
+        [138] = { 0x00FF, 0x00FF, 0x0000 }, /* R138   - PLL 11 */
+        [139] = { 0x00FF, 0x00FF, 0x0000 }, /* R139   - PLL 12 */
+        [140] = { 0x005F, 0x005F, 0x0000 }, /* R140   - PLL 13 */
+        [141] = { 0x00FF, 0x00FF, 0x0000 }, /* R141   - PLL 14 */
+        [142] = { 0x00FF, 0x00FF, 0x0000 }, /* R142   - PLL 15 */
+        [143] = { 0x00FF, 0x00FF, 0x0000 }, /* R143   - PLL 16 */
+        [155] = { 0x0067, 0x0067, 0x0000 }, /* R155   - FLL Control (1) */
+        [156] = { 0x01FB, 0x01FB, 0x0000 }, /* R156   - FLL Control (2) */
+        [157] = { 0x0007, 0x0007, 0x0000 }, /* R157   - FLL Control (3) */
+        [159] = { 0x007F, 0x007F, 0x0000 }, /* R159   - FLL Control (5) */
+        [160] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R160   - FLL Control (6) */
+        [161] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R161   - FLL Control (7) */
+        [162] = { 0x03FF, 0x03FF, 0x0000 }, /* R162   - FLL Control (8) */
+        [252] = { 0x0005, 0x0005, 0x0000 }, /* R252   - General test 1 */
+        [256] = { 0x000F, 0x000F, 0x0000 }, /* R256   - DF1 */
+        [257] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R257   - DF2 */
+        [258] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R258   - DF3 */
+        [259] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R259   - DF4 */
+        [260] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R260   - DF5 */
+        [261] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R261   - DF6 */
+        [262] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R262   - DF7 */
+        [264] = { 0x0003, 0x0003, 0x0000 }, /* R264   - LHPF1 */
+        [265] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R265   - LHPF2 */
+        [268] = { 0x0077, 0x0077, 0x0000 }, /* R268   - THREED1 */
+        [269] = { 0xFFFC, 0xFFFC, 0x0000 }, /* R269   - THREED2 */
+        [270] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R270   - THREED3 */
+        [271] = { 0xFFFC, 0xFFFC, 0x0000 }, /* R271   - THREED4 */
+        [276] = { 0x7FFF, 0x7FFF, 0x0000 }, /* R276   - DRC 1 */
+        [277] = { 0x1FFF, 0x1FFF, 0x0000 }, /* R277   - DRC 2 */
+        [278] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R278   - DRC 3 */
+        [279] = { 0x07FF, 0x07FF, 0x0000 }, /* R279   - DRC 4 */
+        [280] = { 0x03FF, 0x03FF, 0x0000 }, /* R280   - DRC 5 */
+        [285] = { 0x0003, 0x0003, 0x0000 }, /* R285   - Tloopback */
+        [335] = { 0x0007, 0x0007, 0x0000 }, /* R335   - EQ1 */
+        [336] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R336   - EQ2 */
+        [337] = { 0xFFC0, 0xFFC0, 0x0000 }, /* R337   - EQ3 */
+        [338] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R338   - EQ4 */
+        [339] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R339   - EQ5 */
+        [340] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R340   - EQ6 */
+        [341] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R341   - EQ7 */
+        [342] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R342   - EQ8 */
+        [343] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R343   - EQ9 */
+        [344] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R344   - EQ10 */
+        [345] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R345   - EQ11 */
+        [346] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R346   - EQ12 */
+        [347] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R347   - EQ13 */
+        [348] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R348   - EQ14 */
+        [349] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R349   - EQ15 */
+        [350] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R350   - EQ16 */
+        [351] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R351   - EQ17 */
+        [352] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R352   - EQ18 */
+        [353] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R353   - EQ19 */
+        [354] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R354   - EQ20 */
+        [355] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R355   - EQ21 */
+        [356] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R356   - EQ22 */
+        [357] = { 0xFFC0, 0xFFC0, 0x0000 }, /* R357   - EQ23 */
+        [358] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R358   - EQ24 */
+        [359] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R359   - EQ25 */
+        [360] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R360   - EQ26 */
+        [361] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R361   - EQ27 */
+        [362] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R362   - EQ28 */
+        [363] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R363   - EQ29 */
+        [364] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R364   - EQ30 */
+        [365] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R365   - EQ31 */
+        [366] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R366   - EQ32 */
+        [367] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R367   - EQ33 */
+        [368] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R368   - EQ34 */
+        [369] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R369   - EQ35 */
+        [370] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R370   - EQ36 */
+        [371] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R371   - EQ37 */
+        [372] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R372   - EQ38 */
+        [373] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R373   - EQ39 */
+        [374] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R374   - EQ40 */
+        [375] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R375   - EQ41 */
+        [513] = { 0x045F, 0x045F, 0x0000 }, /* R513   - GPIO 2 */
+        [514] = { 0x045F, 0x045F, 0x0000 }, /* R514   - GPIO 3 */
+        [516] = { 0xE75F, 0xE75F, 0x0000 }, /* R516   - GPIO 5 */
+        [517] = { 0xE75F, 0xE75F, 0x0000 }, /* R517   - GPIO 6 */
+        [560] = { 0x0030, 0x0030, 0xFFFF }, /* R560   - Interrupt Status 1 */
+        [561] = { 0xFFED, 0xFFED, 0xFFFF }, /* R561   - Interrupt Status 2 */
+        [568] = { 0x0030, 0x0030, 0x0000 }, /* R568   - Interrupt Status 1 Mask */
+        [569] = { 0xFFED, 0xFFED, 0x0000 }, /* R569   - Interrupt Status 2 Mask */
+        [576] = { 0x0001, 0x0001, 0x0000 }, /* R576   - Interrupt Control */
+        [584] = { 0x002D, 0x002D, 0x0000 }, /* R584   - IRQ Debounce */
+        [586] = { 0xC000, 0xC000, 0x0000 }, /* R586   -  MICINT Source Pol */
+        [768] = { 0x0001, 0x0001, 0x0000 }, /* R768   - DSP2 Power Management */
+        [1037] = { 0x0000, 0x003F, 0x0000 }, /* R1037  - DSP2_ExecControl */
+        [4096] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4096  - Write Sequencer 0 */
+        [4097] = { 0x00FF, 0x00FF, 0x0000 }, /* R4097  - Write Sequencer 1 */
+        [4098] = { 0x070F, 0x070F, 0x0000 }, /* R4098  - Write Sequencer 2 */
+        [4099] = { 0x010F, 0x010F, 0x0000 }, /* R4099  - Write Sequencer 3 */
+        [4100] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4100  - Write Sequencer 4 */
+        [4101] = { 0x00FF, 0x00FF, 0x0000 }, /* R4101  - Write Sequencer 5 */
+        [4102] = { 0x070F, 0x070F, 0x0000 }, /* R4102  - Write Sequencer 6 */
+        [4103] = { 0x010F, 0x010F, 0x0000 }, /* R4103  - Write Sequencer 7 */
+        [4104] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4104  - Write Sequencer 8 */
+        [4105] = { 0x00FF, 0x00FF, 0x0000 }, /* R4105  - Write Sequencer 9 */
+        [4106] = { 0x070F, 0x070F, 0x0000 }, /* R4106  - Write Sequencer 10 */
+        [4107] = { 0x010F, 0x010F, 0x0000 }, /* R4107  - Write Sequencer 11 */
+        [4108] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4108  - Write Sequencer 12 */
+        [4109] = { 0x00FF, 0x00FF, 0x0000 }, /* R4109  - Write Sequencer 13 */
+        [4110] = { 0x070F, 0x070F, 0x0000 }, /* R4110  - Write Sequencer 14 */
+        [4111] = { 0x010F, 0x010F, 0x0000 }, /* R4111  - Write Sequencer 15 */
+        [4112] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4112  - Write Sequencer 16 */
+        [4113] = { 0x00FF, 0x00FF, 0x0000 }, /* R4113  - Write Sequencer 17 */
+        [4114] = { 0x070F, 0x070F, 0x0000 }, /* R4114  - Write Sequencer 18 */
+        [4115] = { 0x010F, 0x010F, 0x0000 }, /* R4115  - Write Sequencer 19 */
+        [4116] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4116  - Write Sequencer 20 */
+        [4117] = { 0x00FF, 0x00FF, 0x0000 }, /* R4117  - Write Sequencer 21 */
+        [4118] = { 0x070F, 0x070F, 0x0000 }, /* R4118  - Write Sequencer 22 */
+        [4119] = { 0x010F, 0x010F, 0x0000 }, /* R4119  - Write Sequencer 23 */
+        [4120] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4120  - Write Sequencer 24 */
+        [4121] = { 0x00FF, 0x00FF, 0x0000 }, /* R4121  - Write Sequencer 25 */
+        [4122] = { 0x070F, 0x070F, 0x0000 }, /* R4122  - Write Sequencer 26 */
+        [4123] = { 0x010F, 0x010F, 0x0000 }, /* R4123  - Write Sequencer 27 */
+        [4124] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4124  - Write Sequencer 28 */
+        [4125] = { 0x00FF, 0x00FF, 0x0000 }, /* R4125  - Write Sequencer 29 */
+        [4126] = { 0x070F, 0x070F, 0x0000 }, /* R4126  - Write Sequencer 30 */
+        [4127] = { 0x010F, 0x010F, 0x0000 }, /* R4127  - Write Sequencer 31 */
+        [4128] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4128  - Write Sequencer 32 */
+        [4129] = { 0x00FF, 0x00FF, 0x0000 }, /* R4129  - Write Sequencer 33 */
+        [4130] = { 0x070F, 0x070F, 0x0000 }, /* R4130  - Write Sequencer 34 */
+        [4131] = { 0x010F, 0x010F, 0x0000 }, /* R4131  - Write Sequencer 35 */
+        [4132] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4132  - Write Sequencer 36 */
+        [4133] = { 0x00FF, 0x00FF, 0x0000 }, /* R4133  - Write Sequencer 37 */
+        [4134] = { 0x070F, 0x070F, 0x0000 }, /* R4134  - Write Sequencer 38 */
+        [4135] = { 0x010F, 0x010F, 0x0000 }, /* R4135  - Write Sequencer 39 */
+        [4136] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4136  - Write Sequencer 40 */
+        [4137] = { 0x00FF, 0x00FF, 0x0000 }, /* R4137  - Write Sequencer 41 */
+        [4138] = { 0x070F, 0x070F, 0x0000 }, /* R4138  - Write Sequencer 42 */
+        [4139] = { 0x010F, 0x010F, 0x0000 }, /* R4139  - Write Sequencer 43 */
+        [4140] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4140  - Write Sequencer 44 */
+        [4141] = { 0x00FF, 0x00FF, 0x0000 }, /* R4141  - Write Sequencer 45 */
+        [4142] = { 0x070F, 0x070F, 0x0000 }, /* R4142  - Write Sequencer 46 */
+        [4143] = { 0x010F, 0x010F, 0x0000 }, /* R4143  - Write Sequencer 47 */
+        [4144] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4144  - Write Sequencer 48 */
+        [4145] = { 0x00FF, 0x00FF, 0x0000 }, /* R4145  - Write Sequencer 49 */
+        [4146] = { 0x070F, 0x070F, 0x0000 }, /* R4146  - Write Sequencer 50 */
+        [4147] = { 0x010F, 0x010F, 0x0000 }, /* R4147  - Write Sequencer 51 */
+        [4148] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4148  - Write Sequencer 52 */
+        [4149] = { 0x00FF, 0x00FF, 0x0000 }, /* R4149  - Write Sequencer 53 */
+        [4150] = { 0x070F, 0x070F, 0x0000 }, /* R4150  - Write Sequencer 54 */
+        [4151] = { 0x010F, 0x010F, 0x0000 }, /* R4151  - Write Sequencer 55 */
+        [4152] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4152  - Write Sequencer 56 */
+        [4153] = { 0x00FF, 0x00FF, 0x0000 }, /* R4153  - Write Sequencer 57 */
+        [4154] = { 0x070F, 0x070F, 0x0000 }, /* R4154  - Write Sequencer 58 */
+        [4155] = { 0x010F, 0x010F, 0x0000 }, /* R4155  - Write Sequencer 59 */
+        [4156] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4156  - Write Sequencer 60 */
+        [4157] = { 0x00FF, 0x00FF, 0x0000 }, /* R4157  - Write Sequencer 61 */
+        [4158] = { 0x070F, 0x070F, 0x0000 }, /* R4158  - Write Sequencer 62 */
+        [4159] = { 0x010F, 0x010F, 0x0000 }, /* R4159  - Write Sequencer 63 */
+        [4160] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4160  - Write Sequencer 64 */
+        [4161] = { 0x00FF, 0x00FF, 0x0000 }, /* R4161  - Write Sequencer 65 */
+        [4162] = { 0x070F, 0x070F, 0x0000 }, /* R4162  - Write Sequencer 66 */
+        [4163] = { 0x010F, 0x010F, 0x0000 }, /* R4163  - Write Sequencer 67 */
+        [4164] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4164  - Write Sequencer 68 */
+        [4165] = { 0x00FF, 0x00FF, 0x0000 }, /* R4165  - Write Sequencer 69 */
+        [4166] = { 0x070F, 0x070F, 0x0000 }, /* R4166  - Write Sequencer 70 */
+        [4167] = { 0x010F, 0x010F, 0x0000 }, /* R4167  - Write Sequencer 71 */
+        [4168] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4168  - Write Sequencer 72 */
+        [4169] = { 0x00FF, 0x00FF, 0x0000 }, /* R4169  - Write Sequencer 73 */
+        [4170] = { 0x070F, 0x070F, 0x0000 }, /* R4170  - Write Sequencer 74 */
+        [4171] = { 0x010F, 0x010F, 0x0000 }, /* R4171  - Write Sequencer 75 */
+        [4172] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4172  - Write Sequencer 76 */
+        [4173] = { 0x00FF, 0x00FF, 0x0000 }, /* R4173  - Write Sequencer 77 */
+        [4174] = { 0x070F, 0x070F, 0x0000 }, /* R4174  - Write Sequencer 78 */
+        [4175] = { 0x010F, 0x010F, 0x0000 }, /* R4175  - Write Sequencer 79 */
+        [4176] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4176  - Write Sequencer 80 */
+        [4177] = { 0x00FF, 0x00FF, 0x0000 }, /* R4177  - Write Sequencer 81 */
+        [4178] = { 0x070F, 0x070F, 0x0000 }, /* R4178  - Write Sequencer 82 */
+        [4179] = { 0x010F, 0x010F, 0x0000 }, /* R4179  - Write Sequencer 83 */
+        [4180] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4180  - Write Sequencer 84 */
+        [4181] = { 0x00FF, 0x00FF, 0x0000 }, /* R4181  - Write Sequencer 85 */
+        [4182] = { 0x070F, 0x070F, 0x0000 }, /* R4182  - Write Sequencer 86 */
+        [4183] = { 0x010F, 0x010F, 0x0000 }, /* R4183  - Write Sequencer 87 */
+        [4184] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4184  - Write Sequencer 88 */
+        [4185] = { 0x00FF, 0x00FF, 0x0000 }, /* R4185  - Write Sequencer 89 */
+        [4186] = { 0x070F, 0x070F, 0x0000 }, /* R4186  - Write Sequencer 90 */
+        [4187] = { 0x010F, 0x010F, 0x0000 }, /* R4187  - Write Sequencer 91 */
+        [4188] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4188  - Write Sequencer 92 */
+        [4189] = { 0x00FF, 0x00FF, 0x0000 }, /* R4189  - Write Sequencer 93 */
+        [4190] = { 0x070F, 0x070F, 0x0000 }, /* R4190  - Write Sequencer 94 */
+        [4191] = { 0x010F, 0x010F, 0x0000 }, /* R4191  - Write Sequencer 95 */
+        [4192] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4192  - Write Sequencer 96 */
+        [4193] = { 0x00FF, 0x00FF, 0x0000 }, /* R4193  - Write Sequencer 97 */
+        [4194] = { 0x070F, 0x070F, 0x0000 }, /* R4194  - Write Sequencer 98 */
+        [4195] = { 0x010F, 0x010F, 0x0000 }, /* R4195  - Write Sequencer 99 */
+        [4196] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4196  - Write Sequencer 100 */
+        [4197] = { 0x00FF, 0x00FF, 0x0000 }, /* R4197  - Write Sequencer 101 */
+        [4198] = { 0x070F, 0x070F, 0x0000 }, /* R4198  - Write Sequencer 102 */
+        [4199] = { 0x010F, 0x010F, 0x0000 }, /* R4199  - Write Sequencer 103 */
+        [4200] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4200  - Write Sequencer 104 */
+        [4201] = { 0x00FF, 0x00FF, 0x0000 }, /* R4201  - Write Sequencer 105 */
+        [4202] = { 0x070F, 0x070F, 0x0000 }, /* R4202  - Write Sequencer 106 */
+        [4203] = { 0x010F, 0x010F, 0x0000 }, /* R4203  - Write Sequencer 107 */
+        [4204] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4204  - Write Sequencer 108 */
+        [4205] = { 0x00FF, 0x00FF, 0x0000 }, /* R4205  - Write Sequencer 109 */
+        [4206] = { 0x070F, 0x070F, 0x0000 }, /* R4206  - Write Sequencer 110 */
+        [4207] = { 0x010F, 0x010F, 0x0000 }, /* R4207  - Write Sequencer 111 */
+        [4208] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4208  - Write Sequencer 112 */
+        [4209] = { 0x00FF, 0x00FF, 0x0000 }, /* R4209  - Write Sequencer 113 */
+        [4210] = { 0x070F, 0x070F, 0x0000 }, /* R4210  - Write Sequencer 114 */
+        [4211] = { 0x010F, 0x010F, 0x0000 }, /* R4211  - Write Sequencer 115 */
+        [4212] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4212  - Write Sequencer 116 */
+        [4213] = { 0x00FF, 0x00FF, 0x0000 }, /* R4213  - Write Sequencer 117 */
+        [4214] = { 0x070F, 0x070F, 0x0000 }, /* R4214  - Write Sequencer 118 */
+        [4215] = { 0x010F, 0x010F, 0x0000 }, /* R4215  - Write Sequencer 119 */
+        [4216] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4216  - Write Sequencer 120 */
+        [4217] = { 0x00FF, 0x00FF, 0x0000 }, /* R4217  - Write Sequencer 121 */
+        [4218] = { 0x070F, 0x070F, 0x0000 }, /* R4218  - Write Sequencer 122 */
+        [4219] = { 0x010F, 0x010F, 0x0000 }, /* R4219  - Write Sequencer 123 */
+        [4220] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4220  - Write Sequencer 124 */
+        [4221] = { 0x00FF, 0x00FF, 0x0000 }, /* R4221  - Write Sequencer 125 */
+        [4222] = { 0x070F, 0x070F, 0x0000 }, /* R4222  - Write Sequencer 126 */
+        [4223] = { 0x010F, 0x010F, 0x0000 }, /* R4223  - Write Sequencer 127 */
+        [4224] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4224  - Write Sequencer 128 */
+        [4225] = { 0x00FF, 0x00FF, 0x0000 }, /* R4225  - Write Sequencer 129 */
+        [4226] = { 0x070F, 0x070F, 0x0000 }, /* R4226  - Write Sequencer 130 */
+        [4227] = { 0x010F, 0x010F, 0x0000 }, /* R4227  - Write Sequencer 131 */
+        [4228] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4228  - Write Sequencer 132 */
+        [4229] = { 0x00FF, 0x00FF, 0x0000 }, /* R4229  - Write Sequencer 133 */
+        [4230] = { 0x070F, 0x070F, 0x0000 }, /* R4230  - Write Sequencer 134 */
+        [4231] = { 0x010F, 0x010F, 0x0000 }, /* R4231  - Write Sequencer 135 */
+        [4232] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4232  - Write Sequencer 136 */
+        [4233] = { 0x00FF, 0x00FF, 0x0000 }, /* R4233  - Write Sequencer 137 */
+        [4234] = { 0x070F, 0x070F, 0x0000 }, /* R4234  - Write Sequencer 138 */
+        [4235] = { 0x010F, 0x010F, 0x0000 }, /* R4235  - Write Sequencer 139 */
+        [4236] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4236  - Write Sequencer 140 */
+        [4237] = { 0x00FF, 0x00FF, 0x0000 }, /* R4237  - Write Sequencer 141 */
+        [4238] = { 0x070F, 0x070F, 0x0000 }, /* R4238  - Write Sequencer 142 */
+        [4239] = { 0x010F, 0x010F, 0x0000 }, /* R4239  - Write Sequencer 143 */
+        [4240] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4240  - Write Sequencer 144 */
+        [4241] = { 0x00FF, 0x00FF, 0x0000 }, /* R4241  - Write Sequencer 145 */
+        [4242] = { 0x070F, 0x070F, 0x0000 }, /* R4242  - Write Sequencer 146 */
+        [4243] = { 0x010F, 0x010F, 0x0000 }, /* R4243  - Write Sequencer 147 */
+        [4244] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4244  - Write Sequencer 148 */
+        [4245] = { 0x00FF, 0x00FF, 0x0000 }, /* R4245  - Write Sequencer 149 */
+        [4246] = { 0x070F, 0x070F, 0x0000 }, /* R4246  - Write Sequencer 150 */
+        [4247] = { 0x010F, 0x010F, 0x0000 }, /* R4247  - Write Sequencer 151 */
+        [4248] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4248  - Write Sequencer 152 */
+        [4249] = { 0x00FF, 0x00FF, 0x0000 }, /* R4249  - Write Sequencer 153 */
+        [4250] = { 0x070F, 0x070F, 0x0000 }, /* R4250  - Write Sequencer 154 */
+        [4251] = { 0x010F, 0x010F, 0x0000 }, /* R4251  - Write Sequencer 155 */
+        [4252] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4252  - Write Sequencer 156 */
+        [4253] = { 0x00FF, 0x00FF, 0x0000 }, /* R4253  - Write Sequencer 157 */
+        [4254] = { 0x070F, 0x070F, 0x0000 }, /* R4254  - Write Sequencer 158 */
+        [4255] = { 0x010F, 0x010F, 0x0000 }, /* R4255  - Write Sequencer 159 */
+        [4256] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4256  - Write Sequencer 160 */
+        [4257] = { 0x00FF, 0x00FF, 0x0000 }, /* R4257  - Write Sequencer 161 */
+        [4258] = { 0x070F, 0x070F, 0x0000 }, /* R4258  - Write Sequencer 162 */
+        [4259] = { 0x010F, 0x010F, 0x0000 }, /* R4259  - Write Sequencer 163 */
+        [4260] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4260  - Write Sequencer 164 */
+        [4261] = { 0x00FF, 0x00FF, 0x0000 }, /* R4261  - Write Sequencer 165 */
+        [4262] = { 0x070F, 0x070F, 0x0000 }, /* R4262  - Write Sequencer 166 */
+        [4263] = { 0x010F, 0x010F, 0x0000 }, /* R4263  - Write Sequencer 167 */
+        [4264] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4264  - Write Sequencer 168 */
+        [4265] = { 0x00FF, 0x00FF, 0x0000 }, /* R4265  - Write Sequencer 169 */
+        [4266] = { 0x070F, 0x070F, 0x0000 }, /* R4266  - Write Sequencer 170 */
+        [4267] = { 0x010F, 0x010F, 0x0000 }, /* R4267  - Write Sequencer 171 */
+        [4268] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4268  - Write Sequencer 172 */
+        [4269] = { 0x00FF, 0x00FF, 0x0000 }, /* R4269  - Write Sequencer 173 */
+        [4270] = { 0x070F, 0x070F, 0x0000 }, /* R4270  - Write Sequencer 174 */
+        [4271] = { 0x010F, 0x010F, 0x0000 }, /* R4271  - Write Sequencer 175 */
+        [4272] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4272  - Write Sequencer 176 */
+        [4273] = { 0x00FF, 0x00FF, 0x0000 }, /* R4273  - Write Sequencer 177 */
+        [4274] = { 0x070F, 0x070F, 0x0000 }, /* R4274  - Write Sequencer 178 */
+        [4275] = { 0x010F, 0x010F, 0x0000 }, /* R4275  - Write Sequencer 179 */
+        [4276] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4276  - Write Sequencer 180 */
+        [4277] = { 0x00FF, 0x00FF, 0x0000 }, /* R4277  - Write Sequencer 181 */
+        [4278] = { 0x070F, 0x070F, 0x0000 }, /* R4278  - Write Sequencer 182 */
+        [4279] = { 0x010F, 0x010F, 0x0000 }, /* R4279  - Write Sequencer 183 */
+        [4280] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4280  - Write Sequencer 184 */
+        [4281] = { 0x00FF, 0x00FF, 0x0000 }, /* R4281  - Write Sequencer 185 */
+        [4282] = { 0x070F, 0x070F, 0x0000 }, /* R4282  - Write Sequencer 186 */
+        [4283] = { 0x010F, 0x010F, 0x0000 }, /* R4283  - Write Sequencer 187 */
+        [4284] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4284  - Write Sequencer 188 */
+        [4285] = { 0x00FF, 0x00FF, 0x0000 }, /* R4285  - Write Sequencer 189 */
+        [4286] = { 0x070F, 0x070F, 0x0000 }, /* R4286  - Write Sequencer 190 */
+        [4287] = { 0x010F, 0x010F, 0x0000 }, /* R4287  - Write Sequencer 191 */
+        [4288] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4288  - Write Sequencer 192 */
+        [4289] = { 0x00FF, 0x00FF, 0x0000 }, /* R4289  - Write Sequencer 193 */
+        [4290] = { 0x070F, 0x070F, 0x0000 }, /* R4290  - Write Sequencer 194 */
+        [4291] = { 0x010F, 0x010F, 0x0000 }, /* R4291  - Write Sequencer 195 */
+        [4292] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4292  - Write Sequencer 196 */
+        [4293] = { 0x00FF, 0x00FF, 0x0000 }, /* R4293  - Write Sequencer 197 */
+        [4294] = { 0x070F, 0x070F, 0x0000 }, /* R4294  - Write Sequencer 198 */
+        [4295] = { 0x010F, 0x010F, 0x0000 }, /* R4295  - Write Sequencer 199 */
+        [4296] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4296  - Write Sequencer 200 */
+        [4297] = { 0x00FF, 0x00FF, 0x0000 }, /* R4297  - Write Sequencer 201 */
+        [4298] = { 0x070F, 0x070F, 0x0000 }, /* R4298  - Write Sequencer 202 */
+        [4299] = { 0x010F, 0x010F, 0x0000 }, /* R4299  - Write Sequencer 203 */
+        [4300] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4300  - Write Sequencer 204 */
+        [4301] = { 0x00FF, 0x00FF, 0x0000 }, /* R4301  - Write Sequencer 205 */
+        [4302] = { 0x070F, 0x070F, 0x0000 }, /* R4302  - Write Sequencer 206 */
+        [4303] = { 0x010F, 0x010F, 0x0000 }, /* R4303  - Write Sequencer 207 */
+        [4304] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4304  - Write Sequencer 208 */
+        [4305] = { 0x00FF, 0x00FF, 0x0000 }, /* R4305  - Write Sequencer 209 */
+        [4306] = { 0x070F, 0x070F, 0x0000 }, /* R4306  - Write Sequencer 210 */
+        [4307] = { 0x010F, 0x010F, 0x0000 }, /* R4307  - Write Sequencer 211 */
+        [4308] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4308  - Write Sequencer 212 */
+        [4309] = { 0x00FF, 0x00FF, 0x0000 }, /* R4309  - Write Sequencer 213 */
+        [4310] = { 0x070F, 0x070F, 0x0000 }, /* R4310  - Write Sequencer 214 */
+        [4311] = { 0x010F, 0x010F, 0x0000 }, /* R4311  - Write Sequencer 215 */
+        [4312] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4312  - Write Sequencer 216 */
+        [4313] = { 0x00FF, 0x00FF, 0x0000 }, /* R4313  - Write Sequencer 217 */
+        [4314] = { 0x070F, 0x070F, 0x0000 }, /* R4314  - Write Sequencer 218 */
+        [4315] = { 0x010F, 0x010F, 0x0000 }, /* R4315  - Write Sequencer 219 */
+        [4316] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4316  - Write Sequencer 220 */
+        [4317] = { 0x00FF, 0x00FF, 0x0000 }, /* R4317  - Write Sequencer 221 */
+        [4318] = { 0x070F, 0x070F, 0x0000 }, /* R4318  - Write Sequencer 222 */
+        [4319] = { 0x010F, 0x010F, 0x0000 }, /* R4319  - Write Sequencer 223 */
+        [4320] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4320  - Write Sequencer 224 */
+        [4321] = { 0x00FF, 0x00FF, 0x0000 }, /* R4321  - Write Sequencer 225 */
+        [4322] = { 0x070F, 0x070F, 0x0000 }, /* R4322  - Write Sequencer 226 */
+        [4323] = { 0x010F, 0x010F, 0x0000 }, /* R4323  - Write Sequencer 227 */
+        [4324] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4324  - Write Sequencer 228 */
+        [4325] = { 0x00FF, 0x00FF, 0x0000 }, /* R4325  - Write Sequencer 229 */
+        [4326] = { 0x070F, 0x070F, 0x0000 }, /* R4326  - Write Sequencer 230 */
+        [4327] = { 0x010F, 0x010F, 0x0000 }, /* R4327  - Write Sequencer 231 */
+        [4328] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4328  - Write Sequencer 232 */
+        [4329] = { 0x00FF, 0x00FF, 0x0000 }, /* R4329  - Write Sequencer 233 */
+        [4330] = { 0x070F, 0x070F, 0x0000 }, /* R4330  - Write Sequencer 234 */
+        [4331] = { 0x010F, 0x010F, 0x0000 }, /* R4331  - Write Sequencer 235 */
+        [4332] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4332  - Write Sequencer 236 */
+        [4333] = { 0x00FF, 0x00FF, 0x0000 }, /* R4333  - Write Sequencer 237 */
+        [4334] = { 0x070F, 0x070F, 0x0000 }, /* R4334  - Write Sequencer 238 */
+        [4335] = { 0x010F, 0x010F, 0x0000 }, /* R4335  - Write Sequencer 239 */
+        [4336] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4336  - Write Sequencer 240 */
+        [4337] = { 0x00FF, 0x00FF, 0x0000 }, /* R4337  - Write Sequencer 241 */
+        [4338] = { 0x070F, 0x070F, 0x0000 }, /* R4338  - Write Sequencer 242 */
+        [4339] = { 0x010F, 0x010F, 0x0000 }, /* R4339  - Write Sequencer 243 */
+        [4340] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4340  - Write Sequencer 244 */
+        [4341] = { 0x00FF, 0x00FF, 0x0000 }, /* R4341  - Write Sequencer 245 */
+        [4342] = { 0x070F, 0x070F, 0x0000 }, /* R4342  - Write Sequencer 246 */
+        [4343] = { 0x010F, 0x010F, 0x0000 }, /* R4343  - Write Sequencer 247 */
+        [4344] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4344  - Write Sequencer 248 */
+        [4345] = { 0x00FF, 0x00FF, 0x0000 }, /* R4345  - Write Sequencer 249 */
+        [4346] = { 0x070F, 0x070F, 0x0000 }, /* R4346  - Write Sequencer 250 */
+        [4347] = { 0x010F, 0x010F, 0x0000 }, /* R4347  - Write Sequencer 251 */
+        [4348] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4348  - Write Sequencer 252 */
+        [4349] = { 0x00FF, 0x00FF, 0x0000 }, /* R4349  - Write Sequencer 253 */
+        [4350] = { 0x070F, 0x070F, 0x0000 }, /* R4350  - Write Sequencer 254 */
+        [4351] = { 0x010F, 0x010F, 0x0000 }, /* R4351  - Write Sequencer 255 */
+        [4352] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4352  - Write Sequencer 256 */
+        [4353] = { 0x00FF, 0x00FF, 0x0000 }, /* R4353  - Write Sequencer 257 */
+        [4354] = { 0x070F, 0x070F, 0x0000 }, /* R4354  - Write Sequencer 258 */
+        [4355] = { 0x010F, 0x010F, 0x0000 }, /* R4355  - Write Sequencer 259 */
+        [4356] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4356  - Write Sequencer 260 */
+        [4357] = { 0x00FF, 0x00FF, 0x0000 }, /* R4357  - Write Sequencer 261 */
+        [4358] = { 0x070F, 0x070F, 0x0000 }, /* R4358  - Write Sequencer 262 */
+        [4359] = { 0x010F, 0x010F, 0x0000 }, /* R4359  - Write Sequencer 263 */
+        [4360] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4360  - Write Sequencer 264 */
+        [4361] = { 0x00FF, 0x00FF, 0x0000 }, /* R4361  - Write Sequencer 265 */
+        [4362] = { 0x070F, 0x070F, 0x0000 }, /* R4362  - Write Sequencer 266 */
+        [4363] = { 0x010F, 0x010F, 0x0000 }, /* R4363  - Write Sequencer 267 */
+        [4364] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4364  - Write Sequencer 268 */
+        [4365] = { 0x00FF, 0x00FF, 0x0000 }, /* R4365  - Write Sequencer 269 */
+        [4366] = { 0x070F, 0x070F, 0x0000 }, /* R4366  - Write Sequencer 270 */
+        [4367] = { 0x010F, 0x010F, 0x0000 }, /* R4367  - Write Sequencer 271 */
+        [4368] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4368  - Write Sequencer 272 */
+        [4369] = { 0x00FF, 0x00FF, 0x0000 }, /* R4369  - Write Sequencer 273 */
+        [4370] = { 0x070F, 0x070F, 0x0000 }, /* R4370  - Write Sequencer 274 */
+        [4371] = { 0x010F, 0x010F, 0x0000 }, /* R4371  - Write Sequencer 275 */
+        [4372] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4372  - Write Sequencer 276 */
+        [4373] = { 0x00FF, 0x00FF, 0x0000 }, /* R4373  - Write Sequencer 277 */
+        [4374] = { 0x070F, 0x070F, 0x0000 }, /* R4374  - Write Sequencer 278 */
+        [4375] = { 0x010F, 0x010F, 0x0000 }, /* R4375  - Write Sequencer 279 */
+        [4376] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4376  - Write Sequencer 280 */
+        [4377] = { 0x00FF, 0x00FF, 0x0000 }, /* R4377  - Write Sequencer 281 */
+        [4378] = { 0x070F, 0x070F, 0x0000 }, /* R4378  - Write Sequencer 282 */
+        [4379] = { 0x010F, 0x010F, 0x0000 }, /* R4379  - Write Sequencer 283 */
+        [4380] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4380  - Write Sequencer 284 */
+        [4381] = { 0x00FF, 0x00FF, 0x0000 }, /* R4381  - Write Sequencer 285 */
+        [4382] = { 0x070F, 0x070F, 0x0000 }, /* R4382  - Write Sequencer 286 */
+        [4383] = { 0x010F, 0x010F, 0x0000 }, /* R4383  - Write Sequencer 287 */
+        [4384] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4384  - Write Sequencer 288 */
+        [4385] = { 0x00FF, 0x00FF, 0x0000 }, /* R4385  - Write Sequencer 289 */
+        [4386] = { 0x070F, 0x070F, 0x0000 }, /* R4386  - Write Sequencer 290 */
+        [4387] = { 0x010F, 0x010F, 0x0000 }, /* R4387  - Write Sequencer 291 */
+        [4388] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4388  - Write Sequencer 292 */
+        [4389] = { 0x00FF, 0x00FF, 0x0000 }, /* R4389  - Write Sequencer 293 */
+        [4390] = { 0x070F, 0x070F, 0x0000 }, /* R4390  - Write Sequencer 294 */
+        [4391] = { 0x010F, 0x010F, 0x0000 }, /* R4391  - Write Sequencer 295 */
+        [4392] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4392  - Write Sequencer 296 */
+        [4393] = { 0x00FF, 0x00FF, 0x0000 }, /* R4393  - Write Sequencer 297 */
+        [4394] = { 0x070F, 0x070F, 0x0000 }, /* R4394  - Write Sequencer 298 */
+        [4395] = { 0x010F, 0x010F, 0x0000 }, /* R4395  - Write Sequencer 299 */
+        [4396] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4396  - Write Sequencer 300 */
+        [4397] = { 0x00FF, 0x00FF, 0x0000 }, /* R4397  - Write Sequencer 301 */
+        [4398] = { 0x070F, 0x070F, 0x0000 }, /* R4398  - Write Sequencer 302 */
+        [4399] = { 0x010F, 0x010F, 0x0000 }, /* R4399  - Write Sequencer 303 */
+        [4400] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4400  - Write Sequencer 304 */
+        [4401] = { 0x00FF, 0x00FF, 0x0000 }, /* R4401  - Write Sequencer 305 */
+        [4402] = { 0x070F, 0x070F, 0x0000 }, /* R4402  - Write Sequencer 306 */
+        [4403] = { 0x010F, 0x010F, 0x0000 }, /* R4403  - Write Sequencer 307 */
+        [4404] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4404  - Write Sequencer 308 */
+        [4405] = { 0x00FF, 0x00FF, 0x0000 }, /* R4405  - Write Sequencer 309 */
+        [4406] = { 0x070F, 0x070F, 0x0000 }, /* R4406  - Write Sequencer 310 */
+        [4407] = { 0x010F, 0x010F, 0x0000 }, /* R4407  - Write Sequencer 311 */
+        [4408] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4408  - Write Sequencer 312 */
+        [4409] = { 0x00FF, 0x00FF, 0x0000 }, /* R4409  - Write Sequencer 313 */
+        [4410] = { 0x070F, 0x070F, 0x0000 }, /* R4410  - Write Sequencer 314 */
+        [4411] = { 0x010F, 0x010F, 0x0000 }, /* R4411  - Write Sequencer 315 */
+        [4412] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4412  - Write Sequencer 316 */
+        [4413] = { 0x00FF, 0x00FF, 0x0000 }, /* R4413  - Write Sequencer 317 */
+        [4414] = { 0x070F, 0x070F, 0x0000 }, /* R4414  - Write Sequencer 318 */
+        [4415] = { 0x010F, 0x010F, 0x0000 }, /* R4415  - Write Sequencer 319 */
+        [4416] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4416  - Write Sequencer 320 */
+        [4417] = { 0x00FF, 0x00FF, 0x0000 }, /* R4417  - Write Sequencer 321 */
+        [4418] = { 0x070F, 0x070F, 0x0000 }, /* R4418  - Write Sequencer 322 */
+        [4419] = { 0x010F, 0x010F, 0x0000 }, /* R4419  - Write Sequencer 323 */
+        [4420] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4420  - Write Sequencer 324 */
+        [4421] = { 0x00FF, 0x00FF, 0x0000 }, /* R4421  - Write Sequencer 325 */
+        [4422] = { 0x070F, 0x070F, 0x0000 }, /* R4422  - Write Sequencer 326 */
+        [4423] = { 0x010F, 0x010F, 0x0000 }, /* R4423  - Write Sequencer 327 */
+        [4424] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4424  - Write Sequencer 328 */
+        [4425] = { 0x00FF, 0x00FF, 0x0000 }, /* R4425  - Write Sequencer 329 */
+        [4426] = { 0x070F, 0x070F, 0x0000 }, /* R4426  - Write Sequencer 330 */
+        [4427] = { 0x010F, 0x010F, 0x0000 }, /* R4427  - Write Sequencer 331 */
+        [4428] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4428  - Write Sequencer 332 */
+        [4429] = { 0x00FF, 0x00FF, 0x0000 }, /* R4429  - Write Sequencer 333 */
+        [4430] = { 0x070F, 0x070F, 0x0000 }, /* R4430  - Write Sequencer 334 */
+        [4431] = { 0x010F, 0x010F, 0x0000 }, /* R4431  - Write Sequencer 335 */
+        [4432] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4432  - Write Sequencer 336 */
+        [4433] = { 0x00FF, 0x00FF, 0x0000 }, /* R4433  - Write Sequencer 337 */
+        [4434] = { 0x070F, 0x070F, 0x0000 }, /* R4434  - Write Sequencer 338 */
+        [4435] = { 0x010F, 0x010F, 0x0000 }, /* R4435  - Write Sequencer 339 */
+        [4436] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4436  - Write Sequencer 340 */
+        [4437] = { 0x00FF, 0x00FF, 0x0000 }, /* R4437  - Write Sequencer 341 */
+        [4438] = { 0x070F, 0x070F, 0x0000 }, /* R4438  - Write Sequencer 342 */
+        [4439] = { 0x010F, 0x010F, 0x0000 }, /* R4439  - Write Sequencer 343 */
+        [4440] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4440  - Write Sequencer 344 */
+        [4441] = { 0x00FF, 0x00FF, 0x0000 }, /* R4441  - Write Sequencer 345 */
+        [4442] = { 0x070F, 0x070F, 0x0000 }, /* R4442  - Write Sequencer 346 */
+        [4443] = { 0x010F, 0x010F, 0x0000 }, /* R4443  - Write Sequencer 347 */
+        [4444] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4444  - Write Sequencer 348 */
+        [4445] = { 0x00FF, 0x00FF, 0x0000 }, /* R4445  - Write Sequencer 349 */
+        [4446] = { 0x070F, 0x070F, 0x0000 }, /* R4446  - Write Sequencer 350 */
+        [4447] = { 0x010F, 0x010F, 0x0000 }, /* R4447  - Write Sequencer 351 */
+        [4448] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4448  - Write Sequencer 352 */
+        [4449] = { 0x00FF, 0x00FF, 0x0000 }, /* R4449  - Write Sequencer 353 */
+        [4450] = { 0x070F, 0x070F, 0x0000 }, /* R4450  - Write Sequencer 354 */
+        [4451] = { 0x010F, 0x010F, 0x0000 }, /* R4451  - Write Sequencer 355 */
+        [4452] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4452  - Write Sequencer 356 */
+        [4453] = { 0x00FF, 0x00FF, 0x0000 }, /* R4453  - Write Sequencer 357 */
+        [4454] = { 0x070F, 0x070F, 0x0000 }, /* R4454  - Write Sequencer 358 */
+        [4455] = { 0x010F, 0x010F, 0x0000 }, /* R4455  - Write Sequencer 359 */
+        [4456] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4456  - Write Sequencer 360 */
+        [4457] = { 0x00FF, 0x00FF, 0x0000 }, /* R4457  - Write Sequencer 361 */
+        [4458] = { 0x070F, 0x070F, 0x0000 }, /* R4458  - Write Sequencer 362 */
+        [4459] = { 0x010F, 0x010F, 0x0000 }, /* R4459  - Write Sequencer 363 */
+        [4460] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4460  - Write Sequencer 364 */
+        [4461] = { 0x00FF, 0x00FF, 0x0000 }, /* R4461  - Write Sequencer 365 */
+        [4462] = { 0x070F, 0x070F, 0x0000 }, /* R4462  - Write Sequencer 366 */
+        [4463] = { 0x010F, 0x010F, 0x0000 }, /* R4463  - Write Sequencer 367 */
+        [4464] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4464  - Write Sequencer 368 */
+        [4465] = { 0x00FF, 0x00FF, 0x0000 }, /* R4465  - Write Sequencer 369 */
+        [4466] = { 0x070F, 0x070F, 0x0000 }, /* R4466  - Write Sequencer 370 */
+        [4467] = { 0x010F, 0x010F, 0x0000 }, /* R4467  - Write Sequencer 371 */
+        [4468] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4468  - Write Sequencer 372 */
+        [4469] = { 0x00FF, 0x00FF, 0x0000 }, /* R4469  - Write Sequencer 373 */
+        [4470] = { 0x070F, 0x070F, 0x0000 }, /* R4470  - Write Sequencer 374 */
+        [4471] = { 0x010F, 0x010F, 0x0000 }, /* R4471  - Write Sequencer 375 */
+        [4472] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4472  - Write Sequencer 376 */
+        [4473] = { 0x00FF, 0x00FF, 0x0000 }, /* R4473  - Write Sequencer 377 */
+        [4474] = { 0x070F, 0x070F, 0x0000 }, /* R4474  - Write Sequencer 378 */
+        [4475] = { 0x010F, 0x010F, 0x0000 }, /* R4475  - Write Sequencer 379 */
+        [4476] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4476  - Write Sequencer 380 */
+        [4477] = { 0x00FF, 0x00FF, 0x0000 }, /* R4477  - Write Sequencer 381 */
+        [4478] = { 0x070F, 0x070F, 0x0000 }, /* R4478  - Write Sequencer 382 */
+        [4479] = { 0x010F, 0x010F, 0x0000 }, /* R4479  - Write Sequencer 383 */
+        [4480] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4480  - Write Sequencer 384 */
+        [4481] = { 0x00FF, 0x00FF, 0x0000 }, /* R4481  - Write Sequencer 385 */
+        [4482] = { 0x070F, 0x070F, 0x0000 }, /* R4482  - Write Sequencer 386 */
+        [4483] = { 0x010F, 0x010F, 0x0000 }, /* R4483  - Write Sequencer 387 */
+        [4484] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4484  - Write Sequencer 388 */
+        [4485] = { 0x00FF, 0x00FF, 0x0000 }, /* R4485  - Write Sequencer 389 */
+        [4486] = { 0x070F, 0x070F, 0x0000 }, /* R4486  - Write Sequencer 390 */
+        [4487] = { 0x010F, 0x010F, 0x0000 }, /* R4487  - Write Sequencer 391 */
+        [4488] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4488  - Write Sequencer 392 */
+        [4489] = { 0x00FF, 0x00FF, 0x0000 }, /* R4489  - Write Sequencer 393 */
+        [4490] = { 0x070F, 0x070F, 0x0000 }, /* R4490  - Write Sequencer 394 */
+        [4491] = { 0x010F, 0x010F, 0x0000 }, /* R4491  - Write Sequencer 395 */
+        [4492] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4492  - Write Sequencer 396 */
+        [4493] = { 0x00FF, 0x00FF, 0x0000 }, /* R4493  - Write Sequencer 397 */
+        [4494] = { 0x070F, 0x070F, 0x0000 }, /* R4494  - Write Sequencer 398 */
+        [4495] = { 0x010F, 0x010F, 0x0000 }, /* R4495  - Write Sequencer 399 */
+        [4496] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4496  - Write Sequencer 400 */
+        [4497] = { 0x00FF, 0x00FF, 0x0000 }, /* R4497  - Write Sequencer 401 */
+        [4498] = { 0x070F, 0x070F, 0x0000 }, /* R4498  - Write Sequencer 402 */
+        [4499] = { 0x010F, 0x010F, 0x0000 }, /* R4499  - Write Sequencer 403 */
+        [4500] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4500  - Write Sequencer 404 */
+        [4501] = { 0x00FF, 0x00FF, 0x0000 }, /* R4501  - Write Sequencer 405 */
+        [4502] = { 0x070F, 0x070F, 0x0000 }, /* R4502  - Write Sequencer 406 */
+        [4503] = { 0x010F, 0x010F, 0x0000 }, /* R4503  - Write Sequencer 407 */
+        [4504] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4504  - Write Sequencer 408 */
+        [4505] = { 0x00FF, 0x00FF, 0x0000 }, /* R4505  - Write Sequencer 409 */
+        [4506] = { 0x070F, 0x070F, 0x0000 }, /* R4506  - Write Sequencer 410 */
+        [4507] = { 0x010F, 0x010F, 0x0000 }, /* R4507  - Write Sequencer 411 */
+        [4508] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4508  - Write Sequencer 412 */
+        [4509] = { 0x00FF, 0x00FF, 0x0000 }, /* R4509  - Write Sequencer 413 */
+        [4510] = { 0x070F, 0x070F, 0x0000 }, /* R4510  - Write Sequencer 414 */
+        [4511] = { 0x010F, 0x010F, 0x0000 }, /* R4511  - Write Sequencer 415 */
+        [4512] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4512  - Write Sequencer 416 */
+        [4513] = { 0x00FF, 0x00FF, 0x0000 }, /* R4513  - Write Sequencer 417 */
+        [4514] = { 0x070F, 0x070F, 0x0000 }, /* R4514  - Write Sequencer 418 */
+        [4515] = { 0x010F, 0x010F, 0x0000 }, /* R4515  - Write Sequencer 419 */
+        [4516] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4516  - Write Sequencer 420 */
+        [4517] = { 0x00FF, 0x00FF, 0x0000 }, /* R4517  - Write Sequencer 421 */
+        [4518] = { 0x070F, 0x070F, 0x0000 }, /* R4518  - Write Sequencer 422 */
+        [4519] = { 0x010F, 0x010F, 0x0000 }, /* R4519  - Write Sequencer 423 */
+        [4520] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4520  - Write Sequencer 424 */
+        [4521] = { 0x00FF, 0x00FF, 0x0000 }, /* R4521  - Write Sequencer 425 */
+        [4522] = { 0x070F, 0x070F, 0x0000 }, /* R4522  - Write Sequencer 426 */
+        [4523] = { 0x010F, 0x010F, 0x0000 }, /* R4523  - Write Sequencer 427 */
+        [4524] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4524  - Write Sequencer 428 */
+        [4525] = { 0x00FF, 0x00FF, 0x0000 }, /* R4525  - Write Sequencer 429 */
+        [4526] = { 0x070F, 0x070F, 0x0000 }, /* R4526  - Write Sequencer 430 */
+        [4527] = { 0x010F, 0x010F, 0x0000 }, /* R4527  - Write Sequencer 431 */
+        [4528] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4528  - Write Sequencer 432 */
+        [4529] = { 0x00FF, 0x00FF, 0x0000 }, /* R4529  - Write Sequencer 433 */
+        [4530] = { 0x070F, 0x070F, 0x0000 }, /* R4530  - Write Sequencer 434 */
+        [4531] = { 0x010F, 0x010F, 0x0000 }, /* R4531  - Write Sequencer 435 */
+        [4532] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4532  - Write Sequencer 436 */
+        [4533] = { 0x00FF, 0x00FF, 0x0000 }, /* R4533  - Write Sequencer 437 */
+        [4534] = { 0x070F, 0x070F, 0x0000 }, /* R4534  - Write Sequencer 438 */
+        [4535] = { 0x010F, 0x010F, 0x0000 }, /* R4535  - Write Sequencer 439 */
+        [4536] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4536  - Write Sequencer 440 */
+        [4537] = { 0x00FF, 0x00FF, 0x0000 }, /* R4537  - Write Sequencer 441 */
+        [4538] = { 0x070F, 0x070F, 0x0000 }, /* R4538  - Write Sequencer 442 */
+        [4539] = { 0x010F, 0x010F, 0x0000 }, /* R4539  - Write Sequencer 443 */
+        [4540] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4540  - Write Sequencer 444 */
+        [4541] = { 0x00FF, 0x00FF, 0x0000 }, /* R4541  - Write Sequencer 445 */
+        [4542] = { 0x070F, 0x070F, 0x0000 }, /* R4542  - Write Sequencer 446 */
+        [4543] = { 0x010F, 0x010F, 0x0000 }, /* R4543  - Write Sequencer 447 */
+        [4544] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4544  - Write Sequencer 448 */
+        [4545] = { 0x00FF, 0x00FF, 0x0000 }, /* R4545  - Write Sequencer 449 */
+        [4546] = { 0x070F, 0x070F, 0x0000 }, /* R4546  - Write Sequencer 450 */
+        [4547] = { 0x010F, 0x010F, 0x0000 }, /* R4547  - Write Sequencer 451 */
+        [4548] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4548  - Write Sequencer 452 */
+        [4549] = { 0x00FF, 0x00FF, 0x0000 }, /* R4549  - Write Sequencer 453 */
+        [4550] = { 0x070F, 0x070F, 0x0000 }, /* R4550  - Write Sequencer 454 */
+        [4551] = { 0x010F, 0x010F, 0x0000 }, /* R4551  - Write Sequencer 455 */
+        [4552] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4552  - Write Sequencer 456 */
+        [4553] = { 0x00FF, 0x00FF, 0x0000 }, /* R4553  - Write Sequencer 457 */
+        [4554] = { 0x070F, 0x070F, 0x0000 }, /* R4554  - Write Sequencer 458 */
+        [4555] = { 0x010F, 0x010F, 0x0000 }, /* R4555  - Write Sequencer 459 */
+        [4556] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4556  - Write Sequencer 460 */
+        [4557] = { 0x00FF, 0x00FF, 0x0000 }, /* R4557  - Write Sequencer 461 */
+        [4558] = { 0x070F, 0x070F, 0x0000 }, /* R4558  - Write Sequencer 462 */
+        [4559] = { 0x010F, 0x010F, 0x0000 }, /* R4559  - Write Sequencer 463 */
+        [4560] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4560  - Write Sequencer 464 */
+        [4561] = { 0x00FF, 0x00FF, 0x0000 }, /* R4561  - Write Sequencer 465 */
+        [4562] = { 0x070F, 0x070F, 0x0000 }, /* R4562  - Write Sequencer 466 */
+        [4563] = { 0x010F, 0x010F, 0x0000 }, /* R4563  - Write Sequencer 467 */
+        [4564] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4564  - Write Sequencer 468 */
+        [4565] = { 0x00FF, 0x00FF, 0x0000 }, /* R4565  - Write Sequencer 469 */
+        [4566] = { 0x070F, 0x070F, 0x0000 }, /* R4566  - Write Sequencer 470 */
+        [4567] = { 0x010F, 0x010F, 0x0000 }, /* R4567  - Write Sequencer 471 */
+        [4568] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4568  - Write Sequencer 472 */
+        [4569] = { 0x00FF, 0x00FF, 0x0000 }, /* R4569  - Write Sequencer 473 */
+        [4570] = { 0x070F, 0x070F, 0x0000 }, /* R4570  - Write Sequencer 474 */
+        [4571] = { 0x010F, 0x010F, 0x0000 }, /* R4571  - Write Sequencer 475 */
+        [4572] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4572  - Write Sequencer 476 */
+        [4573] = { 0x00FF, 0x00FF, 0x0000 }, /* R4573  - Write Sequencer 477 */
+        [4574] = { 0x070F, 0x070F, 0x0000 }, /* R4574  - Write Sequencer 478 */
+        [4575] = { 0x010F, 0x010F, 0x0000 }, /* R4575  - Write Sequencer 479 */
+        [4576] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4576  - Write Sequencer 480 */
+        [4577] = { 0x00FF, 0x00FF, 0x0000 }, /* R4577  - Write Sequencer 481 */
+        [4578] = { 0x070F, 0x070F, 0x0000 }, /* R4578  - Write Sequencer 482 */
+        [4579] = { 0x010F, 0x010F, 0x0000 }, /* R4579  - Write Sequencer 483 */
+        [4580] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4580  - Write Sequencer 484 */
+        [4581] = { 0x00FF, 0x00FF, 0x0000 }, /* R4581  - Write Sequencer 485 */
+        [4582] = { 0x070F, 0x070F, 0x0000 }, /* R4582  - Write Sequencer 486 */
+        [4583] = { 0x010F, 0x010F, 0x0000 }, /* R4583  - Write Sequencer 487 */
+        [4584] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4584  - Write Sequencer 488 */
+        [4585] = { 0x00FF, 0x00FF, 0x0000 }, /* R4585  - Write Sequencer 489 */
+        [4586] = { 0x070F, 0x070F, 0x0000 }, /* R4586  - Write Sequencer 490 */
+        [4587] = { 0x010F, 0x010F, 0x0000 }, /* R4587  - Write Sequencer 491 */
+        [4588] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4588  - Write Sequencer 492 */
+        [4589] = { 0x00FF, 0x00FF, 0x0000 }, /* R4589  - Write Sequencer 493 */
+        [4590] = { 0x070F, 0x070F, 0x0000 }, /* R4590  - Write Sequencer 494 */
+        [4591] = { 0x010F, 0x010F, 0x0000 }, /* R4591  - Write Sequencer 495 */
+        [4592] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4592  - Write Sequencer 496 */
+        [4593] = { 0x00FF, 0x00FF, 0x0000 }, /* R4593  - Write Sequencer 497 */
+        [4594] = { 0x070F, 0x070F, 0x0000 }, /* R4594  - Write Sequencer 498 */
+        [4595] = { 0x010F, 0x010F, 0x0000 }, /* R4595  - Write Sequencer 499 */
+        [4596] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4596  - Write Sequencer 500 */
+        [4597] = { 0x00FF, 0x00FF, 0x0000 }, /* R4597  - Write Sequencer 501 */
+        [4598] = { 0x070F, 0x070F, 0x0000 }, /* R4598  - Write Sequencer 502 */
+        [4599] = { 0x010F, 0x010F, 0x0000 }, /* R4599  - Write Sequencer 503 */
+        [4600] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4600  - Write Sequencer 504 */
+        [4601] = { 0x00FF, 0x00FF, 0x0000 }, /* R4601  - Write Sequencer 505 */
+        [4602] = { 0x070F, 0x070F, 0x0000 }, /* R4602  - Write Sequencer 506 */
+        [4603] = { 0x010F, 0x010F, 0x0000 }, /* R4603  - Write Sequencer 507 */
+        [4604] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4604  - Write Sequencer 508 */
+        [4605] = { 0x00FF, 0x00FF, 0x0000 }, /* R4605  - Write Sequencer 509 */
+        [4606] = { 0x070F, 0x070F, 0x0000 }, /* R4606  - Write Sequencer 510 */
+        [4607] = { 0x010F, 0x010F, 0x0000 }, /* R4607  - Write Sequencer 511 */
+        [8192] = { 0x03FF, 0x03FF, 0x0000 }, /* R8192  - DSP2 Instruction RAM 0 */
+        [9216] = { 0x003F, 0x003F, 0x0000 }, /* R9216  - DSP2 Address RAM 2 */
+        [9217] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R9217  - DSP2 Address RAM 1 */
+        [9218] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R9218  - DSP2 Address RAM 0 */
+        [12288] = { 0x00FF, 0x00FF, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
+        [12289] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
+        [13312] = { 0x00FF, 0x00FF, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
+        [13313] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
+        [14336] = { 0x00FF, 0x00FF, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
+        [14337] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
+        [15360] = { 0x07FF, 0x07FF, 0x0000 }, /* R15360 - DSP2 Coeff RAM 0 */
+        [16384] = { 0x00FF, 0x00FF, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
+        [16385] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
+        [16386] = { 0x00FF, 0x00FF, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
+        [16387] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
+        [16388] = { 0x00FF, 0x00FF, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
+        [16389] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
+        [16896] = { 0x00FF, 0x00FF, 0x0000 }, /* R16896 - HDBASS_AI_1 */
+        [16897] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16897 - HDBASS_AI_0 */
+        [16898] = { 0x00FF, 0x00FF, 0x0000 }, /* R16898 - HDBASS_AR_1 */
+        [16899] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16899 - HDBASS_AR_0 */
+        [16900] = { 0x00FF, 0x00FF, 0x0000 }, /* R16900 - HDBASS_B_1 */
+        [16901] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16901 - HDBASS_B_0 */
+        [16902] = { 0x00FF, 0x00FF, 0x0000 }, /* R16902 - HDBASS_K_1 */
+        [16903] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16903 - HDBASS_K_0 */
+        [16904] = { 0x00FF, 0x00FF, 0x0000 }, /* R16904 - HDBASS_N1_1 */
+        [16905] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16905 - HDBASS_N1_0 */
+        [16906] = { 0x00FF, 0x00FF, 0x0000 }, /* R16906 - HDBASS_N2_1 */
+        [16907] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16907 - HDBASS_N2_0 */
+        [16908] = { 0x00FF, 0x00FF, 0x0000 }, /* R16908 - HDBASS_N3_1 */
+        [16909] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16909 - HDBASS_N3_0 */
+        [16910] = { 0x00FF, 0x00FF, 0x0000 }, /* R16910 - HDBASS_N4_1 */
+        [16911] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16911 - HDBASS_N4_0 */
+        [16912] = { 0x00FF, 0x00FF, 0x0000 }, /* R16912 - HDBASS_N5_1 */
+        [16913] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16913 - HDBASS_N5_0 */
+        [16914] = { 0x00FF, 0x00FF, 0x0000 }, /* R16914 - HDBASS_X1_1 */
+        [16915] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16915 - HDBASS_X1_0 */
+        [16916] = { 0x00FF, 0x00FF, 0x0000 }, /* R16916 - HDBASS_X2_1 */
+        [16917] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16917 - HDBASS_X2_0 */
+        [16918] = { 0x00FF, 0x00FF, 0x0000 }, /* R16918 - HDBASS_X3_1 */
+        [16919] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16919 - HDBASS_X3_0 */
+        [16920] = { 0x00FF, 0x00FF, 0x0000 }, /* R16920 - HDBASS_ATK_1 */
+        [16921] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
+        [16922] = { 0x00FF, 0x00FF, 0x0000 }, /* R16922 - HDBASS_DCY_1 */
+        [16923] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
+        [16924] = { 0x00FF, 0x00FF, 0x0000 }, /* R16924 - HDBASS_PG_1 */
+        [16925] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16925 - HDBASS_PG_0 */
+        [17408] = { 0x00FF, 0x00FF, 0x0000 }, /* R17408 - HPF_C_1 */
+        [17409] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17409 - HPF_C_0 */
+        [17920] = { 0x00FF, 0x00FF, 0x0000 }, /* R17920 - ADCL_RETUNE_C1_1 */
+        [17921] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17921 - ADCL_RETUNE_C1_0 */
+        [17922] = { 0x00FF, 0x00FF, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
+        [17923] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
+        [17924] = { 0x00FF, 0x00FF, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
+        [17925] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
+        [17926] = { 0x00FF, 0x00FF, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
+        [17927] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
+        [17928] = { 0x00FF, 0x00FF, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
+        [17929] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
+        [17930] = { 0x00FF, 0x00FF, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
+        [17931] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
+        [17932] = { 0x00FF, 0x00FF, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
+        [17933] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
+        [17934] = { 0x00FF, 0x00FF, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
+        [17935] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
+        [17936] = { 0x00FF, 0x00FF, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
+        [17937] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
+        [17938] = { 0x00FF, 0x00FF, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
+        [17939] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
+        [17940] = { 0x00FF, 0x00FF, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
+        [17941] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
+        [17942] = { 0x00FF, 0x00FF, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
+        [17943] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
+        [17944] = { 0x00FF, 0x00FF, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
+        [17945] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
+        [17946] = { 0x00FF, 0x00FF, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
+        [17947] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
+        [17948] = { 0x00FF, 0x00FF, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
+        [17949] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
+        [17950] = { 0x00FF, 0x00FF, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
+        [17951] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
+        [17952] = { 0x00FF, 0x00FF, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
+        [17953] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
+        [17954] = { 0x00FF, 0x00FF, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
+        [17955] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
+        [17956] = { 0x00FF, 0x00FF, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
+        [17957] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
+        [17958] = { 0x00FF, 0x00FF, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
+        [17959] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
+        [17960] = { 0x00FF, 0x00FF, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
+        [17961] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
+        [17962] = { 0x00FF, 0x00FF, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
+        [17963] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
+        [17964] = { 0x00FF, 0x00FF, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
+        [17965] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
+        [17966] = { 0x00FF, 0x00FF, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
+        [17967] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
+        [17968] = { 0x00FF, 0x00FF, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
+        [17969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
+        [17970] = { 0x00FF, 0x00FF, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
+        [17971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
+        [17972] = { 0x00FF, 0x00FF, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
+        [17973] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
+        [17974] = { 0x00FF, 0x00FF, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
+        [17975] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
+        [17976] = { 0x00FF, 0x00FF, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
+        [17977] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
+        [17978] = { 0x00FF, 0x00FF, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
+        [17979] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
+        [17980] = { 0x00FF, 0x00FF, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
+        [17981] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
+        [17982] = { 0x00FF, 0x00FF, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
+        [17983] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
+        [18432] = { 0x00FF, 0x00FF, 0x0000 }, /* R18432 - RETUNEADC_PG2_1 */
+        [18433] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
+        [18434] = { 0x00FF, 0x00FF, 0x0000 }, /* R18434 - RETUNEADC_PG_1 */
+        [18435] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
+        [18944] = { 0x00FF, 0x00FF, 0x0000 }, /* R18944 - ADCR_RETUNE_C1_1 */
+        [18945] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18945 - ADCR_RETUNE_C1_0 */
+        [18946] = { 0x00FF, 0x00FF, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
+        [18947] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
+        [18948] = { 0x00FF, 0x00FF, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
+        [18949] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
+        [18950] = { 0x00FF, 0x00FF, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
+        [18951] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
+        [18952] = { 0x00FF, 0x00FF, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
+        [18953] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
+        [18954] = { 0x00FF, 0x00FF, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
+        [18955] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
+        [18956] = { 0x00FF, 0x00FF, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
+        [18957] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
+        [18958] = { 0x00FF, 0x00FF, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
+        [18959] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
+        [18960] = { 0x00FF, 0x00FF, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
+        [18961] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
+        [18962] = { 0x00FF, 0x00FF, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
+        [18963] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
+        [18964] = { 0x00FF, 0x00FF, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
+        [18965] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
+        [18966] = { 0x00FF, 0x00FF, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
+        [18967] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
+        [18968] = { 0x00FF, 0x00FF, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
+        [18969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
+        [18970] = { 0x00FF, 0x00FF, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
+        [18971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
+        [18972] = { 0x00FF, 0x00FF, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
+        [18973] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
+        [18974] = { 0x00FF, 0x00FF, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
+        [18975] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
+        [18976] = { 0x00FF, 0x00FF, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
+        [18977] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
+        [18978] = { 0x00FF, 0x00FF, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
+        [18979] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
+        [18980] = { 0x00FF, 0x00FF, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
+        [18981] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
+        [18982] = { 0x00FF, 0x00FF, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
+        [18983] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
+        [18984] = { 0x00FF, 0x00FF, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
+        [18985] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
+        [18986] = { 0x00FF, 0x00FF, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
+        [18987] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
+        [18988] = { 0x00FF, 0x00FF, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
+        [18989] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
+        [18990] = { 0x00FF, 0x00FF, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
+        [18991] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
+        [18992] = { 0x00FF, 0x00FF, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
+        [18993] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
+        [18994] = { 0x00FF, 0x00FF, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
+        [18995] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
+        [18996] = { 0x00FF, 0x00FF, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
+        [18997] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
+        [18998] = { 0x00FF, 0x00FF, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
+        [18999] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
+        [19000] = { 0x00FF, 0x00FF, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
+        [19001] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
+        [19002] = { 0x00FF, 0x00FF, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
+        [19003] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
+        [19004] = { 0x00FF, 0x00FF, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
+        [19005] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
+        [19006] = { 0x00FF, 0x00FF, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
+        [19007] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
+        [19456] = { 0x00FF, 0x00FF, 0x0000 }, /* R19456 - DACL_RETUNE_C1_1 */
+        [19457] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19457 - DACL_RETUNE_C1_0 */
+        [19458] = { 0x00FF, 0x00FF, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
+        [19459] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
+        [19460] = { 0x00FF, 0x00FF, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
+        [19461] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
+        [19462] = { 0x00FF, 0x00FF, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
+        [19463] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
+        [19464] = { 0x00FF, 0x00FF, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
+        [19465] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
+        [19466] = { 0x00FF, 0x00FF, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
+        [19467] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
+        [19468] = { 0x00FF, 0x00FF, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
+        [19469] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
+        [19470] = { 0x00FF, 0x00FF, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
+        [19471] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
+        [19472] = { 0x00FF, 0x00FF, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
+        [19473] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
+        [19474] = { 0x00FF, 0x00FF, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
+        [19475] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
+        [19476] = { 0x00FF, 0x00FF, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
+        [19477] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
+        [19478] = { 0x00FF, 0x00FF, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
+        [19479] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
+        [19480] = { 0x00FF, 0x00FF, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
+        [19481] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
+        [19482] = { 0x00FF, 0x00FF, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
+        [19483] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
+        [19484] = { 0x00FF, 0x00FF, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
+        [19485] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
+        [19486] = { 0x00FF, 0x00FF, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
+        [19487] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
+        [19488] = { 0x00FF, 0x00FF, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
+        [19489] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
+        [19490] = { 0x00FF, 0x00FF, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
+        [19491] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
+        [19492] = { 0x00FF, 0x00FF, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
+        [19493] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
+        [19494] = { 0x00FF, 0x00FF, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
+        [19495] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
+        [19496] = { 0x00FF, 0x00FF, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
+        [19497] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
+        [19498] = { 0x00FF, 0x00FF, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
+        [19499] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
+        [19500] = { 0x00FF, 0x00FF, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
+        [19501] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
+        [19502] = { 0x00FF, 0x00FF, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
+        [19503] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
+        [19504] = { 0x00FF, 0x00FF, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
+        [19505] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
+        [19506] = { 0x00FF, 0x00FF, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
+        [19507] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
+        [19508] = { 0x00FF, 0x00FF, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
+        [19509] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
+        [19510] = { 0x00FF, 0x00FF, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
+        [19511] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
+        [19512] = { 0x00FF, 0x00FF, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
+        [19513] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
+        [19514] = { 0x00FF, 0x00FF, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
+        [19515] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
+        [19516] = { 0x00FF, 0x00FF, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
+        [19517] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
+        [19518] = { 0x00FF, 0x00FF, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
+        [19519] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
+        [19968] = { 0x00FF, 0x00FF, 0x0000 }, /* R19968 - RETUNEDAC_PG2_1 */
+        [19969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
+        [19970] = { 0x00FF, 0x00FF, 0x0000 }, /* R19970 - RETUNEDAC_PG_1 */
+        [19971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
+        [20480] = { 0x00FF, 0x00FF, 0x0000 }, /* R20480 - DACR_RETUNE_C1_1 */
+        [20481] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20481 - DACR_RETUNE_C1_0 */
+        [20482] = { 0x00FF, 0x00FF, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
+        [20483] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
+        [20484] = { 0x00FF, 0x00FF, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
+        [20485] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
+        [20486] = { 0x00FF, 0x00FF, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
+        [20487] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
+        [20488] = { 0x00FF, 0x00FF, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
+        [20489] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
+        [20490] = { 0x00FF, 0x00FF, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
+        [20491] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
+        [20492] = { 0x00FF, 0x00FF, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
+        [20493] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
+        [20494] = { 0x00FF, 0x00FF, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
+        [20495] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
+        [20496] = { 0x00FF, 0x00FF, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
+        [20497] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
+        [20498] = { 0x00FF, 0x00FF, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
+        [20499] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
+        [20500] = { 0x00FF, 0x00FF, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
+        [20501] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
+        [20502] = { 0x00FF, 0x00FF, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
+        [20503] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
+        [20504] = { 0x00FF, 0x00FF, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
+        [20505] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
+        [20506] = { 0x00FF, 0x00FF, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
+        [20507] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
+        [20508] = { 0x00FF, 0x00FF, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
+        [20509] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
+        [20510] = { 0x00FF, 0x00FF, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
+        [20511] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
+        [20512] = { 0x00FF, 0x00FF, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
+        [20513] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
+        [20514] = { 0x00FF, 0x00FF, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
+        [20515] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
+        [20516] = { 0x00FF, 0x00FF, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
+        [20517] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
+        [20518] = { 0x00FF, 0x00FF, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
+        [20519] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
+        [20520] = { 0x00FF, 0x00FF, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
+        [20521] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
+        [20522] = { 0x00FF, 0x00FF, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
+        [20523] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
+        [20524] = { 0x00FF, 0x00FF, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
+        [20525] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
+        [20526] = { 0x00FF, 0x00FF, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
+        [20527] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
+        [20528] = { 0x00FF, 0x00FF, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
+        [20529] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
+        [20530] = { 0x00FF, 0x00FF, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
+        [20531] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
+        [20532] = { 0x00FF, 0x00FF, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
+        [20533] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
+        [20534] = { 0x00FF, 0x00FF, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
+        [20535] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
+        [20536] = { 0x00FF, 0x00FF, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
+        [20537] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
+        [20538] = { 0x00FF, 0x00FF, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
+        [20539] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
+        [20540] = { 0x00FF, 0x00FF, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
+        [20541] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
+        [20542] = { 0x00FF, 0x00FF, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
+        [20543] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
+        [20992] = { 0x00FF, 0x00FF, 0x0000 }, /* R20992 - VSS_XHD2_1 */
+        [20993] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20993 - VSS_XHD2_0 */
+        [20994] = { 0x00FF, 0x00FF, 0x0000 }, /* R20994 - VSS_XHD3_1 */
+        [20995] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20995 - VSS_XHD3_0 */
+        [20996] = { 0x00FF, 0x00FF, 0x0000 }, /* R20996 - VSS_XHN1_1 */
+        [20997] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20997 - VSS_XHN1_0 */
+        [20998] = { 0x00FF, 0x00FF, 0x0000 }, /* R20998 - VSS_XHN2_1 */
+        [20999] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20999 - VSS_XHN2_0 */
+        [21000] = { 0x00FF, 0x00FF, 0x0000 }, /* R21000 - VSS_XHN3_1 */
+        [21001] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21001 - VSS_XHN3_0 */
+        [21002] = { 0x00FF, 0x00FF, 0x0000 }, /* R21002 - VSS_XLA_1 */
+        [21003] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21003 - VSS_XLA_0 */
+        [21004] = { 0x00FF, 0x00FF, 0x0000 }, /* R21004 - VSS_XLB_1 */
+        [21005] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21005 - VSS_XLB_0 */
+        [21006] = { 0x00FF, 0x00FF, 0x0000 }, /* R21006 - VSS_XLG_1 */
+        [21007] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21007 - VSS_XLG_0 */
+        [21008] = { 0x00FF, 0x00FF, 0x0000 }, /* R21008 - VSS_PG2_1 */
+        [21009] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21009 - VSS_PG2_0 */
+        [21010] = { 0x00FF, 0x00FF, 0x0000 }, /* R21010 - VSS_PG_1 */
+        [21011] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21011 - VSS_PG_0 */
+        [21012] = { 0x00FF, 0x00FF, 0x0000 }, /* R21012 - VSS_XTD1_1 */
+        [21013] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21013 - VSS_XTD1_0 */
+        [21014] = { 0x00FF, 0x00FF, 0x0000 }, /* R21014 - VSS_XTD2_1 */
+        [21015] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21015 - VSS_XTD2_0 */
+        [21016] = { 0x00FF, 0x00FF, 0x0000 }, /* R21016 - VSS_XTD3_1 */
+        [21017] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21017 - VSS_XTD3_0 */
+        [21018] = { 0x00FF, 0x00FF, 0x0000 }, /* R21018 - VSS_XTD4_1 */
+        [21019] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21019 - VSS_XTD4_0 */
+        [21020] = { 0x00FF, 0x00FF, 0x0000 }, /* R21020 - VSS_XTD5_1 */
+        [21021] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21021 - VSS_XTD5_0 */
+        [21022] = { 0x00FF, 0x00FF, 0x0000 }, /* R21022 - VSS_XTD6_1 */
+        [21023] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21023 - VSS_XTD6_0 */
+        [21024] = { 0x00FF, 0x00FF, 0x0000 }, /* R21024 - VSS_XTD7_1 */
+        [21025] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21025 - VSS_XTD7_0 */
+        [21026] = { 0x00FF, 0x00FF, 0x0000 }, /* R21026 - VSS_XTD8_1 */
+        [21027] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21027 - VSS_XTD8_0 */
+        [21028] = { 0x00FF, 0x00FF, 0x0000 }, /* R21028 - VSS_XTD9_1 */
+        [21029] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21029 - VSS_XTD9_0 */
+        [21030] = { 0x00FF, 0x00FF, 0x0000 }, /* R21030 - VSS_XTD10_1 */
+        [21031] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21031 - VSS_XTD10_0 */
+        [21032] = { 0x00FF, 0x00FF, 0x0000 }, /* R21032 - VSS_XTD11_1 */
+        [21033] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21033 - VSS_XTD11_0 */
+        [21034] = { 0x00FF, 0x00FF, 0x0000 }, /* R21034 - VSS_XTD12_1 */
+        [21035] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21035 - VSS_XTD12_0 */
+        [21036] = { 0x00FF, 0x00FF, 0x0000 }, /* R21036 - VSS_XTD13_1 */
+        [21037] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21037 - VSS_XTD13_0 */
+        [21038] = { 0x00FF, 0x00FF, 0x0000 }, /* R21038 - VSS_XTD14_1 */
+        [21039] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21039 - VSS_XTD14_0 */
+        [21040] = { 0x00FF, 0x00FF, 0x0000 }, /* R21040 - VSS_XTD15_1 */
+        [21041] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21041 - VSS_XTD15_0 */
+        [21042] = { 0x00FF, 0x00FF, 0x0000 }, /* R21042 - VSS_XTD16_1 */
+        [21043] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21043 - VSS_XTD16_0 */
+        [21044] = { 0x00FF, 0x00FF, 0x0000 }, /* R21044 - VSS_XTD17_1 */
+        [21045] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21045 - VSS_XTD17_0 */
+        [21046] = { 0x00FF, 0x00FF, 0x0000 }, /* R21046 - VSS_XTD18_1 */
+        [21047] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21047 - VSS_XTD18_0 */
+        [21048] = { 0x00FF, 0x00FF, 0x0000 }, /* R21048 - VSS_XTD19_1 */
+        [21049] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21049 - VSS_XTD19_0 */
+        [21050] = { 0x00FF, 0x00FF, 0x0000 }, /* R21050 - VSS_XTD20_1 */
+        [21051] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21051 - VSS_XTD20_0 */
+        [21052] = { 0x00FF, 0x00FF, 0x0000 }, /* R21052 - VSS_XTD21_1 */
+        [21053] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21053 - VSS_XTD21_0 */
+        [21054] = { 0x00FF, 0x00FF, 0x0000 }, /* R21054 - VSS_XTD22_1 */
+        [21055] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21055 - VSS_XTD22_0 */
+        [21056] = { 0x00FF, 0x00FF, 0x0000 }, /* R21056 - VSS_XTD23_1 */
+        [21057] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21057 - VSS_XTD23_0 */
+        [21058] = { 0x00FF, 0x00FF, 0x0000 }, /* R21058 - VSS_XTD24_1 */
+        [21059] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21059 - VSS_XTD24_0 */
+        [21060] = { 0x00FF, 0x00FF, 0x0000 }, /* R21060 - VSS_XTD25_1 */
+        [21061] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21061 - VSS_XTD25_0 */
+        [21062] = { 0x00FF, 0x00FF, 0x0000 }, /* R21062 - VSS_XTD26_1 */
+        [21063] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21063 - VSS_XTD26_0 */
+        [21064] = { 0x00FF, 0x00FF, 0x0000 }, /* R21064 - VSS_XTD27_1 */
+        [21065] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21065 - VSS_XTD27_0 */
+        [21066] = { 0x00FF, 0x00FF, 0x0000 }, /* R21066 - VSS_XTD28_1 */
+        [21067] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21067 - VSS_XTD28_0 */
+        [21068] = { 0x00FF, 0x00FF, 0x0000 }, /* R21068 - VSS_XTD29_1 */
+        [21069] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21069 - VSS_XTD29_0 */
+        [21070] = { 0x00FF, 0x00FF, 0x0000 }, /* R21070 - VSS_XTD30_1 */
+        [21071] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21071 - VSS_XTD30_0 */
+        [21072] = { 0x00FF, 0x00FF, 0x0000 }, /* R21072 - VSS_XTD31_1 */
+        [21073] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21073 - VSS_XTD31_0 */
+        [21074] = { 0x00FF, 0x00FF, 0x0000 }, /* R21074 - VSS_XTD32_1 */
+        [21075] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21075 - VSS_XTD32_0 */
+        [21076] = { 0x00FF, 0x00FF, 0x0000 }, /* R21076 - VSS_XTS1_1 */
+        [21077] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21077 - VSS_XTS1_0 */
+        [21078] = { 0x00FF, 0x00FF, 0x0000 }, /* R21078 - VSS_XTS2_1 */
+        [21079] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21079 - VSS_XTS2_0 */
+        [21080] = { 0x00FF, 0x00FF, 0x0000 }, /* R21080 - VSS_XTS3_1 */
+        [21081] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21081 - VSS_XTS3_0 */
+        [21082] = { 0x00FF, 0x00FF, 0x0000 }, /* R21082 - VSS_XTS4_1 */
+        [21083] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21083 - VSS_XTS4_0 */
+        [21084] = { 0x00FF, 0x00FF, 0x0000 }, /* R21084 - VSS_XTS5_1 */
+        [21085] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21085 - VSS_XTS5_0 */
+        [21086] = { 0x00FF, 0x00FF, 0x0000 }, /* R21086 - VSS_XTS6_1 */
+        [21087] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21087 - VSS_XTS6_0 */
+        [21088] = { 0x00FF, 0x00FF, 0x0000 }, /* R21088 - VSS_XTS7_1 */
+        [21089] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21089 - VSS_XTS7_0 */
+        [21090] = { 0x00FF, 0x00FF, 0x0000 }, /* R21090 - VSS_XTS8_1 */
+        [21091] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21091 - VSS_XTS8_0 */
+        [21092] = { 0x00FF, 0x00FF, 0x0000 }, /* R21092 - VSS_XTS9_1 */
+        [21093] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21093 - VSS_XTS9_0 */
+        [21094] = { 0x00FF, 0x00FF, 0x0000 }, /* R21094 - VSS_XTS10_1 */
+        [21095] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21095 - VSS_XTS10_0 */
+        [21096] = { 0x00FF, 0x00FF, 0x0000 }, /* R21096 - VSS_XTS11_1 */
+        [21097] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21097 - VSS_XTS11_0 */
+        [21098] = { 0x00FF, 0x00FF, 0x0000 }, /* R21098 - VSS_XTS12_1 */
+        [21099] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21099 - VSS_XTS12_0 */
+        [21100] = { 0x00FF, 0x00FF, 0x0000 }, /* R21100 - VSS_XTS13_1 */
+        [21101] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21101 - VSS_XTS13_0 */
+        [21102] = { 0x00FF, 0x00FF, 0x0000 }, /* R21102 - VSS_XTS14_1 */
+        [21103] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21103 - VSS_XTS14_0 */
+        [21104] = { 0x00FF, 0x00FF, 0x0000 }, /* R21104 - VSS_XTS15_1 */
+        [21105] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21105 - VSS_XTS15_0 */
+        [21106] = { 0x00FF, 0x00FF, 0x0000 }, /* R21106 - VSS_XTS16_1 */
+        [21107] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21107 - VSS_XTS16_0 */
+        [21108] = { 0x00FF, 0x00FF, 0x0000 }, /* R21108 - VSS_XTS17_1 */
+        [21109] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21109 - VSS_XTS17_0 */
+        [21110] = { 0x00FF, 0x00FF, 0x0000 }, /* R21110 - VSS_XTS18_1 */
+        [21111] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21111 - VSS_XTS18_0 */
+        [21112] = { 0x00FF, 0x00FF, 0x0000 }, /* R21112 - VSS_XTS19_1 */
+        [21113] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21113 - VSS_XTS19_0 */
+        [21114] = { 0x00FF, 0x00FF, 0x0000 }, /* R21114 - VSS_XTS20_1 */
+        [21115] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21115 - VSS_XTS20_0 */
+        [21116] = { 0x00FF, 0x00FF, 0x0000 }, /* R21116 - VSS_XTS21_1 */
+        [21117] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21117 - VSS_XTS21_0 */
+        [21118] = { 0x00FF, 0x00FF, 0x0000 }, /* R21118 - VSS_XTS22_1 */
+        [21119] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21119 - VSS_XTS22_0 */
+        [21120] = { 0x00FF, 0x00FF, 0x0000 }, /* R21120 - VSS_XTS23_1 */
+        [21121] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21121 - VSS_XTS23_0 */
+        [21122] = { 0x00FF, 0x00FF, 0x0000 }, /* R21122 - VSS_XTS24_1 */
+        [21123] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21123 - VSS_XTS24_0 */
+        [21124] = { 0x00FF, 0x00FF, 0x0000 }, /* R21124 - VSS_XTS25_1 */
+        [21125] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21125 - VSS_XTS25_0 */
+        [21126] = { 0x00FF, 0x00FF, 0x0000 }, /* R21126 - VSS_XTS26_1 */
+        [21127] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21127 - VSS_XTS26_0 */
+        [21128] = { 0x00FF, 0x00FF, 0x0000 }, /* R21128 - VSS_XTS27_1 */
+        [21129] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21129 - VSS_XTS27_0 */
+        [21130] = { 0x00FF, 0x00FF, 0x0000 }, /* R21130 - VSS_XTS28_1 */
+        [21131] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21131 - VSS_XTS28_0 */
+        [21132] = { 0x00FF, 0x00FF, 0x0000 }, /* R21132 - VSS_XTS29_1 */
+        [21133] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21133 - VSS_XTS29_0 */
+        [21134] = { 0x00FF, 0x00FF, 0x0000 }, /* R21134 - VSS_XTS30_1 */
+        [21135] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21135 - VSS_XTS30_0 */
+        [21136] = { 0x00FF, 0x00FF, 0x0000 }, /* R21136 - VSS_XTS31_1 */
+        [21137] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21137 - VSS_XTS31_0 */
+        [21138] = { 0x00FF, 0x00FF, 0x0000 }, /* R21138 - VSS_XTS32_1 */
+        [21139] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21139 - VSS_XTS32_0 */
+};
+
+static int wm8962_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
+{
+        if (wm8962_reg_access[reg].vol)
+                return 1;
+        else
+                return 0;
+}
+
+static int wm8962_readable_register(struct snd_soc_codec *codec, unsigned int reg)
+{
+        if (wm8962_reg_access[reg].read)
+                return 1;
+        else
+                return 0;
+}
+
+static int wm8962_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243);
+}
+
+static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
+static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
+static const unsigned int mixinpga_tlv[] = {
+        TLV_DB_RANGE_HEAD(7),
+        0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
+        2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
+        3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
+        5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
+        6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
+};
+static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
+static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
+static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
+static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
+static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
+static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
+static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
+static const unsigned int classd_tlv[] = {
+        TLV_DB_RANGE_HEAD(7),
+        0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
+        7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
+};
+
+/* The VU bits for the headphones are in a different register to the mute
+ * bits and only take effect on the PGA if it is actually powered.
+ */
+static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
+                            struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        u16 *reg_cache = codec->reg_cache;
+        int ret;
+
+        /* Apply the update (if any) */
+        ret = snd_soc_put_volsw(kcontrol, ucontrol);
+        if (ret == 0)
+                return 0;
+
+        /* If the left PGA is enabled hit that VU bit... */
+        if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
+                return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
+                                     reg_cache[WM8962_HPOUTL_VOLUME]);
+
+        /* ...otherwise the right.  The VU is stereo. */
+        if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
+                return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
+                                     reg_cache[WM8962_HPOUTR_VOLUME]);
+
+        return 0;
+}
+
+/* The VU bits for the speakers are in a different register to the mute
+ * bits and only take effect on the PGA if it is actually powered.
+ */
+static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
+                            struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        u16 *reg_cache = codec->reg_cache;
+        int ret;
+
+        /* Apply the update (if any) */
+        ret = snd_soc_put_volsw(kcontrol, ucontrol);
+        if (ret == 0)
+                return 0;
+
+        /* If the left PGA is enabled hit that VU bit... */
+        if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
+                return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
+                                     reg_cache[WM8962_SPKOUTL_VOLUME]);
+
+        /* ...otherwise the right.  The VU is stereo. */
+        if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
+                return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
+                                     reg_cache[WM8962_SPKOUTR_VOLUME]);
+
+        return 0;
+}
+
+static const char *cap_hpf_mode_text[] = {
+        "Hi-fi", "Application"
+};
+
+static const struct soc_enum cap_hpf_mode =
+        SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
+
+static const struct snd_kcontrol_new wm8962_snd_controls[] = {
+SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
+
+SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
+               mixin_tlv),
+SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
+               mixinpga_tlv),
+SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
+               mixin_tlv),
+
+SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
+               mixin_tlv),
+SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
+               mixinpga_tlv),
+SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
+               mixin_tlv),
+
+SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
+                 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
+SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
+                 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
+SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
+             WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
+SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
+             WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
+SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
+SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
+SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
+
+SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
+                 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
+
+SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
+                 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
+SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
+
+SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
+           5, 1, 0),
+
+SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
+
+SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
+                 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
+SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
+               snd_soc_get_volsw, wm8962_put_hp_sw),
+SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
+             7, 1, 0),
+SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
+               hp_tlv),
+
+SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
+             WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
+
+SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
+               3, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
+               0, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
+               7, 1, 1, inmix_tlv),
+SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
+               6, 1, 1, inmix_tlv),
+
+SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
+               3, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
+               0, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
+               7, 1, 1, inmix_tlv),
+SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
+               6, 1, 1, inmix_tlv),
+
+SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
+               classd_tlv),
+};
+
+static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
+SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
+SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
+               snd_soc_get_volsw, wm8962_put_spk_sw),
+SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
+
+SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
+SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
+               3, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
+               0, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
+               7, 1, 1, inmix_tlv),
+SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
+               6, 1, 1, inmix_tlv),
+SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
+               7, 1, 0, inmix_tlv),
+SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
+               6, 1, 0, inmix_tlv),
+};
+
+static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
+SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
+                 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
+SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
+               snd_soc_get_volsw, wm8962_put_spk_sw),
+SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
+             7, 1, 0),
+
+SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
+             WM8962_SPEAKER_MIXER_4, 8, 1, 1),
+
+SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
+               3, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
+               0, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
+               7, 1, 1, inmix_tlv),
+SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
+               6, 1, 1, inmix_tlv),
+SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
+               7, 1, 0, inmix_tlv),
+SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
+               6, 1, 0, inmix_tlv),
+
+SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
+               3, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
+               0, 7, 0, bypass_tlv),
+SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
+               7, 1, 1, inmix_tlv),
+SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
+               6, 1, 1, inmix_tlv),
+SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
+               5, 1, 0, inmix_tlv),
+SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
+               4, 1, 0, inmix_tlv),
+};
+
+static int sysclk_event(struct snd_soc_dapm_widget *w,
+                        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        int src;
+        int fll;
+
+        src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
+
+        switch (src) {
+        case 0:      /* MCLK */
+                fll = 0;
+                break;
+        case 0x200:  /* FLL */
+                fll = 1;
+                break;
+        default:
+                dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
+                return -EINVAL;
+        }
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                if (fll)
+                        snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
+                                            WM8962_FLL_ENA, WM8962_FLL_ENA);
+                break;
+
+        case SND_SOC_DAPM_POST_PMD:
+                if (fll)
+                        snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
+                                            WM8962_FLL_ENA, 0);
+                break;
+
+        default:
+                BUG();
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int cp_event(struct snd_soc_dapm_widget *w,
+                    struct snd_kcontrol *kcontrol, int event)
+{
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                msleep(5);
+                break;
+
+        default:
+                BUG();
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int hp_event(struct snd_soc_dapm_widget *w,
+                    struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        int timeout;
+        int reg;
+        int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
+                        WM8962_DCS_STARTUP_DONE_HP1R);
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
+                                    WM8962_HP1L_ENA | WM8962_HP1R_ENA,
+                                    WM8962_HP1L_ENA | WM8962_HP1R_ENA);
+                udelay(20);
+
+                snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
+                                    WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
+                                    WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
+
+                /* Start the DC servo */
+                snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
+                                    WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
+                                    WM8962_HP1L_DCS_STARTUP |
+                                    WM8962_HP1R_DCS_STARTUP,
+                                    WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
+                                    WM8962_HP1L_DCS_STARTUP |
+                                    WM8962_HP1R_DCS_STARTUP);
+
+                /* Wait for it to complete, should be well under 100ms */
+                timeout = 0;
+                do {
+                        msleep(1);
+                        reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
+                        if (reg < 0) {
+                                dev_err(codec->dev,
+                                        "Failed to read DCS status: %d\n",
+                                        reg);
+                                continue;
+                        }
+                        dev_dbg(codec->dev, "DCS status: %x\n", reg);
+                } while (++timeout < 200 && (reg & expected) != expected);
+
+                if ((reg & expected) != expected)
+                        dev_err(codec->dev, "DC servo timed out\n");
+                else
+                        dev_dbg(codec->dev, "DC servo complete after %dms\n",
+                                timeout);
+
+                snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
+                                    WM8962_HP1L_ENA_OUTP |
+                                    WM8962_HP1R_ENA_OUTP,
+                                    WM8962_HP1L_ENA_OUTP |
+                                    WM8962_HP1R_ENA_OUTP);
+                udelay(20);
+
+                snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
+                                    WM8962_HP1L_RMV_SHORT |
+                                    WM8962_HP1R_RMV_SHORT,
+                                    WM8962_HP1L_RMV_SHORT |
+                                    WM8962_HP1R_RMV_SHORT);
+                break;
+
+        case SND_SOC_DAPM_PRE_PMD:
+                snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
+                                    WM8962_HP1L_RMV_SHORT |
+                                    WM8962_HP1R_RMV_SHORT, 0);
+
+                udelay(20);
+
+                snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
+                                    WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
+                                    WM8962_HP1L_DCS_STARTUP |
+                                    WM8962_HP1R_DCS_STARTUP,
+                                    0);
+
+                snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
+                                    WM8962_HP1L_ENA | WM8962_HP1R_ENA |
+                                    WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
+                                    WM8962_HP1L_ENA_OUTP |
+                                    WM8962_HP1R_ENA_OUTP, 0);
+                                    
+                break;
+
+        default:
+                BUG();
+                return -EINVAL;
+        
+        }
+
+        return 0;
+}
+
+/* VU bits for the output PGAs only take effect while the PGA is powered */
+static int out_pga_event(struct snd_soc_dapm_widget *w,
+                         struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        u16 *reg_cache = codec->reg_cache;
+        int reg;
+
+        switch (w->shift) {
+        case WM8962_HPOUTR_PGA_ENA_SHIFT:
+                reg = WM8962_HPOUTR_VOLUME;
+                break;
+        case WM8962_HPOUTL_PGA_ENA_SHIFT:
+                reg = WM8962_HPOUTL_VOLUME;
+                break;
+        case WM8962_SPKOUTR_PGA_ENA_SHIFT:
+                reg = WM8962_SPKOUTR_VOLUME;
+                break;
+        case WM8962_SPKOUTL_PGA_ENA_SHIFT:
+                reg = WM8962_SPKOUTL_VOLUME;
+                break;
+        default:
+                BUG();
+                return -EINVAL;
+        }
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                return snd_soc_write(codec, reg, reg_cache[reg]);
+        default:
+                BUG();
+                return -EINVAL;
+        }
+}
+
+static const char *st_text[] = { "None", "Right", "Left" };
+
+static const struct soc_enum str_enum =
+        SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
+
+static const struct snd_kcontrol_new str_mux =
+        SOC_DAPM_ENUM("Right Sidetone", str_enum);
+
+static const struct soc_enum stl_enum =
+        SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
+
+static const struct snd_kcontrol_new stl_mux =
+        SOC_DAPM_ENUM("Left Sidetone", stl_enum);
+
+static const char *outmux_text[] = { "DAC", "Mixer" };
+
+static const struct soc_enum spkoutr_enum =
+        SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
+
+static const struct snd_kcontrol_new spkoutr_mux =
+        SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
+
+static const struct soc_enum spkoutl_enum =
+        SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
+
+static const struct snd_kcontrol_new spkoutl_mux =
+        SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
+
+static const struct soc_enum hpoutr_enum =
+        SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
+
+static const struct snd_kcontrol_new hpoutr_mux =
+        SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
+
+static const struct soc_enum hpoutl_enum =
+        SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
+
+static const struct snd_kcontrol_new hpoutl_mux =
+        SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
+
+static const struct snd_kcontrol_new inpgal[] = {
+SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
+SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
+SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
+SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new inpgar[] = {
+SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
+SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
+SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
+SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new mixinl[] = {
+SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
+SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
+SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
+};
+
+static const struct snd_kcontrol_new mixinr[] = {
+SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
+SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
+SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new hpmixl[] = {
+SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
+SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
+SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
+SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
+SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
+SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new hpmixr[] = {
+SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
+SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
+SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
+SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
+SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
+SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new spkmixl[] = {
+SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
+SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
+SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
+SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
+SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
+SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new spkmixr[] = {
+SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
+SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
+SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
+SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
+SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
+SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
+SND_SOC_DAPM_INPUT("IN1L"),
+SND_SOC_DAPM_INPUT("IN1R"),
+SND_SOC_DAPM_INPUT("IN2L"),
+SND_SOC_DAPM_INPUT("IN2R"),
+SND_SOC_DAPM_INPUT("IN3L"),
+SND_SOC_DAPM_INPUT("IN3R"),
+SND_SOC_DAPM_INPUT("IN4L"),
+SND_SOC_DAPM_INPUT("IN4R"),
+SND_SOC_DAPM_INPUT("Beep"),
+SND_SOC_DAPM_INPUT("DMICDAT"),
+
+SND_SOC_DAPM_MICBIAS("MICBIAS", WM8962_PWR_MGMT_1, 1, 0),
+
+SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
+SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
+                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
+                    SND_SOC_DAPM_POST_PMU),
+SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
+
+SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
+                   inpgal, ARRAY_SIZE(inpgal)),
+SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
+                   inpgar, ARRAY_SIZE(inpgar)),
+SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
+                   mixinl, ARRAY_SIZE(mixinl)),
+SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
+                   mixinr, ARRAY_SIZE(mixinr)),
+
+SND_SOC_DAPM_AIF_IN("DMIC", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
+
+SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
+SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
+
+SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
+SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
+
+SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
+SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
+
+SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
+                   hpmixl, ARRAY_SIZE(hpmixl)),
+SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
+                   hpmixr, ARRAY_SIZE(hpmixr)),
+
+SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
+                   out_pga_event, SND_SOC_DAPM_POST_PMU),
+SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
+                   out_pga_event, SND_SOC_DAPM_POST_PMU),
+
+SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
+                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+SND_SOC_DAPM_OUTPUT("HPOUTL"),
+SND_SOC_DAPM_OUTPUT("HPOUTR"),
+};
+
+static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
+SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
+                   spkmixl, ARRAY_SIZE(spkmixl)),
+SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
+                   out_pga_event, SND_SOC_DAPM_POST_PMU),
+SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
+SND_SOC_DAPM_OUTPUT("SPKOUT"),
+};
+
+static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
+SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
+                   spkmixl, ARRAY_SIZE(spkmixl)),
+SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
+                   spkmixr, ARRAY_SIZE(spkmixr)),
+
+SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
+                   out_pga_event, SND_SOC_DAPM_POST_PMU),
+SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
+                   out_pga_event, SND_SOC_DAPM_POST_PMU),
+
+SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
+SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
+
+SND_SOC_DAPM_OUTPUT("SPKOUTL"),
+SND_SOC_DAPM_OUTPUT("SPKOUTR"),
+};
+
+static const struct snd_soc_dapm_route wm8962_intercon[] = {
+        { "INPGAL", "IN1L Switch", "IN1L" },
+        { "INPGAL", "IN2L Switch", "IN2L" },
+        { "INPGAL", "IN3L Switch", "IN3L" },
+        { "INPGAL", "IN4L Switch", "IN4L" },
+
+        { "INPGAR", "IN1R Switch", "IN1R" },
+        { "INPGAR", "IN2R Switch", "IN2R" },
+        { "INPGAR", "IN3R Switch", "IN3R" },
+        { "INPGAR", "IN4R Switch", "IN4R" },
+
+        { "MIXINL", "IN2L Switch", "IN2L" },
+        { "MIXINL", "IN3L Switch", "IN3L" },
+        { "MIXINL", "PGA Switch", "INPGAL" },
+
+        { "MIXINR", "IN2R Switch", "IN2R" },
+        { "MIXINR", "IN3R Switch", "IN3R" },
+        { "MIXINR", "PGA Switch", "INPGAR" },
+
+        { "MICBIAS", NULL, "SYSCLK" },
+
+        { "DMIC", NULL, "DMICDAT" },
+
+        { "ADCL", NULL, "SYSCLK" },
+        { "ADCL", NULL, "TOCLK" },
+        { "ADCL", NULL, "MIXINL" },
+        { "ADCL", NULL, "DMIC" },
+
+        { "ADCR", NULL, "SYSCLK" },
+        { "ADCR", NULL, "TOCLK" },
+        { "ADCR", NULL, "MIXINR" },
+        { "ADCR", NULL, "DMIC" },
+
+        { "STL", "Left", "ADCL" },
+        { "STL", "Right", "ADCR" },
+
+        { "STR", "Left", "ADCL" },
+        { "STR", "Right", "ADCR" },
+
+        { "DACL", NULL, "SYSCLK" },
+        { "DACL", NULL, "TOCLK" },
+        { "DACL", NULL, "Beep" },
+        { "DACL", NULL, "STL" },
+
+        { "DACR", NULL, "SYSCLK" },
+        { "DACR", NULL, "TOCLK" },
+        { "DACR", NULL, "Beep" },
+        { "DACR", NULL, "STR" },
+
+        { "HPMIXL", "IN4L Switch", "IN4L" },
+        { "HPMIXL", "IN4R Switch", "IN4R" },
+        { "HPMIXL", "DACL Switch", "DACL" },
+        { "HPMIXL", "DACR Switch", "DACR" },
+        { "HPMIXL", "MIXINL Switch", "MIXINL" },
+        { "HPMIXL", "MIXINR Switch", "MIXINR" },
+
+        { "HPMIXR", "IN4L Switch", "IN4L" },
+        { "HPMIXR", "IN4R Switch", "IN4R" },
+        { "HPMIXR", "DACL Switch", "DACL" },
+        { "HPMIXR", "DACR Switch", "DACR" },
+        { "HPMIXR", "MIXINL Switch", "MIXINL" },
+        { "HPMIXR", "MIXINR Switch", "MIXINR" },
+
+        { "Left Bypass", NULL, "HPMIXL" },
+        { "Left Bypass", NULL, "Class G" },
+
+        { "Right Bypass", NULL, "HPMIXR" },
+        { "Right Bypass", NULL, "Class G" },
+
+        { "HPOUTL PGA", "Mixer", "Left Bypass" },
+        { "HPOUTL PGA", "DAC", "DACL" },
+
+        { "HPOUTR PGA", "Mixer", "Right Bypass" },
+        { "HPOUTR PGA", "DAC", "DACR" },
+
+        { "HPOUT", NULL, "HPOUTL PGA" },
+        { "HPOUT", NULL, "HPOUTR PGA" },
+        { "HPOUT", NULL, "Charge Pump" },
+        { "HPOUT", NULL, "SYSCLK" },
+        { "HPOUT", NULL, "TOCLK" },
+
+        { "HPOUTL", NULL, "HPOUT" },
+        { "HPOUTR", NULL, "HPOUT" },
+};
+
+static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
+        { "Speaker Mixer", "IN4L Switch", "IN4L" },
+        { "Speaker Mixer", "IN4R Switch", "IN4R" },
+        { "Speaker Mixer", "DACL Switch", "DACL" },
+        { "Speaker Mixer", "DACR Switch", "DACR" },
+        { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
+        { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
+
+        { "Speaker PGA", "Mixer", "Speaker Mixer" },
+        { "Speaker PGA", "DAC", "DACL" },
+
+        { "Speaker Output", NULL, "Speaker PGA" },
+        { "Speaker Output", NULL, "SYSCLK" },
+        { "Speaker Output", NULL, "TOCLK" },
+
+        { "SPKOUT", NULL, "Speaker Output" },
+};
+
+static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
+        { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
+        { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
+        { "SPKOUTL Mixer", "DACL Switch", "DACL" },
+        { "SPKOUTL Mixer", "DACR Switch", "DACR" },
+        { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
+        { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
+
+        { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
+        { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
+        { "SPKOUTR Mixer", "DACL Switch", "DACL" },
+        { "SPKOUTR Mixer", "DACR Switch", "DACR" },
+        { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
+        { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
+
+        { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
+        { "SPKOUTL PGA", "DAC", "DACL" },
+
+        { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
+        { "SPKOUTR PGA", "DAC", "DACR" },
+
+        { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
+        { "SPKOUTL Output", NULL, "SYSCLK" },
+        { "SPKOUTL Output", NULL, "TOCLK" },
+
+        { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
+        { "SPKOUTR Output", NULL, "SYSCLK" },
+        { "SPKOUTR Output", NULL, "TOCLK" },
+
+        { "SPKOUTL", NULL, "SPKOUTL Output" },
+        { "SPKOUTR", NULL, "SPKOUTR Output" },
+};
+
+static int wm8962_add_widgets(struct snd_soc_codec *codec)
+{
+        struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+        snd_soc_add_controls(codec, wm8962_snd_controls,
+                             ARRAY_SIZE(wm8962_snd_controls));
+        if (pdata && pdata->spk_mono)
+                snd_soc_add_controls(codec, wm8962_spk_mono_controls,
+                                     ARRAY_SIZE(wm8962_spk_mono_controls));
+        else
+                snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
+                                     ARRAY_SIZE(wm8962_spk_stereo_controls));
+
+
+        snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
+                                  ARRAY_SIZE(wm8962_dapm_widgets));
+        if (pdata && pdata->spk_mono)
+                snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
+                                          ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
+        else
+                snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
+                                          ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
+
+        snd_soc_dapm_add_routes(dapm, wm8962_intercon,
+                                ARRAY_SIZE(wm8962_intercon));
+        if (pdata && pdata->spk_mono)
+                snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
+                                        ARRAY_SIZE(wm8962_spk_mono_intercon));
+        else
+                snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
+                                        ARRAY_SIZE(wm8962_spk_stereo_intercon));
+
+
+        snd_soc_dapm_disable_pin(dapm, "Beep");
+
+        return 0;
+}
+
+static void wm8962_sync_cache(struct snd_soc_codec *codec)
+{
+        u16 *reg_cache = codec->reg_cache;
+        int i;
+
+        if (!codec->cache_sync)
+                return;
+
+        dev_dbg(codec->dev, "Syncing cache\n");
+
+        codec->cache_only = 0;
+
+        /* Sync back cached values if they're different from the
+         * hardware default.
+         */
+        for (i = 1; i < codec->driver->reg_cache_size; i++) {
+                if (i == WM8962_SOFTWARE_RESET)
+                        continue;
+                if (reg_cache[i] == wm8962_reg[i])
+                        continue;
+
+                snd_soc_write(codec, i, reg_cache[i]);
+        }
+
+        codec->cache_sync = 0;
+}
+
+/* -1 for reserved values */
+static const int bclk_divs[] = {
+        1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
+};
+
+static void wm8962_configure_bclk(struct snd_soc_codec *codec)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        int dspclk, i;
+        int clocking2 = 0;
+        int aif2 = 0;
+
+        if (!wm8962->bclk) {
+                dev_dbg(codec->dev, "No BCLK rate configured\n");
+                return;
+        }
+
+        dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
+        if (dspclk < 0) {
+                dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
+                return;
+        }
+
+        dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
+        switch (dspclk) {
+        case 0:
+                dspclk = wm8962->sysclk_rate;
+                break;
+        case 1:
+                dspclk = wm8962->sysclk_rate / 2;
+                break;
+        case 2:
+                dspclk = wm8962->sysclk_rate / 4;
+                break;
+        default:
+                dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
+                dspclk = wm8962->sysclk;
+        }
+
+        dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
+
+        /* We're expecting an exact match */
+        for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
+                if (bclk_divs[i] < 0)
+                        continue;
+
+                if (dspclk / bclk_divs[i] == wm8962->bclk) {
+                        dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
+                                bclk_divs[i], wm8962->bclk);
+                        clocking2 |= i;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(bclk_divs)) {
+                dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
+                        dspclk / wm8962->bclk);
+                return;
+        }
+
+        aif2 |= wm8962->bclk / wm8962->lrclk;
+        dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
+                wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
+
+        snd_soc_update_bits(codec, WM8962_CLOCKING2,
+                            WM8962_BCLK_DIV_MASK, clocking2);
+        snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
+                            WM8962_AIF_RATE_MASK, aif2);
+}
+
+static int wm8962_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        if (level == codec->dapm.bias_level)
+                return 0;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+
+        case SND_SOC_BIAS_PREPARE:
+                /* VMID 2*50k */
+                snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
+                                    WM8962_VMID_SEL_MASK, 0x80);
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
+                                                    wm8962->supplies);
+                        if (ret != 0) {
+                                dev_err(codec->dev,
+                                        "Failed to enable supplies: %d\n",
+                                        ret);
+                                return ret;
+                        }
+
+                        wm8962_sync_cache(codec);
+
+                        snd_soc_update_bits(codec, WM8962_ANTI_POP,
+                                            WM8962_STARTUP_BIAS_ENA |
+                                            WM8962_VMID_BUF_ENA,
+                                            WM8962_STARTUP_BIAS_ENA |
+                                            WM8962_VMID_BUF_ENA);
+
+                        /* Bias enable at 2*50k for ramp */
+                        snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
+                                            WM8962_VMID_SEL_MASK |
+                                            WM8962_BIAS_ENA,
+                                            WM8962_BIAS_ENA | 0x180);
+
+                        msleep(5);
+
+                        snd_soc_update_bits(codec, WM8962_CLOCKING2,
+                                            WM8962_CLKREG_OVD,
+                                            WM8962_CLKREG_OVD);
+
+                        wm8962_configure_bclk(codec);
+                }
+
+                /* VMID 2*250k */
+                snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
+                                    WM8962_VMID_SEL_MASK, 0x100);
+                break;
+
+        case SND_SOC_BIAS_OFF:
+                snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
+                                    WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
+
+                snd_soc_update_bits(codec, WM8962_ANTI_POP,
+                                    WM8962_STARTUP_BIAS_ENA |
+                                    WM8962_VMID_BUF_ENA, 0);
+
+                regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
+                                       wm8962->supplies);
+                break;
+        }
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+static const struct {
+        int rate;
+        int reg;
+} sr_vals[] = {
+        { 48000, 0 },
+        { 44100, 0 },
+        { 32000, 1 },
+        { 22050, 2 },
+        { 24000, 2 },
+        { 16000, 3 },
+        { 11025, 4 },
+        { 12000, 4 },
+        { 8000,  5 },
+        { 88200, 6 },
+        { 96000, 6 },
+};
+
+static const int sysclk_rates[] = {
+        64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
+};
+
+static int wm8962_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        int rate = params_rate(params);
+        int i;
+        int aif0 = 0;
+        int adctl3 = 0;
+        int clocking4 = 0;
+
+        wm8962->bclk = snd_soc_params_to_bclk(params);
+        wm8962->lrclk = params_rate(params);
+
+        for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
+                if (sr_vals[i].rate == rate) {
+                        adctl3 |= sr_vals[i].reg;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(sr_vals)) {
+                dev_err(codec->dev, "Unsupported rate %dHz\n", rate);
+                return -EINVAL;
+        }
+
+        if (rate % 8000 == 0)
+                adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
+
+        for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
+                if (sysclk_rates[i] == wm8962->sysclk_rate / rate) {
+                        clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(sysclk_rates)) {
+                dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
+                        wm8962->sysclk_rate / rate);
+                return -EINVAL;
+        }
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                aif0 |= 0x40;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                aif0 |= 0x80;
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                aif0 |= 0xc0;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
+                            WM8962_WL_MASK, aif0);
+        snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
+                            WM8962_SAMPLE_RATE_INT_MODE |
+                            WM8962_SAMPLE_RATE_MASK, adctl3);
+        snd_soc_update_bits(codec, WM8962_CLOCKING_4,
+                            WM8962_SYSCLK_RATE_MASK, clocking4);
+
+        wm8962_configure_bclk(codec);
+
+        return 0;
+}
+
+static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
+                                 unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        int src;
+
+        switch (clk_id) {
+        case WM8962_SYSCLK_MCLK:
+                wm8962->sysclk = WM8962_SYSCLK_MCLK;
+                src = 0;
+                break;
+        case WM8962_SYSCLK_FLL:
+                wm8962->sysclk = WM8962_SYSCLK_FLL;
+                src = 1 << WM8962_SYSCLK_SRC_SHIFT;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
+                            src);
+
+        wm8962->sysclk_rate = freq;
+
+        return 0;
+}
+
+static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        int aif0 = 0;
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_DSP_A:
+                aif0 |= WM8962_LRCLK_INV;
+        case SND_SOC_DAIFMT_DSP_B:
+                aif0 |= 3;
+
+                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+                case SND_SOC_DAIFMT_NB_NF:
+                case SND_SOC_DAIFMT_IB_NF:
+                        break;
+                default:
+                        return -EINVAL;
+                }
+                break;
+
+        case SND_SOC_DAIFMT_RIGHT_J:
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                aif0 |= 1;
+                break;
+        case SND_SOC_DAIFMT_I2S:
+                aif0 |= 2;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                aif0 |= WM8962_BCLK_INV;
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                aif0 |= WM8962_LRCLK_INV;
+                break;
+        case SND_SOC_DAIFMT_IB_IF:
+                aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                aif0 |= WM8962_MSTR;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
+                            WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
+                            WM8962_LRCLK_INV, aif0);
+
+        return 0;
+}
+
+struct _fll_div {
+        u16 fll_fratio;
+        u16 fll_outdiv;
+        u16 fll_refclk_div;
+        u16 n;
+        u16 theta;
+        u16 lambda;
+};
+
+/* The size in bits of the FLL divide multiplied by 10
+ * to allow rounding later */
+#define FIXED_FLL_SIZE ((1 << 16) * 10)
+
+static struct {
+        unsigned int min;
+        unsigned int max;
+        u16 fll_fratio;
+        int ratio;
+} fll_fratios[] = {
+        {       0,    64000, 4, 16 },
+        {   64000,   128000, 3,  8 },
+        {  128000,   256000, 2,  4 },
+        {  256000,  1000000, 1,  2 },
+        { 1000000, 13500000, 0,  1 },
+};
+
+static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
+                       unsigned int Fout)
+{
+        unsigned int target;
+        unsigned int div;
+        unsigned int fratio, gcd_fll;
+        int i;
+
+        /* Fref must be <=13.5MHz */
+        div = 1;
+        fll_div->fll_refclk_div = 0;
+        while ((Fref / div) > 13500000) {
+                div *= 2;
+                fll_div->fll_refclk_div++;
+
+                if (div > 4) {
+                        pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
+                               Fref);
+                        return -EINVAL;
+                }
+        }
+
+        pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
+
+        /* Apply the division for our remaining calculations */
+        Fref /= div;
+
+        /* Fvco should be 90-100MHz; don't check the upper bound */
+        div = 2;
+        while (Fout * div < 90000000) {
+                div++;
+                if (div > 64) {
+                        pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
+                               Fout);
+                        return -EINVAL;
+                }
+        }
+        target = Fout * div;
+        fll_div->fll_outdiv = div - 1;
+
+        pr_debug("FLL Fvco=%dHz\n", target);
+
+        /* Find an appropriate FLL_FRATIO and factor it out of the target */
+        for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
+                if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
+                        fll_div->fll_fratio = fll_fratios[i].fll_fratio;
+                        fratio = fll_fratios[i].ratio;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(fll_fratios)) {
+                pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
+                return -EINVAL;
+        }
+
+        fll_div->n = target / (fratio * Fref);
+
+        if (target % Fref == 0) {
+                fll_div->theta = 0;
+                fll_div->lambda = 0;
+        } else {
+                gcd_fll = gcd(target, fratio * Fref);
+
+                fll_div->theta = (target - (fll_div->n * fratio * Fref))
+                        / gcd_fll;
+                fll_div->lambda = (fratio * Fref) / gcd_fll;
+        }
+
+        pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
+                 fll_div->n, fll_div->theta, fll_div->lambda);
+        pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
+                 fll_div->fll_fratio, fll_div->fll_outdiv,
+                 fll_div->fll_refclk_div);
+
+        return 0;
+}
+
+static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
+                          unsigned int Fref, unsigned int Fout)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        struct _fll_div fll_div;
+        unsigned long timeout;
+        int ret;
+        int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
+
+        /* Any change? */
+        if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
+            Fout == wm8962->fll_fout)
+                return 0;
+
+        if (Fout == 0) {
+                dev_dbg(codec->dev, "FLL disabled\n");
+
+                wm8962->fll_fref = 0;
+                wm8962->fll_fout = 0;
+
+                snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
+                                    WM8962_FLL_ENA, 0);
+
+                return 0;
+        }
+
+        ret = fll_factors(&fll_div, Fref, Fout);
+        if (ret != 0)
+                return ret;
+
+        switch (fll_id) {
+        case WM8962_FLL_MCLK:
+        case WM8962_FLL_BCLK:
+        case WM8962_FLL_OSC:
+                fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
+                break;
+        case WM8962_FLL_INT:
+                snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
+                                    WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
+                snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
+                                    WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
+                break;
+        default:
+                dev_err(codec->dev, "Unknown FLL source %d\n", ret);
+                return -EINVAL;
+        }
+
+        if (fll_div.theta || fll_div.lambda)
+                fll1 |= WM8962_FLL_FRAC;
+
+        /* Stop the FLL while we reconfigure */
+        snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
+
+        snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
+                            WM8962_FLL_OUTDIV_MASK |
+                            WM8962_FLL_REFCLK_DIV_MASK,
+                            (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
+                            (fll_div.fll_refclk_div));
+
+        snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
+                            WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
+
+        snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
+        snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
+        snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
+
+        snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
+                            WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
+                            WM8962_FLL_ENA, fll1);
+
+        dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
+
+        /* This should be a massive overestimate */
+        timeout = msecs_to_jiffies(1);
+
+        wait_for_completion_timeout(&wm8962->fll_lock, timeout);
+
+        wm8962->fll_fref = Fref;
+        wm8962->fll_fout = Fout;
+        wm8962->fll_src = source;
+
+        return 0;
+}
+
+static int wm8962_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        int val;
+
+        if (mute)
+                val = WM8962_DAC_MUTE;
+        else
+                val = 0;
+
+        return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
+                                   WM8962_DAC_MUTE, val);
+}
+
+#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
+
+#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops wm8962_dai_ops = {
+        .hw_params = wm8962_hw_params,
+        .set_sysclk = wm8962_set_dai_sysclk,
+        .set_fmt = wm8962_set_dai_fmt,
+        .digital_mute = wm8962_mute,
+};
+
+static struct snd_soc_dai_driver wm8962_dai = {
+        .name = "wm8962",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = WM8962_RATES,
+                .formats = WM8962_FORMATS,
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = WM8962_RATES,
+                .formats = WM8962_FORMATS,
+        },
+        .ops = &wm8962_dai_ops,
+        .symmetric_rates = 1,
+};
+
+static void wm8962_mic_work(struct work_struct *work)
+{
+        struct wm8962_priv *wm8962 = container_of(work,
+                                                  struct wm8962_priv,
+                                                  mic_work.work);
+        struct snd_soc_codec *codec = wm8962->codec;
+        int status = 0;
+        int irq_pol = 0;
+        int reg;
+
+        reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
+
+        if (reg & WM8962_MICDET_STS) {
+                status |= SND_JACK_MICROPHONE;
+                irq_pol |= WM8962_MICD_IRQ_POL;
+        }
+
+        if (reg & WM8962_MICSHORT_STS) {
+                status |= SND_JACK_BTN_0;
+                irq_pol |= WM8962_MICSCD_IRQ_POL;
+        }
+
+        snd_soc_jack_report(wm8962->jack, status,
+                            SND_JACK_MICROPHONE | SND_JACK_BTN_0);
+
+        snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
+                            WM8962_MICSCD_IRQ_POL |
+                            WM8962_MICD_IRQ_POL, irq_pol);
+}
+
+static irqreturn_t wm8962_irq(int irq, void *data)
+{
+        struct snd_soc_codec *codec = data;
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        int mask;
+        int active;
+
+        mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2_MASK);
+
+        active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
+        active &= ~mask;
+
+        if (active & WM8962_FLL_LOCK_EINT) {
+                dev_dbg(codec->dev, "FLL locked\n");
+                complete(&wm8962->fll_lock);
+        }
+
+        if (active & WM8962_FIFOS_ERR_EINT)
+                dev_err(codec->dev, "FIFO error\n");
+
+        if (active & WM8962_TEMP_SHUT_EINT)
+                dev_crit(codec->dev, "Thermal shutdown\n");
+
+        if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
+                dev_dbg(codec->dev, "Microphone event detected\n");
+
+#ifndef CONFIG_SND_SOC_WM8962_MODULE
+                trace_snd_soc_jack_irq(dev_name(codec->dev));
+#endif
+
+                pm_wakeup_event(codec->dev, 300);
+
+                schedule_delayed_work(&wm8962->mic_work,
+                                      msecs_to_jiffies(250));
+        }
+
+        /* Acknowledge the interrupts */
+        snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active);
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
+ *
+ * @codec:  WM8962 codec
+ * @jack:   jack to report detection events on
+ *
+ * Enable microphone detection via IRQ on the WM8962.  If GPIOs are
+ * being used to bring out signals to the processor then only platform
+ * data configuration is needed for WM8962 and processor GPIOs should
+ * be configured using snd_soc_jack_add_gpios() instead.
+ *
+ * If no jack is supplied detection will be disabled.
+ */
+int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        int irq_mask, enable;
+
+        wm8962->jack = jack;
+        if (jack) {
+                irq_mask = 0;
+                enable = WM8962_MICDET_ENA;
+        } else {
+                irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
+                enable = 0;
+        }
+
+        snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
+                            WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
+        snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
+                            WM8962_MICDET_ENA, enable);
+
+        /* Send an initial empty report */
+        snd_soc_jack_report(wm8962->jack, 0,
+                            SND_JACK_MICROPHONE | SND_JACK_BTN_0);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(wm8962_mic_detect);
+
+#ifdef CONFIG_PM
+static int wm8962_resume(struct snd_soc_codec *codec)
+{
+        u16 *reg_cache = codec->reg_cache;
+        int i;
+
+        /* Restore the registers */
+        for (i = 1; i < codec->driver->reg_cache_size; i++) {
+                switch (i) {
+                case WM8962_SOFTWARE_RESET:
+                        continue;
+                default:
+                        break;
+                }
+
+                if (reg_cache[i] != wm8962_reg[i])
+                        snd_soc_write(codec, i, reg_cache[i]);
+        }
+
+        return 0;
+}
+#else
+#define wm8962_resume NULL
+#endif
+
+#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
+static int beep_rates[] = {
+        500, 1000, 2000, 4000,
+};
+
+static void wm8962_beep_work(struct work_struct *work)
+{
+        struct wm8962_priv *wm8962 =
+                container_of(work, struct wm8962_priv, beep_work);
+        struct snd_soc_codec *codec = wm8962->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int i;
+        int reg = 0;
+        int best = 0;
+
+        if (wm8962->beep_rate) {
+                for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
+                        if (abs(wm8962->beep_rate - beep_rates[i]) <
+                            abs(wm8962->beep_rate - beep_rates[best]))
+                                best = i;
+                }
+
+                dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
+                        beep_rates[best], wm8962->beep_rate);
+
+                reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
+
+                snd_soc_dapm_enable_pin(dapm, "Beep");
+        } else {
+                dev_dbg(codec->dev, "Disabling beep\n");
+                snd_soc_dapm_disable_pin(dapm, "Beep");
+        }
+
+        snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
+                            WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
+
+        snd_soc_dapm_sync(dapm);
+}
+
+/* For usability define a way of injecting beep events for the device -
+ * many systems will not have a keyboard.
+ */
+static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
+                             unsigned int code, int hz)
+{
+        struct snd_soc_codec *codec = input_get_drvdata(dev);
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+
+        dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
+
+        switch (code) {
+        case SND_BELL:
+                if (hz)
+                        hz = 1000;
+        case SND_TONE:
+                break;
+        default:
+                return -1;
+        }
+
+        /* Kick the beep from a workqueue */
+        wm8962->beep_rate = hz;
+        schedule_work(&wm8962->beep_work);
+        return 0;
+}
+
+static ssize_t wm8962_beep_set(struct device *dev,
+                               struct device_attribute *attr,
+                               const char *buf, size_t count)
+{
+        struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
+        long int time;
+        int ret;
+
+        ret = strict_strtol(buf, 10, &time);
+        if (ret != 0)
+                return ret;
+
+        input_event(wm8962->beep, EV_SND, SND_TONE, time);
+
+        return count;
+}
+
+static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
+
+static void wm8962_init_beep(struct snd_soc_codec *codec)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        wm8962->beep = input_allocate_device();
+        if (!wm8962->beep) {
+                dev_err(codec->dev, "Failed to allocate beep device\n");
+                return;
+        }
+
+        INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
+        wm8962->beep_rate = 0;
+
+        wm8962->beep->name = "WM8962 Beep Generator";
+        wm8962->beep->phys = dev_name(codec->dev);
+        wm8962->beep->id.bustype = BUS_I2C;
+
+        wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
+        wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
+        wm8962->beep->event = wm8962_beep_event;
+        wm8962->beep->dev.parent = codec->dev;
+        input_set_drvdata(wm8962->beep, codec);
+
+        ret = input_register_device(wm8962->beep);
+        if (ret != 0) {
+                input_free_device(wm8962->beep);
+                wm8962->beep = NULL;
+                dev_err(codec->dev, "Failed to register beep device\n");
+        }
+
+        ret = device_create_file(codec->dev, &dev_attr_beep);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to create keyclick file: %d\n",
+                        ret);
+        }
+}
+
+static void wm8962_free_beep(struct snd_soc_codec *codec)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+
+        device_remove_file(codec->dev, &dev_attr_beep);
+        input_unregister_device(wm8962->beep);
+        cancel_work_sync(&wm8962->beep_work);
+        wm8962->beep = NULL;
+
+        snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
+}
+#else
+static void wm8962_init_beep(struct snd_soc_codec *codec)
+{
+}
+
+static void wm8962_free_beep(struct snd_soc_codec *codec)
+{
+}
+#endif
+
+static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
+{
+        int mask = 0;
+        int val = 0;
+
+        /* Some of the GPIOs are behind MFP configuration and need to
+         * be put into GPIO mode. */
+        switch (gpio) {
+        case 2:
+                mask = WM8962_CLKOUT2_SEL_MASK;
+                val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
+                break;
+        case 3:
+                mask = WM8962_CLKOUT3_SEL_MASK;
+                val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
+                break;
+        default:
+                break;
+        }
+
+        if (mask)
+                snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
+                                    mask, val);
+}
+
+#ifdef CONFIG_GPIOLIB
+static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
+{
+        return container_of(chip, struct wm8962_priv, gpio_chip);
+}
+
+static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
+        struct snd_soc_codec *codec = wm8962->codec;
+
+        /* The WM8962 GPIOs aren't linearly numbered.  For simplicity
+         * we export linear numbers and error out if the unsupported
+         * ones are requsted.
+         */
+        switch (offset + 1) {
+        case 2:
+        case 3:
+        case 5:
+        case 6:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        wm8962_set_gpio_mode(codec, offset + 1);
+
+        return 0;
+}
+
+static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
+        struct snd_soc_codec *codec = wm8962->codec;
+
+        snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
+                            WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
+}
+
+static int wm8962_gpio_direction_out(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
+        struct snd_soc_codec *codec = wm8962->codec;
+        int val;
+
+        /* Force function 1 (logic output) */
+        val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
+
+        return snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
+                                   WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
+}
+
+static struct gpio_chip wm8962_template_chip = {
+        .label                  = "wm8962",
+        .owner                  = THIS_MODULE,
+        .request                = wm8962_gpio_request,
+        .direction_output       = wm8962_gpio_direction_out,
+        .set                    = wm8962_gpio_set,
+        .can_sleep              = 1,
+};
+
+static void wm8962_init_gpio(struct snd_soc_codec *codec)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
+        int ret;
+
+        wm8962->gpio_chip = wm8962_template_chip;
+        wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
+        wm8962->gpio_chip.dev = codec->dev;
+
+        if (pdata && pdata->gpio_base)
+                wm8962->gpio_chip.base = pdata->gpio_base;
+        else
+                wm8962->gpio_chip.base = -1;
+
+        ret = gpiochip_add(&wm8962->gpio_chip);
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
+}
+
+static void wm8962_free_gpio(struct snd_soc_codec *codec)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        ret = gpiochip_remove(&wm8962->gpio_chip);
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
+}
+#else
+static void wm8962_init_gpio(struct snd_soc_codec *codec)
+{
+}
+
+static void wm8962_free_gpio(struct snd_soc_codec *codec)
+{
+}
+#endif
+
+static int wm8962_probe(struct snd_soc_codec *codec)
+{
+        int ret;
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
+        struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
+                                              dev);
+        u16 *reg_cache = codec->reg_cache;
+        int i, trigger, irq_pol;
+        bool dmicclk, dmicdat;
+
+        wm8962->codec = codec;
+        INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
+        init_completion(&wm8962->fll_lock);
+
+        codec->cache_sync = 1;
+        codec->dapm.idle_bias_off = 1;
+
+        ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                goto err;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
+                wm8962->supplies[i].supply = wm8962_supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
+                                 wm8962->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                goto err;
+        }
+
+        wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
+        wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
+        wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
+        wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
+        wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
+        wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
+        wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
+        wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
+
+        /* This should really be moved into the regulator core */
+        for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
+                ret = regulator_register_notifier(wm8962->supplies[i].consumer,
+                                                  &wm8962->disable_nb[i]);
+                if (ret != 0) {
+                        dev_err(codec->dev,
+                                "Failed to register regulator notifier: %d\n",
+                                ret);
+                }
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
+                                    wm8962->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                goto err_get;
+        }
+
+        ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read ID register\n");
+                goto err_enable;
+        }
+        if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
+                dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
+                        ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
+                ret = -EINVAL;
+                goto err_enable;
+        }
+
+        ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read device revision: %d\n",
+                        ret);
+                goto err_enable;
+        }
+        
+        dev_info(codec->dev, "customer id %x revision %c\n",
+                 (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
+                 ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
+                 + 'A');
+
+        ret = wm8962_reset(codec);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to issue reset\n");
+                goto err_enable;
+        }
+
+        /* SYSCLK defaults to on; make sure it is off so we can safely
+         * write to registers if the device is declocked.
+         */
+        snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
+
+        regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
+
+        if (pdata) {
+                /* Apply static configuration for GPIOs */
+                for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
+                        if (pdata->gpio_init[i]) {
+                                wm8962_set_gpio_mode(codec, i + 1);
+                                snd_soc_write(codec, 0x200 + i,
+                                              pdata->gpio_init[i] & 0xffff);
+                        }
+
+                /* Put the speakers into mono mode? */
+                if (pdata->spk_mono)
+                        reg_cache[WM8962_CLASS_D_CONTROL_2]
+                                |= WM8962_SPK_MONO;
+
+                /* Micbias setup, detection enable and detection
+                 * threasholds. */
+                if (pdata->mic_cfg)
+                        snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
+                                            WM8962_MICDET_ENA |
+                                            WM8962_MICDET_THR_MASK |
+                                            WM8962_MICSHORT_THR_MASK |
+                                            WM8962_MICBIAS_LVL,
+                                            pdata->mic_cfg);
+        }
+
+        /* Latch volume update bits */
+        snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
+                            WM8962_IN_VU, WM8962_IN_VU);
+        snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
+                            WM8962_IN_VU, WM8962_IN_VU);
+        snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
+                            WM8962_ADC_VU, WM8962_ADC_VU);
+        snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
+                            WM8962_ADC_VU, WM8962_ADC_VU);
+        snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
+                            WM8962_DAC_VU, WM8962_DAC_VU);
+        snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
+                            WM8962_DAC_VU, WM8962_DAC_VU);
+        snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
+                            WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
+        snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
+                            WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
+        snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
+                            WM8962_HPOUT_VU, WM8962_HPOUT_VU);
+        snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
+                            WM8962_HPOUT_VU, WM8962_HPOUT_VU);
+
+        wm8962_add_widgets(codec);
+
+        /* Save boards having to disable DMIC when not in use */
+        dmicclk = false;
+        dmicdat = false;
+        for (i = 0; i < WM8962_MAX_GPIO; i++) {
+                switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
+                        & WM8962_GP2_FN_MASK) {
+                case WM8962_GPIO_FN_DMICCLK:
+                        dmicclk = true;
+                        break;
+                case WM8962_GPIO_FN_DMICDAT:
+                        dmicdat = true;
+                        break;
+                default:
+                        break;
+                }
+        }
+        if (!dmicclk || !dmicdat) {
+                dev_dbg(codec->dev, "DMIC not in use, disabling\n");
+                snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
+        }
+        if (dmicclk != dmicdat)
+                dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
+
+        wm8962_init_beep(codec);
+        wm8962_init_gpio(codec);
+
+        if (i2c->irq) {
+                if (pdata && pdata->irq_active_low) {
+                        trigger = IRQF_TRIGGER_LOW;
+                        irq_pol = WM8962_IRQ_POL;
+                } else {
+                        trigger = IRQF_TRIGGER_HIGH;
+                        irq_pol = 0;
+                }
+
+                snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
+                                    WM8962_IRQ_POL, irq_pol);
+
+                ret = request_threaded_irq(i2c->irq, NULL, wm8962_irq,
+                                           trigger | IRQF_ONESHOT,
+                                           "wm8962", codec);
+                if (ret != 0) {
+                        dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
+                                i2c->irq, ret);
+                        /* Non-fatal */
+                } else {
+                        /* Enable some IRQs by default */
+                        snd_soc_update_bits(codec,
+                                            WM8962_INTERRUPT_STATUS_2_MASK,
+                                            WM8962_FLL_LOCK_EINT |
+                                            WM8962_TEMP_SHUT_EINT |
+                                            WM8962_FIFOS_ERR_EINT, 0);
+                }
+        }
+
+        return 0;
+
+err_enable:
+        regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
+err_get:
+        regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
+err:
+        return ret;
+}
+
+static int wm8962_remove(struct snd_soc_codec *codec)
+{
+        struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+        struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
+                                              dev);
+        int i;
+
+        if (i2c->irq)
+                free_irq(i2c->irq, codec);
+
+        cancel_delayed_work_sync(&wm8962->mic_work);
+
+        wm8962_free_gpio(codec);
+        wm8962_free_beep(codec);
+        for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
+                regulator_unregister_notifier(wm8962->supplies[i].consumer,
+                                              &wm8962->disable_nb[i]);
+        regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
+
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
+        .probe =        wm8962_probe,
+        .remove =       wm8962_remove,
+        .resume =       wm8962_resume,
+        .set_bias_level = wm8962_set_bias_level,
+        .reg_cache_size = WM8962_MAX_REGISTER + 1,
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8962_reg,
+        .volatile_register = wm8962_volatile_register,
+        .readable_register = wm8962_readable_register,
+        .set_pll = wm8962_set_fll,
+};
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8962_priv *wm8962;
+        int ret;
+
+        wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
+        if (wm8962 == NULL)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, wm8962);
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                                     &soc_codec_dev_wm8962, &wm8962_dai, 1);
+        if (ret < 0)
+                kfree(wm8962);
+
+        return ret;
+}
+
+static __devexit int wm8962_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id wm8962_i2c_id[] = {
+        { "wm8962", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
+
+static struct i2c_driver wm8962_i2c_driver = {
+        .driver = {
+                .name = "wm8962",
+                .owner = THIS_MODULE,
+        },
+        .probe =    wm8962_i2c_probe,
+        .remove =   __devexit_p(wm8962_i2c_remove),
+        .id_table = wm8962_i2c_id,
+};
+#endif
+
+static int __init wm8962_modinit(void)
+{
+        int ret;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8962_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
+                       ret);
+        }
+#endif
+        return 0;
+}
+module_init(wm8962_modinit);
+
+static void __exit wm8962_exit(void)
+{
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&wm8962_i2c_driver);
+#endif
+}
+module_exit(wm8962_exit);
+
+MODULE_DESCRIPTION("ASoC WM8962 driver");
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8962.h b/sound/soc/codecs/wm8962.h
new file mode 100644
index 000000000000..a1a5d5294c19
--- /dev/null
+++ b/sound/soc/codecs/wm8962.h
@@ -0,0 +1,3780 @@
+/*
+ * wm8962.h  --  WM8962 ASoC driver
+ *
+ * Copyright 2010 Wolfson Microelectronics, plc
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8962_H
+#define _WM8962_H
+
+#include <asm/types.h>
+#include <sound/soc.h>
+
+#define WM8962_SYSCLK_MCLK 1
+#define WM8962_SYSCLK_FLL  2
+#define WM8962_SYSCLK_PLL3 3
+
+#define WM8962_FLL  1
+
+#define WM8962_FLL_MCLK 1
+#define WM8962_FLL_BCLK 2
+#define WM8962_FLL_OSC  3
+#define WM8962_FLL_INT  4
+
+/*
+ * Register values.
+ */
+#define WM8962_LEFT_INPUT_VOLUME                0x00
+#define WM8962_RIGHT_INPUT_VOLUME               0x01
+#define WM8962_HPOUTL_VOLUME                    0x02
+#define WM8962_HPOUTR_VOLUME                    0x03
+#define WM8962_CLOCKING1                        0x04
+#define WM8962_ADC_DAC_CONTROL_1                0x05
+#define WM8962_ADC_DAC_CONTROL_2                0x06
+#define WM8962_AUDIO_INTERFACE_0                0x07
+#define WM8962_CLOCKING2                        0x08
+#define WM8962_AUDIO_INTERFACE_1                0x09
+#define WM8962_LEFT_DAC_VOLUME                  0x0A
+#define WM8962_RIGHT_DAC_VOLUME                 0x0B
+#define WM8962_AUDIO_INTERFACE_2                0x0E
+#define WM8962_SOFTWARE_RESET                   0x0F
+#define WM8962_ALC1                             0x11
+#define WM8962_ALC2                             0x12
+#define WM8962_ALC3                             0x13
+#define WM8962_NOISE_GATE                       0x14
+#define WM8962_LEFT_ADC_VOLUME                  0x15
+#define WM8962_RIGHT_ADC_VOLUME                 0x16
+#define WM8962_ADDITIONAL_CONTROL_1             0x17
+#define WM8962_ADDITIONAL_CONTROL_2             0x18
+#define WM8962_PWR_MGMT_1                       0x19
+#define WM8962_PWR_MGMT_2                       0x1A
+#define WM8962_ADDITIONAL_CONTROL_3             0x1B
+#define WM8962_ANTI_POP                         0x1C
+#define WM8962_CLOCKING_3                       0x1E
+#define WM8962_INPUT_MIXER_CONTROL_1            0x1F
+#define WM8962_LEFT_INPUT_MIXER_VOLUME          0x20
+#define WM8962_RIGHT_INPUT_MIXER_VOLUME         0x21
+#define WM8962_INPUT_MIXER_CONTROL_2            0x22
+#define WM8962_INPUT_BIAS_CONTROL               0x23
+#define WM8962_LEFT_INPUT_PGA_CONTROL           0x25
+#define WM8962_RIGHT_INPUT_PGA_CONTROL          0x26
+#define WM8962_SPKOUTL_VOLUME                   0x28
+#define WM8962_SPKOUTR_VOLUME                   0x29
+#define WM8962_THERMAL_SHUTDOWN_STATUS          0x2F
+#define WM8962_ADDITIONAL_CONTROL_4             0x30
+#define WM8962_CLASS_D_CONTROL_1                0x31
+#define WM8962_CLASS_D_CONTROL_2                0x33
+#define WM8962_CLOCKING_4                       0x38
+#define WM8962_DAC_DSP_MIXING_1                 0x39
+#define WM8962_DAC_DSP_MIXING_2                 0x3A
+#define WM8962_DC_SERVO_0                       0x3C
+#define WM8962_DC_SERVO_1                       0x3D
+#define WM8962_DC_SERVO_4                       0x40
+#define WM8962_DC_SERVO_6                       0x42
+#define WM8962_ANALOGUE_PGA_BIAS                0x44
+#define WM8962_ANALOGUE_HP_0                    0x45
+#define WM8962_ANALOGUE_HP_2                    0x47
+#define WM8962_CHARGE_PUMP_1                    0x48
+#define WM8962_CHARGE_PUMP_B                    0x52
+#define WM8962_WRITE_SEQUENCER_CONTROL_1        0x57
+#define WM8962_WRITE_SEQUENCER_CONTROL_2        0x5A
+#define WM8962_WRITE_SEQUENCER_CONTROL_3        0x5D
+#define WM8962_CONTROL_INTERFACE                0x5E
+#define WM8962_MIXER_ENABLES                    0x63
+#define WM8962_HEADPHONE_MIXER_1                0x64
+#define WM8962_HEADPHONE_MIXER_2                0x65
+#define WM8962_HEADPHONE_MIXER_3                0x66
+#define WM8962_HEADPHONE_MIXER_4                0x67
+#define WM8962_SPEAKER_MIXER_1                  0x69
+#define WM8962_SPEAKER_MIXER_2                  0x6A
+#define WM8962_SPEAKER_MIXER_3                  0x6B
+#define WM8962_SPEAKER_MIXER_4                  0x6C
+#define WM8962_SPEAKER_MIXER_5                  0x6D
+#define WM8962_BEEP_GENERATOR_1                 0x6E
+#define WM8962_OSCILLATOR_TRIM_3                0x73
+#define WM8962_OSCILLATOR_TRIM_4                0x74
+#define WM8962_OSCILLATOR_TRIM_7                0x77
+#define WM8962_ANALOGUE_CLOCKING1               0x7C
+#define WM8962_ANALOGUE_CLOCKING2               0x7D
+#define WM8962_ANALOGUE_CLOCKING3               0x7E
+#define WM8962_PLL_SOFTWARE_RESET               0x7F
+#define WM8962_PLL2                             0x81
+#define WM8962_PLL_4                            0x83
+#define WM8962_PLL_9                            0x88
+#define WM8962_PLL_10                           0x89
+#define WM8962_PLL_11                           0x8A
+#define WM8962_PLL_12                           0x8B
+#define WM8962_PLL_13                           0x8C
+#define WM8962_PLL_14                           0x8D
+#define WM8962_PLL_15                           0x8E
+#define WM8962_PLL_16                           0x8F
+#define WM8962_FLL_CONTROL_1                    0x9B
+#define WM8962_FLL_CONTROL_2                    0x9C
+#define WM8962_FLL_CONTROL_3                    0x9D
+#define WM8962_FLL_CONTROL_5                    0x9F
+#define WM8962_FLL_CONTROL_6                    0xA0
+#define WM8962_FLL_CONTROL_7                    0xA1
+#define WM8962_FLL_CONTROL_8                    0xA2
+#define WM8962_GENERAL_TEST_1                   0xFC
+#define WM8962_DF1                              0x100
+#define WM8962_DF2                              0x101
+#define WM8962_DF3                              0x102
+#define WM8962_DF4                              0x103
+#define WM8962_DF5                              0x104
+#define WM8962_DF6                              0x105
+#define WM8962_DF7                              0x106
+#define WM8962_LHPF1                            0x108
+#define WM8962_LHPF2                            0x109
+#define WM8962_THREED1                          0x10C
+#define WM8962_THREED2                          0x10D
+#define WM8962_THREED3                          0x10E
+#define WM8962_THREED4                          0x10F
+#define WM8962_DRC_1                            0x114
+#define WM8962_DRC_2                            0x115
+#define WM8962_DRC_3                            0x116
+#define WM8962_DRC_4                            0x117
+#define WM8962_DRC_5                            0x118
+#define WM8962_TLOOPBACK                        0x11D
+#define WM8962_EQ1                              0x14F
+#define WM8962_EQ2                              0x150
+#define WM8962_EQ3                              0x151
+#define WM8962_EQ4                              0x152
+#define WM8962_EQ5                              0x153
+#define WM8962_EQ6                              0x154
+#define WM8962_EQ7                              0x155
+#define WM8962_EQ8                              0x156
+#define WM8962_EQ9                              0x157
+#define WM8962_EQ10                             0x158
+#define WM8962_EQ11                             0x159
+#define WM8962_EQ12                             0x15A
+#define WM8962_EQ13                             0x15B
+#define WM8962_EQ14                             0x15C
+#define WM8962_EQ15                             0x15D
+#define WM8962_EQ16                             0x15E
+#define WM8962_EQ17                             0x15F
+#define WM8962_EQ18                             0x160
+#define WM8962_EQ19                             0x161
+#define WM8962_EQ20                             0x162
+#define WM8962_EQ21                             0x163
+#define WM8962_EQ22                             0x164
+#define WM8962_EQ23                             0x165
+#define WM8962_EQ24                             0x166
+#define WM8962_EQ25                             0x167
+#define WM8962_EQ26                             0x168
+#define WM8962_EQ27                             0x169
+#define WM8962_EQ28                             0x16A
+#define WM8962_EQ29                             0x16B
+#define WM8962_EQ30                             0x16C
+#define WM8962_EQ31                             0x16D
+#define WM8962_EQ32                             0x16E
+#define WM8962_EQ33                             0x16F
+#define WM8962_EQ34                             0x170
+#define WM8962_EQ35                             0x171
+#define WM8962_EQ36                             0x172
+#define WM8962_EQ37                             0x173
+#define WM8962_EQ38                             0x174
+#define WM8962_EQ39                             0x175
+#define WM8962_EQ40                             0x176
+#define WM8962_EQ41                             0x177
+#define WM8962_GPIO_BASE                        0x200
+#define WM8962_GPIO_2                           0x201
+#define WM8962_GPIO_3                           0x202
+#define WM8962_GPIO_5                           0x204
+#define WM8962_GPIO_6                           0x205
+#define WM8962_INTERRUPT_STATUS_1               0x230
+#define WM8962_INTERRUPT_STATUS_2               0x231
+#define WM8962_INTERRUPT_STATUS_1_MASK          0x238
+#define WM8962_INTERRUPT_STATUS_2_MASK          0x239
+#define WM8962_INTERRUPT_CONTROL                0x240
+#define WM8962_IRQ_DEBOUNCE                     0x248
+#define WM8962_MICINT_SOURCE_POL                0x24A
+#define WM8962_DSP2_POWER_MANAGEMENT            0x300
+#define WM8962_DSP2_EXECCONTROL                 0x40D
+#define WM8962_WRITE_SEQUENCER_0                0x1000
+#define WM8962_WRITE_SEQUENCER_1                0x1001
+#define WM8962_WRITE_SEQUENCER_2                0x1002
+#define WM8962_WRITE_SEQUENCER_3                0x1003
+#define WM8962_WRITE_SEQUENCER_4                0x1004
+#define WM8962_WRITE_SEQUENCER_5                0x1005
+#define WM8962_WRITE_SEQUENCER_6                0x1006
+#define WM8962_WRITE_SEQUENCER_7                0x1007
+#define WM8962_WRITE_SEQUENCER_8                0x1008
+#define WM8962_WRITE_SEQUENCER_9                0x1009
+#define WM8962_WRITE_SEQUENCER_10               0x100A
+#define WM8962_WRITE_SEQUENCER_11               0x100B
+#define WM8962_WRITE_SEQUENCER_12               0x100C
+#define WM8962_WRITE_SEQUENCER_13               0x100D
+#define WM8962_WRITE_SEQUENCER_14               0x100E
+#define WM8962_WRITE_SEQUENCER_15               0x100F
+#define WM8962_WRITE_SEQUENCER_16               0x1010
+#define WM8962_WRITE_SEQUENCER_17               0x1011
+#define WM8962_WRITE_SEQUENCER_18               0x1012
+#define WM8962_WRITE_SEQUENCER_19               0x1013
+#define WM8962_WRITE_SEQUENCER_20               0x1014
+#define WM8962_WRITE_SEQUENCER_21               0x1015
+#define WM8962_WRITE_SEQUENCER_22               0x1016
+#define WM8962_WRITE_SEQUENCER_23               0x1017
+#define WM8962_WRITE_SEQUENCER_24               0x1018
+#define WM8962_WRITE_SEQUENCER_25               0x1019
+#define WM8962_WRITE_SEQUENCER_26               0x101A
+#define WM8962_WRITE_SEQUENCER_27               0x101B
+#define WM8962_WRITE_SEQUENCER_28               0x101C
+#define WM8962_WRITE_SEQUENCER_29               0x101D
+#define WM8962_WRITE_SEQUENCER_30               0x101E
+#define WM8962_WRITE_SEQUENCER_31               0x101F
+#define WM8962_WRITE_SEQUENCER_32               0x1020
+#define WM8962_WRITE_SEQUENCER_33               0x1021
+#define WM8962_WRITE_SEQUENCER_34               0x1022
+#define WM8962_WRITE_SEQUENCER_35               0x1023
+#define WM8962_WRITE_SEQUENCER_36               0x1024
+#define WM8962_WRITE_SEQUENCER_37               0x1025
+#define WM8962_WRITE_SEQUENCER_38               0x1026
+#define WM8962_WRITE_SEQUENCER_39               0x1027
+#define WM8962_WRITE_SEQUENCER_40               0x1028
+#define WM8962_WRITE_SEQUENCER_41               0x1029
+#define WM8962_WRITE_SEQUENCER_42               0x102A
+#define WM8962_WRITE_SEQUENCER_43               0x102B
+#define WM8962_WRITE_SEQUENCER_44               0x102C
+#define WM8962_WRITE_SEQUENCER_45               0x102D
+#define WM8962_WRITE_SEQUENCER_46               0x102E
+#define WM8962_WRITE_SEQUENCER_47               0x102F
+#define WM8962_WRITE_SEQUENCER_48               0x1030
+#define WM8962_WRITE_SEQUENCER_49               0x1031
+#define WM8962_WRITE_SEQUENCER_50               0x1032
+#define WM8962_WRITE_SEQUENCER_51               0x1033
+#define WM8962_WRITE_SEQUENCER_52               0x1034
+#define WM8962_WRITE_SEQUENCER_53               0x1035
+#define WM8962_WRITE_SEQUENCER_54               0x1036
+#define WM8962_WRITE_SEQUENCER_55               0x1037
+#define WM8962_WRITE_SEQUENCER_56               0x1038
+#define WM8962_WRITE_SEQUENCER_57               0x1039
+#define WM8962_WRITE_SEQUENCER_58               0x103A
+#define WM8962_WRITE_SEQUENCER_59               0x103B
+#define WM8962_WRITE_SEQUENCER_60               0x103C
+#define WM8962_WRITE_SEQUENCER_61               0x103D
+#define WM8962_WRITE_SEQUENCER_62               0x103E
+#define WM8962_WRITE_SEQUENCER_63               0x103F
+#define WM8962_WRITE_SEQUENCER_64               0x1040
+#define WM8962_WRITE_SEQUENCER_65               0x1041
+#define WM8962_WRITE_SEQUENCER_66               0x1042
+#define WM8962_WRITE_SEQUENCER_67               0x1043
+#define WM8962_WRITE_SEQUENCER_68               0x1044
+#define WM8962_WRITE_SEQUENCER_69               0x1045
+#define WM8962_WRITE_SEQUENCER_70               0x1046
+#define WM8962_WRITE_SEQUENCER_71               0x1047
+#define WM8962_WRITE_SEQUENCER_72               0x1048
+#define WM8962_WRITE_SEQUENCER_73               0x1049
+#define WM8962_WRITE_SEQUENCER_74               0x104A
+#define WM8962_WRITE_SEQUENCER_75               0x104B
+#define WM8962_WRITE_SEQUENCER_76               0x104C
+#define WM8962_WRITE_SEQUENCER_77               0x104D
+#define WM8962_WRITE_SEQUENCER_78               0x104E
+#define WM8962_WRITE_SEQUENCER_79               0x104F
+#define WM8962_WRITE_SEQUENCER_80               0x1050
+#define WM8962_WRITE_SEQUENCER_81               0x1051
+#define WM8962_WRITE_SEQUENCER_82               0x1052
+#define WM8962_WRITE_SEQUENCER_83               0x1053
+#define WM8962_WRITE_SEQUENCER_84               0x1054
+#define WM8962_WRITE_SEQUENCER_85               0x1055
+#define WM8962_WRITE_SEQUENCER_86               0x1056
+#define WM8962_WRITE_SEQUENCER_87               0x1057
+#define WM8962_WRITE_SEQUENCER_88               0x1058
+#define WM8962_WRITE_SEQUENCER_89               0x1059
+#define WM8962_WRITE_SEQUENCER_90               0x105A
+#define WM8962_WRITE_SEQUENCER_91               0x105B
+#define WM8962_WRITE_SEQUENCER_92               0x105C
+#define WM8962_WRITE_SEQUENCER_93               0x105D
+#define WM8962_WRITE_SEQUENCER_94               0x105E
+#define WM8962_WRITE_SEQUENCER_95               0x105F
+#define WM8962_WRITE_SEQUENCER_96               0x1060
+#define WM8962_WRITE_SEQUENCER_97               0x1061
+#define WM8962_WRITE_SEQUENCER_98               0x1062
+#define WM8962_WRITE_SEQUENCER_99               0x1063
+#define WM8962_WRITE_SEQUENCER_100              0x1064
+#define WM8962_WRITE_SEQUENCER_101              0x1065
+#define WM8962_WRITE_SEQUENCER_102              0x1066
+#define WM8962_WRITE_SEQUENCER_103              0x1067
+#define WM8962_WRITE_SEQUENCER_104              0x1068
+#define WM8962_WRITE_SEQUENCER_105              0x1069
+#define WM8962_WRITE_SEQUENCER_106              0x106A
+#define WM8962_WRITE_SEQUENCER_107              0x106B
+#define WM8962_WRITE_SEQUENCER_108              0x106C
+#define WM8962_WRITE_SEQUENCER_109              0x106D
+#define WM8962_WRITE_SEQUENCER_110              0x106E
+#define WM8962_WRITE_SEQUENCER_111              0x106F
+#define WM8962_WRITE_SEQUENCER_112              0x1070
+#define WM8962_WRITE_SEQUENCER_113              0x1071
+#define WM8962_WRITE_SEQUENCER_114              0x1072
+#define WM8962_WRITE_SEQUENCER_115              0x1073
+#define WM8962_WRITE_SEQUENCER_116              0x1074
+#define WM8962_WRITE_SEQUENCER_117              0x1075
+#define WM8962_WRITE_SEQUENCER_118              0x1076
+#define WM8962_WRITE_SEQUENCER_119              0x1077
+#define WM8962_WRITE_SEQUENCER_120              0x1078
+#define WM8962_WRITE_SEQUENCER_121              0x1079
+#define WM8962_WRITE_SEQUENCER_122              0x107A
+#define WM8962_WRITE_SEQUENCER_123              0x107B
+#define WM8962_WRITE_SEQUENCER_124              0x107C
+#define WM8962_WRITE_SEQUENCER_125              0x107D
+#define WM8962_WRITE_SEQUENCER_126              0x107E
+#define WM8962_WRITE_SEQUENCER_127              0x107F
+#define WM8962_WRITE_SEQUENCER_128              0x1080
+#define WM8962_WRITE_SEQUENCER_129              0x1081
+#define WM8962_WRITE_SEQUENCER_130              0x1082
+#define WM8962_WRITE_SEQUENCER_131              0x1083
+#define WM8962_WRITE_SEQUENCER_132              0x1084
+#define WM8962_WRITE_SEQUENCER_133              0x1085
+#define WM8962_WRITE_SEQUENCER_134              0x1086
+#define WM8962_WRITE_SEQUENCER_135              0x1087
+#define WM8962_WRITE_SEQUENCER_136              0x1088
+#define WM8962_WRITE_SEQUENCER_137              0x1089
+#define WM8962_WRITE_SEQUENCER_138              0x108A
+#define WM8962_WRITE_SEQUENCER_139              0x108B
+#define WM8962_WRITE_SEQUENCER_140              0x108C
+#define WM8962_WRITE_SEQUENCER_141              0x108D
+#define WM8962_WRITE_SEQUENCER_142              0x108E
+#define WM8962_WRITE_SEQUENCER_143              0x108F
+#define WM8962_WRITE_SEQUENCER_144              0x1090
+#define WM8962_WRITE_SEQUENCER_145              0x1091
+#define WM8962_WRITE_SEQUENCER_146              0x1092
+#define WM8962_WRITE_SEQUENCER_147              0x1093
+#define WM8962_WRITE_SEQUENCER_148              0x1094
+#define WM8962_WRITE_SEQUENCER_149              0x1095
+#define WM8962_WRITE_SEQUENCER_150              0x1096
+#define WM8962_WRITE_SEQUENCER_151              0x1097
+#define WM8962_WRITE_SEQUENCER_152              0x1098
+#define WM8962_WRITE_SEQUENCER_153              0x1099
+#define WM8962_WRITE_SEQUENCER_154              0x109A
+#define WM8962_WRITE_SEQUENCER_155              0x109B
+#define WM8962_WRITE_SEQUENCER_156              0x109C
+#define WM8962_WRITE_SEQUENCER_157              0x109D
+#define WM8962_WRITE_SEQUENCER_158              0x109E
+#define WM8962_WRITE_SEQUENCER_159              0x109F
+#define WM8962_WRITE_SEQUENCER_160              0x10A0
+#define WM8962_WRITE_SEQUENCER_161              0x10A1
+#define WM8962_WRITE_SEQUENCER_162              0x10A2
+#define WM8962_WRITE_SEQUENCER_163              0x10A3
+#define WM8962_WRITE_SEQUENCER_164              0x10A4
+#define WM8962_WRITE_SEQUENCER_165              0x10A5
+#define WM8962_WRITE_SEQUENCER_166              0x10A6
+#define WM8962_WRITE_SEQUENCER_167              0x10A7
+#define WM8962_WRITE_SEQUENCER_168              0x10A8
+#define WM8962_WRITE_SEQUENCER_169              0x10A9
+#define WM8962_WRITE_SEQUENCER_170              0x10AA
+#define WM8962_WRITE_SEQUENCER_171              0x10AB
+#define WM8962_WRITE_SEQUENCER_172              0x10AC
+#define WM8962_WRITE_SEQUENCER_173              0x10AD
+#define WM8962_WRITE_SEQUENCER_174              0x10AE
+#define WM8962_WRITE_SEQUENCER_175              0x10AF
+#define WM8962_WRITE_SEQUENCER_176              0x10B0
+#define WM8962_WRITE_SEQUENCER_177              0x10B1
+#define WM8962_WRITE_SEQUENCER_178              0x10B2
+#define WM8962_WRITE_SEQUENCER_179              0x10B3
+#define WM8962_WRITE_SEQUENCER_180              0x10B4
+#define WM8962_WRITE_SEQUENCER_181              0x10B5
+#define WM8962_WRITE_SEQUENCER_182              0x10B6
+#define WM8962_WRITE_SEQUENCER_183              0x10B7
+#define WM8962_WRITE_SEQUENCER_184              0x10B8
+#define WM8962_WRITE_SEQUENCER_185              0x10B9
+#define WM8962_WRITE_SEQUENCER_186              0x10BA
+#define WM8962_WRITE_SEQUENCER_187              0x10BB
+#define WM8962_WRITE_SEQUENCER_188              0x10BC
+#define WM8962_WRITE_SEQUENCER_189              0x10BD
+#define WM8962_WRITE_SEQUENCER_190              0x10BE
+#define WM8962_WRITE_SEQUENCER_191              0x10BF
+#define WM8962_WRITE_SEQUENCER_192              0x10C0
+#define WM8962_WRITE_SEQUENCER_193              0x10C1
+#define WM8962_WRITE_SEQUENCER_194              0x10C2
+#define WM8962_WRITE_SEQUENCER_195              0x10C3
+#define WM8962_WRITE_SEQUENCER_196              0x10C4
+#define WM8962_WRITE_SEQUENCER_197              0x10C5
+#define WM8962_WRITE_SEQUENCER_198              0x10C6
+#define WM8962_WRITE_SEQUENCER_199              0x10C7
+#define WM8962_WRITE_SEQUENCER_200              0x10C8
+#define WM8962_WRITE_SEQUENCER_201              0x10C9
+#define WM8962_WRITE_SEQUENCER_202              0x10CA
+#define WM8962_WRITE_SEQUENCER_203              0x10CB
+#define WM8962_WRITE_SEQUENCER_204              0x10CC
+#define WM8962_WRITE_SEQUENCER_205              0x10CD
+#define WM8962_WRITE_SEQUENCER_206              0x10CE
+#define WM8962_WRITE_SEQUENCER_207              0x10CF
+#define WM8962_WRITE_SEQUENCER_208              0x10D0
+#define WM8962_WRITE_SEQUENCER_209              0x10D1
+#define WM8962_WRITE_SEQUENCER_210              0x10D2
+#define WM8962_WRITE_SEQUENCER_211              0x10D3
+#define WM8962_WRITE_SEQUENCER_212              0x10D4
+#define WM8962_WRITE_SEQUENCER_213              0x10D5
+#define WM8962_WRITE_SEQUENCER_214              0x10D6
+#define WM8962_WRITE_SEQUENCER_215              0x10D7
+#define WM8962_WRITE_SEQUENCER_216              0x10D8
+#define WM8962_WRITE_SEQUENCER_217              0x10D9
+#define WM8962_WRITE_SEQUENCER_218              0x10DA
+#define WM8962_WRITE_SEQUENCER_219              0x10DB
+#define WM8962_WRITE_SEQUENCER_220              0x10DC
+#define WM8962_WRITE_SEQUENCER_221              0x10DD
+#define WM8962_WRITE_SEQUENCER_222              0x10DE
+#define WM8962_WRITE_SEQUENCER_223              0x10DF
+#define WM8962_WRITE_SEQUENCER_224              0x10E0
+#define WM8962_WRITE_SEQUENCER_225              0x10E1
+#define WM8962_WRITE_SEQUENCER_226              0x10E2
+#define WM8962_WRITE_SEQUENCER_227              0x10E3
+#define WM8962_WRITE_SEQUENCER_228              0x10E4
+#define WM8962_WRITE_SEQUENCER_229              0x10E5
+#define WM8962_WRITE_SEQUENCER_230              0x10E6
+#define WM8962_WRITE_SEQUENCER_231              0x10E7
+#define WM8962_WRITE_SEQUENCER_232              0x10E8
+#define WM8962_WRITE_SEQUENCER_233              0x10E9
+#define WM8962_WRITE_SEQUENCER_234              0x10EA
+#define WM8962_WRITE_SEQUENCER_235              0x10EB
+#define WM8962_WRITE_SEQUENCER_236              0x10EC
+#define WM8962_WRITE_SEQUENCER_237              0x10ED
+#define WM8962_WRITE_SEQUENCER_238              0x10EE
+#define WM8962_WRITE_SEQUENCER_239              0x10EF
+#define WM8962_WRITE_SEQUENCER_240              0x10F0
+#define WM8962_WRITE_SEQUENCER_241              0x10F1
+#define WM8962_WRITE_SEQUENCER_242              0x10F2
+#define WM8962_WRITE_SEQUENCER_243              0x10F3
+#define WM8962_WRITE_SEQUENCER_244              0x10F4
+#define WM8962_WRITE_SEQUENCER_245              0x10F5
+#define WM8962_WRITE_SEQUENCER_246              0x10F6
+#define WM8962_WRITE_SEQUENCER_247              0x10F7
+#define WM8962_WRITE_SEQUENCER_248              0x10F8
+#define WM8962_WRITE_SEQUENCER_249              0x10F9
+#define WM8962_WRITE_SEQUENCER_250              0x10FA
+#define WM8962_WRITE_SEQUENCER_251              0x10FB
+#define WM8962_WRITE_SEQUENCER_252              0x10FC
+#define WM8962_WRITE_SEQUENCER_253              0x10FD
+#define WM8962_WRITE_SEQUENCER_254              0x10FE
+#define WM8962_WRITE_SEQUENCER_255              0x10FF
+#define WM8962_WRITE_SEQUENCER_256              0x1100
+#define WM8962_WRITE_SEQUENCER_257              0x1101
+#define WM8962_WRITE_SEQUENCER_258              0x1102
+#define WM8962_WRITE_SEQUENCER_259              0x1103
+#define WM8962_WRITE_SEQUENCER_260              0x1104
+#define WM8962_WRITE_SEQUENCER_261              0x1105
+#define WM8962_WRITE_SEQUENCER_262              0x1106
+#define WM8962_WRITE_SEQUENCER_263              0x1107
+#define WM8962_WRITE_SEQUENCER_264              0x1108
+#define WM8962_WRITE_SEQUENCER_265              0x1109
+#define WM8962_WRITE_SEQUENCER_266              0x110A
+#define WM8962_WRITE_SEQUENCER_267              0x110B
+#define WM8962_WRITE_SEQUENCER_268              0x110C
+#define WM8962_WRITE_SEQUENCER_269              0x110D
+#define WM8962_WRITE_SEQUENCER_270              0x110E
+#define WM8962_WRITE_SEQUENCER_271              0x110F
+#define WM8962_WRITE_SEQUENCER_272              0x1110
+#define WM8962_WRITE_SEQUENCER_273              0x1111
+#define WM8962_WRITE_SEQUENCER_274              0x1112
+#define WM8962_WRITE_SEQUENCER_275              0x1113
+#define WM8962_WRITE_SEQUENCER_276              0x1114
+#define WM8962_WRITE_SEQUENCER_277              0x1115
+#define WM8962_WRITE_SEQUENCER_278              0x1116
+#define WM8962_WRITE_SEQUENCER_279              0x1117
+#define WM8962_WRITE_SEQUENCER_280              0x1118
+#define WM8962_WRITE_SEQUENCER_281              0x1119
+#define WM8962_WRITE_SEQUENCER_282              0x111A
+#define WM8962_WRITE_SEQUENCER_283              0x111B
+#define WM8962_WRITE_SEQUENCER_284              0x111C
+#define WM8962_WRITE_SEQUENCER_285              0x111D
+#define WM8962_WRITE_SEQUENCER_286              0x111E
+#define WM8962_WRITE_SEQUENCER_287              0x111F
+#define WM8962_WRITE_SEQUENCER_288              0x1120
+#define WM8962_WRITE_SEQUENCER_289              0x1121
+#define WM8962_WRITE_SEQUENCER_290              0x1122
+#define WM8962_WRITE_SEQUENCER_291              0x1123
+#define WM8962_WRITE_SEQUENCER_292              0x1124
+#define WM8962_WRITE_SEQUENCER_293              0x1125
+#define WM8962_WRITE_SEQUENCER_294              0x1126
+#define WM8962_WRITE_SEQUENCER_295              0x1127
+#define WM8962_WRITE_SEQUENCER_296              0x1128
+#define WM8962_WRITE_SEQUENCER_297              0x1129
+#define WM8962_WRITE_SEQUENCER_298              0x112A
+#define WM8962_WRITE_SEQUENCER_299              0x112B
+#define WM8962_WRITE_SEQUENCER_300              0x112C
+#define WM8962_WRITE_SEQUENCER_301              0x112D
+#define WM8962_WRITE_SEQUENCER_302              0x112E
+#define WM8962_WRITE_SEQUENCER_303              0x112F
+#define WM8962_WRITE_SEQUENCER_304              0x1130
+#define WM8962_WRITE_SEQUENCER_305              0x1131
+#define WM8962_WRITE_SEQUENCER_306              0x1132
+#define WM8962_WRITE_SEQUENCER_307              0x1133
+#define WM8962_WRITE_SEQUENCER_308              0x1134
+#define WM8962_WRITE_SEQUENCER_309              0x1135
+#define WM8962_WRITE_SEQUENCER_310              0x1136
+#define WM8962_WRITE_SEQUENCER_311              0x1137
+#define WM8962_WRITE_SEQUENCER_312              0x1138
+#define WM8962_WRITE_SEQUENCER_313              0x1139
+#define WM8962_WRITE_SEQUENCER_314              0x113A
+#define WM8962_WRITE_SEQUENCER_315              0x113B
+#define WM8962_WRITE_SEQUENCER_316              0x113C
+#define WM8962_WRITE_SEQUENCER_317              0x113D
+#define WM8962_WRITE_SEQUENCER_318              0x113E
+#define WM8962_WRITE_SEQUENCER_319              0x113F
+#define WM8962_WRITE_SEQUENCER_320              0x1140
+#define WM8962_WRITE_SEQUENCER_321              0x1141
+#define WM8962_WRITE_SEQUENCER_322              0x1142
+#define WM8962_WRITE_SEQUENCER_323              0x1143
+#define WM8962_WRITE_SEQUENCER_324              0x1144
+#define WM8962_WRITE_SEQUENCER_325              0x1145
+#define WM8962_WRITE_SEQUENCER_326              0x1146
+#define WM8962_WRITE_SEQUENCER_327              0x1147
+#define WM8962_WRITE_SEQUENCER_328              0x1148
+#define WM8962_WRITE_SEQUENCER_329              0x1149
+#define WM8962_WRITE_SEQUENCER_330              0x114A
+#define WM8962_WRITE_SEQUENCER_331              0x114B
+#define WM8962_WRITE_SEQUENCER_332              0x114C
+#define WM8962_WRITE_SEQUENCER_333              0x114D
+#define WM8962_WRITE_SEQUENCER_334              0x114E
+#define WM8962_WRITE_SEQUENCER_335              0x114F
+#define WM8962_WRITE_SEQUENCER_336              0x1150
+#define WM8962_WRITE_SEQUENCER_337              0x1151
+#define WM8962_WRITE_SEQUENCER_338              0x1152
+#define WM8962_WRITE_SEQUENCER_339              0x1153
+#define WM8962_WRITE_SEQUENCER_340              0x1154
+#define WM8962_WRITE_SEQUENCER_341              0x1155
+#define WM8962_WRITE_SEQUENCER_342              0x1156
+#define WM8962_WRITE_SEQUENCER_343              0x1157
+#define WM8962_WRITE_SEQUENCER_344              0x1158
+#define WM8962_WRITE_SEQUENCER_345              0x1159
+#define WM8962_WRITE_SEQUENCER_346              0x115A
+#define WM8962_WRITE_SEQUENCER_347              0x115B
+#define WM8962_WRITE_SEQUENCER_348              0x115C
+#define WM8962_WRITE_SEQUENCER_349              0x115D
+#define WM8962_WRITE_SEQUENCER_350              0x115E
+#define WM8962_WRITE_SEQUENCER_351              0x115F
+#define WM8962_WRITE_SEQUENCER_352              0x1160
+#define WM8962_WRITE_SEQUENCER_353              0x1161
+#define WM8962_WRITE_SEQUENCER_354              0x1162
+#define WM8962_WRITE_SEQUENCER_355              0x1163
+#define WM8962_WRITE_SEQUENCER_356              0x1164
+#define WM8962_WRITE_SEQUENCER_357              0x1165
+#define WM8962_WRITE_SEQUENCER_358              0x1166
+#define WM8962_WRITE_SEQUENCER_359              0x1167
+#define WM8962_WRITE_SEQUENCER_360              0x1168
+#define WM8962_WRITE_SEQUENCER_361              0x1169
+#define WM8962_WRITE_SEQUENCER_362              0x116A
+#define WM8962_WRITE_SEQUENCER_363              0x116B
+#define WM8962_WRITE_SEQUENCER_364              0x116C
+#define WM8962_WRITE_SEQUENCER_365              0x116D
+#define WM8962_WRITE_SEQUENCER_366              0x116E
+#define WM8962_WRITE_SEQUENCER_367              0x116F
+#define WM8962_WRITE_SEQUENCER_368              0x1170
+#define WM8962_WRITE_SEQUENCER_369              0x1171
+#define WM8962_WRITE_SEQUENCER_370              0x1172
+#define WM8962_WRITE_SEQUENCER_371              0x1173
+#define WM8962_WRITE_SEQUENCER_372              0x1174
+#define WM8962_WRITE_SEQUENCER_373              0x1175
+#define WM8962_WRITE_SEQUENCER_374              0x1176
+#define WM8962_WRITE_SEQUENCER_375              0x1177
+#define WM8962_WRITE_SEQUENCER_376              0x1178
+#define WM8962_WRITE_SEQUENCER_377              0x1179
+#define WM8962_WRITE_SEQUENCER_378              0x117A
+#define WM8962_WRITE_SEQUENCER_379              0x117B
+#define WM8962_WRITE_SEQUENCER_380              0x117C
+#define WM8962_WRITE_SEQUENCER_381              0x117D
+#define WM8962_WRITE_SEQUENCER_382              0x117E
+#define WM8962_WRITE_SEQUENCER_383              0x117F
+#define WM8962_WRITE_SEQUENCER_384              0x1180
+#define WM8962_WRITE_SEQUENCER_385              0x1181
+#define WM8962_WRITE_SEQUENCER_386              0x1182
+#define WM8962_WRITE_SEQUENCER_387              0x1183
+#define WM8962_WRITE_SEQUENCER_388              0x1184
+#define WM8962_WRITE_SEQUENCER_389              0x1185
+#define WM8962_WRITE_SEQUENCER_390              0x1186
+#define WM8962_WRITE_SEQUENCER_391              0x1187
+#define WM8962_WRITE_SEQUENCER_392              0x1188
+#define WM8962_WRITE_SEQUENCER_393              0x1189
+#define WM8962_WRITE_SEQUENCER_394              0x118A
+#define WM8962_WRITE_SEQUENCER_395              0x118B
+#define WM8962_WRITE_SEQUENCER_396              0x118C
+#define WM8962_WRITE_SEQUENCER_397              0x118D
+#define WM8962_WRITE_SEQUENCER_398              0x118E
+#define WM8962_WRITE_SEQUENCER_399              0x118F
+#define WM8962_WRITE_SEQUENCER_400              0x1190
+#define WM8962_WRITE_SEQUENCER_401              0x1191
+#define WM8962_WRITE_SEQUENCER_402              0x1192
+#define WM8962_WRITE_SEQUENCER_403              0x1193
+#define WM8962_WRITE_SEQUENCER_404              0x1194
+#define WM8962_WRITE_SEQUENCER_405              0x1195
+#define WM8962_WRITE_SEQUENCER_406              0x1196
+#define WM8962_WRITE_SEQUENCER_407              0x1197
+#define WM8962_WRITE_SEQUENCER_408              0x1198
+#define WM8962_WRITE_SEQUENCER_409              0x1199
+#define WM8962_WRITE_SEQUENCER_410              0x119A
+#define WM8962_WRITE_SEQUENCER_411              0x119B
+#define WM8962_WRITE_SEQUENCER_412              0x119C
+#define WM8962_WRITE_SEQUENCER_413              0x119D
+#define WM8962_WRITE_SEQUENCER_414              0x119E
+#define WM8962_WRITE_SEQUENCER_415              0x119F
+#define WM8962_WRITE_SEQUENCER_416              0x11A0
+#define WM8962_WRITE_SEQUENCER_417              0x11A1
+#define WM8962_WRITE_SEQUENCER_418              0x11A2
+#define WM8962_WRITE_SEQUENCER_419              0x11A3
+#define WM8962_WRITE_SEQUENCER_420              0x11A4
+#define WM8962_WRITE_SEQUENCER_421              0x11A5
+#define WM8962_WRITE_SEQUENCER_422              0x11A6
+#define WM8962_WRITE_SEQUENCER_423              0x11A7
+#define WM8962_WRITE_SEQUENCER_424              0x11A8
+#define WM8962_WRITE_SEQUENCER_425              0x11A9
+#define WM8962_WRITE_SEQUENCER_426              0x11AA
+#define WM8962_WRITE_SEQUENCER_427              0x11AB
+#define WM8962_WRITE_SEQUENCER_428              0x11AC
+#define WM8962_WRITE_SEQUENCER_429              0x11AD
+#define WM8962_WRITE_SEQUENCER_430              0x11AE
+#define WM8962_WRITE_SEQUENCER_431              0x11AF
+#define WM8962_WRITE_SEQUENCER_432              0x11B0
+#define WM8962_WRITE_SEQUENCER_433              0x11B1
+#define WM8962_WRITE_SEQUENCER_434              0x11B2
+#define WM8962_WRITE_SEQUENCER_435              0x11B3
+#define WM8962_WRITE_SEQUENCER_436              0x11B4
+#define WM8962_WRITE_SEQUENCER_437              0x11B5
+#define WM8962_WRITE_SEQUENCER_438              0x11B6
+#define WM8962_WRITE_SEQUENCER_439              0x11B7
+#define WM8962_WRITE_SEQUENCER_440              0x11B8
+#define WM8962_WRITE_SEQUENCER_441              0x11B9
+#define WM8962_WRITE_SEQUENCER_442              0x11BA
+#define WM8962_WRITE_SEQUENCER_443              0x11BB
+#define WM8962_WRITE_SEQUENCER_444              0x11BC
+#define WM8962_WRITE_SEQUENCER_445              0x11BD
+#define WM8962_WRITE_SEQUENCER_446              0x11BE
+#define WM8962_WRITE_SEQUENCER_447              0x11BF
+#define WM8962_WRITE_SEQUENCER_448              0x11C0
+#define WM8962_WRITE_SEQUENCER_449              0x11C1
+#define WM8962_WRITE_SEQUENCER_450              0x11C2
+#define WM8962_WRITE_SEQUENCER_451              0x11C3
+#define WM8962_WRITE_SEQUENCER_452              0x11C4
+#define WM8962_WRITE_SEQUENCER_453              0x11C5
+#define WM8962_WRITE_SEQUENCER_454              0x11C6
+#define WM8962_WRITE_SEQUENCER_455              0x11C7
+#define WM8962_WRITE_SEQUENCER_456              0x11C8
+#define WM8962_WRITE_SEQUENCER_457              0x11C9
+#define WM8962_WRITE_SEQUENCER_458              0x11CA
+#define WM8962_WRITE_SEQUENCER_459              0x11CB
+#define WM8962_WRITE_SEQUENCER_460              0x11CC
+#define WM8962_WRITE_SEQUENCER_461              0x11CD
+#define WM8962_WRITE_SEQUENCER_462              0x11CE
+#define WM8962_WRITE_SEQUENCER_463              0x11CF
+#define WM8962_WRITE_SEQUENCER_464              0x11D0
+#define WM8962_WRITE_SEQUENCER_465              0x11D1
+#define WM8962_WRITE_SEQUENCER_466              0x11D2
+#define WM8962_WRITE_SEQUENCER_467              0x11D3
+#define WM8962_WRITE_SEQUENCER_468              0x11D4
+#define WM8962_WRITE_SEQUENCER_469              0x11D5
+#define WM8962_WRITE_SEQUENCER_470              0x11D6
+#define WM8962_WRITE_SEQUENCER_471              0x11D7
+#define WM8962_WRITE_SEQUENCER_472              0x11D8
+#define WM8962_WRITE_SEQUENCER_473              0x11D9
+#define WM8962_WRITE_SEQUENCER_474              0x11DA
+#define WM8962_WRITE_SEQUENCER_475              0x11DB
+#define WM8962_WRITE_SEQUENCER_476              0x11DC
+#define WM8962_WRITE_SEQUENCER_477              0x11DD
+#define WM8962_WRITE_SEQUENCER_478              0x11DE
+#define WM8962_WRITE_SEQUENCER_479              0x11DF
+#define WM8962_WRITE_SEQUENCER_480              0x11E0
+#define WM8962_WRITE_SEQUENCER_481              0x11E1
+#define WM8962_WRITE_SEQUENCER_482              0x11E2
+#define WM8962_WRITE_SEQUENCER_483              0x11E3
+#define WM8962_WRITE_SEQUENCER_484              0x11E4
+#define WM8962_WRITE_SEQUENCER_485              0x11E5
+#define WM8962_WRITE_SEQUENCER_486              0x11E6
+#define WM8962_WRITE_SEQUENCER_487              0x11E7
+#define WM8962_WRITE_SEQUENCER_488              0x11E8
+#define WM8962_WRITE_SEQUENCER_489              0x11E9
+#define WM8962_WRITE_SEQUENCER_490              0x11EA
+#define WM8962_WRITE_SEQUENCER_491              0x11EB
+#define WM8962_WRITE_SEQUENCER_492              0x11EC
+#define WM8962_WRITE_SEQUENCER_493              0x11ED
+#define WM8962_WRITE_SEQUENCER_494              0x11EE
+#define WM8962_WRITE_SEQUENCER_495              0x11EF
+#define WM8962_WRITE_SEQUENCER_496              0x11F0
+#define WM8962_WRITE_SEQUENCER_497              0x11F1
+#define WM8962_WRITE_SEQUENCER_498              0x11F2
+#define WM8962_WRITE_SEQUENCER_499              0x11F3
+#define WM8962_WRITE_SEQUENCER_500              0x11F4
+#define WM8962_WRITE_SEQUENCER_501              0x11F5
+#define WM8962_WRITE_SEQUENCER_502              0x11F6
+#define WM8962_WRITE_SEQUENCER_503              0x11F7
+#define WM8962_WRITE_SEQUENCER_504              0x11F8
+#define WM8962_WRITE_SEQUENCER_505              0x11F9
+#define WM8962_WRITE_SEQUENCER_506              0x11FA
+#define WM8962_WRITE_SEQUENCER_507              0x11FB
+#define WM8962_WRITE_SEQUENCER_508              0x11FC
+#define WM8962_WRITE_SEQUENCER_509              0x11FD
+#define WM8962_WRITE_SEQUENCER_510              0x11FE
+#define WM8962_WRITE_SEQUENCER_511              0x11FF
+#define WM8962_DSP2_INSTRUCTION_RAM_0           0x2000
+#define WM8962_DSP2_ADDRESS_RAM_2               0x2400
+#define WM8962_DSP2_ADDRESS_RAM_1               0x2401
+#define WM8962_DSP2_ADDRESS_RAM_0               0x2402
+#define WM8962_DSP2_DATA1_RAM_1                 0x3000
+#define WM8962_DSP2_DATA1_RAM_0                 0x3001
+#define WM8962_DSP2_DATA2_RAM_1                 0x3400
+#define WM8962_DSP2_DATA2_RAM_0                 0x3401
+#define WM8962_DSP2_DATA3_RAM_1                 0x3800
+#define WM8962_DSP2_DATA3_RAM_0                 0x3801
+#define WM8962_DSP2_COEFF_RAM_0                 0x3C00
+#define WM8962_RETUNEADC_SHARED_COEFF_1         0x4000
+#define WM8962_RETUNEADC_SHARED_COEFF_0         0x4001
+#define WM8962_RETUNEDAC_SHARED_COEFF_1         0x4002
+#define WM8962_RETUNEDAC_SHARED_COEFF_0         0x4003
+#define WM8962_SOUNDSTAGE_ENABLES_1             0x4004
+#define WM8962_SOUNDSTAGE_ENABLES_0             0x4005
+#define WM8962_HDBASS_AI_1                      0x4200
+#define WM8962_HDBASS_AI_0                      0x4201
+#define WM8962_HDBASS_AR_1                      0x4202
+#define WM8962_HDBASS_AR_0                      0x4203
+#define WM8962_HDBASS_B_1                       0x4204
+#define WM8962_HDBASS_B_0                       0x4205
+#define WM8962_HDBASS_K_1                       0x4206
+#define WM8962_HDBASS_K_0                       0x4207
+#define WM8962_HDBASS_N1_1                      0x4208
+#define WM8962_HDBASS_N1_0                      0x4209
+#define WM8962_HDBASS_N2_1                      0x420A
+#define WM8962_HDBASS_N2_0                      0x420B
+#define WM8962_HDBASS_N3_1                      0x420C
+#define WM8962_HDBASS_N3_0                      0x420D
+#define WM8962_HDBASS_N4_1                      0x420E
+#define WM8962_HDBASS_N4_0                      0x420F
+#define WM8962_HDBASS_N5_1                      0x4210
+#define WM8962_HDBASS_N5_0                      0x4211
+#define WM8962_HDBASS_X1_1                      0x4212
+#define WM8962_HDBASS_X1_0                      0x4213
+#define WM8962_HDBASS_X2_1                      0x4214
+#define WM8962_HDBASS_X2_0                      0x4215
+#define WM8962_HDBASS_X3_1                      0x4216
+#define WM8962_HDBASS_X3_0                      0x4217
+#define WM8962_HDBASS_ATK_1                     0x4218
+#define WM8962_HDBASS_ATK_0                     0x4219
+#define WM8962_HDBASS_DCY_1                     0x421A
+#define WM8962_HDBASS_DCY_0                     0x421B
+#define WM8962_HDBASS_PG_1                      0x421C
+#define WM8962_HDBASS_PG_0                      0x421D
+#define WM8962_HPF_C_1                          0x4400
+#define WM8962_HPF_C_0                          0x4401
+#define WM8962_ADCL_RETUNE_C1_1                 0x4600
+#define WM8962_ADCL_RETUNE_C1_0                 0x4601
+#define WM8962_ADCL_RETUNE_C2_1                 0x4602
+#define WM8962_ADCL_RETUNE_C2_0                 0x4603
+#define WM8962_ADCL_RETUNE_C3_1                 0x4604
+#define WM8962_ADCL_RETUNE_C3_0                 0x4605
+#define WM8962_ADCL_RETUNE_C4_1                 0x4606
+#define WM8962_ADCL_RETUNE_C4_0                 0x4607
+#define WM8962_ADCL_RETUNE_C5_1                 0x4608
+#define WM8962_ADCL_RETUNE_C5_0                 0x4609
+#define WM8962_ADCL_RETUNE_C6_1                 0x460A
+#define WM8962_ADCL_RETUNE_C6_0                 0x460B
+#define WM8962_ADCL_RETUNE_C7_1                 0x460C
+#define WM8962_ADCL_RETUNE_C7_0                 0x460D
+#define WM8962_ADCL_RETUNE_C8_1                 0x460E
+#define WM8962_ADCL_RETUNE_C8_0                 0x460F
+#define WM8962_ADCL_RETUNE_C9_1                 0x4610
+#define WM8962_ADCL_RETUNE_C9_0                 0x4611
+#define WM8962_ADCL_RETUNE_C10_1                0x4612
+#define WM8962_ADCL_RETUNE_C10_0                0x4613
+#define WM8962_ADCL_RETUNE_C11_1                0x4614
+#define WM8962_ADCL_RETUNE_C11_0                0x4615
+#define WM8962_ADCL_RETUNE_C12_1                0x4616
+#define WM8962_ADCL_RETUNE_C12_0                0x4617
+#define WM8962_ADCL_RETUNE_C13_1                0x4618
+#define WM8962_ADCL_RETUNE_C13_0                0x4619
+#define WM8962_ADCL_RETUNE_C14_1                0x461A
+#define WM8962_ADCL_RETUNE_C14_0                0x461B
+#define WM8962_ADCL_RETUNE_C15_1                0x461C
+#define WM8962_ADCL_RETUNE_C15_0                0x461D
+#define WM8962_ADCL_RETUNE_C16_1                0x461E
+#define WM8962_ADCL_RETUNE_C16_0                0x461F
+#define WM8962_ADCL_RETUNE_C17_1                0x4620
+#define WM8962_ADCL_RETUNE_C17_0                0x4621
+#define WM8962_ADCL_RETUNE_C18_1                0x4622
+#define WM8962_ADCL_RETUNE_C18_0                0x4623
+#define WM8962_ADCL_RETUNE_C19_1                0x4624
+#define WM8962_ADCL_RETUNE_C19_0                0x4625
+#define WM8962_ADCL_RETUNE_C20_1                0x4626
+#define WM8962_ADCL_RETUNE_C20_0                0x4627
+#define WM8962_ADCL_RETUNE_C21_1                0x4628
+#define WM8962_ADCL_RETUNE_C21_0                0x4629
+#define WM8962_ADCL_RETUNE_C22_1                0x462A
+#define WM8962_ADCL_RETUNE_C22_0                0x462B
+#define WM8962_ADCL_RETUNE_C23_1                0x462C
+#define WM8962_ADCL_RETUNE_C23_0                0x462D
+#define WM8962_ADCL_RETUNE_C24_1                0x462E
+#define WM8962_ADCL_RETUNE_C24_0                0x462F
+#define WM8962_ADCL_RETUNE_C25_1                0x4630
+#define WM8962_ADCL_RETUNE_C25_0                0x4631
+#define WM8962_ADCL_RETUNE_C26_1                0x4632
+#define WM8962_ADCL_RETUNE_C26_0                0x4633
+#define WM8962_ADCL_RETUNE_C27_1                0x4634
+#define WM8962_ADCL_RETUNE_C27_0                0x4635
+#define WM8962_ADCL_RETUNE_C28_1                0x4636
+#define WM8962_ADCL_RETUNE_C28_0                0x4637
+#define WM8962_ADCL_RETUNE_C29_1                0x4638
+#define WM8962_ADCL_RETUNE_C29_0                0x4639
+#define WM8962_ADCL_RETUNE_C30_1                0x463A
+#define WM8962_ADCL_RETUNE_C30_0                0x463B
+#define WM8962_ADCL_RETUNE_C31_1                0x463C
+#define WM8962_ADCL_RETUNE_C31_0                0x463D
+#define WM8962_ADCL_RETUNE_C32_1                0x463E
+#define WM8962_ADCL_RETUNE_C32_0                0x463F
+#define WM8962_RETUNEADC_PG2_1                  0x4800
+#define WM8962_RETUNEADC_PG2_0                  0x4801
+#define WM8962_RETUNEADC_PG_1                   0x4802
+#define WM8962_RETUNEADC_PG_0                   0x4803
+#define WM8962_ADCR_RETUNE_C1_1                 0x4A00
+#define WM8962_ADCR_RETUNE_C1_0                 0x4A01
+#define WM8962_ADCR_RETUNE_C2_1                 0x4A02
+#define WM8962_ADCR_RETUNE_C2_0                 0x4A03
+#define WM8962_ADCR_RETUNE_C3_1                 0x4A04
+#define WM8962_ADCR_RETUNE_C3_0                 0x4A05
+#define WM8962_ADCR_RETUNE_C4_1                 0x4A06
+#define WM8962_ADCR_RETUNE_C4_0                 0x4A07
+#define WM8962_ADCR_RETUNE_C5_1                 0x4A08
+#define WM8962_ADCR_RETUNE_C5_0                 0x4A09
+#define WM8962_ADCR_RETUNE_C6_1                 0x4A0A
+#define WM8962_ADCR_RETUNE_C6_0                 0x4A0B
+#define WM8962_ADCR_RETUNE_C7_1                 0x4A0C
+#define WM8962_ADCR_RETUNE_C7_0                 0x4A0D
+#define WM8962_ADCR_RETUNE_C8_1                 0x4A0E
+#define WM8962_ADCR_RETUNE_C8_0                 0x4A0F
+#define WM8962_ADCR_RETUNE_C9_1                 0x4A10
+#define WM8962_ADCR_RETUNE_C9_0                 0x4A11
+#define WM8962_ADCR_RETUNE_C10_1                0x4A12
+#define WM8962_ADCR_RETUNE_C10_0                0x4A13
+#define WM8962_ADCR_RETUNE_C11_1                0x4A14
+#define WM8962_ADCR_RETUNE_C11_0                0x4A15
+#define WM8962_ADCR_RETUNE_C12_1                0x4A16
+#define WM8962_ADCR_RETUNE_C12_0                0x4A17
+#define WM8962_ADCR_RETUNE_C13_1                0x4A18
+#define WM8962_ADCR_RETUNE_C13_0                0x4A19
+#define WM8962_ADCR_RETUNE_C14_1                0x4A1A
+#define WM8962_ADCR_RETUNE_C14_0                0x4A1B
+#define WM8962_ADCR_RETUNE_C15_1                0x4A1C
+#define WM8962_ADCR_RETUNE_C15_0                0x4A1D
+#define WM8962_ADCR_RETUNE_C16_1                0x4A1E
+#define WM8962_ADCR_RETUNE_C16_0                0x4A1F
+#define WM8962_ADCR_RETUNE_C17_1                0x4A20
+#define WM8962_ADCR_RETUNE_C17_0                0x4A21
+#define WM8962_ADCR_RETUNE_C18_1                0x4A22
+#define WM8962_ADCR_RETUNE_C18_0                0x4A23
+#define WM8962_ADCR_RETUNE_C19_1                0x4A24
+#define WM8962_ADCR_RETUNE_C19_0                0x4A25
+#define WM8962_ADCR_RETUNE_C20_1                0x4A26
+#define WM8962_ADCR_RETUNE_C20_0                0x4A27
+#define WM8962_ADCR_RETUNE_C21_1                0x4A28
+#define WM8962_ADCR_RETUNE_C21_0                0x4A29
+#define WM8962_ADCR_RETUNE_C22_1                0x4A2A
+#define WM8962_ADCR_RETUNE_C22_0                0x4A2B
+#define WM8962_ADCR_RETUNE_C23_1                0x4A2C
+#define WM8962_ADCR_RETUNE_C23_0                0x4A2D
+#define WM8962_ADCR_RETUNE_C24_1                0x4A2E
+#define WM8962_ADCR_RETUNE_C24_0                0x4A2F
+#define WM8962_ADCR_RETUNE_C25_1                0x4A30
+#define WM8962_ADCR_RETUNE_C25_0                0x4A31
+#define WM8962_ADCR_RETUNE_C26_1                0x4A32
+#define WM8962_ADCR_RETUNE_C26_0                0x4A33
+#define WM8962_ADCR_RETUNE_C27_1                0x4A34
+#define WM8962_ADCR_RETUNE_C27_0                0x4A35
+#define WM8962_ADCR_RETUNE_C28_1                0x4A36
+#define WM8962_ADCR_RETUNE_C28_0                0x4A37
+#define WM8962_ADCR_RETUNE_C29_1                0x4A38
+#define WM8962_ADCR_RETUNE_C29_0                0x4A39
+#define WM8962_ADCR_RETUNE_C30_1                0x4A3A
+#define WM8962_ADCR_RETUNE_C30_0                0x4A3B
+#define WM8962_ADCR_RETUNE_C31_1                0x4A3C
+#define WM8962_ADCR_RETUNE_C31_0                0x4A3D
+#define WM8962_ADCR_RETUNE_C32_1                0x4A3E
+#define WM8962_ADCR_RETUNE_C32_0                0x4A3F
+#define WM8962_DACL_RETUNE_C1_1                 0x4C00
+#define WM8962_DACL_RETUNE_C1_0                 0x4C01
+#define WM8962_DACL_RETUNE_C2_1                 0x4C02
+#define WM8962_DACL_RETUNE_C2_0                 0x4C03
+#define WM8962_DACL_RETUNE_C3_1                 0x4C04
+#define WM8962_DACL_RETUNE_C3_0                 0x4C05
+#define WM8962_DACL_RETUNE_C4_1                 0x4C06
+#define WM8962_DACL_RETUNE_C4_0                 0x4C07
+#define WM8962_DACL_RETUNE_C5_1                 0x4C08
+#define WM8962_DACL_RETUNE_C5_0                 0x4C09
+#define WM8962_DACL_RETUNE_C6_1                 0x4C0A
+#define WM8962_DACL_RETUNE_C6_0                 0x4C0B
+#define WM8962_DACL_RETUNE_C7_1                 0x4C0C
+#define WM8962_DACL_RETUNE_C7_0                 0x4C0D
+#define WM8962_DACL_RETUNE_C8_1                 0x4C0E
+#define WM8962_DACL_RETUNE_C8_0                 0x4C0F
+#define WM8962_DACL_RETUNE_C9_1                 0x4C10
+#define WM8962_DACL_RETUNE_C9_0                 0x4C11
+#define WM8962_DACL_RETUNE_C10_1                0x4C12
+#define WM8962_DACL_RETUNE_C10_0                0x4C13
+#define WM8962_DACL_RETUNE_C11_1                0x4C14
+#define WM8962_DACL_RETUNE_C11_0                0x4C15
+#define WM8962_DACL_RETUNE_C12_1                0x4C16
+#define WM8962_DACL_RETUNE_C12_0                0x4C17
+#define WM8962_DACL_RETUNE_C13_1                0x4C18
+#define WM8962_DACL_RETUNE_C13_0                0x4C19
+#define WM8962_DACL_RETUNE_C14_1                0x4C1A
+#define WM8962_DACL_RETUNE_C14_0                0x4C1B
+#define WM8962_DACL_RETUNE_C15_1                0x4C1C
+#define WM8962_DACL_RETUNE_C15_0                0x4C1D
+#define WM8962_DACL_RETUNE_C16_1                0x4C1E
+#define WM8962_DACL_RETUNE_C16_0                0x4C1F
+#define WM8962_DACL_RETUNE_C17_1                0x4C20
+#define WM8962_DACL_RETUNE_C17_0                0x4C21
+#define WM8962_DACL_RETUNE_C18_1                0x4C22
+#define WM8962_DACL_RETUNE_C18_0                0x4C23
+#define WM8962_DACL_RETUNE_C19_1                0x4C24
+#define WM8962_DACL_RETUNE_C19_0                0x4C25
+#define WM8962_DACL_RETUNE_C20_1                0x4C26
+#define WM8962_DACL_RETUNE_C20_0                0x4C27
+#define WM8962_DACL_RETUNE_C21_1                0x4C28
+#define WM8962_DACL_RETUNE_C21_0                0x4C29
+#define WM8962_DACL_RETUNE_C22_1                0x4C2A
+#define WM8962_DACL_RETUNE_C22_0                0x4C2B
+#define WM8962_DACL_RETUNE_C23_1                0x4C2C
+#define WM8962_DACL_RETUNE_C23_0                0x4C2D
+#define WM8962_DACL_RETUNE_C24_1                0x4C2E
+#define WM8962_DACL_RETUNE_C24_0                0x4C2F
+#define WM8962_DACL_RETUNE_C25_1                0x4C30
+#define WM8962_DACL_RETUNE_C25_0                0x4C31
+#define WM8962_DACL_RETUNE_C26_1                0x4C32
+#define WM8962_DACL_RETUNE_C26_0                0x4C33
+#define WM8962_DACL_RETUNE_C27_1                0x4C34
+#define WM8962_DACL_RETUNE_C27_0                0x4C35
+#define WM8962_DACL_RETUNE_C28_1                0x4C36
+#define WM8962_DACL_RETUNE_C28_0                0x4C37
+#define WM8962_DACL_RETUNE_C29_1                0x4C38
+#define WM8962_DACL_RETUNE_C29_0                0x4C39
+#define WM8962_DACL_RETUNE_C30_1                0x4C3A
+#define WM8962_DACL_RETUNE_C30_0                0x4C3B
+#define WM8962_DACL_RETUNE_C31_1                0x4C3C
+#define WM8962_DACL_RETUNE_C31_0                0x4C3D
+#define WM8962_DACL_RETUNE_C32_1                0x4C3E
+#define WM8962_DACL_RETUNE_C32_0                0x4C3F
+#define WM8962_RETUNEDAC_PG2_1                  0x4E00
+#define WM8962_RETUNEDAC_PG2_0                  0x4E01
+#define WM8962_RETUNEDAC_PG_1                   0x4E02
+#define WM8962_RETUNEDAC_PG_0                   0x4E03
+#define WM8962_DACR_RETUNE_C1_1                 0x5000
+#define WM8962_DACR_RETUNE_C1_0                 0x5001
+#define WM8962_DACR_RETUNE_C2_1                 0x5002
+#define WM8962_DACR_RETUNE_C2_0                 0x5003
+#define WM8962_DACR_RETUNE_C3_1                 0x5004
+#define WM8962_DACR_RETUNE_C3_0                 0x5005
+#define WM8962_DACR_RETUNE_C4_1                 0x5006
+#define WM8962_DACR_RETUNE_C4_0                 0x5007
+#define WM8962_DACR_RETUNE_C5_1                 0x5008
+#define WM8962_DACR_RETUNE_C5_0                 0x5009
+#define WM8962_DACR_RETUNE_C6_1                 0x500A
+#define WM8962_DACR_RETUNE_C6_0                 0x500B
+#define WM8962_DACR_RETUNE_C7_1                 0x500C
+#define WM8962_DACR_RETUNE_C7_0                 0x500D
+#define WM8962_DACR_RETUNE_C8_1                 0x500E
+#define WM8962_DACR_RETUNE_C8_0                 0x500F
+#define WM8962_DACR_RETUNE_C9_1                 0x5010
+#define WM8962_DACR_RETUNE_C9_0                 0x5011
+#define WM8962_DACR_RETUNE_C10_1                0x5012
+#define WM8962_DACR_RETUNE_C10_0                0x5013
+#define WM8962_DACR_RETUNE_C11_1                0x5014
+#define WM8962_DACR_RETUNE_C11_0                0x5015
+#define WM8962_DACR_RETUNE_C12_1                0x5016
+#define WM8962_DACR_RETUNE_C12_0                0x5017
+#define WM8962_DACR_RETUNE_C13_1                0x5018
+#define WM8962_DACR_RETUNE_C13_0                0x5019
+#define WM8962_DACR_RETUNE_C14_1                0x501A
+#define WM8962_DACR_RETUNE_C14_0                0x501B
+#define WM8962_DACR_RETUNE_C15_1                0x501C
+#define WM8962_DACR_RETUNE_C15_0                0x501D
+#define WM8962_DACR_RETUNE_C16_1                0x501E
+#define WM8962_DACR_RETUNE_C16_0                0x501F
+#define WM8962_DACR_RETUNE_C17_1                0x5020
+#define WM8962_DACR_RETUNE_C17_0                0x5021
+#define WM8962_DACR_RETUNE_C18_1                0x5022
+#define WM8962_DACR_RETUNE_C18_0                0x5023
+#define WM8962_DACR_RETUNE_C19_1                0x5024
+#define WM8962_DACR_RETUNE_C19_0                0x5025
+#define WM8962_DACR_RETUNE_C20_1                0x5026
+#define WM8962_DACR_RETUNE_C20_0                0x5027
+#define WM8962_DACR_RETUNE_C21_1                0x5028
+#define WM8962_DACR_RETUNE_C21_0                0x5029
+#define WM8962_DACR_RETUNE_C22_1                0x502A
+#define WM8962_DACR_RETUNE_C22_0                0x502B
+#define WM8962_DACR_RETUNE_C23_1                0x502C
+#define WM8962_DACR_RETUNE_C23_0                0x502D
+#define WM8962_DACR_RETUNE_C24_1                0x502E
+#define WM8962_DACR_RETUNE_C24_0                0x502F
+#define WM8962_DACR_RETUNE_C25_1                0x5030
+#define WM8962_DACR_RETUNE_C25_0                0x5031
+#define WM8962_DACR_RETUNE_C26_1                0x5032
+#define WM8962_DACR_RETUNE_C26_0                0x5033
+#define WM8962_DACR_RETUNE_C27_1                0x5034
+#define WM8962_DACR_RETUNE_C27_0                0x5035
+#define WM8962_DACR_RETUNE_C28_1                0x5036
+#define WM8962_DACR_RETUNE_C28_0                0x5037
+#define WM8962_DACR_RETUNE_C29_1                0x5038
+#define WM8962_DACR_RETUNE_C29_0                0x5039
+#define WM8962_DACR_RETUNE_C30_1                0x503A
+#define WM8962_DACR_RETUNE_C30_0                0x503B
+#define WM8962_DACR_RETUNE_C31_1                0x503C
+#define WM8962_DACR_RETUNE_C31_0                0x503D
+#define WM8962_DACR_RETUNE_C32_1                0x503E
+#define WM8962_DACR_RETUNE_C32_0                0x503F
+#define WM8962_VSS_XHD2_1                       0x5200
+#define WM8962_VSS_XHD2_0                       0x5201
+#define WM8962_VSS_XHD3_1                       0x5202
+#define WM8962_VSS_XHD3_0                       0x5203
+#define WM8962_VSS_XHN1_1                       0x5204
+#define WM8962_VSS_XHN1_0                       0x5205
+#define WM8962_VSS_XHN2_1                       0x5206
+#define WM8962_VSS_XHN2_0                       0x5207
+#define WM8962_VSS_XHN3_1                       0x5208
+#define WM8962_VSS_XHN3_0                       0x5209
+#define WM8962_VSS_XLA_1                        0x520A
+#define WM8962_VSS_XLA_0                        0x520B
+#define WM8962_VSS_XLB_1                        0x520C
+#define WM8962_VSS_XLB_0                        0x520D
+#define WM8962_VSS_XLG_1                        0x520E
+#define WM8962_VSS_XLG_0                        0x520F
+#define WM8962_VSS_PG2_1                        0x5210
+#define WM8962_VSS_PG2_0                        0x5211
+#define WM8962_VSS_PG_1                         0x5212
+#define WM8962_VSS_PG_0                         0x5213
+#define WM8962_VSS_XTD1_1                       0x5214
+#define WM8962_VSS_XTD1_0                       0x5215
+#define WM8962_VSS_XTD2_1                       0x5216
+#define WM8962_VSS_XTD2_0                       0x5217
+#define WM8962_VSS_XTD3_1                       0x5218
+#define WM8962_VSS_XTD3_0                       0x5219
+#define WM8962_VSS_XTD4_1                       0x521A
+#define WM8962_VSS_XTD4_0                       0x521B
+#define WM8962_VSS_XTD5_1                       0x521C
+#define WM8962_VSS_XTD5_0                       0x521D
+#define WM8962_VSS_XTD6_1                       0x521E
+#define WM8962_VSS_XTD6_0                       0x521F
+#define WM8962_VSS_XTD7_1                       0x5220
+#define WM8962_VSS_XTD7_0                       0x5221
+#define WM8962_VSS_XTD8_1                       0x5222
+#define WM8962_VSS_XTD8_0                       0x5223
+#define WM8962_VSS_XTD9_1                       0x5224
+#define WM8962_VSS_XTD9_0                       0x5225
+#define WM8962_VSS_XTD10_1                      0x5226
+#define WM8962_VSS_XTD10_0                      0x5227
+#define WM8962_VSS_XTD11_1                      0x5228
+#define WM8962_VSS_XTD11_0                      0x5229
+#define WM8962_VSS_XTD12_1                      0x522A
+#define WM8962_VSS_XTD12_0                      0x522B
+#define WM8962_VSS_XTD13_1                      0x522C
+#define WM8962_VSS_XTD13_0                      0x522D
+#define WM8962_VSS_XTD14_1                      0x522E
+#define WM8962_VSS_XTD14_0                      0x522F
+#define WM8962_VSS_XTD15_1                      0x5230
+#define WM8962_VSS_XTD15_0                      0x5231
+#define WM8962_VSS_XTD16_1                      0x5232
+#define WM8962_VSS_XTD16_0                      0x5233
+#define WM8962_VSS_XTD17_1                      0x5234
+#define WM8962_VSS_XTD17_0                      0x5235
+#define WM8962_VSS_XTD18_1                      0x5236
+#define WM8962_VSS_XTD18_0                      0x5237
+#define WM8962_VSS_XTD19_1                      0x5238
+#define WM8962_VSS_XTD19_0                      0x5239
+#define WM8962_VSS_XTD20_1                      0x523A
+#define WM8962_VSS_XTD20_0                      0x523B
+#define WM8962_VSS_XTD21_1                      0x523C
+#define WM8962_VSS_XTD21_0                      0x523D
+#define WM8962_VSS_XTD22_1                      0x523E
+#define WM8962_VSS_XTD22_0                      0x523F
+#define WM8962_VSS_XTD23_1                      0x5240
+#define WM8962_VSS_XTD23_0                      0x5241
+#define WM8962_VSS_XTD24_1                      0x5242
+#define WM8962_VSS_XTD24_0                      0x5243
+#define WM8962_VSS_XTD25_1                      0x5244
+#define WM8962_VSS_XTD25_0                      0x5245
+#define WM8962_VSS_XTD26_1                      0x5246
+#define WM8962_VSS_XTD26_0                      0x5247
+#define WM8962_VSS_XTD27_1                      0x5248
+#define WM8962_VSS_XTD27_0                      0x5249
+#define WM8962_VSS_XTD28_1                      0x524A
+#define WM8962_VSS_XTD28_0                      0x524B
+#define WM8962_VSS_XTD29_1                      0x524C
+#define WM8962_VSS_XTD29_0                      0x524D
+#define WM8962_VSS_XTD30_1                      0x524E
+#define WM8962_VSS_XTD30_0                      0x524F
+#define WM8962_VSS_XTD31_1                      0x5250
+#define WM8962_VSS_XTD31_0                      0x5251
+#define WM8962_VSS_XTD32_1                      0x5252
+#define WM8962_VSS_XTD32_0                      0x5253
+#define WM8962_VSS_XTS1_1                       0x5254
+#define WM8962_VSS_XTS1_0                       0x5255
+#define WM8962_VSS_XTS2_1                       0x5256
+#define WM8962_VSS_XTS2_0                       0x5257
+#define WM8962_VSS_XTS3_1                       0x5258
+#define WM8962_VSS_XTS3_0                       0x5259
+#define WM8962_VSS_XTS4_1                       0x525A
+#define WM8962_VSS_XTS4_0                       0x525B
+#define WM8962_VSS_XTS5_1                       0x525C
+#define WM8962_VSS_XTS5_0                       0x525D
+#define WM8962_VSS_XTS6_1                       0x525E
+#define WM8962_VSS_XTS6_0                       0x525F
+#define WM8962_VSS_XTS7_1                       0x5260
+#define WM8962_VSS_XTS7_0                       0x5261
+#define WM8962_VSS_XTS8_1                       0x5262
+#define WM8962_VSS_XTS8_0                       0x5263
+#define WM8962_VSS_XTS9_1                       0x5264
+#define WM8962_VSS_XTS9_0                       0x5265
+#define WM8962_VSS_XTS10_1                      0x5266
+#define WM8962_VSS_XTS10_0                      0x5267
+#define WM8962_VSS_XTS11_1                      0x5268
+#define WM8962_VSS_XTS11_0                      0x5269
+#define WM8962_VSS_XTS12_1                      0x526A
+#define WM8962_VSS_XTS12_0                      0x526B
+#define WM8962_VSS_XTS13_1                      0x526C
+#define WM8962_VSS_XTS13_0                      0x526D
+#define WM8962_VSS_XTS14_1                      0x526E
+#define WM8962_VSS_XTS14_0                      0x526F
+#define WM8962_VSS_XTS15_1                      0x5270
+#define WM8962_VSS_XTS15_0                      0x5271
+#define WM8962_VSS_XTS16_1                      0x5272
+#define WM8962_VSS_XTS16_0                      0x5273
+#define WM8962_VSS_XTS17_1                      0x5274
+#define WM8962_VSS_XTS17_0                      0x5275
+#define WM8962_VSS_XTS18_1                      0x5276
+#define WM8962_VSS_XTS18_0                      0x5277
+#define WM8962_VSS_XTS19_1                      0x5278
+#define WM8962_VSS_XTS19_0                      0x5279
+#define WM8962_VSS_XTS20_1                      0x527A
+#define WM8962_VSS_XTS20_0                      0x527B
+#define WM8962_VSS_XTS21_1                      0x527C
+#define WM8962_VSS_XTS21_0                      0x527D
+#define WM8962_VSS_XTS22_1                      0x527E
+#define WM8962_VSS_XTS22_0                      0x527F
+#define WM8962_VSS_XTS23_1                      0x5280
+#define WM8962_VSS_XTS23_0                      0x5281
+#define WM8962_VSS_XTS24_1                      0x5282
+#define WM8962_VSS_XTS24_0                      0x5283
+#define WM8962_VSS_XTS25_1                      0x5284
+#define WM8962_VSS_XTS25_0                      0x5285
+#define WM8962_VSS_XTS26_1                      0x5286
+#define WM8962_VSS_XTS26_0                      0x5287
+#define WM8962_VSS_XTS27_1                      0x5288
+#define WM8962_VSS_XTS27_0                      0x5289
+#define WM8962_VSS_XTS28_1                      0x528A
+#define WM8962_VSS_XTS28_0                      0x528B
+#define WM8962_VSS_XTS29_1                      0x528C
+#define WM8962_VSS_XTS29_0                      0x528D
+#define WM8962_VSS_XTS30_1                      0x528E
+#define WM8962_VSS_XTS30_0                      0x528F
+#define WM8962_VSS_XTS31_1                      0x5290
+#define WM8962_VSS_XTS31_0                      0x5291
+#define WM8962_VSS_XTS32_1                      0x5292
+#define WM8962_VSS_XTS32_0                      0x5293
+
+#define WM8962_REGISTER_COUNT                   1138
+#define WM8962_MAX_REGISTER                     0x5293
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Left Input volume
+ */
+#define WM8962_IN_VU                            0x0100  /* IN_VU */
+#define WM8962_IN_VU_MASK                       0x0100  /* IN_VU */
+#define WM8962_IN_VU_SHIFT                           8  /* IN_VU */
+#define WM8962_IN_VU_WIDTH                           1  /* IN_VU */
+#define WM8962_INPGAL_MUTE                      0x0080  /* INPGAL_MUTE */
+#define WM8962_INPGAL_MUTE_MASK                 0x0080  /* INPGAL_MUTE */
+#define WM8962_INPGAL_MUTE_SHIFT                     7  /* INPGAL_MUTE */
+#define WM8962_INPGAL_MUTE_WIDTH                     1  /* INPGAL_MUTE */
+#define WM8962_INL_ZC                           0x0040  /* INL_ZC */
+#define WM8962_INL_ZC_MASK                      0x0040  /* INL_ZC */
+#define WM8962_INL_ZC_SHIFT                          6  /* INL_ZC */
+#define WM8962_INL_ZC_WIDTH                          1  /* INL_ZC */
+#define WM8962_INL_VOL_MASK                     0x003F  /* INL_VOL - [5:0] */
+#define WM8962_INL_VOL_SHIFT                         0  /* INL_VOL - [5:0] */
+#define WM8962_INL_VOL_WIDTH                         6  /* INL_VOL - [5:0] */
+
+/*
+ * R1 (0x01) - Right Input volume
+ */
+#define WM8962_CUST_ID_MASK                     0xF000  /* CUST_ID - [15:12] */
+#define WM8962_CUST_ID_SHIFT                        12  /* CUST_ID - [15:12] */
+#define WM8962_CUST_ID_WIDTH                         4  /* CUST_ID - [15:12] */
+#define WM8962_CHIP_REV_MASK                    0x0E00  /* CHIP_REV - [11:9] */
+#define WM8962_CHIP_REV_SHIFT                        9  /* CHIP_REV - [11:9] */
+#define WM8962_CHIP_REV_WIDTH                        3  /* CHIP_REV - [11:9] */
+#define WM8962_IN_VU                            0x0100  /* IN_VU */
+#define WM8962_IN_VU_MASK                       0x0100  /* IN_VU */
+#define WM8962_IN_VU_SHIFT                           8  /* IN_VU */
+#define WM8962_IN_VU_WIDTH                           1  /* IN_VU */
+#define WM8962_INPGAR_MUTE                      0x0080  /* INPGAR_MUTE */
+#define WM8962_INPGAR_MUTE_MASK                 0x0080  /* INPGAR_MUTE */
+#define WM8962_INPGAR_MUTE_SHIFT                     7  /* INPGAR_MUTE */
+#define WM8962_INPGAR_MUTE_WIDTH                     1  /* INPGAR_MUTE */
+#define WM8962_INR_ZC                           0x0040  /* INR_ZC */
+#define WM8962_INR_ZC_MASK                      0x0040  /* INR_ZC */
+#define WM8962_INR_ZC_SHIFT                          6  /* INR_ZC */
+#define WM8962_INR_ZC_WIDTH                          1  /* INR_ZC */
+#define WM8962_INR_VOL_MASK                     0x003F  /* INR_VOL - [5:0] */
+#define WM8962_INR_VOL_SHIFT                         0  /* INR_VOL - [5:0] */
+#define WM8962_INR_VOL_WIDTH                         6  /* INR_VOL - [5:0] */
+
+/*
+ * R2 (0x02) - HPOUTL volume
+ */
+#define WM8962_HPOUT_VU                         0x0100  /* HPOUT_VU */
+#define WM8962_HPOUT_VU_MASK                    0x0100  /* HPOUT_VU */
+#define WM8962_HPOUT_VU_SHIFT                        8  /* HPOUT_VU */
+#define WM8962_HPOUT_VU_WIDTH                        1  /* HPOUT_VU */
+#define WM8962_HPOUTL_ZC                        0x0080  /* HPOUTL_ZC */
+#define WM8962_HPOUTL_ZC_MASK                   0x0080  /* HPOUTL_ZC */
+#define WM8962_HPOUTL_ZC_SHIFT                       7  /* HPOUTL_ZC */
+#define WM8962_HPOUTL_ZC_WIDTH                       1  /* HPOUTL_ZC */
+#define WM8962_HPOUTL_VOL_MASK                  0x007F  /* HPOUTL_VOL - [6:0] */
+#define WM8962_HPOUTL_VOL_SHIFT                      0  /* HPOUTL_VOL - [6:0] */
+#define WM8962_HPOUTL_VOL_WIDTH                      7  /* HPOUTL_VOL - [6:0] */
+
+/*
+ * R3 (0x03) - HPOUTR volume
+ */
+#define WM8962_HPOUT_VU                         0x0100  /* HPOUT_VU */
+#define WM8962_HPOUT_VU_MASK                    0x0100  /* HPOUT_VU */
+#define WM8962_HPOUT_VU_SHIFT                        8  /* HPOUT_VU */
+#define WM8962_HPOUT_VU_WIDTH                        1  /* HPOUT_VU */
+#define WM8962_HPOUTR_ZC                        0x0080  /* HPOUTR_ZC */
+#define WM8962_HPOUTR_ZC_MASK                   0x0080  /* HPOUTR_ZC */
+#define WM8962_HPOUTR_ZC_SHIFT                       7  /* HPOUTR_ZC */
+#define WM8962_HPOUTR_ZC_WIDTH                       1  /* HPOUTR_ZC */
+#define WM8962_HPOUTR_VOL_MASK                  0x007F  /* HPOUTR_VOL - [6:0] */
+#define WM8962_HPOUTR_VOL_SHIFT                      0  /* HPOUTR_VOL - [6:0] */
+#define WM8962_HPOUTR_VOL_WIDTH                      7  /* HPOUTR_VOL - [6:0] */
+
+/*
+ * R4 (0x04) - Clocking1
+ */
+#define WM8962_DSPCLK_DIV_MASK                  0x0600  /* DSPCLK_DIV - [10:9] */
+#define WM8962_DSPCLK_DIV_SHIFT                      9  /* DSPCLK_DIV - [10:9] */
+#define WM8962_DSPCLK_DIV_WIDTH                      2  /* DSPCLK_DIV - [10:9] */
+#define WM8962_ADCSYS_CLK_DIV_MASK              0x01C0  /* ADCSYS_CLK_DIV - [8:6] */
+#define WM8962_ADCSYS_CLK_DIV_SHIFT                  6  /* ADCSYS_CLK_DIV - [8:6] */
+#define WM8962_ADCSYS_CLK_DIV_WIDTH                  3  /* ADCSYS_CLK_DIV - [8:6] */
+#define WM8962_DACSYS_CLK_DIV_MASK              0x0038  /* DACSYS_CLK_DIV - [5:3] */
+#define WM8962_DACSYS_CLK_DIV_SHIFT                  3  /* DACSYS_CLK_DIV - [5:3] */
+#define WM8962_DACSYS_CLK_DIV_WIDTH                  3  /* DACSYS_CLK_DIV - [5:3] */
+#define WM8962_MCLKDIV_MASK                     0x0006  /* MCLKDIV - [2:1] */
+#define WM8962_MCLKDIV_SHIFT                         1  /* MCLKDIV - [2:1] */
+#define WM8962_MCLKDIV_WIDTH                         2  /* MCLKDIV - [2:1] */
+
+/*
+ * R5 (0x05) - ADC & DAC Control 1
+ */
+#define WM8962_ADCR_DAT_INV                     0x0040  /* ADCR_DAT_INV */
+#define WM8962_ADCR_DAT_INV_MASK                0x0040  /* ADCR_DAT_INV */
+#define WM8962_ADCR_DAT_INV_SHIFT                    6  /* ADCR_DAT_INV */
+#define WM8962_ADCR_DAT_INV_WIDTH                    1  /* ADCR_DAT_INV */
+#define WM8962_ADCL_DAT_INV                     0x0020  /* ADCL_DAT_INV */
+#define WM8962_ADCL_DAT_INV_MASK                0x0020  /* ADCL_DAT_INV */
+#define WM8962_ADCL_DAT_INV_SHIFT                    5  /* ADCL_DAT_INV */
+#define WM8962_ADCL_DAT_INV_WIDTH                    1  /* ADCL_DAT_INV */
+#define WM8962_DAC_MUTE_RAMP                    0x0010  /* DAC_MUTE_RAMP */
+#define WM8962_DAC_MUTE_RAMP_MASK               0x0010  /* DAC_MUTE_RAMP */
+#define WM8962_DAC_MUTE_RAMP_SHIFT                   4  /* DAC_MUTE_RAMP */
+#define WM8962_DAC_MUTE_RAMP_WIDTH                   1  /* DAC_MUTE_RAMP */
+#define WM8962_DAC_MUTE                         0x0008  /* DAC_MUTE */
+#define WM8962_DAC_MUTE_MASK                    0x0008  /* DAC_MUTE */
+#define WM8962_DAC_MUTE_SHIFT                        3  /* DAC_MUTE */
+#define WM8962_DAC_MUTE_WIDTH                        1  /* DAC_MUTE */
+#define WM8962_DAC_DEEMP_MASK                   0x0006  /* DAC_DEEMP - [2:1] */
+#define WM8962_DAC_DEEMP_SHIFT                       1  /* DAC_DEEMP - [2:1] */
+#define WM8962_DAC_DEEMP_WIDTH                       2  /* DAC_DEEMP - [2:1] */
+#define WM8962_ADC_HPF_DIS                      0x0001  /* ADC_HPF_DIS */
+#define WM8962_ADC_HPF_DIS_MASK                 0x0001  /* ADC_HPF_DIS */
+#define WM8962_ADC_HPF_DIS_SHIFT                     0  /* ADC_HPF_DIS */
+#define WM8962_ADC_HPF_DIS_WIDTH                     1  /* ADC_HPF_DIS */
+
+/*
+ * R6 (0x06) - ADC & DAC Control 2
+ */
+#define WM8962_ADC_HPF_SR_MASK                  0x3000  /* ADC_HPF_SR - [13:12] */
+#define WM8962_ADC_HPF_SR_SHIFT                     12  /* ADC_HPF_SR - [13:12] */
+#define WM8962_ADC_HPF_SR_WIDTH                      2  /* ADC_HPF_SR - [13:12] */
+#define WM8962_ADC_HPF_MODE                     0x0400  /* ADC_HPF_MODE */
+#define WM8962_ADC_HPF_MODE_MASK                0x0400  /* ADC_HPF_MODE */
+#define WM8962_ADC_HPF_MODE_SHIFT                   10  /* ADC_HPF_MODE */
+#define WM8962_ADC_HPF_MODE_WIDTH                    1  /* ADC_HPF_MODE */
+#define WM8962_ADC_HPF_CUT_MASK                 0x0380  /* ADC_HPF_CUT - [9:7] */
+#define WM8962_ADC_HPF_CUT_SHIFT                     7  /* ADC_HPF_CUT - [9:7] */
+#define WM8962_ADC_HPF_CUT_WIDTH                     3  /* ADC_HPF_CUT - [9:7] */
+#define WM8962_DACR_DAT_INV                     0x0040  /* DACR_DAT_INV */
+#define WM8962_DACR_DAT_INV_MASK                0x0040  /* DACR_DAT_INV */
+#define WM8962_DACR_DAT_INV_SHIFT                    6  /* DACR_DAT_INV */
+#define WM8962_DACR_DAT_INV_WIDTH                    1  /* DACR_DAT_INV */
+#define WM8962_DACL_DAT_INV                     0x0020  /* DACL_DAT_INV */
+#define WM8962_DACL_DAT_INV_MASK                0x0020  /* DACL_DAT_INV */
+#define WM8962_DACL_DAT_INV_SHIFT                    5  /* DACL_DAT_INV */
+#define WM8962_DACL_DAT_INV_WIDTH                    1  /* DACL_DAT_INV */
+#define WM8962_DAC_UNMUTE_RAMP                  0x0008  /* DAC_UNMUTE_RAMP */
+#define WM8962_DAC_UNMUTE_RAMP_MASK             0x0008  /* DAC_UNMUTE_RAMP */
+#define WM8962_DAC_UNMUTE_RAMP_SHIFT                 3  /* DAC_UNMUTE_RAMP */
+#define WM8962_DAC_UNMUTE_RAMP_WIDTH                 1  /* DAC_UNMUTE_RAMP */
+#define WM8962_DAC_MUTERATE                     0x0004  /* DAC_MUTERATE */
+#define WM8962_DAC_MUTERATE_MASK                0x0004  /* DAC_MUTERATE */
+#define WM8962_DAC_MUTERATE_SHIFT                    2  /* DAC_MUTERATE */
+#define WM8962_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
+#define WM8962_DAC_HP                           0x0001  /* DAC_HP */
+#define WM8962_DAC_HP_MASK                      0x0001  /* DAC_HP */
+#define WM8962_DAC_HP_SHIFT                          0  /* DAC_HP */
+#define WM8962_DAC_HP_WIDTH                          1  /* DAC_HP */
+
+/*
+ * R7 (0x07) - Audio Interface 0
+ */
+#define WM8962_AIFDAC_TDM_MODE                  0x1000  /* AIFDAC_TDM_MODE */
+#define WM8962_AIFDAC_TDM_MODE_MASK             0x1000  /* AIFDAC_TDM_MODE */
+#define WM8962_AIFDAC_TDM_MODE_SHIFT                12  /* AIFDAC_TDM_MODE */
+#define WM8962_AIFDAC_TDM_MODE_WIDTH                 1  /* AIFDAC_TDM_MODE */
+#define WM8962_AIFDAC_TDM_SLOT                  0x0800  /* AIFDAC_TDM_SLOT */
+#define WM8962_AIFDAC_TDM_SLOT_MASK             0x0800  /* AIFDAC_TDM_SLOT */
+#define WM8962_AIFDAC_TDM_SLOT_SHIFT                11  /* AIFDAC_TDM_SLOT */
+#define WM8962_AIFDAC_TDM_SLOT_WIDTH                 1  /* AIFDAC_TDM_SLOT */
+#define WM8962_AIFADC_TDM_MODE                  0x0400  /* AIFADC_TDM_MODE */
+#define WM8962_AIFADC_TDM_MODE_MASK             0x0400  /* AIFADC_TDM_MODE */
+#define WM8962_AIFADC_TDM_MODE_SHIFT                10  /* AIFADC_TDM_MODE */
+#define WM8962_AIFADC_TDM_MODE_WIDTH                 1  /* AIFADC_TDM_MODE */
+#define WM8962_AIFADC_TDM_SLOT                  0x0200  /* AIFADC_TDM_SLOT */
+#define WM8962_AIFADC_TDM_SLOT_MASK             0x0200  /* AIFADC_TDM_SLOT */
+#define WM8962_AIFADC_TDM_SLOT_SHIFT                 9  /* AIFADC_TDM_SLOT */
+#define WM8962_AIFADC_TDM_SLOT_WIDTH                 1  /* AIFADC_TDM_SLOT */
+#define WM8962_ADC_LRSWAP                       0x0100  /* ADC_LRSWAP */
+#define WM8962_ADC_LRSWAP_MASK                  0x0100  /* ADC_LRSWAP */
+#define WM8962_ADC_LRSWAP_SHIFT                      8  /* ADC_LRSWAP */
+#define WM8962_ADC_LRSWAP_WIDTH                      1  /* ADC_LRSWAP */
+#define WM8962_BCLK_INV                         0x0080  /* BCLK_INV */
+#define WM8962_BCLK_INV_MASK                    0x0080  /* BCLK_INV */
+#define WM8962_BCLK_INV_SHIFT                        7  /* BCLK_INV */
+#define WM8962_BCLK_INV_WIDTH                        1  /* BCLK_INV */
+#define WM8962_MSTR                             0x0040  /* MSTR */
+#define WM8962_MSTR_MASK                        0x0040  /* MSTR */
+#define WM8962_MSTR_SHIFT                            6  /* MSTR */
+#define WM8962_MSTR_WIDTH                            1  /* MSTR */
+#define WM8962_DAC_LRSWAP                       0x0020  /* DAC_LRSWAP */
+#define WM8962_DAC_LRSWAP_MASK                  0x0020  /* DAC_LRSWAP */
+#define WM8962_DAC_LRSWAP_SHIFT                      5  /* DAC_LRSWAP */
+#define WM8962_DAC_LRSWAP_WIDTH                      1  /* DAC_LRSWAP */
+#define WM8962_LRCLK_INV                        0x0010  /* LRCLK_INV */
+#define WM8962_LRCLK_INV_MASK                   0x0010  /* LRCLK_INV */
+#define WM8962_LRCLK_INV_SHIFT                       4  /* LRCLK_INV */
+#define WM8962_LRCLK_INV_WIDTH                       1  /* LRCLK_INV */
+#define WM8962_WL_MASK                          0x000C  /* WL - [3:2] */
+#define WM8962_WL_SHIFT                              2  /* WL - [3:2] */
+#define WM8962_WL_WIDTH                              2  /* WL - [3:2] */
+#define WM8962_FMT_MASK                         0x0003  /* FMT - [1:0] */
+#define WM8962_FMT_SHIFT                             0  /* FMT - [1:0] */
+#define WM8962_FMT_WIDTH                             2  /* FMT - [1:0] */
+
+/*
+ * R8 (0x08) - Clocking2
+ */
+#define WM8962_CLKREG_OVD                       0x0800  /* CLKREG_OVD */
+#define WM8962_CLKREG_OVD_MASK                  0x0800  /* CLKREG_OVD */
+#define WM8962_CLKREG_OVD_SHIFT                     11  /* CLKREG_OVD */
+#define WM8962_CLKREG_OVD_WIDTH                      1  /* CLKREG_OVD */
+#define WM8962_SYSCLK_SRC_MASK                  0x0600  /* SYSCLK_SRC - [10:9] */
+#define WM8962_SYSCLK_SRC_SHIFT                      9  /* SYSCLK_SRC - [10:9] */
+#define WM8962_SYSCLK_SRC_WIDTH                      2  /* SYSCLK_SRC - [10:9] */
+#define WM8962_CLASSD_CLK_DIV_MASK              0x01C0  /* CLASSD_CLK_DIV - [8:6] */
+#define WM8962_CLASSD_CLK_DIV_SHIFT                  6  /* CLASSD_CLK_DIV - [8:6] */
+#define WM8962_CLASSD_CLK_DIV_WIDTH                  3  /* CLASSD_CLK_DIV - [8:6] */
+#define WM8962_SYSCLK_ENA                       0x0020  /* SYSCLK_ENA */
+#define WM8962_SYSCLK_ENA_MASK                  0x0020  /* SYSCLK_ENA */
+#define WM8962_SYSCLK_ENA_SHIFT                      5  /* SYSCLK_ENA */
+#define WM8962_SYSCLK_ENA_WIDTH                      1  /* SYSCLK_ENA */
+#define WM8962_BCLK_DIV_MASK                    0x000F  /* BCLK_DIV - [3:0] */
+#define WM8962_BCLK_DIV_SHIFT                        0  /* BCLK_DIV - [3:0] */
+#define WM8962_BCLK_DIV_WIDTH                        4  /* BCLK_DIV - [3:0] */
+
+/*
+ * R9 (0x09) - Audio Interface 1
+ */
+#define WM8962_AUTOMUTE_STS                     0x0800  /* AUTOMUTE_STS */
+#define WM8962_AUTOMUTE_STS_MASK                0x0800  /* AUTOMUTE_STS */
+#define WM8962_AUTOMUTE_STS_SHIFT                   11  /* AUTOMUTE_STS */
+#define WM8962_AUTOMUTE_STS_WIDTH                    1  /* AUTOMUTE_STS */
+#define WM8962_DAC_AUTOMUTE_SAMPLES_MASK        0x0300  /* DAC_AUTOMUTE_SAMPLES - [9:8] */
+#define WM8962_DAC_AUTOMUTE_SAMPLES_SHIFT            8  /* DAC_AUTOMUTE_SAMPLES - [9:8] */
+#define WM8962_DAC_AUTOMUTE_SAMPLES_WIDTH            2  /* DAC_AUTOMUTE_SAMPLES - [9:8] */
+#define WM8962_DAC_AUTOMUTE                     0x0080  /* DAC_AUTOMUTE */
+#define WM8962_DAC_AUTOMUTE_MASK                0x0080  /* DAC_AUTOMUTE */
+#define WM8962_DAC_AUTOMUTE_SHIFT                    7  /* DAC_AUTOMUTE */
+#define WM8962_DAC_AUTOMUTE_WIDTH                    1  /* DAC_AUTOMUTE */
+#define WM8962_DAC_COMP                         0x0010  /* DAC_COMP */
+#define WM8962_DAC_COMP_MASK                    0x0010  /* DAC_COMP */
+#define WM8962_DAC_COMP_SHIFT                        4  /* DAC_COMP */
+#define WM8962_DAC_COMP_WIDTH                        1  /* DAC_COMP */
+#define WM8962_DAC_COMPMODE                     0x0008  /* DAC_COMPMODE */
+#define WM8962_DAC_COMPMODE_MASK                0x0008  /* DAC_COMPMODE */
+#define WM8962_DAC_COMPMODE_SHIFT                    3  /* DAC_COMPMODE */
+#define WM8962_DAC_COMPMODE_WIDTH                    1  /* DAC_COMPMODE */
+#define WM8962_ADC_COMP                         0x0004  /* ADC_COMP */
+#define WM8962_ADC_COMP_MASK                    0x0004  /* ADC_COMP */
+#define WM8962_ADC_COMP_SHIFT                        2  /* ADC_COMP */
+#define WM8962_ADC_COMP_WIDTH                        1  /* ADC_COMP */
+#define WM8962_ADC_COMPMODE                     0x0002  /* ADC_COMPMODE */
+#define WM8962_ADC_COMPMODE_MASK                0x0002  /* ADC_COMPMODE */
+#define WM8962_ADC_COMPMODE_SHIFT                    1  /* ADC_COMPMODE */
+#define WM8962_ADC_COMPMODE_WIDTH                    1  /* ADC_COMPMODE */
+#define WM8962_LOOPBACK                         0x0001  /* LOOPBACK */
+#define WM8962_LOOPBACK_MASK                    0x0001  /* LOOPBACK */
+#define WM8962_LOOPBACK_SHIFT                        0  /* LOOPBACK */
+#define WM8962_LOOPBACK_WIDTH                        1  /* LOOPBACK */
+
+/*
+ * R10 (0x0A) - Left DAC volume
+ */
+#define WM8962_DAC_VU                           0x0100  /* DAC_VU */
+#define WM8962_DAC_VU_MASK                      0x0100  /* DAC_VU */
+#define WM8962_DAC_VU_SHIFT                          8  /* DAC_VU */
+#define WM8962_DAC_VU_WIDTH                          1  /* DAC_VU */
+#define WM8962_DACL_VOL_MASK                    0x00FF  /* DACL_VOL - [7:0] */
+#define WM8962_DACL_VOL_SHIFT                        0  /* DACL_VOL - [7:0] */
+#define WM8962_DACL_VOL_WIDTH                        8  /* DACL_VOL - [7:0] */
+
+/*
+ * R11 (0x0B) - Right DAC volume
+ */
+#define WM8962_DAC_VU                           0x0100  /* DAC_VU */
+#define WM8962_DAC_VU_MASK                      0x0100  /* DAC_VU */
+#define WM8962_DAC_VU_SHIFT                          8  /* DAC_VU */
+#define WM8962_DAC_VU_WIDTH                          1  /* DAC_VU */
+#define WM8962_DACR_VOL_MASK                    0x00FF  /* DACR_VOL - [7:0] */
+#define WM8962_DACR_VOL_SHIFT                        0  /* DACR_VOL - [7:0] */
+#define WM8962_DACR_VOL_WIDTH                        8  /* DACR_VOL - [7:0] */
+
+/*
+ * R14 (0x0E) - Audio Interface 2
+ */
+#define WM8962_AIF_RATE_MASK                    0x07FF  /* AIF_RATE - [10:0] */
+#define WM8962_AIF_RATE_SHIFT                        0  /* AIF_RATE - [10:0] */
+#define WM8962_AIF_RATE_WIDTH                       11  /* AIF_RATE - [10:0] */
+
+/*
+ * R15 (0x0F) - Software Reset
+ */
+#define WM8962_SW_RESET_MASK                    0xFFFF  /* SW_RESET - [15:0] */
+#define WM8962_SW_RESET_SHIFT                        0  /* SW_RESET - [15:0] */
+#define WM8962_SW_RESET_WIDTH                       16  /* SW_RESET - [15:0] */
+
+/*
+ * R17 (0x11) - ALC1
+ */
+#define WM8962_ALC_INACTIVE_ENA                 0x0400  /* ALC_INACTIVE_ENA */
+#define WM8962_ALC_INACTIVE_ENA_MASK            0x0400  /* ALC_INACTIVE_ENA */
+#define WM8962_ALC_INACTIVE_ENA_SHIFT               10  /* ALC_INACTIVE_ENA */
+#define WM8962_ALC_INACTIVE_ENA_WIDTH                1  /* ALC_INACTIVE_ENA */
+#define WM8962_ALC_LVL_MODE                     0x0200  /* ALC_LVL_MODE */
+#define WM8962_ALC_LVL_MODE_MASK                0x0200  /* ALC_LVL_MODE */
+#define WM8962_ALC_LVL_MODE_SHIFT                    9  /* ALC_LVL_MODE */
+#define WM8962_ALC_LVL_MODE_WIDTH                    1  /* ALC_LVL_MODE */
+#define WM8962_ALCL_ENA                         0x0100  /* ALCL_ENA */
+#define WM8962_ALCL_ENA_MASK                    0x0100  /* ALCL_ENA */
+#define WM8962_ALCL_ENA_SHIFT                        8  /* ALCL_ENA */
+#define WM8962_ALCL_ENA_WIDTH                        1  /* ALCL_ENA */
+#define WM8962_ALCR_ENA                         0x0080  /* ALCR_ENA */
+#define WM8962_ALCR_ENA_MASK                    0x0080  /* ALCR_ENA */
+#define WM8962_ALCR_ENA_SHIFT                        7  /* ALCR_ENA */
+#define WM8962_ALCR_ENA_WIDTH                        1  /* ALCR_ENA */
+#define WM8962_ALC_MAXGAIN_MASK                 0x0070  /* ALC_MAXGAIN - [6:4] */
+#define WM8962_ALC_MAXGAIN_SHIFT                     4  /* ALC_MAXGAIN - [6:4] */
+#define WM8962_ALC_MAXGAIN_WIDTH                     3  /* ALC_MAXGAIN - [6:4] */
+#define WM8962_ALC_LVL_MASK                     0x000F  /* ALC_LVL - [3:0] */
+#define WM8962_ALC_LVL_SHIFT                         0  /* ALC_LVL - [3:0] */
+#define WM8962_ALC_LVL_WIDTH                         4  /* ALC_LVL - [3:0] */
+
+/*
+ * R18 (0x12) - ALC2
+ */
+#define WM8962_ALC_LOCK_STS                     0x8000  /* ALC_LOCK_STS */
+#define WM8962_ALC_LOCK_STS_MASK                0x8000  /* ALC_LOCK_STS */
+#define WM8962_ALC_LOCK_STS_SHIFT                   15  /* ALC_LOCK_STS */
+#define WM8962_ALC_LOCK_STS_WIDTH                    1  /* ALC_LOCK_STS */
+#define WM8962_ALC_THRESH_STS                   0x4000  /* ALC_THRESH_STS */
+#define WM8962_ALC_THRESH_STS_MASK              0x4000  /* ALC_THRESH_STS */
+#define WM8962_ALC_THRESH_STS_SHIFT                 14  /* ALC_THRESH_STS */
+#define WM8962_ALC_THRESH_STS_WIDTH                  1  /* ALC_THRESH_STS */
+#define WM8962_ALC_SAT_STS                      0x2000  /* ALC_SAT_STS */
+#define WM8962_ALC_SAT_STS_MASK                 0x2000  /* ALC_SAT_STS */
+#define WM8962_ALC_SAT_STS_SHIFT                    13  /* ALC_SAT_STS */
+#define WM8962_ALC_SAT_STS_WIDTH                     1  /* ALC_SAT_STS */
+#define WM8962_ALC_PKOVR_STS                    0x1000  /* ALC_PKOVR_STS */
+#define WM8962_ALC_PKOVR_STS_MASK               0x1000  /* ALC_PKOVR_STS */
+#define WM8962_ALC_PKOVR_STS_SHIFT                  12  /* ALC_PKOVR_STS */
+#define WM8962_ALC_PKOVR_STS_WIDTH                   1  /* ALC_PKOVR_STS */
+#define WM8962_ALC_NGATE_STS                    0x0800  /* ALC_NGATE_STS */
+#define WM8962_ALC_NGATE_STS_MASK               0x0800  /* ALC_NGATE_STS */
+#define WM8962_ALC_NGATE_STS_SHIFT                  11  /* ALC_NGATE_STS */
+#define WM8962_ALC_NGATE_STS_WIDTH                   1  /* ALC_NGATE_STS */
+#define WM8962_ALC_ZC                           0x0080  /* ALC_ZC */
+#define WM8962_ALC_ZC_MASK                      0x0080  /* ALC_ZC */
+#define WM8962_ALC_ZC_SHIFT                          7  /* ALC_ZC */
+#define WM8962_ALC_ZC_WIDTH                          1  /* ALC_ZC */
+#define WM8962_ALC_MINGAIN_MASK                 0x0070  /* ALC_MINGAIN - [6:4] */
+#define WM8962_ALC_MINGAIN_SHIFT                     4  /* ALC_MINGAIN - [6:4] */
+#define WM8962_ALC_MINGAIN_WIDTH                     3  /* ALC_MINGAIN - [6:4] */
+#define WM8962_ALC_HLD_MASK                     0x000F  /* ALC_HLD - [3:0] */
+#define WM8962_ALC_HLD_SHIFT                         0  /* ALC_HLD - [3:0] */
+#define WM8962_ALC_HLD_WIDTH                         4  /* ALC_HLD - [3:0] */
+
+/*
+ * R19 (0x13) - ALC3
+ */
+#define WM8962_ALC_NGATE_GAIN_MASK              0x1C00  /* ALC_NGATE_GAIN - [12:10] */
+#define WM8962_ALC_NGATE_GAIN_SHIFT                 10  /* ALC_NGATE_GAIN - [12:10] */
+#define WM8962_ALC_NGATE_GAIN_WIDTH                  3  /* ALC_NGATE_GAIN - [12:10] */
+#define WM8962_ALC_MODE                         0x0100  /* ALC_MODE */
+#define WM8962_ALC_MODE_MASK                    0x0100  /* ALC_MODE */
+#define WM8962_ALC_MODE_SHIFT                        8  /* ALC_MODE */
+#define WM8962_ALC_MODE_WIDTH                        1  /* ALC_MODE */
+#define WM8962_ALC_DCY_MASK                     0x00F0  /* ALC_DCY - [7:4] */
+#define WM8962_ALC_DCY_SHIFT                         4  /* ALC_DCY - [7:4] */
+#define WM8962_ALC_DCY_WIDTH                         4  /* ALC_DCY - [7:4] */
+#define WM8962_ALC_ATK_MASK                     0x000F  /* ALC_ATK - [3:0] */
+#define WM8962_ALC_ATK_SHIFT                         0  /* ALC_ATK - [3:0] */
+#define WM8962_ALC_ATK_WIDTH                         4  /* ALC_ATK - [3:0] */
+
+/*
+ * R20 (0x14) - Noise Gate
+ */
+#define WM8962_ALC_NGATE_DCY_MASK               0xF000  /* ALC_NGATE_DCY - [15:12] */
+#define WM8962_ALC_NGATE_DCY_SHIFT                  12  /* ALC_NGATE_DCY - [15:12] */
+#define WM8962_ALC_NGATE_DCY_WIDTH                   4  /* ALC_NGATE_DCY - [15:12] */
+#define WM8962_ALC_NGATE_ATK_MASK               0x0F00  /* ALC_NGATE_ATK - [11:8] */
+#define WM8962_ALC_NGATE_ATK_SHIFT                   8  /* ALC_NGATE_ATK - [11:8] */
+#define WM8962_ALC_NGATE_ATK_WIDTH                   4  /* ALC_NGATE_ATK - [11:8] */
+#define WM8962_ALC_NGATE_THR_MASK               0x00F8  /* ALC_NGATE_THR - [7:3] */
+#define WM8962_ALC_NGATE_THR_SHIFT                   3  /* ALC_NGATE_THR - [7:3] */
+#define WM8962_ALC_NGATE_THR_WIDTH                   5  /* ALC_NGATE_THR - [7:3] */
+#define WM8962_ALC_NGATE_MODE_MASK              0x0006  /* ALC_NGATE_MODE - [2:1] */
+#define WM8962_ALC_NGATE_MODE_SHIFT                  1  /* ALC_NGATE_MODE - [2:1] */
+#define WM8962_ALC_NGATE_MODE_WIDTH                  2  /* ALC_NGATE_MODE - [2:1] */
+#define WM8962_ALC_NGATE_ENA                    0x0001  /* ALC_NGATE_ENA */
+#define WM8962_ALC_NGATE_ENA_MASK               0x0001  /* ALC_NGATE_ENA */
+#define WM8962_ALC_NGATE_ENA_SHIFT                   0  /* ALC_NGATE_ENA */
+#define WM8962_ALC_NGATE_ENA_WIDTH                   1  /* ALC_NGATE_ENA */
+
+/*
+ * R21 (0x15) - Left ADC volume
+ */
+#define WM8962_ADC_VU                           0x0100  /* ADC_VU */
+#define WM8962_ADC_VU_MASK                      0x0100  /* ADC_VU */
+#define WM8962_ADC_VU_SHIFT                          8  /* ADC_VU */
+#define WM8962_ADC_VU_WIDTH                          1  /* ADC_VU */
+#define WM8962_ADCL_VOL_MASK                    0x00FF  /* ADCL_VOL - [7:0] */
+#define WM8962_ADCL_VOL_SHIFT                        0  /* ADCL_VOL - [7:0] */
+#define WM8962_ADCL_VOL_WIDTH                        8  /* ADCL_VOL - [7:0] */
+
+/*
+ * R22 (0x16) - Right ADC volume
+ */
+#define WM8962_ADC_VU                           0x0100  /* ADC_VU */
+#define WM8962_ADC_VU_MASK                      0x0100  /* ADC_VU */
+#define WM8962_ADC_VU_SHIFT                          8  /* ADC_VU */
+#define WM8962_ADC_VU_WIDTH                          1  /* ADC_VU */
+#define WM8962_ADCR_VOL_MASK                    0x00FF  /* ADCR_VOL - [7:0] */
+#define WM8962_ADCR_VOL_SHIFT                        0  /* ADCR_VOL - [7:0] */
+#define WM8962_ADCR_VOL_WIDTH                        8  /* ADCR_VOL - [7:0] */
+
+/*
+ * R23 (0x17) - Additional control(1)
+ */
+#define WM8962_THERR_ACT                        0x0100  /* THERR_ACT */
+#define WM8962_THERR_ACT_MASK                   0x0100  /* THERR_ACT */
+#define WM8962_THERR_ACT_SHIFT                       8  /* THERR_ACT */
+#define WM8962_THERR_ACT_WIDTH                       1  /* THERR_ACT */
+#define WM8962_ADC_BIAS                         0x0040  /* ADC_BIAS */
+#define WM8962_ADC_BIAS_MASK                    0x0040  /* ADC_BIAS */
+#define WM8962_ADC_BIAS_SHIFT                        6  /* ADC_BIAS */
+#define WM8962_ADC_BIAS_WIDTH                        1  /* ADC_BIAS */
+#define WM8962_ADC_HP                           0x0020  /* ADC_HP */
+#define WM8962_ADC_HP_MASK                      0x0020  /* ADC_HP */
+#define WM8962_ADC_HP_SHIFT                          5  /* ADC_HP */
+#define WM8962_ADC_HP_WIDTH                          1  /* ADC_HP */
+#define WM8962_TOCLK_ENA                        0x0001  /* TOCLK_ENA */
+#define WM8962_TOCLK_ENA_MASK                   0x0001  /* TOCLK_ENA */
+#define WM8962_TOCLK_ENA_SHIFT                       0  /* TOCLK_ENA */
+#define WM8962_TOCLK_ENA_WIDTH                       1  /* TOCLK_ENA */
+
+/*
+ * R24 (0x18) - Additional control(2)
+ */
+#define WM8962_AIF_TRI                          0x0008  /* AIF_TRI */
+#define WM8962_AIF_TRI_MASK                     0x0008  /* AIF_TRI */
+#define WM8962_AIF_TRI_SHIFT                         3  /* AIF_TRI */
+#define WM8962_AIF_TRI_WIDTH                         1  /* AIF_TRI */
+
+/*
+ * R25 (0x19) - Pwr Mgmt (1)
+ */
+#define WM8962_DMIC_ENA                         0x0400  /* DMIC_ENA */
+#define WM8962_DMIC_ENA_MASK                    0x0400  /* DMIC_ENA */
+#define WM8962_DMIC_ENA_SHIFT                       10  /* DMIC_ENA */
+#define WM8962_DMIC_ENA_WIDTH                        1  /* DMIC_ENA */
+#define WM8962_OPCLK_ENA                        0x0200  /* OPCLK_ENA */
+#define WM8962_OPCLK_ENA_MASK                   0x0200  /* OPCLK_ENA */
+#define WM8962_OPCLK_ENA_SHIFT                       9  /* OPCLK_ENA */
+#define WM8962_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
+#define WM8962_VMID_SEL_MASK                    0x0180  /* VMID_SEL - [8:7] */
+#define WM8962_VMID_SEL_SHIFT                        7  /* VMID_SEL - [8:7] */
+#define WM8962_VMID_SEL_WIDTH                        2  /* VMID_SEL - [8:7] */
+#define WM8962_BIAS_ENA                         0x0040  /* BIAS_ENA */
+#define WM8962_BIAS_ENA_MASK                    0x0040  /* BIAS_ENA */
+#define WM8962_BIAS_ENA_SHIFT                        6  /* BIAS_ENA */
+#define WM8962_BIAS_ENA_WIDTH                        1  /* BIAS_ENA */
+#define WM8962_INL_ENA                          0x0020  /* INL_ENA */
+#define WM8962_INL_ENA_MASK                     0x0020  /* INL_ENA */
+#define WM8962_INL_ENA_SHIFT                         5  /* INL_ENA */
+#define WM8962_INL_ENA_WIDTH                         1  /* INL_ENA */
+#define WM8962_INR_ENA                          0x0010  /* INR_ENA */
+#define WM8962_INR_ENA_MASK                     0x0010  /* INR_ENA */
+#define WM8962_INR_ENA_SHIFT                         4  /* INR_ENA */
+#define WM8962_INR_ENA_WIDTH                         1  /* INR_ENA */
+#define WM8962_ADCL_ENA                         0x0008  /* ADCL_ENA */
+#define WM8962_ADCL_ENA_MASK                    0x0008  /* ADCL_ENA */
+#define WM8962_ADCL_ENA_SHIFT                        3  /* ADCL_ENA */
+#define WM8962_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
+#define WM8962_ADCR_ENA                         0x0004  /* ADCR_ENA */
+#define WM8962_ADCR_ENA_MASK                    0x0004  /* ADCR_ENA */
+#define WM8962_ADCR_ENA_SHIFT                        2  /* ADCR_ENA */
+#define WM8962_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
+#define WM8962_MICBIAS_ENA                      0x0002  /* MICBIAS_ENA */
+#define WM8962_MICBIAS_ENA_MASK                 0x0002  /* MICBIAS_ENA */
+#define WM8962_MICBIAS_ENA_SHIFT                     1  /* MICBIAS_ENA */
+#define WM8962_MICBIAS_ENA_WIDTH                     1  /* MICBIAS_ENA */
+
+/*
+ * R26 (0x1A) - Pwr Mgmt (2)
+ */
+#define WM8962_DACL_ENA                         0x0100  /* DACL_ENA */
+#define WM8962_DACL_ENA_MASK                    0x0100  /* DACL_ENA */
+#define WM8962_DACL_ENA_SHIFT                        8  /* DACL_ENA */
+#define WM8962_DACL_ENA_WIDTH                        1  /* DACL_ENA */
+#define WM8962_DACR_ENA                         0x0080  /* DACR_ENA */
+#define WM8962_DACR_ENA_MASK                    0x0080  /* DACR_ENA */
+#define WM8962_DACR_ENA_SHIFT                        7  /* DACR_ENA */
+#define WM8962_DACR_ENA_WIDTH                        1  /* DACR_ENA */
+#define WM8962_HPOUTL_PGA_ENA                   0x0040  /* HPOUTL_PGA_ENA */
+#define WM8962_HPOUTL_PGA_ENA_MASK              0x0040  /* HPOUTL_PGA_ENA */
+#define WM8962_HPOUTL_PGA_ENA_SHIFT                  6  /* HPOUTL_PGA_ENA */
+#define WM8962_HPOUTL_PGA_ENA_WIDTH                  1  /* HPOUTL_PGA_ENA */
+#define WM8962_HPOUTR_PGA_ENA                   0x0020  /* HPOUTR_PGA_ENA */
+#define WM8962_HPOUTR_PGA_ENA_MASK              0x0020  /* HPOUTR_PGA_ENA */
+#define WM8962_HPOUTR_PGA_ENA_SHIFT                  5  /* HPOUTR_PGA_ENA */
+#define WM8962_HPOUTR_PGA_ENA_WIDTH                  1  /* HPOUTR_PGA_ENA */
+#define WM8962_SPKOUTL_PGA_ENA                  0x0010  /* SPKOUTL_PGA_ENA */
+#define WM8962_SPKOUTL_PGA_ENA_MASK             0x0010  /* SPKOUTL_PGA_ENA */
+#define WM8962_SPKOUTL_PGA_ENA_SHIFT                 4  /* SPKOUTL_PGA_ENA */
+#define WM8962_SPKOUTL_PGA_ENA_WIDTH                 1  /* SPKOUTL_PGA_ENA */
+#define WM8962_SPKOUTR_PGA_ENA                  0x0008  /* SPKOUTR_PGA_ENA */
+#define WM8962_SPKOUTR_PGA_ENA_MASK             0x0008  /* SPKOUTR_PGA_ENA */
+#define WM8962_SPKOUTR_PGA_ENA_SHIFT                 3  /* SPKOUTR_PGA_ENA */
+#define WM8962_SPKOUTR_PGA_ENA_WIDTH                 1  /* SPKOUTR_PGA_ENA */
+#define WM8962_HPOUTL_PGA_MUTE                  0x0002  /* HPOUTL_PGA_MUTE */
+#define WM8962_HPOUTL_PGA_MUTE_MASK             0x0002  /* HPOUTL_PGA_MUTE */
+#define WM8962_HPOUTL_PGA_MUTE_SHIFT                 1  /* HPOUTL_PGA_MUTE */
+#define WM8962_HPOUTL_PGA_MUTE_WIDTH                 1  /* HPOUTL_PGA_MUTE */
+#define WM8962_HPOUTR_PGA_MUTE                  0x0001  /* HPOUTR_PGA_MUTE */
+#define WM8962_HPOUTR_PGA_MUTE_MASK             0x0001  /* HPOUTR_PGA_MUTE */
+#define WM8962_HPOUTR_PGA_MUTE_SHIFT                 0  /* HPOUTR_PGA_MUTE */
+#define WM8962_HPOUTR_PGA_MUTE_WIDTH                 1  /* HPOUTR_PGA_MUTE */
+
+/*
+ * R27 (0x1B) - Additional Control (3)
+ */
+#define WM8962_SAMPLE_RATE_INT_MODE             0x0010  /* SAMPLE_RATE_INT_MODE */
+#define WM8962_SAMPLE_RATE_INT_MODE_MASK        0x0010  /* SAMPLE_RATE_INT_MODE */
+#define WM8962_SAMPLE_RATE_INT_MODE_SHIFT            4  /* SAMPLE_RATE_INT_MODE */
+#define WM8962_SAMPLE_RATE_INT_MODE_WIDTH            1  /* SAMPLE_RATE_INT_MODE */
+#define WM8962_SAMPLE_RATE_MASK                 0x0007  /* SAMPLE_RATE - [2:0] */
+#define WM8962_SAMPLE_RATE_SHIFT                     0  /* SAMPLE_RATE - [2:0] */
+#define WM8962_SAMPLE_RATE_WIDTH                     3  /* SAMPLE_RATE - [2:0] */
+
+/*
+ * R28 (0x1C) - Anti-pop
+ */
+#define WM8962_STARTUP_BIAS_ENA                 0x0010  /* STARTUP_BIAS_ENA */
+#define WM8962_STARTUP_BIAS_ENA_MASK            0x0010  /* STARTUP_BIAS_ENA */
+#define WM8962_STARTUP_BIAS_ENA_SHIFT                4  /* STARTUP_BIAS_ENA */
+#define WM8962_STARTUP_BIAS_ENA_WIDTH                1  /* STARTUP_BIAS_ENA */
+#define WM8962_VMID_BUF_ENA                     0x0008  /* VMID_BUF_ENA */
+#define WM8962_VMID_BUF_ENA_MASK                0x0008  /* VMID_BUF_ENA */
+#define WM8962_VMID_BUF_ENA_SHIFT                    3  /* VMID_BUF_ENA */
+#define WM8962_VMID_BUF_ENA_WIDTH                    1  /* VMID_BUF_ENA */
+#define WM8962_VMID_RAMP                        0x0004  /* VMID_RAMP */
+#define WM8962_VMID_RAMP_MASK                   0x0004  /* VMID_RAMP */
+#define WM8962_VMID_RAMP_SHIFT                       2  /* VMID_RAMP */
+#define WM8962_VMID_RAMP_WIDTH                       1  /* VMID_RAMP */
+
+/*
+ * R30 (0x1E) - Clocking 3
+ */
+#define WM8962_DBCLK_DIV_MASK                   0xE000  /* DBCLK_DIV - [15:13] */
+#define WM8962_DBCLK_DIV_SHIFT                      13  /* DBCLK_DIV - [15:13] */
+#define WM8962_DBCLK_DIV_WIDTH                       3  /* DBCLK_DIV - [15:13] */
+#define WM8962_OPCLK_DIV_MASK                   0x1C00  /* OPCLK_DIV - [12:10] */
+#define WM8962_OPCLK_DIV_SHIFT                      10  /* OPCLK_DIV - [12:10] */
+#define WM8962_OPCLK_DIV_WIDTH                       3  /* OPCLK_DIV - [12:10] */
+#define WM8962_TOCLK_DIV_MASK                   0x0380  /* TOCLK_DIV - [9:7] */
+#define WM8962_TOCLK_DIV_SHIFT                       7  /* TOCLK_DIV - [9:7] */
+#define WM8962_TOCLK_DIV_WIDTH                       3  /* TOCLK_DIV - [9:7] */
+#define WM8962_F256KCLK_DIV_MASK                0x007E  /* F256KCLK_DIV - [6:1] */
+#define WM8962_F256KCLK_DIV_SHIFT                    1  /* F256KCLK_DIV - [6:1] */
+#define WM8962_F256KCLK_DIV_WIDTH                    6  /* F256KCLK_DIV - [6:1] */
+
+/*
+ * R31 (0x1F) - Input mixer control (1)
+ */
+#define WM8962_MIXINL_MUTE                      0x0008  /* MIXINL_MUTE */
+#define WM8962_MIXINL_MUTE_MASK                 0x0008  /* MIXINL_MUTE */
+#define WM8962_MIXINL_MUTE_SHIFT                     3  /* MIXINL_MUTE */
+#define WM8962_MIXINL_MUTE_WIDTH                     1  /* MIXINL_MUTE */
+#define WM8962_MIXINR_MUTE                      0x0004  /* MIXINR_MUTE */
+#define WM8962_MIXINR_MUTE_MASK                 0x0004  /* MIXINR_MUTE */
+#define WM8962_MIXINR_MUTE_SHIFT                     2  /* MIXINR_MUTE */
+#define WM8962_MIXINR_MUTE_WIDTH                     1  /* MIXINR_MUTE */
+#define WM8962_MIXINL_ENA                       0x0002  /* MIXINL_ENA */
+#define WM8962_MIXINL_ENA_MASK                  0x0002  /* MIXINL_ENA */
+#define WM8962_MIXINL_ENA_SHIFT                      1  /* MIXINL_ENA */
+#define WM8962_MIXINL_ENA_WIDTH                      1  /* MIXINL_ENA */
+#define WM8962_MIXINR_ENA                       0x0001  /* MIXINR_ENA */
+#define WM8962_MIXINR_ENA_MASK                  0x0001  /* MIXINR_ENA */
+#define WM8962_MIXINR_ENA_SHIFT                      0  /* MIXINR_ENA */
+#define WM8962_MIXINR_ENA_WIDTH                      1  /* MIXINR_ENA */
+
+/*
+ * R32 (0x20) - Left input mixer volume
+ */
+#define WM8962_IN2L_MIXINL_VOL_MASK             0x01C0  /* IN2L_MIXINL_VOL - [8:6] */
+#define WM8962_IN2L_MIXINL_VOL_SHIFT                 6  /* IN2L_MIXINL_VOL - [8:6] */
+#define WM8962_IN2L_MIXINL_VOL_WIDTH                 3  /* IN2L_MIXINL_VOL - [8:6] */
+#define WM8962_INPGAL_MIXINL_VOL_MASK           0x0038  /* INPGAL_MIXINL_VOL - [5:3] */
+#define WM8962_INPGAL_MIXINL_VOL_SHIFT               3  /* INPGAL_MIXINL_VOL - [5:3] */
+#define WM8962_INPGAL_MIXINL_VOL_WIDTH               3  /* INPGAL_MIXINL_VOL - [5:3] */
+#define WM8962_IN3L_MIXINL_VOL_MASK             0x0007  /* IN3L_MIXINL_VOL - [2:0] */
+#define WM8962_IN3L_MIXINL_VOL_SHIFT                 0  /* IN3L_MIXINL_VOL - [2:0] */
+#define WM8962_IN3L_MIXINL_VOL_WIDTH                 3  /* IN3L_MIXINL_VOL - [2:0] */
+
+/*
+ * R33 (0x21) - Right input mixer volume
+ */
+#define WM8962_IN2R_MIXINR_VOL_MASK             0x01C0  /* IN2R_MIXINR_VOL - [8:6] */
+#define WM8962_IN2R_MIXINR_VOL_SHIFT                 6  /* IN2R_MIXINR_VOL - [8:6] */
+#define WM8962_IN2R_MIXINR_VOL_WIDTH                 3  /* IN2R_MIXINR_VOL - [8:6] */
+#define WM8962_INPGAR_MIXINR_VOL_MASK           0x0038  /* INPGAR_MIXINR_VOL - [5:3] */
+#define WM8962_INPGAR_MIXINR_VOL_SHIFT               3  /* INPGAR_MIXINR_VOL - [5:3] */
+#define WM8962_INPGAR_MIXINR_VOL_WIDTH               3  /* INPGAR_MIXINR_VOL - [5:3] */
+#define WM8962_IN3R_MIXINR_VOL_MASK             0x0007  /* IN3R_MIXINR_VOL - [2:0] */
+#define WM8962_IN3R_MIXINR_VOL_SHIFT                 0  /* IN3R_MIXINR_VOL - [2:0] */
+#define WM8962_IN3R_MIXINR_VOL_WIDTH                 3  /* IN3R_MIXINR_VOL - [2:0] */
+
+/*
+ * R34 (0x22) - Input mixer control (2)
+ */
+#define WM8962_IN2L_TO_MIXINL                   0x0020  /* IN2L_TO_MIXINL */
+#define WM8962_IN2L_TO_MIXINL_MASK              0x0020  /* IN2L_TO_MIXINL */
+#define WM8962_IN2L_TO_MIXINL_SHIFT                  5  /* IN2L_TO_MIXINL */
+#define WM8962_IN2L_TO_MIXINL_WIDTH                  1  /* IN2L_TO_MIXINL */
+#define WM8962_IN3L_TO_MIXINL                   0x0010  /* IN3L_TO_MIXINL */
+#define WM8962_IN3L_TO_MIXINL_MASK              0x0010  /* IN3L_TO_MIXINL */
+#define WM8962_IN3L_TO_MIXINL_SHIFT                  4  /* IN3L_TO_MIXINL */
+#define WM8962_IN3L_TO_MIXINL_WIDTH                  1  /* IN3L_TO_MIXINL */
+#define WM8962_INPGAL_TO_MIXINL                 0x0008  /* INPGAL_TO_MIXINL */
+#define WM8962_INPGAL_TO_MIXINL_MASK            0x0008  /* INPGAL_TO_MIXINL */
+#define WM8962_INPGAL_TO_MIXINL_SHIFT                3  /* INPGAL_TO_MIXINL */
+#define WM8962_INPGAL_TO_MIXINL_WIDTH                1  /* INPGAL_TO_MIXINL */
+#define WM8962_IN2R_TO_MIXINR                   0x0004  /* IN2R_TO_MIXINR */
+#define WM8962_IN2R_TO_MIXINR_MASK              0x0004  /* IN2R_TO_MIXINR */
+#define WM8962_IN2R_TO_MIXINR_SHIFT                  2  /* IN2R_TO_MIXINR */
+#define WM8962_IN2R_TO_MIXINR_WIDTH                  1  /* IN2R_TO_MIXINR */
+#define WM8962_IN3R_TO_MIXINR                   0x0002  /* IN3R_TO_MIXINR */
+#define WM8962_IN3R_TO_MIXINR_MASK              0x0002  /* IN3R_TO_MIXINR */
+#define WM8962_IN3R_TO_MIXINR_SHIFT                  1  /* IN3R_TO_MIXINR */
+#define WM8962_IN3R_TO_MIXINR_WIDTH                  1  /* IN3R_TO_MIXINR */
+#define WM8962_INPGAR_TO_MIXINR                 0x0001  /* INPGAR_TO_MIXINR */
+#define WM8962_INPGAR_TO_MIXINR_MASK            0x0001  /* INPGAR_TO_MIXINR */
+#define WM8962_INPGAR_TO_MIXINR_SHIFT                0  /* INPGAR_TO_MIXINR */
+#define WM8962_INPGAR_TO_MIXINR_WIDTH                1  /* INPGAR_TO_MIXINR */
+
+/*
+ * R35 (0x23) - Input bias control
+ */
+#define WM8962_MIXIN_BIAS_MASK                  0x0038  /* MIXIN_BIAS - [5:3] */
+#define WM8962_MIXIN_BIAS_SHIFT                      3  /* MIXIN_BIAS - [5:3] */
+#define WM8962_MIXIN_BIAS_WIDTH                      3  /* MIXIN_BIAS - [5:3] */
+#define WM8962_INPGA_BIAS_MASK                  0x0007  /* INPGA_BIAS - [2:0] */
+#define WM8962_INPGA_BIAS_SHIFT                      0  /* INPGA_BIAS - [2:0] */
+#define WM8962_INPGA_BIAS_WIDTH                      3  /* INPGA_BIAS - [2:0] */
+
+/*
+ * R37 (0x25) - Left input PGA control
+ */
+#define WM8962_INPGAL_ENA                       0x0010  /* INPGAL_ENA */
+#define WM8962_INPGAL_ENA_MASK                  0x0010  /* INPGAL_ENA */
+#define WM8962_INPGAL_ENA_SHIFT                      4  /* INPGAL_ENA */
+#define WM8962_INPGAL_ENA_WIDTH                      1  /* INPGAL_ENA */
+#define WM8962_IN1L_TO_INPGAL                   0x0008  /* IN1L_TO_INPGAL */
+#define WM8962_IN1L_TO_INPGAL_MASK              0x0008  /* IN1L_TO_INPGAL */
+#define WM8962_IN1L_TO_INPGAL_SHIFT                  3  /* IN1L_TO_INPGAL */
+#define WM8962_IN1L_TO_INPGAL_WIDTH                  1  /* IN1L_TO_INPGAL */
+#define WM8962_IN2L_TO_INPGAL                   0x0004  /* IN2L_TO_INPGAL */
+#define WM8962_IN2L_TO_INPGAL_MASK              0x0004  /* IN2L_TO_INPGAL */
+#define WM8962_IN2L_TO_INPGAL_SHIFT                  2  /* IN2L_TO_INPGAL */
+#define WM8962_IN2L_TO_INPGAL_WIDTH                  1  /* IN2L_TO_INPGAL */
+#define WM8962_IN3L_TO_INPGAL                   0x0002  /* IN3L_TO_INPGAL */
+#define WM8962_IN3L_TO_INPGAL_MASK              0x0002  /* IN3L_TO_INPGAL */
+#define WM8962_IN3L_TO_INPGAL_SHIFT                  1  /* IN3L_TO_INPGAL */
+#define WM8962_IN3L_TO_INPGAL_WIDTH                  1  /* IN3L_TO_INPGAL */
+#define WM8962_IN4L_TO_INPGAL                   0x0001  /* IN4L_TO_INPGAL */
+#define WM8962_IN4L_TO_INPGAL_MASK              0x0001  /* IN4L_TO_INPGAL */
+#define WM8962_IN4L_TO_INPGAL_SHIFT                  0  /* IN4L_TO_INPGAL */
+#define WM8962_IN4L_TO_INPGAL_WIDTH                  1  /* IN4L_TO_INPGAL */
+
+/*
+ * R38 (0x26) - Right input PGA control
+ */
+#define WM8962_INPGAR_ENA                       0x0010  /* INPGAR_ENA */
+#define WM8962_INPGAR_ENA_MASK                  0x0010  /* INPGAR_ENA */
+#define WM8962_INPGAR_ENA_SHIFT                      4  /* INPGAR_ENA */
+#define WM8962_INPGAR_ENA_WIDTH                      1  /* INPGAR_ENA */
+#define WM8962_IN1R_TO_INPGAR                   0x0008  /* IN1R_TO_INPGAR */
+#define WM8962_IN1R_TO_INPGAR_MASK              0x0008  /* IN1R_TO_INPGAR */
+#define WM8962_IN1R_TO_INPGAR_SHIFT                  3  /* IN1R_TO_INPGAR */
+#define WM8962_IN1R_TO_INPGAR_WIDTH                  1  /* IN1R_TO_INPGAR */
+#define WM8962_IN2R_TO_INPGAR                   0x0004  /* IN2R_TO_INPGAR */
+#define WM8962_IN2R_TO_INPGAR_MASK              0x0004  /* IN2R_TO_INPGAR */
+#define WM8962_IN2R_TO_INPGAR_SHIFT                  2  /* IN2R_TO_INPGAR */
+#define WM8962_IN2R_TO_INPGAR_WIDTH                  1  /* IN2R_TO_INPGAR */
+#define WM8962_IN3R_TO_INPGAR                   0x0002  /* IN3R_TO_INPGAR */
+#define WM8962_IN3R_TO_INPGAR_MASK              0x0002  /* IN3R_TO_INPGAR */
+#define WM8962_IN3R_TO_INPGAR_SHIFT                  1  /* IN3R_TO_INPGAR */
+#define WM8962_IN3R_TO_INPGAR_WIDTH                  1  /* IN3R_TO_INPGAR */
+#define WM8962_IN4R_TO_INPGAR                   0x0001  /* IN4R_TO_INPGAR */
+#define WM8962_IN4R_TO_INPGAR_MASK              0x0001  /* IN4R_TO_INPGAR */
+#define WM8962_IN4R_TO_INPGAR_SHIFT                  0  /* IN4R_TO_INPGAR */
+#define WM8962_IN4R_TO_INPGAR_WIDTH                  1  /* IN4R_TO_INPGAR */
+
+/*
+ * R40 (0x28) - SPKOUTL volume
+ */
+#define WM8962_SPKOUT_VU                        0x0100  /* SPKOUT_VU */
+#define WM8962_SPKOUT_VU_MASK                   0x0100  /* SPKOUT_VU */
+#define WM8962_SPKOUT_VU_SHIFT                       8  /* SPKOUT_VU */
+#define WM8962_SPKOUT_VU_WIDTH                       1  /* SPKOUT_VU */
+#define WM8962_SPKOUTL_ZC                       0x0080  /* SPKOUTL_ZC */
+#define WM8962_SPKOUTL_ZC_MASK                  0x0080  /* SPKOUTL_ZC */
+#define WM8962_SPKOUTL_ZC_SHIFT                      7  /* SPKOUTL_ZC */
+#define WM8962_SPKOUTL_ZC_WIDTH                      1  /* SPKOUTL_ZC */
+#define WM8962_SPKOUTL_VOL_MASK                 0x007F  /* SPKOUTL_VOL - [6:0] */
+#define WM8962_SPKOUTL_VOL_SHIFT                     0  /* SPKOUTL_VOL - [6:0] */
+#define WM8962_SPKOUTL_VOL_WIDTH                     7  /* SPKOUTL_VOL - [6:0] */
+
+/*
+ * R41 (0x29) - SPKOUTR volume
+ */
+#define WM8962_SPKOUTR_ZC                       0x0080  /* SPKOUTR_ZC */
+#define WM8962_SPKOUTR_ZC_MASK                  0x0080  /* SPKOUTR_ZC */
+#define WM8962_SPKOUTR_ZC_SHIFT                      7  /* SPKOUTR_ZC */
+#define WM8962_SPKOUTR_ZC_WIDTH                      1  /* SPKOUTR_ZC */
+#define WM8962_SPKOUTR_VOL_MASK                 0x007F  /* SPKOUTR_VOL - [6:0] */
+#define WM8962_SPKOUTR_VOL_SHIFT                     0  /* SPKOUTR_VOL - [6:0] */
+#define WM8962_SPKOUTR_VOL_WIDTH                     7  /* SPKOUTR_VOL - [6:0] */
+
+/*
+ * R47 (0x2F) - Thermal Shutdown Status
+ */
+#define WM8962_TEMP_ERR_HP                      0x0008  /* TEMP_ERR_HP */
+#define WM8962_TEMP_ERR_HP_MASK                 0x0008  /* TEMP_ERR_HP */
+#define WM8962_TEMP_ERR_HP_SHIFT                     3  /* TEMP_ERR_HP */
+#define WM8962_TEMP_ERR_HP_WIDTH                     1  /* TEMP_ERR_HP */
+#define WM8962_TEMP_WARN_HP                     0x0004  /* TEMP_WARN_HP */
+#define WM8962_TEMP_WARN_HP_MASK                0x0004  /* TEMP_WARN_HP */
+#define WM8962_TEMP_WARN_HP_SHIFT                    2  /* TEMP_WARN_HP */
+#define WM8962_TEMP_WARN_HP_WIDTH                    1  /* TEMP_WARN_HP */
+#define WM8962_TEMP_ERR_SPK                     0x0002  /* TEMP_ERR_SPK */
+#define WM8962_TEMP_ERR_SPK_MASK                0x0002  /* TEMP_ERR_SPK */
+#define WM8962_TEMP_ERR_SPK_SHIFT                    1  /* TEMP_ERR_SPK */
+#define WM8962_TEMP_ERR_SPK_WIDTH                    1  /* TEMP_ERR_SPK */
+#define WM8962_TEMP_WARN_SPK                    0x0001  /* TEMP_WARN_SPK */
+#define WM8962_TEMP_WARN_SPK_MASK               0x0001  /* TEMP_WARN_SPK */
+#define WM8962_TEMP_WARN_SPK_SHIFT                   0  /* TEMP_WARN_SPK */
+#define WM8962_TEMP_WARN_SPK_WIDTH                   1  /* TEMP_WARN_SPK */
+
+/*
+ * R48 (0x30) - Additional Control (4)
+ */
+#define WM8962_MICDET_THR_MASK                  0x7000  /* MICDET_THR - [14:12] */
+#define WM8962_MICDET_THR_SHIFT                     12  /* MICDET_THR - [14:12] */
+#define WM8962_MICDET_THR_WIDTH                      3  /* MICDET_THR - [14:12] */
+#define WM8962_MICSHORT_THR_MASK                0x0C00  /* MICSHORT_THR - [11:10] */
+#define WM8962_MICSHORT_THR_SHIFT                   10  /* MICSHORT_THR - [11:10] */
+#define WM8962_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [11:10] */
+#define WM8962_MICDET_ENA                       0x0200  /* MICDET_ENA */
+#define WM8962_MICDET_ENA_MASK                  0x0200  /* MICDET_ENA */
+#define WM8962_MICDET_ENA_SHIFT                      9  /* MICDET_ENA */
+#define WM8962_MICDET_ENA_WIDTH                      1  /* MICDET_ENA */
+#define WM8962_MICDET_STS                       0x0080  /* MICDET_STS */
+#define WM8962_MICDET_STS_MASK                  0x0080  /* MICDET_STS */
+#define WM8962_MICDET_STS_SHIFT                      7  /* MICDET_STS */
+#define WM8962_MICDET_STS_WIDTH                      1  /* MICDET_STS */
+#define WM8962_MICSHORT_STS                     0x0040  /* MICSHORT_STS */
+#define WM8962_MICSHORT_STS_MASK                0x0040  /* MICSHORT_STS */
+#define WM8962_MICSHORT_STS_SHIFT                    6  /* MICSHORT_STS */
+#define WM8962_MICSHORT_STS_WIDTH                    1  /* MICSHORT_STS */
+#define WM8962_TEMP_ENA_HP                      0x0004  /* TEMP_ENA_HP */
+#define WM8962_TEMP_ENA_HP_MASK                 0x0004  /* TEMP_ENA_HP */
+#define WM8962_TEMP_ENA_HP_SHIFT                     2  /* TEMP_ENA_HP */
+#define WM8962_TEMP_ENA_HP_WIDTH                     1  /* TEMP_ENA_HP */
+#define WM8962_TEMP_ENA_SPK                     0x0002  /* TEMP_ENA_SPK */
+#define WM8962_TEMP_ENA_SPK_MASK                0x0002  /* TEMP_ENA_SPK */
+#define WM8962_TEMP_ENA_SPK_SHIFT                    1  /* TEMP_ENA_SPK */
+#define WM8962_TEMP_ENA_SPK_WIDTH                    1  /* TEMP_ENA_SPK */
+#define WM8962_MICBIAS_LVL                      0x0001  /* MICBIAS_LVL */
+#define WM8962_MICBIAS_LVL_MASK                 0x0001  /* MICBIAS_LVL */
+#define WM8962_MICBIAS_LVL_SHIFT                     0  /* MICBIAS_LVL */
+#define WM8962_MICBIAS_LVL_WIDTH                     1  /* MICBIAS_LVL */
+
+/*
+ * R49 (0x31) - Class D Control 1
+ */
+#define WM8962_SPKOUTR_ENA                      0x0080  /* SPKOUTR_ENA */
+#define WM8962_SPKOUTR_ENA_MASK                 0x0080  /* SPKOUTR_ENA */
+#define WM8962_SPKOUTR_ENA_SHIFT                     7  /* SPKOUTR_ENA */
+#define WM8962_SPKOUTR_ENA_WIDTH                     1  /* SPKOUTR_ENA */
+#define WM8962_SPKOUTL_ENA                      0x0040  /* SPKOUTL_ENA */
+#define WM8962_SPKOUTL_ENA_MASK                 0x0040  /* SPKOUTL_ENA */
+#define WM8962_SPKOUTL_ENA_SHIFT                     6  /* SPKOUTL_ENA */
+#define WM8962_SPKOUTL_ENA_WIDTH                     1  /* SPKOUTL_ENA */
+#define WM8962_SPKOUTL_PGA_MUTE                 0x0002  /* SPKOUTL_PGA_MUTE */
+#define WM8962_SPKOUTL_PGA_MUTE_MASK            0x0002  /* SPKOUTL_PGA_MUTE */
+#define WM8962_SPKOUTL_PGA_MUTE_SHIFT                1  /* SPKOUTL_PGA_MUTE */
+#define WM8962_SPKOUTL_PGA_MUTE_WIDTH                1  /* SPKOUTL_PGA_MUTE */
+#define WM8962_SPKOUTR_PGA_MUTE                 0x0001  /* SPKOUTR_PGA_MUTE */
+#define WM8962_SPKOUTR_PGA_MUTE_MASK            0x0001  /* SPKOUTR_PGA_MUTE */
+#define WM8962_SPKOUTR_PGA_MUTE_SHIFT                0  /* SPKOUTR_PGA_MUTE */
+#define WM8962_SPKOUTR_PGA_MUTE_WIDTH                1  /* SPKOUTR_PGA_MUTE */
+
+/*
+ * R51 (0x33) - Class D Control 2
+ */
+#define WM8962_SPK_MONO                         0x0040  /* SPK_MONO */
+#define WM8962_SPK_MONO_MASK                    0x0040  /* SPK_MONO */
+#define WM8962_SPK_MONO_SHIFT                        6  /* SPK_MONO */
+#define WM8962_SPK_MONO_WIDTH                        1  /* SPK_MONO */
+#define WM8962_CLASSD_VOL_MASK                  0x0007  /* CLASSD_VOL - [2:0] */
+#define WM8962_CLASSD_VOL_SHIFT                      0  /* CLASSD_VOL - [2:0] */
+#define WM8962_CLASSD_VOL_WIDTH                      3  /* CLASSD_VOL - [2:0] */
+
+/*
+ * R56 (0x38) - Clocking 4
+ */
+#define WM8962_SYSCLK_RATE_MASK                 0x001E  /* SYSCLK_RATE - [4:1] */
+#define WM8962_SYSCLK_RATE_SHIFT                     1  /* SYSCLK_RATE - [4:1] */
+#define WM8962_SYSCLK_RATE_WIDTH                     4  /* SYSCLK_RATE - [4:1] */
+
+/*
+ * R57 (0x39) - DAC DSP Mixing (1)
+ */
+#define WM8962_DAC_MONOMIX                      0x0200  /* DAC_MONOMIX */
+#define WM8962_DAC_MONOMIX_MASK                 0x0200  /* DAC_MONOMIX */
+#define WM8962_DAC_MONOMIX_SHIFT                     9  /* DAC_MONOMIX */
+#define WM8962_DAC_MONOMIX_WIDTH                     1  /* DAC_MONOMIX */
+#define WM8962_ADCR_DAC_SVOL_MASK               0x00F0  /* ADCR_DAC_SVOL - [7:4] */
+#define WM8962_ADCR_DAC_SVOL_SHIFT                   4  /* ADCR_DAC_SVOL - [7:4] */
+#define WM8962_ADCR_DAC_SVOL_WIDTH                   4  /* ADCR_DAC_SVOL - [7:4] */
+#define WM8962_ADC_TO_DACR_MASK                 0x000C  /* ADC_TO_DACR - [3:2] */
+#define WM8962_ADC_TO_DACR_SHIFT                     2  /* ADC_TO_DACR - [3:2] */
+#define WM8962_ADC_TO_DACR_WIDTH                     2  /* ADC_TO_DACR - [3:2] */
+
+/*
+ * R58 (0x3A) - DAC DSP Mixing (2)
+ */
+#define WM8962_ADCL_DAC_SVOL_MASK               0x00F0  /* ADCL_DAC_SVOL - [7:4] */
+#define WM8962_ADCL_DAC_SVOL_SHIFT                   4  /* ADCL_DAC_SVOL - [7:4] */
+#define WM8962_ADCL_DAC_SVOL_WIDTH                   4  /* ADCL_DAC_SVOL - [7:4] */
+#define WM8962_ADC_TO_DACL_MASK                 0x000C  /* ADC_TO_DACL - [3:2] */
+#define WM8962_ADC_TO_DACL_SHIFT                     2  /* ADC_TO_DACL - [3:2] */
+#define WM8962_ADC_TO_DACL_WIDTH                     2  /* ADC_TO_DACL - [3:2] */
+
+/*
+ * R60 (0x3C) - DC Servo 0
+ */
+#define WM8962_INL_DCS_ENA                      0x0080  /* INL_DCS_ENA */
+#define WM8962_INL_DCS_ENA_MASK                 0x0080  /* INL_DCS_ENA */
+#define WM8962_INL_DCS_ENA_SHIFT                     7  /* INL_DCS_ENA */
+#define WM8962_INL_DCS_ENA_WIDTH                     1  /* INL_DCS_ENA */
+#define WM8962_INL_DCS_STARTUP                  0x0040  /* INL_DCS_STARTUP */
+#define WM8962_INL_DCS_STARTUP_MASK             0x0040  /* INL_DCS_STARTUP */
+#define WM8962_INL_DCS_STARTUP_SHIFT                 6  /* INL_DCS_STARTUP */
+#define WM8962_INL_DCS_STARTUP_WIDTH                 1  /* INL_DCS_STARTUP */
+#define WM8962_INR_DCS_ENA                      0x0008  /* INR_DCS_ENA */
+#define WM8962_INR_DCS_ENA_MASK                 0x0008  /* INR_DCS_ENA */
+#define WM8962_INR_DCS_ENA_SHIFT                     3  /* INR_DCS_ENA */
+#define WM8962_INR_DCS_ENA_WIDTH                     1  /* INR_DCS_ENA */
+#define WM8962_INR_DCS_STARTUP                  0x0004  /* INR_DCS_STARTUP */
+#define WM8962_INR_DCS_STARTUP_MASK             0x0004  /* INR_DCS_STARTUP */
+#define WM8962_INR_DCS_STARTUP_SHIFT                 2  /* INR_DCS_STARTUP */
+#define WM8962_INR_DCS_STARTUP_WIDTH                 1  /* INR_DCS_STARTUP */
+
+/*
+ * R61 (0x3D) - DC Servo 1
+ */
+#define WM8962_HP1L_DCS_ENA                     0x0080  /* HP1L_DCS_ENA */
+#define WM8962_HP1L_DCS_ENA_MASK                0x0080  /* HP1L_DCS_ENA */
+#define WM8962_HP1L_DCS_ENA_SHIFT                    7  /* HP1L_DCS_ENA */
+#define WM8962_HP1L_DCS_ENA_WIDTH                    1  /* HP1L_DCS_ENA */
+#define WM8962_HP1L_DCS_STARTUP                 0x0040  /* HP1L_DCS_STARTUP */
+#define WM8962_HP1L_DCS_STARTUP_MASK            0x0040  /* HP1L_DCS_STARTUP */
+#define WM8962_HP1L_DCS_STARTUP_SHIFT                6  /* HP1L_DCS_STARTUP */
+#define WM8962_HP1L_DCS_STARTUP_WIDTH                1  /* HP1L_DCS_STARTUP */
+#define WM8962_HP1L_DCS_SYNC                    0x0010  /* HP1L_DCS_SYNC */
+#define WM8962_HP1L_DCS_SYNC_MASK               0x0010  /* HP1L_DCS_SYNC */
+#define WM8962_HP1L_DCS_SYNC_SHIFT                   4  /* HP1L_DCS_SYNC */
+#define WM8962_HP1L_DCS_SYNC_WIDTH                   1  /* HP1L_DCS_SYNC */
+#define WM8962_HP1R_DCS_ENA                     0x0008  /* HP1R_DCS_ENA */
+#define WM8962_HP1R_DCS_ENA_MASK                0x0008  /* HP1R_DCS_ENA */
+#define WM8962_HP1R_DCS_ENA_SHIFT                    3  /* HP1R_DCS_ENA */
+#define WM8962_HP1R_DCS_ENA_WIDTH                    1  /* HP1R_DCS_ENA */
+#define WM8962_HP1R_DCS_STARTUP                 0x0004  /* HP1R_DCS_STARTUP */
+#define WM8962_HP1R_DCS_STARTUP_MASK            0x0004  /* HP1R_DCS_STARTUP */
+#define WM8962_HP1R_DCS_STARTUP_SHIFT                2  /* HP1R_DCS_STARTUP */
+#define WM8962_HP1R_DCS_STARTUP_WIDTH                1  /* HP1R_DCS_STARTUP */
+#define WM8962_HP1R_DCS_SYNC                    0x0001  /* HP1R_DCS_SYNC */
+#define WM8962_HP1R_DCS_SYNC_MASK               0x0001  /* HP1R_DCS_SYNC */
+#define WM8962_HP1R_DCS_SYNC_SHIFT                   0  /* HP1R_DCS_SYNC */
+#define WM8962_HP1R_DCS_SYNC_WIDTH                   1  /* HP1R_DCS_SYNC */
+
+/*
+ * R64 (0x40) - DC Servo 4
+ */
+#define WM8962_HP1_DCS_SYNC_STEPS_MASK          0x3F80  /* HP1_DCS_SYNC_STEPS - [13:7] */
+#define WM8962_HP1_DCS_SYNC_STEPS_SHIFT              7  /* HP1_DCS_SYNC_STEPS - [13:7] */
+#define WM8962_HP1_DCS_SYNC_STEPS_WIDTH              7  /* HP1_DCS_SYNC_STEPS - [13:7] */
+
+/*
+ * R66 (0x42) - DC Servo 6
+ */
+#define WM8962_DCS_STARTUP_DONE_INL             0x0400  /* DCS_STARTUP_DONE_INL */
+#define WM8962_DCS_STARTUP_DONE_INL_MASK        0x0400  /* DCS_STARTUP_DONE_INL */
+#define WM8962_DCS_STARTUP_DONE_INL_SHIFT           10  /* DCS_STARTUP_DONE_INL */
+#define WM8962_DCS_STARTUP_DONE_INL_WIDTH            1  /* DCS_STARTUP_DONE_INL */
+#define WM8962_DCS_STARTUP_DONE_INR             0x0200  /* DCS_STARTUP_DONE_INR */
+#define WM8962_DCS_STARTUP_DONE_INR_MASK        0x0200  /* DCS_STARTUP_DONE_INR */
+#define WM8962_DCS_STARTUP_DONE_INR_SHIFT            9  /* DCS_STARTUP_DONE_INR */
+#define WM8962_DCS_STARTUP_DONE_INR_WIDTH            1  /* DCS_STARTUP_DONE_INR */
+#define WM8962_DCS_STARTUP_DONE_HP1L            0x0100  /* DCS_STARTUP_DONE_HP1L */
+#define WM8962_DCS_STARTUP_DONE_HP1L_MASK       0x0100  /* DCS_STARTUP_DONE_HP1L */
+#define WM8962_DCS_STARTUP_DONE_HP1L_SHIFT           8  /* DCS_STARTUP_DONE_HP1L */
+#define WM8962_DCS_STARTUP_DONE_HP1L_WIDTH           1  /* DCS_STARTUP_DONE_HP1L */
+#define WM8962_DCS_STARTUP_DONE_HP1R            0x0080  /* DCS_STARTUP_DONE_HP1R */
+#define WM8962_DCS_STARTUP_DONE_HP1R_MASK       0x0080  /* DCS_STARTUP_DONE_HP1R */
+#define WM8962_DCS_STARTUP_DONE_HP1R_SHIFT           7  /* DCS_STARTUP_DONE_HP1R */
+#define WM8962_DCS_STARTUP_DONE_HP1R_WIDTH           1  /* DCS_STARTUP_DONE_HP1R */
+
+/*
+ * R68 (0x44) - Analogue PGA Bias
+ */
+#define WM8962_HP_PGAS_BIAS_MASK                0x0007  /* HP_PGAS_BIAS - [2:0] */
+#define WM8962_HP_PGAS_BIAS_SHIFT                    0  /* HP_PGAS_BIAS - [2:0] */
+#define WM8962_HP_PGAS_BIAS_WIDTH                    3  /* HP_PGAS_BIAS - [2:0] */
+
+/*
+ * R69 (0x45) - Analogue HP 0
+ */
+#define WM8962_HP1L_RMV_SHORT                   0x0080  /* HP1L_RMV_SHORT */
+#define WM8962_HP1L_RMV_SHORT_MASK              0x0080  /* HP1L_RMV_SHORT */
+#define WM8962_HP1L_RMV_SHORT_SHIFT                  7  /* HP1L_RMV_SHORT */
+#define WM8962_HP1L_RMV_SHORT_WIDTH                  1  /* HP1L_RMV_SHORT */
+#define WM8962_HP1L_ENA_OUTP                    0x0040  /* HP1L_ENA_OUTP */
+#define WM8962_HP1L_ENA_OUTP_MASK               0x0040  /* HP1L_ENA_OUTP */
+#define WM8962_HP1L_ENA_OUTP_SHIFT                   6  /* HP1L_ENA_OUTP */
+#define WM8962_HP1L_ENA_OUTP_WIDTH                   1  /* HP1L_ENA_OUTP */
+#define WM8962_HP1L_ENA_DLY                     0x0020  /* HP1L_ENA_DLY */
+#define WM8962_HP1L_ENA_DLY_MASK                0x0020  /* HP1L_ENA_DLY */
+#define WM8962_HP1L_ENA_DLY_SHIFT                    5  /* HP1L_ENA_DLY */
+#define WM8962_HP1L_ENA_DLY_WIDTH                    1  /* HP1L_ENA_DLY */
+#define WM8962_HP1L_ENA                         0x0010  /* HP1L_ENA */
+#define WM8962_HP1L_ENA_MASK                    0x0010  /* HP1L_ENA */
+#define WM8962_HP1L_ENA_SHIFT                        4  /* HP1L_ENA */
+#define WM8962_HP1L_ENA_WIDTH                        1  /* HP1L_ENA */
+#define WM8962_HP1R_RMV_SHORT                   0x0008  /* HP1R_RMV_SHORT */
+#define WM8962_HP1R_RMV_SHORT_MASK              0x0008  /* HP1R_RMV_SHORT */
+#define WM8962_HP1R_RMV_SHORT_SHIFT                  3  /* HP1R_RMV_SHORT */
+#define WM8962_HP1R_RMV_SHORT_WIDTH                  1  /* HP1R_RMV_SHORT */
+#define WM8962_HP1R_ENA_OUTP                    0x0004  /* HP1R_ENA_OUTP */
+#define WM8962_HP1R_ENA_OUTP_MASK               0x0004  /* HP1R_ENA_OUTP */
+#define WM8962_HP1R_ENA_OUTP_SHIFT                   2  /* HP1R_ENA_OUTP */
+#define WM8962_HP1R_ENA_OUTP_WIDTH                   1  /* HP1R_ENA_OUTP */
+#define WM8962_HP1R_ENA_DLY                     0x0002  /* HP1R_ENA_DLY */
+#define WM8962_HP1R_ENA_DLY_MASK                0x0002  /* HP1R_ENA_DLY */
+#define WM8962_HP1R_ENA_DLY_SHIFT                    1  /* HP1R_ENA_DLY */
+#define WM8962_HP1R_ENA_DLY_WIDTH                    1  /* HP1R_ENA_DLY */
+#define WM8962_HP1R_ENA                         0x0001  /* HP1R_ENA */
+#define WM8962_HP1R_ENA_MASK                    0x0001  /* HP1R_ENA */
+#define WM8962_HP1R_ENA_SHIFT                        0  /* HP1R_ENA */
+#define WM8962_HP1R_ENA_WIDTH                        1  /* HP1R_ENA */
+
+/*
+ * R71 (0x47) - Analogue HP 2
+ */
+#define WM8962_HP1L_VOL_MASK                    0x01C0  /* HP1L_VOL - [8:6] */
+#define WM8962_HP1L_VOL_SHIFT                        6  /* HP1L_VOL - [8:6] */
+#define WM8962_HP1L_VOL_WIDTH                        3  /* HP1L_VOL - [8:6] */
+#define WM8962_HP1R_VOL_MASK                    0x0038  /* HP1R_VOL - [5:3] */
+#define WM8962_HP1R_VOL_SHIFT                        3  /* HP1R_VOL - [5:3] */
+#define WM8962_HP1R_VOL_WIDTH                        3  /* HP1R_VOL - [5:3] */
+#define WM8962_HP_BIAS_BOOST_MASK               0x0007  /* HP_BIAS_BOOST - [2:0] */
+#define WM8962_HP_BIAS_BOOST_SHIFT                   0  /* HP_BIAS_BOOST - [2:0] */
+#define WM8962_HP_BIAS_BOOST_WIDTH                   3  /* HP_BIAS_BOOST - [2:0] */
+
+/*
+ * R72 (0x48) - Charge Pump 1
+ */
+#define WM8962_CP_ENA                           0x0001  /* CP_ENA */
+#define WM8962_CP_ENA_MASK                      0x0001  /* CP_ENA */
+#define WM8962_CP_ENA_SHIFT                          0  /* CP_ENA */
+#define WM8962_CP_ENA_WIDTH                          1  /* CP_ENA */
+
+/*
+ * R82 (0x52) - Charge Pump B
+ */
+#define WM8962_CP_DYN_PWR                       0x0001  /* CP_DYN_PWR */
+#define WM8962_CP_DYN_PWR_MASK                  0x0001  /* CP_DYN_PWR */
+#define WM8962_CP_DYN_PWR_SHIFT                      0  /* CP_DYN_PWR */
+#define WM8962_CP_DYN_PWR_WIDTH                      1  /* CP_DYN_PWR */
+
+/*
+ * R87 (0x57) - Write Sequencer Control 1
+ */
+#define WM8962_WSEQ_AUTOSEQ_ENA                 0x0080  /* WSEQ_AUTOSEQ_ENA */
+#define WM8962_WSEQ_AUTOSEQ_ENA_MASK            0x0080  /* WSEQ_AUTOSEQ_ENA */
+#define WM8962_WSEQ_AUTOSEQ_ENA_SHIFT                7  /* WSEQ_AUTOSEQ_ENA */
+#define WM8962_WSEQ_AUTOSEQ_ENA_WIDTH                1  /* WSEQ_AUTOSEQ_ENA */
+#define WM8962_WSEQ_ENA                         0x0020  /* WSEQ_ENA */
+#define WM8962_WSEQ_ENA_MASK                    0x0020  /* WSEQ_ENA */
+#define WM8962_WSEQ_ENA_SHIFT                        5  /* WSEQ_ENA */
+#define WM8962_WSEQ_ENA_WIDTH                        1  /* WSEQ_ENA */
+
+/*
+ * R90 (0x5A) - Write Sequencer Control 2
+ */
+#define WM8962_WSEQ_ABORT                       0x0100  /* WSEQ_ABORT */
+#define WM8962_WSEQ_ABORT_MASK                  0x0100  /* WSEQ_ABORT */
+#define WM8962_WSEQ_ABORT_SHIFT                      8  /* WSEQ_ABORT */
+#define WM8962_WSEQ_ABORT_WIDTH                      1  /* WSEQ_ABORT */
+#define WM8962_WSEQ_START                       0x0080  /* WSEQ_START */
+#define WM8962_WSEQ_START_MASK                  0x0080  /* WSEQ_START */
+#define WM8962_WSEQ_START_SHIFT                      7  /* WSEQ_START */
+#define WM8962_WSEQ_START_WIDTH                      1  /* WSEQ_START */
+#define WM8962_WSEQ_START_INDEX_MASK            0x007F  /* WSEQ_START_INDEX - [6:0] */
+#define WM8962_WSEQ_START_INDEX_SHIFT                0  /* WSEQ_START_INDEX - [6:0] */
+#define WM8962_WSEQ_START_INDEX_WIDTH                7  /* WSEQ_START_INDEX - [6:0] */
+
+/*
+ * R93 (0x5D) - Write Sequencer Control 3
+ */
+#define WM8962_WSEQ_CURRENT_INDEX_MASK          0x03F8  /* WSEQ_CURRENT_INDEX - [9:3] */
+#define WM8962_WSEQ_CURRENT_INDEX_SHIFT              3  /* WSEQ_CURRENT_INDEX - [9:3] */
+#define WM8962_WSEQ_CURRENT_INDEX_WIDTH              7  /* WSEQ_CURRENT_INDEX - [9:3] */
+#define WM8962_WSEQ_BUSY                        0x0001  /* WSEQ_BUSY */
+#define WM8962_WSEQ_BUSY_MASK                   0x0001  /* WSEQ_BUSY */
+#define WM8962_WSEQ_BUSY_SHIFT                       0  /* WSEQ_BUSY */
+#define WM8962_WSEQ_BUSY_WIDTH                       1  /* WSEQ_BUSY */
+
+/*
+ * R94 (0x5E) - Control Interface
+ */
+#define WM8962_SPI_CONTRD                       0x0040  /* SPI_CONTRD */
+#define WM8962_SPI_CONTRD_MASK                  0x0040  /* SPI_CONTRD */
+#define WM8962_SPI_CONTRD_SHIFT                      6  /* SPI_CONTRD */
+#define WM8962_SPI_CONTRD_WIDTH                      1  /* SPI_CONTRD */
+#define WM8962_SPI_4WIRE                        0x0020  /* SPI_4WIRE */
+#define WM8962_SPI_4WIRE_MASK                   0x0020  /* SPI_4WIRE */
+#define WM8962_SPI_4WIRE_SHIFT                       5  /* SPI_4WIRE */
+#define WM8962_SPI_4WIRE_WIDTH                       1  /* SPI_4WIRE */
+#define WM8962_SPI_CFG                          0x0010  /* SPI_CFG */
+#define WM8962_SPI_CFG_MASK                     0x0010  /* SPI_CFG */
+#define WM8962_SPI_CFG_SHIFT                         4  /* SPI_CFG */
+#define WM8962_SPI_CFG_WIDTH                         1  /* SPI_CFG */
+
+/*
+ * R99 (0x63) - Mixer Enables
+ */
+#define WM8962_HPMIXL_ENA                       0x0008  /* HPMIXL_ENA */
+#define WM8962_HPMIXL_ENA_MASK                  0x0008  /* HPMIXL_ENA */
+#define WM8962_HPMIXL_ENA_SHIFT                      3  /* HPMIXL_ENA */
+#define WM8962_HPMIXL_ENA_WIDTH                      1  /* HPMIXL_ENA */
+#define WM8962_HPMIXR_ENA                       0x0004  /* HPMIXR_ENA */
+#define WM8962_HPMIXR_ENA_MASK                  0x0004  /* HPMIXR_ENA */
+#define WM8962_HPMIXR_ENA_SHIFT                      2  /* HPMIXR_ENA */
+#define WM8962_HPMIXR_ENA_WIDTH                      1  /* HPMIXR_ENA */
+#define WM8962_SPKMIXL_ENA                      0x0002  /* SPKMIXL_ENA */
+#define WM8962_SPKMIXL_ENA_MASK                 0x0002  /* SPKMIXL_ENA */
+#define WM8962_SPKMIXL_ENA_SHIFT                     1  /* SPKMIXL_ENA */
+#define WM8962_SPKMIXL_ENA_WIDTH                     1  /* SPKMIXL_ENA */
+#define WM8962_SPKMIXR_ENA                      0x0001  /* SPKMIXR_ENA */
+#define WM8962_SPKMIXR_ENA_MASK                 0x0001  /* SPKMIXR_ENA */
+#define WM8962_SPKMIXR_ENA_SHIFT                     0  /* SPKMIXR_ENA */
+#define WM8962_SPKMIXR_ENA_WIDTH                     1  /* SPKMIXR_ENA */
+
+/*
+ * R100 (0x64) - Headphone Mixer (1)
+ */
+#define WM8962_HPMIXL_TO_HPOUTL_PGA             0x0080  /* HPMIXL_TO_HPOUTL_PGA */
+#define WM8962_HPMIXL_TO_HPOUTL_PGA_MASK        0x0080  /* HPMIXL_TO_HPOUTL_PGA */
+#define WM8962_HPMIXL_TO_HPOUTL_PGA_SHIFT            7  /* HPMIXL_TO_HPOUTL_PGA */
+#define WM8962_HPMIXL_TO_HPOUTL_PGA_WIDTH            1  /* HPMIXL_TO_HPOUTL_PGA */
+#define WM8962_DACL_TO_HPMIXL                   0x0020  /* DACL_TO_HPMIXL */
+#define WM8962_DACL_TO_HPMIXL_MASK              0x0020  /* DACL_TO_HPMIXL */
+#define WM8962_DACL_TO_HPMIXL_SHIFT                  5  /* DACL_TO_HPMIXL */
+#define WM8962_DACL_TO_HPMIXL_WIDTH                  1  /* DACL_TO_HPMIXL */
+#define WM8962_DACR_TO_HPMIXL                   0x0010  /* DACR_TO_HPMIXL */
+#define WM8962_DACR_TO_HPMIXL_MASK              0x0010  /* DACR_TO_HPMIXL */
+#define WM8962_DACR_TO_HPMIXL_SHIFT                  4  /* DACR_TO_HPMIXL */
+#define WM8962_DACR_TO_HPMIXL_WIDTH                  1  /* DACR_TO_HPMIXL */
+#define WM8962_MIXINL_TO_HPMIXL                 0x0008  /* MIXINL_TO_HPMIXL */
+#define WM8962_MIXINL_TO_HPMIXL_MASK            0x0008  /* MIXINL_TO_HPMIXL */
+#define WM8962_MIXINL_TO_HPMIXL_SHIFT                3  /* MIXINL_TO_HPMIXL */
+#define WM8962_MIXINL_TO_HPMIXL_WIDTH                1  /* MIXINL_TO_HPMIXL */
+#define WM8962_MIXINR_TO_HPMIXL                 0x0004  /* MIXINR_TO_HPMIXL */
+#define WM8962_MIXINR_TO_HPMIXL_MASK            0x0004  /* MIXINR_TO_HPMIXL */
+#define WM8962_MIXINR_TO_HPMIXL_SHIFT                2  /* MIXINR_TO_HPMIXL */
+#define WM8962_MIXINR_TO_HPMIXL_WIDTH                1  /* MIXINR_TO_HPMIXL */
+#define WM8962_IN4L_TO_HPMIXL                   0x0002  /* IN4L_TO_HPMIXL */
+#define WM8962_IN4L_TO_HPMIXL_MASK              0x0002  /* IN4L_TO_HPMIXL */
+#define WM8962_IN4L_TO_HPMIXL_SHIFT                  1  /* IN4L_TO_HPMIXL */
+#define WM8962_IN4L_TO_HPMIXL_WIDTH                  1  /* IN4L_TO_HPMIXL */
+#define WM8962_IN4R_TO_HPMIXL                   0x0001  /* IN4R_TO_HPMIXL */
+#define WM8962_IN4R_TO_HPMIXL_MASK              0x0001  /* IN4R_TO_HPMIXL */
+#define WM8962_IN4R_TO_HPMIXL_SHIFT                  0  /* IN4R_TO_HPMIXL */
+#define WM8962_IN4R_TO_HPMIXL_WIDTH                  1  /* IN4R_TO_HPMIXL */
+
+/*
+ * R101 (0x65) - Headphone Mixer (2)
+ */
+#define WM8962_HPMIXR_TO_HPOUTR_PGA             0x0080  /* HPMIXR_TO_HPOUTR_PGA */
+#define WM8962_HPMIXR_TO_HPOUTR_PGA_MASK        0x0080  /* HPMIXR_TO_HPOUTR_PGA */
+#define WM8962_HPMIXR_TO_HPOUTR_PGA_SHIFT            7  /* HPMIXR_TO_HPOUTR_PGA */
+#define WM8962_HPMIXR_TO_HPOUTR_PGA_WIDTH            1  /* HPMIXR_TO_HPOUTR_PGA */
+#define WM8962_DACL_TO_HPMIXR                   0x0020  /* DACL_TO_HPMIXR */
+#define WM8962_DACL_TO_HPMIXR_MASK              0x0020  /* DACL_TO_HPMIXR */
+#define WM8962_DACL_TO_HPMIXR_SHIFT                  5  /* DACL_TO_HPMIXR */
+#define WM8962_DACL_TO_HPMIXR_WIDTH                  1  /* DACL_TO_HPMIXR */
+#define WM8962_DACR_TO_HPMIXR                   0x0010  /* DACR_TO_HPMIXR */
+#define WM8962_DACR_TO_HPMIXR_MASK              0x0010  /* DACR_TO_HPMIXR */
+#define WM8962_DACR_TO_HPMIXR_SHIFT                  4  /* DACR_TO_HPMIXR */
+#define WM8962_DACR_TO_HPMIXR_WIDTH                  1  /* DACR_TO_HPMIXR */
+#define WM8962_MIXINL_TO_HPMIXR                 0x0008  /* MIXINL_TO_HPMIXR */
+#define WM8962_MIXINL_TO_HPMIXR_MASK            0x0008  /* MIXINL_TO_HPMIXR */
+#define WM8962_MIXINL_TO_HPMIXR_SHIFT                3  /* MIXINL_TO_HPMIXR */
+#define WM8962_MIXINL_TO_HPMIXR_WIDTH                1  /* MIXINL_TO_HPMIXR */
+#define WM8962_MIXINR_TO_HPMIXR                 0x0004  /* MIXINR_TO_HPMIXR */
+#define WM8962_MIXINR_TO_HPMIXR_MASK            0x0004  /* MIXINR_TO_HPMIXR */
+#define WM8962_MIXINR_TO_HPMIXR_SHIFT                2  /* MIXINR_TO_HPMIXR */
+#define WM8962_MIXINR_TO_HPMIXR_WIDTH                1  /* MIXINR_TO_HPMIXR */
+#define WM8962_IN4L_TO_HPMIXR                   0x0002  /* IN4L_TO_HPMIXR */
+#define WM8962_IN4L_TO_HPMIXR_MASK              0x0002  /* IN4L_TO_HPMIXR */
+#define WM8962_IN4L_TO_HPMIXR_SHIFT                  1  /* IN4L_TO_HPMIXR */
+#define WM8962_IN4L_TO_HPMIXR_WIDTH                  1  /* IN4L_TO_HPMIXR */
+#define WM8962_IN4R_TO_HPMIXR                   0x0001  /* IN4R_TO_HPMIXR */
+#define WM8962_IN4R_TO_HPMIXR_MASK              0x0001  /* IN4R_TO_HPMIXR */
+#define WM8962_IN4R_TO_HPMIXR_SHIFT                  0  /* IN4R_TO_HPMIXR */
+#define WM8962_IN4R_TO_HPMIXR_WIDTH                  1  /* IN4R_TO_HPMIXR */
+
+/*
+ * R102 (0x66) - Headphone Mixer (3)
+ */
+#define WM8962_HPMIXL_MUTE                      0x0100  /* HPMIXL_MUTE */
+#define WM8962_HPMIXL_MUTE_MASK                 0x0100  /* HPMIXL_MUTE */
+#define WM8962_HPMIXL_MUTE_SHIFT                     8  /* HPMIXL_MUTE */
+#define WM8962_HPMIXL_MUTE_WIDTH                     1  /* HPMIXL_MUTE */
+#define WM8962_MIXINL_HPMIXL_VOL                0x0080  /* MIXINL_HPMIXL_VOL */
+#define WM8962_MIXINL_HPMIXL_VOL_MASK           0x0080  /* MIXINL_HPMIXL_VOL */
+#define WM8962_MIXINL_HPMIXL_VOL_SHIFT               7  /* MIXINL_HPMIXL_VOL */
+#define WM8962_MIXINL_HPMIXL_VOL_WIDTH               1  /* MIXINL_HPMIXL_VOL */
+#define WM8962_MIXINR_HPMIXL_VOL                0x0040  /* MIXINR_HPMIXL_VOL */
+#define WM8962_MIXINR_HPMIXL_VOL_MASK           0x0040  /* MIXINR_HPMIXL_VOL */
+#define WM8962_MIXINR_HPMIXL_VOL_SHIFT               6  /* MIXINR_HPMIXL_VOL */
+#define WM8962_MIXINR_HPMIXL_VOL_WIDTH               1  /* MIXINR_HPMIXL_VOL */
+#define WM8962_IN4L_HPMIXL_VOL_MASK             0x0038  /* IN4L_HPMIXL_VOL - [5:3] */
+#define WM8962_IN4L_HPMIXL_VOL_SHIFT                 3  /* IN4L_HPMIXL_VOL - [5:3] */
+#define WM8962_IN4L_HPMIXL_VOL_WIDTH                 3  /* IN4L_HPMIXL_VOL - [5:3] */
+#define WM8962_IN4R_HPMIXL_VOL_MASK             0x0007  /* IN4R_HPMIXL_VOL - [2:0] */
+#define WM8962_IN4R_HPMIXL_VOL_SHIFT                 0  /* IN4R_HPMIXL_VOL - [2:0] */
+#define WM8962_IN4R_HPMIXL_VOL_WIDTH                 3  /* IN4R_HPMIXL_VOL - [2:0] */
+
+/*
+ * R103 (0x67) - Headphone Mixer (4)
+ */
+#define WM8962_HPMIXR_MUTE                      0x0100  /* HPMIXR_MUTE */
+#define WM8962_HPMIXR_MUTE_MASK                 0x0100  /* HPMIXR_MUTE */
+#define WM8962_HPMIXR_MUTE_SHIFT                     8  /* HPMIXR_MUTE */
+#define WM8962_HPMIXR_MUTE_WIDTH                     1  /* HPMIXR_MUTE */
+#define WM8962_MIXINL_HPMIXR_VOL                0x0080  /* MIXINL_HPMIXR_VOL */
+#define WM8962_MIXINL_HPMIXR_VOL_MASK           0x0080  /* MIXINL_HPMIXR_VOL */
+#define WM8962_MIXINL_HPMIXR_VOL_SHIFT               7  /* MIXINL_HPMIXR_VOL */
+#define WM8962_MIXINL_HPMIXR_VOL_WIDTH               1  /* MIXINL_HPMIXR_VOL */
+#define WM8962_MIXINR_HPMIXR_VOL                0x0040  /* MIXINR_HPMIXR_VOL */
+#define WM8962_MIXINR_HPMIXR_VOL_MASK           0x0040  /* MIXINR_HPMIXR_VOL */
+#define WM8962_MIXINR_HPMIXR_VOL_SHIFT               6  /* MIXINR_HPMIXR_VOL */
+#define WM8962_MIXINR_HPMIXR_VOL_WIDTH               1  /* MIXINR_HPMIXR_VOL */
+#define WM8962_IN4L_HPMIXR_VOL_MASK             0x0038  /* IN4L_HPMIXR_VOL - [5:3] */
+#define WM8962_IN4L_HPMIXR_VOL_SHIFT                 3  /* IN4L_HPMIXR_VOL - [5:3] */
+#define WM8962_IN4L_HPMIXR_VOL_WIDTH                 3  /* IN4L_HPMIXR_VOL - [5:3] */
+#define WM8962_IN4R_HPMIXR_VOL_MASK             0x0007  /* IN4R_HPMIXR_VOL - [2:0] */
+#define WM8962_IN4R_HPMIXR_VOL_SHIFT                 0  /* IN4R_HPMIXR_VOL - [2:0] */
+#define WM8962_IN4R_HPMIXR_VOL_WIDTH                 3  /* IN4R_HPMIXR_VOL - [2:0] */
+
+/*
+ * R105 (0x69) - Speaker Mixer (1)
+ */
+#define WM8962_SPKMIXL_TO_SPKOUTL_PGA           0x0080  /* SPKMIXL_TO_SPKOUTL_PGA */
+#define WM8962_SPKMIXL_TO_SPKOUTL_PGA_MASK      0x0080  /* SPKMIXL_TO_SPKOUTL_PGA */
+#define WM8962_SPKMIXL_TO_SPKOUTL_PGA_SHIFT          7  /* SPKMIXL_TO_SPKOUTL_PGA */
+#define WM8962_SPKMIXL_TO_SPKOUTL_PGA_WIDTH          1  /* SPKMIXL_TO_SPKOUTL_PGA */
+#define WM8962_DACL_TO_SPKMIXL                  0x0020  /* DACL_TO_SPKMIXL */
+#define WM8962_DACL_TO_SPKMIXL_MASK             0x0020  /* DACL_TO_SPKMIXL */
+#define WM8962_DACL_TO_SPKMIXL_SHIFT                 5  /* DACL_TO_SPKMIXL */
+#define WM8962_DACL_TO_SPKMIXL_WIDTH                 1  /* DACL_TO_SPKMIXL */
+#define WM8962_DACR_TO_SPKMIXL                  0x0010  /* DACR_TO_SPKMIXL */
+#define WM8962_DACR_TO_SPKMIXL_MASK             0x0010  /* DACR_TO_SPKMIXL */
+#define WM8962_DACR_TO_SPKMIXL_SHIFT                 4  /* DACR_TO_SPKMIXL */
+#define WM8962_DACR_TO_SPKMIXL_WIDTH                 1  /* DACR_TO_SPKMIXL */
+#define WM8962_MIXINL_TO_SPKMIXL                0x0008  /* MIXINL_TO_SPKMIXL */
+#define WM8962_MIXINL_TO_SPKMIXL_MASK           0x0008  /* MIXINL_TO_SPKMIXL */
+#define WM8962_MIXINL_TO_SPKMIXL_SHIFT               3  /* MIXINL_TO_SPKMIXL */
+#define WM8962_MIXINL_TO_SPKMIXL_WIDTH               1  /* MIXINL_TO_SPKMIXL */
+#define WM8962_MIXINR_TO_SPKMIXL                0x0004  /* MIXINR_TO_SPKMIXL */
+#define WM8962_MIXINR_TO_SPKMIXL_MASK           0x0004  /* MIXINR_TO_SPKMIXL */
+#define WM8962_MIXINR_TO_SPKMIXL_SHIFT               2  /* MIXINR_TO_SPKMIXL */
+#define WM8962_MIXINR_TO_SPKMIXL_WIDTH               1  /* MIXINR_TO_SPKMIXL */
+#define WM8962_IN4L_TO_SPKMIXL                  0x0002  /* IN4L_TO_SPKMIXL */
+#define WM8962_IN4L_TO_SPKMIXL_MASK             0x0002  /* IN4L_TO_SPKMIXL */
+#define WM8962_IN4L_TO_SPKMIXL_SHIFT                 1  /* IN4L_TO_SPKMIXL */
+#define WM8962_IN4L_TO_SPKMIXL_WIDTH                 1  /* IN4L_TO_SPKMIXL */
+#define WM8962_IN4R_TO_SPKMIXL                  0x0001  /* IN4R_TO_SPKMIXL */
+#define WM8962_IN4R_TO_SPKMIXL_MASK             0x0001  /* IN4R_TO_SPKMIXL */
+#define WM8962_IN4R_TO_SPKMIXL_SHIFT                 0  /* IN4R_TO_SPKMIXL */
+#define WM8962_IN4R_TO_SPKMIXL_WIDTH                 1  /* IN4R_TO_SPKMIXL */
+
+/*
+ * R106 (0x6A) - Speaker Mixer (2)
+ */
+#define WM8962_SPKMIXR_TO_SPKOUTR_PGA           0x0080  /* SPKMIXR_TO_SPKOUTR_PGA */
+#define WM8962_SPKMIXR_TO_SPKOUTR_PGA_MASK      0x0080  /* SPKMIXR_TO_SPKOUTR_PGA */
+#define WM8962_SPKMIXR_TO_SPKOUTR_PGA_SHIFT          7  /* SPKMIXR_TO_SPKOUTR_PGA */
+#define WM8962_SPKMIXR_TO_SPKOUTR_PGA_WIDTH          1  /* SPKMIXR_TO_SPKOUTR_PGA */
+#define WM8962_DACL_TO_SPKMIXR                  0x0020  /* DACL_TO_SPKMIXR */
+#define WM8962_DACL_TO_SPKMIXR_MASK             0x0020  /* DACL_TO_SPKMIXR */
+#define WM8962_DACL_TO_SPKMIXR_SHIFT                 5  /* DACL_TO_SPKMIXR */
+#define WM8962_DACL_TO_SPKMIXR_WIDTH                 1  /* DACL_TO_SPKMIXR */
+#define WM8962_DACR_TO_SPKMIXR                  0x0010  /* DACR_TO_SPKMIXR */
+#define WM8962_DACR_TO_SPKMIXR_MASK             0x0010  /* DACR_TO_SPKMIXR */
+#define WM8962_DACR_TO_SPKMIXR_SHIFT                 4  /* DACR_TO_SPKMIXR */
+#define WM8962_DACR_TO_SPKMIXR_WIDTH                 1  /* DACR_TO_SPKMIXR */
+#define WM8962_MIXINL_TO_SPKMIXR                0x0008  /* MIXINL_TO_SPKMIXR */
+#define WM8962_MIXINL_TO_SPKMIXR_MASK           0x0008  /* MIXINL_TO_SPKMIXR */
+#define WM8962_MIXINL_TO_SPKMIXR_SHIFT               3  /* MIXINL_TO_SPKMIXR */
+#define WM8962_MIXINL_TO_SPKMIXR_WIDTH               1  /* MIXINL_TO_SPKMIXR */
+#define WM8962_MIXINR_TO_SPKMIXR                0x0004  /* MIXINR_TO_SPKMIXR */
+#define WM8962_MIXINR_TO_SPKMIXR_MASK           0x0004  /* MIXINR_TO_SPKMIXR */
+#define WM8962_MIXINR_TO_SPKMIXR_SHIFT               2  /* MIXINR_TO_SPKMIXR */
+#define WM8962_MIXINR_TO_SPKMIXR_WIDTH               1  /* MIXINR_TO_SPKMIXR */
+#define WM8962_IN4L_TO_SPKMIXR                  0x0002  /* IN4L_TO_SPKMIXR */
+#define WM8962_IN4L_TO_SPKMIXR_MASK             0x0002  /* IN4L_TO_SPKMIXR */
+#define WM8962_IN4L_TO_SPKMIXR_SHIFT                 1  /* IN4L_TO_SPKMIXR */
+#define WM8962_IN4L_TO_SPKMIXR_WIDTH                 1  /* IN4L_TO_SPKMIXR */
+#define WM8962_IN4R_TO_SPKMIXR                  0x0001  /* IN4R_TO_SPKMIXR */
+#define WM8962_IN4R_TO_SPKMIXR_MASK             0x0001  /* IN4R_TO_SPKMIXR */
+#define WM8962_IN4R_TO_SPKMIXR_SHIFT                 0  /* IN4R_TO_SPKMIXR */
+#define WM8962_IN4R_TO_SPKMIXR_WIDTH                 1  /* IN4R_TO_SPKMIXR */
+
+/*
+ * R107 (0x6B) - Speaker Mixer (3)
+ */
+#define WM8962_SPKMIXL_MUTE                     0x0100  /* SPKMIXL_MUTE */
+#define WM8962_SPKMIXL_MUTE_MASK                0x0100  /* SPKMIXL_MUTE */
+#define WM8962_SPKMIXL_MUTE_SHIFT                    8  /* SPKMIXL_MUTE */
+#define WM8962_SPKMIXL_MUTE_WIDTH                    1  /* SPKMIXL_MUTE */
+#define WM8962_MIXINL_SPKMIXL_VOL               0x0080  /* MIXINL_SPKMIXL_VOL */
+#define WM8962_MIXINL_SPKMIXL_VOL_MASK          0x0080  /* MIXINL_SPKMIXL_VOL */
+#define WM8962_MIXINL_SPKMIXL_VOL_SHIFT              7  /* MIXINL_SPKMIXL_VOL */
+#define WM8962_MIXINL_SPKMIXL_VOL_WIDTH              1  /* MIXINL_SPKMIXL_VOL */
+#define WM8962_MIXINR_SPKMIXL_VOL               0x0040  /* MIXINR_SPKMIXL_VOL */
+#define WM8962_MIXINR_SPKMIXL_VOL_MASK          0x0040  /* MIXINR_SPKMIXL_VOL */
+#define WM8962_MIXINR_SPKMIXL_VOL_SHIFT              6  /* MIXINR_SPKMIXL_VOL */
+#define WM8962_MIXINR_SPKMIXL_VOL_WIDTH              1  /* MIXINR_SPKMIXL_VOL */
+#define WM8962_IN4L_SPKMIXL_VOL_MASK            0x0038  /* IN4L_SPKMIXL_VOL - [5:3] */
+#define WM8962_IN4L_SPKMIXL_VOL_SHIFT                3  /* IN4L_SPKMIXL_VOL - [5:3] */
+#define WM8962_IN4L_SPKMIXL_VOL_WIDTH                3  /* IN4L_SPKMIXL_VOL - [5:3] */
+#define WM8962_IN4R_SPKMIXL_VOL_MASK            0x0007  /* IN4R_SPKMIXL_VOL - [2:0] */
+#define WM8962_IN4R_SPKMIXL_VOL_SHIFT                0  /* IN4R_SPKMIXL_VOL - [2:0] */
+#define WM8962_IN4R_SPKMIXL_VOL_WIDTH                3  /* IN4R_SPKMIXL_VOL - [2:0] */
+
+/*
+ * R108 (0x6C) - Speaker Mixer (4)
+ */
+#define WM8962_SPKMIXR_MUTE                     0x0100  /* SPKMIXR_MUTE */
+#define WM8962_SPKMIXR_MUTE_MASK                0x0100  /* SPKMIXR_MUTE */
+#define WM8962_SPKMIXR_MUTE_SHIFT                    8  /* SPKMIXR_MUTE */
+#define WM8962_SPKMIXR_MUTE_WIDTH                    1  /* SPKMIXR_MUTE */
+#define WM8962_MIXINL_SPKMIXR_VOL               0x0080  /* MIXINL_SPKMIXR_VOL */
+#define WM8962_MIXINL_SPKMIXR_VOL_MASK          0x0080  /* MIXINL_SPKMIXR_VOL */
+#define WM8962_MIXINL_SPKMIXR_VOL_SHIFT              7  /* MIXINL_SPKMIXR_VOL */
+#define WM8962_MIXINL_SPKMIXR_VOL_WIDTH              1  /* MIXINL_SPKMIXR_VOL */
+#define WM8962_MIXINR_SPKMIXR_VOL               0x0040  /* MIXINR_SPKMIXR_VOL */
+#define WM8962_MIXINR_SPKMIXR_VOL_MASK          0x0040  /* MIXINR_SPKMIXR_VOL */
+#define WM8962_MIXINR_SPKMIXR_VOL_SHIFT              6  /* MIXINR_SPKMIXR_VOL */
+#define WM8962_MIXINR_SPKMIXR_VOL_WIDTH              1  /* MIXINR_SPKMIXR_VOL */
+#define WM8962_IN4L_SPKMIXR_VOL_MASK            0x0038  /* IN4L_SPKMIXR_VOL - [5:3] */
+#define WM8962_IN4L_SPKMIXR_VOL_SHIFT                3  /* IN4L_SPKMIXR_VOL - [5:3] */
+#define WM8962_IN4L_SPKMIXR_VOL_WIDTH                3  /* IN4L_SPKMIXR_VOL - [5:3] */
+#define WM8962_IN4R_SPKMIXR_VOL_MASK            0x0007  /* IN4R_SPKMIXR_VOL - [2:0] */
+#define WM8962_IN4R_SPKMIXR_VOL_SHIFT                0  /* IN4R_SPKMIXR_VOL - [2:0] */
+#define WM8962_IN4R_SPKMIXR_VOL_WIDTH                3  /* IN4R_SPKMIXR_VOL - [2:0] */
+
+/*
+ * R109 (0x6D) - Speaker Mixer (5)
+ */
+#define WM8962_DACL_SPKMIXL_VOL                 0x0080  /* DACL_SPKMIXL_VOL */
+#define WM8962_DACL_SPKMIXL_VOL_MASK            0x0080  /* DACL_SPKMIXL_VOL */
+#define WM8962_DACL_SPKMIXL_VOL_SHIFT                7  /* DACL_SPKMIXL_VOL */
+#define WM8962_DACL_SPKMIXL_VOL_WIDTH                1  /* DACL_SPKMIXL_VOL */
+#define WM8962_DACR_SPKMIXL_VOL                 0x0040  /* DACR_SPKMIXL_VOL */
+#define WM8962_DACR_SPKMIXL_VOL_MASK            0x0040  /* DACR_SPKMIXL_VOL */
+#define WM8962_DACR_SPKMIXL_VOL_SHIFT                6  /* DACR_SPKMIXL_VOL */
+#define WM8962_DACR_SPKMIXL_VOL_WIDTH                1  /* DACR_SPKMIXL_VOL */
+#define WM8962_DACL_SPKMIXR_VOL                 0x0020  /* DACL_SPKMIXR_VOL */
+#define WM8962_DACL_SPKMIXR_VOL_MASK            0x0020  /* DACL_SPKMIXR_VOL */
+#define WM8962_DACL_SPKMIXR_VOL_SHIFT                5  /* DACL_SPKMIXR_VOL */
+#define WM8962_DACL_SPKMIXR_VOL_WIDTH                1  /* DACL_SPKMIXR_VOL */
+#define WM8962_DACR_SPKMIXR_VOL                 0x0010  /* DACR_SPKMIXR_VOL */
+#define WM8962_DACR_SPKMIXR_VOL_MASK            0x0010  /* DACR_SPKMIXR_VOL */
+#define WM8962_DACR_SPKMIXR_VOL_SHIFT                4  /* DACR_SPKMIXR_VOL */
+#define WM8962_DACR_SPKMIXR_VOL_WIDTH                1  /* DACR_SPKMIXR_VOL */
+
+/*
+ * R110 (0x6E) - Beep Generator (1)
+ */
+#define WM8962_BEEP_GAIN_MASK                   0x00F0  /* BEEP_GAIN - [7:4] */
+#define WM8962_BEEP_GAIN_SHIFT                       4  /* BEEP_GAIN - [7:4] */
+#define WM8962_BEEP_GAIN_WIDTH                       4  /* BEEP_GAIN - [7:4] */
+#define WM8962_BEEP_RATE_MASK                   0x0006  /* BEEP_RATE - [2:1] */
+#define WM8962_BEEP_RATE_SHIFT                       1  /* BEEP_RATE - [2:1] */
+#define WM8962_BEEP_RATE_WIDTH                       2  /* BEEP_RATE - [2:1] */
+#define WM8962_BEEP_ENA                         0x0001  /* BEEP_ENA */
+#define WM8962_BEEP_ENA_MASK                    0x0001  /* BEEP_ENA */
+#define WM8962_BEEP_ENA_SHIFT                        0  /* BEEP_ENA */
+#define WM8962_BEEP_ENA_WIDTH                        1  /* BEEP_ENA */
+
+/*
+ * R115 (0x73) - Oscillator Trim (3)
+ */
+#define WM8962_OSC_TRIM_XTI_MASK                0x001F  /* OSC_TRIM_XTI - [4:0] */
+#define WM8962_OSC_TRIM_XTI_SHIFT                    0  /* OSC_TRIM_XTI - [4:0] */
+#define WM8962_OSC_TRIM_XTI_WIDTH                    5  /* OSC_TRIM_XTI - [4:0] */
+
+/*
+ * R116 (0x74) - Oscillator Trim (4)
+ */
+#define WM8962_OSC_TRIM_XTO_MASK                0x001F  /* OSC_TRIM_XTO - [4:0] */
+#define WM8962_OSC_TRIM_XTO_SHIFT                    0  /* OSC_TRIM_XTO - [4:0] */
+#define WM8962_OSC_TRIM_XTO_WIDTH                    5  /* OSC_TRIM_XTO - [4:0] */
+
+/*
+ * R119 (0x77) - Oscillator Trim (7)
+ */
+#define WM8962_XTO_CAP_SEL_MASK                 0x00F0  /* XTO_CAP_SEL - [7:4] */
+#define WM8962_XTO_CAP_SEL_SHIFT                     4  /* XTO_CAP_SEL - [7:4] */
+#define WM8962_XTO_CAP_SEL_WIDTH                     4  /* XTO_CAP_SEL - [7:4] */
+#define WM8962_XTI_CAP_SEL_MASK                 0x000F  /* XTI_CAP_SEL - [3:0] */
+#define WM8962_XTI_CAP_SEL_SHIFT                     0  /* XTI_CAP_SEL - [3:0] */
+#define WM8962_XTI_CAP_SEL_WIDTH                     4  /* XTI_CAP_SEL - [3:0] */
+
+/*
+ * R124 (0x7C) - Analogue Clocking1
+ */
+#define WM8962_CLKOUT2_SEL_MASK                 0x0060  /* CLKOUT2_SEL - [6:5] */
+#define WM8962_CLKOUT2_SEL_SHIFT                     5  /* CLKOUT2_SEL - [6:5] */
+#define WM8962_CLKOUT2_SEL_WIDTH                     2  /* CLKOUT2_SEL - [6:5] */
+#define WM8962_CLKOUT3_SEL_MASK                 0x0018  /* CLKOUT3_SEL - [4:3] */
+#define WM8962_CLKOUT3_SEL_SHIFT                     3  /* CLKOUT3_SEL - [4:3] */
+#define WM8962_CLKOUT3_SEL_WIDTH                     2  /* CLKOUT3_SEL - [4:3] */
+#define WM8962_CLKOUT5_SEL                      0x0001  /* CLKOUT5_SEL */
+#define WM8962_CLKOUT5_SEL_MASK                 0x0001  /* CLKOUT5_SEL */
+#define WM8962_CLKOUT5_SEL_SHIFT                     0  /* CLKOUT5_SEL */
+#define WM8962_CLKOUT5_SEL_WIDTH                     1  /* CLKOUT5_SEL */
+
+/*
+ * R125 (0x7D) - Analogue Clocking2
+ */
+#define WM8962_PLL2_OUTDIV                      0x0080  /* PLL2_OUTDIV */
+#define WM8962_PLL2_OUTDIV_MASK                 0x0080  /* PLL2_OUTDIV */
+#define WM8962_PLL2_OUTDIV_SHIFT                     7  /* PLL2_OUTDIV */
+#define WM8962_PLL2_OUTDIV_WIDTH                     1  /* PLL2_OUTDIV */
+#define WM8962_PLL3_OUTDIV                      0x0040  /* PLL3_OUTDIV */
+#define WM8962_PLL3_OUTDIV_MASK                 0x0040  /* PLL3_OUTDIV */
+#define WM8962_PLL3_OUTDIV_SHIFT                     6  /* PLL3_OUTDIV */
+#define WM8962_PLL3_OUTDIV_WIDTH                     1  /* PLL3_OUTDIV */
+#define WM8962_PLL_SYSCLK_DIV_MASK              0x0018  /* PLL_SYSCLK_DIV - [4:3] */
+#define WM8962_PLL_SYSCLK_DIV_SHIFT                  3  /* PLL_SYSCLK_DIV - [4:3] */
+#define WM8962_PLL_SYSCLK_DIV_WIDTH                  2  /* PLL_SYSCLK_DIV - [4:3] */
+#define WM8962_CLKOUT3_DIV                      0x0004  /* CLKOUT3_DIV */
+#define WM8962_CLKOUT3_DIV_MASK                 0x0004  /* CLKOUT3_DIV */
+#define WM8962_CLKOUT3_DIV_SHIFT                     2  /* CLKOUT3_DIV */
+#define WM8962_CLKOUT3_DIV_WIDTH                     1  /* CLKOUT3_DIV */
+#define WM8962_CLKOUT2_DIV                      0x0002  /* CLKOUT2_DIV */
+#define WM8962_CLKOUT2_DIV_MASK                 0x0002  /* CLKOUT2_DIV */
+#define WM8962_CLKOUT2_DIV_SHIFT                     1  /* CLKOUT2_DIV */
+#define WM8962_CLKOUT2_DIV_WIDTH                     1  /* CLKOUT2_DIV */
+#define WM8962_CLKOUT5_DIV                      0x0001  /* CLKOUT5_DIV */
+#define WM8962_CLKOUT5_DIV_MASK                 0x0001  /* CLKOUT5_DIV */
+#define WM8962_CLKOUT5_DIV_SHIFT                     0  /* CLKOUT5_DIV */
+#define WM8962_CLKOUT5_DIV_WIDTH                     1  /* CLKOUT5_DIV */
+
+/*
+ * R126 (0x7E) - Analogue Clocking3
+ */
+#define WM8962_CLKOUT2_OE                       0x0008  /* CLKOUT2_OE */
+#define WM8962_CLKOUT2_OE_MASK                  0x0008  /* CLKOUT2_OE */
+#define WM8962_CLKOUT2_OE_SHIFT                      3  /* CLKOUT2_OE */
+#define WM8962_CLKOUT2_OE_WIDTH                      1  /* CLKOUT2_OE */
+#define WM8962_CLKOUT3_OE                       0x0004  /* CLKOUT3_OE */
+#define WM8962_CLKOUT3_OE_MASK                  0x0004  /* CLKOUT3_OE */
+#define WM8962_CLKOUT3_OE_SHIFT                      2  /* CLKOUT3_OE */
+#define WM8962_CLKOUT3_OE_WIDTH                      1  /* CLKOUT3_OE */
+#define WM8962_CLKOUT5_OE                       0x0001  /* CLKOUT5_OE */
+#define WM8962_CLKOUT5_OE_MASK                  0x0001  /* CLKOUT5_OE */
+#define WM8962_CLKOUT5_OE_SHIFT                      0  /* CLKOUT5_OE */
+#define WM8962_CLKOUT5_OE_WIDTH                      1  /* CLKOUT5_OE */
+
+/*
+ * R127 (0x7F) - PLL Software Reset
+ */
+#define WM8962_SW_RESET_PLL_MASK                0xFFFF  /* SW_RESET_PLL - [15:0] */
+#define WM8962_SW_RESET_PLL_SHIFT                    0  /* SW_RESET_PLL - [15:0] */
+#define WM8962_SW_RESET_PLL_WIDTH                   16  /* SW_RESET_PLL - [15:0] */
+
+/*
+ * R129 (0x81) - PLL2
+ */
+#define WM8962_OSC_ENA                          0x0080  /* OSC_ENA */
+#define WM8962_OSC_ENA_MASK                     0x0080  /* OSC_ENA */
+#define WM8962_OSC_ENA_SHIFT                         7  /* OSC_ENA */
+#define WM8962_OSC_ENA_WIDTH                         1  /* OSC_ENA */
+#define WM8962_PLL2_ENA                         0x0020  /* PLL2_ENA */
+#define WM8962_PLL2_ENA_MASK                    0x0020  /* PLL2_ENA */
+#define WM8962_PLL2_ENA_SHIFT                        5  /* PLL2_ENA */
+#define WM8962_PLL2_ENA_WIDTH                        1  /* PLL2_ENA */
+#define WM8962_PLL3_ENA                         0x0010  /* PLL3_ENA */
+#define WM8962_PLL3_ENA_MASK                    0x0010  /* PLL3_ENA */
+#define WM8962_PLL3_ENA_SHIFT                        4  /* PLL3_ENA */
+#define WM8962_PLL3_ENA_WIDTH                        1  /* PLL3_ENA */
+
+/*
+ * R131 (0x83) - PLL 4
+ */
+#define WM8962_PLL_CLK_SRC                      0x0002  /* PLL_CLK_SRC */
+#define WM8962_PLL_CLK_SRC_MASK                 0x0002  /* PLL_CLK_SRC */
+#define WM8962_PLL_CLK_SRC_SHIFT                     1  /* PLL_CLK_SRC */
+#define WM8962_PLL_CLK_SRC_WIDTH                     1  /* PLL_CLK_SRC */
+#define WM8962_FLL_TO_PLL3                      0x0001  /* FLL_TO_PLL3 */
+#define WM8962_FLL_TO_PLL3_MASK                 0x0001  /* FLL_TO_PLL3 */
+#define WM8962_FLL_TO_PLL3_SHIFT                     0  /* FLL_TO_PLL3 */
+#define WM8962_FLL_TO_PLL3_WIDTH                     1  /* FLL_TO_PLL3 */
+
+/*
+ * R136 (0x88) - PLL 9
+ */
+#define WM8962_PLL2_FRAC                        0x0040  /* PLL2_FRAC */
+#define WM8962_PLL2_FRAC_MASK                   0x0040  /* PLL2_FRAC */
+#define WM8962_PLL2_FRAC_SHIFT                       6  /* PLL2_FRAC */
+#define WM8962_PLL2_FRAC_WIDTH                       1  /* PLL2_FRAC */
+#define WM8962_PLL2_N_MASK                      0x001F  /* PLL2_N - [4:0] */
+#define WM8962_PLL2_N_SHIFT                          0  /* PLL2_N - [4:0] */
+#define WM8962_PLL2_N_WIDTH                          5  /* PLL2_N - [4:0] */
+
+/*
+ * R137 (0x89) - PLL 10
+ */
+#define WM8962_PLL2_K_MASK                      0x00FF  /* PLL2_K - [7:0] */
+#define WM8962_PLL2_K_SHIFT                          0  /* PLL2_K - [7:0] */
+#define WM8962_PLL2_K_WIDTH                          8  /* PLL2_K - [7:0] */
+
+/*
+ * R138 (0x8A) - PLL 11
+ */
+#define WM8962_PLL2_K_MASK                      0x00FF  /* PLL2_K - [7:0] */
+#define WM8962_PLL2_K_SHIFT                          0  /* PLL2_K - [7:0] */
+#define WM8962_PLL2_K_WIDTH                          8  /* PLL2_K - [7:0] */
+
+/*
+ * R139 (0x8B) - PLL 12
+ */
+#define WM8962_PLL2_K_MASK                      0x00FF  /* PLL2_K - [7:0] */
+#define WM8962_PLL2_K_SHIFT                          0  /* PLL2_K - [7:0] */
+#define WM8962_PLL2_K_WIDTH                          8  /* PLL2_K - [7:0] */
+
+/*
+ * R140 (0x8C) - PLL 13
+ */
+#define WM8962_PLL3_FRAC                        0x0040  /* PLL3_FRAC */
+#define WM8962_PLL3_FRAC_MASK                   0x0040  /* PLL3_FRAC */
+#define WM8962_PLL3_FRAC_SHIFT                       6  /* PLL3_FRAC */
+#define WM8962_PLL3_FRAC_WIDTH                       1  /* PLL3_FRAC */
+#define WM8962_PLL3_N_MASK                      0x001F  /* PLL3_N - [4:0] */
+#define WM8962_PLL3_N_SHIFT                          0  /* PLL3_N - [4:0] */
+#define WM8962_PLL3_N_WIDTH                          5  /* PLL3_N - [4:0] */
+
+/*
+ * R141 (0x8D) - PLL 14
+ */
+#define WM8962_PLL3_K_MASK                      0x00FF  /* PLL3_K - [7:0] */
+#define WM8962_PLL3_K_SHIFT                          0  /* PLL3_K - [7:0] */
+#define WM8962_PLL3_K_WIDTH                          8  /* PLL3_K - [7:0] */
+
+/*
+ * R142 (0x8E) - PLL 15
+ */
+#define WM8962_PLL3_K_MASK                      0x00FF  /* PLL3_K - [7:0] */
+#define WM8962_PLL3_K_SHIFT                          0  /* PLL3_K - [7:0] */
+#define WM8962_PLL3_K_WIDTH                          8  /* PLL3_K - [7:0] */
+
+/*
+ * R143 (0x8F) - PLL 16
+ */
+#define WM8962_PLL3_K_MASK                      0x00FF  /* PLL3_K - [7:0] */
+#define WM8962_PLL3_K_SHIFT                          0  /* PLL3_K - [7:0] */
+#define WM8962_PLL3_K_WIDTH                          8  /* PLL3_K - [7:0] */
+
+/*
+ * R155 (0x9B) - FLL Control (1)
+ */
+#define WM8962_FLL_REFCLK_SRC_MASK              0x0060  /* FLL_REFCLK_SRC - [6:5] */
+#define WM8962_FLL_REFCLK_SRC_SHIFT                  5  /* FLL_REFCLK_SRC - [6:5] */
+#define WM8962_FLL_REFCLK_SRC_WIDTH                  2  /* FLL_REFCLK_SRC - [6:5] */
+#define WM8962_FLL_FRAC                         0x0004  /* FLL_FRAC */
+#define WM8962_FLL_FRAC_MASK                    0x0004  /* FLL_FRAC */
+#define WM8962_FLL_FRAC_SHIFT                        2  /* FLL_FRAC */
+#define WM8962_FLL_FRAC_WIDTH                        1  /* FLL_FRAC */
+#define WM8962_FLL_OSC_ENA                      0x0002  /* FLL_OSC_ENA */
+#define WM8962_FLL_OSC_ENA_MASK                 0x0002  /* FLL_OSC_ENA */
+#define WM8962_FLL_OSC_ENA_SHIFT                     1  /* FLL_OSC_ENA */
+#define WM8962_FLL_OSC_ENA_WIDTH                     1  /* FLL_OSC_ENA */
+#define WM8962_FLL_ENA                          0x0001  /* FLL_ENA */
+#define WM8962_FLL_ENA_MASK                     0x0001  /* FLL_ENA */
+#define WM8962_FLL_ENA_SHIFT                         0  /* FLL_ENA */
+#define WM8962_FLL_ENA_WIDTH                         1  /* FLL_ENA */
+
+/*
+ * R156 (0x9C) - FLL Control (2)
+ */
+#define WM8962_FLL_OUTDIV_MASK                  0x01F8  /* FLL_OUTDIV - [8:3] */
+#define WM8962_FLL_OUTDIV_SHIFT                      3  /* FLL_OUTDIV - [8:3] */
+#define WM8962_FLL_OUTDIV_WIDTH                      6  /* FLL_OUTDIV - [8:3] */
+#define WM8962_FLL_REFCLK_DIV_MASK              0x0003  /* FLL_REFCLK_DIV - [1:0] */
+#define WM8962_FLL_REFCLK_DIV_SHIFT                  0  /* FLL_REFCLK_DIV - [1:0] */
+#define WM8962_FLL_REFCLK_DIV_WIDTH                  2  /* FLL_REFCLK_DIV - [1:0] */
+
+/*
+ * R157 (0x9D) - FLL Control (3)
+ */
+#define WM8962_FLL_FRATIO_MASK                  0x0007  /* FLL_FRATIO - [2:0] */
+#define WM8962_FLL_FRATIO_SHIFT                      0  /* FLL_FRATIO - [2:0] */
+#define WM8962_FLL_FRATIO_WIDTH                      3  /* FLL_FRATIO - [2:0] */
+
+/*
+ * R159 (0x9F) - FLL Control (5)
+ */
+#define WM8962_FLL_FRC_NCO_VAL_MASK             0x007E  /* FLL_FRC_NCO_VAL - [6:1] */
+#define WM8962_FLL_FRC_NCO_VAL_SHIFT                 1  /* FLL_FRC_NCO_VAL - [6:1] */
+#define WM8962_FLL_FRC_NCO_VAL_WIDTH                 6  /* FLL_FRC_NCO_VAL - [6:1] */
+#define WM8962_FLL_FRC_NCO                      0x0001  /* FLL_FRC_NCO */
+#define WM8962_FLL_FRC_NCO_MASK                 0x0001  /* FLL_FRC_NCO */
+#define WM8962_FLL_FRC_NCO_SHIFT                     0  /* FLL_FRC_NCO */
+#define WM8962_FLL_FRC_NCO_WIDTH                     1  /* FLL_FRC_NCO */
+
+/*
+ * R160 (0xA0) - FLL Control (6)
+ */
+#define WM8962_FLL_THETA_MASK                   0xFFFF  /* FLL_THETA - [15:0] */
+#define WM8962_FLL_THETA_SHIFT                       0  /* FLL_THETA - [15:0] */
+#define WM8962_FLL_THETA_WIDTH                      16  /* FLL_THETA - [15:0] */
+
+/*
+ * R161 (0xA1) - FLL Control (7)
+ */
+#define WM8962_FLL_LAMBDA_MASK                  0xFFFF  /* FLL_LAMBDA - [15:0] */
+#define WM8962_FLL_LAMBDA_SHIFT                      0  /* FLL_LAMBDA - [15:0] */
+#define WM8962_FLL_LAMBDA_WIDTH                     16  /* FLL_LAMBDA - [15:0] */
+
+/*
+ * R162 (0xA2) - FLL Control (8)
+ */
+#define WM8962_FLL_N_MASK                       0x03FF  /* FLL_N - [9:0] */
+#define WM8962_FLL_N_SHIFT                           0  /* FLL_N - [9:0] */
+#define WM8962_FLL_N_WIDTH                          10  /* FLL_N - [9:0] */
+
+/*
+ * R252 (0xFC) - General test 1
+ */
+#define WM8962_REG_SYNC                         0x0004  /* REG_SYNC */
+#define WM8962_REG_SYNC_MASK                    0x0004  /* REG_SYNC */
+#define WM8962_REG_SYNC_SHIFT                        2  /* REG_SYNC */
+#define WM8962_REG_SYNC_WIDTH                        1  /* REG_SYNC */
+#define WM8962_AUTO_INC                         0x0001  /* AUTO_INC */
+#define WM8962_AUTO_INC_MASK                    0x0001  /* AUTO_INC */
+#define WM8962_AUTO_INC_SHIFT                        0  /* AUTO_INC */
+#define WM8962_AUTO_INC_WIDTH                        1  /* AUTO_INC */
+
+/*
+ * R256 (0x100) - DF1
+ */
+#define WM8962_DRC_DF1_ENA                      0x0008  /* DRC_DF1_ENA */
+#define WM8962_DRC_DF1_ENA_MASK                 0x0008  /* DRC_DF1_ENA */
+#define WM8962_DRC_DF1_ENA_SHIFT                     3  /* DRC_DF1_ENA */
+#define WM8962_DRC_DF1_ENA_WIDTH                     1  /* DRC_DF1_ENA */
+#define WM8962_DF1_SHARED_COEFF                 0x0004  /* DF1_SHARED_COEFF */
+#define WM8962_DF1_SHARED_COEFF_MASK            0x0004  /* DF1_SHARED_COEFF */
+#define WM8962_DF1_SHARED_COEFF_SHIFT                2  /* DF1_SHARED_COEFF */
+#define WM8962_DF1_SHARED_COEFF_WIDTH                1  /* DF1_SHARED_COEFF */
+#define WM8962_DF1_SHARED_COEFF_SEL             0x0002  /* DF1_SHARED_COEFF_SEL */
+#define WM8962_DF1_SHARED_COEFF_SEL_MASK        0x0002  /* DF1_SHARED_COEFF_SEL */
+#define WM8962_DF1_SHARED_COEFF_SEL_SHIFT            1  /* DF1_SHARED_COEFF_SEL */
+#define WM8962_DF1_SHARED_COEFF_SEL_WIDTH            1  /* DF1_SHARED_COEFF_SEL */
+#define WM8962_DF1_ENA                          0x0001  /* DF1_ENA */
+#define WM8962_DF1_ENA_MASK                     0x0001  /* DF1_ENA */
+#define WM8962_DF1_ENA_SHIFT                         0  /* DF1_ENA */
+#define WM8962_DF1_ENA_WIDTH                         1  /* DF1_ENA */
+
+/*
+ * R257 (0x101) - DF2
+ */
+#define WM8962_DF1_COEFF_L0_MASK                0xFFFF  /* DF1_COEFF_L0 - [15:0] */
+#define WM8962_DF1_COEFF_L0_SHIFT                    0  /* DF1_COEFF_L0 - [15:0] */
+#define WM8962_DF1_COEFF_L0_WIDTH                   16  /* DF1_COEFF_L0 - [15:0] */
+
+/*
+ * R258 (0x102) - DF3
+ */
+#define WM8962_DF1_COEFF_L1_MASK                0xFFFF  /* DF1_COEFF_L1 - [15:0] */
+#define WM8962_DF1_COEFF_L1_SHIFT                    0  /* DF1_COEFF_L1 - [15:0] */
+#define WM8962_DF1_COEFF_L1_WIDTH                   16  /* DF1_COEFF_L1 - [15:0] */
+
+/*
+ * R259 (0x103) - DF4
+ */
+#define WM8962_DF1_COEFF_L2_MASK                0xFFFF  /* DF1_COEFF_L2 - [15:0] */
+#define WM8962_DF1_COEFF_L2_SHIFT                    0  /* DF1_COEFF_L2 - [15:0] */
+#define WM8962_DF1_COEFF_L2_WIDTH                   16  /* DF1_COEFF_L2 - [15:0] */
+
+/*
+ * R260 (0x104) - DF5
+ */
+#define WM8962_DF1_COEFF_R0_MASK                0xFFFF  /* DF1_COEFF_R0 - [15:0] */
+#define WM8962_DF1_COEFF_R0_SHIFT                    0  /* DF1_COEFF_R0 - [15:0] */
+#define WM8962_DF1_COEFF_R0_WIDTH                   16  /* DF1_COEFF_R0 - [15:0] */
+
+/*
+ * R261 (0x105) - DF6
+ */
+#define WM8962_DF1_COEFF_R1_MASK                0xFFFF  /* DF1_COEFF_R1 - [15:0] */
+#define WM8962_DF1_COEFF_R1_SHIFT                    0  /* DF1_COEFF_R1 - [15:0] */
+#define WM8962_DF1_COEFF_R1_WIDTH                   16  /* DF1_COEFF_R1 - [15:0] */
+
+/*
+ * R262 (0x106) - DF7
+ */
+#define WM8962_DF1_COEFF_R2_MASK                0xFFFF  /* DF1_COEFF_R2 - [15:0] */
+#define WM8962_DF1_COEFF_R2_SHIFT                    0  /* DF1_COEFF_R2 - [15:0] */
+#define WM8962_DF1_COEFF_R2_WIDTH                   16  /* DF1_COEFF_R2 - [15:0] */
+
+/*
+ * R264 (0x108) - LHPF1
+ */
+#define WM8962_LHPF_MODE                        0x0002  /* LHPF_MODE */
+#define WM8962_LHPF_MODE_MASK                   0x0002  /* LHPF_MODE */
+#define WM8962_LHPF_MODE_SHIFT                       1  /* LHPF_MODE */
+#define WM8962_LHPF_MODE_WIDTH                       1  /* LHPF_MODE */
+#define WM8962_LHPF_ENA                         0x0001  /* LHPF_ENA */
+#define WM8962_LHPF_ENA_MASK                    0x0001  /* LHPF_ENA */
+#define WM8962_LHPF_ENA_SHIFT                        0  /* LHPF_ENA */
+#define WM8962_LHPF_ENA_WIDTH                        1  /* LHPF_ENA */
+
+/*
+ * R265 (0x109) - LHPF2
+ */
+#define WM8962_LHPF_COEFF_MASK                  0xFFFF  /* LHPF_COEFF - [15:0] */
+#define WM8962_LHPF_COEFF_SHIFT                      0  /* LHPF_COEFF - [15:0] */
+#define WM8962_LHPF_COEFF_WIDTH                     16  /* LHPF_COEFF - [15:0] */
+
+/*
+ * R268 (0x10C) - THREED1
+ */
+#define WM8962_ADC_MONOMIX                      0x0040  /* ADC_MONOMIX */
+#define WM8962_ADC_MONOMIX_MASK                 0x0040  /* ADC_MONOMIX */
+#define WM8962_ADC_MONOMIX_SHIFT                     6  /* ADC_MONOMIX */
+#define WM8962_ADC_MONOMIX_WIDTH                     1  /* ADC_MONOMIX */
+#define WM8962_THREED_SIGN_L                    0x0020  /* THREED_SIGN_L */
+#define WM8962_THREED_SIGN_L_MASK               0x0020  /* THREED_SIGN_L */
+#define WM8962_THREED_SIGN_L_SHIFT                   5  /* THREED_SIGN_L */
+#define WM8962_THREED_SIGN_L_WIDTH                   1  /* THREED_SIGN_L */
+#define WM8962_THREED_SIGN_R                    0x0010  /* THREED_SIGN_R */
+#define WM8962_THREED_SIGN_R_MASK               0x0010  /* THREED_SIGN_R */
+#define WM8962_THREED_SIGN_R_SHIFT                   4  /* THREED_SIGN_R */
+#define WM8962_THREED_SIGN_R_WIDTH                   1  /* THREED_SIGN_R */
+#define WM8962_THREED_LHPF_MODE                 0x0004  /* THREED_LHPF_MODE */
+#define WM8962_THREED_LHPF_MODE_MASK            0x0004  /* THREED_LHPF_MODE */
+#define WM8962_THREED_LHPF_MODE_SHIFT                2  /* THREED_LHPF_MODE */
+#define WM8962_THREED_LHPF_MODE_WIDTH                1  /* THREED_LHPF_MODE */
+#define WM8962_THREED_LHPF_ENA                  0x0002  /* THREED_LHPF_ENA */
+#define WM8962_THREED_LHPF_ENA_MASK             0x0002  /* THREED_LHPF_ENA */
+#define WM8962_THREED_LHPF_ENA_SHIFT                 1  /* THREED_LHPF_ENA */
+#define WM8962_THREED_LHPF_ENA_WIDTH                 1  /* THREED_LHPF_ENA */
+#define WM8962_THREED_ENA                       0x0001  /* THREED_ENA */
+#define WM8962_THREED_ENA_MASK                  0x0001  /* THREED_ENA */
+#define WM8962_THREED_ENA_SHIFT                      0  /* THREED_ENA */
+#define WM8962_THREED_ENA_WIDTH                      1  /* THREED_ENA */
+
+/*
+ * R269 (0x10D) - THREED2
+ */
+#define WM8962_THREED_FGAINL_MASK               0xF800  /* THREED_FGAINL - [15:11] */
+#define WM8962_THREED_FGAINL_SHIFT                  11  /* THREED_FGAINL - [15:11] */
+#define WM8962_THREED_FGAINL_WIDTH                   5  /* THREED_FGAINL - [15:11] */
+#define WM8962_THREED_CGAINL_MASK               0x07C0  /* THREED_CGAINL - [10:6] */
+#define WM8962_THREED_CGAINL_SHIFT                   6  /* THREED_CGAINL - [10:6] */
+#define WM8962_THREED_CGAINL_WIDTH                   5  /* THREED_CGAINL - [10:6] */
+#define WM8962_THREED_DELAYL_MASK               0x003C  /* THREED_DELAYL - [5:2] */
+#define WM8962_THREED_DELAYL_SHIFT                   2  /* THREED_DELAYL - [5:2] */
+#define WM8962_THREED_DELAYL_WIDTH                   4  /* THREED_DELAYL - [5:2] */
+
+/*
+ * R270 (0x10E) - THREED3
+ */
+#define WM8962_THREED_LHPF_COEFF_MASK           0xFFFF  /* THREED_LHPF_COEFF - [15:0] */
+#define WM8962_THREED_LHPF_COEFF_SHIFT               0  /* THREED_LHPF_COEFF - [15:0] */
+#define WM8962_THREED_LHPF_COEFF_WIDTH              16  /* THREED_LHPF_COEFF - [15:0] */
+
+/*
+ * R271 (0x10F) - THREED4
+ */
+#define WM8962_THREED_FGAINR_MASK               0xF800  /* THREED_FGAINR - [15:11] */
+#define WM8962_THREED_FGAINR_SHIFT                  11  /* THREED_FGAINR - [15:11] */
+#define WM8962_THREED_FGAINR_WIDTH                   5  /* THREED_FGAINR - [15:11] */
+#define WM8962_THREED_CGAINR_MASK               0x07C0  /* THREED_CGAINR - [10:6] */
+#define WM8962_THREED_CGAINR_SHIFT                   6  /* THREED_CGAINR - [10:6] */
+#define WM8962_THREED_CGAINR_WIDTH                   5  /* THREED_CGAINR - [10:6] */
+#define WM8962_THREED_DELAYR_MASK               0x003C  /* THREED_DELAYR - [5:2] */
+#define WM8962_THREED_DELAYR_SHIFT                   2  /* THREED_DELAYR - [5:2] */
+#define WM8962_THREED_DELAYR_WIDTH                   4  /* THREED_DELAYR - [5:2] */
+
+/*
+ * R276 (0x114) - DRC 1
+ */
+#define WM8962_DRC_SIG_DET_RMS_MASK             0x7C00  /* DRC_SIG_DET_RMS - [14:10] */
+#define WM8962_DRC_SIG_DET_RMS_SHIFT                10  /* DRC_SIG_DET_RMS - [14:10] */
+#define WM8962_DRC_SIG_DET_RMS_WIDTH                 5  /* DRC_SIG_DET_RMS - [14:10] */
+#define WM8962_DRC_SIG_DET_PK_MASK              0x0300  /* DRC_SIG_DET_PK - [9:8] */
+#define WM8962_DRC_SIG_DET_PK_SHIFT                  8  /* DRC_SIG_DET_PK - [9:8] */
+#define WM8962_DRC_SIG_DET_PK_WIDTH                  2  /* DRC_SIG_DET_PK - [9:8] */
+#define WM8962_DRC_NG_ENA                       0x0080  /* DRC_NG_ENA */
+#define WM8962_DRC_NG_ENA_MASK                  0x0080  /* DRC_NG_ENA */
+#define WM8962_DRC_NG_ENA_SHIFT                      7  /* DRC_NG_ENA */
+#define WM8962_DRC_NG_ENA_WIDTH                      1  /* DRC_NG_ENA */
+#define WM8962_DRC_SIG_DET_MODE                 0x0040  /* DRC_SIG_DET_MODE */
+#define WM8962_DRC_SIG_DET_MODE_MASK            0x0040  /* DRC_SIG_DET_MODE */
+#define WM8962_DRC_SIG_DET_MODE_SHIFT                6  /* DRC_SIG_DET_MODE */
+#define WM8962_DRC_SIG_DET_MODE_WIDTH                1  /* DRC_SIG_DET_MODE */
+#define WM8962_DRC_SIG_DET                      0x0020  /* DRC_SIG_DET */
+#define WM8962_DRC_SIG_DET_MASK                 0x0020  /* DRC_SIG_DET */
+#define WM8962_DRC_SIG_DET_SHIFT                     5  /* DRC_SIG_DET */
+#define WM8962_DRC_SIG_DET_WIDTH                     1  /* DRC_SIG_DET */
+#define WM8962_DRC_KNEE2_OP_ENA                 0x0010  /* DRC_KNEE2_OP_ENA */
+#define WM8962_DRC_KNEE2_OP_ENA_MASK            0x0010  /* DRC_KNEE2_OP_ENA */
+#define WM8962_DRC_KNEE2_OP_ENA_SHIFT                4  /* DRC_KNEE2_OP_ENA */
+#define WM8962_DRC_KNEE2_OP_ENA_WIDTH                1  /* DRC_KNEE2_OP_ENA */
+#define WM8962_DRC_QR                           0x0008  /* DRC_QR */
+#define WM8962_DRC_QR_MASK                      0x0008  /* DRC_QR */
+#define WM8962_DRC_QR_SHIFT                          3  /* DRC_QR */
+#define WM8962_DRC_QR_WIDTH                          1  /* DRC_QR */
+#define WM8962_DRC_ANTICLIP                     0x0004  /* DRC_ANTICLIP */
+#define WM8962_DRC_ANTICLIP_MASK                0x0004  /* DRC_ANTICLIP */
+#define WM8962_DRC_ANTICLIP_SHIFT                    2  /* DRC_ANTICLIP */
+#define WM8962_DRC_ANTICLIP_WIDTH                    1  /* DRC_ANTICLIP */
+#define WM8962_DRC_MODE                         0x0002  /* DRC_MODE */
+#define WM8962_DRC_MODE_MASK                    0x0002  /* DRC_MODE */
+#define WM8962_DRC_MODE_SHIFT                        1  /* DRC_MODE */
+#define WM8962_DRC_MODE_WIDTH                        1  /* DRC_MODE */
+#define WM8962_DRC_ENA                          0x0001  /* DRC_ENA */
+#define WM8962_DRC_ENA_MASK                     0x0001  /* DRC_ENA */
+#define WM8962_DRC_ENA_SHIFT                         0  /* DRC_ENA */
+#define WM8962_DRC_ENA_WIDTH                         1  /* DRC_ENA */
+
+/*
+ * R277 (0x115) - DRC 2
+ */
+#define WM8962_DRC_ATK_MASK                     0x1E00  /* DRC_ATK - [12:9] */
+#define WM8962_DRC_ATK_SHIFT                         9  /* DRC_ATK - [12:9] */
+#define WM8962_DRC_ATK_WIDTH                         4  /* DRC_ATK - [12:9] */
+#define WM8962_DRC_DCY_MASK                     0x01E0  /* DRC_DCY - [8:5] */
+#define WM8962_DRC_DCY_SHIFT                         5  /* DRC_DCY - [8:5] */
+#define WM8962_DRC_DCY_WIDTH                         4  /* DRC_DCY - [8:5] */
+#define WM8962_DRC_MINGAIN_MASK                 0x001C  /* DRC_MINGAIN - [4:2] */
+#define WM8962_DRC_MINGAIN_SHIFT                     2  /* DRC_MINGAIN - [4:2] */
+#define WM8962_DRC_MINGAIN_WIDTH                     3  /* DRC_MINGAIN - [4:2] */
+#define WM8962_DRC_MAXGAIN_MASK                 0x0003  /* DRC_MAXGAIN - [1:0] */
+#define WM8962_DRC_MAXGAIN_SHIFT                     0  /* DRC_MAXGAIN - [1:0] */
+#define WM8962_DRC_MAXGAIN_WIDTH                     2  /* DRC_MAXGAIN - [1:0] */
+
+/*
+ * R278 (0x116) - DRC 3
+ */
+#define WM8962_DRC_NG_MINGAIN_MASK              0xF000  /* DRC_NG_MINGAIN - [15:12] */
+#define WM8962_DRC_NG_MINGAIN_SHIFT                 12  /* DRC_NG_MINGAIN - [15:12] */
+#define WM8962_DRC_NG_MINGAIN_WIDTH                  4  /* DRC_NG_MINGAIN - [15:12] */
+#define WM8962_DRC_QR_THR_MASK                  0x0C00  /* DRC_QR_THR - [11:10] */
+#define WM8962_DRC_QR_THR_SHIFT                     10  /* DRC_QR_THR - [11:10] */
+#define WM8962_DRC_QR_THR_WIDTH                      2  /* DRC_QR_THR - [11:10] */
+#define WM8962_DRC_QR_DCY_MASK                  0x0300  /* DRC_QR_DCY - [9:8] */
+#define WM8962_DRC_QR_DCY_SHIFT                      8  /* DRC_QR_DCY - [9:8] */
+#define WM8962_DRC_QR_DCY_WIDTH                      2  /* DRC_QR_DCY - [9:8] */
+#define WM8962_DRC_NG_EXP_MASK                  0x00C0  /* DRC_NG_EXP - [7:6] */
+#define WM8962_DRC_NG_EXP_SHIFT                      6  /* DRC_NG_EXP - [7:6] */
+#define WM8962_DRC_NG_EXP_WIDTH                      2  /* DRC_NG_EXP - [7:6] */
+#define WM8962_DRC_HI_COMP_MASK                 0x0038  /* DRC_HI_COMP - [5:3] */
+#define WM8962_DRC_HI_COMP_SHIFT                     3  /* DRC_HI_COMP - [5:3] */
+#define WM8962_DRC_HI_COMP_WIDTH                     3  /* DRC_HI_COMP - [5:3] */
+#define WM8962_DRC_LO_COMP_MASK                 0x0007  /* DRC_LO_COMP - [2:0] */
+#define WM8962_DRC_LO_COMP_SHIFT                     0  /* DRC_LO_COMP - [2:0] */
+#define WM8962_DRC_LO_COMP_WIDTH                     3  /* DRC_LO_COMP - [2:0] */
+
+/*
+ * R279 (0x117) - DRC 4
+ */
+#define WM8962_DRC_KNEE_IP_MASK                 0x07E0  /* DRC_KNEE_IP - [10:5] */
+#define WM8962_DRC_KNEE_IP_SHIFT                     5  /* DRC_KNEE_IP - [10:5] */
+#define WM8962_DRC_KNEE_IP_WIDTH                     6  /* DRC_KNEE_IP - [10:5] */
+#define WM8962_DRC_KNEE_OP_MASK                 0x001F  /* DRC_KNEE_OP - [4:0] */
+#define WM8962_DRC_KNEE_OP_SHIFT                     0  /* DRC_KNEE_OP - [4:0] */
+#define WM8962_DRC_KNEE_OP_WIDTH                     5  /* DRC_KNEE_OP - [4:0] */
+
+/*
+ * R280 (0x118) - DRC 5
+ */
+#define WM8962_DRC_KNEE2_IP_MASK                0x03E0  /* DRC_KNEE2_IP - [9:5] */
+#define WM8962_DRC_KNEE2_IP_SHIFT                    5  /* DRC_KNEE2_IP - [9:5] */
+#define WM8962_DRC_KNEE2_IP_WIDTH                    5  /* DRC_KNEE2_IP - [9:5] */
+#define WM8962_DRC_KNEE2_OP_MASK                0x001F  /* DRC_KNEE2_OP - [4:0] */
+#define WM8962_DRC_KNEE2_OP_SHIFT                    0  /* DRC_KNEE2_OP - [4:0] */
+#define WM8962_DRC_KNEE2_OP_WIDTH                    5  /* DRC_KNEE2_OP - [4:0] */
+
+/*
+ * R285 (0x11D) - Tloopback
+ */
+#define WM8962_TLB_ENA                          0x0002  /* TLB_ENA */
+#define WM8962_TLB_ENA_MASK                     0x0002  /* TLB_ENA */
+#define WM8962_TLB_ENA_SHIFT                         1  /* TLB_ENA */
+#define WM8962_TLB_ENA_WIDTH                         1  /* TLB_ENA */
+#define WM8962_TLB_MODE                         0x0001  /* TLB_MODE */
+#define WM8962_TLB_MODE_MASK                    0x0001  /* TLB_MODE */
+#define WM8962_TLB_MODE_SHIFT                        0  /* TLB_MODE */
+#define WM8962_TLB_MODE_WIDTH                        1  /* TLB_MODE */
+
+/*
+ * R335 (0x14F) - EQ1
+ */
+#define WM8962_EQ_SHARED_COEFF                  0x0004  /* EQ_SHARED_COEFF */
+#define WM8962_EQ_SHARED_COEFF_MASK             0x0004  /* EQ_SHARED_COEFF */
+#define WM8962_EQ_SHARED_COEFF_SHIFT                 2  /* EQ_SHARED_COEFF */
+#define WM8962_EQ_SHARED_COEFF_WIDTH                 1  /* EQ_SHARED_COEFF */
+#define WM8962_EQ_SHARED_COEFF_SEL              0x0002  /* EQ_SHARED_COEFF_SEL */
+#define WM8962_EQ_SHARED_COEFF_SEL_MASK         0x0002  /* EQ_SHARED_COEFF_SEL */
+#define WM8962_EQ_SHARED_COEFF_SEL_SHIFT             1  /* EQ_SHARED_COEFF_SEL */
+#define WM8962_EQ_SHARED_COEFF_SEL_WIDTH             1  /* EQ_SHARED_COEFF_SEL */
+#define WM8962_EQ_ENA                           0x0001  /* EQ_ENA */
+#define WM8962_EQ_ENA_MASK                      0x0001  /* EQ_ENA */
+#define WM8962_EQ_ENA_SHIFT                          0  /* EQ_ENA */
+#define WM8962_EQ_ENA_WIDTH                          1  /* EQ_ENA */
+
+/*
+ * R336 (0x150) - EQ2
+ */
+#define WM8962_EQL_B1_GAIN_MASK                 0xF800  /* EQL_B1_GAIN - [15:11] */
+#define WM8962_EQL_B1_GAIN_SHIFT                    11  /* EQL_B1_GAIN - [15:11] */
+#define WM8962_EQL_B1_GAIN_WIDTH                     5  /* EQL_B1_GAIN - [15:11] */
+#define WM8962_EQL_B2_GAIN_MASK                 0x07C0  /* EQL_B2_GAIN - [10:6] */
+#define WM8962_EQL_B2_GAIN_SHIFT                     6  /* EQL_B2_GAIN - [10:6] */
+#define WM8962_EQL_B2_GAIN_WIDTH                     5  /* EQL_B2_GAIN - [10:6] */
+#define WM8962_EQL_B3_GAIN_MASK                 0x003E  /* EQL_B3_GAIN - [5:1] */
+#define WM8962_EQL_B3_GAIN_SHIFT                     1  /* EQL_B3_GAIN - [5:1] */
+#define WM8962_EQL_B3_GAIN_WIDTH                     5  /* EQL_B3_GAIN - [5:1] */
+
+/*
+ * R337 (0x151) - EQ3
+ */
+#define WM8962_EQL_B4_GAIN_MASK                 0xF800  /* EQL_B4_GAIN - [15:11] */
+#define WM8962_EQL_B4_GAIN_SHIFT                    11  /* EQL_B4_GAIN - [15:11] */
+#define WM8962_EQL_B4_GAIN_WIDTH                     5  /* EQL_B4_GAIN - [15:11] */
+#define WM8962_EQL_B5_GAIN_MASK                 0x07C0  /* EQL_B5_GAIN - [10:6] */
+#define WM8962_EQL_B5_GAIN_SHIFT                     6  /* EQL_B5_GAIN - [10:6] */
+#define WM8962_EQL_B5_GAIN_WIDTH                     5  /* EQL_B5_GAIN - [10:6] */
+
+/*
+ * R338 (0x152) - EQ4
+ */
+#define WM8962_EQL_B1_A_MASK                    0xFFFF  /* EQL_B1_A - [15:0] */
+#define WM8962_EQL_B1_A_SHIFT                        0  /* EQL_B1_A - [15:0] */
+#define WM8962_EQL_B1_A_WIDTH                       16  /* EQL_B1_A - [15:0] */
+
+/*
+ * R339 (0x153) - EQ5
+ */
+#define WM8962_EQL_B1_B_MASK                    0xFFFF  /* EQL_B1_B - [15:0] */
+#define WM8962_EQL_B1_B_SHIFT                        0  /* EQL_B1_B - [15:0] */
+#define WM8962_EQL_B1_B_WIDTH                       16  /* EQL_B1_B - [15:0] */
+
+/*
+ * R340 (0x154) - EQ6
+ */
+#define WM8962_EQL_B1_PG_MASK                   0xFFFF  /* EQL_B1_PG - [15:0] */
+#define WM8962_EQL_B1_PG_SHIFT                       0  /* EQL_B1_PG - [15:0] */
+#define WM8962_EQL_B1_PG_WIDTH                      16  /* EQL_B1_PG - [15:0] */
+
+/*
+ * R341 (0x155) - EQ7
+ */
+#define WM8962_EQL_B2_A_MASK                    0xFFFF  /* EQL_B2_A - [15:0] */
+#define WM8962_EQL_B2_A_SHIFT                        0  /* EQL_B2_A - [15:0] */
+#define WM8962_EQL_B2_A_WIDTH                       16  /* EQL_B2_A - [15:0] */
+
+/*
+ * R342 (0x156) - EQ8
+ */
+#define WM8962_EQL_B2_B_MASK                    0xFFFF  /* EQL_B2_B - [15:0] */
+#define WM8962_EQL_B2_B_SHIFT                        0  /* EQL_B2_B - [15:0] */
+#define WM8962_EQL_B2_B_WIDTH                       16  /* EQL_B2_B - [15:0] */
+
+/*
+ * R343 (0x157) - EQ9
+ */
+#define WM8962_EQL_B2_C_MASK                    0xFFFF  /* EQL_B2_C - [15:0] */
+#define WM8962_EQL_B2_C_SHIFT                        0  /* EQL_B2_C - [15:0] */
+#define WM8962_EQL_B2_C_WIDTH                       16  /* EQL_B2_C - [15:0] */
+
+/*
+ * R344 (0x158) - EQ10
+ */
+#define WM8962_EQL_B2_PG_MASK                   0xFFFF  /* EQL_B2_PG - [15:0] */
+#define WM8962_EQL_B2_PG_SHIFT                       0  /* EQL_B2_PG - [15:0] */
+#define WM8962_EQL_B2_PG_WIDTH                      16  /* EQL_B2_PG - [15:0] */
+
+/*
+ * R345 (0x159) - EQ11
+ */
+#define WM8962_EQL_B3_A_MASK                    0xFFFF  /* EQL_B3_A - [15:0] */
+#define WM8962_EQL_B3_A_SHIFT                        0  /* EQL_B3_A - [15:0] */
+#define WM8962_EQL_B3_A_WIDTH                       16  /* EQL_B3_A - [15:0] */
+
+/*
+ * R346 (0x15A) - EQ12
+ */
+#define WM8962_EQL_B3_B_MASK                    0xFFFF  /* EQL_B3_B - [15:0] */
+#define WM8962_EQL_B3_B_SHIFT                        0  /* EQL_B3_B - [15:0] */
+#define WM8962_EQL_B3_B_WIDTH                       16  /* EQL_B3_B - [15:0] */
+
+/*
+ * R347 (0x15B) - EQ13
+ */
+#define WM8962_EQL_B3_C_MASK                    0xFFFF  /* EQL_B3_C - [15:0] */
+#define WM8962_EQL_B3_C_SHIFT                        0  /* EQL_B3_C - [15:0] */
+#define WM8962_EQL_B3_C_WIDTH                       16  /* EQL_B3_C - [15:0] */
+
+/*
+ * R348 (0x15C) - EQ14
+ */
+#define WM8962_EQL_B3_PG_MASK                   0xFFFF  /* EQL_B3_PG - [15:0] */
+#define WM8962_EQL_B3_PG_SHIFT                       0  /* EQL_B3_PG - [15:0] */
+#define WM8962_EQL_B3_PG_WIDTH                      16  /* EQL_B3_PG - [15:0] */
+
+/*
+ * R349 (0x15D) - EQ15
+ */
+#define WM8962_EQL_B4_A_MASK                    0xFFFF  /* EQL_B4_A - [15:0] */
+#define WM8962_EQL_B4_A_SHIFT                        0  /* EQL_B4_A - [15:0] */
+#define WM8962_EQL_B4_A_WIDTH                       16  /* EQL_B4_A - [15:0] */
+
+/*
+ * R350 (0x15E) - EQ16
+ */
+#define WM8962_EQL_B4_B_MASK                    0xFFFF  /* EQL_B4_B - [15:0] */
+#define WM8962_EQL_B4_B_SHIFT                        0  /* EQL_B4_B - [15:0] */
+#define WM8962_EQL_B4_B_WIDTH                       16  /* EQL_B4_B - [15:0] */
+
+/*
+ * R351 (0x15F) - EQ17
+ */
+#define WM8962_EQL_B4_C_MASK                    0xFFFF  /* EQL_B4_C - [15:0] */
+#define WM8962_EQL_B4_C_SHIFT                        0  /* EQL_B4_C - [15:0] */
+#define WM8962_EQL_B4_C_WIDTH                       16  /* EQL_B4_C - [15:0] */
+
+/*
+ * R352 (0x160) - EQ18
+ */
+#define WM8962_EQL_B4_PG_MASK                   0xFFFF  /* EQL_B4_PG - [15:0] */
+#define WM8962_EQL_B4_PG_SHIFT                       0  /* EQL_B4_PG - [15:0] */
+#define WM8962_EQL_B4_PG_WIDTH                      16  /* EQL_B4_PG - [15:0] */
+
+/*
+ * R353 (0x161) - EQ19
+ */
+#define WM8962_EQL_B5_A_MASK                    0xFFFF  /* EQL_B5_A - [15:0] */
+#define WM8962_EQL_B5_A_SHIFT                        0  /* EQL_B5_A - [15:0] */
+#define WM8962_EQL_B5_A_WIDTH                       16  /* EQL_B5_A - [15:0] */
+
+/*
+ * R354 (0x162) - EQ20
+ */
+#define WM8962_EQL_B5_B_MASK                    0xFFFF  /* EQL_B5_B - [15:0] */
+#define WM8962_EQL_B5_B_SHIFT                        0  /* EQL_B5_B - [15:0] */
+#define WM8962_EQL_B5_B_WIDTH                       16  /* EQL_B5_B - [15:0] */
+
+/*
+ * R355 (0x163) - EQ21
+ */
+#define WM8962_EQL_B5_PG_MASK                   0xFFFF  /* EQL_B5_PG - [15:0] */
+#define WM8962_EQL_B5_PG_SHIFT                       0  /* EQL_B5_PG - [15:0] */
+#define WM8962_EQL_B5_PG_WIDTH                      16  /* EQL_B5_PG - [15:0] */
+
+/*
+ * R356 (0x164) - EQ22
+ */
+#define WM8962_EQR_B1_GAIN_MASK                 0xF800  /* EQR_B1_GAIN - [15:11] */
+#define WM8962_EQR_B1_GAIN_SHIFT                    11  /* EQR_B1_GAIN - [15:11] */
+#define WM8962_EQR_B1_GAIN_WIDTH                     5  /* EQR_B1_GAIN - [15:11] */
+#define WM8962_EQR_B2_GAIN_MASK                 0x07C0  /* EQR_B2_GAIN - [10:6] */
+#define WM8962_EQR_B2_GAIN_SHIFT                     6  /* EQR_B2_GAIN - [10:6] */
+#define WM8962_EQR_B2_GAIN_WIDTH                     5  /* EQR_B2_GAIN - [10:6] */
+#define WM8962_EQR_B3_GAIN_MASK                 0x003E  /* EQR_B3_GAIN - [5:1] */
+#define WM8962_EQR_B3_GAIN_SHIFT                     1  /* EQR_B3_GAIN - [5:1] */
+#define WM8962_EQR_B3_GAIN_WIDTH                     5  /* EQR_B3_GAIN - [5:1] */
+
+/*
+ * R357 (0x165) - EQ23
+ */
+#define WM8962_EQR_B4_GAIN_MASK                 0xF800  /* EQR_B4_GAIN - [15:11] */
+#define WM8962_EQR_B4_GAIN_SHIFT                    11  /* EQR_B4_GAIN - [15:11] */
+#define WM8962_EQR_B4_GAIN_WIDTH                     5  /* EQR_B4_GAIN - [15:11] */
+#define WM8962_EQR_B5_GAIN_MASK                 0x07C0  /* EQR_B5_GAIN - [10:6] */
+#define WM8962_EQR_B5_GAIN_SHIFT                     6  /* EQR_B5_GAIN - [10:6] */
+#define WM8962_EQR_B5_GAIN_WIDTH                     5  /* EQR_B5_GAIN - [10:6] */
+
+/*
+ * R358 (0x166) - EQ24
+ */
+#define WM8962_EQR_B1_A_MASK                    0xFFFF  /* EQR_B1_A - [15:0] */
+#define WM8962_EQR_B1_A_SHIFT                        0  /* EQR_B1_A - [15:0] */
+#define WM8962_EQR_B1_A_WIDTH                       16  /* EQR_B1_A - [15:0] */
+
+/*
+ * R359 (0x167) - EQ25
+ */
+#define WM8962_EQR_B1_B_MASK                    0xFFFF  /* EQR_B1_B - [15:0] */
+#define WM8962_EQR_B1_B_SHIFT                        0  /* EQR_B1_B - [15:0] */
+#define WM8962_EQR_B1_B_WIDTH                       16  /* EQR_B1_B - [15:0] */
+
+/*
+ * R360 (0x168) - EQ26
+ */
+#define WM8962_EQR_B1_PG_MASK                   0xFFFF  /* EQR_B1_PG - [15:0] */
+#define WM8962_EQR_B1_PG_SHIFT                       0  /* EQR_B1_PG - [15:0] */
+#define WM8962_EQR_B1_PG_WIDTH                      16  /* EQR_B1_PG - [15:0] */
+
+/*
+ * R361 (0x169) - EQ27
+ */
+#define WM8962_EQR_B2_A_MASK                    0xFFFF  /* EQR_B2_A - [15:0] */
+#define WM8962_EQR_B2_A_SHIFT                        0  /* EQR_B2_A - [15:0] */
+#define WM8962_EQR_B2_A_WIDTH                       16  /* EQR_B2_A - [15:0] */
+
+/*
+ * R362 (0x16A) - EQ28
+ */
+#define WM8962_EQR_B2_B_MASK                    0xFFFF  /* EQR_B2_B - [15:0] */
+#define WM8962_EQR_B2_B_SHIFT                        0  /* EQR_B2_B - [15:0] */
+#define WM8962_EQR_B2_B_WIDTH                       16  /* EQR_B2_B - [15:0] */
+
+/*
+ * R363 (0x16B) - EQ29
+ */
+#define WM8962_EQR_B2_C_MASK                    0xFFFF  /* EQR_B2_C - [15:0] */
+#define WM8962_EQR_B2_C_SHIFT                        0  /* EQR_B2_C - [15:0] */
+#define WM8962_EQR_B2_C_WIDTH                       16  /* EQR_B2_C - [15:0] */
+
+/*
+ * R364 (0x16C) - EQ30
+ */
+#define WM8962_EQR_B2_PG_MASK                   0xFFFF  /* EQR_B2_PG - [15:0] */
+#define WM8962_EQR_B2_PG_SHIFT                       0  /* EQR_B2_PG - [15:0] */
+#define WM8962_EQR_B2_PG_WIDTH                      16  /* EQR_B2_PG - [15:0] */
+
+/*
+ * R365 (0x16D) - EQ31
+ */
+#define WM8962_EQR_B3_A_MASK                    0xFFFF  /* EQR_B3_A - [15:0] */
+#define WM8962_EQR_B3_A_SHIFT                        0  /* EQR_B3_A - [15:0] */
+#define WM8962_EQR_B3_A_WIDTH                       16  /* EQR_B3_A - [15:0] */
+
+/*
+ * R366 (0x16E) - EQ32
+ */
+#define WM8962_EQR_B3_B_MASK                    0xFFFF  /* EQR_B3_B - [15:0] */
+#define WM8962_EQR_B3_B_SHIFT                        0  /* EQR_B3_B - [15:0] */
+#define WM8962_EQR_B3_B_WIDTH                       16  /* EQR_B3_B - [15:0] */
+
+/*
+ * R367 (0x16F) - EQ33
+ */
+#define WM8962_EQR_B3_C_MASK                    0xFFFF  /* EQR_B3_C - [15:0] */
+#define WM8962_EQR_B3_C_SHIFT                        0  /* EQR_B3_C - [15:0] */
+#define WM8962_EQR_B3_C_WIDTH                       16  /* EQR_B3_C - [15:0] */
+
+/*
+ * R368 (0x170) - EQ34
+ */
+#define WM8962_EQR_B3_PG_MASK                   0xFFFF  /* EQR_B3_PG - [15:0] */
+#define WM8962_EQR_B3_PG_SHIFT                       0  /* EQR_B3_PG - [15:0] */
+#define WM8962_EQR_B3_PG_WIDTH                      16  /* EQR_B3_PG - [15:0] */
+
+/*
+ * R369 (0x171) - EQ35
+ */
+#define WM8962_EQR_B4_A_MASK                    0xFFFF  /* EQR_B4_A - [15:0] */
+#define WM8962_EQR_B4_A_SHIFT                        0  /* EQR_B4_A - [15:0] */
+#define WM8962_EQR_B4_A_WIDTH                       16  /* EQR_B4_A - [15:0] */
+
+/*
+ * R370 (0x172) - EQ36
+ */
+#define WM8962_EQR_B4_B_MASK                    0xFFFF  /* EQR_B4_B - [15:0] */
+#define WM8962_EQR_B4_B_SHIFT                        0  /* EQR_B4_B - [15:0] */
+#define WM8962_EQR_B4_B_WIDTH                       16  /* EQR_B4_B - [15:0] */
+
+/*
+ * R371 (0x173) - EQ37
+ */
+#define WM8962_EQR_B4_C_MASK                    0xFFFF  /* EQR_B4_C - [15:0] */
+#define WM8962_EQR_B4_C_SHIFT                        0  /* EQR_B4_C - [15:0] */
+#define WM8962_EQR_B4_C_WIDTH                       16  /* EQR_B4_C - [15:0] */
+
+/*
+ * R372 (0x174) - EQ38
+ */
+#define WM8962_EQR_B4_PG_MASK                   0xFFFF  /* EQR_B4_PG - [15:0] */
+#define WM8962_EQR_B4_PG_SHIFT                       0  /* EQR_B4_PG - [15:0] */
+#define WM8962_EQR_B4_PG_WIDTH                      16  /* EQR_B4_PG - [15:0] */
+
+/*
+ * R373 (0x175) - EQ39
+ */
+#define WM8962_EQR_B5_A_MASK                    0xFFFF  /* EQR_B5_A - [15:0] */
+#define WM8962_EQR_B5_A_SHIFT                        0  /* EQR_B5_A - [15:0] */
+#define WM8962_EQR_B5_A_WIDTH                       16  /* EQR_B5_A - [15:0] */
+
+/*
+ * R374 (0x176) - EQ40
+ */
+#define WM8962_EQR_B5_B_MASK                    0xFFFF  /* EQR_B5_B - [15:0] */
+#define WM8962_EQR_B5_B_SHIFT                        0  /* EQR_B5_B - [15:0] */
+#define WM8962_EQR_B5_B_WIDTH                       16  /* EQR_B5_B - [15:0] */
+
+/*
+ * R375 (0x177) - EQ41
+ */
+#define WM8962_EQR_B5_PG_MASK                   0xFFFF  /* EQR_B5_PG - [15:0] */
+#define WM8962_EQR_B5_PG_SHIFT                       0  /* EQR_B5_PG - [15:0] */
+#define WM8962_EQR_B5_PG_WIDTH                      16  /* EQR_B5_PG - [15:0] */
+
+/*
+ * R513 (0x201) - GPIO 2
+ */
+#define WM8962_GP2_POL                          0x0400  /* GP2_POL */
+#define WM8962_GP2_POL_MASK                     0x0400  /* GP2_POL */
+#define WM8962_GP2_POL_SHIFT                        10  /* GP2_POL */
+#define WM8962_GP2_POL_WIDTH                         1  /* GP2_POL */
+#define WM8962_GP2_LVL                          0x0040  /* GP2_LVL */
+#define WM8962_GP2_LVL_MASK                     0x0040  /* GP2_LVL */
+#define WM8962_GP2_LVL_SHIFT                         6  /* GP2_LVL */
+#define WM8962_GP2_LVL_WIDTH                         1  /* GP2_LVL */
+#define WM8962_GP2_FN_MASK                      0x001F  /* GP2_FN - [4:0] */
+#define WM8962_GP2_FN_SHIFT                          0  /* GP2_FN - [4:0] */
+#define WM8962_GP2_FN_WIDTH                          5  /* GP2_FN - [4:0] */
+
+/*
+ * R514 (0x202) - GPIO 3
+ */
+#define WM8962_GP3_POL                          0x0400  /* GP3_POL */
+#define WM8962_GP3_POL_MASK                     0x0400  /* GP3_POL */
+#define WM8962_GP3_POL_SHIFT                        10  /* GP3_POL */
+#define WM8962_GP3_POL_WIDTH                         1  /* GP3_POL */
+#define WM8962_GP3_LVL                          0x0040  /* GP3_LVL */
+#define WM8962_GP3_LVL_MASK                     0x0040  /* GP3_LVL */
+#define WM8962_GP3_LVL_SHIFT                         6  /* GP3_LVL */
+#define WM8962_GP3_LVL_WIDTH                         1  /* GP3_LVL */
+#define WM8962_GP3_FN_MASK                      0x001F  /* GP3_FN - [4:0] */
+#define WM8962_GP3_FN_SHIFT                          0  /* GP3_FN - [4:0] */
+#define WM8962_GP3_FN_WIDTH                          5  /* GP3_FN - [4:0] */
+
+/*
+ * R516 (0x204) - GPIO 5
+ */
+#define WM8962_GP5_DIR                          0x8000  /* GP5_DIR */
+#define WM8962_GP5_DIR_MASK                     0x8000  /* GP5_DIR */
+#define WM8962_GP5_DIR_SHIFT                        15  /* GP5_DIR */
+#define WM8962_GP5_DIR_WIDTH                         1  /* GP5_DIR */
+#define WM8962_GP5_PU                           0x4000  /* GP5_PU */
+#define WM8962_GP5_PU_MASK                      0x4000  /* GP5_PU */
+#define WM8962_GP5_PU_SHIFT                         14  /* GP5_PU */
+#define WM8962_GP5_PU_WIDTH                          1  /* GP5_PU */
+#define WM8962_GP5_PD                           0x2000  /* GP5_PD */
+#define WM8962_GP5_PD_MASK                      0x2000  /* GP5_PD */
+#define WM8962_GP5_PD_SHIFT                         13  /* GP5_PD */
+#define WM8962_GP5_PD_WIDTH                          1  /* GP5_PD */
+#define WM8962_GP5_POL                          0x0400  /* GP5_POL */
+#define WM8962_GP5_POL_MASK                     0x0400  /* GP5_POL */
+#define WM8962_GP5_POL_SHIFT                        10  /* GP5_POL */
+#define WM8962_GP5_POL_WIDTH                         1  /* GP5_POL */
+#define WM8962_GP5_OP_CFG                       0x0200  /* GP5_OP_CFG */
+#define WM8962_GP5_OP_CFG_MASK                  0x0200  /* GP5_OP_CFG */
+#define WM8962_GP5_OP_CFG_SHIFT                      9  /* GP5_OP_CFG */
+#define WM8962_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
+#define WM8962_GP5_DB                           0x0100  /* GP5_DB */
+#define WM8962_GP5_DB_MASK                      0x0100  /* GP5_DB */
+#define WM8962_GP5_DB_SHIFT                          8  /* GP5_DB */
+#define WM8962_GP5_DB_WIDTH                          1  /* GP5_DB */
+#define WM8962_GP5_LVL                          0x0040  /* GP5_LVL */
+#define WM8962_GP5_LVL_MASK                     0x0040  /* GP5_LVL */
+#define WM8962_GP5_LVL_SHIFT                         6  /* GP5_LVL */
+#define WM8962_GP5_LVL_WIDTH                         1  /* GP5_LVL */
+#define WM8962_GP5_FN_MASK                      0x001F  /* GP5_FN - [4:0] */
+#define WM8962_GP5_FN_SHIFT                          0  /* GP5_FN - [4:0] */
+#define WM8962_GP5_FN_WIDTH                          5  /* GP5_FN - [4:0] */
+
+/*
+ * R517 (0x205) - GPIO 6
+ */
+#define WM8962_GP6_DIR                          0x8000  /* GP6_DIR */
+#define WM8962_GP6_DIR_MASK                     0x8000  /* GP6_DIR */
+#define WM8962_GP6_DIR_SHIFT                        15  /* GP6_DIR */
+#define WM8962_GP6_DIR_WIDTH                         1  /* GP6_DIR */
+#define WM8962_GP6_PU                           0x4000  /* GP6_PU */
+#define WM8962_GP6_PU_MASK                      0x4000  /* GP6_PU */
+#define WM8962_GP6_PU_SHIFT                         14  /* GP6_PU */
+#define WM8962_GP6_PU_WIDTH                          1  /* GP6_PU */
+#define WM8962_GP6_PD                           0x2000  /* GP6_PD */
+#define WM8962_GP6_PD_MASK                      0x2000  /* GP6_PD */
+#define WM8962_GP6_PD_SHIFT                         13  /* GP6_PD */
+#define WM8962_GP6_PD_WIDTH                          1  /* GP6_PD */
+#define WM8962_GP6_POL                          0x0400  /* GP6_POL */
+#define WM8962_GP6_POL_MASK                     0x0400  /* GP6_POL */
+#define WM8962_GP6_POL_SHIFT                        10  /* GP6_POL */
+#define WM8962_GP6_POL_WIDTH                         1  /* GP6_POL */
+#define WM8962_GP6_OP_CFG                       0x0200  /* GP6_OP_CFG */
+#define WM8962_GP6_OP_CFG_MASK                  0x0200  /* GP6_OP_CFG */
+#define WM8962_GP6_OP_CFG_SHIFT                      9  /* GP6_OP_CFG */
+#define WM8962_GP6_OP_CFG_WIDTH                      1  /* GP6_OP_CFG */
+#define WM8962_GP6_DB                           0x0100  /* GP6_DB */
+#define WM8962_GP6_DB_MASK                      0x0100  /* GP6_DB */
+#define WM8962_GP6_DB_SHIFT                          8  /* GP6_DB */
+#define WM8962_GP6_DB_WIDTH                          1  /* GP6_DB */
+#define WM8962_GP6_LVL                          0x0040  /* GP6_LVL */
+#define WM8962_GP6_LVL_MASK                     0x0040  /* GP6_LVL */
+#define WM8962_GP6_LVL_SHIFT                         6  /* GP6_LVL */
+#define WM8962_GP6_LVL_WIDTH                         1  /* GP6_LVL */
+#define WM8962_GP6_FN_MASK                      0x001F  /* GP6_FN - [4:0] */
+#define WM8962_GP6_FN_SHIFT                          0  /* GP6_FN - [4:0] */
+#define WM8962_GP6_FN_WIDTH                          5  /* GP6_FN - [4:0] */
+
+/*
+ * R560 (0x230) - Interrupt Status 1
+ */
+#define WM8962_GP6_EINT                         0x0020  /* GP6_EINT */
+#define WM8962_GP6_EINT_MASK                    0x0020  /* GP6_EINT */
+#define WM8962_GP6_EINT_SHIFT                        5  /* GP6_EINT */
+#define WM8962_GP6_EINT_WIDTH                        1  /* GP6_EINT */
+#define WM8962_GP5_EINT                         0x0010  /* GP5_EINT */
+#define WM8962_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
+#define WM8962_GP5_EINT_SHIFT                        4  /* GP5_EINT */
+#define WM8962_GP5_EINT_WIDTH                        1  /* GP5_EINT */
+
+/*
+ * R561 (0x231) - Interrupt Status 2
+ */
+#define WM8962_MICSCD_EINT                      0x8000  /* MICSCD_EINT */
+#define WM8962_MICSCD_EINT_MASK                 0x8000  /* MICSCD_EINT */
+#define WM8962_MICSCD_EINT_SHIFT                    15  /* MICSCD_EINT */
+#define WM8962_MICSCD_EINT_WIDTH                     1  /* MICSCD_EINT */
+#define WM8962_MICD_EINT                        0x4000  /* MICD_EINT */
+#define WM8962_MICD_EINT_MASK                   0x4000  /* MICD_EINT */
+#define WM8962_MICD_EINT_SHIFT                      14  /* MICD_EINT */
+#define WM8962_MICD_EINT_WIDTH                       1  /* MICD_EINT */
+#define WM8962_FIFOS_ERR_EINT                   0x2000  /* FIFOS_ERR_EINT */
+#define WM8962_FIFOS_ERR_EINT_MASK              0x2000  /* FIFOS_ERR_EINT */
+#define WM8962_FIFOS_ERR_EINT_SHIFT                 13  /* FIFOS_ERR_EINT */
+#define WM8962_FIFOS_ERR_EINT_WIDTH                  1  /* FIFOS_ERR_EINT */
+#define WM8962_ALC_LOCK_EINT                    0x1000  /* ALC_LOCK_EINT */
+#define WM8962_ALC_LOCK_EINT_MASK               0x1000  /* ALC_LOCK_EINT */
+#define WM8962_ALC_LOCK_EINT_SHIFT                  12  /* ALC_LOCK_EINT */
+#define WM8962_ALC_LOCK_EINT_WIDTH                   1  /* ALC_LOCK_EINT */
+#define WM8962_ALC_THRESH_EINT                  0x0800  /* ALC_THRESH_EINT */
+#define WM8962_ALC_THRESH_EINT_MASK             0x0800  /* ALC_THRESH_EINT */
+#define WM8962_ALC_THRESH_EINT_SHIFT                11  /* ALC_THRESH_EINT */
+#define WM8962_ALC_THRESH_EINT_WIDTH                 1  /* ALC_THRESH_EINT */
+#define WM8962_ALC_SAT_EINT                     0x0400  /* ALC_SAT_EINT */
+#define WM8962_ALC_SAT_EINT_MASK                0x0400  /* ALC_SAT_EINT */
+#define WM8962_ALC_SAT_EINT_SHIFT                   10  /* ALC_SAT_EINT */
+#define WM8962_ALC_SAT_EINT_WIDTH                    1  /* ALC_SAT_EINT */
+#define WM8962_ALC_PKOVR_EINT                   0x0200  /* ALC_PKOVR_EINT */
+#define WM8962_ALC_PKOVR_EINT_MASK              0x0200  /* ALC_PKOVR_EINT */
+#define WM8962_ALC_PKOVR_EINT_SHIFT                  9  /* ALC_PKOVR_EINT */
+#define WM8962_ALC_PKOVR_EINT_WIDTH                  1  /* ALC_PKOVR_EINT */
+#define WM8962_ALC_NGATE_EINT                   0x0100  /* ALC_NGATE_EINT */
+#define WM8962_ALC_NGATE_EINT_MASK              0x0100  /* ALC_NGATE_EINT */
+#define WM8962_ALC_NGATE_EINT_SHIFT                  8  /* ALC_NGATE_EINT */
+#define WM8962_ALC_NGATE_EINT_WIDTH                  1  /* ALC_NGATE_EINT */
+#define WM8962_WSEQ_DONE_EINT                   0x0080  /* WSEQ_DONE_EINT */
+#define WM8962_WSEQ_DONE_EINT_MASK              0x0080  /* WSEQ_DONE_EINT */
+#define WM8962_WSEQ_DONE_EINT_SHIFT                  7  /* WSEQ_DONE_EINT */
+#define WM8962_WSEQ_DONE_EINT_WIDTH                  1  /* WSEQ_DONE_EINT */
+#define WM8962_DRC_ACTDET_EINT                  0x0040  /* DRC_ACTDET_EINT */
+#define WM8962_DRC_ACTDET_EINT_MASK             0x0040  /* DRC_ACTDET_EINT */
+#define WM8962_DRC_ACTDET_EINT_SHIFT                 6  /* DRC_ACTDET_EINT */
+#define WM8962_DRC_ACTDET_EINT_WIDTH                 1  /* DRC_ACTDET_EINT */
+#define WM8962_FLL_LOCK_EINT                    0x0020  /* FLL_LOCK_EINT */
+#define WM8962_FLL_LOCK_EINT_MASK               0x0020  /* FLL_LOCK_EINT */
+#define WM8962_FLL_LOCK_EINT_SHIFT                   5  /* FLL_LOCK_EINT */
+#define WM8962_FLL_LOCK_EINT_WIDTH                   1  /* FLL_LOCK_EINT */
+#define WM8962_PLL3_LOCK_EINT                   0x0008  /* PLL3_LOCK_EINT */
+#define WM8962_PLL3_LOCK_EINT_MASK              0x0008  /* PLL3_LOCK_EINT */
+#define WM8962_PLL3_LOCK_EINT_SHIFT                  3  /* PLL3_LOCK_EINT */
+#define WM8962_PLL3_LOCK_EINT_WIDTH                  1  /* PLL3_LOCK_EINT */
+#define WM8962_PLL2_LOCK_EINT                   0x0004  /* PLL2_LOCK_EINT */
+#define WM8962_PLL2_LOCK_EINT_MASK              0x0004  /* PLL2_LOCK_EINT */
+#define WM8962_PLL2_LOCK_EINT_SHIFT                  2  /* PLL2_LOCK_EINT */
+#define WM8962_PLL2_LOCK_EINT_WIDTH                  1  /* PLL2_LOCK_EINT */
+#define WM8962_TEMP_SHUT_EINT                   0x0001  /* TEMP_SHUT_EINT */
+#define WM8962_TEMP_SHUT_EINT_MASK              0x0001  /* TEMP_SHUT_EINT */
+#define WM8962_TEMP_SHUT_EINT_SHIFT                  0  /* TEMP_SHUT_EINT */
+#define WM8962_TEMP_SHUT_EINT_WIDTH                  1  /* TEMP_SHUT_EINT */
+
+/*
+ * R568 (0x238) - Interrupt Status 1 Mask
+ */
+#define WM8962_IM_GP6_EINT                      0x0020  /* IM_GP6_EINT */
+#define WM8962_IM_GP6_EINT_MASK                 0x0020  /* IM_GP6_EINT */
+#define WM8962_IM_GP6_EINT_SHIFT                     5  /* IM_GP6_EINT */
+#define WM8962_IM_GP6_EINT_WIDTH                     1  /* IM_GP6_EINT */
+#define WM8962_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
+#define WM8962_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
+#define WM8962_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
+#define WM8962_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
+
+/*
+ * R569 (0x239) - Interrupt Status 2 Mask
+ */
+#define WM8962_IM_MICSCD_EINT                   0x8000  /* IM_MICSCD_EINT */
+#define WM8962_IM_MICSCD_EINT_MASK              0x8000  /* IM_MICSCD_EINT */
+#define WM8962_IM_MICSCD_EINT_SHIFT                 15  /* IM_MICSCD_EINT */
+#define WM8962_IM_MICSCD_EINT_WIDTH                  1  /* IM_MICSCD_EINT */
+#define WM8962_IM_MICD_EINT                     0x4000  /* IM_MICD_EINT */
+#define WM8962_IM_MICD_EINT_MASK                0x4000  /* IM_MICD_EINT */
+#define WM8962_IM_MICD_EINT_SHIFT                   14  /* IM_MICD_EINT */
+#define WM8962_IM_MICD_EINT_WIDTH                    1  /* IM_MICD_EINT */
+#define WM8962_IM_FIFOS_ERR_EINT                0x2000  /* IM_FIFOS_ERR_EINT */
+#define WM8962_IM_FIFOS_ERR_EINT_MASK           0x2000  /* IM_FIFOS_ERR_EINT */
+#define WM8962_IM_FIFOS_ERR_EINT_SHIFT              13  /* IM_FIFOS_ERR_EINT */
+#define WM8962_IM_FIFOS_ERR_EINT_WIDTH               1  /* IM_FIFOS_ERR_EINT */
+#define WM8962_IM_ALC_LOCK_EINT                 0x1000  /* IM_ALC_LOCK_EINT */
+#define WM8962_IM_ALC_LOCK_EINT_MASK            0x1000  /* IM_ALC_LOCK_EINT */
+#define WM8962_IM_ALC_LOCK_EINT_SHIFT               12  /* IM_ALC_LOCK_EINT */
+#define WM8962_IM_ALC_LOCK_EINT_WIDTH                1  /* IM_ALC_LOCK_EINT */
+#define WM8962_IM_ALC_THRESH_EINT               0x0800  /* IM_ALC_THRESH_EINT */
+#define WM8962_IM_ALC_THRESH_EINT_MASK          0x0800  /* IM_ALC_THRESH_EINT */
+#define WM8962_IM_ALC_THRESH_EINT_SHIFT             11  /* IM_ALC_THRESH_EINT */
+#define WM8962_IM_ALC_THRESH_EINT_WIDTH              1  /* IM_ALC_THRESH_EINT */
+#define WM8962_IM_ALC_SAT_EINT                  0x0400  /* IM_ALC_SAT_EINT */
+#define WM8962_IM_ALC_SAT_EINT_MASK             0x0400  /* IM_ALC_SAT_EINT */
+#define WM8962_IM_ALC_SAT_EINT_SHIFT                10  /* IM_ALC_SAT_EINT */
+#define WM8962_IM_ALC_SAT_EINT_WIDTH                 1  /* IM_ALC_SAT_EINT */
+#define WM8962_IM_ALC_PKOVR_EINT                0x0200  /* IM_ALC_PKOVR_EINT */
+#define WM8962_IM_ALC_PKOVR_EINT_MASK           0x0200  /* IM_ALC_PKOVR_EINT */
+#define WM8962_IM_ALC_PKOVR_EINT_SHIFT               9  /* IM_ALC_PKOVR_EINT */
+#define WM8962_IM_ALC_PKOVR_EINT_WIDTH               1  /* IM_ALC_PKOVR_EINT */
+#define WM8962_IM_ALC_NGATE_EINT                0x0100  /* IM_ALC_NGATE_EINT */
+#define WM8962_IM_ALC_NGATE_EINT_MASK           0x0100  /* IM_ALC_NGATE_EINT */
+#define WM8962_IM_ALC_NGATE_EINT_SHIFT               8  /* IM_ALC_NGATE_EINT */
+#define WM8962_IM_ALC_NGATE_EINT_WIDTH               1  /* IM_ALC_NGATE_EINT */
+#define WM8962_IM_WSEQ_DONE_EINT                0x0080  /* IM_WSEQ_DONE_EINT */
+#define WM8962_IM_WSEQ_DONE_EINT_MASK           0x0080  /* IM_WSEQ_DONE_EINT */
+#define WM8962_IM_WSEQ_DONE_EINT_SHIFT               7  /* IM_WSEQ_DONE_EINT */
+#define WM8962_IM_WSEQ_DONE_EINT_WIDTH               1  /* IM_WSEQ_DONE_EINT */
+#define WM8962_IM_DRC_ACTDET_EINT               0x0040  /* IM_DRC_ACTDET_EINT */
+#define WM8962_IM_DRC_ACTDET_EINT_MASK          0x0040  /* IM_DRC_ACTDET_EINT */
+#define WM8962_IM_DRC_ACTDET_EINT_SHIFT              6  /* IM_DRC_ACTDET_EINT */
+#define WM8962_IM_DRC_ACTDET_EINT_WIDTH              1  /* IM_DRC_ACTDET_EINT */
+#define WM8962_IM_FLL_LOCK_EINT                 0x0020  /* IM_FLL_LOCK_EINT */
+#define WM8962_IM_FLL_LOCK_EINT_MASK            0x0020  /* IM_FLL_LOCK_EINT */
+#define WM8962_IM_FLL_LOCK_EINT_SHIFT                5  /* IM_FLL_LOCK_EINT */
+#define WM8962_IM_FLL_LOCK_EINT_WIDTH                1  /* IM_FLL_LOCK_EINT */
+#define WM8962_IM_PLL3_LOCK_EINT                0x0008  /* IM_PLL3_LOCK_EINT */
+#define WM8962_IM_PLL3_LOCK_EINT_MASK           0x0008  /* IM_PLL3_LOCK_EINT */
+#define WM8962_IM_PLL3_LOCK_EINT_SHIFT               3  /* IM_PLL3_LOCK_EINT */
+#define WM8962_IM_PLL3_LOCK_EINT_WIDTH               1  /* IM_PLL3_LOCK_EINT */
+#define WM8962_IM_PLL2_LOCK_EINT                0x0004  /* IM_PLL2_LOCK_EINT */
+#define WM8962_IM_PLL2_LOCK_EINT_MASK           0x0004  /* IM_PLL2_LOCK_EINT */
+#define WM8962_IM_PLL2_LOCK_EINT_SHIFT               2  /* IM_PLL2_LOCK_EINT */
+#define WM8962_IM_PLL2_LOCK_EINT_WIDTH               1  /* IM_PLL2_LOCK_EINT */
+#define WM8962_IM_TEMP_SHUT_EINT                0x0001  /* IM_TEMP_SHUT_EINT */
+#define WM8962_IM_TEMP_SHUT_EINT_MASK           0x0001  /* IM_TEMP_SHUT_EINT */
+#define WM8962_IM_TEMP_SHUT_EINT_SHIFT               0  /* IM_TEMP_SHUT_EINT */
+#define WM8962_IM_TEMP_SHUT_EINT_WIDTH               1  /* IM_TEMP_SHUT_EINT */
+
+/*
+ * R576 (0x240) - Interrupt Control
+ */
+#define WM8962_IRQ_POL                          0x0001  /* IRQ_POL */
+#define WM8962_IRQ_POL_MASK                     0x0001  /* IRQ_POL */
+#define WM8962_IRQ_POL_SHIFT                         0  /* IRQ_POL */
+#define WM8962_IRQ_POL_WIDTH                         1  /* IRQ_POL */
+
+/*
+ * R584 (0x248) - IRQ Debounce
+ */
+#define WM8962_FLL_LOCK_DB                      0x0020  /* FLL_LOCK_DB */
+#define WM8962_FLL_LOCK_DB_MASK                 0x0020  /* FLL_LOCK_DB */
+#define WM8962_FLL_LOCK_DB_SHIFT                     5  /* FLL_LOCK_DB */
+#define WM8962_FLL_LOCK_DB_WIDTH                     1  /* FLL_LOCK_DB */
+#define WM8962_PLL3_LOCK_DB                     0x0008  /* PLL3_LOCK_DB */
+#define WM8962_PLL3_LOCK_DB_MASK                0x0008  /* PLL3_LOCK_DB */
+#define WM8962_PLL3_LOCK_DB_SHIFT                    3  /* PLL3_LOCK_DB */
+#define WM8962_PLL3_LOCK_DB_WIDTH                    1  /* PLL3_LOCK_DB */
+#define WM8962_PLL2_LOCK_DB                     0x0004  /* PLL2_LOCK_DB */
+#define WM8962_PLL2_LOCK_DB_MASK                0x0004  /* PLL2_LOCK_DB */
+#define WM8962_PLL2_LOCK_DB_SHIFT                    2  /* PLL2_LOCK_DB */
+#define WM8962_PLL2_LOCK_DB_WIDTH                    1  /* PLL2_LOCK_DB */
+#define WM8962_TEMP_SHUT_DB                     0x0001  /* TEMP_SHUT_DB */
+#define WM8962_TEMP_SHUT_DB_MASK                0x0001  /* TEMP_SHUT_DB */
+#define WM8962_TEMP_SHUT_DB_SHIFT                    0  /* TEMP_SHUT_DB */
+#define WM8962_TEMP_SHUT_DB_WIDTH                    1  /* TEMP_SHUT_DB */
+
+/*
+ * R586 (0x24A) -  MICINT Source Pol
+ */
+#define WM8962_MICSCD_IRQ_POL                   0x8000  /* MICSCD_IRQ_POL */
+#define WM8962_MICSCD_IRQ_POL_MASK              0x8000  /* MICSCD_IRQ_POL */
+#define WM8962_MICSCD_IRQ_POL_SHIFT                 15  /* MICSCD_IRQ_POL */
+#define WM8962_MICSCD_IRQ_POL_WIDTH                  1  /* MICSCD_IRQ_POL */
+#define WM8962_MICD_IRQ_POL                     0x4000  /* MICD_IRQ_POL */
+#define WM8962_MICD_IRQ_POL_MASK                0x4000  /* MICD_IRQ_POL */
+#define WM8962_MICD_IRQ_POL_SHIFT                   14  /* MICD_IRQ_POL */
+#define WM8962_MICD_IRQ_POL_WIDTH                    1  /* MICD_IRQ_POL */
+
+/*
+ * R768 (0x300) - DSP2 Power Management
+ */
+#define WM8962_DSP2_ENA                         0x0001  /* DSP2_ENA */
+#define WM8962_DSP2_ENA_MASK                    0x0001  /* DSP2_ENA */
+#define WM8962_DSP2_ENA_SHIFT                        0  /* DSP2_ENA */
+#define WM8962_DSP2_ENA_WIDTH                        1  /* DSP2_ENA */
+
+/*
+ * R1037 (0x40D) - DSP2_ExecControl
+ */
+#define WM8962_DSP2_STOPC                       0x0020  /* DSP2_STOPC */
+#define WM8962_DSP2_STOPC_MASK                  0x0020  /* DSP2_STOPC */
+#define WM8962_DSP2_STOPC_SHIFT                      5  /* DSP2_STOPC */
+#define WM8962_DSP2_STOPC_WIDTH                      1  /* DSP2_STOPC */
+#define WM8962_DSP2_STOPS                       0x0010  /* DSP2_STOPS */
+#define WM8962_DSP2_STOPS_MASK                  0x0010  /* DSP2_STOPS */
+#define WM8962_DSP2_STOPS_SHIFT                      4  /* DSP2_STOPS */
+#define WM8962_DSP2_STOPS_WIDTH                      1  /* DSP2_STOPS */
+#define WM8962_DSP2_STOPI                       0x0008  /* DSP2_STOPI */
+#define WM8962_DSP2_STOPI_MASK                  0x0008  /* DSP2_STOPI */
+#define WM8962_DSP2_STOPI_SHIFT                      3  /* DSP2_STOPI */
+#define WM8962_DSP2_STOPI_WIDTH                      1  /* DSP2_STOPI */
+#define WM8962_DSP2_STOP                        0x0004  /* DSP2_STOP */
+#define WM8962_DSP2_STOP_MASK                   0x0004  /* DSP2_STOP */
+#define WM8962_DSP2_STOP_SHIFT                       2  /* DSP2_STOP */
+#define WM8962_DSP2_STOP_WIDTH                       1  /* DSP2_STOP */
+#define WM8962_DSP2_RUNR                        0x0002  /* DSP2_RUNR */
+#define WM8962_DSP2_RUNR_MASK                   0x0002  /* DSP2_RUNR */
+#define WM8962_DSP2_RUNR_SHIFT                       1  /* DSP2_RUNR */
+#define WM8962_DSP2_RUNR_WIDTH                       1  /* DSP2_RUNR */
+#define WM8962_DSP2_RUN                         0x0001  /* DSP2_RUN */
+#define WM8962_DSP2_RUN_MASK                    0x0001  /* DSP2_RUN */
+#define WM8962_DSP2_RUN_SHIFT                        0  /* DSP2_RUN */
+#define WM8962_DSP2_RUN_WIDTH                        1  /* DSP2_RUN */
+
+/*
+ * R8192 (0x2000) - DSP2 Instruction RAM 0
+ */
+#define WM8962_DSP2_INSTR_RAM_1024_10_9_0_MASK  0x03FF  /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */
+#define WM8962_DSP2_INSTR_RAM_1024_10_9_0_SHIFT      0  /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */
+#define WM8962_DSP2_INSTR_RAM_1024_10_9_0_WIDTH     10  /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */
+
+/*
+ * R9216 (0x2400) - DSP2 Address RAM 2
+ */
+#define WM8962_DSP2_ADDR_RAM_1024_38_37_32_MASK 0x003F  /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */
+#define WM8962_DSP2_ADDR_RAM_1024_38_37_32_SHIFT      0  /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */
+#define WM8962_DSP2_ADDR_RAM_1024_38_37_32_WIDTH      6  /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */
+
+/*
+ * R9217 (0x2401) - DSP2 Address RAM 1
+ */
+#define WM8962_DSP2_ADDR_RAM_1024_38_31_16_MASK 0xFFFF  /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */
+#define WM8962_DSP2_ADDR_RAM_1024_38_31_16_SHIFT      0  /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */
+#define WM8962_DSP2_ADDR_RAM_1024_38_31_16_WIDTH     16  /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */
+
+/*
+ * R9218 (0x2402) - DSP2 Address RAM 0
+ */
+#define WM8962_DSP2_ADDR_RAM_1024_38_15_0_MASK  0xFFFF  /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */
+#define WM8962_DSP2_ADDR_RAM_1024_38_15_0_SHIFT      0  /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */
+#define WM8962_DSP2_ADDR_RAM_1024_38_15_0_WIDTH     16  /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */
+
+/*
+ * R12288 (0x3000) - DSP2 Data1 RAM 1
+ */
+#define WM8962_DSP2_DATA1_RAM_384_24_23_16_MASK 0x00FF  /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */
+#define WM8962_DSP2_DATA1_RAM_384_24_23_16_SHIFT      0  /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */
+#define WM8962_DSP2_DATA1_RAM_384_24_23_16_WIDTH      8  /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */
+
+/*
+ * R12289 (0x3001) - DSP2 Data1 RAM 0
+ */
+#define WM8962_DSP2_DATA1_RAM_384_24_15_0_MASK  0xFFFF  /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */
+#define WM8962_DSP2_DATA1_RAM_384_24_15_0_SHIFT      0  /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */
+#define WM8962_DSP2_DATA1_RAM_384_24_15_0_WIDTH     16  /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */
+
+/*
+ * R13312 (0x3400) - DSP2 Data2 RAM 1
+ */
+#define WM8962_DSP2_DATA2_RAM_384_24_23_16_MASK 0x00FF  /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */
+#define WM8962_DSP2_DATA2_RAM_384_24_23_16_SHIFT      0  /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */
+#define WM8962_DSP2_DATA2_RAM_384_24_23_16_WIDTH      8  /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */
+
+/*
+ * R13313 (0x3401) - DSP2 Data2 RAM 0
+ */
+#define WM8962_DSP2_DATA2_RAM_384_24_15_0_MASK  0xFFFF  /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */
+#define WM8962_DSP2_DATA2_RAM_384_24_15_0_SHIFT      0  /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */
+#define WM8962_DSP2_DATA2_RAM_384_24_15_0_WIDTH     16  /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */
+
+/*
+ * R14336 (0x3800) - DSP2 Data3 RAM 1
+ */
+#define WM8962_DSP2_DATA3_RAM_384_24_23_16_MASK 0x00FF  /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */
+#define WM8962_DSP2_DATA3_RAM_384_24_23_16_SHIFT      0  /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */
+#define WM8962_DSP2_DATA3_RAM_384_24_23_16_WIDTH      8  /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */
+
+/*
+ * R14337 (0x3801) - DSP2 Data3 RAM 0
+ */
+#define WM8962_DSP2_DATA3_RAM_384_24_15_0_MASK  0xFFFF  /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */
+#define WM8962_DSP2_DATA3_RAM_384_24_15_0_SHIFT      0  /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */
+#define WM8962_DSP2_DATA3_RAM_384_24_15_0_WIDTH     16  /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */
+
+/*
+ * R15360 (0x3C00) - DSP2 Coeff RAM 0
+ */
+#define WM8962_DSP2_CMAP_RAM_384_11_10_0_MASK   0x07FF  /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */
+#define WM8962_DSP2_CMAP_RAM_384_11_10_0_SHIFT       0  /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */
+#define WM8962_DSP2_CMAP_RAM_384_11_10_0_WIDTH      11  /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */
+
+/*
+ * R16384 (0x4000) - RETUNEADC_SHARED_COEFF_1
+ */
+#define WM8962_ADC_RETUNE_SCV                   0x0080  /* ADC_RETUNE_SCV */
+#define WM8962_ADC_RETUNE_SCV_MASK              0x0080  /* ADC_RETUNE_SCV */
+#define WM8962_ADC_RETUNE_SCV_SHIFT                  7  /* ADC_RETUNE_SCV */
+#define WM8962_ADC_RETUNE_SCV_WIDTH                  1  /* ADC_RETUNE_SCV */
+#define WM8962_RETUNEADC_SHARED_COEFF_22_16_MASK 0x007F  /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */
+#define WM8962_RETUNEADC_SHARED_COEFF_22_16_SHIFT      0  /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */
+#define WM8962_RETUNEADC_SHARED_COEFF_22_16_WIDTH      7  /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */
+
+/*
+ * R16385 (0x4001) - RETUNEADC_SHARED_COEFF_0
+ */
+#define WM8962_RETUNEADC_SHARED_COEFF_15_00_MASK 0xFFFF  /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */
+#define WM8962_RETUNEADC_SHARED_COEFF_15_00_SHIFT      0  /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */
+#define WM8962_RETUNEADC_SHARED_COEFF_15_00_WIDTH     16  /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */
+
+/*
+ * R16386 (0x4002) - RETUNEDAC_SHARED_COEFF_1
+ */
+#define WM8962_DAC_RETUNE_SCV                   0x0080  /* DAC_RETUNE_SCV */
+#define WM8962_DAC_RETUNE_SCV_MASK              0x0080  /* DAC_RETUNE_SCV */
+#define WM8962_DAC_RETUNE_SCV_SHIFT                  7  /* DAC_RETUNE_SCV */
+#define WM8962_DAC_RETUNE_SCV_WIDTH                  1  /* DAC_RETUNE_SCV */
+#define WM8962_RETUNEDAC_SHARED_COEFF_23_16_MASK 0x007F  /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */
+#define WM8962_RETUNEDAC_SHARED_COEFF_23_16_SHIFT      0  /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */
+#define WM8962_RETUNEDAC_SHARED_COEFF_23_16_WIDTH      7  /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */
+
+/*
+ * R16387 (0x4003) - RETUNEDAC_SHARED_COEFF_0
+ */
+#define WM8962_RETUNEDAC_SHARED_COEFF_15_00_MASK 0xFFFF  /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */
+#define WM8962_RETUNEDAC_SHARED_COEFF_15_00_SHIFT      0  /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */
+#define WM8962_RETUNEDAC_SHARED_COEFF_15_00_WIDTH     16  /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */
+
+/*
+ * R16388 (0x4004) - SOUNDSTAGE_ENABLES_1
+ */
+#define WM8962_SOUNDSTAGE_ENABLES_23_16_MASK    0x00FF  /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */
+#define WM8962_SOUNDSTAGE_ENABLES_23_16_SHIFT        0  /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */
+#define WM8962_SOUNDSTAGE_ENABLES_23_16_WIDTH        8  /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */
+
+/*
+ * R16389 (0x4005) - SOUNDSTAGE_ENABLES_0
+ */
+#define WM8962_SOUNDSTAGE_ENABLES_15_06_MASK    0xFFC0  /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */
+#define WM8962_SOUNDSTAGE_ENABLES_15_06_SHIFT        6  /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */
+#define WM8962_SOUNDSTAGE_ENABLES_15_06_WIDTH       10  /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */
+#define WM8962_RTN_ADC_ENA                      0x0020  /* RTN_ADC_ENA */
+#define WM8962_RTN_ADC_ENA_MASK                 0x0020  /* RTN_ADC_ENA */
+#define WM8962_RTN_ADC_ENA_SHIFT                     5  /* RTN_ADC_ENA */
+#define WM8962_RTN_ADC_ENA_WIDTH                     1  /* RTN_ADC_ENA */
+#define WM8962_RTN_DAC_ENA                      0x0010  /* RTN_DAC_ENA */
+#define WM8962_RTN_DAC_ENA_MASK                 0x0010  /* RTN_DAC_ENA */
+#define WM8962_RTN_DAC_ENA_SHIFT                     4  /* RTN_DAC_ENA */
+#define WM8962_RTN_DAC_ENA_WIDTH                     1  /* RTN_DAC_ENA */
+#define WM8962_HDBASS_ENA                       0x0008  /* HDBASS_ENA */
+#define WM8962_HDBASS_ENA_MASK                  0x0008  /* HDBASS_ENA */
+#define WM8962_HDBASS_ENA_SHIFT                      3  /* HDBASS_ENA */
+#define WM8962_HDBASS_ENA_WIDTH                      1  /* HDBASS_ENA */
+#define WM8962_HPF2_ENA                         0x0004  /* HPF2_ENA */
+#define WM8962_HPF2_ENA_MASK                    0x0004  /* HPF2_ENA */
+#define WM8962_HPF2_ENA_SHIFT                        2  /* HPF2_ENA */
+#define WM8962_HPF2_ENA_WIDTH                        1  /* HPF2_ENA */
+#define WM8962_HPF1_ENA                         0x0002  /* HPF1_ENA */
+#define WM8962_HPF1_ENA_MASK                    0x0002  /* HPF1_ENA */
+#define WM8962_HPF1_ENA_SHIFT                        1  /* HPF1_ENA */
+#define WM8962_HPF1_ENA_WIDTH                        1  /* HPF1_ENA */
+#define WM8962_VSS_ENA                          0x0001  /* VSS_ENA */
+#define WM8962_VSS_ENA_MASK                     0x0001  /* VSS_ENA */
+#define WM8962_VSS_ENA_SHIFT                         0  /* VSS_ENA */
+#define WM8962_VSS_ENA_WIDTH                         1  /* VSS_ENA */
+
+int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+#endif
diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c
index a99620f335d2..572bb80627a4 100644
--- a/sound/soc/codecs/wm8971.c
+++ b/sound/soc/codecs/wm8971.c
@@ -25,19 +25,17 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 
 #include "wm8971.h"
 
-#define WM8971_VERSION "0.9"
-
 #define WM8971_REG_COUNT                43
 
 static struct workqueue_struct *wm8971_workq = NULL;
 
 /* codec private data */
 struct wm8971_priv {
+        enum snd_soc_control_type control_type;
         unsigned int sysclk;
 };
 
@@ -334,10 +332,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8971_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8971_dapm_widgets,
-                                  ARRAY_SIZE(wm8971_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, wm8971_dapm_widgets,
+                                  ARRAY_SIZE(wm8971_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -492,8 +491,7 @@ static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec);
         u16 iface = snd_soc_read(codec, WM8971_IFACE) & 0x1f3;
         u16 srate = snd_soc_read(codec, WM8971_SRATE) & 0x1c0;
@@ -555,7 +553,7 @@ static int wm8971_set_bias_level(struct snd_soc_codec *codec,
                 snd_soc_write(codec, WM8971_PWR1, 0x0001);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -573,8 +571,8 @@ static struct snd_soc_dai_ops wm8971_dai_ops = {
         .set_sysclk     = wm8971_set_dai_sysclk,
 };
 
-struct snd_soc_dai wm8971_dai = {
-        .name = "WM8971",
+static struct snd_soc_dai_driver wm8971_dai = {
+        .name = "wm8971-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -589,28 +587,24 @@ struct snd_soc_dai wm8971_dai = {
                 .formats = WM8971_FORMATS,},
         .ops = &wm8971_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8971_dai);
 
 static void wm8971_work(struct work_struct *work)
 {
-        struct snd_soc_codec *codec =
-                container_of(work, struct snd_soc_codec, delayed_work.work);
-        wm8971_set_bias_level(codec, codec->bias_level);
+        struct snd_soc_dapm_context *dapm =
+                container_of(work, struct snd_soc_dapm_context,
+                             delayed_work.work);
+        struct snd_soc_codec *codec = dapm->codec;
+        wm8971_set_bias_level(codec, codec->dapm.bias_level);
 }
 
-static int wm8971_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8971_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8971_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8971_resume(struct platform_device *pdev)
+static int wm8971_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -628,54 +622,41 @@ static int wm8971_resume(struct platform_device *pdev)
         wm8971_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         /* charge wm8971 caps */
-        if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
+        if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) {
                 reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
                 snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0);
-                codec->bias_level = SND_SOC_BIAS_ON;
-                queue_delayed_work(wm8971_workq, &codec->delayed_work,
+                codec->dapm.bias_level = SND_SOC_BIAS_ON;
+                queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work,
                         msecs_to_jiffies(1000));
         }
 
         return 0;
 }
 
-static int wm8971_init(struct snd_soc_device *socdev,
-                       enum snd_soc_control_type control)
+static int wm8971_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = socdev->card->codec;
-        int reg, ret = 0;
-
-        codec->name = "WM8971";
-        codec->owner = THIS_MODULE;
-        codec->set_bias_level = wm8971_set_bias_level;
-        codec->dai = &wm8971_dai;
-        codec->reg_cache_size = ARRAY_SIZE(wm8971_reg);
-        codec->num_dai = 1;
-        codec->reg_cache = kmemdup(wm8971_reg, sizeof(wm8971_reg), GFP_KERNEL);
-
-        if (codec->reg_cache == NULL)
-                return -ENOMEM;
+        struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec);
+        int ret = 0;
+        u16 reg;
 
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8971->control_type);
         if (ret < 0) {
                 printk(KERN_ERR "wm8971: failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
-        wm8971_reset(codec);
+        INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8971_work);
+        wm8971_workq = create_workqueue("wm8971");
+        if (wm8971_workq == NULL)
+                return -ENOMEM;
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "wm8971: failed to create pcms\n");
-                goto err;
-        }
+        wm8971_reset(codec);
 
         /* charge output caps - set vmid to 5k for quick power up */
         reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
         snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0);
-        codec->bias_level = SND_SOC_BIAS_STANDBY;
-        queue_delayed_work(wm8971_workq, &codec->delayed_work,
+        codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
+        queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work,
                 msecs_to_jiffies(1000));
 
         /* set the update bits */
@@ -704,40 +685,55 @@ static int wm8971_init(struct snd_soc_device *socdev,
         wm8971_add_widgets(codec);
 
         return ret;
-
-err:
-        kfree(codec->reg_cache);
-        return ret;
 }
 
-/* If the i2c layer weren't so broken, we could pass this kind of data
-   around */
-static struct snd_soc_device *wm8971_socdev;
 
-#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
+/* power down chip */
+static int wm8971_remove(struct snd_soc_codec *codec)
+{
+        wm8971_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
-static int wm8971_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+        if (wm8971_workq)
+                destroy_workqueue(wm8971_workq);
+        return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8971 = {
+        .probe =        wm8971_probe,
+        .remove =       wm8971_remove,
+        .suspend =      wm8971_suspend,
+        .resume =       wm8971_resume,
+        .set_bias_level = wm8971_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8971_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8971_reg,
+};
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8971_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
-        struct snd_soc_device *socdev = wm8971_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct wm8971_priv *wm8971;
         int ret;
 
-        i2c_set_clientdata(i2c, codec);
+        wm8971 = kzalloc(sizeof(struct wm8971_priv), GFP_KERNEL);
+        if (wm8971 == NULL)
+                return -ENOMEM;
 
-        codec->control_data = i2c;
+        wm8971->control_type = SND_SOC_I2C;
+        i2c_set_clientdata(i2c, wm8971);
 
-        ret = wm8971_init(socdev, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8971, &wm8971_dai, 1);
         if (ret < 0)
-                pr_err("failed to initialise WM8971\n");
-
+                kfree(wm8971);
         return ret;
 }
 
-static int wm8971_i2c_remove(struct i2c_client *client)
+static __devexit int wm8971_i2c_remove(struct i2c_client *client)
 {
-        struct snd_soc_codec *codec = i2c_get_clientdata(client);
-        kfree(codec->reg_cache);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -749,148 +745,34 @@ MODULE_DEVICE_TABLE(i2c, wm8971_i2c_id);
 
 static struct i2c_driver wm8971_i2c_driver = {
         .driver = {
-                .name = "WM8971 I2C Codec",
+                .name = "wm8971-codec",
                 .owner = THIS_MODULE,
         },
-        .probe    = wm8971_i2c_probe,
-        .remove   = wm8971_i2c_remove,
+        .probe =    wm8971_i2c_probe,
+        .remove =   __devexit_p(wm8971_i2c_remove),
         .id_table = wm8971_i2c_id,
 };
-
-static int wm8971_add_i2c_device(struct platform_device *pdev,
-                                 const struct wm8971_setup_data *setup)
-{
-        struct i2c_board_info info;
-        struct i2c_adapter *adapter;
-        struct i2c_client *client;
-        int ret;
-
-        ret = i2c_add_driver(&wm8971_i2c_driver);
-        if (ret != 0) {
-                dev_err(&pdev->dev, "can't add i2c driver\n");
-                return ret;
-        }
-
-        memset(&info, 0, sizeof(struct i2c_board_info));
-        info.addr = setup->i2c_address;
-        strlcpy(info.type, "wm8971", I2C_NAME_SIZE);
-
-        adapter = i2c_get_adapter(setup->i2c_bus);
-        if (!adapter) {
-                dev_err(&pdev->dev, "can't get i2c adapter %d\n",
-                        setup->i2c_bus);
-                goto err_driver;
-        }
-
-        client = i2c_new_device(adapter, &info);
-        i2c_put_adapter(adapter);
-        if (!client) {
-                dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
-                        (unsigned int)info.addr);
-                goto err_driver;
-        }
-
-        return 0;
-
-err_driver:
-        i2c_del_driver(&wm8971_i2c_driver);
-        return -ENODEV;
-}
-
 #endif
 
-static int wm8971_probe(struct platform_device *pdev)
+static int __init wm8971_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct wm8971_setup_data *setup;
-        struct snd_soc_codec *codec;
-        struct wm8971_priv *wm8971;
         int ret = 0;
-
-        pr_info("WM8971 Audio Codec %s", WM8971_VERSION);
-
-        setup = socdev->codec_data;
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-
-        wm8971 = kzalloc(sizeof(struct wm8971_priv), GFP_KERNEL);
-        if (wm8971 == NULL) {
-                kfree(codec);
-                return -ENOMEM;
-        }
-
-        snd_soc_codec_set_drvdata(codec, wm8971);
-        socdev->card->codec = codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-        wm8971_socdev = socdev;
-
-        INIT_DELAYED_WORK(&codec->delayed_work, wm8971_work);
-        wm8971_workq = create_workqueue("wm8971");
-        if (wm8971_workq == NULL) {
-                kfree(snd_soc_codec_get_drvdata(codec));
-                kfree(codec);
-                return -ENOMEM;
-        }
-
-#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
-        if (setup->i2c_address) {
-                ret = wm8971_add_i2c_device(pdev, setup);
-        }
-#endif
-        /* Add other interfaces here */
-
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8971_i2c_driver);
         if (ret != 0) {
-                destroy_workqueue(wm8971_workq);
-                kfree(snd_soc_codec_get_drvdata(codec));
-                kfree(codec);
+                printk(KERN_ERR "Failed to register WM8971 I2C driver: %d\n",
+                       ret);
         }
-
-        return ret;
-}
-
-/* power down chip */
-static int wm8971_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec->control_data)
-                wm8971_set_bias_level(codec, SND_SOC_BIAS_OFF);
-        if (wm8971_workq)
-                destroy_workqueue(wm8971_workq);
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
-        i2c_unregister_device(codec->control_data);
-        i2c_del_driver(&wm8971_i2c_driver);
 #endif
-        kfree(snd_soc_codec_get_drvdata(codec));
-        kfree(codec);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8971 = {
-        .probe =        wm8971_probe,
-        .remove =       wm8971_remove,
-        .suspend =      wm8971_suspend,
-        .resume =       wm8971_resume,
-};
-
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8971);
-
-static int __init wm8971_modinit(void)
-{
-        return snd_soc_register_dai(&wm8971_dai);
+        return ret;
 }
 module_init(wm8971_modinit);
 
 static void __exit wm8971_exit(void)
 {
-        snd_soc_unregister_dai(&wm8971_dai);
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&wm8971_i2c_driver);
+#endif
 }
 module_exit(wm8971_exit);
 
diff --git a/sound/soc/codecs/wm8971.h b/sound/soc/codecs/wm8971.h
index ef4f08f9f344..f31c38fddfc4 100644
--- a/sound/soc/codecs/wm8971.h
+++ b/sound/soc/codecs/wm8971.h
@@ -53,12 +53,4 @@
 
 #define WM8971_SYSCLK   0
 
-struct wm8971_setup_data {
-        int i2c_bus;
-        unsigned short i2c_address;
-};
-
-extern struct snd_soc_dai wm8971_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8971;
-
 #endif
diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c
index 1468fe10cbbe..ca646a822444 100644
--- a/sound/soc/codecs/wm8974.c
+++ b/sound/soc/codecs/wm8974.c
@@ -23,7 +23,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
@@ -51,12 +50,9 @@ static const u16 wm8974_reg[WM8974_CACHEREGNUM] = {
 #define WM8974_POWER1_BUFIOEN 0x04
 
 struct wm8974_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM8974_CACHEREGNUM];
+        enum snd_soc_control_type control_type;
 };
 
-static struct snd_soc_codec *wm8974_codec;
-
 #define wm8974_reset(c) snd_soc_write(c, WM8974_RESET, 0)
 
 static const char *wm8974_companding[] = {"Off", "NC", "u-law", "A-law" };
@@ -276,10 +272,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8974_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8974_dapm_widgets,
-                                  ARRAY_SIZE(wm8974_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_new_controls(dapm, wm8974_dapm_widgets,
+                                  ARRAY_SIZE(wm8974_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -532,7 +529,7 @@ static int wm8974_set_bias_level(struct snd_soc_codec *codec,
         case SND_SOC_BIAS_STANDBY:
                 power1 |= WM8974_POWER1_BIASEN | WM8974_POWER1_BUFIOEN;
 
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Initial cap charge at VMID 5k */
                         snd_soc_write(codec, WM8974_POWER1, power1 | 0x3);
                         mdelay(100);
@@ -549,7 +546,7 @@ static int wm8974_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -566,8 +563,8 @@ static struct snd_soc_dai_ops wm8974_ops = {
         .set_pll = wm8974_set_dai_pll,
 };
 
-struct snd_soc_dai wm8974_dai = {
-        .name = "WM8974 HiFi",
+static struct snd_soc_dai_driver wm8974_dai = {
+        .name = "wm8974-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -583,21 +580,15 @@ struct snd_soc_dai wm8974_dai = {
         .ops = &wm8974_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8974_dai);
 
-static int wm8974_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8974_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8974_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8974_resume(struct platform_device *pdev)
+static int wm8974_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -613,156 +604,72 @@ static int wm8974_resume(struct platform_device *pdev)
         return 0;
 }
 
-static int wm8974_probe(struct platform_device *pdev)
+static int wm8974_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
         int ret = 0;
 
-        if (wm8974_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
-        socdev->card->codec = wm8974_codec;
-        codec = wm8974_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+        ret = wm8974_reset(codec);
         if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
+                dev_err(codec->dev, "Failed to issue reset\n");
+                return ret;
         }
 
+        wm8974_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         snd_soc_add_controls(codec, wm8974_snd_controls,
                              ARRAY_SIZE(wm8974_snd_controls));
         wm8974_add_widgets(codec);
 
         return ret;
-
-pcm_err:
-        return ret;
 }
 
 /* power down chip */
-static int wm8974_remove(struct platform_device *pdev)
+static int wm8974_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
+        wm8974_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_wm8974 = {
+static struct snd_soc_codec_driver soc_codec_dev_wm8974 = {
         .probe =        wm8974_probe,
         .remove =       wm8974_remove,
         .suspend =      wm8974_suspend,
         .resume =       wm8974_resume,
+        .set_bias_level = wm8974_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8974_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8974_reg,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8974);
-
-static __devinit int wm8974_register(struct wm8974_priv *wm8974)
-{
-        int ret;
-        struct snd_soc_codec *codec = &wm8974->codec;
-
-        if (wm8974_codec) {
-                dev_err(codec->dev, "Another WM8974 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8974);
-        codec->name = "WM8974";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8974_set_bias_level;
-        codec->dai = &wm8974_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8974_CACHEREGNUM;
-        codec->reg_cache = &wm8974->reg_cache;
-
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
-        }
-
-        memcpy(codec->reg_cache, wm8974_reg, sizeof(wm8974_reg));
-
-        ret = wm8974_reset(codec);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to issue reset\n");
-                goto err;
-        }
-
-        wm8974_dai.dev = codec->dev;
-
-        wm8974_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-
-        wm8974_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&wm8974_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
-
-        return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8974);
-        return ret;
-}
-
-static __devexit void wm8974_unregister(struct wm8974_priv *wm8974)
-{
-        wm8974_set_bias_level(&wm8974->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm8974_dai);
-        snd_soc_unregister_codec(&wm8974->codec);
-        kfree(wm8974);
-        wm8974_codec = NULL;
-}
 
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int wm8974_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm8974_priv *wm8974;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8974 = kzalloc(sizeof(struct wm8974_priv), GFP_KERNEL);
         if (wm8974 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8974->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
         i2c_set_clientdata(i2c, wm8974);
-        codec->control_data = i2c;
-
-        codec->dev = &i2c->dev;
 
-        return wm8974_register(wm8974);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8974, &wm8974_dai, 1);
+        if (ret < 0)
+                kfree(wm8974);
+        return ret;
 }
 
 static __devexit int wm8974_i2c_remove(struct i2c_client *client)
 {
-        struct wm8974_priv *wm8974 = i2c_get_clientdata(client);
-        wm8974_unregister(wm8974);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -774,23 +681,34 @@ MODULE_DEVICE_TABLE(i2c, wm8974_i2c_id);
 
 static struct i2c_driver wm8974_i2c_driver = {
         .driver = {
-                .name = "WM8974",
+                .name = "wm8974-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8974_i2c_probe,
         .remove =   __devexit_p(wm8974_i2c_remove),
         .id_table = wm8974_i2c_id,
 };
+#endif
 
 static int __init wm8974_modinit(void)
 {
-        return i2c_add_driver(&wm8974_i2c_driver);
+        int ret = 0;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8974_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8974 I2C driver: %d\n",
+                       ret);
+        }
+#endif
+        return ret;
 }
 module_init(wm8974_modinit);
 
 static void __exit wm8974_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm8974_i2c_driver);
+#endif
 }
 module_exit(wm8974_exit);
 
diff --git a/sound/soc/codecs/wm8974.h b/sound/soc/codecs/wm8974.h
index 896a7f0f3fc4..3c94e7bb55a6 100644
--- a/sound/soc/codecs/wm8974.h
+++ b/sound/soc/codecs/wm8974.h
@@ -83,7 +83,4 @@
 #define WM8974_MCLKDIV_8        (6 << 5)
 #define WM8974_MCLKDIV_12       (7 << 5)
 
-extern struct snd_soc_dai wm8974_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8974;
-
 #endif
diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c
index 8a1ad778e7e3..85e3e630e763 100644
--- a/sound/soc/codecs/wm8978.c
+++ b/sound/soc/codecs/wm8978.c
@@ -24,15 +24,12 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 #include <asm/div64.h>
 
 #include "wm8978.h"
 
-static struct snd_soc_codec *wm8978_codec;
-
 /* wm8978 register cache. Note that register 0 is not included in the cache. */
 static const u16 wm8978_reg[WM8978_CACHEREGNUM] = {
         0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */
@@ -54,14 +51,14 @@ static const u16 wm8978_reg[WM8978_CACHEREGNUM] = {
 
 /* codec private data */
 struct wm8978_priv {
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
+        void *control_data;
         unsigned int f_pllout;
         unsigned int f_mclk;
         unsigned int f_256fs;
         unsigned int f_opclk;
         int mclk_idx;
         enum wm8978_sysclk_src sysclk;
-        u16 reg_cache[WM8978_CACHEREGNUM];
 };
 
 static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
@@ -96,6 +93,7 @@ static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
+static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
 
 static const struct snd_kcontrol_new wm8978_snd_controls[] = {
 
@@ -147,19 +145,19 @@ static const struct snd_kcontrol_new wm8978_snd_controls[] = {
 
         SOC_SINGLE("DAC Playback Limiter Threshold",
                 WM8978_DAC_LIMITER_2, 4, 7, 0),
-        SOC_SINGLE("DAC Playback Limiter Boost",
-                WM8978_DAC_LIMITER_2, 0, 15, 0),
+        SOC_SINGLE_TLV("DAC Playback Limiter Volume",
+                WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
 
         SOC_ENUM("ALC Enable Switch", alc1),
         SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
         SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
 
-        SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 7, 0),
+        SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0),
         SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
 
         SOC_ENUM("ALC Capture Mode", alc3),
-        SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 15, 0),
-        SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 15, 0),
+        SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0),
+        SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0),
 
         SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
         SOC_SINGLE("ALC Capture Noise Gate Threshold",
@@ -214,8 +212,10 @@ static const struct snd_kcontrol_new wm8978_snd_controls[] = {
                 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
 
         /* DAC / ADC oversampling */
-        SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0),
-        SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0),
+        SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL,
+                   5, 1, 0),
+        SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL,
+                   5, 1, 0),
 };
 
 /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
@@ -356,11 +356,12 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8978_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8978_dapm_widgets,
-                                  ARRAY_SIZE(wm8978_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
+        snd_soc_dapm_new_controls(dapm, wm8978_dapm_widgets,
+                                  ARRAY_SIZE(wm8978_dapm_widgets));
         /* set up the WM8978 audio map */
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -374,8 +375,8 @@ struct wm8978_pll_div {
 
 #define FIXED_PLL_SIZE (1 << 24)
 
-static void pll_factors(struct wm8978_pll_div *pll_div, unsigned int target,
-                        unsigned int source)
+static void pll_factors(struct snd_soc_codec *codec,
+                struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source)
 {
         u64 k_part;
         unsigned int k, n_div, n_mod;
@@ -390,7 +391,7 @@ static void pll_factors(struct wm8978_pll_div *pll_div, unsigned int target,
         }
 
         if (n_div < 6 || n_div > 12)
-                dev_warn(wm8978_codec->dev,
+                dev_warn(codec->dev,
                          "WM8978 N value exceeds recommended range! N = %u\n",
                          n_div);
 
@@ -505,7 +506,7 @@ static int wm8978_configure_pll(struct snd_soc_codec *codec)
         dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
                 wm8978->f_mclk, wm8978->f_pllout);
 
-        pll_factors(&pll_div, f2, wm8978->f_mclk);
+        pll_factors(codec, &pll_div, f2, wm8978->f_mclk);
 
         dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
                 __func__, pll_div.n, pll_div.k, pll_div.div2);
@@ -690,8 +691,7 @@ static int wm8978_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
         /* Word length mask = 0x60 */
         u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
@@ -839,7 +839,7 @@ static int wm8978_set_bias_level(struct snd_soc_codec *codec,
                 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
                 power1 |= 0xc;
 
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Initial cap charge at VMID 5k */
                         snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
                                       power1 | 0x3);
@@ -859,7 +859,7 @@ static int wm8978_set_bias_level(struct snd_soc_codec *codec,
 
         dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -875,9 +875,8 @@ static struct snd_soc_dai_ops wm8978_dai_ops = {
 };
 
 /* Also supports 12kHz */
-struct snd_soc_dai wm8978_dai = {
-        .name = "WM8978 HiFi",
-        .id = 1,
+static struct snd_soc_dai_driver wm8978_dai = {
+        .name = "wm8978-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -894,13 +893,9 @@ struct snd_soc_dai wm8978_dai = {
         },
         .ops = &wm8978_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8978_dai);
 
-static int wm8978_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8978_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
         /* Also switch PLL off */
         snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0);
@@ -908,10 +903,8 @@ static int wm8978_suspend(struct platform_device *pdev, pm_message_t state)
         return 0;
 }
 
-static int wm8978_resume(struct platform_device *pdev)
+static int wm8978_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
         int i;
         u16 *cache = codec->reg_cache;
@@ -933,54 +926,6 @@ static int wm8978_resume(struct platform_device *pdev)
         return 0;
 }
 
-static int wm8978_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8978_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8978_codec;
-        codec = wm8978_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8978_snd_controls,
-                             ARRAY_SIZE(wm8978_snd_controls));
-        wm8978_add_widgets(codec);
-
-pcm_err:
-        return ret;
-}
-
-/* power down chip */
-static int wm8978_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8978 = {
-        .probe          = wm8978_probe,
-        .remove         = wm8978_remove,
-        .suspend        = wm8978_suspend,
-        .resume         = wm8978_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8978);
-
 /*
  * These registers contain an "update" bit - bit 8. This means, for example,
  * that one can write new DAC digital volume for both channels, but only when
@@ -1000,124 +945,90 @@ static const int update_reg[] = {
         WM8978_ROUT2_SPK_CONTROL,
 };
 
-static __devinit int wm8978_register(struct wm8978_priv *wm8978)
+static int wm8978_probe(struct snd_soc_codec *codec)
 {
-        int ret, i;
-        struct snd_soc_codec *codec = &wm8978->codec;
-
-        if (wm8978_codec) {
-                dev_err(codec->dev, "Another WM8978 is registered\n");
-                return -EINVAL;
-        }
+        struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
+        int ret = 0, i;
 
         /*
          * Set default system clock to PLL, it is more precise, this is also the
          * default hardware setting
          */
         wm8978->sysclk = WM8978_PLL;
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8978);
-        codec->name = "WM8978";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8978_set_bias_level;
-        codec->dai = &wm8978_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = WM8978_CACHEREGNUM;
-        codec->reg_cache = &wm8978->reg_cache;
-
+        codec->control_data = wm8978->control_data;
         ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
-        memcpy(codec->reg_cache, wm8978_reg, sizeof(wm8978_reg));
-
         /*
          * Set the update bit in all registers, that have one. This way all
          * writes to those registers will also cause the update bit to be
          * written.
          */
         for (i = 0; i < ARRAY_SIZE(update_reg); i++)
-                ((u16 *)codec->reg_cache)[update_reg[i]] |= 0x100;
+                snd_soc_update_bits(codec, update_reg[i], 0x100, 0x100);
 
         /* Reset the codec */
         ret = snd_soc_write(codec, WM8978_RESET, 0);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to issue reset\n");
-                goto err;
+                return ret;
         }
 
-        wm8978_dai.dev = codec->dev;
-
         wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
-        wm8978_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&wm8978_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+        snd_soc_add_controls(codec, wm8978_snd_controls,
+                             ARRAY_SIZE(wm8978_snd_controls));
+        wm8978_add_widgets(codec);
 
         return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        return ret;
 }
 
-static __devexit void wm8978_unregister(struct wm8978_priv *wm8978)
+/* power down chip */
+static int wm8978_remove(struct snd_soc_codec *codec)
 {
-        wm8978_set_bias_level(&wm8978->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm8978_dai);
-        snd_soc_unregister_codec(&wm8978->codec);
-        wm8978_codec = NULL;
+        wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8978 = {
+        .probe =        wm8978_probe,
+        .remove =       wm8978_remove,
+        .suspend =      wm8978_suspend,
+        .resume =       wm8978_resume,
+        .set_bias_level = wm8978_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8978_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8978_reg,
+};
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int wm8978_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
-        int ret;
         struct wm8978_priv *wm8978;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL);
         if (wm8978 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8978->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-
         i2c_set_clientdata(i2c, wm8978);
-        codec->control_data = i2c;
-
-        codec->dev = &i2c->dev;
+        wm8978->control_data = i2c;
 
-        ret = wm8978_register(wm8978);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8978, &wm8978_dai, 1);
         if (ret < 0)
                 kfree(wm8978);
-
         return ret;
 }
 
 static __devexit int wm8978_i2c_remove(struct i2c_client *client)
 {
-        struct wm8978_priv *wm8978 = i2c_get_clientdata(client);
-        wm8978_unregister(wm8978);
-        kfree(wm8978);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -1129,23 +1040,34 @@ MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
 
 static struct i2c_driver wm8978_i2c_driver = {
         .driver = {
-                .name = "WM8978",
+                .name = "wm8978",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8978_i2c_probe,
         .remove =   __devexit_p(wm8978_i2c_remove),
         .id_table = wm8978_i2c_id,
 };
+#endif
 
 static int __init wm8978_modinit(void)
 {
-        return i2c_add_driver(&wm8978_i2c_driver);
+        int ret = 0;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8978_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8978 I2C driver: %d\n",
+                       ret);
+        }
+#endif
+        return ret;
 }
 module_init(wm8978_modinit);
 
 static void __exit wm8978_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm8978_i2c_driver);
+#endif
 }
 module_exit(wm8978_exit);
 
diff --git a/sound/soc/codecs/wm8978.h b/sound/soc/codecs/wm8978.h
index 56ec83270917..c75525b7f154 100644
--- a/sound/soc/codecs/wm8978.h
+++ b/sound/soc/codecs/wm8978.h
@@ -80,7 +80,4 @@ enum wm8978_sysclk_src {
         WM8978_MCLK
 };
 
-extern struct snd_soc_dai wm8978_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8978;
-
 #endif  /* __WM8978_H__ */
diff --git a/sound/soc/codecs/wm8985.c b/sound/soc/codecs/wm8985.c
new file mode 100644
index 000000000000..bae510acdec8
--- /dev/null
+++ b/sound/soc/codecs/wm8985.c
@@ -0,0 +1,1192 @@
+/*
+ * wm8985.c  --  WM8985 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * TODO:
+ *  o Add OUT3/OUT4 mixer controls.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "wm8985.h"
+
+#define WM8985_NUM_SUPPLIES 4
+static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
+        "DCVDD",
+        "DBVDD",
+        "AVDD1",
+        "AVDD2"
+};
+
+static const u16 wm8985_reg_defs[] = {
+        0x0000,     /* R0  - Software Reset */
+        0x0000,     /* R1  - Power management 1 */
+        0x0000,     /* R2  - Power management 2 */
+        0x0000,     /* R3  - Power management 3 */
+        0x0050,     /* R4  - Audio Interface */
+        0x0000,     /* R5  - Companding control */
+        0x0140,     /* R6  - Clock Gen control */
+        0x0000,     /* R7  - Additional control */
+        0x0000,     /* R8  - GPIO Control */
+        0x0000,     /* R9  - Jack Detect Control 1 */
+        0x0000,     /* R10 - DAC Control */
+        0x00FF,     /* R11 - Left DAC digital Vol */
+        0x00FF,     /* R12 - Right DAC digital vol */
+        0x0000,     /* R13 - Jack Detect Control 2 */
+        0x0100,     /* R14 - ADC Control */
+        0x00FF,     /* R15 - Left ADC Digital Vol */
+        0x00FF,     /* R16 - Right ADC Digital Vol */
+        0x0000,     /* R17 */
+        0x012C,     /* R18 - EQ1 - low shelf */
+        0x002C,     /* R19 - EQ2 - peak 1 */
+        0x002C,     /* R20 - EQ3 - peak 2 */
+        0x002C,     /* R21 - EQ4 - peak 3 */
+        0x002C,     /* R22 - EQ5 - high shelf */
+        0x0000,     /* R23 */
+        0x0032,     /* R24 - DAC Limiter 1 */
+        0x0000,     /* R25 - DAC Limiter 2 */
+        0x0000,     /* R26 */
+        0x0000,     /* R27 - Notch Filter 1 */
+        0x0000,     /* R28 - Notch Filter 2 */
+        0x0000,     /* R29 - Notch Filter 3 */
+        0x0000,     /* R30 - Notch Filter 4 */
+        0x0000,     /* R31 */
+        0x0038,     /* R32 - ALC control 1 */
+        0x000B,     /* R33 - ALC control 2 */
+        0x0032,     /* R34 - ALC control 3 */
+        0x0000,     /* R35 - Noise Gate */
+        0x0008,     /* R36 - PLL N */
+        0x000C,     /* R37 - PLL K 1 */
+        0x0093,     /* R38 - PLL K 2 */
+        0x00E9,     /* R39 - PLL K 3 */
+        0x0000,     /* R40 */
+        0x0000,     /* R41 - 3D control */
+        0x0000,     /* R42 - OUT4 to ADC */
+        0x0000,     /* R43 - Beep control */
+        0x0033,     /* R44 - Input ctrl */
+        0x0010,     /* R45 - Left INP PGA gain ctrl */
+        0x0010,     /* R46 - Right INP PGA gain ctrl */
+        0x0100,     /* R47 - Left ADC BOOST ctrl */
+        0x0100,     /* R48 - Right ADC BOOST ctrl */
+        0x0002,     /* R49 - Output ctrl */
+        0x0001,     /* R50 - Left mixer ctrl */
+        0x0001,     /* R51 - Right mixer ctrl */
+        0x0039,     /* R52 - LOUT1 (HP) volume ctrl */
+        0x0039,     /* R53 - ROUT1 (HP) volume ctrl */
+        0x0039,     /* R54 - LOUT2 (SPK) volume ctrl */
+        0x0039,     /* R55 - ROUT2 (SPK) volume ctrl */
+        0x0001,     /* R56 - OUT3 mixer ctrl */
+        0x0001,     /* R57 - OUT4 (MONO) mix ctrl */
+        0x0001,     /* R58 */
+        0x0000,     /* R59 */
+        0x0004,     /* R60 - OUTPUT ctrl */
+        0x0000,     /* R61 - BIAS CTRL */
+        0x0180,     /* R62 */
+        0x0000      /* R63 */
+};
+
+/*
+ * latch bit 8 of these registers to ensure instant
+ * volume updates
+ */
+static const int volume_update_regs[] = {
+        WM8985_LEFT_DAC_DIGITAL_VOL,
+        WM8985_RIGHT_DAC_DIGITAL_VOL,
+        WM8985_LEFT_ADC_DIGITAL_VOL,
+        WM8985_RIGHT_ADC_DIGITAL_VOL,
+        WM8985_LOUT2_SPK_VOLUME_CTRL,
+        WM8985_ROUT2_SPK_VOLUME_CTRL,
+        WM8985_LOUT1_HP_VOLUME_CTRL,
+        WM8985_ROUT1_HP_VOLUME_CTRL,
+        WM8985_LEFT_INP_PGA_GAIN_CTRL,
+        WM8985_RIGHT_INP_PGA_GAIN_CTRL
+};
+
+struct wm8985_priv {
+        enum snd_soc_control_type control_type;
+        struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
+        unsigned int sysclk;
+        unsigned int bclk;
+};
+
+static const struct {
+        int div;
+        int ratio;
+} fs_ratios[] = {
+        { 10, 128 },
+        { 15, 192 },
+        { 20, 256 },
+        { 30, 384 },
+        { 40, 512 },
+        { 60, 768 },
+        { 80, 1024 },
+        { 120, 1536 }
+};
+
+static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
+
+static const int bclk_divs[] = {
+        1, 2, 4, 8, 16, 32
+};
+
+static int eqmode_get(struct snd_kcontrol *kcontrol,
+                      struct snd_ctl_elem_value *ucontrol);
+static int eqmode_put(struct snd_kcontrol *kcontrol,
+                      struct snd_ctl_elem_value *ucontrol);
+
+static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
+static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
+static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
+static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
+static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
+static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
+static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
+static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
+static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
+static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
+static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
+static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
+static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
+static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
+
+static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
+static const SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7,
+                                  alc_sel_text);
+
+static const char *alc_mode_text[] = { "ALC", "Limiter" };
+static const SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8,
+                                  alc_mode_text);
+
+static const char *filter_mode_text[] = { "Audio", "Application" };
+static const SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
+                                  filter_mode_text);
+
+static const char *eq_bw_text[] = { "Narrow", "Wide" };
+static const char *eqmode_text[] = { "Capture", "Playback" };
+static const SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
+
+static const char *eq1_cutoff_text[] = {
+        "80Hz", "105Hz", "135Hz", "175Hz"
+};
+static const SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
+                                  eq1_cutoff_text);
+static const char *eq2_cutoff_text[] = {
+        "230Hz", "300Hz", "385Hz", "500Hz"
+};
+static const SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
+static const SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5,
+                                  eq2_cutoff_text);
+static const char *eq3_cutoff_text[] = {
+        "650Hz", "850Hz", "1.1kHz", "1.4kHz"
+};
+static const SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
+static const SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
+                                  eq3_cutoff_text);
+static const char *eq4_cutoff_text[] = {
+        "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
+};
+static const SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
+static const SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5,
+                                  eq4_cutoff_text);
+static const char *eq5_cutoff_text[] = {
+        "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
+};
+static const SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
+                                  eq5_cutoff_text);
+
+static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
+static const SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
+
+static const char *depth_3d_text[] = {
+        "Off",
+        "6.67%",
+        "13.3%",
+        "20%",
+        "26.7%",
+        "33.3%",
+        "40%",
+        "46.6%",
+        "53.3%",
+        "60%",
+        "66.7%",
+        "73.3%",
+        "80%",
+        "86.7%",
+        "93.3%",
+        "100%"
+};
+static const SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0,
+                                  depth_3d_text);
+
+static const struct snd_kcontrol_new wm8985_snd_controls[] = {
+        SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
+                0, 1, 0),
+
+        SOC_ENUM("ALC Capture Function", alc_sel),
+        SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
+                3, 7, 0, alc_max_tlv),
+        SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
+                0, 7, 0, alc_min_tlv),
+        SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
+                0, 15, 0, alc_tar_tlv),
+        SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
+        SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
+        SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
+        SOC_ENUM("ALC Mode", alc_mode),
+        SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
+                3, 1, 0),
+        SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
+                0, 7, 1),
+
+        SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
+                WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
+        SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
+                WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
+        SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
+                WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
+
+        SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
+                WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
+                8, 1, 0, pga_boost_tlv),
+
+        SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
+        SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
+
+        SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
+                WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
+
+        SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
+        SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
+        SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
+        SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
+                4, 7, 1, lim_thresh_tlv),
+        SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
+                0, 12, 0, lim_boost_tlv),
+        SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
+        SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
+        SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
+
+        SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
+                WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
+        SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
+                WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
+        SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
+                WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
+
+        SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
+                WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
+        SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
+                WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
+        SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
+                WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
+
+        SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
+        SOC_ENUM("High Pass Filter Mode", filter_mode),
+        SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
+
+        SOC_DOUBLE_R_TLV("Aux Bypass Volume",
+                WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
+                aux_tlv),
+
+        SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
+                WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
+                bypass_tlv),
+
+        SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
+        SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
+        SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF,  0, 24, 1, eq_tlv),
+        SOC_ENUM("EQ2 Bandwith", eq2_bw),
+        SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
+        SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
+        SOC_ENUM("EQ3 Bandwith", eq3_bw),
+        SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
+        SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
+        SOC_ENUM("EQ4 Bandwith", eq4_bw),
+        SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
+        SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
+        SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
+        SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
+
+        SOC_ENUM("3D Depth", depth_3d),
+
+        SOC_ENUM("Speaker Mode", speaker_mode)
+};
+
+static const struct snd_kcontrol_new left_out_mixer[] = {
+        SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
+        SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
+        SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new right_out_mixer[] = {
+        SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
+        SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
+        SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new left_input_mixer[] = {
+        SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
+        SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
+        SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new right_input_mixer[] = {
+        SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
+        SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
+        SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
+};
+
+static const struct snd_kcontrol_new left_boost_mixer[] = {
+        SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
+                4, 7, 0, boost_tlv),
+        SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
+                0, 7, 0, boost_tlv)
+};
+
+static const struct snd_kcontrol_new right_boost_mixer[] = {
+        SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
+                4, 7, 0, boost_tlv),
+        SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
+                0, 7, 0, boost_tlv)
+};
+
+static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
+        SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
+                0, 0),
+        SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
+                1, 0),
+        SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
+                0, 0),
+        SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
+                1, 0),
+
+        SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
+                2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
+        SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
+                3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
+
+        SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
+                2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
+        SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
+                3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
+
+        SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
+                4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
+        SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
+                5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
+
+        SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
+                6, 1, NULL, 0),
+        SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
+                6, 1, NULL, 0),
+
+        SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
+                7, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
+                8, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
+                5, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
+                6, 0, NULL, 0),
+
+        SND_SOC_DAPM_MICBIAS("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0),
+
+        SND_SOC_DAPM_INPUT("LIN"),
+        SND_SOC_DAPM_INPUT("LIP"),
+        SND_SOC_DAPM_INPUT("RIN"),
+        SND_SOC_DAPM_INPUT("RIP"),
+        SND_SOC_DAPM_INPUT("AUXL"),
+        SND_SOC_DAPM_INPUT("AUXR"),
+        SND_SOC_DAPM_INPUT("L2"),
+        SND_SOC_DAPM_INPUT("R2"),
+        SND_SOC_DAPM_OUTPUT("HPL"),
+        SND_SOC_DAPM_OUTPUT("HPR"),
+        SND_SOC_DAPM_OUTPUT("SPKL"),
+        SND_SOC_DAPM_OUTPUT("SPKR")
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+        { "Right Output Mixer", "PCM Switch", "Right DAC" },
+        { "Right Output Mixer", "Aux Switch", "AUXR" },
+        { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
+
+        { "Left Output Mixer", "PCM Switch", "Left DAC" },
+        { "Left Output Mixer", "Aux Switch", "AUXL" },
+        { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
+
+        { "Right Headphone Out", NULL, "Right Output Mixer" },
+        { "HPR", NULL, "Right Headphone Out" },
+
+        { "Left Headphone Out", NULL, "Left Output Mixer" },
+        { "HPL", NULL, "Left Headphone Out" },
+
+        { "Right Speaker Out", NULL, "Right Output Mixer" },
+        { "SPKR", NULL, "Right Speaker Out" },
+
+        { "Left Speaker Out", NULL, "Left Output Mixer" },
+        { "SPKL", NULL, "Left Speaker Out" },
+
+        { "Right ADC", NULL, "Right Boost Mixer" },
+
+        { "Right Boost Mixer", "AUXR Volume", "AUXR" },
+        { "Right Boost Mixer", NULL, "Right Capture PGA" },
+        { "Right Boost Mixer", "R2 Volume", "R2" },
+
+        { "Left ADC", NULL, "Left Boost Mixer" },
+
+        { "Left Boost Mixer", "AUXL Volume", "AUXL" },
+        { "Left Boost Mixer", NULL, "Left Capture PGA" },
+        { "Left Boost Mixer", "L2 Volume", "L2" },
+
+        { "Right Capture PGA", NULL, "Right Input Mixer" },
+        { "Left Capture PGA", NULL, "Left Input Mixer" },
+
+        { "Right Input Mixer", "R2 Switch", "R2" },
+        { "Right Input Mixer", "MicN Switch", "RIN" },
+        { "Right Input Mixer", "MicP Switch", "RIP" },
+
+        { "Left Input Mixer", "L2 Switch", "L2" },
+        { "Left Input Mixer", "MicN Switch", "LIN" },
+        { "Left Input Mixer", "MicP Switch", "LIP" },
+};
+
+static int eqmode_get(struct snd_kcontrol *kcontrol,
+                      struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int reg;
+
+        reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
+        if (reg & WM8985_EQ3DMODE)
+                ucontrol->value.integer.value[0] = 1;
+        else
+                ucontrol->value.integer.value[0] = 0;
+
+        return 0;
+}
+
+static int eqmode_put(struct snd_kcontrol *kcontrol,
+                      struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int regpwr2, regpwr3;
+        unsigned int reg_eq;
+
+        if (ucontrol->value.integer.value[0] != 0
+                        && ucontrol->value.integer.value[0] != 1)
+                return -EINVAL;
+
+        reg_eq = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
+        switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
+        case 0:
+                if (!ucontrol->value.integer.value[0])
+                        return 0;
+                break;
+        case 1:
+                if (ucontrol->value.integer.value[0])
+                        return 0;
+                break;
+        }
+
+        regpwr2 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_2);
+        regpwr3 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_3);
+        /* disable the DACs and ADCs */
+        snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_2,
+                            WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
+        snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_3,
+                            WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
+        snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
+                            WM8985_M128ENB_MASK, WM8985_M128ENB);
+        /* set the desired eqmode */
+        snd_soc_update_bits(codec, WM8985_EQ1_LOW_SHELF,
+                            WM8985_EQ3DMODE_MASK,
+                            ucontrol->value.integer.value[0]
+                            << WM8985_EQ3DMODE_SHIFT);
+        /* restore DAC/ADC configuration */
+        snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, regpwr2);
+        snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, regpwr3);
+        return 0;
+}
+
+static int wm8985_add_widgets(struct snd_soc_codec *codec)
+{
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+        snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
+                                  ARRAY_SIZE(wm8985_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map,
+                                ARRAY_SIZE(audio_map));
+        return 0;
+}
+
+static int wm8985_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, WM8985_SOFTWARE_RESET, 0x0);
+}
+
+static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+
+        return snd_soc_update_bits(codec, WM8985_DAC_CONTROL,
+                                   WM8985_SOFTMUTE_MASK,
+                                   !!mute << WM8985_SOFTMUTE_SHIFT);
+}
+
+static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec;
+        u16 format, master, bcp, lrp;
+
+        codec = dai->codec;
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                format = 0x2;
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                format = 0x0;
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                format = 0x1;
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+        case SND_SOC_DAIFMT_DSP_B:
+                format = 0x3;
+                break;
+        default:
+                dev_err(dai->dev, "Unknown dai format\n");
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
+                            WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                master = 1;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                master = 0;
+                break;
+        default:
+                dev_err(dai->dev, "Unknown master/slave configuration\n");
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
+                            WM8985_MS_MASK, master << WM8985_MS_SHIFT);
+
+        /* frame inversion is not valid for dsp modes */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_DSP_A:
+        case SND_SOC_DAIFMT_DSP_B:
+                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+                case SND_SOC_DAIFMT_IB_IF:
+                case SND_SOC_DAIFMT_NB_IF:
+                        return -EINVAL;
+                default:
+                        break;
+                }
+                break;
+        default:
+                break;
+        }
+
+        bcp = lrp = 0;
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_IF:
+                bcp = lrp = 1;
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                bcp = 1;
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                lrp = 1;
+                break;
+        default:
+                dev_err(dai->dev, "Unknown polarity configuration\n");
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
+                            WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
+        snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
+                            WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
+        return 0;
+}
+
+static int wm8985_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        int i;
+        struct snd_soc_codec *codec;
+        struct wm8985_priv *wm8985;
+        u16 blen, srate_idx;
+        unsigned int tmp;
+        int srate_best;
+
+        codec = dai->codec;
+        wm8985 = snd_soc_codec_get_drvdata(codec);
+
+        wm8985->bclk = snd_soc_params_to_bclk(params);
+        if ((int)wm8985->bclk < 0)
+                return wm8985->bclk;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                blen = 0x0;
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                blen = 0x1;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                blen = 0x2;
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                blen = 0x3;
+                break;
+        default:
+                dev_err(dai->dev, "Unsupported word length %u\n",
+                        params_format(params));
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
+                            WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
+
+        /*
+         * match to the nearest possible sample rate and rely
+         * on the array index to configure the SR register
+         */
+        srate_idx = 0;
+        srate_best = abs(srates[0] - params_rate(params));
+        for (i = 1; i < ARRAY_SIZE(srates); ++i) {
+                if (abs(srates[i] - params_rate(params)) >= srate_best)
+                        continue;
+                srate_idx = i;
+                srate_best = abs(srates[i] - params_rate(params));
+        }
+
+        dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
+        snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
+                            WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
+
+        dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
+        dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
+
+        for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
+                if (wm8985->sysclk / params_rate(params)
+                                == fs_ratios[i].ratio)
+                        break;
+        }
+
+        if (i == ARRAY_SIZE(fs_ratios)) {
+                dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
+                        wm8985->sysclk, params_rate(params));
+                return -EINVAL;
+        }
+
+        dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
+        snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
+                            WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
+
+        /* select the appropriate bclk divider */
+        tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
+        for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
+                if (wm8985->bclk == tmp / bclk_divs[i])
+                        break;
+        }
+
+        if (i == ARRAY_SIZE(bclk_divs)) {
+                dev_err(dai->dev, "No matching BCLK divider found\n");
+                return -EINVAL;
+        }
+
+        dev_dbg(dai->dev, "BCLK div = %d\n", i);
+        snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
+                            WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
+        return 0;
+}
+
+struct pll_div {
+        u32 div2:1;
+        u32 n:4;
+        u32 k:24;
+};
+
+#define FIXED_PLL_SIZE ((1ULL << 24) * 10)
+static int pll_factors(struct pll_div *pll_div, unsigned int target,
+                       unsigned int source)
+{
+        u64 Kpart;
+        unsigned long int K, Ndiv, Nmod;
+
+        pll_div->div2 = 0;
+        Ndiv = target / source;
+        if (Ndiv < 6) {
+                source >>= 1;
+                pll_div->div2 = 1;
+                Ndiv = target / source;
+        }
+
+        if (Ndiv < 6 || Ndiv > 12) {
+                printk(KERN_ERR "%s: WM8985 N value is not within"
+                       " the recommended range: %lu\n", __func__, Ndiv);
+                return -EINVAL;
+        }
+        pll_div->n = Ndiv;
+
+        Nmod = target % source;
+        Kpart = FIXED_PLL_SIZE * (u64)Nmod;
+
+        do_div(Kpart, source);
+
+        K = Kpart & 0xffffffff;
+        if ((K % 10) >= 5)
+                K += 5;
+        K /= 10;
+        pll_div->k = K;
+
+        return 0;
+}
+
+static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
+                          int source, unsigned int freq_in,
+                          unsigned int freq_out)
+{
+        int ret;
+        struct snd_soc_codec *codec;
+        struct pll_div pll_div;
+
+        codec = dai->codec;
+        if (freq_in && freq_out) {
+                ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
+                if (ret)
+                        return ret;
+        }
+
+        /* disable the PLL before reprogramming it */
+        snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
+                            WM8985_PLLEN_MASK, 0);
+        
+        if (!freq_in || !freq_out)
+                return 0;
+
+        /* set PLLN and PRESCALE */
+        snd_soc_write(codec, WM8985_PLL_N,
+                      (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
+                      | pll_div.n);
+        /* set PLLK */
+        snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff);
+        snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
+        snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18));
+        /* set the source of the clock to be the PLL */
+        snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
+                            WM8985_CLKSEL_MASK, WM8985_CLKSEL);
+        /* enable the PLL */
+        snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
+                            WM8985_PLLEN_MASK, WM8985_PLLEN);
+        return 0;
+}
+
+static int wm8985_set_sysclk(struct snd_soc_dai *dai,
+                             int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec;
+        struct wm8985_priv *wm8985;
+
+        codec = dai->codec;
+        wm8985 = snd_soc_codec_get_drvdata(codec);
+
+        switch (clk_id) {
+        case WM8985_CLKSRC_MCLK:
+                snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
+                                    WM8985_CLKSEL_MASK, 0);
+                snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
+                                    WM8985_PLLEN_MASK, 0);
+                break;
+        case WM8985_CLKSRC_PLL:
+                snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
+                                    WM8985_CLKSEL_MASK, WM8985_CLKSEL);
+                break;
+        default:
+                dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
+                return -EINVAL;
+        }
+
+        wm8985->sysclk = freq;
+        return 0;
+}
+
+static void wm8985_sync_cache(struct snd_soc_codec *codec)
+{
+        short i;
+        u16 *cache;
+
+        if (!codec->cache_sync)
+                return;
+        codec->cache_only = 0;
+        /* restore cache */
+        cache = codec->reg_cache;
+        for (i = 0; i < codec->driver->reg_cache_size; i++) {
+                if (i == WM8985_SOFTWARE_RESET
+                                || cache[i] == wm8985_reg_defs[i])
+                        continue;
+                snd_soc_write(codec, i, cache[i]);
+        }
+        codec->cache_sync = 0;
+}
+
+static int wm8985_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        int ret;
+        struct wm8985_priv *wm8985;
+
+        wm8985 = snd_soc_codec_get_drvdata(codec);
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+        case SND_SOC_BIAS_PREPARE:
+                /* VMID at 75k */
+                snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
+                                    WM8985_VMIDSEL_MASK,
+                                    1 << WM8985_VMIDSEL_SHIFT);
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
+                                                    wm8985->supplies);
+                        if (ret) {
+                                dev_err(codec->dev,
+                                        "Failed to enable supplies: %d\n",
+                                        ret);
+                                return ret;
+                        }
+
+                        wm8985_sync_cache(codec);
+
+                        /* enable anti-pop features */
+                        snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
+                                            WM8985_POBCTRL_MASK,
+                                            WM8985_POBCTRL);
+                        /* enable thermal shutdown */
+                        snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
+                                            WM8985_TSDEN_MASK, WM8985_TSDEN);
+                        snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
+                                            WM8985_TSOPCTRL_MASK,
+                                            WM8985_TSOPCTRL);
+                        /* enable BIASEN */
+                        snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
+                                            WM8985_BIASEN_MASK, WM8985_BIASEN);
+                        /* VMID at 75k */
+                        snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
+                                            WM8985_VMIDSEL_MASK,
+                                            1 << WM8985_VMIDSEL_SHIFT);
+                        msleep(500);
+                        /* disable anti-pop features */
+                        snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
+                                            WM8985_POBCTRL_MASK, 0);
+                }
+                /* VMID at 300k */
+                snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
+                                    WM8985_VMIDSEL_MASK,
+                                    2 << WM8985_VMIDSEL_SHIFT);
+                break;
+        case SND_SOC_BIAS_OFF:
+                /* disable thermal shutdown */
+                snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
+                                    WM8985_TSOPCTRL_MASK, 0);
+                snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
+                                    WM8985_TSDEN_MASK, 0);
+                /* disable VMIDSEL and BIASEN */
+                snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
+                                    WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
+                                    0);
+                snd_soc_write(codec, WM8985_POWER_MANAGEMENT_1, 0);
+                snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, 0);
+                snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, 0);
+
+                codec->cache_sync = 1;
+
+                regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
+                                       wm8985->supplies);
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int wm8985_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int wm8985_resume(struct snd_soc_codec *codec)
+{
+        wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+#else
+#define wm8985_suspend NULL
+#define wm8985_resume NULL
+#endif
+
+static int wm8985_remove(struct snd_soc_codec *codec)
+{
+        struct wm8985_priv *wm8985;
+
+        wm8985 = snd_soc_codec_get_drvdata(codec);
+        wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
+        return 0;
+}
+
+static int wm8985_probe(struct snd_soc_codec *codec)
+{
+        size_t i;
+        struct wm8985_priv *wm8985;
+        int ret;
+        u16 *cache;
+
+        wm8985 = snd_soc_codec_get_drvdata(codec);
+
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8985->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
+                return ret;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
+                wm8985->supplies[i].supply = wm8985_supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies),
+                                 wm8985->supplies);
+        if (ret) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                return ret;
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
+                                    wm8985->supplies);
+        if (ret) {
+                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                goto err_reg_get;
+        }
+
+        ret = wm8985_reset(codec);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
+                goto err_reg_enable;
+        }
+
+        cache = codec->reg_cache;
+        /* latch volume update bits */
+        for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
+                cache[volume_update_regs[i]] |= 0x100;
+        /* enable BIASCUT */
+        cache[WM8985_BIAS_CTRL] |= WM8985_BIASCUT;
+        codec->cache_sync = 1;
+
+        snd_soc_add_controls(codec, wm8985_snd_controls,
+                             ARRAY_SIZE(wm8985_snd_controls));
+        wm8985_add_widgets(codec);
+
+        wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+
+err_reg_enable:
+        regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
+err_reg_get:
+        regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
+        return ret;
+}
+
+static struct snd_soc_dai_ops wm8985_dai_ops = {
+        .digital_mute = wm8985_dac_mute,
+        .hw_params = wm8985_hw_params,
+        .set_fmt = wm8985_set_fmt,
+        .set_sysclk = wm8985_set_sysclk,
+        .set_pll = wm8985_set_pll
+};
+
+#define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver wm8985_dai = {
+        .name = "wm8985-hifi",
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_48000,
+                .formats = WM8985_FORMATS,
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_48000,
+                .formats = WM8985_FORMATS,
+        },
+        .ops = &wm8985_dai_ops,
+        .symmetric_rates = 1
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8985 = {
+        .probe = wm8985_probe,
+        .remove = wm8985_remove,
+        .suspend = wm8985_suspend,
+        .resume = wm8985_resume,
+        .set_bias_level = wm8985_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8985_reg_defs),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8985_reg_defs
+};
+
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8985_spi_probe(struct spi_device *spi)
+{
+        struct wm8985_priv *wm8985;
+        int ret;
+
+        wm8985 = kzalloc(sizeof *wm8985, GFP_KERNEL);
+        if (!wm8985)
+                return -ENOMEM;
+
+        wm8985->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8985);
+
+        ret = snd_soc_register_codec(&spi->dev,
+                                     &soc_codec_dev_wm8985, &wm8985_dai, 1);
+        if (ret < 0)
+                kfree(wm8985);
+        return ret;
+}
+
+static int __devexit wm8985_spi_remove(struct spi_device *spi)
+{
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
+}
+
+static struct spi_driver wm8985_spi_driver = {
+        .driver = {
+                .name = "wm8985",
+                .owner = THIS_MODULE,
+        },
+        .probe = wm8985_spi_probe,
+        .remove = __devexit_p(wm8985_spi_remove)
+};
+#endif
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8985_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8985_priv *wm8985;
+        int ret;
+
+        wm8985 = kzalloc(sizeof *wm8985, GFP_KERNEL);
+        if (!wm8985)
+                return -ENOMEM;
+
+        wm8985->control_type = SND_SOC_I2C;
+        i2c_set_clientdata(i2c, wm8985);
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                                     &soc_codec_dev_wm8985, &wm8985_dai, 1);
+        if (ret < 0)
+                kfree(wm8985);
+        return ret;
+}
+
+static __devexit int wm8985_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id wm8985_i2c_id[] = {
+        { "wm8985", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
+
+static struct i2c_driver wm8985_i2c_driver = {
+        .driver = {
+                .name = "wm8985",
+                .owner = THIS_MODULE,
+        },
+        .probe = wm8985_i2c_probe,
+        .remove = __devexit_p(wm8985_i2c_remove),
+        .id_table = wm8985_i2c_id
+};
+#endif
+
+static int __init wm8985_modinit(void)
+{
+        int ret = 0;
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8985_i2c_driver);
+        if (ret) {
+                printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
+                       ret);
+        }
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        ret = spi_register_driver(&wm8985_spi_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
+                       ret);
+        }
+#endif
+        return ret;
+}
+module_init(wm8985_modinit);
+
+static void __exit wm8985_exit(void)
+{
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&wm8985_i2c_driver);
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        spi_unregister_driver(&wm8985_spi_driver);
+#endif
+}
+module_exit(wm8985_exit);
+
+MODULE_DESCRIPTION("ASoC WM8985 driver");
+MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8985.h b/sound/soc/codecs/wm8985.h
new file mode 100644
index 000000000000..2e71ff507638
--- /dev/null
+++ b/sound/soc/codecs/wm8985.h
@@ -0,0 +1,1045 @@
+/*
+ * wm8985.h  --  WM8985 ASoC driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8985_H
+#define _WM8985_H
+
+#define WM8985_SOFTWARE_RESET                   0x00
+#define WM8985_POWER_MANAGEMENT_1               0x01
+#define WM8985_POWER_MANAGEMENT_2               0x02
+#define WM8985_POWER_MANAGEMENT_3               0x03
+#define WM8985_AUDIO_INTERFACE                  0x04
+#define WM8985_COMPANDING_CONTROL               0x05
+#define WM8985_CLOCK_GEN_CONTROL                0x06
+#define WM8985_ADDITIONAL_CONTROL               0x07
+#define WM8985_GPIO_CONTROL                     0x08
+#define WM8985_JACK_DETECT_CONTROL_1            0x09
+#define WM8985_DAC_CONTROL                      0x0A
+#define WM8985_LEFT_DAC_DIGITAL_VOL             0x0B
+#define WM8985_RIGHT_DAC_DIGITAL_VOL            0x0C
+#define WM8985_JACK_DETECT_CONTROL_2            0x0D
+#define WM8985_ADC_CONTROL                      0x0E
+#define WM8985_LEFT_ADC_DIGITAL_VOL             0x0F
+#define WM8985_RIGHT_ADC_DIGITAL_VOL            0x10
+#define WM8985_EQ1_LOW_SHELF                    0x12
+#define WM8985_EQ2_PEAK_1                       0x13
+#define WM8985_EQ3_PEAK_2                       0x14
+#define WM8985_EQ4_PEAK_3                       0x15
+#define WM8985_EQ5_HIGH_SHELF                   0x16
+#define WM8985_DAC_LIMITER_1                    0x18
+#define WM8985_DAC_LIMITER_2                    0x19
+#define WM8985_NOTCH_FILTER_1                   0x1B
+#define WM8985_NOTCH_FILTER_2                   0x1C
+#define WM8985_NOTCH_FILTER_3                   0x1D
+#define WM8985_NOTCH_FILTER_4                   0x1E
+#define WM8985_ALC_CONTROL_1                    0x20
+#define WM8985_ALC_CONTROL_2                    0x21
+#define WM8985_ALC_CONTROL_3                    0x22
+#define WM8985_NOISE_GATE                       0x23
+#define WM8985_PLL_N                            0x24
+#define WM8985_PLL_K_1                          0x25
+#define WM8985_PLL_K_2                          0x26
+#define WM8985_PLL_K_3                          0x27
+#define WM8985_3D_CONTROL                       0x29
+#define WM8985_OUT4_TO_ADC                      0x2A
+#define WM8985_BEEP_CONTROL                     0x2B
+#define WM8985_INPUT_CTRL                       0x2C
+#define WM8985_LEFT_INP_PGA_GAIN_CTRL           0x2D
+#define WM8985_RIGHT_INP_PGA_GAIN_CTRL          0x2E
+#define WM8985_LEFT_ADC_BOOST_CTRL              0x2F
+#define WM8985_RIGHT_ADC_BOOST_CTRL             0x30
+#define WM8985_OUTPUT_CTRL0                     0x31
+#define WM8985_LEFT_MIXER_CTRL                  0x32
+#define WM8985_RIGHT_MIXER_CTRL                 0x33
+#define WM8985_LOUT1_HP_VOLUME_CTRL             0x34
+#define WM8985_ROUT1_HP_VOLUME_CTRL             0x35
+#define WM8985_LOUT2_SPK_VOLUME_CTRL            0x36
+#define WM8985_ROUT2_SPK_VOLUME_CTRL            0x37
+#define WM8985_OUT3_MIXER_CTRL                  0x38
+#define WM8985_OUT4_MONO_MIX_CTRL               0x39
+#define WM8985_OUTPUT_CTRL1                     0x3C
+#define WM8985_BIAS_CTRL                        0x3D
+
+#define WM8985_REGISTER_COUNT                   59
+#define WM8985_MAX_REGISTER                     0x3F
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Software Reset
+ */
+#define WM8985_SOFTWARE_RESET_MASK              0x01FF  /* SOFTWARE_RESET - [8:0] */
+#define WM8985_SOFTWARE_RESET_SHIFT                  0  /* SOFTWARE_RESET - [8:0] */
+#define WM8985_SOFTWARE_RESET_WIDTH                  9  /* SOFTWARE_RESET - [8:0] */
+
+/*
+ * R1 (0x01) - Power management 1
+ */
+#define WM8985_OUT4MIXEN                        0x0080  /* OUT4MIXEN */
+#define WM8985_OUT4MIXEN_MASK                   0x0080  /* OUT4MIXEN */
+#define WM8985_OUT4MIXEN_SHIFT                       7  /* OUT4MIXEN */
+#define WM8985_OUT4MIXEN_WIDTH                       1  /* OUT4MIXEN */
+#define WM8985_OUT3MIXEN                        0x0040  /* OUT3MIXEN */
+#define WM8985_OUT3MIXEN_MASK                   0x0040  /* OUT3MIXEN */
+#define WM8985_OUT3MIXEN_SHIFT                       6  /* OUT3MIXEN */
+#define WM8985_OUT3MIXEN_WIDTH                       1  /* OUT3MIXEN */
+#define WM8985_PLLEN                            0x0020  /* PLLEN */
+#define WM8985_PLLEN_MASK                       0x0020  /* PLLEN */
+#define WM8985_PLLEN_SHIFT                           5  /* PLLEN */
+#define WM8985_PLLEN_WIDTH                           1  /* PLLEN */
+#define WM8985_MICBEN                           0x0010  /* MICBEN */
+#define WM8985_MICBEN_MASK                      0x0010  /* MICBEN */
+#define WM8985_MICBEN_SHIFT                          4  /* MICBEN */
+#define WM8985_MICBEN_WIDTH                          1  /* MICBEN */
+#define WM8985_BIASEN                           0x0008  /* BIASEN */
+#define WM8985_BIASEN_MASK                      0x0008  /* BIASEN */
+#define WM8985_BIASEN_SHIFT                          3  /* BIASEN */
+#define WM8985_BIASEN_WIDTH                          1  /* BIASEN */
+#define WM8985_BUFIOEN                          0x0004  /* BUFIOEN */
+#define WM8985_BUFIOEN_MASK                     0x0004  /* BUFIOEN */
+#define WM8985_BUFIOEN_SHIFT                         2  /* BUFIOEN */
+#define WM8985_BUFIOEN_WIDTH                         1  /* BUFIOEN */
+#define WM8985_VMIDSEL                          0x0003  /* VMIDSEL */
+#define WM8985_VMIDSEL_MASK                     0x0003  /* VMIDSEL - [1:0] */
+#define WM8985_VMIDSEL_SHIFT                         0  /* VMIDSEL - [1:0] */
+#define WM8985_VMIDSEL_WIDTH                         2  /* VMIDSEL - [1:0] */
+
+/*
+ * R2 (0x02) - Power management 2
+ */
+#define WM8985_ROUT1EN                          0x0100  /* ROUT1EN */
+#define WM8985_ROUT1EN_MASK                     0x0100  /* ROUT1EN */
+#define WM8985_ROUT1EN_SHIFT                         8  /* ROUT1EN */
+#define WM8985_ROUT1EN_WIDTH                         1  /* ROUT1EN */
+#define WM8985_LOUT1EN                          0x0080  /* LOUT1EN */
+#define WM8985_LOUT1EN_MASK                     0x0080  /* LOUT1EN */
+#define WM8985_LOUT1EN_SHIFT                         7  /* LOUT1EN */
+#define WM8985_LOUT1EN_WIDTH                         1  /* LOUT1EN */
+#define WM8985_SLEEP                            0x0040  /* SLEEP */
+#define WM8985_SLEEP_MASK                       0x0040  /* SLEEP */
+#define WM8985_SLEEP_SHIFT                           6  /* SLEEP */
+#define WM8985_SLEEP_WIDTH                           1  /* SLEEP */
+#define WM8985_BOOSTENR                         0x0020  /* BOOSTENR */
+#define WM8985_BOOSTENR_MASK                    0x0020  /* BOOSTENR */
+#define WM8985_BOOSTENR_SHIFT                        5  /* BOOSTENR */
+#define WM8985_BOOSTENR_WIDTH                        1  /* BOOSTENR */
+#define WM8985_BOOSTENL                         0x0010  /* BOOSTENL */
+#define WM8985_BOOSTENL_MASK                    0x0010  /* BOOSTENL */
+#define WM8985_BOOSTENL_SHIFT                        4  /* BOOSTENL */
+#define WM8985_BOOSTENL_WIDTH                        1  /* BOOSTENL */
+#define WM8985_INPGAENR                         0x0008  /* INPGAENR */
+#define WM8985_INPGAENR_MASK                    0x0008  /* INPGAENR */
+#define WM8985_INPGAENR_SHIFT                        3  /* INPGAENR */
+#define WM8985_INPGAENR_WIDTH                        1  /* INPGAENR */
+#define WM8985_INPPGAENL                        0x0004  /* INPPGAENL */
+#define WM8985_INPPGAENL_MASK                   0x0004  /* INPPGAENL */
+#define WM8985_INPPGAENL_SHIFT                       2  /* INPPGAENL */
+#define WM8985_INPPGAENL_WIDTH                       1  /* INPPGAENL */
+#define WM8985_ADCENR                           0x0002  /* ADCENR */
+#define WM8985_ADCENR_MASK                      0x0002  /* ADCENR */
+#define WM8985_ADCENR_SHIFT                          1  /* ADCENR */
+#define WM8985_ADCENR_WIDTH                          1  /* ADCENR */
+#define WM8985_ADCENL                           0x0001  /* ADCENL */
+#define WM8985_ADCENL_MASK                      0x0001  /* ADCENL */
+#define WM8985_ADCENL_SHIFT                          0  /* ADCENL */
+#define WM8985_ADCENL_WIDTH                          1  /* ADCENL */
+
+/*
+ * R3 (0x03) - Power management 3
+ */
+#define WM8985_OUT4EN                           0x0100  /* OUT4EN */
+#define WM8985_OUT4EN_MASK                      0x0100  /* OUT4EN */
+#define WM8985_OUT4EN_SHIFT                          8  /* OUT4EN */
+#define WM8985_OUT4EN_WIDTH                          1  /* OUT4EN */
+#define WM8985_OUT3EN                           0x0080  /* OUT3EN */
+#define WM8985_OUT3EN_MASK                      0x0080  /* OUT3EN */
+#define WM8985_OUT3EN_SHIFT                          7  /* OUT3EN */
+#define WM8985_OUT3EN_WIDTH                          1  /* OUT3EN */
+#define WM8985_ROUT2EN                          0x0040  /* ROUT2EN */
+#define WM8985_ROUT2EN_MASK                     0x0040  /* ROUT2EN */
+#define WM8985_ROUT2EN_SHIFT                         6  /* ROUT2EN */
+#define WM8985_ROUT2EN_WIDTH                         1  /* ROUT2EN */
+#define WM8985_LOUT2EN                          0x0020  /* LOUT2EN */
+#define WM8985_LOUT2EN_MASK                     0x0020  /* LOUT2EN */
+#define WM8985_LOUT2EN_SHIFT                         5  /* LOUT2EN */
+#define WM8985_LOUT2EN_WIDTH                         1  /* LOUT2EN */
+#define WM8985_RMIXEN                           0x0008  /* RMIXEN */
+#define WM8985_RMIXEN_MASK                      0x0008  /* RMIXEN */
+#define WM8985_RMIXEN_SHIFT                          3  /* RMIXEN */
+#define WM8985_RMIXEN_WIDTH                          1  /* RMIXEN */
+#define WM8985_LMIXEN                           0x0004  /* LMIXEN */
+#define WM8985_LMIXEN_MASK                      0x0004  /* LMIXEN */
+#define WM8985_LMIXEN_SHIFT                          2  /* LMIXEN */
+#define WM8985_LMIXEN_WIDTH                          1  /* LMIXEN */
+#define WM8985_DACENR                           0x0002  /* DACENR */
+#define WM8985_DACENR_MASK                      0x0002  /* DACENR */
+#define WM8985_DACENR_SHIFT                          1  /* DACENR */
+#define WM8985_DACENR_WIDTH                          1  /* DACENR */
+#define WM8985_DACENL                           0x0001  /* DACENL */
+#define WM8985_DACENL_MASK                      0x0001  /* DACENL */
+#define WM8985_DACENL_SHIFT                          0  /* DACENL */
+#define WM8985_DACENL_WIDTH                          1  /* DACENL */
+
+/*
+ * R4 (0x04) - Audio Interface
+ */
+#define WM8985_BCP                              0x0100  /* BCP */
+#define WM8985_BCP_MASK                         0x0100  /* BCP */
+#define WM8985_BCP_SHIFT                             8  /* BCP */
+#define WM8985_BCP_WIDTH                             1  /* BCP */
+#define WM8985_LRP                              0x0080  /* LRP */
+#define WM8985_LRP_MASK                         0x0080  /* LRP */
+#define WM8985_LRP_SHIFT                             7  /* LRP */
+#define WM8985_LRP_WIDTH                             1  /* LRP */
+#define WM8985_WL_MASK                          0x0060  /* WL - [6:5] */
+#define WM8985_WL_SHIFT                              5  /* WL - [6:5] */
+#define WM8985_WL_WIDTH                              2  /* WL - [6:5] */
+#define WM8985_FMT_MASK                         0x0018  /* FMT - [4:3] */
+#define WM8985_FMT_SHIFT                             3  /* FMT - [4:3] */
+#define WM8985_FMT_WIDTH                             2  /* FMT - [4:3] */
+#define WM8985_DLRSWAP                          0x0004  /* DLRSWAP */
+#define WM8985_DLRSWAP_MASK                     0x0004  /* DLRSWAP */
+#define WM8985_DLRSWAP_SHIFT                         2  /* DLRSWAP */
+#define WM8985_DLRSWAP_WIDTH                         1  /* DLRSWAP */
+#define WM8985_ALRSWAP                          0x0002  /* ALRSWAP */
+#define WM8985_ALRSWAP_MASK                     0x0002  /* ALRSWAP */
+#define WM8985_ALRSWAP_SHIFT                         1  /* ALRSWAP */
+#define WM8985_ALRSWAP_WIDTH                         1  /* ALRSWAP */
+#define WM8985_MONO                             0x0001  /* MONO */
+#define WM8985_MONO_MASK                        0x0001  /* MONO */
+#define WM8985_MONO_SHIFT                            0  /* MONO */
+#define WM8985_MONO_WIDTH                            1  /* MONO */
+
+/*
+ * R5 (0x05) - Companding control
+ */
+#define WM8985_WL8                              0x0020  /* WL8 */
+#define WM8985_WL8_MASK                         0x0020  /* WL8 */
+#define WM8985_WL8_SHIFT                             5  /* WL8 */
+#define WM8985_WL8_WIDTH                             1  /* WL8 */
+#define WM8985_DAC_COMP_MASK                    0x0018  /* DAC_COMP - [4:3] */
+#define WM8985_DAC_COMP_SHIFT                        3  /* DAC_COMP - [4:3] */
+#define WM8985_DAC_COMP_WIDTH                        2  /* DAC_COMP - [4:3] */
+#define WM8985_ADC_COMP_MASK                    0x0006  /* ADC_COMP - [2:1] */
+#define WM8985_ADC_COMP_SHIFT                        1  /* ADC_COMP - [2:1] */
+#define WM8985_ADC_COMP_WIDTH                        2  /* ADC_COMP - [2:1] */
+#define WM8985_LOOPBACK                         0x0001  /* LOOPBACK */
+#define WM8985_LOOPBACK_MASK                    0x0001  /* LOOPBACK */
+#define WM8985_LOOPBACK_SHIFT                        0  /* LOOPBACK */
+#define WM8985_LOOPBACK_WIDTH                        1  /* LOOPBACK */
+
+/*
+ * R6 (0x06) - Clock Gen control
+ */
+#define WM8985_CLKSEL                           0x0100  /* CLKSEL */
+#define WM8985_CLKSEL_MASK                      0x0100  /* CLKSEL */
+#define WM8985_CLKSEL_SHIFT                          8  /* CLKSEL */
+#define WM8985_CLKSEL_WIDTH                          1  /* CLKSEL */
+#define WM8985_MCLKDIV_MASK                     0x00E0  /* MCLKDIV - [7:5] */
+#define WM8985_MCLKDIV_SHIFT                         5  /* MCLKDIV - [7:5] */
+#define WM8985_MCLKDIV_WIDTH                         3  /* MCLKDIV - [7:5] */
+#define WM8985_BCLKDIV_MASK                     0x001C  /* BCLKDIV - [4:2] */
+#define WM8985_BCLKDIV_SHIFT                         2  /* BCLKDIV - [4:2] */
+#define WM8985_BCLKDIV_WIDTH                         3  /* BCLKDIV - [4:2] */
+#define WM8985_MS                               0x0001  /* MS */
+#define WM8985_MS_MASK                          0x0001  /* MS */
+#define WM8985_MS_SHIFT                              0  /* MS */
+#define WM8985_MS_WIDTH                              1  /* MS */
+
+/*
+ * R7 (0x07) - Additional control
+ */
+#define WM8985_M128ENB                          0x0100  /* M128ENB */
+#define WM8985_M128ENB_MASK                     0x0100  /* M128ENB */
+#define WM8985_M128ENB_SHIFT                         8  /* M128ENB */
+#define WM8985_M128ENB_WIDTH                         1  /* M128ENB */
+#define WM8985_DCLKDIV_MASK                     0x00F0  /* DCLKDIV - [7:4] */
+#define WM8985_DCLKDIV_SHIFT                         4  /* DCLKDIV - [7:4] */
+#define WM8985_DCLKDIV_WIDTH                         4  /* DCLKDIV - [7:4] */
+#define WM8985_SR_MASK                          0x000E  /* SR - [3:1] */
+#define WM8985_SR_SHIFT                              1  /* SR - [3:1] */
+#define WM8985_SR_WIDTH                              3  /* SR - [3:1] */
+#define WM8985_SLOWCLKEN                        0x0001  /* SLOWCLKEN */
+#define WM8985_SLOWCLKEN_MASK                   0x0001  /* SLOWCLKEN */
+#define WM8985_SLOWCLKEN_SHIFT                       0  /* SLOWCLKEN */
+#define WM8985_SLOWCLKEN_WIDTH                       1  /* SLOWCLKEN */
+
+/*
+ * R8 (0x08) - GPIO Control
+ */
+#define WM8985_GPIO1GP                          0x0100  /* GPIO1GP */
+#define WM8985_GPIO1GP_MASK                     0x0100  /* GPIO1GP */
+#define WM8985_GPIO1GP_SHIFT                         8  /* GPIO1GP */
+#define WM8985_GPIO1GP_WIDTH                         1  /* GPIO1GP */
+#define WM8985_GPIO1GPU                         0x0080  /* GPIO1GPU */
+#define WM8985_GPIO1GPU_MASK                    0x0080  /* GPIO1GPU */
+#define WM8985_GPIO1GPU_SHIFT                        7  /* GPIO1GPU */
+#define WM8985_GPIO1GPU_WIDTH                        1  /* GPIO1GPU */
+#define WM8985_GPIO1GPD                         0x0040  /* GPIO1GPD */
+#define WM8985_GPIO1GPD_MASK                    0x0040  /* GPIO1GPD */
+#define WM8985_GPIO1GPD_SHIFT                        6  /* GPIO1GPD */
+#define WM8985_GPIO1GPD_WIDTH                        1  /* GPIO1GPD */
+#define WM8985_GPIO1POL                         0x0008  /* GPIO1POL */
+#define WM8985_GPIO1POL_MASK                    0x0008  /* GPIO1POL */
+#define WM8985_GPIO1POL_SHIFT                        3  /* GPIO1POL */
+#define WM8985_GPIO1POL_WIDTH                        1  /* GPIO1POL */
+#define WM8985_GPIO1SEL_MASK                    0x0007  /* GPIO1SEL - [2:0] */
+#define WM8985_GPIO1SEL_SHIFT                        0  /* GPIO1SEL - [2:0] */
+#define WM8985_GPIO1SEL_WIDTH                        3  /* GPIO1SEL - [2:0] */
+
+/*
+ * R9 (0x09) - Jack Detect Control 1
+ */
+#define WM8985_JD_EN                            0x0040  /* JD_EN */
+#define WM8985_JD_EN_MASK                       0x0040  /* JD_EN */
+#define WM8985_JD_EN_SHIFT                           6  /* JD_EN */
+#define WM8985_JD_EN_WIDTH                           1  /* JD_EN */
+#define WM8985_JD_SEL_MASK                      0x0030  /* JD_SEL - [5:4] */
+#define WM8985_JD_SEL_SHIFT                          4  /* JD_SEL - [5:4] */
+#define WM8985_JD_SEL_WIDTH                          2  /* JD_SEL - [5:4] */
+
+/*
+ * R10 (0x0A) - DAC Control
+ */
+#define WM8985_SOFTMUTE                         0x0040  /* SOFTMUTE */
+#define WM8985_SOFTMUTE_MASK                    0x0040  /* SOFTMUTE */
+#define WM8985_SOFTMUTE_SHIFT                        6  /* SOFTMUTE */
+#define WM8985_SOFTMUTE_WIDTH                        1  /* SOFTMUTE */
+#define WM8985_DACOSR128                        0x0008  /* DACOSR128 */
+#define WM8985_DACOSR128_MASK                   0x0008  /* DACOSR128 */
+#define WM8985_DACOSR128_SHIFT                       3  /* DACOSR128 */
+#define WM8985_DACOSR128_WIDTH                       1  /* DACOSR128 */
+#define WM8985_AMUTE                            0x0004  /* AMUTE */
+#define WM8985_AMUTE_MASK                       0x0004  /* AMUTE */
+#define WM8985_AMUTE_SHIFT                           2  /* AMUTE */
+#define WM8985_AMUTE_WIDTH                           1  /* AMUTE */
+#define WM8985_DACPOLR                          0x0002  /* DACPOLR */
+#define WM8985_DACPOLR_MASK                     0x0002  /* DACPOLR */
+#define WM8985_DACPOLR_SHIFT                         1  /* DACPOLR */
+#define WM8985_DACPOLR_WIDTH                         1  /* DACPOLR */
+#define WM8985_DACPOLL                          0x0001  /* DACPOLL */
+#define WM8985_DACPOLL_MASK                     0x0001  /* DACPOLL */
+#define WM8985_DACPOLL_SHIFT                         0  /* DACPOLL */
+#define WM8985_DACPOLL_WIDTH                         1  /* DACPOLL */
+
+/*
+ * R11 (0x0B) - Left DAC digital Vol
+ */
+#define WM8985_DACVU                            0x0100  /* DACVU */
+#define WM8985_DACVU_MASK                       0x0100  /* DACVU */
+#define WM8985_DACVU_SHIFT                           8  /* DACVU */
+#define WM8985_DACVU_WIDTH                           1  /* DACVU */
+#define WM8985_DACVOLL_MASK                     0x00FF  /* DACVOLL - [7:0] */
+#define WM8985_DACVOLL_SHIFT                         0  /* DACVOLL - [7:0] */
+#define WM8985_DACVOLL_WIDTH                         8  /* DACVOLL - [7:0] */
+
+/*
+ * R12 (0x0C) - Right DAC digital vol
+ */
+#define WM8985_DACVU                            0x0100  /* DACVU */
+#define WM8985_DACVU_MASK                       0x0100  /* DACVU */
+#define WM8985_DACVU_SHIFT                           8  /* DACVU */
+#define WM8985_DACVU_WIDTH                           1  /* DACVU */
+#define WM8985_DACVOLR_MASK                     0x00FF  /* DACVOLR - [7:0] */
+#define WM8985_DACVOLR_SHIFT                         0  /* DACVOLR - [7:0] */
+#define WM8985_DACVOLR_WIDTH                         8  /* DACVOLR - [7:0] */
+
+/*
+ * R13 (0x0D) - Jack Detect Control 2
+ */
+#define WM8985_JD_EN1_MASK                      0x00F0  /* JD_EN1 - [7:4] */
+#define WM8985_JD_EN1_SHIFT                          4  /* JD_EN1 - [7:4] */
+#define WM8985_JD_EN1_WIDTH                          4  /* JD_EN1 - [7:4] */
+#define WM8985_JD_EN0_MASK                      0x000F  /* JD_EN0 - [3:0] */
+#define WM8985_JD_EN0_SHIFT                          0  /* JD_EN0 - [3:0] */
+#define WM8985_JD_EN0_WIDTH                          4  /* JD_EN0 - [3:0] */
+
+/*
+ * R14 (0x0E) - ADC Control
+ */
+#define WM8985_HPFEN                            0x0100  /* HPFEN */
+#define WM8985_HPFEN_MASK                       0x0100  /* HPFEN */
+#define WM8985_HPFEN_SHIFT                           8  /* HPFEN */
+#define WM8985_HPFEN_WIDTH                           1  /* HPFEN */
+#define WM8985_HPFAPP                           0x0080  /* HPFAPP */
+#define WM8985_HPFAPP_MASK                      0x0080  /* HPFAPP */
+#define WM8985_HPFAPP_SHIFT                          7  /* HPFAPP */
+#define WM8985_HPFAPP_WIDTH                          1  /* HPFAPP */
+#define WM8985_HPFCUT_MASK                      0x0070  /* HPFCUT - [6:4] */
+#define WM8985_HPFCUT_SHIFT                          4  /* HPFCUT - [6:4] */
+#define WM8985_HPFCUT_WIDTH                          3  /* HPFCUT - [6:4] */
+#define WM8985_ADCOSR128                        0x0008  /* ADCOSR128 */
+#define WM8985_ADCOSR128_MASK                   0x0008  /* ADCOSR128 */
+#define WM8985_ADCOSR128_SHIFT                       3  /* ADCOSR128 */
+#define WM8985_ADCOSR128_WIDTH                       1  /* ADCOSR128 */
+#define WM8985_ADCRPOL                          0x0002  /* ADCRPOL */
+#define WM8985_ADCRPOL_MASK                     0x0002  /* ADCRPOL */
+#define WM8985_ADCRPOL_SHIFT                         1  /* ADCRPOL */
+#define WM8985_ADCRPOL_WIDTH                         1  /* ADCRPOL */
+#define WM8985_ADCLPOL                          0x0001  /* ADCLPOL */
+#define WM8985_ADCLPOL_MASK                     0x0001  /* ADCLPOL */
+#define WM8985_ADCLPOL_SHIFT                         0  /* ADCLPOL */
+#define WM8985_ADCLPOL_WIDTH                         1  /* ADCLPOL */
+
+/*
+ * R15 (0x0F) - Left ADC Digital Vol
+ */
+#define WM8985_ADCVU                            0x0100  /* ADCVU */
+#define WM8985_ADCVU_MASK                       0x0100  /* ADCVU */
+#define WM8985_ADCVU_SHIFT                           8  /* ADCVU */
+#define WM8985_ADCVU_WIDTH                           1  /* ADCVU */
+#define WM8985_ADCVOLL_MASK                     0x00FF  /* ADCVOLL - [7:0] */
+#define WM8985_ADCVOLL_SHIFT                         0  /* ADCVOLL - [7:0] */
+#define WM8985_ADCVOLL_WIDTH                         8  /* ADCVOLL - [7:0] */
+
+/*
+ * R16 (0x10) - Right ADC Digital Vol
+ */
+#define WM8985_ADCVU                            0x0100  /* ADCVU */
+#define WM8985_ADCVU_MASK                       0x0100  /* ADCVU */
+#define WM8985_ADCVU_SHIFT                           8  /* ADCVU */
+#define WM8985_ADCVU_WIDTH                           1  /* ADCVU */
+#define WM8985_ADCVOLR_MASK                     0x00FF  /* ADCVOLR - [7:0] */
+#define WM8985_ADCVOLR_SHIFT                         0  /* ADCVOLR - [7:0] */
+#define WM8985_ADCVOLR_WIDTH                         8  /* ADCVOLR - [7:0] */
+
+/*
+ * R18 (0x12) - EQ1 - low shelf
+ */
+#define WM8985_EQ3DMODE                         0x0100  /* EQ3DMODE */
+#define WM8985_EQ3DMODE_MASK                    0x0100  /* EQ3DMODE */
+#define WM8985_EQ3DMODE_SHIFT                        8  /* EQ3DMODE */
+#define WM8985_EQ3DMODE_WIDTH                        1  /* EQ3DMODE */
+#define WM8985_EQ1C_MASK                        0x0060  /* EQ1C - [6:5] */
+#define WM8985_EQ1C_SHIFT                            5  /* EQ1C - [6:5] */
+#define WM8985_EQ1C_WIDTH                            2  /* EQ1C - [6:5] */
+#define WM8985_EQ1G_MASK                        0x001F  /* EQ1G - [4:0] */
+#define WM8985_EQ1G_SHIFT                            0  /* EQ1G - [4:0] */
+#define WM8985_EQ1G_WIDTH                            5  /* EQ1G - [4:0] */
+
+/*
+ * R19 (0x13) - EQ2 - peak 1
+ */
+#define WM8985_EQ2BW                            0x0100  /* EQ2BW */
+#define WM8985_EQ2BW_MASK                       0x0100  /* EQ2BW */
+#define WM8985_EQ2BW_SHIFT                           8  /* EQ2BW */
+#define WM8985_EQ2BW_WIDTH                           1  /* EQ2BW */
+#define WM8985_EQ2C_MASK                        0x0060  /* EQ2C - [6:5] */
+#define WM8985_EQ2C_SHIFT                            5  /* EQ2C - [6:5] */
+#define WM8985_EQ2C_WIDTH                            2  /* EQ2C - [6:5] */
+#define WM8985_EQ2G_MASK                        0x001F  /* EQ2G - [4:0] */
+#define WM8985_EQ2G_SHIFT                            0  /* EQ2G - [4:0] */
+#define WM8985_EQ2G_WIDTH                            5  /* EQ2G - [4:0] */
+
+/*
+ * R20 (0x14) - EQ3 - peak 2
+ */
+#define WM8985_EQ3BW                            0x0100  /* EQ3BW */
+#define WM8985_EQ3BW_MASK                       0x0100  /* EQ3BW */
+#define WM8985_EQ3BW_SHIFT                           8  /* EQ3BW */
+#define WM8985_EQ3BW_WIDTH                           1  /* EQ3BW */
+#define WM8985_EQ3C_MASK                        0x0060  /* EQ3C - [6:5] */
+#define WM8985_EQ3C_SHIFT                            5  /* EQ3C - [6:5] */
+#define WM8985_EQ3C_WIDTH                            2  /* EQ3C - [6:5] */
+#define WM8985_EQ3G_MASK                        0x001F  /* EQ3G - [4:0] */
+#define WM8985_EQ3G_SHIFT                            0  /* EQ3G - [4:0] */
+#define WM8985_EQ3G_WIDTH                            5  /* EQ3G - [4:0] */
+
+/*
+ * R21 (0x15) - EQ4 - peak 3
+ */
+#define WM8985_EQ4BW                            0x0100  /* EQ4BW */
+#define WM8985_EQ4BW_MASK                       0x0100  /* EQ4BW */
+#define WM8985_EQ4BW_SHIFT                           8  /* EQ4BW */
+#define WM8985_EQ4BW_WIDTH                           1  /* EQ4BW */
+#define WM8985_EQ4C_MASK                        0x0060  /* EQ4C - [6:5] */
+#define WM8985_EQ4C_SHIFT                            5  /* EQ4C - [6:5] */
+#define WM8985_EQ4C_WIDTH                            2  /* EQ4C - [6:5] */
+#define WM8985_EQ4G_MASK                        0x001F  /* EQ4G - [4:0] */
+#define WM8985_EQ4G_SHIFT                            0  /* EQ4G - [4:0] */
+#define WM8985_EQ4G_WIDTH                            5  /* EQ4G - [4:0] */
+
+/*
+ * R22 (0x16) - EQ5 - high shelf
+ */
+#define WM8985_EQ5C_MASK                        0x0060  /* EQ5C - [6:5] */
+#define WM8985_EQ5C_SHIFT                            5  /* EQ5C - [6:5] */
+#define WM8985_EQ5C_WIDTH                            2  /* EQ5C - [6:5] */
+#define WM8985_EQ5G_MASK                        0x001F  /* EQ5G - [4:0] */
+#define WM8985_EQ5G_SHIFT                            0  /* EQ5G - [4:0] */
+#define WM8985_EQ5G_WIDTH                            5  /* EQ5G - [4:0] */
+
+/*
+ * R24 (0x18) - DAC Limiter 1
+ */
+#define WM8985_LIMEN                            0x0100  /* LIMEN */
+#define WM8985_LIMEN_MASK                       0x0100  /* LIMEN */
+#define WM8985_LIMEN_SHIFT                           8  /* LIMEN */
+#define WM8985_LIMEN_WIDTH                           1  /* LIMEN */
+#define WM8985_LIMDCY_MASK                      0x00F0  /* LIMDCY - [7:4] */
+#define WM8985_LIMDCY_SHIFT                          4  /* LIMDCY - [7:4] */
+#define WM8985_LIMDCY_WIDTH                          4  /* LIMDCY - [7:4] */
+#define WM8985_LIMATK_MASK                      0x000F  /* LIMATK - [3:0] */
+#define WM8985_LIMATK_SHIFT                          0  /* LIMATK - [3:0] */
+#define WM8985_LIMATK_WIDTH                          4  /* LIMATK - [3:0] */
+
+/*
+ * R25 (0x19) - DAC Limiter 2
+ */
+#define WM8985_LIMLVL_MASK                      0x0070  /* LIMLVL - [6:4] */
+#define WM8985_LIMLVL_SHIFT                          4  /* LIMLVL - [6:4] */
+#define WM8985_LIMLVL_WIDTH                          3  /* LIMLVL - [6:4] */
+#define WM8985_LIMBOOST_MASK                    0x000F  /* LIMBOOST - [3:0] */
+#define WM8985_LIMBOOST_SHIFT                        0  /* LIMBOOST - [3:0] */
+#define WM8985_LIMBOOST_WIDTH                        4  /* LIMBOOST - [3:0] */
+
+/*
+ * R27 (0x1B) - Notch Filter 1
+ */
+#define WM8985_NFU                              0x0100  /* NFU */
+#define WM8985_NFU_MASK                         0x0100  /* NFU */
+#define WM8985_NFU_SHIFT                             8  /* NFU */
+#define WM8985_NFU_WIDTH                             1  /* NFU */
+#define WM8985_NFEN                             0x0080  /* NFEN */
+#define WM8985_NFEN_MASK                        0x0080  /* NFEN */
+#define WM8985_NFEN_SHIFT                            7  /* NFEN */
+#define WM8985_NFEN_WIDTH                            1  /* NFEN */
+#define WM8985_NFA0_13_7_MASK                   0x007F  /* NFA0(13:7) - [6:0] */
+#define WM8985_NFA0_13_7_SHIFT                       0  /* NFA0(13:7) - [6:0] */
+#define WM8985_NFA0_13_7_WIDTH                       7  /* NFA0(13:7) - [6:0] */
+
+/*
+ * R28 (0x1C) - Notch Filter 2
+ */
+#define WM8985_NFU                              0x0100  /* NFU */
+#define WM8985_NFU_MASK                         0x0100  /* NFU */
+#define WM8985_NFU_SHIFT                             8  /* NFU */
+#define WM8985_NFU_WIDTH                             1  /* NFU */
+#define WM8985_NFA0_6_0_MASK                    0x007F  /* NFA0(6:0) - [6:0] */
+#define WM8985_NFA0_6_0_SHIFT                        0  /* NFA0(6:0) - [6:0] */
+#define WM8985_NFA0_6_0_WIDTH                        7  /* NFA0(6:0) - [6:0] */
+
+/*
+ * R29 (0x1D) - Notch Filter 3
+ */
+#define WM8985_NFU                              0x0100  /* NFU */
+#define WM8985_NFU_MASK                         0x0100  /* NFU */
+#define WM8985_NFU_SHIFT                             8  /* NFU */
+#define WM8985_NFU_WIDTH                             1  /* NFU */
+#define WM8985_NFA1_13_7_MASK                   0x007F  /* NFA1(13:7) - [6:0] */
+#define WM8985_NFA1_13_7_SHIFT                       0  /* NFA1(13:7) - [6:0] */
+#define WM8985_NFA1_13_7_WIDTH                       7  /* NFA1(13:7) - [6:0] */
+
+/*
+ * R30 (0x1E) - Notch Filter 4
+ */
+#define WM8985_NFU                              0x0100  /* NFU */
+#define WM8985_NFU_MASK                         0x0100  /* NFU */
+#define WM8985_NFU_SHIFT                             8  /* NFU */
+#define WM8985_NFU_WIDTH                             1  /* NFU */
+#define WM8985_NFA1_6_0_MASK                    0x007F  /* NFA1(6:0) - [6:0] */
+#define WM8985_NFA1_6_0_SHIFT                        0  /* NFA1(6:0) - [6:0] */
+#define WM8985_NFA1_6_0_WIDTH                        7  /* NFA1(6:0) - [6:0] */
+
+/*
+ * R32 (0x20) - ALC control 1
+ */
+#define WM8985_ALCSEL_MASK                      0x0180  /* ALCSEL - [8:7] */
+#define WM8985_ALCSEL_SHIFT                          7  /* ALCSEL - [8:7] */
+#define WM8985_ALCSEL_WIDTH                          2  /* ALCSEL - [8:7] */
+#define WM8985_ALCMAX_MASK                      0x0038  /* ALCMAX - [5:3] */
+#define WM8985_ALCMAX_SHIFT                          3  /* ALCMAX - [5:3] */
+#define WM8985_ALCMAX_WIDTH                          3  /* ALCMAX - [5:3] */
+#define WM8985_ALCMIN_MASK                      0x0007  /* ALCMIN - [2:0] */
+#define WM8985_ALCMIN_SHIFT                          0  /* ALCMIN - [2:0] */
+#define WM8985_ALCMIN_WIDTH                          3  /* ALCMIN - [2:0] */
+
+/*
+ * R33 (0x21) - ALC control 2
+ */
+#define WM8985_ALCHLD_MASK                      0x00F0  /* ALCHLD - [7:4] */
+#define WM8985_ALCHLD_SHIFT                          4  /* ALCHLD - [7:4] */
+#define WM8985_ALCHLD_WIDTH                          4  /* ALCHLD - [7:4] */
+#define WM8985_ALCLVL_MASK                      0x000F  /* ALCLVL - [3:0] */
+#define WM8985_ALCLVL_SHIFT                          0  /* ALCLVL - [3:0] */
+#define WM8985_ALCLVL_WIDTH                          4  /* ALCLVL - [3:0] */
+
+/*
+ * R34 (0x22) - ALC control 3
+ */
+#define WM8985_ALCMODE                          0x0100  /* ALCMODE */
+#define WM8985_ALCMODE_MASK                     0x0100  /* ALCMODE */
+#define WM8985_ALCMODE_SHIFT                         8  /* ALCMODE */
+#define WM8985_ALCMODE_WIDTH                         1  /* ALCMODE */
+#define WM8985_ALCDCY_MASK                      0x00F0  /* ALCDCY - [7:4] */
+#define WM8985_ALCDCY_SHIFT                          4  /* ALCDCY - [7:4] */
+#define WM8985_ALCDCY_WIDTH                          4  /* ALCDCY - [7:4] */
+#define WM8985_ALCATK_MASK                      0x000F  /* ALCATK - [3:0] */
+#define WM8985_ALCATK_SHIFT                          0  /* ALCATK - [3:0] */
+#define WM8985_ALCATK_WIDTH                          4  /* ALCATK - [3:0] */
+
+/*
+ * R35 (0x23) - Noise Gate
+ */
+#define WM8985_NGEN                             0x0008  /* NGEN */
+#define WM8985_NGEN_MASK                        0x0008  /* NGEN */
+#define WM8985_NGEN_SHIFT                            3  /* NGEN */
+#define WM8985_NGEN_WIDTH                            1  /* NGEN */
+#define WM8985_NGTH_MASK                        0x0007  /* NGTH - [2:0] */
+#define WM8985_NGTH_SHIFT                            0  /* NGTH - [2:0] */
+#define WM8985_NGTH_WIDTH                            3  /* NGTH - [2:0] */
+
+/*
+ * R36 (0x24) - PLL N
+ */
+#define WM8985_PLL_PRESCALE                     0x0010  /* PLL_PRESCALE */
+#define WM8985_PLL_PRESCALE_MASK                0x0010  /* PLL_PRESCALE */
+#define WM8985_PLL_PRESCALE_SHIFT                    4  /* PLL_PRESCALE */
+#define WM8985_PLL_PRESCALE_WIDTH                    1  /* PLL_PRESCALE */
+#define WM8985_PLLN_MASK                        0x000F  /* PLLN - [3:0] */
+#define WM8985_PLLN_SHIFT                            0  /* PLLN - [3:0] */
+#define WM8985_PLLN_WIDTH                            4  /* PLLN - [3:0] */
+
+/*
+ * R37 (0x25) - PLL K 1
+ */
+#define WM8985_PLLK_23_18_MASK                  0x003F  /* PLLK(23:18) - [5:0] */
+#define WM8985_PLLK_23_18_SHIFT                      0  /* PLLK(23:18) - [5:0] */
+#define WM8985_PLLK_23_18_WIDTH                      6  /* PLLK(23:18) - [5:0] */
+
+/*
+ * R38 (0x26) - PLL K 2
+ */
+#define WM8985_PLLK_17_9_MASK                   0x01FF  /* PLLK(17:9) - [8:0] */
+#define WM8985_PLLK_17_9_SHIFT                       0  /* PLLK(17:9) - [8:0] */
+#define WM8985_PLLK_17_9_WIDTH                       9  /* PLLK(17:9) - [8:0] */
+
+/*
+ * R39 (0x27) - PLL K 3
+ */
+#define WM8985_PLLK_8_0_MASK                    0x01FF  /* PLLK(8:0) - [8:0] */
+#define WM8985_PLLK_8_0_SHIFT                        0  /* PLLK(8:0) - [8:0] */
+#define WM8985_PLLK_8_0_WIDTH                        9  /* PLLK(8:0) - [8:0] */
+
+/*
+ * R41 (0x29) - 3D control
+ */
+#define WM8985_DEPTH3D_MASK                     0x000F  /* DEPTH3D - [3:0] */
+#define WM8985_DEPTH3D_SHIFT                         0  /* DEPTH3D - [3:0] */
+#define WM8985_DEPTH3D_WIDTH                         4  /* DEPTH3D - [3:0] */
+
+/*
+ * R42 (0x2A) - OUT4 to ADC
+ */
+#define WM8985_OUT4_2ADCVOL_MASK                0x01C0  /* OUT4_2ADCVOL - [8:6] */
+#define WM8985_OUT4_2ADCVOL_SHIFT                    6  /* OUT4_2ADCVOL - [8:6] */
+#define WM8985_OUT4_2ADCVOL_WIDTH                    3  /* OUT4_2ADCVOL - [8:6] */
+#define WM8985_OUT4_2LNR                        0x0020  /* OUT4_2LNR */
+#define WM8985_OUT4_2LNR_MASK                   0x0020  /* OUT4_2LNR */
+#define WM8985_OUT4_2LNR_SHIFT                       5  /* OUT4_2LNR */
+#define WM8985_OUT4_2LNR_WIDTH                       1  /* OUT4_2LNR */
+#define WM8985_POBCTRL                          0x0004  /* POBCTRL */
+#define WM8985_POBCTRL_MASK                     0x0004  /* POBCTRL */
+#define WM8985_POBCTRL_SHIFT                         2  /* POBCTRL */
+#define WM8985_POBCTRL_WIDTH                         1  /* POBCTRL */
+#define WM8985_DELEN                            0x0002  /* DELEN */
+#define WM8985_DELEN_MASK                       0x0002  /* DELEN */
+#define WM8985_DELEN_SHIFT                           1  /* DELEN */
+#define WM8985_DELEN_WIDTH                           1  /* DELEN */
+#define WM8985_OUT1DEL                          0x0001  /* OUT1DEL */
+#define WM8985_OUT1DEL_MASK                     0x0001  /* OUT1DEL */
+#define WM8985_OUT1DEL_SHIFT                         0  /* OUT1DEL */
+#define WM8985_OUT1DEL_WIDTH                         1  /* OUT1DEL */
+
+/*
+ * R43 (0x2B) - Beep control
+ */
+#define WM8985_BYPL2RMIX                        0x0100  /* BYPL2RMIX */
+#define WM8985_BYPL2RMIX_MASK                   0x0100  /* BYPL2RMIX */
+#define WM8985_BYPL2RMIX_SHIFT                       8  /* BYPL2RMIX */
+#define WM8985_BYPL2RMIX_WIDTH                       1  /* BYPL2RMIX */
+#define WM8985_BYPR2LMIX                        0x0080  /* BYPR2LMIX */
+#define WM8985_BYPR2LMIX_MASK                   0x0080  /* BYPR2LMIX */
+#define WM8985_BYPR2LMIX_SHIFT                       7  /* BYPR2LMIX */
+#define WM8985_BYPR2LMIX_WIDTH                       1  /* BYPR2LMIX */
+#define WM8985_MUTERPGA2INV                     0x0020  /* MUTERPGA2INV */
+#define WM8985_MUTERPGA2INV_MASK                0x0020  /* MUTERPGA2INV */
+#define WM8985_MUTERPGA2INV_SHIFT                    5  /* MUTERPGA2INV */
+#define WM8985_MUTERPGA2INV_WIDTH                    1  /* MUTERPGA2INV */
+#define WM8985_INVROUT2                         0x0010  /* INVROUT2 */
+#define WM8985_INVROUT2_MASK                    0x0010  /* INVROUT2 */
+#define WM8985_INVROUT2_SHIFT                        4  /* INVROUT2 */
+#define WM8985_INVROUT2_WIDTH                        1  /* INVROUT2 */
+#define WM8985_BEEPVOL_MASK                     0x000E  /* BEEPVOL - [3:1] */
+#define WM8985_BEEPVOL_SHIFT                         1  /* BEEPVOL - [3:1] */
+#define WM8985_BEEPVOL_WIDTH                         3  /* BEEPVOL - [3:1] */
+#define WM8985_BEEPEN                           0x0001  /* BEEPEN */
+#define WM8985_BEEPEN_MASK                      0x0001  /* BEEPEN */
+#define WM8985_BEEPEN_SHIFT                          0  /* BEEPEN */
+#define WM8985_BEEPEN_WIDTH                          1  /* BEEPEN */
+
+/*
+ * R44 (0x2C) - Input ctrl
+ */
+#define WM8985_MBVSEL                           0x0100  /* MBVSEL */
+#define WM8985_MBVSEL_MASK                      0x0100  /* MBVSEL */
+#define WM8985_MBVSEL_SHIFT                          8  /* MBVSEL */
+#define WM8985_MBVSEL_WIDTH                          1  /* MBVSEL */
+#define WM8985_R2_2INPPGA                       0x0040  /* R2_2INPPGA */
+#define WM8985_R2_2INPPGA_MASK                  0x0040  /* R2_2INPPGA */
+#define WM8985_R2_2INPPGA_SHIFT                      6  /* R2_2INPPGA */
+#define WM8985_R2_2INPPGA_WIDTH                      1  /* R2_2INPPGA */
+#define WM8985_RIN2INPPGA                       0x0020  /* RIN2INPPGA */
+#define WM8985_RIN2INPPGA_MASK                  0x0020  /* RIN2INPPGA */
+#define WM8985_RIN2INPPGA_SHIFT                      5  /* RIN2INPPGA */
+#define WM8985_RIN2INPPGA_WIDTH                      1  /* RIN2INPPGA */
+#define WM8985_RIP2INPPGA                       0x0010  /* RIP2INPPGA */
+#define WM8985_RIP2INPPGA_MASK                  0x0010  /* RIP2INPPGA */
+#define WM8985_RIP2INPPGA_SHIFT                      4  /* RIP2INPPGA */
+#define WM8985_RIP2INPPGA_WIDTH                      1  /* RIP2INPPGA */
+#define WM8985_L2_2INPPGA                       0x0004  /* L2_2INPPGA */
+#define WM8985_L2_2INPPGA_MASK                  0x0004  /* L2_2INPPGA */
+#define WM8985_L2_2INPPGA_SHIFT                      2  /* L2_2INPPGA */
+#define WM8985_L2_2INPPGA_WIDTH                      1  /* L2_2INPPGA */
+#define WM8985_LIN2INPPGA                       0x0002  /* LIN2INPPGA */
+#define WM8985_LIN2INPPGA_MASK                  0x0002  /* LIN2INPPGA */
+#define WM8985_LIN2INPPGA_SHIFT                      1  /* LIN2INPPGA */
+#define WM8985_LIN2INPPGA_WIDTH                      1  /* LIN2INPPGA */
+#define WM8985_LIP2INPPGA                       0x0001  /* LIP2INPPGA */
+#define WM8985_LIP2INPPGA_MASK                  0x0001  /* LIP2INPPGA */
+#define WM8985_LIP2INPPGA_SHIFT                      0  /* LIP2INPPGA */
+#define WM8985_LIP2INPPGA_WIDTH                      1  /* LIP2INPPGA */
+
+/*
+ * R45 (0x2D) - Left INP PGA gain ctrl
+ */
+#define WM8985_INPGAVU                          0x0100  /* INPGAVU */
+#define WM8985_INPGAVU_MASK                     0x0100  /* INPGAVU */
+#define WM8985_INPGAVU_SHIFT                         8  /* INPGAVU */
+#define WM8985_INPGAVU_WIDTH                         1  /* INPGAVU */
+#define WM8985_INPPGAZCL                        0x0080  /* INPPGAZCL */
+#define WM8985_INPPGAZCL_MASK                   0x0080  /* INPPGAZCL */
+#define WM8985_INPPGAZCL_SHIFT                       7  /* INPPGAZCL */
+#define WM8985_INPPGAZCL_WIDTH                       1  /* INPPGAZCL */
+#define WM8985_INPPGAMUTEL                      0x0040  /* INPPGAMUTEL */
+#define WM8985_INPPGAMUTEL_MASK                 0x0040  /* INPPGAMUTEL */
+#define WM8985_INPPGAMUTEL_SHIFT                     6  /* INPPGAMUTEL */
+#define WM8985_INPPGAMUTEL_WIDTH                     1  /* INPPGAMUTEL */
+#define WM8985_INPPGAVOLL_MASK                  0x003F  /* INPPGAVOLL - [5:0] */
+#define WM8985_INPPGAVOLL_SHIFT                      0  /* INPPGAVOLL - [5:0] */
+#define WM8985_INPPGAVOLL_WIDTH                      6  /* INPPGAVOLL - [5:0] */
+
+/*
+ * R46 (0x2E) - Right INP PGA gain ctrl
+ */
+#define WM8985_INPGAVU                          0x0100  /* INPGAVU */
+#define WM8985_INPGAVU_MASK                     0x0100  /* INPGAVU */
+#define WM8985_INPGAVU_SHIFT                         8  /* INPGAVU */
+#define WM8985_INPGAVU_WIDTH                         1  /* INPGAVU */
+#define WM8985_INPPGAZCR                        0x0080  /* INPPGAZCR */
+#define WM8985_INPPGAZCR_MASK                   0x0080  /* INPPGAZCR */
+#define WM8985_INPPGAZCR_SHIFT                       7  /* INPPGAZCR */
+#define WM8985_INPPGAZCR_WIDTH                       1  /* INPPGAZCR */
+#define WM8985_INPPGAMUTER                      0x0040  /* INPPGAMUTER */
+#define WM8985_INPPGAMUTER_MASK                 0x0040  /* INPPGAMUTER */
+#define WM8985_INPPGAMUTER_SHIFT                     6  /* INPPGAMUTER */
+#define WM8985_INPPGAMUTER_WIDTH                     1  /* INPPGAMUTER */
+#define WM8985_INPPGAVOLR_MASK                  0x003F  /* INPPGAVOLR - [5:0] */
+#define WM8985_INPPGAVOLR_SHIFT                      0  /* INPPGAVOLR - [5:0] */
+#define WM8985_INPPGAVOLR_WIDTH                      6  /* INPPGAVOLR - [5:0] */
+
+/*
+ * R47 (0x2F) - Left ADC BOOST ctrl
+ */
+#define WM8985_PGABOOSTL                        0x0100  /* PGABOOSTL */
+#define WM8985_PGABOOSTL_MASK                   0x0100  /* PGABOOSTL */
+#define WM8985_PGABOOSTL_SHIFT                       8  /* PGABOOSTL */
+#define WM8985_PGABOOSTL_WIDTH                       1  /* PGABOOSTL */
+#define WM8985_L2_2BOOSTVOL_MASK                0x0070  /* L2_2BOOSTVOL - [6:4] */
+#define WM8985_L2_2BOOSTVOL_SHIFT                    4  /* L2_2BOOSTVOL - [6:4] */
+#define WM8985_L2_2BOOSTVOL_WIDTH                    3  /* L2_2BOOSTVOL - [6:4] */
+#define WM8985_AUXL2BOOSTVOL_MASK               0x0007  /* AUXL2BOOSTVOL - [2:0] */
+#define WM8985_AUXL2BOOSTVOL_SHIFT                   0  /* AUXL2BOOSTVOL - [2:0] */
+#define WM8985_AUXL2BOOSTVOL_WIDTH                   3  /* AUXL2BOOSTVOL - [2:0] */
+
+/*
+ * R48 (0x30) - Right ADC BOOST ctrl
+ */
+#define WM8985_PGABOOSTR                        0x0100  /* PGABOOSTR */
+#define WM8985_PGABOOSTR_MASK                   0x0100  /* PGABOOSTR */
+#define WM8985_PGABOOSTR_SHIFT                       8  /* PGABOOSTR */
+#define WM8985_PGABOOSTR_WIDTH                       1  /* PGABOOSTR */
+#define WM8985_R2_2BOOSTVOL_MASK                0x0070  /* R2_2BOOSTVOL - [6:4] */
+#define WM8985_R2_2BOOSTVOL_SHIFT                    4  /* R2_2BOOSTVOL - [6:4] */
+#define WM8985_R2_2BOOSTVOL_WIDTH                    3  /* R2_2BOOSTVOL - [6:4] */
+#define WM8985_AUXR2BOOSTVOL_MASK               0x0007  /* AUXR2BOOSTVOL - [2:0] */
+#define WM8985_AUXR2BOOSTVOL_SHIFT                   0  /* AUXR2BOOSTVOL - [2:0] */
+#define WM8985_AUXR2BOOSTVOL_WIDTH                   3  /* AUXR2BOOSTVOL - [2:0] */
+
+/*
+ * R49 (0x31) - Output ctrl
+ */
+#define WM8985_DACL2RMIX                        0x0040  /* DACL2RMIX */
+#define WM8985_DACL2RMIX_MASK                   0x0040  /* DACL2RMIX */
+#define WM8985_DACL2RMIX_SHIFT                       6  /* DACL2RMIX */
+#define WM8985_DACL2RMIX_WIDTH                       1  /* DACL2RMIX */
+#define WM8985_DACR2LMIX                        0x0020  /* DACR2LMIX */
+#define WM8985_DACR2LMIX_MASK                   0x0020  /* DACR2LMIX */
+#define WM8985_DACR2LMIX_SHIFT                       5  /* DACR2LMIX */
+#define WM8985_DACR2LMIX_WIDTH                       1  /* DACR2LMIX */
+#define WM8985_OUT4BOOST                        0x0010  /* OUT4BOOST */
+#define WM8985_OUT4BOOST_MASK                   0x0010  /* OUT4BOOST */
+#define WM8985_OUT4BOOST_SHIFT                       4  /* OUT4BOOST */
+#define WM8985_OUT4BOOST_WIDTH                       1  /* OUT4BOOST */
+#define WM8985_OUT3BOOST                        0x0008  /* OUT3BOOST */
+#define WM8985_OUT3BOOST_MASK                   0x0008  /* OUT3BOOST */
+#define WM8985_OUT3BOOST_SHIFT                       3  /* OUT3BOOST */
+#define WM8985_OUT3BOOST_WIDTH                       1  /* OUT3BOOST */
+#define WM8985_TSOPCTRL                         0x0004  /* TSOPCTRL */
+#define WM8985_TSOPCTRL_MASK                    0x0004  /* TSOPCTRL */
+#define WM8985_TSOPCTRL_SHIFT                        2  /* TSOPCTRL */
+#define WM8985_TSOPCTRL_WIDTH                        1  /* TSOPCTRL */
+#define WM8985_TSDEN                            0x0002  /* TSDEN */
+#define WM8985_TSDEN_MASK                       0x0002  /* TSDEN */
+#define WM8985_TSDEN_SHIFT                           1  /* TSDEN */
+#define WM8985_TSDEN_WIDTH                           1  /* TSDEN */
+#define WM8985_VROI                             0x0001  /* VROI */
+#define WM8985_VROI_MASK                        0x0001  /* VROI */
+#define WM8985_VROI_SHIFT                            0  /* VROI */
+#define WM8985_VROI_WIDTH                            1  /* VROI */
+
+/*
+ * R50 (0x32) - Left mixer ctrl
+ */
+#define WM8985_AUXLMIXVOL_MASK                  0x01C0  /* AUXLMIXVOL - [8:6] */
+#define WM8985_AUXLMIXVOL_SHIFT                      6  /* AUXLMIXVOL - [8:6] */
+#define WM8985_AUXLMIXVOL_WIDTH                      3  /* AUXLMIXVOL - [8:6] */
+#define WM8985_AUXL2LMIX                        0x0020  /* AUXL2LMIX */
+#define WM8985_AUXL2LMIX_MASK                   0x0020  /* AUXL2LMIX */
+#define WM8985_AUXL2LMIX_SHIFT                       5  /* AUXL2LMIX */
+#define WM8985_AUXL2LMIX_WIDTH                       1  /* AUXL2LMIX */
+#define WM8985_BYPLMIXVOL_MASK                  0x001C  /* BYPLMIXVOL - [4:2] */
+#define WM8985_BYPLMIXVOL_SHIFT                      2  /* BYPLMIXVOL - [4:2] */
+#define WM8985_BYPLMIXVOL_WIDTH                      3  /* BYPLMIXVOL - [4:2] */
+#define WM8985_BYPL2LMIX                        0x0002  /* BYPL2LMIX */
+#define WM8985_BYPL2LMIX_MASK                   0x0002  /* BYPL2LMIX */
+#define WM8985_BYPL2LMIX_SHIFT                       1  /* BYPL2LMIX */
+#define WM8985_BYPL2LMIX_WIDTH                       1  /* BYPL2LMIX */
+#define WM8985_DACL2LMIX                        0x0001  /* DACL2LMIX */
+#define WM8985_DACL2LMIX_MASK                   0x0001  /* DACL2LMIX */
+#define WM8985_DACL2LMIX_SHIFT                       0  /* DACL2LMIX */
+#define WM8985_DACL2LMIX_WIDTH                       1  /* DACL2LMIX */
+
+/*
+ * R51 (0x33) - Right mixer ctrl
+ */
+#define WM8985_AUXRMIXVOL_MASK                  0x01C0  /* AUXRMIXVOL - [8:6] */
+#define WM8985_AUXRMIXVOL_SHIFT                      6  /* AUXRMIXVOL - [8:6] */
+#define WM8985_AUXRMIXVOL_WIDTH                      3  /* AUXRMIXVOL - [8:6] */
+#define WM8985_AUXR2RMIX                        0x0020  /* AUXR2RMIX */
+#define WM8985_AUXR2RMIX_MASK                   0x0020  /* AUXR2RMIX */
+#define WM8985_AUXR2RMIX_SHIFT                       5  /* AUXR2RMIX */
+#define WM8985_AUXR2RMIX_WIDTH                       1  /* AUXR2RMIX */
+#define WM8985_BYPRMIXVOL_MASK                  0x001C  /* BYPRMIXVOL - [4:2] */
+#define WM8985_BYPRMIXVOL_SHIFT                      2  /* BYPRMIXVOL - [4:2] */
+#define WM8985_BYPRMIXVOL_WIDTH                      3  /* BYPRMIXVOL - [4:2] */
+#define WM8985_BYPR2RMIX                        0x0002  /* BYPR2RMIX */
+#define WM8985_BYPR2RMIX_MASK                   0x0002  /* BYPR2RMIX */
+#define WM8985_BYPR2RMIX_SHIFT                       1  /* BYPR2RMIX */
+#define WM8985_BYPR2RMIX_WIDTH                       1  /* BYPR2RMIX */
+#define WM8985_DACR2RMIX                        0x0001  /* DACR2RMIX */
+#define WM8985_DACR2RMIX_MASK                   0x0001  /* DACR2RMIX */
+#define WM8985_DACR2RMIX_SHIFT                       0  /* DACR2RMIX */
+#define WM8985_DACR2RMIX_WIDTH                       1  /* DACR2RMIX */
+
+/*
+ * R52 (0x34) - LOUT1 (HP) volume ctrl
+ */
+#define WM8985_OUT1VU                           0x0100  /* OUT1VU */
+#define WM8985_OUT1VU_MASK                      0x0100  /* OUT1VU */
+#define WM8985_OUT1VU_SHIFT                          8  /* OUT1VU */
+#define WM8985_OUT1VU_WIDTH                          1  /* OUT1VU */
+#define WM8985_LOUT1ZC                          0x0080  /* LOUT1ZC */
+#define WM8985_LOUT1ZC_MASK                     0x0080  /* LOUT1ZC */
+#define WM8985_LOUT1ZC_SHIFT                         7  /* LOUT1ZC */
+#define WM8985_LOUT1ZC_WIDTH                         1  /* LOUT1ZC */
+#define WM8985_LOUT1MUTE                        0x0040  /* LOUT1MUTE */
+#define WM8985_LOUT1MUTE_MASK                   0x0040  /* LOUT1MUTE */
+#define WM8985_LOUT1MUTE_SHIFT                       6  /* LOUT1MUTE */
+#define WM8985_LOUT1MUTE_WIDTH                       1  /* LOUT1MUTE */
+#define WM8985_LOUT1VOL_MASK                    0x003F  /* LOUT1VOL - [5:0] */
+#define WM8985_LOUT1VOL_SHIFT                        0  /* LOUT1VOL - [5:0] */
+#define WM8985_LOUT1VOL_WIDTH                        6  /* LOUT1VOL - [5:0] */
+
+/*
+ * R53 (0x35) - ROUT1 (HP) volume ctrl
+ */
+#define WM8985_OUT1VU                           0x0100  /* OUT1VU */
+#define WM8985_OUT1VU_MASK                      0x0100  /* OUT1VU */
+#define WM8985_OUT1VU_SHIFT                          8  /* OUT1VU */
+#define WM8985_OUT1VU_WIDTH                          1  /* OUT1VU */
+#define WM8985_ROUT1ZC                          0x0080  /* ROUT1ZC */
+#define WM8985_ROUT1ZC_MASK                     0x0080  /* ROUT1ZC */
+#define WM8985_ROUT1ZC_SHIFT                         7  /* ROUT1ZC */
+#define WM8985_ROUT1ZC_WIDTH                         1  /* ROUT1ZC */
+#define WM8985_ROUT1MUTE                        0x0040  /* ROUT1MUTE */
+#define WM8985_ROUT1MUTE_MASK                   0x0040  /* ROUT1MUTE */
+#define WM8985_ROUT1MUTE_SHIFT                       6  /* ROUT1MUTE */
+#define WM8985_ROUT1MUTE_WIDTH                       1  /* ROUT1MUTE */
+#define WM8985_ROUT1VOL_MASK                    0x003F  /* ROUT1VOL - [5:0] */
+#define WM8985_ROUT1VOL_SHIFT                        0  /* ROUT1VOL - [5:0] */
+#define WM8985_ROUT1VOL_WIDTH                        6  /* ROUT1VOL - [5:0] */
+
+/*
+ * R54 (0x36) - LOUT2 (SPK) volume ctrl
+ */
+#define WM8985_OUT2VU                           0x0100  /* OUT2VU */
+#define WM8985_OUT2VU_MASK                      0x0100  /* OUT2VU */
+#define WM8985_OUT2VU_SHIFT                          8  /* OUT2VU */
+#define WM8985_OUT2VU_WIDTH                          1  /* OUT2VU */
+#define WM8985_LOUT2ZC                          0x0080  /* LOUT2ZC */
+#define WM8985_LOUT2ZC_MASK                     0x0080  /* LOUT2ZC */
+#define WM8985_LOUT2ZC_SHIFT                         7  /* LOUT2ZC */
+#define WM8985_LOUT2ZC_WIDTH                         1  /* LOUT2ZC */
+#define WM8985_LOUT2MUTE                        0x0040  /* LOUT2MUTE */
+#define WM8985_LOUT2MUTE_MASK                   0x0040  /* LOUT2MUTE */
+#define WM8985_LOUT2MUTE_SHIFT                       6  /* LOUT2MUTE */
+#define WM8985_LOUT2MUTE_WIDTH                       1  /* LOUT2MUTE */
+#define WM8985_LOUT2VOL_MASK                    0x003F  /* LOUT2VOL - [5:0] */
+#define WM8985_LOUT2VOL_SHIFT                        0  /* LOUT2VOL - [5:0] */
+#define WM8985_LOUT2VOL_WIDTH                        6  /* LOUT2VOL - [5:0] */
+
+/*
+ * R55 (0x37) - ROUT2 (SPK) volume ctrl
+ */
+#define WM8985_OUT2VU                           0x0100  /* OUT2VU */
+#define WM8985_OUT2VU_MASK                      0x0100  /* OUT2VU */
+#define WM8985_OUT2VU_SHIFT                          8  /* OUT2VU */
+#define WM8985_OUT2VU_WIDTH                          1  /* OUT2VU */
+#define WM8985_ROUT2ZC                          0x0080  /* ROUT2ZC */
+#define WM8985_ROUT2ZC_MASK                     0x0080  /* ROUT2ZC */
+#define WM8985_ROUT2ZC_SHIFT                         7  /* ROUT2ZC */
+#define WM8985_ROUT2ZC_WIDTH                         1  /* ROUT2ZC */
+#define WM8985_ROUT2MUTE                        0x0040  /* ROUT2MUTE */
+#define WM8985_ROUT2MUTE_MASK                   0x0040  /* ROUT2MUTE */
+#define WM8985_ROUT2MUTE_SHIFT                       6  /* ROUT2MUTE */
+#define WM8985_ROUT2MUTE_WIDTH                       1  /* ROUT2MUTE */
+#define WM8985_ROUT2VOL_MASK                    0x003F  /* ROUT2VOL - [5:0] */
+#define WM8985_ROUT2VOL_SHIFT                        0  /* ROUT2VOL - [5:0] */
+#define WM8985_ROUT2VOL_WIDTH                        6  /* ROUT2VOL - [5:0] */
+
+/*
+ * R56 (0x38) - OUT3 mixer ctrl
+ */
+#define WM8985_OUT3MUTE                         0x0040  /* OUT3MUTE */
+#define WM8985_OUT3MUTE_MASK                    0x0040  /* OUT3MUTE */
+#define WM8985_OUT3MUTE_SHIFT                        6  /* OUT3MUTE */
+#define WM8985_OUT3MUTE_WIDTH                        1  /* OUT3MUTE */
+#define WM8985_OUT4_2OUT3                       0x0008  /* OUT4_2OUT3 */
+#define WM8985_OUT4_2OUT3_MASK                  0x0008  /* OUT4_2OUT3 */
+#define WM8985_OUT4_2OUT3_SHIFT                      3  /* OUT4_2OUT3 */
+#define WM8985_OUT4_2OUT3_WIDTH                      1  /* OUT4_2OUT3 */
+#define WM8985_BYPL2OUT3                        0x0004  /* BYPL2OUT3 */
+#define WM8985_BYPL2OUT3_MASK                   0x0004  /* BYPL2OUT3 */
+#define WM8985_BYPL2OUT3_SHIFT                       2  /* BYPL2OUT3 */
+#define WM8985_BYPL2OUT3_WIDTH                       1  /* BYPL2OUT3 */
+#define WM8985_LMIX2OUT3                        0x0002  /* LMIX2OUT3 */
+#define WM8985_LMIX2OUT3_MASK                   0x0002  /* LMIX2OUT3 */
+#define WM8985_LMIX2OUT3_SHIFT                       1  /* LMIX2OUT3 */
+#define WM8985_LMIX2OUT3_WIDTH                       1  /* LMIX2OUT3 */
+#define WM8985_LDAC2OUT3                        0x0001  /* LDAC2OUT3 */
+#define WM8985_LDAC2OUT3_MASK                   0x0001  /* LDAC2OUT3 */
+#define WM8985_LDAC2OUT3_SHIFT                       0  /* LDAC2OUT3 */
+#define WM8985_LDAC2OUT3_WIDTH                       1  /* LDAC2OUT3 */
+
+/*
+ * R57 (0x39) - OUT4 (MONO) mix ctrl
+ */
+#define WM8985_OUT3_2OUT4                       0x0080  /* OUT3_2OUT4 */
+#define WM8985_OUT3_2OUT4_MASK                  0x0080  /* OUT3_2OUT4 */
+#define WM8985_OUT3_2OUT4_SHIFT                      7  /* OUT3_2OUT4 */
+#define WM8985_OUT3_2OUT4_WIDTH                      1  /* OUT3_2OUT4 */
+#define WM8985_OUT4MUTE                         0x0040  /* OUT4MUTE */
+#define WM8985_OUT4MUTE_MASK                    0x0040  /* OUT4MUTE */
+#define WM8985_OUT4MUTE_SHIFT                        6  /* OUT4MUTE */
+#define WM8985_OUT4MUTE_WIDTH                        1  /* OUT4MUTE */
+#define WM8985_OUT4ATTN                         0x0020  /* OUT4ATTN */
+#define WM8985_OUT4ATTN_MASK                    0x0020  /* OUT4ATTN */
+#define WM8985_OUT4ATTN_SHIFT                        5  /* OUT4ATTN */
+#define WM8985_OUT4ATTN_WIDTH                        1  /* OUT4ATTN */
+#define WM8985_LMIX2OUT4                        0x0010  /* LMIX2OUT4 */
+#define WM8985_LMIX2OUT4_MASK                   0x0010  /* LMIX2OUT4 */
+#define WM8985_LMIX2OUT4_SHIFT                       4  /* LMIX2OUT4 */
+#define WM8985_LMIX2OUT4_WIDTH                       1  /* LMIX2OUT4 */
+#define WM8985_LDAC2OUT4                        0x0008  /* LDAC2OUT4 */
+#define WM8985_LDAC2OUT4_MASK                   0x0008  /* LDAC2OUT4 */
+#define WM8985_LDAC2OUT4_SHIFT                       3  /* LDAC2OUT4 */
+#define WM8985_LDAC2OUT4_WIDTH                       1  /* LDAC2OUT4 */
+#define WM8985_BYPR2OUT4                        0x0004  /* BYPR2OUT4 */
+#define WM8985_BYPR2OUT4_MASK                   0x0004  /* BYPR2OUT4 */
+#define WM8985_BYPR2OUT4_SHIFT                       2  /* BYPR2OUT4 */
+#define WM8985_BYPR2OUT4_WIDTH                       1  /* BYPR2OUT4 */
+#define WM8985_RMIX2OUT4                        0x0002  /* RMIX2OUT4 */
+#define WM8985_RMIX2OUT4_MASK                   0x0002  /* RMIX2OUT4 */
+#define WM8985_RMIX2OUT4_SHIFT                       1  /* RMIX2OUT4 */
+#define WM8985_RMIX2OUT4_WIDTH                       1  /* RMIX2OUT4 */
+#define WM8985_RDAC2OUT4                        0x0001  /* RDAC2OUT4 */
+#define WM8985_RDAC2OUT4_MASK                   0x0001  /* RDAC2OUT4 */
+#define WM8985_RDAC2OUT4_SHIFT                       0  /* RDAC2OUT4 */
+#define WM8985_RDAC2OUT4_WIDTH                       1  /* RDAC2OUT4 */
+
+/*
+ * R60 (0x3C) - OUTPUT ctrl
+ */
+#define WM8985_VIDBUFFTST_MASK                  0x01E0  /* VIDBUFFTST - [8:5] */
+#define WM8985_VIDBUFFTST_SHIFT                      5  /* VIDBUFFTST - [8:5] */
+#define WM8985_VIDBUFFTST_WIDTH                      4  /* VIDBUFFTST - [8:5] */
+#define WM8985_HPTOG                            0x0008  /* HPTOG */
+#define WM8985_HPTOG_MASK                       0x0008  /* HPTOG */
+#define WM8985_HPTOG_SHIFT                           3  /* HPTOG */
+#define WM8985_HPTOG_WIDTH                           1  /* HPTOG */
+
+/*
+ * R61 (0x3D) - BIAS CTRL
+ */
+#define WM8985_BIASCUT                          0x0100  /* BIASCUT */
+#define WM8985_BIASCUT_MASK                     0x0100  /* BIASCUT */
+#define WM8985_BIASCUT_SHIFT                         8  /* BIASCUT */
+#define WM8985_BIASCUT_WIDTH                         1  /* BIASCUT */
+#define WM8985_HALFIPBIAS                       0x0080  /* HALFIPBIAS */
+#define WM8985_HALFIPBIAS_MASK                  0x0080  /* HALFIPBIAS */
+#define WM8985_HALFIPBIAS_SHIFT                      7  /* HALFIPBIAS */
+#define WM8985_HALFIPBIAS_WIDTH                      1  /* HALFIPBIAS */
+#define WM8985_VBBIASTST_MASK                   0x0060  /* VBBIASTST - [6:5] */
+#define WM8985_VBBIASTST_SHIFT                       5  /* VBBIASTST - [6:5] */
+#define WM8985_VBBIASTST_WIDTH                       2  /* VBBIASTST - [6:5] */
+#define WM8985_BUFBIAS_MASK                     0x0018  /* BUFBIAS - [4:3] */
+#define WM8985_BUFBIAS_SHIFT                         3  /* BUFBIAS - [4:3] */
+#define WM8985_BUFBIAS_WIDTH                         2  /* BUFBIAS - [4:3] */
+#define WM8985_ADCBIAS_MASK                     0x0006  /* ADCBIAS - [2:1] */
+#define WM8985_ADCBIAS_SHIFT                         1  /* ADCBIAS - [2:1] */
+#define WM8985_ADCBIAS_WIDTH                         2  /* ADCBIAS - [2:1] */
+#define WM8985_HALFOPBIAS                       0x0001  /* HALFOPBIAS */
+#define WM8985_HALFOPBIAS_MASK                  0x0001  /* HALFOPBIAS */
+#define WM8985_HALFOPBIAS_SHIFT                      0  /* HALFOPBIAS */
+#define WM8985_HALFOPBIAS_WIDTH                      1  /* HALFOPBIAS */
+
+enum clk_src {
+        WM8985_CLKSRC_MCLK,
+        WM8985_CLKSRC_PLL
+};
+
+#define WM8985_PLL 0
+
+#endif
diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c
index 19ad590ca0b3..d7170f1381aa 100644
--- a/sound/soc/codecs/wm8988.c
+++ b/sound/soc/codecs/wm8988.c
@@ -25,7 +25,6 @@
 #include <sound/pcm_params.h>
 #include <sound/tlv.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 
 #include "wm8988.h"
@@ -52,9 +51,8 @@ static const u16 wm8988_reg[] = {
 /* codec private data */
 struct wm8988_priv {
         unsigned int sysclk;
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
         struct snd_pcm_hw_constraint_list *sysclk_constraints;
-        u16 reg_cache[WM8988_NUM_REG];
 };
 
 
@@ -608,8 +606,7 @@ static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
                                 struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
         u16 iface = snd_soc_read(codec, WM8988_IFACE) & 0x1f3;
         u16 srate = snd_soc_read(codec, WM8988_SRATE) & 0x180;
@@ -678,7 +675,7 @@ static int wm8988_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* VREF, VMID=2x5k */
                         snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1);
 
@@ -694,7 +691,7 @@ static int wm8988_set_bias_level(struct snd_soc_codec *codec,
                 snd_soc_write(codec, WM8988_PWR1, 0x0000);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -711,8 +708,8 @@ static struct snd_soc_dai_ops wm8988_ops = {
         .digital_mute = wm8988_mute,
 };
 
-struct snd_soc_dai wm8988_dai = {
-        .name = "WM8988",
+static struct snd_soc_dai_driver wm8988_dai = {
+        .name = "wm8988-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -730,21 +727,15 @@ struct snd_soc_dai wm8988_dai = {
         .ops = &wm8988_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8988_dai);
 
-static int wm8988_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8988_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8988_resume(struct platform_device *pdev)
+static int wm8988_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -763,99 +754,23 @@ static int wm8988_resume(struct platform_device *pdev)
         return 0;
 }
 
-static struct snd_soc_codec *wm8988_codec;
-
-static int wm8988_probe(struct platform_device *pdev)
+static int wm8988_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
+        struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
         int ret = 0;
-
-        if (wm8988_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
-
-        socdev->card->codec = wm8988_codec;
-        codec = wm8988_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
-        }
-
-        snd_soc_add_controls(codec, wm8988_snd_controls,
-                                ARRAY_SIZE(wm8988_snd_controls));
-        snd_soc_dapm_new_controls(codec, wm8988_dapm_widgets,
-                                  ARRAY_SIZE(wm8988_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
-
-        return ret;
-
-pcm_err:
-        return ret;
-}
-
-static int wm8988_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8988 = {
-        .probe =        wm8988_probe,
-        .remove =       wm8988_remove,
-        .suspend =      wm8988_suspend,
-        .resume =       wm8988_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8988);
-
-static int wm8988_register(struct wm8988_priv *wm8988,
-                           enum snd_soc_control_type control)
-{
-        struct snd_soc_codec *codec = &wm8988->codec;
-        int ret;
         u16 reg;
 
-        if (wm8988_codec) {
-                dev_err(codec->dev, "Another WM8988 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm8988);
-        codec->name = "WM8988";
-        codec->owner = THIS_MODULE;
-        codec->dai = &wm8988_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(wm8988->reg_cache);
-        codec->reg_cache = &wm8988->reg_cache;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8988_set_bias_level;
-
-        memcpy(codec->reg_cache, wm8988_reg,
-               sizeof(wm8988_reg));
-
-        ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
+        ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8988->control_type);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
+                return ret;
         }
 
         ret = wm8988_reset(codec);
         if (ret < 0) {
                 dev_err(codec->dev, "Failed to issue reset\n");
-                goto err;
+                return ret;
         }
 
         /* set the update bits (we always update left then right) */
@@ -870,139 +785,132 @@ static int wm8988_register(struct wm8988_priv *wm8988,
         reg = snd_soc_read(codec, WM8988_RINVOL);
         snd_soc_write(codec, WM8988_RINVOL, reg | 0x0100);
 
-        wm8988_set_bias_level(&wm8988->codec, SND_SOC_BIAS_STANDBY);
-
-        wm8988_dai.dev = codec->dev;
-
-        wm8988_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
+        wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
-        ret = snd_soc_register_dai(&wm8988_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
+        snd_soc_add_controls(codec, wm8988_snd_controls,
+                                ARRAY_SIZE(wm8988_snd_controls));
+        snd_soc_dapm_new_controls(dapm, wm8988_dapm_widgets,
+                                  ARRAY_SIZE(wm8988_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
-
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm8988);
-        return ret;
 }
 
-static void wm8988_unregister(struct wm8988_priv *wm8988)
+static int wm8988_remove(struct snd_soc_codec *codec)
 {
-        wm8988_set_bias_level(&wm8988->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm8988_dai);
-        snd_soc_unregister_codec(&wm8988->codec);
-        kfree(wm8988);
-        wm8988_codec = NULL;
+        wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-static int wm8988_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+static struct snd_soc_codec_driver soc_codec_dev_wm8988 = {
+        .probe =        wm8988_probe,
+        .remove =       wm8988_remove,
+        .suspend =      wm8988_suspend,
+        .resume =       wm8988_resume,
+        .set_bias_level = wm8988_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8988_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8988_reg,
+};
+
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8988_spi_probe(struct spi_device *spi)
 {
         struct wm8988_priv *wm8988;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
         if (wm8988 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8988->codec;
-
-        i2c_set_clientdata(i2c, wm8988);
-        codec->control_data = i2c;
-
-        codec->dev = &i2c->dev;
+        wm8988->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8988);
 
-        return wm8988_register(wm8988, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&spi->dev,
+                        &soc_codec_dev_wm8988, &wm8988_dai, 1);
+        if (ret < 0)
+                kfree(wm8988);
+        return ret;
 }
 
-static int wm8988_i2c_remove(struct i2c_client *client)
+static int __devexit wm8988_spi_remove(struct spi_device *spi)
 {
-        struct wm8988_priv *wm8988 = i2c_get_clientdata(client);
-        wm8988_unregister(wm8988);
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
         return 0;
 }
 
-static const struct i2c_device_id wm8988_i2c_id[] = {
-        { "wm8988", 0 },
-        { }
-};
-MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
-
-static struct i2c_driver wm8988_i2c_driver = {
+static struct spi_driver wm8988_spi_driver = {
         .driver = {
-                .name = "WM8988",
-                .owner = THIS_MODULE,
+                .name   = "wm8988-codec",
+                .owner  = THIS_MODULE,
         },
-        .probe = wm8988_i2c_probe,
-        .remove = wm8988_i2c_remove,
-        .id_table = wm8988_i2c_id,
+        .probe          = wm8988_spi_probe,
+        .remove         = __devexit_p(wm8988_spi_remove),
 };
-#endif
+#endif /* CONFIG_SPI_MASTER */
 
-#if defined(CONFIG_SPI_MASTER)
-static int __devinit wm8988_spi_probe(struct spi_device *spi)
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8988_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
         struct wm8988_priv *wm8988;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
         if (wm8988 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8988->codec;
-        codec->control_data = spi;
-        codec->dev = &spi->dev;
-
-        dev_set_drvdata(&spi->dev, wm8988);
+        i2c_set_clientdata(i2c, wm8988);
+        wm8988->control_type = SND_SOC_I2C;
 
-        return wm8988_register(wm8988, SND_SOC_SPI);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8988, &wm8988_dai, 1);
+        if (ret < 0)
+                kfree(wm8988);
+        return ret;
 }
 
-static int __devexit wm8988_spi_remove(struct spi_device *spi)
+static __devexit int wm8988_i2c_remove(struct i2c_client *client)
 {
-        struct wm8988_priv *wm8988 = dev_get_drvdata(&spi->dev);
-
-        wm8988_unregister(wm8988);
-
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
-static struct spi_driver wm8988_spi_driver = {
+static const struct i2c_device_id wm8988_i2c_id[] = {
+        { "wm8988", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
+
+static struct i2c_driver wm8988_i2c_driver = {
         .driver = {
-                .name   = "wm8988",
-                .bus    = &spi_bus_type,
-                .owner  = THIS_MODULE,
+                .name = "wm8988-codec",
+                .owner = THIS_MODULE,
         },
-        .probe          = wm8988_spi_probe,
-        .remove         = __devexit_p(wm8988_spi_remove),
+        .probe =    wm8988_i2c_probe,
+        .remove =   __devexit_p(wm8988_i2c_remove),
+        .id_table = wm8988_i2c_id,
 };
 #endif
 
 static int __init wm8988_modinit(void)
 {
-        int ret;
-
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8988_i2c_driver);
-        if (ret != 0)
-                pr_err("WM8988: Unable to register I2C driver: %d\n", ret);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8988 I2C driver: %d\n",
+                       ret);
+        }
 #endif
 #if defined(CONFIG_SPI_MASTER)
         ret = spi_register_driver(&wm8988_spi_driver);
-        if (ret != 0)
-                pr_err("WM8988: Unable to register SPI driver: %d\n", ret);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8988 SPI driver: %d\n",
+                       ret);
+        }
 #endif
         return ret;
 }
diff --git a/sound/soc/codecs/wm8988.h b/sound/soc/codecs/wm8988.h
index 4552d37fdd41..5c04024e5f9f 100644
--- a/sound/soc/codecs/wm8988.h
+++ b/sound/soc/codecs/wm8988.h
@@ -54,7 +54,4 @@
 
 #define WM8988_SYSCLK   0
 
-extern struct snd_soc_dai wm8988_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8988;
-
 #endif
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
index dd8d909788c1..100aeee5ba96 100644
--- a/sound/soc/codecs/wm8990.c
+++ b/sound/soc/codecs/wm8990.c
@@ -23,7 +23,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 #include <asm/div64.h>
@@ -32,6 +31,7 @@
 
 /* codec private data */
 struct wm8990_priv {
+        enum snd_soc_control_type control_type;
         unsigned int sysclk;
         unsigned int pcmclk;
 };
@@ -913,11 +913,12 @@ static const struct snd_soc_dapm_route audio_map[] = {
 
 static int wm8990_add_widgets(struct snd_soc_codec *codec)
 {
-        snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets,
-                                  ARRAY_SIZE(wm8990_dapm_widgets));
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
 
+        snd_soc_dapm_new_controls(dapm, wm8990_dapm_widgets,
+                                  ARRAY_SIZE(wm8990_dapm_widgets));
         /* set up the WM8990 audio map */
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         return 0;
 }
@@ -1114,8 +1115,7 @@ static int wm8990_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
 
         audio1 &= ~WM8990_AIF_WL_MASK;
@@ -1170,7 +1170,7 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Enable all output discharge bits */
                         snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
                                 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
@@ -1183,7 +1183,7 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
                                      WM8990_VMIDTOG);
 
                         /* Delay to allow output caps to discharge */
-                        msleep(msecs_to_jiffies(300));
+                        msleep(300);
 
                         /* Disable VMIDTOG */
                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
@@ -1195,17 +1195,17 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
                         /* Enable outputs */
                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
 
-                        msleep(msecs_to_jiffies(50));
+                        msleep(50);
 
                         /* Enable VMID at 2x50k */
                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
 
-                        msleep(msecs_to_jiffies(100));
+                        msleep(100);
 
                         /* Enable VREF */
                         snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
 
-                        msleep(msecs_to_jiffies(600));
+                        msleep(600);
 
                         /* Enable BUFIOEN */
                         snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
@@ -1250,7 +1250,7 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
                 /* Disable VMID */
                 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
 
-                msleep(msecs_to_jiffies(300));
+                msleep(300);
 
                 /* Enable all output discharge bits */
                 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
@@ -1266,7 +1266,7 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -1293,10 +1293,9 @@ static struct snd_soc_dai_ops wm8990_dai_ops = {
         .set_sysclk     = wm8990_set_dai_sysclk,
 };
 
-struct snd_soc_dai wm8990_dai = {
+static struct snd_soc_dai_driver wm8990_dai = {
 /* ADC/DAC on primary */
-        .name = "WM8990 ADC/DAC Primary",
-        .id = 1,
+        .name = "wm8990-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -1311,21 +1310,15 @@ struct snd_soc_dai wm8990_dai = {
                 .formats = WM8990_FORMATS,},
         .ops = &wm8990_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm8990_dai);
 
-static int wm8990_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8990_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm8990_resume(struct platform_device *pdev)
+static int wm8990_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i;
         u8 data[2];
         u16 *cache = codec->reg_cache;
@@ -1347,40 +1340,20 @@ static int wm8990_resume(struct platform_device *pdev)
  * initialise the WM8990 driver
  * register the mixer and dsp interfaces with the kernel
  */
-static int wm8990_init(struct snd_soc_device *socdev)
+static int wm8990_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_codec *codec = socdev->card->codec;
+        int ret;
         u16 reg;
-        int ret = 0;
-
-        codec->name = "WM8990";
-        codec->owner = THIS_MODULE;
-        codec->set_bias_level = wm8990_set_bias_level;
-        codec->dai = &wm8990_dai;
-        codec->num_dai = 2;
-        codec->reg_cache_size = ARRAY_SIZE(wm8990_reg);
-        codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL);
-
-        if (codec->reg_cache == NULL)
-                return -ENOMEM;
 
         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
         if (ret < 0) {
                 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret);
-                goto pcm_err;
+                return ret;
         }
 
         wm8990_reset(codec);
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                printk(KERN_ERR "wm8990: failed to create pcms\n");
-                goto pcm_err;
-        }
-
         /* charge output caps */
-        codec->bias_level = SND_SOC_BIAS_OFF;
         wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4);
@@ -1400,47 +1373,51 @@ static int wm8990_init(struct snd_soc_device *socdev)
                                 ARRAY_SIZE(wm8990_snd_controls));
         wm8990_add_widgets(codec);
 
-        return ret;
+        return 0;
+}
 
-pcm_err:
-        kfree(codec->reg_cache);
-        return ret;
+/* power down chip */
+static int wm8990_remove(struct snd_soc_codec *codec)
+{
+        wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
 }
 
-/* If the i2c layer weren't so broken, we could pass this kind of data
-   around */
-static struct snd_soc_device *wm8990_socdev;
+static struct snd_soc_codec_driver soc_codec_dev_wm8990 = {
+        .probe =        wm8990_probe,
+        .remove =       wm8990_remove,
+        .suspend =      wm8990_suspend,
+        .resume =       wm8990_resume,
+        .set_bias_level = wm8990_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8990_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8990_reg,
+};
 
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-
-/*
- * WM891 2 wire address is determined by GPIO5
- * state during powerup.
- *    low  = 0x34
- *    high = 0x36
- */
-
-static int wm8990_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+static __devinit int wm8990_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
-        struct snd_soc_device *socdev = wm8990_socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct wm8990_priv *wm8990;
         int ret;
 
-        i2c_set_clientdata(i2c, codec);
-        codec->control_data = i2c;
+        wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
+        if (wm8990 == NULL)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, wm8990);
 
-        ret = wm8990_init(socdev);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8990, &wm8990_dai, 1);
         if (ret < 0)
-                pr_err("failed to initialise WM8990\n");
-
+                kfree(wm8990);
         return ret;
 }
 
-static int wm8990_i2c_remove(struct i2c_client *client)
+static __devexit int wm8990_i2c_remove(struct i2c_client *client)
 {
-        struct snd_soc_codec *codec = i2c_get_clientdata(client);
-        kfree(codec->reg_cache);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -1452,134 +1429,34 @@ MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
 
 static struct i2c_driver wm8990_i2c_driver = {
         .driver = {
-                .name = "WM8990 I2C Codec",
+                .name = "wm8990-codec",
                 .owner = THIS_MODULE,
         },
         .probe =    wm8990_i2c_probe,
-        .remove =   wm8990_i2c_remove,
+        .remove =   __devexit_p(wm8990_i2c_remove),
         .id_table = wm8990_i2c_id,
 };
-
-static int wm8990_add_i2c_device(struct platform_device *pdev,
-                                 const struct wm8990_setup_data *setup)
-{
-        struct i2c_board_info info;
-        struct i2c_adapter *adapter;
-        struct i2c_client *client;
-        int ret;
-
-        ret = i2c_add_driver(&wm8990_i2c_driver);
-        if (ret != 0) {
-                dev_err(&pdev->dev, "can't add i2c driver\n");
-                return ret;
-        }
-
-        memset(&info, 0, sizeof(struct i2c_board_info));
-        info.addr = setup->i2c_address;
-        strlcpy(info.type, "wm8990", I2C_NAME_SIZE);
-
-        adapter = i2c_get_adapter(setup->i2c_bus);
-        if (!adapter) {
-                dev_err(&pdev->dev, "can't get i2c adapter %d\n",
-                        setup->i2c_bus);
-                goto err_driver;
-        }
-
-        client = i2c_new_device(adapter, &info);
-        i2c_put_adapter(adapter);
-        if (!client) {
-                dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
-                        (unsigned int)info.addr);
-                goto err_driver;
-        }
-
-        return 0;
-
-err_driver:
-        i2c_del_driver(&wm8990_i2c_driver);
-        return -ENODEV;
-}
 #endif
 
-static int wm8990_probe(struct platform_device *pdev)
+static int __init wm8990_modinit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct wm8990_setup_data *setup;
-        struct snd_soc_codec *codec;
-        struct wm8990_priv *wm8990;
-        int ret;
-
-        setup = socdev->codec_data;
-        codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
-        if (codec == NULL)
-                return -ENOMEM;
-
-        wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
-        if (wm8990 == NULL) {
-                kfree(codec);
-                return -ENOMEM;
-        }
-
-        snd_soc_codec_set_drvdata(codec, wm8990);
-        socdev->card->codec = codec;
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-        wm8990_socdev = socdev;
-
-        ret = -ENODEV;
-
+        int ret = 0;
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        if (setup->i2c_address) {
-                codec->hw_write = (hw_write_t)i2c_master_send;
-                ret = wm8990_add_i2c_device(pdev, setup);
-        }
-#endif
-
+        ret = i2c_add_driver(&wm8990_i2c_driver);
         if (ret != 0) {
-                kfree(snd_soc_codec_get_drvdata(codec));
-                kfree(codec);
+                printk(KERN_ERR "Failed to register wm8990 I2C driver: %d\n",
+                       ret);
         }
+#endif
         return ret;
 }
+module_init(wm8990_modinit);
 
-/* power down chip */
-static int wm8990_remove(struct platform_device *pdev)
+static void __exit wm8990_exit(void)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec->control_data)
-                wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-        i2c_unregister_device(codec->control_data);
         i2c_del_driver(&wm8990_i2c_driver);
 #endif
-        kfree(snd_soc_codec_get_drvdata(codec));
-        kfree(codec);
-
-        return 0;
-}
-
-struct snd_soc_codec_device soc_codec_dev_wm8990 = {
-        .probe =        wm8990_probe,
-        .remove =       wm8990_remove,
-        .suspend =      wm8990_suspend,
-        .resume =       wm8990_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990);
-
-static int __init wm8990_modinit(void)
-{
-        return snd_soc_register_dai(&wm8990_dai);
-}
-module_init(wm8990_modinit);
-
-static void __exit wm8990_exit(void)
-{
-        snd_soc_unregister_dai(&wm8990_dai);
 }
 module_exit(wm8990_exit);
 
diff --git a/sound/soc/codecs/wm8990.h b/sound/soc/codecs/wm8990.h
index 7114ddc88b4b..77c98a4bfe9c 100644
--- a/sound/soc/codecs/wm8990.h
+++ b/sound/soc/codecs/wm8990.h
@@ -826,18 +826,10 @@
 #define WM8990_INMIXR_PWR_BIT                   2
 #define WM8990_AINRMUX_PWR_BIT                  3
 
-struct wm8990_setup_data {
-        unsigned i2c_bus;
-        unsigned short i2c_address;
-};
-
 #define WM8990_MCLK_DIV 0
 #define WM8990_DACCLK_DIV 1
 #define WM8990_ADCCLK_DIV 2
 #define WM8990_BCLK_DIV 3
 
-extern struct snd_soc_dai wm8990_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8990;
-
 #endif  /* __WM8990REGISTERDEFS_H__ */
 /*------------------------------ END OF FILE ---------------------------------*/
diff --git a/sound/soc/codecs/wm8991.c b/sound/soc/codecs/wm8991.c
new file mode 100644
index 000000000000..6af23d06870f
--- /dev/null
+++ b/sound/soc/codecs/wm8991.c
@@ -0,0 +1,1426 @@
+/*
+ * wm8991.c  --  WM8991 ALSA Soc Audio driver
+ *
+ * Copyright 2007-2010 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory
+ *         linux@wolfsonmicro.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <asm/div64.h>
+
+#include "wm8991.h"
+
+struct wm8991_priv {
+        enum snd_soc_control_type control_type;
+        unsigned int pcmclk;
+};
+
+static const u16 wm8991_reg_defs[] = {
+        0x8991,     /* R0  - Reset */
+        0x0000,     /* R1  - Power Management (1) */
+        0x6000,     /* R2  - Power Management (2) */
+        0x0000,     /* R3  - Power Management (3) */
+        0x4050,     /* R4  - Audio Interface (1) */
+        0x4000,     /* R5  - Audio Interface (2) */
+        0x01C8,     /* R6  - Clocking (1) */
+        0x0000,     /* R7  - Clocking (2) */
+        0x0040,     /* R8  - Audio Interface (3) */
+        0x0040,     /* R9  - Audio Interface (4) */
+        0x0004,     /* R10 - DAC CTRL */
+        0x00C0,     /* R11 - Left DAC Digital Volume */
+        0x00C0,     /* R12 - Right DAC Digital Volume */
+        0x0000,     /* R13 - Digital Side Tone */
+        0x0100,     /* R14 - ADC CTRL */
+        0x00C0,     /* R15 - Left ADC Digital Volume */
+        0x00C0,     /* R16 - Right ADC Digital Volume */
+        0x0000,     /* R17 */
+        0x0000,     /* R18 - GPIO CTRL 1 */
+        0x1000,     /* R19 - GPIO1 & GPIO2 */
+        0x1010,     /* R20 - GPIO3 & GPIO4 */
+        0x1010,     /* R21 - GPIO5 & GPIO6 */
+        0x8000,     /* R22 - GPIOCTRL 2 */
+        0x0800,     /* R23 - GPIO_POL */
+        0x008B,     /* R24 - Left Line Input 1&2 Volume */
+        0x008B,     /* R25 - Left Line Input 3&4 Volume */
+        0x008B,     /* R26 - Right Line Input 1&2 Volume */
+        0x008B,     /* R27 - Right Line Input 3&4 Volume */
+        0x0000,     /* R28 - Left Output Volume */
+        0x0000,     /* R29 - Right Output Volume */
+        0x0066,     /* R30 - Line Outputs Volume */
+        0x0022,     /* R31 - Out3/4 Volume */
+        0x0079,     /* R32 - Left OPGA Volume */
+        0x0079,     /* R33 - Right OPGA Volume */
+        0x0003,     /* R34 - Speaker Volume */
+        0x0003,     /* R35 - ClassD1 */
+        0x0000,     /* R36 */
+        0x0100,     /* R37 - ClassD3 */
+        0x0000,     /* R38 */
+        0x0000,     /* R39 - Input Mixer1 */
+        0x0000,     /* R40 - Input Mixer2 */
+        0x0000,     /* R41 - Input Mixer3 */
+        0x0000,     /* R42 - Input Mixer4 */
+        0x0000,     /* R43 - Input Mixer5 */
+        0x0000,     /* R44 - Input Mixer6 */
+        0x0000,     /* R45 - Output Mixer1 */
+        0x0000,     /* R46 - Output Mixer2 */
+        0x0000,     /* R47 - Output Mixer3 */
+        0x0000,     /* R48 - Output Mixer4 */
+        0x0000,     /* R49 - Output Mixer5 */
+        0x0000,     /* R50 - Output Mixer6 */
+        0x0180,     /* R51 - Out3/4 Mixer */
+        0x0000,     /* R52 - Line Mixer1 */
+        0x0000,     /* R53 - Line Mixer2 */
+        0x0000,     /* R54 - Speaker Mixer */
+        0x0000,     /* R55 - Additional Control */
+        0x0000,     /* R56 - AntiPOP1 */
+        0x0000,     /* R57 - AntiPOP2 */
+        0x0000,     /* R58 - MICBIAS */
+        0x0000,     /* R59 */
+        0x0008,     /* R60 - PLL1 */
+        0x0031,     /* R61 - PLL2 */
+        0x0026,     /* R62 - PLL3 */
+};
+
+#define wm8991_reset(c) snd_soc_write(c, WM8991_RESET, 0)
+
+static const unsigned int rec_mix_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 7, TLV_DB_LINEAR_ITEM(-1500, 600),
+};
+
+static const unsigned int in_pga_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 0x1F, TLV_DB_LINEAR_ITEM(-1650, 3000),
+};
+
+static const unsigned int out_mix_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 7, TLV_DB_LINEAR_ITEM(0, -2100),
+};
+
+static const unsigned int out_pga_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 127, TLV_DB_LINEAR_ITEM(-7300, 600),
+};
+
+static const unsigned int out_omix_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 7, TLV_DB_LINEAR_ITEM(-600, 0),
+};
+
+static const unsigned int out_dac_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 255, TLV_DB_LINEAR_ITEM(-7163, 0),
+};
+
+static const unsigned int in_adc_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 255, TLV_DB_LINEAR_ITEM(-7163, 1763),
+};
+
+static const unsigned int out_sidetone_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 31, TLV_DB_LINEAR_ITEM(-3600, 0),
+};
+
+static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
+                                      struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        int reg = kcontrol->private_value & 0xff;
+        int ret;
+        u16 val;
+
+        ret = snd_soc_put_volsw(kcontrol, ucontrol);
+        if (ret < 0)
+                return ret;
+
+        /* now hit the volume update bits (always bit 8) */
+        val = snd_soc_read(codec, reg);
+        return snd_soc_write(codec, reg, val | 0x0100);
+}
+
+static const char *wm8991_digital_sidetone[] =
+{"None", "Left ADC", "Right ADC", "Reserved"};
+
+static const struct soc_enum wm8991_left_digital_sidetone_enum =
+        SOC_ENUM_SINGLE(WM8991_DIGITAL_SIDE_TONE,
+                        WM8991_ADC_TO_DACL_SHIFT,
+                        WM8991_ADC_TO_DACL_MASK,
+                        wm8991_digital_sidetone);
+
+static const struct soc_enum wm8991_right_digital_sidetone_enum =
+        SOC_ENUM_SINGLE(WM8991_DIGITAL_SIDE_TONE,
+                        WM8991_ADC_TO_DACR_SHIFT,
+                        WM8991_ADC_TO_DACR_MASK,
+                        wm8991_digital_sidetone);
+
+static const char *wm8991_adcmode[] =
+{"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
+
+static const struct soc_enum wm8991_right_adcmode_enum =
+        SOC_ENUM_SINGLE(WM8991_ADC_CTRL,
+                        WM8991_ADC_HPF_CUT_SHIFT,
+                        WM8991_ADC_HPF_CUT_MASK,
+                        wm8991_adcmode);
+
+static const struct snd_kcontrol_new wm8991_snd_controls[] = {
+        /* INMIXL */
+        SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0),
+        SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0),
+        /* INMIXR */
+        SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0),
+        SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0),
+
+        /* LOMIX */
+        SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3,
+                WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
+                WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
+                WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5,
+                WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
+                WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
+                WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
+
+        /* ROMIX */
+        SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4,
+                WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
+                WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
+                WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6,
+                WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
+                WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv),
+        SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
+                WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv),
+
+        /* LOUT */
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME,
+                WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv),
+        SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0),
+
+        /* ROUT */
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME,
+                WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv),
+        SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0),
+
+        /* LOPGA */
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME,
+                WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv),
+        SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME,
+                WM8991_LOPGAZC_BIT, 1, 0),
+
+        /* ROPGA */
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME,
+                WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv),
+        SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME,
+                WM8991_ROPGAZC_BIT, 1, 0),
+
+        SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
+                WM8991_LONMUTE_BIT, 1, 0),
+        SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
+                WM8991_LOPMUTE_BIT, 1, 0),
+        SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
+                WM8991_LOATTN_BIT, 1, 0),
+        SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
+                WM8991_RONMUTE_BIT, 1, 0),
+        SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
+                WM8991_ROPMUTE_BIT, 1, 0),
+        SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
+                WM8991_ROATTN_BIT, 1, 0),
+
+        SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME,
+                WM8991_OUT3MUTE_BIT, 1, 0),
+        SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME,
+                WM8991_OUT3ATTN_BIT, 1, 0),
+
+        SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME,
+                WM8991_OUT4MUTE_BIT, 1, 0),
+        SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME,
+                WM8991_OUT4ATTN_BIT, 1, 0),
+
+        SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1,
+                WM8991_CDMODE_BIT, 1, 0),
+
+        SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME,
+                WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0),
+        SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3,
+                WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0),
+        SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3,
+                WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0),
+
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
+                WM8991_LEFT_DAC_DIGITAL_VOLUME,
+                WM8991_DACL_VOL_SHIFT,
+                WM8991_DACL_VOL_MASK,
+                0,
+                out_dac_tlv),
+
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
+                WM8991_RIGHT_DAC_DIGITAL_VOLUME,
+                WM8991_DACR_VOL_SHIFT,
+                WM8991_DACR_VOL_MASK,
+                0,
+                out_dac_tlv),
+
+        SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum),
+        SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum),
+
+        SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
+                WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0,
+                out_sidetone_tlv),
+        SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
+                WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0,
+                out_sidetone_tlv),
+
+        SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL,
+                WM8991_ADC_HPF_ENA_BIT, 1, 0),
+
+        SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum),
+
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
+                WM8991_LEFT_ADC_DIGITAL_VOLUME,
+                WM8991_ADCL_VOL_SHIFT,
+                WM8991_ADCL_VOL_MASK,
+                0,
+                in_adc_tlv),
+
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
+                WM8991_RIGHT_ADC_DIGITAL_VOLUME,
+                WM8991_ADCR_VOL_SHIFT,
+                WM8991_ADCR_VOL_MASK,
+                0,
+                in_adc_tlv),
+
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
+                WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
+                WM8991_LIN12VOL_SHIFT,
+                WM8991_LIN12VOL_MASK,
+                0,
+                in_pga_tlv),
+
+        SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
+                WM8991_LI12ZC_BIT, 1, 0),
+
+        SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
+                WM8991_LI12MUTE_BIT, 1, 0),
+
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
+                WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
+                WM8991_LIN34VOL_SHIFT,
+                WM8991_LIN34VOL_MASK,
+                0,
+                in_pga_tlv),
+
+        SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
+                WM8991_LI34ZC_BIT, 1, 0),
+
+        SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
+                WM8991_LI34MUTE_BIT, 1, 0),
+
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
+                WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
+                WM8991_RIN12VOL_SHIFT,
+                WM8991_RIN12VOL_MASK,
+                0,
+                in_pga_tlv),
+
+        SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
+                WM8991_RI12ZC_BIT, 1, 0),
+
+        SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
+                WM8991_RI12MUTE_BIT, 1, 0),
+
+        SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
+                WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
+                WM8991_RIN34VOL_SHIFT,
+                WM8991_RIN34VOL_MASK,
+                0,
+                in_pga_tlv),
+
+        SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
+                WM8991_RI34ZC_BIT, 1, 0),
+
+        SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
+                WM8991_RI34MUTE_BIT, 1, 0),
+};
+
+/*
+ * _DAPM_ Controls
+ */
+static int inmixer_event(struct snd_soc_dapm_widget *w,
+                         struct snd_kcontrol *kcontrol, int event)
+{
+        u16 reg, fakepower;
+
+        reg = snd_soc_read(w->codec, WM8991_POWER_MANAGEMENT_2);
+        fakepower = snd_soc_read(w->codec, WM8991_INTDRIVBITS);
+
+        if (fakepower & ((1 << WM8991_INMIXL_PWR_BIT) |
+                         (1 << WM8991_AINLMUX_PWR_BIT)))
+                reg |= WM8991_AINL_ENA;
+        else
+                reg &= ~WM8991_AINL_ENA;
+
+        if (fakepower & ((1 << WM8991_INMIXR_PWR_BIT) |
+                         (1 << WM8991_AINRMUX_PWR_BIT)))
+                reg |= WM8991_AINR_ENA;
+        else
+                reg &= ~WM8991_AINL_ENA;
+
+        snd_soc_write(w->codec, WM8991_POWER_MANAGEMENT_2, reg);
+        return 0;
+}
+
+static int outmixer_event(struct snd_soc_dapm_widget *w,
+                          struct snd_kcontrol *kcontrol, int event)
+{
+        u32 reg_shift = kcontrol->private_value & 0xfff;
+        int ret = 0;
+        u16 reg;
+
+        switch (reg_shift) {
+        case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8):
+                reg = snd_soc_read(w->codec, WM8991_OUTPUT_MIXER1);
+                if (reg & WM8991_LDLO) {
+                        printk(KERN_WARNING
+                               "Cannot set as Output Mixer 1 LDLO Set\n");
+                        ret = -1;
+                }
+                break;
+
+        case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8):
+                reg = snd_soc_read(w->codec, WM8991_OUTPUT_MIXER2);
+                if (reg & WM8991_RDRO) {
+                        printk(KERN_WARNING
+                               "Cannot set as Output Mixer 2 RDRO Set\n");
+                        ret = -1;
+                }
+                break;
+
+        case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8):
+                reg = snd_soc_read(w->codec, WM8991_SPEAKER_MIXER);
+                if (reg & WM8991_LDSPK) {
+                        printk(KERN_WARNING
+                               "Cannot set as Speaker Mixer LDSPK Set\n");
+                        ret = -1;
+                }
+                break;
+
+        case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8):
+                reg = snd_soc_read(w->codec, WM8991_SPEAKER_MIXER);
+                if (reg & WM8991_RDSPK) {
+                        printk(KERN_WARNING
+                               "Cannot set as Speaker Mixer RDSPK Set\n");
+                        ret = -1;
+                }
+                break;
+        }
+
+        return ret;
+}
+
+/* INMIX dB values */
+static const unsigned int in_mix_tlv[] = {
+        TLV_DB_RANGE_HEAD(1),
+        0, 7, TLV_DB_LINEAR_ITEM(-1200, 600),
+};
+
+/* Left In PGA Connections */
+static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = {
+        SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = {
+        SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0),
+};
+
+/* Right In PGA Connections */
+static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = {
+        SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0),
+        SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = {
+        SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0),
+        SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0),
+};
+
+/* INMIXL */
+static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = {
+        SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3,
+                WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv),
+        SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT,
+                7, 0, in_mix_tlv),
+        SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
+                1, 0),
+        SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
+                1, 0),
+};
+
+/* INMIXR */
+static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = {
+        SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4,
+                WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv),
+        SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT,
+                7, 0, in_mix_tlv),
+        SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
+                1, 0),
+        SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
+                1, 0),
+};
+
+/* AINLMUX */
+static const char *wm8991_ainlmux[] =
+{"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
+
+static const struct soc_enum wm8991_ainlmux_enum =
+        SOC_ENUM_SINGLE(WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT,
+                        ARRAY_SIZE(wm8991_ainlmux), wm8991_ainlmux);
+
+static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls =
+        SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum);
+
+/* DIFFINL */
+
+/* AINRMUX */
+static const char *wm8991_ainrmux[] =
+{"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
+
+static const struct soc_enum wm8991_ainrmux_enum =
+        SOC_ENUM_SINGLE(WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT,
+                        ARRAY_SIZE(wm8991_ainrmux), wm8991_ainrmux);
+
+static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls =
+        SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum);
+
+/* RXVOICE */
+static const struct snd_kcontrol_new wm8991_dapm_rxvoice_controls[] = {
+        SOC_DAPM_SINGLE_TLV("LIN4RXN", WM8991_INPUT_MIXER5, WM8991_LR4BVOL_SHIFT,
+                WM8991_LR4BVOL_MASK, 0, in_mix_tlv),
+        SOC_DAPM_SINGLE_TLV("RIN4RXP", WM8991_INPUT_MIXER6, WM8991_RL4BVOL_SHIFT,
+                WM8991_RL4BVOL_MASK, 0, in_mix_tlv),
+};
+
+/* LOMIX */
+static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = {
+        SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
+                WM8991_LRBLO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
+                WM8991_LLBLO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
+                WM8991_LRI3LO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
+                WM8991_LLI3LO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
+                WM8991_LR12LO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
+                WM8991_LL12LO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1,
+                WM8991_LDLO_BIT, 1, 0),
+};
+
+/* ROMIX */
+static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = {
+        SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
+                WM8991_RLBRO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
+                WM8991_RRBRO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
+                WM8991_RLI3RO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
+                WM8991_RRI3RO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
+                WM8991_RL12RO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
+                WM8991_RR12RO_BIT, 1, 0),
+        SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2,
+                WM8991_RDRO_BIT, 1, 0),
+};
+
+/* LONMIX */
+static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = {
+        SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
+                WM8991_LLOPGALON_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1,
+                WM8991_LROPGALON_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1,
+                WM8991_LOPLON_BIT, 1, 0),
+};
+
+/* LOPMIX */
+static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = {
+        SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1,
+                WM8991_LR12LOP_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1,
+                WM8991_LL12LOP_BIT, 1, 0),
+        SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
+                WM8991_LLOPGALOP_BIT, 1, 0),
+};
+
+/* RONMIX */
+static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = {
+        SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
+                WM8991_RROPGARON_BIT, 1, 0),
+        SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2,
+                WM8991_RLOPGARON_BIT, 1, 0),
+        SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2,
+                WM8991_ROPRON_BIT, 1, 0),
+};
+
+/* ROPMIX */
+static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = {
+        SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2,
+                WM8991_RL12ROP_BIT, 1, 0),
+        SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2,
+                WM8991_RR12ROP_BIT, 1, 0),
+        SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
+                WM8991_RROPGAROP_BIT, 1, 0),
+};
+
+/* OUT3MIX */
+static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = {
+        SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER,
+                WM8991_LI4O3_BIT, 1, 0),
+        SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER,
+                WM8991_LPGAO3_BIT, 1, 0),
+};
+
+/* OUT4MIX */
+static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = {
+        SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER,
+                WM8991_RPGAO4_BIT, 1, 0),
+        SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER,
+                WM8991_RI4O4_BIT, 1, 0),
+};
+
+/* SPKMIX */
+static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = {
+        SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
+                WM8991_LI2SPK_BIT, 1, 0),
+        SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER,
+                WM8991_LB2SPK_BIT, 1, 0),
+        SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER,
+                WM8991_LOPGASPK_BIT, 1, 0),
+        SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER,
+                WM8991_LDSPK_BIT, 1, 0),
+        SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER,
+                WM8991_RDSPK_BIT, 1, 0),
+        SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER,
+                WM8991_ROPGASPK_BIT, 1, 0),
+        SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER,
+                WM8991_RL12ROP_BIT, 1, 0),
+        SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
+                WM8991_RI2SPK_BIT, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = {
+        /* Input Side */
+        /* Input Lines */
+        SND_SOC_DAPM_INPUT("LIN1"),
+        SND_SOC_DAPM_INPUT("LIN2"),
+        SND_SOC_DAPM_INPUT("LIN3"),
+        SND_SOC_DAPM_INPUT("LIN4RXN"),
+        SND_SOC_DAPM_INPUT("RIN3"),
+        SND_SOC_DAPM_INPUT("RIN4RXP"),
+        SND_SOC_DAPM_INPUT("RIN1"),
+        SND_SOC_DAPM_INPUT("RIN2"),
+        SND_SOC_DAPM_INPUT("Internal ADC Source"),
+
+        /* DACs */
+        SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2,
+                WM8991_ADCL_ENA_BIT, 0),
+        SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2,
+                WM8991_ADCR_ENA_BIT, 0),
+
+        /* Input PGAs */
+        SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT,
+                0, &wm8991_dapm_lin12_pga_controls[0],
+                ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)),
+        SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT,
+                0, &wm8991_dapm_lin34_pga_controls[0],
+                ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)),
+        SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT,
+                0, &wm8991_dapm_rin12_pga_controls[0],
+                ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)),
+        SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT,
+                0, &wm8991_dapm_rin34_pga_controls[0],
+                ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)),
+
+        /* INMIXL */
+        SND_SOC_DAPM_MIXER_E("INMIXL", WM8991_INTDRIVBITS, WM8991_INMIXL_PWR_BIT, 0,
+                &wm8991_dapm_inmixl_controls[0],
+                ARRAY_SIZE(wm8991_dapm_inmixl_controls),
+                inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+        /* AINLMUX */
+        SND_SOC_DAPM_MUX_E("AINLMUX", WM8991_INTDRIVBITS, WM8991_AINLMUX_PWR_BIT, 0,
+                &wm8991_dapm_ainlmux_controls, inmixer_event,
+                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+        /* INMIXR */
+        SND_SOC_DAPM_MIXER_E("INMIXR", WM8991_INTDRIVBITS, WM8991_INMIXR_PWR_BIT, 0,
+                &wm8991_dapm_inmixr_controls[0],
+                ARRAY_SIZE(wm8991_dapm_inmixr_controls),
+                inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+        /* AINRMUX */
+        SND_SOC_DAPM_MUX_E("AINRMUX", WM8991_INTDRIVBITS, WM8991_AINRMUX_PWR_BIT, 0,
+                &wm8991_dapm_ainrmux_controls, inmixer_event,
+                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+        /* Output Side */
+        /* DACs */
+        SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3,
+                WM8991_DACL_ENA_BIT, 0),
+        SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3,
+                WM8991_DACR_ENA_BIT, 0),
+
+        /* LOMIX */
+        SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT,
+                0, &wm8991_dapm_lomix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_lomix_controls),
+                outmixer_event, SND_SOC_DAPM_PRE_REG),
+
+        /* LONMIX */
+        SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0,
+                &wm8991_dapm_lonmix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_lonmix_controls)),
+
+        /* LOPMIX */
+        SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0,
+                &wm8991_dapm_lopmix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_lopmix_controls)),
+
+        /* OUT3MIX */
+        SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0,
+                &wm8991_dapm_out3mix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_out3mix_controls)),
+
+        /* SPKMIX */
+        SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0,
+                &wm8991_dapm_spkmix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event,
+                SND_SOC_DAPM_PRE_REG),
+
+        /* OUT4MIX */
+        SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0,
+                &wm8991_dapm_out4mix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_out4mix_controls)),
+
+        /* ROPMIX */
+        SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0,
+                &wm8991_dapm_ropmix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_ropmix_controls)),
+
+        /* RONMIX */
+        SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0,
+                &wm8991_dapm_ronmix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_ronmix_controls)),
+
+        /* ROMIX */
+        SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT,
+                0, &wm8991_dapm_romix_controls[0],
+                ARRAY_SIZE(wm8991_dapm_romix_controls),
+                outmixer_event, SND_SOC_DAPM_PRE_REG),
+
+        /* LOUT PGA */
+        SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0,
+                NULL, 0),
+
+        /* ROUT PGA */
+        SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0,
+                NULL, 0),
+
+        /* LOPGA */
+        SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0,
+                NULL, 0),
+
+        /* ROPGA */
+        SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0,
+                NULL, 0),
+
+        /* MICBIAS */
+        SND_SOC_DAPM_MICBIAS("MICBIAS", WM8991_POWER_MANAGEMENT_1,
+                WM8991_MICBIAS_ENA_BIT, 0),
+
+        SND_SOC_DAPM_OUTPUT("LON"),
+        SND_SOC_DAPM_OUTPUT("LOP"),
+        SND_SOC_DAPM_OUTPUT("OUT3"),
+        SND_SOC_DAPM_OUTPUT("LOUT"),
+        SND_SOC_DAPM_OUTPUT("SPKN"),
+        SND_SOC_DAPM_OUTPUT("SPKP"),
+        SND_SOC_DAPM_OUTPUT("ROUT"),
+        SND_SOC_DAPM_OUTPUT("OUT4"),
+        SND_SOC_DAPM_OUTPUT("ROP"),
+        SND_SOC_DAPM_OUTPUT("RON"),
+        SND_SOC_DAPM_OUTPUT("OUT"),
+
+        SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+        /* Make DACs turn on when playing even if not mixed into any outputs */
+        {"Internal DAC Sink", NULL, "Left DAC"},
+        {"Internal DAC Sink", NULL, "Right DAC"},
+
+        /* Make ADCs turn on when recording even if not mixed from any inputs */
+        {"Left ADC", NULL, "Internal ADC Source"},
+        {"Right ADC", NULL, "Internal ADC Source"},
+
+        /* Input Side */
+        /* LIN12 PGA */
+        {"LIN12 PGA", "LIN1 Switch", "LIN1"},
+        {"LIN12 PGA", "LIN2 Switch", "LIN2"},
+        /* LIN34 PGA */
+        {"LIN34 PGA", "LIN3 Switch", "LIN3"},
+        {"LIN34 PGA", "LIN4 Switch", "LIN4RXN"},
+        /* INMIXL */
+        {"INMIXL", "Record Left Volume", "LOMIX"},
+        {"INMIXL", "LIN2 Volume", "LIN2"},
+        {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
+        {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
+        /* AINLMUX */
+        {"AINLMUX", "INMIXL Mix", "INMIXL"},
+        {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
+        {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
+        {"AINLMUX", "RXVOICE Mix", "LIN4RXN"},
+        {"AINLMUX", "RXVOICE Mix", "RIN4RXP"},
+        /* ADC */
+        {"Left ADC", NULL, "AINLMUX"},
+
+        /* RIN12 PGA */
+        {"RIN12 PGA", "RIN1 Switch", "RIN1"},
+        {"RIN12 PGA", "RIN2 Switch", "RIN2"},
+        /* RIN34 PGA */
+        {"RIN34 PGA", "RIN3 Switch", "RIN3"},
+        {"RIN34 PGA", "RIN4 Switch", "RIN4RXP"},
+        /* INMIXL */
+        {"INMIXR", "Record Right Volume", "ROMIX"},
+        {"INMIXR", "RIN2 Volume", "RIN2"},
+        {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
+        {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
+        /* AINRMUX */
+        {"AINRMUX", "INMIXR Mix", "INMIXR"},
+        {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
+        {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
+        {"AINRMUX", "RXVOICE Mix", "LIN4RXN"},
+        {"AINRMUX", "RXVOICE Mix", "RIN4RXP"},
+        /* ADC */
+        {"Right ADC", NULL, "AINRMUX"},
+
+        /* LOMIX */
+        {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
+        {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
+        {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
+        {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
+        {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
+        {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
+        {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
+
+        /* ROMIX */
+        {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
+        {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
+        {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
+        {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
+        {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
+        {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
+        {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
+
+        /* SPKMIX */
+        {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
+        {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
+        {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
+        {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
+        {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
+        {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
+        {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
+        {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
+
+        /* LONMIX */
+        {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
+        {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
+        {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
+
+        /* LOPMIX */
+        {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
+        {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
+        {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
+
+        /* OUT3MIX */
+        {"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"},
+        {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
+
+        /* OUT4MIX */
+        {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
+        {"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"},
+
+        /* RONMIX */
+        {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
+        {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
+        {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
+
+        /* ROPMIX */
+        {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
+        {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
+        {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
+
+        /* Out Mixer PGAs */
+        {"LOPGA", NULL, "LOMIX"},
+        {"ROPGA", NULL, "ROMIX"},
+
+        {"LOUT PGA", NULL, "LOMIX"},
+        {"ROUT PGA", NULL, "ROMIX"},
+
+        /* Output Pins */
+        {"LON", NULL, "LONMIX"},
+        {"LOP", NULL, "LOPMIX"},
+        {"OUT", NULL, "OUT3MIX"},
+        {"LOUT", NULL, "LOUT PGA"},
+        {"SPKN", NULL, "SPKMIX"},
+        {"ROUT", NULL, "ROUT PGA"},
+        {"OUT4", NULL, "OUT4MIX"},
+        {"ROP", NULL, "ROPMIX"},
+        {"RON", NULL, "RONMIX"},
+};
+
+/* PLL divisors */
+struct _pll_div {
+        u32 div2;
+        u32 n;
+        u32 k;
+};
+
+/* The size in bits of the pll divide multiplied by 10
+ * to allow rounding later */
+#define FIXED_PLL_SIZE ((1 << 16) * 10)
+
+static void pll_factors(struct _pll_div *pll_div, unsigned int target,
+                        unsigned int source)
+{
+        u64 Kpart;
+        unsigned int K, Ndiv, Nmod;
+
+
+        Ndiv = target / source;
+        if (Ndiv < 6) {
+                source >>= 1;
+                pll_div->div2 = 1;
+                Ndiv = target / source;
+        } else
+                pll_div->div2 = 0;
+
+        if ((Ndiv < 6) || (Ndiv > 12))
+                printk(KERN_WARNING
+                       "WM8991 N value outwith recommended range! N = %d\n", Ndiv);
+
+        pll_div->n = Ndiv;
+        Nmod = target % source;
+        Kpart = FIXED_PLL_SIZE * (long long)Nmod;
+
+        do_div(Kpart, source);
+
+        K = Kpart & 0xFFFFFFFF;
+
+        /* Check if we need to round */
+        if ((K % 10) >= 5)
+                K += 5;
+
+        /* Move down to proper range now rounding is done */
+        K /= 10;
+
+        pll_div->k = K;
+}
+
+static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai,
+                              int pll_id, int src, unsigned int freq_in, unsigned int freq_out)
+{
+        u16 reg;
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct _pll_div pll_div;
+
+        if (freq_in && freq_out) {
+                pll_factors(&pll_div, freq_out * 4, freq_in);
+
+                /* Turn on PLL */
+                reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2);
+                reg |= WM8991_PLL_ENA;
+                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg);
+
+                /* sysclk comes from PLL */
+                reg = snd_soc_read(codec, WM8991_CLOCKING_2);
+                snd_soc_write(codec, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC);
+
+                /* set up N , fractional mode and pre-divisor if necessary */
+                snd_soc_write(codec, WM8991_PLL1, pll_div.n | WM8991_SDM |
+                              (pll_div.div2 ? WM8991_PRESCALE : 0));
+                snd_soc_write(codec, WM8991_PLL2, (u8)(pll_div.k>>8));
+                snd_soc_write(codec, WM8991_PLL3, (u8)(pll_div.k & 0xFF));
+        } else {
+                /* Turn on PLL */
+                reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2);
+                reg &= ~WM8991_PLL_ENA;
+                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg);
+        }
+        return 0;
+}
+
+/*
+ * Set's ADC and Voice DAC format.
+ */
+static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                              unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        u16 audio1, audio3;
+
+        audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1);
+        audio3 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_3);
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBS_CFS:
+                audio3 &= ~WM8991_AIF_MSTR1;
+                break;
+        case SND_SOC_DAIFMT_CBM_CFM:
+                audio3 |= WM8991_AIF_MSTR1;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        audio1 &= ~WM8991_AIF_FMT_MASK;
+
+        /* interface format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                audio1 |= WM8991_AIF_TMF_I2S;
+                audio1 &= ~WM8991_AIF_LRCLK_INV;
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                audio1 |= WM8991_AIF_TMF_RIGHTJ;
+                audio1 &= ~WM8991_AIF_LRCLK_INV;
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                audio1 |= WM8991_AIF_TMF_LEFTJ;
+                audio1 &= ~WM8991_AIF_LRCLK_INV;
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+                audio1 |= WM8991_AIF_TMF_DSP;
+                audio1 &= ~WM8991_AIF_LRCLK_INV;
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1);
+        snd_soc_write(codec, WM8991_AUDIO_INTERFACE_3, audio3);
+        return 0;
+}
+
+static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
+                                 int div_id, int div)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        u16 reg;
+
+        switch (div_id) {
+        case WM8991_MCLK_DIV:
+                reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
+                      ~WM8991_MCLK_DIV_MASK;
+                snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
+                break;
+        case WM8991_DACCLK_DIV:
+                reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
+                      ~WM8991_DAC_CLKDIV_MASK;
+                snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
+                break;
+        case WM8991_ADCCLK_DIV:
+                reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
+                      ~WM8991_ADC_CLKDIV_MASK;
+                snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
+                break;
+        case WM8991_BCLK_DIV:
+                reg = snd_soc_read(codec, WM8991_CLOCKING_1) &
+                      ~WM8991_BCLK_DIV_MASK;
+                snd_soc_write(codec, WM8991_CLOCKING_1, reg | div);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+/*
+ * Set PCM DAI bit size and sample rate.
+ */
+static int wm8991_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        u16 audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1);
+
+        audio1 &= ~WM8991_AIF_WL_MASK;
+        /* bit size */
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                audio1 |= WM8991_AIF_WL_20BITS;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                audio1 |= WM8991_AIF_WL_24BITS;
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                audio1 |= WM8991_AIF_WL_32BITS;
+                break;
+        }
+
+        snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1);
+        return 0;
+}
+
+static int wm8991_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        u16 val;
+
+        val  = snd_soc_read(codec, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE;
+        if (mute)
+                snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
+        else
+                snd_soc_write(codec, WM8991_DAC_CTRL, val);
+        return 0;
+}
+
+static int wm8991_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        u16 val;
+
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+                break;
+
+        case SND_SOC_BIAS_PREPARE:
+                /* VMID=2*50k */
+                val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) &
+                      ~WM8991_VMID_MODE_MASK;
+                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x2);
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        snd_soc_cache_sync(codec);
+                        /* Enable all output discharge bits */
+                        snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
+                                      WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
+                                      WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
+                                      WM8991_DIS_ROUT);
+
+                        /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
+                        snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
+                                      WM8991_BUFDCOPEN | WM8991_POBCTRL |
+                                      WM8991_VMIDTOG);
+
+                        /* Delay to allow output caps to discharge */
+                        msleep(300);
+
+                        /* Disable VMIDTOG */
+                        snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
+                                      WM8991_BUFDCOPEN | WM8991_POBCTRL);
+
+                        /* disable all output discharge bits */
+                        snd_soc_write(codec, WM8991_ANTIPOP1, 0);
+
+                        /* Enable outputs */
+                        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1b00);
+
+                        msleep(50);
+
+                        /* Enable VMID at 2x50k */
+                        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f02);
+
+                        msleep(100);
+
+                        /* Enable VREF */
+                        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03);
+
+                        msleep(600);
+
+                        /* Enable BUFIOEN */
+                        snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
+                                      WM8991_BUFDCOPEN | WM8991_POBCTRL |
+                                      WM8991_BUFIOEN);
+
+                        /* Disable outputs */
+                        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x3);
+
+                        /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
+                        snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_BUFIOEN);
+                }
+
+                /* VMID=2*250k */
+                val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) &
+                      ~WM8991_VMID_MODE_MASK;
+                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x4);
+                break;
+
+        case SND_SOC_BIAS_OFF:
+                /* Enable POBCTRL and SOFT_ST */
+                snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
+                              WM8991_POBCTRL | WM8991_BUFIOEN);
+
+                /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
+                snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
+                              WM8991_BUFDCOPEN | WM8991_POBCTRL |
+                              WM8991_BUFIOEN);
+
+                /* mute DAC */
+                val = snd_soc_read(codec, WM8991_DAC_CTRL);
+                snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
+
+                /* Enable any disabled outputs */
+                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03);
+
+                /* Disable VMID */
+                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f01);
+
+                msleep(300);
+
+                /* Enable all output discharge bits */
+                snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
+                              WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
+                              WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
+                              WM8991_DIS_ROUT);
+
+                /* Disable VREF */
+                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x0);
+
+                /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
+                snd_soc_write(codec, WM8991_ANTIPOP2, 0x0);
+                codec->cache_sync = 1;
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+static int wm8991_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        wm8991_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int wm8991_resume(struct snd_soc_codec *codec)
+{
+        wm8991_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+
+/* power down chip */
+static int wm8991_remove(struct snd_soc_codec *codec)
+{
+        wm8991_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int wm8991_probe(struct snd_soc_codec *codec)
+{
+        struct wm8991_priv *wm8991;
+        int ret;
+        unsigned int reg;
+
+        wm8991 = snd_soc_codec_get_drvdata(codec);
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8991->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
+                return ret;
+        }
+
+        ret = wm8991_reset(codec);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to issue reset\n");
+                return ret;
+        }
+
+        wm8991_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        reg = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_4);
+        snd_soc_write(codec, WM8991_AUDIO_INTERFACE_4, reg | WM8991_ALRCGPIO1);
+
+        reg = snd_soc_read(codec, WM8991_GPIO1_GPIO2) &
+              ~WM8991_GPIO1_SEL_MASK;
+        snd_soc_write(codec, WM8991_GPIO1_GPIO2, reg | 1);
+
+        reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1);
+        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, reg | WM8991_VREF_ENA|
+                      WM8991_VMID_MODE_MASK);
+
+        reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2);
+        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg | WM8991_OPCLK_ENA);
+
+        snd_soc_write(codec, WM8991_DAC_CTRL, 0);
+        snd_soc_write(codec, WM8991_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
+        snd_soc_write(codec, WM8991_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
+
+        snd_soc_add_controls(codec, wm8991_snd_controls,
+                             ARRAY_SIZE(wm8991_snd_controls));
+
+        snd_soc_dapm_new_controls(&codec->dapm, wm8991_dapm_widgets,
+                                  ARRAY_SIZE(wm8991_dapm_widgets));
+        snd_soc_dapm_add_routes(&codec->dapm, audio_map,
+                                ARRAY_SIZE(audio_map));
+        return 0;
+}
+
+#define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+                        SNDRV_PCM_FMTBIT_S24_LE)
+
+static struct snd_soc_dai_ops wm8991_ops = {
+        .hw_params = wm8991_hw_params,
+        .digital_mute = wm8991_mute,
+        .set_fmt = wm8991_set_dai_fmt,
+        .set_clkdiv = wm8991_set_dai_clkdiv,
+        .set_pll = wm8991_set_dai_pll
+};
+
+/*
+ * The WM8991 supports 2 different and mutually exclusive DAI
+ * configurations.
+ *
+ * 1. ADC/DAC on Primary Interface
+ * 2. ADC on Primary Interface/DAC on secondary
+ */
+static struct snd_soc_dai_driver wm8991_dai = {
+        /* ADC/DAC on primary */
+        .name = "wm8991",
+        .id = 1,
+        .playback = {
+                .stream_name = "Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_96000,
+                .formats = WM8991_FORMATS
+        },
+        .capture = {
+                .stream_name = "Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_96000,
+                .formats = WM8991_FORMATS
+        },
+        .ops = &wm8991_ops
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8991 = {
+        .probe = wm8991_probe,
+        .remove = wm8991_remove,
+        .suspend = wm8991_suspend,
+        .resume = wm8991_resume,
+        .set_bias_level = wm8991_set_bias_level,
+        .reg_cache_size = WM8991_MAX_REGISTER + 1,
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8991_reg_defs
+};
+
+static __devinit int wm8991_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8991_priv *wm8991;
+        int ret;
+
+        wm8991 = kzalloc(sizeof *wm8991, GFP_KERNEL);
+        if (!wm8991)
+                return -ENOMEM;
+
+        wm8991->control_type = SND_SOC_I2C;
+        i2c_set_clientdata(i2c, wm8991);
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                                     &soc_codec_dev_wm8991, &wm8991_dai, 1);
+        if (ret < 0)
+                kfree(wm8991);
+        return ret;
+}
+
+static __devexit int wm8991_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id wm8991_i2c_id[] = {
+        { "wm8991", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id);
+
+static struct i2c_driver wm8991_i2c_driver = {
+        .driver = {
+                .name = "wm8991",
+                .owner = THIS_MODULE,
+        },
+        .probe = wm8991_i2c_probe,
+        .remove = __devexit_p(wm8991_i2c_remove),
+        .id_table = wm8991_i2c_id,
+};
+
+static int __init wm8991_modinit(void)
+{
+        int ret;
+        ret = i2c_add_driver(&wm8991_i2c_driver);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to register WM8991 I2C driver: %d\n",
+                       ret);
+        }
+        return 0;
+}
+module_init(wm8991_modinit);
+
+static void __exit wm8991_exit(void)
+{
+        i2c_del_driver(&wm8991_i2c_driver);
+}
+module_exit(wm8991_exit);
+
+MODULE_DESCRIPTION("ASoC WM8991 driver");
+MODULE_AUTHOR("Graeme Gregory");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8991.h b/sound/soc/codecs/wm8991.h
new file mode 100644
index 000000000000..8a942efd18a5
--- /dev/null
+++ b/sound/soc/codecs/wm8991.h
@@ -0,0 +1,833 @@
+/*
+ * wm8991.h  --  audio driver for WM8991
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory
+ *         graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef _WM8991_H
+#define _WM8991_H
+
+/*
+ * Register values.
+ */
+#define WM8991_RESET                            0x00
+#define WM8991_POWER_MANAGEMENT_1               0x01
+#define WM8991_POWER_MANAGEMENT_2               0x02
+#define WM8991_POWER_MANAGEMENT_3               0x03
+#define WM8991_AUDIO_INTERFACE_1                0x04
+#define WM8991_AUDIO_INTERFACE_2                0x05
+#define WM8991_CLOCKING_1                       0x06
+#define WM8991_CLOCKING_2                       0x07
+#define WM8991_AUDIO_INTERFACE_3                0x08
+#define WM8991_AUDIO_INTERFACE_4                0x09
+#define WM8991_DAC_CTRL                         0x0A
+#define WM8991_LEFT_DAC_DIGITAL_VOLUME          0x0B
+#define WM8991_RIGHT_DAC_DIGITAL_VOLUME         0x0C
+#define WM8991_DIGITAL_SIDE_TONE                0x0D
+#define WM8991_ADC_CTRL                         0x0E
+#define WM8991_LEFT_ADC_DIGITAL_VOLUME          0x0F
+#define WM8991_RIGHT_ADC_DIGITAL_VOLUME         0x10
+#define WM8991_GPIO_CTRL_1                      0x12
+#define WM8991_GPIO1_GPIO2                      0x13
+#define WM8991_GPIO3_GPIO4                      0x14
+#define WM8991_GPIO5_GPIO6                      0x15
+#define WM8991_GPIOCTRL_2                       0x16
+#define WM8991_GPIO_POL                         0x17
+#define WM8991_LEFT_LINE_INPUT_1_2_VOLUME       0x18
+#define WM8991_LEFT_LINE_INPUT_3_4_VOLUME       0x19
+#define WM8991_RIGHT_LINE_INPUT_1_2_VOLUME      0x1A
+#define WM8991_RIGHT_LINE_INPUT_3_4_VOLUME      0x1B
+#define WM8991_LEFT_OUTPUT_VOLUME               0x1C
+#define WM8991_RIGHT_OUTPUT_VOLUME              0x1D
+#define WM8991_LINE_OUTPUTS_VOLUME              0x1E
+#define WM8991_OUT3_4_VOLUME                    0x1F
+#define WM8991_LEFT_OPGA_VOLUME                 0x20
+#define WM8991_RIGHT_OPGA_VOLUME                0x21
+#define WM8991_SPEAKER_VOLUME                   0x22
+#define WM8991_CLASSD1                          0x23
+#define WM8991_CLASSD3                          0x25
+#define WM8991_INPUT_MIXER1                     0x27
+#define WM8991_INPUT_MIXER2                     0x28
+#define WM8991_INPUT_MIXER3                     0x29
+#define WM8991_INPUT_MIXER4                     0x2A
+#define WM8991_INPUT_MIXER5                     0x2B
+#define WM8991_INPUT_MIXER6                     0x2C
+#define WM8991_OUTPUT_MIXER1                    0x2D
+#define WM8991_OUTPUT_MIXER2                    0x2E
+#define WM8991_OUTPUT_MIXER3                    0x2F
+#define WM8991_OUTPUT_MIXER4                    0x30
+#define WM8991_OUTPUT_MIXER5                    0x31
+#define WM8991_OUTPUT_MIXER6                    0x32
+#define WM8991_OUT3_4_MIXER                     0x33
+#define WM8991_LINE_MIXER1                      0x34
+#define WM8991_LINE_MIXER2                      0x35
+#define WM8991_SPEAKER_MIXER                    0x36
+#define WM8991_ADDITIONAL_CONTROL               0x37
+#define WM8991_ANTIPOP1                         0x38
+#define WM8991_ANTIPOP2                         0x39
+#define WM8991_MICBIAS                          0x3A
+#define WM8991_PLL1                             0x3C
+#define WM8991_PLL2                             0x3D
+#define WM8991_PLL3                             0x3E
+#define WM8991_INTDRIVBITS                      0x3F
+
+#define WM8991_REGISTER_COUNT                   60
+#define WM8991_MAX_REGISTER                     0x3F
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Reset
+ */
+#define WM8991_SW_RESET_CHIP_ID_MASK            0xFFFF  /* SW_RESET_CHIP_ID - [15:0] */
+
+/*
+ * R1 (0x01) - Power Management (1)
+ */
+#define WM8991_SPK_ENA                          0x1000  /* SPK_ENA */
+#define WM8991_SPK_ENA_BIT                      12
+#define WM8991_OUT3_ENA                         0x0800  /* OUT3_ENA */
+#define WM8991_OUT3_ENA_BIT                     11
+#define WM8991_OUT4_ENA                         0x0400  /* OUT4_ENA */
+#define WM8991_OUT4_ENA_BIT                     10
+#define WM8991_LOUT_ENA                         0x0200  /* LOUT_ENA */
+#define WM8991_LOUT_ENA_BIT                     9
+#define WM8991_ROUT_ENA                         0x0100  /* ROUT_ENA */
+#define WM8991_ROUT_ENA_BIT                     8
+#define WM8991_MICBIAS_ENA                      0x0010  /* MICBIAS_ENA */
+#define WM8991_MICBIAS_ENA_BIT                  4
+#define WM8991_VMID_MODE_MASK                   0x0006  /* VMID_MODE - [2:1] */
+#define WM8991_VREF_ENA                         0x0001  /* VREF_ENA */
+#define WM8991_VREF_ENA_BIT                     0
+
+/*
+ * R2 (0x02) - Power Management (2)
+ */
+#define WM8991_PLL_ENA                          0x8000  /* PLL_ENA */
+#define WM8991_PLL_ENA_BIT                      15
+#define WM8991_TSHUT_ENA                        0x4000  /* TSHUT_ENA */
+#define WM8991_TSHUT_ENA_BIT                    14
+#define WM8991_TSHUT_OPDIS                      0x2000  /* TSHUT_OPDIS */
+#define WM8991_TSHUT_OPDIS_BIT                  13
+#define WM8991_OPCLK_ENA                        0x0800  /* OPCLK_ENA */
+#define WM8991_OPCLK_ENA_BIT                    11
+#define WM8991_AINL_ENA                         0x0200  /* AINL_ENA */
+#define WM8991_AINL_ENA_BIT                     9
+#define WM8991_AINR_ENA                         0x0100  /* AINR_ENA */
+#define WM8991_AINR_ENA_BIT                     8
+#define WM8991_LIN34_ENA                        0x0080  /* LIN34_ENA */
+#define WM8991_LIN34_ENA_BIT                    7
+#define WM8991_LIN12_ENA                        0x0040  /* LIN12_ENA */
+#define WM8991_LIN12_ENA_BIT                    6
+#define WM8991_RIN34_ENA                        0x0020  /* RIN34_ENA */
+#define WM8991_RIN34_ENA_BIT                    5
+#define WM8991_RIN12_ENA                        0x0010  /* RIN12_ENA */
+#define WM8991_RIN12_ENA_BIT                    4
+#define WM8991_ADCL_ENA                         0x0002  /* ADCL_ENA */
+#define WM8991_ADCL_ENA_BIT                     1
+#define WM8991_ADCR_ENA                         0x0001  /* ADCR_ENA */
+#define WM8991_ADCR_ENA_BIT                     0
+
+/*
+ * R3 (0x03) - Power Management (3)
+ */
+#define WM8991_LON_ENA                          0x2000  /* LON_ENA */
+#define WM8991_LON_ENA_BIT                      13
+#define WM8991_LOP_ENA                          0x1000  /* LOP_ENA */
+#define WM8991_LOP_ENA_BIT                      12
+#define WM8991_RON_ENA                          0x0800  /* RON_ENA */
+#define WM8991_RON_ENA_BIT                      11
+#define WM8991_ROP_ENA                          0x0400  /* ROP_ENA */
+#define WM8991_ROP_ENA_BIT                      10
+#define WM8991_LOPGA_ENA                        0x0080  /* LOPGA_ENA */
+#define WM8991_LOPGA_ENA_BIT                    7
+#define WM8991_ROPGA_ENA                        0x0040  /* ROPGA_ENA */
+#define WM8991_ROPGA_ENA_BIT                    6
+#define WM8991_LOMIX_ENA                        0x0020  /* LOMIX_ENA */
+#define WM8991_LOMIX_ENA_BIT                    5
+#define WM8991_ROMIX_ENA                        0x0010  /* ROMIX_ENA */
+#define WM8991_ROMIX_ENA_BIT                    4
+#define WM8991_DACL_ENA                         0x0002  /* DACL_ENA */
+#define WM8991_DACL_ENA_BIT                     1
+#define WM8991_DACR_ENA                         0x0001  /* DACR_ENA */
+#define WM8991_DACR_ENA_BIT                     0
+
+/*
+ * R4 (0x04) - Audio Interface (1)
+ */
+#define WM8991_AIFADCL_SRC                      0x8000  /* AIFADCL_SRC */
+#define WM8991_AIFADCR_SRC                      0x4000  /* AIFADCR_SRC */
+#define WM8991_AIFADC_TDM                       0x2000  /* AIFADC_TDM */
+#define WM8991_AIFADC_TDM_CHAN                  0x1000  /* AIFADC_TDM_CHAN */
+#define WM8991_AIF_BCLK_INV                     0x0100  /* AIF_BCLK_INV */
+#define WM8991_AIF_LRCLK_INV                    0x0080  /* AIF_LRCLK_INV */
+#define WM8991_AIF_WL_MASK                      0x0060  /* AIF_WL - [6:5] */
+#define WM8991_AIF_WL_16BITS                    (0 << 5)
+#define WM8991_AIF_WL_20BITS                    (1 << 5)
+#define WM8991_AIF_WL_24BITS                    (2 << 5)
+#define WM8991_AIF_WL_32BITS                    (3 << 5)
+#define WM8991_AIF_FMT_MASK                     0x0018  /* AIF_FMT - [4:3] */
+#define WM8991_AIF_TMF_RIGHTJ                   (0 << 3)
+#define WM8991_AIF_TMF_LEFTJ                    (1 << 3)
+#define WM8991_AIF_TMF_I2S                      (2 << 3)
+#define WM8991_AIF_TMF_DSP                      (3 << 3)
+
+/*
+ * R5 (0x05) - Audio Interface (2)
+ */
+#define WM8991_DACL_SRC                         0x8000  /* DACL_SRC */
+#define WM8991_DACR_SRC                         0x4000  /* DACR_SRC */
+#define WM8991_AIFDAC_TDM                       0x2000  /* AIFDAC_TDM */
+#define WM8991_AIFDAC_TDM_CHAN                  0x1000  /* AIFDAC_TDM_CHAN */
+#define WM8991_DAC_BOOST_MASK                   0x0C00  /* DAC_BOOST - [11:10] */
+#define WM8991_DAC_COMP                         0x0010  /* DAC_COMP */
+#define WM8991_DAC_COMPMODE                     0x0008  /* DAC_COMPMODE */
+#define WM8991_ADC_COMP                         0x0004  /* ADC_COMP */
+#define WM8991_ADC_COMPMODE                     0x0002  /* ADC_COMPMODE */
+#define WM8991_LOOPBACK                         0x0001  /* LOOPBACK */
+
+/*
+ * R6 (0x06) - Clocking (1)
+ */
+#define WM8991_TOCLK_RATE                       0x8000  /* TOCLK_RATE */
+#define WM8991_TOCLK_ENA                        0x4000  /* TOCLK_ENA */
+#define WM8991_OPCLKDIV_MASK                    0x1E00  /* OPCLKDIV - [12:9] */
+#define WM8991_DCLKDIV_MASK                     0x01C0  /* DCLKDIV - [8:6] */
+#define WM8991_BCLK_DIV_MASK                    0x001E  /* BCLK_DIV - [4:1] */
+#define WM8991_BCLK_DIV_1                       (0x0 << 1)
+#define WM8991_BCLK_DIV_1_5                     (0x1 << 1)
+#define WM8991_BCLK_DIV_2                       (0x2 << 1)
+#define WM8991_BCLK_DIV_3                       (0x3 << 1)
+#define WM8991_BCLK_DIV_4                       (0x4 << 1)
+#define WM8991_BCLK_DIV_5_5                     (0x5 << 1)
+#define WM8991_BCLK_DIV_6                       (0x6 << 1)
+#define WM8991_BCLK_DIV_8                       (0x7 << 1)
+#define WM8991_BCLK_DIV_11                      (0x8 << 1)
+#define WM8991_BCLK_DIV_12                      (0x9 << 1)
+#define WM8991_BCLK_DIV_16                      (0xA << 1)
+#define WM8991_BCLK_DIV_22                      (0xB << 1)
+#define WM8991_BCLK_DIV_24                      (0xC << 1)
+#define WM8991_BCLK_DIV_32                      (0xD << 1)
+#define WM8991_BCLK_DIV_44                      (0xE << 1)
+#define WM8991_BCLK_DIV_48                      (0xF << 1)
+
+/*
+ * R7 (0x07) - Clocking (2)
+ */
+#define WM8991_MCLK_SRC                         0x8000  /* MCLK_SRC */
+#define WM8991_SYSCLK_SRC                       0x4000  /* SYSCLK_SRC */
+#define WM8991_CLK_FORCE                        0x2000  /* CLK_FORCE */
+#define WM8991_MCLK_DIV_MASK                    0x1800  /* MCLK_DIV - [12:11] */
+#define WM8991_MCLK_DIV_1                       (0 << 11)
+#define WM8991_MCLK_DIV_2                       ( 2 << 11)
+#define WM8991_MCLK_INV                         0x0400  /* MCLK_INV */
+#define WM8991_ADC_CLKDIV_MASK                  0x00E0  /* ADC_CLKDIV - [7:5] */
+#define WM8991_ADC_CLKDIV_1                     (0 << 5)
+#define WM8991_ADC_CLKDIV_1_5                   (1 << 5)
+#define WM8991_ADC_CLKDIV_2                     (2 << 5)
+#define WM8991_ADC_CLKDIV_3                     (3 << 5)
+#define WM8991_ADC_CLKDIV_4                     (4 << 5)
+#define WM8991_ADC_CLKDIV_5_5                   (5 << 5)
+#define WM8991_ADC_CLKDIV_6                     (6 << 5)
+#define WM8991_DAC_CLKDIV_MASK                  0x001C  /* DAC_CLKDIV - [4:2] */
+#define WM8991_DAC_CLKDIV_1                     (0 << 2)
+#define WM8991_DAC_CLKDIV_1_5                   (1 << 2)
+#define WM8991_DAC_CLKDIV_2                     (2 << 2)
+#define WM8991_DAC_CLKDIV_3                     (3 << 2)
+#define WM8991_DAC_CLKDIV_4                     (4 << 2)
+#define WM8991_DAC_CLKDIV_5_5                   (5 << 2)
+#define WM8991_DAC_CLKDIV_6                     (6 << 2)
+
+/*
+ * R8 (0x08) - Audio Interface (3)
+ */
+#define WM8991_AIF_MSTR1                        0x8000  /* AIF_MSTR1 */
+#define WM8991_AIF_MSTR2                        0x4000  /* AIF_MSTR2 */
+#define WM8991_AIF_SEL                          0x2000  /* AIF_SEL */
+#define WM8991_ADCLRC_DIR                       0x0800  /* ADCLRC_DIR */
+#define WM8991_ADCLRC_RATE_MASK                 0x07FF  /* ADCLRC_RATE - [10:0] */
+
+/*
+ * R9 (0x09) - Audio Interface (4)
+ */
+#define WM8991_ALRCGPIO1                        0x8000  /* ALRCGPIO1 */
+#define WM8991_ALRCBGPIO6                       0x4000  /* ALRCBGPIO6 */
+#define WM8991_AIF_TRIS                         0x2000  /* AIF_TRIS */
+#define WM8991_DACLRC_DIR                       0x0800  /* DACLRC_DIR */
+#define WM8991_DACLRC_RATE_MASK                 0x07FF  /* DACLRC_RATE - [10:0] */
+
+/*
+ * R10 (0x0A) - DAC CTRL
+ */
+#define WM8991_AIF_LRCLKRATE                    0x0400  /* AIF_LRCLKRATE */
+#define WM8991_DAC_MONO                         0x0200  /* DAC_MONO */
+#define WM8991_DAC_SB_FILT                      0x0100  /* DAC_SB_FILT */
+#define WM8991_DAC_MUTERATE                     0x0080  /* DAC_MUTERATE */
+#define WM8991_DAC_MUTEMODE                     0x0040  /* DAC_MUTEMODE */
+#define WM8991_DEEMP_MASK                       0x0030  /* DEEMP - [5:4] */
+#define WM8991_DAC_MUTE                         0x0004  /* DAC_MUTE */
+#define WM8991_DACL_DATINV                      0x0002  /* DACL_DATINV */
+#define WM8991_DACR_DATINV                      0x0001  /* DACR_DATINV */
+
+/*
+ * R11 (0x0B) - Left DAC Digital Volume
+ */
+#define WM8991_DAC_VU                           0x0100  /* DAC_VU */
+#define WM8991_DACL_VOL_MASK                    0x00FF  /* DACL_VOL - [7:0] */
+#define WM8991_DACL_VOL_SHIFT                   0
+/*
+ * R12 (0x0C) - Right DAC Digital Volume
+ */
+#define WM8991_DAC_VU                           0x0100  /* DAC_VU */
+#define WM8991_DACR_VOL_MASK                    0x00FF  /* DACR_VOL - [7:0] */
+#define WM8991_DACR_VOL_SHIFT                   0
+/*
+ * R13 (0x0D) - Digital Side Tone
+ */
+#define WM8991_ADCL_DAC_SVOL_MASK               0x0F  /* ADCL_DAC_SVOL - [12:9] */
+#define WM8991_ADCL_DAC_SVOL_SHIFT              9
+#define WM8991_ADCR_DAC_SVOL_MASK               0x0F  /* ADCR_DAC_SVOL - [8:5] */
+#define WM8991_ADCR_DAC_SVOL_SHIFT              5
+#define WM8991_ADC_TO_DACL_MASK                 0x03  /* ADC_TO_DACL - [3:2] */
+#define WM8991_ADC_TO_DACL_SHIFT                2
+#define WM8991_ADC_TO_DACR_MASK                 0x03  /* ADC_TO_DACR - [1:0] */
+#define WM8991_ADC_TO_DACR_SHIFT                0
+
+/*
+ * R14 (0x0E) - ADC CTRL
+ */
+#define WM8991_ADC_HPF_ENA                      0x0100  /* ADC_HPF_ENA */
+#define WM8991_ADC_HPF_ENA_BIT                  8
+#define WM8991_ADC_HPF_CUT_MASK                 0x03  /* ADC_HPF_CUT - [6:5] */
+#define WM8991_ADC_HPF_CUT_SHIFT                5
+#define WM8991_ADCL_DATINV                      0x0002  /* ADCL_DATINV */
+#define WM8991_ADCL_DATINV_BIT                  1
+#define WM8991_ADCR_DATINV                      0x0001  /* ADCR_DATINV */
+#define WM8991_ADCR_DATINV_BIT                  0
+
+/*
+ * R15 (0x0F) - Left ADC Digital Volume
+ */
+#define WM8991_ADC_VU                           0x0100  /* ADC_VU */
+#define WM8991_ADCL_VOL_MASK                    0x00FF  /* ADCL_VOL - [7:0] */
+#define WM8991_ADCL_VOL_SHIFT                   0
+
+/*
+ * R16 (0x10) - Right ADC Digital Volume
+ */
+#define WM8991_ADC_VU                           0x0100  /* ADC_VU */
+#define WM8991_ADCR_VOL_MASK                    0x00FF  /* ADCR_VOL - [7:0] */
+#define WM8991_ADCR_VOL_SHIFT                   0
+
+/*
+ * R18 (0x12) - GPIO CTRL 1
+ */
+#define WM8991_IRQ                              0x1000  /* IRQ */
+#define WM8991_TEMPOK                           0x0800  /* TEMPOK */
+#define WM8991_MICSHRT                          0x0400  /* MICSHRT */
+#define WM8991_MICDET                           0x0200  /* MICDET */
+#define WM8991_PLL_LCK                          0x0100  /* PLL_LCK */
+#define WM8991_GPI8_STATUS                      0x0080  /* GPI8_STATUS */
+#define WM8991_GPI7_STATUS                      0x0040  /* GPI7_STATUS */
+#define WM8991_GPIO6_STATUS                     0x0020  /* GPIO6_STATUS */
+#define WM8991_GPIO5_STATUS                     0x0010  /* GPIO5_STATUS */
+#define WM8991_GPIO4_STATUS                     0x0008  /* GPIO4_STATUS */
+#define WM8991_GPIO3_STATUS                     0x0004  /* GPIO3_STATUS */
+#define WM8991_GPIO2_STATUS                     0x0002  /* GPIO2_STATUS */
+#define WM8991_GPIO1_STATUS                     0x0001  /* GPIO1_STATUS */
+
+/*
+ * R19 (0x13) - GPIO1 & GPIO2
+ */
+#define WM8991_GPIO2_DEB_ENA                    0x8000  /* GPIO2_DEB_ENA */
+#define WM8991_GPIO2_IRQ_ENA                    0x4000  /* GPIO2_IRQ_ENA */
+#define WM8991_GPIO2_PU                         0x2000  /* GPIO2_PU */
+#define WM8991_GPIO2_PD                         0x1000  /* GPIO2_PD */
+#define WM8991_GPIO2_SEL_MASK                   0x0F00  /* GPIO2_SEL - [11:8] */
+#define WM8991_GPIO1_DEB_ENA                    0x0080  /* GPIO1_DEB_ENA */
+#define WM8991_GPIO1_IRQ_ENA                    0x0040  /* GPIO1_IRQ_ENA */
+#define WM8991_GPIO1_PU                         0x0020  /* GPIO1_PU */
+#define WM8991_GPIO1_PD                         0x0010  /* GPIO1_PD */
+#define WM8991_GPIO1_SEL_MASK                   0x000F  /* GPIO1_SEL - [3:0] */
+
+/*
+ * R20 (0x14) - GPIO3 & GPIO4
+ */
+#define WM8991_GPIO4_DEB_ENA                    0x8000  /* GPIO4_DEB_ENA */
+#define WM8991_GPIO4_IRQ_ENA                    0x4000  /* GPIO4_IRQ_ENA */
+#define WM8991_GPIO4_PU                         0x2000  /* GPIO4_PU */
+#define WM8991_GPIO4_PD                         0x1000  /* GPIO4_PD */
+#define WM8991_GPIO4_SEL_MASK                   0x0F00  /* GPIO4_SEL - [11:8] */
+#define WM8991_GPIO3_DEB_ENA                    0x0080  /* GPIO3_DEB_ENA */
+#define WM8991_GPIO3_IRQ_ENA                    0x0040  /* GPIO3_IRQ_ENA */
+#define WM8991_GPIO3_PU                         0x0020  /* GPIO3_PU */
+#define WM8991_GPIO3_PD                         0x0010  /* GPIO3_PD */
+#define WM8991_GPIO3_SEL_MASK                   0x000F  /* GPIO3_SEL - [3:0] */
+
+/*
+ * R21 (0x15) - GPIO5 & GPIO6
+ */
+#define WM8991_GPIO6_DEB_ENA                    0x8000  /* GPIO6_DEB_ENA */
+#define WM8991_GPIO6_IRQ_ENA                    0x4000  /* GPIO6_IRQ_ENA */
+#define WM8991_GPIO6_PU                         0x2000  /* GPIO6_PU */
+#define WM8991_GPIO6_PD                         0x1000  /* GPIO6_PD */
+#define WM8991_GPIO6_SEL_MASK                   0x0F00  /* GPIO6_SEL - [11:8] */
+#define WM8991_GPIO5_DEB_ENA                    0x0080  /* GPIO5_DEB_ENA */
+#define WM8991_GPIO5_IRQ_ENA                    0x0040  /* GPIO5_IRQ_ENA */
+#define WM8991_GPIO5_PU                         0x0020  /* GPIO5_PU */
+#define WM8991_GPIO5_PD                         0x0010  /* GPIO5_PD */
+#define WM8991_GPIO5_SEL_MASK                   0x000F  /* GPIO5_SEL - [3:0] */
+
+/*
+ * R22 (0x16) - GPIOCTRL 2
+ */
+#define WM8991_RD_3W_ENA                        0x8000  /* RD_3W_ENA */
+#define WM8991_MODE_3W4W                        0x4000  /* MODE_3W4W */
+#define WM8991_TEMPOK_IRQ_ENA                   0x0800  /* TEMPOK_IRQ_ENA */
+#define WM8991_MICSHRT_IRQ_ENA                  0x0400  /* MICSHRT_IRQ_ENA */
+#define WM8991_MICDET_IRQ_ENA                   0x0200  /* MICDET_IRQ_ENA */
+#define WM8991_PLL_LCK_IRQ_ENA                  0x0100  /* PLL_LCK_IRQ_ENA */
+#define WM8991_GPI8_DEB_ENA                     0x0080  /* GPI8_DEB_ENA */
+#define WM8991_GPI8_IRQ_ENA                     0x0040  /* GPI8_IRQ_ENA */
+#define WM8991_GPI8_ENA                         0x0010  /* GPI8_ENA */
+#define WM8991_GPI7_DEB_ENA                     0x0008  /* GPI7_DEB_ENA */
+#define WM8991_GPI7_IRQ_ENA                     0x0004  /* GPI7_IRQ_ENA */
+#define WM8991_GPI7_ENA                         0x0001  /* GPI7_ENA */
+
+/*
+ * R23 (0x17) - GPIO_POL
+ */
+#define WM8991_IRQ_INV                          0x1000  /* IRQ_INV */
+#define WM8991_TEMPOK_POL                       0x0800  /* TEMPOK_POL */
+#define WM8991_MICSHRT_POL                      0x0400  /* MICSHRT_POL */
+#define WM8991_MICDET_POL                       0x0200  /* MICDET_POL */
+#define WM8991_PLL_LCK_POL                      0x0100  /* PLL_LCK_POL */
+#define WM8991_GPI8_POL                         0x0080  /* GPI8_POL */
+#define WM8991_GPI7_POL                         0x0040  /* GPI7_POL */
+#define WM8991_GPIO6_POL                        0x0020  /* GPIO6_POL */
+#define WM8991_GPIO5_POL                        0x0010  /* GPIO5_POL */
+#define WM8991_GPIO4_POL                        0x0008  /* GPIO4_POL */
+#define WM8991_GPIO3_POL                        0x0004  /* GPIO3_POL */
+#define WM8991_GPIO2_POL                        0x0002  /* GPIO2_POL */
+#define WM8991_GPIO1_POL                        0x0001  /* GPIO1_POL */
+
+/*
+ * R24 (0x18) - Left Line Input 1&2 Volume
+ */
+#define WM8991_IPVU                             0x0100  /* IPVU */
+#define WM8991_LI12MUTE                         0x0080  /* LI12MUTE */
+#define WM8991_LI12MUTE_BIT                     7
+#define WM8991_LI12ZC                           0x0040  /* LI12ZC */
+#define WM8991_LI12ZC_BIT                       6
+#define WM8991_LIN12VOL_MASK                    0x001F  /* LIN12VOL - [4:0] */
+#define WM8991_LIN12VOL_SHIFT                   0
+/*
+ * R25 (0x19) - Left Line Input 3&4 Volume
+ */
+#define WM8991_IPVU                             0x0100  /* IPVU */
+#define WM8991_LI34MUTE                         0x0080  /* LI34MUTE */
+#define WM8991_LI34MUTE_BIT                     7
+#define WM8991_LI34ZC                           0x0040  /* LI34ZC */
+#define WM8991_LI34ZC_BIT                       6
+#define WM8991_LIN34VOL_MASK                    0x001F  /* LIN34VOL - [4:0] */
+#define WM8991_LIN34VOL_SHIFT                   0
+
+/*
+ * R26 (0x1A) - Right Line Input 1&2 Volume
+ */
+#define WM8991_IPVU                             0x0100  /* IPVU */
+#define WM8991_RI12MUTE                         0x0080  /* RI12MUTE */
+#define WM8991_RI12MUTE_BIT                     7
+#define WM8991_RI12ZC                           0x0040  /* RI12ZC */
+#define WM8991_RI12ZC_BIT                       6
+#define WM8991_RIN12VOL_MASK                    0x001F  /* RIN12VOL - [4:0] */
+#define WM8991_RIN12VOL_SHIFT                   0
+
+/*
+ * R27 (0x1B) - Right Line Input 3&4 Volume
+ */
+#define WM8991_IPVU                             0x0100  /* IPVU */
+#define WM8991_RI34MUTE                         0x0080  /* RI34MUTE */
+#define WM8991_RI34MUTE_BIT                     7
+#define WM8991_RI34ZC                           0x0040  /* RI34ZC */
+#define WM8991_RI34ZC_BIT                       6
+#define WM8991_RIN34VOL_MASK                    0x001F  /* RIN34VOL - [4:0] */
+#define WM8991_RIN34VOL_SHIFT                   0
+
+/*
+ * R28 (0x1C) - Left Output Volume
+ */
+#define WM8991_OPVU                             0x0100  /* OPVU */
+#define WM8991_LOZC                             0x0080  /* LOZC */
+#define WM8991_LOZC_BIT                         7
+#define WM8991_LOUTVOL_MASK                     0x007F  /* LOUTVOL - [6:0] */
+#define WM8991_LOUTVOL_SHIFT                    0
+/*
+ * R29 (0x1D) - Right Output Volume
+ */
+#define WM8991_OPVU                             0x0100  /* OPVU */
+#define WM8991_ROZC                             0x0080  /* ROZC */
+#define WM8991_ROZC_BIT                         7
+#define WM8991_ROUTVOL_MASK                     0x007F  /* ROUTVOL - [6:0] */
+#define WM8991_ROUTVOL_SHIFT                    0
+/*
+ * R30 (0x1E) - Line Outputs Volume
+ */
+#define WM8991_LONMUTE                          0x0040  /* LONMUTE */
+#define WM8991_LONMUTE_BIT                      6
+#define WM8991_LOPMUTE                          0x0020  /* LOPMUTE */
+#define WM8991_LOPMUTE_BIT                      5
+#define WM8991_LOATTN                           0x0010  /* LOATTN */
+#define WM8991_LOATTN_BIT                       4
+#define WM8991_RONMUTE                          0x0004  /* RONMUTE */
+#define WM8991_RONMUTE_BIT                      2
+#define WM8991_ROPMUTE                          0x0002  /* ROPMUTE */
+#define WM8991_ROPMUTE_BIT                      1
+#define WM8991_ROATTN                           0x0001  /* ROATTN */
+#define WM8991_ROATTN_BIT                       0
+
+/*
+ * R31 (0x1F) - Out3/4 Volume
+ */
+#define WM8991_OUT3MUTE                         0x0020  /* OUT3MUTE */
+#define WM8991_OUT3MUTE_BIT                     5
+#define WM8991_OUT3ATTN                         0x0010  /* OUT3ATTN */
+#define WM8991_OUT3ATTN_BIT                     4
+#define WM8991_OUT4MUTE                         0x0002  /* OUT4MUTE */
+#define WM8991_OUT4MUTE_BIT                     1
+#define WM8991_OUT4ATTN                         0x0001  /* OUT4ATTN */
+#define WM8991_OUT4ATTN_BIT                     0
+
+/*
+ * R32 (0x20) - Left OPGA Volume
+ */
+#define WM8991_OPVU                             0x0100  /* OPVU */
+#define WM8991_LOPGAZC                          0x0080  /* LOPGAZC */
+#define WM8991_LOPGAZC_BIT                      7
+#define WM8991_LOPGAVOL_MASK                    0x007F  /* LOPGAVOL - [6:0] */
+#define WM8991_LOPGAVOL_SHIFT                   0
+
+/*
+ * R33 (0x21) - Right OPGA Volume
+ */
+#define WM8991_OPVU                             0x0100  /* OPVU */
+#define WM8991_ROPGAZC                          0x0080  /* ROPGAZC */
+#define WM8991_ROPGAZC_BIT                      7
+#define WM8991_ROPGAVOL_MASK                    0x007F  /* ROPGAVOL - [6:0] */
+#define WM8991_ROPGAVOL_SHIFT                   0
+/*
+ * R34 (0x22) - Speaker Volume
+ */
+#define WM8991_SPKVOL_MASK                      0x0003  /* SPKVOL - [1:0] */
+#define WM8991_SPKVOL_SHIFT                     0
+
+/*
+ * R35 (0x23) - ClassD1
+ */
+#define WM8991_CDMODE                           0x0100  /* CDMODE */
+#define WM8991_CDMODE_BIT                       8
+
+/*
+ * R37 (0x25) - ClassD3
+ */
+#define WM8991_DCGAIN_MASK                      0x0007  /* DCGAIN - [5:3] */
+#define WM8991_DCGAIN_SHIFT                     3
+#define WM8991_ACGAIN_MASK                      0x0007  /* ACGAIN - [2:0] */
+#define WM8991_ACGAIN_SHIFT                     0
+/*
+ * R39 (0x27) - Input Mixer1
+ */
+#define WM8991_AINLMODE_MASK                    0x000C  /* AINLMODE - [3:2] */
+#define WM8991_AINLMODE_SHIFT                   2
+#define WM8991_AINRMODE_MASK                    0x0003  /* AINRMODE - [1:0] */
+#define WM8991_AINRMODE_SHIFT                   0
+
+/*
+ * R40 (0x28) - Input Mixer2
+ */
+#define WM8991_LMP4                                                             0x0080  /* LMP4 */
+#define WM8991_LMP4_BIT                         7               /* LMP4 */
+#define WM8991_LMN3                             0x0040  /* LMN3 */
+#define WM8991_LMN3_BIT                         6       /* LMN3 */
+#define WM8991_LMP2                             0x0020  /* LMP2 */
+#define WM8991_LMP2_BIT                         5       /* LMP2 */
+#define WM8991_LMN1                             0x0010  /* LMN1 */
+#define WM8991_LMN1_BIT                         4       /* LMN1 */
+#define WM8991_RMP4                             0x0008  /* RMP4 */
+#define WM8991_RMP4_BIT                         3       /* RMP4 */
+#define WM8991_RMN3                             0x0004  /* RMN3 */
+#define WM8991_RMN3_BIT                         2       /* RMN3 */
+#define WM8991_RMP2                             0x0002  /* RMP2 */
+#define WM8991_RMP2_BIT                         1       /* RMP2 */
+#define WM8991_RMN1                             0x0001  /* RMN1 */
+#define WM8991_RMN1_BIT                         0       /* RMN1 */
+
+/*
+ * R41 (0x29) - Input Mixer3
+ */
+#define WM8991_L34MNB                           0x0100  /* L34MNB */
+#define WM8991_L34MNB_BIT                       8
+#define WM8991_L34MNBST                         0x0080  /* L34MNBST */
+#define WM8991_L34MNBST_BIT                     7
+#define WM8991_L12MNB                           0x0020  /* L12MNB */
+#define WM8991_L12MNB_BIT                       5
+#define WM8991_L12MNBST                         0x0010  /* L12MNBST */
+#define WM8991_L12MNBST_BIT                     4
+#define WM8991_LDBVOL_MASK                      0x0007  /* LDBVOL - [2:0] */
+#define WM8991_LDBVOL_SHIFT                     0
+
+/*
+ * R42 (0x2A) - Input Mixer4
+ */
+#define WM8991_R34MNB                           0x0100  /* R34MNB */
+#define WM8991_R34MNB_BIT                       8
+#define WM8991_R34MNBST                         0x0080  /* R34MNBST */
+#define WM8991_R34MNBST_BIT                     7
+#define WM8991_R12MNB                           0x0020  /* R12MNB */
+#define WM8991_R12MNB_BIT                       5
+#define WM8991_R12MNBST                         0x0010  /* R12MNBST */
+#define WM8991_R12MNBST_BIT                     4
+#define WM8991_RDBVOL_MASK                      0x0007  /* RDBVOL - [2:0] */
+#define WM8991_RDBVOL_SHIFT                     0
+
+/*
+ * R43 (0x2B) - Input Mixer5
+ */
+#define WM8991_LI2BVOL_MASK                     0x07  /* LI2BVOL - [8:6] */
+#define WM8991_LI2BVOL_SHIFT                    6
+#define WM8991_LR4BVOL_MASK                     0x07  /* LR4BVOL - [5:3] */
+#define WM8991_LR4BVOL_SHIFT                    3
+#define WM8991_LL4BVOL_MASK                     0x07  /* LL4BVOL - [2:0] */
+#define WM8991_LL4BVOL_SHIFT                    0
+
+/*
+ * R44 (0x2C) - Input Mixer6
+ */
+#define WM8991_RI2BVOL_MASK                     0x07  /* RI2BVOL - [8:6] */
+#define WM8991_RI2BVOL_SHIFT                    6
+#define WM8991_RL4BVOL_MASK                     0x07  /* RL4BVOL - [5:3] */
+#define WM8991_RL4BVOL_SHIFT                    3
+#define WM8991_RR4BVOL_MASK                     0x07  /* RR4BVOL - [2:0] */
+#define WM8991_RR4BVOL_SHIFT                    0
+
+/*
+ * R45 (0x2D) - Output Mixer1
+ */
+#define WM8991_LRBLO                            0x0080  /* LRBLO */
+#define WM8991_LRBLO_BIT                        7
+#define WM8991_LLBLO                            0x0040  /* LLBLO */
+#define WM8991_LLBLO_BIT                        6
+#define WM8991_LRI3LO                           0x0020  /* LRI3LO */
+#define WM8991_LRI3LO_BIT                       5
+#define WM8991_LLI3LO                           0x0010  /* LLI3LO */
+#define WM8991_LLI3LO_BIT                       4
+#define WM8991_LR12LO                           0x0008  /* LR12LO */
+#define WM8991_LR12LO_BIT                       3
+#define WM8991_LL12LO                           0x0004  /* LL12LO */
+#define WM8991_LL12LO_BIT                       2
+#define WM8991_LDLO                             0x0001  /* LDLO */
+#define WM8991_LDLO_BIT                         0
+
+/*
+ * R46 (0x2E) - Output Mixer2
+ */
+#define WM8991_RLBRO                            0x0080  /* RLBRO */
+#define WM8991_RLBRO_BIT                        7
+#define WM8991_RRBRO                            0x0040  /* RRBRO */
+#define WM8991_RRBRO_BIT                        6
+#define WM8991_RLI3RO                           0x0020  /* RLI3RO */
+#define WM8991_RLI3RO_BIT                       5
+#define WM8991_RRI3RO                           0x0010  /* RRI3RO */
+#define WM8991_RRI3RO_BIT                       4
+#define WM8991_RL12RO                           0x0008  /* RL12RO */
+#define WM8991_RL12RO_BIT                       3
+#define WM8991_RR12RO                           0x0004  /* RR12RO */
+#define WM8991_RR12RO_BIT                       2
+#define WM8991_RDRO                             0x0001  /* RDRO */
+#define WM8991_RDRO_BIT                         0
+
+/*
+ * R47 (0x2F) - Output Mixer3
+ */
+#define WM8991_LLI3LOVOL_MASK                   0x07  /* LLI3LOVOL - [8:6] */
+#define WM8991_LLI3LOVOL_SHIFT                  6
+#define WM8991_LR12LOVOL_MASK                   0x07  /* LR12LOVOL - [5:3] */
+#define WM8991_LR12LOVOL_SHIFT                  3
+#define WM8991_LL12LOVOL_MASK                   0x07  /* LL12LOVOL - [2:0] */
+#define WM8991_LL12LOVOL_SHIFT                  0
+
+/*
+ * R48 (0x30) - Output Mixer4
+ */
+#define WM8991_RRI3ROVOL_MASK                   0x07  /* RRI3ROVOL - [8:6] */
+#define WM8991_RRI3ROVOL_SHIFT                  6
+#define WM8991_RL12ROVOL_MASK                   0x07  /* RL12ROVOL - [5:3] */
+#define WM8991_RL12ROVOL_SHIFT                  3
+#define WM8991_RR12ROVOL_MASK                   0x07  /* RR12ROVOL - [2:0] */
+#define WM8991_RR12ROVOL_SHIFT                  0
+
+/*
+ * R49 (0x31) - Output Mixer5
+ */
+#define WM8991_LRI3LOVOL_MASK                   0x07  /* LRI3LOVOL - [8:6] */
+#define WM8991_LRI3LOVOL_SHIFT                  6
+#define WM8991_LRBLOVOL_MASK                    0x07  /* LRBLOVOL - [5:3] */
+#define WM8991_LRBLOVOL_SHIFT                   3
+#define WM8991_LLBLOVOL_MASK                    0x07  /* LLBLOVOL - [2:0] */
+#define WM8991_LLBLOVOL_SHIFT                   0
+
+/*
+ * R50 (0x32) - Output Mixer6
+ */
+#define WM8991_RLI3ROVOL_MASK                   0x07  /* RLI3ROVOL - [8:6] */
+#define WM8991_RLI3ROVOL_SHIFT                  6
+#define WM8991_RLBROVOL_MASK                    0x07  /* RLBROVOL - [5:3] */
+#define WM8991_RLBROVOL_SHIFT                   3
+#define WM8991_RRBROVOL_MASK                    0x07  /* RRBROVOL - [2:0] */
+#define WM8991_RRBROVOL_SHIFT                   0
+
+/*
+ * R51 (0x33) - Out3/4 Mixer
+ */
+#define WM8991_VSEL_MASK                        0x0180  /* VSEL - [8:7] */
+#define WM8991_LI4O3                            0x0020  /* LI4O3 */
+#define WM8991_LI4O3_BIT                        5
+#define WM8991_LPGAO3                           0x0010  /* LPGAO3 */
+#define WM8991_LPGAO3_BIT                       4
+#define WM8991_RI4O4                            0x0002  /* RI4O4 */
+#define WM8991_RI4O4_BIT                        1
+#define WM8991_RPGAO4                           0x0001  /* RPGAO4 */
+#define WM8991_RPGAO4_BIT                       0
+/*
+ * R52 (0x34) - Line Mixer1
+ */
+#define WM8991_LLOPGALON                        0x0040  /* LLOPGALON */
+#define WM8991_LLOPGALON_BIT                    6
+#define WM8991_LROPGALON                        0x0020  /* LROPGALON */
+#define WM8991_LROPGALON_BIT                    5
+#define WM8991_LOPLON                           0x0010  /* LOPLON */
+#define WM8991_LOPLON_BIT                       4
+#define WM8991_LR12LOP                          0x0004  /* LR12LOP */
+#define WM8991_LR12LOP_BIT                      2
+#define WM8991_LL12LOP                          0x0002  /* LL12LOP */
+#define WM8991_LL12LOP_BIT                      1
+#define WM8991_LLOPGALOP                        0x0001  /* LLOPGALOP */
+#define WM8991_LLOPGALOP_BIT                    0
+/*
+ * R53 (0x35) - Line Mixer2
+ */
+#define WM8991_RROPGARON                        0x0040  /* RROPGARON */
+#define WM8991_RROPGARON_BIT                    6
+#define WM8991_RLOPGARON                        0x0020  /* RLOPGARON */
+#define WM8991_RLOPGARON_BIT                    5
+#define WM8991_ROPRON                           0x0010  /* ROPRON */
+#define WM8991_ROPRON_BIT                       4
+#define WM8991_RL12ROP                          0x0004  /* RL12ROP */
+#define WM8991_RL12ROP_BIT                      2
+#define WM8991_RR12ROP                          0x0002  /* RR12ROP */
+#define WM8991_RR12ROP_BIT                      1
+#define WM8991_RROPGAROP                        0x0001  /* RROPGAROP */
+#define WM8991_RROPGAROP_BIT                    0
+
+/*
+ * R54 (0x36) - Speaker Mixer
+ */
+#define WM8991_LB2SPK                           0x0080  /* LB2SPK */
+#define WM8991_LB2SPK_BIT                       7
+#define WM8991_RB2SPK                           0x0040  /* RB2SPK */
+#define WM8991_RB2SPK_BIT                       6
+#define WM8991_LI2SPK                           0x0020  /* LI2SPK */
+#define WM8991_LI2SPK_BIT                       5
+#define WM8991_RI2SPK                           0x0010  /* RI2SPK */
+#define WM8991_RI2SPK_BIT                       4
+#define WM8991_LOPGASPK                         0x0008  /* LOPGASPK */
+#define WM8991_LOPGASPK_BIT                     3
+#define WM8991_ROPGASPK                         0x0004  /* ROPGASPK */
+#define WM8991_ROPGASPK_BIT                     2
+#define WM8991_LDSPK                            0x0002  /* LDSPK */
+#define WM8991_LDSPK_BIT                        1
+#define WM8991_RDSPK                            0x0001  /* RDSPK */
+#define WM8991_RDSPK_BIT                        0
+
+/*
+ * R55 (0x37) - Additional Control
+ */
+#define WM8991_VROI                             0x0001  /* VROI */
+
+/*
+ * R56 (0x38) - AntiPOP1
+ */
+#define WM8991_DIS_LLINE                        0x0020  /* DIS_LLINE */
+#define WM8991_DIS_RLINE                        0x0010  /* DIS_RLINE */
+#define WM8991_DIS_OUT3                         0x0008  /* DIS_OUT3 */
+#define WM8991_DIS_OUT4                         0x0004  /* DIS_OUT4 */
+#define WM8991_DIS_LOUT                         0x0002  /* DIS_LOUT */
+#define WM8991_DIS_ROUT                         0x0001  /* DIS_ROUT */
+
+/*
+ * R57 (0x39) - AntiPOP2
+ */
+#define WM8991_SOFTST                           0x0040  /* SOFTST */
+#define WM8991_BUFIOEN                          0x0008  /* BUFIOEN */
+#define WM8991_BUFDCOPEN                        0x0004  /* BUFDCOPEN */
+#define WM8991_POBCTRL                          0x0002  /* POBCTRL */
+#define WM8991_VMIDTOG                          0x0001  /* VMIDTOG */
+
+/*
+ * R58 (0x3A) - MICBIAS
+ */
+#define WM8991_MCDSCTH_MASK                     0x00C0  /* MCDSCTH - [7:6] */
+#define WM8991_MCDTHR_MASK                      0x0038  /* MCDTHR - [5:3] */
+#define WM8991_MCD                              0x0004  /* MCD */
+#define WM8991_MBSEL                            0x0001  /* MBSEL */
+
+/*
+ * R60 (0x3C) - PLL1
+ */
+#define WM8991_SDM                              0x0080  /* SDM */
+#define WM8991_PRESCALE                         0x0040  /* PRESCALE */
+#define WM8991_PLLN_MASK                        0x000F  /* PLLN - [3:0] */
+
+/*
+ * R61 (0x3D) - PLL2
+ */
+#define WM8991_PLLK1_MASK                       0x00FF  /* PLLK1 - [7:0] */
+
+/*
+ * R62 (0x3E) - PLL3
+ */
+#define WM8991_PLLK2_MASK                       0x00FF  /* PLLK2 - [7:0] */
+
+/*
+ * R63 (0x3F) - Internal Driver Bits
+ */
+#define WM8991_INMIXL_PWR_BIT                   0
+#define WM8991_AINLMUX_PWR_BIT                  1
+#define WM8991_INMIXR_PWR_BIT                   2
+#define WM8991_AINRMUX_PWR_BIT                  3
+
+#define WM8991_MCLK_DIV 0
+#define WM8991_DACCLK_DIV 1
+#define WM8991_ADCCLK_DIV 2
+#define WM8991_BCLK_DIV 3
+
+#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
+                                         tlv_array) \
+{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+        .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+                 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+        .tlv.p = (tlv_array), \
+        .info = snd_soc_info_volsw, \
+        .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
+        .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
+
+#endif /* _WM8991_H */
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c
index d8d300c6175f..9e5ff789b805 100644
--- a/sound/soc/codecs/wm8993.c
+++ b/sound/soc/codecs/wm8993.c
@@ -24,7 +24,6 @@
 #include <sound/pcm_params.h>
 #include <sound/tlv.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/wm8993.h>
 
@@ -226,10 +225,9 @@ static struct {
 
 struct wm8993_priv {
         struct wm_hubs_data hubs_data;
-        u16 reg_cache[WM8993_REGISTER_COUNT];
         struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
         struct wm8993_platform_data pdata;
-        struct snd_soc_codec codec;
+        enum snd_soc_control_type control_type;
         int master;
         int sysclk_source;
         int tdm_slots;
@@ -244,7 +242,7 @@ struct wm8993_priv {
         int fll_src;
 };
 
-static int wm8993_volatile(unsigned int reg)
+static int wm8993_volatile(struct snd_soc_codec *codec, unsigned int reg)
 {
         switch (reg) {
         case WM8993_SOFTWARE_RESET:
@@ -326,7 +324,7 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
 
         pr_debug("Fvco=%dHz\n", target);
 
-        /* Find an appropraite FLL_FRATIO and factor it out of the target */
+        /* Find an appropriate FLL_FRATIO and factor it out of the target */
         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
@@ -367,10 +365,9 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
         return 0;
 }
 
-static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
+static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
                           unsigned int Fref, unsigned int Fout)
 {
-        struct snd_soc_codec *codec = dai->codec;
         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
         u16 reg1, reg4, reg5;
         struct _fll_div fll_div;
@@ -456,6 +453,12 @@ static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
         return 0;
 }
 
+static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
+                          unsigned int Fref, unsigned int Fout)
+{
+        return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout);
+}
+
 static int configure_clock(struct snd_soc_codec *codec)
 {
         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
@@ -715,7 +718,8 @@ static int clk_sys_event(struct snd_soc_dapm_widget *w,
 static int class_w_put(struct snd_kcontrol *kcontrol,
                        struct snd_ctl_elem_value *ucontrol)
 {
-        struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget *widget = wlist->widgets[0];
         struct snd_soc_codec *codec = widget->codec;
         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
         int ret;
@@ -730,6 +734,7 @@ static int class_w_put(struct snd_kcontrol *kcontrol,
                                             0);
                 }
                 wm8993->class_w_users++;
+                wm8993->hubs_data.class_w = true;
         }
 
         /* Implement the change */
@@ -746,6 +751,7 @@ static int class_w_put(struct snd_kcontrol *kcontrol,
                                             WM8993_CP_DYN_V);
                 }
                 wm8993->class_w_users--;
+                wm8993->hubs_data.class_w = false;
         }
 
         dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
@@ -963,7 +969,7 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
                                                     wm8993->supplies);
                         if (ret != 0)
@@ -1024,6 +1030,12 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec,
                                     WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
                                     0);
 
+                snd_soc_update_bits(codec, WM8993_ANTIPOP2,
+                                    WM8993_STARTUP_BIAS_ENA |
+                                    WM8993_VMID_BUF_ENA |
+                                    WM8993_VMID_RAMP_MASK |
+                                    WM8993_BIAS_SRC, 0);
+
 #ifdef CONFIG_REGULATOR
                /* Post 2.6.34 we will be able to get a callback when
                 * the regulators are disabled which we can use but
@@ -1038,7 +1050,7 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -1220,7 +1232,7 @@ static int wm8993_hw_params(struct snd_pcm_substream *substream,
                        - wm8993->fs);
         for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
                 cur_val = abs((wm8993->sysclk_rate /
-                               clk_sys_rates[i].ratio) - wm8993->fs);;
+                               clk_sys_rates[i].ratio) - wm8993->fs);
                 if (cur_val < best_val) {
                         best = i;
                         best_val = cur_val;
@@ -1394,8 +1406,8 @@ static struct snd_soc_dai_ops wm8993_ops = {
                         SNDRV_PCM_FMTBIT_S24_LE |\
                         SNDRV_PCM_FMTBIT_S32_LE)
 
-struct snd_soc_dai wm8993_dai = {
-        .name = "WM8993",
+static struct snd_soc_dai_driver wm8993_dai = {
+        .name = "wm8993-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 1,
@@ -1413,32 +1425,82 @@ struct snd_soc_dai wm8993_dai = {
         .ops = &wm8993_ops,
         .symmetric_rates = 1,
 };
-EXPORT_SYMBOL_GPL(wm8993_dai);
-
-static struct snd_soc_codec *wm8993_codec;
 
-static int wm8993_probe(struct platform_device *pdev)
+static int wm8993_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        struct wm8993_priv *wm8993;
-        int ret = 0;
+        struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret, i, val;
 
-        if (!wm8993_codec) {
-                dev_err(&pdev->dev, "I2C device not yet probed\n");
-                goto err;
+        wm8993->hubs_data.hp_startup_mode = 1;
+        wm8993->hubs_data.dcs_codes = -2;
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
-        socdev->card->codec = wm8993_codec;
-        codec = wm8993_codec;
-        wm8993 = snd_soc_codec_get_drvdata(codec);
+        for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
+                wm8993->supplies[i].supply = wm8993_supply_names[i];
 
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms\n");
-                goto err;
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies),
+                                 wm8993->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                return ret;
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
+                                    wm8993->supplies);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                goto err_get;
         }
 
+        val = snd_soc_read(codec, WM8993_SOFTWARE_RESET);
+        if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
+                dev_err(codec->dev, "Invalid ID register value %x\n", val);
+                ret = -EINVAL;
+                goto err_enable;
+        }
+
+        ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
+        if (ret != 0)
+                goto err_enable;
+
+        codec->cache_only = 1;
+
+        /* By default we're using the output mixers */
+        wm8993->class_w_users = 2;
+
+        /* Latch volume update bits and default ZC on */
+        snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
+                            WM8993_DAC_VU, WM8993_DAC_VU);
+        snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
+                            WM8993_ADC_VU, WM8993_ADC_VU);
+
+        /* Manualy manage the HPOUT sequencing for independent stereo
+         * control. */
+        snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
+                            WM8993_HPOUT1_AUTO_PU, 0);
+
+        /* Use automatic clock configuration */
+        snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
+
+        wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
+                                      wm8993->pdata.lineout2_diff,
+                                      wm8993->pdata.lineout1fb,
+                                      wm8993->pdata.lineout2fb,
+                                      wm8993->pdata.jd_scthr,
+                                      wm8993->pdata.jd_thr,
+                                      wm8993->pdata.micbias1_lvl,
+                                      wm8993->pdata.micbias2_lvl);
+
+        ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        if (ret != 0)
+                goto err_enable;
+
         snd_soc_add_controls(codec, wm8993_snd_controls,
                              ARRAY_SIZE(wm8993_snd_controls));
         if (wm8993->pdata.num_retune_configs != 0) {
@@ -1449,44 +1511,44 @@ static int wm8993_probe(struct platform_device *pdev)
                                      ARRAY_SIZE(wm8993_eq_controls));
         }
 
-        snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
+        snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
                                   ARRAY_SIZE(wm8993_dapm_widgets));
         wm_hubs_add_analogue_controls(codec);
 
-        snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
+        snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
         wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
                                     wm8993->pdata.lineout2_diff);
 
-        return ret;
+        return 0;
 
-err:
+err_enable:
+        regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
+err_get:
+        regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
         return ret;
 }
 
-static int wm8993_remove(struct platform_device *pdev)
+static int wm8993_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
+        struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
 
+        wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
         return 0;
 }
 
 #ifdef CONFIG_PM
-static int wm8993_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8993_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
         int fll_fout = wm8993->fll_fout;
         int fll_fref  = wm8993->fll_fref;
         int ret;
 
         /* Stop the FLL in an orderly fashion */
-        ret = wm8993_set_fll(codec->dai, 0, 0, 0, 0);
+        ret = _wm8993_set_fll(codec, 0, 0, 0, 0);
         if (ret != 0) {
-                dev_err(&pdev->dev, "Failed to stop FLL\n");
+                dev_err(codec->dev, "Failed to stop FLL\n");
                 return ret;
         }
 
@@ -1498,10 +1560,8 @@ static int wm8993_suspend(struct platform_device *pdev, pm_message_t state)
         return 0;
 }
 
-static int wm8993_resume(struct platform_device *pdev)
+static int wm8993_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
         int ret;
 
@@ -1515,7 +1575,7 @@ static int wm8993_resume(struct platform_device *pdev)
                 wm8993->fll_fref = 0;
                 wm8993->fll_fout = 0;
 
-                ret = wm8993_set_fll(codec->dai, 0, wm8993->fll_src,
+                ret = _wm8993_set_fll(codec, 0, wm8993->fll_src,
                                      fll_fref, fll_fout);
                 if (ret != 0)
                         dev_err(codec->dev, "Failed to restart FLL\n");
@@ -1528,162 +1588,42 @@ static int wm8993_resume(struct platform_device *pdev)
 #define wm8993_resume NULL
 #endif
 
-struct snd_soc_codec_device soc_codec_dev_wm8993 = {
+static struct snd_soc_codec_driver soc_codec_dev_wm8993 = {
         .probe =        wm8993_probe,
         .remove =       wm8993_remove,
         .suspend =      wm8993_suspend,
         .resume =       wm8993_resume,
+        .set_bias_level = wm8993_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8993_reg_defaults),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8993_reg_defaults,
+        .volatile_register = wm8993_volatile,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993);
 
-static int wm8993_i2c_probe(struct i2c_client *i2c,
-                            const struct i2c_device_id *id)
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8993_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
 {
         struct wm8993_priv *wm8993;
-        struct snd_soc_codec *codec;
-        unsigned int val;
         int ret;
-        int i;
-
-        if (wm8993_codec) {
-                dev_err(&i2c->dev, "A WM8993 is already registered\n");
-                return -EINVAL;
-        }
 
         wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
         if (wm8993 == NULL)
                 return -ENOMEM;
 
-        codec = &wm8993->codec;
-        if (i2c->dev.platform_data)
-                memcpy(&wm8993->pdata, i2c->dev.platform_data,
-                       sizeof(wm8993->pdata));
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->name = "WM8993";
-        codec->volatile_register = wm8993_volatile;
-        codec->reg_cache = wm8993->reg_cache;
-        codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache);
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8993_set_bias_level;
-        codec->dai = &wm8993_dai;
-        codec->num_dai = 1;
-        snd_soc_codec_set_drvdata(codec, wm8993);
-
-        wm8993->hubs_data.hp_startup_mode = 1;
-        wm8993->hubs_data.dcs_codes = -2;
-
-        memcpy(wm8993->reg_cache, wm8993_reg_defaults,
-               sizeof(wm8993->reg_cache));
-
-        ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
-        }
-
         i2c_set_clientdata(i2c, wm8993);
-        codec->control_data = i2c;
-        wm8993_codec = codec;
-
-        codec->dev = &i2c->dev;
-
-        for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
-                wm8993->supplies[i].supply = wm8993_supply_names[i];
-
-        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies),
-                                 wm8993->supplies);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
-                goto err;
-        }
-
-        ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
-                                    wm8993->supplies);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
-                goto err_get;
-        }
-
-        val = snd_soc_read(codec, WM8993_SOFTWARE_RESET);
-        if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
-                dev_err(codec->dev, "Invalid ID register value %x\n", val);
-                ret = -EINVAL;
-                goto err_enable;
-        }
-
-        ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
-        if (ret != 0)
-                goto err_enable;
-
-        codec->cache_only = 1;
-
-        /* By default we're using the output mixers */
-        wm8993->class_w_users = 2;
-
-        /* Latch volume update bits and default ZC on */
-        snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
-                            WM8993_DAC_VU, WM8993_DAC_VU);
-        snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
-                            WM8993_ADC_VU, WM8993_ADC_VU);
 
-        /* Manualy manage the HPOUT sequencing for independent stereo
-         * control. */
-        snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
-                            WM8993_HPOUT1_AUTO_PU, 0);
-
-        /* Use automatic clock configuration */
-        snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
-
-        wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
-                                      wm8993->pdata.lineout2_diff,
-                                      wm8993->pdata.lineout1fb,
-                                      wm8993->pdata.lineout2fb,
-                                      wm8993->pdata.jd_scthr,
-                                      wm8993->pdata.jd_thr,
-                                      wm8993->pdata.micbias1_lvl,
-                                      wm8993->pdata.micbias2_lvl);
-                             
-        ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-        if (ret != 0)
-                goto err_enable;
-
-        wm8993_dai.dev = codec->dev;
-
-        ret = snd_soc_register_dai(&wm8993_dai);
-        if (ret != 0)
-                goto err_bias;
-
-        ret = snd_soc_register_codec(codec);
-
-        return 0;
-
-err_bias:
-        wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
-err_enable:
-        regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
-err_get:
-        regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
-err:
-        wm8993_codec = NULL;
-        kfree(wm8993);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm8993, &wm8993_dai, 1);
+        if (ret < 0)
+                kfree(wm8993);
         return ret;
 }
 
-static int wm8993_i2c_remove(struct i2c_client *client)
+static __devexit int wm8993_i2c_remove(struct i2c_client *client)
 {
-        struct wm8993_priv *wm8993 = i2c_get_clientdata(client);
-
-        snd_soc_unregister_codec(&wm8993->codec);
-        snd_soc_unregister_dai(&wm8993_dai);
-
-        wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF);
-        regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
-        kfree(wm8993);
-
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -1695,30 +1635,34 @@ MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
 
 static struct i2c_driver wm8993_i2c_driver = {
         .driver = {
-                .name = "WM8993",
+                .name = "wm8993-codec",
                 .owner = THIS_MODULE,
         },
-        .probe = wm8993_i2c_probe,
-        .remove = wm8993_i2c_remove,
+        .probe =    wm8993_i2c_probe,
+        .remove =   __devexit_p(wm8993_i2c_remove),
         .id_table = wm8993_i2c_id,
 };
-
+#endif
 
 static int __init wm8993_modinit(void)
 {
-        int ret;
-
+        int ret = 0;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm8993_i2c_driver);
-        if (ret != 0)
-                pr_err("WM8993: Unable to register I2C driver: %d\n", ret);
-
+        if (ret != 0) {
+                pr_err("WM8993: Unable to register I2C driver: %d\n",
+                       ret);
+        }
+#endif
         return ret;
 }
 module_init(wm8993_modinit);
 
 static void __exit wm8993_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm8993_i2c_driver);
+#endif
 }
 module_exit(wm8993_exit);
 
diff --git a/sound/soc/codecs/wm8993.h b/sound/soc/codecs/wm8993.h
index 30e71ca88dad..2184617b9611 100644
--- a/sound/soc/codecs/wm8993.h
+++ b/sound/soc/codecs/wm8993.h
@@ -1,9 +1,6 @@
 #ifndef WM8993_H
 #define WM8993_H
 
-extern struct snd_soc_dai wm8993_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm8993;
-
 #define WM8993_SYSCLK_MCLK     1
 #define WM8993_SYSCLK_FLL      2
 
diff --git a/sound/soc/codecs/wm8994-tables.c b/sound/soc/codecs/wm8994-tables.c
new file mode 100644
index 000000000000..a87adbd05ee1
--- /dev/null
+++ b/sound/soc/codecs/wm8994-tables.c
@@ -0,0 +1,3147 @@
+#include "wm8994.h"
+
+const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = {
+        { 0xFFFF, 0xFFFF }, /* R0     - Software Reset */
+        { 0x3B37, 0x3B37 }, /* R1     - Power Management (1) */
+        { 0x6BF0, 0x6BF0 }, /* R2     - Power Management (2) */
+        { 0x3FF0, 0x3FF0 }, /* R3     - Power Management (3) */
+        { 0x3F3F, 0x3F3F }, /* R4     - Power Management (4) */
+        { 0x3F0F, 0x3F0F }, /* R5     - Power Management (5) */
+        { 0x003F, 0x003F }, /* R6     - Power Management (6) */
+        { 0x0000, 0x0000 }, /* R7 */
+        { 0x0000, 0x0000 }, /* R8 */
+        { 0x0000, 0x0000 }, /* R9 */
+        { 0x0000, 0x0000 }, /* R10 */
+        { 0x0000, 0x0000 }, /* R11 */
+        { 0x0000, 0x0000 }, /* R12 */
+        { 0x0000, 0x0000 }, /* R13 */
+        { 0x0000, 0x0000 }, /* R14 */
+        { 0x0000, 0x0000 }, /* R15 */
+        { 0x0000, 0x0000 }, /* R16 */
+        { 0x0000, 0x0000 }, /* R17 */
+        { 0x0000, 0x0000 }, /* R18 */
+        { 0x0000, 0x0000 }, /* R19 */
+        { 0x0000, 0x0000 }, /* R20 */
+        { 0x01C0, 0x01C0 }, /* R21    - Input Mixer (1) */
+        { 0x0000, 0x0000 }, /* R22 */
+        { 0x0000, 0x0000 }, /* R23 */
+        { 0x00DF, 0x01DF }, /* R24    - Left Line Input 1&2 Volume */
+        { 0x00DF, 0x01DF }, /* R25    - Left Line Input 3&4 Volume */
+        { 0x00DF, 0x01DF }, /* R26    - Right Line Input 1&2 Volume */
+        { 0x00DF, 0x01DF }, /* R27    - Right Line Input 3&4 Volume */
+        { 0x00FF, 0x01FF }, /* R28    - Left Output Volume */
+        { 0x00FF, 0x01FF }, /* R29    - Right Output Volume */
+        { 0x0077, 0x0077 }, /* R30    - Line Outputs Volume */
+        { 0x0030, 0x0030 }, /* R31    - HPOUT2 Volume */
+        { 0x00FF, 0x01FF }, /* R32    - Left OPGA Volume */
+        { 0x00FF, 0x01FF }, /* R33    - Right OPGA Volume */
+        { 0x007F, 0x007F }, /* R34    - SPKMIXL Attenuation */
+        { 0x017F, 0x017F }, /* R35    - SPKMIXR Attenuation */
+        { 0x003F, 0x003F }, /* R36    - SPKOUT Mixers */
+        { 0x003F, 0x003F }, /* R37    - ClassD */
+        { 0x00FF, 0x01FF }, /* R38    - Speaker Volume Left */
+        { 0x00FF, 0x01FF }, /* R39    - Speaker Volume Right */
+        { 0x00FF, 0x00FF }, /* R40    - Input Mixer (2) */
+        { 0x01B7, 0x01B7 }, /* R41    - Input Mixer (3) */
+        { 0x01B7, 0x01B7 }, /* R42    - Input Mixer (4) */
+        { 0x01C7, 0x01C7 }, /* R43    - Input Mixer (5) */
+        { 0x01C7, 0x01C7 }, /* R44    - Input Mixer (6) */
+        { 0x01FF, 0x01FF }, /* R45    - Output Mixer (1) */
+        { 0x01FF, 0x01FF }, /* R46    - Output Mixer (2) */
+        { 0x0FFF, 0x0FFF }, /* R47    - Output Mixer (3) */
+        { 0x0FFF, 0x0FFF }, /* R48    - Output Mixer (4) */
+        { 0x0FFF, 0x0FFF }, /* R49    - Output Mixer (5) */
+        { 0x0FFF, 0x0FFF }, /* R50    - Output Mixer (6) */
+        { 0x0038, 0x0038 }, /* R51    - HPOUT2 Mixer */
+        { 0x0077, 0x0077 }, /* R52    - Line Mixer (1) */
+        { 0x0077, 0x0077 }, /* R53    - Line Mixer (2) */
+        { 0x03FF, 0x03FF }, /* R54    - Speaker Mixer */
+        { 0x00C1, 0x00C1 }, /* R55    - Additional Control */
+        { 0x00F0, 0x00F0 }, /* R56    - AntiPOP (1) */
+        { 0x01EF, 0x01EF }, /* R57    - AntiPOP (2) */
+        { 0x00FF, 0x00FF }, /* R58    - MICBIAS */
+        { 0x000F, 0x000F }, /* R59    - LDO 1 */
+        { 0x0007, 0x0007 }, /* R60    - LDO 2 */
+        { 0xFFFF, 0xFFFF }, /* R61 */
+        { 0xFFFF, 0xFFFF }, /* R62 */
+        { 0x0000, 0x0000 }, /* R63 */
+        { 0x0000, 0x0000 }, /* R64 */
+        { 0x0000, 0x0000 }, /* R65 */
+        { 0x0000, 0x0000 }, /* R66 */
+        { 0x0000, 0x0000 }, /* R67 */
+        { 0x0000, 0x0000 }, /* R68 */
+        { 0x0000, 0x0000 }, /* R69 */
+        { 0x0000, 0x0000 }, /* R70 */
+        { 0x0000, 0x0000 }, /* R71 */
+        { 0x0000, 0x0000 }, /* R72 */
+        { 0x0000, 0x0000 }, /* R73 */
+        { 0x0000, 0x0000 }, /* R74 */
+        { 0x0000, 0x0000 }, /* R75 */
+        { 0x8000, 0x8000 }, /* R76    - Charge Pump (1) */
+        { 0x0000, 0x0000 }, /* R77 */
+        { 0x0000, 0x0000 }, /* R78 */
+        { 0x0000, 0x0000 }, /* R79 */
+        { 0x0000, 0x0000 }, /* R80 */
+        { 0x0301, 0x0301 }, /* R81    - Class W (1) */
+        { 0x0000, 0x0000 }, /* R82 */
+        { 0x0000, 0x0000 }, /* R83 */
+        { 0x333F, 0x333F }, /* R84    - DC Servo (1) */
+        { 0x0FEF, 0x0FEF }, /* R85    - DC Servo (2) */
+        { 0x0000, 0x0000 }, /* R86 */
+        { 0xFFFF, 0xFFFF }, /* R87    - DC Servo (4) */
+        { 0x0333, 0x0000 }, /* R88    - DC Servo Readback */
+        { 0x0000, 0x0000 }, /* R89 */
+        { 0x0000, 0x0000 }, /* R90 */
+        { 0x0000, 0x0000 }, /* R91 */
+        { 0x0000, 0x0000 }, /* R92 */
+        { 0x0000, 0x0000 }, /* R93 */
+        { 0x0000, 0x0000 }, /* R94 */
+        { 0x0000, 0x0000 }, /* R95 */
+        { 0x00EE, 0x00EE }, /* R96    - Analogue HP (1) */
+        { 0x0000, 0x0000 }, /* R97 */
+        { 0x0000, 0x0000 }, /* R98 */
+        { 0x0000, 0x0000 }, /* R99 */
+        { 0x0000, 0x0000 }, /* R100 */
+        { 0x0000, 0x0000 }, /* R101 */
+        { 0x0000, 0x0000 }, /* R102 */
+        { 0x0000, 0x0000 }, /* R103 */
+        { 0x0000, 0x0000 }, /* R104 */
+        { 0x0000, 0x0000 }, /* R105 */
+        { 0x0000, 0x0000 }, /* R106 */
+        { 0x0000, 0x0000 }, /* R107 */
+        { 0x0000, 0x0000 }, /* R108 */
+        { 0x0000, 0x0000 }, /* R109 */
+        { 0x0000, 0x0000 }, /* R110 */
+        { 0x0000, 0x0000 }, /* R111 */
+        { 0x0000, 0x0000 }, /* R112 */
+        { 0x0000, 0x0000 }, /* R113 */
+        { 0x0000, 0x0000 }, /* R114 */
+        { 0x0000, 0x0000 }, /* R115 */
+        { 0x0000, 0x0000 }, /* R116 */
+        { 0x0000, 0x0000 }, /* R117 */
+        { 0x0000, 0x0000 }, /* R118 */
+        { 0x0000, 0x0000 }, /* R119 */
+        { 0x0000, 0x0000 }, /* R120 */
+        { 0x0000, 0x0000 }, /* R121 */
+        { 0x0000, 0x0000 }, /* R122 */
+        { 0x0000, 0x0000 }, /* R123 */
+        { 0x0000, 0x0000 }, /* R124 */
+        { 0x0000, 0x0000 }, /* R125 */
+        { 0x0000, 0x0000 }, /* R126 */
+        { 0x0000, 0x0000 }, /* R127 */
+        { 0x0000, 0x0000 }, /* R128 */
+        { 0x0000, 0x0000 }, /* R129 */
+        { 0x0000, 0x0000 }, /* R130 */
+        { 0x0000, 0x0000 }, /* R131 */
+        { 0x0000, 0x0000 }, /* R132 */
+        { 0x0000, 0x0000 }, /* R133 */
+        { 0x0000, 0x0000 }, /* R134 */
+        { 0x0000, 0x0000 }, /* R135 */
+        { 0x0000, 0x0000 }, /* R136 */
+        { 0x0000, 0x0000 }, /* R137 */
+        { 0x0000, 0x0000 }, /* R138 */
+        { 0x0000, 0x0000 }, /* R139 */
+        { 0x0000, 0x0000 }, /* R140 */
+        { 0x0000, 0x0000 }, /* R141 */
+        { 0x0000, 0x0000 }, /* R142 */
+        { 0x0000, 0x0000 }, /* R143 */
+        { 0x0000, 0x0000 }, /* R144 */
+        { 0x0000, 0x0000 }, /* R145 */
+        { 0x0000, 0x0000 }, /* R146 */
+        { 0x0000, 0x0000 }, /* R147 */
+        { 0x0000, 0x0000 }, /* R148 */
+        { 0x0000, 0x0000 }, /* R149 */
+        { 0x0000, 0x0000 }, /* R150 */
+        { 0x0000, 0x0000 }, /* R151 */
+        { 0x0000, 0x0000 }, /* R152 */
+        { 0x0000, 0x0000 }, /* R153 */
+        { 0x0000, 0x0000 }, /* R154 */
+        { 0x0000, 0x0000 }, /* R155 */
+        { 0x0000, 0x0000 }, /* R156 */
+        { 0x0000, 0x0000 }, /* R157 */
+        { 0x0000, 0x0000 }, /* R158 */
+        { 0x0000, 0x0000 }, /* R159 */
+        { 0x0000, 0x0000 }, /* R160 */
+        { 0x0000, 0x0000 }, /* R161 */
+        { 0x0000, 0x0000 }, /* R162 */
+        { 0x0000, 0x0000 }, /* R163 */
+        { 0x0000, 0x0000 }, /* R164 */
+        { 0x0000, 0x0000 }, /* R165 */
+        { 0x0000, 0x0000 }, /* R166 */
+        { 0x0000, 0x0000 }, /* R167 */
+        { 0x0000, 0x0000 }, /* R168 */
+        { 0x0000, 0x0000 }, /* R169 */
+        { 0x0000, 0x0000 }, /* R170 */
+        { 0x0000, 0x0000 }, /* R171 */
+        { 0x0000, 0x0000 }, /* R172 */
+        { 0x0000, 0x0000 }, /* R173 */
+        { 0x0000, 0x0000 }, /* R174 */
+        { 0x0000, 0x0000 }, /* R175 */
+        { 0x0000, 0x0000 }, /* R176 */
+        { 0x0000, 0x0000 }, /* R177 */
+        { 0x0000, 0x0000 }, /* R178 */
+        { 0x0000, 0x0000 }, /* R179 */
+        { 0x0000, 0x0000 }, /* R180 */
+        { 0x0000, 0x0000 }, /* R181 */
+        { 0x0000, 0x0000 }, /* R182 */
+        { 0x0000, 0x0000 }, /* R183 */
+        { 0x0000, 0x0000 }, /* R184 */
+        { 0x0000, 0x0000 }, /* R185 */
+        { 0x0000, 0x0000 }, /* R186 */
+        { 0x0000, 0x0000 }, /* R187 */
+        { 0x0000, 0x0000 }, /* R188 */
+        { 0x0000, 0x0000 }, /* R189 */
+        { 0x0000, 0x0000 }, /* R190 */
+        { 0x0000, 0x0000 }, /* R191 */
+        { 0x0000, 0x0000 }, /* R192 */
+        { 0x0000, 0x0000 }, /* R193 */
+        { 0x0000, 0x0000 }, /* R194 */
+        { 0x0000, 0x0000 }, /* R195 */
+        { 0x0000, 0x0000 }, /* R196 */
+        { 0x0000, 0x0000 }, /* R197 */
+        { 0x0000, 0x0000 }, /* R198 */
+        { 0x0000, 0x0000 }, /* R199 */
+        { 0x0000, 0x0000 }, /* R200 */
+        { 0x0000, 0x0000 }, /* R201 */
+        { 0x0000, 0x0000 }, /* R202 */
+        { 0x0000, 0x0000 }, /* R203 */
+        { 0x0000, 0x0000 }, /* R204 */
+        { 0x0000, 0x0000 }, /* R205 */
+        { 0x0000, 0x0000 }, /* R206 */
+        { 0x0000, 0x0000 }, /* R207 */
+        { 0xFFFF, 0xFFFF }, /* R208 */
+        { 0xFFFF, 0xFFFF }, /* R209 */
+        { 0xFFFF, 0xFFFF }, /* R210 */
+        { 0x0000, 0x0000 }, /* R211 */
+        { 0x0000, 0x0000 }, /* R212 */
+        { 0x0000, 0x0000 }, /* R213 */
+        { 0x0000, 0x0000 }, /* R214 */
+        { 0x0000, 0x0000 }, /* R215 */
+        { 0x0000, 0x0000 }, /* R216 */
+        { 0x0000, 0x0000 }, /* R217 */
+        { 0x0000, 0x0000 }, /* R218 */
+        { 0x0000, 0x0000 }, /* R219 */
+        { 0x0000, 0x0000 }, /* R220 */
+        { 0x0000, 0x0000 }, /* R221 */
+        { 0x0000, 0x0000 }, /* R222 */
+        { 0x0000, 0x0000 }, /* R223 */
+        { 0x0000, 0x0000 }, /* R224 */
+        { 0x0000, 0x0000 }, /* R225 */
+        { 0x0000, 0x0000 }, /* R226 */
+        { 0x0000, 0x0000 }, /* R227 */
+        { 0x0000, 0x0000 }, /* R228 */
+        { 0x0000, 0x0000 }, /* R229 */
+        { 0x0000, 0x0000 }, /* R230 */
+        { 0x0000, 0x0000 }, /* R231 */
+        { 0x0000, 0x0000 }, /* R232 */
+        { 0x0000, 0x0000 }, /* R233 */
+        { 0x0000, 0x0000 }, /* R234 */
+        { 0x0000, 0x0000 }, /* R235 */
+        { 0x0000, 0x0000 }, /* R236 */
+        { 0x0000, 0x0000 }, /* R237 */
+        { 0x0000, 0x0000 }, /* R238 */
+        { 0x0000, 0x0000 }, /* R239 */
+        { 0x0000, 0x0000 }, /* R240 */
+        { 0x0000, 0x0000 }, /* R241 */
+        { 0x0000, 0x0000 }, /* R242 */
+        { 0x0000, 0x0000 }, /* R243 */
+        { 0x0000, 0x0000 }, /* R244 */
+        { 0x0000, 0x0000 }, /* R245 */
+        { 0x0000, 0x0000 }, /* R246 */
+        { 0x0000, 0x0000 }, /* R247 */
+        { 0x0000, 0x0000 }, /* R248 */
+        { 0x0000, 0x0000 }, /* R249 */
+        { 0x0000, 0x0000 }, /* R250 */
+        { 0x0000, 0x0000 }, /* R251 */
+        { 0x0000, 0x0000 }, /* R252 */
+        { 0x0000, 0x0000 }, /* R253 */
+        { 0x0000, 0x0000 }, /* R254 */
+        { 0x0000, 0x0000 }, /* R255 */
+        { 0x000F, 0x0000 }, /* R256   - Chip Revision */
+        { 0x0074, 0x0074 }, /* R257   - Control Interface */
+        { 0x0000, 0x0000 }, /* R258 */
+        { 0x0000, 0x0000 }, /* R259 */
+        { 0x0000, 0x0000 }, /* R260 */
+        { 0x0000, 0x0000 }, /* R261 */
+        { 0x0000, 0x0000 }, /* R262 */
+        { 0x0000, 0x0000 }, /* R263 */
+        { 0x0000, 0x0000 }, /* R264 */
+        { 0x0000, 0x0000 }, /* R265 */
+        { 0x0000, 0x0000 }, /* R266 */
+        { 0x0000, 0x0000 }, /* R267 */
+        { 0x0000, 0x0000 }, /* R268 */
+        { 0x0000, 0x0000 }, /* R269 */
+        { 0x0000, 0x0000 }, /* R270 */
+        { 0x0000, 0x0000 }, /* R271 */
+        { 0x807F, 0x837F }, /* R272   - Write Sequencer Ctrl (1) */
+        { 0x017F, 0x0000 }, /* R273   - Write Sequencer Ctrl (2) */
+        { 0x0000, 0x0000 }, /* R274 */
+        { 0x0000, 0x0000 }, /* R275 */
+        { 0x0000, 0x0000 }, /* R276 */
+        { 0x0000, 0x0000 }, /* R277 */
+        { 0x0000, 0x0000 }, /* R278 */
+        { 0x0000, 0x0000 }, /* R279 */
+        { 0x0000, 0x0000 }, /* R280 */
+        { 0x0000, 0x0000 }, /* R281 */
+        { 0x0000, 0x0000 }, /* R282 */
+        { 0x0000, 0x0000 }, /* R283 */
+        { 0x0000, 0x0000 }, /* R284 */
+        { 0x0000, 0x0000 }, /* R285 */
+        { 0x0000, 0x0000 }, /* R286 */
+        { 0x0000, 0x0000 }, /* R287 */
+        { 0x0000, 0x0000 }, /* R288 */
+        { 0x0000, 0x0000 }, /* R289 */
+        { 0x0000, 0x0000 }, /* R290 */
+        { 0x0000, 0x0000 }, /* R291 */
+        { 0x0000, 0x0000 }, /* R292 */
+        { 0x0000, 0x0000 }, /* R293 */
+        { 0x0000, 0x0000 }, /* R294 */
+        { 0x0000, 0x0000 }, /* R295 */
+        { 0x0000, 0x0000 }, /* R296 */
+        { 0x0000, 0x0000 }, /* R297 */
+        { 0x0000, 0x0000 }, /* R298 */
+        { 0x0000, 0x0000 }, /* R299 */
+        { 0x0000, 0x0000 }, /* R300 */
+        { 0x0000, 0x0000 }, /* R301 */
+        { 0x0000, 0x0000 }, /* R302 */
+        { 0x0000, 0x0000 }, /* R303 */
+        { 0x0000, 0x0000 }, /* R304 */
+        { 0x0000, 0x0000 }, /* R305 */
+        { 0x0000, 0x0000 }, /* R306 */
+        { 0x0000, 0x0000 }, /* R307 */
+        { 0x0000, 0x0000 }, /* R308 */
+        { 0x0000, 0x0000 }, /* R309 */
+        { 0x0000, 0x0000 }, /* R310 */
+        { 0x0000, 0x0000 }, /* R311 */
+        { 0x0000, 0x0000 }, /* R312 */
+        { 0x0000, 0x0000 }, /* R313 */
+        { 0x0000, 0x0000 }, /* R314 */
+        { 0x0000, 0x0000 }, /* R315 */
+        { 0x0000, 0x0000 }, /* R316 */
+        { 0x0000, 0x0000 }, /* R317 */
+        { 0x0000, 0x0000 }, /* R318 */
+        { 0x0000, 0x0000 }, /* R319 */
+        { 0x0000, 0x0000 }, /* R320 */
+        { 0x0000, 0x0000 }, /* R321 */
+        { 0x0000, 0x0000 }, /* R322 */
+        { 0x0000, 0x0000 }, /* R323 */
+        { 0x0000, 0x0000 }, /* R324 */
+        { 0x0000, 0x0000 }, /* R325 */
+        { 0x0000, 0x0000 }, /* R326 */
+        { 0x0000, 0x0000 }, /* R327 */
+        { 0x0000, 0x0000 }, /* R328 */
+        { 0x0000, 0x0000 }, /* R329 */
+        { 0x0000, 0x0000 }, /* R330 */
+        { 0x0000, 0x0000 }, /* R331 */
+        { 0x0000, 0x0000 }, /* R332 */
+        { 0x0000, 0x0000 }, /* R333 */
+        { 0x0000, 0x0000 }, /* R334 */
+        { 0x0000, 0x0000 }, /* R335 */
+        { 0x0000, 0x0000 }, /* R336 */
+        { 0x0000, 0x0000 }, /* R337 */
+        { 0x0000, 0x0000 }, /* R338 */
+        { 0x0000, 0x0000 }, /* R339 */
+        { 0x0000, 0x0000 }, /* R340 */
+        { 0x0000, 0x0000 }, /* R341 */
+        { 0x0000, 0x0000 }, /* R342 */
+        { 0x0000, 0x0000 }, /* R343 */
+        { 0x0000, 0x0000 }, /* R344 */
+        { 0x0000, 0x0000 }, /* R345 */
+        { 0x0000, 0x0000 }, /* R346 */
+        { 0x0000, 0x0000 }, /* R347 */
+        { 0x0000, 0x0000 }, /* R348 */
+        { 0x0000, 0x0000 }, /* R349 */
+        { 0x0000, 0x0000 }, /* R350 */
+        { 0x0000, 0x0000 }, /* R351 */
+        { 0x0000, 0x0000 }, /* R352 */
+        { 0x0000, 0x0000 }, /* R353 */
+        { 0x0000, 0x0000 }, /* R354 */
+        { 0x0000, 0x0000 }, /* R355 */
+        { 0x0000, 0x0000 }, /* R356 */
+        { 0x0000, 0x0000 }, /* R357 */
+        { 0x0000, 0x0000 }, /* R358 */
+        { 0x0000, 0x0000 }, /* R359 */
+        { 0x0000, 0x0000 }, /* R360 */
+        { 0x0000, 0x0000 }, /* R361 */
+        { 0x0000, 0x0000 }, /* R362 */
+        { 0x0000, 0x0000 }, /* R363 */
+        { 0x0000, 0x0000 }, /* R364 */
+        { 0x0000, 0x0000 }, /* R365 */
+        { 0x0000, 0x0000 }, /* R366 */
+        { 0x0000, 0x0000 }, /* R367 */
+        { 0x0000, 0x0000 }, /* R368 */
+        { 0x0000, 0x0000 }, /* R369 */
+        { 0x0000, 0x0000 }, /* R370 */
+        { 0x0000, 0x0000 }, /* R371 */
+        { 0x0000, 0x0000 }, /* R372 */
+        { 0x0000, 0x0000 }, /* R373 */
+        { 0x0000, 0x0000 }, /* R374 */
+        { 0x0000, 0x0000 }, /* R375 */
+        { 0x0000, 0x0000 }, /* R376 */
+        { 0x0000, 0x0000 }, /* R377 */
+        { 0x0000, 0x0000 }, /* R378 */
+        { 0x0000, 0x0000 }, /* R379 */
+        { 0x0000, 0x0000 }, /* R380 */
+        { 0x0000, 0x0000 }, /* R381 */
+        { 0x0000, 0x0000 }, /* R382 */
+        { 0x0000, 0x0000 }, /* R383 */
+        { 0x0000, 0x0000 }, /* R384 */
+        { 0x0000, 0x0000 }, /* R385 */
+        { 0x0000, 0x0000 }, /* R386 */
+        { 0x0000, 0x0000 }, /* R387 */
+        { 0x0000, 0x0000 }, /* R388 */
+        { 0x0000, 0x0000 }, /* R389 */
+        { 0x0000, 0x0000 }, /* R390 */
+        { 0x0000, 0x0000 }, /* R391 */
+        { 0x0000, 0x0000 }, /* R392 */
+        { 0x0000, 0x0000 }, /* R393 */
+        { 0x0000, 0x0000 }, /* R394 */
+        { 0x0000, 0x0000 }, /* R395 */
+        { 0x0000, 0x0000 }, /* R396 */
+        { 0x0000, 0x0000 }, /* R397 */
+        { 0x0000, 0x0000 }, /* R398 */
+        { 0x0000, 0x0000 }, /* R399 */
+        { 0x0000, 0x0000 }, /* R400 */
+        { 0x0000, 0x0000 }, /* R401 */
+        { 0x0000, 0x0000 }, /* R402 */
+        { 0x0000, 0x0000 }, /* R403 */
+        { 0x0000, 0x0000 }, /* R404 */
+        { 0x0000, 0x0000 }, /* R405 */
+        { 0x0000, 0x0000 }, /* R406 */
+        { 0x0000, 0x0000 }, /* R407 */
+        { 0x0000, 0x0000 }, /* R408 */
+        { 0x0000, 0x0000 }, /* R409 */
+        { 0x0000, 0x0000 }, /* R410 */
+        { 0x0000, 0x0000 }, /* R411 */
+        { 0x0000, 0x0000 }, /* R412 */
+        { 0x0000, 0x0000 }, /* R413 */
+        { 0x0000, 0x0000 }, /* R414 */
+        { 0x0000, 0x0000 }, /* R415 */
+        { 0x0000, 0x0000 }, /* R416 */
+        { 0x0000, 0x0000 }, /* R417 */
+        { 0x0000, 0x0000 }, /* R418 */
+        { 0x0000, 0x0000 }, /* R419 */
+        { 0x0000, 0x0000 }, /* R420 */
+        { 0x0000, 0x0000 }, /* R421 */
+        { 0x0000, 0x0000 }, /* R422 */
+        { 0x0000, 0x0000 }, /* R423 */
+        { 0x0000, 0x0000 }, /* R424 */
+        { 0x0000, 0x0000 }, /* R425 */
+        { 0x0000, 0x0000 }, /* R426 */
+        { 0x0000, 0x0000 }, /* R427 */
+        { 0x0000, 0x0000 }, /* R428 */
+        { 0x0000, 0x0000 }, /* R429 */
+        { 0x0000, 0x0000 }, /* R430 */
+        { 0x0000, 0x0000 }, /* R431 */
+        { 0x0000, 0x0000 }, /* R432 */
+        { 0x0000, 0x0000 }, /* R433 */
+        { 0x0000, 0x0000 }, /* R434 */
+        { 0x0000, 0x0000 }, /* R435 */
+        { 0x0000, 0x0000 }, /* R436 */
+        { 0x0000, 0x0000 }, /* R437 */
+        { 0x0000, 0x0000 }, /* R438 */
+        { 0x0000, 0x0000 }, /* R439 */
+        { 0x0000, 0x0000 }, /* R440 */
+        { 0x0000, 0x0000 }, /* R441 */
+        { 0x0000, 0x0000 }, /* R442 */
+        { 0x0000, 0x0000 }, /* R443 */
+        { 0x0000, 0x0000 }, /* R444 */
+        { 0x0000, 0x0000 }, /* R445 */
+        { 0x0000, 0x0000 }, /* R446 */
+        { 0x0000, 0x0000 }, /* R447 */
+        { 0x0000, 0x0000 }, /* R448 */
+        { 0x0000, 0x0000 }, /* R449 */
+        { 0x0000, 0x0000 }, /* R450 */
+        { 0x0000, 0x0000 }, /* R451 */
+        { 0x0000, 0x0000 }, /* R452 */
+        { 0x0000, 0x0000 }, /* R453 */
+        { 0x0000, 0x0000 }, /* R454 */
+        { 0x0000, 0x0000 }, /* R455 */
+        { 0x0000, 0x0000 }, /* R456 */
+        { 0x0000, 0x0000 }, /* R457 */
+        { 0x0000, 0x0000 }, /* R458 */
+        { 0x0000, 0x0000 }, /* R459 */
+        { 0x0000, 0x0000 }, /* R460 */
+        { 0x0000, 0x0000 }, /* R461 */
+        { 0x0000, 0x0000 }, /* R462 */
+        { 0x0000, 0x0000 }, /* R463 */
+        { 0x0000, 0x0000 }, /* R464 */
+        { 0x0000, 0x0000 }, /* R465 */
+        { 0x0000, 0x0000 }, /* R466 */
+        { 0x0000, 0x0000 }, /* R467 */
+        { 0x0000, 0x0000 }, /* R468 */
+        { 0x0000, 0x0000 }, /* R469 */
+        { 0x0000, 0x0000 }, /* R470 */
+        { 0x0000, 0x0000 }, /* R471 */
+        { 0x0000, 0x0000 }, /* R472 */
+        { 0x0000, 0x0000 }, /* R473 */
+        { 0x0000, 0x0000 }, /* R474 */
+        { 0x0000, 0x0000 }, /* R475 */
+        { 0x0000, 0x0000 }, /* R476 */
+        { 0x0000, 0x0000 }, /* R477 */
+        { 0x0000, 0x0000 }, /* R478 */
+        { 0x0000, 0x0000 }, /* R479 */
+        { 0x0000, 0x0000 }, /* R480 */
+        { 0x0000, 0x0000 }, /* R481 */
+        { 0x0000, 0x0000 }, /* R482 */
+        { 0x0000, 0x0000 }, /* R483 */
+        { 0x0000, 0x0000 }, /* R484 */
+        { 0x0000, 0x0000 }, /* R485 */
+        { 0x0000, 0x0000 }, /* R486 */
+        { 0x0000, 0x0000 }, /* R487 */
+        { 0x0000, 0x0000 }, /* R488 */
+        { 0x0000, 0x0000 }, /* R489 */
+        { 0x0000, 0x0000 }, /* R490 */
+        { 0x0000, 0x0000 }, /* R491 */
+        { 0x0000, 0x0000 }, /* R492 */
+        { 0x0000, 0x0000 }, /* R493 */
+        { 0x0000, 0x0000 }, /* R494 */
+        { 0x0000, 0x0000 }, /* R495 */
+        { 0x0000, 0x0000 }, /* R496 */
+        { 0x0000, 0x0000 }, /* R497 */
+        { 0x0000, 0x0000 }, /* R498 */
+        { 0x0000, 0x0000 }, /* R499 */
+        { 0x0000, 0x0000 }, /* R500 */
+        { 0x0000, 0x0000 }, /* R501 */
+        { 0x0000, 0x0000 }, /* R502 */
+        { 0x0000, 0x0000 }, /* R503 */
+        { 0x0000, 0x0000 }, /* R504 */
+        { 0x0000, 0x0000 }, /* R505 */
+        { 0x0000, 0x0000 }, /* R506 */
+        { 0x0000, 0x0000 }, /* R507 */
+        { 0x0000, 0x0000 }, /* R508 */
+        { 0x0000, 0x0000 }, /* R509 */
+        { 0x0000, 0x0000 }, /* R510 */
+        { 0x0000, 0x0000 }, /* R511 */
+        { 0x001F, 0x001F }, /* R512   - AIF1 Clocking (1) */
+        { 0x003F, 0x003F }, /* R513   - AIF1 Clocking (2) */
+        { 0x0000, 0x0000 }, /* R514 */
+        { 0x0000, 0x0000 }, /* R515 */
+        { 0x001F, 0x001F }, /* R516   - AIF2 Clocking (1) */
+        { 0x003F, 0x003F }, /* R517   - AIF2 Clocking (2) */
+        { 0x0000, 0x0000 }, /* R518 */
+        { 0x0000, 0x0000 }, /* R519 */
+        { 0x001F, 0x001F }, /* R520   - Clocking (1) */
+        { 0x0777, 0x0777 }, /* R521   - Clocking (2) */
+        { 0x0000, 0x0000 }, /* R522 */
+        { 0x0000, 0x0000 }, /* R523 */
+        { 0x0000, 0x0000 }, /* R524 */
+        { 0x0000, 0x0000 }, /* R525 */
+        { 0x0000, 0x0000 }, /* R526 */
+        { 0x0000, 0x0000 }, /* R527 */
+        { 0x00FF, 0x00FF }, /* R528   - AIF1 Rate */
+        { 0x00FF, 0x00FF }, /* R529   - AIF2 Rate */
+        { 0x000F, 0x0000 }, /* R530   - Rate Status */
+        { 0x0000, 0x0000 }, /* R531 */
+        { 0x0000, 0x0000 }, /* R532 */
+        { 0x0000, 0x0000 }, /* R533 */
+        { 0x0000, 0x0000 }, /* R534 */
+        { 0x0000, 0x0000 }, /* R535 */
+        { 0x0000, 0x0000 }, /* R536 */
+        { 0x0000, 0x0000 }, /* R537 */
+        { 0x0000, 0x0000 }, /* R538 */
+        { 0x0000, 0x0000 }, /* R539 */
+        { 0x0000, 0x0000 }, /* R540 */
+        { 0x0000, 0x0000 }, /* R541 */
+        { 0x0000, 0x0000 }, /* R542 */
+        { 0x0000, 0x0000 }, /* R543 */
+        { 0x0007, 0x0007 }, /* R544   - FLL1 Control (1) */
+        { 0x3F77, 0x3F77 }, /* R545   - FLL1 Control (2) */
+        { 0xFFFF, 0xFFFF }, /* R546   - FLL1 Control (3) */
+        { 0x7FEF, 0x7FEF }, /* R547   - FLL1 Control (4) */
+        { 0x1FDB, 0x1FDB }, /* R548   - FLL1 Control (5) */
+        { 0x0000, 0x0000 }, /* R549 */
+        { 0x0000, 0x0000 }, /* R550 */
+        { 0x0000, 0x0000 }, /* R551 */
+        { 0x0000, 0x0000 }, /* R552 */
+        { 0x0000, 0x0000 }, /* R553 */
+        { 0x0000, 0x0000 }, /* R554 */
+        { 0x0000, 0x0000 }, /* R555 */
+        { 0x0000, 0x0000 }, /* R556 */
+        { 0x0000, 0x0000 }, /* R557 */
+        { 0x0000, 0x0000 }, /* R558 */
+        { 0x0000, 0x0000 }, /* R559 */
+        { 0x0000, 0x0000 }, /* R560 */
+        { 0x0000, 0x0000 }, /* R561 */
+        { 0x0000, 0x0000 }, /* R562 */
+        { 0x0000, 0x0000 }, /* R563 */
+        { 0x0000, 0x0000 }, /* R564 */
+        { 0x0000, 0x0000 }, /* R565 */
+        { 0x0000, 0x0000 }, /* R566 */
+        { 0x0000, 0x0000 }, /* R567 */
+        { 0x0000, 0x0000 }, /* R568 */
+        { 0x0000, 0x0000 }, /* R569 */
+        { 0x0000, 0x0000 }, /* R570 */
+        { 0x0000, 0x0000 }, /* R571 */
+        { 0x0000, 0x0000 }, /* R572 */
+        { 0x0000, 0x0000 }, /* R573 */
+        { 0x0000, 0x0000 }, /* R574 */
+        { 0x0000, 0x0000 }, /* R575 */
+        { 0x0007, 0x0007 }, /* R576   - FLL2 Control (1) */
+        { 0x3F77, 0x3F77 }, /* R577   - FLL2 Control (2) */
+        { 0xFFFF, 0xFFFF }, /* R578   - FLL2 Control (3) */
+        { 0x7FEF, 0x7FEF }, /* R579   - FLL2 Control (4) */
+        { 0x1FDB, 0x1FDB }, /* R580   - FLL2 Control (5) */
+        { 0x0000, 0x0000 }, /* R581 */
+        { 0x0000, 0x0000 }, /* R582 */
+        { 0x0000, 0x0000 }, /* R583 */
+        { 0x0000, 0x0000 }, /* R584 */
+        { 0x0000, 0x0000 }, /* R585 */
+        { 0x0000, 0x0000 }, /* R586 */
+        { 0x0000, 0x0000 }, /* R587 */
+        { 0x0000, 0x0000 }, /* R588 */
+        { 0x0000, 0x0000 }, /* R589 */
+        { 0x0000, 0x0000 }, /* R590 */
+        { 0x0000, 0x0000 }, /* R591 */
+        { 0x0000, 0x0000 }, /* R592 */
+        { 0x0000, 0x0000 }, /* R593 */
+        { 0x0000, 0x0000 }, /* R594 */
+        { 0x0000, 0x0000 }, /* R595 */
+        { 0x0000, 0x0000 }, /* R596 */
+        { 0x0000, 0x0000 }, /* R597 */
+        { 0x0000, 0x0000 }, /* R598 */
+        { 0x0000, 0x0000 }, /* R599 */
+        { 0x0000, 0x0000 }, /* R600 */
+        { 0x0000, 0x0000 }, /* R601 */
+        { 0x0000, 0x0000 }, /* R602 */
+        { 0x0000, 0x0000 }, /* R603 */
+        { 0x0000, 0x0000 }, /* R604 */
+        { 0x0000, 0x0000 }, /* R605 */
+        { 0x0000, 0x0000 }, /* R606 */
+        { 0x0000, 0x0000 }, /* R607 */
+        { 0x0000, 0x0000 }, /* R608 */
+        { 0x0000, 0x0000 }, /* R609 */
+        { 0x0000, 0x0000 }, /* R610 */
+        { 0x0000, 0x0000 }, /* R611 */
+        { 0x0000, 0x0000 }, /* R612 */
+        { 0x0000, 0x0000 }, /* R613 */
+        { 0x0000, 0x0000 }, /* R614 */
+        { 0x0000, 0x0000 }, /* R615 */
+        { 0x0000, 0x0000 }, /* R616 */
+        { 0x0000, 0x0000 }, /* R617 */
+        { 0x0000, 0x0000 }, /* R618 */
+        { 0x0000, 0x0000 }, /* R619 */
+        { 0x0000, 0x0000 }, /* R620 */
+        { 0x0000, 0x0000 }, /* R621 */
+        { 0x0000, 0x0000 }, /* R622 */
+        { 0x0000, 0x0000 }, /* R623 */
+        { 0x0000, 0x0000 }, /* R624 */
+        { 0x0000, 0x0000 }, /* R625 */
+        { 0x0000, 0x0000 }, /* R626 */
+        { 0x0000, 0x0000 }, /* R627 */
+        { 0x0000, 0x0000 }, /* R628 */
+        { 0x0000, 0x0000 }, /* R629 */
+        { 0x0000, 0x0000 }, /* R630 */
+        { 0x0000, 0x0000 }, /* R631 */
+        { 0x0000, 0x0000 }, /* R632 */
+        { 0x0000, 0x0000 }, /* R633 */
+        { 0x0000, 0x0000 }, /* R634 */
+        { 0x0000, 0x0000 }, /* R635 */
+        { 0x0000, 0x0000 }, /* R636 */
+        { 0x0000, 0x0000 }, /* R637 */
+        { 0x0000, 0x0000 }, /* R638 */
+        { 0x0000, 0x0000 }, /* R639 */
+        { 0x0000, 0x0000 }, /* R640 */
+        { 0x0000, 0x0000 }, /* R641 */
+        { 0x0000, 0x0000 }, /* R642 */
+        { 0x0000, 0x0000 }, /* R643 */
+        { 0x0000, 0x0000 }, /* R644 */
+        { 0x0000, 0x0000 }, /* R645 */
+        { 0x0000, 0x0000 }, /* R646 */
+        { 0x0000, 0x0000 }, /* R647 */
+        { 0x0000, 0x0000 }, /* R648 */
+        { 0x0000, 0x0000 }, /* R649 */
+        { 0x0000, 0x0000 }, /* R650 */
+        { 0x0000, 0x0000 }, /* R651 */
+        { 0x0000, 0x0000 }, /* R652 */
+        { 0x0000, 0x0000 }, /* R653 */
+        { 0x0000, 0x0000 }, /* R654 */
+        { 0x0000, 0x0000 }, /* R655 */
+        { 0x0000, 0x0000 }, /* R656 */
+        { 0x0000, 0x0000 }, /* R657 */
+        { 0x0000, 0x0000 }, /* R658 */
+        { 0x0000, 0x0000 }, /* R659 */
+        { 0x0000, 0x0000 }, /* R660 */
+        { 0x0000, 0x0000 }, /* R661 */
+        { 0x0000, 0x0000 }, /* R662 */
+        { 0x0000, 0x0000 }, /* R663 */
+        { 0x0000, 0x0000 }, /* R664 */
+        { 0x0000, 0x0000 }, /* R665 */
+        { 0x0000, 0x0000 }, /* R666 */
+        { 0x0000, 0x0000 }, /* R667 */
+        { 0x0000, 0x0000 }, /* R668 */
+        { 0x0000, 0x0000 }, /* R669 */
+        { 0x0000, 0x0000 }, /* R670 */
+        { 0x0000, 0x0000 }, /* R671 */
+        { 0x0000, 0x0000 }, /* R672 */
+        { 0x0000, 0x0000 }, /* R673 */
+        { 0x0000, 0x0000 }, /* R674 */
+        { 0x0000, 0x0000 }, /* R675 */
+        { 0x0000, 0x0000 }, /* R676 */
+        { 0x0000, 0x0000 }, /* R677 */
+        { 0x0000, 0x0000 }, /* R678 */
+        { 0x0000, 0x0000 }, /* R679 */
+        { 0x0000, 0x0000 }, /* R680 */
+        { 0x0000, 0x0000 }, /* R681 */
+        { 0x0000, 0x0000 }, /* R682 */
+        { 0x0000, 0x0000 }, /* R683 */
+        { 0x0000, 0x0000 }, /* R684 */
+        { 0x0000, 0x0000 }, /* R685 */
+        { 0x0000, 0x0000 }, /* R686 */
+        { 0x0000, 0x0000 }, /* R687 */
+        { 0x0000, 0x0000 }, /* R688 */
+        { 0x0000, 0x0000 }, /* R689 */
+        { 0x0000, 0x0000 }, /* R690 */
+        { 0x0000, 0x0000 }, /* R691 */
+        { 0x0000, 0x0000 }, /* R692 */
+        { 0x0000, 0x0000 }, /* R693 */
+        { 0x0000, 0x0000 }, /* R694 */
+        { 0x0000, 0x0000 }, /* R695 */
+        { 0x0000, 0x0000 }, /* R696 */
+        { 0x0000, 0x0000 }, /* R697 */
+        { 0x0000, 0x0000 }, /* R698 */
+        { 0x0000, 0x0000 }, /* R699 */
+        { 0x0000, 0x0000 }, /* R700 */
+        { 0x0000, 0x0000 }, /* R701 */
+        { 0x0000, 0x0000 }, /* R702 */
+        { 0x0000, 0x0000 }, /* R703 */
+        { 0x0000, 0x0000 }, /* R704 */
+        { 0x0000, 0x0000 }, /* R705 */
+        { 0x0000, 0x0000 }, /* R706 */
+        { 0x0000, 0x0000 }, /* R707 */
+        { 0x0000, 0x0000 }, /* R708 */
+        { 0x0000, 0x0000 }, /* R709 */
+        { 0x0000, 0x0000 }, /* R710 */
+        { 0x0000, 0x0000 }, /* R711 */
+        { 0x0000, 0x0000 }, /* R712 */
+        { 0x0000, 0x0000 }, /* R713 */
+        { 0x0000, 0x0000 }, /* R714 */
+        { 0x0000, 0x0000 }, /* R715 */
+        { 0x0000, 0x0000 }, /* R716 */
+        { 0x0000, 0x0000 }, /* R717 */
+        { 0x0000, 0x0000 }, /* R718 */
+        { 0x0000, 0x0000 }, /* R719 */
+        { 0x0000, 0x0000 }, /* R720 */
+        { 0x0000, 0x0000 }, /* R721 */
+        { 0x0000, 0x0000 }, /* R722 */
+        { 0x0000, 0x0000 }, /* R723 */
+        { 0x0000, 0x0000 }, /* R724 */
+        { 0x0000, 0x0000 }, /* R725 */
+        { 0x0000, 0x0000 }, /* R726 */
+        { 0x0000, 0x0000 }, /* R727 */
+        { 0x0000, 0x0000 }, /* R728 */
+        { 0x0000, 0x0000 }, /* R729 */
+        { 0x0000, 0x0000 }, /* R730 */
+        { 0x0000, 0x0000 }, /* R731 */
+        { 0x0000, 0x0000 }, /* R732 */
+        { 0x0000, 0x0000 }, /* R733 */
+        { 0x0000, 0x0000 }, /* R734 */
+        { 0x0000, 0x0000 }, /* R735 */
+        { 0x0000, 0x0000 }, /* R736 */
+        { 0x0000, 0x0000 }, /* R737 */
+        { 0x0000, 0x0000 }, /* R738 */
+        { 0x0000, 0x0000 }, /* R739 */
+        { 0x0000, 0x0000 }, /* R740 */
+        { 0x0000, 0x0000 }, /* R741 */
+        { 0x0000, 0x0000 }, /* R742 */
+        { 0x0000, 0x0000 }, /* R743 */
+        { 0x0000, 0x0000 }, /* R744 */
+        { 0x0000, 0x0000 }, /* R745 */
+        { 0x0000, 0x0000 }, /* R746 */
+        { 0x0000, 0x0000 }, /* R747 */
+        { 0x0000, 0x0000 }, /* R748 */
+        { 0x0000, 0x0000 }, /* R749 */
+        { 0x0000, 0x0000 }, /* R750 */
+        { 0x0000, 0x0000 }, /* R751 */
+        { 0x0000, 0x0000 }, /* R752 */
+        { 0x0000, 0x0000 }, /* R753 */
+        { 0x0000, 0x0000 }, /* R754 */
+        { 0x0000, 0x0000 }, /* R755 */
+        { 0x0000, 0x0000 }, /* R756 */
+        { 0x0000, 0x0000 }, /* R757 */
+        { 0x0000, 0x0000 }, /* R758 */
+        { 0x0000, 0x0000 }, /* R759 */
+        { 0x0000, 0x0000 }, /* R760 */
+        { 0x0000, 0x0000 }, /* R761 */
+        { 0x0000, 0x0000 }, /* R762 */
+        { 0x0000, 0x0000 }, /* R763 */
+        { 0x0000, 0x0000 }, /* R764 */
+        { 0x0000, 0x0000 }, /* R765 */
+        { 0x0000, 0x0000 }, /* R766 */
+        { 0x0000, 0x0000 }, /* R767 */
+        { 0xE1F8, 0xE1F8 }, /* R768   - AIF1 Control (1) */
+        { 0xCD1F, 0xCD1F }, /* R769   - AIF1 Control (2) */
+        { 0xF000, 0xF000 }, /* R770   - AIF1 Master/Slave */
+        { 0x01F0, 0x01F0 }, /* R771   - AIF1 BCLK */
+        { 0x0FFF, 0x0FFF }, /* R772   - AIF1ADC LRCLK */
+        { 0x0FFF, 0x0FFF }, /* R773   - AIF1DAC LRCLK */
+        { 0x0003, 0x0003 }, /* R774   - AIF1DAC Data */
+        { 0x0003, 0x0003 }, /* R775   - AIF1ADC Data */
+        { 0x0000, 0x0000 }, /* R776 */
+        { 0x0000, 0x0000 }, /* R777 */
+        { 0x0000, 0x0000 }, /* R778 */
+        { 0x0000, 0x0000 }, /* R779 */
+        { 0x0000, 0x0000 }, /* R780 */
+        { 0x0000, 0x0000 }, /* R781 */
+        { 0x0000, 0x0000 }, /* R782 */
+        { 0x0000, 0x0000 }, /* R783 */
+        { 0xF1F8, 0xF1F8 }, /* R784   - AIF2 Control (1) */
+        { 0xFD1F, 0xFD1F }, /* R785   - AIF2 Control (2) */
+        { 0xF000, 0xF000 }, /* R786   - AIF2 Master/Slave */
+        { 0x01F0, 0x01F0 }, /* R787   - AIF2 BCLK */
+        { 0x0FFF, 0x0FFF }, /* R788   - AIF2ADC LRCLK */
+        { 0x0FFF, 0x0FFF }, /* R789   - AIF2DAC LRCLK */
+        { 0x0003, 0x0003 }, /* R790   - AIF2DAC Data */
+        { 0x0003, 0x0003 }, /* R791   - AIF2ADC Data */
+        { 0x0000, 0x0000 }, /* R792 */
+        { 0x0000, 0x0000 }, /* R793 */
+        { 0x0000, 0x0000 }, /* R794 */
+        { 0x0000, 0x0000 }, /* R795 */
+        { 0x0000, 0x0000 }, /* R796 */
+        { 0x0000, 0x0000 }, /* R797 */
+        { 0x0000, 0x0000 }, /* R798 */
+        { 0x0000, 0x0000 }, /* R799 */
+        { 0x0000, 0x0000 }, /* R800 */
+        { 0x0000, 0x0000 }, /* R801 */
+        { 0x0000, 0x0000 }, /* R802 */
+        { 0x0000, 0x0000 }, /* R803 */
+        { 0x0000, 0x0000 }, /* R804 */
+        { 0x0000, 0x0000 }, /* R805 */
+        { 0x0000, 0x0000 }, /* R806 */
+        { 0x0000, 0x0000 }, /* R807 */
+        { 0x0000, 0x0000 }, /* R808 */
+        { 0x0000, 0x0000 }, /* R809 */
+        { 0x0000, 0x0000 }, /* R810 */
+        { 0x0000, 0x0000 }, /* R811 */
+        { 0x0000, 0x0000 }, /* R812 */
+        { 0x0000, 0x0000 }, /* R813 */
+        { 0x0000, 0x0000 }, /* R814 */
+        { 0x0000, 0x0000 }, /* R815 */
+        { 0x0000, 0x0000 }, /* R816 */
+        { 0x0000, 0x0000 }, /* R817 */
+        { 0x0000, 0x0000 }, /* R818 */
+        { 0x0000, 0x0000 }, /* R819 */
+        { 0x0000, 0x0000 }, /* R820 */
+        { 0x0000, 0x0000 }, /* R821 */
+        { 0x0000, 0x0000 }, /* R822 */
+        { 0x0000, 0x0000 }, /* R823 */
+        { 0x0000, 0x0000 }, /* R824 */
+        { 0x0000, 0x0000 }, /* R825 */
+        { 0x0000, 0x0000 }, /* R826 */
+        { 0x0000, 0x0000 }, /* R827 */
+        { 0x0000, 0x0000 }, /* R828 */
+        { 0x0000, 0x0000 }, /* R829 */
+        { 0x0000, 0x0000 }, /* R830 */
+        { 0x0000, 0x0000 }, /* R831 */
+        { 0x0000, 0x0000 }, /* R832 */
+        { 0x0000, 0x0000 }, /* R833 */
+        { 0x0000, 0x0000 }, /* R834 */
+        { 0x0000, 0x0000 }, /* R835 */
+        { 0x0000, 0x0000 }, /* R836 */
+        { 0x0000, 0x0000 }, /* R837 */
+        { 0x0000, 0x0000 }, /* R838 */
+        { 0x0000, 0x0000 }, /* R839 */
+        { 0x0000, 0x0000 }, /* R840 */
+        { 0x0000, 0x0000 }, /* R841 */
+        { 0x0000, 0x0000 }, /* R842 */
+        { 0x0000, 0x0000 }, /* R843 */
+        { 0x0000, 0x0000 }, /* R844 */
+        { 0x0000, 0x0000 }, /* R845 */
+        { 0x0000, 0x0000 }, /* R846 */
+        { 0x0000, 0x0000 }, /* R847 */
+        { 0x0000, 0x0000 }, /* R848 */
+        { 0x0000, 0x0000 }, /* R849 */
+        { 0x0000, 0x0000 }, /* R850 */
+        { 0x0000, 0x0000 }, /* R851 */
+        { 0x0000, 0x0000 }, /* R852 */
+        { 0x0000, 0x0000 }, /* R853 */
+        { 0x0000, 0x0000 }, /* R854 */
+        { 0x0000, 0x0000 }, /* R855 */
+        { 0x0000, 0x0000 }, /* R856 */
+        { 0x0000, 0x0000 }, /* R857 */
+        { 0x0000, 0x0000 }, /* R858 */
+        { 0x0000, 0x0000 }, /* R859 */
+        { 0x0000, 0x0000 }, /* R860 */
+        { 0x0000, 0x0000 }, /* R861 */
+        { 0x0000, 0x0000 }, /* R862 */
+        { 0x0000, 0x0000 }, /* R863 */
+        { 0x0000, 0x0000 }, /* R864 */
+        { 0x0000, 0x0000 }, /* R865 */
+        { 0x0000, 0x0000 }, /* R866 */
+        { 0x0000, 0x0000 }, /* R867 */
+        { 0x0000, 0x0000 }, /* R868 */
+        { 0x0000, 0x0000 }, /* R869 */
+        { 0x0000, 0x0000 }, /* R870 */
+        { 0x0000, 0x0000 }, /* R871 */
+        { 0x0000, 0x0000 }, /* R872 */
+        { 0x0000, 0x0000 }, /* R873 */
+        { 0x0000, 0x0000 }, /* R874 */
+        { 0x0000, 0x0000 }, /* R875 */
+        { 0x0000, 0x0000 }, /* R876 */
+        { 0x0000, 0x0000 }, /* R877 */
+        { 0x0000, 0x0000 }, /* R878 */
+        { 0x0000, 0x0000 }, /* R879 */
+        { 0x0000, 0x0000 }, /* R880 */
+        { 0x0000, 0x0000 }, /* R881 */
+        { 0x0000, 0x0000 }, /* R882 */
+        { 0x0000, 0x0000 }, /* R883 */
+        { 0x0000, 0x0000 }, /* R884 */
+        { 0x0000, 0x0000 }, /* R885 */
+        { 0x0000, 0x0000 }, /* R886 */
+        { 0x0000, 0x0000 }, /* R887 */
+        { 0x0000, 0x0000 }, /* R888 */
+        { 0x0000, 0x0000 }, /* R889 */
+        { 0x0000, 0x0000 }, /* R890 */
+        { 0x0000, 0x0000 }, /* R891 */
+        { 0x0000, 0x0000 }, /* R892 */
+        { 0x0000, 0x0000 }, /* R893 */
+        { 0x0000, 0x0000 }, /* R894 */
+        { 0x0000, 0x0000 }, /* R895 */
+        { 0x0000, 0x0000 }, /* R896 */
+        { 0x0000, 0x0000 }, /* R897 */
+        { 0x0000, 0x0000 }, /* R898 */
+        { 0x0000, 0x0000 }, /* R899 */
+        { 0x0000, 0x0000 }, /* R900 */
+        { 0x0000, 0x0000 }, /* R901 */
+        { 0x0000, 0x0000 }, /* R902 */
+        { 0x0000, 0x0000 }, /* R903 */
+        { 0x0000, 0x0000 }, /* R904 */
+        { 0x0000, 0x0000 }, /* R905 */
+        { 0x0000, 0x0000 }, /* R906 */
+        { 0x0000, 0x0000 }, /* R907 */
+        { 0x0000, 0x0000 }, /* R908 */
+        { 0x0000, 0x0000 }, /* R909 */
+        { 0x0000, 0x0000 }, /* R910 */
+        { 0x0000, 0x0000 }, /* R911 */
+        { 0x0000, 0x0000 }, /* R912 */
+        { 0x0000, 0x0000 }, /* R913 */
+        { 0x0000, 0x0000 }, /* R914 */
+        { 0x0000, 0x0000 }, /* R915 */
+        { 0x0000, 0x0000 }, /* R916 */
+        { 0x0000, 0x0000 }, /* R917 */
+        { 0x0000, 0x0000 }, /* R918 */
+        { 0x0000, 0x0000 }, /* R919 */
+        { 0x0000, 0x0000 }, /* R920 */
+        { 0x0000, 0x0000 }, /* R921 */
+        { 0x0000, 0x0000 }, /* R922 */
+        { 0x0000, 0x0000 }, /* R923 */
+        { 0x0000, 0x0000 }, /* R924 */
+        { 0x0000, 0x0000 }, /* R925 */
+        { 0x0000, 0x0000 }, /* R926 */
+        { 0x0000, 0x0000 }, /* R927 */
+        { 0x0000, 0x0000 }, /* R928 */
+        { 0x0000, 0x0000 }, /* R929 */
+        { 0x0000, 0x0000 }, /* R930 */
+        { 0x0000, 0x0000 }, /* R931 */
+        { 0x0000, 0x0000 }, /* R932 */
+        { 0x0000, 0x0000 }, /* R933 */
+        { 0x0000, 0x0000 }, /* R934 */
+        { 0x0000, 0x0000 }, /* R935 */
+        { 0x0000, 0x0000 }, /* R936 */
+        { 0x0000, 0x0000 }, /* R937 */
+        { 0x0000, 0x0000 }, /* R938 */
+        { 0x0000, 0x0000 }, /* R939 */
+        { 0x0000, 0x0000 }, /* R940 */
+        { 0x0000, 0x0000 }, /* R941 */
+        { 0x0000, 0x0000 }, /* R942 */
+        { 0x0000, 0x0000 }, /* R943 */
+        { 0x0000, 0x0000 }, /* R944 */
+        { 0x0000, 0x0000 }, /* R945 */
+        { 0x0000, 0x0000 }, /* R946 */
+        { 0x0000, 0x0000 }, /* R947 */
+        { 0x0000, 0x0000 }, /* R948 */
+        { 0x0000, 0x0000 }, /* R949 */
+        { 0x0000, 0x0000 }, /* R950 */
+        { 0x0000, 0x0000 }, /* R951 */
+        { 0x0000, 0x0000 }, /* R952 */
+        { 0x0000, 0x0000 }, /* R953 */
+        { 0x0000, 0x0000 }, /* R954 */
+        { 0x0000, 0x0000 }, /* R955 */
+        { 0x0000, 0x0000 }, /* R956 */
+        { 0x0000, 0x0000 }, /* R957 */
+        { 0x0000, 0x0000 }, /* R958 */
+        { 0x0000, 0x0000 }, /* R959 */
+        { 0x0000, 0x0000 }, /* R960 */
+        { 0x0000, 0x0000 }, /* R961 */
+        { 0x0000, 0x0000 }, /* R962 */
+        { 0x0000, 0x0000 }, /* R963 */
+        { 0x0000, 0x0000 }, /* R964 */
+        { 0x0000, 0x0000 }, /* R965 */
+        { 0x0000, 0x0000 }, /* R966 */
+        { 0x0000, 0x0000 }, /* R967 */
+        { 0x0000, 0x0000 }, /* R968 */
+        { 0x0000, 0x0000 }, /* R969 */
+        { 0x0000, 0x0000 }, /* R970 */
+        { 0x0000, 0x0000 }, /* R971 */
+        { 0x0000, 0x0000 }, /* R972 */
+        { 0x0000, 0x0000 }, /* R973 */
+        { 0x0000, 0x0000 }, /* R974 */
+        { 0x0000, 0x0000 }, /* R975 */
+        { 0x0000, 0x0000 }, /* R976 */
+        { 0x0000, 0x0000 }, /* R977 */
+        { 0x0000, 0x0000 }, /* R978 */
+        { 0x0000, 0x0000 }, /* R979 */
+        { 0x0000, 0x0000 }, /* R980 */
+        { 0x0000, 0x0000 }, /* R981 */
+        { 0x0000, 0x0000 }, /* R982 */
+        { 0x0000, 0x0000 }, /* R983 */
+        { 0x0000, 0x0000 }, /* R984 */
+        { 0x0000, 0x0000 }, /* R985 */
+        { 0x0000, 0x0000 }, /* R986 */
+        { 0x0000, 0x0000 }, /* R987 */
+        { 0x0000, 0x0000 }, /* R988 */
+        { 0x0000, 0x0000 }, /* R989 */
+        { 0x0000, 0x0000 }, /* R990 */
+        { 0x0000, 0x0000 }, /* R991 */
+        { 0x0000, 0x0000 }, /* R992 */
+        { 0x0000, 0x0000 }, /* R993 */
+        { 0x0000, 0x0000 }, /* R994 */
+        { 0x0000, 0x0000 }, /* R995 */
+        { 0x0000, 0x0000 }, /* R996 */
+        { 0x0000, 0x0000 }, /* R997 */
+        { 0x0000, 0x0000 }, /* R998 */
+        { 0x0000, 0x0000 }, /* R999 */
+        { 0x0000, 0x0000 }, /* R1000 */
+        { 0x0000, 0x0000 }, /* R1001 */
+        { 0x0000, 0x0000 }, /* R1002 */
+        { 0x0000, 0x0000 }, /* R1003 */
+        { 0x0000, 0x0000 }, /* R1004 */
+        { 0x0000, 0x0000 }, /* R1005 */
+        { 0x0000, 0x0000 }, /* R1006 */
+        { 0x0000, 0x0000 }, /* R1007 */
+        { 0x0000, 0x0000 }, /* R1008 */
+        { 0x0000, 0x0000 }, /* R1009 */
+        { 0x0000, 0x0000 }, /* R1010 */
+        { 0x0000, 0x0000 }, /* R1011 */
+        { 0x0000, 0x0000 }, /* R1012 */
+        { 0x0000, 0x0000 }, /* R1013 */
+        { 0x0000, 0x0000 }, /* R1014 */
+        { 0x0000, 0x0000 }, /* R1015 */
+        { 0x0000, 0x0000 }, /* R1016 */
+        { 0x0000, 0x0000 }, /* R1017 */
+        { 0x0000, 0x0000 }, /* R1018 */
+        { 0x0000, 0x0000 }, /* R1019 */
+        { 0x0000, 0x0000 }, /* R1020 */
+        { 0x0000, 0x0000 }, /* R1021 */
+        { 0x0000, 0x0000 }, /* R1022 */
+        { 0x0000, 0x0000 }, /* R1023 */
+        { 0x00FF, 0x01FF }, /* R1024  - AIF1 ADC1 Left Volume */
+        { 0x00FF, 0x01FF }, /* R1025  - AIF1 ADC1 Right Volume */
+        { 0x00FF, 0x01FF }, /* R1026  - AIF1 DAC1 Left Volume */
+        { 0x00FF, 0x01FF }, /* R1027  - AIF1 DAC1 Right Volume */
+        { 0x00FF, 0x01FF }, /* R1028  - AIF1 ADC2 Left Volume */
+        { 0x00FF, 0x01FF }, /* R1029  - AIF1 ADC2 Right Volume */
+        { 0x00FF, 0x01FF }, /* R1030  - AIF1 DAC2 Left Volume */
+        { 0x00FF, 0x01FF }, /* R1031  - AIF1 DAC2 Right Volume */
+        { 0x0000, 0x0000 }, /* R1032 */
+        { 0x0000, 0x0000 }, /* R1033 */
+        { 0x0000, 0x0000 }, /* R1034 */
+        { 0x0000, 0x0000 }, /* R1035 */
+        { 0x0000, 0x0000 }, /* R1036 */
+        { 0x0000, 0x0000 }, /* R1037 */
+        { 0x0000, 0x0000 }, /* R1038 */
+        { 0x0000, 0x0000 }, /* R1039 */
+        { 0xF800, 0xF800 }, /* R1040  - AIF1 ADC1 Filters */
+        { 0x7800, 0x7800 }, /* R1041  - AIF1 ADC2 Filters */
+        { 0x0000, 0x0000 }, /* R1042 */
+        { 0x0000, 0x0000 }, /* R1043 */
+        { 0x0000, 0x0000 }, /* R1044 */
+        { 0x0000, 0x0000 }, /* R1045 */
+        { 0x0000, 0x0000 }, /* R1046 */
+        { 0x0000, 0x0000 }, /* R1047 */
+        { 0x0000, 0x0000 }, /* R1048 */
+        { 0x0000, 0x0000 }, /* R1049 */
+        { 0x0000, 0x0000 }, /* R1050 */
+        { 0x0000, 0x0000 }, /* R1051 */
+        { 0x0000, 0x0000 }, /* R1052 */
+        { 0x0000, 0x0000 }, /* R1053 */
+        { 0x0000, 0x0000 }, /* R1054 */
+        { 0x0000, 0x0000 }, /* R1055 */
+        { 0x02B6, 0x02B6 }, /* R1056  - AIF1 DAC1 Filters (1) */
+        { 0x3F00, 0x3F00 }, /* R1057  - AIF1 DAC1 Filters (2) */
+        { 0x02B6, 0x02B6 }, /* R1058  - AIF1 DAC2 Filters (1) */
+        { 0x3F00, 0x3F00 }, /* R1059  - AIF1 DAC2 Filters (2) */
+        { 0x0000, 0x0000 }, /* R1060 */
+        { 0x0000, 0x0000 }, /* R1061 */
+        { 0x0000, 0x0000 }, /* R1062 */
+        { 0x0000, 0x0000 }, /* R1063 */
+        { 0x0000, 0x0000 }, /* R1064 */
+        { 0x0000, 0x0000 }, /* R1065 */
+        { 0x0000, 0x0000 }, /* R1066 */
+        { 0x0000, 0x0000 }, /* R1067 */
+        { 0x0000, 0x0000 }, /* R1068 */
+        { 0x0000, 0x0000 }, /* R1069 */
+        { 0x0000, 0x0000 }, /* R1070 */
+        { 0x0000, 0x0000 }, /* R1071 */
+        { 0x0000, 0x0000 }, /* R1072 */
+        { 0x0000, 0x0000 }, /* R1073 */
+        { 0x0000, 0x0000 }, /* R1074 */
+        { 0x0000, 0x0000 }, /* R1075 */
+        { 0x0000, 0x0000 }, /* R1076 */
+        { 0x0000, 0x0000 }, /* R1077 */
+        { 0x0000, 0x0000 }, /* R1078 */
+        { 0x0000, 0x0000 }, /* R1079 */
+        { 0x0000, 0x0000 }, /* R1080 */
+        { 0x0000, 0x0000 }, /* R1081 */
+        { 0x0000, 0x0000 }, /* R1082 */
+        { 0x0000, 0x0000 }, /* R1083 */
+        { 0x0000, 0x0000 }, /* R1084 */
+        { 0x0000, 0x0000 }, /* R1085 */
+        { 0x0000, 0x0000 }, /* R1086 */
+        { 0x0000, 0x0000 }, /* R1087 */
+        { 0xFFFF, 0xFFFF }, /* R1088  - AIF1 DRC1 (1) */
+        { 0x1FFF, 0x1FFF }, /* R1089  - AIF1 DRC1 (2) */
+        { 0xFFFF, 0xFFFF }, /* R1090  - AIF1 DRC1 (3) */
+        { 0x07FF, 0x07FF }, /* R1091  - AIF1 DRC1 (4) */
+        { 0x03FF, 0x03FF }, /* R1092  - AIF1 DRC1 (5) */
+        { 0x0000, 0x0000 }, /* R1093 */
+        { 0x0000, 0x0000 }, /* R1094 */
+        { 0x0000, 0x0000 }, /* R1095 */
+        { 0x0000, 0x0000 }, /* R1096 */
+        { 0x0000, 0x0000 }, /* R1097 */
+        { 0x0000, 0x0000 }, /* R1098 */
+        { 0x0000, 0x0000 }, /* R1099 */
+        { 0x0000, 0x0000 }, /* R1100 */
+        { 0x0000, 0x0000 }, /* R1101 */
+        { 0x0000, 0x0000 }, /* R1102 */
+        { 0x0000, 0x0000 }, /* R1103 */
+        { 0xFFFF, 0xFFFF }, /* R1104  - AIF1 DRC2 (1) */
+        { 0x1FFF, 0x1FFF }, /* R1105  - AIF1 DRC2 (2) */
+        { 0xFFFF, 0xFFFF }, /* R1106  - AIF1 DRC2 (3) */
+        { 0x07FF, 0x07FF }, /* R1107  - AIF1 DRC2 (4) */
+        { 0x03FF, 0x03FF }, /* R1108  - AIF1 DRC2 (5) */
+        { 0x0000, 0x0000 }, /* R1109 */
+        { 0x0000, 0x0000 }, /* R1110 */
+        { 0x0000, 0x0000 }, /* R1111 */
+        { 0x0000, 0x0000 }, /* R1112 */
+        { 0x0000, 0x0000 }, /* R1113 */
+        { 0x0000, 0x0000 }, /* R1114 */
+        { 0x0000, 0x0000 }, /* R1115 */
+        { 0x0000, 0x0000 }, /* R1116 */
+        { 0x0000, 0x0000 }, /* R1117 */
+        { 0x0000, 0x0000 }, /* R1118 */
+        { 0x0000, 0x0000 }, /* R1119 */
+        { 0x0000, 0x0000 }, /* R1120 */
+        { 0x0000, 0x0000 }, /* R1121 */
+        { 0x0000, 0x0000 }, /* R1122 */
+        { 0x0000, 0x0000 }, /* R1123 */
+        { 0x0000, 0x0000 }, /* R1124 */
+        { 0x0000, 0x0000 }, /* R1125 */
+        { 0x0000, 0x0000 }, /* R1126 */
+        { 0x0000, 0x0000 }, /* R1127 */
+        { 0x0000, 0x0000 }, /* R1128 */
+        { 0x0000, 0x0000 }, /* R1129 */
+        { 0x0000, 0x0000 }, /* R1130 */
+        { 0x0000, 0x0000 }, /* R1131 */
+        { 0x0000, 0x0000 }, /* R1132 */
+        { 0x0000, 0x0000 }, /* R1133 */
+        { 0x0000, 0x0000 }, /* R1134 */
+        { 0x0000, 0x0000 }, /* R1135 */
+        { 0x0000, 0x0000 }, /* R1136 */
+        { 0x0000, 0x0000 }, /* R1137 */
+        { 0x0000, 0x0000 }, /* R1138 */
+        { 0x0000, 0x0000 }, /* R1139 */
+        { 0x0000, 0x0000 }, /* R1140 */
+        { 0x0000, 0x0000 }, /* R1141 */
+        { 0x0000, 0x0000 }, /* R1142 */
+        { 0x0000, 0x0000 }, /* R1143 */
+        { 0x0000, 0x0000 }, /* R1144 */
+        { 0x0000, 0x0000 }, /* R1145 */
+        { 0x0000, 0x0000 }, /* R1146 */
+        { 0x0000, 0x0000 }, /* R1147 */
+        { 0x0000, 0x0000 }, /* R1148 */
+        { 0x0000, 0x0000 }, /* R1149 */
+        { 0x0000, 0x0000 }, /* R1150 */
+        { 0x0000, 0x0000 }, /* R1151 */
+        { 0xFFFF, 0xFFFF }, /* R1152  - AIF1 DAC1 EQ Gains (1) */
+        { 0xFFC0, 0xFFC0 }, /* R1153  - AIF1 DAC1 EQ Gains (2) */
+        { 0xFFFF, 0xFFFF }, /* R1154  - AIF1 DAC1 EQ Band 1 A */
+        { 0xFFFF, 0xFFFF }, /* R1155  - AIF1 DAC1 EQ Band 1 B */
+        { 0xFFFF, 0xFFFF }, /* R1156  - AIF1 DAC1 EQ Band 1 PG */
+        { 0xFFFF, 0xFFFF }, /* R1157  - AIF1 DAC1 EQ Band 2 A */
+        { 0xFFFF, 0xFFFF }, /* R1158  - AIF1 DAC1 EQ Band 2 B */
+        { 0xFFFF, 0xFFFF }, /* R1159  - AIF1 DAC1 EQ Band 2 C */
+        { 0xFFFF, 0xFFFF }, /* R1160  - AIF1 DAC1 EQ Band 2 PG */
+        { 0xFFFF, 0xFFFF }, /* R1161  - AIF1 DAC1 EQ Band 3 A */
+        { 0xFFFF, 0xFFFF }, /* R1162  - AIF1 DAC1 EQ Band 3 B */
+        { 0xFFFF, 0xFFFF }, /* R1163  - AIF1 DAC1 EQ Band 3 C */
+        { 0xFFFF, 0xFFFF }, /* R1164  - AIF1 DAC1 EQ Band 3 PG */
+        { 0xFFFF, 0xFFFF }, /* R1165  - AIF1 DAC1 EQ Band 4 A */
+        { 0xFFFF, 0xFFFF }, /* R1166  - AIF1 DAC1 EQ Band 4 B */
+        { 0xFFFF, 0xFFFF }, /* R1167  - AIF1 DAC1 EQ Band 4 C */
+        { 0xFFFF, 0xFFFF }, /* R1168  - AIF1 DAC1 EQ Band 4 PG */
+        { 0xFFFF, 0xFFFF }, /* R1169  - AIF1 DAC1 EQ Band 5 A */
+        { 0xFFFF, 0xFFFF }, /* R1170  - AIF1 DAC1 EQ Band 5 B */
+        { 0xFFFF, 0xFFFF }, /* R1171  - AIF1 DAC1 EQ Band 5 PG */
+        { 0x0000, 0x0000 }, /* R1172 */
+        { 0x0000, 0x0000 }, /* R1173 */
+        { 0x0000, 0x0000 }, /* R1174 */
+        { 0x0000, 0x0000 }, /* R1175 */
+        { 0x0000, 0x0000 }, /* R1176 */
+        { 0x0000, 0x0000 }, /* R1177 */
+        { 0x0000, 0x0000 }, /* R1178 */
+        { 0x0000, 0x0000 }, /* R1179 */
+        { 0x0000, 0x0000 }, /* R1180 */
+        { 0x0000, 0x0000 }, /* R1181 */
+        { 0x0000, 0x0000 }, /* R1182 */
+        { 0x0000, 0x0000 }, /* R1183 */
+        { 0xFFFF, 0xFFFF }, /* R1184  - AIF1 DAC2 EQ Gains (1) */
+        { 0xFFC0, 0xFFC0 }, /* R1185  - AIF1 DAC2 EQ Gains (2) */
+        { 0xFFFF, 0xFFFF }, /* R1186  - AIF1 DAC2 EQ Band 1 A */
+        { 0xFFFF, 0xFFFF }, /* R1187  - AIF1 DAC2 EQ Band 1 B */
+        { 0xFFFF, 0xFFFF }, /* R1188  - AIF1 DAC2 EQ Band 1 PG */
+        { 0xFFFF, 0xFFFF }, /* R1189  - AIF1 DAC2 EQ Band 2 A */
+        { 0xFFFF, 0xFFFF }, /* R1190  - AIF1 DAC2 EQ Band 2 B */
+        { 0xFFFF, 0xFFFF }, /* R1191  - AIF1 DAC2 EQ Band 2 C */
+        { 0xFFFF, 0xFFFF }, /* R1192  - AIF1 DAC2 EQ Band 2 PG */
+        { 0xFFFF, 0xFFFF }, /* R1193  - AIF1 DAC2 EQ Band 3 A */
+        { 0xFFFF, 0xFFFF }, /* R1194  - AIF1 DAC2 EQ Band 3 B */
+        { 0xFFFF, 0xFFFF }, /* R1195  - AIF1 DAC2 EQ Band 3 C */
+        { 0xFFFF, 0xFFFF }, /* R1196  - AIF1 DAC2 EQ Band 3 PG */
+        { 0xFFFF, 0xFFFF }, /* R1197  - AIF1 DAC2 EQ Band 4 A */
+        { 0xFFFF, 0xFFFF }, /* R1198  - AIF1 DAC2 EQ Band 4 B */
+        { 0xFFFF, 0xFFFF }, /* R1199  - AIF1 DAC2 EQ Band 4 C */
+        { 0xFFFF, 0xFFFF }, /* R1200  - AIF1 DAC2 EQ Band 4 PG */
+        { 0xFFFF, 0xFFFF }, /* R1201  - AIF1 DAC2 EQ Band 5 A */
+        { 0xFFFF, 0xFFFF }, /* R1202  - AIF1 DAC2 EQ Band 5 B */
+        { 0xFFFF, 0xFFFF }, /* R1203  - AIF1 DAC2 EQ Band 5 PG */
+        { 0x0000, 0x0000 }, /* R1204 */
+        { 0x0000, 0x0000 }, /* R1205 */
+        { 0x0000, 0x0000 }, /* R1206 */
+        { 0x0000, 0x0000 }, /* R1207 */
+        { 0x0000, 0x0000 }, /* R1208 */
+        { 0x0000, 0x0000 }, /* R1209 */
+        { 0x0000, 0x0000 }, /* R1210 */
+        { 0x0000, 0x0000 }, /* R1211 */
+        { 0x0000, 0x0000 }, /* R1212 */
+        { 0x0000, 0x0000 }, /* R1213 */
+        { 0x0000, 0x0000 }, /* R1214 */
+        { 0x0000, 0x0000 }, /* R1215 */
+        { 0x0000, 0x0000 }, /* R1216 */
+        { 0x0000, 0x0000 }, /* R1217 */
+        { 0x0000, 0x0000 }, /* R1218 */
+        { 0x0000, 0x0000 }, /* R1219 */
+        { 0x0000, 0x0000 }, /* R1220 */
+        { 0x0000, 0x0000 }, /* R1221 */
+        { 0x0000, 0x0000 }, /* R1222 */
+        { 0x0000, 0x0000 }, /* R1223 */
+        { 0x0000, 0x0000 }, /* R1224 */
+        { 0x0000, 0x0000 }, /* R1225 */
+        { 0x0000, 0x0000 }, /* R1226 */
+        { 0x0000, 0x0000 }, /* R1227 */
+        { 0x0000, 0x0000 }, /* R1228 */
+        { 0x0000, 0x0000 }, /* R1229 */
+        { 0x0000, 0x0000 }, /* R1230 */
+        { 0x0000, 0x0000 }, /* R1231 */
+        { 0x0000, 0x0000 }, /* R1232 */
+        { 0x0000, 0x0000 }, /* R1233 */
+        { 0x0000, 0x0000 }, /* R1234 */
+        { 0x0000, 0x0000 }, /* R1235 */
+        { 0x0000, 0x0000 }, /* R1236 */
+        { 0x0000, 0x0000 }, /* R1237 */
+        { 0x0000, 0x0000 }, /* R1238 */
+        { 0x0000, 0x0000 }, /* R1239 */
+        { 0x0000, 0x0000 }, /* R1240 */
+        { 0x0000, 0x0000 }, /* R1241 */
+        { 0x0000, 0x0000 }, /* R1242 */
+        { 0x0000, 0x0000 }, /* R1243 */
+        { 0x0000, 0x0000 }, /* R1244 */
+        { 0x0000, 0x0000 }, /* R1245 */
+        { 0x0000, 0x0000 }, /* R1246 */
+        { 0x0000, 0x0000 }, /* R1247 */
+        { 0x0000, 0x0000 }, /* R1248 */
+        { 0x0000, 0x0000 }, /* R1249 */
+        { 0x0000, 0x0000 }, /* R1250 */
+        { 0x0000, 0x0000 }, /* R1251 */
+        { 0x0000, 0x0000 }, /* R1252 */
+        { 0x0000, 0x0000 }, /* R1253 */
+        { 0x0000, 0x0000 }, /* R1254 */
+        { 0x0000, 0x0000 }, /* R1255 */
+        { 0x0000, 0x0000 }, /* R1256 */
+        { 0x0000, 0x0000 }, /* R1257 */
+        { 0x0000, 0x0000 }, /* R1258 */
+        { 0x0000, 0x0000 }, /* R1259 */
+        { 0x0000, 0x0000 }, /* R1260 */
+        { 0x0000, 0x0000 }, /* R1261 */
+        { 0x0000, 0x0000 }, /* R1262 */
+        { 0x0000, 0x0000 }, /* R1263 */
+        { 0x0000, 0x0000 }, /* R1264 */
+        { 0x0000, 0x0000 }, /* R1265 */
+        { 0x0000, 0x0000 }, /* R1266 */
+        { 0x0000, 0x0000 }, /* R1267 */
+        { 0x0000, 0x0000 }, /* R1268 */
+        { 0x0000, 0x0000 }, /* R1269 */
+        { 0x0000, 0x0000 }, /* R1270 */
+        { 0x0000, 0x0000 }, /* R1271 */
+        { 0x0000, 0x0000 }, /* R1272 */
+        { 0x0000, 0x0000 }, /* R1273 */
+        { 0x0000, 0x0000 }, /* R1274 */
+        { 0x0000, 0x0000 }, /* R1275 */
+        { 0x0000, 0x0000 }, /* R1276 */
+        { 0x0000, 0x0000 }, /* R1277 */
+        { 0x0000, 0x0000 }, /* R1278 */
+        { 0x0000, 0x0000 }, /* R1279 */
+        { 0x00FF, 0x01FF }, /* R1280  - AIF2 ADC Left Volume */
+        { 0x00FF, 0x01FF }, /* R1281  - AIF2 ADC Right Volume */
+        { 0x00FF, 0x01FF }, /* R1282  - AIF2 DAC Left Volume */
+        { 0x00FF, 0x01FF }, /* R1283  - AIF2 DAC Right Volume */
+        { 0x0000, 0x0000 }, /* R1284 */
+        { 0x0000, 0x0000 }, /* R1285 */
+        { 0x0000, 0x0000 }, /* R1286 */
+        { 0x0000, 0x0000 }, /* R1287 */
+        { 0x0000, 0x0000 }, /* R1288 */
+        { 0x0000, 0x0000 }, /* R1289 */
+        { 0x0000, 0x0000 }, /* R1290 */
+        { 0x0000, 0x0000 }, /* R1291 */
+        { 0x0000, 0x0000 }, /* R1292 */
+        { 0x0000, 0x0000 }, /* R1293 */
+        { 0x0000, 0x0000 }, /* R1294 */
+        { 0x0000, 0x0000 }, /* R1295 */
+        { 0xF800, 0xF800 }, /* R1296  - AIF2 ADC Filters */
+        { 0x0000, 0x0000 }, /* R1297 */
+        { 0x0000, 0x0000 }, /* R1298 */
+        { 0x0000, 0x0000 }, /* R1299 */
+        { 0x0000, 0x0000 }, /* R1300 */
+        { 0x0000, 0x0000 }, /* R1301 */
+        { 0x0000, 0x0000 }, /* R1302 */
+        { 0x0000, 0x0000 }, /* R1303 */
+        { 0x0000, 0x0000 }, /* R1304 */
+        { 0x0000, 0x0000 }, /* R1305 */
+        { 0x0000, 0x0000 }, /* R1306 */
+        { 0x0000, 0x0000 }, /* R1307 */
+        { 0x0000, 0x0000 }, /* R1308 */
+        { 0x0000, 0x0000 }, /* R1309 */
+        { 0x0000, 0x0000 }, /* R1310 */
+        { 0x0000, 0x0000 }, /* R1311 */
+        { 0x02B6, 0x02B6 }, /* R1312  - AIF2 DAC Filters (1) */
+        { 0x3F00, 0x3F00 }, /* R1313  - AIF2 DAC Filters (2) */
+        { 0x0000, 0x0000 }, /* R1314 */
+        { 0x0000, 0x0000 }, /* R1315 */
+        { 0x0000, 0x0000 }, /* R1316 */
+        { 0x0000, 0x0000 }, /* R1317 */
+        { 0x0000, 0x0000 }, /* R1318 */
+        { 0x0000, 0x0000 }, /* R1319 */
+        { 0x0000, 0x0000 }, /* R1320 */
+        { 0x0000, 0x0000 }, /* R1321 */
+        { 0x0000, 0x0000 }, /* R1322 */
+        { 0x0000, 0x0000 }, /* R1323 */
+        { 0x0000, 0x0000 }, /* R1324 */
+        { 0x0000, 0x0000 }, /* R1325 */
+        { 0x0000, 0x0000 }, /* R1326 */
+        { 0x0000, 0x0000 }, /* R1327 */
+        { 0x0000, 0x0000 }, /* R1328 */
+        { 0x0000, 0x0000 }, /* R1329 */
+        { 0x0000, 0x0000 }, /* R1330 */
+        { 0x0000, 0x0000 }, /* R1331 */
+        { 0x0000, 0x0000 }, /* R1332 */
+        { 0x0000, 0x0000 }, /* R1333 */
+        { 0x0000, 0x0000 }, /* R1334 */
+        { 0x0000, 0x0000 }, /* R1335 */
+        { 0x0000, 0x0000 }, /* R1336 */
+        { 0x0000, 0x0000 }, /* R1337 */
+        { 0x0000, 0x0000 }, /* R1338 */
+        { 0x0000, 0x0000 }, /* R1339 */
+        { 0x0000, 0x0000 }, /* R1340 */
+        { 0x0000, 0x0000 }, /* R1341 */
+        { 0x0000, 0x0000 }, /* R1342 */
+        { 0x0000, 0x0000 }, /* R1343 */
+        { 0xFFFF, 0xFFFF }, /* R1344  - AIF2 DRC (1) */
+        { 0x1FFF, 0x1FFF }, /* R1345  - AIF2 DRC (2) */
+        { 0xFFFF, 0xFFFF }, /* R1346  - AIF2 DRC (3) */
+        { 0x07FF, 0x07FF }, /* R1347  - AIF2 DRC (4) */
+        { 0x03FF, 0x03FF }, /* R1348  - AIF2 DRC (5) */
+        { 0x0000, 0x0000 }, /* R1349 */
+        { 0x0000, 0x0000 }, /* R1350 */
+        { 0x0000, 0x0000 }, /* R1351 */
+        { 0x0000, 0x0000 }, /* R1352 */
+        { 0x0000, 0x0000 }, /* R1353 */
+        { 0x0000, 0x0000 }, /* R1354 */
+        { 0x0000, 0x0000 }, /* R1355 */
+        { 0x0000, 0x0000 }, /* R1356 */
+        { 0x0000, 0x0000 }, /* R1357 */
+        { 0x0000, 0x0000 }, /* R1358 */
+        { 0x0000, 0x0000 }, /* R1359 */
+        { 0x0000, 0x0000 }, /* R1360 */
+        { 0x0000, 0x0000 }, /* R1361 */
+        { 0x0000, 0x0000 }, /* R1362 */
+        { 0x0000, 0x0000 }, /* R1363 */
+        { 0x0000, 0x0000 }, /* R1364 */
+        { 0x0000, 0x0000 }, /* R1365 */
+        { 0x0000, 0x0000 }, /* R1366 */
+        { 0x0000, 0x0000 }, /* R1367 */
+        { 0x0000, 0x0000 }, /* R1368 */
+        { 0x0000, 0x0000 }, /* R1369 */
+        { 0x0000, 0x0000 }, /* R1370 */
+        { 0x0000, 0x0000 }, /* R1371 */
+        { 0x0000, 0x0000 }, /* R1372 */
+        { 0x0000, 0x0000 }, /* R1373 */
+        { 0x0000, 0x0000 }, /* R1374 */
+        { 0x0000, 0x0000 }, /* R1375 */
+        { 0x0000, 0x0000 }, /* R1376 */
+        { 0x0000, 0x0000 }, /* R1377 */
+        { 0x0000, 0x0000 }, /* R1378 */
+        { 0x0000, 0x0000 }, /* R1379 */
+        { 0x0000, 0x0000 }, /* R1380 */
+        { 0x0000, 0x0000 }, /* R1381 */
+        { 0x0000, 0x0000 }, /* R1382 */
+        { 0x0000, 0x0000 }, /* R1383 */
+        { 0x0000, 0x0000 }, /* R1384 */
+        { 0x0000, 0x0000 }, /* R1385 */
+        { 0x0000, 0x0000 }, /* R1386 */
+        { 0x0000, 0x0000 }, /* R1387 */
+        { 0x0000, 0x0000 }, /* R1388 */
+        { 0x0000, 0x0000 }, /* R1389 */
+        { 0x0000, 0x0000 }, /* R1390 */
+        { 0x0000, 0x0000 }, /* R1391 */
+        { 0x0000, 0x0000 }, /* R1392 */
+        { 0x0000, 0x0000 }, /* R1393 */
+        { 0x0000, 0x0000 }, /* R1394 */
+        { 0x0000, 0x0000 }, /* R1395 */
+        { 0x0000, 0x0000 }, /* R1396 */
+        { 0x0000, 0x0000 }, /* R1397 */
+        { 0x0000, 0x0000 }, /* R1398 */
+        { 0x0000, 0x0000 }, /* R1399 */
+        { 0x0000, 0x0000 }, /* R1400 */
+        { 0x0000, 0x0000 }, /* R1401 */
+        { 0x0000, 0x0000 }, /* R1402 */
+        { 0x0000, 0x0000 }, /* R1403 */
+        { 0x0000, 0x0000 }, /* R1404 */
+        { 0x0000, 0x0000 }, /* R1405 */
+        { 0x0000, 0x0000 }, /* R1406 */
+        { 0x0000, 0x0000 }, /* R1407 */
+        { 0xFFFF, 0xFFFF }, /* R1408  - AIF2 EQ Gains (1) */
+        { 0xFFC0, 0xFFC0 }, /* R1409  - AIF2 EQ Gains (2) */
+        { 0xFFFF, 0xFFFF }, /* R1410  - AIF2 EQ Band 1 A */
+        { 0xFFFF, 0xFFFF }, /* R1411  - AIF2 EQ Band 1 B */
+        { 0xFFFF, 0xFFFF }, /* R1412  - AIF2 EQ Band 1 PG */
+        { 0xFFFF, 0xFFFF }, /* R1413  - AIF2 EQ Band 2 A */
+        { 0xFFFF, 0xFFFF }, /* R1414  - AIF2 EQ Band 2 B */
+        { 0xFFFF, 0xFFFF }, /* R1415  - AIF2 EQ Band 2 C */
+        { 0xFFFF, 0xFFFF }, /* R1416  - AIF2 EQ Band 2 PG */
+        { 0xFFFF, 0xFFFF }, /* R1417  - AIF2 EQ Band 3 A */
+        { 0xFFFF, 0xFFFF }, /* R1418  - AIF2 EQ Band 3 B */
+        { 0xFFFF, 0xFFFF }, /* R1419  - AIF2 EQ Band 3 C */
+        { 0xFFFF, 0xFFFF }, /* R1420  - AIF2 EQ Band 3 PG */
+        { 0xFFFF, 0xFFFF }, /* R1421  - AIF2 EQ Band 4 A */
+        { 0xFFFF, 0xFFFF }, /* R1422  - AIF2 EQ Band 4 B */
+        { 0xFFFF, 0xFFFF }, /* R1423  - AIF2 EQ Band 4 C */
+        { 0xFFFF, 0xFFFF }, /* R1424  - AIF2 EQ Band 4 PG */
+        { 0xFFFF, 0xFFFF }, /* R1425  - AIF2 EQ Band 5 A */
+        { 0xFFFF, 0xFFFF }, /* R1426  - AIF2 EQ Band 5 B */
+        { 0xFFFF, 0xFFFF }, /* R1427  - AIF2 EQ Band 5 PG */
+        { 0x0000, 0x0000 }, /* R1428 */
+        { 0x0000, 0x0000 }, /* R1429 */
+        { 0x0000, 0x0000 }, /* R1430 */
+        { 0x0000, 0x0000 }, /* R1431 */
+        { 0x0000, 0x0000 }, /* R1432 */
+        { 0x0000, 0x0000 }, /* R1433 */
+        { 0x0000, 0x0000 }, /* R1434 */
+        { 0x0000, 0x0000 }, /* R1435 */
+        { 0x0000, 0x0000 }, /* R1436 */
+        { 0x0000, 0x0000 }, /* R1437 */
+        { 0x0000, 0x0000 }, /* R1438 */
+        { 0x0000, 0x0000 }, /* R1439 */
+        { 0x0000, 0x0000 }, /* R1440 */
+        { 0x0000, 0x0000 }, /* R1441 */
+        { 0x0000, 0x0000 }, /* R1442 */
+        { 0x0000, 0x0000 }, /* R1443 */
+        { 0x0000, 0x0000 }, /* R1444 */
+        { 0x0000, 0x0000 }, /* R1445 */
+        { 0x0000, 0x0000 }, /* R1446 */
+        { 0x0000, 0x0000 }, /* R1447 */
+        { 0x0000, 0x0000 }, /* R1448 */
+        { 0x0000, 0x0000 }, /* R1449 */
+        { 0x0000, 0x0000 }, /* R1450 */
+        { 0x0000, 0x0000 }, /* R1451 */
+        { 0x0000, 0x0000 }, /* R1452 */
+        { 0x0000, 0x0000 }, /* R1453 */
+        { 0x0000, 0x0000 }, /* R1454 */
+        { 0x0000, 0x0000 }, /* R1455 */
+        { 0x0000, 0x0000 }, /* R1456 */
+        { 0x0000, 0x0000 }, /* R1457 */
+        { 0x0000, 0x0000 }, /* R1458 */
+        { 0x0000, 0x0000 }, /* R1459 */
+        { 0x0000, 0x0000 }, /* R1460 */
+        { 0x0000, 0x0000 }, /* R1461 */
+        { 0x0000, 0x0000 }, /* R1462 */
+        { 0x0000, 0x0000 }, /* R1463 */
+        { 0x0000, 0x0000 }, /* R1464 */
+        { 0x0000, 0x0000 }, /* R1465 */
+        { 0x0000, 0x0000 }, /* R1466 */
+        { 0x0000, 0x0000 }, /* R1467 */
+        { 0x0000, 0x0000 }, /* R1468 */
+        { 0x0000, 0x0000 }, /* R1469 */
+        { 0x0000, 0x0000 }, /* R1470 */
+        { 0x0000, 0x0000 }, /* R1471 */
+        { 0x0000, 0x0000 }, /* R1472 */
+        { 0x0000, 0x0000 }, /* R1473 */
+        { 0x0000, 0x0000 }, /* R1474 */
+        { 0x0000, 0x0000 }, /* R1475 */
+        { 0x0000, 0x0000 }, /* R1476 */
+        { 0x0000, 0x0000 }, /* R1477 */
+        { 0x0000, 0x0000 }, /* R1478 */
+        { 0x0000, 0x0000 }, /* R1479 */
+        { 0x0000, 0x0000 }, /* R1480 */
+        { 0x0000, 0x0000 }, /* R1481 */
+        { 0x0000, 0x0000 }, /* R1482 */
+        { 0x0000, 0x0000 }, /* R1483 */
+        { 0x0000, 0x0000 }, /* R1484 */
+        { 0x0000, 0x0000 }, /* R1485 */
+        { 0x0000, 0x0000 }, /* R1486 */
+        { 0x0000, 0x0000 }, /* R1487 */
+        { 0x0000, 0x0000 }, /* R1488 */
+        { 0x0000, 0x0000 }, /* R1489 */
+        { 0x0000, 0x0000 }, /* R1490 */
+        { 0x0000, 0x0000 }, /* R1491 */
+        { 0x0000, 0x0000 }, /* R1492 */
+        { 0x0000, 0x0000 }, /* R1493 */
+        { 0x0000, 0x0000 }, /* R1494 */
+        { 0x0000, 0x0000 }, /* R1495 */
+        { 0x0000, 0x0000 }, /* R1496 */
+        { 0x0000, 0x0000 }, /* R1497 */
+        { 0x0000, 0x0000 }, /* R1498 */
+        { 0x0000, 0x0000 }, /* R1499 */
+        { 0x0000, 0x0000 }, /* R1500 */
+        { 0x0000, 0x0000 }, /* R1501 */
+        { 0x0000, 0x0000 }, /* R1502 */
+        { 0x0000, 0x0000 }, /* R1503 */
+        { 0x0000, 0x0000 }, /* R1504 */
+        { 0x0000, 0x0000 }, /* R1505 */
+        { 0x0000, 0x0000 }, /* R1506 */
+        { 0x0000, 0x0000 }, /* R1507 */
+        { 0x0000, 0x0000 }, /* R1508 */
+        { 0x0000, 0x0000 }, /* R1509 */
+        { 0x0000, 0x0000 }, /* R1510 */
+        { 0x0000, 0x0000 }, /* R1511 */
+        { 0x0000, 0x0000 }, /* R1512 */
+        { 0x0000, 0x0000 }, /* R1513 */
+        { 0x0000, 0x0000 }, /* R1514 */
+        { 0x0000, 0x0000 }, /* R1515 */
+        { 0x0000, 0x0000 }, /* R1516 */
+        { 0x0000, 0x0000 }, /* R1517 */
+        { 0x0000, 0x0000 }, /* R1518 */
+        { 0x0000, 0x0000 }, /* R1519 */
+        { 0x0000, 0x0000 }, /* R1520 */
+        { 0x0000, 0x0000 }, /* R1521 */
+        { 0x0000, 0x0000 }, /* R1522 */
+        { 0x0000, 0x0000 }, /* R1523 */
+        { 0x0000, 0x0000 }, /* R1524 */
+        { 0x0000, 0x0000 }, /* R1525 */
+        { 0x0000, 0x0000 }, /* R1526 */
+        { 0x0000, 0x0000 }, /* R1527 */
+        { 0x0000, 0x0000 }, /* R1528 */
+        { 0x0000, 0x0000 }, /* R1529 */
+        { 0x0000, 0x0000 }, /* R1530 */
+        { 0x0000, 0x0000 }, /* R1531 */
+        { 0x0000, 0x0000 }, /* R1532 */
+        { 0x0000, 0x0000 }, /* R1533 */
+        { 0x0000, 0x0000 }, /* R1534 */
+        { 0x0000, 0x0000 }, /* R1535 */
+        { 0x01EF, 0x01EF }, /* R1536  - DAC1 Mixer Volumes */
+        { 0x0037, 0x0037 }, /* R1537  - DAC1 Left Mixer Routing */
+        { 0x0037, 0x0037 }, /* R1538  - DAC1 Right Mixer Routing */
+        { 0x01EF, 0x01EF }, /* R1539  - DAC2 Mixer Volumes */
+        { 0x0037, 0x0037 }, /* R1540  - DAC2 Left Mixer Routing */
+        { 0x0037, 0x0037 }, /* R1541  - DAC2 Right Mixer Routing */
+        { 0x0003, 0x0003 }, /* R1542  - AIF1 ADC1 Left Mixer Routing */
+        { 0x0003, 0x0003 }, /* R1543  - AIF1 ADC1 Right Mixer Routing */
+        { 0x0003, 0x0003 }, /* R1544  - AIF1 ADC2 Left Mixer Routing */
+        { 0x0003, 0x0003 }, /* R1545  - AIF1 ADC2 Right mixer Routing */
+        { 0x0000, 0x0000 }, /* R1546 */
+        { 0x0000, 0x0000 }, /* R1547 */
+        { 0x0000, 0x0000 }, /* R1548 */
+        { 0x0000, 0x0000 }, /* R1549 */
+        { 0x0000, 0x0000 }, /* R1550 */
+        { 0x0000, 0x0000 }, /* R1551 */
+        { 0x02FF, 0x03FF }, /* R1552  - DAC1 Left Volume */
+        { 0x02FF, 0x03FF }, /* R1553  - DAC1 Right Volume */
+        { 0x02FF, 0x03FF }, /* R1554  - DAC2 Left Volume */
+        { 0x02FF, 0x03FF }, /* R1555  - DAC2 Right Volume */
+        { 0x0003, 0x0003 }, /* R1556  - DAC Softmute */
+        { 0x0000, 0x0000 }, /* R1557 */
+        { 0x0000, 0x0000 }, /* R1558 */
+        { 0x0000, 0x0000 }, /* R1559 */
+        { 0x0000, 0x0000 }, /* R1560 */
+        { 0x0000, 0x0000 }, /* R1561 */
+        { 0x0000, 0x0000 }, /* R1562 */
+        { 0x0000, 0x0000 }, /* R1563 */
+        { 0x0000, 0x0000 }, /* R1564 */
+        { 0x0000, 0x0000 }, /* R1565 */
+        { 0x0000, 0x0000 }, /* R1566 */
+        { 0x0000, 0x0000 }, /* R1567 */
+        { 0x0003, 0x0003 }, /* R1568  - Oversampling */
+        { 0x03C3, 0x03C3 }, /* R1569  - Sidetone */
+};
+
+const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = {
+        0x8994,     /* R0     - Software Reset */
+        0x0000,     /* R1     - Power Management (1) */
+        0x6000,     /* R2     - Power Management (2) */
+        0x0000,     /* R3     - Power Management (3) */
+        0x0000,     /* R4     - Power Management (4) */
+        0x0000,     /* R5     - Power Management (5) */
+        0x0000,     /* R6     - Power Management (6) */
+        0x0000,     /* R7 */
+        0x0000,     /* R8 */
+        0x0000,     /* R9 */
+        0x0000,     /* R10 */
+        0x0000,     /* R11 */
+        0x0000,     /* R12 */
+        0x0000,     /* R13 */
+        0x0000,     /* R14 */
+        0x0000,     /* R15 */
+        0x0000,     /* R16 */
+        0x0000,     /* R17 */
+        0x0000,     /* R18 */
+        0x0000,     /* R19 */
+        0x0000,     /* R20 */
+        0x0000,     /* R21    - Input Mixer (1) */
+        0x0000,     /* R22 */
+        0x0000,     /* R23 */
+        0x008B,     /* R24    - Left Line Input 1&2 Volume */
+        0x008B,     /* R25    - Left Line Input 3&4 Volume */
+        0x008B,     /* R26    - Right Line Input 1&2 Volume */
+        0x008B,     /* R27    - Right Line Input 3&4 Volume */
+        0x006D,     /* R28    - Left Output Volume */
+        0x006D,     /* R29    - Right Output Volume */
+        0x0066,     /* R30    - Line Outputs Volume */
+        0x0020,     /* R31    - HPOUT2 Volume */
+        0x0079,     /* R32    - Left OPGA Volume */
+        0x0079,     /* R33    - Right OPGA Volume */
+        0x0003,     /* R34    - SPKMIXL Attenuation */
+        0x0003,     /* R35    - SPKMIXR Attenuation */
+        0x0011,     /* R36    - SPKOUT Mixers */
+        0x0140,     /* R37    - ClassD */
+        0x0079,     /* R38    - Speaker Volume Left */
+        0x0079,     /* R39    - Speaker Volume Right */
+        0x0000,     /* R40    - Input Mixer (2) */
+        0x0000,     /* R41    - Input Mixer (3) */
+        0x0000,     /* R42    - Input Mixer (4) */
+        0x0000,     /* R43    - Input Mixer (5) */
+        0x0000,     /* R44    - Input Mixer (6) */
+        0x0000,     /* R45    - Output Mixer (1) */
+        0x0000,     /* R46    - Output Mixer (2) */
+        0x0000,     /* R47    - Output Mixer (3) */
+        0x0000,     /* R48    - Output Mixer (4) */
+        0x0000,     /* R49    - Output Mixer (5) */
+        0x0000,     /* R50    - Output Mixer (6) */
+        0x0000,     /* R51    - HPOUT2 Mixer */
+        0x0000,     /* R52    - Line Mixer (1) */
+        0x0000,     /* R53    - Line Mixer (2) */
+        0x0000,     /* R54    - Speaker Mixer */
+        0x0000,     /* R55    - Additional Control */
+        0x0000,     /* R56    - AntiPOP (1) */
+        0x0000,     /* R57    - AntiPOP (2) */
+        0x0000,     /* R58    - MICBIAS */
+        0x000D,     /* R59    - LDO 1 */
+        0x0003,     /* R60    - LDO 2 */
+        0x0000,     /* R61 */
+        0x0000,     /* R62 */
+        0x0000,     /* R63 */
+        0x0000,     /* R64 */
+        0x0000,     /* R65 */
+        0x0000,     /* R66 */
+        0x0000,     /* R67 */
+        0x0000,     /* R68 */
+        0x0000,     /* R69 */
+        0x0000,     /* R70 */
+        0x0000,     /* R71 */
+        0x0000,     /* R72 */
+        0x0000,     /* R73 */
+        0x0000,     /* R74 */
+        0x0000,     /* R75 */
+        0x1F25,     /* R76    - Charge Pump (1) */
+        0x0000,     /* R77 */
+        0x0000,     /* R78 */
+        0x0000,     /* R79 */
+        0x0000,     /* R80 */
+        0x0004,     /* R81    - Class W (1) */
+        0x0000,     /* R82 */
+        0x0000,     /* R83 */
+        0x0000,     /* R84    - DC Servo (1) */
+        0x054A,     /* R85    - DC Servo (2) */
+        0x0000,     /* R86 */
+        0x0000,     /* R87    - DC Servo (4) */
+        0x0000,     /* R88    - DC Servo Readback */
+        0x0000,     /* R89 */
+        0x0000,     /* R90 */
+        0x0000,     /* R91 */
+        0x0000,     /* R92 */
+        0x0000,     /* R93 */
+        0x0000,     /* R94 */
+        0x0000,     /* R95 */
+        0x0000,     /* R96    - Analogue HP (1) */
+        0x0000,     /* R97 */
+        0x0000,     /* R98 */
+        0x0000,     /* R99 */
+        0x0000,     /* R100 */
+        0x0000,     /* R101 */
+        0x0000,     /* R102 */
+        0x0000,     /* R103 */
+        0x0000,     /* R104 */
+        0x0000,     /* R105 */
+        0x0000,     /* R106 */
+        0x0000,     /* R107 */
+        0x0000,     /* R108 */
+        0x0000,     /* R109 */
+        0x0000,     /* R110 */
+        0x0000,     /* R111 */
+        0x0000,     /* R112 */
+        0x0000,     /* R113 */
+        0x0000,     /* R114 */
+        0x0000,     /* R115 */
+        0x0000,     /* R116 */
+        0x0000,     /* R117 */
+        0x0000,     /* R118 */
+        0x0000,     /* R119 */
+        0x0000,     /* R120 */
+        0x0000,     /* R121 */
+        0x0000,     /* R122 */
+        0x0000,     /* R123 */
+        0x0000,     /* R124 */
+        0x0000,     /* R125 */
+        0x0000,     /* R126 */
+        0x0000,     /* R127 */
+        0x0000,     /* R128 */
+        0x0000,     /* R129 */
+        0x0000,     /* R130 */
+        0x0000,     /* R131 */
+        0x0000,     /* R132 */
+        0x0000,     /* R133 */
+        0x0000,     /* R134 */
+        0x0000,     /* R135 */
+        0x0000,     /* R136 */
+        0x0000,     /* R137 */
+        0x0000,     /* R138 */
+        0x0000,     /* R139 */
+        0x0000,     /* R140 */
+        0x0000,     /* R141 */
+        0x0000,     /* R142 */
+        0x0000,     /* R143 */
+        0x0000,     /* R144 */
+        0x0000,     /* R145 */
+        0x0000,     /* R146 */
+        0x0000,     /* R147 */
+        0x0000,     /* R148 */
+        0x0000,     /* R149 */
+        0x0000,     /* R150 */
+        0x0000,     /* R151 */
+        0x0000,     /* R152 */
+        0x0000,     /* R153 */
+        0x0000,     /* R154 */
+        0x0000,     /* R155 */
+        0x0000,     /* R156 */
+        0x0000,     /* R157 */
+        0x0000,     /* R158 */
+        0x0000,     /* R159 */
+        0x0000,     /* R160 */
+        0x0000,     /* R161 */
+        0x0000,     /* R162 */
+        0x0000,     /* R163 */
+        0x0000,     /* R164 */
+        0x0000,     /* R165 */
+        0x0000,     /* R166 */
+        0x0000,     /* R167 */
+        0x0000,     /* R168 */
+        0x0000,     /* R169 */
+        0x0000,     /* R170 */
+        0x0000,     /* R171 */
+        0x0000,     /* R172 */
+        0x0000,     /* R173 */
+        0x0000,     /* R174 */
+        0x0000,     /* R175 */
+        0x0000,     /* R176 */
+        0x0000,     /* R177 */
+        0x0000,     /* R178 */
+        0x0000,     /* R179 */
+        0x0000,     /* R180 */
+        0x0000,     /* R181 */
+        0x0000,     /* R182 */
+        0x0000,     /* R183 */
+        0x0000,     /* R184 */
+        0x0000,     /* R185 */
+        0x0000,     /* R186 */
+        0x0000,     /* R187 */
+        0x0000,     /* R188 */
+        0x0000,     /* R189 */
+        0x0000,     /* R190 */
+        0x0000,     /* R191 */
+        0x0000,     /* R192 */
+        0x0000,     /* R193 */
+        0x0000,     /* R194 */
+        0x0000,     /* R195 */
+        0x0000,     /* R196 */
+        0x0000,     /* R197 */
+        0x0000,     /* R198 */
+        0x0000,     /* R199 */
+        0x0000,     /* R200 */
+        0x0000,     /* R201 */
+        0x0000,     /* R202 */
+        0x0000,     /* R203 */
+        0x0000,     /* R204 */
+        0x0000,     /* R205 */
+        0x0000,     /* R206 */
+        0x0000,     /* R207 */
+        0x0000,     /* R208 */
+        0x0000,     /* R209 */
+        0x0000,     /* R210 */
+        0x0000,     /* R211 */
+        0x0000,     /* R212 */
+        0x0000,     /* R213 */
+        0x0000,     /* R214 */
+        0x0000,     /* R215 */
+        0x0000,     /* R216 */
+        0x0000,     /* R217 */
+        0x0000,     /* R218 */
+        0x0000,     /* R219 */
+        0x0000,     /* R220 */
+        0x0000,     /* R221 */
+        0x0000,     /* R222 */
+        0x0000,     /* R223 */
+        0x0000,     /* R224 */
+        0x0000,     /* R225 */
+        0x0000,     /* R226 */
+        0x0000,     /* R227 */
+        0x0000,     /* R228 */
+        0x0000,     /* R229 */
+        0x0000,     /* R230 */
+        0x0000,     /* R231 */
+        0x0000,     /* R232 */
+        0x0000,     /* R233 */
+        0x0000,     /* R234 */
+        0x0000,     /* R235 */
+        0x0000,     /* R236 */
+        0x0000,     /* R237 */
+        0x0000,     /* R238 */
+        0x0000,     /* R239 */
+        0x0000,     /* R240 */
+        0x0000,     /* R241 */
+        0x0000,     /* R242 */
+        0x0000,     /* R243 */
+        0x0000,     /* R244 */
+        0x0000,     /* R245 */
+        0x0000,     /* R246 */
+        0x0000,     /* R247 */
+        0x0000,     /* R248 */
+        0x0000,     /* R249 */
+        0x0000,     /* R250 */
+        0x0000,     /* R251 */
+        0x0000,     /* R252 */
+        0x0000,     /* R253 */
+        0x0000,     /* R254 */
+        0x0000,     /* R255 */
+        0x0003,     /* R256   - Chip Revision */
+        0x8004,     /* R257   - Control Interface */
+        0x0000,     /* R258 */
+        0x0000,     /* R259 */
+        0x0000,     /* R260 */
+        0x0000,     /* R261 */
+        0x0000,     /* R262 */
+        0x0000,     /* R263 */
+        0x0000,     /* R264 */
+        0x0000,     /* R265 */
+        0x0000,     /* R266 */
+        0x0000,     /* R267 */
+        0x0000,     /* R268 */
+        0x0000,     /* R269 */
+        0x0000,     /* R270 */
+        0x0000,     /* R271 */
+        0x0000,     /* R272   - Write Sequencer Ctrl (1) */
+        0x0000,     /* R273   - Write Sequencer Ctrl (2) */
+        0x0000,     /* R274 */
+        0x0000,     /* R275 */
+        0x0000,     /* R276 */
+        0x0000,     /* R277 */
+        0x0000,     /* R278 */
+        0x0000,     /* R279 */
+        0x0000,     /* R280 */
+        0x0000,     /* R281 */
+        0x0000,     /* R282 */
+        0x0000,     /* R283 */
+        0x0000,     /* R284 */
+        0x0000,     /* R285 */
+        0x0000,     /* R286 */
+        0x0000,     /* R287 */
+        0x0000,     /* R288 */
+        0x0000,     /* R289 */
+        0x0000,     /* R290 */
+        0x0000,     /* R291 */
+        0x0000,     /* R292 */
+        0x0000,     /* R293 */
+        0x0000,     /* R294 */
+        0x0000,     /* R295 */
+        0x0000,     /* R296 */
+        0x0000,     /* R297 */
+        0x0000,     /* R298 */
+        0x0000,     /* R299 */
+        0x0000,     /* R300 */
+        0x0000,     /* R301 */
+        0x0000,     /* R302 */
+        0x0000,     /* R303 */
+        0x0000,     /* R304 */
+        0x0000,     /* R305 */
+        0x0000,     /* R306 */
+        0x0000,     /* R307 */
+        0x0000,     /* R308 */
+        0x0000,     /* R309 */
+        0x0000,     /* R310 */
+        0x0000,     /* R311 */
+        0x0000,     /* R312 */
+        0x0000,     /* R313 */
+        0x0000,     /* R314 */
+        0x0000,     /* R315 */
+        0x0000,     /* R316 */
+        0x0000,     /* R317 */
+        0x0000,     /* R318 */
+        0x0000,     /* R319 */
+        0x0000,     /* R320 */
+        0x0000,     /* R321 */
+        0x0000,     /* R322 */
+        0x0000,     /* R323 */
+        0x0000,     /* R324 */
+        0x0000,     /* R325 */
+        0x0000,     /* R326 */
+        0x0000,     /* R327 */
+        0x0000,     /* R328 */
+        0x0000,     /* R329 */
+        0x0000,     /* R330 */
+        0x0000,     /* R331 */
+        0x0000,     /* R332 */
+        0x0000,     /* R333 */
+        0x0000,     /* R334 */
+        0x0000,     /* R335 */
+        0x0000,     /* R336 */
+        0x0000,     /* R337 */
+        0x0000,     /* R338 */
+        0x0000,     /* R339 */
+        0x0000,     /* R340 */
+        0x0000,     /* R341 */
+        0x0000,     /* R342 */
+        0x0000,     /* R343 */
+        0x0000,     /* R344 */
+        0x0000,     /* R345 */
+        0x0000,     /* R346 */
+        0x0000,     /* R347 */
+        0x0000,     /* R348 */
+        0x0000,     /* R349 */
+        0x0000,     /* R350 */
+        0x0000,     /* R351 */
+        0x0000,     /* R352 */
+        0x0000,     /* R353 */
+        0x0000,     /* R354 */
+        0x0000,     /* R355 */
+        0x0000,     /* R356 */
+        0x0000,     /* R357 */
+        0x0000,     /* R358 */
+        0x0000,     /* R359 */
+        0x0000,     /* R360 */
+        0x0000,     /* R361 */
+        0x0000,     /* R362 */
+        0x0000,     /* R363 */
+        0x0000,     /* R364 */
+        0x0000,     /* R365 */
+        0x0000,     /* R366 */
+        0x0000,     /* R367 */
+        0x0000,     /* R368 */
+        0x0000,     /* R369 */
+        0x0000,     /* R370 */
+        0x0000,     /* R371 */
+        0x0000,     /* R372 */
+        0x0000,     /* R373 */
+        0x0000,     /* R374 */
+        0x0000,     /* R375 */
+        0x0000,     /* R376 */
+        0x0000,     /* R377 */
+        0x0000,     /* R378 */
+        0x0000,     /* R379 */
+        0x0000,     /* R380 */
+        0x0000,     /* R381 */
+        0x0000,     /* R382 */
+        0x0000,     /* R383 */
+        0x0000,     /* R384 */
+        0x0000,     /* R385 */
+        0x0000,     /* R386 */
+        0x0000,     /* R387 */
+        0x0000,     /* R388 */
+        0x0000,     /* R389 */
+        0x0000,     /* R390 */
+        0x0000,     /* R391 */
+        0x0000,     /* R392 */
+        0x0000,     /* R393 */
+        0x0000,     /* R394 */
+        0x0000,     /* R395 */
+        0x0000,     /* R396 */
+        0x0000,     /* R397 */
+        0x0000,     /* R398 */
+        0x0000,     /* R399 */
+        0x0000,     /* R400 */
+        0x0000,     /* R401 */
+        0x0000,     /* R402 */
+        0x0000,     /* R403 */
+        0x0000,     /* R404 */
+        0x0000,     /* R405 */
+        0x0000,     /* R406 */
+        0x0000,     /* R407 */
+        0x0000,     /* R408 */
+        0x0000,     /* R409 */
+        0x0000,     /* R410 */
+        0x0000,     /* R411 */
+        0x0000,     /* R412 */
+        0x0000,     /* R413 */
+        0x0000,     /* R414 */
+        0x0000,     /* R415 */
+        0x0000,     /* R416 */
+        0x0000,     /* R417 */
+        0x0000,     /* R418 */
+        0x0000,     /* R419 */
+        0x0000,     /* R420 */
+        0x0000,     /* R421 */
+        0x0000,     /* R422 */
+        0x0000,     /* R423 */
+        0x0000,     /* R424 */
+        0x0000,     /* R425 */
+        0x0000,     /* R426 */
+        0x0000,     /* R427 */
+        0x0000,     /* R428 */
+        0x0000,     /* R429 */
+        0x0000,     /* R430 */
+        0x0000,     /* R431 */
+        0x0000,     /* R432 */
+        0x0000,     /* R433 */
+        0x0000,     /* R434 */
+        0x0000,     /* R435 */
+        0x0000,     /* R436 */
+        0x0000,     /* R437 */
+        0x0000,     /* R438 */
+        0x0000,     /* R439 */
+        0x0000,     /* R440 */
+        0x0000,     /* R441 */
+        0x0000,     /* R442 */
+        0x0000,     /* R443 */
+        0x0000,     /* R444 */
+        0x0000,     /* R445 */
+        0x0000,     /* R446 */
+        0x0000,     /* R447 */
+        0x0000,     /* R448 */
+        0x0000,     /* R449 */
+        0x0000,     /* R450 */
+        0x0000,     /* R451 */
+        0x0000,     /* R452 */
+        0x0000,     /* R453 */
+        0x0000,     /* R454 */
+        0x0000,     /* R455 */
+        0x0000,     /* R456 */
+        0x0000,     /* R457 */
+        0x0000,     /* R458 */
+        0x0000,     /* R459 */
+        0x0000,     /* R460 */
+        0x0000,     /* R461 */
+        0x0000,     /* R462 */
+        0x0000,     /* R463 */
+        0x0000,     /* R464 */
+        0x0000,     /* R465 */
+        0x0000,     /* R466 */
+        0x0000,     /* R467 */
+        0x0000,     /* R468 */
+        0x0000,     /* R469 */
+        0x0000,     /* R470 */
+        0x0000,     /* R471 */
+        0x0000,     /* R472 */
+        0x0000,     /* R473 */
+        0x0000,     /* R474 */
+        0x0000,     /* R475 */
+        0x0000,     /* R476 */
+        0x0000,     /* R477 */
+        0x0000,     /* R478 */
+        0x0000,     /* R479 */
+        0x0000,     /* R480 */
+        0x0000,     /* R481 */
+        0x0000,     /* R482 */
+        0x0000,     /* R483 */
+        0x0000,     /* R484 */
+        0x0000,     /* R485 */
+        0x0000,     /* R486 */
+        0x0000,     /* R487 */
+        0x0000,     /* R488 */
+        0x0000,     /* R489 */
+        0x0000,     /* R490 */
+        0x0000,     /* R491 */
+        0x0000,     /* R492 */
+        0x0000,     /* R493 */
+        0x0000,     /* R494 */
+        0x0000,     /* R495 */
+        0x0000,     /* R496 */
+        0x0000,     /* R497 */
+        0x0000,     /* R498 */
+        0x0000,     /* R499 */
+        0x0000,     /* R500 */
+        0x0000,     /* R501 */
+        0x0000,     /* R502 */
+        0x0000,     /* R503 */
+        0x0000,     /* R504 */
+        0x0000,     /* R505 */
+        0x0000,     /* R506 */
+        0x0000,     /* R507 */
+        0x0000,     /* R508 */
+        0x0000,     /* R509 */
+        0x0000,     /* R510 */
+        0x0000,     /* R511 */
+        0x0000,     /* R512   - AIF1 Clocking (1) */
+        0x0000,     /* R513   - AIF1 Clocking (2) */
+        0x0000,     /* R514 */
+        0x0000,     /* R515 */
+        0x0000,     /* R516   - AIF2 Clocking (1) */
+        0x0000,     /* R517   - AIF2 Clocking (2) */
+        0x0000,     /* R518 */
+        0x0000,     /* R519 */
+        0x0000,     /* R520   - Clocking (1) */
+        0x0000,     /* R521   - Clocking (2) */
+        0x0000,     /* R522 */
+        0x0000,     /* R523 */
+        0x0000,     /* R524 */
+        0x0000,     /* R525 */
+        0x0000,     /* R526 */
+        0x0000,     /* R527 */
+        0x0083,     /* R528   - AIF1 Rate */
+        0x0083,     /* R529   - AIF2 Rate */
+        0x0000,     /* R530   - Rate Status */
+        0x0000,     /* R531 */
+        0x0000,     /* R532 */
+        0x0000,     /* R533 */
+        0x0000,     /* R534 */
+        0x0000,     /* R535 */
+        0x0000,     /* R536 */
+        0x0000,     /* R537 */
+        0x0000,     /* R538 */
+        0x0000,     /* R539 */
+        0x0000,     /* R540 */
+        0x0000,     /* R541 */
+        0x0000,     /* R542 */
+        0x0000,     /* R543 */
+        0x0000,     /* R544   - FLL1 Control (1) */
+        0x0000,     /* R545   - FLL1 Control (2) */
+        0x0000,     /* R546   - FLL1 Control (3) */
+        0x0000,     /* R547   - FLL1 Control (4) */
+        0x0C80,     /* R548   - FLL1 Control (5) */
+        0x0000,     /* R549 */
+        0x0000,     /* R550 */
+        0x0000,     /* R551 */
+        0x0000,     /* R552 */
+        0x0000,     /* R553 */
+        0x0000,     /* R554 */
+        0x0000,     /* R555 */
+        0x0000,     /* R556 */
+        0x0000,     /* R557 */
+        0x0000,     /* R558 */
+        0x0000,     /* R559 */
+        0x0000,     /* R560 */
+        0x0000,     /* R561 */
+        0x0000,     /* R562 */
+        0x0000,     /* R563 */
+        0x0000,     /* R564 */
+        0x0000,     /* R565 */
+        0x0000,     /* R566 */
+        0x0000,     /* R567 */
+        0x0000,     /* R568 */
+        0x0000,     /* R569 */
+        0x0000,     /* R570 */
+        0x0000,     /* R571 */
+        0x0000,     /* R572 */
+        0x0000,     /* R573 */
+        0x0000,     /* R574 */
+        0x0000,     /* R575 */
+        0x0000,     /* R576   - FLL2 Control (1) */
+        0x0000,     /* R577   - FLL2 Control (2) */
+        0x0000,     /* R578   - FLL2 Control (3) */
+        0x0000,     /* R579   - FLL2 Control (4) */
+        0x0C80,     /* R580   - FLL2 Control (5) */
+        0x0000,     /* R581 */
+        0x0000,     /* R582 */
+        0x0000,     /* R583 */
+        0x0000,     /* R584 */
+        0x0000,     /* R585 */
+        0x0000,     /* R586 */
+        0x0000,     /* R587 */
+        0x0000,     /* R588 */
+        0x0000,     /* R589 */
+        0x0000,     /* R590 */
+        0x0000,     /* R591 */
+        0x0000,     /* R592 */
+        0x0000,     /* R593 */
+        0x0000,     /* R594 */
+        0x0000,     /* R595 */
+        0x0000,     /* R596 */
+        0x0000,     /* R597 */
+        0x0000,     /* R598 */
+        0x0000,     /* R599 */
+        0x0000,     /* R600 */
+        0x0000,     /* R601 */
+        0x0000,     /* R602 */
+        0x0000,     /* R603 */
+        0x0000,     /* R604 */
+        0x0000,     /* R605 */
+        0x0000,     /* R606 */
+        0x0000,     /* R607 */
+        0x0000,     /* R608 */
+        0x0000,     /* R609 */
+        0x0000,     /* R610 */
+        0x0000,     /* R611 */
+        0x0000,     /* R612 */
+        0x0000,     /* R613 */
+        0x0000,     /* R614 */
+        0x0000,     /* R615 */
+        0x0000,     /* R616 */
+        0x0000,     /* R617 */
+        0x0000,     /* R618 */
+        0x0000,     /* R619 */
+        0x0000,     /* R620 */
+        0x0000,     /* R621 */
+        0x0000,     /* R622 */
+        0x0000,     /* R623 */
+        0x0000,     /* R624 */
+        0x0000,     /* R625 */
+        0x0000,     /* R626 */
+        0x0000,     /* R627 */
+        0x0000,     /* R628 */
+        0x0000,     /* R629 */
+        0x0000,     /* R630 */
+        0x0000,     /* R631 */
+        0x0000,     /* R632 */
+        0x0000,     /* R633 */
+        0x0000,     /* R634 */
+        0x0000,     /* R635 */
+        0x0000,     /* R636 */
+        0x0000,     /* R637 */
+        0x0000,     /* R638 */
+        0x0000,     /* R639 */
+        0x0000,     /* R640 */
+        0x0000,     /* R641 */
+        0x0000,     /* R642 */
+        0x0000,     /* R643 */
+        0x0000,     /* R644 */
+        0x0000,     /* R645 */
+        0x0000,     /* R646 */
+        0x0000,     /* R647 */
+        0x0000,     /* R648 */
+        0x0000,     /* R649 */
+        0x0000,     /* R650 */
+        0x0000,     /* R651 */
+        0x0000,     /* R652 */
+        0x0000,     /* R653 */
+        0x0000,     /* R654 */
+        0x0000,     /* R655 */
+        0x0000,     /* R656 */
+        0x0000,     /* R657 */
+        0x0000,     /* R658 */
+        0x0000,     /* R659 */
+        0x0000,     /* R660 */
+        0x0000,     /* R661 */
+        0x0000,     /* R662 */
+        0x0000,     /* R663 */
+        0x0000,     /* R664 */
+        0x0000,     /* R665 */
+        0x0000,     /* R666 */
+        0x0000,     /* R667 */
+        0x0000,     /* R668 */
+        0x0000,     /* R669 */
+        0x0000,     /* R670 */
+        0x0000,     /* R671 */
+        0x0000,     /* R672 */
+        0x0000,     /* R673 */
+        0x0000,     /* R674 */
+        0x0000,     /* R675 */
+        0x0000,     /* R676 */
+        0x0000,     /* R677 */
+        0x0000,     /* R678 */
+        0x0000,     /* R679 */
+        0x0000,     /* R680 */
+        0x0000,     /* R681 */
+        0x0000,     /* R682 */
+        0x0000,     /* R683 */
+        0x0000,     /* R684 */
+        0x0000,     /* R685 */
+        0x0000,     /* R686 */
+        0x0000,     /* R687 */
+        0x0000,     /* R688 */
+        0x0000,     /* R689 */
+        0x0000,     /* R690 */
+        0x0000,     /* R691 */
+        0x0000,     /* R692 */
+        0x0000,     /* R693 */
+        0x0000,     /* R694 */
+        0x0000,     /* R695 */
+        0x0000,     /* R696 */
+        0x0000,     /* R697 */
+        0x0000,     /* R698 */
+        0x0000,     /* R699 */
+        0x0000,     /* R700 */
+        0x0000,     /* R701 */
+        0x0000,     /* R702 */
+        0x0000,     /* R703 */
+        0x0000,     /* R704 */
+        0x0000,     /* R705 */
+        0x0000,     /* R706 */
+        0x0000,     /* R707 */
+        0x0000,     /* R708 */
+        0x0000,     /* R709 */
+        0x0000,     /* R710 */
+        0x0000,     /* R711 */
+        0x0000,     /* R712 */
+        0x0000,     /* R713 */
+        0x0000,     /* R714 */
+        0x0000,     /* R715 */
+        0x0000,     /* R716 */
+        0x0000,     /* R717 */
+        0x0000,     /* R718 */
+        0x0000,     /* R719 */
+        0x0000,     /* R720 */
+        0x0000,     /* R721 */
+        0x0000,     /* R722 */
+        0x0000,     /* R723 */
+        0x0000,     /* R724 */
+        0x0000,     /* R725 */
+        0x0000,     /* R726 */
+        0x0000,     /* R727 */
+        0x0000,     /* R728 */
+        0x0000,     /* R729 */
+        0x0000,     /* R730 */
+        0x0000,     /* R731 */
+        0x0000,     /* R732 */
+        0x0000,     /* R733 */
+        0x0000,     /* R734 */
+        0x0000,     /* R735 */
+        0x0000,     /* R736 */
+        0x0000,     /* R737 */
+        0x0000,     /* R738 */
+        0x0000,     /* R739 */
+        0x0000,     /* R740 */
+        0x0000,     /* R741 */
+        0x0000,     /* R742 */
+        0x0000,     /* R743 */
+        0x0000,     /* R744 */
+        0x0000,     /* R745 */
+        0x0000,     /* R746 */
+        0x0000,     /* R747 */
+        0x0000,     /* R748 */
+        0x0000,     /* R749 */
+        0x0000,     /* R750 */
+        0x0000,     /* R751 */
+        0x0000,     /* R752 */
+        0x0000,     /* R753 */
+        0x0000,     /* R754 */
+        0x0000,     /* R755 */
+        0x0000,     /* R756 */
+        0x0000,     /* R757 */
+        0x0000,     /* R758 */
+        0x0000,     /* R759 */
+        0x0000,     /* R760 */
+        0x0000,     /* R761 */
+        0x0000,     /* R762 */
+        0x0000,     /* R763 */
+        0x0000,     /* R764 */
+        0x0000,     /* R765 */
+        0x0000,     /* R766 */
+        0x0000,     /* R767 */
+        0x4050,     /* R768   - AIF1 Control (1) */
+        0x4000,     /* R769   - AIF1 Control (2) */
+        0x0000,     /* R770   - AIF1 Master/Slave */
+        0x0040,     /* R771   - AIF1 BCLK */
+        0x0040,     /* R772   - AIF1ADC LRCLK */
+        0x0040,     /* R773   - AIF1DAC LRCLK */
+        0x0004,     /* R774   - AIF1DAC Data */
+        0x0100,     /* R775   - AIF1ADC Data */
+        0x0000,     /* R776 */
+        0x0000,     /* R777 */
+        0x0000,     /* R778 */
+        0x0000,     /* R779 */
+        0x0000,     /* R780 */
+        0x0000,     /* R781 */
+        0x0000,     /* R782 */
+        0x0000,     /* R783 */
+        0x4050,     /* R784   - AIF2 Control (1) */
+        0x4000,     /* R785   - AIF2 Control (2) */
+        0x0000,     /* R786   - AIF2 Master/Slave */
+        0x0040,     /* R787   - AIF2 BCLK */
+        0x0040,     /* R788   - AIF2ADC LRCLK */
+        0x0040,     /* R789   - AIF2DAC LRCLK */
+        0x0000,     /* R790   - AIF2DAC Data */
+        0x0000,     /* R791   - AIF2ADC Data */
+        0x0000,     /* R792 */
+        0x0000,     /* R793 */
+        0x0000,     /* R794 */
+        0x0000,     /* R795 */
+        0x0000,     /* R796 */
+        0x0000,     /* R797 */
+        0x0000,     /* R798 */
+        0x0000,     /* R799 */
+        0x0000,     /* R800 */
+        0x0000,     /* R801 */
+        0x0000,     /* R802 */
+        0x0000,     /* R803 */
+        0x0000,     /* R804 */
+        0x0000,     /* R805 */
+        0x0000,     /* R806 */
+        0x0000,     /* R807 */
+        0x0000,     /* R808 */
+        0x0000,     /* R809 */
+        0x0000,     /* R810 */
+        0x0000,     /* R811 */
+        0x0000,     /* R812 */
+        0x0000,     /* R813 */
+        0x0000,     /* R814 */
+        0x0000,     /* R815 */
+        0x0000,     /* R816 */
+        0x0000,     /* R817 */
+        0x0000,     /* R818 */
+        0x0000,     /* R819 */
+        0x0000,     /* R820 */
+        0x0000,     /* R821 */
+        0x0000,     /* R822 */
+        0x0000,     /* R823 */
+        0x0000,     /* R824 */
+        0x0000,     /* R825 */
+        0x0000,     /* R826 */
+        0x0000,     /* R827 */
+        0x0000,     /* R828 */
+        0x0000,     /* R829 */
+        0x0000,     /* R830 */
+        0x0000,     /* R831 */
+        0x0000,     /* R832 */
+        0x0000,     /* R833 */
+        0x0000,     /* R834 */
+        0x0000,     /* R835 */
+        0x0000,     /* R836 */
+        0x0000,     /* R837 */
+        0x0000,     /* R838 */
+        0x0000,     /* R839 */
+        0x0000,     /* R840 */
+        0x0000,     /* R841 */
+        0x0000,     /* R842 */
+        0x0000,     /* R843 */
+        0x0000,     /* R844 */
+        0x0000,     /* R845 */
+        0x0000,     /* R846 */
+        0x0000,     /* R847 */
+        0x0000,     /* R848 */
+        0x0000,     /* R849 */
+        0x0000,     /* R850 */
+        0x0000,     /* R851 */
+        0x0000,     /* R852 */
+        0x0000,     /* R853 */
+        0x0000,     /* R854 */
+        0x0000,     /* R855 */
+        0x0000,     /* R856 */
+        0x0000,     /* R857 */
+        0x0000,     /* R858 */
+        0x0000,     /* R859 */
+        0x0000,     /* R860 */
+        0x0000,     /* R861 */
+        0x0000,     /* R862 */
+        0x0000,     /* R863 */
+        0x0000,     /* R864 */
+        0x0000,     /* R865 */
+        0x0000,     /* R866 */
+        0x0000,     /* R867 */
+        0x0000,     /* R868 */
+        0x0000,     /* R869 */
+        0x0000,     /* R870 */
+        0x0000,     /* R871 */
+        0x0000,     /* R872 */
+        0x0000,     /* R873 */
+        0x0000,     /* R874 */
+        0x0000,     /* R875 */
+        0x0000,     /* R876 */
+        0x0000,     /* R877 */
+        0x0000,     /* R878 */
+        0x0000,     /* R879 */
+        0x0000,     /* R880 */
+        0x0000,     /* R881 */
+        0x0000,     /* R882 */
+        0x0000,     /* R883 */
+        0x0000,     /* R884 */
+        0x0000,     /* R885 */
+        0x0000,     /* R886 */
+        0x0000,     /* R887 */
+        0x0000,     /* R888 */
+        0x0000,     /* R889 */
+        0x0000,     /* R890 */
+        0x0000,     /* R891 */
+        0x0000,     /* R892 */
+        0x0000,     /* R893 */
+        0x0000,     /* R894 */
+        0x0000,     /* R895 */
+        0x0000,     /* R896 */
+        0x0000,     /* R897 */
+        0x0000,     /* R898 */
+        0x0000,     /* R899 */
+        0x0000,     /* R900 */
+        0x0000,     /* R901 */
+        0x0000,     /* R902 */
+        0x0000,     /* R903 */
+        0x0000,     /* R904 */
+        0x0000,     /* R905 */
+        0x0000,     /* R906 */
+        0x0000,     /* R907 */
+        0x0000,     /* R908 */
+        0x0000,     /* R909 */
+        0x0000,     /* R910 */
+        0x0000,     /* R911 */
+        0x0000,     /* R912 */
+        0x0000,     /* R913 */
+        0x0000,     /* R914 */
+        0x0000,     /* R915 */
+        0x0000,     /* R916 */
+        0x0000,     /* R917 */
+        0x0000,     /* R918 */
+        0x0000,     /* R919 */
+        0x0000,     /* R920 */
+        0x0000,     /* R921 */
+        0x0000,     /* R922 */
+        0x0000,     /* R923 */
+        0x0000,     /* R924 */
+        0x0000,     /* R925 */
+        0x0000,     /* R926 */
+        0x0000,     /* R927 */
+        0x0000,     /* R928 */
+        0x0000,     /* R929 */
+        0x0000,     /* R930 */
+        0x0000,     /* R931 */
+        0x0000,     /* R932 */
+        0x0000,     /* R933 */
+        0x0000,     /* R934 */
+        0x0000,     /* R935 */
+        0x0000,     /* R936 */
+        0x0000,     /* R937 */
+        0x0000,     /* R938 */
+        0x0000,     /* R939 */
+        0x0000,     /* R940 */
+        0x0000,     /* R941 */
+        0x0000,     /* R942 */
+        0x0000,     /* R943 */
+        0x0000,     /* R944 */
+        0x0000,     /* R945 */
+        0x0000,     /* R946 */
+        0x0000,     /* R947 */
+        0x0000,     /* R948 */
+        0x0000,     /* R949 */
+        0x0000,     /* R950 */
+        0x0000,     /* R951 */
+        0x0000,     /* R952 */
+        0x0000,     /* R953 */
+        0x0000,     /* R954 */
+        0x0000,     /* R955 */
+        0x0000,     /* R956 */
+        0x0000,     /* R957 */
+        0x0000,     /* R958 */
+        0x0000,     /* R959 */
+        0x0000,     /* R960 */
+        0x0000,     /* R961 */
+        0x0000,     /* R962 */
+        0x0000,     /* R963 */
+        0x0000,     /* R964 */
+        0x0000,     /* R965 */
+        0x0000,     /* R966 */
+        0x0000,     /* R967 */
+        0x0000,     /* R968 */
+        0x0000,     /* R969 */
+        0x0000,     /* R970 */
+        0x0000,     /* R971 */
+        0x0000,     /* R972 */
+        0x0000,     /* R973 */
+        0x0000,     /* R974 */
+        0x0000,     /* R975 */
+        0x0000,     /* R976 */
+        0x0000,     /* R977 */
+        0x0000,     /* R978 */
+        0x0000,     /* R979 */
+        0x0000,     /* R980 */
+        0x0000,     /* R981 */
+        0x0000,     /* R982 */
+        0x0000,     /* R983 */
+        0x0000,     /* R984 */
+        0x0000,     /* R985 */
+        0x0000,     /* R986 */
+        0x0000,     /* R987 */
+        0x0000,     /* R988 */
+        0x0000,     /* R989 */
+        0x0000,     /* R990 */
+        0x0000,     /* R991 */
+        0x0000,     /* R992 */
+        0x0000,     /* R993 */
+        0x0000,     /* R994 */
+        0x0000,     /* R995 */
+        0x0000,     /* R996 */
+        0x0000,     /* R997 */
+        0x0000,     /* R998 */
+        0x0000,     /* R999 */
+        0x0000,     /* R1000 */
+        0x0000,     /* R1001 */
+        0x0000,     /* R1002 */
+        0x0000,     /* R1003 */
+        0x0000,     /* R1004 */
+        0x0000,     /* R1005 */
+        0x0000,     /* R1006 */
+        0x0000,     /* R1007 */
+        0x0000,     /* R1008 */
+        0x0000,     /* R1009 */
+        0x0000,     /* R1010 */
+        0x0000,     /* R1011 */
+        0x0000,     /* R1012 */
+        0x0000,     /* R1013 */
+        0x0000,     /* R1014 */
+        0x0000,     /* R1015 */
+        0x0000,     /* R1016 */
+        0x0000,     /* R1017 */
+        0x0000,     /* R1018 */
+        0x0000,     /* R1019 */
+        0x0000,     /* R1020 */
+        0x0000,     /* R1021 */
+        0x0000,     /* R1022 */
+        0x0000,     /* R1023 */
+        0x00C0,     /* R1024  - AIF1 ADC1 Left Volume */
+        0x00C0,     /* R1025  - AIF1 ADC1 Right Volume */
+        0x00C0,     /* R1026  - AIF1 DAC1 Left Volume */
+        0x00C0,     /* R1027  - AIF1 DAC1 Right Volume */
+        0x00C0,     /* R1028  - AIF1 ADC2 Left Volume */
+        0x00C0,     /* R1029  - AIF1 ADC2 Right Volume */
+        0x00C0,     /* R1030  - AIF1 DAC2 Left Volume */
+        0x00C0,     /* R1031  - AIF1 DAC2 Right Volume */
+        0x0000,     /* R1032 */
+        0x0000,     /* R1033 */
+        0x0000,     /* R1034 */
+        0x0000,     /* R1035 */
+        0x0000,     /* R1036 */
+        0x0000,     /* R1037 */
+        0x0000,     /* R1038 */
+        0x0000,     /* R1039 */
+        0x0000,     /* R1040  - AIF1 ADC1 Filters */
+        0x0000,     /* R1041  - AIF1 ADC2 Filters */
+        0x0000,     /* R1042 */
+        0x0000,     /* R1043 */
+        0x0000,     /* R1044 */
+        0x0000,     /* R1045 */
+        0x0000,     /* R1046 */
+        0x0000,     /* R1047 */
+        0x0000,     /* R1048 */
+        0x0000,     /* R1049 */
+        0x0000,     /* R1050 */
+        0x0000,     /* R1051 */
+        0x0000,     /* R1052 */
+        0x0000,     /* R1053 */
+        0x0000,     /* R1054 */
+        0x0000,     /* R1055 */
+        0x0200,     /* R1056  - AIF1 DAC1 Filters (1) */
+        0x0010,     /* R1057  - AIF1 DAC1 Filters (2) */
+        0x0200,     /* R1058  - AIF1 DAC2 Filters (1) */
+        0x0010,     /* R1059  - AIF1 DAC2 Filters (2) */
+        0x0000,     /* R1060 */
+        0x0000,     /* R1061 */
+        0x0000,     /* R1062 */
+        0x0000,     /* R1063 */
+        0x0000,     /* R1064 */
+        0x0000,     /* R1065 */
+        0x0000,     /* R1066 */
+        0x0000,     /* R1067 */
+        0x0000,     /* R1068 */
+        0x0000,     /* R1069 */
+        0x0000,     /* R1070 */
+        0x0000,     /* R1071 */
+        0x0000,     /* R1072 */
+        0x0000,     /* R1073 */
+        0x0000,     /* R1074 */
+        0x0000,     /* R1075 */
+        0x0000,     /* R1076 */
+        0x0000,     /* R1077 */
+        0x0000,     /* R1078 */
+        0x0000,     /* R1079 */
+        0x0000,     /* R1080 */
+        0x0000,     /* R1081 */
+        0x0000,     /* R1082 */
+        0x0000,     /* R1083 */
+        0x0000,     /* R1084 */
+        0x0000,     /* R1085 */
+        0x0000,     /* R1086 */
+        0x0000,     /* R1087 */
+        0x0098,     /* R1088  - AIF1 DRC1 (1) */
+        0x0845,     /* R1089  - AIF1 DRC1 (2) */
+        0x0000,     /* R1090  - AIF1 DRC1 (3) */
+        0x0000,     /* R1091  - AIF1 DRC1 (4) */
+        0x0000,     /* R1092  - AIF1 DRC1 (5) */
+        0x0000,     /* R1093 */
+        0x0000,     /* R1094 */
+        0x0000,     /* R1095 */
+        0x0000,     /* R1096 */
+        0x0000,     /* R1097 */
+        0x0000,     /* R1098 */
+        0x0000,     /* R1099 */
+        0x0000,     /* R1100 */
+        0x0000,     /* R1101 */
+        0x0000,     /* R1102 */
+        0x0000,     /* R1103 */
+        0x0098,     /* R1104  - AIF1 DRC2 (1) */
+        0x0845,     /* R1105  - AIF1 DRC2 (2) */
+        0x0000,     /* R1106  - AIF1 DRC2 (3) */
+        0x0000,     /* R1107  - AIF1 DRC2 (4) */
+        0x0000,     /* R1108  - AIF1 DRC2 (5) */
+        0x0000,     /* R1109 */
+        0x0000,     /* R1110 */
+        0x0000,     /* R1111 */
+        0x0000,     /* R1112 */
+        0x0000,     /* R1113 */
+        0x0000,     /* R1114 */
+        0x0000,     /* R1115 */
+        0x0000,     /* R1116 */
+        0x0000,     /* R1117 */
+        0x0000,     /* R1118 */
+        0x0000,     /* R1119 */
+        0x0000,     /* R1120 */
+        0x0000,     /* R1121 */
+        0x0000,     /* R1122 */
+        0x0000,     /* R1123 */
+        0x0000,     /* R1124 */
+        0x0000,     /* R1125 */
+        0x0000,     /* R1126 */
+        0x0000,     /* R1127 */
+        0x0000,     /* R1128 */
+        0x0000,     /* R1129 */
+        0x0000,     /* R1130 */
+        0x0000,     /* R1131 */
+        0x0000,     /* R1132 */
+        0x0000,     /* R1133 */
+        0x0000,     /* R1134 */
+        0x0000,     /* R1135 */
+        0x0000,     /* R1136 */
+        0x0000,     /* R1137 */
+        0x0000,     /* R1138 */
+        0x0000,     /* R1139 */
+        0x0000,     /* R1140 */
+        0x0000,     /* R1141 */
+        0x0000,     /* R1142 */
+        0x0000,     /* R1143 */
+        0x0000,     /* R1144 */
+        0x0000,     /* R1145 */
+        0x0000,     /* R1146 */
+        0x0000,     /* R1147 */
+        0x0000,     /* R1148 */
+        0x0000,     /* R1149 */
+        0x0000,     /* R1150 */
+        0x0000,     /* R1151 */
+        0x6318,     /* R1152  - AIF1 DAC1 EQ Gains (1) */
+        0x6300,     /* R1153  - AIF1 DAC1 EQ Gains (2) */
+        0x0FCA,     /* R1154  - AIF1 DAC1 EQ Band 1 A */
+        0x0400,     /* R1155  - AIF1 DAC1 EQ Band 1 B */
+        0x00D8,     /* R1156  - AIF1 DAC1 EQ Band 1 PG */
+        0x1EB5,     /* R1157  - AIF1 DAC1 EQ Band 2 A */
+        0xF145,     /* R1158  - AIF1 DAC1 EQ Band 2 B */
+        0x0B75,     /* R1159  - AIF1 DAC1 EQ Band 2 C */
+        0x01C5,     /* R1160  - AIF1 DAC1 EQ Band 2 PG */
+        0x1C58,     /* R1161  - AIF1 DAC1 EQ Band 3 A */
+        0xF373,     /* R1162  - AIF1 DAC1 EQ Band 3 B */
+        0x0A54,     /* R1163  - AIF1 DAC1 EQ Band 3 C */
+        0x0558,     /* R1164  - AIF1 DAC1 EQ Band 3 PG */
+        0x168E,     /* R1165  - AIF1 DAC1 EQ Band 4 A */
+        0xF829,     /* R1166  - AIF1 DAC1 EQ Band 4 B */
+        0x07AD,     /* R1167  - AIF1 DAC1 EQ Band 4 C */
+        0x1103,     /* R1168  - AIF1 DAC1 EQ Band 4 PG */
+        0x0564,     /* R1169  - AIF1 DAC1 EQ Band 5 A */
+        0x0559,     /* R1170  - AIF1 DAC1 EQ Band 5 B */
+        0x4000,     /* R1171  - AIF1 DAC1 EQ Band 5 PG */
+        0x0000,     /* R1172 */
+        0x0000,     /* R1173 */
+        0x0000,     /* R1174 */
+        0x0000,     /* R1175 */
+        0x0000,     /* R1176 */
+        0x0000,     /* R1177 */
+        0x0000,     /* R1178 */
+        0x0000,     /* R1179 */
+        0x0000,     /* R1180 */
+        0x0000,     /* R1181 */
+        0x0000,     /* R1182 */
+        0x0000,     /* R1183 */
+        0x6318,     /* R1184  - AIF1 DAC2 EQ Gains (1) */
+        0x6300,     /* R1185  - AIF1 DAC2 EQ Gains (2) */
+        0x0FCA,     /* R1186  - AIF1 DAC2 EQ Band 1 A */
+        0x0400,     /* R1187  - AIF1 DAC2 EQ Band 1 B */
+        0x00D8,     /* R1188  - AIF1 DAC2 EQ Band 1 PG */
+        0x1EB5,     /* R1189  - AIF1 DAC2 EQ Band 2 A */
+        0xF145,     /* R1190  - AIF1 DAC2 EQ Band 2 B */
+        0x0B75,     /* R1191  - AIF1 DAC2 EQ Band 2 C */
+        0x01C5,     /* R1192  - AIF1 DAC2 EQ Band 2 PG */
+        0x1C58,     /* R1193  - AIF1 DAC2 EQ Band 3 A */
+        0xF373,     /* R1194  - AIF1 DAC2 EQ Band 3 B */
+        0x0A54,     /* R1195  - AIF1 DAC2 EQ Band 3 C */
+        0x0558,     /* R1196  - AIF1 DAC2 EQ Band 3 PG */
+        0x168E,     /* R1197  - AIF1 DAC2 EQ Band 4 A */
+        0xF829,     /* R1198  - AIF1 DAC2 EQ Band 4 B */
+        0x07AD,     /* R1199  - AIF1 DAC2 EQ Band 4 C */
+        0x1103,     /* R1200  - AIF1 DAC2 EQ Band 4 PG */
+        0x0564,     /* R1201  - AIF1 DAC2 EQ Band 5 A */
+        0x0559,     /* R1202  - AIF1 DAC2 EQ Band 5 B */
+        0x4000,     /* R1203  - AIF1 DAC2 EQ Band 5 PG */
+        0x0000,     /* R1204 */
+        0x0000,     /* R1205 */
+        0x0000,     /* R1206 */
+        0x0000,     /* R1207 */
+        0x0000,     /* R1208 */
+        0x0000,     /* R1209 */
+        0x0000,     /* R1210 */
+        0x0000,     /* R1211 */
+        0x0000,     /* R1212 */
+        0x0000,     /* R1213 */
+        0x0000,     /* R1214 */
+        0x0000,     /* R1215 */
+        0x0000,     /* R1216 */
+        0x0000,     /* R1217 */
+        0x0000,     /* R1218 */
+        0x0000,     /* R1219 */
+        0x0000,     /* R1220 */
+        0x0000,     /* R1221 */
+        0x0000,     /* R1222 */
+        0x0000,     /* R1223 */
+        0x0000,     /* R1224 */
+        0x0000,     /* R1225 */
+        0x0000,     /* R1226 */
+        0x0000,     /* R1227 */
+        0x0000,     /* R1228 */
+        0x0000,     /* R1229 */
+        0x0000,     /* R1230 */
+        0x0000,     /* R1231 */
+        0x0000,     /* R1232 */
+        0x0000,     /* R1233 */
+        0x0000,     /* R1234 */
+        0x0000,     /* R1235 */
+        0x0000,     /* R1236 */
+        0x0000,     /* R1237 */
+        0x0000,     /* R1238 */
+        0x0000,     /* R1239 */
+        0x0000,     /* R1240 */
+        0x0000,     /* R1241 */
+        0x0000,     /* R1242 */
+        0x0000,     /* R1243 */
+        0x0000,     /* R1244 */
+        0x0000,     /* R1245 */
+        0x0000,     /* R1246 */
+        0x0000,     /* R1247 */
+        0x0000,     /* R1248 */
+        0x0000,     /* R1249 */
+        0x0000,     /* R1250 */
+        0x0000,     /* R1251 */
+        0x0000,     /* R1252 */
+        0x0000,     /* R1253 */
+        0x0000,     /* R1254 */
+        0x0000,     /* R1255 */
+        0x0000,     /* R1256 */
+        0x0000,     /* R1257 */
+        0x0000,     /* R1258 */
+        0x0000,     /* R1259 */
+        0x0000,     /* R1260 */
+        0x0000,     /* R1261 */
+        0x0000,     /* R1262 */
+        0x0000,     /* R1263 */
+        0x0000,     /* R1264 */
+        0x0000,     /* R1265 */
+        0x0000,     /* R1266 */
+        0x0000,     /* R1267 */
+        0x0000,     /* R1268 */
+        0x0000,     /* R1269 */
+        0x0000,     /* R1270 */
+        0x0000,     /* R1271 */
+        0x0000,     /* R1272 */
+        0x0000,     /* R1273 */
+        0x0000,     /* R1274 */
+        0x0000,     /* R1275 */
+        0x0000,     /* R1276 */
+        0x0000,     /* R1277 */
+        0x0000,     /* R1278 */
+        0x0000,     /* R1279 */
+        0x00C0,     /* R1280  - AIF2 ADC Left Volume */
+        0x00C0,     /* R1281  - AIF2 ADC Right Volume */
+        0x00C0,     /* R1282  - AIF2 DAC Left Volume */
+        0x00C0,     /* R1283  - AIF2 DAC Right Volume */
+        0x0000,     /* R1284 */
+        0x0000,     /* R1285 */
+        0x0000,     /* R1286 */
+        0x0000,     /* R1287 */
+        0x0000,     /* R1288 */
+        0x0000,     /* R1289 */
+        0x0000,     /* R1290 */
+        0x0000,     /* R1291 */
+        0x0000,     /* R1292 */
+        0x0000,     /* R1293 */
+        0x0000,     /* R1294 */
+        0x0000,     /* R1295 */
+        0x0000,     /* R1296  - AIF2 ADC Filters */
+        0x0000,     /* R1297 */
+        0x0000,     /* R1298 */
+        0x0000,     /* R1299 */
+        0x0000,     /* R1300 */
+        0x0000,     /* R1301 */
+        0x0000,     /* R1302 */
+        0x0000,     /* R1303 */
+        0x0000,     /* R1304 */
+        0x0000,     /* R1305 */
+        0x0000,     /* R1306 */
+        0x0000,     /* R1307 */
+        0x0000,     /* R1308 */
+        0x0000,     /* R1309 */
+        0x0000,     /* R1310 */
+        0x0000,     /* R1311 */
+        0x0200,     /* R1312  - AIF2 DAC Filters (1) */
+        0x0010,     /* R1313  - AIF2 DAC Filters (2) */
+        0x0000,     /* R1314 */
+        0x0000,     /* R1315 */
+        0x0000,     /* R1316 */
+        0x0000,     /* R1317 */
+        0x0000,     /* R1318 */
+        0x0000,     /* R1319 */
+        0x0000,     /* R1320 */
+        0x0000,     /* R1321 */
+        0x0000,     /* R1322 */
+        0x0000,     /* R1323 */
+        0x0000,     /* R1324 */
+        0x0000,     /* R1325 */
+        0x0000,     /* R1326 */
+        0x0000,     /* R1327 */
+        0x0000,     /* R1328 */
+        0x0000,     /* R1329 */
+        0x0000,     /* R1330 */
+        0x0000,     /* R1331 */
+        0x0000,     /* R1332 */
+        0x0000,     /* R1333 */
+        0x0000,     /* R1334 */
+        0x0000,     /* R1335 */
+        0x0000,     /* R1336 */
+        0x0000,     /* R1337 */
+        0x0000,     /* R1338 */
+        0x0000,     /* R1339 */
+        0x0000,     /* R1340 */
+        0x0000,     /* R1341 */
+        0x0000,     /* R1342 */
+        0x0000,     /* R1343 */
+        0x0098,     /* R1344  - AIF2 DRC (1) */
+        0x0845,     /* R1345  - AIF2 DRC (2) */
+        0x0000,     /* R1346  - AIF2 DRC (3) */
+        0x0000,     /* R1347  - AIF2 DRC (4) */
+        0x0000,     /* R1348  - AIF2 DRC (5) */
+        0x0000,     /* R1349 */
+        0x0000,     /* R1350 */
+        0x0000,     /* R1351 */
+        0x0000,     /* R1352 */
+        0x0000,     /* R1353 */
+        0x0000,     /* R1354 */
+        0x0000,     /* R1355 */
+        0x0000,     /* R1356 */
+        0x0000,     /* R1357 */
+        0x0000,     /* R1358 */
+        0x0000,     /* R1359 */
+        0x0000,     /* R1360 */
+        0x0000,     /* R1361 */
+        0x0000,     /* R1362 */
+        0x0000,     /* R1363 */
+        0x0000,     /* R1364 */
+        0x0000,     /* R1365 */
+        0x0000,     /* R1366 */
+        0x0000,     /* R1367 */
+        0x0000,     /* R1368 */
+        0x0000,     /* R1369 */
+        0x0000,     /* R1370 */
+        0x0000,     /* R1371 */
+        0x0000,     /* R1372 */
+        0x0000,     /* R1373 */
+        0x0000,     /* R1374 */
+        0x0000,     /* R1375 */
+        0x0000,     /* R1376 */
+        0x0000,     /* R1377 */
+        0x0000,     /* R1378 */
+        0x0000,     /* R1379 */
+        0x0000,     /* R1380 */
+        0x0000,     /* R1381 */
+        0x0000,     /* R1382 */
+        0x0000,     /* R1383 */
+        0x0000,     /* R1384 */
+        0x0000,     /* R1385 */
+        0x0000,     /* R1386 */
+        0x0000,     /* R1387 */
+        0x0000,     /* R1388 */
+        0x0000,     /* R1389 */
+        0x0000,     /* R1390 */
+        0x0000,     /* R1391 */
+        0x0000,     /* R1392 */
+        0x0000,     /* R1393 */
+        0x0000,     /* R1394 */
+        0x0000,     /* R1395 */
+        0x0000,     /* R1396 */
+        0x0000,     /* R1397 */
+        0x0000,     /* R1398 */
+        0x0000,     /* R1399 */
+        0x0000,     /* R1400 */
+        0x0000,     /* R1401 */
+        0x0000,     /* R1402 */
+        0x0000,     /* R1403 */
+        0x0000,     /* R1404 */
+        0x0000,     /* R1405 */
+        0x0000,     /* R1406 */
+        0x0000,     /* R1407 */
+        0x6318,     /* R1408  - AIF2 EQ Gains (1) */
+        0x6300,     /* R1409  - AIF2 EQ Gains (2) */
+        0x0FCA,     /* R1410  - AIF2 EQ Band 1 A */
+        0x0400,     /* R1411  - AIF2 EQ Band 1 B */
+        0x00D8,     /* R1412  - AIF2 EQ Band 1 PG */
+        0x1EB5,     /* R1413  - AIF2 EQ Band 2 A */
+        0xF145,     /* R1414  - AIF2 EQ Band 2 B */
+        0x0B75,     /* R1415  - AIF2 EQ Band 2 C */
+        0x01C5,     /* R1416  - AIF2 EQ Band 2 PG */
+        0x1C58,     /* R1417  - AIF2 EQ Band 3 A */
+        0xF373,     /* R1418  - AIF2 EQ Band 3 B */
+        0x0A54,     /* R1419  - AIF2 EQ Band 3 C */
+        0x0558,     /* R1420  - AIF2 EQ Band 3 PG */
+        0x168E,     /* R1421  - AIF2 EQ Band 4 A */
+        0xF829,     /* R1422  - AIF2 EQ Band 4 B */
+        0x07AD,     /* R1423  - AIF2 EQ Band 4 C */
+        0x1103,     /* R1424  - AIF2 EQ Band 4 PG */
+        0x0564,     /* R1425  - AIF2 EQ Band 5 A */
+        0x0559,     /* R1426  - AIF2 EQ Band 5 B */
+        0x4000,     /* R1427  - AIF2 EQ Band 5 PG */
+        0x0000,     /* R1428 */
+        0x0000,     /* R1429 */
+        0x0000,     /* R1430 */
+        0x0000,     /* R1431 */
+        0x0000,     /* R1432 */
+        0x0000,     /* R1433 */
+        0x0000,     /* R1434 */
+        0x0000,     /* R1435 */
+        0x0000,     /* R1436 */
+        0x0000,     /* R1437 */
+        0x0000,     /* R1438 */
+        0x0000,     /* R1439 */
+        0x0000,     /* R1440 */
+        0x0000,     /* R1441 */
+        0x0000,     /* R1442 */
+        0x0000,     /* R1443 */
+        0x0000,     /* R1444 */
+        0x0000,     /* R1445 */
+        0x0000,     /* R1446 */
+        0x0000,     /* R1447 */
+        0x0000,     /* R1448 */
+        0x0000,     /* R1449 */
+        0x0000,     /* R1450 */
+        0x0000,     /* R1451 */
+        0x0000,     /* R1452 */
+        0x0000,     /* R1453 */
+        0x0000,     /* R1454 */
+        0x0000,     /* R1455 */
+        0x0000,     /* R1456 */
+        0x0000,     /* R1457 */
+        0x0000,     /* R1458 */
+        0x0000,     /* R1459 */
+        0x0000,     /* R1460 */
+        0x0000,     /* R1461 */
+        0x0000,     /* R1462 */
+        0x0000,     /* R1463 */
+        0x0000,     /* R1464 */
+        0x0000,     /* R1465 */
+        0x0000,     /* R1466 */
+        0x0000,     /* R1467 */
+        0x0000,     /* R1468 */
+        0x0000,     /* R1469 */
+        0x0000,     /* R1470 */
+        0x0000,     /* R1471 */
+        0x0000,     /* R1472 */
+        0x0000,     /* R1473 */
+        0x0000,     /* R1474 */
+        0x0000,     /* R1475 */
+        0x0000,     /* R1476 */
+        0x0000,     /* R1477 */
+        0x0000,     /* R1478 */
+        0x0000,     /* R1479 */
+        0x0000,     /* R1480 */
+        0x0000,     /* R1481 */
+        0x0000,     /* R1482 */
+        0x0000,     /* R1483 */
+        0x0000,     /* R1484 */
+        0x0000,     /* R1485 */
+        0x0000,     /* R1486 */
+        0x0000,     /* R1487 */
+        0x0000,     /* R1488 */
+        0x0000,     /* R1489 */
+        0x0000,     /* R1490 */
+        0x0000,     /* R1491 */
+        0x0000,     /* R1492 */
+        0x0000,     /* R1493 */
+        0x0000,     /* R1494 */
+        0x0000,     /* R1495 */
+        0x0000,     /* R1496 */
+        0x0000,     /* R1497 */
+        0x0000,     /* R1498 */
+        0x0000,     /* R1499 */
+        0x0000,     /* R1500 */
+        0x0000,     /* R1501 */
+        0x0000,     /* R1502 */
+        0x0000,     /* R1503 */
+        0x0000,     /* R1504 */
+        0x0000,     /* R1505 */
+        0x0000,     /* R1506 */
+        0x0000,     /* R1507 */
+        0x0000,     /* R1508 */
+        0x0000,     /* R1509 */
+        0x0000,     /* R1510 */
+        0x0000,     /* R1511 */
+        0x0000,     /* R1512 */
+        0x0000,     /* R1513 */
+        0x0000,     /* R1514 */
+        0x0000,     /* R1515 */
+        0x0000,     /* R1516 */
+        0x0000,     /* R1517 */
+        0x0000,     /* R1518 */
+        0x0000,     /* R1519 */
+        0x0000,     /* R1520 */
+        0x0000,     /* R1521 */
+        0x0000,     /* R1522 */
+        0x0000,     /* R1523 */
+        0x0000,     /* R1524 */
+        0x0000,     /* R1525 */
+        0x0000,     /* R1526 */
+        0x0000,     /* R1527 */
+        0x0000,     /* R1528 */
+        0x0000,     /* R1529 */
+        0x0000,     /* R1530 */
+        0x0000,     /* R1531 */
+        0x0000,     /* R1532 */
+        0x0000,     /* R1533 */
+        0x0000,     /* R1534 */
+        0x0000,     /* R1535 */
+        0x0000,     /* R1536  - DAC1 Mixer Volumes */
+        0x0000,     /* R1537  - DAC1 Left Mixer Routing */
+        0x0000,     /* R1538  - DAC1 Right Mixer Routing */
+        0x0000,     /* R1539  - DAC2 Mixer Volumes */
+        0x0000,     /* R1540  - DAC2 Left Mixer Routing */
+        0x0000,     /* R1541  - DAC2 Right Mixer Routing */
+        0x0000,     /* R1542  - AIF1 ADC1 Left Mixer Routing */
+        0x0000,     /* R1543  - AIF1 ADC1 Right Mixer Routing */
+        0x0000,     /* R1544  - AIF1 ADC2 Left Mixer Routing */
+        0x0000,     /* R1545  - AIF1 ADC2 Right mixer Routing */
+        0x0000,     /* R1546 */
+        0x0000,     /* R1547 */
+        0x0000,     /* R1548 */
+        0x0000,     /* R1549 */
+        0x0000,     /* R1550 */
+        0x0000,     /* R1551 */
+        0x02C0,     /* R1552  - DAC1 Left Volume */
+        0x02C0,     /* R1553  - DAC1 Right Volume */
+        0x02C0,     /* R1554  - DAC2 Left Volume */
+        0x02C0,     /* R1555  - DAC2 Right Volume */
+        0x0000,     /* R1556  - DAC Softmute */
+        0x0000,     /* R1557 */
+        0x0000,     /* R1558 */
+        0x0000,     /* R1559 */
+        0x0000,     /* R1560 */
+        0x0000,     /* R1561 */
+        0x0000,     /* R1562 */
+        0x0000,     /* R1563 */
+        0x0000,     /* R1564 */
+        0x0000,     /* R1565 */
+        0x0000,     /* R1566 */
+        0x0000,     /* R1567 */
+        0x0002,     /* R1568  - Oversampling */
+        0x0000,     /* R1569  - Sidetone */
+};
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 522249d5c2b4..83014a7c2e14 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -18,15 +18,17 @@
 #include <linux/pm.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/regulator/consumer.h>
 #include <linux/slab.h>
 #include <sound/core.h>
+#include <sound/jack.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
+#include <trace/events/asoc.h>
 
 #include <linux/mfd/wm8994/core.h>
 #include <linux/mfd/wm8994/registers.h>
@@ -36,15 +38,6 @@
 #include "wm8994.h"
 #include "wm_hubs.h"
 
-static struct snd_soc_codec *wm8994_codec;
-struct snd_soc_codec_device soc_codec_dev_wm8994;
-
-struct fll_config {
-        int src;
-        int in;
-        int out;
-};
-
 #define WM8994_NUM_DRC 3
 #define WM8994_NUM_EQ  3
 
@@ -60,1624 +53,11 @@ static int wm8994_retune_mobile_base[] = {
         WM8994_AIF2_EQ_GAINS_1,
 };
 
-#define WM8994_REG_CACHE_SIZE  0x621
-
-struct wm8994_micdet {
-        struct snd_soc_jack *jack;
-        int det;
-        int shrt;
-};
-
-/* codec private data */
-struct wm8994_priv {
-        struct wm_hubs_data hubs;
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
-        int sysclk[2];
-        int sysclk_rate[2];
-        int mclk[2];
-        int aifclk[2];
-        struct fll_config fll[2], fll_suspend[2];
-
-        int dac_rates[2];
-        int lrclk_shared[2];
-
-        /* Platform dependant DRC configuration */
-        const char **drc_texts;
-        int drc_cfg[WM8994_NUM_DRC];
-        struct soc_enum drc_enum;
-
-        /* Platform dependant ReTune mobile configuration */
-        int num_retune_mobile_texts;
-        const char **retune_mobile_texts;
-        int retune_mobile_cfg[WM8994_NUM_EQ];
-        struct soc_enum retune_mobile_enum;
-
-        struct wm8994_micdet micdet[2];
-
-        int revision;
-        struct wm8994_pdata *pdata;
-};
-
-static struct {
-        unsigned short  readable;   /* Mask of readable bits */
-        unsigned short  writable;   /* Mask of writable bits */
-        unsigned short  vol;        /* Mask of volatile bits */
-} access_masks[] = {
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R0     - Software Reset */
-        { 0x3B37, 0x3B37, 0x0000 }, /* R1     - Power Management (1) */
-        { 0x6BF0, 0x6BF0, 0x0000 }, /* R2     - Power Management (2) */
-        { 0x3FF0, 0x3FF0, 0x0000 }, /* R3     - Power Management (3) */
-        { 0x3F3F, 0x3F3F, 0x0000 }, /* R4     - Power Management (4) */
-        { 0x3F0F, 0x3F0F, 0x0000 }, /* R5     - Power Management (5) */
-        { 0x003F, 0x003F, 0x0000 }, /* R6     - Power Management (6) */
-        { 0x0000, 0x0000, 0x0000 }, /* R7 */
-        { 0x0000, 0x0000, 0x0000 }, /* R8 */
-        { 0x0000, 0x0000, 0x0000 }, /* R9 */
-        { 0x0000, 0x0000, 0x0000 }, /* R10 */
-        { 0x0000, 0x0000, 0x0000 }, /* R11 */
-        { 0x0000, 0x0000, 0x0000 }, /* R12 */
-        { 0x0000, 0x0000, 0x0000 }, /* R13 */
-        { 0x0000, 0x0000, 0x0000 }, /* R14 */
-        { 0x0000, 0x0000, 0x0000 }, /* R15 */
-        { 0x0000, 0x0000, 0x0000 }, /* R16 */
-        { 0x0000, 0x0000, 0x0000 }, /* R17 */
-        { 0x0000, 0x0000, 0x0000 }, /* R18 */
-        { 0x0000, 0x0000, 0x0000 }, /* R19 */
-        { 0x0000, 0x0000, 0x0000 }, /* R20 */
-        { 0x01C0, 0x01C0, 0x0000 }, /* R21    - Input Mixer (1) */
-        { 0x0000, 0x0000, 0x0000 }, /* R22 */
-        { 0x0000, 0x0000, 0x0000 }, /* R23 */
-        { 0x00DF, 0x01DF, 0x0000 }, /* R24    - Left Line Input 1&2 Volume */
-        { 0x00DF, 0x01DF, 0x0000 }, /* R25    - Left Line Input 3&4 Volume */
-        { 0x00DF, 0x01DF, 0x0000 }, /* R26    - Right Line Input 1&2 Volume */
-        { 0x00DF, 0x01DF, 0x0000 }, /* R27    - Right Line Input 3&4 Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R28    - Left Output Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R29    - Right Output Volume */
-        { 0x0077, 0x0077, 0x0000 }, /* R30    - Line Outputs Volume */
-        { 0x0030, 0x0030, 0x0000 }, /* R31    - HPOUT2 Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R32    - Left OPGA Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R33    - Right OPGA Volume */
-        { 0x007F, 0x007F, 0x0000 }, /* R34    - SPKMIXL Attenuation */
-        { 0x017F, 0x017F, 0x0000 }, /* R35    - SPKMIXR Attenuation */
-        { 0x003F, 0x003F, 0x0000 }, /* R36    - SPKOUT Mixers */
-        { 0x003F, 0x003F, 0x0000 }, /* R37    - ClassD */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R38    - Speaker Volume Left */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R39    - Speaker Volume Right */
-        { 0x00FF, 0x00FF, 0x0000 }, /* R40    - Input Mixer (2) */
-        { 0x01B7, 0x01B7, 0x0000 }, /* R41    - Input Mixer (3) */
-        { 0x01B7, 0x01B7, 0x0000 }, /* R42    - Input Mixer (4) */
-        { 0x01C7, 0x01C7, 0x0000 }, /* R43    - Input Mixer (5) */
-        { 0x01C7, 0x01C7, 0x0000 }, /* R44    - Input Mixer (6) */
-        { 0x01FF, 0x01FF, 0x0000 }, /* R45    - Output Mixer (1) */
-        { 0x01FF, 0x01FF, 0x0000 }, /* R46    - Output Mixer (2) */
-        { 0x0FFF, 0x0FFF, 0x0000 }, /* R47    - Output Mixer (3) */
-        { 0x0FFF, 0x0FFF, 0x0000 }, /* R48    - Output Mixer (4) */
-        { 0x0FFF, 0x0FFF, 0x0000 }, /* R49    - Output Mixer (5) */
-        { 0x0FFF, 0x0FFF, 0x0000 }, /* R50    - Output Mixer (6) */
-        { 0x0038, 0x0038, 0x0000 }, /* R51    - HPOUT2 Mixer */
-        { 0x0077, 0x0077, 0x0000 }, /* R52    - Line Mixer (1) */
-        { 0x0077, 0x0077, 0x0000 }, /* R53    - Line Mixer (2) */
-        { 0x03FF, 0x03FF, 0x0000 }, /* R54    - Speaker Mixer */
-        { 0x00C1, 0x00C1, 0x0000 }, /* R55    - Additional Control */
-        { 0x00F0, 0x00F0, 0x0000 }, /* R56    - AntiPOP (1) */
-        { 0x01EF, 0x01EF, 0x0000 }, /* R57    - AntiPOP (2) */
-        { 0x00FF, 0x00FF, 0x0000 }, /* R58    - MICBIAS */
-        { 0x000F, 0x000F, 0x0000 }, /* R59    - LDO 1 */
-        { 0x0007, 0x0007, 0x0000 }, /* R60    - LDO 2 */
-        { 0x0000, 0x0000, 0x0000 }, /* R61 */
-        { 0x0000, 0x0000, 0x0000 }, /* R62 */
-        { 0x0000, 0x0000, 0x0000 }, /* R63 */
-        { 0x0000, 0x0000, 0x0000 }, /* R64 */
-        { 0x0000, 0x0000, 0x0000 }, /* R65 */
-        { 0x0000, 0x0000, 0x0000 }, /* R66 */
-        { 0x0000, 0x0000, 0x0000 }, /* R67 */
-        { 0x0000, 0x0000, 0x0000 }, /* R68 */
-        { 0x0000, 0x0000, 0x0000 }, /* R69 */
-        { 0x0000, 0x0000, 0x0000 }, /* R70 */
-        { 0x0000, 0x0000, 0x0000 }, /* R71 */
-        { 0x0000, 0x0000, 0x0000 }, /* R72 */
-        { 0x0000, 0x0000, 0x0000 }, /* R73 */
-        { 0x0000, 0x0000, 0x0000 }, /* R74 */
-        { 0x0000, 0x0000, 0x0000 }, /* R75 */
-        { 0x8000, 0x8000, 0x0000 }, /* R76    - Charge Pump (1) */
-        { 0x0000, 0x0000, 0x0000 }, /* R77 */
-        { 0x0000, 0x0000, 0x0000 }, /* R78 */
-        { 0x0000, 0x0000, 0x0000 }, /* R79 */
-        { 0x0000, 0x0000, 0x0000 }, /* R80 */
-        { 0x0301, 0x0301, 0x0000 }, /* R81    - Class W (1) */
-        { 0x0000, 0x0000, 0x0000 }, /* R82 */
-        { 0x0000, 0x0000, 0x0000 }, /* R83 */
-        { 0x333F, 0x333F, 0x0000 }, /* R84    - DC Servo (1) */
-        { 0x0FEF, 0x0FEF, 0x0000 }, /* R85    - DC Servo (2) */
-        { 0x0000, 0x0000, 0x0000 }, /* R86 */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R87    - DC Servo (4) */
-        { 0x0333, 0x0000, 0x0000 }, /* R88    - DC Servo Readback */
-        { 0x0000, 0x0000, 0x0000 }, /* R89 */
-        { 0x0000, 0x0000, 0x0000 }, /* R90 */
-        { 0x0000, 0x0000, 0x0000 }, /* R91 */
-        { 0x0000, 0x0000, 0x0000 }, /* R92 */
-        { 0x0000, 0x0000, 0x0000 }, /* R93 */
-        { 0x0000, 0x0000, 0x0000 }, /* R94 */
-        { 0x0000, 0x0000, 0x0000 }, /* R95 */
-        { 0x00EE, 0x00EE, 0x0000 }, /* R96    - Analogue HP (1) */
-        { 0x0000, 0x0000, 0x0000 }, /* R97 */
-        { 0x0000, 0x0000, 0x0000 }, /* R98 */
-        { 0x0000, 0x0000, 0x0000 }, /* R99 */
-        { 0x0000, 0x0000, 0x0000 }, /* R100 */
-        { 0x0000, 0x0000, 0x0000 }, /* R101 */
-        { 0x0000, 0x0000, 0x0000 }, /* R102 */
-        { 0x0000, 0x0000, 0x0000 }, /* R103 */
-        { 0x0000, 0x0000, 0x0000 }, /* R104 */
-        { 0x0000, 0x0000, 0x0000 }, /* R105 */
-        { 0x0000, 0x0000, 0x0000 }, /* R106 */
-        { 0x0000, 0x0000, 0x0000 }, /* R107 */
-        { 0x0000, 0x0000, 0x0000 }, /* R108 */
-        { 0x0000, 0x0000, 0x0000 }, /* R109 */
-        { 0x0000, 0x0000, 0x0000 }, /* R110 */
-        { 0x0000, 0x0000, 0x0000 }, /* R111 */
-        { 0x0000, 0x0000, 0x0000 }, /* R112 */
-        { 0x0000, 0x0000, 0x0000 }, /* R113 */
-        { 0x0000, 0x0000, 0x0000 }, /* R114 */
-        { 0x0000, 0x0000, 0x0000 }, /* R115 */
-        { 0x0000, 0x0000, 0x0000 }, /* R116 */
-        { 0x0000, 0x0000, 0x0000 }, /* R117 */
-        { 0x0000, 0x0000, 0x0000 }, /* R118 */
-        { 0x0000, 0x0000, 0x0000 }, /* R119 */
-        { 0x0000, 0x0000, 0x0000 }, /* R120 */
-        { 0x0000, 0x0000, 0x0000 }, /* R121 */
-        { 0x0000, 0x0000, 0x0000 }, /* R122 */
-        { 0x0000, 0x0000, 0x0000 }, /* R123 */
-        { 0x0000, 0x0000, 0x0000 }, /* R124 */
-        { 0x0000, 0x0000, 0x0000 }, /* R125 */
-        { 0x0000, 0x0000, 0x0000 }, /* R126 */
-        { 0x0000, 0x0000, 0x0000 }, /* R127 */
-        { 0x0000, 0x0000, 0x0000 }, /* R128 */
-        { 0x0000, 0x0000, 0x0000 }, /* R129 */
-        { 0x0000, 0x0000, 0x0000 }, /* R130 */
-        { 0x0000, 0x0000, 0x0000 }, /* R131 */
-        { 0x0000, 0x0000, 0x0000 }, /* R132 */
-        { 0x0000, 0x0000, 0x0000 }, /* R133 */
-        { 0x0000, 0x0000, 0x0000 }, /* R134 */
-        { 0x0000, 0x0000, 0x0000 }, /* R135 */
-        { 0x0000, 0x0000, 0x0000 }, /* R136 */
-        { 0x0000, 0x0000, 0x0000 }, /* R137 */
-        { 0x0000, 0x0000, 0x0000 }, /* R138 */
-        { 0x0000, 0x0000, 0x0000 }, /* R139 */
-        { 0x0000, 0x0000, 0x0000 }, /* R140 */
-        { 0x0000, 0x0000, 0x0000 }, /* R141 */
-        { 0x0000, 0x0000, 0x0000 }, /* R142 */
-        { 0x0000, 0x0000, 0x0000 }, /* R143 */
-        { 0x0000, 0x0000, 0x0000 }, /* R144 */
-        { 0x0000, 0x0000, 0x0000 }, /* R145 */
-        { 0x0000, 0x0000, 0x0000 }, /* R146 */
-        { 0x0000, 0x0000, 0x0000 }, /* R147 */
-        { 0x0000, 0x0000, 0x0000 }, /* R148 */
-        { 0x0000, 0x0000, 0x0000 }, /* R149 */
-        { 0x0000, 0x0000, 0x0000 }, /* R150 */
-        { 0x0000, 0x0000, 0x0000 }, /* R151 */
-        { 0x0000, 0x0000, 0x0000 }, /* R152 */
-        { 0x0000, 0x0000, 0x0000 }, /* R153 */
-        { 0x0000, 0x0000, 0x0000 }, /* R154 */
-        { 0x0000, 0x0000, 0x0000 }, /* R155 */
-        { 0x0000, 0x0000, 0x0000 }, /* R156 */
-        { 0x0000, 0x0000, 0x0000 }, /* R157 */
-        { 0x0000, 0x0000, 0x0000 }, /* R158 */
-        { 0x0000, 0x0000, 0x0000 }, /* R159 */
-        { 0x0000, 0x0000, 0x0000 }, /* R160 */
-        { 0x0000, 0x0000, 0x0000 }, /* R161 */
-        { 0x0000, 0x0000, 0x0000 }, /* R162 */
-        { 0x0000, 0x0000, 0x0000 }, /* R163 */
-        { 0x0000, 0x0000, 0x0000 }, /* R164 */
-        { 0x0000, 0x0000, 0x0000 }, /* R165 */
-        { 0x0000, 0x0000, 0x0000 }, /* R166 */
-        { 0x0000, 0x0000, 0x0000 }, /* R167 */
-        { 0x0000, 0x0000, 0x0000 }, /* R168 */
-        { 0x0000, 0x0000, 0x0000 }, /* R169 */
-        { 0x0000, 0x0000, 0x0000 }, /* R170 */
-        { 0x0000, 0x0000, 0x0000 }, /* R171 */
-        { 0x0000, 0x0000, 0x0000 }, /* R172 */
-        { 0x0000, 0x0000, 0x0000 }, /* R173 */
-        { 0x0000, 0x0000, 0x0000 }, /* R174 */
-        { 0x0000, 0x0000, 0x0000 }, /* R175 */
-        { 0x0000, 0x0000, 0x0000 }, /* R176 */
-        { 0x0000, 0x0000, 0x0000 }, /* R177 */
-        { 0x0000, 0x0000, 0x0000 }, /* R178 */
-        { 0x0000, 0x0000, 0x0000 }, /* R179 */
-        { 0x0000, 0x0000, 0x0000 }, /* R180 */
-        { 0x0000, 0x0000, 0x0000 }, /* R181 */
-        { 0x0000, 0x0000, 0x0000 }, /* R182 */
-        { 0x0000, 0x0000, 0x0000 }, /* R183 */
-        { 0x0000, 0x0000, 0x0000 }, /* R184 */
-        { 0x0000, 0x0000, 0x0000 }, /* R185 */
-        { 0x0000, 0x0000, 0x0000 }, /* R186 */
-        { 0x0000, 0x0000, 0x0000 }, /* R187 */
-        { 0x0000, 0x0000, 0x0000 }, /* R188 */
-        { 0x0000, 0x0000, 0x0000 }, /* R189 */
-        { 0x0000, 0x0000, 0x0000 }, /* R190 */
-        { 0x0000, 0x0000, 0x0000 }, /* R191 */
-        { 0x0000, 0x0000, 0x0000 }, /* R192 */
-        { 0x0000, 0x0000, 0x0000 }, /* R193 */
-        { 0x0000, 0x0000, 0x0000 }, /* R194 */
-        { 0x0000, 0x0000, 0x0000 }, /* R195 */
-        { 0x0000, 0x0000, 0x0000 }, /* R196 */
-        { 0x0000, 0x0000, 0x0000 }, /* R197 */
-        { 0x0000, 0x0000, 0x0000 }, /* R198 */
-        { 0x0000, 0x0000, 0x0000 }, /* R199 */
-        { 0x0000, 0x0000, 0x0000 }, /* R200 */
-        { 0x0000, 0x0000, 0x0000 }, /* R201 */
-        { 0x0000, 0x0000, 0x0000 }, /* R202 */
-        { 0x0000, 0x0000, 0x0000 }, /* R203 */
-        { 0x0000, 0x0000, 0x0000 }, /* R204 */
-        { 0x0000, 0x0000, 0x0000 }, /* R205 */
-        { 0x0000, 0x0000, 0x0000 }, /* R206 */
-        { 0x0000, 0x0000, 0x0000 }, /* R207 */
-        { 0x0000, 0x0000, 0x0000 }, /* R208 */
-        { 0x0000, 0x0000, 0x0000 }, /* R209 */
-        { 0x0000, 0x0000, 0x0000 }, /* R210 */
-        { 0x0000, 0x0000, 0x0000 }, /* R211 */
-        { 0x0000, 0x0000, 0x0000 }, /* R212 */
-        { 0x0000, 0x0000, 0x0000 }, /* R213 */
-        { 0x0000, 0x0000, 0x0000 }, /* R214 */
-        { 0x0000, 0x0000, 0x0000 }, /* R215 */
-        { 0x0000, 0x0000, 0x0000 }, /* R216 */
-        { 0x0000, 0x0000, 0x0000 }, /* R217 */
-        { 0x0000, 0x0000, 0x0000 }, /* R218 */
-        { 0x0000, 0x0000, 0x0000 }, /* R219 */
-        { 0x0000, 0x0000, 0x0000 }, /* R220 */
-        { 0x0000, 0x0000, 0x0000 }, /* R221 */
-        { 0x0000, 0x0000, 0x0000 }, /* R222 */
-        { 0x0000, 0x0000, 0x0000 }, /* R223 */
-        { 0x0000, 0x0000, 0x0000 }, /* R224 */
-        { 0x0000, 0x0000, 0x0000 }, /* R225 */
-        { 0x0000, 0x0000, 0x0000 }, /* R226 */
-        { 0x0000, 0x0000, 0x0000 }, /* R227 */
-        { 0x0000, 0x0000, 0x0000 }, /* R228 */
-        { 0x0000, 0x0000, 0x0000 }, /* R229 */
-        { 0x0000, 0x0000, 0x0000 }, /* R230 */
-        { 0x0000, 0x0000, 0x0000 }, /* R231 */
-        { 0x0000, 0x0000, 0x0000 }, /* R232 */
-        { 0x0000, 0x0000, 0x0000 }, /* R233 */
-        { 0x0000, 0x0000, 0x0000 }, /* R234 */
-        { 0x0000, 0x0000, 0x0000 }, /* R235 */
-        { 0x0000, 0x0000, 0x0000 }, /* R236 */
-        { 0x0000, 0x0000, 0x0000 }, /* R237 */
-        { 0x0000, 0x0000, 0x0000 }, /* R238 */
-        { 0x0000, 0x0000, 0x0000 }, /* R239 */
-        { 0x0000, 0x0000, 0x0000 }, /* R240 */
-        { 0x0000, 0x0000, 0x0000 }, /* R241 */
-        { 0x0000, 0x0000, 0x0000 }, /* R242 */
-        { 0x0000, 0x0000, 0x0000 }, /* R243 */
-        { 0x0000, 0x0000, 0x0000 }, /* R244 */
-        { 0x0000, 0x0000, 0x0000 }, /* R245 */
-        { 0x0000, 0x0000, 0x0000 }, /* R246 */
-        { 0x0000, 0x0000, 0x0000 }, /* R247 */
-        { 0x0000, 0x0000, 0x0000 }, /* R248 */
-        { 0x0000, 0x0000, 0x0000 }, /* R249 */
-        { 0x0000, 0x0000, 0x0000 }, /* R250 */
-        { 0x0000, 0x0000, 0x0000 }, /* R251 */
-        { 0x0000, 0x0000, 0x0000 }, /* R252 */
-        { 0x0000, 0x0000, 0x0000 }, /* R253 */
-        { 0x0000, 0x0000, 0x0000 }, /* R254 */
-        { 0x0000, 0x0000, 0x0000 }, /* R255 */
-        { 0x000F, 0x0000, 0x0000 }, /* R256   - Chip Revision */
-        { 0x0074, 0x0074, 0x0000 }, /* R257   - Control Interface */
-        { 0x0000, 0x0000, 0x0000 }, /* R258 */
-        { 0x0000, 0x0000, 0x0000 }, /* R259 */
-        { 0x0000, 0x0000, 0x0000 }, /* R260 */
-        { 0x0000, 0x0000, 0x0000 }, /* R261 */
-        { 0x0000, 0x0000, 0x0000 }, /* R262 */
-        { 0x0000, 0x0000, 0x0000 }, /* R263 */
-        { 0x0000, 0x0000, 0x0000 }, /* R264 */
-        { 0x0000, 0x0000, 0x0000 }, /* R265 */
-        { 0x0000, 0x0000, 0x0000 }, /* R266 */
-        { 0x0000, 0x0000, 0x0000 }, /* R267 */
-        { 0x0000, 0x0000, 0x0000 }, /* R268 */
-        { 0x0000, 0x0000, 0x0000 }, /* R269 */
-        { 0x0000, 0x0000, 0x0000 }, /* R270 */
-        { 0x0000, 0x0000, 0x0000 }, /* R271 */
-        { 0x807F, 0x837F, 0x0000 }, /* R272   - Write Sequencer Ctrl (1) */
-        { 0x017F, 0x0000, 0x0000 }, /* R273   - Write Sequencer Ctrl (2) */
-        { 0x0000, 0x0000, 0x0000 }, /* R274 */
-        { 0x0000, 0x0000, 0x0000 }, /* R275 */
-        { 0x0000, 0x0000, 0x0000 }, /* R276 */
-        { 0x0000, 0x0000, 0x0000 }, /* R277 */
-        { 0x0000, 0x0000, 0x0000 }, /* R278 */
-        { 0x0000, 0x0000, 0x0000 }, /* R279 */
-        { 0x0000, 0x0000, 0x0000 }, /* R280 */
-        { 0x0000, 0x0000, 0x0000 }, /* R281 */
-        { 0x0000, 0x0000, 0x0000 }, /* R282 */
-        { 0x0000, 0x0000, 0x0000 }, /* R283 */
-        { 0x0000, 0x0000, 0x0000 }, /* R284 */
-        { 0x0000, 0x0000, 0x0000 }, /* R285 */
-        { 0x0000, 0x0000, 0x0000 }, /* R286 */
-        { 0x0000, 0x0000, 0x0000 }, /* R287 */
-        { 0x0000, 0x0000, 0x0000 }, /* R288 */
-        { 0x0000, 0x0000, 0x0000 }, /* R289 */
-        { 0x0000, 0x0000, 0x0000 }, /* R290 */
-        { 0x0000, 0x0000, 0x0000 }, /* R291 */
-        { 0x0000, 0x0000, 0x0000 }, /* R292 */
-        { 0x0000, 0x0000, 0x0000 }, /* R293 */
-        { 0x0000, 0x0000, 0x0000 }, /* R294 */
-        { 0x0000, 0x0000, 0x0000 }, /* R295 */
-        { 0x0000, 0x0000, 0x0000 }, /* R296 */
-        { 0x0000, 0x0000, 0x0000 }, /* R297 */
-        { 0x0000, 0x0000, 0x0000 }, /* R298 */
-        { 0x0000, 0x0000, 0x0000 }, /* R299 */
-        { 0x0000, 0x0000, 0x0000 }, /* R300 */
-        { 0x0000, 0x0000, 0x0000 }, /* R301 */
-        { 0x0000, 0x0000, 0x0000 }, /* R302 */
-        { 0x0000, 0x0000, 0x0000 }, /* R303 */
-        { 0x0000, 0x0000, 0x0000 }, /* R304 */
-        { 0x0000, 0x0000, 0x0000 }, /* R305 */
-        { 0x0000, 0x0000, 0x0000 }, /* R306 */
-        { 0x0000, 0x0000, 0x0000 }, /* R307 */
-        { 0x0000, 0x0000, 0x0000 }, /* R308 */
-        { 0x0000, 0x0000, 0x0000 }, /* R309 */
-        { 0x0000, 0x0000, 0x0000 }, /* R310 */
-        { 0x0000, 0x0000, 0x0000 }, /* R311 */
-        { 0x0000, 0x0000, 0x0000 }, /* R312 */
-        { 0x0000, 0x0000, 0x0000 }, /* R313 */
-        { 0x0000, 0x0000, 0x0000 }, /* R314 */
-        { 0x0000, 0x0000, 0x0000 }, /* R315 */
-        { 0x0000, 0x0000, 0x0000 }, /* R316 */
-        { 0x0000, 0x0000, 0x0000 }, /* R317 */
-        { 0x0000, 0x0000, 0x0000 }, /* R318 */
-        { 0x0000, 0x0000, 0x0000 }, /* R319 */
-        { 0x0000, 0x0000, 0x0000 }, /* R320 */
-        { 0x0000, 0x0000, 0x0000 }, /* R321 */
-        { 0x0000, 0x0000, 0x0000 }, /* R322 */
-        { 0x0000, 0x0000, 0x0000 }, /* R323 */
-        { 0x0000, 0x0000, 0x0000 }, /* R324 */
-        { 0x0000, 0x0000, 0x0000 }, /* R325 */
-        { 0x0000, 0x0000, 0x0000 }, /* R326 */
-        { 0x0000, 0x0000, 0x0000 }, /* R327 */
-        { 0x0000, 0x0000, 0x0000 }, /* R328 */
-        { 0x0000, 0x0000, 0x0000 }, /* R329 */
-        { 0x0000, 0x0000, 0x0000 }, /* R330 */
-        { 0x0000, 0x0000, 0x0000 }, /* R331 */
-        { 0x0000, 0x0000, 0x0000 }, /* R332 */
-        { 0x0000, 0x0000, 0x0000 }, /* R333 */
-        { 0x0000, 0x0000, 0x0000 }, /* R334 */
-        { 0x0000, 0x0000, 0x0000 }, /* R335 */
-        { 0x0000, 0x0000, 0x0000 }, /* R336 */
-        { 0x0000, 0x0000, 0x0000 }, /* R337 */
-        { 0x0000, 0x0000, 0x0000 }, /* R338 */
-        { 0x0000, 0x0000, 0x0000 }, /* R339 */
-        { 0x0000, 0x0000, 0x0000 }, /* R340 */
-        { 0x0000, 0x0000, 0x0000 }, /* R341 */
-        { 0x0000, 0x0000, 0x0000 }, /* R342 */
-        { 0x0000, 0x0000, 0x0000 }, /* R343 */
-        { 0x0000, 0x0000, 0x0000 }, /* R344 */
-        { 0x0000, 0x0000, 0x0000 }, /* R345 */
-        { 0x0000, 0x0000, 0x0000 }, /* R346 */
-        { 0x0000, 0x0000, 0x0000 }, /* R347 */
-        { 0x0000, 0x0000, 0x0000 }, /* R348 */
-        { 0x0000, 0x0000, 0x0000 }, /* R349 */
-        { 0x0000, 0x0000, 0x0000 }, /* R350 */
-        { 0x0000, 0x0000, 0x0000 }, /* R351 */
-        { 0x0000, 0x0000, 0x0000 }, /* R352 */
-        { 0x0000, 0x0000, 0x0000 }, /* R353 */
-        { 0x0000, 0x0000, 0x0000 }, /* R354 */
-        { 0x0000, 0x0000, 0x0000 }, /* R355 */
-        { 0x0000, 0x0000, 0x0000 }, /* R356 */
-        { 0x0000, 0x0000, 0x0000 }, /* R357 */
-        { 0x0000, 0x0000, 0x0000 }, /* R358 */
-        { 0x0000, 0x0000, 0x0000 }, /* R359 */
-        { 0x0000, 0x0000, 0x0000 }, /* R360 */
-        { 0x0000, 0x0000, 0x0000 }, /* R361 */
-        { 0x0000, 0x0000, 0x0000 }, /* R362 */
-        { 0x0000, 0x0000, 0x0000 }, /* R363 */
-        { 0x0000, 0x0000, 0x0000 }, /* R364 */
-        { 0x0000, 0x0000, 0x0000 }, /* R365 */
-        { 0x0000, 0x0000, 0x0000 }, /* R366 */
-        { 0x0000, 0x0000, 0x0000 }, /* R367 */
-        { 0x0000, 0x0000, 0x0000 }, /* R368 */
-        { 0x0000, 0x0000, 0x0000 }, /* R369 */
-        { 0x0000, 0x0000, 0x0000 }, /* R370 */
-        { 0x0000, 0x0000, 0x0000 }, /* R371 */
-        { 0x0000, 0x0000, 0x0000 }, /* R372 */
-        { 0x0000, 0x0000, 0x0000 }, /* R373 */
-        { 0x0000, 0x0000, 0x0000 }, /* R374 */
-        { 0x0000, 0x0000, 0x0000 }, /* R375 */
-        { 0x0000, 0x0000, 0x0000 }, /* R376 */
-        { 0x0000, 0x0000, 0x0000 }, /* R377 */
-        { 0x0000, 0x0000, 0x0000 }, /* R378 */
-        { 0x0000, 0x0000, 0x0000 }, /* R379 */
-        { 0x0000, 0x0000, 0x0000 }, /* R380 */
-        { 0x0000, 0x0000, 0x0000 }, /* R381 */
-        { 0x0000, 0x0000, 0x0000 }, /* R382 */
-        { 0x0000, 0x0000, 0x0000 }, /* R383 */
-        { 0x0000, 0x0000, 0x0000 }, /* R384 */
-        { 0x0000, 0x0000, 0x0000 }, /* R385 */
-        { 0x0000, 0x0000, 0x0000 }, /* R386 */
-        { 0x0000, 0x0000, 0x0000 }, /* R387 */
-        { 0x0000, 0x0000, 0x0000 }, /* R388 */
-        { 0x0000, 0x0000, 0x0000 }, /* R389 */
-        { 0x0000, 0x0000, 0x0000 }, /* R390 */
-        { 0x0000, 0x0000, 0x0000 }, /* R391 */
-        { 0x0000, 0x0000, 0x0000 }, /* R392 */
-        { 0x0000, 0x0000, 0x0000 }, /* R393 */
-        { 0x0000, 0x0000, 0x0000 }, /* R394 */
-        { 0x0000, 0x0000, 0x0000 }, /* R395 */
-        { 0x0000, 0x0000, 0x0000 }, /* R396 */
-        { 0x0000, 0x0000, 0x0000 }, /* R397 */
-        { 0x0000, 0x0000, 0x0000 }, /* R398 */
-        { 0x0000, 0x0000, 0x0000 }, /* R399 */
-        { 0x0000, 0x0000, 0x0000 }, /* R400 */
-        { 0x0000, 0x0000, 0x0000 }, /* R401 */
-        { 0x0000, 0x0000, 0x0000 }, /* R402 */
-        { 0x0000, 0x0000, 0x0000 }, /* R403 */
-        { 0x0000, 0x0000, 0x0000 }, /* R404 */
-        { 0x0000, 0x0000, 0x0000 }, /* R405 */
-        { 0x0000, 0x0000, 0x0000 }, /* R406 */
-        { 0x0000, 0x0000, 0x0000 }, /* R407 */
-        { 0x0000, 0x0000, 0x0000 }, /* R408 */
-        { 0x0000, 0x0000, 0x0000 }, /* R409 */
-        { 0x0000, 0x0000, 0x0000 }, /* R410 */
-        { 0x0000, 0x0000, 0x0000 }, /* R411 */
-        { 0x0000, 0x0000, 0x0000 }, /* R412 */
-        { 0x0000, 0x0000, 0x0000 }, /* R413 */
-        { 0x0000, 0x0000, 0x0000 }, /* R414 */
-        { 0x0000, 0x0000, 0x0000 }, /* R415 */
-        { 0x0000, 0x0000, 0x0000 }, /* R416 */
-        { 0x0000, 0x0000, 0x0000 }, /* R417 */
-        { 0x0000, 0x0000, 0x0000 }, /* R418 */
-        { 0x0000, 0x0000, 0x0000 }, /* R419 */
-        { 0x0000, 0x0000, 0x0000 }, /* R420 */
-        { 0x0000, 0x0000, 0x0000 }, /* R421 */
-        { 0x0000, 0x0000, 0x0000 }, /* R422 */
-        { 0x0000, 0x0000, 0x0000 }, /* R423 */
-        { 0x0000, 0x0000, 0x0000 }, /* R424 */
-        { 0x0000, 0x0000, 0x0000 }, /* R425 */
-        { 0x0000, 0x0000, 0x0000 }, /* R426 */
-        { 0x0000, 0x0000, 0x0000 }, /* R427 */
-        { 0x0000, 0x0000, 0x0000 }, /* R428 */
-        { 0x0000, 0x0000, 0x0000 }, /* R429 */
-        { 0x0000, 0x0000, 0x0000 }, /* R430 */
-        { 0x0000, 0x0000, 0x0000 }, /* R431 */
-        { 0x0000, 0x0000, 0x0000 }, /* R432 */
-        { 0x0000, 0x0000, 0x0000 }, /* R433 */
-        { 0x0000, 0x0000, 0x0000 }, /* R434 */
-        { 0x0000, 0x0000, 0x0000 }, /* R435 */
-        { 0x0000, 0x0000, 0x0000 }, /* R436 */
-        { 0x0000, 0x0000, 0x0000 }, /* R437 */
-        { 0x0000, 0x0000, 0x0000 }, /* R438 */
-        { 0x0000, 0x0000, 0x0000 }, /* R439 */
-        { 0x0000, 0x0000, 0x0000 }, /* R440 */
-        { 0x0000, 0x0000, 0x0000 }, /* R441 */
-        { 0x0000, 0x0000, 0x0000 }, /* R442 */
-        { 0x0000, 0x0000, 0x0000 }, /* R443 */
-        { 0x0000, 0x0000, 0x0000 }, /* R444 */
-        { 0x0000, 0x0000, 0x0000 }, /* R445 */
-        { 0x0000, 0x0000, 0x0000 }, /* R446 */
-        { 0x0000, 0x0000, 0x0000 }, /* R447 */
-        { 0x0000, 0x0000, 0x0000 }, /* R448 */
-        { 0x0000, 0x0000, 0x0000 }, /* R449 */
-        { 0x0000, 0x0000, 0x0000 }, /* R450 */
-        { 0x0000, 0x0000, 0x0000 }, /* R451 */
-        { 0x0000, 0x0000, 0x0000 }, /* R452 */
-        { 0x0000, 0x0000, 0x0000 }, /* R453 */
-        { 0x0000, 0x0000, 0x0000 }, /* R454 */
-        { 0x0000, 0x0000, 0x0000 }, /* R455 */
-        { 0x0000, 0x0000, 0x0000 }, /* R456 */
-        { 0x0000, 0x0000, 0x0000 }, /* R457 */
-        { 0x0000, 0x0000, 0x0000 }, /* R458 */
-        { 0x0000, 0x0000, 0x0000 }, /* R459 */
-        { 0x0000, 0x0000, 0x0000 }, /* R460 */
-        { 0x0000, 0x0000, 0x0000 }, /* R461 */
-        { 0x0000, 0x0000, 0x0000 }, /* R462 */
-        { 0x0000, 0x0000, 0x0000 }, /* R463 */
-        { 0x0000, 0x0000, 0x0000 }, /* R464 */
-        { 0x0000, 0x0000, 0x0000 }, /* R465 */
-        { 0x0000, 0x0000, 0x0000 }, /* R466 */
-        { 0x0000, 0x0000, 0x0000 }, /* R467 */
-        { 0x0000, 0x0000, 0x0000 }, /* R468 */
-        { 0x0000, 0x0000, 0x0000 }, /* R469 */
-        { 0x0000, 0x0000, 0x0000 }, /* R470 */
-        { 0x0000, 0x0000, 0x0000 }, /* R471 */
-        { 0x0000, 0x0000, 0x0000 }, /* R472 */
-        { 0x0000, 0x0000, 0x0000 }, /* R473 */
-        { 0x0000, 0x0000, 0x0000 }, /* R474 */
-        { 0x0000, 0x0000, 0x0000 }, /* R475 */
-        { 0x0000, 0x0000, 0x0000 }, /* R476 */
-        { 0x0000, 0x0000, 0x0000 }, /* R477 */
-        { 0x0000, 0x0000, 0x0000 }, /* R478 */
-        { 0x0000, 0x0000, 0x0000 }, /* R479 */
-        { 0x0000, 0x0000, 0x0000 }, /* R480 */
-        { 0x0000, 0x0000, 0x0000 }, /* R481 */
-        { 0x0000, 0x0000, 0x0000 }, /* R482 */
-        { 0x0000, 0x0000, 0x0000 }, /* R483 */
-        { 0x0000, 0x0000, 0x0000 }, /* R484 */
-        { 0x0000, 0x0000, 0x0000 }, /* R485 */
-        { 0x0000, 0x0000, 0x0000 }, /* R486 */
-        { 0x0000, 0x0000, 0x0000 }, /* R487 */
-        { 0x0000, 0x0000, 0x0000 }, /* R488 */
-        { 0x0000, 0x0000, 0x0000 }, /* R489 */
-        { 0x0000, 0x0000, 0x0000 }, /* R490 */
-        { 0x0000, 0x0000, 0x0000 }, /* R491 */
-        { 0x0000, 0x0000, 0x0000 }, /* R492 */
-        { 0x0000, 0x0000, 0x0000 }, /* R493 */
-        { 0x0000, 0x0000, 0x0000 }, /* R494 */
-        { 0x0000, 0x0000, 0x0000 }, /* R495 */
-        { 0x0000, 0x0000, 0x0000 }, /* R496 */
-        { 0x0000, 0x0000, 0x0000 }, /* R497 */
-        { 0x0000, 0x0000, 0x0000 }, /* R498 */
-        { 0x0000, 0x0000, 0x0000 }, /* R499 */
-        { 0x0000, 0x0000, 0x0000 }, /* R500 */
-        { 0x0000, 0x0000, 0x0000 }, /* R501 */
-        { 0x0000, 0x0000, 0x0000 }, /* R502 */
-        { 0x0000, 0x0000, 0x0000 }, /* R503 */
-        { 0x0000, 0x0000, 0x0000 }, /* R504 */
-        { 0x0000, 0x0000, 0x0000 }, /* R505 */
-        { 0x0000, 0x0000, 0x0000 }, /* R506 */
-        { 0x0000, 0x0000, 0x0000 }, /* R507 */
-        { 0x0000, 0x0000, 0x0000 }, /* R508 */
-        { 0x0000, 0x0000, 0x0000 }, /* R509 */
-        { 0x0000, 0x0000, 0x0000 }, /* R510 */
-        { 0x0000, 0x0000, 0x0000 }, /* R511 */
-        { 0x001F, 0x001F, 0x0000 }, /* R512   - AIF1 Clocking (1) */
-        { 0x003F, 0x003F, 0x0000 }, /* R513   - AIF1 Clocking (2) */
-        { 0x0000, 0x0000, 0x0000 }, /* R514 */
-        { 0x0000, 0x0000, 0x0000 }, /* R515 */
-        { 0x001F, 0x001F, 0x0000 }, /* R516   - AIF2 Clocking (1) */
-        { 0x003F, 0x003F, 0x0000 }, /* R517   - AIF2 Clocking (2) */
-        { 0x0000, 0x0000, 0x0000 }, /* R518 */
-        { 0x0000, 0x0000, 0x0000 }, /* R519 */
-        { 0x001F, 0x001F, 0x0000 }, /* R520   - Clocking (1) */
-        { 0x0777, 0x0777, 0x0000 }, /* R521   - Clocking (2) */
-        { 0x0000, 0x0000, 0x0000 }, /* R522 */
-        { 0x0000, 0x0000, 0x0000 }, /* R523 */
-        { 0x0000, 0x0000, 0x0000 }, /* R524 */
-        { 0x0000, 0x0000, 0x0000 }, /* R525 */
-        { 0x0000, 0x0000, 0x0000 }, /* R526 */
-        { 0x0000, 0x0000, 0x0000 }, /* R527 */
-        { 0x00FF, 0x00FF, 0x0000 }, /* R528   - AIF1 Rate */
-        { 0x00FF, 0x00FF, 0x0000 }, /* R529   - AIF2 Rate */
-        { 0x000F, 0x0000, 0x0000 }, /* R530   - Rate Status */
-        { 0x0000, 0x0000, 0x0000 }, /* R531 */
-        { 0x0000, 0x0000, 0x0000 }, /* R532 */
-        { 0x0000, 0x0000, 0x0000 }, /* R533 */
-        { 0x0000, 0x0000, 0x0000 }, /* R534 */
-        { 0x0000, 0x0000, 0x0000 }, /* R535 */
-        { 0x0000, 0x0000, 0x0000 }, /* R536 */
-        { 0x0000, 0x0000, 0x0000 }, /* R537 */
-        { 0x0000, 0x0000, 0x0000 }, /* R538 */
-        { 0x0000, 0x0000, 0x0000 }, /* R539 */
-        { 0x0000, 0x0000, 0x0000 }, /* R540 */
-        { 0x0000, 0x0000, 0x0000 }, /* R541 */
-        { 0x0000, 0x0000, 0x0000 }, /* R542 */
-        { 0x0000, 0x0000, 0x0000 }, /* R543 */
-        { 0x0007, 0x0007, 0x0000 }, /* R544   - FLL1 Control (1) */
-        { 0x3F77, 0x3F77, 0x0000 }, /* R545   - FLL1 Control (2) */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R546   - FLL1 Control (3) */
-        { 0x7FEF, 0x7FEF, 0x0000 }, /* R547   - FLL1 Control (4) */
-        { 0x1FDB, 0x1FDB, 0x0000 }, /* R548   - FLL1 Control (5) */
-        { 0x0000, 0x0000, 0x0000 }, /* R549 */
-        { 0x0000, 0x0000, 0x0000 }, /* R550 */
-        { 0x0000, 0x0000, 0x0000 }, /* R551 */
-        { 0x0000, 0x0000, 0x0000 }, /* R552 */
-        { 0x0000, 0x0000, 0x0000 }, /* R553 */
-        { 0x0000, 0x0000, 0x0000 }, /* R554 */
-        { 0x0000, 0x0000, 0x0000 }, /* R555 */
-        { 0x0000, 0x0000, 0x0000 }, /* R556 */
-        { 0x0000, 0x0000, 0x0000 }, /* R557 */
-        { 0x0000, 0x0000, 0x0000 }, /* R558 */
-        { 0x0000, 0x0000, 0x0000 }, /* R559 */
-        { 0x0000, 0x0000, 0x0000 }, /* R560 */
-        { 0x0000, 0x0000, 0x0000 }, /* R561 */
-        { 0x0000, 0x0000, 0x0000 }, /* R562 */
-        { 0x0000, 0x0000, 0x0000 }, /* R563 */
-        { 0x0000, 0x0000, 0x0000 }, /* R564 */
-        { 0x0000, 0x0000, 0x0000 }, /* R565 */
-        { 0x0000, 0x0000, 0x0000 }, /* R566 */
-        { 0x0000, 0x0000, 0x0000 }, /* R567 */
-        { 0x0000, 0x0000, 0x0000 }, /* R568 */
-        { 0x0000, 0x0000, 0x0000 }, /* R569 */
-        { 0x0000, 0x0000, 0x0000 }, /* R570 */
-        { 0x0000, 0x0000, 0x0000 }, /* R571 */
-        { 0x0000, 0x0000, 0x0000 }, /* R572 */
-        { 0x0000, 0x0000, 0x0000 }, /* R573 */
-        { 0x0000, 0x0000, 0x0000 }, /* R574 */
-        { 0x0000, 0x0000, 0x0000 }, /* R575 */
-        { 0x0007, 0x0007, 0x0000 }, /* R576   - FLL2 Control (1) */
-        { 0x3F77, 0x3F77, 0x0000 }, /* R577   - FLL2 Control (2) */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R578   - FLL2 Control (3) */
-        { 0x7FEF, 0x7FEF, 0x0000 }, /* R579   - FLL2 Control (4) */
-        { 0x1FDB, 0x1FDB, 0x0000 }, /* R580   - FLL2 Control (5) */
-        { 0x0000, 0x0000, 0x0000 }, /* R581 */
-        { 0x0000, 0x0000, 0x0000 }, /* R582 */
-        { 0x0000, 0x0000, 0x0000 }, /* R583 */
-        { 0x0000, 0x0000, 0x0000 }, /* R584 */
-        { 0x0000, 0x0000, 0x0000 }, /* R585 */
-        { 0x0000, 0x0000, 0x0000 }, /* R586 */
-        { 0x0000, 0x0000, 0x0000 }, /* R587 */
-        { 0x0000, 0x0000, 0x0000 }, /* R588 */
-        { 0x0000, 0x0000, 0x0000 }, /* R589 */
-        { 0x0000, 0x0000, 0x0000 }, /* R590 */
-        { 0x0000, 0x0000, 0x0000 }, /* R591 */
-        { 0x0000, 0x0000, 0x0000 }, /* R592 */
-        { 0x0000, 0x0000, 0x0000 }, /* R593 */
-        { 0x0000, 0x0000, 0x0000 }, /* R594 */
-        { 0x0000, 0x0000, 0x0000 }, /* R595 */
-        { 0x0000, 0x0000, 0x0000 }, /* R596 */
-        { 0x0000, 0x0000, 0x0000 }, /* R597 */
-        { 0x0000, 0x0000, 0x0000 }, /* R598 */
-        { 0x0000, 0x0000, 0x0000 }, /* R599 */
-        { 0x0000, 0x0000, 0x0000 }, /* R600 */
-        { 0x0000, 0x0000, 0x0000 }, /* R601 */
-        { 0x0000, 0x0000, 0x0000 }, /* R602 */
-        { 0x0000, 0x0000, 0x0000 }, /* R603 */
-        { 0x0000, 0x0000, 0x0000 }, /* R604 */
-        { 0x0000, 0x0000, 0x0000 }, /* R605 */
-        { 0x0000, 0x0000, 0x0000 }, /* R606 */
-        { 0x0000, 0x0000, 0x0000 }, /* R607 */
-        { 0x0000, 0x0000, 0x0000 }, /* R608 */
-        { 0x0000, 0x0000, 0x0000 }, /* R609 */
-        { 0x0000, 0x0000, 0x0000 }, /* R610 */
-        { 0x0000, 0x0000, 0x0000 }, /* R611 */
-        { 0x0000, 0x0000, 0x0000 }, /* R612 */
-        { 0x0000, 0x0000, 0x0000 }, /* R613 */
-        { 0x0000, 0x0000, 0x0000 }, /* R614 */
-        { 0x0000, 0x0000, 0x0000 }, /* R615 */
-        { 0x0000, 0x0000, 0x0000 }, /* R616 */
-        { 0x0000, 0x0000, 0x0000 }, /* R617 */
-        { 0x0000, 0x0000, 0x0000 }, /* R618 */
-        { 0x0000, 0x0000, 0x0000 }, /* R619 */
-        { 0x0000, 0x0000, 0x0000 }, /* R620 */
-        { 0x0000, 0x0000, 0x0000 }, /* R621 */
-        { 0x0000, 0x0000, 0x0000 }, /* R622 */
-        { 0x0000, 0x0000, 0x0000 }, /* R623 */
-        { 0x0000, 0x0000, 0x0000 }, /* R624 */
-        { 0x0000, 0x0000, 0x0000 }, /* R625 */
-        { 0x0000, 0x0000, 0x0000 }, /* R626 */
-        { 0x0000, 0x0000, 0x0000 }, /* R627 */
-        { 0x0000, 0x0000, 0x0000 }, /* R628 */
-        { 0x0000, 0x0000, 0x0000 }, /* R629 */
-        { 0x0000, 0x0000, 0x0000 }, /* R630 */
-        { 0x0000, 0x0000, 0x0000 }, /* R631 */
-        { 0x0000, 0x0000, 0x0000 }, /* R632 */
-        { 0x0000, 0x0000, 0x0000 }, /* R633 */
-        { 0x0000, 0x0000, 0x0000 }, /* R634 */
-        { 0x0000, 0x0000, 0x0000 }, /* R635 */
-        { 0x0000, 0x0000, 0x0000 }, /* R636 */
-        { 0x0000, 0x0000, 0x0000 }, /* R637 */
-        { 0x0000, 0x0000, 0x0000 }, /* R638 */
-        { 0x0000, 0x0000, 0x0000 }, /* R639 */
-        { 0x0000, 0x0000, 0x0000 }, /* R640 */
-        { 0x0000, 0x0000, 0x0000 }, /* R641 */
-        { 0x0000, 0x0000, 0x0000 }, /* R642 */
-        { 0x0000, 0x0000, 0x0000 }, /* R643 */
-        { 0x0000, 0x0000, 0x0000 }, /* R644 */
-        { 0x0000, 0x0000, 0x0000 }, /* R645 */
-        { 0x0000, 0x0000, 0x0000 }, /* R646 */
-        { 0x0000, 0x0000, 0x0000 }, /* R647 */
-        { 0x0000, 0x0000, 0x0000 }, /* R648 */
-        { 0x0000, 0x0000, 0x0000 }, /* R649 */
-        { 0x0000, 0x0000, 0x0000 }, /* R650 */
-        { 0x0000, 0x0000, 0x0000 }, /* R651 */
-        { 0x0000, 0x0000, 0x0000 }, /* R652 */
-        { 0x0000, 0x0000, 0x0000 }, /* R653 */
-        { 0x0000, 0x0000, 0x0000 }, /* R654 */
-        { 0x0000, 0x0000, 0x0000 }, /* R655 */
-        { 0x0000, 0x0000, 0x0000 }, /* R656 */
-        { 0x0000, 0x0000, 0x0000 }, /* R657 */
-        { 0x0000, 0x0000, 0x0000 }, /* R658 */
-        { 0x0000, 0x0000, 0x0000 }, /* R659 */
-        { 0x0000, 0x0000, 0x0000 }, /* R660 */
-        { 0x0000, 0x0000, 0x0000 }, /* R661 */
-        { 0x0000, 0x0000, 0x0000 }, /* R662 */
-        { 0x0000, 0x0000, 0x0000 }, /* R663 */
-        { 0x0000, 0x0000, 0x0000 }, /* R664 */
-        { 0x0000, 0x0000, 0x0000 }, /* R665 */
-        { 0x0000, 0x0000, 0x0000 }, /* R666 */
-        { 0x0000, 0x0000, 0x0000 }, /* R667 */
-        { 0x0000, 0x0000, 0x0000 }, /* R668 */
-        { 0x0000, 0x0000, 0x0000 }, /* R669 */
-        { 0x0000, 0x0000, 0x0000 }, /* R670 */
-        { 0x0000, 0x0000, 0x0000 }, /* R671 */
-        { 0x0000, 0x0000, 0x0000 }, /* R672 */
-        { 0x0000, 0x0000, 0x0000 }, /* R673 */
-        { 0x0000, 0x0000, 0x0000 }, /* R674 */
-        { 0x0000, 0x0000, 0x0000 }, /* R675 */
-        { 0x0000, 0x0000, 0x0000 }, /* R676 */
-        { 0x0000, 0x0000, 0x0000 }, /* R677 */
-        { 0x0000, 0x0000, 0x0000 }, /* R678 */
-        { 0x0000, 0x0000, 0x0000 }, /* R679 */
-        { 0x0000, 0x0000, 0x0000 }, /* R680 */
-        { 0x0000, 0x0000, 0x0000 }, /* R681 */
-        { 0x0000, 0x0000, 0x0000 }, /* R682 */
-        { 0x0000, 0x0000, 0x0000 }, /* R683 */
-        { 0x0000, 0x0000, 0x0000 }, /* R684 */
-        { 0x0000, 0x0000, 0x0000 }, /* R685 */
-        { 0x0000, 0x0000, 0x0000 }, /* R686 */
-        { 0x0000, 0x0000, 0x0000 }, /* R687 */
-        { 0x0000, 0x0000, 0x0000 }, /* R688 */
-        { 0x0000, 0x0000, 0x0000 }, /* R689 */
-        { 0x0000, 0x0000, 0x0000 }, /* R690 */
-        { 0x0000, 0x0000, 0x0000 }, /* R691 */
-        { 0x0000, 0x0000, 0x0000 }, /* R692 */
-        { 0x0000, 0x0000, 0x0000 }, /* R693 */
-        { 0x0000, 0x0000, 0x0000 }, /* R694 */
-        { 0x0000, 0x0000, 0x0000 }, /* R695 */
-        { 0x0000, 0x0000, 0x0000 }, /* R696 */
-        { 0x0000, 0x0000, 0x0000 }, /* R697 */
-        { 0x0000, 0x0000, 0x0000 }, /* R698 */
-        { 0x0000, 0x0000, 0x0000 }, /* R699 */
-        { 0x0000, 0x0000, 0x0000 }, /* R700 */
-        { 0x0000, 0x0000, 0x0000 }, /* R701 */
-        { 0x0000, 0x0000, 0x0000 }, /* R702 */
-        { 0x0000, 0x0000, 0x0000 }, /* R703 */
-        { 0x0000, 0x0000, 0x0000 }, /* R704 */
-        { 0x0000, 0x0000, 0x0000 }, /* R705 */
-        { 0x0000, 0x0000, 0x0000 }, /* R706 */
-        { 0x0000, 0x0000, 0x0000 }, /* R707 */
-        { 0x0000, 0x0000, 0x0000 }, /* R708 */
-        { 0x0000, 0x0000, 0x0000 }, /* R709 */
-        { 0x0000, 0x0000, 0x0000 }, /* R710 */
-        { 0x0000, 0x0000, 0x0000 }, /* R711 */
-        { 0x0000, 0x0000, 0x0000 }, /* R712 */
-        { 0x0000, 0x0000, 0x0000 }, /* R713 */
-        { 0x0000, 0x0000, 0x0000 }, /* R714 */
-        { 0x0000, 0x0000, 0x0000 }, /* R715 */
-        { 0x0000, 0x0000, 0x0000 }, /* R716 */
-        { 0x0000, 0x0000, 0x0000 }, /* R717 */
-        { 0x0000, 0x0000, 0x0000 }, /* R718 */
-        { 0x0000, 0x0000, 0x0000 }, /* R719 */
-        { 0x0000, 0x0000, 0x0000 }, /* R720 */
-        { 0x0000, 0x0000, 0x0000 }, /* R721 */
-        { 0x0000, 0x0000, 0x0000 }, /* R722 */
-        { 0x0000, 0x0000, 0x0000 }, /* R723 */
-        { 0x0000, 0x0000, 0x0000 }, /* R724 */
-        { 0x0000, 0x0000, 0x0000 }, /* R725 */
-        { 0x0000, 0x0000, 0x0000 }, /* R726 */
-        { 0x0000, 0x0000, 0x0000 }, /* R727 */
-        { 0x0000, 0x0000, 0x0000 }, /* R728 */
-        { 0x0000, 0x0000, 0x0000 }, /* R729 */
-        { 0x0000, 0x0000, 0x0000 }, /* R730 */
-        { 0x0000, 0x0000, 0x0000 }, /* R731 */
-        { 0x0000, 0x0000, 0x0000 }, /* R732 */
-        { 0x0000, 0x0000, 0x0000 }, /* R733 */
-        { 0x0000, 0x0000, 0x0000 }, /* R734 */
-        { 0x0000, 0x0000, 0x0000 }, /* R735 */
-        { 0x0000, 0x0000, 0x0000 }, /* R736 */
-        { 0x0000, 0x0000, 0x0000 }, /* R737 */
-        { 0x0000, 0x0000, 0x0000 }, /* R738 */
-        { 0x0000, 0x0000, 0x0000 }, /* R739 */
-        { 0x0000, 0x0000, 0x0000 }, /* R740 */
-        { 0x0000, 0x0000, 0x0000 }, /* R741 */
-        { 0x0000, 0x0000, 0x0000 }, /* R742 */
-        { 0x0000, 0x0000, 0x0000 }, /* R743 */
-        { 0x0000, 0x0000, 0x0000 }, /* R744 */
-        { 0x0000, 0x0000, 0x0000 }, /* R745 */
-        { 0x0000, 0x0000, 0x0000 }, /* R746 */
-        { 0x0000, 0x0000, 0x0000 }, /* R747 */
-        { 0x0000, 0x0000, 0x0000 }, /* R748 */
-        { 0x0000, 0x0000, 0x0000 }, /* R749 */
-        { 0x0000, 0x0000, 0x0000 }, /* R750 */
-        { 0x0000, 0x0000, 0x0000 }, /* R751 */
-        { 0x0000, 0x0000, 0x0000 }, /* R752 */
-        { 0x0000, 0x0000, 0x0000 }, /* R753 */
-        { 0x0000, 0x0000, 0x0000 }, /* R754 */
-        { 0x0000, 0x0000, 0x0000 }, /* R755 */
-        { 0x0000, 0x0000, 0x0000 }, /* R756 */
-        { 0x0000, 0x0000, 0x0000 }, /* R757 */
-        { 0x0000, 0x0000, 0x0000 }, /* R758 */
-        { 0x0000, 0x0000, 0x0000 }, /* R759 */
-        { 0x0000, 0x0000, 0x0000 }, /* R760 */
-        { 0x0000, 0x0000, 0x0000 }, /* R761 */
-        { 0x0000, 0x0000, 0x0000 }, /* R762 */
-        { 0x0000, 0x0000, 0x0000 }, /* R763 */
-        { 0x0000, 0x0000, 0x0000 }, /* R764 */
-        { 0x0000, 0x0000, 0x0000 }, /* R765 */
-        { 0x0000, 0x0000, 0x0000 }, /* R766 */
-        { 0x0000, 0x0000, 0x0000 }, /* R767 */
-        { 0xE1F8, 0xE1F8, 0x0000 }, /* R768   - AIF1 Control (1) */
-        { 0xCD1F, 0xCD1F, 0x0000 }, /* R769   - AIF1 Control (2) */
-        { 0xF000, 0xF000, 0x0000 }, /* R770   - AIF1 Master/Slave */
-        { 0x01F0, 0x01F0, 0x0000 }, /* R771   - AIF1 BCLK */
-        { 0x0FFF, 0x0FFF, 0x0000 }, /* R772   - AIF1ADC LRCLK */
-        { 0x0FFF, 0x0FFF, 0x0000 }, /* R773   - AIF1DAC LRCLK */
-        { 0x0003, 0x0003, 0x0000 }, /* R774   - AIF1DAC Data */
-        { 0x0003, 0x0003, 0x0000 }, /* R775   - AIF1ADC Data */
-        { 0x0000, 0x0000, 0x0000 }, /* R776 */
-        { 0x0000, 0x0000, 0x0000 }, /* R777 */
-        { 0x0000, 0x0000, 0x0000 }, /* R778 */
-        { 0x0000, 0x0000, 0x0000 }, /* R779 */
-        { 0x0000, 0x0000, 0x0000 }, /* R780 */
-        { 0x0000, 0x0000, 0x0000 }, /* R781 */
-        { 0x0000, 0x0000, 0x0000 }, /* R782 */
-        { 0x0000, 0x0000, 0x0000 }, /* R783 */
-        { 0xF1F8, 0xF1F8, 0x0000 }, /* R784   - AIF2 Control (1) */
-        { 0xFD1F, 0xFD1F, 0x0000 }, /* R785   - AIF2 Control (2) */
-        { 0xF000, 0xF000, 0x0000 }, /* R786   - AIF2 Master/Slave */
-        { 0x01F0, 0x01F0, 0x0000 }, /* R787   - AIF2 BCLK */
-        { 0x0FFF, 0x0FFF, 0x0000 }, /* R788   - AIF2ADC LRCLK */
-        { 0x0FFF, 0x0FFF, 0x0000 }, /* R789   - AIF2DAC LRCLK */
-        { 0x0003, 0x0003, 0x0000 }, /* R790   - AIF2DAC Data */
-        { 0x0003, 0x0003, 0x0000 }, /* R791   - AIF2ADC Data */
-        { 0x0000, 0x0000, 0x0000 }, /* R792 */
-        { 0x0000, 0x0000, 0x0000 }, /* R793 */
-        { 0x0000, 0x0000, 0x0000 }, /* R794 */
-        { 0x0000, 0x0000, 0x0000 }, /* R795 */
-        { 0x0000, 0x0000, 0x0000 }, /* R796 */
-        { 0x0000, 0x0000, 0x0000 }, /* R797 */
-        { 0x0000, 0x0000, 0x0000 }, /* R798 */
-        { 0x0000, 0x0000, 0x0000 }, /* R799 */
-        { 0x0000, 0x0000, 0x0000 }, /* R800 */
-        { 0x0000, 0x0000, 0x0000 }, /* R801 */
-        { 0x0000, 0x0000, 0x0000 }, /* R802 */
-        { 0x0000, 0x0000, 0x0000 }, /* R803 */
-        { 0x0000, 0x0000, 0x0000 }, /* R804 */
-        { 0x0000, 0x0000, 0x0000 }, /* R805 */
-        { 0x0000, 0x0000, 0x0000 }, /* R806 */
-        { 0x0000, 0x0000, 0x0000 }, /* R807 */
-        { 0x0000, 0x0000, 0x0000 }, /* R808 */
-        { 0x0000, 0x0000, 0x0000 }, /* R809 */
-        { 0x0000, 0x0000, 0x0000 }, /* R810 */
-        { 0x0000, 0x0000, 0x0000 }, /* R811 */
-        { 0x0000, 0x0000, 0x0000 }, /* R812 */
-        { 0x0000, 0x0000, 0x0000 }, /* R813 */
-        { 0x0000, 0x0000, 0x0000 }, /* R814 */
-        { 0x0000, 0x0000, 0x0000 }, /* R815 */
-        { 0x0000, 0x0000, 0x0000 }, /* R816 */
-        { 0x0000, 0x0000, 0x0000 }, /* R817 */
-        { 0x0000, 0x0000, 0x0000 }, /* R818 */
-        { 0x0000, 0x0000, 0x0000 }, /* R819 */
-        { 0x0000, 0x0000, 0x0000 }, /* R820 */
-        { 0x0000, 0x0000, 0x0000 }, /* R821 */
-        { 0x0000, 0x0000, 0x0000 }, /* R822 */
-        { 0x0000, 0x0000, 0x0000 }, /* R823 */
-        { 0x0000, 0x0000, 0x0000 }, /* R824 */
-        { 0x0000, 0x0000, 0x0000 }, /* R825 */
-        { 0x0000, 0x0000, 0x0000 }, /* R826 */
-        { 0x0000, 0x0000, 0x0000 }, /* R827 */
-        { 0x0000, 0x0000, 0x0000 }, /* R828 */
-        { 0x0000, 0x0000, 0x0000 }, /* R829 */
-        { 0x0000, 0x0000, 0x0000 }, /* R830 */
-        { 0x0000, 0x0000, 0x0000 }, /* R831 */
-        { 0x0000, 0x0000, 0x0000 }, /* R832 */
-        { 0x0000, 0x0000, 0x0000 }, /* R833 */
-        { 0x0000, 0x0000, 0x0000 }, /* R834 */
-        { 0x0000, 0x0000, 0x0000 }, /* R835 */
-        { 0x0000, 0x0000, 0x0000 }, /* R836 */
-        { 0x0000, 0x0000, 0x0000 }, /* R837 */
-        { 0x0000, 0x0000, 0x0000 }, /* R838 */
-        { 0x0000, 0x0000, 0x0000 }, /* R839 */
-        { 0x0000, 0x0000, 0x0000 }, /* R840 */
-        { 0x0000, 0x0000, 0x0000 }, /* R841 */
-        { 0x0000, 0x0000, 0x0000 }, /* R842 */
-        { 0x0000, 0x0000, 0x0000 }, /* R843 */
-        { 0x0000, 0x0000, 0x0000 }, /* R844 */
-        { 0x0000, 0x0000, 0x0000 }, /* R845 */
-        { 0x0000, 0x0000, 0x0000 }, /* R846 */
-        { 0x0000, 0x0000, 0x0000 }, /* R847 */
-        { 0x0000, 0x0000, 0x0000 }, /* R848 */
-        { 0x0000, 0x0000, 0x0000 }, /* R849 */
-        { 0x0000, 0x0000, 0x0000 }, /* R850 */
-        { 0x0000, 0x0000, 0x0000 }, /* R851 */
-        { 0x0000, 0x0000, 0x0000 }, /* R852 */
-        { 0x0000, 0x0000, 0x0000 }, /* R853 */
-        { 0x0000, 0x0000, 0x0000 }, /* R854 */
-        { 0x0000, 0x0000, 0x0000 }, /* R855 */
-        { 0x0000, 0x0000, 0x0000 }, /* R856 */
-        { 0x0000, 0x0000, 0x0000 }, /* R857 */
-        { 0x0000, 0x0000, 0x0000 }, /* R858 */
-        { 0x0000, 0x0000, 0x0000 }, /* R859 */
-        { 0x0000, 0x0000, 0x0000 }, /* R860 */
-        { 0x0000, 0x0000, 0x0000 }, /* R861 */
-        { 0x0000, 0x0000, 0x0000 }, /* R862 */
-        { 0x0000, 0x0000, 0x0000 }, /* R863 */
-        { 0x0000, 0x0000, 0x0000 }, /* R864 */
-        { 0x0000, 0x0000, 0x0000 }, /* R865 */
-        { 0x0000, 0x0000, 0x0000 }, /* R866 */
-        { 0x0000, 0x0000, 0x0000 }, /* R867 */
-        { 0x0000, 0x0000, 0x0000 }, /* R868 */
-        { 0x0000, 0x0000, 0x0000 }, /* R869 */
-        { 0x0000, 0x0000, 0x0000 }, /* R870 */
-        { 0x0000, 0x0000, 0x0000 }, /* R871 */
-        { 0x0000, 0x0000, 0x0000 }, /* R872 */
-        { 0x0000, 0x0000, 0x0000 }, /* R873 */
-        { 0x0000, 0x0000, 0x0000 }, /* R874 */
-        { 0x0000, 0x0000, 0x0000 }, /* R875 */
-        { 0x0000, 0x0000, 0x0000 }, /* R876 */
-        { 0x0000, 0x0000, 0x0000 }, /* R877 */
-        { 0x0000, 0x0000, 0x0000 }, /* R878 */
-        { 0x0000, 0x0000, 0x0000 }, /* R879 */
-        { 0x0000, 0x0000, 0x0000 }, /* R880 */
-        { 0x0000, 0x0000, 0x0000 }, /* R881 */
-        { 0x0000, 0x0000, 0x0000 }, /* R882 */
-        { 0x0000, 0x0000, 0x0000 }, /* R883 */
-        { 0x0000, 0x0000, 0x0000 }, /* R884 */
-        { 0x0000, 0x0000, 0x0000 }, /* R885 */
-        { 0x0000, 0x0000, 0x0000 }, /* R886 */
-        { 0x0000, 0x0000, 0x0000 }, /* R887 */
-        { 0x0000, 0x0000, 0x0000 }, /* R888 */
-        { 0x0000, 0x0000, 0x0000 }, /* R889 */
-        { 0x0000, 0x0000, 0x0000 }, /* R890 */
-        { 0x0000, 0x0000, 0x0000 }, /* R891 */
-        { 0x0000, 0x0000, 0x0000 }, /* R892 */
-        { 0x0000, 0x0000, 0x0000 }, /* R893 */
-        { 0x0000, 0x0000, 0x0000 }, /* R894 */
-        { 0x0000, 0x0000, 0x0000 }, /* R895 */
-        { 0x0000, 0x0000, 0x0000 }, /* R896 */
-        { 0x0000, 0x0000, 0x0000 }, /* R897 */
-        { 0x0000, 0x0000, 0x0000 }, /* R898 */
-        { 0x0000, 0x0000, 0x0000 }, /* R899 */
-        { 0x0000, 0x0000, 0x0000 }, /* R900 */
-        { 0x0000, 0x0000, 0x0000 }, /* R901 */
-        { 0x0000, 0x0000, 0x0000 }, /* R902 */
-        { 0x0000, 0x0000, 0x0000 }, /* R903 */
-        { 0x0000, 0x0000, 0x0000 }, /* R904 */
-        { 0x0000, 0x0000, 0x0000 }, /* R905 */
-        { 0x0000, 0x0000, 0x0000 }, /* R906 */
-        { 0x0000, 0x0000, 0x0000 }, /* R907 */
-        { 0x0000, 0x0000, 0x0000 }, /* R908 */
-        { 0x0000, 0x0000, 0x0000 }, /* R909 */
-        { 0x0000, 0x0000, 0x0000 }, /* R910 */
-        { 0x0000, 0x0000, 0x0000 }, /* R911 */
-        { 0x0000, 0x0000, 0x0000 }, /* R912 */
-        { 0x0000, 0x0000, 0x0000 }, /* R913 */
-        { 0x0000, 0x0000, 0x0000 }, /* R914 */
-        { 0x0000, 0x0000, 0x0000 }, /* R915 */
-        { 0x0000, 0x0000, 0x0000 }, /* R916 */
-        { 0x0000, 0x0000, 0x0000 }, /* R917 */
-        { 0x0000, 0x0000, 0x0000 }, /* R918 */
-        { 0x0000, 0x0000, 0x0000 }, /* R919 */
-        { 0x0000, 0x0000, 0x0000 }, /* R920 */
-        { 0x0000, 0x0000, 0x0000 }, /* R921 */
-        { 0x0000, 0x0000, 0x0000 }, /* R922 */
-        { 0x0000, 0x0000, 0x0000 }, /* R923 */
-        { 0x0000, 0x0000, 0x0000 }, /* R924 */
-        { 0x0000, 0x0000, 0x0000 }, /* R925 */
-        { 0x0000, 0x0000, 0x0000 }, /* R926 */
-        { 0x0000, 0x0000, 0x0000 }, /* R927 */
-        { 0x0000, 0x0000, 0x0000 }, /* R928 */
-        { 0x0000, 0x0000, 0x0000 }, /* R929 */
-        { 0x0000, 0x0000, 0x0000 }, /* R930 */
-        { 0x0000, 0x0000, 0x0000 }, /* R931 */
-        { 0x0000, 0x0000, 0x0000 }, /* R932 */
-        { 0x0000, 0x0000, 0x0000 }, /* R933 */
-        { 0x0000, 0x0000, 0x0000 }, /* R934 */
-        { 0x0000, 0x0000, 0x0000 }, /* R935 */
-        { 0x0000, 0x0000, 0x0000 }, /* R936 */
-        { 0x0000, 0x0000, 0x0000 }, /* R937 */
-        { 0x0000, 0x0000, 0x0000 }, /* R938 */
-        { 0x0000, 0x0000, 0x0000 }, /* R939 */
-        { 0x0000, 0x0000, 0x0000 }, /* R940 */
-        { 0x0000, 0x0000, 0x0000 }, /* R941 */
-        { 0x0000, 0x0000, 0x0000 }, /* R942 */
-        { 0x0000, 0x0000, 0x0000 }, /* R943 */
-        { 0x0000, 0x0000, 0x0000 }, /* R944 */
-        { 0x0000, 0x0000, 0x0000 }, /* R945 */
-        { 0x0000, 0x0000, 0x0000 }, /* R946 */
-        { 0x0000, 0x0000, 0x0000 }, /* R947 */
-        { 0x0000, 0x0000, 0x0000 }, /* R948 */
-        { 0x0000, 0x0000, 0x0000 }, /* R949 */
-        { 0x0000, 0x0000, 0x0000 }, /* R950 */
-        { 0x0000, 0x0000, 0x0000 }, /* R951 */
-        { 0x0000, 0x0000, 0x0000 }, /* R952 */
-        { 0x0000, 0x0000, 0x0000 }, /* R953 */
-        { 0x0000, 0x0000, 0x0000 }, /* R954 */
-        { 0x0000, 0x0000, 0x0000 }, /* R955 */
-        { 0x0000, 0x0000, 0x0000 }, /* R956 */
-        { 0x0000, 0x0000, 0x0000 }, /* R957 */
-        { 0x0000, 0x0000, 0x0000 }, /* R958 */
-        { 0x0000, 0x0000, 0x0000 }, /* R959 */
-        { 0x0000, 0x0000, 0x0000 }, /* R960 */
-        { 0x0000, 0x0000, 0x0000 }, /* R961 */
-        { 0x0000, 0x0000, 0x0000 }, /* R962 */
-        { 0x0000, 0x0000, 0x0000 }, /* R963 */
-        { 0x0000, 0x0000, 0x0000 }, /* R964 */
-        { 0x0000, 0x0000, 0x0000 }, /* R965 */
-        { 0x0000, 0x0000, 0x0000 }, /* R966 */
-        { 0x0000, 0x0000, 0x0000 }, /* R967 */
-        { 0x0000, 0x0000, 0x0000 }, /* R968 */
-        { 0x0000, 0x0000, 0x0000 }, /* R969 */
-        { 0x0000, 0x0000, 0x0000 }, /* R970 */
-        { 0x0000, 0x0000, 0x0000 }, /* R971 */
-        { 0x0000, 0x0000, 0x0000 }, /* R972 */
-        { 0x0000, 0x0000, 0x0000 }, /* R973 */
-        { 0x0000, 0x0000, 0x0000 }, /* R974 */
-        { 0x0000, 0x0000, 0x0000 }, /* R975 */
-        { 0x0000, 0x0000, 0x0000 }, /* R976 */
-        { 0x0000, 0x0000, 0x0000 }, /* R977 */
-        { 0x0000, 0x0000, 0x0000 }, /* R978 */
-        { 0x0000, 0x0000, 0x0000 }, /* R979 */
-        { 0x0000, 0x0000, 0x0000 }, /* R980 */
-        { 0x0000, 0x0000, 0x0000 }, /* R981 */
-        { 0x0000, 0x0000, 0x0000 }, /* R982 */
-        { 0x0000, 0x0000, 0x0000 }, /* R983 */
-        { 0x0000, 0x0000, 0x0000 }, /* R984 */
-        { 0x0000, 0x0000, 0x0000 }, /* R985 */
-        { 0x0000, 0x0000, 0x0000 }, /* R986 */
-        { 0x0000, 0x0000, 0x0000 }, /* R987 */
-        { 0x0000, 0x0000, 0x0000 }, /* R988 */
-        { 0x0000, 0x0000, 0x0000 }, /* R989 */
-        { 0x0000, 0x0000, 0x0000 }, /* R990 */
-        { 0x0000, 0x0000, 0x0000 }, /* R991 */
-        { 0x0000, 0x0000, 0x0000 }, /* R992 */
-        { 0x0000, 0x0000, 0x0000 }, /* R993 */
-        { 0x0000, 0x0000, 0x0000 }, /* R994 */
-        { 0x0000, 0x0000, 0x0000 }, /* R995 */
-        { 0x0000, 0x0000, 0x0000 }, /* R996 */
-        { 0x0000, 0x0000, 0x0000 }, /* R997 */
-        { 0x0000, 0x0000, 0x0000 }, /* R998 */
-        { 0x0000, 0x0000, 0x0000 }, /* R999 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1000 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1001 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1002 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1003 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1004 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1005 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1006 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1007 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1008 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1009 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1010 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1011 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1012 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1013 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1014 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1015 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1016 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1017 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1018 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1019 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1020 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1021 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1022 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1023 */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1024  - AIF1 ADC1 Left Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1025  - AIF1 ADC1 Right Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1026  - AIF1 DAC1 Left Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1027  - AIF1 DAC1 Right Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1028  - AIF1 ADC2 Left Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1029  - AIF1 ADC2 Right Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1030  - AIF1 DAC2 Left Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1031  - AIF1 DAC2 Right Volume */
-        { 0x0000, 0x0000, 0x0000 }, /* R1032 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1033 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1034 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1035 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1036 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1037 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1038 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1039 */
-        { 0xF800, 0xF800, 0x0000 }, /* R1040  - AIF1 ADC1 Filters */
-        { 0x7800, 0x7800, 0x0000 }, /* R1041  - AIF1 ADC2 Filters */
-        { 0x0000, 0x0000, 0x0000 }, /* R1042 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1043 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1044 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1045 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1046 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1047 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1048 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1049 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1050 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1051 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1052 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1053 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1054 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1055 */
-        { 0x02B6, 0x02B6, 0x0000 }, /* R1056  - AIF1 DAC1 Filters (1) */
-        { 0x3F00, 0x3F00, 0x0000 }, /* R1057  - AIF1 DAC1 Filters (2) */
-        { 0x02B6, 0x02B6, 0x0000 }, /* R1058  - AIF1 DAC2 Filters (1) */
-        { 0x3F00, 0x3F00, 0x0000 }, /* R1059  - AIF1 DAC2 Filters (2) */
-        { 0x0000, 0x0000, 0x0000 }, /* R1060 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1061 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1062 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1063 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1064 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1065 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1066 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1067 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1068 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1069 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1070 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1071 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1072 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1073 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1074 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1075 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1076 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1077 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1078 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1079 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1080 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1081 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1082 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1083 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1084 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1085 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1086 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1087 */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1088  - AIF1 DRC1 (1) */
-        { 0x1FFF, 0x1FFF, 0x0000 }, /* R1089  - AIF1 DRC1 (2) */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1090  - AIF1 DRC1 (3) */
-        { 0x07FF, 0x07FF, 0x0000 }, /* R1091  - AIF1 DRC1 (4) */
-        { 0x03FF, 0x03FF, 0x0000 }, /* R1092  - AIF1 DRC1 (5) */
-        { 0x0000, 0x0000, 0x0000 }, /* R1093 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1094 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1095 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1096 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1097 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1098 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1099 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1100 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1101 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1102 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1103 */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1104  - AIF1 DRC2 (1) */
-        { 0x1FFF, 0x1FFF, 0x0000 }, /* R1105  - AIF1 DRC2 (2) */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1106  - AIF1 DRC2 (3) */
-        { 0x07FF, 0x07FF, 0x0000 }, /* R1107  - AIF1 DRC2 (4) */
-        { 0x03FF, 0x03FF, 0x0000 }, /* R1108  - AIF1 DRC2 (5) */
-        { 0x0000, 0x0000, 0x0000 }, /* R1109 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1110 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1111 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1112 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1113 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1114 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1115 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1116 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1117 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1118 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1119 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1120 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1121 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1122 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1123 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1124 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1125 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1126 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1127 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1128 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1129 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1130 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1131 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1132 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1133 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1134 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1135 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1136 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1137 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1138 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1139 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1140 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1141 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1142 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1143 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1144 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1145 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1146 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1147 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1148 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1149 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1150 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1151 */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1152  - AIF1 DAC1 EQ Gains (1) */
-        { 0xFFC0, 0xFFC0, 0x0000 }, /* R1153  - AIF1 DAC1 EQ Gains (2) */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1154  - AIF1 DAC1 EQ Band 1 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1155  - AIF1 DAC1 EQ Band 1 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1156  - AIF1 DAC1 EQ Band 1 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1157  - AIF1 DAC1 EQ Band 2 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1158  - AIF1 DAC1 EQ Band 2 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1159  - AIF1 DAC1 EQ Band 2 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1160  - AIF1 DAC1 EQ Band 2 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1161  - AIF1 DAC1 EQ Band 3 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1162  - AIF1 DAC1 EQ Band 3 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1163  - AIF1 DAC1 EQ Band 3 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1164  - AIF1 DAC1 EQ Band 3 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1165  - AIF1 DAC1 EQ Band 4 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1166  - AIF1 DAC1 EQ Band 4 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1167  - AIF1 DAC1 EQ Band 4 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1168  - AIF1 DAC1 EQ Band 4 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1169  - AIF1 DAC1 EQ Band 5 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1170  - AIF1 DAC1 EQ Band 5 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1171  - AIF1 DAC1 EQ Band 5 PG */
-        { 0x0000, 0x0000, 0x0000 }, /* R1172 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1173 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1174 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1175 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1176 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1177 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1178 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1179 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1180 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1181 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1182 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1183 */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1184  - AIF1 DAC2 EQ Gains (1) */
-        { 0xFFC0, 0xFFC0, 0x0000 }, /* R1185  - AIF1 DAC2 EQ Gains (2) */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1186  - AIF1 DAC2 EQ Band 1 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1187  - AIF1 DAC2 EQ Band 1 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1188  - AIF1 DAC2 EQ Band 1 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1189  - AIF1 DAC2 EQ Band 2 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1190  - AIF1 DAC2 EQ Band 2 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1191  - AIF1 DAC2 EQ Band 2 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1192  - AIF1 DAC2 EQ Band 2 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1193  - AIF1 DAC2 EQ Band 3 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1194  - AIF1 DAC2 EQ Band 3 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1195  - AIF1 DAC2 EQ Band 3 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1196  - AIF1 DAC2 EQ Band 3 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1197  - AIF1 DAC2 EQ Band 4 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1198  - AIF1 DAC2 EQ Band 4 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1199  - AIF1 DAC2 EQ Band 4 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1200  - AIF1 DAC2 EQ Band 4 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1201  - AIF1 DAC2 EQ Band 5 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1202  - AIF1 DAC2 EQ Band 5 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1203  - AIF1 DAC2 EQ Band 5 PG */
-        { 0x0000, 0x0000, 0x0000 }, /* R1204 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1205 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1206 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1207 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1208 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1209 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1210 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1211 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1212 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1213 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1214 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1215 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1216 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1217 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1218 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1219 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1220 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1221 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1222 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1223 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1224 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1225 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1226 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1227 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1228 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1229 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1230 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1231 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1232 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1233 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1234 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1235 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1236 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1237 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1238 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1239 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1240 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1241 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1242 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1243 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1244 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1245 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1246 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1247 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1248 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1249 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1250 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1251 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1252 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1253 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1254 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1255 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1256 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1257 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1258 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1259 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1260 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1261 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1262 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1263 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1264 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1265 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1266 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1267 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1268 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1269 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1270 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1271 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1272 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1273 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1274 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1275 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1276 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1277 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1278 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1279 */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1280  - AIF2 ADC Left Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1281  - AIF2 ADC Right Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1282  - AIF2 DAC Left Volume */
-        { 0x00FF, 0x01FF, 0x0000 }, /* R1283  - AIF2 DAC Right Volume */
-        { 0x0000, 0x0000, 0x0000 }, /* R1284 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1285 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1286 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1287 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1288 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1289 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1290 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1291 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1292 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1293 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1294 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1295 */
-        { 0xF800, 0xF800, 0x0000 }, /* R1296  - AIF2 ADC Filters */
-        { 0x0000, 0x0000, 0x0000 }, /* R1297 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1298 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1299 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1300 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1301 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1302 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1303 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1304 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1305 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1306 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1307 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1308 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1309 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1310 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1311 */
-        { 0x02B6, 0x02B6, 0x0000 }, /* R1312  - AIF2 DAC Filters (1) */
-        { 0x3F00, 0x3F00, 0x0000 }, /* R1313  - AIF2 DAC Filters (2) */
-        { 0x0000, 0x0000, 0x0000 }, /* R1314 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1315 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1316 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1317 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1318 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1319 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1320 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1321 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1322 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1323 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1324 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1325 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1326 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1327 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1328 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1329 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1330 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1331 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1332 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1333 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1334 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1335 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1336 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1337 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1338 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1339 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1340 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1341 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1342 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1343 */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1344  - AIF2 DRC (1) */
-        { 0x1FFF, 0x1FFF, 0x0000 }, /* R1345  - AIF2 DRC (2) */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1346  - AIF2 DRC (3) */
-        { 0x07FF, 0x07FF, 0x0000 }, /* R1347  - AIF2 DRC (4) */
-        { 0x03FF, 0x03FF, 0x0000 }, /* R1348  - AIF2 DRC (5) */
-        { 0x0000, 0x0000, 0x0000 }, /* R1349 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1350 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1351 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1352 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1353 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1354 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1355 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1356 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1357 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1358 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1359 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1360 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1361 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1362 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1363 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1364 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1365 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1366 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1367 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1368 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1369 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1370 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1371 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1372 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1373 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1374 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1375 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1376 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1377 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1378 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1379 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1380 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1381 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1382 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1383 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1384 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1385 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1386 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1387 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1388 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1389 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1390 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1391 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1392 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1393 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1394 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1395 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1396 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1397 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1398 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1399 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1400 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1401 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1402 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1403 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1404 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1405 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1406 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1407 */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1408  - AIF2 EQ Gains (1) */
-        { 0xFFC0, 0xFFC0, 0x0000 }, /* R1409  - AIF2 EQ Gains (2) */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1410  - AIF2 EQ Band 1 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1411  - AIF2 EQ Band 1 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1412  - AIF2 EQ Band 1 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1413  - AIF2 EQ Band 2 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1414  - AIF2 EQ Band 2 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1415  - AIF2 EQ Band 2 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1416  - AIF2 EQ Band 2 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1417  - AIF2 EQ Band 3 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1418  - AIF2 EQ Band 3 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1419  - AIF2 EQ Band 3 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1420  - AIF2 EQ Band 3 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1421  - AIF2 EQ Band 4 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1422  - AIF2 EQ Band 4 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1423  - AIF2 EQ Band 4 C */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1424  - AIF2 EQ Band 4 PG */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1425  - AIF2 EQ Band 5 A */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1426  - AIF2 EQ Band 5 B */
-        { 0xFFFF, 0xFFFF, 0x0000 }, /* R1427  - AIF2 EQ Band 5 PG */
-        { 0x0000, 0x0000, 0x0000 }, /* R1428 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1429 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1430 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1431 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1432 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1433 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1434 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1435 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1436 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1437 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1438 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1439 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1440 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1441 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1442 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1443 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1444 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1445 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1446 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1447 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1448 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1449 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1450 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1451 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1452 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1453 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1454 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1455 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1456 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1457 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1458 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1459 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1460 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1461 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1462 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1463 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1464 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1465 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1466 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1467 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1468 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1469 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1470 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1471 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1472 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1473 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1474 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1475 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1476 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1477 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1478 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1479 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1480 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1481 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1482 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1483 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1484 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1485 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1486 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1487 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1488 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1489 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1490 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1491 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1492 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1493 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1494 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1495 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1496 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1497 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1498 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1499 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1500 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1501 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1502 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1503 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1504 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1505 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1506 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1507 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1508 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1509 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1510 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1511 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1512 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1513 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1514 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1515 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1516 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1517 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1518 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1519 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1520 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1521 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1522 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1523 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1524 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1525 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1526 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1527 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1528 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1529 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1530 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1531 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1532 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1533 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1534 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1535 */
-        { 0x01EF, 0x01EF, 0x0000 }, /* R1536  - DAC1 Mixer Volumes */
-        { 0x0037, 0x0037, 0x0000 }, /* R1537  - DAC1 Left Mixer Routing */
-        { 0x0037, 0x0037, 0x0000 }, /* R1538  - DAC1 Right Mixer Routing */
-        { 0x01EF, 0x01EF, 0x0000 }, /* R1539  - DAC2 Mixer Volumes */
-        { 0x0037, 0x0037, 0x0000 }, /* R1540  - DAC2 Left Mixer Routing */
-        { 0x0037, 0x0037, 0x0000 }, /* R1541  - DAC2 Right Mixer Routing */
-        { 0x0003, 0x0003, 0x0000 }, /* R1542  - AIF1 ADC1 Left Mixer Routing */
-        { 0x0003, 0x0003, 0x0000 }, /* R1543  - AIF1 ADC1 Right Mixer Routing */
-        { 0x0003, 0x0003, 0x0000 }, /* R1544  - AIF1 ADC2 Left Mixer Routing */
-        { 0x0003, 0x0003, 0x0000 }, /* R1545  - AIF1 ADC2 Right mixer Routing */
-        { 0x0000, 0x0000, 0x0000 }, /* R1546 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1547 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1548 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1549 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1550 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1551 */
-        { 0x02FF, 0x03FF, 0x0000 }, /* R1552  - DAC1 Left Volume */
-        { 0x02FF, 0x03FF, 0x0000 }, /* R1553  - DAC1 Right Volume */
-        { 0x02FF, 0x03FF, 0x0000 }, /* R1554  - DAC2 Left Volume */
-        { 0x02FF, 0x03FF, 0x0000 }, /* R1555  - DAC2 Right Volume */
-        { 0x0003, 0x0003, 0x0000 }, /* R1556  - DAC Softmute */
-        { 0x0000, 0x0000, 0x0000 }, /* R1557 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1558 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1559 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1560 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1561 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1562 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1563 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1564 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1565 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1566 */
-        { 0x0000, 0x0000, 0x0000 }, /* R1567 */
-        { 0x0003, 0x0003, 0x0000 }, /* R1568  - Oversampling */
-        { 0x03C3, 0x03C3, 0x0000 }, /* R1569  - Sidetone */
-};
-
-static int wm8994_readable(unsigned int reg)
+static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
 {
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994 *control = wm8994->control_data;
+
         switch (reg) {
         case WM8994_GPIO_1:
         case WM8994_GPIO_2:
@@ -1694,18 +74,27 @@ static int wm8994_readable(unsigned int reg)
         case WM8994_INTERRUPT_STATUS_2:
         case WM8994_INTERRUPT_RAW_STATUS_2:
                 return 1;
+
+        case WM8958_DSP2_PROGRAM:
+        case WM8958_DSP2_CONFIG:
+        case WM8958_DSP2_EXECCONTROL:
+                if (control->type == WM8958)
+                        return 1;
+                else
+                        return 0;
+
         default:
                 break;
         }
 
-        if (reg >= ARRAY_SIZE(access_masks))
+        if (reg >= WM8994_CACHE_SIZE)
                 return 0;
-        return access_masks[reg].readable != 0;
+        return wm8994_access_masks[reg].readable != 0;
 }
 
-static int wm8994_volatile(unsigned int reg)
+static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
 {
-        if (reg >= WM8994_REG_CACHE_SIZE)
+        if (reg >= WM8994_CACHE_SIZE)
                 return 1;
 
         switch (reg) {
@@ -1716,6 +105,8 @@ static int wm8994_volatile(unsigned int reg)
         case WM8994_RATE_STATUS:
         case WM8994_LDO_1:
         case WM8994_LDO_2:
+        case WM8958_DSP2_EXECCONTROL:
+        case WM8958_MIC_DETECT_3:
                 return 1;
         default:
                 return 0;
@@ -1725,14 +116,16 @@ static int wm8994_volatile(unsigned int reg)
 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
         unsigned int value)
 {
-        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        int ret;
 
         BUG_ON(reg > WM8994_MAX_REGISTER);
 
-        if (!wm8994_volatile(reg))
-                wm8994->reg_cache[reg] = value;
-
-        dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
+        if (!wm8994_volatile(codec, reg)) {
+                ret = snd_soc_cache_write(codec, reg, value);
+                if (ret != 0)
+                        dev_err(codec->dev, "Cache write to %x failed: %d\n",
+                                reg, ret);
+        }
 
         return wm8994_reg_write(codec->control_data, reg, value);
 }
@@ -1740,14 +133,22 @@ static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 static unsigned int wm8994_read(struct snd_soc_codec *codec,
                                 unsigned int reg)
 {
-        u16 *reg_cache = codec->reg_cache;
+        unsigned int val;
+        int ret;
 
         BUG_ON(reg > WM8994_MAX_REGISTER);
 
-        if (wm8994_volatile(reg))
-                return wm8994_reg_read(codec->control_data, reg);
-        else
-                return reg_cache[reg];
+        if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
+            reg < codec->driver->reg_cache_size) {
+                ret = snd_soc_cache_read(codec, reg, &val);
+                if (ret >= 0)
+                        return val;
+                else
+                        dev_err(codec->dev, "Cache read from %x failed: %d\n",
+                                reg, ret);
+        }
+
+        return wm8994_reg_read(codec->control_data, reg);
 }
 
 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
@@ -1839,7 +240,7 @@ static int configure_clock(struct snd_soc_codec *codec)
 
         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 
-        snd_soc_dapm_sync(codec);
+        snd_soc_dapm_sync(&codec->dapm);
 
         return 0;
 }
@@ -1866,6 +267,19 @@ static const char *sidetone_hpf_text[] = {
 static const struct soc_enum sidetone_hpf =
         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 
+static const char *adc_hpf_text[] = {
+        "HiFi", "Voice 1", "Voice 2", "Voice 3"
+};
+
+static const struct soc_enum aif1adc1_hpf =
+        SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
+
+static const struct soc_enum aif1adc2_hpf =
+        SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
+
+static const struct soc_enum aif2adc_hpf =
+        SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
+
 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
@@ -1902,8 +316,6 @@ static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
         return snd_soc_put_volsw(kcontrol, ucontrol);
 }
 
-
-
 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 {
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
@@ -1942,7 +354,7 @@ static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
                                struct snd_ctl_elem_value *ucontrol)
 {
         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);  
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
         struct wm8994_pdata *pdata = wm8994->pdata;
         int drc = wm8994_get_drc(kcontrol->id.name);
         int value = ucontrol->value.integer.value[0];
@@ -2045,7 +457,7 @@ static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
                                          struct snd_ctl_elem_value *ucontrol)
 {
         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);  
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
         struct wm8994_pdata *pdata = wm8994->pdata;
         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
         int value = ucontrol->value.integer.value[0];
@@ -2075,6 +487,44 @@ static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
         return 0;
 }
 
+static const char *aif_chan_src_text[] = {
+        "Left", "Right"
+};
+
+static const struct soc_enum aif1adcl_src =
+        SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
+
+static const struct soc_enum aif1adcr_src =
+        SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
+
+static const struct soc_enum aif2adcl_src =
+        SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
+
+static const struct soc_enum aif2adcr_src =
+        SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
+
+static const struct soc_enum aif1dacl_src =
+        SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
+
+static const struct soc_enum aif1dacr_src =
+        SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
+
+static const struct soc_enum aif2dacl_src =
+        SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
+
+static const struct soc_enum aif2dacr_src =
+        SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
+
+static const char *osr_text[] = {
+        "Low Power", "High Performance",
+};
+
+static const struct soc_enum dac_osr =
+        SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
+
+static const struct soc_enum adc_osr =
+        SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
+
 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
@@ -2086,6 +536,16 @@ SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
                  WM8994_AIF2_ADC_RIGHT_VOLUME,
                  1, 119, 0, digital_tlv),
 
+SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
+SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
+SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
+SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
+
+SOC_ENUM("AIF1DACL Source", aif1dacl_src),
+SOC_ENUM("AIF1DACR Source", aif1dacr_src),
+SOC_ENUM("AIF2DACL Source", aif2dacl_src),
+SOC_ENUM("AIF2DACR Source", aif2dacr_src),
+
 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
@@ -2123,6 +583,18 @@ SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 
+SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
+SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
+
+SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
+SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
+
+SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
+SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
+
+SOC_ENUM("ADC OSR", adc_osr),
+SOC_ENUM("DAC OSR", dac_osr),
+
 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
@@ -2145,15 +617,15 @@ SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 
 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
                10, 15, 0, wm8994_3d_tlv),
-SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
+SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
            8, 1, 0),
 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
                10, 15, 0, wm8994_3d_tlv),
 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
            8, 1, 0),
-SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
+SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
                10, 15, 0, wm8994_3d_tlv),
-SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
+SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
            8, 1, 0),
 };
 
@@ -2192,6 +664,10 @@ SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
                eq_tlv),
 };
 
+static const struct snd_kcontrol_new wm8958_snd_controls[] = {
+SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
+};
+
 static int clk_sys_event(struct snd_soc_dapm_widget *w,
                          struct snd_kcontrol *kcontrol, int event)
 {
@@ -2211,6 +687,7 @@ static int clk_sys_event(struct snd_soc_dapm_widget *w,
 
 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 {
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
         int enable = 1;
         int source = 0;  /* GCC flow analysis can't track enable */
         int reg, reg_r;
@@ -2261,12 +738,128 @@ static void wm8994_update_class_w(struct snd_soc_codec *codec)
                                     WM8994_CP_DYN_PWR |
                                     WM8994_CP_DYN_SRC_SEL_MASK,
                                     source | WM8994_CP_DYN_PWR);
+                wm8994->hubs.class_w = true;
                 
         } else {
                 dev_dbg(codec->dev, "Class W disabled\n");
                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
                                     WM8994_CP_DYN_PWR, 0);
+                wm8994->hubs.class_w = false;
+        }
+}
+
+static int late_enable_ev(struct snd_soc_dapm_widget *w,
+                          struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                if (wm8994->aif1clk_enable) {
+                        snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+                                            WM8994_AIF1CLK_ENA_MASK,
+                                            WM8994_AIF1CLK_ENA);
+                        wm8994->aif1clk_enable = 0;
+                }
+                if (wm8994->aif2clk_enable) {
+                        snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+                                            WM8994_AIF2CLK_ENA_MASK,
+                                            WM8994_AIF2CLK_ENA);
+                        wm8994->aif2clk_enable = 0;
+                }
+                break;
+        }
+
+        /* We may also have postponed startup of DSP, handle that. */
+        wm8958_aif_ev(w, kcontrol, event);
+
+        return 0;
+}
+
+static int late_disable_ev(struct snd_soc_dapm_widget *w,
+                           struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMD:
+                if (wm8994->aif1clk_disable) {
+                        snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+                                            WM8994_AIF1CLK_ENA_MASK, 0);
+                        wm8994->aif1clk_disable = 0;
+                }
+                if (wm8994->aif2clk_disable) {
+                        snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+                                            WM8994_AIF2CLK_ENA_MASK, 0);
+                        wm8994->aif2clk_disable = 0;
+                }
+                break;
+        }
+
+        return 0;
+}
+
+static int aif1clk_ev(struct snd_soc_dapm_widget *w,
+                      struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                wm8994->aif1clk_enable = 1;
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                wm8994->aif1clk_disable = 1;
+                break;
+        }
+
+        return 0;
+}
+
+static int aif2clk_ev(struct snd_soc_dapm_widget *w,
+                      struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                wm8994->aif2clk_enable = 1;
+                break;
+        case SND_SOC_DAPM_POST_PMD:
+                wm8994->aif2clk_disable = 1;
+                break;
         }
+
+        return 0;
+}
+
+static int adc_mux_ev(struct snd_soc_dapm_widget *w,
+                      struct snd_kcontrol *kcontrol, int event)
+{
+        late_enable_ev(w, kcontrol, event);
+        return 0;
+}
+
+static int micbias_ev(struct snd_soc_dapm_widget *w,
+                      struct snd_kcontrol *kcontrol, int event)
+{
+        late_enable_ev(w, kcontrol, event);
+        return 0;
+}
+
+static int dac_ev(struct snd_soc_dapm_widget *w,
+                  struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        unsigned int mask = 1 << w->shift;
+
+        snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                            mask, mask);
+        return 0;
 }
 
 static const char *hp_mux_text[] = {
@@ -2284,7 +877,8 @@ static const char *hp_mux_text[] = {
 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
                               struct snd_ctl_elem_value *ucontrol)
 {
-        struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget *w = wlist->widgets[0];
         struct snd_soc_codec *codec = w->codec;
         int ret;
 
@@ -2411,7 +1005,8 @@ SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
                               struct snd_ctl_elem_value *ucontrol)
 {
-        struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget *w = wlist->widgets[0];
         struct snd_soc_codec *codec = w->codec;
         int ret;
 
@@ -2495,20 +1090,109 @@ static const struct snd_kcontrol_new aif2adc_mux =
         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
 
 static const char *aif3adc_text[] = {
-        "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT",
+        "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
 };
 
-static const struct soc_enum aif3adc_enum =
+static const struct soc_enum wm8994_aif3adc_enum =
         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
 
-static const struct snd_kcontrol_new aif3adc_mux =
-        SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum);
+static const struct snd_kcontrol_new wm8994_aif3adc_mux =
+        SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
+
+static const struct soc_enum wm8958_aif3adc_enum =
+        SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
+
+static const struct snd_kcontrol_new wm8958_aif3adc_mux =
+        SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
+
+static const char *mono_pcm_out_text[] = {
+        "None", "AIF2ADCL", "AIF2ADCR", 
+};
+
+static const struct soc_enum mono_pcm_out_enum =
+        SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
+
+static const struct snd_kcontrol_new mono_pcm_out_mux =
+        SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
+
+static const char *aif2dac_src_text[] = {
+        "AIF2", "AIF3",
+};
+
+/* Note that these two control shouldn't be simultaneously switched to AIF3 */
+static const struct soc_enum aif2dacl_src_enum =
+        SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
+
+static const struct snd_kcontrol_new aif2dacl_src_mux =
+        SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
+
+static const struct soc_enum aif2dacr_src_enum =
+        SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
+
+static const struct snd_kcontrol_new aif2dacr_src_mux =
+        SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
+
+static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
+SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
+        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
+        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
+
+SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
+};
+
+static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
+SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
+};
+
+static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
+SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
+        dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
+        dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
+        dac_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
+        dac_ev, SND_SOC_DAPM_PRE_PMU),
+};
+
+static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
+SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
+SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
+SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
+};
+
+static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
+SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
+                   adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
+SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
+                   adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
+};
+
+static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
+SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
+SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
+};
 
 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
 SND_SOC_DAPM_INPUT("DMIC1DAT"),
 SND_SOC_DAPM_INPUT("DMIC2DAT"),
 SND_SOC_DAPM_INPUT("Clock"),
 
+SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
+                      SND_SOC_DAPM_PRE_PMU),
+
 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 
@@ -2516,26 +1200,27 @@ SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
 
-SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
-SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
-
-SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
+SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
-SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
+SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
-SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
-                    WM8994_POWER_MANAGEMENT_5, 9, 0),
-SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
-                    WM8994_POWER_MANAGEMENT_5, 8, 0),
-
-SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
+SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
+                      WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
+                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
+                      WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
+                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
-SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
+SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
-SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0,
-                    WM8994_POWER_MANAGEMENT_5, 11, 0),
-SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0,
-                    WM8994_POWER_MANAGEMENT_5, 10, 0),
+SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
+                      WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
+                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
+                      WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
+                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 
 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
@@ -2564,19 +1249,21 @@ SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
                      WM8994_POWER_MANAGEMENT_4, 13, 0),
 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
                      WM8994_POWER_MANAGEMENT_4, 12, 0),
-SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0,
-                    WM8994_POWER_MANAGEMENT_5, 13, 0),
-SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0,
-                    WM8994_POWER_MANAGEMENT_5, 12, 0),
+SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
+                      WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
+                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
+                      WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
+                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 
 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
 
 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
-SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
 
 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
@@ -2595,14 +1282,6 @@ SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
 
-SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
-SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
-
-SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
-SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
-SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
-SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
-
 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
 
@@ -2614,8 +1293,18 @@ SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
 SND_SOC_DAPM_POST("Debug log", post_ev),
 };
 
-static const struct snd_soc_dapm_route intercon[] = {
+static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
+SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
+};
+
+static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
+SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
+SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
+SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
+SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
+};
 
+static const struct snd_soc_dapm_route intercon[] = {
         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
 
@@ -2723,9 +1412,6 @@ static const struct snd_soc_dapm_route intercon[] = {
         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
 
-        { "AIF2DACL", NULL, "AIF2DAC Mux" },
-        { "AIF2DACR", NULL, "AIF2DAC Mux" },
-
         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
@@ -2735,14 +1421,12 @@ static const struct snd_soc_dapm_route intercon[] = {
         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
 
         /* DAC1 inputs */
-        { "DAC1L", NULL, "DAC1L Mixer" },
         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
 
-        { "DAC1R", NULL, "DAC1R Mixer" },
         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
@@ -2751,7 +1435,6 @@ static const struct snd_soc_dapm_route intercon[] = {
 
         /* DAC2/AIF2 outputs  */
         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
-        { "DAC2L", NULL, "AIF2DAC2L Mixer" },
         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
@@ -2759,13 +1442,17 @@ static const struct snd_soc_dapm_route intercon[] = {
         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
 
         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
-        { "DAC2R", NULL, "AIF2DAC2R Mixer" },
         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
 
+        { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
+        { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
+        { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
+        { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
+
         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
 
         /* AIF3 output */
@@ -2798,6 +1485,55 @@ static const struct snd_soc_dapm_route intercon[] = {
         { "Right Headphone Mux", "DAC", "DAC1R" },
 };
 
+static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
+        { "DAC1L", NULL, "Late DAC1L Enable PGA" },
+        { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
+        { "DAC1R", NULL, "Late DAC1R Enable PGA" },
+        { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
+        { "DAC2L", NULL, "Late DAC2L Enable PGA" },
+        { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
+        { "DAC2R", NULL, "Late DAC2R Enable PGA" },
+        { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
+};
+
+static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
+        { "DAC1L", NULL, "DAC1L Mixer" },
+        { "DAC1R", NULL, "DAC1R Mixer" },
+        { "DAC2L", NULL, "AIF2DAC2L Mixer" },
+        { "DAC2R", NULL, "AIF2DAC2R Mixer" },
+};
+
+static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
+        { "AIF1DACDAT", NULL, "AIF2DACDAT" },
+        { "AIF2DACDAT", NULL, "AIF1DACDAT" },
+        { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
+        { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
+        { "MICBIAS1", NULL, "CLK_SYS" },
+        { "MICBIAS1", NULL, "MICBIAS Supply" },
+        { "MICBIAS2", NULL, "CLK_SYS" },
+        { "MICBIAS2", NULL, "MICBIAS Supply" },
+};
+
+static const struct snd_soc_dapm_route wm8994_intercon[] = {
+        { "AIF2DACL", NULL, "AIF2DAC Mux" },
+        { "AIF2DACR", NULL, "AIF2DAC Mux" },
+};
+
+static const struct snd_soc_dapm_route wm8958_intercon[] = {
+        { "AIF2DACL", NULL, "AIF2DACL Mux" },
+        { "AIF2DACR", NULL, "AIF2DACR Mux" },
+
+        { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
+        { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
+        { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
+        { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
+
+        { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
+        { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
+
+        { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
+};
+
 /* The size in bits of the FLL divide multiplied by 10
  * to allow rounding later */
 #define FIXED_FLL_SIZE ((1 << 16) * 10)
@@ -2881,10 +1617,9 @@ static int wm8994_get_fll_config(struct fll_div *fll,
         return 0;
 }
 
-static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
+static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
                           unsigned int freq_in, unsigned int freq_out)
 {
-        struct snd_soc_codec *codec = dai->codec;
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
         int reg_offset, ret;
         struct fll_div fll;
@@ -2914,6 +1649,7 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
                 /* Allow no source specification when stopping */
                 if (freq_out)
                         return -EINVAL;
+                src = wm8994->fll[id].src;
                 break;
         case WM8994_FLL_SRC_MCLK1:
         case WM8994_FLL_SRC_MCLK2:
@@ -2978,6 +1714,8 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
                                     reg);
+
+                msleep(5);
         }
 
         wm8994->fll[id].in = freq_in;
@@ -2995,8 +1733,15 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
         return 0;
 }
 
+
 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
 
+static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
+                          unsigned int freq_in, unsigned int freq_out)
+{
+        return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
+}
+
 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
                 int clk_id, unsigned int freq, int dir)
 {
@@ -3071,6 +1816,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
                                  enum snd_soc_bias_level level)
 {
+        struct wm8994 *control = codec->control_data;
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 
         switch (level) {
@@ -3084,16 +1830,36 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
-                        /* Tweak DC servo and DSP configuration for
-                         * improved performance. */
-                        if (wm8994->revision < 4) {
-                                /* Tweak DC servo and DSP configuration for
-                                 * improved performance. */
-                                snd_soc_write(codec, 0x102, 0x3);
-                                snd_soc_write(codec, 0x56, 0x3);
-                                snd_soc_write(codec, 0x817, 0);
-                                snd_soc_write(codec, 0x102, 0);
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        pm_runtime_get_sync(codec->dev);
+
+                        switch (control->type) {
+                        case WM8994:
+                                if (wm8994->revision < 4) {
+                                        /* Tweak DC servo and DSP
+                                         * configuration for improved
+                                         * performance. */
+                                        snd_soc_write(codec, 0x102, 0x3);
+                                        snd_soc_write(codec, 0x56, 0x3);
+                                        snd_soc_write(codec, 0x817, 0);
+                                        snd_soc_write(codec, 0x102, 0);
+                                }
+                                break;
+
+                        case WM8958:
+                                if (wm8994->revision == 0) {
+                                        /* Optimise performance for rev A */
+                                        snd_soc_write(codec, 0x102, 0x3);
+                                        snd_soc_write(codec, 0xcb, 0x81);
+                                        snd_soc_write(codec, 0x817, 0);
+                                        snd_soc_write(codec, 0x102, 0);
+
+                                        snd_soc_update_bits(codec,
+                                                            WM8958_CHARGE_PUMP_2,
+                                                            WM8958_CP_DISCH,
+                                                            WM8958_CP_DISCH);
+                                }
+                                break;
                         }
 
                         /* Discharge LINEOUT1 & 2 */
@@ -3128,7 +1894,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_OFF:
-                if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
                         /* Switch over to startup biases */
                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
                                             WM8994_BIAS_SRC |
@@ -3160,16 +1926,21 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
                                             WM8994_STARTUP_BIAS_ENA |
                                             WM8994_VMID_BUF_ENA |
                                             WM8994_VMID_RAMP_MASK, 0);
+
+                        wm8994->cur_fw = NULL;
+
+                        pm_runtime_put(codec->dev);
                 }
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 {
         struct snd_soc_codec *codec = dai->codec;
+        struct wm8994 *control = codec->control_data;
         int ms_reg;
         int aif1_reg;
         int ms = 0;
@@ -3254,6 +2025,13 @@ static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
                 return -EINVAL;
         }
 
+        /* The AIF2 format configuration needs to be mirrored to AIF3
+         * on WM8958 if it's in use so just do it all the time. */
+        if (control->type == WM8958 && dai->id == 2)
+                snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
+                                    WM8994_AIF1_LRCLK_INV |
+                                    WM8958_AIF3_FMT_MASK, aif1);
+
         snd_soc_update_bits(codec, aif1_reg,
                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
                             WM8994_AIF1_FMT_MASK,
@@ -3294,12 +2072,15 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
                             struct snd_soc_dai *dai)
 {
         struct snd_soc_codec *codec = dai->codec;
+        struct wm8994 *control = codec->control_data;
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
         int aif1_reg;
+        int aif2_reg;
         int bclk_reg;
         int lrclk_reg;
         int rate_reg;
         int aif1 = 0;
+        int aif2 = 0;
         int bclk = 0;
         int lrclk = 0;
         int rate_val = 0;
@@ -3310,24 +2091,38 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
         switch (dai->id) {
         case 1:
                 aif1_reg = WM8994_AIF1_CONTROL_1;
+                aif2_reg = WM8994_AIF1_CONTROL_2;
                 bclk_reg = WM8994_AIF1_BCLK;
                 rate_reg = WM8994_AIF1_RATE;
                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
-                    wm8994->lrclk_shared[0])
+                    wm8994->lrclk_shared[0]) {
                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
-                else
+                } else {
                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
+                        dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
+                }
                 break;
         case 2:
                 aif1_reg = WM8994_AIF2_CONTROL_1;
+                aif2_reg = WM8994_AIF2_CONTROL_2;
                 bclk_reg = WM8994_AIF2_BCLK;
                 rate_reg = WM8994_AIF2_RATE;
                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
-                    wm8994->lrclk_shared[1])
+                    wm8994->lrclk_shared[1]) {
                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
-                else
+                } else {
                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
+                        dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
+                }
                 break;
+        case 3:
+                switch (control->type) {
+                case WM8958:
+                        aif1_reg = WM8958_AIF3_CONTROL_1;
+                        break;
+                default:
+                        return 0;
+                }
         default:
                 return -EINVAL;
         }
@@ -3365,6 +2160,10 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
                 dai->id, wm8994->aifclk[id], bclk_rate);
 
+        if (params_channels(params) == 1 &&
+            (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
+                aif2 |= WM8994_AIF1_MONO;
+
         if (wm8994->aifclk[id] == 0) {
                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
                 return -EINVAL;
@@ -3408,6 +2207,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
                 lrclk, bclk_rate / lrclk);
 
         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
+        snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
                             lrclk);
@@ -3431,6 +2231,47 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
         return 0;
 }
 
+static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
+                                 struct snd_pcm_hw_params *params,
+                                 struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct wm8994 *control = codec->control_data;
+        int aif1_reg;
+        int aif1 = 0;
+
+        switch (dai->id) {
+        case 3:
+                switch (control->type) {
+                case WM8958:
+                        aif1_reg = WM8958_AIF3_CONTROL_1;
+                        break;
+                default:
+                        return 0;
+                }
+        default:
+                return 0;
+        }
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                aif1 |= 0x20;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                aif1 |= 0x40;
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                aif1 |= 0x60;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
+}
+
 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
 {
         struct snd_soc_codec *codec = codec_dai->codec;
@@ -3485,13 +2326,13 @@ static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
         else
                 val = 0;
 
-        return snd_soc_update_bits(codec, reg, mask, reg);
+        return snd_soc_update_bits(codec, reg, mask, val);
 }
 
 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
 
 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
-                        SNDRV_PCM_FMTBIT_S24_LE)
+                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 
 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
         .set_sysclk     = wm8994_set_dai_sysclk,
@@ -3512,23 +2353,24 @@ static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
 };
 
 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
+        .hw_params      = wm8994_aif3_hw_params,
         .set_tristate   = wm8994_set_tristate,
 };
 
-struct snd_soc_dai wm8994_dai[] = {
+static struct snd_soc_dai_driver wm8994_dai[] = {
         {
-                .name = "WM8994 AIF1",
+                .name = "wm8994-aif1",
                 .id = 1,
                 .playback = {
                         .stream_name = "AIF1 Playback",
-                        .channels_min = 2,
+                        .channels_min = 1,
                         .channels_max = 2,
                         .rates = WM8994_RATES,
                         .formats = WM8994_FORMATS,
                 },
                 .capture = {
                         .stream_name = "AIF1 Capture",
-                        .channels_min = 2,
+                        .channels_min = 1,
                         .channels_max = 2,
                         .rates = WM8994_RATES,
                         .formats = WM8994_FORMATS,
@@ -3536,18 +2378,18 @@ struct snd_soc_dai wm8994_dai[] = {
                 .ops = &wm8994_aif1_dai_ops,
         },
         {
-                .name = "WM8994 AIF2",
+                .name = "wm8994-aif2",
                 .id = 2,
                 .playback = {
                         .stream_name = "AIF2 Playback",
-                        .channels_min = 2,
+                        .channels_min = 1,
                         .channels_max = 2,
                         .rates = WM8994_RATES,
                         .formats = WM8994_FORMATS,
                 },
                 .capture = {
                         .stream_name = "AIF2 Capture",
-                        .channels_min = 2,
+                        .channels_min = 1,
                         .channels_max = 2,
                         .rates = WM8994_RATES,
                         .formats = WM8994_FORMATS,
@@ -3555,18 +2397,18 @@ struct snd_soc_dai wm8994_dai[] = {
                 .ops = &wm8994_aif2_dai_ops,
         },
         {
-                .name = "WM8994 AIF3",
+                .name = "wm8994-aif3",
                 .id = 3,
                 .playback = {
                         .stream_name = "AIF3 Playback",
-                        .channels_min = 2,
+                        .channels_min = 1,
                         .channels_max = 2,
                         .rates = WM8994_RATES,
                         .formats = WM8994_FORMATS,
                 },
                 .capture = {
                         .stream_name = "AIF3 Capture",
-                        .channels_min = 2,
+                        .channels_min = 1,
                         .channels_max = 2,
                         .rates = WM8994_RATES,
                         .formats = WM8994_FORMATS,
@@ -3574,20 +2416,28 @@ struct snd_soc_dai wm8994_dai[] = {
                 .ops = &wm8994_aif3_dai_ops,
         }
 };
-EXPORT_SYMBOL_GPL(wm8994_dai);
 
 #ifdef CONFIG_PM
-static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994 *control = codec->control_data;
         int i, ret;
 
+        switch (control->type) {
+        case WM8994:
+                snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
+                break;
+        case WM8958:
+                snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
+                                    WM8958_MICD_ENA, 0);
+                break;
+        }
+
         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
-                       sizeof(struct fll_config));
-                ret = wm8994_set_fll(&codec->dai[0], i + 1, 0, 0, 0);
+                       sizeof(struct wm8994_fll_config));
+                ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
                 if (ret < 0)
                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
                                  i + 1, ret);
@@ -3598,31 +2448,32 @@ static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
         return 0;
 }
 
-static int wm8994_resume(struct platform_device *pdev)
+static int wm8994_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
-        u16 *reg_cache = codec->reg_cache;
+        struct wm8994 *control = codec->control_data;
         int i, ret;
+        unsigned int val, mask;
+
+        if (wm8994->revision < 4) {
+                /* force a HW read */
+                val = wm8994_reg_read(codec->control_data,
+                                      WM8994_POWER_MANAGEMENT_5);
+
+                /* modify the cache only */
+                codec->cache_only = 1;
+                mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
+                        WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
+                val &= mask;
+                snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                                    mask, val);
+                codec->cache_only = 0;
+        }
 
         /* Restore the registers */
-        for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
-                switch (i) {
-                case WM8994_LDO_1:
-                case WM8994_LDO_2:
-                case WM8994_SOFTWARE_RESET:
-                        /* Handled by other MFD drivers */
-                        continue;
-                default:
-                        break;
-                }
-
-                if (!access_masks[i].writable)
-                        continue;
-
-                wm8994_reg_write(codec->control_data, i, reg_cache[i]);
-        }
+        ret = snd_soc_cache_sync(codec);
+        if (ret != 0)
+                dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
 
         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
@@ -3630,7 +2481,7 @@ static int wm8994_resume(struct platform_device *pdev)
                 if (!wm8994->fll_suspend[i].out)
                         continue;
 
-                ret = wm8994_set_fll(&codec->dai[0], i + 1,
+                ret = _wm8994_set_fll(codec, i + 1,
                                      wm8994->fll_suspend[i].src,
                                      wm8994->fll_suspend[i].in,
                                      wm8994->fll_suspend[i].out);
@@ -3639,6 +2490,19 @@ static int wm8994_resume(struct platform_device *pdev)
                                  i + 1, ret);
         }
 
+        switch (control->type) {
+        case WM8994:
+                if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
+                        snd_soc_update_bits(codec, WM8994_MICBIAS,
+                                            WM8994_MICD_ENA, WM8994_MICD_ENA);
+                break;
+        case WM8958:
+                if (wm8994->jack_cb)
+                        snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
+                                            WM8958_MICD_ENA, WM8958_MICD_ENA);
+                break;
+        }
+
         return 0;
 }
 #else
@@ -3648,7 +2512,7 @@ static int wm8994_resume(struct platform_device *pdev)
 
 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
 {
-        struct snd_soc_codec *codec = &wm8994->codec;
+        struct snd_soc_codec *codec = wm8994->codec;
         struct wm8994_pdata *pdata = wm8994->pdata;
         struct snd_kcontrol_new controls[] = {
                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
@@ -3706,16 +2570,16 @@ static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
 
-        ret = snd_soc_add_controls(&wm8994->codec, controls,
+        ret = snd_soc_add_controls(wm8994->codec, controls,
                                    ARRAY_SIZE(controls));
         if (ret != 0)
-                dev_err(wm8994->codec.dev,
+                dev_err(wm8994->codec->dev,
                         "Failed to add ReTune Mobile controls: %d\n", ret);
 }
 
 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
 {
-        struct snd_soc_codec *codec = &wm8994->codec;
+        struct snd_soc_codec *codec = wm8994->codec;
         struct wm8994_pdata *pdata = wm8994->pdata;
         int ret, i;
 
@@ -3747,7 +2611,7 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
                 wm8994->drc_texts = kmalloc(sizeof(char *)
                                             * pdata->num_drc_cfgs, GFP_KERNEL);
                 if (!wm8994->drc_texts) {
-                        dev_err(wm8994->codec.dev,
+                        dev_err(wm8994->codec->dev,
                                 "Failed to allocate %d DRC config texts\n",
                                 pdata->num_drc_cfgs);
                         return;
@@ -3759,10 +2623,10 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
                 wm8994->drc_enum.texts = wm8994->drc_texts;
 
-                ret = snd_soc_add_controls(&wm8994->codec, controls,
+                ret = snd_soc_add_controls(wm8994->codec, controls,
                                            ARRAY_SIZE(controls));
                 if (ret != 0)
-                        dev_err(wm8994->codec.dev,
+                        dev_err(wm8994->codec->dev,
                                 "Failed to add DRC mode controls: %d\n", ret);
 
                 for (i = 0; i < WM8994_NUM_DRC; i++)
@@ -3775,62 +2639,17 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
         if (pdata->num_retune_mobile_cfgs)
                 wm8994_handle_retune_mobile_pdata(wm8994);
         else
-                snd_soc_add_controls(&wm8994->codec, wm8994_eq_controls,
+                snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
                                      ARRAY_SIZE(wm8994_eq_controls));
-}
-
-static int wm8994_probe(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
-
-        if (wm8994_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
-        }
 
-        socdev->card->codec = wm8994_codec;
-        codec = wm8994_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                return ret;
+        for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
+                if (pdata->micbias[i]) {
+                        snd_soc_write(codec, WM8958_MICBIAS1 + i,
+                                pdata->micbias[i] & 0xffff);
+                }
         }
-
-        wm8994_handle_pdata(snd_soc_codec_get_drvdata(codec));
-
-        wm_hubs_add_analogue_controls(codec);
-        snd_soc_add_controls(codec, wm8994_snd_controls,
-                             ARRAY_SIZE(wm8994_snd_controls));
-        snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets,
-                                  ARRAY_SIZE(wm8994_dapm_widgets));
-        wm_hubs_add_analogue_routes(codec, 0, 0);
-        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
-
-        return 0;
-}
-
-static int wm8994_remove(struct platform_device *pdev)
-{
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
-        return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_wm8994 = {
-        .probe =        wm8994_probe,
-        .remove =       wm8994_remove,
-        .suspend =      wm8994_suspend,
-        .resume =       wm8994_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
-
 /**
  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
  *
@@ -3842,7 +2661,7 @@ EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
  *
  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
  * being used to bring out signals to the processor then only platform
- * data configuration is needed for WM8903 and processor GPIOs should
+ * data configuration is needed for WM8994 and processor GPIOs should
  * be configured using snd_soc_jack_add_gpios() instead.
  *
  * Configuration of detection levels is available via the micbias1_lvl
@@ -3853,8 +2672,12 @@ int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
 {
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
         struct wm8994_micdet *micdet;
+        struct wm8994 *control = codec->control_data;
         int reg;
 
+        if (control->type != WM8994)
+                return -EINVAL;
+
         switch (micbias) {
         case 1:
                 micdet = &wm8994->micdet[0];
@@ -3889,10 +2712,14 @@ EXPORT_SYMBOL_GPL(wm8994_mic_detect);
 static irqreturn_t wm8994_mic_irq(int irq, void *data)
 {
         struct wm8994_priv *priv = data;
-        struct snd_soc_codec *codec = &priv->codec;
+        struct snd_soc_codec *codec = priv->codec;
         int reg;
         int report;
 
+#ifndef CONFIG_SND_SOC_WM8994_MODULE
+        trace_snd_soc_jack_irq(dev_name(codec->dev));
+#endif
+
         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
         if (reg < 0) {
                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
@@ -3921,101 +2748,233 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
         return IRQ_HANDLED;
 }
 
-static int wm8994_codec_probe(struct platform_device *pdev)
+/* Default microphone detection handler for WM8958 - the user can
+ * override this if they wish.
+ */
+static void wm8958_default_micdet(u16 status, void *data)
 {
-        int ret;
-        struct wm8994_priv *wm8994;
-        struct snd_soc_codec *codec;
-        int i;
+        struct snd_soc_codec *codec = data;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        int report = 0;
+
+        /* If nothing present then clear our statuses */
+        if (!(status & WM8958_MICD_STS))
+                goto done;
+
+        report = SND_JACK_MICROPHONE;
+
+        /* Everything else is buttons; just assign slots */
+        if (status & 0x1c)
+                report |= SND_JACK_BTN_0;
+
+done:
+        snd_soc_jack_report(wm8994->micdet[0].jack, report,
+                            SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
+}
+
+/**
+ * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
+ *
+ * @codec:   WM8958 codec
+ * @jack:    jack to report detection events on
+ *
+ * Enable microphone detection functionality for the WM8958.  By
+ * default simple detection which supports the detection of up to 6
+ * buttons plus video and microphone functionality is supported.
+ *
+ * The WM8958 has an advanced jack detection facility which is able to
+ * support complex accessory detection, especially when used in
+ * conjunction with external circuitry.  In order to provide maximum
+ * flexiblity a callback is provided which allows a completely custom
+ * detection algorithm.
+ */
+int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
+                      wm8958_micdet_cb cb, void *cb_data)
+{
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994 *control = codec->control_data;
 
-        if (wm8994_codec) {
-                dev_err(&pdev->dev, "Another WM8994 is registered\n");
+        if (control->type != WM8958)
                 return -EINVAL;
+
+        if (jack) {
+                if (!cb) {
+                        dev_dbg(codec->dev, "Using default micdet callback\n");
+                        cb = wm8958_default_micdet;
+                        cb_data = codec;
+                }
+
+                wm8994->micdet[0].jack = jack;
+                wm8994->jack_cb = cb;
+                wm8994->jack_cb_data = cb_data;
+
+                snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
+                                    WM8958_MICD_ENA, WM8958_MICD_ENA);
+        } else {
+                snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
+                                    WM8958_MICD_ENA, 0);
         }
 
-        wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
-        if (!wm8994) {
-                dev_err(&pdev->dev, "Failed to allocate private data\n");
-                return -ENOMEM;
+        return 0;
+}
+EXPORT_SYMBOL_GPL(wm8958_mic_detect);
+
+static irqreturn_t wm8958_mic_irq(int irq, void *data)
+{
+        struct wm8994_priv *wm8994 = data;
+        struct snd_soc_codec *codec = wm8994->codec;
+        int reg;
+
+        reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
+        if (reg < 0) {
+                dev_err(codec->dev, "Failed to read mic detect status: %d\n",
+                        reg);
+                return IRQ_NONE;
         }
 
-        codec = &wm8994->codec;
+        if (!(reg & WM8958_MICD_VALID)) {
+                dev_dbg(codec->dev, "Mic detect data not valid\n");
+                goto out;
+        }
+
+#ifndef CONFIG_SND_SOC_WM8994_MODULE
+        trace_snd_soc_jack_irq(dev_name(codec->dev));
+#endif
+
+        if (wm8994->jack_cb)
+                wm8994->jack_cb(reg, wm8994->jack_cb_data);
+        else
+                dev_warn(codec->dev, "Accessory detection with no callback\n");
+
+out:
+        return IRQ_HANDLED;
+}
+
+static int wm8994_codec_probe(struct snd_soc_codec *codec)
+{
+        struct wm8994 *control;
+        struct wm8994_priv *wm8994;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret, i;
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
+        codec->control_data = dev_get_drvdata(codec->dev->parent);
+        control = codec->control_data;
 
+        wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
+        if (wm8994 == NULL)
+                return -ENOMEM;
         snd_soc_codec_set_drvdata(codec, wm8994);
-        codec->control_data = dev_get_drvdata(pdev->dev.parent);
-        codec->name = "WM8994";
-        codec->owner = THIS_MODULE;
-        codec->read = wm8994_read;
-        codec->write = wm8994_write;
-        codec->readable_register = wm8994_readable;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm8994_set_bias_level;
-        codec->dai = &wm8994_dai[0];
-        codec->num_dai = 3;
-        codec->reg_cache_size = WM8994_MAX_REGISTER;
-        codec->reg_cache = &wm8994->reg_cache;
-        codec->dev = &pdev->dev;
-
-        wm8994->pdata = pdev->dev.parent->platform_data;
-
-        /* Fill the cache with physical values we inherited; don't reset */
-        ret = wm8994_bulk_read(codec->control_data, 0,
-                               ARRAY_SIZE(wm8994->reg_cache) - 1,
-                               codec->reg_cache);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to fill register cache: %d\n",
-                        ret);
-                goto err;
-        }
 
-        /* Clear the cached values for unreadable/volatile registers to
-         * avoid potential confusion.
-         */
-        for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
-                if (wm8994_volatile(i) || !wm8994_readable(i))
-                        wm8994->reg_cache[i] = 0;
+        wm8994->pdata = dev_get_platdata(codec->dev->parent);
+        wm8994->codec = codec;
+
+        if (wm8994->pdata && wm8994->pdata->micdet_irq)
+                wm8994->micdet_irq = wm8994->pdata->micdet_irq;
+        else if (wm8994->pdata && wm8994->pdata->irq_base)
+                wm8994->micdet_irq = wm8994->pdata->irq_base +
+                                     WM8994_IRQ_MIC1_DET;
+
+        pm_runtime_enable(codec->dev);
+        pm_runtime_resume(codec->dev);
+
+        /* Read our current status back from the chip - we don't want to
+         * reset as this may interfere with the GPIO or LDO operation. */
+        for (i = 0; i < WM8994_CACHE_SIZE; i++) {
+                if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
+                        continue;
+
+                ret = wm8994_reg_read(codec->control_data, i);
+                if (ret <= 0)
+                        continue;
+
+                ret = snd_soc_cache_write(codec, i, ret);
+                if (ret != 0) {
+                        dev_err(codec->dev,
+                                "Failed to initialise cache for 0x%x: %d\n",
+                                i, ret);
+                        goto err;
+                }
+        }
 
         /* Set revision-specific configuration */
         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
-        switch (wm8994->revision) {
-        case 2:
-        case 3:
-                wm8994->hubs.dcs_codes = -5;
-                wm8994->hubs.hp_startup_mode = 1;
+        switch (control->type) {
+        case WM8994:
+                switch (wm8994->revision) {
+                case 2:
+                case 3:
+                        wm8994->hubs.dcs_codes = -5;
+                        wm8994->hubs.hp_startup_mode = 1;
+                        wm8994->hubs.dcs_readback_mode = 1;
+                        break;
+                default:
+                        wm8994->hubs.dcs_readback_mode = 1;
+                        break;
+                }
+
+        case WM8958:
                 wm8994->hubs.dcs_readback_mode = 1;
                 break;
+
         default:
-                wm8994->hubs.dcs_readback_mode = 1;
                 break;
         }
 
-        ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
-                                 wm8994_mic_irq, "Mic 1 detect", wm8994);
-        if (ret != 0)
-                dev_warn(&pdev->dev,
-                         "Failed to request Mic1 detect IRQ: %d\n", ret);
-
-        ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
-                                 wm8994_mic_irq, "Mic 1 short", wm8994);
-        if (ret != 0)
-                dev_warn(&pdev->dev,
-                         "Failed to request Mic1 short IRQ: %d\n", ret);
+        switch (control->type) {
+        case WM8994:
+                if (wm8994->micdet_irq) {
+                        ret = request_threaded_irq(wm8994->micdet_irq, NULL,
+                                                   wm8994_mic_irq,
+                                                   IRQF_TRIGGER_RISING,
+                                                   "Mic1 detect",
+                                                   wm8994);
+                        if (ret != 0)
+                                dev_warn(codec->dev,
+                                         "Failed to request Mic1 detect IRQ: %d\n",
+                                         ret);
+                }
 
-        ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
-                                 wm8994_mic_irq, "Mic 2 detect", wm8994);
-        if (ret != 0)
-                dev_warn(&pdev->dev,
-                         "Failed to request Mic2 detect IRQ: %d\n", ret);
+                ret = wm8994_request_irq(codec->control_data,
+                                         WM8994_IRQ_MIC1_SHRT,
+                                         wm8994_mic_irq, "Mic 1 short",
+                                         wm8994);
+                if (ret != 0)
+                        dev_warn(codec->dev,
+                                 "Failed to request Mic1 short IRQ: %d\n",
+                                 ret);
+
+                ret = wm8994_request_irq(codec->control_data,
+                                         WM8994_IRQ_MIC2_DET,
+                                         wm8994_mic_irq, "Mic 2 detect",
+                                         wm8994);
+                if (ret != 0)
+                        dev_warn(codec->dev,
+                                 "Failed to request Mic2 detect IRQ: %d\n",
+                                 ret);
+
+                ret = wm8994_request_irq(codec->control_data,
+                                         WM8994_IRQ_MIC2_SHRT,
+                                         wm8994_mic_irq, "Mic 2 short",
+                                         wm8994);
+                if (ret != 0)
+                        dev_warn(codec->dev,
+                                 "Failed to request Mic2 short IRQ: %d\n",
+                                 ret);
+                break;
 
-        ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
-                                 wm8994_mic_irq, "Mic 2 short", wm8994);
-        if (ret != 0)
-                dev_warn(&pdev->dev,
-                         "Failed to request Mic2 short IRQ: %d\n", ret);
+        case WM8958:
+                if (wm8994->micdet_irq) {
+                        ret = request_threaded_irq(wm8994->micdet_irq, NULL,
+                                                   wm8958_mic_irq,
+                                                   IRQF_TRIGGER_RISING,
+                                                   "Mic detect",
+                                                   wm8994);
+                        if (ret != 0)
+                                dev_warn(codec->dev,
+                                         "Failed to request Mic detect IRQ: %d\n",
+                                         ret);
+                }
+        }
 
         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
          * configured on init - if a system wants to do this dynamically
@@ -4045,28 +3004,39 @@ static int wm8994_codec_probe(struct platform_device *pdev)
                 wm8994->lrclk_shared[1] = 0;
         }
 
-        for (i = 0; i < ARRAY_SIZE(wm8994_dai); i++)
-                wm8994_dai[i].dev = codec->dev;
-
         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
-        wm8994_codec = codec;
-
         /* Latch volume updates (right only; we always do left then right). */
+        snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
+                            WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
+        snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
+                            WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
+        snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
+                            WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
+        snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
+                            WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
+        snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
+                            WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
+        snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
+                            WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
+        snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
+                            WM8994_DAC1_VU, WM8994_DAC1_VU);
         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
                             WM8994_DAC1_VU, WM8994_DAC1_VU);
+        snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
+                            WM8994_DAC2_VU, WM8994_DAC2_VU);
         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
                             WM8994_DAC2_VU, WM8994_DAC2_VU);
 
@@ -4088,59 +3058,181 @@ static int wm8994_codec_probe(struct platform_device *pdev)
 
         wm8994_update_class_w(codec);
 
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err_irq;
-        }
+        wm8994_handle_pdata(wm8994);
 
-        ret = snd_soc_register_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
-                goto err_codec;
+        wm_hubs_add_analogue_controls(codec);
+        snd_soc_add_controls(codec, wm8994_snd_controls,
+                             ARRAY_SIZE(wm8994_snd_controls));
+        snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
+                                  ARRAY_SIZE(wm8994_dapm_widgets));
+
+        switch (control->type) {
+        case WM8994:
+                snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
+                                          ARRAY_SIZE(wm8994_specific_dapm_widgets));
+                if (wm8994->revision < 4) {
+                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_lateclk_revd_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_adc_revd_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_dac_revd_widgets));
+                } else {
+                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
+                                                  ARRAY_SIZE(wm8994_lateclk_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
+                                                  ARRAY_SIZE(wm8994_adc_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
+                                                  ARRAY_SIZE(wm8994_dac_widgets));
+                }
+                break;
+        case WM8958:
+                snd_soc_add_controls(codec, wm8958_snd_controls,
+                                     ARRAY_SIZE(wm8958_snd_controls));
+                snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
+                                          ARRAY_SIZE(wm8958_dapm_widgets));
+                if (wm8994->revision < 1) {
+                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_lateclk_revd_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_adc_revd_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
+                                                  ARRAY_SIZE(wm8994_dac_revd_widgets));
+                } else {
+                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
+                                                  ARRAY_SIZE(wm8994_lateclk_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
+                                                  ARRAY_SIZE(wm8994_adc_widgets));
+                        snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
+                                                  ARRAY_SIZE(wm8994_dac_widgets));
+                }
+                break;
         }
+                
 
-        platform_set_drvdata(pdev, wm8994);
+        wm_hubs_add_analogue_routes(codec, 0, 0);
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
+
+        switch (control->type) {
+        case WM8994:
+                snd_soc_dapm_add_routes(dapm, wm8994_intercon,
+                                        ARRAY_SIZE(wm8994_intercon));
+
+                if (wm8994->revision < 4) {
+                        snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
+                                                ARRAY_SIZE(wm8994_revd_intercon));
+                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
+                                                ARRAY_SIZE(wm8994_lateclk_revd_intercon));
+                } else {
+                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
+                                                ARRAY_SIZE(wm8994_lateclk_intercon));
+                }
+                break;
+        case WM8958:
+                if (wm8994->revision < 1) {
+                        snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
+                                                ARRAY_SIZE(wm8994_revd_intercon));
+                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
+                                                ARRAY_SIZE(wm8994_lateclk_revd_intercon));
+                } else {
+                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
+                                                ARRAY_SIZE(wm8994_lateclk_intercon));
+                        snd_soc_dapm_add_routes(dapm, wm8958_intercon,
+                                                ARRAY_SIZE(wm8958_intercon));
+                }
+
+                wm8958_dsp2_init(codec);
+                break;
+        }
 
         return 0;
 
-err_codec:
-        snd_soc_unregister_codec(codec);
 err_irq:
         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
-        wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
+        if (wm8994->micdet_irq)
+                free_irq(wm8994->micdet_irq, wm8994);
 err:
         kfree(wm8994);
         return ret;
 }
 
-static int __devexit wm8994_codec_remove(struct platform_device *pdev)
+static int  wm8994_codec_remove(struct snd_soc_codec *codec)
 {
-        struct wm8994_priv *wm8994 = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = &wm8994->codec;
+        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+        struct wm8994 *control = codec->control_data;
 
         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
-        snd_soc_unregister_codec(&wm8994->codec);
-        wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
-        wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
-        wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
-        wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
+
+        pm_runtime_disable(codec->dev);
+
+        switch (control->type) {
+        case WM8994:
+                if (wm8994->micdet_irq)
+                        free_irq(wm8994->micdet_irq, wm8994);
+                wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
+                                wm8994);
+                wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
+                                wm8994);
+                wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
+                                wm8994);
+                break;
+
+        case WM8958:
+                if (wm8994->micdet_irq)
+                        free_irq(wm8994->micdet_irq, wm8994);
+                break;
+        }
+        if (wm8994->mbc)
+                release_firmware(wm8994->mbc);
+        if (wm8994->mbc_vss)
+                release_firmware(wm8994->mbc_vss);
+        if (wm8994->enh_eq)
+                release_firmware(wm8994->enh_eq);
+        kfree(wm8994->retune_mobile_texts);
+        kfree(wm8994->drc_texts);
         kfree(wm8994);
-        wm8994_codec = NULL;
 
         return 0;
 }
 
+static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
+        .probe =        wm8994_codec_probe,
+        .remove =       wm8994_codec_remove,
+        .suspend =      wm8994_suspend,
+        .resume =       wm8994_resume,
+        .read =         wm8994_read,
+        .write =        wm8994_write,
+        .readable_register = wm8994_readable,
+        .volatile_register = wm8994_volatile,
+        .set_bias_level = wm8994_set_bias_level,
+
+        .reg_cache_size = WM8994_CACHE_SIZE,
+        .reg_cache_default = wm8994_reg_defaults,
+        .reg_word_size = 2,
+        .compress_type = SND_SOC_RBTREE_COMPRESSION,
+};
+
+static int __devinit wm8994_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
+                        wm8994_dai, ARRAY_SIZE(wm8994_dai));
+}
+
+static int __devexit wm8994_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
 static struct platform_driver wm8994_codec_driver = {
         .driver = {
                    .name = "wm8994-codec",
                    .owner = THIS_MODULE,
                    },
-        .probe = wm8994_codec_probe,
-        .remove = __devexit_p(wm8994_codec_remove),
+        .probe = wm8994_probe,
+        .remove = __devexit_p(wm8994_remove),
 };
 
 static __init int wm8994_init(void)
diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h
index 2e0ca67a8df7..0a1db04b73bd 100644
--- a/sound/soc/codecs/wm8994.h
+++ b/sound/soc/codecs/wm8994.h
@@ -10,9 +10,9 @@
 #define _WM8994_H
 
 #include <sound/soc.h>
+#include <linux/firmware.h>
 
-extern struct snd_soc_codec_device soc_codec_dev_wm8994;
-extern struct snd_soc_dai wm8994_dai[];
+#include "wm_hubs.h"
 
 /* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
 #define WM8994_SYSCLK_MCLK1 1
@@ -31,7 +31,115 @@ extern struct snd_soc_dai wm8994_dai[];
 #define WM8994_FLL_SRC_LRCLK  3
 #define WM8994_FLL_SRC_BCLK   4
 
+typedef void (*wm8958_micdet_cb)(u16 status, void *data);
+
 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
                       int micbias, int det, int shrt);
+int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
+                      wm8958_micdet_cb cb, void *cb_data);
+
+#define WM8994_CACHE_SIZE 1570
+
+struct wm8994_access_mask {
+        unsigned short readable;   /* Mask of readable bits */
+        unsigned short writable;   /* Mask of writable bits */
+};
+
+extern const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE];
+extern const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE];
+
+int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
+                  struct snd_kcontrol *kcontrol, int event);
+
+void wm8958_dsp2_init(struct snd_soc_codec *codec);
+
+struct wm8994_micdet {
+        struct snd_soc_jack *jack;
+        int det;
+        int shrt;
+};
+
+/* codec private data */
+struct wm8994_fll_config {
+        int src;
+        int in;
+        int out;
+};
+
+#define WM8994_NUM_DRC 3
+#define WM8994_NUM_EQ  3
+
+struct wm8994_priv {
+        struct wm_hubs_data hubs;
+        enum snd_soc_control_type control_type;
+        void *control_data;
+        struct snd_soc_codec *codec;
+        int sysclk[2];
+        int sysclk_rate[2];
+        int mclk[2];
+        int aifclk[2];
+        struct wm8994_fll_config fll[2], fll_suspend[2];
+
+        int dac_rates[2];
+        int lrclk_shared[2];
+
+        int mbc_ena[3];
+        int hpf1_ena[3];
+        int hpf2_ena[3];
+        int vss_ena[3];
+        int enh_eq_ena[3];
+
+        /* Platform dependant DRC configuration */
+        const char **drc_texts;
+        int drc_cfg[WM8994_NUM_DRC];
+        struct soc_enum drc_enum;
+
+        /* Platform dependant ReTune mobile configuration */
+        int num_retune_mobile_texts;
+        const char **retune_mobile_texts;
+        int retune_mobile_cfg[WM8994_NUM_EQ];
+        struct soc_enum retune_mobile_enum;
+
+        /* Platform dependant MBC configuration */
+        int mbc_cfg;
+        const char **mbc_texts;
+        struct soc_enum mbc_enum;
+
+        /* Platform dependant VSS configuration */
+        int vss_cfg;
+        const char **vss_texts;
+        struct soc_enum vss_enum;
+
+        /* Platform dependant VSS HPF configuration */
+        int vss_hpf_cfg;
+        const char **vss_hpf_texts;
+        struct soc_enum vss_hpf_enum;
+
+        /* Platform dependant enhanced EQ configuration */
+        int enh_eq_cfg;
+        const char **enh_eq_texts;
+        struct soc_enum enh_eq_enum;
+
+        struct wm8994_micdet micdet[2];
+
+        wm8958_micdet_cb jack_cb;
+        void *jack_cb_data;
+        int micdet_irq;
+
+        int revision;
+        struct wm8994_pdata *pdata;
+
+        unsigned int aif1clk_enable:1;
+        unsigned int aif2clk_enable:1;
+
+        unsigned int aif1clk_disable:1;
+        unsigned int aif2clk_disable:1;
+
+        int dsp_active;
+        const struct firmware *cur_fw;
+        const struct firmware *mbc;
+        const struct firmware *mbc_vss;
+        const struct firmware *enh_eq;
+};
 
 #endif
diff --git a/sound/soc/codecs/wm8995.c b/sound/soc/codecs/wm8995.c
new file mode 100644
index 000000000000..5ad873fda814
--- /dev/null
+++ b/sound/soc/codecs/wm8995.c
@@ -0,0 +1,1911 @@
+/*
+ * wm8995.c  --  WM8995 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+ *
+ * Based on wm8994.c and wm_hubs.c by Mark Brown
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "wm8995.h"
+
+#define WM8995_NUM_SUPPLIES 8
+static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = {
+        "DCVDD",
+        "DBVDD1",
+        "DBVDD2",
+        "DBVDD3",
+        "AVDD1",
+        "AVDD2",
+        "CPVDD",
+        "MICVDD"
+};
+
+static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] = {
+        [0]     = 0x8995, [5]     = 0x0100, [16]    = 0x000b, [17]    = 0x000b,
+        [24]    = 0x02c0, [25]    = 0x02c0, [26]    = 0x02c0, [27]    = 0x02c0,
+        [28]    = 0x000f, [32]    = 0x0005, [33]    = 0x0005, [40]    = 0x0003,
+        [41]    = 0x0013, [48]    = 0x0004, [56]    = 0x09f8, [64]    = 0x1f25,
+        [69]    = 0x0004, [82]    = 0xaaaa, [84]    = 0x2a2a, [146]   = 0x0060,
+        [256]   = 0x0002, [257]   = 0x8004, [520]   = 0x0010, [528]   = 0x0083,
+        [529]   = 0x0083, [548]   = 0x0c80, [580]   = 0x0c80, [768]   = 0x4050,
+        [769]   = 0x4000, [771]   = 0x0040, [772]   = 0x0040, [773]   = 0x0040,
+        [774]   = 0x0004, [775]   = 0x0100, [784]   = 0x4050, [785]   = 0x4000,
+        [787]   = 0x0040, [788]   = 0x0040, [789]   = 0x0040, [1024]  = 0x00c0,
+        [1025]  = 0x00c0, [1026]  = 0x00c0, [1027]  = 0x00c0, [1028]  = 0x00c0,
+        [1029]  = 0x00c0, [1030]  = 0x00c0, [1031]  = 0x00c0, [1056]  = 0x0200,
+        [1057]  = 0x0010, [1058]  = 0x0200, [1059]  = 0x0010, [1088]  = 0x0098,
+        [1089]  = 0x0845, [1104]  = 0x0098, [1105]  = 0x0845, [1152]  = 0x6318,
+        [1153]  = 0x6300, [1154]  = 0x0fca, [1155]  = 0x0400, [1156]  = 0x00d8,
+        [1157]  = 0x1eb5, [1158]  = 0xf145, [1159]  = 0x0b75, [1160]  = 0x01c5,
+        [1161]  = 0x1c58, [1162]  = 0xf373, [1163]  = 0x0a54, [1164]  = 0x0558,
+        [1165]  = 0x168e, [1166]  = 0xf829, [1167]  = 0x07ad, [1168]  = 0x1103,
+        [1169]  = 0x0564, [1170]  = 0x0559, [1171]  = 0x4000, [1184]  = 0x6318,
+        [1185]  = 0x6300, [1186]  = 0x0fca, [1187]  = 0x0400, [1188]  = 0x00d8,
+        [1189]  = 0x1eb5, [1190]  = 0xf145, [1191]  = 0x0b75, [1192]  = 0x01c5,
+        [1193]  = 0x1c58, [1194]  = 0xf373, [1195]  = 0x0a54, [1196]  = 0x0558,
+        [1197]  = 0x168e, [1198]  = 0xf829, [1199]  = 0x07ad, [1200]  = 0x1103,
+        [1201]  = 0x0564, [1202]  = 0x0559, [1203]  = 0x4000, [1280]  = 0x00c0,
+        [1281]  = 0x00c0, [1282]  = 0x00c0, [1283]  = 0x00c0, [1312]  = 0x0200,
+        [1313]  = 0x0010, [1344]  = 0x0098, [1345]  = 0x0845, [1408]  = 0x6318,
+        [1409]  = 0x6300, [1410]  = 0x0fca, [1411]  = 0x0400, [1412]  = 0x00d8,
+        [1413]  = 0x1eb5, [1414]  = 0xf145, [1415]  = 0x0b75, [1416]  = 0x01c5,
+        [1417]  = 0x1c58, [1418]  = 0xf373, [1419]  = 0x0a54, [1420]  = 0x0558,
+        [1421]  = 0x168e, [1422]  = 0xf829, [1423]  = 0x07ad, [1424]  = 0x1103,
+        [1425]  = 0x0564, [1426]  = 0x0559, [1427]  = 0x4000, [1568]  = 0x0002,
+        [1792]  = 0xa100, [1793]  = 0xa101, [1794]  = 0xa101, [1795]  = 0xa101,
+        [1796]  = 0xa101, [1797]  = 0xa101, [1798]  = 0xa101, [1799]  = 0xa101,
+        [1800]  = 0xa101, [1801]  = 0xa101, [1802]  = 0xa101, [1803]  = 0xa101,
+        [1804]  = 0xa101, [1805]  = 0xa101, [1825]  = 0x0055, [1848]  = 0x3fff,
+        [1849]  = 0x1fff, [2049]  = 0x0001, [2050]  = 0x0069, [2056]  = 0x0002,
+        [2057]  = 0x0003, [2058]  = 0x0069, [12288] = 0x0001, [12289] = 0x0001,
+        [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f,
+        [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104,
+        [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050,
+        [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003,
+        [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b,
+        [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff,
+        [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff,
+        [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001,
+        [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001,
+        [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003,
+        [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401,
+        [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060,
+        [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff,
+        [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff,
+        [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff,
+        [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006,
+        [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006,
+        [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061,
+        [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003,
+        [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106,
+        [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502,
+        [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff,
+        [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff,
+        [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001,
+        [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f,
+        [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106,
+        [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050,
+        [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b,
+        [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff,
+        [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff,
+        [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff,
+        [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100,
+        [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff,
+        [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff,
+        [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff,
+        [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff,
+        [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102,
+        [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff,
+        [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff,
+        [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff,
+        [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff,
+        [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601,
+        [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304,
+        [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100
+};
+
+struct fll_config {
+        int src;
+        int in;
+        int out;
+};
+
+struct wm8995_priv {
+        enum snd_soc_control_type control_type;
+        int sysclk[2];
+        int mclk[2];
+        int aifclk[2];
+        struct fll_config fll[2], fll_suspend[2];
+        struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES];
+        struct notifier_block disable_nb[WM8995_NUM_SUPPLIES];
+        struct snd_soc_codec *codec;
+};
+
+/*
+ * We can't use the same notifier block for more than one supply and
+ * there's no way I can see to get from a callback to the caller
+ * except container_of().
+ */
+#define WM8995_REGULATOR_EVENT(n) \
+static int wm8995_regulator_event_##n(struct notifier_block *nb, \
+                                      unsigned long event, void *data)    \
+{ \
+        struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \
+                                     disable_nb[n]); \
+        if (event & REGULATOR_EVENT_DISABLE) { \
+                wm8995->codec->cache_sync = 1; \
+        } \
+        return 0; \
+}
+
+WM8995_REGULATOR_EVENT(0)
+WM8995_REGULATOR_EVENT(1)
+WM8995_REGULATOR_EVENT(2)
+WM8995_REGULATOR_EVENT(3)
+WM8995_REGULATOR_EVENT(4)
+WM8995_REGULATOR_EVENT(5)
+WM8995_REGULATOR_EVENT(6)
+WM8995_REGULATOR_EVENT(7)
+
+static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
+static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
+static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
+static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
+
+static const char *in1l_text[] = {
+        "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
+};
+
+static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
+                                  2, in1l_text);
+
+static const char *in1r_text[] = {
+        "Differential", "Single-ended IN1RN", "Single-ended IN1RP"
+};
+
+static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
+                                  0, in1r_text);
+
+static const char *dmic_src_text[] = {
+        "DMICDAT1", "DMICDAT2", "DMICDAT3"
+};
+
+static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
+                                  8, dmic_src_text);
+static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
+                                  6, dmic_src_text);
+
+static const struct snd_kcontrol_new wm8995_snd_controls[] = {
+        SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
+                WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
+        SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
+                WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
+
+        SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
+                WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
+        SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
+                WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
+
+        SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
+                WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
+        SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
+                WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
+        SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
+                WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
+
+        SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
+                WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
+
+        SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
+                4, 3, 0, in1l_boost_tlv),
+
+        SOC_ENUM("IN1L Mode", in1l_enum),
+        SOC_ENUM("IN1R Mode", in1r_enum),
+
+        SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
+        SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
+
+        SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
+                24, 0, sidetone_tlv),
+        SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
+                24, 0, sidetone_tlv),
+
+        SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
+                WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
+        SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
+                WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
+        SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
+                WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
+};
+
+static void wm8995_update_class_w(struct snd_soc_codec *codec)
+{
+        int enable = 1;
+        int source = 0;  /* GCC flow analysis can't track enable */
+        int reg, reg_r;
+
+        /* We also need the same setting for L/R and only one path */
+        reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING);
+        switch (reg) {
+        case WM8995_AIF2DACL_TO_DAC1L:
+                dev_dbg(codec->dev, "Class W source AIF2DAC\n");
+                source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
+                break;
+        case WM8995_AIF1DAC2L_TO_DAC1L:
+                dev_dbg(codec->dev, "Class W source AIF1DAC2\n");
+                source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
+                break;
+        case WM8995_AIF1DAC1L_TO_DAC1L:
+                dev_dbg(codec->dev, "Class W source AIF1DAC1\n");
+                source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
+                break;
+        default:
+                dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg);
+                enable = 0;
+                break;
+        }
+
+        reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING);
+        if (reg_r != reg) {
+                dev_dbg(codec->dev, "Left and right DAC mixers different\n");
+                enable = 0;
+        }
+
+        if (enable) {
+                dev_dbg(codec->dev, "Class W enabled\n");
+                snd_soc_update_bits(codec, WM8995_CLASS_W_1,
+                                    WM8995_CP_DYN_PWR_MASK |
+                                    WM8995_CP_DYN_SRC_SEL_MASK,
+                                    source | WM8995_CP_DYN_PWR);
+        } else {
+                dev_dbg(codec->dev, "Class W disabled\n");
+                snd_soc_update_bits(codec, WM8995_CLASS_W_1,
+                                    WM8995_CP_DYN_PWR_MASK, 0);
+        }
+}
+
+static int check_clk_sys(struct snd_soc_dapm_widget *source,
+                         struct snd_soc_dapm_widget *sink)
+{
+        unsigned int reg;
+        const char *clk;
+
+        reg = snd_soc_read(source->codec, WM8995_CLOCKING_1);
+        /* Check what we're currently using for CLK_SYS */
+        if (reg & WM8995_SYSCLK_SRC)
+                clk = "AIF2CLK";
+        else
+                clk = "AIF1CLK";
+        return !strcmp(source->name, clk);
+}
+
+static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
+                              struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+        struct snd_soc_dapm_widget *w = wlist->widgets[0];
+        struct snd_soc_codec *codec;
+        int ret;
+
+        codec = w->codec;
+        ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
+        wm8995_update_class_w(codec);
+        return ret;
+}
+
+static int hp_supply_event(struct snd_soc_dapm_widget *w,
+                           struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec;
+        struct wm8995_priv *wm8995;
+
+        codec = w->codec;
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                /* Enable the headphone amp */
+                snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
+                                    WM8995_HPOUT1L_ENA_MASK |
+                                    WM8995_HPOUT1R_ENA_MASK,
+                                    WM8995_HPOUT1L_ENA |
+                                    WM8995_HPOUT1R_ENA);
+
+                /* Enable the second stage */
+                snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
+                                    WM8995_HPOUT1L_DLY_MASK |
+                                    WM8995_HPOUT1R_DLY_MASK,
+                                    WM8995_HPOUT1L_DLY |
+                                    WM8995_HPOUT1R_DLY);
+                break;
+        case SND_SOC_DAPM_PRE_PMD:
+                snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
+                                    WM8995_CP_ENA_MASK, 0);
+                break;
+        }
+
+        return 0;
+}
+
+static void dc_servo_cmd(struct snd_soc_codec *codec,
+                         unsigned int reg, unsigned int val, unsigned int mask)
+{
+        int timeout = 10;
+
+        dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
+                __func__, reg, val, mask);
+
+        snd_soc_write(codec, reg, val);
+        while (timeout--) {
+                msleep(10);
+                val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0);
+                if ((val & mask) == mask)
+                        return;
+        }
+
+        dev_err(codec->dev, "Timed out waiting for DC Servo\n");
+}
+
+static int hp_event(struct snd_soc_dapm_widget *w,
+                    struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec;
+        unsigned int reg;
+
+        codec = w->codec;
+        reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1);
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
+                                    WM8995_CP_ENA_MASK, WM8995_CP_ENA);
+
+                msleep(5);
+
+                snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
+                                    WM8995_HPOUT1L_ENA_MASK |
+                                    WM8995_HPOUT1R_ENA_MASK,
+                                    WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
+
+                udelay(20);
+
+                reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
+                snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
+
+                snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
+                              WM8995_DCS_ENA_CHAN_1);
+
+                dc_servo_cmd(codec, WM8995_DC_SERVO_2,
+                             WM8995_DCS_TRIG_STARTUP_0 |
+                             WM8995_DCS_TRIG_STARTUP_1,
+                             WM8995_DCS_TRIG_DAC_WR_0 |
+                             WM8995_DCS_TRIG_DAC_WR_1);
+
+                reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
+                       WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
+                snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
+
+                break;
+        case SND_SOC_DAPM_PRE_PMD:
+                snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
+                                    WM8995_HPOUT1L_OUTP_MASK |
+                                    WM8995_HPOUT1R_OUTP_MASK |
+                                    WM8995_HPOUT1L_RMV_SHORT_MASK |
+                                    WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
+
+                snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
+                                    WM8995_HPOUT1L_DLY_MASK |
+                                    WM8995_HPOUT1R_DLY_MASK, 0);
+
+                snd_soc_write(codec, WM8995_DC_SERVO_1, 0);
+
+                snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
+                                    WM8995_HPOUT1L_ENA_MASK |
+                                    WM8995_HPOUT1R_ENA_MASK,
+                                    0);
+                break;
+        }
+
+        return 0;
+}
+
+static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
+{
+        struct wm8995_priv *wm8995;
+        int rate;
+        int reg1 = 0;
+        int offset;
+
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+
+        if (aif)
+                offset = 4;
+        else
+                offset = 0;
+
+        switch (wm8995->sysclk[aif]) {
+        case WM8995_SYSCLK_MCLK1:
+                rate = wm8995->mclk[0];
+                break;
+        case WM8995_SYSCLK_MCLK2:
+                reg1 |= 0x8;
+                rate = wm8995->mclk[1];
+                break;
+        case WM8995_SYSCLK_FLL1:
+                reg1 |= 0x10;
+                rate = wm8995->fll[0].out;
+                break;
+        case WM8995_SYSCLK_FLL2:
+                reg1 |= 0x18;
+                rate = wm8995->fll[1].out;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (rate >= 13500000) {
+                rate /= 2;
+                reg1 |= WM8995_AIF1CLK_DIV;
+
+                dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
+                        aif + 1, rate);
+        }
+
+        wm8995->aifclk[aif] = rate;
+
+        snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset,
+                            WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
+                            reg1);
+        return 0;
+}
+
+static int configure_clock(struct snd_soc_codec *codec)
+{
+        struct wm8995_priv *wm8995;
+        int old, new;
+
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+
+        /* Bring up the AIF clocks first */
+        configure_aif_clock(codec, 0);
+        configure_aif_clock(codec, 1);
+
+        /*
+         * Then switch CLK_SYS over to the higher of them; a change
+         * can only happen as a result of a clocking change which can
+         * only be made outside of DAPM so we can safely redo the
+         * clocking.
+         */
+
+        /* If they're equal it doesn't matter which is used */
+        if (wm8995->aifclk[0] == wm8995->aifclk[1])
+                return 0;
+
+        if (wm8995->aifclk[0] < wm8995->aifclk[1])
+                new = WM8995_SYSCLK_SRC;
+        else
+                new = 0;
+
+        old = snd_soc_read(codec, WM8995_CLOCKING_1) & WM8995_SYSCLK_SRC;
+
+        /* If there's no change then we're done. */
+        if (old == new)
+                return 0;
+
+        snd_soc_update_bits(codec, WM8995_CLOCKING_1,
+                            WM8995_SYSCLK_SRC_MASK, new);
+
+        snd_soc_dapm_sync(&codec->dapm);
+
+        return 0;
+}
+
+static int clk_sys_event(struct snd_soc_dapm_widget *w,
+                         struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec;
+
+        codec = w->codec;
+
+        switch (event) {
+        case SND_SOC_DAPM_PRE_PMU:
+                return configure_clock(codec);
+
+        case SND_SOC_DAPM_POST_PMD:
+                configure_clock(codec);
+                break;
+        }
+
+        return 0;
+}
+
+static const char *sidetone_text[] = {
+        "ADC/DMIC1", "DMIC2",
+};
+
+static const struct soc_enum sidetone1_enum =
+        SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text);
+
+static const struct snd_kcontrol_new sidetone1_mux =
+        SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
+
+static const struct soc_enum sidetone2_enum =
+        SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text);
+
+static const struct snd_kcontrol_new sidetone2_mux =
+        SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
+
+static const struct snd_kcontrol_new aif1adc1l_mix[] = {
+        SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
+                1, 1, 0),
+        SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new aif1adc1r_mix[] = {
+        SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
+                1, 1, 0),
+        SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new aif1adc2l_mix[] = {
+        SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
+                1, 1, 0),
+        SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new aif1adc2r_mix[] = {
+        SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
+                1, 1, 0),
+        SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dac1l_mix[] = {
+        WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
+                5, 1, 0),
+        WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
+                4, 1, 0),
+        WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
+                2, 1, 0),
+        WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
+                1, 1, 0),
+        WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new dac1r_mix[] = {
+        WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
+                5, 1, 0),
+        WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
+                4, 1, 0),
+        WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
+                2, 1, 0),
+        WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
+                1, 1, 0),
+        WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new aif2dac2l_mix[] = {
+        SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
+                5, 1, 0),
+        SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
+                4, 1, 0),
+        SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
+                2, 1, 0),
+        SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
+                1, 1, 0),
+        SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new aif2dac2r_mix[] = {
+        SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
+                5, 1, 0),
+        SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
+                4, 1, 0),
+        SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
+                2, 1, 0),
+        SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
+                1, 1, 0),
+        SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
+                0, 1, 0),
+};
+
+static const struct snd_kcontrol_new in1l_pga =
+        SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
+
+static const struct snd_kcontrol_new in1r_pga =
+        SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
+
+static const char *adc_mux_text[] = {
+        "ADC",
+        "DMIC",
+};
+
+static const struct soc_enum adc_enum =
+        SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
+
+static const struct snd_kcontrol_new adcl_mux =
+        SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
+
+static const struct snd_kcontrol_new adcr_mux =
+        SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
+
+static const char *spk_src_text[] = {
+        "DAC1L", "DAC1R", "DAC2L", "DAC2R"
+};
+
+static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
+                                  0, spk_src_text);
+static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
+                                  0, spk_src_text);
+static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
+                                  0, spk_src_text);
+static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
+                                  0, spk_src_text);
+
+static const struct snd_kcontrol_new spk1l_mux =
+        SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
+static const struct snd_kcontrol_new spk1r_mux =
+        SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
+static const struct snd_kcontrol_new spk2l_mux =
+        SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
+static const struct snd_kcontrol_new spk2r_mux =
+        SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
+
+static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
+        SND_SOC_DAPM_INPUT("DMIC1DAT"),
+        SND_SOC_DAPM_INPUT("DMIC2DAT"),
+
+        SND_SOC_DAPM_INPUT("IN1L"),
+        SND_SOC_DAPM_INPUT("IN1R"),
+
+        SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
+                &in1l_pga, 1),
+        SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
+                &in1r_pga, 1),
+
+        SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0),
+        SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0),
+
+        SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
+                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+        SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
+                WM8995_POWER_MANAGEMENT_3, 9, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
+                WM8995_POWER_MANAGEMENT_3, 8, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
+        SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
+                0, WM8995_POWER_MANAGEMENT_3, 11, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
+                0, WM8995_POWER_MANAGEMENT_3, 10, 0),
+
+        SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0,
+                &adcl_mux),
+        SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
+                &adcr_mux),
+
+        SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
+        SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
+        SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
+        SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
+
+        SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
+        SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
+
+        SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
+                aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
+        SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
+                aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
+        SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
+                aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
+        SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
+                aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
+
+        SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
+                9, 0),
+        SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
+                8, 0),
+        SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
+                0, 0),
+
+        SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
+                11, 0),
+        SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
+                10, 0),
+
+        SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
+                aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
+        SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
+                aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
+
+        SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
+        SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
+        SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
+        SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
+
+        SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
+                ARRAY_SIZE(dac1l_mix)),
+        SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
+                ARRAY_SIZE(dac1r_mix)),
+
+        SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
+        SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
+
+        SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+                hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+        SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
+                hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+
+        SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
+                4, 0, &spk1l_mux),
+        SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
+                4, 0, &spk1r_mux),
+        SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
+                4, 0, &spk2l_mux),
+        SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
+                4, 0, &spk2r_mux),
+
+        SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
+
+        SND_SOC_DAPM_OUTPUT("HP1L"),
+        SND_SOC_DAPM_OUTPUT("HP1R"),
+        SND_SOC_DAPM_OUTPUT("SPK1L"),
+        SND_SOC_DAPM_OUTPUT("SPK1R"),
+        SND_SOC_DAPM_OUTPUT("SPK2L"),
+        SND_SOC_DAPM_OUTPUT("SPK2R")
+};
+
+static const struct snd_soc_dapm_route wm8995_intercon[] = {
+        { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
+        { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
+
+        { "DSP1CLK", NULL, "CLK_SYS" },
+        { "DSP2CLK", NULL, "CLK_SYS" },
+        { "SYSDSPCLK", NULL, "CLK_SYS" },
+
+        { "AIF1ADC1L", NULL, "AIF1CLK" },
+        { "AIF1ADC1L", NULL, "DSP1CLK" },
+        { "AIF1ADC1R", NULL, "AIF1CLK" },
+        { "AIF1ADC1R", NULL, "DSP1CLK" },
+        { "AIF1ADC1R", NULL, "SYSDSPCLK" },
+
+        { "AIF1ADC2L", NULL, "AIF1CLK" },
+        { "AIF1ADC2L", NULL, "DSP1CLK" },
+        { "AIF1ADC2R", NULL, "AIF1CLK" },
+        { "AIF1ADC2R", NULL, "DSP1CLK" },
+        { "AIF1ADC2R", NULL, "SYSDSPCLK" },
+
+        { "DMIC1L", NULL, "DMIC1DAT" },
+        { "DMIC1L", NULL, "CLK_SYS" },
+        { "DMIC1R", NULL, "DMIC1DAT" },
+        { "DMIC1R", NULL, "CLK_SYS" },
+        { "DMIC2L", NULL, "DMIC2DAT" },
+        { "DMIC2L", NULL, "CLK_SYS" },
+        { "DMIC2R", NULL, "DMIC2DAT" },
+        { "DMIC2R", NULL, "CLK_SYS" },
+
+        { "ADCL", NULL, "AIF1CLK" },
+        { "ADCL", NULL, "DSP1CLK" },
+        { "ADCL", NULL, "SYSDSPCLK" },
+
+        { "ADCR", NULL, "AIF1CLK" },
+        { "ADCR", NULL, "DSP1CLK" },
+        { "ADCR", NULL, "SYSDSPCLK" },
+
+        { "IN1L PGA", "IN1L Switch", "IN1L" },
+        { "IN1R PGA", "IN1R Switch", "IN1R" },
+        { "IN1L PGA", NULL, "LDO2" },
+        { "IN1R PGA", NULL, "LDO2" },
+
+        { "ADCL", NULL, "IN1L PGA" },
+        { "ADCR", NULL, "IN1R PGA" },
+
+        { "ADCL Mux", "ADC", "ADCL" },
+        { "ADCL Mux", "DMIC", "DMIC1L" },
+        { "ADCR Mux", "ADC", "ADCR" },
+        { "ADCR Mux", "DMIC", "DMIC1R" },
+
+        /* AIF1 outputs */
+        { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
+        { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
+
+        { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
+        { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
+
+        { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
+        { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
+
+        { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
+        { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
+
+        /* Sidetone */
+        { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
+        { "Left Sidetone", "DMIC2", "AIF1ADC2L" },
+        { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
+        { "Right Sidetone", "DMIC2", "AIF1ADC2R" },
+
+        { "AIF1DAC1L", NULL, "AIF1CLK" },
+        { "AIF1DAC1L", NULL, "DSP1CLK" },
+        { "AIF1DAC1R", NULL, "AIF1CLK" },
+        { "AIF1DAC1R", NULL, "DSP1CLK" },
+        { "AIF1DAC1R", NULL, "SYSDSPCLK" },
+
+        { "AIF1DAC2L", NULL, "AIF1CLK" },
+        { "AIF1DAC2L", NULL, "DSP1CLK" },
+        { "AIF1DAC2R", NULL, "AIF1CLK" },
+        { "AIF1DAC2R", NULL, "DSP1CLK" },
+        { "AIF1DAC2R", NULL, "SYSDSPCLK" },
+
+        { "DAC1L", NULL, "AIF1CLK" },
+        { "DAC1L", NULL, "DSP1CLK" },
+        { "DAC1L", NULL, "SYSDSPCLK" },
+
+        { "DAC1R", NULL, "AIF1CLK" },
+        { "DAC1R", NULL, "DSP1CLK" },
+        { "DAC1R", NULL, "SYSDSPCLK" },
+
+        { "AIF1DAC1L", NULL, "AIF1DACDAT" },
+        { "AIF1DAC1R", NULL, "AIF1DACDAT" },
+        { "AIF1DAC2L", NULL, "AIF1DACDAT" },
+        { "AIF1DAC2R", NULL, "AIF1DACDAT" },
+
+        /* DAC1 inputs */
+        { "DAC1L", NULL, "DAC1L Mixer" },
+        { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
+        { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
+        { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
+        { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
+
+        { "DAC1R", NULL, "DAC1R Mixer" },
+        { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
+        { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
+        { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
+        { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
+
+        /* DAC2/AIF2 outputs */
+        { "DAC2L", NULL, "AIF2DAC2L Mixer" },
+        { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
+        { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
+
+        { "DAC2R", NULL, "AIF2DAC2R Mixer" },
+        { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
+        { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
+
+        /* Output stages */
+        { "Headphone PGA", NULL, "DAC1L" },
+        { "Headphone PGA", NULL, "DAC1R" },
+
+        { "Headphone PGA", NULL, "DAC2L" },
+        { "Headphone PGA", NULL, "DAC2R" },
+
+        { "Headphone PGA", NULL, "Headphone Supply" },
+        { "Headphone PGA", NULL, "CLK_SYS" },
+        { "Headphone PGA", NULL, "LDO2" },
+
+        { "HP1L", NULL, "Headphone PGA" },
+        { "HP1R", NULL, "Headphone PGA" },
+
+        { "SPK1L Driver", "DAC1L", "DAC1L" },
+        { "SPK1L Driver", "DAC1R", "DAC1R" },
+        { "SPK1L Driver", "DAC2L", "DAC2L" },
+        { "SPK1L Driver", "DAC2R", "DAC2R" },
+        { "SPK1L Driver", NULL, "CLK_SYS" },
+
+        { "SPK1R Driver", "DAC1L", "DAC1L" },
+        { "SPK1R Driver", "DAC1R", "DAC1R" },
+        { "SPK1R Driver", "DAC2L", "DAC2L" },
+        { "SPK1R Driver", "DAC2R", "DAC2R" },
+        { "SPK1R Driver", NULL, "CLK_SYS" },
+
+        { "SPK2L Driver", "DAC1L", "DAC1L" },
+        { "SPK2L Driver", "DAC1R", "DAC1R" },
+        { "SPK2L Driver", "DAC2L", "DAC2L" },
+        { "SPK2L Driver", "DAC2R", "DAC2R" },
+        { "SPK2L Driver", NULL, "CLK_SYS" },
+
+        { "SPK2R Driver", "DAC1L", "DAC1L" },
+        { "SPK2R Driver", "DAC1R", "DAC1R" },
+        { "SPK2R Driver", "DAC2L", "DAC2L" },
+        { "SPK2R Driver", "DAC2R", "DAC2R" },
+        { "SPK2R Driver", NULL, "CLK_SYS" },
+
+        { "SPK1L", NULL, "SPK1L Driver" },
+        { "SPK1R", NULL, "SPK1R Driver" },
+        { "SPK2L", NULL, "SPK2L Driver" },
+        { "SPK2R", NULL, "SPK2R Driver" }
+};
+
+static int wm8995_volatile(struct snd_soc_codec *codec, unsigned int reg)
+{
+        /* out of bounds registers are generally considered
+         * volatile to support register banks that are partially
+         * owned by something else for e.g. a DSP
+         */
+        if (reg > WM8995_MAX_CACHED_REGISTER)
+                return 1;
+
+        switch (reg) {
+        case WM8995_SOFTWARE_RESET:
+        case WM8995_DC_SERVO_READBACK_0:
+        case WM8995_INTERRUPT_STATUS_1:
+        case WM8995_INTERRUPT_STATUS_2:
+        case WM8995_INTERRUPT_STATUS_1_MASK:
+        case WM8995_INTERRUPT_STATUS_2_MASK:
+        case WM8995_INTERRUPT_CONTROL:
+        case WM8995_ACCESSORY_DETECT_MODE1:
+        case WM8995_ACCESSORY_DETECT_MODE2:
+        case WM8995_HEADPHONE_DETECT1:
+        case WM8995_HEADPHONE_DETECT2:
+                return 1;
+        }
+
+        return 0;
+}
+
+static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        int mute_reg;
+
+        switch (dai->id) {
+        case 0:
+                mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
+                break;
+        case 1:
+                mute_reg = WM8995_AIF2_DAC_FILTERS_1;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
+                            !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
+        return 0;
+}
+
+static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec;
+        int master;
+        int aif;
+
+        codec = dai->codec;
+
+        master = 0;
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBS_CFS:
+                break;
+        case SND_SOC_DAIFMT_CBM_CFM:
+                master = WM8995_AIF1_MSTR;
+                break;
+        default:
+                dev_err(dai->dev, "Unknown master/slave configuration\n");
+                return -EINVAL;
+        }
+
+        aif = 0;
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_DSP_B:
+                aif |= WM8995_AIF1_LRCLK_INV;
+        case SND_SOC_DAIFMT_DSP_A:
+                aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
+                break;
+        case SND_SOC_DAIFMT_I2S:
+                aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
+                break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
+                break;
+        default:
+                dev_err(dai->dev, "Unknown dai format\n");
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_DSP_A:
+        case SND_SOC_DAIFMT_DSP_B:
+                /* frame inversion not valid for DSP modes */
+                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+                case SND_SOC_DAIFMT_NB_NF:
+                        break;
+                case SND_SOC_DAIFMT_IB_NF:
+                        aif |= WM8995_AIF1_BCLK_INV;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+                break;
+
+        case SND_SOC_DAIFMT_I2S:
+        case SND_SOC_DAIFMT_RIGHT_J:
+        case SND_SOC_DAIFMT_LEFT_J:
+                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+                case SND_SOC_DAIFMT_NB_NF:
+                        break;
+                case SND_SOC_DAIFMT_IB_IF:
+                        aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
+                        break;
+                case SND_SOC_DAIFMT_IB_NF:
+                        aif |= WM8995_AIF1_BCLK_INV;
+                        break;
+                case SND_SOC_DAIFMT_NB_IF:
+                        aif |= WM8995_AIF1_LRCLK_INV;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1,
+                            WM8995_AIF1_BCLK_INV_MASK |
+                            WM8995_AIF1_LRCLK_INV_MASK |
+                            WM8995_AIF1_FMT_MASK, aif);
+        snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE,
+                            WM8995_AIF1_MSTR_MASK, master);
+        return 0;
+}
+
+static const int srs[] = {
+        8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
+        48000, 88200, 96000
+};
+
+static const int fs_ratios[] = {
+        -1 /* reserved */,
+        128, 192, 256, 384, 512, 768, 1024, 1408, 1536
+};
+
+static const int bclk_divs[] = {
+        10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
+};
+
+static int wm8995_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params,
+                            struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec;
+        struct wm8995_priv *wm8995;
+        int aif1_reg;
+        int bclk_reg;
+        int lrclk_reg;
+        int rate_reg;
+        int bclk_rate;
+        int aif1;
+        int lrclk, bclk;
+        int i, rate_val, best, best_val, cur_val;
+
+        codec = dai->codec;
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+
+        switch (dai->id) {
+        case 0:
+                aif1_reg = WM8995_AIF1_CONTROL_1;
+                bclk_reg = WM8995_AIF1_BCLK;
+                rate_reg = WM8995_AIF1_RATE;
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
+                        wm8995->lrclk_shared[0] */) {
+                        lrclk_reg = WM8995_AIF1DAC_LRCLK;
+                } else {
+                        lrclk_reg = WM8995_AIF1ADC_LRCLK;
+                        dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
+                }
+                break;
+        case 1:
+                aif1_reg = WM8995_AIF2_CONTROL_1;
+                bclk_reg = WM8995_AIF2_BCLK;
+                rate_reg = WM8995_AIF2_RATE;
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
+                    wm8995->lrclk_shared[1] */) {
+                        lrclk_reg = WM8995_AIF2DAC_LRCLK;
+                } else {
+                        lrclk_reg = WM8995_AIF2ADC_LRCLK;
+                        dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        bclk_rate = snd_soc_params_to_bclk(params);
+        if (bclk_rate < 0)
+                return bclk_rate;
+
+        aif1 = 0;
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
+                break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
+                break;
+        default:
+                dev_err(dai->dev, "Unsupported word length %u\n",
+                        params_format(params));
+                return -EINVAL;
+        }
+
+        /* try to find a suitable sample rate */
+        for (i = 0; i < ARRAY_SIZE(srs); ++i)
+                if (srs[i] == params_rate(params))
+                        break;
+        if (i == ARRAY_SIZE(srs)) {
+                dev_err(dai->dev, "Sample rate %d is not supported\n",
+                        params_rate(params));
+                return -EINVAL;
+        }
+        rate_val = i << WM8995_AIF1_SR_SHIFT;
+
+        dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
+        dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
+                dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
+
+        /* AIFCLK/fs ratio; look for a close match in either direction */
+        best = 1;
+        best_val = abs((fs_ratios[1] * params_rate(params))
+                       - wm8995->aifclk[dai->id]);
+        for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
+                cur_val = abs((fs_ratios[i] * params_rate(params))
+                              - wm8995->aifclk[dai->id]);
+                if (cur_val >= best_val)
+                        continue;
+                best = i;
+                best_val = cur_val;
+        }
+        rate_val |= best;
+
+        dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
+                dai->id + 1, fs_ratios[best]);
+
+        /*
+         * We may not get quite the right frequency if using
+         * approximate clocks so look for the closest match that is
+         * higher than the target (we need to ensure that there enough
+         * BCLKs to clock out the samples).
+         */
+        best = 0;
+        bclk = 0;
+        for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
+                cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
+                if (cur_val < 0) /* BCLK table is sorted */
+                        break;
+                best = i;
+        }
+        bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
+
+        bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
+        dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
+                bclk_divs[best], bclk_rate);
+
+        lrclk = bclk_rate / params_rate(params);
+        dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
+                lrclk, bclk_rate / lrclk);
+
+        snd_soc_update_bits(codec, aif1_reg,
+                            WM8995_AIF1_WL_MASK, aif1);
+        snd_soc_update_bits(codec, bclk_reg,
+                            WM8995_AIF1_BCLK_DIV_MASK, bclk);
+        snd_soc_update_bits(codec, lrclk_reg,
+                            WM8995_AIF1DAC_RATE_MASK, lrclk);
+        snd_soc_update_bits(codec, rate_reg,
+                            WM8995_AIF1_SR_MASK |
+                            WM8995_AIF1CLK_RATE_MASK, rate_val);
+        return 0;
+}
+
+static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        int reg, val, mask;
+
+        switch (codec_dai->id) {
+        case 0:
+                reg = WM8995_AIF1_MASTER_SLAVE;
+                mask = WM8995_AIF1_TRI;
+                break;
+        case 1:
+                reg = WM8995_AIF2_MASTER_SLAVE;
+                mask = WM8995_AIF2_TRI;
+                break;
+        case 2:
+                reg = WM8995_POWER_MANAGEMENT_5;
+                mask = WM8995_AIF3_TRI;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (tristate)
+                val = mask;
+        else
+                val = 0;
+
+        return snd_soc_update_bits(codec, reg, mask, val);
+}
+
+/* The size in bits of the FLL divide multiplied by 10
+ * to allow rounding later */
+#define FIXED_FLL_SIZE ((1 << 16) * 10)
+
+struct fll_div {
+        u16 outdiv;
+        u16 n;
+        u16 k;
+        u16 clk_ref_div;
+        u16 fll_fratio;
+};
+
+static int wm8995_get_fll_config(struct fll_div *fll,
+                                 int freq_in, int freq_out)
+{
+        u64 Kpart;
+        unsigned int K, Ndiv, Nmod;
+
+        pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
+
+        /* Scale the input frequency down to <= 13.5MHz */
+        fll->clk_ref_div = 0;
+        while (freq_in > 13500000) {
+                fll->clk_ref_div++;
+                freq_in /= 2;
+
+                if (fll->clk_ref_div > 3)
+                        return -EINVAL;
+        }
+        pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
+
+        /* Scale the output to give 90MHz<=Fvco<=100MHz */
+        fll->outdiv = 3;
+        while (freq_out * (fll->outdiv + 1) < 90000000) {
+                fll->outdiv++;
+                if (fll->outdiv > 63)
+                        return -EINVAL;
+        }
+        freq_out *= fll->outdiv + 1;
+        pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
+
+        if (freq_in > 1000000) {
+                fll->fll_fratio = 0;
+        } else if (freq_in > 256000) {
+                fll->fll_fratio = 1;
+                freq_in *= 2;
+        } else if (freq_in > 128000) {
+                fll->fll_fratio = 2;
+                freq_in *= 4;
+        } else if (freq_in > 64000) {
+                fll->fll_fratio = 3;
+                freq_in *= 8;
+        } else {
+                fll->fll_fratio = 4;
+                freq_in *= 16;
+        }
+        pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
+
+        /* Now, calculate N.K */
+        Ndiv = freq_out / freq_in;
+
+        fll->n = Ndiv;
+        Nmod = freq_out % freq_in;
+        pr_debug("Nmod=%d\n", Nmod);
+
+        /* Calculate fractional part - scale up so we can round. */
+        Kpart = FIXED_FLL_SIZE * (long long)Nmod;
+
+        do_div(Kpart, freq_in);
+
+        K = Kpart & 0xFFFFFFFF;
+
+        if ((K % 10) >= 5)
+                K += 5;
+
+        /* Move down to proper range now rounding is done */
+        fll->k = K / 10;
+
+        pr_debug("N=%x K=%x\n", fll->n, fll->k);
+
+        return 0;
+}
+
+static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
+                          int src, unsigned int freq_in,
+                          unsigned int freq_out)
+{
+        struct snd_soc_codec *codec;
+        struct wm8995_priv *wm8995;
+        int reg_offset, ret;
+        struct fll_div fll;
+        u16 reg, aif1, aif2;
+
+        codec = dai->codec;
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+
+        aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1)
+               & WM8995_AIF1CLK_ENA;
+
+        aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1)
+               & WM8995_AIF2CLK_ENA;
+
+        switch (id) {
+        case WM8995_FLL1:
+                reg_offset = 0;
+                id = 0;
+                break;
+        case WM8995_FLL2:
+                reg_offset = 0x20;
+                id = 1;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (src) {
+        case 0:
+                /* Allow no source specification when stopping */
+                if (freq_out)
+                        return -EINVAL;
+                break;
+        case WM8995_FLL_SRC_MCLK1:
+        case WM8995_FLL_SRC_MCLK2:
+        case WM8995_FLL_SRC_LRCLK:
+        case WM8995_FLL_SRC_BCLK:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Are we changing anything? */
+        if (wm8995->fll[id].src == src &&
+            wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
+                return 0;
+
+        /* If we're stopping the FLL redo the old config - no
+         * registers will actually be written but we avoid GCC flow
+         * analysis bugs spewing warnings.
+         */
+        if (freq_out)
+                ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
+        else
+                ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
+                                            wm8995->fll[id].out);
+        if (ret < 0)
+                return ret;
+
+        /* Gate the AIF clocks while we reclock */
+        snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
+                            WM8995_AIF1CLK_ENA_MASK, 0);
+        snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
+                            WM8995_AIF2CLK_ENA_MASK, 0);
+
+        /* We always need to disable the FLL while reconfiguring */
+        snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
+                            WM8995_FLL1_ENA_MASK, 0);
+
+        reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
+              (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
+        snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset,
+                            WM8995_FLL1_OUTDIV_MASK |
+                            WM8995_FLL1_FRATIO_MASK, reg);
+
+        snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
+
+        snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset,
+                            WM8995_FLL1_N_MASK,
+                            fll.n << WM8995_FLL1_N_SHIFT);
+
+        snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset,
+                            WM8995_FLL1_REFCLK_DIV_MASK |
+                            WM8995_FLL1_REFCLK_SRC_MASK,
+                            (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
+                            (src - 1));
+
+        if (freq_out)
+                snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
+                                    WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
+
+        wm8995->fll[id].in = freq_in;
+        wm8995->fll[id].out = freq_out;
+        wm8995->fll[id].src = src;
+
+        /* Enable any gated AIF clocks */
+        snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
+                            WM8995_AIF1CLK_ENA_MASK, aif1);
+        snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
+                            WM8995_AIF2CLK_ENA_MASK, aif2);
+
+        configure_clock(codec);
+
+        return 0;
+}
+
+static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
+                                 int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec;
+        struct wm8995_priv *wm8995;
+
+        codec = dai->codec;
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+
+        switch (dai->id) {
+        case 0:
+        case 1:
+                break;
+        default:
+                /* AIF3 shares clocking with AIF1/2 */
+                return -EINVAL;
+        }
+
+        switch (clk_id) {
+        case WM8995_SYSCLK_MCLK1:
+                wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
+                wm8995->mclk[0] = freq;
+                dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
+                        dai->id + 1, freq);
+                break;
+        case WM8995_SYSCLK_MCLK2:
+                wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
+                wm8995->mclk[1] = freq;
+                dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
+                        dai->id + 1, freq);
+                break;
+        case WM8995_SYSCLK_FLL1:
+                wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
+                dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
+                break;
+        case WM8995_SYSCLK_FLL2:
+                wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
+                dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
+                break;
+        case WM8995_SYSCLK_OPCLK:
+        default:
+                dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
+                return -EINVAL;
+        }
+
+        configure_clock(codec);
+
+        return 0;
+}
+
+static int wm8995_set_bias_level(struct snd_soc_codec *codec,
+                                 enum snd_soc_bias_level level)
+{
+        struct wm8995_priv *wm8995;
+        int ret;
+
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+        case SND_SOC_BIAS_PREPARE:
+                break;
+        case SND_SOC_BIAS_STANDBY:
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                        ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
+                                                    wm8995->supplies);
+                        if (ret)
+                                return ret;
+
+                        ret = snd_soc_cache_sync(codec);
+                        if (ret) {
+                                dev_err(codec->dev,
+                                        "Failed to sync cache: %d\n", ret);
+                                return ret;
+                        }
+
+                        snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
+                                            WM8995_BG_ENA_MASK, WM8995_BG_ENA);
+                }
+                break;
+        case SND_SOC_BIAS_OFF:
+                snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
+                                    WM8995_BG_ENA_MASK, 0);
+                regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies),
+                                       wm8995->supplies);
+                break;
+        }
+
+        codec->dapm.bias_level = level;
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int wm8995_resume(struct snd_soc_codec *codec)
+{
+        wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+#else
+#define wm8995_suspend NULL
+#define wm8995_resume NULL
+#endif
+
+static int wm8995_remove(struct snd_soc_codec *codec)
+{
+        struct wm8995_priv *wm8995;
+        struct i2c_client *i2c;
+
+        i2c = container_of(codec->dev, struct i2c_client, dev);
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+        wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int wm8995_probe(struct snd_soc_codec *codec)
+{
+        struct wm8995_priv *wm8995;
+        int i;
+        int ret;
+
+        codec->dapm.idle_bias_off = 1;
+        wm8995 = snd_soc_codec_get_drvdata(codec);
+        wm8995->codec = codec;
+
+        ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
+                return ret;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++)
+                wm8995->supplies[i].supply = wm8995_supply_names[i];
+
+        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8995->supplies),
+                                 wm8995->supplies);
+        if (ret) {
+                dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+                return ret;
+        }
+
+        wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0;
+        wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1;
+        wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2;
+        wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3;
+        wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4;
+        wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5;
+        wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6;
+        wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7;
+
+        /* This should really be moved into the regulator core */
+        for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) {
+                ret = regulator_register_notifier(wm8995->supplies[i].consumer,
+                                                  &wm8995->disable_nb[i]);
+                if (ret) {
+                        dev_err(codec->dev,
+                                "Failed to register regulator notifier: %d\n",
+                                ret);
+                }
+        }
+
+        ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
+                                    wm8995->supplies);
+        if (ret) {
+                dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+                goto err_reg_get;
+        }
+
+        ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read device ID: %d\n", ret);
+                goto err_reg_enable;
+        }
+
+        if (ret != 0x8995) {
+                dev_err(codec->dev, "Invalid device ID: %#x\n", ret);
+                goto err_reg_enable;
+        }
+
+        ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
+                goto err_reg_enable;
+        }
+
+        wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        /* Latch volume updates (right only; we always do left then right). */
+        snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME,
+                            WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
+        snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME,
+                            WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
+        snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME,
+                            WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
+        snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME,
+                            WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
+        snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME,
+                            WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
+        snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME,
+                            WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
+        snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME,
+                            WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
+        snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME,
+                            WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
+        snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
+                            WM8995_IN1_VU_MASK, WM8995_IN1_VU);
+
+        wm8995_update_class_w(codec);
+
+        snd_soc_add_controls(codec, wm8995_snd_controls,
+                             ARRAY_SIZE(wm8995_snd_controls));
+        snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets,
+                                  ARRAY_SIZE(wm8995_dapm_widgets));
+        snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon,
+                                ARRAY_SIZE(wm8995_intercon));
+
+        return 0;
+
+err_reg_enable:
+        regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
+err_reg_get:
+        regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
+        return ret;
+}
+
+#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
+        .set_sysclk = wm8995_set_dai_sysclk,
+        .set_fmt = wm8995_set_dai_fmt,
+        .hw_params = wm8995_hw_params,
+        .digital_mute = wm8995_aif_mute,
+        .set_pll = wm8995_set_fll,
+        .set_tristate = wm8995_set_tristate,
+};
+
+static struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
+        .set_sysclk = wm8995_set_dai_sysclk,
+        .set_fmt = wm8995_set_dai_fmt,
+        .hw_params = wm8995_hw_params,
+        .digital_mute = wm8995_aif_mute,
+        .set_pll = wm8995_set_fll,
+        .set_tristate = wm8995_set_tristate,
+};
+
+static struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
+        .set_tristate = wm8995_set_tristate,
+};
+
+static struct snd_soc_dai_driver wm8995_dai[] = {
+        {
+                .name = "wm8995-aif1",
+                .playback = {
+                        .stream_name = "AIF1 Playback",
+                        .channels_min = 2,
+                        .channels_max = 2,
+                        .rates = SNDRV_PCM_RATE_8000_96000,
+                        .formats = WM8995_FORMATS
+                },
+                .capture = {
+                        .stream_name = "AIF1 Capture",
+                        .channels_min = 2,
+                        .channels_max = 2,
+                        .rates = SNDRV_PCM_RATE_8000_48000,
+                        .formats = WM8995_FORMATS
+                },
+                .ops = &wm8995_aif1_dai_ops
+        },
+        {
+                .name = "wm8995-aif2",
+                .playback = {
+                        .stream_name = "AIF2 Playback",
+                        .channels_min = 2,
+                        .channels_max = 2,
+                        .rates = SNDRV_PCM_RATE_8000_96000,
+                        .formats = WM8995_FORMATS
+                },
+                .capture = {
+                        .stream_name = "AIF2 Capture",
+                        .channels_min = 2,
+                        .channels_max = 2,
+                        .rates = SNDRV_PCM_RATE_8000_48000,
+                        .formats = WM8995_FORMATS
+                },
+                .ops = &wm8995_aif2_dai_ops
+        },
+        {
+                .name = "wm8995-aif3",
+                .playback = {
+                        .stream_name = "AIF3 Playback",
+                        .channels_min = 2,
+                        .channels_max = 2,
+                        .rates = SNDRV_PCM_RATE_8000_96000,
+                        .formats = WM8995_FORMATS
+                },
+                .capture = {
+                        .stream_name = "AIF3 Capture",
+                        .channels_min = 2,
+                        .channels_max = 2,
+                        .rates = SNDRV_PCM_RATE_8000_48000,
+                        .formats = WM8995_FORMATS
+                },
+                .ops = &wm8995_aif3_dai_ops
+        }
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8995 = {
+        .probe = wm8995_probe,
+        .remove = wm8995_remove,
+        .suspend = wm8995_suspend,
+        .resume = wm8995_resume,
+        .set_bias_level = wm8995_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm8995_reg_defs,
+        .volatile_register = wm8995_volatile,
+        .compress_type = SND_SOC_RBTREE_COMPRESSION
+};
+
+#if defined(CONFIG_SPI_MASTER)
+static int __devinit wm8995_spi_probe(struct spi_device *spi)
+{
+        struct wm8995_priv *wm8995;
+        int ret;
+
+        wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL);
+        if (!wm8995)
+                return -ENOMEM;
+
+        wm8995->control_type = SND_SOC_SPI;
+        spi_set_drvdata(spi, wm8995);
+
+        ret = snd_soc_register_codec(&spi->dev,
+                                     &soc_codec_dev_wm8995, wm8995_dai,
+                                     ARRAY_SIZE(wm8995_dai));
+        if (ret < 0)
+                kfree(wm8995);
+        return ret;
+}
+
+static int __devexit wm8995_spi_remove(struct spi_device *spi)
+{
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(spi_get_drvdata(spi));
+        return 0;
+}
+
+static struct spi_driver wm8995_spi_driver = {
+        .driver = {
+                .name = "wm8995",
+                .owner = THIS_MODULE,
+        },
+        .probe = wm8995_spi_probe,
+        .remove = __devexit_p(wm8995_spi_remove)
+};
+#endif
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static __devinit int wm8995_i2c_probe(struct i2c_client *i2c,
+                                      const struct i2c_device_id *id)
+{
+        struct wm8995_priv *wm8995;
+        int ret;
+
+        wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL);
+        if (!wm8995)
+                return -ENOMEM;
+
+        wm8995->control_type = SND_SOC_I2C;
+        i2c_set_clientdata(i2c, wm8995);
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                                     &soc_codec_dev_wm8995, wm8995_dai,
+                                     ARRAY_SIZE(wm8995_dai));
+        if (ret < 0)
+                kfree(wm8995);
+        return ret;
+}
+
+static __devexit int wm8995_i2c_remove(struct i2c_client *client)
+{
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
+        return 0;
+}
+
+static const struct i2c_device_id wm8995_i2c_id[] = {
+        {"wm8995", 0},
+        {}
+};
+
+MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
+
+static struct i2c_driver wm8995_i2c_driver = {
+        .driver = {
+                .name = "wm8995",
+                .owner = THIS_MODULE,
+        },
+        .probe = wm8995_i2c_probe,
+        .remove = __devexit_p(wm8995_i2c_remove),
+        .id_table = wm8995_i2c_id
+};
+#endif
+
+static int __init wm8995_modinit(void)
+{
+        int ret = 0;
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&wm8995_i2c_driver);
+        if (ret) {
+                printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
+                       ret);
+        }
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        ret = spi_register_driver(&wm8995_spi_driver);
+        if (ret) {
+                printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
+                       ret);
+        }
+#endif
+        return ret;
+}
+
+module_init(wm8995_modinit);
+
+static void __exit wm8995_exit(void)
+{
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&wm8995_i2c_driver);
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        spi_unregister_driver(&wm8995_spi_driver);
+#endif
+}
+
+module_exit(wm8995_exit);
+
+MODULE_DESCRIPTION("ASoC WM8995 driver");
+MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8995.h b/sound/soc/codecs/wm8995.h
new file mode 100644
index 000000000000..5642121c4977
--- /dev/null
+++ b/sound/soc/codecs/wm8995.h
@@ -0,0 +1,4269 @@
+/*
+ * wm8995.h  --  WM8995 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Wolfson Microelectronics plc
+ *
+ * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8995_H
+#define _WM8995_H
+
+#include <asm/types.h>
+
+/*
+ * Register values.
+ */
+#define WM8995_SOFTWARE_RESET                   0x00
+#define WM8995_POWER_MANAGEMENT_1               0x01
+#define WM8995_POWER_MANAGEMENT_2               0x02
+#define WM8995_POWER_MANAGEMENT_3               0x03
+#define WM8995_POWER_MANAGEMENT_4               0x04
+#define WM8995_POWER_MANAGEMENT_5               0x05
+#define WM8995_LEFT_LINE_INPUT_1_VOLUME         0x10
+#define WM8995_RIGHT_LINE_INPUT_1_VOLUME        0x11
+#define WM8995_LEFT_LINE_INPUT_CONTROL          0x12
+#define WM8995_DAC1_LEFT_VOLUME                 0x18
+#define WM8995_DAC1_RIGHT_VOLUME                0x19
+#define WM8995_DAC2_LEFT_VOLUME                 0x1A
+#define WM8995_DAC2_RIGHT_VOLUME                0x1B
+#define WM8995_OUTPUT_VOLUME_ZC_1               0x1C
+#define WM8995_MICBIAS_1                        0x20
+#define WM8995_MICBIAS_2                        0x21
+#define WM8995_LDO_1                            0x28
+#define WM8995_LDO_2                            0x29
+#define WM8995_ACCESSORY_DETECT_MODE1           0x30
+#define WM8995_ACCESSORY_DETECT_MODE2           0x31
+#define WM8995_HEADPHONE_DETECT1                0x34
+#define WM8995_HEADPHONE_DETECT2                0x35
+#define WM8995_MIC_DETECT_1                     0x38
+#define WM8995_MIC_DETECT_2                     0x39
+#define WM8995_CHARGE_PUMP_1                    0x40
+#define WM8995_CLASS_W_1                        0x45
+#define WM8995_DC_SERVO_1                       0x50
+#define WM8995_DC_SERVO_2                       0x51
+#define WM8995_DC_SERVO_3                       0x52
+#define WM8995_DC_SERVO_5                       0x54
+#define WM8995_DC_SERVO_6                       0x55
+#define WM8995_DC_SERVO_7                       0x56
+#define WM8995_DC_SERVO_READBACK_0              0x57
+#define WM8995_ANALOGUE_HP_1                    0x60
+#define WM8995_ANALOGUE_HP_2                    0x61
+#define WM8995_CHIP_REVISION                    0x100
+#define WM8995_CONTROL_INTERFACE_1              0x101
+#define WM8995_CONTROL_INTERFACE_2              0x102
+#define WM8995_WRITE_SEQUENCER_CTRL_1           0x110
+#define WM8995_WRITE_SEQUENCER_CTRL_2           0x111
+#define WM8995_AIF1_CLOCKING_1                  0x200
+#define WM8995_AIF1_CLOCKING_2                  0x201
+#define WM8995_AIF2_CLOCKING_1                  0x204
+#define WM8995_AIF2_CLOCKING_2                  0x205
+#define WM8995_CLOCKING_1                       0x208
+#define WM8995_CLOCKING_2                       0x209
+#define WM8995_AIF1_RATE                        0x210
+#define WM8995_AIF2_RATE                        0x211
+#define WM8995_RATE_STATUS                      0x212
+#define WM8995_FLL1_CONTROL_1                   0x220
+#define WM8995_FLL1_CONTROL_2                   0x221
+#define WM8995_FLL1_CONTROL_3                   0x222
+#define WM8995_FLL1_CONTROL_4                   0x223
+#define WM8995_FLL1_CONTROL_5                   0x224
+#define WM8995_FLL2_CONTROL_1                   0x240
+#define WM8995_FLL2_CONTROL_2                   0x241
+#define WM8995_FLL2_CONTROL_3                   0x242
+#define WM8995_FLL2_CONTROL_4                   0x243
+#define WM8995_FLL2_CONTROL_5                   0x244
+#define WM8995_AIF1_CONTROL_1                   0x300
+#define WM8995_AIF1_CONTROL_2                   0x301
+#define WM8995_AIF1_MASTER_SLAVE                0x302
+#define WM8995_AIF1_BCLK                        0x303
+#define WM8995_AIF1ADC_LRCLK                    0x304
+#define WM8995_AIF1DAC_LRCLK                    0x305
+#define WM8995_AIF1DAC_DATA                     0x306
+#define WM8995_AIF1ADC_DATA                     0x307
+#define WM8995_AIF2_CONTROL_1                   0x310
+#define WM8995_AIF2_CONTROL_2                   0x311
+#define WM8995_AIF2_MASTER_SLAVE                0x312
+#define WM8995_AIF2_BCLK                        0x313
+#define WM8995_AIF2ADC_LRCLK                    0x314
+#define WM8995_AIF2DAC_LRCLK                    0x315
+#define WM8995_AIF2DAC_DATA                     0x316
+#define WM8995_AIF2ADC_DATA                     0x317
+#define WM8995_AIF1_ADC1_LEFT_VOLUME            0x400
+#define WM8995_AIF1_ADC1_RIGHT_VOLUME           0x401
+#define WM8995_AIF1_DAC1_LEFT_VOLUME            0x402
+#define WM8995_AIF1_DAC1_RIGHT_VOLUME           0x403
+#define WM8995_AIF1_ADC2_LEFT_VOLUME            0x404
+#define WM8995_AIF1_ADC2_RIGHT_VOLUME           0x405
+#define WM8995_AIF1_DAC2_LEFT_VOLUME            0x406
+#define WM8995_AIF1_DAC2_RIGHT_VOLUME           0x407
+#define WM8995_AIF1_ADC1_FILTERS                0x410
+#define WM8995_AIF1_ADC2_FILTERS                0x411
+#define WM8995_AIF1_DAC1_FILTERS_1              0x420
+#define WM8995_AIF1_DAC1_FILTERS_2              0x421
+#define WM8995_AIF1_DAC2_FILTERS_1              0x422
+#define WM8995_AIF1_DAC2_FILTERS_2              0x423
+#define WM8995_AIF1_DRC1_1                      0x440
+#define WM8995_AIF1_DRC1_2                      0x441
+#define WM8995_AIF1_DRC1_3                      0x442
+#define WM8995_AIF1_DRC1_4                      0x443
+#define WM8995_AIF1_DRC1_5                      0x444
+#define WM8995_AIF1_DRC2_1                      0x450
+#define WM8995_AIF1_DRC2_2                      0x451
+#define WM8995_AIF1_DRC2_3                      0x452
+#define WM8995_AIF1_DRC2_4                      0x453
+#define WM8995_AIF1_DRC2_5                      0x454
+#define WM8995_AIF1_DAC1_EQ_GAINS_1             0x480
+#define WM8995_AIF1_DAC1_EQ_GAINS_2             0x481
+#define WM8995_AIF1_DAC1_EQ_BAND_1_A            0x482
+#define WM8995_AIF1_DAC1_EQ_BAND_1_B            0x483
+#define WM8995_AIF1_DAC1_EQ_BAND_1_PG           0x484
+#define WM8995_AIF1_DAC1_EQ_BAND_2_A            0x485
+#define WM8995_AIF1_DAC1_EQ_BAND_2_B            0x486
+#define WM8995_AIF1_DAC1_EQ_BAND_2_C            0x487
+#define WM8995_AIF1_DAC1_EQ_BAND_2_PG           0x488
+#define WM8995_AIF1_DAC1_EQ_BAND_3_A            0x489
+#define WM8995_AIF1_DAC1_EQ_BAND_3_B            0x48A
+#define WM8995_AIF1_DAC1_EQ_BAND_3_C            0x48B
+#define WM8995_AIF1_DAC1_EQ_BAND_3_PG           0x48C
+#define WM8995_AIF1_DAC1_EQ_BAND_4_A            0x48D
+#define WM8995_AIF1_DAC1_EQ_BAND_4_B            0x48E
+#define WM8995_AIF1_DAC1_EQ_BAND_4_C            0x48F
+#define WM8995_AIF1_DAC1_EQ_BAND_4_PG           0x490
+#define WM8995_AIF1_DAC1_EQ_BAND_5_A            0x491
+#define WM8995_AIF1_DAC1_EQ_BAND_5_B            0x492
+#define WM8995_AIF1_DAC1_EQ_BAND_5_PG           0x493
+#define WM8995_AIF1_DAC2_EQ_GAINS_1             0x4A0
+#define WM8995_AIF1_DAC2_EQ_GAINS_2             0x4A1
+#define WM8995_AIF1_DAC2_EQ_BAND_1_A            0x4A2
+#define WM8995_AIF1_DAC2_EQ_BAND_1_B            0x4A3
+#define WM8995_AIF1_DAC2_EQ_BAND_1_PG           0x4A4
+#define WM8995_AIF1_DAC2_EQ_BAND_2_A            0x4A5
+#define WM8995_AIF1_DAC2_EQ_BAND_2_B            0x4A6
+#define WM8995_AIF1_DAC2_EQ_BAND_2_C            0x4A7
+#define WM8995_AIF1_DAC2_EQ_BAND_2_PG           0x4A8
+#define WM8995_AIF1_DAC2_EQ_BAND_3_A            0x4A9
+#define WM8995_AIF1_DAC2_EQ_BAND_3_B            0x4AA
+#define WM8995_AIF1_DAC2_EQ_BAND_3_C            0x4AB
+#define WM8995_AIF1_DAC2_EQ_BAND_3_PG           0x4AC
+#define WM8995_AIF1_DAC2_EQ_BAND_4_A            0x4AD
+#define WM8995_AIF1_DAC2_EQ_BAND_4_B            0x4AE
+#define WM8995_AIF1_DAC2_EQ_BAND_4_C            0x4AF
+#define WM8995_AIF1_DAC2_EQ_BAND_4_PG           0x4B0
+#define WM8995_AIF1_DAC2_EQ_BAND_5_A            0x4B1
+#define WM8995_AIF1_DAC2_EQ_BAND_5_B            0x4B2
+#define WM8995_AIF1_DAC2_EQ_BAND_5_PG           0x4B3
+#define WM8995_AIF2_ADC_LEFT_VOLUME             0x500
+#define WM8995_AIF2_ADC_RIGHT_VOLUME            0x501
+#define WM8995_AIF2_DAC_LEFT_VOLUME             0x502
+#define WM8995_AIF2_DAC_RIGHT_VOLUME            0x503
+#define WM8995_AIF2_ADC_FILTERS                 0x510
+#define WM8995_AIF2_DAC_FILTERS_1               0x520
+#define WM8995_AIF2_DAC_FILTERS_2               0x521
+#define WM8995_AIF2_DRC_1                       0x540
+#define WM8995_AIF2_DRC_2                       0x541
+#define WM8995_AIF2_DRC_3                       0x542
+#define WM8995_AIF2_DRC_4                       0x543
+#define WM8995_AIF2_DRC_5                       0x544
+#define WM8995_AIF2_EQ_GAINS_1                  0x580
+#define WM8995_AIF2_EQ_GAINS_2                  0x581
+#define WM8995_AIF2_EQ_BAND_1_A                 0x582
+#define WM8995_AIF2_EQ_BAND_1_B                 0x583
+#define WM8995_AIF2_EQ_BAND_1_PG                0x584
+#define WM8995_AIF2_EQ_BAND_2_A                 0x585
+#define WM8995_AIF2_EQ_BAND_2_B                 0x586
+#define WM8995_AIF2_EQ_BAND_2_C                 0x587
+#define WM8995_AIF2_EQ_BAND_2_PG                0x588
+#define WM8995_AIF2_EQ_BAND_3_A                 0x589
+#define WM8995_AIF2_EQ_BAND_3_B                 0x58A
+#define WM8995_AIF2_EQ_BAND_3_C                 0x58B
+#define WM8995_AIF2_EQ_BAND_3_PG                0x58C
+#define WM8995_AIF2_EQ_BAND_4_A                 0x58D
+#define WM8995_AIF2_EQ_BAND_4_B                 0x58E
+#define WM8995_AIF2_EQ_BAND_4_C                 0x58F
+#define WM8995_AIF2_EQ_BAND_4_PG                0x590
+#define WM8995_AIF2_EQ_BAND_5_A                 0x591
+#define WM8995_AIF2_EQ_BAND_5_B                 0x592
+#define WM8995_AIF2_EQ_BAND_5_PG                0x593
+#define WM8995_DAC1_MIXER_VOLUMES               0x600
+#define WM8995_DAC1_LEFT_MIXER_ROUTING          0x601
+#define WM8995_DAC1_RIGHT_MIXER_ROUTING         0x602
+#define WM8995_DAC2_MIXER_VOLUMES               0x603
+#define WM8995_DAC2_LEFT_MIXER_ROUTING          0x604
+#define WM8995_DAC2_RIGHT_MIXER_ROUTING         0x605
+#define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING     0x606
+#define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING    0x607
+#define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING     0x608
+#define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING    0x609
+#define WM8995_DAC_SOFTMUTE                     0x610
+#define WM8995_OVERSAMPLING                     0x620
+#define WM8995_SIDETONE                         0x621
+#define WM8995_GPIO_1                           0x700
+#define WM8995_GPIO_2                           0x701
+#define WM8995_GPIO_3                           0x702
+#define WM8995_GPIO_4                           0x703
+#define WM8995_GPIO_5                           0x704
+#define WM8995_GPIO_6                           0x705
+#define WM8995_GPIO_7                           0x706
+#define WM8995_GPIO_8                           0x707
+#define WM8995_GPIO_9                           0x708
+#define WM8995_GPIO_10                          0x709
+#define WM8995_GPIO_11                          0x70A
+#define WM8995_GPIO_12                          0x70B
+#define WM8995_GPIO_13                          0x70C
+#define WM8995_GPIO_14                          0x70D
+#define WM8995_PULL_CONTROL_1                   0x720
+#define WM8995_PULL_CONTROL_2                   0x721
+#define WM8995_INTERRUPT_STATUS_1               0x730
+#define WM8995_INTERRUPT_STATUS_2               0x731
+#define WM8995_INTERRUPT_RAW_STATUS_2           0x732
+#define WM8995_INTERRUPT_STATUS_1_MASK          0x738
+#define WM8995_INTERRUPT_STATUS_2_MASK          0x739
+#define WM8995_INTERRUPT_CONTROL                0x740
+#define WM8995_LEFT_PDM_SPEAKER_1               0x800
+#define WM8995_RIGHT_PDM_SPEAKER_1              0x801
+#define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE      0x802
+#define WM8995_LEFT_PDM_SPEAKER_2               0x808
+#define WM8995_RIGHT_PDM_SPEAKER_2              0x809
+#define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE      0x80A
+#define WM8995_WRITE_SEQUENCER_0                0x3000
+#define WM8995_WRITE_SEQUENCER_1                0x3001
+#define WM8995_WRITE_SEQUENCER_2                0x3002
+#define WM8995_WRITE_SEQUENCER_3                0x3003
+#define WM8995_WRITE_SEQUENCER_4                0x3004
+#define WM8995_WRITE_SEQUENCER_5                0x3005
+#define WM8995_WRITE_SEQUENCER_6                0x3006
+#define WM8995_WRITE_SEQUENCER_7                0x3007
+#define WM8995_WRITE_SEQUENCER_8                0x3008
+#define WM8995_WRITE_SEQUENCER_9                0x3009
+#define WM8995_WRITE_SEQUENCER_10               0x300A
+#define WM8995_WRITE_SEQUENCER_11               0x300B
+#define WM8995_WRITE_SEQUENCER_12               0x300C
+#define WM8995_WRITE_SEQUENCER_13               0x300D
+#define WM8995_WRITE_SEQUENCER_14               0x300E
+#define WM8995_WRITE_SEQUENCER_15               0x300F
+#define WM8995_WRITE_SEQUENCER_16               0x3010
+#define WM8995_WRITE_SEQUENCER_17               0x3011
+#define WM8995_WRITE_SEQUENCER_18               0x3012
+#define WM8995_WRITE_SEQUENCER_19               0x3013
+#define WM8995_WRITE_SEQUENCER_20               0x3014
+#define WM8995_WRITE_SEQUENCER_21               0x3015
+#define WM8995_WRITE_SEQUENCER_22               0x3016
+#define WM8995_WRITE_SEQUENCER_23               0x3017
+#define WM8995_WRITE_SEQUENCER_24               0x3018
+#define WM8995_WRITE_SEQUENCER_25               0x3019
+#define WM8995_WRITE_SEQUENCER_26               0x301A
+#define WM8995_WRITE_SEQUENCER_27               0x301B
+#define WM8995_WRITE_SEQUENCER_28               0x301C
+#define WM8995_WRITE_SEQUENCER_29               0x301D
+#define WM8995_WRITE_SEQUENCER_30               0x301E
+#define WM8995_WRITE_SEQUENCER_31               0x301F
+#define WM8995_WRITE_SEQUENCER_32               0x3020
+#define WM8995_WRITE_SEQUENCER_33               0x3021
+#define WM8995_WRITE_SEQUENCER_34               0x3022
+#define WM8995_WRITE_SEQUENCER_35               0x3023
+#define WM8995_WRITE_SEQUENCER_36               0x3024
+#define WM8995_WRITE_SEQUENCER_37               0x3025
+#define WM8995_WRITE_SEQUENCER_38               0x3026
+#define WM8995_WRITE_SEQUENCER_39               0x3027
+#define WM8995_WRITE_SEQUENCER_40               0x3028
+#define WM8995_WRITE_SEQUENCER_41               0x3029
+#define WM8995_WRITE_SEQUENCER_42               0x302A
+#define WM8995_WRITE_SEQUENCER_43               0x302B
+#define WM8995_WRITE_SEQUENCER_44               0x302C
+#define WM8995_WRITE_SEQUENCER_45               0x302D
+#define WM8995_WRITE_SEQUENCER_46               0x302E
+#define WM8995_WRITE_SEQUENCER_47               0x302F
+#define WM8995_WRITE_SEQUENCER_48               0x3030
+#define WM8995_WRITE_SEQUENCER_49               0x3031
+#define WM8995_WRITE_SEQUENCER_50               0x3032
+#define WM8995_WRITE_SEQUENCER_51               0x3033
+#define WM8995_WRITE_SEQUENCER_52               0x3034
+#define WM8995_WRITE_SEQUENCER_53               0x3035
+#define WM8995_WRITE_SEQUENCER_54               0x3036
+#define WM8995_WRITE_SEQUENCER_55               0x3037
+#define WM8995_WRITE_SEQUENCER_56               0x3038
+#define WM8995_WRITE_SEQUENCER_57               0x3039
+#define WM8995_WRITE_SEQUENCER_58               0x303A
+#define WM8995_WRITE_SEQUENCER_59               0x303B
+#define WM8995_WRITE_SEQUENCER_60               0x303C
+#define WM8995_WRITE_SEQUENCER_61               0x303D
+#define WM8995_WRITE_SEQUENCER_62               0x303E
+#define WM8995_WRITE_SEQUENCER_63               0x303F
+#define WM8995_WRITE_SEQUENCER_64               0x3040
+#define WM8995_WRITE_SEQUENCER_65               0x3041
+#define WM8995_WRITE_SEQUENCER_66               0x3042
+#define WM8995_WRITE_SEQUENCER_67               0x3043
+#define WM8995_WRITE_SEQUENCER_68               0x3044
+#define WM8995_WRITE_SEQUENCER_69               0x3045
+#define WM8995_WRITE_SEQUENCER_70               0x3046
+#define WM8995_WRITE_SEQUENCER_71               0x3047
+#define WM8995_WRITE_SEQUENCER_72               0x3048
+#define WM8995_WRITE_SEQUENCER_73               0x3049
+#define WM8995_WRITE_SEQUENCER_74               0x304A
+#define WM8995_WRITE_SEQUENCER_75               0x304B
+#define WM8995_WRITE_SEQUENCER_76               0x304C
+#define WM8995_WRITE_SEQUENCER_77               0x304D
+#define WM8995_WRITE_SEQUENCER_78               0x304E
+#define WM8995_WRITE_SEQUENCER_79               0x304F
+#define WM8995_WRITE_SEQUENCER_80               0x3050
+#define WM8995_WRITE_SEQUENCER_81               0x3051
+#define WM8995_WRITE_SEQUENCER_82               0x3052
+#define WM8995_WRITE_SEQUENCER_83               0x3053
+#define WM8995_WRITE_SEQUENCER_84               0x3054
+#define WM8995_WRITE_SEQUENCER_85               0x3055
+#define WM8995_WRITE_SEQUENCER_86               0x3056
+#define WM8995_WRITE_SEQUENCER_87               0x3057
+#define WM8995_WRITE_SEQUENCER_88               0x3058
+#define WM8995_WRITE_SEQUENCER_89               0x3059
+#define WM8995_WRITE_SEQUENCER_90               0x305A
+#define WM8995_WRITE_SEQUENCER_91               0x305B
+#define WM8995_WRITE_SEQUENCER_92               0x305C
+#define WM8995_WRITE_SEQUENCER_93               0x305D
+#define WM8995_WRITE_SEQUENCER_94               0x305E
+#define WM8995_WRITE_SEQUENCER_95               0x305F
+#define WM8995_WRITE_SEQUENCER_96               0x3060
+#define WM8995_WRITE_SEQUENCER_97               0x3061
+#define WM8995_WRITE_SEQUENCER_98               0x3062
+#define WM8995_WRITE_SEQUENCER_99               0x3063
+#define WM8995_WRITE_SEQUENCER_100              0x3064
+#define WM8995_WRITE_SEQUENCER_101              0x3065
+#define WM8995_WRITE_SEQUENCER_102              0x3066
+#define WM8995_WRITE_SEQUENCER_103              0x3067
+#define WM8995_WRITE_SEQUENCER_104              0x3068
+#define WM8995_WRITE_SEQUENCER_105              0x3069
+#define WM8995_WRITE_SEQUENCER_106              0x306A
+#define WM8995_WRITE_SEQUENCER_107              0x306B
+#define WM8995_WRITE_SEQUENCER_108              0x306C
+#define WM8995_WRITE_SEQUENCER_109              0x306D
+#define WM8995_WRITE_SEQUENCER_110              0x306E
+#define WM8995_WRITE_SEQUENCER_111              0x306F
+#define WM8995_WRITE_SEQUENCER_112              0x3070
+#define WM8995_WRITE_SEQUENCER_113              0x3071
+#define WM8995_WRITE_SEQUENCER_114              0x3072
+#define WM8995_WRITE_SEQUENCER_115              0x3073
+#define WM8995_WRITE_SEQUENCER_116              0x3074
+#define WM8995_WRITE_SEQUENCER_117              0x3075
+#define WM8995_WRITE_SEQUENCER_118              0x3076
+#define WM8995_WRITE_SEQUENCER_119              0x3077
+#define WM8995_WRITE_SEQUENCER_120              0x3078
+#define WM8995_WRITE_SEQUENCER_121              0x3079
+#define WM8995_WRITE_SEQUENCER_122              0x307A
+#define WM8995_WRITE_SEQUENCER_123              0x307B
+#define WM8995_WRITE_SEQUENCER_124              0x307C
+#define WM8995_WRITE_SEQUENCER_125              0x307D
+#define WM8995_WRITE_SEQUENCER_126              0x307E
+#define WM8995_WRITE_SEQUENCER_127              0x307F
+#define WM8995_WRITE_SEQUENCER_128              0x3080
+#define WM8995_WRITE_SEQUENCER_129              0x3081
+#define WM8995_WRITE_SEQUENCER_130              0x3082
+#define WM8995_WRITE_SEQUENCER_131              0x3083
+#define WM8995_WRITE_SEQUENCER_132              0x3084
+#define WM8995_WRITE_SEQUENCER_133              0x3085
+#define WM8995_WRITE_SEQUENCER_134              0x3086
+#define WM8995_WRITE_SEQUENCER_135              0x3087
+#define WM8995_WRITE_SEQUENCER_136              0x3088
+#define WM8995_WRITE_SEQUENCER_137              0x3089
+#define WM8995_WRITE_SEQUENCER_138              0x308A
+#define WM8995_WRITE_SEQUENCER_139              0x308B
+#define WM8995_WRITE_SEQUENCER_140              0x308C
+#define WM8995_WRITE_SEQUENCER_141              0x308D
+#define WM8995_WRITE_SEQUENCER_142              0x308E
+#define WM8995_WRITE_SEQUENCER_143              0x308F
+#define WM8995_WRITE_SEQUENCER_144              0x3090
+#define WM8995_WRITE_SEQUENCER_145              0x3091
+#define WM8995_WRITE_SEQUENCER_146              0x3092
+#define WM8995_WRITE_SEQUENCER_147              0x3093
+#define WM8995_WRITE_SEQUENCER_148              0x3094
+#define WM8995_WRITE_SEQUENCER_149              0x3095
+#define WM8995_WRITE_SEQUENCER_150              0x3096
+#define WM8995_WRITE_SEQUENCER_151              0x3097
+#define WM8995_WRITE_SEQUENCER_152              0x3098
+#define WM8995_WRITE_SEQUENCER_153              0x3099
+#define WM8995_WRITE_SEQUENCER_154              0x309A
+#define WM8995_WRITE_SEQUENCER_155              0x309B
+#define WM8995_WRITE_SEQUENCER_156              0x309C
+#define WM8995_WRITE_SEQUENCER_157              0x309D
+#define WM8995_WRITE_SEQUENCER_158              0x309E
+#define WM8995_WRITE_SEQUENCER_159              0x309F
+#define WM8995_WRITE_SEQUENCER_160              0x30A0
+#define WM8995_WRITE_SEQUENCER_161              0x30A1
+#define WM8995_WRITE_SEQUENCER_162              0x30A2
+#define WM8995_WRITE_SEQUENCER_163              0x30A3
+#define WM8995_WRITE_SEQUENCER_164              0x30A4
+#define WM8995_WRITE_SEQUENCER_165              0x30A5
+#define WM8995_WRITE_SEQUENCER_166              0x30A6
+#define WM8995_WRITE_SEQUENCER_167              0x30A7
+#define WM8995_WRITE_SEQUENCER_168              0x30A8
+#define WM8995_WRITE_SEQUENCER_169              0x30A9
+#define WM8995_WRITE_SEQUENCER_170              0x30AA
+#define WM8995_WRITE_SEQUENCER_171              0x30AB
+#define WM8995_WRITE_SEQUENCER_172              0x30AC
+#define WM8995_WRITE_SEQUENCER_173              0x30AD
+#define WM8995_WRITE_SEQUENCER_174              0x30AE
+#define WM8995_WRITE_SEQUENCER_175              0x30AF
+#define WM8995_WRITE_SEQUENCER_176              0x30B0
+#define WM8995_WRITE_SEQUENCER_177              0x30B1
+#define WM8995_WRITE_SEQUENCER_178              0x30B2
+#define WM8995_WRITE_SEQUENCER_179              0x30B3
+#define WM8995_WRITE_SEQUENCER_180              0x30B4
+#define WM8995_WRITE_SEQUENCER_181              0x30B5
+#define WM8995_WRITE_SEQUENCER_182              0x30B6
+#define WM8995_WRITE_SEQUENCER_183              0x30B7
+#define WM8995_WRITE_SEQUENCER_184              0x30B8
+#define WM8995_WRITE_SEQUENCER_185              0x30B9
+#define WM8995_WRITE_SEQUENCER_186              0x30BA
+#define WM8995_WRITE_SEQUENCER_187              0x30BB
+#define WM8995_WRITE_SEQUENCER_188              0x30BC
+#define WM8995_WRITE_SEQUENCER_189              0x30BD
+#define WM8995_WRITE_SEQUENCER_190              0x30BE
+#define WM8995_WRITE_SEQUENCER_191              0x30BF
+#define WM8995_WRITE_SEQUENCER_192              0x30C0
+#define WM8995_WRITE_SEQUENCER_193              0x30C1
+#define WM8995_WRITE_SEQUENCER_194              0x30C2
+#define WM8995_WRITE_SEQUENCER_195              0x30C3
+#define WM8995_WRITE_SEQUENCER_196              0x30C4
+#define WM8995_WRITE_SEQUENCER_197              0x30C5
+#define WM8995_WRITE_SEQUENCER_198              0x30C6
+#define WM8995_WRITE_SEQUENCER_199              0x30C7
+#define WM8995_WRITE_SEQUENCER_200              0x30C8
+#define WM8995_WRITE_SEQUENCER_201              0x30C9
+#define WM8995_WRITE_SEQUENCER_202              0x30CA
+#define WM8995_WRITE_SEQUENCER_203              0x30CB
+#define WM8995_WRITE_SEQUENCER_204              0x30CC
+#define WM8995_WRITE_SEQUENCER_205              0x30CD
+#define WM8995_WRITE_SEQUENCER_206              0x30CE
+#define WM8995_WRITE_SEQUENCER_207              0x30CF
+#define WM8995_WRITE_SEQUENCER_208              0x30D0
+#define WM8995_WRITE_SEQUENCER_209              0x30D1
+#define WM8995_WRITE_SEQUENCER_210              0x30D2
+#define WM8995_WRITE_SEQUENCER_211              0x30D3
+#define WM8995_WRITE_SEQUENCER_212              0x30D4
+#define WM8995_WRITE_SEQUENCER_213              0x30D5
+#define WM8995_WRITE_SEQUENCER_214              0x30D6
+#define WM8995_WRITE_SEQUENCER_215              0x30D7
+#define WM8995_WRITE_SEQUENCER_216              0x30D8
+#define WM8995_WRITE_SEQUENCER_217              0x30D9
+#define WM8995_WRITE_SEQUENCER_218              0x30DA
+#define WM8995_WRITE_SEQUENCER_219              0x30DB
+#define WM8995_WRITE_SEQUENCER_220              0x30DC
+#define WM8995_WRITE_SEQUENCER_221              0x30DD
+#define WM8995_WRITE_SEQUENCER_222              0x30DE
+#define WM8995_WRITE_SEQUENCER_223              0x30DF
+#define WM8995_WRITE_SEQUENCER_224              0x30E0
+#define WM8995_WRITE_SEQUENCER_225              0x30E1
+#define WM8995_WRITE_SEQUENCER_226              0x30E2
+#define WM8995_WRITE_SEQUENCER_227              0x30E3
+#define WM8995_WRITE_SEQUENCER_228              0x30E4
+#define WM8995_WRITE_SEQUENCER_229              0x30E5
+#define WM8995_WRITE_SEQUENCER_230              0x30E6
+#define WM8995_WRITE_SEQUENCER_231              0x30E7
+#define WM8995_WRITE_SEQUENCER_232              0x30E8
+#define WM8995_WRITE_SEQUENCER_233              0x30E9
+#define WM8995_WRITE_SEQUENCER_234              0x30EA
+#define WM8995_WRITE_SEQUENCER_235              0x30EB
+#define WM8995_WRITE_SEQUENCER_236              0x30EC
+#define WM8995_WRITE_SEQUENCER_237              0x30ED
+#define WM8995_WRITE_SEQUENCER_238              0x30EE
+#define WM8995_WRITE_SEQUENCER_239              0x30EF
+#define WM8995_WRITE_SEQUENCER_240              0x30F0
+#define WM8995_WRITE_SEQUENCER_241              0x30F1
+#define WM8995_WRITE_SEQUENCER_242              0x30F2
+#define WM8995_WRITE_SEQUENCER_243              0x30F3
+#define WM8995_WRITE_SEQUENCER_244              0x30F4
+#define WM8995_WRITE_SEQUENCER_245              0x30F5
+#define WM8995_WRITE_SEQUENCER_246              0x30F6
+#define WM8995_WRITE_SEQUENCER_247              0x30F7
+#define WM8995_WRITE_SEQUENCER_248              0x30F8
+#define WM8995_WRITE_SEQUENCER_249              0x30F9
+#define WM8995_WRITE_SEQUENCER_250              0x30FA
+#define WM8995_WRITE_SEQUENCER_251              0x30FB
+#define WM8995_WRITE_SEQUENCER_252              0x30FC
+#define WM8995_WRITE_SEQUENCER_253              0x30FD
+#define WM8995_WRITE_SEQUENCER_254              0x30FE
+#define WM8995_WRITE_SEQUENCER_255              0x30FF
+#define WM8995_WRITE_SEQUENCER_256              0x3100
+#define WM8995_WRITE_SEQUENCER_257              0x3101
+#define WM8995_WRITE_SEQUENCER_258              0x3102
+#define WM8995_WRITE_SEQUENCER_259              0x3103
+#define WM8995_WRITE_SEQUENCER_260              0x3104
+#define WM8995_WRITE_SEQUENCER_261              0x3105
+#define WM8995_WRITE_SEQUENCER_262              0x3106
+#define WM8995_WRITE_SEQUENCER_263              0x3107
+#define WM8995_WRITE_SEQUENCER_264              0x3108
+#define WM8995_WRITE_SEQUENCER_265              0x3109
+#define WM8995_WRITE_SEQUENCER_266              0x310A
+#define WM8995_WRITE_SEQUENCER_267              0x310B
+#define WM8995_WRITE_SEQUENCER_268              0x310C
+#define WM8995_WRITE_SEQUENCER_269              0x310D
+#define WM8995_WRITE_SEQUENCER_270              0x310E
+#define WM8995_WRITE_SEQUENCER_271              0x310F
+#define WM8995_WRITE_SEQUENCER_272              0x3110
+#define WM8995_WRITE_SEQUENCER_273              0x3111
+#define WM8995_WRITE_SEQUENCER_274              0x3112
+#define WM8995_WRITE_SEQUENCER_275              0x3113
+#define WM8995_WRITE_SEQUENCER_276              0x3114
+#define WM8995_WRITE_SEQUENCER_277              0x3115
+#define WM8995_WRITE_SEQUENCER_278              0x3116
+#define WM8995_WRITE_SEQUENCER_279              0x3117
+#define WM8995_WRITE_SEQUENCER_280              0x3118
+#define WM8995_WRITE_SEQUENCER_281              0x3119
+#define WM8995_WRITE_SEQUENCER_282              0x311A
+#define WM8995_WRITE_SEQUENCER_283              0x311B
+#define WM8995_WRITE_SEQUENCER_284              0x311C
+#define WM8995_WRITE_SEQUENCER_285              0x311D
+#define WM8995_WRITE_SEQUENCER_286              0x311E
+#define WM8995_WRITE_SEQUENCER_287              0x311F
+#define WM8995_WRITE_SEQUENCER_288              0x3120
+#define WM8995_WRITE_SEQUENCER_289              0x3121
+#define WM8995_WRITE_SEQUENCER_290              0x3122
+#define WM8995_WRITE_SEQUENCER_291              0x3123
+#define WM8995_WRITE_SEQUENCER_292              0x3124
+#define WM8995_WRITE_SEQUENCER_293              0x3125
+#define WM8995_WRITE_SEQUENCER_294              0x3126
+#define WM8995_WRITE_SEQUENCER_295              0x3127
+#define WM8995_WRITE_SEQUENCER_296              0x3128
+#define WM8995_WRITE_SEQUENCER_297              0x3129
+#define WM8995_WRITE_SEQUENCER_298              0x312A
+#define WM8995_WRITE_SEQUENCER_299              0x312B
+#define WM8995_WRITE_SEQUENCER_300              0x312C
+#define WM8995_WRITE_SEQUENCER_301              0x312D
+#define WM8995_WRITE_SEQUENCER_302              0x312E
+#define WM8995_WRITE_SEQUENCER_303              0x312F
+#define WM8995_WRITE_SEQUENCER_304              0x3130
+#define WM8995_WRITE_SEQUENCER_305              0x3131
+#define WM8995_WRITE_SEQUENCER_306              0x3132
+#define WM8995_WRITE_SEQUENCER_307              0x3133
+#define WM8995_WRITE_SEQUENCER_308              0x3134
+#define WM8995_WRITE_SEQUENCER_309              0x3135
+#define WM8995_WRITE_SEQUENCER_310              0x3136
+#define WM8995_WRITE_SEQUENCER_311              0x3137
+#define WM8995_WRITE_SEQUENCER_312              0x3138
+#define WM8995_WRITE_SEQUENCER_313              0x3139
+#define WM8995_WRITE_SEQUENCER_314              0x313A
+#define WM8995_WRITE_SEQUENCER_315              0x313B
+#define WM8995_WRITE_SEQUENCER_316              0x313C
+#define WM8995_WRITE_SEQUENCER_317              0x313D
+#define WM8995_WRITE_SEQUENCER_318              0x313E
+#define WM8995_WRITE_SEQUENCER_319              0x313F
+#define WM8995_WRITE_SEQUENCER_320              0x3140
+#define WM8995_WRITE_SEQUENCER_321              0x3141
+#define WM8995_WRITE_SEQUENCER_322              0x3142
+#define WM8995_WRITE_SEQUENCER_323              0x3143
+#define WM8995_WRITE_SEQUENCER_324              0x3144
+#define WM8995_WRITE_SEQUENCER_325              0x3145
+#define WM8995_WRITE_SEQUENCER_326              0x3146
+#define WM8995_WRITE_SEQUENCER_327              0x3147
+#define WM8995_WRITE_SEQUENCER_328              0x3148
+#define WM8995_WRITE_SEQUENCER_329              0x3149
+#define WM8995_WRITE_SEQUENCER_330              0x314A
+#define WM8995_WRITE_SEQUENCER_331              0x314B
+#define WM8995_WRITE_SEQUENCER_332              0x314C
+#define WM8995_WRITE_SEQUENCER_333              0x314D
+#define WM8995_WRITE_SEQUENCER_334              0x314E
+#define WM8995_WRITE_SEQUENCER_335              0x314F
+#define WM8995_WRITE_SEQUENCER_336              0x3150
+#define WM8995_WRITE_SEQUENCER_337              0x3151
+#define WM8995_WRITE_SEQUENCER_338              0x3152
+#define WM8995_WRITE_SEQUENCER_339              0x3153
+#define WM8995_WRITE_SEQUENCER_340              0x3154
+#define WM8995_WRITE_SEQUENCER_341              0x3155
+#define WM8995_WRITE_SEQUENCER_342              0x3156
+#define WM8995_WRITE_SEQUENCER_343              0x3157
+#define WM8995_WRITE_SEQUENCER_344              0x3158
+#define WM8995_WRITE_SEQUENCER_345              0x3159
+#define WM8995_WRITE_SEQUENCER_346              0x315A
+#define WM8995_WRITE_SEQUENCER_347              0x315B
+#define WM8995_WRITE_SEQUENCER_348              0x315C
+#define WM8995_WRITE_SEQUENCER_349              0x315D
+#define WM8995_WRITE_SEQUENCER_350              0x315E
+#define WM8995_WRITE_SEQUENCER_351              0x315F
+#define WM8995_WRITE_SEQUENCER_352              0x3160
+#define WM8995_WRITE_SEQUENCER_353              0x3161
+#define WM8995_WRITE_SEQUENCER_354              0x3162
+#define WM8995_WRITE_SEQUENCER_355              0x3163
+#define WM8995_WRITE_SEQUENCER_356              0x3164
+#define WM8995_WRITE_SEQUENCER_357              0x3165
+#define WM8995_WRITE_SEQUENCER_358              0x3166
+#define WM8995_WRITE_SEQUENCER_359              0x3167
+#define WM8995_WRITE_SEQUENCER_360              0x3168
+#define WM8995_WRITE_SEQUENCER_361              0x3169
+#define WM8995_WRITE_SEQUENCER_362              0x316A
+#define WM8995_WRITE_SEQUENCER_363              0x316B
+#define WM8995_WRITE_SEQUENCER_364              0x316C
+#define WM8995_WRITE_SEQUENCER_365              0x316D
+#define WM8995_WRITE_SEQUENCER_366              0x316E
+#define WM8995_WRITE_SEQUENCER_367              0x316F
+#define WM8995_WRITE_SEQUENCER_368              0x3170
+#define WM8995_WRITE_SEQUENCER_369              0x3171
+#define WM8995_WRITE_SEQUENCER_370              0x3172
+#define WM8995_WRITE_SEQUENCER_371              0x3173
+#define WM8995_WRITE_SEQUENCER_372              0x3174
+#define WM8995_WRITE_SEQUENCER_373              0x3175
+#define WM8995_WRITE_SEQUENCER_374              0x3176
+#define WM8995_WRITE_SEQUENCER_375              0x3177
+#define WM8995_WRITE_SEQUENCER_376              0x3178
+#define WM8995_WRITE_SEQUENCER_377              0x3179
+#define WM8995_WRITE_SEQUENCER_378              0x317A
+#define WM8995_WRITE_SEQUENCER_379              0x317B
+#define WM8995_WRITE_SEQUENCER_380              0x317C
+#define WM8995_WRITE_SEQUENCER_381              0x317D
+#define WM8995_WRITE_SEQUENCER_382              0x317E
+#define WM8995_WRITE_SEQUENCER_383              0x317F
+#define WM8995_WRITE_SEQUENCER_384              0x3180
+#define WM8995_WRITE_SEQUENCER_385              0x3181
+#define WM8995_WRITE_SEQUENCER_386              0x3182
+#define WM8995_WRITE_SEQUENCER_387              0x3183
+#define WM8995_WRITE_SEQUENCER_388              0x3184
+#define WM8995_WRITE_SEQUENCER_389              0x3185
+#define WM8995_WRITE_SEQUENCER_390              0x3186
+#define WM8995_WRITE_SEQUENCER_391              0x3187
+#define WM8995_WRITE_SEQUENCER_392              0x3188
+#define WM8995_WRITE_SEQUENCER_393              0x3189
+#define WM8995_WRITE_SEQUENCER_394              0x318A
+#define WM8995_WRITE_SEQUENCER_395              0x318B
+#define WM8995_WRITE_SEQUENCER_396              0x318C
+#define WM8995_WRITE_SEQUENCER_397              0x318D
+#define WM8995_WRITE_SEQUENCER_398              0x318E
+#define WM8995_WRITE_SEQUENCER_399              0x318F
+#define WM8995_WRITE_SEQUENCER_400              0x3190
+#define WM8995_WRITE_SEQUENCER_401              0x3191
+#define WM8995_WRITE_SEQUENCER_402              0x3192
+#define WM8995_WRITE_SEQUENCER_403              0x3193
+#define WM8995_WRITE_SEQUENCER_404              0x3194
+#define WM8995_WRITE_SEQUENCER_405              0x3195
+#define WM8995_WRITE_SEQUENCER_406              0x3196
+#define WM8995_WRITE_SEQUENCER_407              0x3197
+#define WM8995_WRITE_SEQUENCER_408              0x3198
+#define WM8995_WRITE_SEQUENCER_409              0x3199
+#define WM8995_WRITE_SEQUENCER_410              0x319A
+#define WM8995_WRITE_SEQUENCER_411              0x319B
+#define WM8995_WRITE_SEQUENCER_412              0x319C
+#define WM8995_WRITE_SEQUENCER_413              0x319D
+#define WM8995_WRITE_SEQUENCER_414              0x319E
+#define WM8995_WRITE_SEQUENCER_415              0x319F
+#define WM8995_WRITE_SEQUENCER_416              0x31A0
+#define WM8995_WRITE_SEQUENCER_417              0x31A1
+#define WM8995_WRITE_SEQUENCER_418              0x31A2
+#define WM8995_WRITE_SEQUENCER_419              0x31A3
+#define WM8995_WRITE_SEQUENCER_420              0x31A4
+#define WM8995_WRITE_SEQUENCER_421              0x31A5
+#define WM8995_WRITE_SEQUENCER_422              0x31A6
+#define WM8995_WRITE_SEQUENCER_423              0x31A7
+#define WM8995_WRITE_SEQUENCER_424              0x31A8
+#define WM8995_WRITE_SEQUENCER_425              0x31A9
+#define WM8995_WRITE_SEQUENCER_426              0x31AA
+#define WM8995_WRITE_SEQUENCER_427              0x31AB
+#define WM8995_WRITE_SEQUENCER_428              0x31AC
+#define WM8995_WRITE_SEQUENCER_429              0x31AD
+#define WM8995_WRITE_SEQUENCER_430              0x31AE
+#define WM8995_WRITE_SEQUENCER_431              0x31AF
+#define WM8995_WRITE_SEQUENCER_432              0x31B0
+#define WM8995_WRITE_SEQUENCER_433              0x31B1
+#define WM8995_WRITE_SEQUENCER_434              0x31B2
+#define WM8995_WRITE_SEQUENCER_435              0x31B3
+#define WM8995_WRITE_SEQUENCER_436              0x31B4
+#define WM8995_WRITE_SEQUENCER_437              0x31B5
+#define WM8995_WRITE_SEQUENCER_438              0x31B6
+#define WM8995_WRITE_SEQUENCER_439              0x31B7
+#define WM8995_WRITE_SEQUENCER_440              0x31B8
+#define WM8995_WRITE_SEQUENCER_441              0x31B9
+#define WM8995_WRITE_SEQUENCER_442              0x31BA
+#define WM8995_WRITE_SEQUENCER_443              0x31BB
+#define WM8995_WRITE_SEQUENCER_444              0x31BC
+#define WM8995_WRITE_SEQUENCER_445              0x31BD
+#define WM8995_WRITE_SEQUENCER_446              0x31BE
+#define WM8995_WRITE_SEQUENCER_447              0x31BF
+#define WM8995_WRITE_SEQUENCER_448              0x31C0
+#define WM8995_WRITE_SEQUENCER_449              0x31C1
+#define WM8995_WRITE_SEQUENCER_450              0x31C2
+#define WM8995_WRITE_SEQUENCER_451              0x31C3
+#define WM8995_WRITE_SEQUENCER_452              0x31C4
+#define WM8995_WRITE_SEQUENCER_453              0x31C5
+#define WM8995_WRITE_SEQUENCER_454              0x31C6
+#define WM8995_WRITE_SEQUENCER_455              0x31C7
+#define WM8995_WRITE_SEQUENCER_456              0x31C8
+#define WM8995_WRITE_SEQUENCER_457              0x31C9
+#define WM8995_WRITE_SEQUENCER_458              0x31CA
+#define WM8995_WRITE_SEQUENCER_459              0x31CB
+#define WM8995_WRITE_SEQUENCER_460              0x31CC
+#define WM8995_WRITE_SEQUENCER_461              0x31CD
+#define WM8995_WRITE_SEQUENCER_462              0x31CE
+#define WM8995_WRITE_SEQUENCER_463              0x31CF
+#define WM8995_WRITE_SEQUENCER_464              0x31D0
+#define WM8995_WRITE_SEQUENCER_465              0x31D1
+#define WM8995_WRITE_SEQUENCER_466              0x31D2
+#define WM8995_WRITE_SEQUENCER_467              0x31D3
+#define WM8995_WRITE_SEQUENCER_468              0x31D4
+#define WM8995_WRITE_SEQUENCER_469              0x31D5
+#define WM8995_WRITE_SEQUENCER_470              0x31D6
+#define WM8995_WRITE_SEQUENCER_471              0x31D7
+#define WM8995_WRITE_SEQUENCER_472              0x31D8
+#define WM8995_WRITE_SEQUENCER_473              0x31D9
+#define WM8995_WRITE_SEQUENCER_474              0x31DA
+#define WM8995_WRITE_SEQUENCER_475              0x31DB
+#define WM8995_WRITE_SEQUENCER_476              0x31DC
+#define WM8995_WRITE_SEQUENCER_477              0x31DD
+#define WM8995_WRITE_SEQUENCER_478              0x31DE
+#define WM8995_WRITE_SEQUENCER_479              0x31DF
+#define WM8995_WRITE_SEQUENCER_480              0x31E0
+#define WM8995_WRITE_SEQUENCER_481              0x31E1
+#define WM8995_WRITE_SEQUENCER_482              0x31E2
+#define WM8995_WRITE_SEQUENCER_483              0x31E3
+#define WM8995_WRITE_SEQUENCER_484              0x31E4
+#define WM8995_WRITE_SEQUENCER_485              0x31E5
+#define WM8995_WRITE_SEQUENCER_486              0x31E6
+#define WM8995_WRITE_SEQUENCER_487              0x31E7
+#define WM8995_WRITE_SEQUENCER_488              0x31E8
+#define WM8995_WRITE_SEQUENCER_489              0x31E9
+#define WM8995_WRITE_SEQUENCER_490              0x31EA
+#define WM8995_WRITE_SEQUENCER_491              0x31EB
+#define WM8995_WRITE_SEQUENCER_492              0x31EC
+#define WM8995_WRITE_SEQUENCER_493              0x31ED
+#define WM8995_WRITE_SEQUENCER_494              0x31EE
+#define WM8995_WRITE_SEQUENCER_495              0x31EF
+#define WM8995_WRITE_SEQUENCER_496              0x31F0
+#define WM8995_WRITE_SEQUENCER_497              0x31F1
+#define WM8995_WRITE_SEQUENCER_498              0x31F2
+#define WM8995_WRITE_SEQUENCER_499              0x31F3
+#define WM8995_WRITE_SEQUENCER_500              0x31F4
+#define WM8995_WRITE_SEQUENCER_501              0x31F5
+#define WM8995_WRITE_SEQUENCER_502              0x31F6
+#define WM8995_WRITE_SEQUENCER_503              0x31F7
+#define WM8995_WRITE_SEQUENCER_504              0x31F8
+#define WM8995_WRITE_SEQUENCER_505              0x31F9
+#define WM8995_WRITE_SEQUENCER_506              0x31FA
+#define WM8995_WRITE_SEQUENCER_507              0x31FB
+#define WM8995_WRITE_SEQUENCER_508              0x31FC
+#define WM8995_WRITE_SEQUENCER_509              0x31FD
+#define WM8995_WRITE_SEQUENCER_510              0x31FE
+#define WM8995_WRITE_SEQUENCER_511              0x31FF
+
+#define WM8995_REGISTER_COUNT                   725
+#define WM8995_MAX_REGISTER                     0x31FF
+
+#define WM8995_MAX_CACHED_REGISTER              WM8995_MAX_REGISTER
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Software Reset
+ */
+#define WM8995_SW_RESET_MASK                    0xFFFF  /* SW_RESET - [15:0] */
+#define WM8995_SW_RESET_SHIFT                        0  /* SW_RESET - [15:0] */
+#define WM8995_SW_RESET_WIDTH                       16  /* SW_RESET - [15:0] */
+
+/*
+ * R1 (0x01) - Power Management (1)
+ */
+#define WM8995_MICB2_ENA                        0x0200  /* MICB2_ENA */
+#define WM8995_MICB2_ENA_MASK                   0x0200  /* MICB2_ENA */
+#define WM8995_MICB2_ENA_SHIFT                       9  /* MICB2_ENA */
+#define WM8995_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
+#define WM8995_MICB1_ENA                        0x0100  /* MICB1_ENA */
+#define WM8995_MICB1_ENA_MASK                   0x0100  /* MICB1_ENA */
+#define WM8995_MICB1_ENA_SHIFT                       8  /* MICB1_ENA */
+#define WM8995_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
+#define WM8995_HPOUT2L_ENA                      0x0080  /* HPOUT2L_ENA */
+#define WM8995_HPOUT2L_ENA_MASK                 0x0080  /* HPOUT2L_ENA */
+#define WM8995_HPOUT2L_ENA_SHIFT                     7  /* HPOUT2L_ENA */
+#define WM8995_HPOUT2L_ENA_WIDTH                     1  /* HPOUT2L_ENA */
+#define WM8995_HPOUT2R_ENA                      0x0040  /* HPOUT2R_ENA */
+#define WM8995_HPOUT2R_ENA_MASK                 0x0040  /* HPOUT2R_ENA */
+#define WM8995_HPOUT2R_ENA_SHIFT                     6  /* HPOUT2R_ENA */
+#define WM8995_HPOUT2R_ENA_WIDTH                     1  /* HPOUT2R_ENA */
+#define WM8995_HPOUT1L_ENA                      0x0020  /* HPOUT1L_ENA */
+#define WM8995_HPOUT1L_ENA_MASK                 0x0020  /* HPOUT1L_ENA */
+#define WM8995_HPOUT1L_ENA_SHIFT                     5  /* HPOUT1L_ENA */
+#define WM8995_HPOUT1L_ENA_WIDTH                     1  /* HPOUT1L_ENA */
+#define WM8995_HPOUT1R_ENA                      0x0010  /* HPOUT1R_ENA */
+#define WM8995_HPOUT1R_ENA_MASK                 0x0010  /* HPOUT1R_ENA */
+#define WM8995_HPOUT1R_ENA_SHIFT                     4  /* HPOUT1R_ENA */
+#define WM8995_HPOUT1R_ENA_WIDTH                     1  /* HPOUT1R_ENA */
+#define WM8995_BG_ENA                           0x0001  /* BG_ENA */
+#define WM8995_BG_ENA_MASK                      0x0001  /* BG_ENA */
+#define WM8995_BG_ENA_SHIFT                          0  /* BG_ENA */
+#define WM8995_BG_ENA_WIDTH                          1  /* BG_ENA */
+
+/*
+ * R2 (0x02) - Power Management (2)
+ */
+#define WM8995_OPCLK_ENA                        0x0800  /* OPCLK_ENA */
+#define WM8995_OPCLK_ENA_MASK                   0x0800  /* OPCLK_ENA */
+#define WM8995_OPCLK_ENA_SHIFT                      11  /* OPCLK_ENA */
+#define WM8995_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
+#define WM8995_IN1L_ENA                         0x0020  /* IN1L_ENA */
+#define WM8995_IN1L_ENA_MASK                    0x0020  /* IN1L_ENA */
+#define WM8995_IN1L_ENA_SHIFT                        5  /* IN1L_ENA */
+#define WM8995_IN1L_ENA_WIDTH                        1  /* IN1L_ENA */
+#define WM8995_IN1R_ENA                         0x0010  /* IN1R_ENA */
+#define WM8995_IN1R_ENA_MASK                    0x0010  /* IN1R_ENA */
+#define WM8995_IN1R_ENA_SHIFT                        4  /* IN1R_ENA */
+#define WM8995_IN1R_ENA_WIDTH                        1  /* IN1R_ENA */
+#define WM8995_LDO2_ENA                         0x0002  /* LDO2_ENA */
+#define WM8995_LDO2_ENA_MASK                    0x0002  /* LDO2_ENA */
+#define WM8995_LDO2_ENA_SHIFT                        1  /* LDO2_ENA */
+#define WM8995_LDO2_ENA_WIDTH                        1  /* LDO2_ENA */
+
+/*
+ * R3 (0x03) - Power Management (3)
+ */
+#define WM8995_AIF2ADCL_ENA                     0x2000  /* AIF2ADCL_ENA */
+#define WM8995_AIF2ADCL_ENA_MASK                0x2000  /* AIF2ADCL_ENA */
+#define WM8995_AIF2ADCL_ENA_SHIFT                   13  /* AIF2ADCL_ENA */
+#define WM8995_AIF2ADCL_ENA_WIDTH                    1  /* AIF2ADCL_ENA */
+#define WM8995_AIF2ADCR_ENA                     0x1000  /* AIF2ADCR_ENA */
+#define WM8995_AIF2ADCR_ENA_MASK                0x1000  /* AIF2ADCR_ENA */
+#define WM8995_AIF2ADCR_ENA_SHIFT                   12  /* AIF2ADCR_ENA */
+#define WM8995_AIF2ADCR_ENA_WIDTH                    1  /* AIF2ADCR_ENA */
+#define WM8995_AIF1ADC2L_ENA                    0x0800  /* AIF1ADC2L_ENA */
+#define WM8995_AIF1ADC2L_ENA_MASK               0x0800  /* AIF1ADC2L_ENA */
+#define WM8995_AIF1ADC2L_ENA_SHIFT                  11  /* AIF1ADC2L_ENA */
+#define WM8995_AIF1ADC2L_ENA_WIDTH                   1  /* AIF1ADC2L_ENA */
+#define WM8995_AIF1ADC2R_ENA                    0x0400  /* AIF1ADC2R_ENA */
+#define WM8995_AIF1ADC2R_ENA_MASK               0x0400  /* AIF1ADC2R_ENA */
+#define WM8995_AIF1ADC2R_ENA_SHIFT                  10  /* AIF1ADC2R_ENA */
+#define WM8995_AIF1ADC2R_ENA_WIDTH                   1  /* AIF1ADC2R_ENA */
+#define WM8995_AIF1ADC1L_ENA                    0x0200  /* AIF1ADC1L_ENA */
+#define WM8995_AIF1ADC1L_ENA_MASK               0x0200  /* AIF1ADC1L_ENA */
+#define WM8995_AIF1ADC1L_ENA_SHIFT                   9  /* AIF1ADC1L_ENA */
+#define WM8995_AIF1ADC1L_ENA_WIDTH                   1  /* AIF1ADC1L_ENA */
+#define WM8995_AIF1ADC1R_ENA                    0x0100  /* AIF1ADC1R_ENA */
+#define WM8995_AIF1ADC1R_ENA_MASK               0x0100  /* AIF1ADC1R_ENA */
+#define WM8995_AIF1ADC1R_ENA_SHIFT                   8  /* AIF1ADC1R_ENA */
+#define WM8995_AIF1ADC1R_ENA_WIDTH                   1  /* AIF1ADC1R_ENA */
+#define WM8995_DMIC3L_ENA                       0x0080  /* DMIC3L_ENA */
+#define WM8995_DMIC3L_ENA_MASK                  0x0080  /* DMIC3L_ENA */
+#define WM8995_DMIC3L_ENA_SHIFT                      7  /* DMIC3L_ENA */
+#define WM8995_DMIC3L_ENA_WIDTH                      1  /* DMIC3L_ENA */
+#define WM8995_DMIC3R_ENA                       0x0040  /* DMIC3R_ENA */
+#define WM8995_DMIC3R_ENA_MASK                  0x0040  /* DMIC3R_ENA */
+#define WM8995_DMIC3R_ENA_SHIFT                      6  /* DMIC3R_ENA */
+#define WM8995_DMIC3R_ENA_WIDTH                      1  /* DMIC3R_ENA */
+#define WM8995_DMIC2L_ENA                       0x0020  /* DMIC2L_ENA */
+#define WM8995_DMIC2L_ENA_MASK                  0x0020  /* DMIC2L_ENA */
+#define WM8995_DMIC2L_ENA_SHIFT                      5  /* DMIC2L_ENA */
+#define WM8995_DMIC2L_ENA_WIDTH                      1  /* DMIC2L_ENA */
+#define WM8995_DMIC2R_ENA                       0x0010  /* DMIC2R_ENA */
+#define WM8995_DMIC2R_ENA_MASK                  0x0010  /* DMIC2R_ENA */
+#define WM8995_DMIC2R_ENA_SHIFT                      4  /* DMIC2R_ENA */
+#define WM8995_DMIC2R_ENA_WIDTH                      1  /* DMIC2R_ENA */
+#define WM8995_DMIC1L_ENA                       0x0008  /* DMIC1L_ENA */
+#define WM8995_DMIC1L_ENA_MASK                  0x0008  /* DMIC1L_ENA */
+#define WM8995_DMIC1L_ENA_SHIFT                      3  /* DMIC1L_ENA */
+#define WM8995_DMIC1L_ENA_WIDTH                      1  /* DMIC1L_ENA */
+#define WM8995_DMIC1R_ENA                       0x0004  /* DMIC1R_ENA */
+#define WM8995_DMIC1R_ENA_MASK                  0x0004  /* DMIC1R_ENA */
+#define WM8995_DMIC1R_ENA_SHIFT                      2  /* DMIC1R_ENA */
+#define WM8995_DMIC1R_ENA_WIDTH                      1  /* DMIC1R_ENA */
+#define WM8995_ADCL_ENA                         0x0002  /* ADCL_ENA */
+#define WM8995_ADCL_ENA_MASK                    0x0002  /* ADCL_ENA */
+#define WM8995_ADCL_ENA_SHIFT                        1  /* ADCL_ENA */
+#define WM8995_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
+#define WM8995_ADCR_ENA                         0x0001  /* ADCR_ENA */
+#define WM8995_ADCR_ENA_MASK                    0x0001  /* ADCR_ENA */
+#define WM8995_ADCR_ENA_SHIFT                        0  /* ADCR_ENA */
+#define WM8995_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
+
+/*
+ * R4 (0x04) - Power Management (4)
+ */
+#define WM8995_AIF2DACL_ENA                     0x2000  /* AIF2DACL_ENA */
+#define WM8995_AIF2DACL_ENA_MASK                0x2000  /* AIF2DACL_ENA */
+#define WM8995_AIF2DACL_ENA_SHIFT                   13  /* AIF2DACL_ENA */
+#define WM8995_AIF2DACL_ENA_WIDTH                    1  /* AIF2DACL_ENA */
+#define WM8995_AIF2DACR_ENA                     0x1000  /* AIF2DACR_ENA */
+#define WM8995_AIF2DACR_ENA_MASK                0x1000  /* AIF2DACR_ENA */
+#define WM8995_AIF2DACR_ENA_SHIFT                   12  /* AIF2DACR_ENA */
+#define WM8995_AIF2DACR_ENA_WIDTH                    1  /* AIF2DACR_ENA */
+#define WM8995_AIF1DAC2L_ENA                    0x0800  /* AIF1DAC2L_ENA */
+#define WM8995_AIF1DAC2L_ENA_MASK               0x0800  /* AIF1DAC2L_ENA */
+#define WM8995_AIF1DAC2L_ENA_SHIFT                  11  /* AIF1DAC2L_ENA */
+#define WM8995_AIF1DAC2L_ENA_WIDTH                   1  /* AIF1DAC2L_ENA */
+#define WM8995_AIF1DAC2R_ENA                    0x0400  /* AIF1DAC2R_ENA */
+#define WM8995_AIF1DAC2R_ENA_MASK               0x0400  /* AIF1DAC2R_ENA */
+#define WM8995_AIF1DAC2R_ENA_SHIFT                  10  /* AIF1DAC2R_ENA */
+#define WM8995_AIF1DAC2R_ENA_WIDTH                   1  /* AIF1DAC2R_ENA */
+#define WM8995_AIF1DAC1L_ENA                    0x0200  /* AIF1DAC1L_ENA */
+#define WM8995_AIF1DAC1L_ENA_MASK               0x0200  /* AIF1DAC1L_ENA */
+#define WM8995_AIF1DAC1L_ENA_SHIFT                   9  /* AIF1DAC1L_ENA */
+#define WM8995_AIF1DAC1L_ENA_WIDTH                   1  /* AIF1DAC1L_ENA */
+#define WM8995_AIF1DAC1R_ENA                    0x0100  /* AIF1DAC1R_ENA */
+#define WM8995_AIF1DAC1R_ENA_MASK               0x0100  /* AIF1DAC1R_ENA */
+#define WM8995_AIF1DAC1R_ENA_SHIFT                   8  /* AIF1DAC1R_ENA */
+#define WM8995_AIF1DAC1R_ENA_WIDTH                   1  /* AIF1DAC1R_ENA */
+#define WM8995_DAC2L_ENA                        0x0008  /* DAC2L_ENA */
+#define WM8995_DAC2L_ENA_MASK                   0x0008  /* DAC2L_ENA */
+#define WM8995_DAC2L_ENA_SHIFT                       3  /* DAC2L_ENA */
+#define WM8995_DAC2L_ENA_WIDTH                       1  /* DAC2L_ENA */
+#define WM8995_DAC2R_ENA                        0x0004  /* DAC2R_ENA */
+#define WM8995_DAC2R_ENA_MASK                   0x0004  /* DAC2R_ENA */
+#define WM8995_DAC2R_ENA_SHIFT                       2  /* DAC2R_ENA */
+#define WM8995_DAC2R_ENA_WIDTH                       1  /* DAC2R_ENA */
+#define WM8995_DAC1L_ENA                        0x0002  /* DAC1L_ENA */
+#define WM8995_DAC1L_ENA_MASK                   0x0002  /* DAC1L_ENA */
+#define WM8995_DAC1L_ENA_SHIFT                       1  /* DAC1L_ENA */
+#define WM8995_DAC1L_ENA_WIDTH                       1  /* DAC1L_ENA */
+#define WM8995_DAC1R_ENA                        0x0001  /* DAC1R_ENA */
+#define WM8995_DAC1R_ENA_MASK                   0x0001  /* DAC1R_ENA */
+#define WM8995_DAC1R_ENA_SHIFT                       0  /* DAC1R_ENA */
+#define WM8995_DAC1R_ENA_WIDTH                       1  /* DAC1R_ENA */
+
+/*
+ * R5 (0x05) - Power Management (5)
+ */
+#define WM8995_DMIC_SRC2_MASK                   0x0300  /* DMIC_SRC2 - [9:8] */
+#define WM8995_DMIC_SRC2_SHIFT                       8  /* DMIC_SRC2 - [9:8] */
+#define WM8995_DMIC_SRC2_WIDTH                       2  /* DMIC_SRC2 - [9:8] */
+#define WM8995_DMIC_SRC1_MASK                   0x00C0  /* DMIC_SRC1 - [7:6] */
+#define WM8995_DMIC_SRC1_SHIFT                       6  /* DMIC_SRC1 - [7:6] */
+#define WM8995_DMIC_SRC1_WIDTH                       2  /* DMIC_SRC1 - [7:6] */
+#define WM8995_AIF3_TRI                         0x0020  /* AIF3_TRI */
+#define WM8995_AIF3_TRI_MASK                    0x0020  /* AIF3_TRI */
+#define WM8995_AIF3_TRI_SHIFT                        5  /* AIF3_TRI */
+#define WM8995_AIF3_TRI_WIDTH                        1  /* AIF3_TRI */
+#define WM8995_AIF3_ADCDAT_SRC_MASK             0x0018  /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8995_AIF3_ADCDAT_SRC_SHIFT                 3  /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8995_AIF3_ADCDAT_SRC_WIDTH                 2  /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8995_AIF2_ADCDAT_SRC                  0x0004  /* AIF2_ADCDAT_SRC */
+#define WM8995_AIF2_ADCDAT_SRC_MASK             0x0004  /* AIF2_ADCDAT_SRC */
+#define WM8995_AIF2_ADCDAT_SRC_SHIFT                 2  /* AIF2_ADCDAT_SRC */
+#define WM8995_AIF2_ADCDAT_SRC_WIDTH                 1  /* AIF2_ADCDAT_SRC */
+#define WM8995_AIF2_DACDAT_SRC                  0x0002  /* AIF2_DACDAT_SRC */
+#define WM8995_AIF2_DACDAT_SRC_MASK             0x0002  /* AIF2_DACDAT_SRC */
+#define WM8995_AIF2_DACDAT_SRC_SHIFT                 1  /* AIF2_DACDAT_SRC */
+#define WM8995_AIF2_DACDAT_SRC_WIDTH                 1  /* AIF2_DACDAT_SRC */
+#define WM8995_AIF1_DACDAT_SRC                  0x0001  /* AIF1_DACDAT_SRC */
+#define WM8995_AIF1_DACDAT_SRC_MASK             0x0001  /* AIF1_DACDAT_SRC */
+#define WM8995_AIF1_DACDAT_SRC_SHIFT                 0  /* AIF1_DACDAT_SRC */
+#define WM8995_AIF1_DACDAT_SRC_WIDTH                 1  /* AIF1_DACDAT_SRC */
+
+/*
+ * R16 (0x10) - Left Line Input 1 Volume
+ */
+#define WM8995_IN1_VU                           0x0080  /* IN1_VU */
+#define WM8995_IN1_VU_MASK                      0x0080  /* IN1_VU */
+#define WM8995_IN1_VU_SHIFT                          7  /* IN1_VU */
+#define WM8995_IN1_VU_WIDTH                          1  /* IN1_VU */
+#define WM8995_IN1L_ZC                          0x0020  /* IN1L_ZC */
+#define WM8995_IN1L_ZC_MASK                     0x0020  /* IN1L_ZC */
+#define WM8995_IN1L_ZC_SHIFT                         5  /* IN1L_ZC */
+#define WM8995_IN1L_ZC_WIDTH                         1  /* IN1L_ZC */
+#define WM8995_IN1L_VOL_MASK                    0x001F  /* IN1L_VOL - [4:0] */
+#define WM8995_IN1L_VOL_SHIFT                        0  /* IN1L_VOL - [4:0] */
+#define WM8995_IN1L_VOL_WIDTH                        5  /* IN1L_VOL - [4:0] */
+
+/*
+ * R17 (0x11) - Right Line Input 1 Volume
+ */
+#define WM8995_IN1_VU                           0x0080  /* IN1_VU */
+#define WM8995_IN1_VU_MASK                      0x0080  /* IN1_VU */
+#define WM8995_IN1_VU_SHIFT                          7  /* IN1_VU */
+#define WM8995_IN1_VU_WIDTH                          1  /* IN1_VU */
+#define WM8995_IN1R_ZC                          0x0020  /* IN1R_ZC */
+#define WM8995_IN1R_ZC_MASK                     0x0020  /* IN1R_ZC */
+#define WM8995_IN1R_ZC_SHIFT                         5  /* IN1R_ZC */
+#define WM8995_IN1R_ZC_WIDTH                         1  /* IN1R_ZC */
+#define WM8995_IN1R_VOL_MASK                    0x001F  /* IN1R_VOL - [4:0] */
+#define WM8995_IN1R_VOL_SHIFT                        0  /* IN1R_VOL - [4:0] */
+#define WM8995_IN1R_VOL_WIDTH                        5  /* IN1R_VOL - [4:0] */
+
+/*
+ * R18 (0x12) - Left Line Input Control
+ */
+#define WM8995_IN1L_BOOST_MASK                  0x0030  /* IN1L_BOOST - [5:4] */
+#define WM8995_IN1L_BOOST_SHIFT                      4  /* IN1L_BOOST - [5:4] */
+#define WM8995_IN1L_BOOST_WIDTH                      2  /* IN1L_BOOST - [5:4] */
+#define WM8995_IN1L_MODE_MASK                   0x000C  /* IN1L_MODE - [3:2] */
+#define WM8995_IN1L_MODE_SHIFT                       2  /* IN1L_MODE - [3:2] */
+#define WM8995_IN1L_MODE_WIDTH                       2  /* IN1L_MODE - [3:2] */
+#define WM8995_IN1R_MODE_MASK                   0x0003  /* IN1R_MODE - [1:0] */
+#define WM8995_IN1R_MODE_SHIFT                       0  /* IN1R_MODE - [1:0] */
+#define WM8995_IN1R_MODE_WIDTH                       2  /* IN1R_MODE - [1:0] */
+
+/*
+ * R24 (0x18) - DAC1 Left Volume
+ */
+#define WM8995_DAC1L_MUTE                       0x0200  /* DAC1L_MUTE */
+#define WM8995_DAC1L_MUTE_MASK                  0x0200  /* DAC1L_MUTE */
+#define WM8995_DAC1L_MUTE_SHIFT                      9  /* DAC1L_MUTE */
+#define WM8995_DAC1L_MUTE_WIDTH                      1  /* DAC1L_MUTE */
+#define WM8995_DAC1_VU                          0x0100  /* DAC1_VU */
+#define WM8995_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
+#define WM8995_DAC1_VU_SHIFT                         8  /* DAC1_VU */
+#define WM8995_DAC1_VU_WIDTH                         1  /* DAC1_VU */
+#define WM8995_DAC1L_VOL_MASK                   0x00FF  /* DAC1L_VOL - [7:0] */
+#define WM8995_DAC1L_VOL_SHIFT                       0  /* DAC1L_VOL - [7:0] */
+#define WM8995_DAC1L_VOL_WIDTH                       8  /* DAC1L_VOL - [7:0] */
+
+/*
+ * R25 (0x19) - DAC1 Right Volume
+ */
+#define WM8995_DAC1R_MUTE                       0x0200  /* DAC1R_MUTE */
+#define WM8995_DAC1R_MUTE_MASK                  0x0200  /* DAC1R_MUTE */
+#define WM8995_DAC1R_MUTE_SHIFT                      9  /* DAC1R_MUTE */
+#define WM8995_DAC1R_MUTE_WIDTH                      1  /* DAC1R_MUTE */
+#define WM8995_DAC1_VU                          0x0100  /* DAC1_VU */
+#define WM8995_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
+#define WM8995_DAC1_VU_SHIFT                         8  /* DAC1_VU */
+#define WM8995_DAC1_VU_WIDTH                         1  /* DAC1_VU */
+#define WM8995_DAC1R_VOL_MASK                   0x00FF  /* DAC1R_VOL - [7:0] */
+#define WM8995_DAC1R_VOL_SHIFT                       0  /* DAC1R_VOL - [7:0] */
+#define WM8995_DAC1R_VOL_WIDTH                       8  /* DAC1R_VOL - [7:0] */
+
+/*
+ * R26 (0x1A) - DAC2 Left Volume
+ */
+#define WM8995_DAC2L_MUTE                       0x0200  /* DAC2L_MUTE */
+#define WM8995_DAC2L_MUTE_MASK                  0x0200  /* DAC2L_MUTE */
+#define WM8995_DAC2L_MUTE_SHIFT                      9  /* DAC2L_MUTE */
+#define WM8995_DAC2L_MUTE_WIDTH                      1  /* DAC2L_MUTE */
+#define WM8995_DAC2_VU                          0x0100  /* DAC2_VU */
+#define WM8995_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
+#define WM8995_DAC2_VU_SHIFT                         8  /* DAC2_VU */
+#define WM8995_DAC2_VU_WIDTH                         1  /* DAC2_VU */
+#define WM8995_DAC2L_VOL_MASK                   0x00FF  /* DAC2L_VOL - [7:0] */
+#define WM8995_DAC2L_VOL_SHIFT                       0  /* DAC2L_VOL - [7:0] */
+#define WM8995_DAC2L_VOL_WIDTH                       8  /* DAC2L_VOL - [7:0] */
+
+/*
+ * R27 (0x1B) - DAC2 Right Volume
+ */
+#define WM8995_DAC2R_MUTE                       0x0200  /* DAC2R_MUTE */
+#define WM8995_DAC2R_MUTE_MASK                  0x0200  /* DAC2R_MUTE */
+#define WM8995_DAC2R_MUTE_SHIFT                      9  /* DAC2R_MUTE */
+#define WM8995_DAC2R_MUTE_WIDTH                      1  /* DAC2R_MUTE */
+#define WM8995_DAC2_VU                          0x0100  /* DAC2_VU */
+#define WM8995_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
+#define WM8995_DAC2_VU_SHIFT                         8  /* DAC2_VU */
+#define WM8995_DAC2_VU_WIDTH                         1  /* DAC2_VU */
+#define WM8995_DAC2R_VOL_MASK                   0x00FF  /* DAC2R_VOL - [7:0] */
+#define WM8995_DAC2R_VOL_SHIFT                       0  /* DAC2R_VOL - [7:0] */
+#define WM8995_DAC2R_VOL_WIDTH                       8  /* DAC2R_VOL - [7:0] */
+
+/*
+ * R28 (0x1C) - Output Volume ZC (1)
+ */
+#define WM8995_HPOUT2L_ZC                       0x0008  /* HPOUT2L_ZC */
+#define WM8995_HPOUT2L_ZC_MASK                  0x0008  /* HPOUT2L_ZC */
+#define WM8995_HPOUT2L_ZC_SHIFT                      3  /* HPOUT2L_ZC */
+#define WM8995_HPOUT2L_ZC_WIDTH                      1  /* HPOUT2L_ZC */
+#define WM8995_HPOUT2R_ZC                       0x0004  /* HPOUT2R_ZC */
+#define WM8995_HPOUT2R_ZC_MASK                  0x0004  /* HPOUT2R_ZC */
+#define WM8995_HPOUT2R_ZC_SHIFT                      2  /* HPOUT2R_ZC */
+#define WM8995_HPOUT2R_ZC_WIDTH                      1  /* HPOUT2R_ZC */
+#define WM8995_HPOUT1L_ZC                       0x0002  /* HPOUT1L_ZC */
+#define WM8995_HPOUT1L_ZC_MASK                  0x0002  /* HPOUT1L_ZC */
+#define WM8995_HPOUT1L_ZC_SHIFT                      1  /* HPOUT1L_ZC */
+#define WM8995_HPOUT1L_ZC_WIDTH                      1  /* HPOUT1L_ZC */
+#define WM8995_HPOUT1R_ZC                       0x0001  /* HPOUT1R_ZC */
+#define WM8995_HPOUT1R_ZC_MASK                  0x0001  /* HPOUT1R_ZC */
+#define WM8995_HPOUT1R_ZC_SHIFT                      0  /* HPOUT1R_ZC */
+#define WM8995_HPOUT1R_ZC_WIDTH                      1  /* HPOUT1R_ZC */
+
+/*
+ * R32 (0x20) - MICBIAS (1)
+ */
+#define WM8995_MICB1_MODE                       0x0008  /* MICB1_MODE */
+#define WM8995_MICB1_MODE_MASK                  0x0008  /* MICB1_MODE */
+#define WM8995_MICB1_MODE_SHIFT                      3  /* MICB1_MODE */
+#define WM8995_MICB1_MODE_WIDTH                      1  /* MICB1_MODE */
+#define WM8995_MICB1_LVL_MASK                   0x0006  /* MICB1_LVL - [2:1] */
+#define WM8995_MICB1_LVL_SHIFT                       1  /* MICB1_LVL - [2:1] */
+#define WM8995_MICB1_LVL_WIDTH                       2  /* MICB1_LVL - [2:1] */
+#define WM8995_MICB1_DISCH                      0x0001  /* MICB1_DISCH */
+#define WM8995_MICB1_DISCH_MASK                 0x0001  /* MICB1_DISCH */
+#define WM8995_MICB1_DISCH_SHIFT                     0  /* MICB1_DISCH */
+#define WM8995_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
+
+/*
+ * R33 (0x21) - MICBIAS (2)
+ */
+#define WM8995_MICB2_MODE                       0x0008  /* MICB2_MODE */
+#define WM8995_MICB2_MODE_MASK                  0x0008  /* MICB2_MODE */
+#define WM8995_MICB2_MODE_SHIFT                      3  /* MICB2_MODE */
+#define WM8995_MICB2_MODE_WIDTH                      1  /* MICB2_MODE */
+#define WM8995_MICB2_LVL_MASK                   0x0006  /* MICB2_LVL - [2:1] */
+#define WM8995_MICB2_LVL_SHIFT                       1  /* MICB2_LVL - [2:1] */
+#define WM8995_MICB2_LVL_WIDTH                       2  /* MICB2_LVL - [2:1] */
+#define WM8995_MICB2_DISCH                      0x0001  /* MICB2_DISCH */
+#define WM8995_MICB2_DISCH_MASK                 0x0001  /* MICB2_DISCH */
+#define WM8995_MICB2_DISCH_SHIFT                     0  /* MICB2_DISCH */
+#define WM8995_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
+
+/*
+ * R40 (0x28) - LDO 1
+ */
+#define WM8995_LDO1_MODE                        0x0020  /* LDO1_MODE */
+#define WM8995_LDO1_MODE_MASK                   0x0020  /* LDO1_MODE */
+#define WM8995_LDO1_MODE_SHIFT                       5  /* LDO1_MODE */
+#define WM8995_LDO1_MODE_WIDTH                       1  /* LDO1_MODE */
+#define WM8995_LDO1_VSEL_MASK                   0x0006  /* LDO1_VSEL - [2:1] */
+#define WM8995_LDO1_VSEL_SHIFT                       1  /* LDO1_VSEL - [2:1] */
+#define WM8995_LDO1_VSEL_WIDTH                       2  /* LDO1_VSEL - [2:1] */
+#define WM8995_LDO1_DISCH                       0x0001  /* LDO1_DISCH */
+#define WM8995_LDO1_DISCH_MASK                  0x0001  /* LDO1_DISCH */
+#define WM8995_LDO1_DISCH_SHIFT                      0  /* LDO1_DISCH */
+#define WM8995_LDO1_DISCH_WIDTH                      1  /* LDO1_DISCH */
+
+/*
+ * R41 (0x29) - LDO 2
+ */
+#define WM8995_LDO2_MODE                        0x0020  /* LDO2_MODE */
+#define WM8995_LDO2_MODE_MASK                   0x0020  /* LDO2_MODE */
+#define WM8995_LDO2_MODE_SHIFT                       5  /* LDO2_MODE */
+#define WM8995_LDO2_MODE_WIDTH                       1  /* LDO2_MODE */
+#define WM8995_LDO2_VSEL_MASK                   0x001E  /* LDO2_VSEL - [4:1] */
+#define WM8995_LDO2_VSEL_SHIFT                       1  /* LDO2_VSEL - [4:1] */
+#define WM8995_LDO2_VSEL_WIDTH                       4  /* LDO2_VSEL - [4:1] */
+#define WM8995_LDO2_DISCH                       0x0001  /* LDO2_DISCH */
+#define WM8995_LDO2_DISCH_MASK                  0x0001  /* LDO2_DISCH */
+#define WM8995_LDO2_DISCH_SHIFT                      0  /* LDO2_DISCH */
+#define WM8995_LDO2_DISCH_WIDTH                      1  /* LDO2_DISCH */
+
+/*
+ * R48 (0x30) - Accessory Detect Mode1
+ */
+#define WM8995_JD_MODE_MASK                     0x0003  /* JD_MODE - [1:0] */
+#define WM8995_JD_MODE_SHIFT                         0  /* JD_MODE - [1:0] */
+#define WM8995_JD_MODE_WIDTH                         2  /* JD_MODE - [1:0] */
+
+/*
+ * R49 (0x31) - Accessory Detect Mode2
+ */
+#define WM8995_VID_ENA                          0x0001  /* VID_ENA */
+#define WM8995_VID_ENA_MASK                     0x0001  /* VID_ENA */
+#define WM8995_VID_ENA_SHIFT                         0  /* VID_ENA */
+#define WM8995_VID_ENA_WIDTH                         1  /* VID_ENA */
+
+/*
+ * R52 (0x34) - Headphone Detect1
+ */
+#define WM8995_HP_RAMPRATE                      0x0002  /* HP_RAMPRATE */
+#define WM8995_HP_RAMPRATE_MASK                 0x0002  /* HP_RAMPRATE */
+#define WM8995_HP_RAMPRATE_SHIFT                     1  /* HP_RAMPRATE */
+#define WM8995_HP_RAMPRATE_WIDTH                     1  /* HP_RAMPRATE */
+#define WM8995_HP_POLL                          0x0001  /* HP_POLL */
+#define WM8995_HP_POLL_MASK                     0x0001  /* HP_POLL */
+#define WM8995_HP_POLL_SHIFT                         0  /* HP_POLL */
+#define WM8995_HP_POLL_WIDTH                         1  /* HP_POLL */
+
+/*
+ * R53 (0x35) - Headphone Detect2
+ */
+#define WM8995_HP_DONE                          0x0080  /* HP_DONE */
+#define WM8995_HP_DONE_MASK                     0x0080  /* HP_DONE */
+#define WM8995_HP_DONE_SHIFT                         7  /* HP_DONE */
+#define WM8995_HP_DONE_WIDTH                         1  /* HP_DONE */
+#define WM8995_HP_LVL_MASK                      0x007F  /* HP_LVL - [6:0] */
+#define WM8995_HP_LVL_SHIFT                          0  /* HP_LVL - [6:0] */
+#define WM8995_HP_LVL_WIDTH                          7  /* HP_LVL - [6:0] */
+
+/*
+ * R56 (0x38) - Mic Detect (1)
+ */
+#define WM8995_MICD_RATE_MASK                   0x7800  /* MICD_RATE - [14:11] */
+#define WM8995_MICD_RATE_SHIFT                      11  /* MICD_RATE - [14:11] */
+#define WM8995_MICD_RATE_WIDTH                       4  /* MICD_RATE - [14:11] */
+#define WM8995_MICD_LVL_SEL_MASK                0x01F8  /* MICD_LVL_SEL - [8:3] */
+#define WM8995_MICD_LVL_SEL_SHIFT                    3  /* MICD_LVL_SEL - [8:3] */
+#define WM8995_MICD_LVL_SEL_WIDTH                    6  /* MICD_LVL_SEL - [8:3] */
+#define WM8995_MICD_DBTIME                      0x0002  /* MICD_DBTIME */
+#define WM8995_MICD_DBTIME_MASK                 0x0002  /* MICD_DBTIME */
+#define WM8995_MICD_DBTIME_SHIFT                     1  /* MICD_DBTIME */
+#define WM8995_MICD_DBTIME_WIDTH                     1  /* MICD_DBTIME */
+#define WM8995_MICD_ENA                         0x0001  /* MICD_ENA */
+#define WM8995_MICD_ENA_MASK                    0x0001  /* MICD_ENA */
+#define WM8995_MICD_ENA_SHIFT                        0  /* MICD_ENA */
+#define WM8995_MICD_ENA_WIDTH                        1  /* MICD_ENA */
+
+/*
+ * R57 (0x39) - Mic Detect (2)
+ */
+#define WM8995_MICD_LVL_MASK                    0x01FC  /* MICD_LVL - [8:2] */
+#define WM8995_MICD_LVL_SHIFT                        2  /* MICD_LVL - [8:2] */
+#define WM8995_MICD_LVL_WIDTH                        7  /* MICD_LVL - [8:2] */
+#define WM8995_MICD_VALID                       0x0002  /* MICD_VALID */
+#define WM8995_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
+#define WM8995_MICD_VALID_SHIFT                      1  /* MICD_VALID */
+#define WM8995_MICD_VALID_WIDTH                      1  /* MICD_VALID */
+#define WM8995_MICD_STS                         0x0001  /* MICD_STS */
+#define WM8995_MICD_STS_MASK                    0x0001  /* MICD_STS */
+#define WM8995_MICD_STS_SHIFT                        0  /* MICD_STS */
+#define WM8995_MICD_STS_WIDTH                        1  /* MICD_STS */
+
+/*
+ * R64 (0x40) - Charge Pump (1)
+ */
+#define WM8995_CP_ENA                           0x8000  /* CP_ENA */
+#define WM8995_CP_ENA_MASK                      0x8000  /* CP_ENA */
+#define WM8995_CP_ENA_SHIFT                         15  /* CP_ENA */
+#define WM8995_CP_ENA_WIDTH                          1  /* CP_ENA */
+
+/*
+ * R69 (0x45) - Class W (1)
+ */
+#define WM8995_CP_DYN_SRC_SEL_MASK              0x0300  /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8995_CP_DYN_SRC_SEL_SHIFT                  8  /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8995_CP_DYN_SRC_SEL_WIDTH                  2  /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8995_CP_DYN_PWR                       0x0001  /* CP_DYN_PWR */
+#define WM8995_CP_DYN_PWR_MASK                  0x0001  /* CP_DYN_PWR */
+#define WM8995_CP_DYN_PWR_SHIFT                      0  /* CP_DYN_PWR */
+#define WM8995_CP_DYN_PWR_WIDTH                      1  /* CP_DYN_PWR */
+
+/*
+ * R80 (0x50) - DC Servo (1)
+ */
+#define WM8995_DCS_ENA_CHAN_3                   0x0008  /* DCS_ENA_CHAN_3 */
+#define WM8995_DCS_ENA_CHAN_3_MASK              0x0008  /* DCS_ENA_CHAN_3 */
+#define WM8995_DCS_ENA_CHAN_3_SHIFT                  3  /* DCS_ENA_CHAN_3 */
+#define WM8995_DCS_ENA_CHAN_3_WIDTH                  1  /* DCS_ENA_CHAN_3 */
+#define WM8995_DCS_ENA_CHAN_2                   0x0004  /* DCS_ENA_CHAN_2 */
+#define WM8995_DCS_ENA_CHAN_2_MASK              0x0004  /* DCS_ENA_CHAN_2 */
+#define WM8995_DCS_ENA_CHAN_2_SHIFT                  2  /* DCS_ENA_CHAN_2 */
+#define WM8995_DCS_ENA_CHAN_2_WIDTH                  1  /* DCS_ENA_CHAN_2 */
+#define WM8995_DCS_ENA_CHAN_1                   0x0002  /* DCS_ENA_CHAN_1 */
+#define WM8995_DCS_ENA_CHAN_1_MASK              0x0002  /* DCS_ENA_CHAN_1 */
+#define WM8995_DCS_ENA_CHAN_1_SHIFT                  1  /* DCS_ENA_CHAN_1 */
+#define WM8995_DCS_ENA_CHAN_1_WIDTH                  1  /* DCS_ENA_CHAN_1 */
+#define WM8995_DCS_ENA_CHAN_0                   0x0001  /* DCS_ENA_CHAN_0 */
+#define WM8995_DCS_ENA_CHAN_0_MASK              0x0001  /* DCS_ENA_CHAN_0 */
+#define WM8995_DCS_ENA_CHAN_0_SHIFT                  0  /* DCS_ENA_CHAN_0 */
+#define WM8995_DCS_ENA_CHAN_0_WIDTH                  1  /* DCS_ENA_CHAN_0 */
+
+/*
+ * R81 (0x51) - DC Servo (2)
+ */
+#define WM8995_DCS_TRIG_SINGLE_3                0x8000  /* DCS_TRIG_SINGLE_3 */
+#define WM8995_DCS_TRIG_SINGLE_3_MASK           0x8000  /* DCS_TRIG_SINGLE_3 */
+#define WM8995_DCS_TRIG_SINGLE_3_SHIFT              15  /* DCS_TRIG_SINGLE_3 */
+#define WM8995_DCS_TRIG_SINGLE_3_WIDTH               1  /* DCS_TRIG_SINGLE_3 */
+#define WM8995_DCS_TRIG_SINGLE_2                0x4000  /* DCS_TRIG_SINGLE_2 */
+#define WM8995_DCS_TRIG_SINGLE_2_MASK           0x4000  /* DCS_TRIG_SINGLE_2 */
+#define WM8995_DCS_TRIG_SINGLE_2_SHIFT              14  /* DCS_TRIG_SINGLE_2 */
+#define WM8995_DCS_TRIG_SINGLE_2_WIDTH               1  /* DCS_TRIG_SINGLE_2 */
+#define WM8995_DCS_TRIG_SINGLE_1                0x2000  /* DCS_TRIG_SINGLE_1 */
+#define WM8995_DCS_TRIG_SINGLE_1_MASK           0x2000  /* DCS_TRIG_SINGLE_1 */
+#define WM8995_DCS_TRIG_SINGLE_1_SHIFT              13  /* DCS_TRIG_SINGLE_1 */
+#define WM8995_DCS_TRIG_SINGLE_1_WIDTH               1  /* DCS_TRIG_SINGLE_1 */
+#define WM8995_DCS_TRIG_SINGLE_0                0x1000  /* DCS_TRIG_SINGLE_0 */
+#define WM8995_DCS_TRIG_SINGLE_0_MASK           0x1000  /* DCS_TRIG_SINGLE_0 */
+#define WM8995_DCS_TRIG_SINGLE_0_SHIFT              12  /* DCS_TRIG_SINGLE_0 */
+#define WM8995_DCS_TRIG_SINGLE_0_WIDTH               1  /* DCS_TRIG_SINGLE_0 */
+#define WM8995_DCS_TRIG_SERIES_3                0x0800  /* DCS_TRIG_SERIES_3 */
+#define WM8995_DCS_TRIG_SERIES_3_MASK           0x0800  /* DCS_TRIG_SERIES_3 */
+#define WM8995_DCS_TRIG_SERIES_3_SHIFT              11  /* DCS_TRIG_SERIES_3 */
+#define WM8995_DCS_TRIG_SERIES_3_WIDTH               1  /* DCS_TRIG_SERIES_3 */
+#define WM8995_DCS_TRIG_SERIES_2                0x0400  /* DCS_TRIG_SERIES_2 */
+#define WM8995_DCS_TRIG_SERIES_2_MASK           0x0400  /* DCS_TRIG_SERIES_2 */
+#define WM8995_DCS_TRIG_SERIES_2_SHIFT              10  /* DCS_TRIG_SERIES_2 */
+#define WM8995_DCS_TRIG_SERIES_2_WIDTH               1  /* DCS_TRIG_SERIES_2 */
+#define WM8995_DCS_TRIG_SERIES_1                0x0200  /* DCS_TRIG_SERIES_1 */
+#define WM8995_DCS_TRIG_SERIES_1_MASK           0x0200  /* DCS_TRIG_SERIES_1 */
+#define WM8995_DCS_TRIG_SERIES_1_SHIFT               9  /* DCS_TRIG_SERIES_1 */
+#define WM8995_DCS_TRIG_SERIES_1_WIDTH               1  /* DCS_TRIG_SERIES_1 */
+#define WM8995_DCS_TRIG_SERIES_0                0x0100  /* DCS_TRIG_SERIES_0 */
+#define WM8995_DCS_TRIG_SERIES_0_MASK           0x0100  /* DCS_TRIG_SERIES_0 */
+#define WM8995_DCS_TRIG_SERIES_0_SHIFT               8  /* DCS_TRIG_SERIES_0 */
+#define WM8995_DCS_TRIG_SERIES_0_WIDTH               1  /* DCS_TRIG_SERIES_0 */
+#define WM8995_DCS_TRIG_STARTUP_3               0x0080  /* DCS_TRIG_STARTUP_3 */
+#define WM8995_DCS_TRIG_STARTUP_3_MASK          0x0080  /* DCS_TRIG_STARTUP_3 */
+#define WM8995_DCS_TRIG_STARTUP_3_SHIFT              7  /* DCS_TRIG_STARTUP_3 */
+#define WM8995_DCS_TRIG_STARTUP_3_WIDTH              1  /* DCS_TRIG_STARTUP_3 */
+#define WM8995_DCS_TRIG_STARTUP_2               0x0040  /* DCS_TRIG_STARTUP_2 */
+#define WM8995_DCS_TRIG_STARTUP_2_MASK          0x0040  /* DCS_TRIG_STARTUP_2 */
+#define WM8995_DCS_TRIG_STARTUP_2_SHIFT              6  /* DCS_TRIG_STARTUP_2 */
+#define WM8995_DCS_TRIG_STARTUP_2_WIDTH              1  /* DCS_TRIG_STARTUP_2 */
+#define WM8995_DCS_TRIG_STARTUP_1               0x0020  /* DCS_TRIG_STARTUP_1 */
+#define WM8995_DCS_TRIG_STARTUP_1_MASK          0x0020  /* DCS_TRIG_STARTUP_1 */
+#define WM8995_DCS_TRIG_STARTUP_1_SHIFT              5  /* DCS_TRIG_STARTUP_1 */
+#define WM8995_DCS_TRIG_STARTUP_1_WIDTH              1  /* DCS_TRIG_STARTUP_1 */
+#define WM8995_DCS_TRIG_STARTUP_0               0x0010  /* DCS_TRIG_STARTUP_0 */
+#define WM8995_DCS_TRIG_STARTUP_0_MASK          0x0010  /* DCS_TRIG_STARTUP_0 */
+#define WM8995_DCS_TRIG_STARTUP_0_SHIFT              4  /* DCS_TRIG_STARTUP_0 */
+#define WM8995_DCS_TRIG_STARTUP_0_WIDTH              1  /* DCS_TRIG_STARTUP_0 */
+#define WM8995_DCS_TRIG_DAC_WR_3                0x0008  /* DCS_TRIG_DAC_WR_3 */
+#define WM8995_DCS_TRIG_DAC_WR_3_MASK           0x0008  /* DCS_TRIG_DAC_WR_3 */
+#define WM8995_DCS_TRIG_DAC_WR_3_SHIFT               3  /* DCS_TRIG_DAC_WR_3 */
+#define WM8995_DCS_TRIG_DAC_WR_3_WIDTH               1  /* DCS_TRIG_DAC_WR_3 */
+#define WM8995_DCS_TRIG_DAC_WR_2                0x0004  /* DCS_TRIG_DAC_WR_2 */
+#define WM8995_DCS_TRIG_DAC_WR_2_MASK           0x0004  /* DCS_TRIG_DAC_WR_2 */
+#define WM8995_DCS_TRIG_DAC_WR_2_SHIFT               2  /* DCS_TRIG_DAC_WR_2 */
+#define WM8995_DCS_TRIG_DAC_WR_2_WIDTH               1  /* DCS_TRIG_DAC_WR_2 */
+#define WM8995_DCS_TRIG_DAC_WR_1                0x0002  /* DCS_TRIG_DAC_WR_1 */
+#define WM8995_DCS_TRIG_DAC_WR_1_MASK           0x0002  /* DCS_TRIG_DAC_WR_1 */
+#define WM8995_DCS_TRIG_DAC_WR_1_SHIFT               1  /* DCS_TRIG_DAC_WR_1 */
+#define WM8995_DCS_TRIG_DAC_WR_1_WIDTH               1  /* DCS_TRIG_DAC_WR_1 */
+#define WM8995_DCS_TRIG_DAC_WR_0                0x0001  /* DCS_TRIG_DAC_WR_0 */
+#define WM8995_DCS_TRIG_DAC_WR_0_MASK           0x0001  /* DCS_TRIG_DAC_WR_0 */
+#define WM8995_DCS_TRIG_DAC_WR_0_SHIFT               0  /* DCS_TRIG_DAC_WR_0 */
+#define WM8995_DCS_TRIG_DAC_WR_0_WIDTH               1  /* DCS_TRIG_DAC_WR_0 */
+
+/*
+ * R82 (0x52) - DC Servo (3)
+ */
+#define WM8995_DCS_TIMER_PERIOD_23_MASK         0x0F00  /* DCS_TIMER_PERIOD_23 - [11:8] */
+#define WM8995_DCS_TIMER_PERIOD_23_SHIFT             8  /* DCS_TIMER_PERIOD_23 - [11:8] */
+#define WM8995_DCS_TIMER_PERIOD_23_WIDTH             4  /* DCS_TIMER_PERIOD_23 - [11:8] */
+#define WM8995_DCS_TIMER_PERIOD_01_MASK         0x000F  /* DCS_TIMER_PERIOD_01 - [3:0] */
+#define WM8995_DCS_TIMER_PERIOD_01_SHIFT             0  /* DCS_TIMER_PERIOD_01 - [3:0] */
+#define WM8995_DCS_TIMER_PERIOD_01_WIDTH             4  /* DCS_TIMER_PERIOD_01 - [3:0] */
+
+/*
+ * R84 (0x54) - DC Servo (5)
+ */
+#define WM8995_DCS_SERIES_NO_23_MASK            0x7F00  /* DCS_SERIES_NO_23 - [14:8] */
+#define WM8995_DCS_SERIES_NO_23_SHIFT                8  /* DCS_SERIES_NO_23 - [14:8] */
+#define WM8995_DCS_SERIES_NO_23_WIDTH                7  /* DCS_SERIES_NO_23 - [14:8] */
+#define WM8995_DCS_SERIES_NO_01_MASK            0x007F  /* DCS_SERIES_NO_01 - [6:0] */
+#define WM8995_DCS_SERIES_NO_01_SHIFT                0  /* DCS_SERIES_NO_01 - [6:0] */
+#define WM8995_DCS_SERIES_NO_01_WIDTH                7  /* DCS_SERIES_NO_01 - [6:0] */
+
+/*
+ * R85 (0x55) - DC Servo (6)
+ */
+#define WM8995_DCS_DAC_WR_VAL_3_MASK            0xFF00  /* DCS_DAC_WR_VAL_3 - [15:8] */
+#define WM8995_DCS_DAC_WR_VAL_3_SHIFT                8  /* DCS_DAC_WR_VAL_3 - [15:8] */
+#define WM8995_DCS_DAC_WR_VAL_3_WIDTH                8  /* DCS_DAC_WR_VAL_3 - [15:8] */
+#define WM8995_DCS_DAC_WR_VAL_2_MASK            0x00FF  /* DCS_DAC_WR_VAL_2 - [7:0] */
+#define WM8995_DCS_DAC_WR_VAL_2_SHIFT                0  /* DCS_DAC_WR_VAL_2 - [7:0] */
+#define WM8995_DCS_DAC_WR_VAL_2_WIDTH                8  /* DCS_DAC_WR_VAL_2 - [7:0] */
+
+/*
+ * R86 (0x56) - DC Servo (7)
+ */
+#define WM8995_DCS_DAC_WR_VAL_1_MASK            0xFF00  /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8995_DCS_DAC_WR_VAL_1_SHIFT                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8995_DCS_DAC_WR_VAL_1_WIDTH                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8995_DCS_DAC_WR_VAL_0_MASK            0x00FF  /* DCS_DAC_WR_VAL_0 - [7:0] */
+#define WM8995_DCS_DAC_WR_VAL_0_SHIFT                0  /* DCS_DAC_WR_VAL_0 - [7:0] */
+#define WM8995_DCS_DAC_WR_VAL_0_WIDTH                8  /* DCS_DAC_WR_VAL_0 - [7:0] */
+
+/*
+ * R87 (0x57) - DC Servo Readback 0
+ */
+#define WM8995_DCS_CAL_COMPLETE_MASK            0x0F00  /* DCS_CAL_COMPLETE - [11:8] */
+#define WM8995_DCS_CAL_COMPLETE_SHIFT                8  /* DCS_CAL_COMPLETE - [11:8] */
+#define WM8995_DCS_CAL_COMPLETE_WIDTH                4  /* DCS_CAL_COMPLETE - [11:8] */
+#define WM8995_DCS_DAC_WR_COMPLETE_MASK         0x00F0  /* DCS_DAC_WR_COMPLETE - [7:4] */
+#define WM8995_DCS_DAC_WR_COMPLETE_SHIFT             4  /* DCS_DAC_WR_COMPLETE - [7:4] */
+#define WM8995_DCS_DAC_WR_COMPLETE_WIDTH             4  /* DCS_DAC_WR_COMPLETE - [7:4] */
+#define WM8995_DCS_STARTUP_COMPLETE_MASK        0x000F  /* DCS_STARTUP_COMPLETE - [3:0] */
+#define WM8995_DCS_STARTUP_COMPLETE_SHIFT            0  /* DCS_STARTUP_COMPLETE - [3:0] */
+#define WM8995_DCS_STARTUP_COMPLETE_WIDTH            4  /* DCS_STARTUP_COMPLETE - [3:0] */
+
+/*
+ * R96 (0x60) - Analogue HP (1)
+ */
+#define WM8995_HPOUT1L_RMV_SHORT                0x0080  /* HPOUT1L_RMV_SHORT */
+#define WM8995_HPOUT1L_RMV_SHORT_MASK           0x0080  /* HPOUT1L_RMV_SHORT */
+#define WM8995_HPOUT1L_RMV_SHORT_SHIFT               7  /* HPOUT1L_RMV_SHORT */
+#define WM8995_HPOUT1L_RMV_SHORT_WIDTH               1  /* HPOUT1L_RMV_SHORT */
+#define WM8995_HPOUT1L_OUTP                     0x0040  /* HPOUT1L_OUTP */
+#define WM8995_HPOUT1L_OUTP_MASK                0x0040  /* HPOUT1L_OUTP */
+#define WM8995_HPOUT1L_OUTP_SHIFT                    6  /* HPOUT1L_OUTP */
+#define WM8995_HPOUT1L_OUTP_WIDTH                    1  /* HPOUT1L_OUTP */
+#define WM8995_HPOUT1L_DLY                      0x0020  /* HPOUT1L_DLY */
+#define WM8995_HPOUT1L_DLY_MASK                 0x0020  /* HPOUT1L_DLY */
+#define WM8995_HPOUT1L_DLY_SHIFT                     5  /* HPOUT1L_DLY */
+#define WM8995_HPOUT1L_DLY_WIDTH                     1  /* HPOUT1L_DLY */
+#define WM8995_HPOUT1R_RMV_SHORT                0x0008  /* HPOUT1R_RMV_SHORT */
+#define WM8995_HPOUT1R_RMV_SHORT_MASK           0x0008  /* HPOUT1R_RMV_SHORT */
+#define WM8995_HPOUT1R_RMV_SHORT_SHIFT               3  /* HPOUT1R_RMV_SHORT */
+#define WM8995_HPOUT1R_RMV_SHORT_WIDTH               1  /* HPOUT1R_RMV_SHORT */
+#define WM8995_HPOUT1R_OUTP                     0x0004  /* HPOUT1R_OUTP */
+#define WM8995_HPOUT1R_OUTP_MASK                0x0004  /* HPOUT1R_OUTP */
+#define WM8995_HPOUT1R_OUTP_SHIFT                    2  /* HPOUT1R_OUTP */
+#define WM8995_HPOUT1R_OUTP_WIDTH                    1  /* HPOUT1R_OUTP */
+#define WM8995_HPOUT1R_DLY                      0x0002  /* HPOUT1R_DLY */
+#define WM8995_HPOUT1R_DLY_MASK                 0x0002  /* HPOUT1R_DLY */
+#define WM8995_HPOUT1R_DLY_SHIFT                     1  /* HPOUT1R_DLY */
+#define WM8995_HPOUT1R_DLY_WIDTH                     1  /* HPOUT1R_DLY */
+
+/*
+ * R97 (0x61) - Analogue HP (2)
+ */
+#define WM8995_HPOUT2L_RMV_SHORT                0x0080  /* HPOUT2L_RMV_SHORT */
+#define WM8995_HPOUT2L_RMV_SHORT_MASK           0x0080  /* HPOUT2L_RMV_SHORT */
+#define WM8995_HPOUT2L_RMV_SHORT_SHIFT               7  /* HPOUT2L_RMV_SHORT */
+#define WM8995_HPOUT2L_RMV_SHORT_WIDTH               1  /* HPOUT2L_RMV_SHORT */
+#define WM8995_HPOUT2L_OUTP                     0x0040  /* HPOUT2L_OUTP */
+#define WM8995_HPOUT2L_OUTP_MASK                0x0040  /* HPOUT2L_OUTP */
+#define WM8995_HPOUT2L_OUTP_SHIFT                    6  /* HPOUT2L_OUTP */
+#define WM8995_HPOUT2L_OUTP_WIDTH                    1  /* HPOUT2L_OUTP */
+#define WM8995_HPOUT2L_DLY                      0x0020  /* HPOUT2L_DLY */
+#define WM8995_HPOUT2L_DLY_MASK                 0x0020  /* HPOUT2L_DLY */
+#define WM8995_HPOUT2L_DLY_SHIFT                     5  /* HPOUT2L_DLY */
+#define WM8995_HPOUT2L_DLY_WIDTH                     1  /* HPOUT2L_DLY */
+#define WM8995_HPOUT2R_RMV_SHORT                0x0008  /* HPOUT2R_RMV_SHORT */
+#define WM8995_HPOUT2R_RMV_SHORT_MASK           0x0008  /* HPOUT2R_RMV_SHORT */
+#define WM8995_HPOUT2R_RMV_SHORT_SHIFT               3  /* HPOUT2R_RMV_SHORT */
+#define WM8995_HPOUT2R_RMV_SHORT_WIDTH               1  /* HPOUT2R_RMV_SHORT */
+#define WM8995_HPOUT2R_OUTP                     0x0004  /* HPOUT2R_OUTP */
+#define WM8995_HPOUT2R_OUTP_MASK                0x0004  /* HPOUT2R_OUTP */
+#define WM8995_HPOUT2R_OUTP_SHIFT                    2  /* HPOUT2R_OUTP */
+#define WM8995_HPOUT2R_OUTP_WIDTH                    1  /* HPOUT2R_OUTP */
+#define WM8995_HPOUT2R_DLY                      0x0002  /* HPOUT2R_DLY */
+#define WM8995_HPOUT2R_DLY_MASK                 0x0002  /* HPOUT2R_DLY */
+#define WM8995_HPOUT2R_DLY_SHIFT                     1  /* HPOUT2R_DLY */
+#define WM8995_HPOUT2R_DLY_WIDTH                     1  /* HPOUT2R_DLY */
+
+/*
+ * R256 (0x100) - Chip Revision
+ */
+#define WM8995_CHIP_REV_MASK                    0x000F  /* CHIP_REV - [3:0] */
+#define WM8995_CHIP_REV_SHIFT                        0  /* CHIP_REV - [3:0] */
+#define WM8995_CHIP_REV_WIDTH                        4  /* CHIP_REV - [3:0] */
+
+/*
+ * R257 (0x101) - Control Interface (1)
+ */
+#define WM8995_REG_SYNC                         0x8000  /* REG_SYNC */
+#define WM8995_REG_SYNC_MASK                    0x8000  /* REG_SYNC */
+#define WM8995_REG_SYNC_SHIFT                       15  /* REG_SYNC */
+#define WM8995_REG_SYNC_WIDTH                        1  /* REG_SYNC */
+#define WM8995_SPI_CONTRD                       0x0040  /* SPI_CONTRD */
+#define WM8995_SPI_CONTRD_MASK                  0x0040  /* SPI_CONTRD */
+#define WM8995_SPI_CONTRD_SHIFT                      6  /* SPI_CONTRD */
+#define WM8995_SPI_CONTRD_WIDTH                      1  /* SPI_CONTRD */
+#define WM8995_SPI_4WIRE                        0x0020  /* SPI_4WIRE */
+#define WM8995_SPI_4WIRE_MASK                   0x0020  /* SPI_4WIRE */
+#define WM8995_SPI_4WIRE_SHIFT                       5  /* SPI_4WIRE */
+#define WM8995_SPI_4WIRE_WIDTH                       1  /* SPI_4WIRE */
+#define WM8995_SPI_CFG                          0x0010  /* SPI_CFG */
+#define WM8995_SPI_CFG_MASK                     0x0010  /* SPI_CFG */
+#define WM8995_SPI_CFG_SHIFT                         4  /* SPI_CFG */
+#define WM8995_SPI_CFG_WIDTH                         1  /* SPI_CFG */
+#define WM8995_AUTO_INC                         0x0004  /* AUTO_INC */
+#define WM8995_AUTO_INC_MASK                    0x0004  /* AUTO_INC */
+#define WM8995_AUTO_INC_SHIFT                        2  /* AUTO_INC */
+#define WM8995_AUTO_INC_WIDTH                        1  /* AUTO_INC */
+
+/*
+ * R258 (0x102) - Control Interface (2)
+ */
+#define WM8995_CTRL_IF_SRC                      0x0001  /* CTRL_IF_SRC */
+#define WM8995_CTRL_IF_SRC_MASK                 0x0001  /* CTRL_IF_SRC */
+#define WM8995_CTRL_IF_SRC_SHIFT                     0  /* CTRL_IF_SRC */
+#define WM8995_CTRL_IF_SRC_WIDTH                     1  /* CTRL_IF_SRC */
+
+/*
+ * R272 (0x110) - Write Sequencer Ctrl (1)
+ */
+#define WM8995_WSEQ_ENA                         0x8000  /* WSEQ_ENA */
+#define WM8995_WSEQ_ENA_MASK                    0x8000  /* WSEQ_ENA */
+#define WM8995_WSEQ_ENA_SHIFT                       15  /* WSEQ_ENA */
+#define WM8995_WSEQ_ENA_WIDTH                        1  /* WSEQ_ENA */
+#define WM8995_WSEQ_ABORT                       0x0200  /* WSEQ_ABORT */
+#define WM8995_WSEQ_ABORT_MASK                  0x0200  /* WSEQ_ABORT */
+#define WM8995_WSEQ_ABORT_SHIFT                      9  /* WSEQ_ABORT */
+#define WM8995_WSEQ_ABORT_WIDTH                      1  /* WSEQ_ABORT */
+#define WM8995_WSEQ_START                       0x0100  /* WSEQ_START */
+#define WM8995_WSEQ_START_MASK                  0x0100  /* WSEQ_START */
+#define WM8995_WSEQ_START_SHIFT                      8  /* WSEQ_START */
+#define WM8995_WSEQ_START_WIDTH                      1  /* WSEQ_START */
+#define WM8995_WSEQ_START_INDEX_MASK            0x007F  /* WSEQ_START_INDEX - [6:0] */
+#define WM8995_WSEQ_START_INDEX_SHIFT                0  /* WSEQ_START_INDEX - [6:0] */
+#define WM8995_WSEQ_START_INDEX_WIDTH                7  /* WSEQ_START_INDEX - [6:0] */
+
+/*
+ * R273 (0x111) - Write Sequencer Ctrl (2)
+ */
+#define WM8995_WSEQ_BUSY                        0x0100  /* WSEQ_BUSY */
+#define WM8995_WSEQ_BUSY_MASK                   0x0100  /* WSEQ_BUSY */
+#define WM8995_WSEQ_BUSY_SHIFT                       8  /* WSEQ_BUSY */
+#define WM8995_WSEQ_BUSY_WIDTH                       1  /* WSEQ_BUSY */
+#define WM8995_WSEQ_CURRENT_INDEX_MASK          0x007F  /* WSEQ_CURRENT_INDEX - [6:0] */
+#define WM8995_WSEQ_CURRENT_INDEX_SHIFT              0  /* WSEQ_CURRENT_INDEX - [6:0] */
+#define WM8995_WSEQ_CURRENT_INDEX_WIDTH              7  /* WSEQ_CURRENT_INDEX - [6:0] */
+
+/*
+ * R512 (0x200) - AIF1 Clocking (1)
+ */
+#define WM8995_AIF1CLK_SRC_MASK                 0x0018  /* AIF1CLK_SRC - [4:3] */
+#define WM8995_AIF1CLK_SRC_SHIFT                     3  /* AIF1CLK_SRC - [4:3] */
+#define WM8995_AIF1CLK_SRC_WIDTH                     2  /* AIF1CLK_SRC - [4:3] */
+#define WM8995_AIF1CLK_INV                      0x0004  /* AIF1CLK_INV */
+#define WM8995_AIF1CLK_INV_MASK                 0x0004  /* AIF1CLK_INV */
+#define WM8995_AIF1CLK_INV_SHIFT                     2  /* AIF1CLK_INV */
+#define WM8995_AIF1CLK_INV_WIDTH                     1  /* AIF1CLK_INV */
+#define WM8995_AIF1CLK_DIV                      0x0002  /* AIF1CLK_DIV */
+#define WM8995_AIF1CLK_DIV_MASK                 0x0002  /* AIF1CLK_DIV */
+#define WM8995_AIF1CLK_DIV_SHIFT                     1  /* AIF1CLK_DIV */
+#define WM8995_AIF1CLK_DIV_WIDTH                     1  /* AIF1CLK_DIV */
+#define WM8995_AIF1CLK_ENA                      0x0001  /* AIF1CLK_ENA */
+#define WM8995_AIF1CLK_ENA_MASK                 0x0001  /* AIF1CLK_ENA */
+#define WM8995_AIF1CLK_ENA_SHIFT                     0  /* AIF1CLK_ENA */
+#define WM8995_AIF1CLK_ENA_WIDTH                     1  /* AIF1CLK_ENA */
+
+/*
+ * R513 (0x201) - AIF1 Clocking (2)
+ */
+#define WM8995_AIF1DAC_DIV_MASK                 0x0038  /* AIF1DAC_DIV - [5:3] */
+#define WM8995_AIF1DAC_DIV_SHIFT                     3  /* AIF1DAC_DIV - [5:3] */
+#define WM8995_AIF1DAC_DIV_WIDTH                     3  /* AIF1DAC_DIV - [5:3] */
+#define WM8995_AIF1ADC_DIV_MASK                 0x0007  /* AIF1ADC_DIV - [2:0] */
+#define WM8995_AIF1ADC_DIV_SHIFT                     0  /* AIF1ADC_DIV - [2:0] */
+#define WM8995_AIF1ADC_DIV_WIDTH                     3  /* AIF1ADC_DIV - [2:0] */
+
+/*
+ * R516 (0x204) - AIF2 Clocking (1)
+ */
+#define WM8995_AIF2CLK_SRC_MASK                 0x0018  /* AIF2CLK_SRC - [4:3] */
+#define WM8995_AIF2CLK_SRC_SHIFT                     3  /* AIF2CLK_SRC - [4:3] */
+#define WM8995_AIF2CLK_SRC_WIDTH                     2  /* AIF2CLK_SRC - [4:3] */
+#define WM8995_AIF2CLK_INV                      0x0004  /* AIF2CLK_INV */
+#define WM8995_AIF2CLK_INV_MASK                 0x0004  /* AIF2CLK_INV */
+#define WM8995_AIF2CLK_INV_SHIFT                     2  /* AIF2CLK_INV */
+#define WM8995_AIF2CLK_INV_WIDTH                     1  /* AIF2CLK_INV */
+#define WM8995_AIF2CLK_DIV                      0x0002  /* AIF2CLK_DIV */
+#define WM8995_AIF2CLK_DIV_MASK                 0x0002  /* AIF2CLK_DIV */
+#define WM8995_AIF2CLK_DIV_SHIFT                     1  /* AIF2CLK_DIV */
+#define WM8995_AIF2CLK_DIV_WIDTH                     1  /* AIF2CLK_DIV */
+#define WM8995_AIF2CLK_ENA                      0x0001  /* AIF2CLK_ENA */
+#define WM8995_AIF2CLK_ENA_MASK                 0x0001  /* AIF2CLK_ENA */
+#define WM8995_AIF2CLK_ENA_SHIFT                     0  /* AIF2CLK_ENA */
+#define WM8995_AIF2CLK_ENA_WIDTH                     1  /* AIF2CLK_ENA */
+
+/*
+ * R517 (0x205) - AIF2 Clocking (2)
+ */
+#define WM8995_AIF2DAC_DIV_MASK                 0x0038  /* AIF2DAC_DIV - [5:3] */
+#define WM8995_AIF2DAC_DIV_SHIFT                     3  /* AIF2DAC_DIV - [5:3] */
+#define WM8995_AIF2DAC_DIV_WIDTH                     3  /* AIF2DAC_DIV - [5:3] */
+#define WM8995_AIF2ADC_DIV_MASK                 0x0007  /* AIF2ADC_DIV - [2:0] */
+#define WM8995_AIF2ADC_DIV_SHIFT                     0  /* AIF2ADC_DIV - [2:0] */
+#define WM8995_AIF2ADC_DIV_WIDTH                     3  /* AIF2ADC_DIV - [2:0] */
+
+/*
+ * R520 (0x208) - Clocking (1)
+ */
+#define WM8995_LFCLK_ENA                        0x0020  /* LFCLK_ENA */
+#define WM8995_LFCLK_ENA_MASK                   0x0020  /* LFCLK_ENA */
+#define WM8995_LFCLK_ENA_SHIFT                       5  /* LFCLK_ENA */
+#define WM8995_LFCLK_ENA_WIDTH                       1  /* LFCLK_ENA */
+#define WM8995_TOCLK_ENA                        0x0010  /* TOCLK_ENA */
+#define WM8995_TOCLK_ENA_MASK                   0x0010  /* TOCLK_ENA */
+#define WM8995_TOCLK_ENA_SHIFT                       4  /* TOCLK_ENA */
+#define WM8995_TOCLK_ENA_WIDTH                       1  /* TOCLK_ENA */
+#define WM8995_AIF1DSPCLK_ENA                   0x0008  /* AIF1DSPCLK_ENA */
+#define WM8995_AIF1DSPCLK_ENA_MASK              0x0008  /* AIF1DSPCLK_ENA */
+#define WM8995_AIF1DSPCLK_ENA_SHIFT                  3  /* AIF1DSPCLK_ENA */
+#define WM8995_AIF1DSPCLK_ENA_WIDTH                  1  /* AIF1DSPCLK_ENA */
+#define WM8995_AIF2DSPCLK_ENA                   0x0004  /* AIF2DSPCLK_ENA */
+#define WM8995_AIF2DSPCLK_ENA_MASK              0x0004  /* AIF2DSPCLK_ENA */
+#define WM8995_AIF2DSPCLK_ENA_SHIFT                  2  /* AIF2DSPCLK_ENA */
+#define WM8995_AIF2DSPCLK_ENA_WIDTH                  1  /* AIF2DSPCLK_ENA */
+#define WM8995_SYSDSPCLK_ENA                    0x0002  /* SYSDSPCLK_ENA */
+#define WM8995_SYSDSPCLK_ENA_MASK               0x0002  /* SYSDSPCLK_ENA */
+#define WM8995_SYSDSPCLK_ENA_SHIFT                   1  /* SYSDSPCLK_ENA */
+#define WM8995_SYSDSPCLK_ENA_WIDTH                   1  /* SYSDSPCLK_ENA */
+#define WM8995_SYSCLK_SRC                       0x0001  /* SYSCLK_SRC */
+#define WM8995_SYSCLK_SRC_MASK                  0x0001  /* SYSCLK_SRC */
+#define WM8995_SYSCLK_SRC_SHIFT                      0  /* SYSCLK_SRC */
+#define WM8995_SYSCLK_SRC_WIDTH                      1  /* SYSCLK_SRC */
+
+/*
+ * R521 (0x209) - Clocking (2)
+ */
+#define WM8995_TOCLK_DIV_MASK                   0x0700  /* TOCLK_DIV - [10:8] */
+#define WM8995_TOCLK_DIV_SHIFT                       8  /* TOCLK_DIV - [10:8] */
+#define WM8995_TOCLK_DIV_WIDTH                       3  /* TOCLK_DIV - [10:8] */
+#define WM8995_DBCLK_DIV_MASK                   0x00F0  /* DBCLK_DIV - [7:4] */
+#define WM8995_DBCLK_DIV_SHIFT                       4  /* DBCLK_DIV - [7:4] */
+#define WM8995_DBCLK_DIV_WIDTH                       4  /* DBCLK_DIV - [7:4] */
+#define WM8995_OPCLK_DIV_MASK                   0x0007  /* OPCLK_DIV - [2:0] */
+#define WM8995_OPCLK_DIV_SHIFT                       0  /* OPCLK_DIV - [2:0] */
+#define WM8995_OPCLK_DIV_WIDTH                       3  /* OPCLK_DIV - [2:0] */
+
+/*
+ * R528 (0x210) - AIF1 Rate
+ */
+#define WM8995_AIF1_SR_MASK                     0x00F0  /* AIF1_SR - [7:4] */
+#define WM8995_AIF1_SR_SHIFT                         4  /* AIF1_SR - [7:4] */
+#define WM8995_AIF1_SR_WIDTH                         4  /* AIF1_SR - [7:4] */
+#define WM8995_AIF1CLK_RATE_MASK                0x000F  /* AIF1CLK_RATE - [3:0] */
+#define WM8995_AIF1CLK_RATE_SHIFT                    0  /* AIF1CLK_RATE - [3:0] */
+#define WM8995_AIF1CLK_RATE_WIDTH                    4  /* AIF1CLK_RATE - [3:0] */
+
+/*
+ * R529 (0x211) - AIF2 Rate
+ */
+#define WM8995_AIF2_SR_MASK                     0x00F0  /* AIF2_SR - [7:4] */
+#define WM8995_AIF2_SR_SHIFT                         4  /* AIF2_SR - [7:4] */
+#define WM8995_AIF2_SR_WIDTH                         4  /* AIF2_SR - [7:4] */
+#define WM8995_AIF2CLK_RATE_MASK                0x000F  /* AIF2CLK_RATE - [3:0] */
+#define WM8995_AIF2CLK_RATE_SHIFT                    0  /* AIF2CLK_RATE - [3:0] */
+#define WM8995_AIF2CLK_RATE_WIDTH                    4  /* AIF2CLK_RATE - [3:0] */
+
+/*
+ * R530 (0x212) - Rate Status
+ */
+#define WM8995_SR_ERROR_MASK                    0x000F  /* SR_ERROR - [3:0] */
+#define WM8995_SR_ERROR_SHIFT                        0  /* SR_ERROR - [3:0] */
+#define WM8995_SR_ERROR_WIDTH                        4  /* SR_ERROR - [3:0] */
+
+/*
+ * R544 (0x220) - FLL1 Control (1)
+ */
+#define WM8995_FLL1_OSC_ENA                     0x0002  /* FLL1_OSC_ENA */
+#define WM8995_FLL1_OSC_ENA_MASK                0x0002  /* FLL1_OSC_ENA */
+#define WM8995_FLL1_OSC_ENA_SHIFT                    1  /* FLL1_OSC_ENA */
+#define WM8995_FLL1_OSC_ENA_WIDTH                    1  /* FLL1_OSC_ENA */
+#define WM8995_FLL1_ENA                         0x0001  /* FLL1_ENA */
+#define WM8995_FLL1_ENA_MASK                    0x0001  /* FLL1_ENA */
+#define WM8995_FLL1_ENA_SHIFT                        0  /* FLL1_ENA */
+#define WM8995_FLL1_ENA_WIDTH                        1  /* FLL1_ENA */
+
+/*
+ * R545 (0x221) - FLL1 Control (2)
+ */
+#define WM8995_FLL1_OUTDIV_MASK                 0x3F00  /* FLL1_OUTDIV - [13:8] */
+#define WM8995_FLL1_OUTDIV_SHIFT                     8  /* FLL1_OUTDIV - [13:8] */
+#define WM8995_FLL1_OUTDIV_WIDTH                     6  /* FLL1_OUTDIV - [13:8] */
+#define WM8995_FLL1_CTRL_RATE_MASK              0x0070  /* FLL1_CTRL_RATE - [6:4] */
+#define WM8995_FLL1_CTRL_RATE_SHIFT                  4  /* FLL1_CTRL_RATE - [6:4] */
+#define WM8995_FLL1_CTRL_RATE_WIDTH                  3  /* FLL1_CTRL_RATE - [6:4] */
+#define WM8995_FLL1_FRATIO_MASK                 0x0007  /* FLL1_FRATIO - [2:0] */
+#define WM8995_FLL1_FRATIO_SHIFT                     0  /* FLL1_FRATIO - [2:0] */
+#define WM8995_FLL1_FRATIO_WIDTH                     3  /* FLL1_FRATIO - [2:0] */
+
+/*
+ * R546 (0x222) - FLL1 Control (3)
+ */
+#define WM8995_FLL1_K_MASK                      0xFFFF  /* FLL1_K - [15:0] */
+#define WM8995_FLL1_K_SHIFT                          0  /* FLL1_K - [15:0] */
+#define WM8995_FLL1_K_WIDTH                         16  /* FLL1_K - [15:0] */
+
+/*
+ * R547 (0x223) - FLL1 Control (4)
+ */
+#define WM8995_FLL1_N_MASK                      0x7FE0  /* FLL1_N - [14:5] */
+#define WM8995_FLL1_N_SHIFT                          5  /* FLL1_N - [14:5] */
+#define WM8995_FLL1_N_WIDTH                         10  /* FLL1_N - [14:5] */
+#define WM8995_FLL1_LOOP_GAIN_MASK              0x000F  /* FLL1_LOOP_GAIN - [3:0] */
+#define WM8995_FLL1_LOOP_GAIN_SHIFT                  0  /* FLL1_LOOP_GAIN - [3:0] */
+#define WM8995_FLL1_LOOP_GAIN_WIDTH                  4  /* FLL1_LOOP_GAIN - [3:0] */
+
+/*
+ * R548 (0x224) - FLL1 Control (5)
+ */
+#define WM8995_FLL1_FRC_NCO_VAL_MASK            0x1F80  /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8995_FLL1_FRC_NCO_VAL_SHIFT                7  /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8995_FLL1_FRC_NCO_VAL_WIDTH                6  /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8995_FLL1_FRC_NCO                     0x0040  /* FLL1_FRC_NCO */
+#define WM8995_FLL1_FRC_NCO_MASK                0x0040  /* FLL1_FRC_NCO */
+#define WM8995_FLL1_FRC_NCO_SHIFT                    6  /* FLL1_FRC_NCO */
+#define WM8995_FLL1_FRC_NCO_WIDTH                    1  /* FLL1_FRC_NCO */
+#define WM8995_FLL1_REFCLK_DIV_MASK             0x0018  /* FLL1_REFCLK_DIV - [4:3] */
+#define WM8995_FLL1_REFCLK_DIV_SHIFT                 3  /* FLL1_REFCLK_DIV - [4:3] */
+#define WM8995_FLL1_REFCLK_DIV_WIDTH                 2  /* FLL1_REFCLK_DIV - [4:3] */
+#define WM8995_FLL1_REFCLK_SRC_MASK             0x0003  /* FLL1_REFCLK_SRC - [1:0] */
+#define WM8995_FLL1_REFCLK_SRC_SHIFT                 0  /* FLL1_REFCLK_SRC - [1:0] */
+#define WM8995_FLL1_REFCLK_SRC_WIDTH                 2  /* FLL1_REFCLK_SRC - [1:0] */
+
+/*
+ * R576 (0x240) - FLL2 Control (1)
+ */
+#define WM8995_FLL2_OSC_ENA                     0x0002  /* FLL2_OSC_ENA */
+#define WM8995_FLL2_OSC_ENA_MASK                0x0002  /* FLL2_OSC_ENA */
+#define WM8995_FLL2_OSC_ENA_SHIFT                    1  /* FLL2_OSC_ENA */
+#define WM8995_FLL2_OSC_ENA_WIDTH                    1  /* FLL2_OSC_ENA */
+#define WM8995_FLL2_ENA                         0x0001  /* FLL2_ENA */
+#define WM8995_FLL2_ENA_MASK                    0x0001  /* FLL2_ENA */
+#define WM8995_FLL2_ENA_SHIFT                        0  /* FLL2_ENA */
+#define WM8995_FLL2_ENA_WIDTH                        1  /* FLL2_ENA */
+
+/*
+ * R577 (0x241) - FLL2 Control (2)
+ */
+#define WM8995_FLL2_OUTDIV_MASK                 0x3F00  /* FLL2_OUTDIV - [13:8] */
+#define WM8995_FLL2_OUTDIV_SHIFT                     8  /* FLL2_OUTDIV - [13:8] */
+#define WM8995_FLL2_OUTDIV_WIDTH                     6  /* FLL2_OUTDIV - [13:8] */
+#define WM8995_FLL2_CTRL_RATE_MASK              0x0070  /* FLL2_CTRL_RATE - [6:4] */
+#define WM8995_FLL2_CTRL_RATE_SHIFT                  4  /* FLL2_CTRL_RATE - [6:4] */
+#define WM8995_FLL2_CTRL_RATE_WIDTH                  3  /* FLL2_CTRL_RATE - [6:4] */
+#define WM8995_FLL2_FRATIO_MASK                 0x0007  /* FLL2_FRATIO - [2:0] */
+#define WM8995_FLL2_FRATIO_SHIFT                     0  /* FLL2_FRATIO - [2:0] */
+#define WM8995_FLL2_FRATIO_WIDTH                     3  /* FLL2_FRATIO - [2:0] */
+
+/*
+ * R578 (0x242) - FLL2 Control (3)
+ */
+#define WM8995_FLL2_K_MASK                      0xFFFF  /* FLL2_K - [15:0] */
+#define WM8995_FLL2_K_SHIFT                          0  /* FLL2_K - [15:0] */
+#define WM8995_FLL2_K_WIDTH                         16  /* FLL2_K - [15:0] */
+
+/*
+ * R579 (0x243) - FLL2 Control (4)
+ */
+#define WM8995_FLL2_N_MASK                      0x7FE0  /* FLL2_N - [14:5] */
+#define WM8995_FLL2_N_SHIFT                          5  /* FLL2_N - [14:5] */
+#define WM8995_FLL2_N_WIDTH                         10  /* FLL2_N - [14:5] */
+#define WM8995_FLL2_LOOP_GAIN_MASK              0x000F  /* FLL2_LOOP_GAIN - [3:0] */
+#define WM8995_FLL2_LOOP_GAIN_SHIFT                  0  /* FLL2_LOOP_GAIN - [3:0] */
+#define WM8995_FLL2_LOOP_GAIN_WIDTH                  4  /* FLL2_LOOP_GAIN - [3:0] */
+
+/*
+ * R580 (0x244) - FLL2 Control (5)
+ */
+#define WM8995_FLL2_FRC_NCO_VAL_MASK            0x1F80  /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8995_FLL2_FRC_NCO_VAL_SHIFT                7  /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8995_FLL2_FRC_NCO_VAL_WIDTH                6  /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8995_FLL2_FRC_NCO                     0x0040  /* FLL2_FRC_NCO */
+#define WM8995_FLL2_FRC_NCO_MASK                0x0040  /* FLL2_FRC_NCO */
+#define WM8995_FLL2_FRC_NCO_SHIFT                    6  /* FLL2_FRC_NCO */
+#define WM8995_FLL2_FRC_NCO_WIDTH                    1  /* FLL2_FRC_NCO */
+#define WM8995_FLL2_REFCLK_DIV_MASK             0x0018  /* FLL2_REFCLK_DIV - [4:3] */
+#define WM8995_FLL2_REFCLK_DIV_SHIFT                 3  /* FLL2_REFCLK_DIV - [4:3] */
+#define WM8995_FLL2_REFCLK_DIV_WIDTH                 2  /* FLL2_REFCLK_DIV - [4:3] */
+#define WM8995_FLL2_REFCLK_SRC_MASK             0x0003  /* FLL2_REFCLK_SRC - [1:0] */
+#define WM8995_FLL2_REFCLK_SRC_SHIFT                 0  /* FLL2_REFCLK_SRC - [1:0] */
+#define WM8995_FLL2_REFCLK_SRC_WIDTH                 2  /* FLL2_REFCLK_SRC - [1:0] */
+
+/*
+ * R768 (0x300) - AIF1 Control (1)
+ */
+#define WM8995_AIF1ADCL_SRC                     0x8000  /* AIF1ADCL_SRC */
+#define WM8995_AIF1ADCL_SRC_MASK                0x8000  /* AIF1ADCL_SRC */
+#define WM8995_AIF1ADCL_SRC_SHIFT                   15  /* AIF1ADCL_SRC */
+#define WM8995_AIF1ADCL_SRC_WIDTH                    1  /* AIF1ADCL_SRC */
+#define WM8995_AIF1ADCR_SRC                     0x4000  /* AIF1ADCR_SRC */
+#define WM8995_AIF1ADCR_SRC_MASK                0x4000  /* AIF1ADCR_SRC */
+#define WM8995_AIF1ADCR_SRC_SHIFT                   14  /* AIF1ADCR_SRC */
+#define WM8995_AIF1ADCR_SRC_WIDTH                    1  /* AIF1ADCR_SRC */
+#define WM8995_AIF1ADC_TDM                      0x2000  /* AIF1ADC_TDM */
+#define WM8995_AIF1ADC_TDM_MASK                 0x2000  /* AIF1ADC_TDM */
+#define WM8995_AIF1ADC_TDM_SHIFT                    13  /* AIF1ADC_TDM */
+#define WM8995_AIF1ADC_TDM_WIDTH                     1  /* AIF1ADC_TDM */
+#define WM8995_AIF1_BCLK_INV                    0x0100  /* AIF1_BCLK_INV */
+#define WM8995_AIF1_BCLK_INV_MASK               0x0100  /* AIF1_BCLK_INV */
+#define WM8995_AIF1_BCLK_INV_SHIFT                   8  /* AIF1_BCLK_INV */
+#define WM8995_AIF1_BCLK_INV_WIDTH                   1  /* AIF1_BCLK_INV */
+#define WM8995_AIF1_LRCLK_INV                   0x0080  /* AIF1_LRCLK_INV */
+#define WM8995_AIF1_LRCLK_INV_MASK              0x0080  /* AIF1_LRCLK_INV */
+#define WM8995_AIF1_LRCLK_INV_SHIFT                  7  /* AIF1_LRCLK_INV */
+#define WM8995_AIF1_LRCLK_INV_WIDTH                  1  /* AIF1_LRCLK_INV */
+#define WM8995_AIF1_WL_MASK                     0x0060  /* AIF1_WL - [6:5] */
+#define WM8995_AIF1_WL_SHIFT                         5  /* AIF1_WL - [6:5] */
+#define WM8995_AIF1_WL_WIDTH                         2  /* AIF1_WL - [6:5] */
+#define WM8995_AIF1_FMT_MASK                    0x0018  /* AIF1_FMT - [4:3] */
+#define WM8995_AIF1_FMT_SHIFT                        3  /* AIF1_FMT - [4:3] */
+#define WM8995_AIF1_FMT_WIDTH                        2  /* AIF1_FMT - [4:3] */
+
+/*
+ * R769 (0x301) - AIF1 Control (2)
+ */
+#define WM8995_AIF1DACL_SRC                     0x8000  /* AIF1DACL_SRC */
+#define WM8995_AIF1DACL_SRC_MASK                0x8000  /* AIF1DACL_SRC */
+#define WM8995_AIF1DACL_SRC_SHIFT                   15  /* AIF1DACL_SRC */
+#define WM8995_AIF1DACL_SRC_WIDTH                    1  /* AIF1DACL_SRC */
+#define WM8995_AIF1DACR_SRC                     0x4000  /* AIF1DACR_SRC */
+#define WM8995_AIF1DACR_SRC_MASK                0x4000  /* AIF1DACR_SRC */
+#define WM8995_AIF1DACR_SRC_SHIFT                   14  /* AIF1DACR_SRC */
+#define WM8995_AIF1DACR_SRC_WIDTH                    1  /* AIF1DACR_SRC */
+#define WM8995_AIF1DAC_BOOST_MASK               0x0C00  /* AIF1DAC_BOOST - [11:10] */
+#define WM8995_AIF1DAC_BOOST_SHIFT                  10  /* AIF1DAC_BOOST - [11:10] */
+#define WM8995_AIF1DAC_BOOST_WIDTH                   2  /* AIF1DAC_BOOST - [11:10] */
+#define WM8995_AIF1DAC_COMP                     0x0010  /* AIF1DAC_COMP */
+#define WM8995_AIF1DAC_COMP_MASK                0x0010  /* AIF1DAC_COMP */
+#define WM8995_AIF1DAC_COMP_SHIFT                    4  /* AIF1DAC_COMP */
+#define WM8995_AIF1DAC_COMP_WIDTH                    1  /* AIF1DAC_COMP */
+#define WM8995_AIF1DAC_COMPMODE                 0x0008  /* AIF1DAC_COMPMODE */
+#define WM8995_AIF1DAC_COMPMODE_MASK            0x0008  /* AIF1DAC_COMPMODE */
+#define WM8995_AIF1DAC_COMPMODE_SHIFT                3  /* AIF1DAC_COMPMODE */
+#define WM8995_AIF1DAC_COMPMODE_WIDTH                1  /* AIF1DAC_COMPMODE */
+#define WM8995_AIF1ADC_COMP                     0x0004  /* AIF1ADC_COMP */
+#define WM8995_AIF1ADC_COMP_MASK                0x0004  /* AIF1ADC_COMP */
+#define WM8995_AIF1ADC_COMP_SHIFT                    2  /* AIF1ADC_COMP */
+#define WM8995_AIF1ADC_COMP_WIDTH                    1  /* AIF1ADC_COMP */
+#define WM8995_AIF1ADC_COMPMODE                 0x0002  /* AIF1ADC_COMPMODE */
+#define WM8995_AIF1ADC_COMPMODE_MASK            0x0002  /* AIF1ADC_COMPMODE */
+#define WM8995_AIF1ADC_COMPMODE_SHIFT                1  /* AIF1ADC_COMPMODE */
+#define WM8995_AIF1ADC_COMPMODE_WIDTH                1  /* AIF1ADC_COMPMODE */
+#define WM8995_AIF1_LOOPBACK                    0x0001  /* AIF1_LOOPBACK */
+#define WM8995_AIF1_LOOPBACK_MASK               0x0001  /* AIF1_LOOPBACK */
+#define WM8995_AIF1_LOOPBACK_SHIFT                   0  /* AIF1_LOOPBACK */
+#define WM8995_AIF1_LOOPBACK_WIDTH                   1  /* AIF1_LOOPBACK */
+
+/*
+ * R770 (0x302) - AIF1 Master/Slave
+ */
+#define WM8995_AIF1_TRI                         0x8000  /* AIF1_TRI */
+#define WM8995_AIF1_TRI_MASK                    0x8000  /* AIF1_TRI */
+#define WM8995_AIF1_TRI_SHIFT                       15  /* AIF1_TRI */
+#define WM8995_AIF1_TRI_WIDTH                        1  /* AIF1_TRI */
+#define WM8995_AIF1_MSTR                        0x4000  /* AIF1_MSTR */
+#define WM8995_AIF1_MSTR_MASK                   0x4000  /* AIF1_MSTR */
+#define WM8995_AIF1_MSTR_SHIFT                      14  /* AIF1_MSTR */
+#define WM8995_AIF1_MSTR_WIDTH                       1  /* AIF1_MSTR */
+#define WM8995_AIF1_CLK_FRC                     0x2000  /* AIF1_CLK_FRC */
+#define WM8995_AIF1_CLK_FRC_MASK                0x2000  /* AIF1_CLK_FRC */
+#define WM8995_AIF1_CLK_FRC_SHIFT                   13  /* AIF1_CLK_FRC */
+#define WM8995_AIF1_CLK_FRC_WIDTH                    1  /* AIF1_CLK_FRC */
+#define WM8995_AIF1_LRCLK_FRC                   0x1000  /* AIF1_LRCLK_FRC */
+#define WM8995_AIF1_LRCLK_FRC_MASK              0x1000  /* AIF1_LRCLK_FRC */
+#define WM8995_AIF1_LRCLK_FRC_SHIFT                 12  /* AIF1_LRCLK_FRC */
+#define WM8995_AIF1_LRCLK_FRC_WIDTH                  1  /* AIF1_LRCLK_FRC */
+
+/*
+ * R771 (0x303) - AIF1 BCLK
+ */
+#define WM8995_AIF1_BCLK_DIV_MASK               0x00F0  /* AIF1_BCLK_DIV - [7:4] */
+#define WM8995_AIF1_BCLK_DIV_SHIFT                   4  /* AIF1_BCLK_DIV - [7:4] */
+#define WM8995_AIF1_BCLK_DIV_WIDTH                   4  /* AIF1_BCLK_DIV - [7:4] */
+
+/*
+ * R772 (0x304) - AIF1ADC LRCLK
+ */
+#define WM8995_AIF1ADC_LRCLK_DIR                0x0800  /* AIF1ADC_LRCLK_DIR */
+#define WM8995_AIF1ADC_LRCLK_DIR_MASK           0x0800  /* AIF1ADC_LRCLK_DIR */
+#define WM8995_AIF1ADC_LRCLK_DIR_SHIFT              11  /* AIF1ADC_LRCLK_DIR */
+#define WM8995_AIF1ADC_LRCLK_DIR_WIDTH               1  /* AIF1ADC_LRCLK_DIR */
+#define WM8995_AIF1ADC_RATE_MASK                0x07FF  /* AIF1ADC_RATE - [10:0] */
+#define WM8995_AIF1ADC_RATE_SHIFT                    0  /* AIF1ADC_RATE - [10:0] */
+#define WM8995_AIF1ADC_RATE_WIDTH                   11  /* AIF1ADC_RATE - [10:0] */
+
+/*
+ * R773 (0x305) - AIF1DAC LRCLK
+ */
+#define WM8995_AIF1DAC_LRCLK_DIR                0x0800  /* AIF1DAC_LRCLK_DIR */
+#define WM8995_AIF1DAC_LRCLK_DIR_MASK           0x0800  /* AIF1DAC_LRCLK_DIR */
+#define WM8995_AIF1DAC_LRCLK_DIR_SHIFT              11  /* AIF1DAC_LRCLK_DIR */
+#define WM8995_AIF1DAC_LRCLK_DIR_WIDTH               1  /* AIF1DAC_LRCLK_DIR */
+#define WM8995_AIF1DAC_RATE_MASK                0x07FF  /* AIF1DAC_RATE - [10:0] */
+#define WM8995_AIF1DAC_RATE_SHIFT                    0  /* AIF1DAC_RATE - [10:0] */
+#define WM8995_AIF1DAC_RATE_WIDTH                   11  /* AIF1DAC_RATE - [10:0] */
+
+/*
+ * R774 (0x306) - AIF1DAC Data
+ */
+#define WM8995_AIF1DACL_DAT_INV                 0x0002  /* AIF1DACL_DAT_INV */
+#define WM8995_AIF1DACL_DAT_INV_MASK            0x0002  /* AIF1DACL_DAT_INV */
+#define WM8995_AIF1DACL_DAT_INV_SHIFT                1  /* AIF1DACL_DAT_INV */
+#define WM8995_AIF1DACL_DAT_INV_WIDTH                1  /* AIF1DACL_DAT_INV */
+#define WM8995_AIF1DACR_DAT_INV                 0x0001  /* AIF1DACR_DAT_INV */
+#define WM8995_AIF1DACR_DAT_INV_MASK            0x0001  /* AIF1DACR_DAT_INV */
+#define WM8995_AIF1DACR_DAT_INV_SHIFT                0  /* AIF1DACR_DAT_INV */
+#define WM8995_AIF1DACR_DAT_INV_WIDTH                1  /* AIF1DACR_DAT_INV */
+
+/*
+ * R775 (0x307) - AIF1ADC Data
+ */
+#define WM8995_AIF1ADCL_DAT_INV                 0x0002  /* AIF1ADCL_DAT_INV */
+#define WM8995_AIF1ADCL_DAT_INV_MASK            0x0002  /* AIF1ADCL_DAT_INV */
+#define WM8995_AIF1ADCL_DAT_INV_SHIFT                1  /* AIF1ADCL_DAT_INV */
+#define WM8995_AIF1ADCL_DAT_INV_WIDTH                1  /* AIF1ADCL_DAT_INV */
+#define WM8995_AIF1ADCR_DAT_INV                 0x0001  /* AIF1ADCR_DAT_INV */
+#define WM8995_AIF1ADCR_DAT_INV_MASK            0x0001  /* AIF1ADCR_DAT_INV */
+#define WM8995_AIF1ADCR_DAT_INV_SHIFT                0  /* AIF1ADCR_DAT_INV */
+#define WM8995_AIF1ADCR_DAT_INV_WIDTH                1  /* AIF1ADCR_DAT_INV */
+
+/*
+ * R784 (0x310) - AIF2 Control (1)
+ */
+#define WM8995_AIF2ADCL_SRC                     0x8000  /* AIF2ADCL_SRC */
+#define WM8995_AIF2ADCL_SRC_MASK                0x8000  /* AIF2ADCL_SRC */
+#define WM8995_AIF2ADCL_SRC_SHIFT                   15  /* AIF2ADCL_SRC */
+#define WM8995_AIF2ADCL_SRC_WIDTH                    1  /* AIF2ADCL_SRC */
+#define WM8995_AIF2ADCR_SRC                     0x4000  /* AIF2ADCR_SRC */
+#define WM8995_AIF2ADCR_SRC_MASK                0x4000  /* AIF2ADCR_SRC */
+#define WM8995_AIF2ADCR_SRC_SHIFT                   14  /* AIF2ADCR_SRC */
+#define WM8995_AIF2ADCR_SRC_WIDTH                    1  /* AIF2ADCR_SRC */
+#define WM8995_AIF2ADC_TDM                      0x2000  /* AIF2ADC_TDM */
+#define WM8995_AIF2ADC_TDM_MASK                 0x2000  /* AIF2ADC_TDM */
+#define WM8995_AIF2ADC_TDM_SHIFT                    13  /* AIF2ADC_TDM */
+#define WM8995_AIF2ADC_TDM_WIDTH                     1  /* AIF2ADC_TDM */
+#define WM8995_AIF2ADC_TDM_CHAN                 0x1000  /* AIF2ADC_TDM_CHAN */
+#define WM8995_AIF2ADC_TDM_CHAN_MASK            0x1000  /* AIF2ADC_TDM_CHAN */
+#define WM8995_AIF2ADC_TDM_CHAN_SHIFT               12  /* AIF2ADC_TDM_CHAN */
+#define WM8995_AIF2ADC_TDM_CHAN_WIDTH                1  /* AIF2ADC_TDM_CHAN */
+#define WM8995_AIF2_BCLK_INV                    0x0100  /* AIF2_BCLK_INV */
+#define WM8995_AIF2_BCLK_INV_MASK               0x0100  /* AIF2_BCLK_INV */
+#define WM8995_AIF2_BCLK_INV_SHIFT                   8  /* AIF2_BCLK_INV */
+#define WM8995_AIF2_BCLK_INV_WIDTH                   1  /* AIF2_BCLK_INV */
+#define WM8995_AIF2_LRCLK_INV                   0x0080  /* AIF2_LRCLK_INV */
+#define WM8995_AIF2_LRCLK_INV_MASK              0x0080  /* AIF2_LRCLK_INV */
+#define WM8995_AIF2_LRCLK_INV_SHIFT                  7  /* AIF2_LRCLK_INV */
+#define WM8995_AIF2_LRCLK_INV_WIDTH                  1  /* AIF2_LRCLK_INV */
+#define WM8995_AIF2_WL_MASK                     0x0060  /* AIF2_WL - [6:5] */
+#define WM8995_AIF2_WL_SHIFT                         5  /* AIF2_WL - [6:5] */
+#define WM8995_AIF2_WL_WIDTH                         2  /* AIF2_WL - [6:5] */
+#define WM8995_AIF2_FMT_MASK                    0x0018  /* AIF2_FMT - [4:3] */
+#define WM8995_AIF2_FMT_SHIFT                        3  /* AIF2_FMT - [4:3] */
+#define WM8995_AIF2_FMT_WIDTH                        2  /* AIF2_FMT - [4:3] */
+
+/*
+ * R785 (0x311) - AIF2 Control (2)
+ */
+#define WM8995_AIF2DACL_SRC                     0x8000  /* AIF2DACL_SRC */
+#define WM8995_AIF2DACL_SRC_MASK                0x8000  /* AIF2DACL_SRC */
+#define WM8995_AIF2DACL_SRC_SHIFT                   15  /* AIF2DACL_SRC */
+#define WM8995_AIF2DACL_SRC_WIDTH                    1  /* AIF2DACL_SRC */
+#define WM8995_AIF2DACR_SRC                     0x4000  /* AIF2DACR_SRC */
+#define WM8995_AIF2DACR_SRC_MASK                0x4000  /* AIF2DACR_SRC */
+#define WM8995_AIF2DACR_SRC_SHIFT                   14  /* AIF2DACR_SRC */
+#define WM8995_AIF2DACR_SRC_WIDTH                    1  /* AIF2DACR_SRC */
+#define WM8995_AIF2DAC_TDM                      0x2000  /* AIF2DAC_TDM */
+#define WM8995_AIF2DAC_TDM_MASK                 0x2000  /* AIF2DAC_TDM */
+#define WM8995_AIF2DAC_TDM_SHIFT                    13  /* AIF2DAC_TDM */
+#define WM8995_AIF2DAC_TDM_WIDTH                     1  /* AIF2DAC_TDM */
+#define WM8995_AIF2DAC_TDM_CHAN                 0x1000  /* AIF2DAC_TDM_CHAN */
+#define WM8995_AIF2DAC_TDM_CHAN_MASK            0x1000  /* AIF2DAC_TDM_CHAN */
+#define WM8995_AIF2DAC_TDM_CHAN_SHIFT               12  /* AIF2DAC_TDM_CHAN */
+#define WM8995_AIF2DAC_TDM_CHAN_WIDTH                1  /* AIF2DAC_TDM_CHAN */
+#define WM8995_AIF2DAC_BOOST_MASK               0x0C00  /* AIF2DAC_BOOST - [11:10] */
+#define WM8995_AIF2DAC_BOOST_SHIFT                  10  /* AIF2DAC_BOOST - [11:10] */
+#define WM8995_AIF2DAC_BOOST_WIDTH                   2  /* AIF2DAC_BOOST - [11:10] */
+#define WM8995_AIF2DAC_COMP                     0x0010  /* AIF2DAC_COMP */
+#define WM8995_AIF2DAC_COMP_MASK                0x0010  /* AIF2DAC_COMP */
+#define WM8995_AIF2DAC_COMP_SHIFT                    4  /* AIF2DAC_COMP */
+#define WM8995_AIF2DAC_COMP_WIDTH                    1  /* AIF2DAC_COMP */
+#define WM8995_AIF2DAC_COMPMODE                 0x0008  /* AIF2DAC_COMPMODE */
+#define WM8995_AIF2DAC_COMPMODE_MASK            0x0008  /* AIF2DAC_COMPMODE */
+#define WM8995_AIF2DAC_COMPMODE_SHIFT                3  /* AIF2DAC_COMPMODE */
+#define WM8995_AIF2DAC_COMPMODE_WIDTH                1  /* AIF2DAC_COMPMODE */
+#define WM8995_AIF2ADC_COMP                     0x0004  /* AIF2ADC_COMP */
+#define WM8995_AIF2ADC_COMP_MASK                0x0004  /* AIF2ADC_COMP */
+#define WM8995_AIF2ADC_COMP_SHIFT                    2  /* AIF2ADC_COMP */
+#define WM8995_AIF2ADC_COMP_WIDTH                    1  /* AIF2ADC_COMP */
+#define WM8995_AIF2ADC_COMPMODE                 0x0002  /* AIF2ADC_COMPMODE */
+#define WM8995_AIF2ADC_COMPMODE_MASK            0x0002  /* AIF2ADC_COMPMODE */
+#define WM8995_AIF2ADC_COMPMODE_SHIFT                1  /* AIF2ADC_COMPMODE */
+#define WM8995_AIF2ADC_COMPMODE_WIDTH                1  /* AIF2ADC_COMPMODE */
+#define WM8995_AIF2_LOOPBACK                    0x0001  /* AIF2_LOOPBACK */
+#define WM8995_AIF2_LOOPBACK_MASK               0x0001  /* AIF2_LOOPBACK */
+#define WM8995_AIF2_LOOPBACK_SHIFT                   0  /* AIF2_LOOPBACK */
+#define WM8995_AIF2_LOOPBACK_WIDTH                   1  /* AIF2_LOOPBACK */
+
+/*
+ * R786 (0x312) - AIF2 Master/Slave
+ */
+#define WM8995_AIF2_TRI                         0x8000  /* AIF2_TRI */
+#define WM8995_AIF2_TRI_MASK                    0x8000  /* AIF2_TRI */
+#define WM8995_AIF2_TRI_SHIFT                       15  /* AIF2_TRI */
+#define WM8995_AIF2_TRI_WIDTH                        1  /* AIF2_TRI */
+#define WM8995_AIF2_MSTR                        0x4000  /* AIF2_MSTR */
+#define WM8995_AIF2_MSTR_MASK                   0x4000  /* AIF2_MSTR */
+#define WM8995_AIF2_MSTR_SHIFT                      14  /* AIF2_MSTR */
+#define WM8995_AIF2_MSTR_WIDTH                       1  /* AIF2_MSTR */
+#define WM8995_AIF2_CLK_FRC                     0x2000  /* AIF2_CLK_FRC */
+#define WM8995_AIF2_CLK_FRC_MASK                0x2000  /* AIF2_CLK_FRC */
+#define WM8995_AIF2_CLK_FRC_SHIFT                   13  /* AIF2_CLK_FRC */
+#define WM8995_AIF2_CLK_FRC_WIDTH                    1  /* AIF2_CLK_FRC */
+#define WM8995_AIF2_LRCLK_FRC                   0x1000  /* AIF2_LRCLK_FRC */
+#define WM8995_AIF2_LRCLK_FRC_MASK              0x1000  /* AIF2_LRCLK_FRC */
+#define WM8995_AIF2_LRCLK_FRC_SHIFT                 12  /* AIF2_LRCLK_FRC */
+#define WM8995_AIF2_LRCLK_FRC_WIDTH                  1  /* AIF2_LRCLK_FRC */
+
+/*
+ * R787 (0x313) - AIF2 BCLK
+ */
+#define WM8995_AIF2_BCLK_DIV_MASK               0x00F0  /* AIF2_BCLK_DIV - [7:4] */
+#define WM8995_AIF2_BCLK_DIV_SHIFT                   4  /* AIF2_BCLK_DIV - [7:4] */
+#define WM8995_AIF2_BCLK_DIV_WIDTH                   4  /* AIF2_BCLK_DIV - [7:4] */
+
+/*
+ * R788 (0x314) - AIF2ADC LRCLK
+ */
+#define WM8995_AIF2ADC_LRCLK_DIR                0x0800  /* AIF2ADC_LRCLK_DIR */
+#define WM8995_AIF2ADC_LRCLK_DIR_MASK           0x0800  /* AIF2ADC_LRCLK_DIR */
+#define WM8995_AIF2ADC_LRCLK_DIR_SHIFT              11  /* AIF2ADC_LRCLK_DIR */
+#define WM8995_AIF2ADC_LRCLK_DIR_WIDTH               1  /* AIF2ADC_LRCLK_DIR */
+#define WM8995_AIF2ADC_RATE_MASK                0x07FF  /* AIF2ADC_RATE - [10:0] */
+#define WM8995_AIF2ADC_RATE_SHIFT                    0  /* AIF2ADC_RATE - [10:0] */
+#define WM8995_AIF2ADC_RATE_WIDTH                   11  /* AIF2ADC_RATE - [10:0] */
+
+/*
+ * R789 (0x315) - AIF2DAC LRCLK
+ */
+#define WM8995_AIF2DAC_LRCLK_DIR                0x0800  /* AIF2DAC_LRCLK_DIR */
+#define WM8995_AIF2DAC_LRCLK_DIR_MASK           0x0800  /* AIF2DAC_LRCLK_DIR */
+#define WM8995_AIF2DAC_LRCLK_DIR_SHIFT              11  /* AIF2DAC_LRCLK_DIR */
+#define WM8995_AIF2DAC_LRCLK_DIR_WIDTH               1  /* AIF2DAC_LRCLK_DIR */
+#define WM8995_AIF2DAC_RATE_MASK                0x07FF  /* AIF2DAC_RATE - [10:0] */
+#define WM8995_AIF2DAC_RATE_SHIFT                    0  /* AIF2DAC_RATE - [10:0] */
+#define WM8995_AIF2DAC_RATE_WIDTH                   11  /* AIF2DAC_RATE - [10:0] */
+
+/*
+ * R790 (0x316) - AIF2DAC Data
+ */
+#define WM8995_AIF2DACL_DAT_INV                 0x0002  /* AIF2DACL_DAT_INV */
+#define WM8995_AIF2DACL_DAT_INV_MASK            0x0002  /* AIF2DACL_DAT_INV */
+#define WM8995_AIF2DACL_DAT_INV_SHIFT                1  /* AIF2DACL_DAT_INV */
+#define WM8995_AIF2DACL_DAT_INV_WIDTH                1  /* AIF2DACL_DAT_INV */
+#define WM8995_AIF2DACR_DAT_INV                 0x0001  /* AIF2DACR_DAT_INV */
+#define WM8995_AIF2DACR_DAT_INV_MASK            0x0001  /* AIF2DACR_DAT_INV */
+#define WM8995_AIF2DACR_DAT_INV_SHIFT                0  /* AIF2DACR_DAT_INV */
+#define WM8995_AIF2DACR_DAT_INV_WIDTH                1  /* AIF2DACR_DAT_INV */
+
+/*
+ * R791 (0x317) - AIF2ADC Data
+ */
+#define WM8995_AIF2ADCL_DAT_INV                 0x0002  /* AIF2ADCL_DAT_INV */
+#define WM8995_AIF2ADCL_DAT_INV_MASK            0x0002  /* AIF2ADCL_DAT_INV */
+#define WM8995_AIF2ADCL_DAT_INV_SHIFT                1  /* AIF2ADCL_DAT_INV */
+#define WM8995_AIF2ADCL_DAT_INV_WIDTH                1  /* AIF2ADCL_DAT_INV */
+#define WM8995_AIF2ADCR_DAT_INV                 0x0001  /* AIF2ADCR_DAT_INV */
+#define WM8995_AIF2ADCR_DAT_INV_MASK            0x0001  /* AIF2ADCR_DAT_INV */
+#define WM8995_AIF2ADCR_DAT_INV_SHIFT                0  /* AIF2ADCR_DAT_INV */
+#define WM8995_AIF2ADCR_DAT_INV_WIDTH                1  /* AIF2ADCR_DAT_INV */
+
+/*
+ * R1024 (0x400) - AIF1 ADC1 Left Volume
+ */
+#define WM8995_AIF1ADC1_VU                      0x0100  /* AIF1ADC1_VU */
+#define WM8995_AIF1ADC1_VU_MASK                 0x0100  /* AIF1ADC1_VU */
+#define WM8995_AIF1ADC1_VU_SHIFT                     8  /* AIF1ADC1_VU */
+#define WM8995_AIF1ADC1_VU_WIDTH                     1  /* AIF1ADC1_VU */
+#define WM8995_AIF1ADC1L_VOL_MASK               0x00FF  /* AIF1ADC1L_VOL - [7:0] */
+#define WM8995_AIF1ADC1L_VOL_SHIFT                   0  /* AIF1ADC1L_VOL - [7:0] */
+#define WM8995_AIF1ADC1L_VOL_WIDTH                   8  /* AIF1ADC1L_VOL - [7:0] */
+
+/*
+ * R1025 (0x401) - AIF1 ADC1 Right Volume
+ */
+#define WM8995_AIF1ADC1_VU                      0x0100  /* AIF1ADC1_VU */
+#define WM8995_AIF1ADC1_VU_MASK                 0x0100  /* AIF1ADC1_VU */
+#define WM8995_AIF1ADC1_VU_SHIFT                     8  /* AIF1ADC1_VU */
+#define WM8995_AIF1ADC1_VU_WIDTH                     1  /* AIF1ADC1_VU */
+#define WM8995_AIF1ADC1R_VOL_MASK               0x00FF  /* AIF1ADC1R_VOL - [7:0] */
+#define WM8995_AIF1ADC1R_VOL_SHIFT                   0  /* AIF1ADC1R_VOL - [7:0] */
+#define WM8995_AIF1ADC1R_VOL_WIDTH                   8  /* AIF1ADC1R_VOL - [7:0] */
+
+/*
+ * R1026 (0x402) - AIF1 DAC1 Left Volume
+ */
+#define WM8995_AIF1DAC1_VU                      0x0100  /* AIF1DAC1_VU */
+#define WM8995_AIF1DAC1_VU_MASK                 0x0100  /* AIF1DAC1_VU */
+#define WM8995_AIF1DAC1_VU_SHIFT                     8  /* AIF1DAC1_VU */
+#define WM8995_AIF1DAC1_VU_WIDTH                     1  /* AIF1DAC1_VU */
+#define WM8995_AIF1DAC1L_VOL_MASK               0x00FF  /* AIF1DAC1L_VOL - [7:0] */
+#define WM8995_AIF1DAC1L_VOL_SHIFT                   0  /* AIF1DAC1L_VOL - [7:0] */
+#define WM8995_AIF1DAC1L_VOL_WIDTH                   8  /* AIF1DAC1L_VOL - [7:0] */
+
+/*
+ * R1027 (0x403) - AIF1 DAC1 Right Volume
+ */
+#define WM8995_AIF1DAC1_VU                      0x0100  /* AIF1DAC1_VU */
+#define WM8995_AIF1DAC1_VU_MASK                 0x0100  /* AIF1DAC1_VU */
+#define WM8995_AIF1DAC1_VU_SHIFT                     8  /* AIF1DAC1_VU */
+#define WM8995_AIF1DAC1_VU_WIDTH                     1  /* AIF1DAC1_VU */
+#define WM8995_AIF1DAC1R_VOL_MASK               0x00FF  /* AIF1DAC1R_VOL - [7:0] */
+#define WM8995_AIF1DAC1R_VOL_SHIFT                   0  /* AIF1DAC1R_VOL - [7:0] */
+#define WM8995_AIF1DAC1R_VOL_WIDTH                   8  /* AIF1DAC1R_VOL - [7:0] */
+
+/*
+ * R1028 (0x404) - AIF1 ADC2 Left Volume
+ */
+#define WM8995_AIF1ADC2_VU                      0x0100  /* AIF1ADC2_VU */
+#define WM8995_AIF1ADC2_VU_MASK                 0x0100  /* AIF1ADC2_VU */
+#define WM8995_AIF1ADC2_VU_SHIFT                     8  /* AIF1ADC2_VU */
+#define WM8995_AIF1ADC2_VU_WIDTH                     1  /* AIF1ADC2_VU */
+#define WM8995_AIF1ADC2L_VOL_MASK               0x00FF  /* AIF1ADC2L_VOL - [7:0] */
+#define WM8995_AIF1ADC2L_VOL_SHIFT                   0  /* AIF1ADC2L_VOL - [7:0] */
+#define WM8995_AIF1ADC2L_VOL_WIDTH                   8  /* AIF1ADC2L_VOL - [7:0] */
+
+/*
+ * R1029 (0x405) - AIF1 ADC2 Right Volume
+ */
+#define WM8995_AIF1ADC2_VU                      0x0100  /* AIF1ADC2_VU */
+#define WM8995_AIF1ADC2_VU_MASK                 0x0100  /* AIF1ADC2_VU */
+#define WM8995_AIF1ADC2_VU_SHIFT                     8  /* AIF1ADC2_VU */
+#define WM8995_AIF1ADC2_VU_WIDTH                     1  /* AIF1ADC2_VU */
+#define WM8995_AIF1ADC2R_VOL_MASK               0x00FF  /* AIF1ADC2R_VOL - [7:0] */
+#define WM8995_AIF1ADC2R_VOL_SHIFT                   0  /* AIF1ADC2R_VOL - [7:0] */
+#define WM8995_AIF1ADC2R_VOL_WIDTH                   8  /* AIF1ADC2R_VOL - [7:0] */
+
+/*
+ * R1030 (0x406) - AIF1 DAC2 Left Volume
+ */
+#define WM8995_AIF1DAC2_VU                      0x0100  /* AIF1DAC2_VU */
+#define WM8995_AIF1DAC2_VU_MASK                 0x0100  /* AIF1DAC2_VU */
+#define WM8995_AIF1DAC2_VU_SHIFT                     8  /* AIF1DAC2_VU */
+#define WM8995_AIF1DAC2_VU_WIDTH                     1  /* AIF1DAC2_VU */
+#define WM8995_AIF1DAC2L_VOL_MASK               0x00FF  /* AIF1DAC2L_VOL - [7:0] */
+#define WM8995_AIF1DAC2L_VOL_SHIFT                   0  /* AIF1DAC2L_VOL - [7:0] */
+#define WM8995_AIF1DAC2L_VOL_WIDTH                   8  /* AIF1DAC2L_VOL - [7:0] */
+
+/*
+ * R1031 (0x407) - AIF1 DAC2 Right Volume
+ */
+#define WM8995_AIF1DAC2_VU                      0x0100  /* AIF1DAC2_VU */
+#define WM8995_AIF1DAC2_VU_MASK                 0x0100  /* AIF1DAC2_VU */
+#define WM8995_AIF1DAC2_VU_SHIFT                     8  /* AIF1DAC2_VU */
+#define WM8995_AIF1DAC2_VU_WIDTH                     1  /* AIF1DAC2_VU */
+#define WM8995_AIF1DAC2R_VOL_MASK               0x00FF  /* AIF1DAC2R_VOL - [7:0] */
+#define WM8995_AIF1DAC2R_VOL_SHIFT                   0  /* AIF1DAC2R_VOL - [7:0] */
+#define WM8995_AIF1DAC2R_VOL_WIDTH                   8  /* AIF1DAC2R_VOL - [7:0] */
+
+/*
+ * R1040 (0x410) - AIF1 ADC1 Filters
+ */
+#define WM8995_AIF1ADC_4FS                      0x8000  /* AIF1ADC_4FS */
+#define WM8995_AIF1ADC_4FS_MASK                 0x8000  /* AIF1ADC_4FS */
+#define WM8995_AIF1ADC_4FS_SHIFT                    15  /* AIF1ADC_4FS */
+#define WM8995_AIF1ADC_4FS_WIDTH                     1  /* AIF1ADC_4FS */
+#define WM8995_AIF1ADC1L_HPF                    0x1000  /* AIF1ADC1L_HPF */
+#define WM8995_AIF1ADC1L_HPF_MASK               0x1000  /* AIF1ADC1L_HPF */
+#define WM8995_AIF1ADC1L_HPF_SHIFT                  12  /* AIF1ADC1L_HPF */
+#define WM8995_AIF1ADC1L_HPF_WIDTH                   1  /* AIF1ADC1L_HPF */
+#define WM8995_AIF1ADC1R_HPF                    0x0800  /* AIF1ADC1R_HPF */
+#define WM8995_AIF1ADC1R_HPF_MASK               0x0800  /* AIF1ADC1R_HPF */
+#define WM8995_AIF1ADC1R_HPF_SHIFT                  11  /* AIF1ADC1R_HPF */
+#define WM8995_AIF1ADC1R_HPF_WIDTH                   1  /* AIF1ADC1R_HPF */
+#define WM8995_AIF1ADC1_HPF_MODE                0x0008  /* AIF1ADC1_HPF_MODE */
+#define WM8995_AIF1ADC1_HPF_MODE_MASK           0x0008  /* AIF1ADC1_HPF_MODE */
+#define WM8995_AIF1ADC1_HPF_MODE_SHIFT               3  /* AIF1ADC1_HPF_MODE */
+#define WM8995_AIF1ADC1_HPF_MODE_WIDTH               1  /* AIF1ADC1_HPF_MODE */
+#define WM8995_AIF1ADC1_HPF_CUT_MASK            0x0007  /* AIF1ADC1_HPF_CUT - [2:0] */
+#define WM8995_AIF1ADC1_HPF_CUT_SHIFT                0  /* AIF1ADC1_HPF_CUT - [2:0] */
+#define WM8995_AIF1ADC1_HPF_CUT_WIDTH                3  /* AIF1ADC1_HPF_CUT - [2:0] */
+
+/*
+ * R1041 (0x411) - AIF1 ADC2 Filters
+ */
+#define WM8995_AIF1ADC2L_HPF                    0x1000  /* AIF1ADC2L_HPF */
+#define WM8995_AIF1ADC2L_HPF_MASK               0x1000  /* AIF1ADC2L_HPF */
+#define WM8995_AIF1ADC2L_HPF_SHIFT                  12  /* AIF1ADC2L_HPF */
+#define WM8995_AIF1ADC2L_HPF_WIDTH                   1  /* AIF1ADC2L_HPF */
+#define WM8995_AIF1ADC2R_HPF                    0x0800  /* AIF1ADC2R_HPF */
+#define WM8995_AIF1ADC2R_HPF_MASK               0x0800  /* AIF1ADC2R_HPF */
+#define WM8995_AIF1ADC2R_HPF_SHIFT                  11  /* AIF1ADC2R_HPF */
+#define WM8995_AIF1ADC2R_HPF_WIDTH                   1  /* AIF1ADC2R_HPF */
+#define WM8995_AIF1ADC2_HPF_MODE                0x0008  /* AIF1ADC2_HPF_MODE */
+#define WM8995_AIF1ADC2_HPF_MODE_MASK           0x0008  /* AIF1ADC2_HPF_MODE */
+#define WM8995_AIF1ADC2_HPF_MODE_SHIFT               3  /* AIF1ADC2_HPF_MODE */
+#define WM8995_AIF1ADC2_HPF_MODE_WIDTH               1  /* AIF1ADC2_HPF_MODE */
+#define WM8995_AIF1ADC2_HPF_CUT_MASK            0x0007  /* AIF1ADC2_HPF_CUT - [2:0] */
+#define WM8995_AIF1ADC2_HPF_CUT_SHIFT                0  /* AIF1ADC2_HPF_CUT - [2:0] */
+#define WM8995_AIF1ADC2_HPF_CUT_WIDTH                3  /* AIF1ADC2_HPF_CUT - [2:0] */
+
+/*
+ * R1056 (0x420) - AIF1 DAC1 Filters (1)
+ */
+#define WM8995_AIF1DAC1_MUTE                    0x0200  /* AIF1DAC1_MUTE */
+#define WM8995_AIF1DAC1_MUTE_MASK               0x0200  /* AIF1DAC1_MUTE */
+#define WM8995_AIF1DAC1_MUTE_SHIFT                   9  /* AIF1DAC1_MUTE */
+#define WM8995_AIF1DAC1_MUTE_WIDTH                   1  /* AIF1DAC1_MUTE */
+#define WM8995_AIF1DAC1_MONO                    0x0080  /* AIF1DAC1_MONO */
+#define WM8995_AIF1DAC1_MONO_MASK               0x0080  /* AIF1DAC1_MONO */
+#define WM8995_AIF1DAC1_MONO_SHIFT                   7  /* AIF1DAC1_MONO */
+#define WM8995_AIF1DAC1_MONO_WIDTH                   1  /* AIF1DAC1_MONO */
+#define WM8995_AIF1DAC1_MUTERATE                0x0020  /* AIF1DAC1_MUTERATE */
+#define WM8995_AIF1DAC1_MUTERATE_MASK           0x0020  /* AIF1DAC1_MUTERATE */
+#define WM8995_AIF1DAC1_MUTERATE_SHIFT               5  /* AIF1DAC1_MUTERATE */
+#define WM8995_AIF1DAC1_MUTERATE_WIDTH               1  /* AIF1DAC1_MUTERATE */
+#define WM8995_AIF1DAC1_UNMUTE_RAMP             0x0010  /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK        0x0010  /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT            4  /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH            1  /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8995_AIF1DAC1_DEEMP_MASK              0x0006  /* AIF1DAC1_DEEMP - [2:1] */
+#define WM8995_AIF1DAC1_DEEMP_SHIFT                  1  /* AIF1DAC1_DEEMP - [2:1] */
+#define WM8995_AIF1DAC1_DEEMP_WIDTH                  2  /* AIF1DAC1_DEEMP - [2:1] */
+
+/*
+ * R1057 (0x421) - AIF1 DAC1 Filters (2)
+ */
+#define WM8995_AIF1DAC1_3D_GAIN_MASK            0x3E00  /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8995_AIF1DAC1_3D_GAIN_SHIFT                9  /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8995_AIF1DAC1_3D_GAIN_WIDTH                5  /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8995_AIF1DAC1_3D_ENA                  0x0100  /* AIF1DAC1_3D_ENA */
+#define WM8995_AIF1DAC1_3D_ENA_MASK             0x0100  /* AIF1DAC1_3D_ENA */
+#define WM8995_AIF1DAC1_3D_ENA_SHIFT                 8  /* AIF1DAC1_3D_ENA */
+#define WM8995_AIF1DAC1_3D_ENA_WIDTH                 1  /* AIF1DAC1_3D_ENA */
+
+/*
+ * R1058 (0x422) - AIF1 DAC2 Filters (1)
+ */
+#define WM8995_AIF1DAC2_MUTE                    0x0200  /* AIF1DAC2_MUTE */
+#define WM8995_AIF1DAC2_MUTE_MASK               0x0200  /* AIF1DAC2_MUTE */
+#define WM8995_AIF1DAC2_MUTE_SHIFT                   9  /* AIF1DAC2_MUTE */
+#define WM8995_AIF1DAC2_MUTE_WIDTH                   1  /* AIF1DAC2_MUTE */
+#define WM8995_AIF1DAC2_MONO                    0x0080  /* AIF1DAC2_MONO */
+#define WM8995_AIF1DAC2_MONO_MASK               0x0080  /* AIF1DAC2_MONO */
+#define WM8995_AIF1DAC2_MONO_SHIFT                   7  /* AIF1DAC2_MONO */
+#define WM8995_AIF1DAC2_MONO_WIDTH                   1  /* AIF1DAC2_MONO */
+#define WM8995_AIF1DAC2_MUTERATE                0x0020  /* AIF1DAC2_MUTERATE */
+#define WM8995_AIF1DAC2_MUTERATE_MASK           0x0020  /* AIF1DAC2_MUTERATE */
+#define WM8995_AIF1DAC2_MUTERATE_SHIFT               5  /* AIF1DAC2_MUTERATE */
+#define WM8995_AIF1DAC2_MUTERATE_WIDTH               1  /* AIF1DAC2_MUTERATE */
+#define WM8995_AIF1DAC2_UNMUTE_RAMP             0x0010  /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK        0x0010  /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT            4  /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH            1  /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8995_AIF1DAC2_DEEMP_MASK              0x0006  /* AIF1DAC2_DEEMP - [2:1] */
+#define WM8995_AIF1DAC2_DEEMP_SHIFT                  1  /* AIF1DAC2_DEEMP - [2:1] */
+#define WM8995_AIF1DAC2_DEEMP_WIDTH                  2  /* AIF1DAC2_DEEMP - [2:1] */
+
+/*
+ * R1059 (0x423) - AIF1 DAC2 Filters (2)
+ */
+#define WM8995_AIF1DAC2_3D_GAIN_MASK            0x3E00  /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8995_AIF1DAC2_3D_GAIN_SHIFT                9  /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8995_AIF1DAC2_3D_GAIN_WIDTH                5  /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8995_AIF1DAC2_3D_ENA                  0x0100  /* AIF1DAC2_3D_ENA */
+#define WM8995_AIF1DAC2_3D_ENA_MASK             0x0100  /* AIF1DAC2_3D_ENA */
+#define WM8995_AIF1DAC2_3D_ENA_SHIFT                 8  /* AIF1DAC2_3D_ENA */
+#define WM8995_AIF1DAC2_3D_ENA_WIDTH                 1  /* AIF1DAC2_3D_ENA */
+
+/*
+ * R1088 (0x440) - AIF1 DRC1 (1)
+ */
+#define WM8995_AIF1DRC1_SIG_DET_RMS_MASK        0xF800  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT           11  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH            5  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF1DRC1_SIG_DET_PK_MASK         0x0600  /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT             9  /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH             2  /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8995_AIF1DRC1_NG_ENA                  0x0100  /* AIF1DRC1_NG_ENA */
+#define WM8995_AIF1DRC1_NG_ENA_MASK             0x0100  /* AIF1DRC1_NG_ENA */
+#define WM8995_AIF1DRC1_NG_ENA_SHIFT                 8  /* AIF1DRC1_NG_ENA */
+#define WM8995_AIF1DRC1_NG_ENA_WIDTH                 1  /* AIF1DRC1_NG_ENA */
+#define WM8995_AIF1DRC1_SIG_DET_MODE            0x0080  /* AIF1DRC1_SIG_DET_MODE */
+#define WM8995_AIF1DRC1_SIG_DET_MODE_MASK       0x0080  /* AIF1DRC1_SIG_DET_MODE */
+#define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT           7  /* AIF1DRC1_SIG_DET_MODE */
+#define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH           1  /* AIF1DRC1_SIG_DET_MODE */
+#define WM8995_AIF1DRC1_SIG_DET                 0x0040  /* AIF1DRC1_SIG_DET */
+#define WM8995_AIF1DRC1_SIG_DET_MASK            0x0040  /* AIF1DRC1_SIG_DET */
+#define WM8995_AIF1DRC1_SIG_DET_SHIFT                6  /* AIF1DRC1_SIG_DET */
+#define WM8995_AIF1DRC1_SIG_DET_WIDTH                1  /* AIF1DRC1_SIG_DET */
+#define WM8995_AIF1DRC1_KNEE2_OP_ENA            0x0020  /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK       0x0020  /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT           5  /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH           1  /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8995_AIF1DRC1_QR                      0x0010  /* AIF1DRC1_QR */
+#define WM8995_AIF1DRC1_QR_MASK                 0x0010  /* AIF1DRC1_QR */
+#define WM8995_AIF1DRC1_QR_SHIFT                     4  /* AIF1DRC1_QR */
+#define WM8995_AIF1DRC1_QR_WIDTH                     1  /* AIF1DRC1_QR */
+#define WM8995_AIF1DRC1_ANTICLIP                0x0008  /* AIF1DRC1_ANTICLIP */
+#define WM8995_AIF1DRC1_ANTICLIP_MASK           0x0008  /* AIF1DRC1_ANTICLIP */
+#define WM8995_AIF1DRC1_ANTICLIP_SHIFT               3  /* AIF1DRC1_ANTICLIP */
+#define WM8995_AIF1DRC1_ANTICLIP_WIDTH               1  /* AIF1DRC1_ANTICLIP */
+#define WM8995_AIF1DAC1_DRC_ENA                 0x0004  /* AIF1DAC1_DRC_ENA */
+#define WM8995_AIF1DAC1_DRC_ENA_MASK            0x0004  /* AIF1DAC1_DRC_ENA */
+#define WM8995_AIF1DAC1_DRC_ENA_SHIFT                2  /* AIF1DAC1_DRC_ENA */
+#define WM8995_AIF1DAC1_DRC_ENA_WIDTH                1  /* AIF1DAC1_DRC_ENA */
+#define WM8995_AIF1ADC1L_DRC_ENA                0x0002  /* AIF1ADC1L_DRC_ENA */
+#define WM8995_AIF1ADC1L_DRC_ENA_MASK           0x0002  /* AIF1ADC1L_DRC_ENA */
+#define WM8995_AIF1ADC1L_DRC_ENA_SHIFT               1  /* AIF1ADC1L_DRC_ENA */
+#define WM8995_AIF1ADC1L_DRC_ENA_WIDTH               1  /* AIF1ADC1L_DRC_ENA */
+#define WM8995_AIF1ADC1R_DRC_ENA                0x0001  /* AIF1ADC1R_DRC_ENA */
+#define WM8995_AIF1ADC1R_DRC_ENA_MASK           0x0001  /* AIF1ADC1R_DRC_ENA */
+#define WM8995_AIF1ADC1R_DRC_ENA_SHIFT               0  /* AIF1ADC1R_DRC_ENA */
+#define WM8995_AIF1ADC1R_DRC_ENA_WIDTH               1  /* AIF1ADC1R_DRC_ENA */
+
+/*
+ * R1089 (0x441) - AIF1 DRC1 (2)
+ */
+#define WM8995_AIF1DRC1_ATK_MASK                0x1E00  /* AIF1DRC1_ATK - [12:9] */
+#define WM8995_AIF1DRC1_ATK_SHIFT                    9  /* AIF1DRC1_ATK - [12:9] */
+#define WM8995_AIF1DRC1_ATK_WIDTH                    4  /* AIF1DRC1_ATK - [12:9] */
+#define WM8995_AIF1DRC1_DCY_MASK                0x01E0  /* AIF1DRC1_DCY - [8:5] */
+#define WM8995_AIF1DRC1_DCY_SHIFT                    5  /* AIF1DRC1_DCY - [8:5] */
+#define WM8995_AIF1DRC1_DCY_WIDTH                    4  /* AIF1DRC1_DCY - [8:5] */
+#define WM8995_AIF1DRC1_MINGAIN_MASK            0x001C  /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8995_AIF1DRC1_MINGAIN_SHIFT                2  /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8995_AIF1DRC1_MINGAIN_WIDTH                3  /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8995_AIF1DRC1_MAXGAIN_MASK            0x0003  /* AIF1DRC1_MAXGAIN - [1:0] */
+#define WM8995_AIF1DRC1_MAXGAIN_SHIFT                0  /* AIF1DRC1_MAXGAIN - [1:0] */
+#define WM8995_AIF1DRC1_MAXGAIN_WIDTH                2  /* AIF1DRC1_MAXGAIN - [1:0] */
+
+/*
+ * R1090 (0x442) - AIF1 DRC1 (3)
+ */
+#define WM8995_AIF1DRC1_NG_MINGAIN_MASK         0xF000  /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT            12  /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH             4  /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8995_AIF1DRC1_NG_EXP_MASK             0x0C00  /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8995_AIF1DRC1_NG_EXP_SHIFT                10  /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8995_AIF1DRC1_NG_EXP_WIDTH                 2  /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8995_AIF1DRC1_QR_THR_MASK             0x0300  /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8995_AIF1DRC1_QR_THR_SHIFT                 8  /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8995_AIF1DRC1_QR_THR_WIDTH                 2  /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8995_AIF1DRC1_QR_DCY_MASK             0x00C0  /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8995_AIF1DRC1_QR_DCY_SHIFT                 6  /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8995_AIF1DRC1_QR_DCY_WIDTH                 2  /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8995_AIF1DRC1_HI_COMP_MASK            0x0038  /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8995_AIF1DRC1_HI_COMP_SHIFT                3  /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8995_AIF1DRC1_HI_COMP_WIDTH                3  /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8995_AIF1DRC1_LO_COMP_MASK            0x0007  /* AIF1DRC1_LO_COMP - [2:0] */
+#define WM8995_AIF1DRC1_LO_COMP_SHIFT                0  /* AIF1DRC1_LO_COMP - [2:0] */
+#define WM8995_AIF1DRC1_LO_COMP_WIDTH                3  /* AIF1DRC1_LO_COMP - [2:0] */
+
+/*
+ * R1091 (0x443) - AIF1 DRC1 (4)
+ */
+#define WM8995_AIF1DRC1_KNEE_IP_MASK            0x07E0  /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8995_AIF1DRC1_KNEE_IP_SHIFT                5  /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8995_AIF1DRC1_KNEE_IP_WIDTH                6  /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8995_AIF1DRC1_KNEE_OP_MASK            0x001F  /* AIF1DRC1_KNEE_OP - [4:0] */
+#define WM8995_AIF1DRC1_KNEE_OP_SHIFT                0  /* AIF1DRC1_KNEE_OP - [4:0] */
+#define WM8995_AIF1DRC1_KNEE_OP_WIDTH                5  /* AIF1DRC1_KNEE_OP - [4:0] */
+
+/*
+ * R1092 (0x444) - AIF1 DRC1 (5)
+ */
+#define WM8995_AIF1DRC1_KNEE2_IP_MASK           0x03E0  /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8995_AIF1DRC1_KNEE2_IP_SHIFT               5  /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8995_AIF1DRC1_KNEE2_IP_WIDTH               5  /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8995_AIF1DRC1_KNEE2_OP_MASK           0x001F  /* AIF1DRC1_KNEE2_OP - [4:0] */
+#define WM8995_AIF1DRC1_KNEE2_OP_SHIFT               0  /* AIF1DRC1_KNEE2_OP - [4:0] */
+#define WM8995_AIF1DRC1_KNEE2_OP_WIDTH               5  /* AIF1DRC1_KNEE2_OP - [4:0] */
+
+/*
+ * R1104 (0x450) - AIF1 DRC2 (1)
+ */
+#define WM8995_AIF1DRC2_SIG_DET_RMS_MASK        0xF800  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT           11  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH            5  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF1DRC2_SIG_DET_PK_MASK         0x0600  /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT             9  /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH             2  /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8995_AIF1DRC2_NG_ENA                  0x0100  /* AIF1DRC2_NG_ENA */
+#define WM8995_AIF1DRC2_NG_ENA_MASK             0x0100  /* AIF1DRC2_NG_ENA */
+#define WM8995_AIF1DRC2_NG_ENA_SHIFT                 8  /* AIF1DRC2_NG_ENA */
+#define WM8995_AIF1DRC2_NG_ENA_WIDTH                 1  /* AIF1DRC2_NG_ENA */
+#define WM8995_AIF1DRC2_SIG_DET_MODE            0x0080  /* AIF1DRC2_SIG_DET_MODE */
+#define WM8995_AIF1DRC2_SIG_DET_MODE_MASK       0x0080  /* AIF1DRC2_SIG_DET_MODE */
+#define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT           7  /* AIF1DRC2_SIG_DET_MODE */
+#define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH           1  /* AIF1DRC2_SIG_DET_MODE */
+#define WM8995_AIF1DRC2_SIG_DET                 0x0040  /* AIF1DRC2_SIG_DET */
+#define WM8995_AIF1DRC2_SIG_DET_MASK            0x0040  /* AIF1DRC2_SIG_DET */
+#define WM8995_AIF1DRC2_SIG_DET_SHIFT                6  /* AIF1DRC2_SIG_DET */
+#define WM8995_AIF1DRC2_SIG_DET_WIDTH                1  /* AIF1DRC2_SIG_DET */
+#define WM8995_AIF1DRC2_KNEE2_OP_ENA            0x0020  /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK       0x0020  /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT           5  /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH           1  /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8995_AIF1DRC2_QR                      0x0010  /* AIF1DRC2_QR */
+#define WM8995_AIF1DRC2_QR_MASK                 0x0010  /* AIF1DRC2_QR */
+#define WM8995_AIF1DRC2_QR_SHIFT                     4  /* AIF1DRC2_QR */
+#define WM8995_AIF1DRC2_QR_WIDTH                     1  /* AIF1DRC2_QR */
+#define WM8995_AIF1DRC2_ANTICLIP                0x0008  /* AIF1DRC2_ANTICLIP */
+#define WM8995_AIF1DRC2_ANTICLIP_MASK           0x0008  /* AIF1DRC2_ANTICLIP */
+#define WM8995_AIF1DRC2_ANTICLIP_SHIFT               3  /* AIF1DRC2_ANTICLIP */
+#define WM8995_AIF1DRC2_ANTICLIP_WIDTH               1  /* AIF1DRC2_ANTICLIP */
+#define WM8995_AIF1DAC2_DRC_ENA                 0x0004  /* AIF1DAC2_DRC_ENA */
+#define WM8995_AIF1DAC2_DRC_ENA_MASK            0x0004  /* AIF1DAC2_DRC_ENA */
+#define WM8995_AIF1DAC2_DRC_ENA_SHIFT                2  /* AIF1DAC2_DRC_ENA */
+#define WM8995_AIF1DAC2_DRC_ENA_WIDTH                1  /* AIF1DAC2_DRC_ENA */
+#define WM8995_AIF1ADC2L_DRC_ENA                0x0002  /* AIF1ADC2L_DRC_ENA */
+#define WM8995_AIF1ADC2L_DRC_ENA_MASK           0x0002  /* AIF1ADC2L_DRC_ENA */
+#define WM8995_AIF1ADC2L_DRC_ENA_SHIFT               1  /* AIF1ADC2L_DRC_ENA */
+#define WM8995_AIF1ADC2L_DRC_ENA_WIDTH               1  /* AIF1ADC2L_DRC_ENA */
+#define WM8995_AIF1ADC2R_DRC_ENA                0x0001  /* AIF1ADC2R_DRC_ENA */
+#define WM8995_AIF1ADC2R_DRC_ENA_MASK           0x0001  /* AIF1ADC2R_DRC_ENA */
+#define WM8995_AIF1ADC2R_DRC_ENA_SHIFT               0  /* AIF1ADC2R_DRC_ENA */
+#define WM8995_AIF1ADC2R_DRC_ENA_WIDTH               1  /* AIF1ADC2R_DRC_ENA */
+
+/*
+ * R1105 (0x451) - AIF1 DRC2 (2)
+ */
+#define WM8995_AIF1DRC2_ATK_MASK                0x1E00  /* AIF1DRC2_ATK - [12:9] */
+#define WM8995_AIF1DRC2_ATK_SHIFT                    9  /* AIF1DRC2_ATK - [12:9] */
+#define WM8995_AIF1DRC2_ATK_WIDTH                    4  /* AIF1DRC2_ATK - [12:9] */
+#define WM8995_AIF1DRC2_DCY_MASK                0x01E0  /* AIF1DRC2_DCY - [8:5] */
+#define WM8995_AIF1DRC2_DCY_SHIFT                    5  /* AIF1DRC2_DCY - [8:5] */
+#define WM8995_AIF1DRC2_DCY_WIDTH                    4  /* AIF1DRC2_DCY - [8:5] */
+#define WM8995_AIF1DRC2_MINGAIN_MASK            0x001C  /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8995_AIF1DRC2_MINGAIN_SHIFT                2  /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8995_AIF1DRC2_MINGAIN_WIDTH                3  /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8995_AIF1DRC2_MAXGAIN_MASK            0x0003  /* AIF1DRC2_MAXGAIN - [1:0] */
+#define WM8995_AIF1DRC2_MAXGAIN_SHIFT                0  /* AIF1DRC2_MAXGAIN - [1:0] */
+#define WM8995_AIF1DRC2_MAXGAIN_WIDTH                2  /* AIF1DRC2_MAXGAIN - [1:0] */
+
+/*
+ * R1106 (0x452) - AIF1 DRC2 (3)
+ */
+#define WM8995_AIF1DRC2_NG_MINGAIN_MASK         0xF000  /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT            12  /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH             4  /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8995_AIF1DRC2_NG_EXP_MASK             0x0C00  /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8995_AIF1DRC2_NG_EXP_SHIFT                10  /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8995_AIF1DRC2_NG_EXP_WIDTH                 2  /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8995_AIF1DRC2_QR_THR_MASK             0x0300  /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8995_AIF1DRC2_QR_THR_SHIFT                 8  /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8995_AIF1DRC2_QR_THR_WIDTH                 2  /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8995_AIF1DRC2_QR_DCY_MASK             0x00C0  /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8995_AIF1DRC2_QR_DCY_SHIFT                 6  /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8995_AIF1DRC2_QR_DCY_WIDTH                 2  /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8995_AIF1DRC2_HI_COMP_MASK            0x0038  /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8995_AIF1DRC2_HI_COMP_SHIFT                3  /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8995_AIF1DRC2_HI_COMP_WIDTH                3  /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8995_AIF1DRC2_LO_COMP_MASK            0x0007  /* AIF1DRC2_LO_COMP - [2:0] */
+#define WM8995_AIF1DRC2_LO_COMP_SHIFT                0  /* AIF1DRC2_LO_COMP - [2:0] */
+#define WM8995_AIF1DRC2_LO_COMP_WIDTH                3  /* AIF1DRC2_LO_COMP - [2:0] */
+
+/*
+ * R1107 (0x453) - AIF1 DRC2 (4)
+ */
+#define WM8995_AIF1DRC2_KNEE_IP_MASK            0x07E0  /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8995_AIF1DRC2_KNEE_IP_SHIFT                5  /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8995_AIF1DRC2_KNEE_IP_WIDTH                6  /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8995_AIF1DRC2_KNEE_OP_MASK            0x001F  /* AIF1DRC2_KNEE_OP - [4:0] */
+#define WM8995_AIF1DRC2_KNEE_OP_SHIFT                0  /* AIF1DRC2_KNEE_OP - [4:0] */
+#define WM8995_AIF1DRC2_KNEE_OP_WIDTH                5  /* AIF1DRC2_KNEE_OP - [4:0] */
+
+/*
+ * R1108 (0x454) - AIF1 DRC2 (5)
+ */
+#define WM8995_AIF1DRC2_KNEE2_IP_MASK           0x03E0  /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8995_AIF1DRC2_KNEE2_IP_SHIFT               5  /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8995_AIF1DRC2_KNEE2_IP_WIDTH               5  /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8995_AIF1DRC2_KNEE2_OP_MASK           0x001F  /* AIF1DRC2_KNEE2_OP - [4:0] */
+#define WM8995_AIF1DRC2_KNEE2_OP_SHIFT               0  /* AIF1DRC2_KNEE2_OP - [4:0] */
+#define WM8995_AIF1DRC2_KNEE2_OP_WIDTH               5  /* AIF1DRC2_KNEE2_OP - [4:0] */
+
+/*
+ * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
+ */
+#define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK         0xF800  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT            11  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK         0x07C0  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT             6  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK         0x003E  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT             1  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF1DAC1_EQ_ENA                  0x0001  /* AIF1DAC1_EQ_ENA */
+#define WM8995_AIF1DAC1_EQ_ENA_MASK             0x0001  /* AIF1DAC1_EQ_ENA */
+#define WM8995_AIF1DAC1_EQ_ENA_SHIFT                 0  /* AIF1DAC1_EQ_ENA */
+#define WM8995_AIF1DAC1_EQ_ENA_WIDTH                 1  /* AIF1DAC1_EQ_ENA */
+
+/*
+ * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
+ */
+#define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK         0xF800  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT            11  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK         0x07C0  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+#define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT             6  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+#define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
+ */
+#define WM8995_AIF1DAC1_EQ_B1_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B1_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B1_A_SHIFT                0  /* AIF1DAC1_EQ_B1_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B1_A_WIDTH               16  /* AIF1DAC1_EQ_B1_A - [15:0] */
+
+/*
+ * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
+ */
+#define WM8995_AIF1DAC1_EQ_B1_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B1_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B1_B_SHIFT                0  /* AIF1DAC1_EQ_B1_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B1_B_WIDTH               16  /* AIF1DAC1_EQ_B1_B - [15:0] */
+
+/*
+ * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
+ */
+#define WM8995_AIF1DAC1_EQ_B1_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B1_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT               0  /* AIF1DAC1_EQ_B1_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH              16  /* AIF1DAC1_EQ_B1_PG - [15:0] */
+
+/*
+ * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
+ */
+#define WM8995_AIF1DAC1_EQ_B2_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B2_A_SHIFT                0  /* AIF1DAC1_EQ_B2_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B2_A_WIDTH               16  /* AIF1DAC1_EQ_B2_A - [15:0] */
+
+/*
+ * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
+ */
+#define WM8995_AIF1DAC1_EQ_B2_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B2_B_SHIFT                0  /* AIF1DAC1_EQ_B2_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B2_B_WIDTH               16  /* AIF1DAC1_EQ_B2_B - [15:0] */
+
+/*
+ * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
+ */
+#define WM8995_AIF1DAC1_EQ_B2_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_C - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B2_C_SHIFT                0  /* AIF1DAC1_EQ_B2_C - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B2_C_WIDTH               16  /* AIF1DAC1_EQ_B2_C - [15:0] */
+
+/*
+ * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
+ */
+#define WM8995_AIF1DAC1_EQ_B2_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B2_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT               0  /* AIF1DAC1_EQ_B2_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH              16  /* AIF1DAC1_EQ_B2_PG - [15:0] */
+
+/*
+ * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
+ */
+#define WM8995_AIF1DAC1_EQ_B3_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B3_A_SHIFT                0  /* AIF1DAC1_EQ_B3_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B3_A_WIDTH               16  /* AIF1DAC1_EQ_B3_A - [15:0] */
+
+/*
+ * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
+ */
+#define WM8995_AIF1DAC1_EQ_B3_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B3_B_SHIFT                0  /* AIF1DAC1_EQ_B3_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B3_B_WIDTH               16  /* AIF1DAC1_EQ_B3_B - [15:0] */
+
+/*
+ * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
+ */
+#define WM8995_AIF1DAC1_EQ_B3_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_C - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B3_C_SHIFT                0  /* AIF1DAC1_EQ_B3_C - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B3_C_WIDTH               16  /* AIF1DAC1_EQ_B3_C - [15:0] */
+
+/*
+ * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
+ */
+#define WM8995_AIF1DAC1_EQ_B3_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B3_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT               0  /* AIF1DAC1_EQ_B3_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH              16  /* AIF1DAC1_EQ_B3_PG - [15:0] */
+
+/*
+ * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
+ */
+#define WM8995_AIF1DAC1_EQ_B4_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B4_A_SHIFT                0  /* AIF1DAC1_EQ_B4_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B4_A_WIDTH               16  /* AIF1DAC1_EQ_B4_A - [15:0] */
+
+/*
+ * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
+ */
+#define WM8995_AIF1DAC1_EQ_B4_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B4_B_SHIFT                0  /* AIF1DAC1_EQ_B4_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B4_B_WIDTH               16  /* AIF1DAC1_EQ_B4_B - [15:0] */
+
+/*
+ * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
+ */
+#define WM8995_AIF1DAC1_EQ_B4_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_C - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B4_C_SHIFT                0  /* AIF1DAC1_EQ_B4_C - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B4_C_WIDTH               16  /* AIF1DAC1_EQ_B4_C - [15:0] */
+
+/*
+ * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
+ */
+#define WM8995_AIF1DAC1_EQ_B4_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B4_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT               0  /* AIF1DAC1_EQ_B4_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH              16  /* AIF1DAC1_EQ_B4_PG - [15:0] */
+
+/*
+ * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
+ */
+#define WM8995_AIF1DAC1_EQ_B5_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B5_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B5_A_SHIFT                0  /* AIF1DAC1_EQ_B5_A - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B5_A_WIDTH               16  /* AIF1DAC1_EQ_B5_A - [15:0] */
+
+/*
+ * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
+ */
+#define WM8995_AIF1DAC1_EQ_B5_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B5_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B5_B_SHIFT                0  /* AIF1DAC1_EQ_B5_B - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B5_B_WIDTH               16  /* AIF1DAC1_EQ_B5_B - [15:0] */
+
+/*
+ * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
+ */
+#define WM8995_AIF1DAC1_EQ_B5_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B5_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT               0  /* AIF1DAC1_EQ_B5_PG - [15:0] */
+#define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH              16  /* AIF1DAC1_EQ_B5_PG - [15:0] */
+
+/*
+ * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
+ */
+#define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK         0xF800  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT            11  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK         0x07C0  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT             6  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK         0x003E  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT             1  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF1DAC2_EQ_ENA                  0x0001  /* AIF1DAC2_EQ_ENA */
+#define WM8995_AIF1DAC2_EQ_ENA_MASK             0x0001  /* AIF1DAC2_EQ_ENA */
+#define WM8995_AIF1DAC2_EQ_ENA_SHIFT                 0  /* AIF1DAC2_EQ_ENA */
+#define WM8995_AIF1DAC2_EQ_ENA_WIDTH                 1  /* AIF1DAC2_EQ_ENA */
+
+/*
+ * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
+ */
+#define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK         0xF800  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT            11  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK         0x07C0  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+#define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT             6  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+#define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
+ */
+#define WM8995_AIF1DAC2_EQ_B1_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B1_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B1_A_SHIFT                0  /* AIF1DAC2_EQ_B1_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B1_A_WIDTH               16  /* AIF1DAC2_EQ_B1_A - [15:0] */
+
+/*
+ * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
+ */
+#define WM8995_AIF1DAC2_EQ_B1_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B1_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B1_B_SHIFT                0  /* AIF1DAC2_EQ_B1_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B1_B_WIDTH               16  /* AIF1DAC2_EQ_B1_B - [15:0] */
+
+/*
+ * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
+ */
+#define WM8995_AIF1DAC2_EQ_B1_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B1_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT               0  /* AIF1DAC2_EQ_B1_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH              16  /* AIF1DAC2_EQ_B1_PG - [15:0] */
+
+/*
+ * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
+ */
+#define WM8995_AIF1DAC2_EQ_B2_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B2_A_SHIFT                0  /* AIF1DAC2_EQ_B2_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B2_A_WIDTH               16  /* AIF1DAC2_EQ_B2_A - [15:0] */
+
+/*
+ * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
+ */
+#define WM8995_AIF1DAC2_EQ_B2_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B2_B_SHIFT                0  /* AIF1DAC2_EQ_B2_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B2_B_WIDTH               16  /* AIF1DAC2_EQ_B2_B - [15:0] */
+
+/*
+ * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
+ */
+#define WM8995_AIF1DAC2_EQ_B2_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_C - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B2_C_SHIFT                0  /* AIF1DAC2_EQ_B2_C - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B2_C_WIDTH               16  /* AIF1DAC2_EQ_B2_C - [15:0] */
+
+/*
+ * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
+ */
+#define WM8995_AIF1DAC2_EQ_B2_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B2_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT               0  /* AIF1DAC2_EQ_B2_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH              16  /* AIF1DAC2_EQ_B2_PG - [15:0] */
+
+/*
+ * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
+ */
+#define WM8995_AIF1DAC2_EQ_B3_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B3_A_SHIFT                0  /* AIF1DAC2_EQ_B3_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B3_A_WIDTH               16  /* AIF1DAC2_EQ_B3_A - [15:0] */
+
+/*
+ * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
+ */
+#define WM8995_AIF1DAC2_EQ_B3_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B3_B_SHIFT                0  /* AIF1DAC2_EQ_B3_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B3_B_WIDTH               16  /* AIF1DAC2_EQ_B3_B - [15:0] */
+
+/*
+ * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
+ */
+#define WM8995_AIF1DAC2_EQ_B3_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_C - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B3_C_SHIFT                0  /* AIF1DAC2_EQ_B3_C - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B3_C_WIDTH               16  /* AIF1DAC2_EQ_B3_C - [15:0] */
+
+/*
+ * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
+ */
+#define WM8995_AIF1DAC2_EQ_B3_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B3_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT               0  /* AIF1DAC2_EQ_B3_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH              16  /* AIF1DAC2_EQ_B3_PG - [15:0] */
+
+/*
+ * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
+ */
+#define WM8995_AIF1DAC2_EQ_B4_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B4_A_SHIFT                0  /* AIF1DAC2_EQ_B4_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B4_A_WIDTH               16  /* AIF1DAC2_EQ_B4_A - [15:0] */
+
+/*
+ * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
+ */
+#define WM8995_AIF1DAC2_EQ_B4_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B4_B_SHIFT                0  /* AIF1DAC2_EQ_B4_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B4_B_WIDTH               16  /* AIF1DAC2_EQ_B4_B - [15:0] */
+
+/*
+ * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
+ */
+#define WM8995_AIF1DAC2_EQ_B4_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_C - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B4_C_SHIFT                0  /* AIF1DAC2_EQ_B4_C - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B4_C_WIDTH               16  /* AIF1DAC2_EQ_B4_C - [15:0] */
+
+/*
+ * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
+ */
+#define WM8995_AIF1DAC2_EQ_B4_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B4_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT               0  /* AIF1DAC2_EQ_B4_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH              16  /* AIF1DAC2_EQ_B4_PG - [15:0] */
+
+/*
+ * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
+ */
+#define WM8995_AIF1DAC2_EQ_B5_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B5_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B5_A_SHIFT                0  /* AIF1DAC2_EQ_B5_A - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B5_A_WIDTH               16  /* AIF1DAC2_EQ_B5_A - [15:0] */
+
+/*
+ * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
+ */
+#define WM8995_AIF1DAC2_EQ_B5_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B5_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B5_B_SHIFT                0  /* AIF1DAC2_EQ_B5_B - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B5_B_WIDTH               16  /* AIF1DAC2_EQ_B5_B - [15:0] */
+
+/*
+ * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
+ */
+#define WM8995_AIF1DAC2_EQ_B5_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B5_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT               0  /* AIF1DAC2_EQ_B5_PG - [15:0] */
+#define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH              16  /* AIF1DAC2_EQ_B5_PG - [15:0] */
+
+/*
+ * R1280 (0x500) - AIF2 ADC Left Volume
+ */
+#define WM8995_AIF2ADC_VU                       0x0100  /* AIF2ADC_VU */
+#define WM8995_AIF2ADC_VU_MASK                  0x0100  /* AIF2ADC_VU */
+#define WM8995_AIF2ADC_VU_SHIFT                      8  /* AIF2ADC_VU */
+#define WM8995_AIF2ADC_VU_WIDTH                      1  /* AIF2ADC_VU */
+#define WM8995_AIF2ADCL_VOL_MASK                0x00FF  /* AIF2ADCL_VOL - [7:0] */
+#define WM8995_AIF2ADCL_VOL_SHIFT                    0  /* AIF2ADCL_VOL - [7:0] */
+#define WM8995_AIF2ADCL_VOL_WIDTH                    8  /* AIF2ADCL_VOL - [7:0] */
+
+/*
+ * R1281 (0x501) - AIF2 ADC Right Volume
+ */
+#define WM8995_AIF2ADC_VU                       0x0100  /* AIF2ADC_VU */
+#define WM8995_AIF2ADC_VU_MASK                  0x0100  /* AIF2ADC_VU */
+#define WM8995_AIF2ADC_VU_SHIFT                      8  /* AIF2ADC_VU */
+#define WM8995_AIF2ADC_VU_WIDTH                      1  /* AIF2ADC_VU */
+#define WM8995_AIF2ADCR_VOL_MASK                0x00FF  /* AIF2ADCR_VOL - [7:0] */
+#define WM8995_AIF2ADCR_VOL_SHIFT                    0  /* AIF2ADCR_VOL - [7:0] */
+#define WM8995_AIF2ADCR_VOL_WIDTH                    8  /* AIF2ADCR_VOL - [7:0] */
+
+/*
+ * R1282 (0x502) - AIF2 DAC Left Volume
+ */
+#define WM8995_AIF2DAC_VU                       0x0100  /* AIF2DAC_VU */
+#define WM8995_AIF2DAC_VU_MASK                  0x0100  /* AIF2DAC_VU */
+#define WM8995_AIF2DAC_VU_SHIFT                      8  /* AIF2DAC_VU */
+#define WM8995_AIF2DAC_VU_WIDTH                      1  /* AIF2DAC_VU */
+#define WM8995_AIF2DACL_VOL_MASK                0x00FF  /* AIF2DACL_VOL - [7:0] */
+#define WM8995_AIF2DACL_VOL_SHIFT                    0  /* AIF2DACL_VOL - [7:0] */
+#define WM8995_AIF2DACL_VOL_WIDTH                    8  /* AIF2DACL_VOL - [7:0] */
+
+/*
+ * R1283 (0x503) - AIF2 DAC Right Volume
+ */
+#define WM8995_AIF2DAC_VU                       0x0100  /* AIF2DAC_VU */
+#define WM8995_AIF2DAC_VU_MASK                  0x0100  /* AIF2DAC_VU */
+#define WM8995_AIF2DAC_VU_SHIFT                      8  /* AIF2DAC_VU */
+#define WM8995_AIF2DAC_VU_WIDTH                      1  /* AIF2DAC_VU */
+#define WM8995_AIF2DACR_VOL_MASK                0x00FF  /* AIF2DACR_VOL - [7:0] */
+#define WM8995_AIF2DACR_VOL_SHIFT                    0  /* AIF2DACR_VOL - [7:0] */
+#define WM8995_AIF2DACR_VOL_WIDTH                    8  /* AIF2DACR_VOL - [7:0] */
+
+/*
+ * R1296 (0x510) - AIF2 ADC Filters
+ */
+#define WM8995_AIF2ADC_4FS                      0x8000  /* AIF2ADC_4FS */
+#define WM8995_AIF2ADC_4FS_MASK                 0x8000  /* AIF2ADC_4FS */
+#define WM8995_AIF2ADC_4FS_SHIFT                    15  /* AIF2ADC_4FS */
+#define WM8995_AIF2ADC_4FS_WIDTH                     1  /* AIF2ADC_4FS */
+#define WM8995_AIF2ADCL_HPF                     0x1000  /* AIF2ADCL_HPF */
+#define WM8995_AIF2ADCL_HPF_MASK                0x1000  /* AIF2ADCL_HPF */
+#define WM8995_AIF2ADCL_HPF_SHIFT                   12  /* AIF2ADCL_HPF */
+#define WM8995_AIF2ADCL_HPF_WIDTH                    1  /* AIF2ADCL_HPF */
+#define WM8995_AIF2ADCR_HPF                     0x0800  /* AIF2ADCR_HPF */
+#define WM8995_AIF2ADCR_HPF_MASK                0x0800  /* AIF2ADCR_HPF */
+#define WM8995_AIF2ADCR_HPF_SHIFT                   11  /* AIF2ADCR_HPF */
+#define WM8995_AIF2ADCR_HPF_WIDTH                    1  /* AIF2ADCR_HPF */
+#define WM8995_AIF2ADC_HPF_MODE                 0x0008  /* AIF2ADC_HPF_MODE */
+#define WM8995_AIF2ADC_HPF_MODE_MASK            0x0008  /* AIF2ADC_HPF_MODE */
+#define WM8995_AIF2ADC_HPF_MODE_SHIFT                3  /* AIF2ADC_HPF_MODE */
+#define WM8995_AIF2ADC_HPF_MODE_WIDTH                1  /* AIF2ADC_HPF_MODE */
+#define WM8995_AIF2ADC_HPF_CUT_MASK             0x0007  /* AIF2ADC_HPF_CUT - [2:0] */
+#define WM8995_AIF2ADC_HPF_CUT_SHIFT                 0  /* AIF2ADC_HPF_CUT - [2:0] */
+#define WM8995_AIF2ADC_HPF_CUT_WIDTH                 3  /* AIF2ADC_HPF_CUT - [2:0] */
+
+/*
+ * R1312 (0x520) - AIF2 DAC Filters (1)
+ */
+#define WM8995_AIF2DAC_MUTE                     0x0200  /* AIF2DAC_MUTE */
+#define WM8995_AIF2DAC_MUTE_MASK                0x0200  /* AIF2DAC_MUTE */
+#define WM8995_AIF2DAC_MUTE_SHIFT                    9  /* AIF2DAC_MUTE */
+#define WM8995_AIF2DAC_MUTE_WIDTH                    1  /* AIF2DAC_MUTE */
+#define WM8995_AIF2DAC_MONO                     0x0080  /* AIF2DAC_MONO */
+#define WM8995_AIF2DAC_MONO_MASK                0x0080  /* AIF2DAC_MONO */
+#define WM8995_AIF2DAC_MONO_SHIFT                    7  /* AIF2DAC_MONO */
+#define WM8995_AIF2DAC_MONO_WIDTH                    1  /* AIF2DAC_MONO */
+#define WM8995_AIF2DAC_MUTERATE                 0x0020  /* AIF2DAC_MUTERATE */
+#define WM8995_AIF2DAC_MUTERATE_MASK            0x0020  /* AIF2DAC_MUTERATE */
+#define WM8995_AIF2DAC_MUTERATE_SHIFT                5  /* AIF2DAC_MUTERATE */
+#define WM8995_AIF2DAC_MUTERATE_WIDTH                1  /* AIF2DAC_MUTERATE */
+#define WM8995_AIF2DAC_UNMUTE_RAMP              0x0010  /* AIF2DAC_UNMUTE_RAMP */
+#define WM8995_AIF2DAC_UNMUTE_RAMP_MASK         0x0010  /* AIF2DAC_UNMUTE_RAMP */
+#define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT             4  /* AIF2DAC_UNMUTE_RAMP */
+#define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH             1  /* AIF2DAC_UNMUTE_RAMP */
+#define WM8995_AIF2DAC_DEEMP_MASK               0x0006  /* AIF2DAC_DEEMP - [2:1] */
+#define WM8995_AIF2DAC_DEEMP_SHIFT                   1  /* AIF2DAC_DEEMP - [2:1] */
+#define WM8995_AIF2DAC_DEEMP_WIDTH                   2  /* AIF2DAC_DEEMP - [2:1] */
+
+/*
+ * R1313 (0x521) - AIF2 DAC Filters (2)
+ */
+#define WM8995_AIF2DAC_3D_GAIN_MASK             0x3E00  /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8995_AIF2DAC_3D_GAIN_SHIFT                 9  /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8995_AIF2DAC_3D_GAIN_WIDTH                 5  /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8995_AIF2DAC_3D_ENA                   0x0100  /* AIF2DAC_3D_ENA */
+#define WM8995_AIF2DAC_3D_ENA_MASK              0x0100  /* AIF2DAC_3D_ENA */
+#define WM8995_AIF2DAC_3D_ENA_SHIFT                  8  /* AIF2DAC_3D_ENA */
+#define WM8995_AIF2DAC_3D_ENA_WIDTH                  1  /* AIF2DAC_3D_ENA */
+
+/*
+ * R1344 (0x540) - AIF2 DRC (1)
+ */
+#define WM8995_AIF2DRC_SIG_DET_RMS_MASK         0xF800  /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT            11  /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH             5  /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8995_AIF2DRC_SIG_DET_PK_MASK          0x0600  /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8995_AIF2DRC_SIG_DET_PK_SHIFT              9  /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8995_AIF2DRC_SIG_DET_PK_WIDTH              2  /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8995_AIF2DRC_NG_ENA                   0x0100  /* AIF2DRC_NG_ENA */
+#define WM8995_AIF2DRC_NG_ENA_MASK              0x0100  /* AIF2DRC_NG_ENA */
+#define WM8995_AIF2DRC_NG_ENA_SHIFT                  8  /* AIF2DRC_NG_ENA */
+#define WM8995_AIF2DRC_NG_ENA_WIDTH                  1  /* AIF2DRC_NG_ENA */
+#define WM8995_AIF2DRC_SIG_DET_MODE             0x0080  /* AIF2DRC_SIG_DET_MODE */
+#define WM8995_AIF2DRC_SIG_DET_MODE_MASK        0x0080  /* AIF2DRC_SIG_DET_MODE */
+#define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT            7  /* AIF2DRC_SIG_DET_MODE */
+#define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH            1  /* AIF2DRC_SIG_DET_MODE */
+#define WM8995_AIF2DRC_SIG_DET                  0x0040  /* AIF2DRC_SIG_DET */
+#define WM8995_AIF2DRC_SIG_DET_MASK             0x0040  /* AIF2DRC_SIG_DET */
+#define WM8995_AIF2DRC_SIG_DET_SHIFT                 6  /* AIF2DRC_SIG_DET */
+#define WM8995_AIF2DRC_SIG_DET_WIDTH                 1  /* AIF2DRC_SIG_DET */
+#define WM8995_AIF2DRC_KNEE2_OP_ENA             0x0020  /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK        0x0020  /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT            5  /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH            1  /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8995_AIF2DRC_QR                       0x0010  /* AIF2DRC_QR */
+#define WM8995_AIF2DRC_QR_MASK                  0x0010  /* AIF2DRC_QR */
+#define WM8995_AIF2DRC_QR_SHIFT                      4  /* AIF2DRC_QR */
+#define WM8995_AIF2DRC_QR_WIDTH                      1  /* AIF2DRC_QR */
+#define WM8995_AIF2DRC_ANTICLIP                 0x0008  /* AIF2DRC_ANTICLIP */
+#define WM8995_AIF2DRC_ANTICLIP_MASK            0x0008  /* AIF2DRC_ANTICLIP */
+#define WM8995_AIF2DRC_ANTICLIP_SHIFT                3  /* AIF2DRC_ANTICLIP */
+#define WM8995_AIF2DRC_ANTICLIP_WIDTH                1  /* AIF2DRC_ANTICLIP */
+#define WM8995_AIF2DAC_DRC_ENA                  0x0004  /* AIF2DAC_DRC_ENA */
+#define WM8995_AIF2DAC_DRC_ENA_MASK             0x0004  /* AIF2DAC_DRC_ENA */
+#define WM8995_AIF2DAC_DRC_ENA_SHIFT                 2  /* AIF2DAC_DRC_ENA */
+#define WM8995_AIF2DAC_DRC_ENA_WIDTH                 1  /* AIF2DAC_DRC_ENA */
+#define WM8995_AIF2ADCL_DRC_ENA                 0x0002  /* AIF2ADCL_DRC_ENA */
+#define WM8995_AIF2ADCL_DRC_ENA_MASK            0x0002  /* AIF2ADCL_DRC_ENA */
+#define WM8995_AIF2ADCL_DRC_ENA_SHIFT                1  /* AIF2ADCL_DRC_ENA */
+#define WM8995_AIF2ADCL_DRC_ENA_WIDTH                1  /* AIF2ADCL_DRC_ENA */
+#define WM8995_AIF2ADCR_DRC_ENA                 0x0001  /* AIF2ADCR_DRC_ENA */
+#define WM8995_AIF2ADCR_DRC_ENA_MASK            0x0001  /* AIF2ADCR_DRC_ENA */
+#define WM8995_AIF2ADCR_DRC_ENA_SHIFT                0  /* AIF2ADCR_DRC_ENA */
+#define WM8995_AIF2ADCR_DRC_ENA_WIDTH                1  /* AIF2ADCR_DRC_ENA */
+
+/*
+ * R1345 (0x541) - AIF2 DRC (2)
+ */
+#define WM8995_AIF2DRC_ATK_MASK                 0x1E00  /* AIF2DRC_ATK - [12:9] */
+#define WM8995_AIF2DRC_ATK_SHIFT                     9  /* AIF2DRC_ATK - [12:9] */
+#define WM8995_AIF2DRC_ATK_WIDTH                     4  /* AIF2DRC_ATK - [12:9] */
+#define WM8995_AIF2DRC_DCY_MASK                 0x01E0  /* AIF2DRC_DCY - [8:5] */
+#define WM8995_AIF2DRC_DCY_SHIFT                     5  /* AIF2DRC_DCY - [8:5] */
+#define WM8995_AIF2DRC_DCY_WIDTH                     4  /* AIF2DRC_DCY - [8:5] */
+#define WM8995_AIF2DRC_MINGAIN_MASK             0x001C  /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8995_AIF2DRC_MINGAIN_SHIFT                 2  /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8995_AIF2DRC_MINGAIN_WIDTH                 3  /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8995_AIF2DRC_MAXGAIN_MASK             0x0003  /* AIF2DRC_MAXGAIN - [1:0] */
+#define WM8995_AIF2DRC_MAXGAIN_SHIFT                 0  /* AIF2DRC_MAXGAIN - [1:0] */
+#define WM8995_AIF2DRC_MAXGAIN_WIDTH                 2  /* AIF2DRC_MAXGAIN - [1:0] */
+
+/*
+ * R1346 (0x542) - AIF2 DRC (3)
+ */
+#define WM8995_AIF2DRC_NG_MINGAIN_MASK          0xF000  /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8995_AIF2DRC_NG_MINGAIN_SHIFT             12  /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8995_AIF2DRC_NG_MINGAIN_WIDTH              4  /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8995_AIF2DRC_NG_EXP_MASK              0x0C00  /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8995_AIF2DRC_NG_EXP_SHIFT                 10  /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8995_AIF2DRC_NG_EXP_WIDTH                  2  /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8995_AIF2DRC_QR_THR_MASK              0x0300  /* AIF2DRC_QR_THR - [9:8] */
+#define WM8995_AIF2DRC_QR_THR_SHIFT                  8  /* AIF2DRC_QR_THR - [9:8] */
+#define WM8995_AIF2DRC_QR_THR_WIDTH                  2  /* AIF2DRC_QR_THR - [9:8] */
+#define WM8995_AIF2DRC_QR_DCY_MASK              0x00C0  /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8995_AIF2DRC_QR_DCY_SHIFT                  6  /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8995_AIF2DRC_QR_DCY_WIDTH                  2  /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8995_AIF2DRC_HI_COMP_MASK             0x0038  /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8995_AIF2DRC_HI_COMP_SHIFT                 3  /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8995_AIF2DRC_HI_COMP_WIDTH                 3  /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8995_AIF2DRC_LO_COMP_MASK             0x0007  /* AIF2DRC_LO_COMP - [2:0] */
+#define WM8995_AIF2DRC_LO_COMP_SHIFT                 0  /* AIF2DRC_LO_COMP - [2:0] */
+#define WM8995_AIF2DRC_LO_COMP_WIDTH                 3  /* AIF2DRC_LO_COMP - [2:0] */
+
+/*
+ * R1347 (0x543) - AIF2 DRC (4)
+ */
+#define WM8995_AIF2DRC_KNEE_IP_MASK             0x07E0  /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8995_AIF2DRC_KNEE_IP_SHIFT                 5  /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8995_AIF2DRC_KNEE_IP_WIDTH                 6  /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8995_AIF2DRC_KNEE_OP_MASK             0x001F  /* AIF2DRC_KNEE_OP - [4:0] */
+#define WM8995_AIF2DRC_KNEE_OP_SHIFT                 0  /* AIF2DRC_KNEE_OP - [4:0] */
+#define WM8995_AIF2DRC_KNEE_OP_WIDTH                 5  /* AIF2DRC_KNEE_OP - [4:0] */
+
+/*
+ * R1348 (0x544) - AIF2 DRC (5)
+ */
+#define WM8995_AIF2DRC_KNEE2_IP_MASK            0x03E0  /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8995_AIF2DRC_KNEE2_IP_SHIFT                5  /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8995_AIF2DRC_KNEE2_IP_WIDTH                5  /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8995_AIF2DRC_KNEE2_OP_MASK            0x001F  /* AIF2DRC_KNEE2_OP - [4:0] */
+#define WM8995_AIF2DRC_KNEE2_OP_SHIFT                0  /* AIF2DRC_KNEE2_OP - [4:0] */
+#define WM8995_AIF2DRC_KNEE2_OP_WIDTH                5  /* AIF2DRC_KNEE2_OP - [4:0] */
+
+/*
+ * R1408 (0x580) - AIF2 EQ Gains (1)
+ */
+#define WM8995_AIF2DAC_EQ_B1_GAIN_MASK          0xF800  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT             11  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH              5  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8995_AIF2DAC_EQ_B2_GAIN_MASK          0x07C0  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT              6  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH              5  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8995_AIF2DAC_EQ_B3_GAIN_MASK          0x003E  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT              1  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH              5  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8995_AIF2DAC_EQ_ENA                   0x0001  /* AIF2DAC_EQ_ENA */
+#define WM8995_AIF2DAC_EQ_ENA_MASK              0x0001  /* AIF2DAC_EQ_ENA */
+#define WM8995_AIF2DAC_EQ_ENA_SHIFT                  0  /* AIF2DAC_EQ_ENA */
+#define WM8995_AIF2DAC_EQ_ENA_WIDTH                  1  /* AIF2DAC_EQ_ENA */
+
+/*
+ * R1409 (0x581) - AIF2 EQ Gains (2)
+ */
+#define WM8995_AIF2DAC_EQ_B4_GAIN_MASK          0xF800  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT             11  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH              5  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8995_AIF2DAC_EQ_B5_GAIN_MASK          0x07C0  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+#define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT              6  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+#define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH              5  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1410 (0x582) - AIF2 EQ Band 1 A
+ */
+#define WM8995_AIF2DAC_EQ_B1_A_MASK             0xFFFF  /* AIF2DAC_EQ_B1_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B1_A_SHIFT                 0  /* AIF2DAC_EQ_B1_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B1_A_WIDTH                16  /* AIF2DAC_EQ_B1_A - [15:0] */
+
+/*
+ * R1411 (0x583) - AIF2 EQ Band 1 B
+ */
+#define WM8995_AIF2DAC_EQ_B1_B_MASK             0xFFFF  /* AIF2DAC_EQ_B1_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B1_B_SHIFT                 0  /* AIF2DAC_EQ_B1_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B1_B_WIDTH                16  /* AIF2DAC_EQ_B1_B - [15:0] */
+
+/*
+ * R1412 (0x584) - AIF2 EQ Band 1 PG
+ */
+#define WM8995_AIF2DAC_EQ_B1_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B1_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B1_PG_SHIFT                0  /* AIF2DAC_EQ_B1_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B1_PG_WIDTH               16  /* AIF2DAC_EQ_B1_PG - [15:0] */
+
+/*
+ * R1413 (0x585) - AIF2 EQ Band 2 A
+ */
+#define WM8995_AIF2DAC_EQ_B2_A_MASK             0xFFFF  /* AIF2DAC_EQ_B2_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B2_A_SHIFT                 0  /* AIF2DAC_EQ_B2_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B2_A_WIDTH                16  /* AIF2DAC_EQ_B2_A - [15:0] */
+
+/*
+ * R1414 (0x586) - AIF2 EQ Band 2 B
+ */
+#define WM8995_AIF2DAC_EQ_B2_B_MASK             0xFFFF  /* AIF2DAC_EQ_B2_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B2_B_SHIFT                 0  /* AIF2DAC_EQ_B2_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B2_B_WIDTH                16  /* AIF2DAC_EQ_B2_B - [15:0] */
+
+/*
+ * R1415 (0x587) - AIF2 EQ Band 2 C
+ */
+#define WM8995_AIF2DAC_EQ_B2_C_MASK             0xFFFF  /* AIF2DAC_EQ_B2_C - [15:0] */
+#define WM8995_AIF2DAC_EQ_B2_C_SHIFT                 0  /* AIF2DAC_EQ_B2_C - [15:0] */
+#define WM8995_AIF2DAC_EQ_B2_C_WIDTH                16  /* AIF2DAC_EQ_B2_C - [15:0] */
+
+/*
+ * R1416 (0x588) - AIF2 EQ Band 2 PG
+ */
+#define WM8995_AIF2DAC_EQ_B2_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B2_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B2_PG_SHIFT                0  /* AIF2DAC_EQ_B2_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B2_PG_WIDTH               16  /* AIF2DAC_EQ_B2_PG - [15:0] */
+
+/*
+ * R1417 (0x589) - AIF2 EQ Band 3 A
+ */
+#define WM8995_AIF2DAC_EQ_B3_A_MASK             0xFFFF  /* AIF2DAC_EQ_B3_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B3_A_SHIFT                 0  /* AIF2DAC_EQ_B3_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B3_A_WIDTH                16  /* AIF2DAC_EQ_B3_A - [15:0] */
+
+/*
+ * R1418 (0x58A) - AIF2 EQ Band 3 B
+ */
+#define WM8995_AIF2DAC_EQ_B3_B_MASK             0xFFFF  /* AIF2DAC_EQ_B3_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B3_B_SHIFT                 0  /* AIF2DAC_EQ_B3_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B3_B_WIDTH                16  /* AIF2DAC_EQ_B3_B - [15:0] */
+
+/*
+ * R1419 (0x58B) - AIF2 EQ Band 3 C
+ */
+#define WM8995_AIF2DAC_EQ_B3_C_MASK             0xFFFF  /* AIF2DAC_EQ_B3_C - [15:0] */
+#define WM8995_AIF2DAC_EQ_B3_C_SHIFT                 0  /* AIF2DAC_EQ_B3_C - [15:0] */
+#define WM8995_AIF2DAC_EQ_B3_C_WIDTH                16  /* AIF2DAC_EQ_B3_C - [15:0] */
+
+/*
+ * R1420 (0x58C) - AIF2 EQ Band 3 PG
+ */
+#define WM8995_AIF2DAC_EQ_B3_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B3_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B3_PG_SHIFT                0  /* AIF2DAC_EQ_B3_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B3_PG_WIDTH               16  /* AIF2DAC_EQ_B3_PG - [15:0] */
+
+/*
+ * R1421 (0x58D) - AIF2 EQ Band 4 A
+ */
+#define WM8995_AIF2DAC_EQ_B4_A_MASK             0xFFFF  /* AIF2DAC_EQ_B4_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B4_A_SHIFT                 0  /* AIF2DAC_EQ_B4_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B4_A_WIDTH                16  /* AIF2DAC_EQ_B4_A - [15:0] */
+
+/*
+ * R1422 (0x58E) - AIF2 EQ Band 4 B
+ */
+#define WM8995_AIF2DAC_EQ_B4_B_MASK             0xFFFF  /* AIF2DAC_EQ_B4_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B4_B_SHIFT                 0  /* AIF2DAC_EQ_B4_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B4_B_WIDTH                16  /* AIF2DAC_EQ_B4_B - [15:0] */
+
+/*
+ * R1423 (0x58F) - AIF2 EQ Band 4 C
+ */
+#define WM8995_AIF2DAC_EQ_B4_C_MASK             0xFFFF  /* AIF2DAC_EQ_B4_C - [15:0] */
+#define WM8995_AIF2DAC_EQ_B4_C_SHIFT                 0  /* AIF2DAC_EQ_B4_C - [15:0] */
+#define WM8995_AIF2DAC_EQ_B4_C_WIDTH                16  /* AIF2DAC_EQ_B4_C - [15:0] */
+
+/*
+ * R1424 (0x590) - AIF2 EQ Band 4 PG
+ */
+#define WM8995_AIF2DAC_EQ_B4_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B4_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B4_PG_SHIFT                0  /* AIF2DAC_EQ_B4_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B4_PG_WIDTH               16  /* AIF2DAC_EQ_B4_PG - [15:0] */
+
+/*
+ * R1425 (0x591) - AIF2 EQ Band 5 A
+ */
+#define WM8995_AIF2DAC_EQ_B5_A_MASK             0xFFFF  /* AIF2DAC_EQ_B5_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B5_A_SHIFT                 0  /* AIF2DAC_EQ_B5_A - [15:0] */
+#define WM8995_AIF2DAC_EQ_B5_A_WIDTH                16  /* AIF2DAC_EQ_B5_A - [15:0] */
+
+/*
+ * R1426 (0x592) - AIF2 EQ Band 5 B
+ */
+#define WM8995_AIF2DAC_EQ_B5_B_MASK             0xFFFF  /* AIF2DAC_EQ_B5_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B5_B_SHIFT                 0  /* AIF2DAC_EQ_B5_B - [15:0] */
+#define WM8995_AIF2DAC_EQ_B5_B_WIDTH                16  /* AIF2DAC_EQ_B5_B - [15:0] */
+
+/*
+ * R1427 (0x593) - AIF2 EQ Band 5 PG
+ */
+#define WM8995_AIF2DAC_EQ_B5_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B5_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B5_PG_SHIFT                0  /* AIF2DAC_EQ_B5_PG - [15:0] */
+#define WM8995_AIF2DAC_EQ_B5_PG_WIDTH               16  /* AIF2DAC_EQ_B5_PG - [15:0] */
+
+/*
+ * R1536 (0x600) - DAC1 Mixer Volumes
+ */
+#define WM8995_ADCR_DAC1_VOL_MASK               0x03E0  /* ADCR_DAC1_VOL - [9:5] */
+#define WM8995_ADCR_DAC1_VOL_SHIFT                   5  /* ADCR_DAC1_VOL - [9:5] */
+#define WM8995_ADCR_DAC1_VOL_WIDTH                   5  /* ADCR_DAC1_VOL - [9:5] */
+#define WM8995_ADCL_DAC1_VOL_MASK               0x001F  /* ADCL_DAC1_VOL - [4:0] */
+#define WM8995_ADCL_DAC1_VOL_SHIFT                   0  /* ADCL_DAC1_VOL - [4:0] */
+#define WM8995_ADCL_DAC1_VOL_WIDTH                   5  /* ADCL_DAC1_VOL - [4:0] */
+
+/*
+ * R1537 (0x601) - DAC1 Left Mixer Routing
+ */
+#define WM8995_ADCR_TO_DAC1L                    0x0020  /* ADCR_TO_DAC1L */
+#define WM8995_ADCR_TO_DAC1L_MASK               0x0020  /* ADCR_TO_DAC1L */
+#define WM8995_ADCR_TO_DAC1L_SHIFT                   5  /* ADCR_TO_DAC1L */
+#define WM8995_ADCR_TO_DAC1L_WIDTH                   1  /* ADCR_TO_DAC1L */
+#define WM8995_ADCL_TO_DAC1L                    0x0010  /* ADCL_TO_DAC1L */
+#define WM8995_ADCL_TO_DAC1L_MASK               0x0010  /* ADCL_TO_DAC1L */
+#define WM8995_ADCL_TO_DAC1L_SHIFT                   4  /* ADCL_TO_DAC1L */
+#define WM8995_ADCL_TO_DAC1L_WIDTH                   1  /* ADCL_TO_DAC1L */
+#define WM8995_AIF2DACL_TO_DAC1L                0x0004  /* AIF2DACL_TO_DAC1L */
+#define WM8995_AIF2DACL_TO_DAC1L_MASK           0x0004  /* AIF2DACL_TO_DAC1L */
+#define WM8995_AIF2DACL_TO_DAC1L_SHIFT               2  /* AIF2DACL_TO_DAC1L */
+#define WM8995_AIF2DACL_TO_DAC1L_WIDTH               1  /* AIF2DACL_TO_DAC1L */
+#define WM8995_AIF1DAC2L_TO_DAC1L               0x0002  /* AIF1DAC2L_TO_DAC1L */
+#define WM8995_AIF1DAC2L_TO_DAC1L_MASK          0x0002  /* AIF1DAC2L_TO_DAC1L */
+#define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT              1  /* AIF1DAC2L_TO_DAC1L */
+#define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH              1  /* AIF1DAC2L_TO_DAC1L */
+#define WM8995_AIF1DAC1L_TO_DAC1L               0x0001  /* AIF1DAC1L_TO_DAC1L */
+#define WM8995_AIF1DAC1L_TO_DAC1L_MASK          0x0001  /* AIF1DAC1L_TO_DAC1L */
+#define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT              0  /* AIF1DAC1L_TO_DAC1L */
+#define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH              1  /* AIF1DAC1L_TO_DAC1L */
+
+/*
+ * R1538 (0x602) - DAC1 Right Mixer Routing
+ */
+#define WM8995_ADCR_TO_DAC1R                    0x0020  /* ADCR_TO_DAC1R */
+#define WM8995_ADCR_TO_DAC1R_MASK               0x0020  /* ADCR_TO_DAC1R */
+#define WM8995_ADCR_TO_DAC1R_SHIFT                   5  /* ADCR_TO_DAC1R */
+#define WM8995_ADCR_TO_DAC1R_WIDTH                   1  /* ADCR_TO_DAC1R */
+#define WM8995_ADCL_TO_DAC1R                    0x0010  /* ADCL_TO_DAC1R */
+#define WM8995_ADCL_TO_DAC1R_MASK               0x0010  /* ADCL_TO_DAC1R */
+#define WM8995_ADCL_TO_DAC1R_SHIFT                   4  /* ADCL_TO_DAC1R */
+#define WM8995_ADCL_TO_DAC1R_WIDTH                   1  /* ADCL_TO_DAC1R */
+#define WM8995_AIF2DACR_TO_DAC1R                0x0004  /* AIF2DACR_TO_DAC1R */
+#define WM8995_AIF2DACR_TO_DAC1R_MASK           0x0004  /* AIF2DACR_TO_DAC1R */
+#define WM8995_AIF2DACR_TO_DAC1R_SHIFT               2  /* AIF2DACR_TO_DAC1R */
+#define WM8995_AIF2DACR_TO_DAC1R_WIDTH               1  /* AIF2DACR_TO_DAC1R */
+#define WM8995_AIF1DAC2R_TO_DAC1R               0x0002  /* AIF1DAC2R_TO_DAC1R */
+#define WM8995_AIF1DAC2R_TO_DAC1R_MASK          0x0002  /* AIF1DAC2R_TO_DAC1R */
+#define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT              1  /* AIF1DAC2R_TO_DAC1R */
+#define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH              1  /* AIF1DAC2R_TO_DAC1R */
+#define WM8995_AIF1DAC1R_TO_DAC1R               0x0001  /* AIF1DAC1R_TO_DAC1R */
+#define WM8995_AIF1DAC1R_TO_DAC1R_MASK          0x0001  /* AIF1DAC1R_TO_DAC1R */
+#define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT              0  /* AIF1DAC1R_TO_DAC1R */
+#define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH              1  /* AIF1DAC1R_TO_DAC1R */
+
+/*
+ * R1539 (0x603) - DAC2 Mixer Volumes
+ */
+#define WM8995_ADCR_DAC2_VOL_MASK               0x03E0  /* ADCR_DAC2_VOL - [9:5] */
+#define WM8995_ADCR_DAC2_VOL_SHIFT                   5  /* ADCR_DAC2_VOL - [9:5] */
+#define WM8995_ADCR_DAC2_VOL_WIDTH                   5  /* ADCR_DAC2_VOL - [9:5] */
+#define WM8995_ADCL_DAC2_VOL_MASK               0x001F  /* ADCL_DAC2_VOL - [4:0] */
+#define WM8995_ADCL_DAC2_VOL_SHIFT                   0  /* ADCL_DAC2_VOL - [4:0] */
+#define WM8995_ADCL_DAC2_VOL_WIDTH                   5  /* ADCL_DAC2_VOL - [4:0] */
+
+/*
+ * R1540 (0x604) - DAC2 Left Mixer Routing
+ */
+#define WM8995_ADCR_TO_DAC2L                    0x0020  /* ADCR_TO_DAC2L */
+#define WM8995_ADCR_TO_DAC2L_MASK               0x0020  /* ADCR_TO_DAC2L */
+#define WM8995_ADCR_TO_DAC2L_SHIFT                   5  /* ADCR_TO_DAC2L */
+#define WM8995_ADCR_TO_DAC2L_WIDTH                   1  /* ADCR_TO_DAC2L */
+#define WM8995_ADCL_TO_DAC2L                    0x0010  /* ADCL_TO_DAC2L */
+#define WM8995_ADCL_TO_DAC2L_MASK               0x0010  /* ADCL_TO_DAC2L */
+#define WM8995_ADCL_TO_DAC2L_SHIFT                   4  /* ADCL_TO_DAC2L */
+#define WM8995_ADCL_TO_DAC2L_WIDTH                   1  /* ADCL_TO_DAC2L */
+#define WM8995_AIF2DACL_TO_DAC2L                0x0004  /* AIF2DACL_TO_DAC2L */
+#define WM8995_AIF2DACL_TO_DAC2L_MASK           0x0004  /* AIF2DACL_TO_DAC2L */
+#define WM8995_AIF2DACL_TO_DAC2L_SHIFT               2  /* AIF2DACL_TO_DAC2L */
+#define WM8995_AIF2DACL_TO_DAC2L_WIDTH               1  /* AIF2DACL_TO_DAC2L */
+#define WM8995_AIF1DAC2L_TO_DAC2L               0x0002  /* AIF1DAC2L_TO_DAC2L */
+#define WM8995_AIF1DAC2L_TO_DAC2L_MASK          0x0002  /* AIF1DAC2L_TO_DAC2L */
+#define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT              1  /* AIF1DAC2L_TO_DAC2L */
+#define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH              1  /* AIF1DAC2L_TO_DAC2L */
+#define WM8995_AIF1DAC1L_TO_DAC2L               0x0001  /* AIF1DAC1L_TO_DAC2L */
+#define WM8995_AIF1DAC1L_TO_DAC2L_MASK          0x0001  /* AIF1DAC1L_TO_DAC2L */
+#define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT              0  /* AIF1DAC1L_TO_DAC2L */
+#define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH              1  /* AIF1DAC1L_TO_DAC2L */
+
+/*
+ * R1541 (0x605) - DAC2 Right Mixer Routing
+ */
+#define WM8995_ADCR_TO_DAC2R                    0x0020  /* ADCR_TO_DAC2R */
+#define WM8995_ADCR_TO_DAC2R_MASK               0x0020  /* ADCR_TO_DAC2R */
+#define WM8995_ADCR_TO_DAC2R_SHIFT                   5  /* ADCR_TO_DAC2R */
+#define WM8995_ADCR_TO_DAC2R_WIDTH                   1  /* ADCR_TO_DAC2R */
+#define WM8995_ADCL_TO_DAC2R                    0x0010  /* ADCL_TO_DAC2R */
+#define WM8995_ADCL_TO_DAC2R_MASK               0x0010  /* ADCL_TO_DAC2R */
+#define WM8995_ADCL_TO_DAC2R_SHIFT                   4  /* ADCL_TO_DAC2R */
+#define WM8995_ADCL_TO_DAC2R_WIDTH                   1  /* ADCL_TO_DAC2R */
+#define WM8995_AIF2DACR_TO_DAC2R                0x0004  /* AIF2DACR_TO_DAC2R */
+#define WM8995_AIF2DACR_TO_DAC2R_MASK           0x0004  /* AIF2DACR_TO_DAC2R */
+#define WM8995_AIF2DACR_TO_DAC2R_SHIFT               2  /* AIF2DACR_TO_DAC2R */
+#define WM8995_AIF2DACR_TO_DAC2R_WIDTH               1  /* AIF2DACR_TO_DAC2R */
+#define WM8995_AIF1DAC2R_TO_DAC2R               0x0002  /* AIF1DAC2R_TO_DAC2R */
+#define WM8995_AIF1DAC2R_TO_DAC2R_MASK          0x0002  /* AIF1DAC2R_TO_DAC2R */
+#define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT              1  /* AIF1DAC2R_TO_DAC2R */
+#define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH              1  /* AIF1DAC2R_TO_DAC2R */
+#define WM8995_AIF1DAC1R_TO_DAC2R               0x0001  /* AIF1DAC1R_TO_DAC2R */
+#define WM8995_AIF1DAC1R_TO_DAC2R_MASK          0x0001  /* AIF1DAC1R_TO_DAC2R */
+#define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT              0  /* AIF1DAC1R_TO_DAC2R */
+#define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH              1  /* AIF1DAC1R_TO_DAC2R */
+
+/*
+ * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
+ */
+#define WM8995_ADC1L_TO_AIF1ADC1L               0x0002  /* ADC1L_TO_AIF1ADC1L */
+#define WM8995_ADC1L_TO_AIF1ADC1L_MASK          0x0002  /* ADC1L_TO_AIF1ADC1L */
+#define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT              1  /* ADC1L_TO_AIF1ADC1L */
+#define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH              1  /* ADC1L_TO_AIF1ADC1L */
+#define WM8995_AIF2DACL_TO_AIF1ADC1L            0x0001  /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK       0x0001  /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT           0  /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH           1  /* AIF2DACL_TO_AIF1ADC1L */
+
+/*
+ * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
+ */
+#define WM8995_ADC1R_TO_AIF1ADC1R               0x0002  /* ADC1R_TO_AIF1ADC1R */
+#define WM8995_ADC1R_TO_AIF1ADC1R_MASK          0x0002  /* ADC1R_TO_AIF1ADC1R */
+#define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT              1  /* ADC1R_TO_AIF1ADC1R */
+#define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH              1  /* ADC1R_TO_AIF1ADC1R */
+#define WM8995_AIF2DACR_TO_AIF1ADC1R            0x0001  /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK       0x0001  /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT           0  /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH           1  /* AIF2DACR_TO_AIF1ADC1R */
+
+/*
+ * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
+ */
+#define WM8995_ADC2L_TO_AIF1ADC2L               0x0002  /* ADC2L_TO_AIF1ADC2L */
+#define WM8995_ADC2L_TO_AIF1ADC2L_MASK          0x0002  /* ADC2L_TO_AIF1ADC2L */
+#define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT              1  /* ADC2L_TO_AIF1ADC2L */
+#define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH              1  /* ADC2L_TO_AIF1ADC2L */
+#define WM8995_AIF2DACL_TO_AIF1ADC2L            0x0001  /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK       0x0001  /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT           0  /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH           1  /* AIF2DACL_TO_AIF1ADC2L */
+
+/*
+ * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
+ */
+#define WM8995_ADC2R_TO_AIF1ADC2R               0x0002  /* ADC2R_TO_AIF1ADC2R */
+#define WM8995_ADC2R_TO_AIF1ADC2R_MASK          0x0002  /* ADC2R_TO_AIF1ADC2R */
+#define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT              1  /* ADC2R_TO_AIF1ADC2R */
+#define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH              1  /* ADC2R_TO_AIF1ADC2R */
+#define WM8995_AIF2DACR_TO_AIF1ADC2R            0x0001  /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK       0x0001  /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT           0  /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH           1  /* AIF2DACR_TO_AIF1ADC2R */
+
+/*
+ * R1552 (0x610) - DAC Softmute
+ */
+#define WM8995_DAC_SOFTMUTEMODE                 0x0002  /* DAC_SOFTMUTEMODE */
+#define WM8995_DAC_SOFTMUTEMODE_MASK            0x0002  /* DAC_SOFTMUTEMODE */
+#define WM8995_DAC_SOFTMUTEMODE_SHIFT                1  /* DAC_SOFTMUTEMODE */
+#define WM8995_DAC_SOFTMUTEMODE_WIDTH                1  /* DAC_SOFTMUTEMODE */
+#define WM8995_DAC_MUTERATE                     0x0001  /* DAC_MUTERATE */
+#define WM8995_DAC_MUTERATE_MASK                0x0001  /* DAC_MUTERATE */
+#define WM8995_DAC_MUTERATE_SHIFT                    0  /* DAC_MUTERATE */
+#define WM8995_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
+
+/*
+ * R1568 (0x620) - Oversampling
+ */
+#define WM8995_ADC_OSR128                       0x0002  /* ADC_OSR128 */
+#define WM8995_ADC_OSR128_MASK                  0x0002  /* ADC_OSR128 */
+#define WM8995_ADC_OSR128_SHIFT                      1  /* ADC_OSR128 */
+#define WM8995_ADC_OSR128_WIDTH                      1  /* ADC_OSR128 */
+#define WM8995_DAC_OSR128                       0x0001  /* DAC_OSR128 */
+#define WM8995_DAC_OSR128_MASK                  0x0001  /* DAC_OSR128 */
+#define WM8995_DAC_OSR128_SHIFT                      0  /* DAC_OSR128 */
+#define WM8995_DAC_OSR128_WIDTH                      1  /* DAC_OSR128 */
+
+/*
+ * R1569 (0x621) - Sidetone
+ */
+#define WM8995_ST_LPF                           0x1000  /* ST_LPF */
+#define WM8995_ST_LPF_MASK                      0x1000  /* ST_LPF */
+#define WM8995_ST_LPF_SHIFT                         12  /* ST_LPF */
+#define WM8995_ST_LPF_WIDTH                          1  /* ST_LPF */
+#define WM8995_ST_HPF_CUT_MASK                  0x0380  /* ST_HPF_CUT - [9:7] */
+#define WM8995_ST_HPF_CUT_SHIFT                      7  /* ST_HPF_CUT - [9:7] */
+#define WM8995_ST_HPF_CUT_WIDTH                      3  /* ST_HPF_CUT - [9:7] */
+#define WM8995_ST_HPF                           0x0040  /* ST_HPF */
+#define WM8995_ST_HPF_MASK                      0x0040  /* ST_HPF */
+#define WM8995_ST_HPF_SHIFT                          6  /* ST_HPF */
+#define WM8995_ST_HPF_WIDTH                          1  /* ST_HPF */
+#define WM8995_STR_SEL                          0x0002  /* STR_SEL */
+#define WM8995_STR_SEL_MASK                     0x0002  /* STR_SEL */
+#define WM8995_STR_SEL_SHIFT                         1  /* STR_SEL */
+#define WM8995_STR_SEL_WIDTH                         1  /* STR_SEL */
+#define WM8995_STL_SEL                          0x0001  /* STL_SEL */
+#define WM8995_STL_SEL_MASK                     0x0001  /* STL_SEL */
+#define WM8995_STL_SEL_SHIFT                         0  /* STL_SEL */
+#define WM8995_STL_SEL_WIDTH                         1  /* STL_SEL */
+
+/*
+ * R1792 (0x700) - GPIO 1
+ */
+#define WM8995_GP1_DIR                          0x8000  /* GP1_DIR */
+#define WM8995_GP1_DIR_MASK                     0x8000  /* GP1_DIR */
+#define WM8995_GP1_DIR_SHIFT                        15  /* GP1_DIR */
+#define WM8995_GP1_DIR_WIDTH                         1  /* GP1_DIR */
+#define WM8995_GP1_PU                           0x4000  /* GP1_PU */
+#define WM8995_GP1_PU_MASK                      0x4000  /* GP1_PU */
+#define WM8995_GP1_PU_SHIFT                         14  /* GP1_PU */
+#define WM8995_GP1_PU_WIDTH                          1  /* GP1_PU */
+#define WM8995_GP1_PD                           0x2000  /* GP1_PD */
+#define WM8995_GP1_PD_MASK                      0x2000  /* GP1_PD */
+#define WM8995_GP1_PD_SHIFT                         13  /* GP1_PD */
+#define WM8995_GP1_PD_WIDTH                          1  /* GP1_PD */
+#define WM8995_GP1_POL                          0x0400  /* GP1_POL */
+#define WM8995_GP1_POL_MASK                     0x0400  /* GP1_POL */
+#define WM8995_GP1_POL_SHIFT                        10  /* GP1_POL */
+#define WM8995_GP1_POL_WIDTH                         1  /* GP1_POL */
+#define WM8995_GP1_OP_CFG                       0x0200  /* GP1_OP_CFG */
+#define WM8995_GP1_OP_CFG_MASK                  0x0200  /* GP1_OP_CFG */
+#define WM8995_GP1_OP_CFG_SHIFT                      9  /* GP1_OP_CFG */
+#define WM8995_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
+#define WM8995_GP1_DB                           0x0100  /* GP1_DB */
+#define WM8995_GP1_DB_MASK                      0x0100  /* GP1_DB */
+#define WM8995_GP1_DB_SHIFT                          8  /* GP1_DB */
+#define WM8995_GP1_DB_WIDTH                          1  /* GP1_DB */
+#define WM8995_GP1_LVL                          0x0040  /* GP1_LVL */
+#define WM8995_GP1_LVL_MASK                     0x0040  /* GP1_LVL */
+#define WM8995_GP1_LVL_SHIFT                         6  /* GP1_LVL */
+#define WM8995_GP1_LVL_WIDTH                         1  /* GP1_LVL */
+#define WM8995_GP1_FN_MASK                      0x001F  /* GP1_FN - [4:0] */
+#define WM8995_GP1_FN_SHIFT                          0  /* GP1_FN - [4:0] */
+#define WM8995_GP1_FN_WIDTH                          5  /* GP1_FN - [4:0] */
+
+/*
+ * R1793 (0x701) - GPIO 2
+ */
+#define WM8995_GP2_DIR                          0x8000  /* GP2_DIR */
+#define WM8995_GP2_DIR_MASK                     0x8000  /* GP2_DIR */
+#define WM8995_GP2_DIR_SHIFT                        15  /* GP2_DIR */
+#define WM8995_GP2_DIR_WIDTH                         1  /* GP2_DIR */
+#define WM8995_GP2_PU                           0x4000  /* GP2_PU */
+#define WM8995_GP2_PU_MASK                      0x4000  /* GP2_PU */
+#define WM8995_GP2_PU_SHIFT                         14  /* GP2_PU */
+#define WM8995_GP2_PU_WIDTH                          1  /* GP2_PU */
+#define WM8995_GP2_PD                           0x2000  /* GP2_PD */
+#define WM8995_GP2_PD_MASK                      0x2000  /* GP2_PD */
+#define WM8995_GP2_PD_SHIFT                         13  /* GP2_PD */
+#define WM8995_GP2_PD_WIDTH                          1  /* GP2_PD */
+#define WM8995_GP2_POL                          0x0400  /* GP2_POL */
+#define WM8995_GP2_POL_MASK                     0x0400  /* GP2_POL */
+#define WM8995_GP2_POL_SHIFT                        10  /* GP2_POL */
+#define WM8995_GP2_POL_WIDTH                         1  /* GP2_POL */
+#define WM8995_GP2_OP_CFG                       0x0200  /* GP2_OP_CFG */
+#define WM8995_GP2_OP_CFG_MASK                  0x0200  /* GP2_OP_CFG */
+#define WM8995_GP2_OP_CFG_SHIFT                      9  /* GP2_OP_CFG */
+#define WM8995_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
+#define WM8995_GP2_DB                           0x0100  /* GP2_DB */
+#define WM8995_GP2_DB_MASK                      0x0100  /* GP2_DB */
+#define WM8995_GP2_DB_SHIFT                          8  /* GP2_DB */
+#define WM8995_GP2_DB_WIDTH                          1  /* GP2_DB */
+#define WM8995_GP2_LVL                          0x0040  /* GP2_LVL */
+#define WM8995_GP2_LVL_MASK                     0x0040  /* GP2_LVL */
+#define WM8995_GP2_LVL_SHIFT                         6  /* GP2_LVL */
+#define WM8995_GP2_LVL_WIDTH                         1  /* GP2_LVL */
+#define WM8995_GP2_FN_MASK                      0x001F  /* GP2_FN - [4:0] */
+#define WM8995_GP2_FN_SHIFT                          0  /* GP2_FN - [4:0] */
+#define WM8995_GP2_FN_WIDTH                          5  /* GP2_FN - [4:0] */
+
+/*
+ * R1794 (0x702) - GPIO 3
+ */
+#define WM8995_GP3_DIR                          0x8000  /* GP3_DIR */
+#define WM8995_GP3_DIR_MASK                     0x8000  /* GP3_DIR */
+#define WM8995_GP3_DIR_SHIFT                        15  /* GP3_DIR */
+#define WM8995_GP3_DIR_WIDTH                         1  /* GP3_DIR */
+#define WM8995_GP3_PU                           0x4000  /* GP3_PU */
+#define WM8995_GP3_PU_MASK                      0x4000  /* GP3_PU */
+#define WM8995_GP3_PU_SHIFT                         14  /* GP3_PU */
+#define WM8995_GP3_PU_WIDTH                          1  /* GP3_PU */
+#define WM8995_GP3_PD                           0x2000  /* GP3_PD */
+#define WM8995_GP3_PD_MASK                      0x2000  /* GP3_PD */
+#define WM8995_GP3_PD_SHIFT                         13  /* GP3_PD */
+#define WM8995_GP3_PD_WIDTH                          1  /* GP3_PD */
+#define WM8995_GP3_POL                          0x0400  /* GP3_POL */
+#define WM8995_GP3_POL_MASK                     0x0400  /* GP3_POL */
+#define WM8995_GP3_POL_SHIFT                        10  /* GP3_POL */
+#define WM8995_GP3_POL_WIDTH                         1  /* GP3_POL */
+#define WM8995_GP3_OP_CFG                       0x0200  /* GP3_OP_CFG */
+#define WM8995_GP3_OP_CFG_MASK                  0x0200  /* GP3_OP_CFG */
+#define WM8995_GP3_OP_CFG_SHIFT                      9  /* GP3_OP_CFG */
+#define WM8995_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
+#define WM8995_GP3_DB                           0x0100  /* GP3_DB */
+#define WM8995_GP3_DB_MASK                      0x0100  /* GP3_DB */
+#define WM8995_GP3_DB_SHIFT                          8  /* GP3_DB */
+#define WM8995_GP3_DB_WIDTH                          1  /* GP3_DB */
+#define WM8995_GP3_LVL                          0x0040  /* GP3_LVL */
+#define WM8995_GP3_LVL_MASK                     0x0040  /* GP3_LVL */
+#define WM8995_GP3_LVL_SHIFT                         6  /* GP3_LVL */
+#define WM8995_GP3_LVL_WIDTH                         1  /* GP3_LVL */
+#define WM8995_GP3_FN_MASK                      0x001F  /* GP3_FN - [4:0] */
+#define WM8995_GP3_FN_SHIFT                          0  /* GP3_FN - [4:0] */
+#define WM8995_GP3_FN_WIDTH                          5  /* GP3_FN - [4:0] */
+
+/*
+ * R1795 (0x703) - GPIO 4
+ */
+#define WM8995_GP4_DIR                          0x8000  /* GP4_DIR */
+#define WM8995_GP4_DIR_MASK                     0x8000  /* GP4_DIR */
+#define WM8995_GP4_DIR_SHIFT                        15  /* GP4_DIR */
+#define WM8995_GP4_DIR_WIDTH                         1  /* GP4_DIR */
+#define WM8995_GP4_PU                           0x4000  /* GP4_PU */
+#define WM8995_GP4_PU_MASK                      0x4000  /* GP4_PU */
+#define WM8995_GP4_PU_SHIFT                         14  /* GP4_PU */
+#define WM8995_GP4_PU_WIDTH                          1  /* GP4_PU */
+#define WM8995_GP4_PD                           0x2000  /* GP4_PD */
+#define WM8995_GP4_PD_MASK                      0x2000  /* GP4_PD */
+#define WM8995_GP4_PD_SHIFT                         13  /* GP4_PD */
+#define WM8995_GP4_PD_WIDTH                          1  /* GP4_PD */
+#define WM8995_GP4_POL                          0x0400  /* GP4_POL */
+#define WM8995_GP4_POL_MASK                     0x0400  /* GP4_POL */
+#define WM8995_GP4_POL_SHIFT                        10  /* GP4_POL */
+#define WM8995_GP4_POL_WIDTH                         1  /* GP4_POL */
+#define WM8995_GP4_OP_CFG                       0x0200  /* GP4_OP_CFG */
+#define WM8995_GP4_OP_CFG_MASK                  0x0200  /* GP4_OP_CFG */
+#define WM8995_GP4_OP_CFG_SHIFT                      9  /* GP4_OP_CFG */
+#define WM8995_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
+#define WM8995_GP4_DB                           0x0100  /* GP4_DB */
+#define WM8995_GP4_DB_MASK                      0x0100  /* GP4_DB */
+#define WM8995_GP4_DB_SHIFT                          8  /* GP4_DB */
+#define WM8995_GP4_DB_WIDTH                          1  /* GP4_DB */
+#define WM8995_GP4_LVL                          0x0040  /* GP4_LVL */
+#define WM8995_GP4_LVL_MASK                     0x0040  /* GP4_LVL */
+#define WM8995_GP4_LVL_SHIFT                         6  /* GP4_LVL */
+#define WM8995_GP4_LVL_WIDTH                         1  /* GP4_LVL */
+#define WM8995_GP4_FN_MASK                      0x001F  /* GP4_FN - [4:0] */
+#define WM8995_GP4_FN_SHIFT                          0  /* GP4_FN - [4:0] */
+#define WM8995_GP4_FN_WIDTH                          5  /* GP4_FN - [4:0] */
+
+/*
+ * R1796 (0x704) - GPIO 5
+ */
+#define WM8995_GP5_DIR                          0x8000  /* GP5_DIR */
+#define WM8995_GP5_DIR_MASK                     0x8000  /* GP5_DIR */
+#define WM8995_GP5_DIR_SHIFT                        15  /* GP5_DIR */
+#define WM8995_GP5_DIR_WIDTH                         1  /* GP5_DIR */
+#define WM8995_GP5_PU                           0x4000  /* GP5_PU */
+#define WM8995_GP5_PU_MASK                      0x4000  /* GP5_PU */
+#define WM8995_GP5_PU_SHIFT                         14  /* GP5_PU */
+#define WM8995_GP5_PU_WIDTH                          1  /* GP5_PU */
+#define WM8995_GP5_PD                           0x2000  /* GP5_PD */
+#define WM8995_GP5_PD_MASK                      0x2000  /* GP5_PD */
+#define WM8995_GP5_PD_SHIFT                         13  /* GP5_PD */
+#define WM8995_GP5_PD_WIDTH                          1  /* GP5_PD */
+#define WM8995_GP5_POL                          0x0400  /* GP5_POL */
+#define WM8995_GP5_POL_MASK                     0x0400  /* GP5_POL */
+#define WM8995_GP5_POL_SHIFT                        10  /* GP5_POL */
+#define WM8995_GP5_POL_WIDTH                         1  /* GP5_POL */
+#define WM8995_GP5_OP_CFG                       0x0200  /* GP5_OP_CFG */
+#define WM8995_GP5_OP_CFG_MASK                  0x0200  /* GP5_OP_CFG */
+#define WM8995_GP5_OP_CFG_SHIFT                      9  /* GP5_OP_CFG */
+#define WM8995_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
+#define WM8995_GP5_DB                           0x0100  /* GP5_DB */
+#define WM8995_GP5_DB_MASK                      0x0100  /* GP5_DB */
+#define WM8995_GP5_DB_SHIFT                          8  /* GP5_DB */
+#define WM8995_GP5_DB_WIDTH                          1  /* GP5_DB */
+#define WM8995_GP5_LVL                          0x0040  /* GP5_LVL */
+#define WM8995_GP5_LVL_MASK                     0x0040  /* GP5_LVL */
+#define WM8995_GP5_LVL_SHIFT                         6  /* GP5_LVL */
+#define WM8995_GP5_LVL_WIDTH                         1  /* GP5_LVL */
+#define WM8995_GP5_FN_MASK                      0x001F  /* GP5_FN - [4:0] */
+#define WM8995_GP5_FN_SHIFT                          0  /* GP5_FN - [4:0] */
+#define WM8995_GP5_FN_WIDTH                          5  /* GP5_FN - [4:0] */
+
+/*
+ * R1797 (0x705) - GPIO 6
+ */
+#define WM8995_GP6_DIR                          0x8000  /* GP6_DIR */
+#define WM8995_GP6_DIR_MASK                     0x8000  /* GP6_DIR */
+#define WM8995_GP6_DIR_SHIFT                        15  /* GP6_DIR */
+#define WM8995_GP6_DIR_WIDTH                         1  /* GP6_DIR */
+#define WM8995_GP6_PU                           0x4000  /* GP6_PU */
+#define WM8995_GP6_PU_MASK                      0x4000  /* GP6_PU */
+#define WM8995_GP6_PU_SHIFT                         14  /* GP6_PU */
+#define WM8995_GP6_PU_WIDTH                          1  /* GP6_PU */
+#define WM8995_GP6_PD                           0x2000  /* GP6_PD */
+#define WM8995_GP6_PD_MASK                      0x2000  /* GP6_PD */
+#define WM8995_GP6_PD_SHIFT                         13  /* GP6_PD */
+#define WM8995_GP6_PD_WIDTH                          1  /* GP6_PD */
+#define WM8995_GP6_POL                          0x0400  /* GP6_POL */
+#define WM8995_GP6_POL_MASK                     0x0400  /* GP6_POL */
+#define WM8995_GP6_POL_SHIFT                        10  /* GP6_POL */
+#define WM8995_GP6_POL_WIDTH                         1  /* GP6_POL */
+#define WM8995_GP6_OP_CFG                       0x0200  /* GP6_OP_CFG */
+#define WM8995_GP6_OP_CFG_MASK                  0x0200  /* GP6_OP_CFG */
+#define WM8995_GP6_OP_CFG_SHIFT                      9  /* GP6_OP_CFG */
+#define WM8995_GP6_OP_CFG_WIDTH                      1  /* GP6_OP_CFG */
+#define WM8995_GP6_DB                           0x0100  /* GP6_DB */
+#define WM8995_GP6_DB_MASK                      0x0100  /* GP6_DB */
+#define WM8995_GP6_DB_SHIFT                          8  /* GP6_DB */
+#define WM8995_GP6_DB_WIDTH                          1  /* GP6_DB */
+#define WM8995_GP6_LVL                          0x0040  /* GP6_LVL */
+#define WM8995_GP6_LVL_MASK                     0x0040  /* GP6_LVL */
+#define WM8995_GP6_LVL_SHIFT                         6  /* GP6_LVL */
+#define WM8995_GP6_LVL_WIDTH                         1  /* GP6_LVL */
+#define WM8995_GP6_FN_MASK                      0x001F  /* GP6_FN - [4:0] */
+#define WM8995_GP6_FN_SHIFT                          0  /* GP6_FN - [4:0] */
+#define WM8995_GP6_FN_WIDTH                          5  /* GP6_FN - [4:0] */
+
+/*
+ * R1798 (0x706) - GPIO 7
+ */
+#define WM8995_GP7_DIR                          0x8000  /* GP7_DIR */
+#define WM8995_GP7_DIR_MASK                     0x8000  /* GP7_DIR */
+#define WM8995_GP7_DIR_SHIFT                        15  /* GP7_DIR */
+#define WM8995_GP7_DIR_WIDTH                         1  /* GP7_DIR */
+#define WM8995_GP7_PU                           0x4000  /* GP7_PU */
+#define WM8995_GP7_PU_MASK                      0x4000  /* GP7_PU */
+#define WM8995_GP7_PU_SHIFT                         14  /* GP7_PU */
+#define WM8995_GP7_PU_WIDTH                          1  /* GP7_PU */
+#define WM8995_GP7_PD                           0x2000  /* GP7_PD */
+#define WM8995_GP7_PD_MASK                      0x2000  /* GP7_PD */
+#define WM8995_GP7_PD_SHIFT                         13  /* GP7_PD */
+#define WM8995_GP7_PD_WIDTH                          1  /* GP7_PD */
+#define WM8995_GP7_POL                          0x0400  /* GP7_POL */
+#define WM8995_GP7_POL_MASK                     0x0400  /* GP7_POL */
+#define WM8995_GP7_POL_SHIFT                        10  /* GP7_POL */
+#define WM8995_GP7_POL_WIDTH                         1  /* GP7_POL */
+#define WM8995_GP7_OP_CFG                       0x0200  /* GP7_OP_CFG */
+#define WM8995_GP7_OP_CFG_MASK                  0x0200  /* GP7_OP_CFG */
+#define WM8995_GP7_OP_CFG_SHIFT                      9  /* GP7_OP_CFG */
+#define WM8995_GP7_OP_CFG_WIDTH                      1  /* GP7_OP_CFG */
+#define WM8995_GP7_DB                           0x0100  /* GP7_DB */
+#define WM8995_GP7_DB_MASK                      0x0100  /* GP7_DB */
+#define WM8995_GP7_DB_SHIFT                          8  /* GP7_DB */
+#define WM8995_GP7_DB_WIDTH                          1  /* GP7_DB */
+#define WM8995_GP7_LVL                          0x0040  /* GP7_LVL */
+#define WM8995_GP7_LVL_MASK                     0x0040  /* GP7_LVL */
+#define WM8995_GP7_LVL_SHIFT                         6  /* GP7_LVL */
+#define WM8995_GP7_LVL_WIDTH                         1  /* GP7_LVL */
+#define WM8995_GP7_FN_MASK                      0x001F  /* GP7_FN - [4:0] */
+#define WM8995_GP7_FN_SHIFT                          0  /* GP7_FN - [4:0] */
+#define WM8995_GP7_FN_WIDTH                          5  /* GP7_FN - [4:0] */
+
+/*
+ * R1799 (0x707) - GPIO 8
+ */
+#define WM8995_GP8_DIR                          0x8000  /* GP8_DIR */
+#define WM8995_GP8_DIR_MASK                     0x8000  /* GP8_DIR */
+#define WM8995_GP8_DIR_SHIFT                        15  /* GP8_DIR */
+#define WM8995_GP8_DIR_WIDTH                         1  /* GP8_DIR */
+#define WM8995_GP8_PU                           0x4000  /* GP8_PU */
+#define WM8995_GP8_PU_MASK                      0x4000  /* GP8_PU */
+#define WM8995_GP8_PU_SHIFT                         14  /* GP8_PU */
+#define WM8995_GP8_PU_WIDTH                          1  /* GP8_PU */
+#define WM8995_GP8_PD                           0x2000  /* GP8_PD */
+#define WM8995_GP8_PD_MASK                      0x2000  /* GP8_PD */
+#define WM8995_GP8_PD_SHIFT                         13  /* GP8_PD */
+#define WM8995_GP8_PD_WIDTH                          1  /* GP8_PD */
+#define WM8995_GP8_POL                          0x0400  /* GP8_POL */
+#define WM8995_GP8_POL_MASK                     0x0400  /* GP8_POL */
+#define WM8995_GP8_POL_SHIFT                        10  /* GP8_POL */
+#define WM8995_GP8_POL_WIDTH                         1  /* GP8_POL */
+#define WM8995_GP8_OP_CFG                       0x0200  /* GP8_OP_CFG */
+#define WM8995_GP8_OP_CFG_MASK                  0x0200  /* GP8_OP_CFG */
+#define WM8995_GP8_OP_CFG_SHIFT                      9  /* GP8_OP_CFG */
+#define WM8995_GP8_OP_CFG_WIDTH                      1  /* GP8_OP_CFG */
+#define WM8995_GP8_DB                           0x0100  /* GP8_DB */
+#define WM8995_GP8_DB_MASK                      0x0100  /* GP8_DB */
+#define WM8995_GP8_DB_SHIFT                          8  /* GP8_DB */
+#define WM8995_GP8_DB_WIDTH                          1  /* GP8_DB */
+#define WM8995_GP8_LVL                          0x0040  /* GP8_LVL */
+#define WM8995_GP8_LVL_MASK                     0x0040  /* GP8_LVL */
+#define WM8995_GP8_LVL_SHIFT                         6  /* GP8_LVL */
+#define WM8995_GP8_LVL_WIDTH                         1  /* GP8_LVL */
+#define WM8995_GP8_FN_MASK                      0x001F  /* GP8_FN - [4:0] */
+#define WM8995_GP8_FN_SHIFT                          0  /* GP8_FN - [4:0] */
+#define WM8995_GP8_FN_WIDTH                          5  /* GP8_FN - [4:0] */
+
+/*
+ * R1800 (0x708) - GPIO 9
+ */
+#define WM8995_GP9_DIR                          0x8000  /* GP9_DIR */
+#define WM8995_GP9_DIR_MASK                     0x8000  /* GP9_DIR */
+#define WM8995_GP9_DIR_SHIFT                        15  /* GP9_DIR */
+#define WM8995_GP9_DIR_WIDTH                         1  /* GP9_DIR */
+#define WM8995_GP9_PU                           0x4000  /* GP9_PU */
+#define WM8995_GP9_PU_MASK                      0x4000  /* GP9_PU */
+#define WM8995_GP9_PU_SHIFT                         14  /* GP9_PU */
+#define WM8995_GP9_PU_WIDTH                          1  /* GP9_PU */
+#define WM8995_GP9_PD                           0x2000  /* GP9_PD */
+#define WM8995_GP9_PD_MASK                      0x2000  /* GP9_PD */
+#define WM8995_GP9_PD_SHIFT                         13  /* GP9_PD */
+#define WM8995_GP9_PD_WIDTH                          1  /* GP9_PD */
+#define WM8995_GP9_POL                          0x0400  /* GP9_POL */
+#define WM8995_GP9_POL_MASK                     0x0400  /* GP9_POL */
+#define WM8995_GP9_POL_SHIFT                        10  /* GP9_POL */
+#define WM8995_GP9_POL_WIDTH                         1  /* GP9_POL */
+#define WM8995_GP9_OP_CFG                       0x0200  /* GP9_OP_CFG */
+#define WM8995_GP9_OP_CFG_MASK                  0x0200  /* GP9_OP_CFG */
+#define WM8995_GP9_OP_CFG_SHIFT                      9  /* GP9_OP_CFG */
+#define WM8995_GP9_OP_CFG_WIDTH                      1  /* GP9_OP_CFG */
+#define WM8995_GP9_DB                           0x0100  /* GP9_DB */
+#define WM8995_GP9_DB_MASK                      0x0100  /* GP9_DB */
+#define WM8995_GP9_DB_SHIFT                          8  /* GP9_DB */
+#define WM8995_GP9_DB_WIDTH                          1  /* GP9_DB */
+#define WM8995_GP9_LVL                          0x0040  /* GP9_LVL */
+#define WM8995_GP9_LVL_MASK                     0x0040  /* GP9_LVL */
+#define WM8995_GP9_LVL_SHIFT                         6  /* GP9_LVL */
+#define WM8995_GP9_LVL_WIDTH                         1  /* GP9_LVL */
+#define WM8995_GP9_FN_MASK                      0x001F  /* GP9_FN - [4:0] */
+#define WM8995_GP9_FN_SHIFT                          0  /* GP9_FN - [4:0] */
+#define WM8995_GP9_FN_WIDTH                          5  /* GP9_FN - [4:0] */
+
+/*
+ * R1801 (0x709) - GPIO 10
+ */
+#define WM8995_GP10_DIR                         0x8000  /* GP10_DIR */
+#define WM8995_GP10_DIR_MASK                    0x8000  /* GP10_DIR */
+#define WM8995_GP10_DIR_SHIFT                       15  /* GP10_DIR */
+#define WM8995_GP10_DIR_WIDTH                        1  /* GP10_DIR */
+#define WM8995_GP10_PU                          0x4000  /* GP10_PU */
+#define WM8995_GP10_PU_MASK                     0x4000  /* GP10_PU */
+#define WM8995_GP10_PU_SHIFT                        14  /* GP10_PU */
+#define WM8995_GP10_PU_WIDTH                         1  /* GP10_PU */
+#define WM8995_GP10_PD                          0x2000  /* GP10_PD */
+#define WM8995_GP10_PD_MASK                     0x2000  /* GP10_PD */
+#define WM8995_GP10_PD_SHIFT                        13  /* GP10_PD */
+#define WM8995_GP10_PD_WIDTH                         1  /* GP10_PD */
+#define WM8995_GP10_POL                         0x0400  /* GP10_POL */
+#define WM8995_GP10_POL_MASK                    0x0400  /* GP10_POL */
+#define WM8995_GP10_POL_SHIFT                       10  /* GP10_POL */
+#define WM8995_GP10_POL_WIDTH                        1  /* GP10_POL */
+#define WM8995_GP10_OP_CFG                      0x0200  /* GP10_OP_CFG */
+#define WM8995_GP10_OP_CFG_MASK                 0x0200  /* GP10_OP_CFG */
+#define WM8995_GP10_OP_CFG_SHIFT                     9  /* GP10_OP_CFG */
+#define WM8995_GP10_OP_CFG_WIDTH                     1  /* GP10_OP_CFG */
+#define WM8995_GP10_DB                          0x0100  /* GP10_DB */
+#define WM8995_GP10_DB_MASK                     0x0100  /* GP10_DB */
+#define WM8995_GP10_DB_SHIFT                         8  /* GP10_DB */
+#define WM8995_GP10_DB_WIDTH                         1  /* GP10_DB */
+#define WM8995_GP10_LVL                         0x0040  /* GP10_LVL */
+#define WM8995_GP10_LVL_MASK                    0x0040  /* GP10_LVL */
+#define WM8995_GP10_LVL_SHIFT                        6  /* GP10_LVL */
+#define WM8995_GP10_LVL_WIDTH                        1  /* GP10_LVL */
+#define WM8995_GP10_FN_MASK                     0x001F  /* GP10_FN - [4:0] */
+#define WM8995_GP10_FN_SHIFT                         0  /* GP10_FN - [4:0] */
+#define WM8995_GP10_FN_WIDTH                         5  /* GP10_FN - [4:0] */
+
+/*
+ * R1802 (0x70A) - GPIO 11
+ */
+#define WM8995_GP11_DIR                         0x8000  /* GP11_DIR */
+#define WM8995_GP11_DIR_MASK                    0x8000  /* GP11_DIR */
+#define WM8995_GP11_DIR_SHIFT                       15  /* GP11_DIR */
+#define WM8995_GP11_DIR_WIDTH                        1  /* GP11_DIR */
+#define WM8995_GP11_PU                          0x4000  /* GP11_PU */
+#define WM8995_GP11_PU_MASK                     0x4000  /* GP11_PU */
+#define WM8995_GP11_PU_SHIFT                        14  /* GP11_PU */
+#define WM8995_GP11_PU_WIDTH                         1  /* GP11_PU */
+#define WM8995_GP11_PD                          0x2000  /* GP11_PD */
+#define WM8995_GP11_PD_MASK                     0x2000  /* GP11_PD */
+#define WM8995_GP11_PD_SHIFT                        13  /* GP11_PD */
+#define WM8995_GP11_PD_WIDTH                         1  /* GP11_PD */
+#define WM8995_GP11_POL                         0x0400  /* GP11_POL */
+#define WM8995_GP11_POL_MASK                    0x0400  /* GP11_POL */
+#define WM8995_GP11_POL_SHIFT                       10  /* GP11_POL */
+#define WM8995_GP11_POL_WIDTH                        1  /* GP11_POL */
+#define WM8995_GP11_OP_CFG                      0x0200  /* GP11_OP_CFG */
+#define WM8995_GP11_OP_CFG_MASK                 0x0200  /* GP11_OP_CFG */
+#define WM8995_GP11_OP_CFG_SHIFT                     9  /* GP11_OP_CFG */
+#define WM8995_GP11_OP_CFG_WIDTH                     1  /* GP11_OP_CFG */
+#define WM8995_GP11_DB                          0x0100  /* GP11_DB */
+#define WM8995_GP11_DB_MASK                     0x0100  /* GP11_DB */
+#define WM8995_GP11_DB_SHIFT                         8  /* GP11_DB */
+#define WM8995_GP11_DB_WIDTH                         1  /* GP11_DB */
+#define WM8995_GP11_LVL                         0x0040  /* GP11_LVL */
+#define WM8995_GP11_LVL_MASK                    0x0040  /* GP11_LVL */
+#define WM8995_GP11_LVL_SHIFT                        6  /* GP11_LVL */
+#define WM8995_GP11_LVL_WIDTH                        1  /* GP11_LVL */
+#define WM8995_GP11_FN_MASK                     0x001F  /* GP11_FN - [4:0] */
+#define WM8995_GP11_FN_SHIFT                         0  /* GP11_FN - [4:0] */
+#define WM8995_GP11_FN_WIDTH                         5  /* GP11_FN - [4:0] */
+
+/*
+ * R1803 (0x70B) - GPIO 12
+ */
+#define WM8995_GP12_DIR                         0x8000  /* GP12_DIR */
+#define WM8995_GP12_DIR_MASK                    0x8000  /* GP12_DIR */
+#define WM8995_GP12_DIR_SHIFT                       15  /* GP12_DIR */
+#define WM8995_GP12_DIR_WIDTH                        1  /* GP12_DIR */
+#define WM8995_GP12_PU                          0x4000  /* GP12_PU */
+#define WM8995_GP12_PU_MASK                     0x4000  /* GP12_PU */
+#define WM8995_GP12_PU_SHIFT                        14  /* GP12_PU */
+#define WM8995_GP12_PU_WIDTH                         1  /* GP12_PU */
+#define WM8995_GP12_PD                          0x2000  /* GP12_PD */
+#define WM8995_GP12_PD_MASK                     0x2000  /* GP12_PD */
+#define WM8995_GP12_PD_SHIFT                        13  /* GP12_PD */
+#define WM8995_GP12_PD_WIDTH                         1  /* GP12_PD */
+#define WM8995_GP12_POL                         0x0400  /* GP12_POL */
+#define WM8995_GP12_POL_MASK                    0x0400  /* GP12_POL */
+#define WM8995_GP12_POL_SHIFT                       10  /* GP12_POL */
+#define WM8995_GP12_POL_WIDTH                        1  /* GP12_POL */
+#define WM8995_GP12_OP_CFG                      0x0200  /* GP12_OP_CFG */
+#define WM8995_GP12_OP_CFG_MASK                 0x0200  /* GP12_OP_CFG */
+#define WM8995_GP12_OP_CFG_SHIFT                     9  /* GP12_OP_CFG */
+#define WM8995_GP12_OP_CFG_WIDTH                     1  /* GP12_OP_CFG */
+#define WM8995_GP12_DB                          0x0100  /* GP12_DB */
+#define WM8995_GP12_DB_MASK                     0x0100  /* GP12_DB */
+#define WM8995_GP12_DB_SHIFT                         8  /* GP12_DB */
+#define WM8995_GP12_DB_WIDTH                         1  /* GP12_DB */
+#define WM8995_GP12_LVL                         0x0040  /* GP12_LVL */
+#define WM8995_GP12_LVL_MASK                    0x0040  /* GP12_LVL */
+#define WM8995_GP12_LVL_SHIFT                        6  /* GP12_LVL */
+#define WM8995_GP12_LVL_WIDTH                        1  /* GP12_LVL */
+#define WM8995_GP12_FN_MASK                     0x001F  /* GP12_FN - [4:0] */
+#define WM8995_GP12_FN_SHIFT                         0  /* GP12_FN - [4:0] */
+#define WM8995_GP12_FN_WIDTH                         5  /* GP12_FN - [4:0] */
+
+/*
+ * R1804 (0x70C) - GPIO 13
+ */
+#define WM8995_GP13_DIR                         0x8000  /* GP13_DIR */
+#define WM8995_GP13_DIR_MASK                    0x8000  /* GP13_DIR */
+#define WM8995_GP13_DIR_SHIFT                       15  /* GP13_DIR */
+#define WM8995_GP13_DIR_WIDTH                        1  /* GP13_DIR */
+#define WM8995_GP13_PU                          0x4000  /* GP13_PU */
+#define WM8995_GP13_PU_MASK                     0x4000  /* GP13_PU */
+#define WM8995_GP13_PU_SHIFT                        14  /* GP13_PU */
+#define WM8995_GP13_PU_WIDTH                         1  /* GP13_PU */
+#define WM8995_GP13_PD                          0x2000  /* GP13_PD */
+#define WM8995_GP13_PD_MASK                     0x2000  /* GP13_PD */
+#define WM8995_GP13_PD_SHIFT                        13  /* GP13_PD */
+#define WM8995_GP13_PD_WIDTH                         1  /* GP13_PD */
+#define WM8995_GP13_POL                         0x0400  /* GP13_POL */
+#define WM8995_GP13_POL_MASK                    0x0400  /* GP13_POL */
+#define WM8995_GP13_POL_SHIFT                       10  /* GP13_POL */
+#define WM8995_GP13_POL_WIDTH                        1  /* GP13_POL */
+#define WM8995_GP13_OP_CFG                      0x0200  /* GP13_OP_CFG */
+#define WM8995_GP13_OP_CFG_MASK                 0x0200  /* GP13_OP_CFG */
+#define WM8995_GP13_OP_CFG_SHIFT                     9  /* GP13_OP_CFG */
+#define WM8995_GP13_OP_CFG_WIDTH                     1  /* GP13_OP_CFG */
+#define WM8995_GP13_DB                          0x0100  /* GP13_DB */
+#define WM8995_GP13_DB_MASK                     0x0100  /* GP13_DB */
+#define WM8995_GP13_DB_SHIFT                         8  /* GP13_DB */
+#define WM8995_GP13_DB_WIDTH                         1  /* GP13_DB */
+#define WM8995_GP13_LVL                         0x0040  /* GP13_LVL */
+#define WM8995_GP13_LVL_MASK                    0x0040  /* GP13_LVL */
+#define WM8995_GP13_LVL_SHIFT                        6  /* GP13_LVL */
+#define WM8995_GP13_LVL_WIDTH                        1  /* GP13_LVL */
+#define WM8995_GP13_FN_MASK                     0x001F  /* GP13_FN - [4:0] */
+#define WM8995_GP13_FN_SHIFT                         0  /* GP13_FN - [4:0] */
+#define WM8995_GP13_FN_WIDTH                         5  /* GP13_FN - [4:0] */
+
+/*
+ * R1805 (0x70D) - GPIO 14
+ */
+#define WM8995_GP14_DIR                         0x8000  /* GP14_DIR */
+#define WM8995_GP14_DIR_MASK                    0x8000  /* GP14_DIR */
+#define WM8995_GP14_DIR_SHIFT                       15  /* GP14_DIR */
+#define WM8995_GP14_DIR_WIDTH                        1  /* GP14_DIR */
+#define WM8995_GP14_PU                          0x4000  /* GP14_PU */
+#define WM8995_GP14_PU_MASK                     0x4000  /* GP14_PU */
+#define WM8995_GP14_PU_SHIFT                        14  /* GP14_PU */
+#define WM8995_GP14_PU_WIDTH                         1  /* GP14_PU */
+#define WM8995_GP14_PD                          0x2000  /* GP14_PD */
+#define WM8995_GP14_PD_MASK                     0x2000  /* GP14_PD */
+#define WM8995_GP14_PD_SHIFT                        13  /* GP14_PD */
+#define WM8995_GP14_PD_WIDTH                         1  /* GP14_PD */
+#define WM8995_GP14_POL                         0x0400  /* GP14_POL */
+#define WM8995_GP14_POL_MASK                    0x0400  /* GP14_POL */
+#define WM8995_GP14_POL_SHIFT                       10  /* GP14_POL */
+#define WM8995_GP14_POL_WIDTH                        1  /* GP14_POL */
+#define WM8995_GP14_OP_CFG                      0x0200  /* GP14_OP_CFG */
+#define WM8995_GP14_OP_CFG_MASK                 0x0200  /* GP14_OP_CFG */
+#define WM8995_GP14_OP_CFG_SHIFT                     9  /* GP14_OP_CFG */
+#define WM8995_GP14_OP_CFG_WIDTH                     1  /* GP14_OP_CFG */
+#define WM8995_GP14_DB                          0x0100  /* GP14_DB */
+#define WM8995_GP14_DB_MASK                     0x0100  /* GP14_DB */
+#define WM8995_GP14_DB_SHIFT                         8  /* GP14_DB */
+#define WM8995_GP14_DB_WIDTH                         1  /* GP14_DB */
+#define WM8995_GP14_LVL                         0x0040  /* GP14_LVL */
+#define WM8995_GP14_LVL_MASK                    0x0040  /* GP14_LVL */
+#define WM8995_GP14_LVL_SHIFT                        6  /* GP14_LVL */
+#define WM8995_GP14_LVL_WIDTH                        1  /* GP14_LVL */
+#define WM8995_GP14_FN_MASK                     0x001F  /* GP14_FN - [4:0] */
+#define WM8995_GP14_FN_SHIFT                         0  /* GP14_FN - [4:0] */
+#define WM8995_GP14_FN_WIDTH                         5  /* GP14_FN - [4:0] */
+
+/*
+ * R1824 (0x720) - Pull Control (1)
+ */
+#define WM8995_DMICDAT3_PD                      0x4000  /* DMICDAT3_PD */
+#define WM8995_DMICDAT3_PD_MASK                 0x4000  /* DMICDAT3_PD */
+#define WM8995_DMICDAT3_PD_SHIFT                    14  /* DMICDAT3_PD */
+#define WM8995_DMICDAT3_PD_WIDTH                     1  /* DMICDAT3_PD */
+#define WM8995_DMICDAT2_PD                      0x1000  /* DMICDAT2_PD */
+#define WM8995_DMICDAT2_PD_MASK                 0x1000  /* DMICDAT2_PD */
+#define WM8995_DMICDAT2_PD_SHIFT                    12  /* DMICDAT2_PD */
+#define WM8995_DMICDAT2_PD_WIDTH                     1  /* DMICDAT2_PD */
+#define WM8995_DMICDAT1_PD                      0x0400  /* DMICDAT1_PD */
+#define WM8995_DMICDAT1_PD_MASK                 0x0400  /* DMICDAT1_PD */
+#define WM8995_DMICDAT1_PD_SHIFT                    10  /* DMICDAT1_PD */
+#define WM8995_DMICDAT1_PD_WIDTH                     1  /* DMICDAT1_PD */
+#define WM8995_MCLK2_PU                         0x0200  /* MCLK2_PU */
+#define WM8995_MCLK2_PU_MASK                    0x0200  /* MCLK2_PU */
+#define WM8995_MCLK2_PU_SHIFT                        9  /* MCLK2_PU */
+#define WM8995_MCLK2_PU_WIDTH                        1  /* MCLK2_PU */
+#define WM8995_MCLK2_PD                         0x0100  /* MCLK2_PD */
+#define WM8995_MCLK2_PD_MASK                    0x0100  /* MCLK2_PD */
+#define WM8995_MCLK2_PD_SHIFT                        8  /* MCLK2_PD */
+#define WM8995_MCLK2_PD_WIDTH                        1  /* MCLK2_PD */
+#define WM8995_MCLK1_PU                         0x0080  /* MCLK1_PU */
+#define WM8995_MCLK1_PU_MASK                    0x0080  /* MCLK1_PU */
+#define WM8995_MCLK1_PU_SHIFT                        7  /* MCLK1_PU */
+#define WM8995_MCLK1_PU_WIDTH                        1  /* MCLK1_PU */
+#define WM8995_MCLK1_PD                         0x0040  /* MCLK1_PD */
+#define WM8995_MCLK1_PD_MASK                    0x0040  /* MCLK1_PD */
+#define WM8995_MCLK1_PD_SHIFT                        6  /* MCLK1_PD */
+#define WM8995_MCLK1_PD_WIDTH                        1  /* MCLK1_PD */
+#define WM8995_DACDAT1_PU                       0x0020  /* DACDAT1_PU */
+#define WM8995_DACDAT1_PU_MASK                  0x0020  /* DACDAT1_PU */
+#define WM8995_DACDAT1_PU_SHIFT                      5  /* DACDAT1_PU */
+#define WM8995_DACDAT1_PU_WIDTH                      1  /* DACDAT1_PU */
+#define WM8995_DACDAT1_PD                       0x0010  /* DACDAT1_PD */
+#define WM8995_DACDAT1_PD_MASK                  0x0010  /* DACDAT1_PD */
+#define WM8995_DACDAT1_PD_SHIFT                      4  /* DACDAT1_PD */
+#define WM8995_DACDAT1_PD_WIDTH                      1  /* DACDAT1_PD */
+#define WM8995_DACLRCLK1_PU                     0x0008  /* DACLRCLK1_PU */
+#define WM8995_DACLRCLK1_PU_MASK                0x0008  /* DACLRCLK1_PU */
+#define WM8995_DACLRCLK1_PU_SHIFT                    3  /* DACLRCLK1_PU */
+#define WM8995_DACLRCLK1_PU_WIDTH                    1  /* DACLRCLK1_PU */
+#define WM8995_DACLRCLK1_PD                     0x0004  /* DACLRCLK1_PD */
+#define WM8995_DACLRCLK1_PD_MASK                0x0004  /* DACLRCLK1_PD */
+#define WM8995_DACLRCLK1_PD_SHIFT                    2  /* DACLRCLK1_PD */
+#define WM8995_DACLRCLK1_PD_WIDTH                    1  /* DACLRCLK1_PD */
+#define WM8995_BCLK1_PU                         0x0002  /* BCLK1_PU */
+#define WM8995_BCLK1_PU_MASK                    0x0002  /* BCLK1_PU */
+#define WM8995_BCLK1_PU_SHIFT                        1  /* BCLK1_PU */
+#define WM8995_BCLK1_PU_WIDTH                        1  /* BCLK1_PU */
+#define WM8995_BCLK1_PD                         0x0001  /* BCLK1_PD */
+#define WM8995_BCLK1_PD_MASK                    0x0001  /* BCLK1_PD */
+#define WM8995_BCLK1_PD_SHIFT                        0  /* BCLK1_PD */
+#define WM8995_BCLK1_PD_WIDTH                        1  /* BCLK1_PD */
+
+/*
+ * R1825 (0x721) - Pull Control (2)
+ */
+#define WM8995_LDO1ENA_PD                       0x0010  /* LDO1ENA_PD */
+#define WM8995_LDO1ENA_PD_MASK                  0x0010  /* LDO1ENA_PD */
+#define WM8995_LDO1ENA_PD_SHIFT                      4  /* LDO1ENA_PD */
+#define WM8995_LDO1ENA_PD_WIDTH                      1  /* LDO1ENA_PD */
+#define WM8995_MODE_PD                          0x0004  /* MODE_PD */
+#define WM8995_MODE_PD_MASK                     0x0004  /* MODE_PD */
+#define WM8995_MODE_PD_SHIFT                         2  /* MODE_PD */
+#define WM8995_MODE_PD_WIDTH                         1  /* MODE_PD */
+#define WM8995_CSNADDR_PD                       0x0001  /* CSNADDR_PD */
+#define WM8995_CSNADDR_PD_MASK                  0x0001  /* CSNADDR_PD */
+#define WM8995_CSNADDR_PD_SHIFT                      0  /* CSNADDR_PD */
+#define WM8995_CSNADDR_PD_WIDTH                      1  /* CSNADDR_PD */
+
+/*
+ * R1840 (0x730) - Interrupt Status 1
+ */
+#define WM8995_GP14_EINT                        0x2000  /* GP14_EINT */
+#define WM8995_GP14_EINT_MASK                   0x2000  /* GP14_EINT */
+#define WM8995_GP14_EINT_SHIFT                      13  /* GP14_EINT */
+#define WM8995_GP14_EINT_WIDTH                       1  /* GP14_EINT */
+#define WM8995_GP13_EINT                        0x1000  /* GP13_EINT */
+#define WM8995_GP13_EINT_MASK                   0x1000  /* GP13_EINT */
+#define WM8995_GP13_EINT_SHIFT                      12  /* GP13_EINT */
+#define WM8995_GP13_EINT_WIDTH                       1  /* GP13_EINT */
+#define WM8995_GP12_EINT                        0x0800  /* GP12_EINT */
+#define WM8995_GP12_EINT_MASK                   0x0800  /* GP12_EINT */
+#define WM8995_GP12_EINT_SHIFT                      11  /* GP12_EINT */
+#define WM8995_GP12_EINT_WIDTH                       1  /* GP12_EINT */
+#define WM8995_GP11_EINT                        0x0400  /* GP11_EINT */
+#define WM8995_GP11_EINT_MASK                   0x0400  /* GP11_EINT */
+#define WM8995_GP11_EINT_SHIFT                      10  /* GP11_EINT */
+#define WM8995_GP11_EINT_WIDTH                       1  /* GP11_EINT */
+#define WM8995_GP10_EINT                        0x0200  /* GP10_EINT */
+#define WM8995_GP10_EINT_MASK                   0x0200  /* GP10_EINT */
+#define WM8995_GP10_EINT_SHIFT                       9  /* GP10_EINT */
+#define WM8995_GP10_EINT_WIDTH                       1  /* GP10_EINT */
+#define WM8995_GP9_EINT                         0x0100  /* GP9_EINT */
+#define WM8995_GP9_EINT_MASK                    0x0100  /* GP9_EINT */
+#define WM8995_GP9_EINT_SHIFT                        8  /* GP9_EINT */
+#define WM8995_GP9_EINT_WIDTH                        1  /* GP9_EINT */
+#define WM8995_GP8_EINT                         0x0080  /* GP8_EINT */
+#define WM8995_GP8_EINT_MASK                    0x0080  /* GP8_EINT */
+#define WM8995_GP8_EINT_SHIFT                        7  /* GP8_EINT */
+#define WM8995_GP8_EINT_WIDTH                        1  /* GP8_EINT */
+#define WM8995_GP7_EINT                         0x0040  /* GP7_EINT */
+#define WM8995_GP7_EINT_MASK                    0x0040  /* GP7_EINT */
+#define WM8995_GP7_EINT_SHIFT                        6  /* GP7_EINT */
+#define WM8995_GP7_EINT_WIDTH                        1  /* GP7_EINT */
+#define WM8995_GP6_EINT                         0x0020  /* GP6_EINT */
+#define WM8995_GP6_EINT_MASK                    0x0020  /* GP6_EINT */
+#define WM8995_GP6_EINT_SHIFT                        5  /* GP6_EINT */
+#define WM8995_GP6_EINT_WIDTH                        1  /* GP6_EINT */
+#define WM8995_GP5_EINT                         0x0010  /* GP5_EINT */
+#define WM8995_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
+#define WM8995_GP5_EINT_SHIFT                        4  /* GP5_EINT */
+#define WM8995_GP5_EINT_WIDTH                        1  /* GP5_EINT */
+#define WM8995_GP4_EINT                         0x0008  /* GP4_EINT */
+#define WM8995_GP4_EINT_MASK                    0x0008  /* GP4_EINT */
+#define WM8995_GP4_EINT_SHIFT                        3  /* GP4_EINT */
+#define WM8995_GP4_EINT_WIDTH                        1  /* GP4_EINT */
+#define WM8995_GP3_EINT                         0x0004  /* GP3_EINT */
+#define WM8995_GP3_EINT_MASK                    0x0004  /* GP3_EINT */
+#define WM8995_GP3_EINT_SHIFT                        2  /* GP3_EINT */
+#define WM8995_GP3_EINT_WIDTH                        1  /* GP3_EINT */
+#define WM8995_GP2_EINT                         0x0002  /* GP2_EINT */
+#define WM8995_GP2_EINT_MASK                    0x0002  /* GP2_EINT */
+#define WM8995_GP2_EINT_SHIFT                        1  /* GP2_EINT */
+#define WM8995_GP2_EINT_WIDTH                        1  /* GP2_EINT */
+#define WM8995_GP1_EINT                         0x0001  /* GP1_EINT */
+#define WM8995_GP1_EINT_MASK                    0x0001  /* GP1_EINT */
+#define WM8995_GP1_EINT_SHIFT                        0  /* GP1_EINT */
+#define WM8995_GP1_EINT_WIDTH                        1  /* GP1_EINT */
+
+/*
+ * R1841 (0x731) - Interrupt Status 2
+ */
+#define WM8995_DCS_DONE_23_EINT                 0x1000  /* DCS_DONE_23_EINT */
+#define WM8995_DCS_DONE_23_EINT_MASK            0x1000  /* DCS_DONE_23_EINT */
+#define WM8995_DCS_DONE_23_EINT_SHIFT               12  /* DCS_DONE_23_EINT */
+#define WM8995_DCS_DONE_23_EINT_WIDTH                1  /* DCS_DONE_23_EINT */
+#define WM8995_DCS_DONE_01_EINT                 0x0800  /* DCS_DONE_01_EINT */
+#define WM8995_DCS_DONE_01_EINT_MASK            0x0800  /* DCS_DONE_01_EINT */
+#define WM8995_DCS_DONE_01_EINT_SHIFT               11  /* DCS_DONE_01_EINT */
+#define WM8995_DCS_DONE_01_EINT_WIDTH                1  /* DCS_DONE_01_EINT */
+#define WM8995_WSEQ_DONE_EINT                   0x0400  /* WSEQ_DONE_EINT */
+#define WM8995_WSEQ_DONE_EINT_MASK              0x0400  /* WSEQ_DONE_EINT */
+#define WM8995_WSEQ_DONE_EINT_SHIFT                 10  /* WSEQ_DONE_EINT */
+#define WM8995_WSEQ_DONE_EINT_WIDTH                  1  /* WSEQ_DONE_EINT */
+#define WM8995_FIFOS_ERR_EINT                   0x0200  /* FIFOS_ERR_EINT */
+#define WM8995_FIFOS_ERR_EINT_MASK              0x0200  /* FIFOS_ERR_EINT */
+#define WM8995_FIFOS_ERR_EINT_SHIFT                  9  /* FIFOS_ERR_EINT */
+#define WM8995_FIFOS_ERR_EINT_WIDTH                  1  /* FIFOS_ERR_EINT */
+#define WM8995_AIF2DRC_SIG_DET_EINT             0x0100  /* AIF2DRC_SIG_DET_EINT */
+#define WM8995_AIF2DRC_SIG_DET_EINT_MASK        0x0100  /* AIF2DRC_SIG_DET_EINT */
+#define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT            8  /* AIF2DRC_SIG_DET_EINT */
+#define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH            1  /* AIF2DRC_SIG_DET_EINT */
+#define WM8995_AIF1DRC2_SIG_DET_EINT            0x0080  /* AIF1DRC2_SIG_DET_EINT */
+#define WM8995_AIF1DRC2_SIG_DET_EINT_MASK       0x0080  /* AIF1DRC2_SIG_DET_EINT */
+#define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT           7  /* AIF1DRC2_SIG_DET_EINT */
+#define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH           1  /* AIF1DRC2_SIG_DET_EINT */
+#define WM8995_AIF1DRC1_SIG_DET_EINT            0x0040  /* AIF1DRC1_SIG_DET_EINT */
+#define WM8995_AIF1DRC1_SIG_DET_EINT_MASK       0x0040  /* AIF1DRC1_SIG_DET_EINT */
+#define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT           6  /* AIF1DRC1_SIG_DET_EINT */
+#define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH           1  /* AIF1DRC1_SIG_DET_EINT */
+#define WM8995_SRC2_LOCK_EINT                   0x0020  /* SRC2_LOCK_EINT */
+#define WM8995_SRC2_LOCK_EINT_MASK              0x0020  /* SRC2_LOCK_EINT */
+#define WM8995_SRC2_LOCK_EINT_SHIFT                  5  /* SRC2_LOCK_EINT */
+#define WM8995_SRC2_LOCK_EINT_WIDTH                  1  /* SRC2_LOCK_EINT */
+#define WM8995_SRC1_LOCK_EINT                   0x0010  /* SRC1_LOCK_EINT */
+#define WM8995_SRC1_LOCK_EINT_MASK              0x0010  /* SRC1_LOCK_EINT */
+#define WM8995_SRC1_LOCK_EINT_SHIFT                  4  /* SRC1_LOCK_EINT */
+#define WM8995_SRC1_LOCK_EINT_WIDTH                  1  /* SRC1_LOCK_EINT */
+#define WM8995_FLL2_LOCK_EINT                   0x0008  /* FLL2_LOCK_EINT */
+#define WM8995_FLL2_LOCK_EINT_MASK              0x0008  /* FLL2_LOCK_EINT */
+#define WM8995_FLL2_LOCK_EINT_SHIFT                  3  /* FLL2_LOCK_EINT */
+#define WM8995_FLL2_LOCK_EINT_WIDTH                  1  /* FLL2_LOCK_EINT */
+#define WM8995_FLL1_LOCK_EINT                   0x0004  /* FLL1_LOCK_EINT */
+#define WM8995_FLL1_LOCK_EINT_MASK              0x0004  /* FLL1_LOCK_EINT */
+#define WM8995_FLL1_LOCK_EINT_SHIFT                  2  /* FLL1_LOCK_EINT */
+#define WM8995_FLL1_LOCK_EINT_WIDTH                  1  /* FLL1_LOCK_EINT */
+#define WM8995_HP_DONE_EINT                     0x0002  /* HP_DONE_EINT */
+#define WM8995_HP_DONE_EINT_MASK                0x0002  /* HP_DONE_EINT */
+#define WM8995_HP_DONE_EINT_SHIFT                    1  /* HP_DONE_EINT */
+#define WM8995_HP_DONE_EINT_WIDTH                    1  /* HP_DONE_EINT */
+#define WM8995_MICD_EINT                        0x0001  /* MICD_EINT */
+#define WM8995_MICD_EINT_MASK                   0x0001  /* MICD_EINT */
+#define WM8995_MICD_EINT_SHIFT                       0  /* MICD_EINT */
+#define WM8995_MICD_EINT_WIDTH                       1  /* MICD_EINT */
+
+/*
+ * R1842 (0x732) - Interrupt Raw Status 2
+ */
+#define WM8995_DCS_DONE_23_STS                  0x1000  /* DCS_DONE_23_STS */
+#define WM8995_DCS_DONE_23_STS_MASK             0x1000  /* DCS_DONE_23_STS */
+#define WM8995_DCS_DONE_23_STS_SHIFT                12  /* DCS_DONE_23_STS */
+#define WM8995_DCS_DONE_23_STS_WIDTH                 1  /* DCS_DONE_23_STS */
+#define WM8995_DCS_DONE_01_STS                  0x0800  /* DCS_DONE_01_STS */
+#define WM8995_DCS_DONE_01_STS_MASK             0x0800  /* DCS_DONE_01_STS */
+#define WM8995_DCS_DONE_01_STS_SHIFT                11  /* DCS_DONE_01_STS */
+#define WM8995_DCS_DONE_01_STS_WIDTH                 1  /* DCS_DONE_01_STS */
+#define WM8995_WSEQ_DONE_STS                    0x0400  /* WSEQ_DONE_STS */
+#define WM8995_WSEQ_DONE_STS_MASK               0x0400  /* WSEQ_DONE_STS */
+#define WM8995_WSEQ_DONE_STS_SHIFT                  10  /* WSEQ_DONE_STS */
+#define WM8995_WSEQ_DONE_STS_WIDTH                   1  /* WSEQ_DONE_STS */
+#define WM8995_FIFOS_ERR_STS                    0x0200  /* FIFOS_ERR_STS */
+#define WM8995_FIFOS_ERR_STS_MASK               0x0200  /* FIFOS_ERR_STS */
+#define WM8995_FIFOS_ERR_STS_SHIFT                   9  /* FIFOS_ERR_STS */
+#define WM8995_FIFOS_ERR_STS_WIDTH                   1  /* FIFOS_ERR_STS */
+#define WM8995_AIF2DRC_SIG_DET_STS              0x0100  /* AIF2DRC_SIG_DET_STS */
+#define WM8995_AIF2DRC_SIG_DET_STS_MASK         0x0100  /* AIF2DRC_SIG_DET_STS */
+#define WM8995_AIF2DRC_SIG_DET_STS_SHIFT             8  /* AIF2DRC_SIG_DET_STS */
+#define WM8995_AIF2DRC_SIG_DET_STS_WIDTH             1  /* AIF2DRC_SIG_DET_STS */
+#define WM8995_AIF1DRC2_SIG_DET_STS             0x0080  /* AIF1DRC2_SIG_DET_STS */
+#define WM8995_AIF1DRC2_SIG_DET_STS_MASK        0x0080  /* AIF1DRC2_SIG_DET_STS */
+#define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT            7  /* AIF1DRC2_SIG_DET_STS */
+#define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH            1  /* AIF1DRC2_SIG_DET_STS */
+#define WM8995_AIF1DRC1_SIG_DET_STS             0x0040  /* AIF1DRC1_SIG_DET_STS */
+#define WM8995_AIF1DRC1_SIG_DET_STS_MASK        0x0040  /* AIF1DRC1_SIG_DET_STS */
+#define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT            6  /* AIF1DRC1_SIG_DET_STS */
+#define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH            1  /* AIF1DRC1_SIG_DET_STS */
+#define WM8995_SRC2_LOCK_STS                    0x0020  /* SRC2_LOCK_STS */
+#define WM8995_SRC2_LOCK_STS_MASK               0x0020  /* SRC2_LOCK_STS */
+#define WM8995_SRC2_LOCK_STS_SHIFT                   5  /* SRC2_LOCK_STS */
+#define WM8995_SRC2_LOCK_STS_WIDTH                   1  /* SRC2_LOCK_STS */
+#define WM8995_SRC1_LOCK_STS                    0x0010  /* SRC1_LOCK_STS */
+#define WM8995_SRC1_LOCK_STS_MASK               0x0010  /* SRC1_LOCK_STS */
+#define WM8995_SRC1_LOCK_STS_SHIFT                   4  /* SRC1_LOCK_STS */
+#define WM8995_SRC1_LOCK_STS_WIDTH                   1  /* SRC1_LOCK_STS */
+#define WM8995_FLL2_LOCK_STS                    0x0008  /* FLL2_LOCK_STS */
+#define WM8995_FLL2_LOCK_STS_MASK               0x0008  /* FLL2_LOCK_STS */
+#define WM8995_FLL2_LOCK_STS_SHIFT                   3  /* FLL2_LOCK_STS */
+#define WM8995_FLL2_LOCK_STS_WIDTH                   1  /* FLL2_LOCK_STS */
+#define WM8995_FLL1_LOCK_STS                    0x0004  /* FLL1_LOCK_STS */
+#define WM8995_FLL1_LOCK_STS_MASK               0x0004  /* FLL1_LOCK_STS */
+#define WM8995_FLL1_LOCK_STS_SHIFT                   2  /* FLL1_LOCK_STS */
+#define WM8995_FLL1_LOCK_STS_WIDTH                   1  /* FLL1_LOCK_STS */
+
+/*
+ * R1848 (0x738) - Interrupt Status 1 Mask
+ */
+#define WM8995_IM_GP14_EINT                     0x2000  /* IM_GP14_EINT */
+#define WM8995_IM_GP14_EINT_MASK                0x2000  /* IM_GP14_EINT */
+#define WM8995_IM_GP14_EINT_SHIFT                   13  /* IM_GP14_EINT */
+#define WM8995_IM_GP14_EINT_WIDTH                    1  /* IM_GP14_EINT */
+#define WM8995_IM_GP13_EINT                     0x1000  /* IM_GP13_EINT */
+#define WM8995_IM_GP13_EINT_MASK                0x1000  /* IM_GP13_EINT */
+#define WM8995_IM_GP13_EINT_SHIFT                   12  /* IM_GP13_EINT */
+#define WM8995_IM_GP13_EINT_WIDTH                    1  /* IM_GP13_EINT */
+#define WM8995_IM_GP12_EINT                     0x0800  /* IM_GP12_EINT */
+#define WM8995_IM_GP12_EINT_MASK                0x0800  /* IM_GP12_EINT */
+#define WM8995_IM_GP12_EINT_SHIFT                   11  /* IM_GP12_EINT */
+#define WM8995_IM_GP12_EINT_WIDTH                    1  /* IM_GP12_EINT */
+#define WM8995_IM_GP11_EINT                     0x0400  /* IM_GP11_EINT */
+#define WM8995_IM_GP11_EINT_MASK                0x0400  /* IM_GP11_EINT */
+#define WM8995_IM_GP11_EINT_SHIFT                   10  /* IM_GP11_EINT */
+#define WM8995_IM_GP11_EINT_WIDTH                    1  /* IM_GP11_EINT */
+#define WM8995_IM_GP10_EINT                     0x0200  /* IM_GP10_EINT */
+#define WM8995_IM_GP10_EINT_MASK                0x0200  /* IM_GP10_EINT */
+#define WM8995_IM_GP10_EINT_SHIFT                    9  /* IM_GP10_EINT */
+#define WM8995_IM_GP10_EINT_WIDTH                    1  /* IM_GP10_EINT */
+#define WM8995_IM_GP9_EINT                      0x0100  /* IM_GP9_EINT */
+#define WM8995_IM_GP9_EINT_MASK                 0x0100  /* IM_GP9_EINT */
+#define WM8995_IM_GP9_EINT_SHIFT                     8  /* IM_GP9_EINT */
+#define WM8995_IM_GP9_EINT_WIDTH                     1  /* IM_GP9_EINT */
+#define WM8995_IM_GP8_EINT                      0x0080  /* IM_GP8_EINT */
+#define WM8995_IM_GP8_EINT_MASK                 0x0080  /* IM_GP8_EINT */
+#define WM8995_IM_GP8_EINT_SHIFT                     7  /* IM_GP8_EINT */
+#define WM8995_IM_GP8_EINT_WIDTH                     1  /* IM_GP8_EINT */
+#define WM8995_IM_GP7_EINT                      0x0040  /* IM_GP7_EINT */
+#define WM8995_IM_GP7_EINT_MASK                 0x0040  /* IM_GP7_EINT */
+#define WM8995_IM_GP7_EINT_SHIFT                     6  /* IM_GP7_EINT */
+#define WM8995_IM_GP7_EINT_WIDTH                     1  /* IM_GP7_EINT */
+#define WM8995_IM_GP6_EINT                      0x0020  /* IM_GP6_EINT */
+#define WM8995_IM_GP6_EINT_MASK                 0x0020  /* IM_GP6_EINT */
+#define WM8995_IM_GP6_EINT_SHIFT                     5  /* IM_GP6_EINT */
+#define WM8995_IM_GP6_EINT_WIDTH                     1  /* IM_GP6_EINT */
+#define WM8995_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
+#define WM8995_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
+#define WM8995_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
+#define WM8995_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
+#define WM8995_IM_GP4_EINT                      0x0008  /* IM_GP4_EINT */
+#define WM8995_IM_GP4_EINT_MASK                 0x0008  /* IM_GP4_EINT */
+#define WM8995_IM_GP4_EINT_SHIFT                     3  /* IM_GP4_EINT */
+#define WM8995_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
+#define WM8995_IM_GP3_EINT                      0x0004  /* IM_GP3_EINT */
+#define WM8995_IM_GP3_EINT_MASK                 0x0004  /* IM_GP3_EINT */
+#define WM8995_IM_GP3_EINT_SHIFT                     2  /* IM_GP3_EINT */
+#define WM8995_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
+#define WM8995_IM_GP2_EINT                      0x0002  /* IM_GP2_EINT */
+#define WM8995_IM_GP2_EINT_MASK                 0x0002  /* IM_GP2_EINT */
+#define WM8995_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
+#define WM8995_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
+#define WM8995_IM_GP1_EINT                      0x0001  /* IM_GP1_EINT */
+#define WM8995_IM_GP1_EINT_MASK                 0x0001  /* IM_GP1_EINT */
+#define WM8995_IM_GP1_EINT_SHIFT                     0  /* IM_GP1_EINT */
+#define WM8995_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
+
+/*
+ * R1849 (0x739) - Interrupt Status 2 Mask
+ */
+#define WM8995_IM_DCS_DONE_23_EINT              0x1000  /* IM_DCS_DONE_23_EINT */
+#define WM8995_IM_DCS_DONE_23_EINT_MASK         0x1000  /* IM_DCS_DONE_23_EINT */
+#define WM8995_IM_DCS_DONE_23_EINT_SHIFT            12  /* IM_DCS_DONE_23_EINT */
+#define WM8995_IM_DCS_DONE_23_EINT_WIDTH             1  /* IM_DCS_DONE_23_EINT */
+#define WM8995_IM_DCS_DONE_01_EINT              0x0800  /* IM_DCS_DONE_01_EINT */
+#define WM8995_IM_DCS_DONE_01_EINT_MASK         0x0800  /* IM_DCS_DONE_01_EINT */
+#define WM8995_IM_DCS_DONE_01_EINT_SHIFT            11  /* IM_DCS_DONE_01_EINT */
+#define WM8995_IM_DCS_DONE_01_EINT_WIDTH             1  /* IM_DCS_DONE_01_EINT */
+#define WM8995_IM_WSEQ_DONE_EINT                0x0400  /* IM_WSEQ_DONE_EINT */
+#define WM8995_IM_WSEQ_DONE_EINT_MASK           0x0400  /* IM_WSEQ_DONE_EINT */
+#define WM8995_IM_WSEQ_DONE_EINT_SHIFT              10  /* IM_WSEQ_DONE_EINT */
+#define WM8995_IM_WSEQ_DONE_EINT_WIDTH               1  /* IM_WSEQ_DONE_EINT */
+#define WM8995_IM_FIFOS_ERR_EINT                0x0200  /* IM_FIFOS_ERR_EINT */
+#define WM8995_IM_FIFOS_ERR_EINT_MASK           0x0200  /* IM_FIFOS_ERR_EINT */
+#define WM8995_IM_FIFOS_ERR_EINT_SHIFT               9  /* IM_FIFOS_ERR_EINT */
+#define WM8995_IM_FIFOS_ERR_EINT_WIDTH               1  /* IM_FIFOS_ERR_EINT */
+#define WM8995_IM_AIF2DRC_SIG_DET_EINT          0x0100  /* IM_AIF2DRC_SIG_DET_EINT */
+#define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK     0x0100  /* IM_AIF2DRC_SIG_DET_EINT */
+#define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT         8  /* IM_AIF2DRC_SIG_DET_EINT */
+#define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH         1  /* IM_AIF2DRC_SIG_DET_EINT */
+#define WM8995_IM_AIF1DRC2_SIG_DET_EINT         0x0080  /* IM_AIF1DRC2_SIG_DET_EINT */
+#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK    0x0080  /* IM_AIF1DRC2_SIG_DET_EINT */
+#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT        7  /* IM_AIF1DRC2_SIG_DET_EINT */
+#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH        1  /* IM_AIF1DRC2_SIG_DET_EINT */
+#define WM8995_IM_AIF1DRC1_SIG_DET_EINT         0x0040  /* IM_AIF1DRC1_SIG_DET_EINT */
+#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK    0x0040  /* IM_AIF1DRC1_SIG_DET_EINT */
+#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT        6  /* IM_AIF1DRC1_SIG_DET_EINT */
+#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH        1  /* IM_AIF1DRC1_SIG_DET_EINT */
+#define WM8995_IM_SRC2_LOCK_EINT                0x0020  /* IM_SRC2_LOCK_EINT */
+#define WM8995_IM_SRC2_LOCK_EINT_MASK           0x0020  /* IM_SRC2_LOCK_EINT */
+#define WM8995_IM_SRC2_LOCK_EINT_SHIFT               5  /* IM_SRC2_LOCK_EINT */
+#define WM8995_IM_SRC2_LOCK_EINT_WIDTH               1  /* IM_SRC2_LOCK_EINT */
+#define WM8995_IM_SRC1_LOCK_EINT                0x0010  /* IM_SRC1_LOCK_EINT */
+#define WM8995_IM_SRC1_LOCK_EINT_MASK           0x0010  /* IM_SRC1_LOCK_EINT */
+#define WM8995_IM_SRC1_LOCK_EINT_SHIFT               4  /* IM_SRC1_LOCK_EINT */
+#define WM8995_IM_SRC1_LOCK_EINT_WIDTH               1  /* IM_SRC1_LOCK_EINT */
+#define WM8995_IM_FLL2_LOCK_EINT                0x0008  /* IM_FLL2_LOCK_EINT */
+#define WM8995_IM_FLL2_LOCK_EINT_MASK           0x0008  /* IM_FLL2_LOCK_EINT */
+#define WM8995_IM_FLL2_LOCK_EINT_SHIFT               3  /* IM_FLL2_LOCK_EINT */
+#define WM8995_IM_FLL2_LOCK_EINT_WIDTH               1  /* IM_FLL2_LOCK_EINT */
+#define WM8995_IM_FLL1_LOCK_EINT                0x0004  /* IM_FLL1_LOCK_EINT */
+#define WM8995_IM_FLL1_LOCK_EINT_MASK           0x0004  /* IM_FLL1_LOCK_EINT */
+#define WM8995_IM_FLL1_LOCK_EINT_SHIFT               2  /* IM_FLL1_LOCK_EINT */
+#define WM8995_IM_FLL1_LOCK_EINT_WIDTH               1  /* IM_FLL1_LOCK_EINT */
+#define WM8995_IM_HP_DONE_EINT                  0x0002  /* IM_HP_DONE_EINT */
+#define WM8995_IM_HP_DONE_EINT_MASK             0x0002  /* IM_HP_DONE_EINT */
+#define WM8995_IM_HP_DONE_EINT_SHIFT                 1  /* IM_HP_DONE_EINT */
+#define WM8995_IM_HP_DONE_EINT_WIDTH                 1  /* IM_HP_DONE_EINT */
+#define WM8995_IM_MICD_EINT                     0x0001  /* IM_MICD_EINT */
+#define WM8995_IM_MICD_EINT_MASK                0x0001  /* IM_MICD_EINT */
+#define WM8995_IM_MICD_EINT_SHIFT                    0  /* IM_MICD_EINT */
+#define WM8995_IM_MICD_EINT_WIDTH                    1  /* IM_MICD_EINT */
+
+/*
+ * R1856 (0x740) - Interrupt Control
+ */
+#define WM8995_IM_IRQ                           0x0001  /* IM_IRQ */
+#define WM8995_IM_IRQ_MASK                      0x0001  /* IM_IRQ */
+#define WM8995_IM_IRQ_SHIFT                          0  /* IM_IRQ */
+#define WM8995_IM_IRQ_WIDTH                          1  /* IM_IRQ */
+
+/*
+ * R2048 (0x800) - Left PDM Speaker 1
+ */
+#define WM8995_SPK1L_ENA                        0x0010  /* SPK1L_ENA */
+#define WM8995_SPK1L_ENA_MASK                   0x0010  /* SPK1L_ENA */
+#define WM8995_SPK1L_ENA_SHIFT                       4  /* SPK1L_ENA */
+#define WM8995_SPK1L_ENA_WIDTH                       1  /* SPK1L_ENA */
+#define WM8995_SPK1L_MUTE                       0x0008  /* SPK1L_MUTE */
+#define WM8995_SPK1L_MUTE_MASK                  0x0008  /* SPK1L_MUTE */
+#define WM8995_SPK1L_MUTE_SHIFT                      3  /* SPK1L_MUTE */
+#define WM8995_SPK1L_MUTE_WIDTH                      1  /* SPK1L_MUTE */
+#define WM8995_SPK1L_MUTE_ZC                    0x0004  /* SPK1L_MUTE_ZC */
+#define WM8995_SPK1L_MUTE_ZC_MASK               0x0004  /* SPK1L_MUTE_ZC */
+#define WM8995_SPK1L_MUTE_ZC_SHIFT                   2  /* SPK1L_MUTE_ZC */
+#define WM8995_SPK1L_MUTE_ZC_WIDTH                   1  /* SPK1L_MUTE_ZC */
+#define WM8995_SPK1L_SRC_MASK                   0x0003  /* SPK1L_SRC - [1:0] */
+#define WM8995_SPK1L_SRC_SHIFT                       0  /* SPK1L_SRC - [1:0] */
+#define WM8995_SPK1L_SRC_WIDTH                       2  /* SPK1L_SRC - [1:0] */
+
+/*
+ * R2049 (0x801) - Right PDM Speaker 1
+ */
+#define WM8995_SPK1R_ENA                        0x0010  /* SPK1R_ENA */
+#define WM8995_SPK1R_ENA_MASK                   0x0010  /* SPK1R_ENA */
+#define WM8995_SPK1R_ENA_SHIFT                       4  /* SPK1R_ENA */
+#define WM8995_SPK1R_ENA_WIDTH                       1  /* SPK1R_ENA */
+#define WM8995_SPK1R_MUTE                       0x0008  /* SPK1R_MUTE */
+#define WM8995_SPK1R_MUTE_MASK                  0x0008  /* SPK1R_MUTE */
+#define WM8995_SPK1R_MUTE_SHIFT                      3  /* SPK1R_MUTE */
+#define WM8995_SPK1R_MUTE_WIDTH                      1  /* SPK1R_MUTE */
+#define WM8995_SPK1R_MUTE_ZC                    0x0004  /* SPK1R_MUTE_ZC */
+#define WM8995_SPK1R_MUTE_ZC_MASK               0x0004  /* SPK1R_MUTE_ZC */
+#define WM8995_SPK1R_MUTE_ZC_SHIFT                   2  /* SPK1R_MUTE_ZC */
+#define WM8995_SPK1R_MUTE_ZC_WIDTH                   1  /* SPK1R_MUTE_ZC */
+#define WM8995_SPK1R_SRC_MASK                   0x0003  /* SPK1R_SRC - [1:0] */
+#define WM8995_SPK1R_SRC_SHIFT                       0  /* SPK1R_SRC - [1:0] */
+#define WM8995_SPK1R_SRC_WIDTH                       2  /* SPK1R_SRC - [1:0] */
+
+/*
+ * R2050 (0x802) - PDM Speaker 1 Mute Sequence
+ */
+#define WM8995_SPK1_MUTE_SEQ1_MASK              0x00FF  /* SPK1_MUTE_SEQ1 - [7:0] */
+#define WM8995_SPK1_MUTE_SEQ1_SHIFT                  0  /* SPK1_MUTE_SEQ1 - [7:0] */
+#define WM8995_SPK1_MUTE_SEQ1_WIDTH                  8  /* SPK1_MUTE_SEQ1 - [7:0] */
+
+/*
+ * R2056 (0x808) - Left PDM Speaker 2
+ */
+#define WM8995_SPK2L_ENA                        0x0010  /* SPK2L_ENA */
+#define WM8995_SPK2L_ENA_MASK                   0x0010  /* SPK2L_ENA */
+#define WM8995_SPK2L_ENA_SHIFT                       4  /* SPK2L_ENA */
+#define WM8995_SPK2L_ENA_WIDTH                       1  /* SPK2L_ENA */
+#define WM8995_SPK2L_MUTE                       0x0008  /* SPK2L_MUTE */
+#define WM8995_SPK2L_MUTE_MASK                  0x0008  /* SPK2L_MUTE */
+#define WM8995_SPK2L_MUTE_SHIFT                      3  /* SPK2L_MUTE */
+#define WM8995_SPK2L_MUTE_WIDTH                      1  /* SPK2L_MUTE */
+#define WM8995_SPK2L_MUTE_ZC                    0x0004  /* SPK2L_MUTE_ZC */
+#define WM8995_SPK2L_MUTE_ZC_MASK               0x0004  /* SPK2L_MUTE_ZC */
+#define WM8995_SPK2L_MUTE_ZC_SHIFT                   2  /* SPK2L_MUTE_ZC */
+#define WM8995_SPK2L_MUTE_ZC_WIDTH                   1  /* SPK2L_MUTE_ZC */
+#define WM8995_SPK2L_SRC_MASK                   0x0003  /* SPK2L_SRC - [1:0] */
+#define WM8995_SPK2L_SRC_SHIFT                       0  /* SPK2L_SRC - [1:0] */
+#define WM8995_SPK2L_SRC_WIDTH                       2  /* SPK2L_SRC - [1:0] */
+
+/*
+ * R2057 (0x809) - Right PDM Speaker 2
+ */
+#define WM8995_SPK2R_ENA                        0x0010  /* SPK2R_ENA */
+#define WM8995_SPK2R_ENA_MASK                   0x0010  /* SPK2R_ENA */
+#define WM8995_SPK2R_ENA_SHIFT                       4  /* SPK2R_ENA */
+#define WM8995_SPK2R_ENA_WIDTH                       1  /* SPK2R_ENA */
+#define WM8995_SPK2R_MUTE                       0x0008  /* SPK2R_MUTE */
+#define WM8995_SPK2R_MUTE_MASK                  0x0008  /* SPK2R_MUTE */
+#define WM8995_SPK2R_MUTE_SHIFT                      3  /* SPK2R_MUTE */
+#define WM8995_SPK2R_MUTE_WIDTH                      1  /* SPK2R_MUTE */
+#define WM8995_SPK2R_MUTE_ZC                    0x0004  /* SPK2R_MUTE_ZC */
+#define WM8995_SPK2R_MUTE_ZC_MASK               0x0004  /* SPK2R_MUTE_ZC */
+#define WM8995_SPK2R_MUTE_ZC_SHIFT                   2  /* SPK2R_MUTE_ZC */
+#define WM8995_SPK2R_MUTE_ZC_WIDTH                   1  /* SPK2R_MUTE_ZC */
+#define WM8995_SPK2R_SRC_MASK                   0x0003  /* SPK2R_SRC - [1:0] */
+#define WM8995_SPK2R_SRC_SHIFT                       0  /* SPK2R_SRC - [1:0] */
+#define WM8995_SPK2R_SRC_WIDTH                       2  /* SPK2R_SRC - [1:0] */
+
+/*
+ * R2058 (0x80A) - PDM Speaker 2 Mute Sequence
+ */
+#define WM8995_SPK2_MUTE_SEQ1_MASK              0x00FF  /* SPK2_MUTE_SEQ1 - [7:0] */
+#define WM8995_SPK2_MUTE_SEQ1_SHIFT                  0  /* SPK2_MUTE_SEQ1 - [7:0] */
+#define WM8995_SPK2_MUTE_SEQ1_WIDTH                  8  /* SPK2_MUTE_SEQ1 - [7:0] */
+
+#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
+{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+        .info = snd_soc_info_volsw, \
+        .get = snd_soc_dapm_get_volsw, .put = wm8995_put_class_w, \
+        .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) \
+}
+
+struct wm8995_reg_access {
+        u16 read;
+        u16 write;
+        u16 vol;
+};
+
+/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
+enum clk_src {
+        WM8995_SYSCLK_MCLK1 = 1,
+        WM8995_SYSCLK_MCLK2,
+        WM8995_SYSCLK_FLL1,
+        WM8995_SYSCLK_FLL2,
+        WM8995_SYSCLK_OPCLK
+};
+
+#define WM8995_FLL1 1
+#define WM8995_FLL2 2
+
+#define WM8995_FLL_SRC_MCLK1  1
+#define WM8995_FLL_SRC_MCLK2  2
+#define WM8995_FLL_SRC_LRCLK  3
+#define WM8995_FLL_SRC_BCLK   4
+
+#endif /* _WM8995_H */
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index 76b37ff6c264..91c6b39de50c 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -15,6 +15,7 @@
 #include <linux/moduleparam.h>
 #include <linux/init.h>
 #include <linux/delay.h>
+#include <linux/device.h>
 #include <linux/pm.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
@@ -23,7 +24,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
@@ -156,8 +156,8 @@ static struct {
 };
 
 struct wm9081_priv {
-        struct snd_soc_codec codec;
-        u16 reg_cache[WM9081_MAX_REGISTER + 1];
+        enum snd_soc_control_type control_type;
+        void *control_data;
         int sysclk_source;
         int mclk_rate;
         int sysclk_rate;
@@ -167,10 +167,10 @@ struct wm9081_priv {
         int fll_fref;
         int fll_fout;
         int tdm_width;
-        struct wm9081_retune_mobile_config *retune;
+        struct wm9081_pdata pdata;
 };
 
-static int wm9081_volatile_register(unsigned int reg)
+static int wm9081_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
 {
         switch (reg) {
         case WM9081_SOFTWARE_RESET:
@@ -305,7 +305,7 @@ static int speaker_mode_get(struct snd_kcontrol *kcontrol,
 /*
  * Stop any attempts to change speaker mode while the speaker is enabled.
  *
- * We also have some special anti-pop controls dependant on speaker
+ * We also have some special anti-pop controls dependent on speaker
  * mode which must be changed along with the mode.
  */
 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
@@ -389,27 +389,6 @@ SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
 };
 
-static int speaker_event(struct snd_soc_dapm_widget *w,
-                         struct snd_kcontrol *kcontrol, int event)
-{
-        struct snd_soc_codec *codec = w->codec;
-        unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
-
-        switch (event) {
-        case SND_SOC_DAPM_POST_PMU:
-                reg |= WM9081_SPK_ENA;
-                break;
-
-        case SND_SOC_DAPM_PRE_PMD:
-                reg &= ~WM9081_SPK_ENA;
-                break;
-        }
-
-        snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
-
-        return 0;
-}
-
 struct _fll_div {
         u16 fll_fratio;
         u16 fll_outdiv;
@@ -477,7 +456,7 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
 
         pr_debug("Fvco=%dHz\n", target);
 
-        /* Find an appropraite FLL_FRATIO and factor it out of the target */
+        /* Find an appropriate FLL_FRATIO and factor it out of the target */
         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
@@ -590,6 +569,10 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
         reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
         snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
 
+        /* Set gain to the recommended value */
+        snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
+                            WM9081_FLL_GAIN_MASK, 0);
+
         /* Enable the FLL */
         snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
 
@@ -743,9 +726,8 @@ SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
 
 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
 
-SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
-                   speaker_event,
-                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
 
 SND_SOC_DAPM_OUTPUT("LINEOUT"),
 SND_SOC_DAPM_OUTPUT("SPKN"),
@@ -758,7 +740,7 @@ SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
 };
 
 
-static const struct snd_soc_dapm_route audio_paths[] = {
+static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
         { "DAC", NULL, "CLK_SYS" },
         { "DAC", NULL, "CLK_DSP" },
 
@@ -776,8 +758,10 @@ static const struct snd_soc_dapm_route audio_paths[] = {
         { "Speaker PGA", NULL, "TOCLK" },
         { "Speaker PGA", NULL, "CLK_SYS" },
 
-        { "SPKN", NULL, "Speaker PGA" },
-        { "SPKP", NULL, "Speaker PGA" },
+        { "Speaker", NULL, "Speaker PGA" },
+
+        { "SPKN", NULL, "Speaker" },
+        { "SPKP", NULL, "Speaker" },
 };
 
 static int wm9081_set_bias_level(struct snd_soc_codec *codec,
@@ -804,7 +788,7 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec,
 
         case SND_SOC_BIAS_STANDBY:
                 /* Initial cold start */
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Disable LINEOUT discharge */
                         reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
                         reg &= ~WM9081_LINEOUT_DISCH;
@@ -864,7 +848,7 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
@@ -1078,21 +1062,22 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
         aif4 |= wm9081->bclk / wm9081->fs;
 
         /* Apply a ReTune Mobile configuration if it's in use */
-        if (wm9081->retune) {
-                struct wm9081_retune_mobile_config *retune = wm9081->retune;
+        if (wm9081->pdata.num_retune_configs) {
+                struct wm9081_pdata *pdata = &wm9081->pdata;
                 struct wm9081_retune_mobile_setting *s;
                 int eq1;
 
                 best = 0;
-                best_val = abs(retune->configs[0].rate - wm9081->fs);
-                for (i = 0; i < retune->num_configs; i++) {
-                        cur_val = abs(retune->configs[i].rate - wm9081->fs);
+                best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
+                for (i = 0; i < pdata->num_retune_configs; i++) {
+                        cur_val = abs(pdata->retune_configs[i].rate -
+                                      wm9081->fs);
                         if (cur_val < best_val) {
                                 best_val = cur_val;
                                 best = i;
                         }
                 }
-                s = &retune->configs[best];
+                s = &pdata->retune_configs[best];
 
                 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
                         s->name, s->rate);
@@ -1135,10 +1120,9 @@ static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
         return 0;
 }
 
-static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
+static int wm9081_set_sysclk(struct snd_soc_codec *codec,
                              int clk_id, unsigned int freq, int dir)
 {
-        struct snd_soc_codec *codec = codec_dai->codec;
         struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
 
         switch (clk_id) {
@@ -1203,7 +1187,6 @@ static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
 
 static struct snd_soc_dai_ops wm9081_dai_ops = {
         .hw_params = wm9081_hw_params,
-        .set_sysclk = wm9081_set_sysclk,
         .set_fmt = wm9081_set_dai_fmt,
         .digital_mute = wm9081_digital_mute,
         .set_tdm_slot = wm9081_set_tdm_slot,
@@ -1212,8 +1195,8 @@ static struct snd_soc_dai_ops wm9081_dai_ops = {
 /* We report two channels because the CODEC processes a stereo signal, even
  * though it is only capable of handling a mono output.
  */
-struct snd_soc_dai wm9081_dai = {
-        .name = "WM9081",
+static struct snd_soc_dai_driver wm9081_dai = {
+        .name = "wm9081-hifi",
         .playback = {
                 .stream_name = "HiFi Playback",
                 .channels_min = 1,
@@ -1223,82 +1206,82 @@ struct snd_soc_dai wm9081_dai = {
         },
         .ops = &wm9081_dai_ops,
 };
-EXPORT_SYMBOL_GPL(wm9081_dai);
 
-
-static struct snd_soc_codec *wm9081_codec;
-
-static int wm9081_probe(struct platform_device *pdev)
+static int wm9081_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        struct wm9081_priv *wm9081;
-        int ret = 0;
+        struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+        u16 reg;
 
-        if (wm9081_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
+        codec->control_data = wm9081->control_data;
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
-        socdev->card->codec = wm9081_codec;
-        codec = wm9081_codec;
-        wm9081 = snd_soc_codec_get_drvdata(codec);
+        reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
+        if (reg != 0x9081) {
+                dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
+                ret = -EINVAL;
+                return ret;
+        }
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+        ret = wm9081_reset(codec);
         if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
+                dev_err(codec->dev, "Failed to issue reset\n");
+                return ret;
         }
 
+        reg = 0;
+        if (wm9081->pdata.irq_high)
+                reg |= WM9081_IRQ_POL;
+        if (!wm9081->pdata.irq_cmos)
+                reg |= WM9081_IRQ_OP_CTRL;
+        snd_soc_update_bits(codec, WM9081_INTERRUPT_CONTROL,
+                            WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
+
+        wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        /* Enable zero cross by default */
+        reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
+        snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
+        reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
+        snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
+                     reg | WM9081_SPKPGAZC);
+
         snd_soc_add_controls(codec, wm9081_snd_controls,
                              ARRAY_SIZE(wm9081_snd_controls));
-        if (!wm9081->retune) {
+        if (!wm9081->pdata.num_retune_configs) {
                 dev_dbg(codec->dev,
                         "No ReTune Mobile data, using normal EQ\n");
                 snd_soc_add_controls(codec, wm9081_eq_controls,
                                      ARRAY_SIZE(wm9081_eq_controls));
         }
 
-        snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets,
-                                  ARRAY_SIZE(wm9081_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
-
-        return ret;
-
-pcm_err:
         return ret;
 }
 
-static int wm9081_remove(struct platform_device *pdev)
+static int wm9081_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
-
+        wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
 #ifdef CONFIG_PM
-static int wm9081_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm9081_resume(struct platform_device *pdev)
+static int wm9081_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         u16 *reg_cache = codec->reg_cache;
         int i;
 
-        for (i = 0; i < codec->reg_cache_size; i++) {
+        for (i = 0; i < codec->driver->reg_cache_size; i++) {
                 if (i == WM9081_SOFTWARE_RESET)
                         continue;
 
@@ -1314,133 +1297,56 @@ static int wm9081_resume(struct platform_device *pdev)
 #define wm9081_resume NULL
 #endif
 
-struct snd_soc_codec_device soc_codec_dev_wm9081 = {
+static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
         .probe =        wm9081_probe,
         .remove =       wm9081_remove,
         .suspend =      wm9081_suspend,
         .resume =       wm9081_resume,
-};
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
 
-static int wm9081_register(struct wm9081_priv *wm9081,
-                           enum snd_soc_control_type control)
-{
-        struct snd_soc_codec *codec = &wm9081->codec;
-        int ret;
-        u16 reg;
-
-        if (wm9081_codec) {
-                dev_err(codec->dev, "Another WM9081 is registered\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        snd_soc_codec_set_drvdata(codec, wm9081);
-        codec->name = "WM9081";
-        codec->owner = THIS_MODULE;
-        codec->dai = &wm9081_dai;
-        codec->num_dai = 1;
-        codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
-        codec->reg_cache = &wm9081->reg_cache;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm9081_set_bias_level;
-        codec->volatile_register = wm9081_volatile_register;
-
-        memcpy(codec->reg_cache, wm9081_reg_defaults,
-               sizeof(wm9081_reg_defaults));
-
-        ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
-        }
-
-        reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
-        if (reg != 0x9081) {
-                dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
-                ret = -EINVAL;
-                goto err;
-        }
-
-        ret = wm9081_reset(codec);
-        if (ret < 0) {
-                dev_err(codec->dev, "Failed to issue reset\n");
-                goto err;
-        }
-
-        wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-
-        /* Enable zero cross by default */
-        reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
-        snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
-        reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
-        snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
-                     reg | WM9081_SPKPGAZC);
-
-        wm9081_dai.dev = codec->dev;
-
-        wm9081_codec = codec;
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register codec: %d\n", ret);
-                goto err;
-        }
-
-        ret = snd_soc_register_dai(&wm9081_dai);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
-                goto err_codec;
-        }
-
-        return 0;
+        .set_sysclk = wm9081_set_sysclk,
+        .set_bias_level = wm9081_set_bias_level,
 
-err_codec:
-        snd_soc_unregister_codec(codec);
-err:
-        kfree(wm9081);
-        return ret;
-}
+        .reg_cache_size = ARRAY_SIZE(wm9081_reg_defaults),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm9081_reg_defaults,
+        .volatile_register = wm9081_volatile_register,
 
-static void wm9081_unregister(struct wm9081_priv *wm9081)
-{
-        wm9081_set_bias_level(&wm9081->codec, SND_SOC_BIAS_OFF);
-        snd_soc_unregister_dai(&wm9081_dai);
-        snd_soc_unregister_codec(&wm9081->codec);
-        kfree(wm9081);
-        wm9081_codec = NULL;
-}
+        .dapm_widgets     = wm9081_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
+        .dapm_routes     = wm9081_audio_paths,
+        .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
+};
 
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
                                       const struct i2c_device_id *id)
 {
         struct wm9081_priv *wm9081;
-        struct snd_soc_codec *codec;
+        int ret;
 
         wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
         if (wm9081 == NULL)
                 return -ENOMEM;
 
-        codec = &wm9081->codec;
-        codec->hw_write = (hw_write_t)i2c_master_send;
-        wm9081->retune = i2c->dev.platform_data;
-
         i2c_set_clientdata(i2c, wm9081);
-        codec->control_data = i2c;
+        wm9081->control_type = SND_SOC_I2C;
+        wm9081->control_data = i2c;
 
-        codec->dev = &i2c->dev;
+        if (dev_get_platdata(&i2c->dev))
+                memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
+                       sizeof(wm9081->pdata));
 
-        return wm9081_register(wm9081, SND_SOC_I2C);
+        ret = snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm9081, &wm9081_dai, 1);
+        if (ret < 0)
+                kfree(wm9081);
+        return ret;
 }
 
 static __devexit int wm9081_i2c_remove(struct i2c_client *client)
 {
-        struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
-        wm9081_unregister(wm9081);
+        snd_soc_unregister_codec(&client->dev);
+        kfree(i2c_get_clientdata(client));
         return 0;
 }
 
@@ -1459,24 +1365,27 @@ static struct i2c_driver wm9081_i2c_driver = {
         .remove =   __devexit_p(wm9081_i2c_remove),
         .id_table = wm9081_i2c_id,
 };
+#endif
 
 static int __init wm9081_modinit(void)
 {
-        int ret;
-
+        int ret = 0;
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         ret = i2c_add_driver(&wm9081_i2c_driver);
         if (ret != 0) {
                 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
                        ret);
         }
-
+#endif
         return ret;
 }
 module_init(wm9081_modinit);
 
 static void __exit wm9081_exit(void)
 {
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
         i2c_del_driver(&wm9081_i2c_driver);
+#endif
 }
 module_exit(wm9081_exit);
 
diff --git a/sound/soc/codecs/wm9081.h b/sound/soc/codecs/wm9081.h
index 42d3bc757021..871cccb066dc 100644
--- a/sound/soc/codecs/wm9081.h
+++ b/sound/soc/codecs/wm9081.h
@@ -15,9 +15,6 @@
 
 #include <sound/soc.h>
 
-extern struct snd_soc_dai wm9081_dai;
-extern struct snd_soc_codec_device soc_codec_dev_wm9081;
-
 /*
  * SYSCLK sources
  */
diff --git a/sound/soc/codecs/wm9090.c b/sound/soc/codecs/wm9090.c
index 1592250daec0..4de12203e611 100644
--- a/sound/soc/codecs/wm9090.c
+++ b/sound/soc/codecs/wm9090.c
@@ -28,14 +28,11 @@
 #include <linux/slab.h>
 #include <sound/initval.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 #include <sound/wm9090.h>
 
 #include "wm9090.h"
 
-static struct snd_soc_codec *wm9090_codec;
-
 static const u16 wm9090_reg_defaults[] = {
         0x9093,     /* R0   - Software Reset */
         0x0006,     /* R1   - Power Management (1) */
@@ -142,18 +139,12 @@ static const u16 wm9090_reg_defaults[] = {
 
 /* This struct is used to save the context */
 struct wm9090_priv {
-        /* We're not really registering as a CODEC since ASoC core
-         * does not yet support multiple CODECs but having the CODEC
-         * structure means we can reuse some of the ASoC core
-         * features.
-         */
-        struct snd_soc_codec codec;
         struct mutex mutex;
-        u16 reg_cache[WM9090_MAX_REGISTER + 1];
         struct wm9090_platform_data pdata;
+        void *control_data;
 };
 
-static int wm9090_volatile(unsigned int reg)
+static int wm9090_volatile(struct snd_soc_codec *codec, unsigned int reg)
 {
         switch (reg) {
         case WM9090_SOFTWARE_RESET:
@@ -450,31 +441,32 @@ static const struct snd_soc_dapm_route audio_map_in2_diff[] = {
 static int wm9090_add_controls(struct snd_soc_codec *codec)
 {
         struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
         int i;
 
-        snd_soc_dapm_new_controls(codec, wm9090_dapm_widgets,
+        snd_soc_dapm_new_controls(dapm, wm9090_dapm_widgets,
                                   ARRAY_SIZE(wm9090_dapm_widgets));
 
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 
         snd_soc_add_controls(codec, wm9090_controls,
                              ARRAY_SIZE(wm9090_controls));
 
         if (wm9090->pdata.lin1_diff) {
-                snd_soc_dapm_add_routes(codec, audio_map_in1_diff,
+                snd_soc_dapm_add_routes(dapm, audio_map_in1_diff,
                                         ARRAY_SIZE(audio_map_in1_diff));
         } else {
-                snd_soc_dapm_add_routes(codec, audio_map_in1_se,
+                snd_soc_dapm_add_routes(dapm, audio_map_in1_se,
                                         ARRAY_SIZE(audio_map_in1_se));
                 snd_soc_add_controls(codec, wm9090_in1_se_controls,
                                      ARRAY_SIZE(wm9090_in1_se_controls));
         }
 
         if (wm9090->pdata.lin2_diff) {
-                snd_soc_dapm_add_routes(codec, audio_map_in2_diff,
+                snd_soc_dapm_add_routes(dapm, audio_map_in2_diff,
                                         ARRAY_SIZE(audio_map_in2_diff));
         } else {
-                snd_soc_dapm_add_routes(codec, audio_map_in2_se,
+                snd_soc_dapm_add_routes(dapm, audio_map_in2_se,
                                         ARRAY_SIZE(audio_map_in2_se));
                 snd_soc_add_controls(codec, wm9090_in2_se_controls,
                                      ARRAY_SIZE(wm9090_in2_se_controls));
@@ -521,12 +513,12 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec,
                 break;
 
         case SND_SOC_BIAS_STANDBY:
-                if (codec->bias_level == SND_SOC_BIAS_OFF) {
+                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
                         /* Restore the register cache */
-                        for (i = 1; i < codec->reg_cache_size; i++) {
+                        for (i = 1; i < codec->driver->reg_cache_size; i++) {
                                 if (reg_cache[i] == wm9090_reg_defaults[i])
                                         continue;
-                                if (wm9090_volatile(i))
+                                if (wm9090_volatile(codec, i))
                                         continue;
 
                                 ret = snd_soc_write(codec, i, reg_cache[i]);
@@ -551,56 +543,80 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec,
                 break;
         }
 
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
 
         return 0;
 }
 
-static int wm9090_probe(struct platform_device *pdev)
+static int wm9090_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
-        int ret = 0;
+        struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec);
+        int ret;
 
-        if (wm9090_codec == NULL) {
-                dev_err(&pdev->dev, "Codec device not registered\n");
-                return -ENODEV;
+        codec->control_data = wm9090->control_data;
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
         }
 
-        socdev->card->codec = wm9090_codec;
-        codec = wm9090_codec;
-
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0) {
-                dev_err(codec->dev, "failed to create pcms: %d\n", ret);
-                goto pcm_err;
+        ret = snd_soc_read(codec, WM9090_SOFTWARE_RESET);
+        if (ret < 0)
+                return ret;
+        if (ret != wm9090_reg_defaults[WM9090_SOFTWARE_RESET]) {
+                dev_err(codec->dev, "Device is not a WM9090, ID=%x\n", ret);
+                return -EINVAL;
         }
 
+        ret = snd_soc_write(codec, WM9090_SOFTWARE_RESET, 0);
+        if (ret < 0)
+                return ret;
+
+        /* Configure some defaults; they will be written out when we
+         * bring the bias up.
+         */
+        snd_soc_update_bits(codec, WM9090_IN1_LINE_INPUT_A_VOLUME,
+                            WM9090_IN1_VU | WM9090_IN1A_ZC,
+                            WM9090_IN1_VU | WM9090_IN1A_ZC);
+        snd_soc_update_bits(codec, WM9090_IN1_LINE_INPUT_B_VOLUME,
+                            WM9090_IN1_VU | WM9090_IN1B_ZC,
+                            WM9090_IN1_VU | WM9090_IN1B_ZC);
+        snd_soc_update_bits(codec, WM9090_IN2_LINE_INPUT_A_VOLUME,
+                            WM9090_IN2_VU | WM9090_IN2A_ZC,
+                            WM9090_IN2_VU | WM9090_IN2A_ZC);
+        snd_soc_update_bits(codec, WM9090_IN2_LINE_INPUT_B_VOLUME,
+                            WM9090_IN2_VU | WM9090_IN2B_ZC,
+                            WM9090_IN2_VU | WM9090_IN2B_ZC);
+        snd_soc_update_bits(codec, WM9090_SPEAKER_VOLUME_LEFT,
+                            WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC,
+                            WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC);
+        snd_soc_update_bits(codec, WM9090_LEFT_OUTPUT_VOLUME,
+                            WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC,
+                            WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC);
+        snd_soc_update_bits(codec, WM9090_RIGHT_OUTPUT_VOLUME,
+                            WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC,
+                            WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC);
+
+        snd_soc_update_bits(codec, WM9090_CLOCKING_1,
+                            WM9090_TOCLK_ENA, WM9090_TOCLK_ENA);
+
+        wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
         wm9090_add_controls(codec);
 
         return 0;
-
-pcm_err:
-        return ret;
 }
 
 #ifdef CONFIG_PM
-static int wm9090_suspend(struct platform_device *pdev, pm_message_t state)
+static int wm9090_suspend(struct snd_soc_codec *codec, pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm9090_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-static int wm9090_resume(struct platform_device *pdev)
+static int wm9090_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 
         return 0;
@@ -610,29 +626,29 @@ static int wm9090_resume(struct platform_device *pdev)
 #define wm9090_resume NULL
 #endif
 
-static int wm9090_remove(struct platform_device *pdev)
+static int wm9090_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-
-        snd_soc_free_pcms(socdev);
-        snd_soc_dapm_free(socdev);
+        wm9090_set_bias_level(codec, SND_SOC_BIAS_OFF);
 
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_wm9090 = {
+static struct snd_soc_codec_driver soc_codec_dev_wm9090 = {
         .probe =        wm9090_probe,
         .remove =       wm9090_remove,
         .suspend =      wm9090_suspend,
         .resume =       wm9090_resume,
+        .set_bias_level = wm9090_set_bias_level,
+        .reg_cache_size = (WM9090_MAX_REGISTER + 1),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = wm9090_reg_defaults,
+        .volatile_register = wm9090_volatile,
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm9090);
 
 static int wm9090_i2c_probe(struct i2c_client *i2c,
                             const struct i2c_device_id *id)
 {
         struct wm9090_priv *wm9090;
-        struct snd_soc_codec *codec;
         int ret;
 
         wm9090 = kzalloc(sizeof(*wm9090), GFP_KERNEL);
@@ -640,102 +656,28 @@ static int wm9090_i2c_probe(struct i2c_client *i2c,
                 dev_err(&i2c->dev, "Can not allocate memory\n");
                 return -ENOMEM;
         }
-        codec = &wm9090->codec;
 
         if (i2c->dev.platform_data)
                 memcpy(&wm9090->pdata, i2c->dev.platform_data,
                        sizeof(wm9090->pdata));
 
-        wm9090_codec = codec;
-
         i2c_set_clientdata(i2c, wm9090);
+        wm9090->control_data = i2c;
+        mutex_init(&wm9090->mutex);
 
-        mutex_init(&codec->mutex);
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
-        codec->control_data = i2c;
-        snd_soc_codec_set_drvdata(codec, wm9090);
-        codec->dev = &i2c->dev;
-        codec->name = "WM9090";
-        codec->owner = THIS_MODULE;
-        codec->bias_level = SND_SOC_BIAS_OFF;
-        codec->set_bias_level = wm9090_set_bias_level,
-        codec->reg_cache_size = WM9090_MAX_REGISTER + 1;
-        codec->reg_cache = &wm9090->reg_cache;
-        codec->volatile_register = wm9090_volatile;
-
-        ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
-        if (ret != 0) {
-                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
-                goto err;
-        }
-
-        memcpy(&wm9090->reg_cache, wm9090_reg_defaults,
-               sizeof(wm9090->reg_cache));
-
-        ret = snd_soc_read(codec, WM9090_SOFTWARE_RESET);
+        ret =  snd_soc_register_codec(&i2c->dev,
+                        &soc_codec_dev_wm9090,  NULL, 0);
         if (ret < 0)
-                goto err;
-        if (ret != wm9090_reg_defaults[WM9090_SOFTWARE_RESET]) {
-                dev_err(&i2c->dev, "Device is not a WM9090, ID=%x\n", ret);
-                ret = -EINVAL;
-                goto err;
-        }
-
-        ret = snd_soc_write(codec, WM9090_SOFTWARE_RESET, 0);
-        if (ret < 0)
-                goto err;
-
-        /* Configure some defaults; they will be written out when we
-         * bring the bias up.
-         */
-        wm9090->reg_cache[WM9090_IN1_LINE_INPUT_A_VOLUME] |= WM9090_IN1_VU
-                | WM9090_IN1A_ZC;
-        wm9090->reg_cache[WM9090_IN1_LINE_INPUT_B_VOLUME] |= WM9090_IN1_VU
-                | WM9090_IN1B_ZC;
-        wm9090->reg_cache[WM9090_IN2_LINE_INPUT_A_VOLUME] |= WM9090_IN2_VU
-                | WM9090_IN2A_ZC;
-        wm9090->reg_cache[WM9090_IN2_LINE_INPUT_B_VOLUME] |= WM9090_IN2_VU
-                | WM9090_IN2B_ZC;
-        wm9090->reg_cache[WM9090_SPEAKER_VOLUME_LEFT] |=
-                WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC;
-        wm9090->reg_cache[WM9090_LEFT_OUTPUT_VOLUME] |= 
-                WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC;
-        wm9090->reg_cache[WM9090_RIGHT_OUTPUT_VOLUME] |=
-                WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC;
-
-        wm9090->reg_cache[WM9090_CLOCKING_1] |= WM9090_TOCLK_ENA;
-
-        wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-
-        ret = snd_soc_register_codec(codec);
-        if (ret != 0) {
-                dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
-                goto err_bias;
-        }
-
-        return 0;
-
-err_bias:
-        wm9090_set_bias_level(codec, SND_SOC_BIAS_OFF);
-err:
-        kfree(wm9090);
-        i2c_set_clientdata(i2c, NULL);
-        wm9090_codec = NULL;
-
+                kfree(wm9090);
         return ret;
 }
 
-static int wm9090_i2c_remove(struct i2c_client *i2c)
+static int __devexit wm9090_i2c_remove(struct i2c_client *i2c)
 {
         struct wm9090_priv *wm9090 = i2c_get_clientdata(i2c);
-        struct snd_soc_codec *codec = &wm9090->codec;
 
-        snd_soc_unregister_codec(codec);
-        wm9090_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        snd_soc_unregister_codec(&i2c->dev);
         kfree(wm9090);
-        wm9090_codec = NULL;
 
         return 0;
 }
@@ -748,7 +690,7 @@ MODULE_DEVICE_TABLE(i2c, wm9090_id);
 
 static struct i2c_driver wm9090_i2c_driver = {
         .driver = {
-                .name = "wm9090",
+                .name = "wm9090-codec",
                 .owner = THIS_MODULE,
         },
         .probe = wm9090_i2c_probe,
diff --git a/sound/soc/codecs/wm9090.h b/sound/soc/codecs/wm9090.h
index b08eab932a5b..29b9d9fc70b4 100644
--- a/sound/soc/codecs/wm9090.h
+++ b/sound/soc/codecs/wm9090.h
@@ -23,8 +23,6 @@
 #ifndef __WM9090_H
 #define __WM9090_H
 
-extern struct snd_soc_codec_device soc_codec_dev_wm9090;
-
 /*
  * Register values.
  */
diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c
index 8793341849d1..646b58dda849 100644
--- a/sound/soc/codecs/wm9705.c
+++ b/sound/soc/codecs/wm9705.c
@@ -19,7 +19,6 @@
 #include <sound/ac97_codec.h>
 #include <sound/initval.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 
 #include "wm9705.h"
 
@@ -143,7 +142,7 @@ static const struct snd_soc_dapm_widget wm9705_dapm_widgets[] = {
  * constantly enabled, we use the mutes on those inputs to simulate such
  * controls.
  */
-static const struct snd_soc_dapm_route audio_map[] = {
+static const struct snd_soc_dapm_route wm9705_audio_map[] = {
         /* HP mixer */
         {"HP Mixer", "PCBeep Playback Switch", "PCBEEP PGA"},
         {"HP Mixer", "CD Playback Switch", "CD PGA"},
@@ -201,15 +200,6 @@ static const struct snd_soc_dapm_route audio_map[] = {
         {"Right ADC", NULL, "ADC PGA"},
 };
 
-static int wm9705_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, wm9705_dapm_widgets,
-                                        ARRAY_SIZE(wm9705_dapm_widgets));
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
-
-        return 0;
-}
-
 /* We use a register cache to enhance read performance. */
 static unsigned int ac97_read(struct snd_soc_codec *codec, unsigned int reg)
 {
@@ -248,8 +238,7 @@ static int ac97_prepare(struct snd_pcm_substream *substream,
 {
         struct snd_pcm_runtime *runtime = substream->runtime;
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         int reg;
         u16 vra;
 
@@ -273,9 +262,9 @@ static struct snd_soc_dai_ops wm9705_dai_ops = {
         .prepare        = ac97_prepare,
 };
 
-struct snd_soc_dai wm9705_dai[] = {
+static struct snd_soc_dai_driver wm9705_dai[] = {
         {
-                .name = "AC97 HiFi",
+                .name = "wm9705-hifi",
                 .ac97_control = 1,
                 .playback = {
                         .stream_name = "HiFi Playback",
@@ -294,7 +283,7 @@ struct snd_soc_dai wm9705_dai[] = {
                 .ops = &wm9705_dai_ops,
         },
         {
-                .name = "AC97 Aux",
+                .name = "wm9705-aux",
                 .playback = {
                         .stream_name = "Aux Playback",
                         .channels_min = 1,
@@ -304,7 +293,6 @@ struct snd_soc_dai wm9705_dai[] = {
                 },
         }
 };
-EXPORT_SYMBOL_GPL(wm9705_dai);
 
 static int wm9705_reset(struct snd_soc_codec *codec)
 {
@@ -318,20 +306,15 @@ static int wm9705_reset(struct snd_soc_codec *codec)
 }
 
 #ifdef CONFIG_PM
-static int wm9705_soc_suspend(struct platform_device *pdev, pm_message_t msg)
+static int wm9705_soc_suspend(struct snd_soc_codec *codec, pm_message_t msg)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         soc_ac97_ops.write(codec->ac97, AC97_POWERDOWN, 0xffff);
 
         return 0;
 }
 
-static int wm9705_soc_resume(struct platform_device *pdev)
+static int wm9705_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i, ret;
         u16 *cache = codec->reg_cache;
 
@@ -352,94 +335,88 @@ static int wm9705_soc_resume(struct platform_device *pdev)
 #define wm9705_soc_resume NULL
 #endif
 
-static int wm9705_soc_probe(struct platform_device *pdev)
+static int wm9705_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
         int ret = 0;
 
         printk(KERN_INFO "WM9705 SoC Audio Codec\n");
 
-        socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec),
-                                      GFP_KERNEL);
-        if (socdev->card->codec == NULL)
-                return -ENOMEM;
-        codec = socdev->card->codec;
-        mutex_init(&codec->mutex);
-
-        codec->reg_cache = kmemdup(wm9705_reg, sizeof(wm9705_reg), GFP_KERNEL);
-        if (codec->reg_cache == NULL) {
-                ret = -ENOMEM;
-                goto cache_err;
-        }
-        codec->reg_cache_size = sizeof(wm9705_reg);
-        codec->reg_cache_step = 2;
-
-        codec->name = "WM9705";
-        codec->owner = THIS_MODULE;
-        codec->dai = wm9705_dai;
-        codec->num_dai = ARRAY_SIZE(wm9705_dai);
-        codec->write = ac97_write;
-        codec->read = ac97_read;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
         ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
         if (ret < 0) {
                 printk(KERN_ERR "wm9705: failed to register AC97 codec\n");
-                goto codec_err;
+                return ret;
         }
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0)
-                goto pcm_err;
-
         ret = wm9705_reset(codec);
         if (ret)
                 goto reset_err;
 
         snd_soc_add_controls(codec, wm9705_snd_ac97_controls,
                                 ARRAY_SIZE(wm9705_snd_ac97_controls));
-        wm9705_add_widgets(codec);
 
         return 0;
 
 reset_err:
-        snd_soc_free_pcms(socdev);
-pcm_err:
         snd_soc_free_ac97_codec(codec);
-codec_err:
-        kfree(codec->reg_cache);
-cache_err:
-        kfree(socdev->card->codec);
-        socdev->card->codec = NULL;
         return ret;
 }
 
-static int wm9705_soc_remove(struct platform_device *pdev)
+static int wm9705_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec == NULL)
-                return 0;
-
-        snd_soc_dapm_free(socdev);
-        snd_soc_free_pcms(socdev);
         snd_soc_free_ac97_codec(codec);
-        kfree(codec->reg_cache);
-        kfree(codec);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_wm9705 = {
+static struct snd_soc_codec_driver soc_codec_dev_wm9705 = {
         .probe =        wm9705_soc_probe,
         .remove =       wm9705_soc_remove,
         .suspend =      wm9705_soc_suspend,
         .resume =       wm9705_soc_resume,
+        .read = ac97_read,
+        .write = ac97_write,
+        .reg_cache_size = ARRAY_SIZE(wm9705_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_step = 2,
+        .reg_cache_default = wm9705_reg,
+        .dapm_widgets = wm9705_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm9705_dapm_widgets),
+        .dapm_routes = wm9705_audio_map,
+        .num_dapm_routes = ARRAY_SIZE(wm9705_audio_map),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm9705);
+
+static __devinit int wm9705_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_wm9705, wm9705_dai, ARRAY_SIZE(wm9705_dai));
+}
+
+static int __devexit wm9705_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver wm9705_codec_driver = {
+        .driver = {
+                        .name = "wm9705-codec",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = wm9705_probe,
+        .remove = __devexit_p(wm9705_remove),
+};
+
+static int __init wm9705_init(void)
+{
+        return platform_driver_register(&wm9705_codec_driver);
+}
+module_init(wm9705_init);
+
+static void __exit wm9705_exit(void)
+{
+        platform_driver_unregister(&wm9705_codec_driver);
+}
+module_exit(wm9705_exit);
 
 MODULE_DESCRIPTION("ASoC WM9705 driver");
 MODULE_AUTHOR("Ian Molton");
diff --git a/sound/soc/codecs/wm9705.h b/sound/soc/codecs/wm9705.h
index d380f110f9e2..23ea9ce47359 100644
--- a/sound/soc/codecs/wm9705.h
+++ b/sound/soc/codecs/wm9705.h
@@ -8,7 +8,4 @@
 #define WM9705_DAI_AC97_HIFI    0
 #define WM9705_DAI_AC97_AUX     1
 
-extern struct snd_soc_dai wm9705_dai[2];
-extern struct snd_soc_codec_device soc_codec_dev_wm9705;
-
 #endif
diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c
index 28790a2ffe8d..90117f8156e8 100644
--- a/sound/soc/codecs/wm9712.c
+++ b/sound/soc/codecs/wm9712.c
@@ -20,7 +20,6 @@
 #include <sound/ac97_codec.h>
 #include <sound/initval.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include "wm9712.h"
 
 #define WM9712_VERSION "0.4"
@@ -333,7 +332,7 @@ SND_SOC_DAPM_INPUT("MIC1"),
 SND_SOC_DAPM_INPUT("MIC2"),
 };
 
-static const struct snd_soc_dapm_route audio_map[] = {
+static const struct snd_soc_dapm_route wm9712_audio_map[] = {
         /* virtual mixer - mixes left & right channels for spk and mono */
         {"AC97 Mixer", NULL, "Left DAC"},
         {"AC97 Mixer", NULL, "Right DAC"},
@@ -430,16 +429,6 @@ static const struct snd_soc_dapm_route audio_map[] = {
         {"ROUT2", NULL, "Speaker PGA"},
 };
 
-static int wm9712_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, wm9712_dapm_widgets,
-                                  ARRAY_SIZE(wm9712_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
-
-        return 0;
-}
-
 static unsigned int ac97_read(struct snd_soc_codec *codec,
         unsigned int reg)
 {
@@ -478,8 +467,7 @@ static int ac97_prepare(struct snd_pcm_substream *substream,
 {
         struct snd_pcm_runtime *runtime = substream->runtime;
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec =rtd->codec;
         int reg;
         u16 vra;
 
@@ -499,8 +487,7 @@ static int ac97_aux_prepare(struct snd_pcm_substream *substream,
 {
         struct snd_pcm_runtime *runtime = substream->runtime;
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
-        struct snd_soc_device *socdev = rtd->socdev;
-        struct snd_soc_codec *codec = socdev->card->codec;
+        struct snd_soc_codec *codec = rtd->codec;
         u16 vra, xsle;
 
         vra = ac97_read(codec, AC97_EXTENDED_STATUS);
@@ -526,9 +513,9 @@ static struct snd_soc_dai_ops wm9712_dai_ops_aux = {
         .prepare        = ac97_aux_prepare,
 };
 
-struct snd_soc_dai wm9712_dai[] = {
+static struct snd_soc_dai_driver wm9712_dai[] = {
 {
-        .name = "AC97 HiFi",
+        .name = "wm9712-hifi",
         .ac97_control = 1,
         .playback = {
                 .stream_name = "HiFi Playback",
@@ -545,7 +532,7 @@ struct snd_soc_dai wm9712_dai[] = {
         .ops = &wm9712_dai_ops_hifi,
 },
 {
-        .name = "AC97 Aux",
+        .name = "wm9712-aux",
         .playback = {
                 .stream_name = "Aux Playback",
                 .channels_min = 1,
@@ -555,7 +542,6 @@ struct snd_soc_dai wm9712_dai[] = {
         .ops = &wm9712_dai_ops_aux,
 }
 };
-EXPORT_SYMBOL_GPL(wm9712_dai);
 
 static int wm9712_set_bias_level(struct snd_soc_codec *codec,
                                  enum snd_soc_bias_level level)
@@ -573,7 +559,7 @@ static int wm9712_set_bias_level(struct snd_soc_codec *codec,
                 ac97_write(codec, AC97_POWERDOWN, 0xffff);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
@@ -597,20 +583,15 @@ err:
         return -EIO;
 }
 
-static int wm9712_soc_suspend(struct platform_device *pdev,
+static int wm9712_soc_suspend(struct snd_soc_codec *codec,
         pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
         wm9712_set_bias_level(codec, SND_SOC_BIAS_OFF);
         return 0;
 }
 
-static int wm9712_soc_resume(struct platform_device *pdev)
+static int wm9712_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         int i, ret;
         u16 *cache = codec->reg_cache;
 
@@ -635,51 +616,18 @@ static int wm9712_soc_resume(struct platform_device *pdev)
         return ret;
 }
 
-static int wm9712_soc_probe(struct platform_device *pdev)
+static int wm9712_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
         int ret = 0;
 
         printk(KERN_INFO "WM9711/WM9712 SoC Audio Codec %s\n", WM9712_VERSION);
 
-        socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec),
-                                      GFP_KERNEL);
-        if (socdev->card->codec == NULL)
-                return -ENOMEM;
-        codec = socdev->card->codec;
-        mutex_init(&codec->mutex);
-
-        codec->reg_cache = kmemdup(wm9712_reg, sizeof(wm9712_reg), GFP_KERNEL);
-
-        if (codec->reg_cache == NULL) {
-                ret = -ENOMEM;
-                goto cache_err;
-        }
-        codec->reg_cache_size = sizeof(wm9712_reg);
-        codec->reg_cache_step = 2;
-
-        codec->name = "WM9712";
-        codec->owner = THIS_MODULE;
-        codec->dai = wm9712_dai;
-        codec->num_dai = ARRAY_SIZE(wm9712_dai);
-        codec->write = ac97_write;
-        codec->read = ac97_read;
-        codec->set_bias_level = wm9712_set_bias_level;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
-
         ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
         if (ret < 0) {
                 printk(KERN_ERR "wm9712: failed to register AC97 codec\n");
-                goto codec_err;
+                return ret;
         }
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0)
-                goto pcm_err;
-
         ret = wm9712_reset(codec, 0);
         if (ret < 0) {
                 printk(KERN_ERR "Failed to reset WM9712: AC97 link error\n");
@@ -692,47 +640,71 @@ static int wm9712_soc_probe(struct platform_device *pdev)
         wm9712_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
         snd_soc_add_controls(codec, wm9712_snd_ac97_controls,
                                 ARRAY_SIZE(wm9712_snd_ac97_controls));
-        wm9712_add_widgets(codec);
 
         return 0;
 
 reset_err:
-        snd_soc_free_pcms(socdev);
-pcm_err:
         snd_soc_free_ac97_codec(codec);
-
-codec_err:
-        kfree(codec->reg_cache);
-
-cache_err:
-        kfree(socdev->card->codec);
-        socdev->card->codec = NULL;
         return ret;
 }
 
-static int wm9712_soc_remove(struct platform_device *pdev)
+static int wm9712_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec == NULL)
-                return 0;
-
-        snd_soc_dapm_free(socdev);
-        snd_soc_free_pcms(socdev);
         snd_soc_free_ac97_codec(codec);
-        kfree(codec->reg_cache);
-        kfree(codec);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_wm9712 = {
+static struct snd_soc_codec_driver soc_codec_dev_wm9712 = {
         .probe =        wm9712_soc_probe,
         .remove =       wm9712_soc_remove,
         .suspend =      wm9712_soc_suspend,
         .resume =       wm9712_soc_resume,
+        .read = ac97_read,
+        .write = ac97_write,
+        .set_bias_level = wm9712_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm9712_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_step = 2,
+        .reg_cache_default = wm9712_reg,
+        .dapm_widgets = wm9712_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm9712_dapm_widgets),
+        .dapm_routes = wm9712_audio_map,
+        .num_dapm_routes = ARRAY_SIZE(wm9712_audio_map),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm9712);
+
+static __devinit int wm9712_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_wm9712, wm9712_dai, ARRAY_SIZE(wm9712_dai));
+}
+
+static int __devexit wm9712_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver wm9712_codec_driver = {
+        .driver = {
+                        .name = "wm9712-codec",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = wm9712_probe,
+        .remove = __devexit_p(wm9712_remove),
+};
+
+static int __init wm9712_init(void)
+{
+        return platform_driver_register(&wm9712_codec_driver);
+}
+module_init(wm9712_init);
+
+static void __exit wm9712_exit(void)
+{
+        platform_driver_unregister(&wm9712_codec_driver);
+}
+module_exit(wm9712_exit);
 
 MODULE_DESCRIPTION("ASoC WM9711/WM9712 driver");
 MODULE_AUTHOR("Liam Girdwood");
diff --git a/sound/soc/codecs/wm9712.h b/sound/soc/codecs/wm9712.h
index d29e8a18ca6d..fb69c3aa4ed0 100644
--- a/sound/soc/codecs/wm9712.h
+++ b/sound/soc/codecs/wm9712.h
@@ -8,7 +8,4 @@
 #define WM9712_DAI_AC97_HIFI    0
 #define WM9712_DAI_AC97_AUX             1
 
-extern struct snd_soc_dai wm9712_dai[2];
-extern struct snd_soc_codec_device soc_codec_dev_wm9712;
-
 #endif
diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c
index 34e0c91092fa..7167cb6787db 100644
--- a/sound/soc/codecs/wm9713.c
+++ b/sound/soc/codecs/wm9713.c
@@ -26,7 +26,6 @@
 #include <sound/pcm_params.h>
 #include <sound/tlv.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 
 #include "wm9713.h"
 
@@ -488,7 +487,7 @@ SND_SOC_DAPM_INPUT("MIC2B"),
 SND_SOC_DAPM_VMID("VMID"),
 };
 
-static const struct snd_soc_dapm_route audio_map[] = {
+static const struct snd_soc_dapm_route wm9713_audio_map[] = {
         /* left HP mixer */
         {"Left HP Mixer", "Beep Playback Switch",    "PCBEEP"},
         {"Left HP Mixer", "Voice Playback Switch",   "Voice DAC"},
@@ -645,16 +644,6 @@ static const struct snd_soc_dapm_route audio_map[] = {
         {"Capture Mono Mux", "Right", "Right Capture Source"},
 };
 
-static int wm9713_add_widgets(struct snd_soc_codec *codec)
-{
-        snd_soc_dapm_new_controls(codec, wm9713_dapm_widgets,
-                                  ARRAY_SIZE(wm9713_dapm_widgets));
-
-        snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
-
-        return 0;
-}
-
 static unsigned int ac97_read(struct snd_soc_codec *codec,
         unsigned int reg)
 {
@@ -1057,9 +1046,9 @@ static struct snd_soc_dai_ops wm9713_dai_ops_voice = {
         .set_tristate   = wm9713_set_dai_tristate,
 };
 
-struct snd_soc_dai wm9713_dai[] = {
+static struct snd_soc_dai_driver wm9713_dai[] = {
 {
-        .name = "AC97 HiFi",
+        .name = "wm9713-hifi",
         .ac97_control = 1,
         .playback = {
                 .stream_name = "HiFi Playback",
@@ -1076,7 +1065,7 @@ struct snd_soc_dai wm9713_dai[] = {
         .ops = &wm9713_dai_ops_hifi,
         },
         {
-        .name = "AC97 Aux",
+        .name = "wm9713-aux",
         .playback = {
                 .stream_name = "Aux Playback",
                 .channels_min = 1,
@@ -1086,7 +1075,7 @@ struct snd_soc_dai wm9713_dai[] = {
         .ops = &wm9713_dai_ops_aux,
         },
         {
-        .name = "WM9713 Voice",
+        .name = "wm9713-voice",
         .playback = {
                 .stream_name = "Voice Playback",
                 .channels_min = 1,
@@ -1103,7 +1092,6 @@ struct snd_soc_dai wm9713_dai[] = {
         .symmetric_rates = 1,
         },
 };
-EXPORT_SYMBOL_GPL(wm9713_dai);
 
 int wm9713_reset(struct snd_soc_codec *codec, int try_warm)
 {
@@ -1148,15 +1136,13 @@ static int wm9713_set_bias_level(struct snd_soc_codec *codec,
                 ac97_write(codec, AC97_POWERDOWN, 0xffff);
                 break;
         }
-        codec->bias_level = level;
+        codec->dapm.bias_level = level;
         return 0;
 }
 
-static int wm9713_soc_suspend(struct platform_device *pdev,
+static int wm9713_soc_suspend(struct snd_soc_codec *codec,
         pm_message_t state)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         u16 reg;
 
         /* Disable everything except touchpanel - that will be handled
@@ -1171,10 +1157,8 @@ static int wm9713_soc_suspend(struct platform_device *pdev,
         return 0;
 }
 
-static int wm9713_soc_resume(struct platform_device *pdev)
+static int wm9713_soc_resume(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
         struct wm9713_priv *wm9713 = snd_soc_codec_get_drvdata(codec);
         int i, ret;
         u16 *cache = codec->reg_cache;
@@ -1204,53 +1188,20 @@ static int wm9713_soc_resume(struct platform_device *pdev)
         return ret;
 }
 
-static int wm9713_soc_probe(struct platform_device *pdev)
+static int wm9713_soc_probe(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec;
+        struct wm9713_priv *wm9713;
         int ret = 0, reg;
 
-        socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec),
-                                      GFP_KERNEL);
-        if (socdev->card->codec == NULL)
+        wm9713 = kzalloc(sizeof(struct wm9713_priv), GFP_KERNEL);
+        if (wm9713 == NULL)
                 return -ENOMEM;
-        codec = socdev->card->codec;
-        mutex_init(&codec->mutex);
-
-        codec->reg_cache = kmemdup(wm9713_reg, sizeof(wm9713_reg), GFP_KERNEL);
-        if (codec->reg_cache == NULL) {
-                ret = -ENOMEM;
-                goto cache_err;
-        }
-        codec->reg_cache_size = sizeof(wm9713_reg);
-        codec->reg_cache_step = 2;
-
-        snd_soc_codec_set_drvdata(codec, kzalloc(sizeof(struct wm9713_priv),
-                                                 GFP_KERNEL));
-        if (snd_soc_codec_get_drvdata(codec) == NULL) {
-                ret = -ENOMEM;
-                goto priv_err;
-        }
-
-        codec->name = "WM9713";
-        codec->owner = THIS_MODULE;
-        codec->dai = wm9713_dai;
-        codec->num_dai = ARRAY_SIZE(wm9713_dai);
-        codec->write = ac97_write;
-        codec->read = ac97_read;
-        codec->set_bias_level = wm9713_set_bias_level;
-        INIT_LIST_HEAD(&codec->dapm_widgets);
-        INIT_LIST_HEAD(&codec->dapm_paths);
+        snd_soc_codec_set_drvdata(codec, wm9713);
 
         ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
         if (ret < 0)
                 goto codec_err;
 
-        /* register pcms */
-        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
-        if (ret < 0)
-                goto pcm_err;
-
         /* do a cold reset for the controller and then try
          * a warm reset followed by an optional cold reset for codec */
         wm9713_reset(codec, 0);
@@ -1268,51 +1219,75 @@ static int wm9713_soc_probe(struct platform_device *pdev)
 
         snd_soc_add_controls(codec, wm9713_snd_ac97_controls,
                                 ARRAY_SIZE(wm9713_snd_ac97_controls));
-        wm9713_add_widgets(codec);
 
         return 0;
 
 reset_err:
-        snd_soc_free_pcms(socdev);
-pcm_err:
         snd_soc_free_ac97_codec(codec);
-
 codec_err:
-        kfree(snd_soc_codec_get_drvdata(codec));
-
-priv_err:
-        kfree(codec->reg_cache);
-
-cache_err:
-        kfree(socdev->card->codec);
-        socdev->card->codec = NULL;
+        kfree(wm9713);
         return ret;
 }
 
-static int wm9713_soc_remove(struct platform_device *pdev)
+static int wm9713_soc_remove(struct snd_soc_codec *codec)
 {
-        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
-        struct snd_soc_codec *codec = socdev->card->codec;
-
-        if (codec == NULL)
-                return 0;
-
-        snd_soc_dapm_free(socdev);
-        snd_soc_free_pcms(socdev);
+        struct wm9713_priv *wm9713 = snd_soc_codec_get_drvdata(codec);
         snd_soc_free_ac97_codec(codec);
-        kfree(snd_soc_codec_get_drvdata(codec));
-        kfree(codec->reg_cache);
-        kfree(codec);
+        kfree(wm9713);
         return 0;
 }
 
-struct snd_soc_codec_device soc_codec_dev_wm9713 = {
+static struct snd_soc_codec_driver soc_codec_dev_wm9713 = {
         .probe =        wm9713_soc_probe,
         .remove =       wm9713_soc_remove,
         .suspend =      wm9713_soc_suspend,
         .resume =       wm9713_soc_resume,
+        .read = ac97_read,
+        .write = ac97_write,
+        .set_bias_level = wm9713_set_bias_level,
+        .reg_cache_size = ARRAY_SIZE(wm9713_reg),
+        .reg_word_size = sizeof(u16),
+        .reg_cache_step = 2,
+        .reg_cache_default = wm9713_reg,
+        .dapm_widgets = wm9713_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(wm9713_dapm_widgets),
+        .dapm_routes = wm9713_audio_map,
+        .num_dapm_routes = ARRAY_SIZE(wm9713_audio_map),
+};
+
+static __devinit int wm9713_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_codec(&pdev->dev,
+                        &soc_codec_dev_wm9713, wm9713_dai, ARRAY_SIZE(wm9713_dai));
+}
+
+static int __devexit wm9713_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_codec(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver wm9713_codec_driver = {
+        .driver = {
+                        .name = "wm9713-codec",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = wm9713_probe,
+        .remove = __devexit_p(wm9713_remove),
 };
-EXPORT_SYMBOL_GPL(soc_codec_dev_wm9713);
+
+static int __init wm9713_init(void)
+{
+        return platform_driver_register(&wm9713_codec_driver);
+}
+module_init(wm9713_init);
+
+static void __exit wm9713_exit(void)
+{
+        platform_driver_unregister(&wm9713_codec_driver);
+}
+module_exit(wm9713_exit);
 
 MODULE_DESCRIPTION("ASoC WM9713/WM9714 driver");
 MODULE_AUTHOR("Liam Girdwood");
diff --git a/sound/soc/codecs/wm9713.h b/sound/soc/codecs/wm9713.h
index 63b8d81756e3..793da863a03d 100644
--- a/sound/soc/codecs/wm9713.h
+++ b/sound/soc/codecs/wm9713.h
@@ -45,9 +45,6 @@
 #define WM9713_DAI_AC97_AUX             1
 #define WM9713_DAI_PCM_VOICE    2
 
-extern struct snd_soc_codec_device soc_codec_dev_wm9713;
-extern struct snd_soc_dai wm9713_dai[3];
-
 int wm9713_reset(struct snd_soc_codec *codec,  int try_warm);
 
 #endif
diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
index 2cb81538cd91..9e370d14ad88 100644
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -22,7 +22,6 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 
@@ -83,7 +82,8 @@ static void wait_for_dc_servo(struct snd_soc_codec *codec, unsigned int op)
         } while (reg & op && count < 400);
 
         if (reg & op)
-                dev_err(codec->dev, "Timed out waiting for DC Servo\n");
+                dev_err(codec->dev, "Timed out waiting for DC Servo %x\n",
+                        op);
 }
 
 /*
@@ -92,54 +92,73 @@ static void wait_for_dc_servo(struct snd_soc_codec *codec, unsigned int op)
 static void calibrate_dc_servo(struct snd_soc_codec *codec)
 {
         struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
+        s8 offset;
         u16 reg, reg_l, reg_r, dcs_cfg;
 
-        /* Set for 32 series updates */
-        snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
-                            WM8993_DCS_SERIES_NO_01_MASK,
-                            32 << WM8993_DCS_SERIES_NO_01_SHIFT);
-        wait_for_dc_servo(codec,
-                          WM8993_DCS_TRIG_SERIES_0 | WM8993_DCS_TRIG_SERIES_1);
+        /* If we're using a digital only path and have a previously
+         * callibrated DC servo offset stored then use that. */
+        if (hubs->class_w && hubs->class_w_dcs) {
+                dev_dbg(codec->dev, "Using cached DC servo offset %x\n",
+                        hubs->class_w_dcs);
+                snd_soc_write(codec, WM8993_DC_SERVO_3, hubs->class_w_dcs);
+                wait_for_dc_servo(codec,
+                                  WM8993_DCS_TRIG_DAC_WR_0 |
+                                  WM8993_DCS_TRIG_DAC_WR_1);
+                return;
+        }
+
+        /* Devices not using a DCS code correction have startup mode */
+        if (hubs->dcs_codes) {
+                /* Set for 32 series updates */
+                snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
+                                    WM8993_DCS_SERIES_NO_01_MASK,
+                                    32 << WM8993_DCS_SERIES_NO_01_SHIFT);
+                wait_for_dc_servo(codec,
+                                  WM8993_DCS_TRIG_SERIES_0 |
+                                  WM8993_DCS_TRIG_SERIES_1);
+        } else {
+                wait_for_dc_servo(codec,
+                                  WM8993_DCS_TRIG_STARTUP_0 |
+                                  WM8993_DCS_TRIG_STARTUP_1);
+        }
+
+        /* Different chips in the family support different readback
+         * methods.
+         */
+        switch (hubs->dcs_readback_mode) {
+        case 0:
+                reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
+                        & WM8993_DCS_INTEG_CHAN_0_MASK;
+                reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
+                        & WM8993_DCS_INTEG_CHAN_1_MASK;
+                break;
+        case 1:
+                reg = snd_soc_read(codec, WM8993_DC_SERVO_3);
+                reg_l = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
+                        >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
+                reg_r = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
+                break;
+        default:
+                WARN(1, "Unknown DCS readback method\n");
+                break;
+        }
+
+        dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r);
 
         /* Apply correction to DC servo result */
         if (hubs->dcs_codes) {
                 dev_dbg(codec->dev, "Applying %d code DC servo correction\n",
                         hubs->dcs_codes);
 
-                /* Different chips in the family support different
-                 * readback methods.
-                 */
-                switch (hubs->dcs_readback_mode) {
-                case 0:
-                        reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
-                                & WM8993_DCS_INTEG_CHAN_0_MASK;;
-                        reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
-                                & WM8993_DCS_INTEG_CHAN_1_MASK;
-                        break;
-                case 1:
-                        reg = snd_soc_read(codec, WM8993_DC_SERVO_3);
-                        reg_l = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
-                                >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
-                        reg_r = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
-                        break;
-                default:
-                        WARN(1, "Unknown DCS readback method");
-                        break;
-                }
-
-                dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r);
-
                 /* HPOUT1L */
-                if (reg_l + hubs->dcs_codes > 0 &&
-                    reg_l + hubs->dcs_codes < 0xff)
-                        reg_l += hubs->dcs_codes;
-                dcs_cfg = reg_l << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
+                offset = reg_l;
+                offset += hubs->dcs_codes;
+                dcs_cfg = (u8)offset << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
 
                 /* HPOUT1R */
-                if (reg_r + hubs->dcs_codes > 0 &&
-                    reg_r + hubs->dcs_codes < 0xff)
-                        reg_r += hubs->dcs_codes;
-                dcs_cfg |= reg_r;
+                offset = reg_r;
+                offset += hubs->dcs_codes;
+                dcs_cfg |= (u8)offset;
 
                 dev_dbg(codec->dev, "DCS result: %x\n", dcs_cfg);
 
@@ -148,7 +167,15 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec)
                 wait_for_dc_servo(codec,
                                   WM8993_DCS_TRIG_DAC_WR_0 |
                                   WM8993_DCS_TRIG_DAC_WR_1);
+        } else {
+                dcs_cfg = reg_l << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
+                dcs_cfg |= reg_r;
         }
+
+        /* Save the callibrated offset if we're in class W mode and
+         * therefore don't have any analogue signal mixed in. */
+        if (hubs->class_w)
+                hubs->class_w_dcs = dcs_cfg;
 }
 
 /*
@@ -163,6 +190,9 @@ static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
 
         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 
+        /* Updating the analogue gains invalidates the DC servo cache */
+        hubs->class_w_dcs = 0;
+
         /* If we're applying an offset correction then updating the
          * callibration would be likely to introduce further offsets. */
         if (hubs->dcs_codes)
@@ -185,23 +215,23 @@ static const struct snd_kcontrol_new analogue_snd_controls[] = {
 SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
                inpga_tlv),
 SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
-SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 0),
+SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
 
 SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
                inpga_tlv),
 SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
-SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 0),
+SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
 
 
 SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
                inpga_tlv),
 SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
-SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 0),
+SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
 
 SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
                inpga_tlv),
 SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
-SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 0),
+SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
 
 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
                inmix_sw_tlv),
@@ -293,7 +323,7 @@ SOC_DOUBLE_R("Speaker Switch",
 SOC_DOUBLE_R("Speaker ZC Switch",
              WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
              7, 1, 0),
-SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 0, 3, 7, 0,
+SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 3, 0, 7, 0,
                spkboost_tlv),
 SOC_ENUM("Speaker Reference", speaker_ref),
 SOC_ENUM("Speaker Mode", speaker_mode),
@@ -645,6 +675,9 @@ SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
 };
 
 static const struct snd_soc_dapm_route analogue_routes[] = {
+        { "MICBIAS1", NULL, "CLK_SYS" },
+        { "MICBIAS2", NULL, "CLK_SYS" },
+
         { "IN1L PGA", "IN1LP Switch", "IN1LP" },
         { "IN1L PGA", "IN1LN Switch", "IN1LN" },
 
@@ -707,12 +740,12 @@ static const struct snd_soc_dapm_route analogue_routes[] = {
 
         { "SPKL", "Input Switch", "MIXINL" },
         { "SPKL", "IN1LP Switch", "IN1LP" },
-        { "SPKL", "Output Switch", "Left Output Mixer" },
+        { "SPKL", "Output Switch", "Left Output PGA" },
         { "SPKL", NULL, "TOCLK" },
 
         { "SPKR", "Input Switch", "MIXINR" },
         { "SPKR", "IN1RP Switch", "IN1RP" },
-        { "SPKR", "Output Switch", "Right Output Mixer" },
+        { "SPKR", "Output Switch", "Right Output PGA" },
         { "SPKR", NULL, "TOCLK" },
 
         { "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
@@ -734,8 +767,8 @@ static const struct snd_soc_dapm_route analogue_routes[] = {
         { "SPKOUTRP", NULL, "SPKR Driver" },
         { "SPKOUTRN", NULL, "SPKR Driver" },
 
-        { "Left Headphone Mux", "Mixer", "Left Output Mixer" },
-        { "Right Headphone Mux", "Mixer", "Right Output Mixer" },
+        { "Left Headphone Mux", "Mixer", "Left Output PGA" },
+        { "Right Headphone Mux", "Mixer", "Right Output PGA" },
 
         { "Headphone PGA", NULL, "Left Headphone Mux" },
         { "Headphone PGA", NULL, "Right Headphone Mux" },
@@ -754,17 +787,17 @@ static const struct snd_soc_dapm_route analogue_routes[] = {
 static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
         { "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
         { "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
-        { "LINEOUT1 Mixer", "Output Switch", "Left Output Mixer" },
+        { "LINEOUT1 Mixer", "Output Switch", "Left Output PGA" },
 
         { "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
         { "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
 };
 
 static const struct snd_soc_dapm_route lineout1_se_routes[] = {
-        { "LINEOUT1N Mixer", "Left Output Switch", "Left Output Mixer" },
-        { "LINEOUT1N Mixer", "Right Output Switch", "Left Output Mixer" },
+        { "LINEOUT1N Mixer", "Left Output Switch", "Left Output PGA" },
+        { "LINEOUT1N Mixer", "Right Output Switch", "Right Output PGA" },
 
-        { "LINEOUT1P Mixer", "Left Output Switch", "Left Output Mixer" },
+        { "LINEOUT1P Mixer", "Left Output Switch", "Left Output PGA" },
 
         { "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
         { "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
@@ -773,17 +806,17 @@ static const struct snd_soc_dapm_route lineout1_se_routes[] = {
 static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
         { "LINEOUT2 Mixer", "IN2L Switch", "IN2L PGA" },
         { "LINEOUT2 Mixer", "IN2R Switch", "IN2R PGA" },
-        { "LINEOUT2 Mixer", "Output Switch", "Right Output Mixer" },
+        { "LINEOUT2 Mixer", "Output Switch", "Right Output PGA" },
 
         { "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
         { "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
 };
 
 static const struct snd_soc_dapm_route lineout2_se_routes[] = {
-        { "LINEOUT2N Mixer", "Left Output Switch", "Left Output Mixer" },
-        { "LINEOUT2N Mixer", "Right Output Switch", "Left Output Mixer" },
+        { "LINEOUT2N Mixer", "Left Output Switch", "Left Output PGA" },
+        { "LINEOUT2N Mixer", "Right Output Switch", "Right Output PGA" },
 
-        { "LINEOUT2P Mixer", "Right Output Switch", "Right Output Mixer" },
+        { "LINEOUT2P Mixer", "Right Output Switch", "Right Output PGA" },
 
         { "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
         { "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
@@ -791,6 +824,8 @@ static const struct snd_soc_dapm_route lineout2_se_routes[] = {
 
 int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
 {
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
         /* Latch volume update bits & default ZC on */
         snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
                             WM8993_IN1_VU, WM8993_IN1_VU);
@@ -801,17 +836,21 @@ int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
         snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
                             WM8993_IN2_VU, WM8993_IN2_VU);
 
+        snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_LEFT,
+                            WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
         snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_RIGHT,
                             WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
 
         snd_soc_update_bits(codec, WM8993_LEFT_OUTPUT_VOLUME,
-                            WM8993_HPOUT1L_ZC, WM8993_HPOUT1L_ZC);
+                            WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC,
+                            WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC);
         snd_soc_update_bits(codec, WM8993_RIGHT_OUTPUT_VOLUME,
                             WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
                             WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
 
         snd_soc_update_bits(codec, WM8993_LEFT_OPGA_VOLUME,
-                            WM8993_MIXOUTL_ZC, WM8993_MIXOUTL_ZC);
+                            WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU,
+                            WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU);
         snd_soc_update_bits(codec, WM8993_RIGHT_OPGA_VOLUME,
                             WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
                             WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
@@ -819,7 +858,7 @@ int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
         snd_soc_add_controls(codec, analogue_snd_controls,
                              ARRAY_SIZE(analogue_snd_controls));
 
-        snd_soc_dapm_new_controls(codec, analogue_dapm_widgets,
+        snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets,
                                   ARRAY_SIZE(analogue_dapm_widgets));
         return 0;
 }
@@ -828,24 +867,26 @@ EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
 int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
                                 int lineout1_diff, int lineout2_diff)
 {
-        snd_soc_dapm_add_routes(codec, analogue_routes,
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+        snd_soc_dapm_add_routes(dapm, analogue_routes,
                                 ARRAY_SIZE(analogue_routes));
 
         if (lineout1_diff)
-                snd_soc_dapm_add_routes(codec,
+                snd_soc_dapm_add_routes(dapm,
                                         lineout1_diff_routes,
                                         ARRAY_SIZE(lineout1_diff_routes));
         else
-                snd_soc_dapm_add_routes(codec,
+                snd_soc_dapm_add_routes(dapm,
                                         lineout1_se_routes,
                                         ARRAY_SIZE(lineout1_se_routes));
 
         if (lineout2_diff)
-                snd_soc_dapm_add_routes(codec,
+                snd_soc_dapm_add_routes(dapm,
                                         lineout2_diff_routes,
                                         ARRAY_SIZE(lineout2_diff_routes));
         else
-                snd_soc_dapm_add_routes(codec,
+                snd_soc_dapm_add_routes(dapm,
                                         lineout2_se_routes,
                                         ARRAY_SIZE(lineout2_se_routes));
 
@@ -872,7 +913,7 @@ int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *codec,
          * VMID as an output and can disable it.
          */
         if (lineout1_diff && lineout2_diff)
-                codec->idle_bias_off = 1;
+                codec->dapm.idle_bias_off = 1;
 
         if (lineout1fb)
                 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
diff --git a/sound/soc/codecs/wm_hubs.h b/sound/soc/codecs/wm_hubs.h
index e51c16683589..f8a5e976b5e6 100644
--- a/sound/soc/codecs/wm_hubs.h
+++ b/sound/soc/codecs/wm_hubs.h
@@ -23,6 +23,9 @@ struct wm_hubs_data {
         int dcs_codes;
         int dcs_readback_mode;
         int hp_startup_mode;
+
+        bool class_w;
+        u16 class_w_dcs;
 };
 
 extern int wm_hubs_add_analogue_controls(struct snd_soc_codec *);