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Diffstat (limited to 'sound/soc/codecs/wm8994.c')
-rw-r--r--sound/soc/codecs/wm8994.c2916
1 files changed, 1004 insertions, 1912 deletions
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 522249d5c2b4..83014a7c2e14 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -18,15 +18,17 @@
18#include <linux/pm.h> 18#include <linux/pm.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
21#include <linux/regulator/consumer.h> 22#include <linux/regulator/consumer.h>
22#include <linux/slab.h> 23#include <linux/slab.h>
23#include <sound/core.h> 24#include <sound/core.h>
25#include <sound/jack.h>
24#include <sound/pcm.h> 26#include <sound/pcm.h>
25#include <sound/pcm_params.h> 27#include <sound/pcm_params.h>
26#include <sound/soc.h> 28#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 29#include <sound/initval.h>
29#include <sound/tlv.h> 30#include <sound/tlv.h>
31#include <trace/events/asoc.h>
30 32
31#include <linux/mfd/wm8994/core.h> 33#include <linux/mfd/wm8994/core.h>
32#include <linux/mfd/wm8994/registers.h> 34#include <linux/mfd/wm8994/registers.h>
@@ -36,15 +38,6 @@
36#include "wm8994.h" 38#include "wm8994.h"
37#include "wm_hubs.h" 39#include "wm_hubs.h"
38 40
39static struct snd_soc_codec *wm8994_codec;
40struct snd_soc_codec_device soc_codec_dev_wm8994;
41
42struct fll_config {
43 int src;
44 int in;
45 int out;
46};
47
48#define WM8994_NUM_DRC 3 41#define WM8994_NUM_DRC 3
49#define WM8994_NUM_EQ 3 42#define WM8994_NUM_EQ 3
50 43
@@ -60,1624 +53,11 @@ static int wm8994_retune_mobile_base[] = {
60 WM8994_AIF2_EQ_GAINS_1, 53 WM8994_AIF2_EQ_GAINS_1,
61}; 54};
62 55
63#define WM8994_REG_CACHE_SIZE 0x621 56static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
64
65struct wm8994_micdet {
66 struct snd_soc_jack *jack;
67 int det;
68 int shrt;
69};
70
71/* codec private data */
72struct wm8994_priv {
73 struct wm_hubs_data hubs;
74 struct snd_soc_codec codec;
75 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
76 int sysclk[2];
77 int sysclk_rate[2];
78 int mclk[2];
79 int aifclk[2];
80 struct fll_config fll[2], fll_suspend[2];
81
82 int dac_rates[2];
83 int lrclk_shared[2];
84
85 /* Platform dependant DRC configuration */
86 const char **drc_texts;
87 int drc_cfg[WM8994_NUM_DRC];
88 struct soc_enum drc_enum;
89
90 /* Platform dependant ReTune mobile configuration */
91 int num_retune_mobile_texts;
92 const char **retune_mobile_texts;
93 int retune_mobile_cfg[WM8994_NUM_EQ];
94 struct soc_enum retune_mobile_enum;
95
96 struct wm8994_micdet micdet[2];
97
98 int revision;
99 struct wm8994_pdata *pdata;
100};
101
102static struct {
103 unsigned short readable; /* Mask of readable bits */
104 unsigned short writable; /* Mask of writable bits */
105 unsigned short vol; /* Mask of volatile bits */
106} access_masks[] = {
107 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Software Reset */
108 { 0x3B37, 0x3B37, 0x0000 }, /* R1 - Power Management (1) */
109 { 0x6BF0, 0x6BF0, 0x0000 }, /* R2 - Power Management (2) */
110 { 0x3FF0, 0x3FF0, 0x0000 }, /* R3 - Power Management (3) */
111 { 0x3F3F, 0x3F3F, 0x0000 }, /* R4 - Power Management (4) */
112 { 0x3F0F, 0x3F0F, 0x0000 }, /* R5 - Power Management (5) */
113 { 0x003F, 0x003F, 0x0000 }, /* R6 - Power Management (6) */
114 { 0x0000, 0x0000, 0x0000 }, /* R7 */
115 { 0x0000, 0x0000, 0x0000 }, /* R8 */
116 { 0x0000, 0x0000, 0x0000 }, /* R9 */
117 { 0x0000, 0x0000, 0x0000 }, /* R10 */
118 { 0x0000, 0x0000, 0x0000 }, /* R11 */
119 { 0x0000, 0x0000, 0x0000 }, /* R12 */
120 { 0x0000, 0x0000, 0x0000 }, /* R13 */
121 { 0x0000, 0x0000, 0x0000 }, /* R14 */
122 { 0x0000, 0x0000, 0x0000 }, /* R15 */
123 { 0x0000, 0x0000, 0x0000 }, /* R16 */
124 { 0x0000, 0x0000, 0x0000 }, /* R17 */
125 { 0x0000, 0x0000, 0x0000 }, /* R18 */
126 { 0x0000, 0x0000, 0x0000 }, /* R19 */
127 { 0x0000, 0x0000, 0x0000 }, /* R20 */
128 { 0x01C0, 0x01C0, 0x0000 }, /* R21 - Input Mixer (1) */
129 { 0x0000, 0x0000, 0x0000 }, /* R22 */
130 { 0x0000, 0x0000, 0x0000 }, /* R23 */
131 { 0x00DF, 0x01DF, 0x0000 }, /* R24 - Left Line Input 1&2 Volume */
132 { 0x00DF, 0x01DF, 0x0000 }, /* R25 - Left Line Input 3&4 Volume */
133 { 0x00DF, 0x01DF, 0x0000 }, /* R26 - Right Line Input 1&2 Volume */
134 { 0x00DF, 0x01DF, 0x0000 }, /* R27 - Right Line Input 3&4 Volume */
135 { 0x00FF, 0x01FF, 0x0000 }, /* R28 - Left Output Volume */
136 { 0x00FF, 0x01FF, 0x0000 }, /* R29 - Right Output Volume */
137 { 0x0077, 0x0077, 0x0000 }, /* R30 - Line Outputs Volume */
138 { 0x0030, 0x0030, 0x0000 }, /* R31 - HPOUT2 Volume */
139 { 0x00FF, 0x01FF, 0x0000 }, /* R32 - Left OPGA Volume */
140 { 0x00FF, 0x01FF, 0x0000 }, /* R33 - Right OPGA Volume */
141 { 0x007F, 0x007F, 0x0000 }, /* R34 - SPKMIXL Attenuation */
142 { 0x017F, 0x017F, 0x0000 }, /* R35 - SPKMIXR Attenuation */
143 { 0x003F, 0x003F, 0x0000 }, /* R36 - SPKOUT Mixers */
144 { 0x003F, 0x003F, 0x0000 }, /* R37 - ClassD */
145 { 0x00FF, 0x01FF, 0x0000 }, /* R38 - Speaker Volume Left */
146 { 0x00FF, 0x01FF, 0x0000 }, /* R39 - Speaker Volume Right */
147 { 0x00FF, 0x00FF, 0x0000 }, /* R40 - Input Mixer (2) */
148 { 0x01B7, 0x01B7, 0x0000 }, /* R41 - Input Mixer (3) */
149 { 0x01B7, 0x01B7, 0x0000 }, /* R42 - Input Mixer (4) */
150 { 0x01C7, 0x01C7, 0x0000 }, /* R43 - Input Mixer (5) */
151 { 0x01C7, 0x01C7, 0x0000 }, /* R44 - Input Mixer (6) */
152 { 0x01FF, 0x01FF, 0x0000 }, /* R45 - Output Mixer (1) */
153 { 0x01FF, 0x01FF, 0x0000 }, /* R46 - Output Mixer (2) */
154 { 0x0FFF, 0x0FFF, 0x0000 }, /* R47 - Output Mixer (3) */
155 { 0x0FFF, 0x0FFF, 0x0000 }, /* R48 - Output Mixer (4) */
156 { 0x0FFF, 0x0FFF, 0x0000 }, /* R49 - Output Mixer (5) */
157 { 0x0FFF, 0x0FFF, 0x0000 }, /* R50 - Output Mixer (6) */
158 { 0x0038, 0x0038, 0x0000 }, /* R51 - HPOUT2 Mixer */
159 { 0x0077, 0x0077, 0x0000 }, /* R52 - Line Mixer (1) */
160 { 0x0077, 0x0077, 0x0000 }, /* R53 - Line Mixer (2) */
161 { 0x03FF, 0x03FF, 0x0000 }, /* R54 - Speaker Mixer */
162 { 0x00C1, 0x00C1, 0x0000 }, /* R55 - Additional Control */
163 { 0x00F0, 0x00F0, 0x0000 }, /* R56 - AntiPOP (1) */
164 { 0x01EF, 0x01EF, 0x0000 }, /* R57 - AntiPOP (2) */
165 { 0x00FF, 0x00FF, 0x0000 }, /* R58 - MICBIAS */
166 { 0x000F, 0x000F, 0x0000 }, /* R59 - LDO 1 */
167 { 0x0007, 0x0007, 0x0000 }, /* R60 - LDO 2 */
168 { 0x0000, 0x0000, 0x0000 }, /* R61 */
169 { 0x0000, 0x0000, 0x0000 }, /* R62 */
170 { 0x0000, 0x0000, 0x0000 }, /* R63 */
171 { 0x0000, 0x0000, 0x0000 }, /* R64 */
172 { 0x0000, 0x0000, 0x0000 }, /* R65 */
173 { 0x0000, 0x0000, 0x0000 }, /* R66 */
174 { 0x0000, 0x0000, 0x0000 }, /* R67 */
175 { 0x0000, 0x0000, 0x0000 }, /* R68 */
176 { 0x0000, 0x0000, 0x0000 }, /* R69 */
177 { 0x0000, 0x0000, 0x0000 }, /* R70 */
178 { 0x0000, 0x0000, 0x0000 }, /* R71 */
179 { 0x0000, 0x0000, 0x0000 }, /* R72 */
180 { 0x0000, 0x0000, 0x0000 }, /* R73 */
181 { 0x0000, 0x0000, 0x0000 }, /* R74 */
182 { 0x0000, 0x0000, 0x0000 }, /* R75 */
183 { 0x8000, 0x8000, 0x0000 }, /* R76 - Charge Pump (1) */
184 { 0x0000, 0x0000, 0x0000 }, /* R77 */
185 { 0x0000, 0x0000, 0x0000 }, /* R78 */
186 { 0x0000, 0x0000, 0x0000 }, /* R79 */
187 { 0x0000, 0x0000, 0x0000 }, /* R80 */
188 { 0x0301, 0x0301, 0x0000 }, /* R81 - Class W (1) */
189 { 0x0000, 0x0000, 0x0000 }, /* R82 */
190 { 0x0000, 0x0000, 0x0000 }, /* R83 */
191 { 0x333F, 0x333F, 0x0000 }, /* R84 - DC Servo (1) */
192 { 0x0FEF, 0x0FEF, 0x0000 }, /* R85 - DC Servo (2) */
193 { 0x0000, 0x0000, 0x0000 }, /* R86 */
194 { 0xFFFF, 0xFFFF, 0x0000 }, /* R87 - DC Servo (4) */
195 { 0x0333, 0x0000, 0x0000 }, /* R88 - DC Servo Readback */
196 { 0x0000, 0x0000, 0x0000 }, /* R89 */
197 { 0x0000, 0x0000, 0x0000 }, /* R90 */
198 { 0x0000, 0x0000, 0x0000 }, /* R91 */
199 { 0x0000, 0x0000, 0x0000 }, /* R92 */
200 { 0x0000, 0x0000, 0x0000 }, /* R93 */
201 { 0x0000, 0x0000, 0x0000 }, /* R94 */
202 { 0x0000, 0x0000, 0x0000 }, /* R95 */
203 { 0x00EE, 0x00EE, 0x0000 }, /* R96 - Analogue HP (1) */
204 { 0x0000, 0x0000, 0x0000 }, /* R97 */
205 { 0x0000, 0x0000, 0x0000 }, /* R98 */
206 { 0x0000, 0x0000, 0x0000 }, /* R99 */
207 { 0x0000, 0x0000, 0x0000 }, /* R100 */
208 { 0x0000, 0x0000, 0x0000 }, /* R101 */
209 { 0x0000, 0x0000, 0x0000 }, /* R102 */
210 { 0x0000, 0x0000, 0x0000 }, /* R103 */
211 { 0x0000, 0x0000, 0x0000 }, /* R104 */
212 { 0x0000, 0x0000, 0x0000 }, /* R105 */
213 { 0x0000, 0x0000, 0x0000 }, /* R106 */
214 { 0x0000, 0x0000, 0x0000 }, /* R107 */
215 { 0x0000, 0x0000, 0x0000 }, /* R108 */
216 { 0x0000, 0x0000, 0x0000 }, /* R109 */
217 { 0x0000, 0x0000, 0x0000 }, /* R110 */
218 { 0x0000, 0x0000, 0x0000 }, /* R111 */
219 { 0x0000, 0x0000, 0x0000 }, /* R112 */
220 { 0x0000, 0x0000, 0x0000 }, /* R113 */
221 { 0x0000, 0x0000, 0x0000 }, /* R114 */
222 { 0x0000, 0x0000, 0x0000 }, /* R115 */
223 { 0x0000, 0x0000, 0x0000 }, /* R116 */
224 { 0x0000, 0x0000, 0x0000 }, /* R117 */
225 { 0x0000, 0x0000, 0x0000 }, /* R118 */
226 { 0x0000, 0x0000, 0x0000 }, /* R119 */
227 { 0x0000, 0x0000, 0x0000 }, /* R120 */
228 { 0x0000, 0x0000, 0x0000 }, /* R121 */
229 { 0x0000, 0x0000, 0x0000 }, /* R122 */
230 { 0x0000, 0x0000, 0x0000 }, /* R123 */
231 { 0x0000, 0x0000, 0x0000 }, /* R124 */
232 { 0x0000, 0x0000, 0x0000 }, /* R125 */
233 { 0x0000, 0x0000, 0x0000 }, /* R126 */
234 { 0x0000, 0x0000, 0x0000 }, /* R127 */
235 { 0x0000, 0x0000, 0x0000 }, /* R128 */
236 { 0x0000, 0x0000, 0x0000 }, /* R129 */
237 { 0x0000, 0x0000, 0x0000 }, /* R130 */
238 { 0x0000, 0x0000, 0x0000 }, /* R131 */
239 { 0x0000, 0x0000, 0x0000 }, /* R132 */
240 { 0x0000, 0x0000, 0x0000 }, /* R133 */
241 { 0x0000, 0x0000, 0x0000 }, /* R134 */
242 { 0x0000, 0x0000, 0x0000 }, /* R135 */
243 { 0x0000, 0x0000, 0x0000 }, /* R136 */
244 { 0x0000, 0x0000, 0x0000 }, /* R137 */
245 { 0x0000, 0x0000, 0x0000 }, /* R138 */
246 { 0x0000, 0x0000, 0x0000 }, /* R139 */
247 { 0x0000, 0x0000, 0x0000 }, /* R140 */
248 { 0x0000, 0x0000, 0x0000 }, /* R141 */
249 { 0x0000, 0x0000, 0x0000 }, /* R142 */
250 { 0x0000, 0x0000, 0x0000 }, /* R143 */
251 { 0x0000, 0x0000, 0x0000 }, /* R144 */
252 { 0x0000, 0x0000, 0x0000 }, /* R145 */
253 { 0x0000, 0x0000, 0x0000 }, /* R146 */
254 { 0x0000, 0x0000, 0x0000 }, /* R147 */
255 { 0x0000, 0x0000, 0x0000 }, /* R148 */
256 { 0x0000, 0x0000, 0x0000 }, /* R149 */
257 { 0x0000, 0x0000, 0x0000 }, /* R150 */
258 { 0x0000, 0x0000, 0x0000 }, /* R151 */
259 { 0x0000, 0x0000, 0x0000 }, /* R152 */
260 { 0x0000, 0x0000, 0x0000 }, /* R153 */
261 { 0x0000, 0x0000, 0x0000 }, /* R154 */
262 { 0x0000, 0x0000, 0x0000 }, /* R155 */
263 { 0x0000, 0x0000, 0x0000 }, /* R156 */
264 { 0x0000, 0x0000, 0x0000 }, /* R157 */
265 { 0x0000, 0x0000, 0x0000 }, /* R158 */
266 { 0x0000, 0x0000, 0x0000 }, /* R159 */
267 { 0x0000, 0x0000, 0x0000 }, /* R160 */
268 { 0x0000, 0x0000, 0x0000 }, /* R161 */
269 { 0x0000, 0x0000, 0x0000 }, /* R162 */
270 { 0x0000, 0x0000, 0x0000 }, /* R163 */
271 { 0x0000, 0x0000, 0x0000 }, /* R164 */
272 { 0x0000, 0x0000, 0x0000 }, /* R165 */
273 { 0x0000, 0x0000, 0x0000 }, /* R166 */
274 { 0x0000, 0x0000, 0x0000 }, /* R167 */
275 { 0x0000, 0x0000, 0x0000 }, /* R168 */
276 { 0x0000, 0x0000, 0x0000 }, /* R169 */
277 { 0x0000, 0x0000, 0x0000 }, /* R170 */
278 { 0x0000, 0x0000, 0x0000 }, /* R171 */
279 { 0x0000, 0x0000, 0x0000 }, /* R172 */
280 { 0x0000, 0x0000, 0x0000 }, /* R173 */
281 { 0x0000, 0x0000, 0x0000 }, /* R174 */
282 { 0x0000, 0x0000, 0x0000 }, /* R175 */
283 { 0x0000, 0x0000, 0x0000 }, /* R176 */
284 { 0x0000, 0x0000, 0x0000 }, /* R177 */
285 { 0x0000, 0x0000, 0x0000 }, /* R178 */
286 { 0x0000, 0x0000, 0x0000 }, /* R179 */
287 { 0x0000, 0x0000, 0x0000 }, /* R180 */
288 { 0x0000, 0x0000, 0x0000 }, /* R181 */
289 { 0x0000, 0x0000, 0x0000 }, /* R182 */
290 { 0x0000, 0x0000, 0x0000 }, /* R183 */
291 { 0x0000, 0x0000, 0x0000 }, /* R184 */
292 { 0x0000, 0x0000, 0x0000 }, /* R185 */
293 { 0x0000, 0x0000, 0x0000 }, /* R186 */
294 { 0x0000, 0x0000, 0x0000 }, /* R187 */
295 { 0x0000, 0x0000, 0x0000 }, /* R188 */
296 { 0x0000, 0x0000, 0x0000 }, /* R189 */
297 { 0x0000, 0x0000, 0x0000 }, /* R190 */
298 { 0x0000, 0x0000, 0x0000 }, /* R191 */
299 { 0x0000, 0x0000, 0x0000 }, /* R192 */
300 { 0x0000, 0x0000, 0x0000 }, /* R193 */
301 { 0x0000, 0x0000, 0x0000 }, /* R194 */
302 { 0x0000, 0x0000, 0x0000 }, /* R195 */
303 { 0x0000, 0x0000, 0x0000 }, /* R196 */
304 { 0x0000, 0x0000, 0x0000 }, /* R197 */
305 { 0x0000, 0x0000, 0x0000 }, /* R198 */
306 { 0x0000, 0x0000, 0x0000 }, /* R199 */
307 { 0x0000, 0x0000, 0x0000 }, /* R200 */
308 { 0x0000, 0x0000, 0x0000 }, /* R201 */
309 { 0x0000, 0x0000, 0x0000 }, /* R202 */
310 { 0x0000, 0x0000, 0x0000 }, /* R203 */
311 { 0x0000, 0x0000, 0x0000 }, /* R204 */
312 { 0x0000, 0x0000, 0x0000 }, /* R205 */
313 { 0x0000, 0x0000, 0x0000 }, /* R206 */
314 { 0x0000, 0x0000, 0x0000 }, /* R207 */
315 { 0x0000, 0x0000, 0x0000 }, /* R208 */
316 { 0x0000, 0x0000, 0x0000 }, /* R209 */
317 { 0x0000, 0x0000, 0x0000 }, /* R210 */
318 { 0x0000, 0x0000, 0x0000 }, /* R211 */
319 { 0x0000, 0x0000, 0x0000 }, /* R212 */
320 { 0x0000, 0x0000, 0x0000 }, /* R213 */
321 { 0x0000, 0x0000, 0x0000 }, /* R214 */
322 { 0x0000, 0x0000, 0x0000 }, /* R215 */
323 { 0x0000, 0x0000, 0x0000 }, /* R216 */
324 { 0x0000, 0x0000, 0x0000 }, /* R217 */
325 { 0x0000, 0x0000, 0x0000 }, /* R218 */
326 { 0x0000, 0x0000, 0x0000 }, /* R219 */
327 { 0x0000, 0x0000, 0x0000 }, /* R220 */
328 { 0x0000, 0x0000, 0x0000 }, /* R221 */
329 { 0x0000, 0x0000, 0x0000 }, /* R222 */
330 { 0x0000, 0x0000, 0x0000 }, /* R223 */
331 { 0x0000, 0x0000, 0x0000 }, /* R224 */
332 { 0x0000, 0x0000, 0x0000 }, /* R225 */
333 { 0x0000, 0x0000, 0x0000 }, /* R226 */
334 { 0x0000, 0x0000, 0x0000 }, /* R227 */
335 { 0x0000, 0x0000, 0x0000 }, /* R228 */
336 { 0x0000, 0x0000, 0x0000 }, /* R229 */
337 { 0x0000, 0x0000, 0x0000 }, /* R230 */
338 { 0x0000, 0x0000, 0x0000 }, /* R231 */
339 { 0x0000, 0x0000, 0x0000 }, /* R232 */
340 { 0x0000, 0x0000, 0x0000 }, /* R233 */
341 { 0x0000, 0x0000, 0x0000 }, /* R234 */
342 { 0x0000, 0x0000, 0x0000 }, /* R235 */
343 { 0x0000, 0x0000, 0x0000 }, /* R236 */
344 { 0x0000, 0x0000, 0x0000 }, /* R237 */
345 { 0x0000, 0x0000, 0x0000 }, /* R238 */
346 { 0x0000, 0x0000, 0x0000 }, /* R239 */
347 { 0x0000, 0x0000, 0x0000 }, /* R240 */
348 { 0x0000, 0x0000, 0x0000 }, /* R241 */
349 { 0x0000, 0x0000, 0x0000 }, /* R242 */
350 { 0x0000, 0x0000, 0x0000 }, /* R243 */
351 { 0x0000, 0x0000, 0x0000 }, /* R244 */
352 { 0x0000, 0x0000, 0x0000 }, /* R245 */
353 { 0x0000, 0x0000, 0x0000 }, /* R246 */
354 { 0x0000, 0x0000, 0x0000 }, /* R247 */
355 { 0x0000, 0x0000, 0x0000 }, /* R248 */
356 { 0x0000, 0x0000, 0x0000 }, /* R249 */
357 { 0x0000, 0x0000, 0x0000 }, /* R250 */
358 { 0x0000, 0x0000, 0x0000 }, /* R251 */
359 { 0x0000, 0x0000, 0x0000 }, /* R252 */
360 { 0x0000, 0x0000, 0x0000 }, /* R253 */
361 { 0x0000, 0x0000, 0x0000 }, /* R254 */
362 { 0x0000, 0x0000, 0x0000 }, /* R255 */
363 { 0x000F, 0x0000, 0x0000 }, /* R256 - Chip Revision */
364 { 0x0074, 0x0074, 0x0000 }, /* R257 - Control Interface */
365 { 0x0000, 0x0000, 0x0000 }, /* R258 */
366 { 0x0000, 0x0000, 0x0000 }, /* R259 */
367 { 0x0000, 0x0000, 0x0000 }, /* R260 */
368 { 0x0000, 0x0000, 0x0000 }, /* R261 */
369 { 0x0000, 0x0000, 0x0000 }, /* R262 */
370 { 0x0000, 0x0000, 0x0000 }, /* R263 */
371 { 0x0000, 0x0000, 0x0000 }, /* R264 */
372 { 0x0000, 0x0000, 0x0000 }, /* R265 */
373 { 0x0000, 0x0000, 0x0000 }, /* R266 */
374 { 0x0000, 0x0000, 0x0000 }, /* R267 */
375 { 0x0000, 0x0000, 0x0000 }, /* R268 */
376 { 0x0000, 0x0000, 0x0000 }, /* R269 */
377 { 0x0000, 0x0000, 0x0000 }, /* R270 */
378 { 0x0000, 0x0000, 0x0000 }, /* R271 */
379 { 0x807F, 0x837F, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
380 { 0x017F, 0x0000, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
381 { 0x0000, 0x0000, 0x0000 }, /* R274 */
382 { 0x0000, 0x0000, 0x0000 }, /* R275 */
383 { 0x0000, 0x0000, 0x0000 }, /* R276 */
384 { 0x0000, 0x0000, 0x0000 }, /* R277 */
385 { 0x0000, 0x0000, 0x0000 }, /* R278 */
386 { 0x0000, 0x0000, 0x0000 }, /* R279 */
387 { 0x0000, 0x0000, 0x0000 }, /* R280 */
388 { 0x0000, 0x0000, 0x0000 }, /* R281 */
389 { 0x0000, 0x0000, 0x0000 }, /* R282 */
390 { 0x0000, 0x0000, 0x0000 }, /* R283 */
391 { 0x0000, 0x0000, 0x0000 }, /* R284 */
392 { 0x0000, 0x0000, 0x0000 }, /* R285 */
393 { 0x0000, 0x0000, 0x0000 }, /* R286 */
394 { 0x0000, 0x0000, 0x0000 }, /* R287 */
395 { 0x0000, 0x0000, 0x0000 }, /* R288 */
396 { 0x0000, 0x0000, 0x0000 }, /* R289 */
397 { 0x0000, 0x0000, 0x0000 }, /* R290 */
398 { 0x0000, 0x0000, 0x0000 }, /* R291 */
399 { 0x0000, 0x0000, 0x0000 }, /* R292 */
400 { 0x0000, 0x0000, 0x0000 }, /* R293 */
401 { 0x0000, 0x0000, 0x0000 }, /* R294 */
402 { 0x0000, 0x0000, 0x0000 }, /* R295 */
403 { 0x0000, 0x0000, 0x0000 }, /* R296 */
404 { 0x0000, 0x0000, 0x0000 }, /* R297 */
405 { 0x0000, 0x0000, 0x0000 }, /* R298 */
406 { 0x0000, 0x0000, 0x0000 }, /* R299 */
407 { 0x0000, 0x0000, 0x0000 }, /* R300 */
408 { 0x0000, 0x0000, 0x0000 }, /* R301 */
409 { 0x0000, 0x0000, 0x0000 }, /* R302 */
410 { 0x0000, 0x0000, 0x0000 }, /* R303 */
411 { 0x0000, 0x0000, 0x0000 }, /* R304 */
412 { 0x0000, 0x0000, 0x0000 }, /* R305 */
413 { 0x0000, 0x0000, 0x0000 }, /* R306 */
414 { 0x0000, 0x0000, 0x0000 }, /* R307 */
415 { 0x0000, 0x0000, 0x0000 }, /* R308 */
416 { 0x0000, 0x0000, 0x0000 }, /* R309 */
417 { 0x0000, 0x0000, 0x0000 }, /* R310 */
418 { 0x0000, 0x0000, 0x0000 }, /* R311 */
419 { 0x0000, 0x0000, 0x0000 }, /* R312 */
420 { 0x0000, 0x0000, 0x0000 }, /* R313 */
421 { 0x0000, 0x0000, 0x0000 }, /* R314 */
422 { 0x0000, 0x0000, 0x0000 }, /* R315 */
423 { 0x0000, 0x0000, 0x0000 }, /* R316 */
424 { 0x0000, 0x0000, 0x0000 }, /* R317 */
425 { 0x0000, 0x0000, 0x0000 }, /* R318 */
426 { 0x0000, 0x0000, 0x0000 }, /* R319 */
427 { 0x0000, 0x0000, 0x0000 }, /* R320 */
428 { 0x0000, 0x0000, 0x0000 }, /* R321 */
429 { 0x0000, 0x0000, 0x0000 }, /* R322 */
430 { 0x0000, 0x0000, 0x0000 }, /* R323 */
431 { 0x0000, 0x0000, 0x0000 }, /* R324 */
432 { 0x0000, 0x0000, 0x0000 }, /* R325 */
433 { 0x0000, 0x0000, 0x0000 }, /* R326 */
434 { 0x0000, 0x0000, 0x0000 }, /* R327 */
435 { 0x0000, 0x0000, 0x0000 }, /* R328 */
436 { 0x0000, 0x0000, 0x0000 }, /* R329 */
437 { 0x0000, 0x0000, 0x0000 }, /* R330 */
438 { 0x0000, 0x0000, 0x0000 }, /* R331 */
439 { 0x0000, 0x0000, 0x0000 }, /* R332 */
440 { 0x0000, 0x0000, 0x0000 }, /* R333 */
441 { 0x0000, 0x0000, 0x0000 }, /* R334 */
442 { 0x0000, 0x0000, 0x0000 }, /* R335 */
443 { 0x0000, 0x0000, 0x0000 }, /* R336 */
444 { 0x0000, 0x0000, 0x0000 }, /* R337 */
445 { 0x0000, 0x0000, 0x0000 }, /* R338 */
446 { 0x0000, 0x0000, 0x0000 }, /* R339 */
447 { 0x0000, 0x0000, 0x0000 }, /* R340 */
448 { 0x0000, 0x0000, 0x0000 }, /* R341 */
449 { 0x0000, 0x0000, 0x0000 }, /* R342 */
450 { 0x0000, 0x0000, 0x0000 }, /* R343 */
451 { 0x0000, 0x0000, 0x0000 }, /* R344 */
452 { 0x0000, 0x0000, 0x0000 }, /* R345 */
453 { 0x0000, 0x0000, 0x0000 }, /* R346 */
454 { 0x0000, 0x0000, 0x0000 }, /* R347 */
455 { 0x0000, 0x0000, 0x0000 }, /* R348 */
456 { 0x0000, 0x0000, 0x0000 }, /* R349 */
457 { 0x0000, 0x0000, 0x0000 }, /* R350 */
458 { 0x0000, 0x0000, 0x0000 }, /* R351 */
459 { 0x0000, 0x0000, 0x0000 }, /* R352 */
460 { 0x0000, 0x0000, 0x0000 }, /* R353 */
461 { 0x0000, 0x0000, 0x0000 }, /* R354 */
462 { 0x0000, 0x0000, 0x0000 }, /* R355 */
463 { 0x0000, 0x0000, 0x0000 }, /* R356 */
464 { 0x0000, 0x0000, 0x0000 }, /* R357 */
465 { 0x0000, 0x0000, 0x0000 }, /* R358 */
466 { 0x0000, 0x0000, 0x0000 }, /* R359 */
467 { 0x0000, 0x0000, 0x0000 }, /* R360 */
468 { 0x0000, 0x0000, 0x0000 }, /* R361 */
469 { 0x0000, 0x0000, 0x0000 }, /* R362 */
470 { 0x0000, 0x0000, 0x0000 }, /* R363 */
471 { 0x0000, 0x0000, 0x0000 }, /* R364 */
472 { 0x0000, 0x0000, 0x0000 }, /* R365 */
473 { 0x0000, 0x0000, 0x0000 }, /* R366 */
474 { 0x0000, 0x0000, 0x0000 }, /* R367 */
475 { 0x0000, 0x0000, 0x0000 }, /* R368 */
476 { 0x0000, 0x0000, 0x0000 }, /* R369 */
477 { 0x0000, 0x0000, 0x0000 }, /* R370 */
478 { 0x0000, 0x0000, 0x0000 }, /* R371 */
479 { 0x0000, 0x0000, 0x0000 }, /* R372 */
480 { 0x0000, 0x0000, 0x0000 }, /* R373 */
481 { 0x0000, 0x0000, 0x0000 }, /* R374 */
482 { 0x0000, 0x0000, 0x0000 }, /* R375 */
483 { 0x0000, 0x0000, 0x0000 }, /* R376 */
484 { 0x0000, 0x0000, 0x0000 }, /* R377 */
485 { 0x0000, 0x0000, 0x0000 }, /* R378 */
486 { 0x0000, 0x0000, 0x0000 }, /* R379 */
487 { 0x0000, 0x0000, 0x0000 }, /* R380 */
488 { 0x0000, 0x0000, 0x0000 }, /* R381 */
489 { 0x0000, 0x0000, 0x0000 }, /* R382 */
490 { 0x0000, 0x0000, 0x0000 }, /* R383 */
491 { 0x0000, 0x0000, 0x0000 }, /* R384 */
492 { 0x0000, 0x0000, 0x0000 }, /* R385 */
493 { 0x0000, 0x0000, 0x0000 }, /* R386 */
494 { 0x0000, 0x0000, 0x0000 }, /* R387 */
495 { 0x0000, 0x0000, 0x0000 }, /* R388 */
496 { 0x0000, 0x0000, 0x0000 }, /* R389 */
497 { 0x0000, 0x0000, 0x0000 }, /* R390 */
498 { 0x0000, 0x0000, 0x0000 }, /* R391 */
499 { 0x0000, 0x0000, 0x0000 }, /* R392 */
500 { 0x0000, 0x0000, 0x0000 }, /* R393 */
501 { 0x0000, 0x0000, 0x0000 }, /* R394 */
502 { 0x0000, 0x0000, 0x0000 }, /* R395 */
503 { 0x0000, 0x0000, 0x0000 }, /* R396 */
504 { 0x0000, 0x0000, 0x0000 }, /* R397 */
505 { 0x0000, 0x0000, 0x0000 }, /* R398 */
506 { 0x0000, 0x0000, 0x0000 }, /* R399 */
507 { 0x0000, 0x0000, 0x0000 }, /* R400 */
508 { 0x0000, 0x0000, 0x0000 }, /* R401 */
509 { 0x0000, 0x0000, 0x0000 }, /* R402 */
510 { 0x0000, 0x0000, 0x0000 }, /* R403 */
511 { 0x0000, 0x0000, 0x0000 }, /* R404 */
512 { 0x0000, 0x0000, 0x0000 }, /* R405 */
513 { 0x0000, 0x0000, 0x0000 }, /* R406 */
514 { 0x0000, 0x0000, 0x0000 }, /* R407 */
515 { 0x0000, 0x0000, 0x0000 }, /* R408 */
516 { 0x0000, 0x0000, 0x0000 }, /* R409 */
517 { 0x0000, 0x0000, 0x0000 }, /* R410 */
518 { 0x0000, 0x0000, 0x0000 }, /* R411 */
519 { 0x0000, 0x0000, 0x0000 }, /* R412 */
520 { 0x0000, 0x0000, 0x0000 }, /* R413 */
521 { 0x0000, 0x0000, 0x0000 }, /* R414 */
522 { 0x0000, 0x0000, 0x0000 }, /* R415 */
523 { 0x0000, 0x0000, 0x0000 }, /* R416 */
524 { 0x0000, 0x0000, 0x0000 }, /* R417 */
525 { 0x0000, 0x0000, 0x0000 }, /* R418 */
526 { 0x0000, 0x0000, 0x0000 }, /* R419 */
527 { 0x0000, 0x0000, 0x0000 }, /* R420 */
528 { 0x0000, 0x0000, 0x0000 }, /* R421 */
529 { 0x0000, 0x0000, 0x0000 }, /* R422 */
530 { 0x0000, 0x0000, 0x0000 }, /* R423 */
531 { 0x0000, 0x0000, 0x0000 }, /* R424 */
532 { 0x0000, 0x0000, 0x0000 }, /* R425 */
533 { 0x0000, 0x0000, 0x0000 }, /* R426 */
534 { 0x0000, 0x0000, 0x0000 }, /* R427 */
535 { 0x0000, 0x0000, 0x0000 }, /* R428 */
536 { 0x0000, 0x0000, 0x0000 }, /* R429 */
537 { 0x0000, 0x0000, 0x0000 }, /* R430 */
538 { 0x0000, 0x0000, 0x0000 }, /* R431 */
539 { 0x0000, 0x0000, 0x0000 }, /* R432 */
540 { 0x0000, 0x0000, 0x0000 }, /* R433 */
541 { 0x0000, 0x0000, 0x0000 }, /* R434 */
542 { 0x0000, 0x0000, 0x0000 }, /* R435 */
543 { 0x0000, 0x0000, 0x0000 }, /* R436 */
544 { 0x0000, 0x0000, 0x0000 }, /* R437 */
545 { 0x0000, 0x0000, 0x0000 }, /* R438 */
546 { 0x0000, 0x0000, 0x0000 }, /* R439 */
547 { 0x0000, 0x0000, 0x0000 }, /* R440 */
548 { 0x0000, 0x0000, 0x0000 }, /* R441 */
549 { 0x0000, 0x0000, 0x0000 }, /* R442 */
550 { 0x0000, 0x0000, 0x0000 }, /* R443 */
551 { 0x0000, 0x0000, 0x0000 }, /* R444 */
552 { 0x0000, 0x0000, 0x0000 }, /* R445 */
553 { 0x0000, 0x0000, 0x0000 }, /* R446 */
554 { 0x0000, 0x0000, 0x0000 }, /* R447 */
555 { 0x0000, 0x0000, 0x0000 }, /* R448 */
556 { 0x0000, 0x0000, 0x0000 }, /* R449 */
557 { 0x0000, 0x0000, 0x0000 }, /* R450 */
558 { 0x0000, 0x0000, 0x0000 }, /* R451 */
559 { 0x0000, 0x0000, 0x0000 }, /* R452 */
560 { 0x0000, 0x0000, 0x0000 }, /* R453 */
561 { 0x0000, 0x0000, 0x0000 }, /* R454 */
562 { 0x0000, 0x0000, 0x0000 }, /* R455 */
563 { 0x0000, 0x0000, 0x0000 }, /* R456 */
564 { 0x0000, 0x0000, 0x0000 }, /* R457 */
565 { 0x0000, 0x0000, 0x0000 }, /* R458 */
566 { 0x0000, 0x0000, 0x0000 }, /* R459 */
567 { 0x0000, 0x0000, 0x0000 }, /* R460 */
568 { 0x0000, 0x0000, 0x0000 }, /* R461 */
569 { 0x0000, 0x0000, 0x0000 }, /* R462 */
570 { 0x0000, 0x0000, 0x0000 }, /* R463 */
571 { 0x0000, 0x0000, 0x0000 }, /* R464 */
572 { 0x0000, 0x0000, 0x0000 }, /* R465 */
573 { 0x0000, 0x0000, 0x0000 }, /* R466 */
574 { 0x0000, 0x0000, 0x0000 }, /* R467 */
575 { 0x0000, 0x0000, 0x0000 }, /* R468 */
576 { 0x0000, 0x0000, 0x0000 }, /* R469 */
577 { 0x0000, 0x0000, 0x0000 }, /* R470 */
578 { 0x0000, 0x0000, 0x0000 }, /* R471 */
579 { 0x0000, 0x0000, 0x0000 }, /* R472 */
580 { 0x0000, 0x0000, 0x0000 }, /* R473 */
581 { 0x0000, 0x0000, 0x0000 }, /* R474 */
582 { 0x0000, 0x0000, 0x0000 }, /* R475 */
583 { 0x0000, 0x0000, 0x0000 }, /* R476 */
584 { 0x0000, 0x0000, 0x0000 }, /* R477 */
585 { 0x0000, 0x0000, 0x0000 }, /* R478 */
586 { 0x0000, 0x0000, 0x0000 }, /* R479 */
587 { 0x0000, 0x0000, 0x0000 }, /* R480 */
588 { 0x0000, 0x0000, 0x0000 }, /* R481 */
589 { 0x0000, 0x0000, 0x0000 }, /* R482 */
590 { 0x0000, 0x0000, 0x0000 }, /* R483 */
591 { 0x0000, 0x0000, 0x0000 }, /* R484 */
592 { 0x0000, 0x0000, 0x0000 }, /* R485 */
593 { 0x0000, 0x0000, 0x0000 }, /* R486 */
594 { 0x0000, 0x0000, 0x0000 }, /* R487 */
595 { 0x0000, 0x0000, 0x0000 }, /* R488 */
596 { 0x0000, 0x0000, 0x0000 }, /* R489 */
597 { 0x0000, 0x0000, 0x0000 }, /* R490 */
598 { 0x0000, 0x0000, 0x0000 }, /* R491 */
599 { 0x0000, 0x0000, 0x0000 }, /* R492 */
600 { 0x0000, 0x0000, 0x0000 }, /* R493 */
601 { 0x0000, 0x0000, 0x0000 }, /* R494 */
602 { 0x0000, 0x0000, 0x0000 }, /* R495 */
603 { 0x0000, 0x0000, 0x0000 }, /* R496 */
604 { 0x0000, 0x0000, 0x0000 }, /* R497 */
605 { 0x0000, 0x0000, 0x0000 }, /* R498 */
606 { 0x0000, 0x0000, 0x0000 }, /* R499 */
607 { 0x0000, 0x0000, 0x0000 }, /* R500 */
608 { 0x0000, 0x0000, 0x0000 }, /* R501 */
609 { 0x0000, 0x0000, 0x0000 }, /* R502 */
610 { 0x0000, 0x0000, 0x0000 }, /* R503 */
611 { 0x0000, 0x0000, 0x0000 }, /* R504 */
612 { 0x0000, 0x0000, 0x0000 }, /* R505 */
613 { 0x0000, 0x0000, 0x0000 }, /* R506 */
614 { 0x0000, 0x0000, 0x0000 }, /* R507 */
615 { 0x0000, 0x0000, 0x0000 }, /* R508 */
616 { 0x0000, 0x0000, 0x0000 }, /* R509 */
617 { 0x0000, 0x0000, 0x0000 }, /* R510 */
618 { 0x0000, 0x0000, 0x0000 }, /* R511 */
619 { 0x001F, 0x001F, 0x0000 }, /* R512 - AIF1 Clocking (1) */
620 { 0x003F, 0x003F, 0x0000 }, /* R513 - AIF1 Clocking (2) */
621 { 0x0000, 0x0000, 0x0000 }, /* R514 */
622 { 0x0000, 0x0000, 0x0000 }, /* R515 */
623 { 0x001F, 0x001F, 0x0000 }, /* R516 - AIF2 Clocking (1) */
624 { 0x003F, 0x003F, 0x0000 }, /* R517 - AIF2 Clocking (2) */
625 { 0x0000, 0x0000, 0x0000 }, /* R518 */
626 { 0x0000, 0x0000, 0x0000 }, /* R519 */
627 { 0x001F, 0x001F, 0x0000 }, /* R520 - Clocking (1) */
628 { 0x0777, 0x0777, 0x0000 }, /* R521 - Clocking (2) */
629 { 0x0000, 0x0000, 0x0000 }, /* R522 */
630 { 0x0000, 0x0000, 0x0000 }, /* R523 */
631 { 0x0000, 0x0000, 0x0000 }, /* R524 */
632 { 0x0000, 0x0000, 0x0000 }, /* R525 */
633 { 0x0000, 0x0000, 0x0000 }, /* R526 */
634 { 0x0000, 0x0000, 0x0000 }, /* R527 */
635 { 0x00FF, 0x00FF, 0x0000 }, /* R528 - AIF1 Rate */
636 { 0x00FF, 0x00FF, 0x0000 }, /* R529 - AIF2 Rate */
637 { 0x000F, 0x0000, 0x0000 }, /* R530 - Rate Status */
638 { 0x0000, 0x0000, 0x0000 }, /* R531 */
639 { 0x0000, 0x0000, 0x0000 }, /* R532 */
640 { 0x0000, 0x0000, 0x0000 }, /* R533 */
641 { 0x0000, 0x0000, 0x0000 }, /* R534 */
642 { 0x0000, 0x0000, 0x0000 }, /* R535 */
643 { 0x0000, 0x0000, 0x0000 }, /* R536 */
644 { 0x0000, 0x0000, 0x0000 }, /* R537 */
645 { 0x0000, 0x0000, 0x0000 }, /* R538 */
646 { 0x0000, 0x0000, 0x0000 }, /* R539 */
647 { 0x0000, 0x0000, 0x0000 }, /* R540 */
648 { 0x0000, 0x0000, 0x0000 }, /* R541 */
649 { 0x0000, 0x0000, 0x0000 }, /* R542 */
650 { 0x0000, 0x0000, 0x0000 }, /* R543 */
651 { 0x0007, 0x0007, 0x0000 }, /* R544 - FLL1 Control (1) */
652 { 0x3F77, 0x3F77, 0x0000 }, /* R545 - FLL1 Control (2) */
653 { 0xFFFF, 0xFFFF, 0x0000 }, /* R546 - FLL1 Control (3) */
654 { 0x7FEF, 0x7FEF, 0x0000 }, /* R547 - FLL1 Control (4) */
655 { 0x1FDB, 0x1FDB, 0x0000 }, /* R548 - FLL1 Control (5) */
656 { 0x0000, 0x0000, 0x0000 }, /* R549 */
657 { 0x0000, 0x0000, 0x0000 }, /* R550 */
658 { 0x0000, 0x0000, 0x0000 }, /* R551 */
659 { 0x0000, 0x0000, 0x0000 }, /* R552 */
660 { 0x0000, 0x0000, 0x0000 }, /* R553 */
661 { 0x0000, 0x0000, 0x0000 }, /* R554 */
662 { 0x0000, 0x0000, 0x0000 }, /* R555 */
663 { 0x0000, 0x0000, 0x0000 }, /* R556 */
664 { 0x0000, 0x0000, 0x0000 }, /* R557 */
665 { 0x0000, 0x0000, 0x0000 }, /* R558 */
666 { 0x0000, 0x0000, 0x0000 }, /* R559 */
667 { 0x0000, 0x0000, 0x0000 }, /* R560 */
668 { 0x0000, 0x0000, 0x0000 }, /* R561 */
669 { 0x0000, 0x0000, 0x0000 }, /* R562 */
670 { 0x0000, 0x0000, 0x0000 }, /* R563 */
671 { 0x0000, 0x0000, 0x0000 }, /* R564 */
672 { 0x0000, 0x0000, 0x0000 }, /* R565 */
673 { 0x0000, 0x0000, 0x0000 }, /* R566 */
674 { 0x0000, 0x0000, 0x0000 }, /* R567 */
675 { 0x0000, 0x0000, 0x0000 }, /* R568 */
676 { 0x0000, 0x0000, 0x0000 }, /* R569 */
677 { 0x0000, 0x0000, 0x0000 }, /* R570 */
678 { 0x0000, 0x0000, 0x0000 }, /* R571 */
679 { 0x0000, 0x0000, 0x0000 }, /* R572 */
680 { 0x0000, 0x0000, 0x0000 }, /* R573 */
681 { 0x0000, 0x0000, 0x0000 }, /* R574 */
682 { 0x0000, 0x0000, 0x0000 }, /* R575 */
683 { 0x0007, 0x0007, 0x0000 }, /* R576 - FLL2 Control (1) */
684 { 0x3F77, 0x3F77, 0x0000 }, /* R577 - FLL2 Control (2) */
685 { 0xFFFF, 0xFFFF, 0x0000 }, /* R578 - FLL2 Control (3) */
686 { 0x7FEF, 0x7FEF, 0x0000 }, /* R579 - FLL2 Control (4) */
687 { 0x1FDB, 0x1FDB, 0x0000 }, /* R580 - FLL2 Control (5) */
688 { 0x0000, 0x0000, 0x0000 }, /* R581 */
689 { 0x0000, 0x0000, 0x0000 }, /* R582 */
690 { 0x0000, 0x0000, 0x0000 }, /* R583 */
691 { 0x0000, 0x0000, 0x0000 }, /* R584 */
692 { 0x0000, 0x0000, 0x0000 }, /* R585 */
693 { 0x0000, 0x0000, 0x0000 }, /* R586 */
694 { 0x0000, 0x0000, 0x0000 }, /* R587 */
695 { 0x0000, 0x0000, 0x0000 }, /* R588 */
696 { 0x0000, 0x0000, 0x0000 }, /* R589 */
697 { 0x0000, 0x0000, 0x0000 }, /* R590 */
698 { 0x0000, 0x0000, 0x0000 }, /* R591 */
699 { 0x0000, 0x0000, 0x0000 }, /* R592 */
700 { 0x0000, 0x0000, 0x0000 }, /* R593 */
701 { 0x0000, 0x0000, 0x0000 }, /* R594 */
702 { 0x0000, 0x0000, 0x0000 }, /* R595 */
703 { 0x0000, 0x0000, 0x0000 }, /* R596 */
704 { 0x0000, 0x0000, 0x0000 }, /* R597 */
705 { 0x0000, 0x0000, 0x0000 }, /* R598 */
706 { 0x0000, 0x0000, 0x0000 }, /* R599 */
707 { 0x0000, 0x0000, 0x0000 }, /* R600 */
708 { 0x0000, 0x0000, 0x0000 }, /* R601 */
709 { 0x0000, 0x0000, 0x0000 }, /* R602 */
710 { 0x0000, 0x0000, 0x0000 }, /* R603 */
711 { 0x0000, 0x0000, 0x0000 }, /* R604 */
712 { 0x0000, 0x0000, 0x0000 }, /* R605 */
713 { 0x0000, 0x0000, 0x0000 }, /* R606 */
714 { 0x0000, 0x0000, 0x0000 }, /* R607 */
715 { 0x0000, 0x0000, 0x0000 }, /* R608 */
716 { 0x0000, 0x0000, 0x0000 }, /* R609 */
717 { 0x0000, 0x0000, 0x0000 }, /* R610 */
718 { 0x0000, 0x0000, 0x0000 }, /* R611 */
719 { 0x0000, 0x0000, 0x0000 }, /* R612 */
720 { 0x0000, 0x0000, 0x0000 }, /* R613 */
721 { 0x0000, 0x0000, 0x0000 }, /* R614 */
722 { 0x0000, 0x0000, 0x0000 }, /* R615 */
723 { 0x0000, 0x0000, 0x0000 }, /* R616 */
724 { 0x0000, 0x0000, 0x0000 }, /* R617 */
725 { 0x0000, 0x0000, 0x0000 }, /* R618 */
726 { 0x0000, 0x0000, 0x0000 }, /* R619 */
727 { 0x0000, 0x0000, 0x0000 }, /* R620 */
728 { 0x0000, 0x0000, 0x0000 }, /* R621 */
729 { 0x0000, 0x0000, 0x0000 }, /* R622 */
730 { 0x0000, 0x0000, 0x0000 }, /* R623 */
731 { 0x0000, 0x0000, 0x0000 }, /* R624 */
732 { 0x0000, 0x0000, 0x0000 }, /* R625 */
733 { 0x0000, 0x0000, 0x0000 }, /* R626 */
734 { 0x0000, 0x0000, 0x0000 }, /* R627 */
735 { 0x0000, 0x0000, 0x0000 }, /* R628 */
736 { 0x0000, 0x0000, 0x0000 }, /* R629 */
737 { 0x0000, 0x0000, 0x0000 }, /* R630 */
738 { 0x0000, 0x0000, 0x0000 }, /* R631 */
739 { 0x0000, 0x0000, 0x0000 }, /* R632 */
740 { 0x0000, 0x0000, 0x0000 }, /* R633 */
741 { 0x0000, 0x0000, 0x0000 }, /* R634 */
742 { 0x0000, 0x0000, 0x0000 }, /* R635 */
743 { 0x0000, 0x0000, 0x0000 }, /* R636 */
744 { 0x0000, 0x0000, 0x0000 }, /* R637 */
745 { 0x0000, 0x0000, 0x0000 }, /* R638 */
746 { 0x0000, 0x0000, 0x0000 }, /* R639 */
747 { 0x0000, 0x0000, 0x0000 }, /* R640 */
748 { 0x0000, 0x0000, 0x0000 }, /* R641 */
749 { 0x0000, 0x0000, 0x0000 }, /* R642 */
750 { 0x0000, 0x0000, 0x0000 }, /* R643 */
751 { 0x0000, 0x0000, 0x0000 }, /* R644 */
752 { 0x0000, 0x0000, 0x0000 }, /* R645 */
753 { 0x0000, 0x0000, 0x0000 }, /* R646 */
754 { 0x0000, 0x0000, 0x0000 }, /* R647 */
755 { 0x0000, 0x0000, 0x0000 }, /* R648 */
756 { 0x0000, 0x0000, 0x0000 }, /* R649 */
757 { 0x0000, 0x0000, 0x0000 }, /* R650 */
758 { 0x0000, 0x0000, 0x0000 }, /* R651 */
759 { 0x0000, 0x0000, 0x0000 }, /* R652 */
760 { 0x0000, 0x0000, 0x0000 }, /* R653 */
761 { 0x0000, 0x0000, 0x0000 }, /* R654 */
762 { 0x0000, 0x0000, 0x0000 }, /* R655 */
763 { 0x0000, 0x0000, 0x0000 }, /* R656 */
764 { 0x0000, 0x0000, 0x0000 }, /* R657 */
765 { 0x0000, 0x0000, 0x0000 }, /* R658 */
766 { 0x0000, 0x0000, 0x0000 }, /* R659 */
767 { 0x0000, 0x0000, 0x0000 }, /* R660 */
768 { 0x0000, 0x0000, 0x0000 }, /* R661 */
769 { 0x0000, 0x0000, 0x0000 }, /* R662 */
770 { 0x0000, 0x0000, 0x0000 }, /* R663 */
771 { 0x0000, 0x0000, 0x0000 }, /* R664 */
772 { 0x0000, 0x0000, 0x0000 }, /* R665 */
773 { 0x0000, 0x0000, 0x0000 }, /* R666 */
774 { 0x0000, 0x0000, 0x0000 }, /* R667 */
775 { 0x0000, 0x0000, 0x0000 }, /* R668 */
776 { 0x0000, 0x0000, 0x0000 }, /* R669 */
777 { 0x0000, 0x0000, 0x0000 }, /* R670 */
778 { 0x0000, 0x0000, 0x0000 }, /* R671 */
779 { 0x0000, 0x0000, 0x0000 }, /* R672 */
780 { 0x0000, 0x0000, 0x0000 }, /* R673 */
781 { 0x0000, 0x0000, 0x0000 }, /* R674 */
782 { 0x0000, 0x0000, 0x0000 }, /* R675 */
783 { 0x0000, 0x0000, 0x0000 }, /* R676 */
784 { 0x0000, 0x0000, 0x0000 }, /* R677 */
785 { 0x0000, 0x0000, 0x0000 }, /* R678 */
786 { 0x0000, 0x0000, 0x0000 }, /* R679 */
787 { 0x0000, 0x0000, 0x0000 }, /* R680 */
788 { 0x0000, 0x0000, 0x0000 }, /* R681 */
789 { 0x0000, 0x0000, 0x0000 }, /* R682 */
790 { 0x0000, 0x0000, 0x0000 }, /* R683 */
791 { 0x0000, 0x0000, 0x0000 }, /* R684 */
792 { 0x0000, 0x0000, 0x0000 }, /* R685 */
793 { 0x0000, 0x0000, 0x0000 }, /* R686 */
794 { 0x0000, 0x0000, 0x0000 }, /* R687 */
795 { 0x0000, 0x0000, 0x0000 }, /* R688 */
796 { 0x0000, 0x0000, 0x0000 }, /* R689 */
797 { 0x0000, 0x0000, 0x0000 }, /* R690 */
798 { 0x0000, 0x0000, 0x0000 }, /* R691 */
799 { 0x0000, 0x0000, 0x0000 }, /* R692 */
800 { 0x0000, 0x0000, 0x0000 }, /* R693 */
801 { 0x0000, 0x0000, 0x0000 }, /* R694 */
802 { 0x0000, 0x0000, 0x0000 }, /* R695 */
803 { 0x0000, 0x0000, 0x0000 }, /* R696 */
804 { 0x0000, 0x0000, 0x0000 }, /* R697 */
805 { 0x0000, 0x0000, 0x0000 }, /* R698 */
806 { 0x0000, 0x0000, 0x0000 }, /* R699 */
807 { 0x0000, 0x0000, 0x0000 }, /* R700 */
808 { 0x0000, 0x0000, 0x0000 }, /* R701 */
809 { 0x0000, 0x0000, 0x0000 }, /* R702 */
810 { 0x0000, 0x0000, 0x0000 }, /* R703 */
811 { 0x0000, 0x0000, 0x0000 }, /* R704 */
812 { 0x0000, 0x0000, 0x0000 }, /* R705 */
813 { 0x0000, 0x0000, 0x0000 }, /* R706 */
814 { 0x0000, 0x0000, 0x0000 }, /* R707 */
815 { 0x0000, 0x0000, 0x0000 }, /* R708 */
816 { 0x0000, 0x0000, 0x0000 }, /* R709 */
817 { 0x0000, 0x0000, 0x0000 }, /* R710 */
818 { 0x0000, 0x0000, 0x0000 }, /* R711 */
819 { 0x0000, 0x0000, 0x0000 }, /* R712 */
820 { 0x0000, 0x0000, 0x0000 }, /* R713 */
821 { 0x0000, 0x0000, 0x0000 }, /* R714 */
822 { 0x0000, 0x0000, 0x0000 }, /* R715 */
823 { 0x0000, 0x0000, 0x0000 }, /* R716 */
824 { 0x0000, 0x0000, 0x0000 }, /* R717 */
825 { 0x0000, 0x0000, 0x0000 }, /* R718 */
826 { 0x0000, 0x0000, 0x0000 }, /* R719 */
827 { 0x0000, 0x0000, 0x0000 }, /* R720 */
828 { 0x0000, 0x0000, 0x0000 }, /* R721 */
829 { 0x0000, 0x0000, 0x0000 }, /* R722 */
830 { 0x0000, 0x0000, 0x0000 }, /* R723 */
831 { 0x0000, 0x0000, 0x0000 }, /* R724 */
832 { 0x0000, 0x0000, 0x0000 }, /* R725 */
833 { 0x0000, 0x0000, 0x0000 }, /* R726 */
834 { 0x0000, 0x0000, 0x0000 }, /* R727 */
835 { 0x0000, 0x0000, 0x0000 }, /* R728 */
836 { 0x0000, 0x0000, 0x0000 }, /* R729 */
837 { 0x0000, 0x0000, 0x0000 }, /* R730 */
838 { 0x0000, 0x0000, 0x0000 }, /* R731 */
839 { 0x0000, 0x0000, 0x0000 }, /* R732 */
840 { 0x0000, 0x0000, 0x0000 }, /* R733 */
841 { 0x0000, 0x0000, 0x0000 }, /* R734 */
842 { 0x0000, 0x0000, 0x0000 }, /* R735 */
843 { 0x0000, 0x0000, 0x0000 }, /* R736 */
844 { 0x0000, 0x0000, 0x0000 }, /* R737 */
845 { 0x0000, 0x0000, 0x0000 }, /* R738 */
846 { 0x0000, 0x0000, 0x0000 }, /* R739 */
847 { 0x0000, 0x0000, 0x0000 }, /* R740 */
848 { 0x0000, 0x0000, 0x0000 }, /* R741 */
849 { 0x0000, 0x0000, 0x0000 }, /* R742 */
850 { 0x0000, 0x0000, 0x0000 }, /* R743 */
851 { 0x0000, 0x0000, 0x0000 }, /* R744 */
852 { 0x0000, 0x0000, 0x0000 }, /* R745 */
853 { 0x0000, 0x0000, 0x0000 }, /* R746 */
854 { 0x0000, 0x0000, 0x0000 }, /* R747 */
855 { 0x0000, 0x0000, 0x0000 }, /* R748 */
856 { 0x0000, 0x0000, 0x0000 }, /* R749 */
857 { 0x0000, 0x0000, 0x0000 }, /* R750 */
858 { 0x0000, 0x0000, 0x0000 }, /* R751 */
859 { 0x0000, 0x0000, 0x0000 }, /* R752 */
860 { 0x0000, 0x0000, 0x0000 }, /* R753 */
861 { 0x0000, 0x0000, 0x0000 }, /* R754 */
862 { 0x0000, 0x0000, 0x0000 }, /* R755 */
863 { 0x0000, 0x0000, 0x0000 }, /* R756 */
864 { 0x0000, 0x0000, 0x0000 }, /* R757 */
865 { 0x0000, 0x0000, 0x0000 }, /* R758 */
866 { 0x0000, 0x0000, 0x0000 }, /* R759 */
867 { 0x0000, 0x0000, 0x0000 }, /* R760 */
868 { 0x0000, 0x0000, 0x0000 }, /* R761 */
869 { 0x0000, 0x0000, 0x0000 }, /* R762 */
870 { 0x0000, 0x0000, 0x0000 }, /* R763 */
871 { 0x0000, 0x0000, 0x0000 }, /* R764 */
872 { 0x0000, 0x0000, 0x0000 }, /* R765 */
873 { 0x0000, 0x0000, 0x0000 }, /* R766 */
874 { 0x0000, 0x0000, 0x0000 }, /* R767 */
875 { 0xE1F8, 0xE1F8, 0x0000 }, /* R768 - AIF1 Control (1) */
876 { 0xCD1F, 0xCD1F, 0x0000 }, /* R769 - AIF1 Control (2) */
877 { 0xF000, 0xF000, 0x0000 }, /* R770 - AIF1 Master/Slave */
878 { 0x01F0, 0x01F0, 0x0000 }, /* R771 - AIF1 BCLK */
879 { 0x0FFF, 0x0FFF, 0x0000 }, /* R772 - AIF1ADC LRCLK */
880 { 0x0FFF, 0x0FFF, 0x0000 }, /* R773 - AIF1DAC LRCLK */
881 { 0x0003, 0x0003, 0x0000 }, /* R774 - AIF1DAC Data */
882 { 0x0003, 0x0003, 0x0000 }, /* R775 - AIF1ADC Data */
883 { 0x0000, 0x0000, 0x0000 }, /* R776 */
884 { 0x0000, 0x0000, 0x0000 }, /* R777 */
885 { 0x0000, 0x0000, 0x0000 }, /* R778 */
886 { 0x0000, 0x0000, 0x0000 }, /* R779 */
887 { 0x0000, 0x0000, 0x0000 }, /* R780 */
888 { 0x0000, 0x0000, 0x0000 }, /* R781 */
889 { 0x0000, 0x0000, 0x0000 }, /* R782 */
890 { 0x0000, 0x0000, 0x0000 }, /* R783 */
891 { 0xF1F8, 0xF1F8, 0x0000 }, /* R784 - AIF2 Control (1) */
892 { 0xFD1F, 0xFD1F, 0x0000 }, /* R785 - AIF2 Control (2) */
893 { 0xF000, 0xF000, 0x0000 }, /* R786 - AIF2 Master/Slave */
894 { 0x01F0, 0x01F0, 0x0000 }, /* R787 - AIF2 BCLK */
895 { 0x0FFF, 0x0FFF, 0x0000 }, /* R788 - AIF2ADC LRCLK */
896 { 0x0FFF, 0x0FFF, 0x0000 }, /* R789 - AIF2DAC LRCLK */
897 { 0x0003, 0x0003, 0x0000 }, /* R790 - AIF2DAC Data */
898 { 0x0003, 0x0003, 0x0000 }, /* R791 - AIF2ADC Data */
899 { 0x0000, 0x0000, 0x0000 }, /* R792 */
900 { 0x0000, 0x0000, 0x0000 }, /* R793 */
901 { 0x0000, 0x0000, 0x0000 }, /* R794 */
902 { 0x0000, 0x0000, 0x0000 }, /* R795 */
903 { 0x0000, 0x0000, 0x0000 }, /* R796 */
904 { 0x0000, 0x0000, 0x0000 }, /* R797 */
905 { 0x0000, 0x0000, 0x0000 }, /* R798 */
906 { 0x0000, 0x0000, 0x0000 }, /* R799 */
907 { 0x0000, 0x0000, 0x0000 }, /* R800 */
908 { 0x0000, 0x0000, 0x0000 }, /* R801 */
909 { 0x0000, 0x0000, 0x0000 }, /* R802 */
910 { 0x0000, 0x0000, 0x0000 }, /* R803 */
911 { 0x0000, 0x0000, 0x0000 }, /* R804 */
912 { 0x0000, 0x0000, 0x0000 }, /* R805 */
913 { 0x0000, 0x0000, 0x0000 }, /* R806 */
914 { 0x0000, 0x0000, 0x0000 }, /* R807 */
915 { 0x0000, 0x0000, 0x0000 }, /* R808 */
916 { 0x0000, 0x0000, 0x0000 }, /* R809 */
917 { 0x0000, 0x0000, 0x0000 }, /* R810 */
918 { 0x0000, 0x0000, 0x0000 }, /* R811 */
919 { 0x0000, 0x0000, 0x0000 }, /* R812 */
920 { 0x0000, 0x0000, 0x0000 }, /* R813 */
921 { 0x0000, 0x0000, 0x0000 }, /* R814 */
922 { 0x0000, 0x0000, 0x0000 }, /* R815 */
923 { 0x0000, 0x0000, 0x0000 }, /* R816 */
924 { 0x0000, 0x0000, 0x0000 }, /* R817 */
925 { 0x0000, 0x0000, 0x0000 }, /* R818 */
926 { 0x0000, 0x0000, 0x0000 }, /* R819 */
927 { 0x0000, 0x0000, 0x0000 }, /* R820 */
928 { 0x0000, 0x0000, 0x0000 }, /* R821 */
929 { 0x0000, 0x0000, 0x0000 }, /* R822 */
930 { 0x0000, 0x0000, 0x0000 }, /* R823 */
931 { 0x0000, 0x0000, 0x0000 }, /* R824 */
932 { 0x0000, 0x0000, 0x0000 }, /* R825 */
933 { 0x0000, 0x0000, 0x0000 }, /* R826 */
934 { 0x0000, 0x0000, 0x0000 }, /* R827 */
935 { 0x0000, 0x0000, 0x0000 }, /* R828 */
936 { 0x0000, 0x0000, 0x0000 }, /* R829 */
937 { 0x0000, 0x0000, 0x0000 }, /* R830 */
938 { 0x0000, 0x0000, 0x0000 }, /* R831 */
939 { 0x0000, 0x0000, 0x0000 }, /* R832 */
940 { 0x0000, 0x0000, 0x0000 }, /* R833 */
941 { 0x0000, 0x0000, 0x0000 }, /* R834 */
942 { 0x0000, 0x0000, 0x0000 }, /* R835 */
943 { 0x0000, 0x0000, 0x0000 }, /* R836 */
944 { 0x0000, 0x0000, 0x0000 }, /* R837 */
945 { 0x0000, 0x0000, 0x0000 }, /* R838 */
946 { 0x0000, 0x0000, 0x0000 }, /* R839 */
947 { 0x0000, 0x0000, 0x0000 }, /* R840 */
948 { 0x0000, 0x0000, 0x0000 }, /* R841 */
949 { 0x0000, 0x0000, 0x0000 }, /* R842 */
950 { 0x0000, 0x0000, 0x0000 }, /* R843 */
951 { 0x0000, 0x0000, 0x0000 }, /* R844 */
952 { 0x0000, 0x0000, 0x0000 }, /* R845 */
953 { 0x0000, 0x0000, 0x0000 }, /* R846 */
954 { 0x0000, 0x0000, 0x0000 }, /* R847 */
955 { 0x0000, 0x0000, 0x0000 }, /* R848 */
956 { 0x0000, 0x0000, 0x0000 }, /* R849 */
957 { 0x0000, 0x0000, 0x0000 }, /* R850 */
958 { 0x0000, 0x0000, 0x0000 }, /* R851 */
959 { 0x0000, 0x0000, 0x0000 }, /* R852 */
960 { 0x0000, 0x0000, 0x0000 }, /* R853 */
961 { 0x0000, 0x0000, 0x0000 }, /* R854 */
962 { 0x0000, 0x0000, 0x0000 }, /* R855 */
963 { 0x0000, 0x0000, 0x0000 }, /* R856 */
964 { 0x0000, 0x0000, 0x0000 }, /* R857 */
965 { 0x0000, 0x0000, 0x0000 }, /* R858 */
966 { 0x0000, 0x0000, 0x0000 }, /* R859 */
967 { 0x0000, 0x0000, 0x0000 }, /* R860 */
968 { 0x0000, 0x0000, 0x0000 }, /* R861 */
969 { 0x0000, 0x0000, 0x0000 }, /* R862 */
970 { 0x0000, 0x0000, 0x0000 }, /* R863 */
971 { 0x0000, 0x0000, 0x0000 }, /* R864 */
972 { 0x0000, 0x0000, 0x0000 }, /* R865 */
973 { 0x0000, 0x0000, 0x0000 }, /* R866 */
974 { 0x0000, 0x0000, 0x0000 }, /* R867 */
975 { 0x0000, 0x0000, 0x0000 }, /* R868 */
976 { 0x0000, 0x0000, 0x0000 }, /* R869 */
977 { 0x0000, 0x0000, 0x0000 }, /* R870 */
978 { 0x0000, 0x0000, 0x0000 }, /* R871 */
979 { 0x0000, 0x0000, 0x0000 }, /* R872 */
980 { 0x0000, 0x0000, 0x0000 }, /* R873 */
981 { 0x0000, 0x0000, 0x0000 }, /* R874 */
982 { 0x0000, 0x0000, 0x0000 }, /* R875 */
983 { 0x0000, 0x0000, 0x0000 }, /* R876 */
984 { 0x0000, 0x0000, 0x0000 }, /* R877 */
985 { 0x0000, 0x0000, 0x0000 }, /* R878 */
986 { 0x0000, 0x0000, 0x0000 }, /* R879 */
987 { 0x0000, 0x0000, 0x0000 }, /* R880 */
988 { 0x0000, 0x0000, 0x0000 }, /* R881 */
989 { 0x0000, 0x0000, 0x0000 }, /* R882 */
990 { 0x0000, 0x0000, 0x0000 }, /* R883 */
991 { 0x0000, 0x0000, 0x0000 }, /* R884 */
992 { 0x0000, 0x0000, 0x0000 }, /* R885 */
993 { 0x0000, 0x0000, 0x0000 }, /* R886 */
994 { 0x0000, 0x0000, 0x0000 }, /* R887 */
995 { 0x0000, 0x0000, 0x0000 }, /* R888 */
996 { 0x0000, 0x0000, 0x0000 }, /* R889 */
997 { 0x0000, 0x0000, 0x0000 }, /* R890 */
998 { 0x0000, 0x0000, 0x0000 }, /* R891 */
999 { 0x0000, 0x0000, 0x0000 }, /* R892 */
1000 { 0x0000, 0x0000, 0x0000 }, /* R893 */
1001 { 0x0000, 0x0000, 0x0000 }, /* R894 */
1002 { 0x0000, 0x0000, 0x0000 }, /* R895 */
1003 { 0x0000, 0x0000, 0x0000 }, /* R896 */
1004 { 0x0000, 0x0000, 0x0000 }, /* R897 */
1005 { 0x0000, 0x0000, 0x0000 }, /* R898 */
1006 { 0x0000, 0x0000, 0x0000 }, /* R899 */
1007 { 0x0000, 0x0000, 0x0000 }, /* R900 */
1008 { 0x0000, 0x0000, 0x0000 }, /* R901 */
1009 { 0x0000, 0x0000, 0x0000 }, /* R902 */
1010 { 0x0000, 0x0000, 0x0000 }, /* R903 */
1011 { 0x0000, 0x0000, 0x0000 }, /* R904 */
1012 { 0x0000, 0x0000, 0x0000 }, /* R905 */
1013 { 0x0000, 0x0000, 0x0000 }, /* R906 */
1014 { 0x0000, 0x0000, 0x0000 }, /* R907 */
1015 { 0x0000, 0x0000, 0x0000 }, /* R908 */
1016 { 0x0000, 0x0000, 0x0000 }, /* R909 */
1017 { 0x0000, 0x0000, 0x0000 }, /* R910 */
1018 { 0x0000, 0x0000, 0x0000 }, /* R911 */
1019 { 0x0000, 0x0000, 0x0000 }, /* R912 */
1020 { 0x0000, 0x0000, 0x0000 }, /* R913 */
1021 { 0x0000, 0x0000, 0x0000 }, /* R914 */
1022 { 0x0000, 0x0000, 0x0000 }, /* R915 */
1023 { 0x0000, 0x0000, 0x0000 }, /* R916 */
1024 { 0x0000, 0x0000, 0x0000 }, /* R917 */
1025 { 0x0000, 0x0000, 0x0000 }, /* R918 */
1026 { 0x0000, 0x0000, 0x0000 }, /* R919 */
1027 { 0x0000, 0x0000, 0x0000 }, /* R920 */
1028 { 0x0000, 0x0000, 0x0000 }, /* R921 */
1029 { 0x0000, 0x0000, 0x0000 }, /* R922 */
1030 { 0x0000, 0x0000, 0x0000 }, /* R923 */
1031 { 0x0000, 0x0000, 0x0000 }, /* R924 */
1032 { 0x0000, 0x0000, 0x0000 }, /* R925 */
1033 { 0x0000, 0x0000, 0x0000 }, /* R926 */
1034 { 0x0000, 0x0000, 0x0000 }, /* R927 */
1035 { 0x0000, 0x0000, 0x0000 }, /* R928 */
1036 { 0x0000, 0x0000, 0x0000 }, /* R929 */
1037 { 0x0000, 0x0000, 0x0000 }, /* R930 */
1038 { 0x0000, 0x0000, 0x0000 }, /* R931 */
1039 { 0x0000, 0x0000, 0x0000 }, /* R932 */
1040 { 0x0000, 0x0000, 0x0000 }, /* R933 */
1041 { 0x0000, 0x0000, 0x0000 }, /* R934 */
1042 { 0x0000, 0x0000, 0x0000 }, /* R935 */
1043 { 0x0000, 0x0000, 0x0000 }, /* R936 */
1044 { 0x0000, 0x0000, 0x0000 }, /* R937 */
1045 { 0x0000, 0x0000, 0x0000 }, /* R938 */
1046 { 0x0000, 0x0000, 0x0000 }, /* R939 */
1047 { 0x0000, 0x0000, 0x0000 }, /* R940 */
1048 { 0x0000, 0x0000, 0x0000 }, /* R941 */
1049 { 0x0000, 0x0000, 0x0000 }, /* R942 */
1050 { 0x0000, 0x0000, 0x0000 }, /* R943 */
1051 { 0x0000, 0x0000, 0x0000 }, /* R944 */
1052 { 0x0000, 0x0000, 0x0000 }, /* R945 */
1053 { 0x0000, 0x0000, 0x0000 }, /* R946 */
1054 { 0x0000, 0x0000, 0x0000 }, /* R947 */
1055 { 0x0000, 0x0000, 0x0000 }, /* R948 */
1056 { 0x0000, 0x0000, 0x0000 }, /* R949 */
1057 { 0x0000, 0x0000, 0x0000 }, /* R950 */
1058 { 0x0000, 0x0000, 0x0000 }, /* R951 */
1059 { 0x0000, 0x0000, 0x0000 }, /* R952 */
1060 { 0x0000, 0x0000, 0x0000 }, /* R953 */
1061 { 0x0000, 0x0000, 0x0000 }, /* R954 */
1062 { 0x0000, 0x0000, 0x0000 }, /* R955 */
1063 { 0x0000, 0x0000, 0x0000 }, /* R956 */
1064 { 0x0000, 0x0000, 0x0000 }, /* R957 */
1065 { 0x0000, 0x0000, 0x0000 }, /* R958 */
1066 { 0x0000, 0x0000, 0x0000 }, /* R959 */
1067 { 0x0000, 0x0000, 0x0000 }, /* R960 */
1068 { 0x0000, 0x0000, 0x0000 }, /* R961 */
1069 { 0x0000, 0x0000, 0x0000 }, /* R962 */
1070 { 0x0000, 0x0000, 0x0000 }, /* R963 */
1071 { 0x0000, 0x0000, 0x0000 }, /* R964 */
1072 { 0x0000, 0x0000, 0x0000 }, /* R965 */
1073 { 0x0000, 0x0000, 0x0000 }, /* R966 */
1074 { 0x0000, 0x0000, 0x0000 }, /* R967 */
1075 { 0x0000, 0x0000, 0x0000 }, /* R968 */
1076 { 0x0000, 0x0000, 0x0000 }, /* R969 */
1077 { 0x0000, 0x0000, 0x0000 }, /* R970 */
1078 { 0x0000, 0x0000, 0x0000 }, /* R971 */
1079 { 0x0000, 0x0000, 0x0000 }, /* R972 */
1080 { 0x0000, 0x0000, 0x0000 }, /* R973 */
1081 { 0x0000, 0x0000, 0x0000 }, /* R974 */
1082 { 0x0000, 0x0000, 0x0000 }, /* R975 */
1083 { 0x0000, 0x0000, 0x0000 }, /* R976 */
1084 { 0x0000, 0x0000, 0x0000 }, /* R977 */
1085 { 0x0000, 0x0000, 0x0000 }, /* R978 */
1086 { 0x0000, 0x0000, 0x0000 }, /* R979 */
1087 { 0x0000, 0x0000, 0x0000 }, /* R980 */
1088 { 0x0000, 0x0000, 0x0000 }, /* R981 */
1089 { 0x0000, 0x0000, 0x0000 }, /* R982 */
1090 { 0x0000, 0x0000, 0x0000 }, /* R983 */
1091 { 0x0000, 0x0000, 0x0000 }, /* R984 */
1092 { 0x0000, 0x0000, 0x0000 }, /* R985 */
1093 { 0x0000, 0x0000, 0x0000 }, /* R986 */
1094 { 0x0000, 0x0000, 0x0000 }, /* R987 */
1095 { 0x0000, 0x0000, 0x0000 }, /* R988 */
1096 { 0x0000, 0x0000, 0x0000 }, /* R989 */
1097 { 0x0000, 0x0000, 0x0000 }, /* R990 */
1098 { 0x0000, 0x0000, 0x0000 }, /* R991 */
1099 { 0x0000, 0x0000, 0x0000 }, /* R992 */
1100 { 0x0000, 0x0000, 0x0000 }, /* R993 */
1101 { 0x0000, 0x0000, 0x0000 }, /* R994 */
1102 { 0x0000, 0x0000, 0x0000 }, /* R995 */
1103 { 0x0000, 0x0000, 0x0000 }, /* R996 */
1104 { 0x0000, 0x0000, 0x0000 }, /* R997 */
1105 { 0x0000, 0x0000, 0x0000 }, /* R998 */
1106 { 0x0000, 0x0000, 0x0000 }, /* R999 */
1107 { 0x0000, 0x0000, 0x0000 }, /* R1000 */
1108 { 0x0000, 0x0000, 0x0000 }, /* R1001 */
1109 { 0x0000, 0x0000, 0x0000 }, /* R1002 */
1110 { 0x0000, 0x0000, 0x0000 }, /* R1003 */
1111 { 0x0000, 0x0000, 0x0000 }, /* R1004 */
1112 { 0x0000, 0x0000, 0x0000 }, /* R1005 */
1113 { 0x0000, 0x0000, 0x0000 }, /* R1006 */
1114 { 0x0000, 0x0000, 0x0000 }, /* R1007 */
1115 { 0x0000, 0x0000, 0x0000 }, /* R1008 */
1116 { 0x0000, 0x0000, 0x0000 }, /* R1009 */
1117 { 0x0000, 0x0000, 0x0000 }, /* R1010 */
1118 { 0x0000, 0x0000, 0x0000 }, /* R1011 */
1119 { 0x0000, 0x0000, 0x0000 }, /* R1012 */
1120 { 0x0000, 0x0000, 0x0000 }, /* R1013 */
1121 { 0x0000, 0x0000, 0x0000 }, /* R1014 */
1122 { 0x0000, 0x0000, 0x0000 }, /* R1015 */
1123 { 0x0000, 0x0000, 0x0000 }, /* R1016 */
1124 { 0x0000, 0x0000, 0x0000 }, /* R1017 */
1125 { 0x0000, 0x0000, 0x0000 }, /* R1018 */
1126 { 0x0000, 0x0000, 0x0000 }, /* R1019 */
1127 { 0x0000, 0x0000, 0x0000 }, /* R1020 */
1128 { 0x0000, 0x0000, 0x0000 }, /* R1021 */
1129 { 0x0000, 0x0000, 0x0000 }, /* R1022 */
1130 { 0x0000, 0x0000, 0x0000 }, /* R1023 */
1131 { 0x00FF, 0x01FF, 0x0000 }, /* R1024 - AIF1 ADC1 Left Volume */
1132 { 0x00FF, 0x01FF, 0x0000 }, /* R1025 - AIF1 ADC1 Right Volume */
1133 { 0x00FF, 0x01FF, 0x0000 }, /* R1026 - AIF1 DAC1 Left Volume */
1134 { 0x00FF, 0x01FF, 0x0000 }, /* R1027 - AIF1 DAC1 Right Volume */
1135 { 0x00FF, 0x01FF, 0x0000 }, /* R1028 - AIF1 ADC2 Left Volume */
1136 { 0x00FF, 0x01FF, 0x0000 }, /* R1029 - AIF1 ADC2 Right Volume */
1137 { 0x00FF, 0x01FF, 0x0000 }, /* R1030 - AIF1 DAC2 Left Volume */
1138 { 0x00FF, 0x01FF, 0x0000 }, /* R1031 - AIF1 DAC2 Right Volume */
1139 { 0x0000, 0x0000, 0x0000 }, /* R1032 */
1140 { 0x0000, 0x0000, 0x0000 }, /* R1033 */
1141 { 0x0000, 0x0000, 0x0000 }, /* R1034 */
1142 { 0x0000, 0x0000, 0x0000 }, /* R1035 */
1143 { 0x0000, 0x0000, 0x0000 }, /* R1036 */
1144 { 0x0000, 0x0000, 0x0000 }, /* R1037 */
1145 { 0x0000, 0x0000, 0x0000 }, /* R1038 */
1146 { 0x0000, 0x0000, 0x0000 }, /* R1039 */
1147 { 0xF800, 0xF800, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
1148 { 0x7800, 0x7800, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
1149 { 0x0000, 0x0000, 0x0000 }, /* R1042 */
1150 { 0x0000, 0x0000, 0x0000 }, /* R1043 */
1151 { 0x0000, 0x0000, 0x0000 }, /* R1044 */
1152 { 0x0000, 0x0000, 0x0000 }, /* R1045 */
1153 { 0x0000, 0x0000, 0x0000 }, /* R1046 */
1154 { 0x0000, 0x0000, 0x0000 }, /* R1047 */
1155 { 0x0000, 0x0000, 0x0000 }, /* R1048 */
1156 { 0x0000, 0x0000, 0x0000 }, /* R1049 */
1157 { 0x0000, 0x0000, 0x0000 }, /* R1050 */
1158 { 0x0000, 0x0000, 0x0000 }, /* R1051 */
1159 { 0x0000, 0x0000, 0x0000 }, /* R1052 */
1160 { 0x0000, 0x0000, 0x0000 }, /* R1053 */
1161 { 0x0000, 0x0000, 0x0000 }, /* R1054 */
1162 { 0x0000, 0x0000, 0x0000 }, /* R1055 */
1163 { 0x02B6, 0x02B6, 0x0000 }, /* R1056 - AIF1 DAC1 Filters (1) */
1164 { 0x3F00, 0x3F00, 0x0000 }, /* R1057 - AIF1 DAC1 Filters (2) */
1165 { 0x02B6, 0x02B6, 0x0000 }, /* R1058 - AIF1 DAC2 Filters (1) */
1166 { 0x3F00, 0x3F00, 0x0000 }, /* R1059 - AIF1 DAC2 Filters (2) */
1167 { 0x0000, 0x0000, 0x0000 }, /* R1060 */
1168 { 0x0000, 0x0000, 0x0000 }, /* R1061 */
1169 { 0x0000, 0x0000, 0x0000 }, /* R1062 */
1170 { 0x0000, 0x0000, 0x0000 }, /* R1063 */
1171 { 0x0000, 0x0000, 0x0000 }, /* R1064 */
1172 { 0x0000, 0x0000, 0x0000 }, /* R1065 */
1173 { 0x0000, 0x0000, 0x0000 }, /* R1066 */
1174 { 0x0000, 0x0000, 0x0000 }, /* R1067 */
1175 { 0x0000, 0x0000, 0x0000 }, /* R1068 */
1176 { 0x0000, 0x0000, 0x0000 }, /* R1069 */
1177 { 0x0000, 0x0000, 0x0000 }, /* R1070 */
1178 { 0x0000, 0x0000, 0x0000 }, /* R1071 */
1179 { 0x0000, 0x0000, 0x0000 }, /* R1072 */
1180 { 0x0000, 0x0000, 0x0000 }, /* R1073 */
1181 { 0x0000, 0x0000, 0x0000 }, /* R1074 */
1182 { 0x0000, 0x0000, 0x0000 }, /* R1075 */
1183 { 0x0000, 0x0000, 0x0000 }, /* R1076 */
1184 { 0x0000, 0x0000, 0x0000 }, /* R1077 */
1185 { 0x0000, 0x0000, 0x0000 }, /* R1078 */
1186 { 0x0000, 0x0000, 0x0000 }, /* R1079 */
1187 { 0x0000, 0x0000, 0x0000 }, /* R1080 */
1188 { 0x0000, 0x0000, 0x0000 }, /* R1081 */
1189 { 0x0000, 0x0000, 0x0000 }, /* R1082 */
1190 { 0x0000, 0x0000, 0x0000 }, /* R1083 */
1191 { 0x0000, 0x0000, 0x0000 }, /* R1084 */
1192 { 0x0000, 0x0000, 0x0000 }, /* R1085 */
1193 { 0x0000, 0x0000, 0x0000 }, /* R1086 */
1194 { 0x0000, 0x0000, 0x0000 }, /* R1087 */
1195 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1088 - AIF1 DRC1 (1) */
1196 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1089 - AIF1 DRC1 (2) */
1197 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
1198 { 0x07FF, 0x07FF, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
1199 { 0x03FF, 0x03FF, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
1200 { 0x0000, 0x0000, 0x0000 }, /* R1093 */
1201 { 0x0000, 0x0000, 0x0000 }, /* R1094 */
1202 { 0x0000, 0x0000, 0x0000 }, /* R1095 */
1203 { 0x0000, 0x0000, 0x0000 }, /* R1096 */
1204 { 0x0000, 0x0000, 0x0000 }, /* R1097 */
1205 { 0x0000, 0x0000, 0x0000 }, /* R1098 */
1206 { 0x0000, 0x0000, 0x0000 }, /* R1099 */
1207 { 0x0000, 0x0000, 0x0000 }, /* R1100 */
1208 { 0x0000, 0x0000, 0x0000 }, /* R1101 */
1209 { 0x0000, 0x0000, 0x0000 }, /* R1102 */
1210 { 0x0000, 0x0000, 0x0000 }, /* R1103 */
1211 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1104 - AIF1 DRC2 (1) */
1212 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1105 - AIF1 DRC2 (2) */
1213 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
1214 { 0x07FF, 0x07FF, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
1215 { 0x03FF, 0x03FF, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
1216 { 0x0000, 0x0000, 0x0000 }, /* R1109 */
1217 { 0x0000, 0x0000, 0x0000 }, /* R1110 */
1218 { 0x0000, 0x0000, 0x0000 }, /* R1111 */
1219 { 0x0000, 0x0000, 0x0000 }, /* R1112 */
1220 { 0x0000, 0x0000, 0x0000 }, /* R1113 */
1221 { 0x0000, 0x0000, 0x0000 }, /* R1114 */
1222 { 0x0000, 0x0000, 0x0000 }, /* R1115 */
1223 { 0x0000, 0x0000, 0x0000 }, /* R1116 */
1224 { 0x0000, 0x0000, 0x0000 }, /* R1117 */
1225 { 0x0000, 0x0000, 0x0000 }, /* R1118 */
1226 { 0x0000, 0x0000, 0x0000 }, /* R1119 */
1227 { 0x0000, 0x0000, 0x0000 }, /* R1120 */
1228 { 0x0000, 0x0000, 0x0000 }, /* R1121 */
1229 { 0x0000, 0x0000, 0x0000 }, /* R1122 */
1230 { 0x0000, 0x0000, 0x0000 }, /* R1123 */
1231 { 0x0000, 0x0000, 0x0000 }, /* R1124 */
1232 { 0x0000, 0x0000, 0x0000 }, /* R1125 */
1233 { 0x0000, 0x0000, 0x0000 }, /* R1126 */
1234 { 0x0000, 0x0000, 0x0000 }, /* R1127 */
1235 { 0x0000, 0x0000, 0x0000 }, /* R1128 */
1236 { 0x0000, 0x0000, 0x0000 }, /* R1129 */
1237 { 0x0000, 0x0000, 0x0000 }, /* R1130 */
1238 { 0x0000, 0x0000, 0x0000 }, /* R1131 */
1239 { 0x0000, 0x0000, 0x0000 }, /* R1132 */
1240 { 0x0000, 0x0000, 0x0000 }, /* R1133 */
1241 { 0x0000, 0x0000, 0x0000 }, /* R1134 */
1242 { 0x0000, 0x0000, 0x0000 }, /* R1135 */
1243 { 0x0000, 0x0000, 0x0000 }, /* R1136 */
1244 { 0x0000, 0x0000, 0x0000 }, /* R1137 */
1245 { 0x0000, 0x0000, 0x0000 }, /* R1138 */
1246 { 0x0000, 0x0000, 0x0000 }, /* R1139 */
1247 { 0x0000, 0x0000, 0x0000 }, /* R1140 */
1248 { 0x0000, 0x0000, 0x0000 }, /* R1141 */
1249 { 0x0000, 0x0000, 0x0000 }, /* R1142 */
1250 { 0x0000, 0x0000, 0x0000 }, /* R1143 */
1251 { 0x0000, 0x0000, 0x0000 }, /* R1144 */
1252 { 0x0000, 0x0000, 0x0000 }, /* R1145 */
1253 { 0x0000, 0x0000, 0x0000 }, /* R1146 */
1254 { 0x0000, 0x0000, 0x0000 }, /* R1147 */
1255 { 0x0000, 0x0000, 0x0000 }, /* R1148 */
1256 { 0x0000, 0x0000, 0x0000 }, /* R1149 */
1257 { 0x0000, 0x0000, 0x0000 }, /* R1150 */
1258 { 0x0000, 0x0000, 0x0000 }, /* R1151 */
1259 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
1260 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
1261 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
1262 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
1263 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
1264 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
1265 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
1266 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
1267 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
1268 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
1269 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
1270 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
1271 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
1272 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
1273 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
1274 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
1275 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
1276 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
1277 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
1278 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
1279 { 0x0000, 0x0000, 0x0000 }, /* R1172 */
1280 { 0x0000, 0x0000, 0x0000 }, /* R1173 */
1281 { 0x0000, 0x0000, 0x0000 }, /* R1174 */
1282 { 0x0000, 0x0000, 0x0000 }, /* R1175 */
1283 { 0x0000, 0x0000, 0x0000 }, /* R1176 */
1284 { 0x0000, 0x0000, 0x0000 }, /* R1177 */
1285 { 0x0000, 0x0000, 0x0000 }, /* R1178 */
1286 { 0x0000, 0x0000, 0x0000 }, /* R1179 */
1287 { 0x0000, 0x0000, 0x0000 }, /* R1180 */
1288 { 0x0000, 0x0000, 0x0000 }, /* R1181 */
1289 { 0x0000, 0x0000, 0x0000 }, /* R1182 */
1290 { 0x0000, 0x0000, 0x0000 }, /* R1183 */
1291 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
1292 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
1293 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
1294 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
1295 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
1296 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
1297 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
1298 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
1299 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
1300 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
1301 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
1302 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
1303 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
1304 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
1305 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
1306 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
1307 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
1308 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
1309 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
1310 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
1311 { 0x0000, 0x0000, 0x0000 }, /* R1204 */
1312 { 0x0000, 0x0000, 0x0000 }, /* R1205 */
1313 { 0x0000, 0x0000, 0x0000 }, /* R1206 */
1314 { 0x0000, 0x0000, 0x0000 }, /* R1207 */
1315 { 0x0000, 0x0000, 0x0000 }, /* R1208 */
1316 { 0x0000, 0x0000, 0x0000 }, /* R1209 */
1317 { 0x0000, 0x0000, 0x0000 }, /* R1210 */
1318 { 0x0000, 0x0000, 0x0000 }, /* R1211 */
1319 { 0x0000, 0x0000, 0x0000 }, /* R1212 */
1320 { 0x0000, 0x0000, 0x0000 }, /* R1213 */
1321 { 0x0000, 0x0000, 0x0000 }, /* R1214 */
1322 { 0x0000, 0x0000, 0x0000 }, /* R1215 */
1323 { 0x0000, 0x0000, 0x0000 }, /* R1216 */
1324 { 0x0000, 0x0000, 0x0000 }, /* R1217 */
1325 { 0x0000, 0x0000, 0x0000 }, /* R1218 */
1326 { 0x0000, 0x0000, 0x0000 }, /* R1219 */
1327 { 0x0000, 0x0000, 0x0000 }, /* R1220 */
1328 { 0x0000, 0x0000, 0x0000 }, /* R1221 */
1329 { 0x0000, 0x0000, 0x0000 }, /* R1222 */
1330 { 0x0000, 0x0000, 0x0000 }, /* R1223 */
1331 { 0x0000, 0x0000, 0x0000 }, /* R1224 */
1332 { 0x0000, 0x0000, 0x0000 }, /* R1225 */
1333 { 0x0000, 0x0000, 0x0000 }, /* R1226 */
1334 { 0x0000, 0x0000, 0x0000 }, /* R1227 */
1335 { 0x0000, 0x0000, 0x0000 }, /* R1228 */
1336 { 0x0000, 0x0000, 0x0000 }, /* R1229 */
1337 { 0x0000, 0x0000, 0x0000 }, /* R1230 */
1338 { 0x0000, 0x0000, 0x0000 }, /* R1231 */
1339 { 0x0000, 0x0000, 0x0000 }, /* R1232 */
1340 { 0x0000, 0x0000, 0x0000 }, /* R1233 */
1341 { 0x0000, 0x0000, 0x0000 }, /* R1234 */
1342 { 0x0000, 0x0000, 0x0000 }, /* R1235 */
1343 { 0x0000, 0x0000, 0x0000 }, /* R1236 */
1344 { 0x0000, 0x0000, 0x0000 }, /* R1237 */
1345 { 0x0000, 0x0000, 0x0000 }, /* R1238 */
1346 { 0x0000, 0x0000, 0x0000 }, /* R1239 */
1347 { 0x0000, 0x0000, 0x0000 }, /* R1240 */
1348 { 0x0000, 0x0000, 0x0000 }, /* R1241 */
1349 { 0x0000, 0x0000, 0x0000 }, /* R1242 */
1350 { 0x0000, 0x0000, 0x0000 }, /* R1243 */
1351 { 0x0000, 0x0000, 0x0000 }, /* R1244 */
1352 { 0x0000, 0x0000, 0x0000 }, /* R1245 */
1353 { 0x0000, 0x0000, 0x0000 }, /* R1246 */
1354 { 0x0000, 0x0000, 0x0000 }, /* R1247 */
1355 { 0x0000, 0x0000, 0x0000 }, /* R1248 */
1356 { 0x0000, 0x0000, 0x0000 }, /* R1249 */
1357 { 0x0000, 0x0000, 0x0000 }, /* R1250 */
1358 { 0x0000, 0x0000, 0x0000 }, /* R1251 */
1359 { 0x0000, 0x0000, 0x0000 }, /* R1252 */
1360 { 0x0000, 0x0000, 0x0000 }, /* R1253 */
1361 { 0x0000, 0x0000, 0x0000 }, /* R1254 */
1362 { 0x0000, 0x0000, 0x0000 }, /* R1255 */
1363 { 0x0000, 0x0000, 0x0000 }, /* R1256 */
1364 { 0x0000, 0x0000, 0x0000 }, /* R1257 */
1365 { 0x0000, 0x0000, 0x0000 }, /* R1258 */
1366 { 0x0000, 0x0000, 0x0000 }, /* R1259 */
1367 { 0x0000, 0x0000, 0x0000 }, /* R1260 */
1368 { 0x0000, 0x0000, 0x0000 }, /* R1261 */
1369 { 0x0000, 0x0000, 0x0000 }, /* R1262 */
1370 { 0x0000, 0x0000, 0x0000 }, /* R1263 */
1371 { 0x0000, 0x0000, 0x0000 }, /* R1264 */
1372 { 0x0000, 0x0000, 0x0000 }, /* R1265 */
1373 { 0x0000, 0x0000, 0x0000 }, /* R1266 */
1374 { 0x0000, 0x0000, 0x0000 }, /* R1267 */
1375 { 0x0000, 0x0000, 0x0000 }, /* R1268 */
1376 { 0x0000, 0x0000, 0x0000 }, /* R1269 */
1377 { 0x0000, 0x0000, 0x0000 }, /* R1270 */
1378 { 0x0000, 0x0000, 0x0000 }, /* R1271 */
1379 { 0x0000, 0x0000, 0x0000 }, /* R1272 */
1380 { 0x0000, 0x0000, 0x0000 }, /* R1273 */
1381 { 0x0000, 0x0000, 0x0000 }, /* R1274 */
1382 { 0x0000, 0x0000, 0x0000 }, /* R1275 */
1383 { 0x0000, 0x0000, 0x0000 }, /* R1276 */
1384 { 0x0000, 0x0000, 0x0000 }, /* R1277 */
1385 { 0x0000, 0x0000, 0x0000 }, /* R1278 */
1386 { 0x0000, 0x0000, 0x0000 }, /* R1279 */
1387 { 0x00FF, 0x01FF, 0x0000 }, /* R1280 - AIF2 ADC Left Volume */
1388 { 0x00FF, 0x01FF, 0x0000 }, /* R1281 - AIF2 ADC Right Volume */
1389 { 0x00FF, 0x01FF, 0x0000 }, /* R1282 - AIF2 DAC Left Volume */
1390 { 0x00FF, 0x01FF, 0x0000 }, /* R1283 - AIF2 DAC Right Volume */
1391 { 0x0000, 0x0000, 0x0000 }, /* R1284 */
1392 { 0x0000, 0x0000, 0x0000 }, /* R1285 */
1393 { 0x0000, 0x0000, 0x0000 }, /* R1286 */
1394 { 0x0000, 0x0000, 0x0000 }, /* R1287 */
1395 { 0x0000, 0x0000, 0x0000 }, /* R1288 */
1396 { 0x0000, 0x0000, 0x0000 }, /* R1289 */
1397 { 0x0000, 0x0000, 0x0000 }, /* R1290 */
1398 { 0x0000, 0x0000, 0x0000 }, /* R1291 */
1399 { 0x0000, 0x0000, 0x0000 }, /* R1292 */
1400 { 0x0000, 0x0000, 0x0000 }, /* R1293 */
1401 { 0x0000, 0x0000, 0x0000 }, /* R1294 */
1402 { 0x0000, 0x0000, 0x0000 }, /* R1295 */
1403 { 0xF800, 0xF800, 0x0000 }, /* R1296 - AIF2 ADC Filters */
1404 { 0x0000, 0x0000, 0x0000 }, /* R1297 */
1405 { 0x0000, 0x0000, 0x0000 }, /* R1298 */
1406 { 0x0000, 0x0000, 0x0000 }, /* R1299 */
1407 { 0x0000, 0x0000, 0x0000 }, /* R1300 */
1408 { 0x0000, 0x0000, 0x0000 }, /* R1301 */
1409 { 0x0000, 0x0000, 0x0000 }, /* R1302 */
1410 { 0x0000, 0x0000, 0x0000 }, /* R1303 */
1411 { 0x0000, 0x0000, 0x0000 }, /* R1304 */
1412 { 0x0000, 0x0000, 0x0000 }, /* R1305 */
1413 { 0x0000, 0x0000, 0x0000 }, /* R1306 */
1414 { 0x0000, 0x0000, 0x0000 }, /* R1307 */
1415 { 0x0000, 0x0000, 0x0000 }, /* R1308 */
1416 { 0x0000, 0x0000, 0x0000 }, /* R1309 */
1417 { 0x0000, 0x0000, 0x0000 }, /* R1310 */
1418 { 0x0000, 0x0000, 0x0000 }, /* R1311 */
1419 { 0x02B6, 0x02B6, 0x0000 }, /* R1312 - AIF2 DAC Filters (1) */
1420 { 0x3F00, 0x3F00, 0x0000 }, /* R1313 - AIF2 DAC Filters (2) */
1421 { 0x0000, 0x0000, 0x0000 }, /* R1314 */
1422 { 0x0000, 0x0000, 0x0000 }, /* R1315 */
1423 { 0x0000, 0x0000, 0x0000 }, /* R1316 */
1424 { 0x0000, 0x0000, 0x0000 }, /* R1317 */
1425 { 0x0000, 0x0000, 0x0000 }, /* R1318 */
1426 { 0x0000, 0x0000, 0x0000 }, /* R1319 */
1427 { 0x0000, 0x0000, 0x0000 }, /* R1320 */
1428 { 0x0000, 0x0000, 0x0000 }, /* R1321 */
1429 { 0x0000, 0x0000, 0x0000 }, /* R1322 */
1430 { 0x0000, 0x0000, 0x0000 }, /* R1323 */
1431 { 0x0000, 0x0000, 0x0000 }, /* R1324 */
1432 { 0x0000, 0x0000, 0x0000 }, /* R1325 */
1433 { 0x0000, 0x0000, 0x0000 }, /* R1326 */
1434 { 0x0000, 0x0000, 0x0000 }, /* R1327 */
1435 { 0x0000, 0x0000, 0x0000 }, /* R1328 */
1436 { 0x0000, 0x0000, 0x0000 }, /* R1329 */
1437 { 0x0000, 0x0000, 0x0000 }, /* R1330 */
1438 { 0x0000, 0x0000, 0x0000 }, /* R1331 */
1439 { 0x0000, 0x0000, 0x0000 }, /* R1332 */
1440 { 0x0000, 0x0000, 0x0000 }, /* R1333 */
1441 { 0x0000, 0x0000, 0x0000 }, /* R1334 */
1442 { 0x0000, 0x0000, 0x0000 }, /* R1335 */
1443 { 0x0000, 0x0000, 0x0000 }, /* R1336 */
1444 { 0x0000, 0x0000, 0x0000 }, /* R1337 */
1445 { 0x0000, 0x0000, 0x0000 }, /* R1338 */
1446 { 0x0000, 0x0000, 0x0000 }, /* R1339 */
1447 { 0x0000, 0x0000, 0x0000 }, /* R1340 */
1448 { 0x0000, 0x0000, 0x0000 }, /* R1341 */
1449 { 0x0000, 0x0000, 0x0000 }, /* R1342 */
1450 { 0x0000, 0x0000, 0x0000 }, /* R1343 */
1451 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1344 - AIF2 DRC (1) */
1452 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1345 - AIF2 DRC (2) */
1453 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1346 - AIF2 DRC (3) */
1454 { 0x07FF, 0x07FF, 0x0000 }, /* R1347 - AIF2 DRC (4) */
1455 { 0x03FF, 0x03FF, 0x0000 }, /* R1348 - AIF2 DRC (5) */
1456 { 0x0000, 0x0000, 0x0000 }, /* R1349 */
1457 { 0x0000, 0x0000, 0x0000 }, /* R1350 */
1458 { 0x0000, 0x0000, 0x0000 }, /* R1351 */
1459 { 0x0000, 0x0000, 0x0000 }, /* R1352 */
1460 { 0x0000, 0x0000, 0x0000 }, /* R1353 */
1461 { 0x0000, 0x0000, 0x0000 }, /* R1354 */
1462 { 0x0000, 0x0000, 0x0000 }, /* R1355 */
1463 { 0x0000, 0x0000, 0x0000 }, /* R1356 */
1464 { 0x0000, 0x0000, 0x0000 }, /* R1357 */
1465 { 0x0000, 0x0000, 0x0000 }, /* R1358 */
1466 { 0x0000, 0x0000, 0x0000 }, /* R1359 */
1467 { 0x0000, 0x0000, 0x0000 }, /* R1360 */
1468 { 0x0000, 0x0000, 0x0000 }, /* R1361 */
1469 { 0x0000, 0x0000, 0x0000 }, /* R1362 */
1470 { 0x0000, 0x0000, 0x0000 }, /* R1363 */
1471 { 0x0000, 0x0000, 0x0000 }, /* R1364 */
1472 { 0x0000, 0x0000, 0x0000 }, /* R1365 */
1473 { 0x0000, 0x0000, 0x0000 }, /* R1366 */
1474 { 0x0000, 0x0000, 0x0000 }, /* R1367 */
1475 { 0x0000, 0x0000, 0x0000 }, /* R1368 */
1476 { 0x0000, 0x0000, 0x0000 }, /* R1369 */
1477 { 0x0000, 0x0000, 0x0000 }, /* R1370 */
1478 { 0x0000, 0x0000, 0x0000 }, /* R1371 */
1479 { 0x0000, 0x0000, 0x0000 }, /* R1372 */
1480 { 0x0000, 0x0000, 0x0000 }, /* R1373 */
1481 { 0x0000, 0x0000, 0x0000 }, /* R1374 */
1482 { 0x0000, 0x0000, 0x0000 }, /* R1375 */
1483 { 0x0000, 0x0000, 0x0000 }, /* R1376 */
1484 { 0x0000, 0x0000, 0x0000 }, /* R1377 */
1485 { 0x0000, 0x0000, 0x0000 }, /* R1378 */
1486 { 0x0000, 0x0000, 0x0000 }, /* R1379 */
1487 { 0x0000, 0x0000, 0x0000 }, /* R1380 */
1488 { 0x0000, 0x0000, 0x0000 }, /* R1381 */
1489 { 0x0000, 0x0000, 0x0000 }, /* R1382 */
1490 { 0x0000, 0x0000, 0x0000 }, /* R1383 */
1491 { 0x0000, 0x0000, 0x0000 }, /* R1384 */
1492 { 0x0000, 0x0000, 0x0000 }, /* R1385 */
1493 { 0x0000, 0x0000, 0x0000 }, /* R1386 */
1494 { 0x0000, 0x0000, 0x0000 }, /* R1387 */
1495 { 0x0000, 0x0000, 0x0000 }, /* R1388 */
1496 { 0x0000, 0x0000, 0x0000 }, /* R1389 */
1497 { 0x0000, 0x0000, 0x0000 }, /* R1390 */
1498 { 0x0000, 0x0000, 0x0000 }, /* R1391 */
1499 { 0x0000, 0x0000, 0x0000 }, /* R1392 */
1500 { 0x0000, 0x0000, 0x0000 }, /* R1393 */
1501 { 0x0000, 0x0000, 0x0000 }, /* R1394 */
1502 { 0x0000, 0x0000, 0x0000 }, /* R1395 */
1503 { 0x0000, 0x0000, 0x0000 }, /* R1396 */
1504 { 0x0000, 0x0000, 0x0000 }, /* R1397 */
1505 { 0x0000, 0x0000, 0x0000 }, /* R1398 */
1506 { 0x0000, 0x0000, 0x0000 }, /* R1399 */
1507 { 0x0000, 0x0000, 0x0000 }, /* R1400 */
1508 { 0x0000, 0x0000, 0x0000 }, /* R1401 */
1509 { 0x0000, 0x0000, 0x0000 }, /* R1402 */
1510 { 0x0000, 0x0000, 0x0000 }, /* R1403 */
1511 { 0x0000, 0x0000, 0x0000 }, /* R1404 */
1512 { 0x0000, 0x0000, 0x0000 }, /* R1405 */
1513 { 0x0000, 0x0000, 0x0000 }, /* R1406 */
1514 { 0x0000, 0x0000, 0x0000 }, /* R1407 */
1515 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1408 - AIF2 EQ Gains (1) */
1516 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1409 - AIF2 EQ Gains (2) */
1517 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1410 - AIF2 EQ Band 1 A */
1518 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1411 - AIF2 EQ Band 1 B */
1519 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1412 - AIF2 EQ Band 1 PG */
1520 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1413 - AIF2 EQ Band 2 A */
1521 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1414 - AIF2 EQ Band 2 B */
1522 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1415 - AIF2 EQ Band 2 C */
1523 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1416 - AIF2 EQ Band 2 PG */
1524 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1417 - AIF2 EQ Band 3 A */
1525 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1418 - AIF2 EQ Band 3 B */
1526 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1419 - AIF2 EQ Band 3 C */
1527 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1420 - AIF2 EQ Band 3 PG */
1528 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1421 - AIF2 EQ Band 4 A */
1529 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1422 - AIF2 EQ Band 4 B */
1530 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1423 - AIF2 EQ Band 4 C */
1531 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1424 - AIF2 EQ Band 4 PG */
1532 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1425 - AIF2 EQ Band 5 A */
1533 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1426 - AIF2 EQ Band 5 B */
1534 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1427 - AIF2 EQ Band 5 PG */
1535 { 0x0000, 0x0000, 0x0000 }, /* R1428 */
1536 { 0x0000, 0x0000, 0x0000 }, /* R1429 */
1537 { 0x0000, 0x0000, 0x0000 }, /* R1430 */
1538 { 0x0000, 0x0000, 0x0000 }, /* R1431 */
1539 { 0x0000, 0x0000, 0x0000 }, /* R1432 */
1540 { 0x0000, 0x0000, 0x0000 }, /* R1433 */
1541 { 0x0000, 0x0000, 0x0000 }, /* R1434 */
1542 { 0x0000, 0x0000, 0x0000 }, /* R1435 */
1543 { 0x0000, 0x0000, 0x0000 }, /* R1436 */
1544 { 0x0000, 0x0000, 0x0000 }, /* R1437 */
1545 { 0x0000, 0x0000, 0x0000 }, /* R1438 */
1546 { 0x0000, 0x0000, 0x0000 }, /* R1439 */
1547 { 0x0000, 0x0000, 0x0000 }, /* R1440 */
1548 { 0x0000, 0x0000, 0x0000 }, /* R1441 */
1549 { 0x0000, 0x0000, 0x0000 }, /* R1442 */
1550 { 0x0000, 0x0000, 0x0000 }, /* R1443 */
1551 { 0x0000, 0x0000, 0x0000 }, /* R1444 */
1552 { 0x0000, 0x0000, 0x0000 }, /* R1445 */
1553 { 0x0000, 0x0000, 0x0000 }, /* R1446 */
1554 { 0x0000, 0x0000, 0x0000 }, /* R1447 */
1555 { 0x0000, 0x0000, 0x0000 }, /* R1448 */
1556 { 0x0000, 0x0000, 0x0000 }, /* R1449 */
1557 { 0x0000, 0x0000, 0x0000 }, /* R1450 */
1558 { 0x0000, 0x0000, 0x0000 }, /* R1451 */
1559 { 0x0000, 0x0000, 0x0000 }, /* R1452 */
1560 { 0x0000, 0x0000, 0x0000 }, /* R1453 */
1561 { 0x0000, 0x0000, 0x0000 }, /* R1454 */
1562 { 0x0000, 0x0000, 0x0000 }, /* R1455 */
1563 { 0x0000, 0x0000, 0x0000 }, /* R1456 */
1564 { 0x0000, 0x0000, 0x0000 }, /* R1457 */
1565 { 0x0000, 0x0000, 0x0000 }, /* R1458 */
1566 { 0x0000, 0x0000, 0x0000 }, /* R1459 */
1567 { 0x0000, 0x0000, 0x0000 }, /* R1460 */
1568 { 0x0000, 0x0000, 0x0000 }, /* R1461 */
1569 { 0x0000, 0x0000, 0x0000 }, /* R1462 */
1570 { 0x0000, 0x0000, 0x0000 }, /* R1463 */
1571 { 0x0000, 0x0000, 0x0000 }, /* R1464 */
1572 { 0x0000, 0x0000, 0x0000 }, /* R1465 */
1573 { 0x0000, 0x0000, 0x0000 }, /* R1466 */
1574 { 0x0000, 0x0000, 0x0000 }, /* R1467 */
1575 { 0x0000, 0x0000, 0x0000 }, /* R1468 */
1576 { 0x0000, 0x0000, 0x0000 }, /* R1469 */
1577 { 0x0000, 0x0000, 0x0000 }, /* R1470 */
1578 { 0x0000, 0x0000, 0x0000 }, /* R1471 */
1579 { 0x0000, 0x0000, 0x0000 }, /* R1472 */
1580 { 0x0000, 0x0000, 0x0000 }, /* R1473 */
1581 { 0x0000, 0x0000, 0x0000 }, /* R1474 */
1582 { 0x0000, 0x0000, 0x0000 }, /* R1475 */
1583 { 0x0000, 0x0000, 0x0000 }, /* R1476 */
1584 { 0x0000, 0x0000, 0x0000 }, /* R1477 */
1585 { 0x0000, 0x0000, 0x0000 }, /* R1478 */
1586 { 0x0000, 0x0000, 0x0000 }, /* R1479 */
1587 { 0x0000, 0x0000, 0x0000 }, /* R1480 */
1588 { 0x0000, 0x0000, 0x0000 }, /* R1481 */
1589 { 0x0000, 0x0000, 0x0000 }, /* R1482 */
1590 { 0x0000, 0x0000, 0x0000 }, /* R1483 */
1591 { 0x0000, 0x0000, 0x0000 }, /* R1484 */
1592 { 0x0000, 0x0000, 0x0000 }, /* R1485 */
1593 { 0x0000, 0x0000, 0x0000 }, /* R1486 */
1594 { 0x0000, 0x0000, 0x0000 }, /* R1487 */
1595 { 0x0000, 0x0000, 0x0000 }, /* R1488 */
1596 { 0x0000, 0x0000, 0x0000 }, /* R1489 */
1597 { 0x0000, 0x0000, 0x0000 }, /* R1490 */
1598 { 0x0000, 0x0000, 0x0000 }, /* R1491 */
1599 { 0x0000, 0x0000, 0x0000 }, /* R1492 */
1600 { 0x0000, 0x0000, 0x0000 }, /* R1493 */
1601 { 0x0000, 0x0000, 0x0000 }, /* R1494 */
1602 { 0x0000, 0x0000, 0x0000 }, /* R1495 */
1603 { 0x0000, 0x0000, 0x0000 }, /* R1496 */
1604 { 0x0000, 0x0000, 0x0000 }, /* R1497 */
1605 { 0x0000, 0x0000, 0x0000 }, /* R1498 */
1606 { 0x0000, 0x0000, 0x0000 }, /* R1499 */
1607 { 0x0000, 0x0000, 0x0000 }, /* R1500 */
1608 { 0x0000, 0x0000, 0x0000 }, /* R1501 */
1609 { 0x0000, 0x0000, 0x0000 }, /* R1502 */
1610 { 0x0000, 0x0000, 0x0000 }, /* R1503 */
1611 { 0x0000, 0x0000, 0x0000 }, /* R1504 */
1612 { 0x0000, 0x0000, 0x0000 }, /* R1505 */
1613 { 0x0000, 0x0000, 0x0000 }, /* R1506 */
1614 { 0x0000, 0x0000, 0x0000 }, /* R1507 */
1615 { 0x0000, 0x0000, 0x0000 }, /* R1508 */
1616 { 0x0000, 0x0000, 0x0000 }, /* R1509 */
1617 { 0x0000, 0x0000, 0x0000 }, /* R1510 */
1618 { 0x0000, 0x0000, 0x0000 }, /* R1511 */
1619 { 0x0000, 0x0000, 0x0000 }, /* R1512 */
1620 { 0x0000, 0x0000, 0x0000 }, /* R1513 */
1621 { 0x0000, 0x0000, 0x0000 }, /* R1514 */
1622 { 0x0000, 0x0000, 0x0000 }, /* R1515 */
1623 { 0x0000, 0x0000, 0x0000 }, /* R1516 */
1624 { 0x0000, 0x0000, 0x0000 }, /* R1517 */
1625 { 0x0000, 0x0000, 0x0000 }, /* R1518 */
1626 { 0x0000, 0x0000, 0x0000 }, /* R1519 */
1627 { 0x0000, 0x0000, 0x0000 }, /* R1520 */
1628 { 0x0000, 0x0000, 0x0000 }, /* R1521 */
1629 { 0x0000, 0x0000, 0x0000 }, /* R1522 */
1630 { 0x0000, 0x0000, 0x0000 }, /* R1523 */
1631 { 0x0000, 0x0000, 0x0000 }, /* R1524 */
1632 { 0x0000, 0x0000, 0x0000 }, /* R1525 */
1633 { 0x0000, 0x0000, 0x0000 }, /* R1526 */
1634 { 0x0000, 0x0000, 0x0000 }, /* R1527 */
1635 { 0x0000, 0x0000, 0x0000 }, /* R1528 */
1636 { 0x0000, 0x0000, 0x0000 }, /* R1529 */
1637 { 0x0000, 0x0000, 0x0000 }, /* R1530 */
1638 { 0x0000, 0x0000, 0x0000 }, /* R1531 */
1639 { 0x0000, 0x0000, 0x0000 }, /* R1532 */
1640 { 0x0000, 0x0000, 0x0000 }, /* R1533 */
1641 { 0x0000, 0x0000, 0x0000 }, /* R1534 */
1642 { 0x0000, 0x0000, 0x0000 }, /* R1535 */
1643 { 0x01EF, 0x01EF, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
1644 { 0x0037, 0x0037, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
1645 { 0x0037, 0x0037, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
1646 { 0x01EF, 0x01EF, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
1647 { 0x0037, 0x0037, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
1648 { 0x0037, 0x0037, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
1649 { 0x0003, 0x0003, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
1650 { 0x0003, 0x0003, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
1651 { 0x0003, 0x0003, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
1652 { 0x0003, 0x0003, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
1653 { 0x0000, 0x0000, 0x0000 }, /* R1546 */
1654 { 0x0000, 0x0000, 0x0000 }, /* R1547 */
1655 { 0x0000, 0x0000, 0x0000 }, /* R1548 */
1656 { 0x0000, 0x0000, 0x0000 }, /* R1549 */
1657 { 0x0000, 0x0000, 0x0000 }, /* R1550 */
1658 { 0x0000, 0x0000, 0x0000 }, /* R1551 */
1659 { 0x02FF, 0x03FF, 0x0000 }, /* R1552 - DAC1 Left Volume */
1660 { 0x02FF, 0x03FF, 0x0000 }, /* R1553 - DAC1 Right Volume */
1661 { 0x02FF, 0x03FF, 0x0000 }, /* R1554 - DAC2 Left Volume */
1662 { 0x02FF, 0x03FF, 0x0000 }, /* R1555 - DAC2 Right Volume */
1663 { 0x0003, 0x0003, 0x0000 }, /* R1556 - DAC Softmute */
1664 { 0x0000, 0x0000, 0x0000 }, /* R1557 */
1665 { 0x0000, 0x0000, 0x0000 }, /* R1558 */
1666 { 0x0000, 0x0000, 0x0000 }, /* R1559 */
1667 { 0x0000, 0x0000, 0x0000 }, /* R1560 */
1668 { 0x0000, 0x0000, 0x0000 }, /* R1561 */
1669 { 0x0000, 0x0000, 0x0000 }, /* R1562 */
1670 { 0x0000, 0x0000, 0x0000 }, /* R1563 */
1671 { 0x0000, 0x0000, 0x0000 }, /* R1564 */
1672 { 0x0000, 0x0000, 0x0000 }, /* R1565 */
1673 { 0x0000, 0x0000, 0x0000 }, /* R1566 */
1674 { 0x0000, 0x0000, 0x0000 }, /* R1567 */
1675 { 0x0003, 0x0003, 0x0000 }, /* R1568 - Oversampling */
1676 { 0x03C3, 0x03C3, 0x0000 }, /* R1569 - Sidetone */
1677};
1678
1679static int wm8994_readable(unsigned int reg)
1680{ 57{
58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
59 struct wm8994 *control = wm8994->control_data;
60
1681 switch (reg) { 61 switch (reg) {
1682 case WM8994_GPIO_1: 62 case WM8994_GPIO_1:
1683 case WM8994_GPIO_2: 63 case WM8994_GPIO_2:
@@ -1694,18 +74,27 @@ static int wm8994_readable(unsigned int reg)
1694 case WM8994_INTERRUPT_STATUS_2: 74 case WM8994_INTERRUPT_STATUS_2:
1695 case WM8994_INTERRUPT_RAW_STATUS_2: 75 case WM8994_INTERRUPT_RAW_STATUS_2:
1696 return 1; 76 return 1;
77
78 case WM8958_DSP2_PROGRAM:
79 case WM8958_DSP2_CONFIG:
80 case WM8958_DSP2_EXECCONTROL:
81 if (control->type == WM8958)
82 return 1;
83 else
84 return 0;
85
1697 default: 86 default:
1698 break; 87 break;
1699 } 88 }
1700 89
1701 if (reg >= ARRAY_SIZE(access_masks)) 90 if (reg >= WM8994_CACHE_SIZE)
1702 return 0; 91 return 0;
1703 return access_masks[reg].readable != 0; 92 return wm8994_access_masks[reg].readable != 0;
1704} 93}
1705 94
1706static int wm8994_volatile(unsigned int reg) 95static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
1707{ 96{
1708 if (reg >= WM8994_REG_CACHE_SIZE) 97 if (reg >= WM8994_CACHE_SIZE)
1709 return 1; 98 return 1;
1710 99
1711 switch (reg) { 100 switch (reg) {
@@ -1716,6 +105,8 @@ static int wm8994_volatile(unsigned int reg)
1716 case WM8994_RATE_STATUS: 105 case WM8994_RATE_STATUS:
1717 case WM8994_LDO_1: 106 case WM8994_LDO_1:
1718 case WM8994_LDO_2: 107 case WM8994_LDO_2:
108 case WM8958_DSP2_EXECCONTROL:
109 case WM8958_MIC_DETECT_3:
1719 return 1; 110 return 1;
1720 default: 111 default:
1721 return 0; 112 return 0;
@@ -1725,14 +116,16 @@ static int wm8994_volatile(unsigned int reg)
1725static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, 116static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1726 unsigned int value) 117 unsigned int value)
1727{ 118{
1728 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 119 int ret;
1729 120
1730 BUG_ON(reg > WM8994_MAX_REGISTER); 121 BUG_ON(reg > WM8994_MAX_REGISTER);
1731 122
1732 if (!wm8994_volatile(reg)) 123 if (!wm8994_volatile(codec, reg)) {
1733 wm8994->reg_cache[reg] = value; 124 ret = snd_soc_cache_write(codec, reg, value);
1734 125 if (ret != 0)
1735 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value); 126 dev_err(codec->dev, "Cache write to %x failed: %d\n",
127 reg, ret);
128 }
1736 129
1737 return wm8994_reg_write(codec->control_data, reg, value); 130 return wm8994_reg_write(codec->control_data, reg, value);
1738} 131}
@@ -1740,14 +133,22 @@ static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1740static unsigned int wm8994_read(struct snd_soc_codec *codec, 133static unsigned int wm8994_read(struct snd_soc_codec *codec,
1741 unsigned int reg) 134 unsigned int reg)
1742{ 135{
1743 u16 *reg_cache = codec->reg_cache; 136 unsigned int val;
137 int ret;
1744 138
1745 BUG_ON(reg > WM8994_MAX_REGISTER); 139 BUG_ON(reg > WM8994_MAX_REGISTER);
1746 140
1747 if (wm8994_volatile(reg)) 141 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
1748 return wm8994_reg_read(codec->control_data, reg); 142 reg < codec->driver->reg_cache_size) {
1749 else 143 ret = snd_soc_cache_read(codec, reg, &val);
1750 return reg_cache[reg]; 144 if (ret >= 0)
145 return val;
146 else
147 dev_err(codec->dev, "Cache read from %x failed: %d\n",
148 reg, ret);
149 }
150
151 return wm8994_reg_read(codec->control_data, reg);
1751} 152}
1752 153
1753static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 154static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
@@ -1839,7 +240,7 @@ static int configure_clock(struct snd_soc_codec *codec)
1839 240
1840 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); 241 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
1841 242
1842 snd_soc_dapm_sync(codec); 243 snd_soc_dapm_sync(&codec->dapm);
1843 244
1844 return 0; 245 return 0;
1845} 246}
@@ -1866,6 +267,19 @@ static const char *sidetone_hpf_text[] = {
1866static const struct soc_enum sidetone_hpf = 267static const struct soc_enum sidetone_hpf =
1867 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 268 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
1868 269
270static const char *adc_hpf_text[] = {
271 "HiFi", "Voice 1", "Voice 2", "Voice 3"
272};
273
274static const struct soc_enum aif1adc1_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
276
277static const struct soc_enum aif1adc2_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
279
280static const struct soc_enum aif2adc_hpf =
281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
282
1869static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 283static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
1870static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 284static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1871static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 285static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
@@ -1902,8 +316,6 @@ static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
1902 return snd_soc_put_volsw(kcontrol, ucontrol); 316 return snd_soc_put_volsw(kcontrol, ucontrol);
1903} 317}
1904 318
1905
1906
1907static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 319static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
1908{ 320{
1909 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 321 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
@@ -1942,7 +354,7 @@ static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
1942 struct snd_ctl_elem_value *ucontrol) 354 struct snd_ctl_elem_value *ucontrol)
1943{ 355{
1944 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 356 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1945 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 357 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1946 struct wm8994_pdata *pdata = wm8994->pdata; 358 struct wm8994_pdata *pdata = wm8994->pdata;
1947 int drc = wm8994_get_drc(kcontrol->id.name); 359 int drc = wm8994_get_drc(kcontrol->id.name);
1948 int value = ucontrol->value.integer.value[0]; 360 int value = ucontrol->value.integer.value[0];
@@ -2045,7 +457,7 @@ static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
2045 struct snd_ctl_elem_value *ucontrol) 457 struct snd_ctl_elem_value *ucontrol)
2046{ 458{
2047 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 459 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2048 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 460 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2049 struct wm8994_pdata *pdata = wm8994->pdata; 461 struct wm8994_pdata *pdata = wm8994->pdata;
2050 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 462 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
2051 int value = ucontrol->value.integer.value[0]; 463 int value = ucontrol->value.integer.value[0];
@@ -2075,6 +487,44 @@ static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
2075 return 0; 487 return 0;
2076} 488}
2077 489
490static const char *aif_chan_src_text[] = {
491 "Left", "Right"
492};
493
494static const struct soc_enum aif1adcl_src =
495 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
496
497static const struct soc_enum aif1adcr_src =
498 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
499
500static const struct soc_enum aif2adcl_src =
501 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
502
503static const struct soc_enum aif2adcr_src =
504 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
505
506static const struct soc_enum aif1dacl_src =
507 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
508
509static const struct soc_enum aif1dacr_src =
510 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
511
512static const struct soc_enum aif2dacl_src =
513 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
514
515static const struct soc_enum aif2dacr_src =
516 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
517
518static const char *osr_text[] = {
519 "Low Power", "High Performance",
520};
521
522static const struct soc_enum dac_osr =
523 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
524
525static const struct soc_enum adc_osr =
526 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
527
2078static const struct snd_kcontrol_new wm8994_snd_controls[] = { 528static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2079SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 529SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
2080 WM8994_AIF1_ADC1_RIGHT_VOLUME, 530 WM8994_AIF1_ADC1_RIGHT_VOLUME,
@@ -2086,6 +536,16 @@ SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
2086 WM8994_AIF2_ADC_RIGHT_VOLUME, 536 WM8994_AIF2_ADC_RIGHT_VOLUME,
2087 1, 119, 0, digital_tlv), 537 1, 119, 0, digital_tlv),
2088 538
539SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
540SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
541SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
542SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
543
544SOC_ENUM("AIF1DACL Source", aif1dacl_src),
545SOC_ENUM("AIF1DACR Source", aif1dacr_src),
546SOC_ENUM("AIF2DACL Source", aif2dacl_src),
547SOC_ENUM("AIF2DACR Source", aif2dacr_src),
548
2089SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 549SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
2090 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 550 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2091SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 551SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
@@ -2123,6 +583,18 @@ SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2123SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 583SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
2124SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 584SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
2125 585
586SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
587SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
588
589SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
590SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
591
592SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
593SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
594
595SOC_ENUM("ADC OSR", adc_osr),
596SOC_ENUM("DAC OSR", dac_osr),
597
2126SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 598SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
2127 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 599 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2128SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 600SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
@@ -2145,15 +617,15 @@ SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
2145 617
2146SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 618SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
2147 10, 15, 0, wm8994_3d_tlv), 619 10, 15, 0, wm8994_3d_tlv),
2148SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 620SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
2149 8, 1, 0), 621 8, 1, 0),
2150SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 622SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
2151 10, 15, 0, wm8994_3d_tlv), 623 10, 15, 0, wm8994_3d_tlv),
2152SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 624SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2153 8, 1, 0), 625 8, 1, 0),
2154SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 626SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
2155 10, 15, 0, wm8994_3d_tlv), 627 10, 15, 0, wm8994_3d_tlv),
2156SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 628SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
2157 8, 1, 0), 629 8, 1, 0),
2158}; 630};
2159 631
@@ -2192,6 +664,10 @@ SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
2192 eq_tlv), 664 eq_tlv),
2193}; 665};
2194 666
667static const struct snd_kcontrol_new wm8958_snd_controls[] = {
668SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
669};
670
2195static int clk_sys_event(struct snd_soc_dapm_widget *w, 671static int clk_sys_event(struct snd_soc_dapm_widget *w,
2196 struct snd_kcontrol *kcontrol, int event) 672 struct snd_kcontrol *kcontrol, int event)
2197{ 673{
@@ -2211,6 +687,7 @@ static int clk_sys_event(struct snd_soc_dapm_widget *w,
2211 687
2212static void wm8994_update_class_w(struct snd_soc_codec *codec) 688static void wm8994_update_class_w(struct snd_soc_codec *codec)
2213{ 689{
690 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2214 int enable = 1; 691 int enable = 1;
2215 int source = 0; /* GCC flow analysis can't track enable */ 692 int source = 0; /* GCC flow analysis can't track enable */
2216 int reg, reg_r; 693 int reg, reg_r;
@@ -2261,12 +738,128 @@ static void wm8994_update_class_w(struct snd_soc_codec *codec)
2261 WM8994_CP_DYN_PWR | 738 WM8994_CP_DYN_PWR |
2262 WM8994_CP_DYN_SRC_SEL_MASK, 739 WM8994_CP_DYN_SRC_SEL_MASK,
2263 source | WM8994_CP_DYN_PWR); 740 source | WM8994_CP_DYN_PWR);
741 wm8994->hubs.class_w = true;
2264 742
2265 } else { 743 } else {
2266 dev_dbg(codec->dev, "Class W disabled\n"); 744 dev_dbg(codec->dev, "Class W disabled\n");
2267 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 745 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2268 WM8994_CP_DYN_PWR, 0); 746 WM8994_CP_DYN_PWR, 0);
747 wm8994->hubs.class_w = false;
748 }
749}
750
751static int late_enable_ev(struct snd_soc_dapm_widget *w,
752 struct snd_kcontrol *kcontrol, int event)
753{
754 struct snd_soc_codec *codec = w->codec;
755 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
756
757 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU:
759 if (wm8994->aif1clk_enable) {
760 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
761 WM8994_AIF1CLK_ENA_MASK,
762 WM8994_AIF1CLK_ENA);
763 wm8994->aif1clk_enable = 0;
764 }
765 if (wm8994->aif2clk_enable) {
766 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
767 WM8994_AIF2CLK_ENA_MASK,
768 WM8994_AIF2CLK_ENA);
769 wm8994->aif2clk_enable = 0;
770 }
771 break;
772 }
773
774 /* We may also have postponed startup of DSP, handle that. */
775 wm8958_aif_ev(w, kcontrol, event);
776
777 return 0;
778}
779
780static int late_disable_ev(struct snd_soc_dapm_widget *w,
781 struct snd_kcontrol *kcontrol, int event)
782{
783 struct snd_soc_codec *codec = w->codec;
784 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
785
786 switch (event) {
787 case SND_SOC_DAPM_POST_PMD:
788 if (wm8994->aif1clk_disable) {
789 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
790 WM8994_AIF1CLK_ENA_MASK, 0);
791 wm8994->aif1clk_disable = 0;
792 }
793 if (wm8994->aif2clk_disable) {
794 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
795 WM8994_AIF2CLK_ENA_MASK, 0);
796 wm8994->aif2clk_disable = 0;
797 }
798 break;
799 }
800
801 return 0;
802}
803
804static int aif1clk_ev(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
806{
807 struct snd_soc_codec *codec = w->codec;
808 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
809
810 switch (event) {
811 case SND_SOC_DAPM_PRE_PMU:
812 wm8994->aif1clk_enable = 1;
813 break;
814 case SND_SOC_DAPM_POST_PMD:
815 wm8994->aif1clk_disable = 1;
816 break;
817 }
818
819 return 0;
820}
821
822static int aif2clk_ev(struct snd_soc_dapm_widget *w,
823 struct snd_kcontrol *kcontrol, int event)
824{
825 struct snd_soc_codec *codec = w->codec;
826 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
827
828 switch (event) {
829 case SND_SOC_DAPM_PRE_PMU:
830 wm8994->aif2clk_enable = 1;
831 break;
832 case SND_SOC_DAPM_POST_PMD:
833 wm8994->aif2clk_disable = 1;
834 break;
2269 } 835 }
836
837 return 0;
838}
839
840static int adc_mux_ev(struct snd_soc_dapm_widget *w,
841 struct snd_kcontrol *kcontrol, int event)
842{
843 late_enable_ev(w, kcontrol, event);
844 return 0;
845}
846
847static int micbias_ev(struct snd_soc_dapm_widget *w,
848 struct snd_kcontrol *kcontrol, int event)
849{
850 late_enable_ev(w, kcontrol, event);
851 return 0;
852}
853
854static int dac_ev(struct snd_soc_dapm_widget *w,
855 struct snd_kcontrol *kcontrol, int event)
856{
857 struct snd_soc_codec *codec = w->codec;
858 unsigned int mask = 1 << w->shift;
859
860 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
861 mask, mask);
862 return 0;
2270} 863}
2271 864
2272static const char *hp_mux_text[] = { 865static const char *hp_mux_text[] = {
@@ -2284,7 +877,8 @@ static const char *hp_mux_text[] = {
2284static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol, 877static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
2285 struct snd_ctl_elem_value *ucontrol) 878 struct snd_ctl_elem_value *ucontrol)
2286{ 879{
2287 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); 880 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
881 struct snd_soc_dapm_widget *w = wlist->widgets[0];
2288 struct snd_soc_codec *codec = w->codec; 882 struct snd_soc_codec *codec = w->codec;
2289 int ret; 883 int ret;
2290 884
@@ -2411,7 +1005,8 @@ SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2411static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1005static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
2412 struct snd_ctl_elem_value *ucontrol) 1006 struct snd_ctl_elem_value *ucontrol)
2413{ 1007{
2414 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); 1008 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1009 struct snd_soc_dapm_widget *w = wlist->widgets[0];
2415 struct snd_soc_codec *codec = w->codec; 1010 struct snd_soc_codec *codec = w->codec;
2416 int ret; 1011 int ret;
2417 1012
@@ -2495,20 +1090,109 @@ static const struct snd_kcontrol_new aif2adc_mux =
2495 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1090 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
2496 1091
2497static const char *aif3adc_text[] = { 1092static const char *aif3adc_text[] = {
2498 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", 1093 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
2499}; 1094};
2500 1095
2501static const struct soc_enum aif3adc_enum = 1096static const struct soc_enum wm8994_aif3adc_enum =
2502 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1097 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
2503 1098
2504static const struct snd_kcontrol_new aif3adc_mux = 1099static const struct snd_kcontrol_new wm8994_aif3adc_mux =
2505 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum); 1100 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1101
1102static const struct soc_enum wm8958_aif3adc_enum =
1103 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1104
1105static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1106 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1107
1108static const char *mono_pcm_out_text[] = {
1109 "None", "AIF2ADCL", "AIF2ADCR",
1110};
1111
1112static const struct soc_enum mono_pcm_out_enum =
1113 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1114
1115static const struct snd_kcontrol_new mono_pcm_out_mux =
1116 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1117
1118static const char *aif2dac_src_text[] = {
1119 "AIF2", "AIF3",
1120};
1121
1122/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1123static const struct soc_enum aif2dacl_src_enum =
1124 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1125
1126static const struct snd_kcontrol_new aif2dacl_src_mux =
1127 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1128
1129static const struct soc_enum aif2dacr_src_enum =
1130 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1131
1132static const struct snd_kcontrol_new aif2dacr_src_mux =
1133 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1134
1135static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1136SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1137 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1138SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1139 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1140
1141SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1145SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1146 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1147SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1148 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1149
1150SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1151};
1152
1153static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1154SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1155SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1156};
1157
1158static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1159SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1160 dac_ev, SND_SOC_DAPM_PRE_PMU),
1161SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1162 dac_ev, SND_SOC_DAPM_PRE_PMU),
1163SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1164 dac_ev, SND_SOC_DAPM_PRE_PMU),
1165SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1166 dac_ev, SND_SOC_DAPM_PRE_PMU),
1167};
1168
1169static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1170SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1171SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1172SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1173SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1174};
1175
1176static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1177SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1178 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1179SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1180 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1181};
1182
1183static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1184SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1185SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1186};
2506 1187
2507static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1188static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2508SND_SOC_DAPM_INPUT("DMIC1DAT"), 1189SND_SOC_DAPM_INPUT("DMIC1DAT"),
2509SND_SOC_DAPM_INPUT("DMIC2DAT"), 1190SND_SOC_DAPM_INPUT("DMIC2DAT"),
2510SND_SOC_DAPM_INPUT("Clock"), 1191SND_SOC_DAPM_INPUT("Clock"),
2511 1192
1193SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1194 SND_SOC_DAPM_PRE_PMU),
1195
2512SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1196SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
2513 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1197 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2514 1198
@@ -2516,26 +1200,27 @@ SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
2516SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0), 1200SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
2517SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0), 1201SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
2518 1202
2519SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0), 1203SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
2520SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
2521
2522SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
2523 0, WM8994_POWER_MANAGEMENT_4, 9, 0), 1204 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
2524SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 1205SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
2525 0, WM8994_POWER_MANAGEMENT_4, 8, 0), 1206 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
2526SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, 1207SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
2527 WM8994_POWER_MANAGEMENT_5, 9, 0), 1208 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
2528SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, 1209 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2529 WM8994_POWER_MANAGEMENT_5, 8, 0), 1210SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
2530 1211 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
2531SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 1212 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1213
1214SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
2532 0, WM8994_POWER_MANAGEMENT_4, 11, 0), 1215 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
2533SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 1216SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
2534 0, WM8994_POWER_MANAGEMENT_4, 10, 0), 1217 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
2535SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, 1218SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
2536 WM8994_POWER_MANAGEMENT_5, 11, 0), 1219 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
2537SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, 1220 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2538 WM8994_POWER_MANAGEMENT_5, 10, 0), 1221SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1222 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1223 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2539 1224
2540SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1225SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
2541 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1226 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
@@ -2564,19 +1249,21 @@ SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
2564 WM8994_POWER_MANAGEMENT_4, 13, 0), 1249 WM8994_POWER_MANAGEMENT_4, 13, 0),
2565SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1250SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
2566 WM8994_POWER_MANAGEMENT_4, 12, 0), 1251 WM8994_POWER_MANAGEMENT_4, 12, 0),
2567SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0, 1252SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
2568 WM8994_POWER_MANAGEMENT_5, 13, 0), 1253 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
2569SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0, 1254 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2570 WM8994_POWER_MANAGEMENT_5, 12, 0), 1255SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1256 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1257 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2571 1258
2572SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1259SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2573SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1260SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1261SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2574SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1262SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2575 1263
2576SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1264SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
2577SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1265SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
2578SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1266SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
2579SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
2580 1267
2581SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 1268SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2582SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 1269SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
@@ -2595,14 +1282,6 @@ SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
2595SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1282SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
2596SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1283SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
2597 1284
2598SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
2599SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
2600
2601SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
2602SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
2603SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
2604SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
2605
2606SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1285SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
2607SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1286SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
2608 1287
@@ -2614,8 +1293,18 @@ SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
2614SND_SOC_DAPM_POST("Debug log", post_ev), 1293SND_SOC_DAPM_POST("Debug log", post_ev),
2615}; 1294};
2616 1295
2617static const struct snd_soc_dapm_route intercon[] = { 1296static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1297SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1298};
1299
1300static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1301SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1302SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1303SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1304SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1305};
2618 1306
1307static const struct snd_soc_dapm_route intercon[] = {
2619 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1308 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
2620 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1309 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
2621 1310
@@ -2723,9 +1412,6 @@ static const struct snd_soc_dapm_route intercon[] = {
2723 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1412 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
2724 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1413 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
2725 1414
2726 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2727 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2728
2729 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1415 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
2730 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1416 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2731 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1417 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
@@ -2735,14 +1421,12 @@ static const struct snd_soc_dapm_route intercon[] = {
2735 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1421 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
2736 1422
2737 /* DAC1 inputs */ 1423 /* DAC1 inputs */
2738 { "DAC1L", NULL, "DAC1L Mixer" },
2739 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1424 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
2740 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1425 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
2741 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1426 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
2742 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1427 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
2743 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1428 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
2744 1429
2745 { "DAC1R", NULL, "DAC1R Mixer" },
2746 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1430 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
2747 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1431 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
2748 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1432 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
@@ -2751,7 +1435,6 @@ static const struct snd_soc_dapm_route intercon[] = {
2751 1435
2752 /* DAC2/AIF2 outputs */ 1436 /* DAC2/AIF2 outputs */
2753 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1437 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
2754 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
2755 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1438 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
2756 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1439 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
2757 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1440 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
@@ -2759,13 +1442,17 @@ static const struct snd_soc_dapm_route intercon[] = {
2759 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1442 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
2760 1443
2761 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1444 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
2762 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2763 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1445 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
2764 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1446 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
2765 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1447 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
2766 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1448 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
2767 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1449 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
2768 1450
1451 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1452 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1453 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1454 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1455
2769 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1456 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
2770 1457
2771 /* AIF3 output */ 1458 /* AIF3 output */
@@ -2798,6 +1485,55 @@ static const struct snd_soc_dapm_route intercon[] = {
2798 { "Right Headphone Mux", "DAC", "DAC1R" }, 1485 { "Right Headphone Mux", "DAC", "DAC1R" },
2799}; 1486};
2800 1487
1488static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1489 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1490 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1491 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1492 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1493 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1494 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1495 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1496 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1497};
1498
1499static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1500 { "DAC1L", NULL, "DAC1L Mixer" },
1501 { "DAC1R", NULL, "DAC1R Mixer" },
1502 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1503 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1504};
1505
1506static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1507 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1508 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1509 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1510 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1511 { "MICBIAS1", NULL, "CLK_SYS" },
1512 { "MICBIAS1", NULL, "MICBIAS Supply" },
1513 { "MICBIAS2", NULL, "CLK_SYS" },
1514 { "MICBIAS2", NULL, "MICBIAS Supply" },
1515};
1516
1517static const struct snd_soc_dapm_route wm8994_intercon[] = {
1518 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1519 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1520};
1521
1522static const struct snd_soc_dapm_route wm8958_intercon[] = {
1523 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1524 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1525
1526 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1527 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1528 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1529 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1530
1531 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1532 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1533
1534 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1535};
1536
2801/* The size in bits of the FLL divide multiplied by 10 1537/* The size in bits of the FLL divide multiplied by 10
2802 * to allow rounding later */ 1538 * to allow rounding later */
2803#define FIXED_FLL_SIZE ((1 << 16) * 10) 1539#define FIXED_FLL_SIZE ((1 << 16) * 10)
@@ -2881,10 +1617,9 @@ static int wm8994_get_fll_config(struct fll_div *fll,
2881 return 0; 1617 return 0;
2882} 1618}
2883 1619
2884static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 1620static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2885 unsigned int freq_in, unsigned int freq_out) 1621 unsigned int freq_in, unsigned int freq_out)
2886{ 1622{
2887 struct snd_soc_codec *codec = dai->codec;
2888 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1623 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2889 int reg_offset, ret; 1624 int reg_offset, ret;
2890 struct fll_div fll; 1625 struct fll_div fll;
@@ -2914,6 +1649,7 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2914 /* Allow no source specification when stopping */ 1649 /* Allow no source specification when stopping */
2915 if (freq_out) 1650 if (freq_out)
2916 return -EINVAL; 1651 return -EINVAL;
1652 src = wm8994->fll[id].src;
2917 break; 1653 break;
2918 case WM8994_FLL_SRC_MCLK1: 1654 case WM8994_FLL_SRC_MCLK1:
2919 case WM8994_FLL_SRC_MCLK2: 1655 case WM8994_FLL_SRC_MCLK2:
@@ -2978,6 +1714,8 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2978 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 1714 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2979 WM8994_FLL1_ENA | WM8994_FLL1_FRAC, 1715 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2980 reg); 1716 reg);
1717
1718 msleep(5);
2981 } 1719 }
2982 1720
2983 wm8994->fll[id].in = freq_in; 1721 wm8994->fll[id].in = freq_in;
@@ -2995,8 +1733,15 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2995 return 0; 1733 return 0;
2996} 1734}
2997 1735
1736
2998static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 1737static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2999 1738
1739static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1740 unsigned int freq_in, unsigned int freq_out)
1741{
1742 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1743}
1744
3000static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 1745static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
3001 int clk_id, unsigned int freq, int dir) 1746 int clk_id, unsigned int freq, int dir)
3002{ 1747{
@@ -3071,6 +1816,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
3071static int wm8994_set_bias_level(struct snd_soc_codec *codec, 1816static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3072 enum snd_soc_bias_level level) 1817 enum snd_soc_bias_level level)
3073{ 1818{
1819 struct wm8994 *control = codec->control_data;
3074 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1820 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3075 1821
3076 switch (level) { 1822 switch (level) {
@@ -3084,16 +1830,36 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3084 break; 1830 break;
3085 1831
3086 case SND_SOC_BIAS_STANDBY: 1832 case SND_SOC_BIAS_STANDBY:
3087 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1833 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
3088 /* Tweak DC servo and DSP configuration for 1834 pm_runtime_get_sync(codec->dev);
3089 * improved performance. */ 1835
3090 if (wm8994->revision < 4) { 1836 switch (control->type) {
3091 /* Tweak DC servo and DSP configuration for 1837 case WM8994:
3092 * improved performance. */ 1838 if (wm8994->revision < 4) {
3093 snd_soc_write(codec, 0x102, 0x3); 1839 /* Tweak DC servo and DSP
3094 snd_soc_write(codec, 0x56, 0x3); 1840 * configuration for improved
3095 snd_soc_write(codec, 0x817, 0); 1841 * performance. */
3096 snd_soc_write(codec, 0x102, 0); 1842 snd_soc_write(codec, 0x102, 0x3);
1843 snd_soc_write(codec, 0x56, 0x3);
1844 snd_soc_write(codec, 0x817, 0);
1845 snd_soc_write(codec, 0x102, 0);
1846 }
1847 break;
1848
1849 case WM8958:
1850 if (wm8994->revision == 0) {
1851 /* Optimise performance for rev A */
1852 snd_soc_write(codec, 0x102, 0x3);
1853 snd_soc_write(codec, 0xcb, 0x81);
1854 snd_soc_write(codec, 0x817, 0);
1855 snd_soc_write(codec, 0x102, 0);
1856
1857 snd_soc_update_bits(codec,
1858 WM8958_CHARGE_PUMP_2,
1859 WM8958_CP_DISCH,
1860 WM8958_CP_DISCH);
1861 }
1862 break;
3097 } 1863 }
3098 1864
3099 /* Discharge LINEOUT1 & 2 */ 1865 /* Discharge LINEOUT1 & 2 */
@@ -3128,7 +1894,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3128 break; 1894 break;
3129 1895
3130 case SND_SOC_BIAS_OFF: 1896 case SND_SOC_BIAS_OFF:
3131 if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 1897 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3132 /* Switch over to startup biases */ 1898 /* Switch over to startup biases */
3133 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1899 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3134 WM8994_BIAS_SRC | 1900 WM8994_BIAS_SRC |
@@ -3160,16 +1926,21 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3160 WM8994_STARTUP_BIAS_ENA | 1926 WM8994_STARTUP_BIAS_ENA |
3161 WM8994_VMID_BUF_ENA | 1927 WM8994_VMID_BUF_ENA |
3162 WM8994_VMID_RAMP_MASK, 0); 1928 WM8994_VMID_RAMP_MASK, 0);
1929
1930 wm8994->cur_fw = NULL;
1931
1932 pm_runtime_put(codec->dev);
3163 } 1933 }
3164 break; 1934 break;
3165 } 1935 }
3166 codec->bias_level = level; 1936 codec->dapm.bias_level = level;
3167 return 0; 1937 return 0;
3168} 1938}
3169 1939
3170static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1940static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3171{ 1941{
3172 struct snd_soc_codec *codec = dai->codec; 1942 struct snd_soc_codec *codec = dai->codec;
1943 struct wm8994 *control = codec->control_data;
3173 int ms_reg; 1944 int ms_reg;
3174 int aif1_reg; 1945 int aif1_reg;
3175 int ms = 0; 1946 int ms = 0;
@@ -3254,6 +2025,13 @@ static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3254 return -EINVAL; 2025 return -EINVAL;
3255 } 2026 }
3256 2027
2028 /* The AIF2 format configuration needs to be mirrored to AIF3
2029 * on WM8958 if it's in use so just do it all the time. */
2030 if (control->type == WM8958 && dai->id == 2)
2031 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2032 WM8994_AIF1_LRCLK_INV |
2033 WM8958_AIF3_FMT_MASK, aif1);
2034
3257 snd_soc_update_bits(codec, aif1_reg, 2035 snd_soc_update_bits(codec, aif1_reg,
3258 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2036 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
3259 WM8994_AIF1_FMT_MASK, 2037 WM8994_AIF1_FMT_MASK,
@@ -3294,12 +2072,15 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3294 struct snd_soc_dai *dai) 2072 struct snd_soc_dai *dai)
3295{ 2073{
3296 struct snd_soc_codec *codec = dai->codec; 2074 struct snd_soc_codec *codec = dai->codec;
2075 struct wm8994 *control = codec->control_data;
3297 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2076 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3298 int aif1_reg; 2077 int aif1_reg;
2078 int aif2_reg;
3299 int bclk_reg; 2079 int bclk_reg;
3300 int lrclk_reg; 2080 int lrclk_reg;
3301 int rate_reg; 2081 int rate_reg;
3302 int aif1 = 0; 2082 int aif1 = 0;
2083 int aif2 = 0;
3303 int bclk = 0; 2084 int bclk = 0;
3304 int lrclk = 0; 2085 int lrclk = 0;
3305 int rate_val = 0; 2086 int rate_val = 0;
@@ -3310,24 +2091,38 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3310 switch (dai->id) { 2091 switch (dai->id) {
3311 case 1: 2092 case 1:
3312 aif1_reg = WM8994_AIF1_CONTROL_1; 2093 aif1_reg = WM8994_AIF1_CONTROL_1;
2094 aif2_reg = WM8994_AIF1_CONTROL_2;
3313 bclk_reg = WM8994_AIF1_BCLK; 2095 bclk_reg = WM8994_AIF1_BCLK;
3314 rate_reg = WM8994_AIF1_RATE; 2096 rate_reg = WM8994_AIF1_RATE;
3315 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2097 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
3316 wm8994->lrclk_shared[0]) 2098 wm8994->lrclk_shared[0]) {
3317 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2099 lrclk_reg = WM8994_AIF1DAC_LRCLK;
3318 else 2100 } else {
3319 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2101 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2102 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2103 }
3320 break; 2104 break;
3321 case 2: 2105 case 2:
3322 aif1_reg = WM8994_AIF2_CONTROL_1; 2106 aif1_reg = WM8994_AIF2_CONTROL_1;
2107 aif2_reg = WM8994_AIF2_CONTROL_2;
3323 bclk_reg = WM8994_AIF2_BCLK; 2108 bclk_reg = WM8994_AIF2_BCLK;
3324 rate_reg = WM8994_AIF2_RATE; 2109 rate_reg = WM8994_AIF2_RATE;
3325 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2110 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
3326 wm8994->lrclk_shared[1]) 2111 wm8994->lrclk_shared[1]) {
3327 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2112 lrclk_reg = WM8994_AIF2DAC_LRCLK;
3328 else 2113 } else {
3329 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2114 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2115 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2116 }
3330 break; 2117 break;
2118 case 3:
2119 switch (control->type) {
2120 case WM8958:
2121 aif1_reg = WM8958_AIF3_CONTROL_1;
2122 break;
2123 default:
2124 return 0;
2125 }
3331 default: 2126 default:
3332 return -EINVAL; 2127 return -EINVAL;
3333 } 2128 }
@@ -3365,6 +2160,10 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3365 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2160 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
3366 dai->id, wm8994->aifclk[id], bclk_rate); 2161 dai->id, wm8994->aifclk[id], bclk_rate);
3367 2162
2163 if (params_channels(params) == 1 &&
2164 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2165 aif2 |= WM8994_AIF1_MONO;
2166
3368 if (wm8994->aifclk[id] == 0) { 2167 if (wm8994->aifclk[id] == 0) {
3369 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2168 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
3370 return -EINVAL; 2169 return -EINVAL;
@@ -3408,6 +2207,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3408 lrclk, bclk_rate / lrclk); 2207 lrclk, bclk_rate / lrclk);
3409 2208
3410 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2209 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2210 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
3411 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2211 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
3412 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2212 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
3413 lrclk); 2213 lrclk);
@@ -3431,6 +2231,47 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3431 return 0; 2231 return 0;
3432} 2232}
3433 2233
2234static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2235 struct snd_pcm_hw_params *params,
2236 struct snd_soc_dai *dai)
2237{
2238 struct snd_soc_codec *codec = dai->codec;
2239 struct wm8994 *control = codec->control_data;
2240 int aif1_reg;
2241 int aif1 = 0;
2242
2243 switch (dai->id) {
2244 case 3:
2245 switch (control->type) {
2246 case WM8958:
2247 aif1_reg = WM8958_AIF3_CONTROL_1;
2248 break;
2249 default:
2250 return 0;
2251 }
2252 default:
2253 return 0;
2254 }
2255
2256 switch (params_format(params)) {
2257 case SNDRV_PCM_FORMAT_S16_LE:
2258 break;
2259 case SNDRV_PCM_FORMAT_S20_3LE:
2260 aif1 |= 0x20;
2261 break;
2262 case SNDRV_PCM_FORMAT_S24_LE:
2263 aif1 |= 0x40;
2264 break;
2265 case SNDRV_PCM_FORMAT_S32_LE:
2266 aif1 |= 0x60;
2267 break;
2268 default:
2269 return -EINVAL;
2270 }
2271
2272 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2273}
2274
3434static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2275static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
3435{ 2276{
3436 struct snd_soc_codec *codec = codec_dai->codec; 2277 struct snd_soc_codec *codec = codec_dai->codec;
@@ -3485,13 +2326,13 @@ static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3485 else 2326 else
3486 val = 0; 2327 val = 0;
3487 2328
3488 return snd_soc_update_bits(codec, reg, mask, reg); 2329 return snd_soc_update_bits(codec, reg, mask, val);
3489} 2330}
3490 2331
3491#define WM8994_RATES SNDRV_PCM_RATE_8000_96000 2332#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3492 2333
3493#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2334#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3494 SNDRV_PCM_FMTBIT_S24_LE) 2335 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3495 2336
3496static struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 2337static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3497 .set_sysclk = wm8994_set_dai_sysclk, 2338 .set_sysclk = wm8994_set_dai_sysclk,
@@ -3512,23 +2353,24 @@ static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3512}; 2353};
3513 2354
3514static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2355static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2356 .hw_params = wm8994_aif3_hw_params,
3515 .set_tristate = wm8994_set_tristate, 2357 .set_tristate = wm8994_set_tristate,
3516}; 2358};
3517 2359
3518struct snd_soc_dai wm8994_dai[] = { 2360static struct snd_soc_dai_driver wm8994_dai[] = {
3519 { 2361 {
3520 .name = "WM8994 AIF1", 2362 .name = "wm8994-aif1",
3521 .id = 1, 2363 .id = 1,
3522 .playback = { 2364 .playback = {
3523 .stream_name = "AIF1 Playback", 2365 .stream_name = "AIF1 Playback",
3524 .channels_min = 2, 2366 .channels_min = 1,
3525 .channels_max = 2, 2367 .channels_max = 2,
3526 .rates = WM8994_RATES, 2368 .rates = WM8994_RATES,
3527 .formats = WM8994_FORMATS, 2369 .formats = WM8994_FORMATS,
3528 }, 2370 },
3529 .capture = { 2371 .capture = {
3530 .stream_name = "AIF1 Capture", 2372 .stream_name = "AIF1 Capture",
3531 .channels_min = 2, 2373 .channels_min = 1,
3532 .channels_max = 2, 2374 .channels_max = 2,
3533 .rates = WM8994_RATES, 2375 .rates = WM8994_RATES,
3534 .formats = WM8994_FORMATS, 2376 .formats = WM8994_FORMATS,
@@ -3536,18 +2378,18 @@ struct snd_soc_dai wm8994_dai[] = {
3536 .ops = &wm8994_aif1_dai_ops, 2378 .ops = &wm8994_aif1_dai_ops,
3537 }, 2379 },
3538 { 2380 {
3539 .name = "WM8994 AIF2", 2381 .name = "wm8994-aif2",
3540 .id = 2, 2382 .id = 2,
3541 .playback = { 2383 .playback = {
3542 .stream_name = "AIF2 Playback", 2384 .stream_name = "AIF2 Playback",
3543 .channels_min = 2, 2385 .channels_min = 1,
3544 .channels_max = 2, 2386 .channels_max = 2,
3545 .rates = WM8994_RATES, 2387 .rates = WM8994_RATES,
3546 .formats = WM8994_FORMATS, 2388 .formats = WM8994_FORMATS,
3547 }, 2389 },
3548 .capture = { 2390 .capture = {
3549 .stream_name = "AIF2 Capture", 2391 .stream_name = "AIF2 Capture",
3550 .channels_min = 2, 2392 .channels_min = 1,
3551 .channels_max = 2, 2393 .channels_max = 2,
3552 .rates = WM8994_RATES, 2394 .rates = WM8994_RATES,
3553 .formats = WM8994_FORMATS, 2395 .formats = WM8994_FORMATS,
@@ -3555,18 +2397,18 @@ struct snd_soc_dai wm8994_dai[] = {
3555 .ops = &wm8994_aif2_dai_ops, 2397 .ops = &wm8994_aif2_dai_ops,
3556 }, 2398 },
3557 { 2399 {
3558 .name = "WM8994 AIF3", 2400 .name = "wm8994-aif3",
3559 .id = 3, 2401 .id = 3,
3560 .playback = { 2402 .playback = {
3561 .stream_name = "AIF3 Playback", 2403 .stream_name = "AIF3 Playback",
3562 .channels_min = 2, 2404 .channels_min = 1,
3563 .channels_max = 2, 2405 .channels_max = 2,
3564 .rates = WM8994_RATES, 2406 .rates = WM8994_RATES,
3565 .formats = WM8994_FORMATS, 2407 .formats = WM8994_FORMATS,
3566 }, 2408 },
3567 .capture = { 2409 .capture = {
3568 .stream_name = "AIF3 Capture", 2410 .stream_name = "AIF3 Capture",
3569 .channels_min = 2, 2411 .channels_min = 1,
3570 .channels_max = 2, 2412 .channels_max = 2,
3571 .rates = WM8994_RATES, 2413 .rates = WM8994_RATES,
3572 .formats = WM8994_FORMATS, 2414 .formats = WM8994_FORMATS,
@@ -3574,20 +2416,28 @@ struct snd_soc_dai wm8994_dai[] = {
3574 .ops = &wm8994_aif3_dai_ops, 2416 .ops = &wm8994_aif3_dai_ops,
3575 } 2417 }
3576}; 2418};
3577EXPORT_SYMBOL_GPL(wm8994_dai);
3578 2419
3579#ifdef CONFIG_PM 2420#ifdef CONFIG_PM
3580static int wm8994_suspend(struct platform_device *pdev, pm_message_t state) 2421static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
3581{ 2422{
3582 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3583 struct snd_soc_codec *codec = socdev->card->codec;
3584 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2423 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2424 struct wm8994 *control = codec->control_data;
3585 int i, ret; 2425 int i, ret;
3586 2426
2427 switch (control->type) {
2428 case WM8994:
2429 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2430 break;
2431 case WM8958:
2432 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2433 WM8958_MICD_ENA, 0);
2434 break;
2435 }
2436
3587 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 2437 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3588 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 2438 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3589 sizeof(struct fll_config)); 2439 sizeof(struct wm8994_fll_config));
3590 ret = wm8994_set_fll(&codec->dai[0], i + 1, 0, 0, 0); 2440 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3591 if (ret < 0) 2441 if (ret < 0)
3592 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 2442 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3593 i + 1, ret); 2443 i + 1, ret);
@@ -3598,31 +2448,32 @@ static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
3598 return 0; 2448 return 0;
3599} 2449}
3600 2450
3601static int wm8994_resume(struct platform_device *pdev) 2451static int wm8994_resume(struct snd_soc_codec *codec)
3602{ 2452{
3603 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3604 struct snd_soc_codec *codec = socdev->card->codec;
3605 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2453 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3606 u16 *reg_cache = codec->reg_cache; 2454 struct wm8994 *control = codec->control_data;
3607 int i, ret; 2455 int i, ret;
2456 unsigned int val, mask;
2457
2458 if (wm8994->revision < 4) {
2459 /* force a HW read */
2460 val = wm8994_reg_read(codec->control_data,
2461 WM8994_POWER_MANAGEMENT_5);
2462
2463 /* modify the cache only */
2464 codec->cache_only = 1;
2465 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2466 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2467 val &= mask;
2468 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2469 mask, val);
2470 codec->cache_only = 0;
2471 }
3608 2472
3609 /* Restore the registers */ 2473 /* Restore the registers */
3610 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) { 2474 ret = snd_soc_cache_sync(codec);
3611 switch (i) { 2475 if (ret != 0)
3612 case WM8994_LDO_1: 2476 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
3613 case WM8994_LDO_2:
3614 case WM8994_SOFTWARE_RESET:
3615 /* Handled by other MFD drivers */
3616 continue;
3617 default:
3618 break;
3619 }
3620
3621 if (!access_masks[i].writable)
3622 continue;
3623
3624 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
3625 }
3626 2477
3627 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2478 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3628 2479
@@ -3630,7 +2481,7 @@ static int wm8994_resume(struct platform_device *pdev)
3630 if (!wm8994->fll_suspend[i].out) 2481 if (!wm8994->fll_suspend[i].out)
3631 continue; 2482 continue;
3632 2483
3633 ret = wm8994_set_fll(&codec->dai[0], i + 1, 2484 ret = _wm8994_set_fll(codec, i + 1,
3634 wm8994->fll_suspend[i].src, 2485 wm8994->fll_suspend[i].src,
3635 wm8994->fll_suspend[i].in, 2486 wm8994->fll_suspend[i].in,
3636 wm8994->fll_suspend[i].out); 2487 wm8994->fll_suspend[i].out);
@@ -3639,6 +2490,19 @@ static int wm8994_resume(struct platform_device *pdev)
3639 i + 1, ret); 2490 i + 1, ret);
3640 } 2491 }
3641 2492
2493 switch (control->type) {
2494 case WM8994:
2495 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2496 snd_soc_update_bits(codec, WM8994_MICBIAS,
2497 WM8994_MICD_ENA, WM8994_MICD_ENA);
2498 break;
2499 case WM8958:
2500 if (wm8994->jack_cb)
2501 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2502 WM8958_MICD_ENA, WM8958_MICD_ENA);
2503 break;
2504 }
2505
3642 return 0; 2506 return 0;
3643} 2507}
3644#else 2508#else
@@ -3648,7 +2512,7 @@ static int wm8994_resume(struct platform_device *pdev)
3648 2512
3649static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 2513static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3650{ 2514{
3651 struct snd_soc_codec *codec = &wm8994->codec; 2515 struct snd_soc_codec *codec = wm8994->codec;
3652 struct wm8994_pdata *pdata = wm8994->pdata; 2516 struct wm8994_pdata *pdata = wm8994->pdata;
3653 struct snd_kcontrol_new controls[] = { 2517 struct snd_kcontrol_new controls[] = {
3654 SOC_ENUM_EXT("AIF1.1 EQ Mode", 2518 SOC_ENUM_EXT("AIF1.1 EQ Mode",
@@ -3706,16 +2570,16 @@ static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3706 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; 2570 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3707 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 2571 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3708 2572
3709 ret = snd_soc_add_controls(&wm8994->codec, controls, 2573 ret = snd_soc_add_controls(wm8994->codec, controls,
3710 ARRAY_SIZE(controls)); 2574 ARRAY_SIZE(controls));
3711 if (ret != 0) 2575 if (ret != 0)
3712 dev_err(wm8994->codec.dev, 2576 dev_err(wm8994->codec->dev,
3713 "Failed to add ReTune Mobile controls: %d\n", ret); 2577 "Failed to add ReTune Mobile controls: %d\n", ret);
3714} 2578}
3715 2579
3716static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 2580static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3717{ 2581{
3718 struct snd_soc_codec *codec = &wm8994->codec; 2582 struct snd_soc_codec *codec = wm8994->codec;
3719 struct wm8994_pdata *pdata = wm8994->pdata; 2583 struct wm8994_pdata *pdata = wm8994->pdata;
3720 int ret, i; 2584 int ret, i;
3721 2585
@@ -3747,7 +2611,7 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3747 wm8994->drc_texts = kmalloc(sizeof(char *) 2611 wm8994->drc_texts = kmalloc(sizeof(char *)
3748 * pdata->num_drc_cfgs, GFP_KERNEL); 2612 * pdata->num_drc_cfgs, GFP_KERNEL);
3749 if (!wm8994->drc_texts) { 2613 if (!wm8994->drc_texts) {
3750 dev_err(wm8994->codec.dev, 2614 dev_err(wm8994->codec->dev,
3751 "Failed to allocate %d DRC config texts\n", 2615 "Failed to allocate %d DRC config texts\n",
3752 pdata->num_drc_cfgs); 2616 pdata->num_drc_cfgs);
3753 return; 2617 return;
@@ -3759,10 +2623,10 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3759 wm8994->drc_enum.max = pdata->num_drc_cfgs; 2623 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3760 wm8994->drc_enum.texts = wm8994->drc_texts; 2624 wm8994->drc_enum.texts = wm8994->drc_texts;
3761 2625
3762 ret = snd_soc_add_controls(&wm8994->codec, controls, 2626 ret = snd_soc_add_controls(wm8994->codec, controls,
3763 ARRAY_SIZE(controls)); 2627 ARRAY_SIZE(controls));
3764 if (ret != 0) 2628 if (ret != 0)
3765 dev_err(wm8994->codec.dev, 2629 dev_err(wm8994->codec->dev,
3766 "Failed to add DRC mode controls: %d\n", ret); 2630 "Failed to add DRC mode controls: %d\n", ret);
3767 2631
3768 for (i = 0; i < WM8994_NUM_DRC; i++) 2632 for (i = 0; i < WM8994_NUM_DRC; i++)
@@ -3775,62 +2639,17 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3775 if (pdata->num_retune_mobile_cfgs) 2639 if (pdata->num_retune_mobile_cfgs)
3776 wm8994_handle_retune_mobile_pdata(wm8994); 2640 wm8994_handle_retune_mobile_pdata(wm8994);
3777 else 2641 else
3778 snd_soc_add_controls(&wm8994->codec, wm8994_eq_controls, 2642 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
3779 ARRAY_SIZE(wm8994_eq_controls)); 2643 ARRAY_SIZE(wm8994_eq_controls));
3780}
3781
3782static int wm8994_probe(struct platform_device *pdev)
3783{
3784 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3785 struct snd_soc_codec *codec;
3786 int ret = 0;
3787
3788 if (wm8994_codec == NULL) {
3789 dev_err(&pdev->dev, "Codec device not registered\n");
3790 return -ENODEV;
3791 }
3792 2644
3793 socdev->card->codec = wm8994_codec; 2645 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3794 codec = wm8994_codec; 2646 if (pdata->micbias[i]) {
3795 2647 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3796 /* register pcms */ 2648 pdata->micbias[i] & 0xffff);
3797 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 2649 }
3798 if (ret < 0) {
3799 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
3800 return ret;
3801 } 2650 }
3802
3803 wm8994_handle_pdata(snd_soc_codec_get_drvdata(codec));
3804
3805 wm_hubs_add_analogue_controls(codec);
3806 snd_soc_add_controls(codec, wm8994_snd_controls,
3807 ARRAY_SIZE(wm8994_snd_controls));
3808 snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets,
3809 ARRAY_SIZE(wm8994_dapm_widgets));
3810 wm_hubs_add_analogue_routes(codec, 0, 0);
3811 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
3812
3813 return 0;
3814}
3815
3816static int wm8994_remove(struct platform_device *pdev)
3817{
3818 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3819
3820 snd_soc_free_pcms(socdev);
3821 snd_soc_dapm_free(socdev);
3822
3823 return 0;
3824} 2651}
3825 2652
3826struct snd_soc_codec_device soc_codec_dev_wm8994 = {
3827 .probe = wm8994_probe,
3828 .remove = wm8994_remove,
3829 .suspend = wm8994_suspend,
3830 .resume = wm8994_resume,
3831};
3832EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
3833
3834/** 2653/**
3835 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 2654 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3836 * 2655 *
@@ -3842,7 +2661,7 @@ EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
3842 * 2661 *
3843 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 2662 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3844 * being used to bring out signals to the processor then only platform 2663 * being used to bring out signals to the processor then only platform
3845 * data configuration is needed for WM8903 and processor GPIOs should 2664 * data configuration is needed for WM8994 and processor GPIOs should
3846 * be configured using snd_soc_jack_add_gpios() instead. 2665 * be configured using snd_soc_jack_add_gpios() instead.
3847 * 2666 *
3848 * Configuration of detection levels is available via the micbias1_lvl 2667 * Configuration of detection levels is available via the micbias1_lvl
@@ -3853,8 +2672,12 @@ int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3853{ 2672{
3854 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2673 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3855 struct wm8994_micdet *micdet; 2674 struct wm8994_micdet *micdet;
2675 struct wm8994 *control = codec->control_data;
3856 int reg; 2676 int reg;
3857 2677
2678 if (control->type != WM8994)
2679 return -EINVAL;
2680
3858 switch (micbias) { 2681 switch (micbias) {
3859 case 1: 2682 case 1:
3860 micdet = &wm8994->micdet[0]; 2683 micdet = &wm8994->micdet[0];
@@ -3889,10 +2712,14 @@ EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3889static irqreturn_t wm8994_mic_irq(int irq, void *data) 2712static irqreturn_t wm8994_mic_irq(int irq, void *data)
3890{ 2713{
3891 struct wm8994_priv *priv = data; 2714 struct wm8994_priv *priv = data;
3892 struct snd_soc_codec *codec = &priv->codec; 2715 struct snd_soc_codec *codec = priv->codec;
3893 int reg; 2716 int reg;
3894 int report; 2717 int report;
3895 2718
2719#ifndef CONFIG_SND_SOC_WM8994_MODULE
2720 trace_snd_soc_jack_irq(dev_name(codec->dev));
2721#endif
2722
3896 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2723 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3897 if (reg < 0) { 2724 if (reg < 0) {
3898 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2725 dev_err(codec->dev, "Failed to read microphone status: %d\n",
@@ -3921,101 +2748,233 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
3921 return IRQ_HANDLED; 2748 return IRQ_HANDLED;
3922} 2749}
3923 2750
3924static int wm8994_codec_probe(struct platform_device *pdev) 2751/* Default microphone detection handler for WM8958 - the user can
2752 * override this if they wish.
2753 */
2754static void wm8958_default_micdet(u16 status, void *data)
3925{ 2755{
3926 int ret; 2756 struct snd_soc_codec *codec = data;
3927 struct wm8994_priv *wm8994; 2757 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3928 struct snd_soc_codec *codec; 2758 int report = 0;
3929 int i; 2759
2760 /* If nothing present then clear our statuses */
2761 if (!(status & WM8958_MICD_STS))
2762 goto done;
2763
2764 report = SND_JACK_MICROPHONE;
2765
2766 /* Everything else is buttons; just assign slots */
2767 if (status & 0x1c)
2768 report |= SND_JACK_BTN_0;
2769
2770done:
2771 snd_soc_jack_report(wm8994->micdet[0].jack, report,
2772 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2773}
2774
2775/**
2776 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2777 *
2778 * @codec: WM8958 codec
2779 * @jack: jack to report detection events on
2780 *
2781 * Enable microphone detection functionality for the WM8958. By
2782 * default simple detection which supports the detection of up to 6
2783 * buttons plus video and microphone functionality is supported.
2784 *
2785 * The WM8958 has an advanced jack detection facility which is able to
2786 * support complex accessory detection, especially when used in
2787 * conjunction with external circuitry. In order to provide maximum
2788 * flexiblity a callback is provided which allows a completely custom
2789 * detection algorithm.
2790 */
2791int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2792 wm8958_micdet_cb cb, void *cb_data)
2793{
2794 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2795 struct wm8994 *control = codec->control_data;
3930 2796
3931 if (wm8994_codec) { 2797 if (control->type != WM8958)
3932 dev_err(&pdev->dev, "Another WM8994 is registered\n");
3933 return -EINVAL; 2798 return -EINVAL;
2799
2800 if (jack) {
2801 if (!cb) {
2802 dev_dbg(codec->dev, "Using default micdet callback\n");
2803 cb = wm8958_default_micdet;
2804 cb_data = codec;
2805 }
2806
2807 wm8994->micdet[0].jack = jack;
2808 wm8994->jack_cb = cb;
2809 wm8994->jack_cb_data = cb_data;
2810
2811 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2812 WM8958_MICD_ENA, WM8958_MICD_ENA);
2813 } else {
2814 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2815 WM8958_MICD_ENA, 0);
3934 } 2816 }
3935 2817
3936 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); 2818 return 0;
3937 if (!wm8994) { 2819}
3938 dev_err(&pdev->dev, "Failed to allocate private data\n"); 2820EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3939 return -ENOMEM; 2821
2822static irqreturn_t wm8958_mic_irq(int irq, void *data)
2823{
2824 struct wm8994_priv *wm8994 = data;
2825 struct snd_soc_codec *codec = wm8994->codec;
2826 int reg;
2827
2828 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2829 if (reg < 0) {
2830 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2831 reg);
2832 return IRQ_NONE;
3940 } 2833 }
3941 2834
3942 codec = &wm8994->codec; 2835 if (!(reg & WM8958_MICD_VALID)) {
2836 dev_dbg(codec->dev, "Mic detect data not valid\n");
2837 goto out;
2838 }
2839
2840#ifndef CONFIG_SND_SOC_WM8994_MODULE
2841 trace_snd_soc_jack_irq(dev_name(codec->dev));
2842#endif
2843
2844 if (wm8994->jack_cb)
2845 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2846 else
2847 dev_warn(codec->dev, "Accessory detection with no callback\n");
2848
2849out:
2850 return IRQ_HANDLED;
2851}
2852
2853static int wm8994_codec_probe(struct snd_soc_codec *codec)
2854{
2855 struct wm8994 *control;
2856 struct wm8994_priv *wm8994;
2857 struct snd_soc_dapm_context *dapm = &codec->dapm;
2858 int ret, i;
3943 2859
3944 mutex_init(&codec->mutex); 2860 codec->control_data = dev_get_drvdata(codec->dev->parent);
3945 INIT_LIST_HEAD(&codec->dapm_widgets); 2861 control = codec->control_data;
3946 INIT_LIST_HEAD(&codec->dapm_paths);
3947 2862
2863 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2864 if (wm8994 == NULL)
2865 return -ENOMEM;
3948 snd_soc_codec_set_drvdata(codec, wm8994); 2866 snd_soc_codec_set_drvdata(codec, wm8994);
3949 codec->control_data = dev_get_drvdata(pdev->dev.parent);
3950 codec->name = "WM8994";
3951 codec->owner = THIS_MODULE;
3952 codec->read = wm8994_read;
3953 codec->write = wm8994_write;
3954 codec->readable_register = wm8994_readable;
3955 codec->bias_level = SND_SOC_BIAS_OFF;
3956 codec->set_bias_level = wm8994_set_bias_level;
3957 codec->dai = &wm8994_dai[0];
3958 codec->num_dai = 3;
3959 codec->reg_cache_size = WM8994_MAX_REGISTER;
3960 codec->reg_cache = &wm8994->reg_cache;
3961 codec->dev = &pdev->dev;
3962
3963 wm8994->pdata = pdev->dev.parent->platform_data;
3964
3965 /* Fill the cache with physical values we inherited; don't reset */
3966 ret = wm8994_bulk_read(codec->control_data, 0,
3967 ARRAY_SIZE(wm8994->reg_cache) - 1,
3968 codec->reg_cache);
3969 if (ret < 0) {
3970 dev_err(codec->dev, "Failed to fill register cache: %d\n",
3971 ret);
3972 goto err;
3973 }
3974 2867
3975 /* Clear the cached values for unreadable/volatile registers to 2868 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3976 * avoid potential confusion. 2869 wm8994->codec = codec;
3977 */ 2870
3978 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++) 2871 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3979 if (wm8994_volatile(i) || !wm8994_readable(i)) 2872 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3980 wm8994->reg_cache[i] = 0; 2873 else if (wm8994->pdata && wm8994->pdata->irq_base)
2874 wm8994->micdet_irq = wm8994->pdata->irq_base +
2875 WM8994_IRQ_MIC1_DET;
2876
2877 pm_runtime_enable(codec->dev);
2878 pm_runtime_resume(codec->dev);
2879
2880 /* Read our current status back from the chip - we don't want to
2881 * reset as this may interfere with the GPIO or LDO operation. */
2882 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2883 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2884 continue;
2885
2886 ret = wm8994_reg_read(codec->control_data, i);
2887 if (ret <= 0)
2888 continue;
2889
2890 ret = snd_soc_cache_write(codec, i, ret);
2891 if (ret != 0) {
2892 dev_err(codec->dev,
2893 "Failed to initialise cache for 0x%x: %d\n",
2894 i, ret);
2895 goto err;
2896 }
2897 }
3981 2898
3982 /* Set revision-specific configuration */ 2899 /* Set revision-specific configuration */
3983 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 2900 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3984 switch (wm8994->revision) { 2901 switch (control->type) {
3985 case 2: 2902 case WM8994:
3986 case 3: 2903 switch (wm8994->revision) {
3987 wm8994->hubs.dcs_codes = -5; 2904 case 2:
3988 wm8994->hubs.hp_startup_mode = 1; 2905 case 3:
2906 wm8994->hubs.dcs_codes = -5;
2907 wm8994->hubs.hp_startup_mode = 1;
2908 wm8994->hubs.dcs_readback_mode = 1;
2909 break;
2910 default:
2911 wm8994->hubs.dcs_readback_mode = 1;
2912 break;
2913 }
2914
2915 case WM8958:
3989 wm8994->hubs.dcs_readback_mode = 1; 2916 wm8994->hubs.dcs_readback_mode = 1;
3990 break; 2917 break;
2918
3991 default: 2919 default:
3992 wm8994->hubs.dcs_readback_mode = 1;
3993 break; 2920 break;
3994 } 2921 }
3995 2922
3996 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 2923 switch (control->type) {
3997 wm8994_mic_irq, "Mic 1 detect", wm8994); 2924 case WM8994:
3998 if (ret != 0) 2925 if (wm8994->micdet_irq) {
3999 dev_warn(&pdev->dev, 2926 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4000 "Failed to request Mic1 detect IRQ: %d\n", ret); 2927 wm8994_mic_irq,
4001 2928 IRQF_TRIGGER_RISING,
4002 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, 2929 "Mic1 detect",
4003 wm8994_mic_irq, "Mic 1 short", wm8994); 2930 wm8994);
4004 if (ret != 0) 2931 if (ret != 0)
4005 dev_warn(&pdev->dev, 2932 dev_warn(codec->dev,
4006 "Failed to request Mic1 short IRQ: %d\n", ret); 2933 "Failed to request Mic1 detect IRQ: %d\n",
2934 ret);
2935 }
4007 2936
4008 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET, 2937 ret = wm8994_request_irq(codec->control_data,
4009 wm8994_mic_irq, "Mic 2 detect", wm8994); 2938 WM8994_IRQ_MIC1_SHRT,
4010 if (ret != 0) 2939 wm8994_mic_irq, "Mic 1 short",
4011 dev_warn(&pdev->dev, 2940 wm8994);
4012 "Failed to request Mic2 detect IRQ: %d\n", ret); 2941 if (ret != 0)
2942 dev_warn(codec->dev,
2943 "Failed to request Mic1 short IRQ: %d\n",
2944 ret);
2945
2946 ret = wm8994_request_irq(codec->control_data,
2947 WM8994_IRQ_MIC2_DET,
2948 wm8994_mic_irq, "Mic 2 detect",
2949 wm8994);
2950 if (ret != 0)
2951 dev_warn(codec->dev,
2952 "Failed to request Mic2 detect IRQ: %d\n",
2953 ret);
2954
2955 ret = wm8994_request_irq(codec->control_data,
2956 WM8994_IRQ_MIC2_SHRT,
2957 wm8994_mic_irq, "Mic 2 short",
2958 wm8994);
2959 if (ret != 0)
2960 dev_warn(codec->dev,
2961 "Failed to request Mic2 short IRQ: %d\n",
2962 ret);
2963 break;
4013 2964
4014 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, 2965 case WM8958:
4015 wm8994_mic_irq, "Mic 2 short", wm8994); 2966 if (wm8994->micdet_irq) {
4016 if (ret != 0) 2967 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4017 dev_warn(&pdev->dev, 2968 wm8958_mic_irq,
4018 "Failed to request Mic2 short IRQ: %d\n", ret); 2969 IRQF_TRIGGER_RISING,
2970 "Mic detect",
2971 wm8994);
2972 if (ret != 0)
2973 dev_warn(codec->dev,
2974 "Failed to request Mic detect IRQ: %d\n",
2975 ret);
2976 }
2977 }
4019 2978
4020 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 2979 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4021 * configured on init - if a system wants to do this dynamically 2980 * configured on init - if a system wants to do this dynamically
@@ -4045,28 +3004,39 @@ static int wm8994_codec_probe(struct platform_device *pdev)
4045 wm8994->lrclk_shared[1] = 0; 3004 wm8994->lrclk_shared[1] = 0;
4046 } 3005 }
4047 3006
4048 for (i = 0; i < ARRAY_SIZE(wm8994_dai); i++)
4049 wm8994_dai[i].dev = codec->dev;
4050
4051 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 3007 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
4052 3008
4053 wm8994_codec = codec;
4054
4055 /* Latch volume updates (right only; we always do left then right). */ 3009 /* Latch volume updates (right only; we always do left then right). */
3010 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3011 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
4056 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME, 3012 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
4057 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); 3013 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3014 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3015 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
4058 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME, 3016 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
4059 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); 3017 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3018 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3019 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
4060 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME, 3020 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
4061 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); 3021 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3022 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3023 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
4062 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME, 3024 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
4063 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); 3025 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3026 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3027 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
4064 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME, 3028 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
4065 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); 3029 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3030 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3031 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
4066 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME, 3032 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
4067 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); 3033 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3034 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3035 WM8994_DAC1_VU, WM8994_DAC1_VU);
4068 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME, 3036 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
4069 WM8994_DAC1_VU, WM8994_DAC1_VU); 3037 WM8994_DAC1_VU, WM8994_DAC1_VU);
3038 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3039 WM8994_DAC2_VU, WM8994_DAC2_VU);
4070 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME, 3040 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
4071 WM8994_DAC2_VU, WM8994_DAC2_VU); 3041 WM8994_DAC2_VU, WM8994_DAC2_VU);
4072 3042
@@ -4088,59 +3058,181 @@ static int wm8994_codec_probe(struct platform_device *pdev)
4088 3058
4089 wm8994_update_class_w(codec); 3059 wm8994_update_class_w(codec);
4090 3060
4091 ret = snd_soc_register_codec(codec); 3061 wm8994_handle_pdata(wm8994);
4092 if (ret != 0) {
4093 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
4094 goto err_irq;
4095 }
4096 3062
4097 ret = snd_soc_register_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai)); 3063 wm_hubs_add_analogue_controls(codec);
4098 if (ret != 0) { 3064 snd_soc_add_controls(codec, wm8994_snd_controls,
4099 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); 3065 ARRAY_SIZE(wm8994_snd_controls));
4100 goto err_codec; 3066 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3067 ARRAY_SIZE(wm8994_dapm_widgets));
3068
3069 switch (control->type) {
3070 case WM8994:
3071 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3072 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3073 if (wm8994->revision < 4) {
3074 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3075 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3076 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3077 ARRAY_SIZE(wm8994_adc_revd_widgets));
3078 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3079 ARRAY_SIZE(wm8994_dac_revd_widgets));
3080 } else {
3081 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3082 ARRAY_SIZE(wm8994_lateclk_widgets));
3083 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3084 ARRAY_SIZE(wm8994_adc_widgets));
3085 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3086 ARRAY_SIZE(wm8994_dac_widgets));
3087 }
3088 break;
3089 case WM8958:
3090 snd_soc_add_controls(codec, wm8958_snd_controls,
3091 ARRAY_SIZE(wm8958_snd_controls));
3092 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3093 ARRAY_SIZE(wm8958_dapm_widgets));
3094 if (wm8994->revision < 1) {
3095 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3096 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3097 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3098 ARRAY_SIZE(wm8994_adc_revd_widgets));
3099 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3100 ARRAY_SIZE(wm8994_dac_revd_widgets));
3101 } else {
3102 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3103 ARRAY_SIZE(wm8994_lateclk_widgets));
3104 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3105 ARRAY_SIZE(wm8994_adc_widgets));
3106 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3107 ARRAY_SIZE(wm8994_dac_widgets));
3108 }
3109 break;
4101 } 3110 }
3111
4102 3112
4103 platform_set_drvdata(pdev, wm8994); 3113 wm_hubs_add_analogue_routes(codec, 0, 0);
3114 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3115
3116 switch (control->type) {
3117 case WM8994:
3118 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3119 ARRAY_SIZE(wm8994_intercon));
3120
3121 if (wm8994->revision < 4) {
3122 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3123 ARRAY_SIZE(wm8994_revd_intercon));
3124 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3125 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3126 } else {
3127 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3128 ARRAY_SIZE(wm8994_lateclk_intercon));
3129 }
3130 break;
3131 case WM8958:
3132 if (wm8994->revision < 1) {
3133 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3134 ARRAY_SIZE(wm8994_revd_intercon));
3135 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3136 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3137 } else {
3138 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3139 ARRAY_SIZE(wm8994_lateclk_intercon));
3140 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3141 ARRAY_SIZE(wm8958_intercon));
3142 }
3143
3144 wm8958_dsp2_init(codec);
3145 break;
3146 }
4104 3147
4105 return 0; 3148 return 0;
4106 3149
4107err_codec:
4108 snd_soc_unregister_codec(codec);
4109err_irq: 3150err_irq:
4110 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3151 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
4111 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3152 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
4112 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3153 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
4113 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 3154 if (wm8994->micdet_irq)
3155 free_irq(wm8994->micdet_irq, wm8994);
4114err: 3156err:
4115 kfree(wm8994); 3157 kfree(wm8994);
4116 return ret; 3158 return ret;
4117} 3159}
4118 3160
4119static int __devexit wm8994_codec_remove(struct platform_device *pdev) 3161static int wm8994_codec_remove(struct snd_soc_codec *codec)
4120{ 3162{
4121 struct wm8994_priv *wm8994 = platform_get_drvdata(pdev); 3163 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4122 struct snd_soc_codec *codec = &wm8994->codec; 3164 struct wm8994 *control = codec->control_data;
4123 3165
4124 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3166 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4125 snd_soc_unregister_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai)); 3167
4126 snd_soc_unregister_codec(&wm8994->codec); 3168 pm_runtime_disable(codec->dev);
4127 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3169
4128 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3170 switch (control->type) {
4129 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3171 case WM8994:
4130 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 3172 if (wm8994->micdet_irq)
3173 free_irq(wm8994->micdet_irq, wm8994);
3174 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3175 wm8994);
3176 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3177 wm8994);
3178 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3179 wm8994);
3180 break;
3181
3182 case WM8958:
3183 if (wm8994->micdet_irq)
3184 free_irq(wm8994->micdet_irq, wm8994);
3185 break;
3186 }
3187 if (wm8994->mbc)
3188 release_firmware(wm8994->mbc);
3189 if (wm8994->mbc_vss)
3190 release_firmware(wm8994->mbc_vss);
3191 if (wm8994->enh_eq)
3192 release_firmware(wm8994->enh_eq);
3193 kfree(wm8994->retune_mobile_texts);
3194 kfree(wm8994->drc_texts);
4131 kfree(wm8994); 3195 kfree(wm8994);
4132 wm8994_codec = NULL;
4133 3196
4134 return 0; 3197 return 0;
4135} 3198}
4136 3199
3200static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3201 .probe = wm8994_codec_probe,
3202 .remove = wm8994_codec_remove,
3203 .suspend = wm8994_suspend,
3204 .resume = wm8994_resume,
3205 .read = wm8994_read,
3206 .write = wm8994_write,
3207 .readable_register = wm8994_readable,
3208 .volatile_register = wm8994_volatile,
3209 .set_bias_level = wm8994_set_bias_level,
3210
3211 .reg_cache_size = WM8994_CACHE_SIZE,
3212 .reg_cache_default = wm8994_reg_defaults,
3213 .reg_word_size = 2,
3214 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3215};
3216
3217static int __devinit wm8994_probe(struct platform_device *pdev)
3218{
3219 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3220 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3221}
3222
3223static int __devexit wm8994_remove(struct platform_device *pdev)
3224{
3225 snd_soc_unregister_codec(&pdev->dev);
3226 return 0;
3227}
3228
4137static struct platform_driver wm8994_codec_driver = { 3229static struct platform_driver wm8994_codec_driver = {
4138 .driver = { 3230 .driver = {
4139 .name = "wm8994-codec", 3231 .name = "wm8994-codec",
4140 .owner = THIS_MODULE, 3232 .owner = THIS_MODULE,
4141 }, 3233 },
4142 .probe = wm8994_codec_probe, 3234 .probe = wm8994_probe,
4143 .remove = __devexit_p(wm8994_codec_remove), 3235 .remove = __devexit_p(wm8994_remove),
4144}; 3236};
4145 3237
4146static __init int wm8994_init(void) 3238static __init int wm8994_init(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-04 16:48:32 -0400