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authorDan Williams <dan.j.williams@intel.com>2007-02-13 11:13:34 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-17 10:05:40 -0500
commit3668b45d46f777b0773ef5ff49531c1144efb6dd (patch)
treed9bb1a1ce8d0cce8bff99578fc0ba4bf8cdedd75 /include
parent4434c5c7fd61c6713de882a2272b66f32fe7cac3 (diff)
[ARM] 4187/1: iop: unify time implementation across iop32x, iop33x, and iop13xx
* architecture specific details are handled in asm/arch/time.h * ARCH_IOP13XX now selects PLAT_IOP * as suggested by Lennert use ifdef CONFIG_XSCALE to skip the cp_wait on XSC3 Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h12
-rw-r--r--include/asm-arm/arch-iop13xx/time.h51
-rw-r--r--include/asm-arm/arch-iop32x/time.h4
-rw-r--r--include/asm-arm/arch-iop33x/time.h4
-rw-r--r--include/asm-arm/hardware/iop3xx.h55
5 files changed, 104 insertions, 22 deletions
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index e7430593d6fb..d26b755a9879 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -9,8 +9,6 @@ void iop13xx_init_irq(void);
9void iop13xx_map_io(void); 9void iop13xx_map_io(void);
10void iop13xx_platform_init(void); 10void iop13xx_platform_init(void);
11void iop13xx_init_irq(void); 11void iop13xx_init_irq(void);
12void iop13xx_init_time(unsigned long tickrate);
13unsigned long iop13xx_gettimeoffset(void);
14 12
15/* CPUID CP6 R0 Page 0 */ 13/* CPUID CP6 R0 Page 0 */
16static inline int iop13xx_cpu_id(void) 14static inline int iop13xx_cpu_id(void)
@@ -453,14 +451,4 @@ static inline int iop13xx_cpu_id(void)
453#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) 451#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
454#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) 452#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
455 453
456#define IOP13XX_TMR_TC 0x01
457#define IOP13XX_TMR_EN 0x02
458#define IOP13XX_TMR_RELOAD 0x04
459#define IOP13XX_TMR_PRIVILEGED 0x08
460
461#define IOP13XX_TMR_RATIO_1_1 0x00
462#define IOP13XX_TMR_RATIO_4_1 0x10
463#define IOP13XX_TMR_RATIO_8_1 0x20
464#define IOP13XX_TMR_RATIO_16_1 0x30
465
466#endif /* _IOP13XX_HW_H_ */ 454#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h
new file mode 100644
index 000000000000..77a837a02dec
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/time.h
@@ -0,0 +1,51 @@
1#ifndef _IOP13XX_TIME_H_
2#define _IOP13XX_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
4
5#define IOP_TMR_EN 0x02
6#define IOP_TMR_RELOAD 0x04
7#define IOP_TMR_PRIVILEGED 0x08
8#define IOP_TMR_RATIO_1_1 0x00
9
10void iop_init_time(unsigned long tickrate);
11unsigned long iop_gettimeoffset(void);
12
13static inline void write_tmr0(u32 val)
14{
15 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
16}
17
18static inline void write_tmr1(u32 val)
19{
20 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
21}
22
23static inline u32 read_tcr0(void)
24{
25 u32 val;
26 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
27 return val;
28}
29
30static inline u32 read_tcr1(void)
31{
32 u32 val;
33 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
34 return val;
35}
36
37static inline void write_trr0(u32 val)
38{
39 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
40}
41
42static inline void write_trr1(u32 val)
43{
44 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
45}
46
47static inline void write_tisr(u32 val)
48{
49 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
50}
51#endif
diff --git a/include/asm-arm/arch-iop32x/time.h b/include/asm-arm/arch-iop32x/time.h
new file mode 100644
index 000000000000..0f28c9949623
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/time.h
@@ -0,0 +1,4 @@
1#ifndef _IOP32X_TIME_H_
2#define _IOP32X_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0
4#endif
diff --git a/include/asm-arm/arch-iop33x/time.h b/include/asm-arm/arch-iop33x/time.h
new file mode 100644
index 000000000000..4ac4d7664f85
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/time.h
@@ -0,0 +1,4 @@
1#ifndef _IOP33X_TIME_H_
2#define _IOP33X_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0
4#endif
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index 47fcbf6f52d3..15141a9caca8 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -188,14 +188,10 @@ extern void gpio_line_set(int line, int value);
188#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) 188#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
189#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) 189#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
190#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) 190#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
191#define IOP3XX_TMR_TC 0x01 191#define IOP_TMR_EN 0x02
192#define IOP3XX_TMR_EN 0x02 192#define IOP_TMR_RELOAD 0x04
193#define IOP3XX_TMR_RELOAD 0x04 193#define IOP_TMR_PRIVILEGED 0x08
194#define IOP3XX_TMR_PRIVILEGED 0x09 194#define IOP_TMR_RATIO_1_1 0x00
195#define IOP3XX_TMR_RATIO_1_1 0x00
196#define IOP3XX_TMR_RATIO_4_1 0x10
197#define IOP3XX_TMR_RATIO_8_1 0x20
198#define IOP3XX_TMR_RATIO_16_1 0x30
199 195
200/* Application accelerator unit */ 196/* Application accelerator unit */
201#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) 197#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
@@ -276,9 +272,48 @@ extern void gpio_line_set(int line, int value);
276 272
277#ifndef __ASSEMBLY__ 273#ifndef __ASSEMBLY__
278void iop3xx_map_io(void); 274void iop3xx_map_io(void);
279void iop3xx_init_time(unsigned long);
280unsigned long iop3xx_gettimeoffset(void);
281void iop_init_cp6_handler(void); 275void iop_init_cp6_handler(void);
276void iop_init_time(unsigned long tickrate);
277unsigned long iop_gettimeoffset(void);
278
279static inline void write_tmr0(u32 val)
280{
281 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
282}
283
284static inline void write_tmr1(u32 val)
285{
286 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
287}
288
289static inline u32 read_tcr0(void)
290{
291 u32 val;
292 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
293 return val;
294}
295
296static inline u32 read_tcr1(void)
297{
298 u32 val;
299 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
300 return val;
301}
302
303static inline void write_trr0(u32 val)
304{
305 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
306}
307
308static inline void write_trr1(u32 val)
309{
310 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
311}
312
313static inline void write_tisr(u32 val)
314{
315 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
316}
282 317
283extern struct platform_device iop3xx_i2c0_device; 318extern struct platform_device iop3xx_i2c0_device;
284extern struct platform_device iop3xx_i2c1_device; 319extern struct platform_device iop3xx_i2c1_device;