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authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-06 15:08:39 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-06 15:08:39 -0400
commit1fe9eb184721132c7254d76d9ef31c96edad8870 (patch)
treec055ffb7f201bc2370714ebe186a922d0eb39d0d /include/linux/mfd
parent0bb464624140bfdd8389d4c5464ba134b2856049 (diff)
parent89abd4df28c6f85645e32f37ffab6426f800e4a1 (diff)
Merge tag 'mfd-for-linus-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into next
Pull MFD updates from Lee Jones: "Changes to existing drivers: - increase DT coverage: arizona, mc13xxx, stmpe-i2c, syscon, sun6i-prcm - regmap use of and/or clean-up: tps65090, twl6040 - basic renaming: max14577 - use new cpufreq helpers: db8500-prcmu - increase regulator support: stmpe, arizona, wm5102 - reduce legacy GPIO overhead: stmpe - provide necessary remove path: bcm590xx - expand sysfs presence: kempld - move driver specific code out to drivers: rtc-s5m, arizona - clk handling: twl6040 - use managed (devm_*) resources: ipaq-micro - clean-up/remove unused/duplicated code: tps65218, sec, pm8921, abx500-core, db8500-prcmu, menelaus - build/boot/sematic bug fixes: rtsx_usb, stmpe, bcm590xx, abx500, mc13xxx, rdc321x-southbridge, mfd-core, sec, max14577, syscon, cros_ec_spi - constify stuff: sm501, tps65910, tps6507x, tps6586x, max77686, max8997, kempld, max77693, max8907, rtsx_usb, db8500-prcmu, max8998, wm8400, sec, lp3943, max14577, as3711, omap-usb-host, ipaq-micro Support for new devices: - add support for max77836 into max14577 - add support for tps658640 into tps6586x - add support for cros-ec-i2c-tunnel into cros_ec - add new driver for rtsx_usb_sdmmc and rtsx_usb_ms - add new driver for axp20x - add new driver for sun6i-prcm - add new driver for ipaq-micro" * tag 'mfd-for-linus-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (77 commits) mfd: wm5102: Correct default for LDO Control 2 register mfd: menelaus: Use module_i2c_driver mfd: tps65218: Terminate of match table mfd: db8500-prcmu: Remove check for CONFIG_DBX500_PRCMU_DEBUG mfd: ti-keystone-devctrl: Add bindings for device state control mfd: palmas: Format the header file mfd: abx500-core: Remove unused function abx500_dump_all_banks() mfd: arizona: Correct addresses of always-on trigger registers mfd: max14577: Cast to architecture agnostic data type i2c: ChromeOS EC tunnel driver mfd: cros_ec: Sync to the latest cros_ec_commands.h from EC sources mfd: cros_ec: spi: Increase cros_ec_spi deadline from 5ms to 100ms mfd: cros_ec: spi: Make the cros_ec_spi timeout more reliable mfd: cros_ec: spi: Add mutex to cros_ec_spi mfd: cros_ec: spi: Calculate delay between transfers correctly mfd: arizona: Correct error message for addition of main IRQ chip mfd: wm8997: Add registers for high power mode mfd: arizona: Add MICVDD to mapped regulators mfd: ipaq-micro: Make mfd_cell array const mfd: ipaq-micro: Use devm_ioremap_resource() ...
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/abx500.h1
-rw-r--r--include/linux/mfd/arizona/registers.h14
-rw-r--r--include/linux/mfd/axp20x.h180
-rw-r--r--include/linux/mfd/cros_ec.h4
-rw-r--r--include/linux/mfd/cros_ec_commands.h1128
-rw-r--r--include/linux/mfd/ipaq-micro.h148
-rw-r--r--include/linux/mfd/kempld.h4
-rw-r--r--include/linux/mfd/mc13xxx.h22
-rw-r--r--include/linux/mfd/palmas.h2166
-rw-r--r--include/linux/mfd/pm8xxx/core.h81
-rw-r--r--include/linux/mfd/rdc321x.h2
-rw-r--r--include/linux/mfd/samsung/core.h35
-rw-r--r--include/linux/mfd/stmpe.h19
-rw-r--r--include/linux/mfd/syscon.h2
-rw-r--r--include/linux/mfd/tps65218.h1
-rw-r--r--include/linux/mfd/twl6040.h3
16 files changed, 2522 insertions, 1288 deletions
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 3301b2031c8d..552cc1d61cc7 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -330,7 +330,6 @@ int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
330int abx500_get_chip_id(struct device *dev); 330int abx500_get_chip_id(struct device *dev);
331int abx500_event_registers_startup_state_get(struct device *dev, u8 *event); 331int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
332int abx500_startup_irq_enabled(struct device *dev, unsigned int irq); 332int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
333void abx500_dump_all_banks(void);
334 333
335struct abx500_ops { 334struct abx500_ops {
336 int (*get_chip_id) (struct device *); 335 int (*get_chip_id) (struct device *);
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 7b35c21170d5..7204d8138b24 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -42,12 +42,14 @@
42#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62 42#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62
43#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63 43#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63
44#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64 44#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64
45#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68 45#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x66
46#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69 46#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x67
47#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A 47#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x68
48#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B 48#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x69
49#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C 49#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6A
50#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D 50#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6B
51#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_7 0x6C
52#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_8 0x6D
51#define ARIZONA_COMFORT_NOISE_GENERATOR 0x70 53#define ARIZONA_COMFORT_NOISE_GENERATOR 0x70
52#define ARIZONA_HAPTICS_CONTROL_1 0x90 54#define ARIZONA_HAPTICS_CONTROL_1 0x90
53#define ARIZONA_HAPTICS_CONTROL_2 0x91 55#define ARIZONA_HAPTICS_CONTROL_2 0x91
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
new file mode 100644
index 000000000000..d0e31a2287ac
--- /dev/null
+++ b/include/linux/mfd/axp20x.h
@@ -0,0 +1,180 @@
1/*
2 * Functions and registers to access AXP20X power management chip.
3 *
4 * Copyright (C) 2013, Carlo Caione <carlo@caione.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_MFD_AXP20X_H
12#define __LINUX_MFD_AXP20X_H
13
14enum {
15 AXP202_ID = 0,
16 AXP209_ID,
17};
18
19#define AXP20X_DATACACHE(m) (0x04 + (m))
20
21/* Power supply */
22#define AXP20X_PWR_INPUT_STATUS 0x00
23#define AXP20X_PWR_OP_MODE 0x01
24#define AXP20X_USB_OTG_STATUS 0x02
25#define AXP20X_PWR_OUT_CTRL 0x12
26#define AXP20X_DCDC2_V_OUT 0x23
27#define AXP20X_DCDC2_LDO3_V_SCAL 0x25
28#define AXP20X_DCDC3_V_OUT 0x27
29#define AXP20X_LDO24_V_OUT 0x28
30#define AXP20X_LDO3_V_OUT 0x29
31#define AXP20X_VBUS_IPSOUT_MGMT 0x30
32#define AXP20X_V_OFF 0x31
33#define AXP20X_OFF_CTRL 0x32
34#define AXP20X_CHRG_CTRL1 0x33
35#define AXP20X_CHRG_CTRL2 0x34
36#define AXP20X_CHRG_BAK_CTRL 0x35
37#define AXP20X_PEK_KEY 0x36
38#define AXP20X_DCDC_FREQ 0x37
39#define AXP20X_V_LTF_CHRG 0x38
40#define AXP20X_V_HTF_CHRG 0x39
41#define AXP20X_APS_WARN_L1 0x3a
42#define AXP20X_APS_WARN_L2 0x3b
43#define AXP20X_V_LTF_DISCHRG 0x3c
44#define AXP20X_V_HTF_DISCHRG 0x3d
45
46/* Interrupt */
47#define AXP20X_IRQ1_EN 0x40
48#define AXP20X_IRQ2_EN 0x41
49#define AXP20X_IRQ3_EN 0x42
50#define AXP20X_IRQ4_EN 0x43
51#define AXP20X_IRQ5_EN 0x44
52#define AXP20X_IRQ1_STATE 0x48
53#define AXP20X_IRQ2_STATE 0x49
54#define AXP20X_IRQ3_STATE 0x4a
55#define AXP20X_IRQ4_STATE 0x4b
56#define AXP20X_IRQ5_STATE 0x4c
57
58/* ADC */
59#define AXP20X_ACIN_V_ADC_H 0x56
60#define AXP20X_ACIN_V_ADC_L 0x57
61#define AXP20X_ACIN_I_ADC_H 0x58
62#define AXP20X_ACIN_I_ADC_L 0x59
63#define AXP20X_VBUS_V_ADC_H 0x5a
64#define AXP20X_VBUS_V_ADC_L 0x5b
65#define AXP20X_VBUS_I_ADC_H 0x5c
66#define AXP20X_VBUS_I_ADC_L 0x5d
67#define AXP20X_TEMP_ADC_H 0x5e
68#define AXP20X_TEMP_ADC_L 0x5f
69#define AXP20X_TS_IN_H 0x62
70#define AXP20X_TS_IN_L 0x63
71#define AXP20X_GPIO0_V_ADC_H 0x64
72#define AXP20X_GPIO0_V_ADC_L 0x65
73#define AXP20X_GPIO1_V_ADC_H 0x66
74#define AXP20X_GPIO1_V_ADC_L 0x67
75#define AXP20X_PWR_BATT_H 0x70
76#define AXP20X_PWR_BATT_M 0x71
77#define AXP20X_PWR_BATT_L 0x72
78#define AXP20X_BATT_V_H 0x78
79#define AXP20X_BATT_V_L 0x79
80#define AXP20X_BATT_CHRG_I_H 0x7a
81#define AXP20X_BATT_CHRG_I_L 0x7b
82#define AXP20X_BATT_DISCHRG_I_H 0x7c
83#define AXP20X_BATT_DISCHRG_I_L 0x7d
84#define AXP20X_IPSOUT_V_HIGH_H 0x7e
85#define AXP20X_IPSOUT_V_HIGH_L 0x7f
86
87/* Power supply */
88#define AXP20X_DCDC_MODE 0x80
89#define AXP20X_ADC_EN1 0x82
90#define AXP20X_ADC_EN2 0x83
91#define AXP20X_ADC_RATE 0x84
92#define AXP20X_GPIO10_IN_RANGE 0x85
93#define AXP20X_GPIO1_ADC_IRQ_RIS 0x86
94#define AXP20X_GPIO1_ADC_IRQ_FAL 0x87
95#define AXP20X_TIMER_CTRL 0x8a
96#define AXP20X_VBUS_MON 0x8b
97#define AXP20X_OVER_TMP 0x8f
98
99/* GPIO */
100#define AXP20X_GPIO0_CTRL 0x90
101#define AXP20X_LDO5_V_OUT 0x91
102#define AXP20X_GPIO1_CTRL 0x92
103#define AXP20X_GPIO2_CTRL 0x93
104#define AXP20X_GPIO20_SS 0x94
105#define AXP20X_GPIO3_CTRL 0x95
106
107/* Battery */
108#define AXP20X_CHRG_CC_31_24 0xb0
109#define AXP20X_CHRG_CC_23_16 0xb1
110#define AXP20X_CHRG_CC_15_8 0xb2
111#define AXP20X_CHRG_CC_7_0 0xb3
112#define AXP20X_DISCHRG_CC_31_24 0xb4
113#define AXP20X_DISCHRG_CC_23_16 0xb5
114#define AXP20X_DISCHRG_CC_15_8 0xb6
115#define AXP20X_DISCHRG_CC_7_0 0xb7
116#define AXP20X_CC_CTRL 0xb8
117#define AXP20X_FG_RES 0xb9
118
119/* Regulators IDs */
120enum {
121 AXP20X_LDO1 = 0,
122 AXP20X_LDO2,
123 AXP20X_LDO3,
124 AXP20X_LDO4,
125 AXP20X_LDO5,
126 AXP20X_DCDC2,
127 AXP20X_DCDC3,
128 AXP20X_REG_ID_MAX,
129};
130
131/* IRQs */
132enum {
133 AXP20X_IRQ_ACIN_OVER_V = 1,
134 AXP20X_IRQ_ACIN_PLUGIN,
135 AXP20X_IRQ_ACIN_REMOVAL,
136 AXP20X_IRQ_VBUS_OVER_V,
137 AXP20X_IRQ_VBUS_PLUGIN,
138 AXP20X_IRQ_VBUS_REMOVAL,
139 AXP20X_IRQ_VBUS_V_LOW,
140 AXP20X_IRQ_BATT_PLUGIN,
141 AXP20X_IRQ_BATT_REMOVAL,
142 AXP20X_IRQ_BATT_ENT_ACT_MODE,
143 AXP20X_IRQ_BATT_EXIT_ACT_MODE,
144 AXP20X_IRQ_CHARG,
145 AXP20X_IRQ_CHARG_DONE,
146 AXP20X_IRQ_BATT_TEMP_HIGH,
147 AXP20X_IRQ_BATT_TEMP_LOW,
148 AXP20X_IRQ_DIE_TEMP_HIGH,
149 AXP20X_IRQ_CHARG_I_LOW,
150 AXP20X_IRQ_DCDC1_V_LONG,
151 AXP20X_IRQ_DCDC2_V_LONG,
152 AXP20X_IRQ_DCDC3_V_LONG,
153 AXP20X_IRQ_PEK_SHORT = 22,
154 AXP20X_IRQ_PEK_LONG,
155 AXP20X_IRQ_N_OE_PWR_ON,
156 AXP20X_IRQ_N_OE_PWR_OFF,
157 AXP20X_IRQ_VBUS_VALID,
158 AXP20X_IRQ_VBUS_NOT_VALID,
159 AXP20X_IRQ_VBUS_SESS_VALID,
160 AXP20X_IRQ_VBUS_SESS_END,
161 AXP20X_IRQ_LOW_PWR_LVL1,
162 AXP20X_IRQ_LOW_PWR_LVL2,
163 AXP20X_IRQ_TIMER,
164 AXP20X_IRQ_PEK_RIS_EDGE,
165 AXP20X_IRQ_PEK_FAL_EDGE,
166 AXP20X_IRQ_GPIO3_INPUT,
167 AXP20X_IRQ_GPIO2_INPUT,
168 AXP20X_IRQ_GPIO1_INPUT,
169 AXP20X_IRQ_GPIO0_INPUT,
170};
171
172struct axp20x_dev {
173 struct device *dev;
174 struct i2c_client *i2c_client;
175 struct regmap *regmap;
176 struct regmap_irq_chip_data *regmap_irqc;
177 long variant;
178};
179
180#endif /* __LINUX_MFD_AXP20X_H */
diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h
index 032af7fc5b2e..887ef4f7bef7 100644
--- a/include/linux/mfd/cros_ec.h
+++ b/include/linux/mfd/cros_ec.h
@@ -29,8 +29,8 @@ enum {
29 EC_MSG_RX_PROTO_BYTES = 3, 29 EC_MSG_RX_PROTO_BYTES = 3,
30 30
31 /* Max length of messages */ 31 /* Max length of messages */
32 EC_MSG_BYTES = EC_HOST_PARAM_SIZE + EC_MSG_TX_PROTO_BYTES, 32 EC_MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE +
33 33 EC_MSG_TX_PROTO_BYTES,
34}; 34};
35 35
36/** 36/**
diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h
index 86fd06953bcd..7853a6410d14 100644
--- a/include/linux/mfd/cros_ec_commands.h
+++ b/include/linux/mfd/cros_ec_commands.h
@@ -24,25 +24,12 @@
24#define __CROS_EC_COMMANDS_H 24#define __CROS_EC_COMMANDS_H
25 25
26/* 26/*
27 * Protocol overview 27 * Current version of this protocol
28 * 28 *
29 * request: CMD [ P0 P1 P2 ... Pn S ] 29 * TODO(crosbug.com/p/11223): This is effectively useless; protocol is
30 * response: ERR [ P0 P1 P2 ... Pn S ] 30 * determined in other ways. Remove this once the kernel code no longer
31 * 31 * depends on it.
32 * where the bytes are defined as follow :
33 * - CMD is the command code. (defined by EC_CMD_ constants)
34 * - ERR is the error code. (defined by EC_RES_ constants)
35 * - Px is the optional payload.
36 * it is not sent if the error code is not success.
37 * (defined by ec_params_ and ec_response_ structures)
38 * - S is the checksum which is the sum of all payload bytes.
39 *
40 * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD
41 * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM.
42 * On I2C, all bytes are sent serially in the same message.
43 */ 32 */
44
45/* Current version of this protocol */
46#define EC_PROTO_VERSION 0x00000002 33#define EC_PROTO_VERSION 0x00000002
47 34
48/* Command version mask */ 35/* Command version mask */
@@ -57,13 +44,19 @@
57#define EC_LPC_ADDR_HOST_CMD 0x204 44#define EC_LPC_ADDR_HOST_CMD 0x204
58 45
59/* I/O addresses for host command args and params */ 46/* I/O addresses for host command args and params */
60#define EC_LPC_ADDR_HOST_ARGS 0x800 47/* Protocol version 2 */
61#define EC_LPC_ADDR_HOST_PARAM 0x804 48#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */
62#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */ 49#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is
63 50 * EC_PROTO2_MAX_PARAM_SIZE */
64/* I/O addresses for host command params, old interface */ 51/* Protocol version 3 */
65#define EC_LPC_ADDR_OLD_PARAM 0x880 52#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
66#define EC_OLD_PARAM_SIZE 0x080 /* Size of param area in bytes */ 53#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
54
55/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
56 * and they tell the kernel that so we have to think of it as two parts. */
57#define EC_HOST_CMD_REGION0 0x800
58#define EC_HOST_CMD_REGION1 0x880
59#define EC_HOST_CMD_REGION_SIZE 0x80
67 60
68/* EC command register bit functions */ 61/* EC command register bit functions */
69#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ 62#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */
@@ -79,18 +72,22 @@
79#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ 72#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
80 73
81/* The offset address of each type of data in mapped memory. */ 74/* The offset address of each type of data in mapped memory. */
82#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors */ 75#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
83#define EC_MEMMAP_FAN 0x10 /* Fan speeds */ 76#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
84#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* Temp sensors (second set) */ 77#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */
85#define EC_MEMMAP_ID 0x20 /* 'E' 'C' */ 78#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */
86#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ 79#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
87#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ 80#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
88#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ 81#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
89#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ 82#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
90#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ 83#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */
91#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host command interface flags */ 84#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */
92#define EC_MEMMAP_SWITCHES 0x30 85/* Unused 0x28 - 0x2f */
93#define EC_MEMMAP_HOST_EVENTS 0x34 86#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */
87/* Unused 0x31 - 0x33 */
88#define EC_MEMMAP_HOST_EVENTS 0x34 /* 32 bits */
89/* Reserve 0x38 - 0x3f for additional host event-related stuff */
90/* Battery values are all 32 bits */
94#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ 91#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */
95#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ 92#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */
96#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ 93#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */
@@ -99,10 +96,24 @@
99#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ 96#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */
100#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ 97#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */
101#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ 98#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */
99/* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */
102#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ 100#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */
103#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ 101#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */
104#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ 102#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */
105#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ 103#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
104#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */
105/* Unused 0x84 - 0x8f */
106#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/
107/* Unused 0x91 */
108#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometer data 0x92 - 0x9f */
109#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */
110/* Unused 0xa6 - 0xfe (remember, 0xff is NOT part of the memmap region) */
111
112
113/* Define the format of the accelerometer mapped memory status byte. */
114#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
115#define EC_MEMMAP_ACC_STATUS_BUSY_BIT (1 << 4)
116#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT (1 << 7)
106 117
107/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ 118/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
108#define EC_TEMP_SENSOR_ENTRIES 16 119#define EC_TEMP_SENSOR_ENTRIES 16
@@ -112,6 +123,8 @@
112 * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. 123 * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
113 */ 124 */
114#define EC_TEMP_SENSOR_B_ENTRIES 8 125#define EC_TEMP_SENSOR_B_ENTRIES 8
126
127/* Special values for mapped temperature sensors */
115#define EC_TEMP_SENSOR_NOT_PRESENT 0xff 128#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
116#define EC_TEMP_SENSOR_ERROR 0xfe 129#define EC_TEMP_SENSOR_ERROR 0xfe
117#define EC_TEMP_SENSOR_NOT_POWERED 0xfd 130#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
@@ -122,6 +135,18 @@
122 */ 135 */
123#define EC_TEMP_SENSOR_OFFSET 200 136#define EC_TEMP_SENSOR_OFFSET 200
124 137
138/*
139 * Number of ALS readings at EC_MEMMAP_ALS
140 */
141#define EC_ALS_ENTRIES 2
142
143/*
144 * The default value a temperature sensor will return when it is present but
145 * has not been read this boot. This is a reasonable number to avoid
146 * triggering alarms on the host.
147 */
148#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
149
125#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ 150#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */
126#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ 151#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */
127#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ 152#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */
@@ -137,8 +162,8 @@
137#define EC_SWITCH_LID_OPEN 0x01 162#define EC_SWITCH_LID_OPEN 0x01
138#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 163#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
139#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 164#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
140/* Recovery requested via keyboard */ 165/* Was recovery requested via keyboard; now unused. */
141#define EC_SWITCH_KEYBOARD_RECOVERY 0x08 166#define EC_SWITCH_IGNORE1 0x08
142/* Recovery requested via dedicated signal (from servo board) */ 167/* Recovery requested via dedicated signal (from servo board) */
143#define EC_SWITCH_DEDICATED_RECOVERY 0x10 168#define EC_SWITCH_DEDICATED_RECOVERY 0x10
144/* Was fake developer mode switch; now unused. Remove in next refactor. */ 169/* Was fake developer mode switch; now unused. Remove in next refactor. */
@@ -147,10 +172,15 @@
147/* Host command interface flags */ 172/* Host command interface flags */
148/* Host command interface supports LPC args (LPC interface only) */ 173/* Host command interface supports LPC args (LPC interface only) */
149#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 174#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
175/* Host command interface supports version 3 protocol */
176#define EC_HOST_CMD_FLAG_VERSION_3 0x02
150 177
151/* Wireless switch flags */ 178/* Wireless switch flags */
152#define EC_WIRELESS_SWITCH_WLAN 0x01 179#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */
153#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 180#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */
181#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */
182#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */
183#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */
154 184
155/* 185/*
156 * This header file is used in coreboot both in C and ACPI code. The ACPI code 186 * This header file is used in coreboot both in C and ACPI code. The ACPI code
@@ -159,6 +189,14 @@
159 */ 189 */
160#ifndef __ACPI__ 190#ifndef __ACPI__
161 191
192/*
193 * Define __packed if someone hasn't beat us to it. Linux kernel style
194 * checking prefers __packed over __attribute__((packed)).
195 */
196#ifndef __packed
197#define __packed __attribute__((packed))
198#endif
199
162/* LPC command status byte masks */ 200/* LPC command status byte masks */
163/* EC has written a byte in the data register and host hasn't read it yet */ 201/* EC has written a byte in the data register and host hasn't read it yet */
164#define EC_LPC_STATUS_TO_HOST 0x01 202#define EC_LPC_STATUS_TO_HOST 0x01
@@ -198,6 +236,9 @@ enum ec_status {
198 EC_RES_UNAVAILABLE = 9, /* No response available */ 236 EC_RES_UNAVAILABLE = 9, /* No response available */
199 EC_RES_TIMEOUT = 10, /* We got a timeout */ 237 EC_RES_TIMEOUT = 10, /* We got a timeout */
200 EC_RES_OVERFLOW = 11, /* Table / data overflow */ 238 EC_RES_OVERFLOW = 11, /* Table / data overflow */
239 EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */
240 EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */
241 EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */
201}; 242};
202 243
203/* 244/*
@@ -235,6 +276,16 @@ enum host_event_code {
235 /* Shutdown due to battery level too low */ 276 /* Shutdown due to battery level too low */
236 EC_HOST_EVENT_BATTERY_SHUTDOWN = 17, 277 EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
237 278
279 /* Suggest that the AP throttle itself */
280 EC_HOST_EVENT_THROTTLE_START = 18,
281 /* Suggest that the AP resume normal speed */
282 EC_HOST_EVENT_THROTTLE_STOP = 19,
283
284 /* Hang detect logic detected a hang and host event timeout expired */
285 EC_HOST_EVENT_HANG_DETECT = 20,
286 /* Hang detect logic detected a hang and warm rebooted the AP */
287 EC_HOST_EVENT_HANG_REBOOT = 21,
288
238 /* 289 /*
239 * The high bit of the event mask is not used as a host event code. If 290 * The high bit of the event mask is not used as a host event code. If
240 * it reads back as set, then the entire event mask should be 291 * it reads back as set, then the entire event mask should be
@@ -279,6 +330,188 @@ struct ec_lpc_host_args {
279 */ 330 */
280#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 331#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
281 332
333/*****************************************************************************/
334/*
335 * Byte codes returned by EC over SPI interface.
336 *
337 * These can be used by the AP to debug the EC interface, and to determine
338 * when the EC is not in a state where it will ever get around to responding
339 * to the AP.
340 *
341 * Example of sequence of bytes read from EC for a current good transfer:
342 * 1. - - AP asserts chip select (CS#)
343 * 2. EC_SPI_OLD_READY - AP sends first byte(s) of request
344 * 3. - - EC starts handling CS# interrupt
345 * 4. EC_SPI_RECEIVING - AP sends remaining byte(s) of request
346 * 5. EC_SPI_PROCESSING - EC starts processing request; AP is clocking in
347 * bytes looking for EC_SPI_FRAME_START
348 * 6. - - EC finishes processing and sets up response
349 * 7. EC_SPI_FRAME_START - AP reads frame byte
350 * 8. (response packet) - AP reads response packet
351 * 9. EC_SPI_PAST_END - Any additional bytes read by AP
352 * 10 - - AP deasserts chip select
353 * 11 - - EC processes CS# interrupt and sets up DMA for
354 * next request
355 *
356 * If the AP is waiting for EC_SPI_FRAME_START and sees any value other than
357 * the following byte values:
358 * EC_SPI_OLD_READY
359 * EC_SPI_RX_READY
360 * EC_SPI_RECEIVING
361 * EC_SPI_PROCESSING
362 *
363 * Then the EC found an error in the request, or was not ready for the request
364 * and lost data. The AP should give up waiting for EC_SPI_FRAME_START,
365 * because the EC is unable to tell when the AP is done sending its request.
366 */
367
368/*
369 * Framing byte which precedes a response packet from the EC. After sending a
370 * request, the AP will clock in bytes until it sees the framing byte, then
371 * clock in the response packet.
372 */
373#define EC_SPI_FRAME_START 0xec
374
375/*
376 * Padding bytes which are clocked out after the end of a response packet.
377 */
378#define EC_SPI_PAST_END 0xed
379
380/*
381 * EC is ready to receive, and has ignored the byte sent by the AP. EC expects
382 * that the AP will send a valid packet header (starting with
383 * EC_COMMAND_PROTOCOL_3) in the next 32 bytes.
384 */
385#define EC_SPI_RX_READY 0xf8
386
387/*
388 * EC has started receiving the request from the AP, but hasn't started
389 * processing it yet.
390 */
391#define EC_SPI_RECEIVING 0xf9
392
393/* EC has received the entire request from the AP and is processing it. */
394#define EC_SPI_PROCESSING 0xfa
395
396/*
397 * EC received bad data from the AP, such as a packet header with an invalid
398 * length. EC will ignore all data until chip select deasserts.
399 */
400#define EC_SPI_RX_BAD_DATA 0xfb
401
402/*
403 * EC received data from the AP before it was ready. That is, the AP asserted
404 * chip select and started clocking data before the EC was ready to receive it.
405 * EC will ignore all data until chip select deasserts.
406 */
407#define EC_SPI_NOT_READY 0xfc
408
409/*
410 * EC was ready to receive a request from the AP. EC has treated the byte sent
411 * by the AP as part of a request packet, or (for old-style ECs) is processing
412 * a fully received packet but is not ready to respond yet.
413 */
414#define EC_SPI_OLD_READY 0xfd
415
416/*****************************************************************************/
417
418/*
419 * Protocol version 2 for I2C and SPI send a request this way:
420 *
421 * 0 EC_CMD_VERSION0 + (command version)
422 * 1 Command number
423 * 2 Length of params = N
424 * 3..N+2 Params, if any
425 * N+3 8-bit checksum of bytes 0..N+2
426 *
427 * The corresponding response is:
428 *
429 * 0 Result code (EC_RES_*)
430 * 1 Length of params = M
431 * 2..M+1 Params, if any
432 * M+2 8-bit checksum of bytes 0..M+1
433 */
434#define EC_PROTO2_REQUEST_HEADER_BYTES 3
435#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
436#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \
437 EC_PROTO2_REQUEST_TRAILER_BYTES)
438
439#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
440#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
441#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \
442 EC_PROTO2_RESPONSE_TRAILER_BYTES)
443
444/* Parameter length was limited by the LPC interface */
445#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
446
447/* Maximum request and response packet sizes for protocol version 2 */
448#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \
449 EC_PROTO2_MAX_PARAM_SIZE)
450#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \
451 EC_PROTO2_MAX_PARAM_SIZE)
452
453/*****************************************************************************/
454
455/*
456 * Value written to legacy command port / prefix byte to indicate protocol
457 * 3+ structs are being used. Usage is bus-dependent.
458 */
459#define EC_COMMAND_PROTOCOL_3 0xda
460
461#define EC_HOST_REQUEST_VERSION 3
462
463/* Version 3 request from host */
464struct ec_host_request {
465 /* Struct version (=3)
466 *
467 * EC will return EC_RES_INVALID_HEADER if it receives a header with a
468 * version it doesn't know how to parse.
469 */
470 uint8_t struct_version;
471
472 /*
473 * Checksum of request and data; sum of all bytes including checksum
474 * should total to 0.
475 */
476 uint8_t checksum;
477
478 /* Command code */
479 uint16_t command;
480
481 /* Command version */
482 uint8_t command_version;
483
484 /* Unused byte in current protocol version; set to 0 */
485 uint8_t reserved;
486
487 /* Length of data which follows this header */
488 uint16_t data_len;
489} __packed;
490
491#define EC_HOST_RESPONSE_VERSION 3
492
493/* Version 3 response from EC */
494struct ec_host_response {
495 /* Struct version (=3) */
496 uint8_t struct_version;
497
498 /*
499 * Checksum of response and data; sum of all bytes including checksum
500 * should total to 0.
501 */
502 uint8_t checksum;
503
504 /* Result code (EC_RES_*) */
505 uint16_t result;
506
507 /* Length of data which follows this header */
508 uint16_t data_len;
509
510 /* Unused bytes in current protocol version; set to 0 */
511 uint16_t reserved;
512} __packed;
513
514/*****************************************************************************/
282/* 515/*
283 * Notes on commands: 516 * Notes on commands:
284 * 517 *
@@ -418,6 +651,68 @@ struct ec_response_get_comms_status {
418 uint32_t flags; /* Mask of enum ec_comms_status */ 651 uint32_t flags; /* Mask of enum ec_comms_status */
419} __packed; 652} __packed;
420 653
654/* Fake a variety of responses, purely for testing purposes. */
655#define EC_CMD_TEST_PROTOCOL 0x0a
656
657/* Tell the EC what to send back to us. */
658struct ec_params_test_protocol {
659 uint32_t ec_result;
660 uint32_t ret_len;
661 uint8_t buf[32];
662} __packed;
663
664/* Here it comes... */
665struct ec_response_test_protocol {
666 uint8_t buf[32];
667} __packed;
668
669/* Get prococol information */
670#define EC_CMD_GET_PROTOCOL_INFO 0x0b
671
672/* Flags for ec_response_get_protocol_info.flags */
673/* EC_RES_IN_PROGRESS may be returned if a command is slow */
674#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0)
675
676struct ec_response_get_protocol_info {
677 /* Fields which exist if at least protocol version 3 supported */
678
679 /* Bitmask of protocol versions supported (1 << n means version n)*/
680 uint32_t protocol_versions;
681
682 /* Maximum request packet size, in bytes */
683 uint16_t max_request_packet_size;
684
685 /* Maximum response packet size, in bytes */
686 uint16_t max_response_packet_size;
687
688 /* Flags; see EC_PROTOCOL_INFO_* */
689 uint32_t flags;
690} __packed;
691
692
693/*****************************************************************************/
694/* Get/Set miscellaneous values */
695
696/* The upper byte of .flags tells what to do (nothing means "get") */
697#define EC_GSV_SET 0x80000000
698
699/* The lower three bytes of .flags identifies the parameter, if that has
700 meaning for an individual command. */
701#define EC_GSV_PARAM_MASK 0x00ffffff
702
703struct ec_params_get_set_value {
704 uint32_t flags;
705 uint32_t value;
706} __packed;
707
708struct ec_response_get_set_value {
709 uint32_t flags;
710 uint32_t value;
711} __packed;
712
713/* More than one command can use these structs to get/set paramters. */
714#define EC_CMD_GSV_PAUSE_IN_S5 0x0c
715
421 716
422/*****************************************************************************/ 717/*****************************************************************************/
423/* Flash commands */ 718/* Flash commands */
@@ -425,6 +720,7 @@ struct ec_response_get_comms_status {
425/* Get flash info */ 720/* Get flash info */
426#define EC_CMD_FLASH_INFO 0x10 721#define EC_CMD_FLASH_INFO 0x10
427 722
723/* Version 0 returns these fields */
428struct ec_response_flash_info { 724struct ec_response_flash_info {
429 /* Usable flash size, in bytes */ 725 /* Usable flash size, in bytes */
430 uint32_t flash_size; 726 uint32_t flash_size;
@@ -445,6 +741,37 @@ struct ec_response_flash_info {
445 uint32_t protect_block_size; 741 uint32_t protect_block_size;
446} __packed; 742} __packed;
447 743
744/* Flags for version 1+ flash info command */
745/* EC flash erases bits to 0 instead of 1 */
746#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0)
747
748/*
749 * Version 1 returns the same initial fields as version 0, with additional
750 * fields following.
751 *
752 * gcc anonymous structs don't seem to get along with the __packed directive;
753 * if they did we'd define the version 0 struct as a sub-struct of this one.
754 */
755struct ec_response_flash_info_1 {
756 /* Version 0 fields; see above for description */
757 uint32_t flash_size;
758 uint32_t write_block_size;
759 uint32_t erase_block_size;
760 uint32_t protect_block_size;
761
762 /* Version 1 adds these fields: */
763 /*
764 * Ideal write size in bytes. Writes will be fastest if size is
765 * exactly this and offset is a multiple of this. For example, an EC
766 * may have a write buffer which can do half-page operations if data is
767 * aligned, and a slower word-at-a-time write mode.
768 */
769 uint32_t write_ideal_size;
770
771 /* Flags; see EC_FLASH_INFO_* */
772 uint32_t flags;
773} __packed;
774
448/* 775/*
449 * Read flash 776 * Read flash
450 * 777 *
@@ -459,15 +786,15 @@ struct ec_params_flash_read {
459 786
460/* Write flash */ 787/* Write flash */
461#define EC_CMD_FLASH_WRITE 0x12 788#define EC_CMD_FLASH_WRITE 0x12
789#define EC_VER_FLASH_WRITE 1
790
791/* Version 0 of the flash command supported only 64 bytes of data */
792#define EC_FLASH_WRITE_VER0_SIZE 64
462 793
463struct ec_params_flash_write { 794struct ec_params_flash_write {
464 uint32_t offset; /* Byte offset to write */ 795 uint32_t offset; /* Byte offset to write */
465 uint32_t size; /* Size to write in bytes */ 796 uint32_t size; /* Size to write in bytes */
466 /* 797 /* Followed by data to write */
467 * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to
468 * use a power of 2 so writes stay aligned.
469 */
470 uint8_t data[64];
471} __packed; 798} __packed;
472 799
473/* Erase flash */ 800/* Erase flash */
@@ -543,7 +870,7 @@ struct ec_response_flash_protect {
543 870
544enum ec_flash_region { 871enum ec_flash_region {
545 /* Region which holds read-only EC image */ 872 /* Region which holds read-only EC image */
546 EC_FLASH_REGION_RO, 873 EC_FLASH_REGION_RO = 0,
547 /* Region which holds rewritable EC image */ 874 /* Region which holds rewritable EC image */
548 EC_FLASH_REGION_RW, 875 EC_FLASH_REGION_RW,
549 /* 876 /*
@@ -551,6 +878,8 @@ enum ec_flash_region {
551 * EC_FLASH_REGION_RO) 878 * EC_FLASH_REGION_RO)
552 */ 879 */
553 EC_FLASH_REGION_WP_RO, 880 EC_FLASH_REGION_WP_RO,
881 /* Number of regions */
882 EC_FLASH_REGION_COUNT,
554}; 883};
555 884
556struct ec_params_flash_region_info { 885struct ec_params_flash_region_info {
@@ -639,15 +968,15 @@ struct rgb_s {
639 */ 968 */
640struct lightbar_params { 969struct lightbar_params {
641 /* Timing */ 970 /* Timing */
642 int google_ramp_up; 971 int32_t google_ramp_up;
643 int google_ramp_down; 972 int32_t google_ramp_down;
644 int s3s0_ramp_up; 973 int32_t s3s0_ramp_up;
645 int s0_tick_delay[2]; /* AC=0/1 */ 974 int32_t s0_tick_delay[2]; /* AC=0/1 */
646 int s0a_tick_delay[2]; /* AC=0/1 */ 975 int32_t s0a_tick_delay[2]; /* AC=0/1 */
647 int s0s3_ramp_down; 976 int32_t s0s3_ramp_down;
648 int s3_sleep_for; 977 int32_t s3_sleep_for;
649 int s3_ramp_up; 978 int32_t s3_ramp_up;
650 int s3_ramp_down; 979 int32_t s3_ramp_down;
651 980
652 /* Oscillation */ 981 /* Oscillation */
653 uint8_t new_s0; 982 uint8_t new_s0;
@@ -676,7 +1005,7 @@ struct ec_params_lightbar {
676 union { 1005 union {
677 struct { 1006 struct {
678 /* no args */ 1007 /* no args */
679 } dump, off, on, init, get_seq, get_params; 1008 } dump, off, on, init, get_seq, get_params, version;
680 1009
681 struct num { 1010 struct num {
682 uint8_t num; 1011 uint8_t num;
@@ -710,6 +1039,11 @@ struct ec_response_lightbar {
710 1039
711 struct lightbar_params get_params; 1040 struct lightbar_params get_params;
712 1041
1042 struct version {
1043 uint32_t num;
1044 uint32_t flags;
1045 } version;
1046
713 struct { 1047 struct {
714 /* no return params */ 1048 /* no return params */
715 } off, on, init, brightness, seq, reg, rgb, demo, set_params; 1049 } off, on, init, brightness, seq, reg, rgb, demo, set_params;
@@ -730,10 +1064,62 @@ enum lightbar_command {
730 LIGHTBAR_CMD_DEMO = 9, 1064 LIGHTBAR_CMD_DEMO = 9,
731 LIGHTBAR_CMD_GET_PARAMS = 10, 1065 LIGHTBAR_CMD_GET_PARAMS = 10,
732 LIGHTBAR_CMD_SET_PARAMS = 11, 1066 LIGHTBAR_CMD_SET_PARAMS = 11,
1067 LIGHTBAR_CMD_VERSION = 12,
733 LIGHTBAR_NUM_CMDS 1068 LIGHTBAR_NUM_CMDS
734}; 1069};
735 1070
736/*****************************************************************************/ 1071/*****************************************************************************/
1072/* LED control commands */
1073
1074#define EC_CMD_LED_CONTROL 0x29
1075
1076enum ec_led_id {
1077 /* LED to indicate battery state of charge */
1078 EC_LED_ID_BATTERY_LED = 0,
1079 /*
1080 * LED to indicate system power state (on or in suspend).
1081 * May be on power button or on C-panel.
1082 */
1083 EC_LED_ID_POWER_LED,
1084 /* LED on power adapter or its plug */
1085 EC_LED_ID_ADAPTER_LED,
1086
1087 EC_LED_ID_COUNT
1088};
1089
1090/* LED control flags */
1091#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
1092#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */
1093
1094enum ec_led_colors {
1095 EC_LED_COLOR_RED = 0,
1096 EC_LED_COLOR_GREEN,
1097 EC_LED_COLOR_BLUE,
1098 EC_LED_COLOR_YELLOW,
1099 EC_LED_COLOR_WHITE,
1100
1101 EC_LED_COLOR_COUNT
1102};
1103
1104struct ec_params_led_control {
1105 uint8_t led_id; /* Which LED to control */
1106 uint8_t flags; /* Control flags */
1107
1108 uint8_t brightness[EC_LED_COLOR_COUNT];
1109} __packed;
1110
1111struct ec_response_led_control {
1112 /*
1113 * Available brightness value range.
1114 *
1115 * Range 0 means color channel not present.
1116 * Range 1 means on/off control.
1117 * Other values means the LED is control by PWM.
1118 */
1119 uint8_t brightness_range[EC_LED_COLOR_COUNT];
1120} __packed;
1121
1122/*****************************************************************************/
737/* Verified boot commands */ 1123/* Verified boot commands */
738 1124
739/* 1125/*
@@ -790,6 +1176,181 @@ enum ec_vboot_hash_status {
790#define EC_VBOOT_HASH_OFFSET_RW 0xfffffffd 1176#define EC_VBOOT_HASH_OFFSET_RW 0xfffffffd
791 1177
792/*****************************************************************************/ 1178/*****************************************************************************/
1179/*
1180 * Motion sense commands. We'll make separate structs for sub-commands with
1181 * different input args, so that we know how much to expect.
1182 */
1183#define EC_CMD_MOTION_SENSE_CMD 0x2B
1184
1185/* Motion sense commands */
1186enum motionsense_command {
1187 /*
1188 * Dump command returns all motion sensor data including motion sense
1189 * module flags and individual sensor flags.
1190 */
1191 MOTIONSENSE_CMD_DUMP = 0,
1192
1193 /*
1194 * Info command returns data describing the details of a given sensor,
1195 * including enum motionsensor_type, enum motionsensor_location, and
1196 * enum motionsensor_chip.
1197 */
1198 MOTIONSENSE_CMD_INFO = 1,
1199
1200 /*
1201 * EC Rate command is a setter/getter command for the EC sampling rate
1202 * of all motion sensors in milliseconds.
1203 */
1204 MOTIONSENSE_CMD_EC_RATE = 2,
1205
1206 /*
1207 * Sensor ODR command is a setter/getter command for the output data
1208 * rate of a specific motion sensor in millihertz.
1209 */
1210 MOTIONSENSE_CMD_SENSOR_ODR = 3,
1211
1212 /*
1213 * Sensor range command is a setter/getter command for the range of
1214 * a specified motion sensor in +/-G's or +/- deg/s.
1215 */
1216 MOTIONSENSE_CMD_SENSOR_RANGE = 4,
1217
1218 /*
1219 * Setter/getter command for the keyboard wake angle. When the lid
1220 * angle is greater than this value, keyboard wake is disabled in S3,
1221 * and when the lid angle goes less than this value, keyboard wake is
1222 * enabled. Note, the lid angle measurement is an approximate,
1223 * un-calibrated value, hence the wake angle isn't exact.
1224 */
1225 MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5,
1226
1227 /* Number of motionsense sub-commands. */
1228 MOTIONSENSE_NUM_CMDS
1229};
1230
1231enum motionsensor_id {
1232 EC_MOTION_SENSOR_ACCEL_BASE = 0,
1233 EC_MOTION_SENSOR_ACCEL_LID = 1,
1234 EC_MOTION_SENSOR_GYRO = 2,
1235
1236 /*
1237 * Note, if more sensors are added and this count changes, the padding
1238 * in ec_response_motion_sense dump command must be modified.
1239 */
1240 EC_MOTION_SENSOR_COUNT = 3
1241};
1242
1243/* List of motion sensor types. */
1244enum motionsensor_type {
1245 MOTIONSENSE_TYPE_ACCEL = 0,
1246 MOTIONSENSE_TYPE_GYRO = 1,
1247};
1248
1249/* List of motion sensor locations. */
1250enum motionsensor_location {
1251 MOTIONSENSE_LOC_BASE = 0,
1252 MOTIONSENSE_LOC_LID = 1,
1253};
1254
1255/* List of motion sensor chips. */
1256enum motionsensor_chip {
1257 MOTIONSENSE_CHIP_KXCJ9 = 0,
1258};
1259
1260/* Module flag masks used for the dump sub-command. */
1261#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0)
1262
1263/* Sensor flag masks used for the dump sub-command. */
1264#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0)
1265
1266/*
1267 * Send this value for the data element to only perform a read. If you
1268 * send any other value, the EC will interpret it as data to set and will
1269 * return the actual value set.
1270 */
1271#define EC_MOTION_SENSE_NO_VALUE -1
1272
1273struct ec_params_motion_sense {
1274 uint8_t cmd;
1275 union {
1276 /* Used for MOTIONSENSE_CMD_DUMP. */
1277 struct {
1278 /* no args */
1279 } dump;
1280
1281 /*
1282 * Used for MOTIONSENSE_CMD_EC_RATE and
1283 * MOTIONSENSE_CMD_KB_WAKE_ANGLE.
1284 */
1285 struct {
1286 /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */
1287 int16_t data;
1288 } ec_rate, kb_wake_angle;
1289
1290 /* Used for MOTIONSENSE_CMD_INFO. */
1291 struct {
1292 /* Should be element of enum motionsensor_id. */
1293 uint8_t sensor_num;
1294 } info;
1295
1296 /*
1297 * Used for MOTIONSENSE_CMD_SENSOR_ODR and
1298 * MOTIONSENSE_CMD_SENSOR_RANGE.
1299 */
1300 struct {
1301 /* Should be element of enum motionsensor_id. */
1302 uint8_t sensor_num;
1303
1304 /* Rounding flag, true for round-up, false for down. */
1305 uint8_t roundup;
1306
1307 uint16_t reserved;
1308
1309 /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */
1310 int32_t data;
1311 } sensor_odr, sensor_range;
1312 };
1313} __packed;
1314
1315struct ec_response_motion_sense {
1316 union {
1317 /* Used for MOTIONSENSE_CMD_DUMP. */
1318 struct {
1319 /* Flags representing the motion sensor module. */
1320 uint8_t module_flags;
1321
1322 /* Flags for each sensor in enum motionsensor_id. */
1323 uint8_t sensor_flags[EC_MOTION_SENSOR_COUNT];
1324
1325 /* Array of all sensor data. Each sensor is 3-axis. */
1326 int16_t data[3*EC_MOTION_SENSOR_COUNT];
1327 } dump;
1328
1329 /* Used for MOTIONSENSE_CMD_INFO. */
1330 struct {
1331 /* Should be element of enum motionsensor_type. */
1332 uint8_t type;
1333
1334 /* Should be element of enum motionsensor_location. */
1335 uint8_t location;
1336
1337 /* Should be element of enum motionsensor_chip. */
1338 uint8_t chip;
1339 } info;
1340
1341 /*
1342 * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR,
1343 * MOTIONSENSE_CMD_SENSOR_RANGE, and
1344 * MOTIONSENSE_CMD_KB_WAKE_ANGLE.
1345 */
1346 struct {
1347 /* Current value of the parameter queried. */
1348 int32_t ret;
1349 } ec_rate, sensor_odr, sensor_range, kb_wake_angle;
1350 };
1351} __packed;
1352
1353/*****************************************************************************/
793/* USB charging control commands */ 1354/* USB charging control commands */
794 1355
795/* Set USB port charging mode */ 1356/* Set USB port charging mode */
@@ -868,20 +1429,27 @@ struct ec_response_port80_last_boot {
868} __packed; 1429} __packed;
869 1430
870/*****************************************************************************/ 1431/*****************************************************************************/
871/* Thermal engine commands */ 1432/* Thermal engine commands. Note that there are two implementations. We'll
1433 * reuse the command number, but the data and behavior is incompatible.
1434 * Version 0 is what originally shipped on Link.
1435 * Version 1 separates the CPU thermal limits from the fan control.
1436 */
872 1437
873/* Set thershold value */
874#define EC_CMD_THERMAL_SET_THRESHOLD 0x50 1438#define EC_CMD_THERMAL_SET_THRESHOLD 0x50
1439#define EC_CMD_THERMAL_GET_THRESHOLD 0x51
1440
1441/* The version 0 structs are opaque. You have to know what they are for
1442 * the get/set commands to make any sense.
1443 */
875 1444
1445/* Version 0 - set */
876struct ec_params_thermal_set_threshold { 1446struct ec_params_thermal_set_threshold {
877 uint8_t sensor_type; 1447 uint8_t sensor_type;
878 uint8_t threshold_id; 1448 uint8_t threshold_id;
879 uint16_t value; 1449 uint16_t value;
880} __packed; 1450} __packed;
881 1451
882/* Get threshold value */ 1452/* Version 0 - get */
883#define EC_CMD_THERMAL_GET_THRESHOLD 0x51
884
885struct ec_params_thermal_get_threshold { 1453struct ec_params_thermal_get_threshold {
886 uint8_t sensor_type; 1454 uint8_t sensor_type;
887 uint8_t threshold_id; 1455 uint8_t threshold_id;
@@ -891,6 +1459,41 @@ struct ec_response_thermal_get_threshold {
891 uint16_t value; 1459 uint16_t value;
892} __packed; 1460} __packed;
893 1461
1462
1463/* The version 1 structs are visible. */
1464enum ec_temp_thresholds {
1465 EC_TEMP_THRESH_WARN = 0,
1466 EC_TEMP_THRESH_HIGH,
1467 EC_TEMP_THRESH_HALT,
1468
1469 EC_TEMP_THRESH_COUNT
1470};
1471
1472/* Thermal configuration for one temperature sensor. Temps are in degrees K.
1473 * Zero values will be silently ignored by the thermal task.
1474 */
1475struct ec_thermal_config {
1476 uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */
1477 uint32_t temp_fan_off; /* no active cooling needed */
1478 uint32_t temp_fan_max; /* max active cooling needed */
1479} __packed;
1480
1481/* Version 1 - get config for one sensor. */
1482struct ec_params_thermal_get_threshold_v1 {
1483 uint32_t sensor_num;
1484} __packed;
1485/* This returns a struct ec_thermal_config */
1486
1487/* Version 1 - set config for one sensor.
1488 * Use read-modify-write for best results! */
1489struct ec_params_thermal_set_threshold_v1 {
1490 uint32_t sensor_num;
1491 struct ec_thermal_config cfg;
1492} __packed;
1493/* This returns no data */
1494
1495/****************************************************************************/
1496
894/* Toggle automatic fan control */ 1497/* Toggle automatic fan control */
895#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x52 1498#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x52
896 1499
@@ -920,6 +1523,18 @@ struct ec_params_tmp006_set_calibration {
920 float b2; 1523 float b2;
921} __packed; 1524} __packed;
922 1525
1526/* Read raw TMP006 data */
1527#define EC_CMD_TMP006_GET_RAW 0x55
1528
1529struct ec_params_tmp006_get_raw {
1530 uint8_t index;
1531} __packed;
1532
1533struct ec_response_tmp006_get_raw {
1534 int32_t t; /* In 1/100 K */
1535 int32_t v; /* In nV */
1536};
1537
923/*****************************************************************************/ 1538/*****************************************************************************/
924/* MKBP - Matrix KeyBoard Protocol */ 1539/* MKBP - Matrix KeyBoard Protocol */
925 1540
@@ -1118,11 +1733,41 @@ struct ec_params_switch_enable_backlight {
1118 1733
1119/* Enable/disable WLAN/Bluetooth */ 1734/* Enable/disable WLAN/Bluetooth */
1120#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x91 1735#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x91
1736#define EC_VER_SWITCH_ENABLE_WIRELESS 1
1121 1737
1122struct ec_params_switch_enable_wireless { 1738/* Version 0 params; no response */
1739struct ec_params_switch_enable_wireless_v0 {
1123 uint8_t enabled; 1740 uint8_t enabled;
1124} __packed; 1741} __packed;
1125 1742
1743/* Version 1 params */
1744struct ec_params_switch_enable_wireless_v1 {
1745 /* Flags to enable now */
1746 uint8_t now_flags;
1747
1748 /* Which flags to copy from now_flags */
1749 uint8_t now_mask;
1750
1751 /*
1752 * Flags to leave enabled in S3, if they're on at the S0->S3
1753 * transition. (Other flags will be disabled by the S0->S3
1754 * transition.)
1755 */
1756 uint8_t suspend_flags;
1757
1758 /* Which flags to copy from suspend_flags */
1759 uint8_t suspend_mask;
1760} __packed;
1761
1762/* Version 1 response */
1763struct ec_response_switch_enable_wireless_v1 {
1764 /* Flags to enable now */
1765 uint8_t now_flags;
1766
1767 /* Flags to leave enabled in S3 */
1768 uint8_t suspend_flags;
1769} __packed;
1770
1126/*****************************************************************************/ 1771/*****************************************************************************/
1127/* GPIO commands. Only available on EC if write protect has been disabled. */ 1772/* GPIO commands. Only available on EC if write protect has been disabled. */
1128 1773
@@ -1147,11 +1792,16 @@ struct ec_response_gpio_get {
1147/*****************************************************************************/ 1792/*****************************************************************************/
1148/* I2C commands. Only available when flash write protect is unlocked. */ 1793/* I2C commands. Only available when flash write protect is unlocked. */
1149 1794
1795/*
1796 * TODO(crosbug.com/p/23570): These commands are deprecated, and will be
1797 * removed soon. Use EC_CMD_I2C_XFER instead.
1798 */
1799
1150/* Read I2C bus */ 1800/* Read I2C bus */
1151#define EC_CMD_I2C_READ 0x94 1801#define EC_CMD_I2C_READ 0x94
1152 1802
1153struct ec_params_i2c_read { 1803struct ec_params_i2c_read {
1154 uint16_t addr; 1804 uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
1155 uint8_t read_size; /* Either 8 or 16. */ 1805 uint8_t read_size; /* Either 8 or 16. */
1156 uint8_t port; 1806 uint8_t port;
1157 uint8_t offset; 1807 uint8_t offset;
@@ -1165,7 +1815,7 @@ struct ec_response_i2c_read {
1165 1815
1166struct ec_params_i2c_write { 1816struct ec_params_i2c_write {
1167 uint16_t data; 1817 uint16_t data;
1168 uint16_t addr; 1818 uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
1169 uint8_t write_size; /* Either 8 or 16. */ 1819 uint8_t write_size; /* Either 8 or 16. */
1170 uint8_t port; 1820 uint8_t port;
1171 uint8_t offset; 1821 uint8_t offset;
@@ -1174,11 +1824,20 @@ struct ec_params_i2c_write {
1174/*****************************************************************************/ 1824/*****************************************************************************/
1175/* Charge state commands. Only available when flash write protect unlocked. */ 1825/* Charge state commands. Only available when flash write protect unlocked. */
1176 1826
1177/* Force charge state machine to stop in idle mode */ 1827/* Force charge state machine to stop charging the battery or force it to
1178#define EC_CMD_CHARGE_FORCE_IDLE 0x96 1828 * discharge the battery.
1829 */
1830#define EC_CMD_CHARGE_CONTROL 0x96
1831#define EC_VER_CHARGE_CONTROL 1
1179 1832
1180struct ec_params_force_idle { 1833enum ec_charge_control_mode {
1181 uint8_t enabled; 1834 CHARGE_CONTROL_NORMAL = 0,
1835 CHARGE_CONTROL_IDLE,
1836 CHARGE_CONTROL_DISCHARGE,
1837};
1838
1839struct ec_params_charge_control {
1840 uint32_t mode; /* enum charge_control_mode */
1182} __packed; 1841} __packed;
1183 1842
1184/*****************************************************************************/ 1843/*****************************************************************************/
@@ -1206,14 +1865,231 @@ struct ec_params_force_idle {
1206#define EC_CMD_BATTERY_CUT_OFF 0x99 1865#define EC_CMD_BATTERY_CUT_OFF 0x99
1207 1866
1208/*****************************************************************************/ 1867/*****************************************************************************/
1209/* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */ 1868/* USB port mux control. */
1210 1869
1211/* 1870/*
1212 * Dump charge state machine context. 1871 * Switch USB mux or return to automatic switching.
1213 * 1872 */
1214 * Response is a binary dump of charge state machine context. 1873#define EC_CMD_USB_MUX 0x9a
1874
1875struct ec_params_usb_mux {
1876 uint8_t mux;
1877} __packed;
1878
1879/*****************************************************************************/
1880/* LDOs / FETs control. */
1881
1882enum ec_ldo_state {
1883 EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */
1884 EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */
1885};
1886
1887/*
1888 * Switch on/off a LDO.
1889 */
1890#define EC_CMD_LDO_SET 0x9b
1891
1892struct ec_params_ldo_set {
1893 uint8_t index;
1894 uint8_t state;
1895} __packed;
1896
1897/*
1898 * Get LDO state.
1899 */
1900#define EC_CMD_LDO_GET 0x9c
1901
1902struct ec_params_ldo_get {
1903 uint8_t index;
1904} __packed;
1905
1906struct ec_response_ldo_get {
1907 uint8_t state;
1908} __packed;
1909
1910/*****************************************************************************/
1911/* Power info. */
1912
1913/*
1914 * Get power info.
1915 */
1916#define EC_CMD_POWER_INFO 0x9d
1917
1918struct ec_response_power_info {
1919 uint32_t usb_dev_type;
1920 uint16_t voltage_ac;
1921 uint16_t voltage_system;
1922 uint16_t current_system;
1923 uint16_t usb_current_limit;
1924} __packed;
1925
1926/*****************************************************************************/
1927/* I2C passthru command */
1928
1929#define EC_CMD_I2C_PASSTHRU 0x9e
1930
1931/* Slave address is 10 (not 7) bit */
1932#define EC_I2C_FLAG_10BIT (1 << 16)
1933
1934/* Read data; if not present, message is a write */
1935#define EC_I2C_FLAG_READ (1 << 15)
1936
1937/* Mask for address */
1938#define EC_I2C_ADDR_MASK 0x3ff
1939
1940#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */
1941#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */
1942
1943/* Any error */
1944#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
1945
1946struct ec_params_i2c_passthru_msg {
1947 uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */
1948 uint16_t len; /* Number of bytes to read or write */
1949} __packed;
1950
1951struct ec_params_i2c_passthru {
1952 uint8_t port; /* I2C port number */
1953 uint8_t num_msgs; /* Number of messages */
1954 struct ec_params_i2c_passthru_msg msg[];
1955 /* Data to write for all messages is concatenated here */
1956} __packed;
1957
1958struct ec_response_i2c_passthru {
1959 uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */
1960 uint8_t num_msgs; /* Number of messages processed */
1961 uint8_t data[]; /* Data read by messages concatenated here */
1962} __packed;
1963
1964/*****************************************************************************/
1965/* Power button hang detect */
1966
1967#define EC_CMD_HANG_DETECT 0x9f
1968
1969/* Reasons to start hang detection timer */
1970/* Power button pressed */
1971#define EC_HANG_START_ON_POWER_PRESS (1 << 0)
1972
1973/* Lid closed */
1974#define EC_HANG_START_ON_LID_CLOSE (1 << 1)
1975
1976 /* Lid opened */
1977#define EC_HANG_START_ON_LID_OPEN (1 << 2)
1978
1979/* Start of AP S3->S0 transition (booting or resuming from suspend) */
1980#define EC_HANG_START_ON_RESUME (1 << 3)
1981
1982/* Reasons to cancel hang detection */
1983
1984/* Power button released */
1985#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8)
1986
1987/* Any host command from AP received */
1988#define EC_HANG_STOP_ON_HOST_COMMAND (1 << 9)
1989
1990/* Stop on end of AP S0->S3 transition (suspending or shutting down) */
1991#define EC_HANG_STOP_ON_SUSPEND (1 << 10)
1992
1993/*
1994 * If this flag is set, all the other fields are ignored, and the hang detect
1995 * timer is started. This provides the AP a way to start the hang timer
1996 * without reconfiguring any of the other hang detect settings. Note that
1997 * you must previously have configured the timeouts.
1998 */
1999#define EC_HANG_START_NOW (1 << 30)
2000
2001/*
2002 * If this flag is set, all the other fields are ignored (including
2003 * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer
2004 * without reconfiguring any of the other hang detect settings.
1215 */ 2005 */
1216#define EC_CMD_CHARGE_DUMP 0xa0 2006#define EC_HANG_STOP_NOW (1 << 31)
2007
2008struct ec_params_hang_detect {
2009 /* Flags; see EC_HANG_* */
2010 uint32_t flags;
2011
2012 /* Timeout in msec before generating host event, if enabled */
2013 uint16_t host_event_timeout_msec;
2014
2015 /* Timeout in msec before generating warm reboot, if enabled */
2016 uint16_t warm_reboot_timeout_msec;
2017} __packed;
2018
2019/*****************************************************************************/
2020/* Commands for battery charging */
2021
2022/*
2023 * This is the single catch-all host command to exchange data regarding the
2024 * charge state machine (v2 and up).
2025 */
2026#define EC_CMD_CHARGE_STATE 0xa0
2027
2028/* Subcommands for this host command */
2029enum charge_state_command {
2030 CHARGE_STATE_CMD_GET_STATE,
2031 CHARGE_STATE_CMD_GET_PARAM,
2032 CHARGE_STATE_CMD_SET_PARAM,
2033 CHARGE_STATE_NUM_CMDS
2034};
2035
2036/*
2037 * Known param numbers are defined here. Ranges are reserved for board-specific
2038 * params, which are handled by the particular implementations.
2039 */
2040enum charge_state_params {
2041 CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */
2042 CS_PARAM_CHG_CURRENT, /* charger current limit */
2043 CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */
2044 CS_PARAM_CHG_STATUS, /* charger-specific status */
2045 CS_PARAM_CHG_OPTION, /* charger-specific options */
2046 /* How many so far? */
2047 CS_NUM_BASE_PARAMS,
2048
2049 /* Range for CONFIG_CHARGER_PROFILE_OVERRIDE params */
2050 CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000,
2051 CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff,
2052
2053 /* Other custom param ranges go here... */
2054};
2055
2056struct ec_params_charge_state {
2057 uint8_t cmd; /* enum charge_state_command */
2058 union {
2059 struct {
2060 /* no args */
2061 } get_state;
2062
2063 struct {
2064 uint32_t param; /* enum charge_state_param */
2065 } get_param;
2066
2067 struct {
2068 uint32_t param; /* param to set */
2069 uint32_t value; /* value to set */
2070 } set_param;
2071 };
2072} __packed;
2073
2074struct ec_response_charge_state {
2075 union {
2076 struct {
2077 int ac;
2078 int chg_voltage;
2079 int chg_current;
2080 int chg_input_current;
2081 int batt_state_of_charge;
2082 } get_state;
2083
2084 struct {
2085 uint32_t value;
2086 } get_param;
2087 struct {
2088 /* no return values */
2089 } set_param;
2090 };
2091} __packed;
2092
1217 2093
1218/* 2094/*
1219 * Set maximum battery charging current. 2095 * Set maximum battery charging current.
@@ -1221,15 +2097,59 @@ struct ec_params_force_idle {
1221#define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1 2097#define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1
1222 2098
1223struct ec_params_current_limit { 2099struct ec_params_current_limit {
1224 uint32_t limit; 2100 uint32_t limit; /* in mA */
2101} __packed;
2102
2103/*
2104 * Set maximum external power current.
2105 */
2106#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2
2107
2108struct ec_params_ext_power_current_limit {
2109 uint32_t limit; /* in mA */
2110} __packed;
2111
2112/*****************************************************************************/
2113/* Smart battery pass-through */
2114
2115/* Get / Set 16-bit smart battery registers */
2116#define EC_CMD_SB_READ_WORD 0xb0
2117#define EC_CMD_SB_WRITE_WORD 0xb1
2118
2119/* Get / Set string smart battery parameters
2120 * formatted as SMBUS "block".
2121 */
2122#define EC_CMD_SB_READ_BLOCK 0xb2
2123#define EC_CMD_SB_WRITE_BLOCK 0xb3
2124
2125struct ec_params_sb_rd {
2126 uint8_t reg;
2127} __packed;
2128
2129struct ec_response_sb_rd_word {
2130 uint16_t value;
2131} __packed;
2132
2133struct ec_params_sb_wr_word {
2134 uint8_t reg;
2135 uint16_t value;
2136} __packed;
2137
2138struct ec_response_sb_rd_block {
2139 uint8_t data[32];
2140} __packed;
2141
2142struct ec_params_sb_wr_block {
2143 uint8_t reg;
2144 uint16_t data[32];
1225} __packed; 2145} __packed;
1226 2146
1227/*****************************************************************************/ 2147/*****************************************************************************/
1228/* System commands */ 2148/* System commands */
1229 2149
1230/* 2150/*
1231 * TODO: this is a confusing name, since it doesn't necessarily reboot the EC. 2151 * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't
1232 * Rename to "set image" or something similar. 2152 * necessarily reboot the EC. Rename to "image" or something similar?
1233 */ 2153 */
1234#define EC_CMD_REBOOT_EC 0xd2 2154#define EC_CMD_REBOOT_EC 0xd2
1235 2155
@@ -1308,6 +2228,7 @@ struct ec_params_reboot_ec {
1308#define EC_CMD_ACPI_QUERY_EVENT 0x84 2228#define EC_CMD_ACPI_QUERY_EVENT 0x84
1309 2229
1310/* Valid addresses in ACPI memory space, for read/write commands */ 2230/* Valid addresses in ACPI memory space, for read/write commands */
2231
1311/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ 2232/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
1312#define EC_ACPI_MEM_VERSION 0x00 2233#define EC_ACPI_MEM_VERSION 0x00
1313/* 2234/*
@@ -1317,8 +2238,60 @@ struct ec_params_reboot_ec {
1317#define EC_ACPI_MEM_TEST 0x01 2238#define EC_ACPI_MEM_TEST 0x01
1318/* Test compliment; writes here are ignored. */ 2239/* Test compliment; writes here are ignored. */
1319#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 2240#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
2241
1320/* Keyboard backlight brightness percent (0 - 100) */ 2242/* Keyboard backlight brightness percent (0 - 100) */
1321#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 2243#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
2244/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */
2245#define EC_ACPI_MEM_FAN_DUTY 0x04
2246
2247/*
2248 * DPTF temp thresholds. Any of the EC's temp sensors can have up to two
2249 * independent thresholds attached to them. The current value of the ID
2250 * register determines which sensor is affected by the THRESHOLD and COMMIT
2251 * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme
2252 * as the memory-mapped sensors. The COMMIT register applies those settings.
2253 *
2254 * The spec does not mandate any way to read back the threshold settings
2255 * themselves, but when a threshold is crossed the AP needs a way to determine
2256 * which sensor(s) are responsible. Each reading of the ID register clears and
2257 * returns one sensor ID that has crossed one of its threshold (in either
2258 * direction) since the last read. A value of 0xFF means "no new thresholds
2259 * have tripped". Setting or enabling the thresholds for a sensor will clear
2260 * the unread event count for that sensor.
2261 */
2262#define EC_ACPI_MEM_TEMP_ID 0x05
2263#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
2264#define EC_ACPI_MEM_TEMP_COMMIT 0x07
2265/*
2266 * Here are the bits for the COMMIT register:
2267 * bit 0 selects the threshold index for the chosen sensor (0/1)
2268 * bit 1 enables/disables the selected threshold (0 = off, 1 = on)
2269 * Each write to the commit register affects one threshold.
2270 */
2271#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0)
2272#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1)
2273/*
2274 * Example:
2275 *
2276 * Set the thresholds for sensor 2 to 50 C and 60 C:
2277 * write 2 to [0x05] -- select temp sensor 2
2278 * write 0x7b to [0x06] -- C_TO_K(50) - EC_TEMP_SENSOR_OFFSET
2279 * write 0x2 to [0x07] -- enable threshold 0 with this value
2280 * write 0x85 to [0x06] -- C_TO_K(60) - EC_TEMP_SENSOR_OFFSET
2281 * write 0x3 to [0x07] -- enable threshold 1 with this value
2282 *
2283 * Disable the 60 C threshold, leaving the 50 C threshold unchanged:
2284 * write 2 to [0x05] -- select temp sensor 2
2285 * write 0x1 to [0x07] -- disable threshold 1
2286 */
2287
2288/* DPTF battery charging current limit */
2289#define EC_ACPI_MEM_CHARGING_LIMIT 0x08
2290
2291/* Charging limit is specified in 64 mA steps */
2292#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
2293/* Value to disable DPTF battery charging limit */
2294#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
1322 2295
1323/* Current version of ACPI memory address space */ 2296/* Current version of ACPI memory address space */
1324#define EC_ACPI_MEM_VERSION_CURRENT 1 2297#define EC_ACPI_MEM_VERSION_CURRENT 1
@@ -1360,10 +2333,21 @@ struct ec_params_reboot_ec {
1360 * Header bytes greater than this indicate a later version. For example, 2333 * Header bytes greater than this indicate a later version. For example,
1361 * EC_CMD_VERSION0 + 1 means we are using version 1. 2334 * EC_CMD_VERSION0 + 1 means we are using version 1.
1362 * 2335 *
1363 * The old EC interface must not use commands 0dc or higher. 2336 * The old EC interface must not use commands 0xdc or higher.
1364 */ 2337 */
1365#define EC_CMD_VERSION0 0xdc 2338#define EC_CMD_VERSION0 0xdc
1366 2339
1367#endif /* !__ACPI__ */ 2340#endif /* !__ACPI__ */
1368 2341
2342/*****************************************************************************/
2343/*
2344 * Deprecated constants. These constants have been renamed for clarity. The
2345 * meaning and size has not changed. Programs that use the old names should
2346 * switch to the new names soon, as the old names may not be carried forward
2347 * forever.
2348 */
2349#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
2350#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
2351#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
2352
1369#endif /* __CROS_EC_COMMANDS_H */ 2353#endif /* __CROS_EC_COMMANDS_H */
diff --git a/include/linux/mfd/ipaq-micro.h b/include/linux/mfd/ipaq-micro.h
new file mode 100644
index 000000000000..5c4d29f6674f
--- /dev/null
+++ b/include/linux/mfd/ipaq-micro.h
@@ -0,0 +1,148 @@
1/*
2 * Header file for the compaq Micro MFD
3 */
4
5#ifndef _MFD_IPAQ_MICRO_H_
6#define _MFD_IPAQ_MICRO_H_
7
8#include <linux/spinlock.h>
9#include <linux/completion.h>
10#include <linux/list.h>
11
12#define TX_BUF_SIZE 32
13#define RX_BUF_SIZE 16
14#define CHAR_SOF 0x02
15
16/*
17 * These are the different messages that can be sent to the microcontroller
18 * to control various aspects.
19 */
20#define MSG_VERSION 0x0
21#define MSG_KEYBOARD 0x2
22#define MSG_TOUCHSCREEN 0x3
23#define MSG_EEPROM_READ 0x4
24#define MSG_EEPROM_WRITE 0x5
25#define MSG_THERMAL_SENSOR 0x6
26#define MSG_NOTIFY_LED 0x8
27#define MSG_BATTERY 0x9
28#define MSG_SPI_READ 0xb
29#define MSG_SPI_WRITE 0xc
30#define MSG_BACKLIGHT 0xd /* H3600 only */
31#define MSG_CODEC_CTRL 0xe /* H3100 only */
32#define MSG_DISPLAY_CTRL 0xf /* H3100 only */
33
34/* state of receiver parser */
35enum rx_state {
36 STATE_SOF = 0, /* Next byte should be start of frame */
37 STATE_ID, /* Next byte is ID & message length */
38 STATE_DATA, /* Next byte is a data byte */
39 STATE_CHKSUM /* Next byte should be checksum */
40};
41
42/**
43 * struct ipaq_micro_txdev - TX state
44 * @len: length of message in TX buffer
45 * @index: current index into TX buffer
46 * @buf: TX buffer
47 */
48struct ipaq_micro_txdev {
49 u8 len;
50 u8 index;
51 u8 buf[TX_BUF_SIZE];
52};
53
54/**
55 * struct ipaq_micro_rxdev - RX state
56 * @state: context of RX state machine
57 * @chksum: calculated checksum
58 * @id: message ID from packet
59 * @len: RX buffer length
60 * @index: RX buffer index
61 * @buf: RX buffer
62 */
63struct ipaq_micro_rxdev {
64 enum rx_state state;
65 unsigned char chksum;
66 u8 id;
67 unsigned int len;
68 unsigned int index;
69 u8 buf[RX_BUF_SIZE];
70};
71
72/**
73 * struct ipaq_micro_msg - message to the iPAQ microcontroller
74 * @id: 4-bit ID of the message
75 * @tx_len: length of TX data
76 * @tx_data: TX data to send
77 * @rx_len: length of receieved RX data
78 * @rx_data: RX data to recieve
79 * @ack: a completion that will be completed when RX is complete
80 * @node: list node if message gets queued
81 */
82struct ipaq_micro_msg {
83 u8 id;
84 u8 tx_len;
85 u8 tx_data[TX_BUF_SIZE];
86 u8 rx_len;
87 u8 rx_data[RX_BUF_SIZE];
88 struct completion ack;
89 struct list_head node;
90};
91
92/**
93 * struct ipaq_micro - iPAQ microcontroller state
94 * @dev: corresponding platform device
95 * @base: virtual memory base for underlying serial device
96 * @sdlc: virtual memory base for Synchronous Data Link Controller
97 * @version: version string
98 * @tx: TX state
99 * @rx: RX state
100 * @lock: lock for this state container
101 * @msg: current message
102 * @queue: message queue
103 * @key: callback for asynchronous key events
104 * @key_data: data to pass along with key events
105 * @ts: callback for asynchronous touchscreen events
106 * @ts_data: data to pass along with key events
107 */
108struct ipaq_micro {
109 struct device *dev;
110 void __iomem *base;
111 void __iomem *sdlc;
112 char version[5];
113 struct ipaq_micro_txdev tx; /* transmit ISR state */
114 struct ipaq_micro_rxdev rx; /* receive ISR state */
115 spinlock_t lock;
116 struct ipaq_micro_msg *msg;
117 struct list_head queue;
118 void (*key) (void *data, int len, unsigned char *rxdata);
119 void *key_data;
120 void (*ts) (void *data, int len, unsigned char *rxdata);
121 void *ts_data;
122};
123
124extern int
125ipaq_micro_tx_msg(struct ipaq_micro *micro, struct ipaq_micro_msg *msg);
126
127static inline int
128ipaq_micro_tx_msg_sync(struct ipaq_micro *micro,
129 struct ipaq_micro_msg *msg)
130{
131 int ret;
132
133 init_completion(&msg->ack);
134 ret = ipaq_micro_tx_msg(micro, msg);
135 wait_for_completion(&msg->ack);
136
137 return ret;
138}
139
140static inline int
141ipaq_micro_tx_msg_async(struct ipaq_micro *micro,
142 struct ipaq_micro_msg *msg)
143{
144 init_completion(&msg->ack);
145 return ipaq_micro_tx_msg(micro, msg);
146}
147
148#endif /* _MFD_IPAQ_MICRO_H_ */
diff --git a/include/linux/mfd/kempld.h b/include/linux/mfd/kempld.h
index b911ef3add03..26e0b469e567 100644
--- a/include/linux/mfd/kempld.h
+++ b/include/linux/mfd/kempld.h
@@ -51,6 +51,8 @@
51#define KEMPLD_TYPE_DEBUG 0x1 51#define KEMPLD_TYPE_DEBUG 0x1
52#define KEMPLD_TYPE_CUSTOM 0x2 52#define KEMPLD_TYPE_CUSTOM 0x2
53 53
54#define KEMPLD_VERSION_LEN 10
55
54/** 56/**
55 * struct kempld_info - PLD device information structure 57 * struct kempld_info - PLD device information structure
56 * @major: PLD major revision 58 * @major: PLD major revision
@@ -60,6 +62,7 @@
60 * @type: PLD type 62 * @type: PLD type
61 * @spec_major: PLD FW specification major revision 63 * @spec_major: PLD FW specification major revision
62 * @spec_minor: PLD FW specification minor revision 64 * @spec_minor: PLD FW specification minor revision
65 * @version: PLD version string
63 */ 66 */
64struct kempld_info { 67struct kempld_info {
65 unsigned int major; 68 unsigned int major;
@@ -69,6 +72,7 @@ struct kempld_info {
69 unsigned int type; 72 unsigned int type;
70 unsigned int spec_major; 73 unsigned int spec_major;
71 unsigned int spec_minor; 74 unsigned int spec_minor;
75 char version[KEMPLD_VERSION_LEN];
72}; 76};
73 77
74/** 78/**
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index a326c850f046..d63b1d309106 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -117,10 +117,6 @@ struct mc13xxx_led_platform_data {
117 117
118#define MAX_LED_CONTROL_REGS 6 118#define MAX_LED_CONTROL_REGS 6
119 119
120struct mc13xxx_leds_platform_data {
121 struct mc13xxx_led_platform_data *led;
122 int num_leds;
123
124/* MC13783 LED Control 0 */ 120/* MC13783 LED Control 0 */
125#define MC13783_LED_C0_ENABLE (1 << 0) 121#define MC13783_LED_C0_ENABLE (1 << 0)
126#define MC13783_LED_C0_TRIODE_MD (1 << 7) 122#define MC13783_LED_C0_TRIODE_MD (1 << 7)
@@ -169,10 +165,13 @@ struct mc13xxx_leds_platform_data {
169/* MC34708 LED Control 0 */ 165/* MC34708 LED Control 0 */
170#define MC34708_LED_C0_CURRENT_R(x) (((x) & 0x3) << 9) 166#define MC34708_LED_C0_CURRENT_R(x) (((x) & 0x3) << 9)
171#define MC34708_LED_C0_CURRENT_G(x) (((x) & 0x3) << 21) 167#define MC34708_LED_C0_CURRENT_G(x) (((x) & 0x3) << 21)
168
169struct mc13xxx_leds_platform_data {
170 struct mc13xxx_led_platform_data *led;
171 int num_leds;
172 u32 led_control[MAX_LED_CONTROL_REGS]; 172 u32 led_control[MAX_LED_CONTROL_REGS];
173}; 173};
174 174
175struct mc13xxx_buttons_platform_data {
176#define MC13783_BUTTON_DBNC_0MS 0 175#define MC13783_BUTTON_DBNC_0MS 0
177#define MC13783_BUTTON_DBNC_30MS 1 176#define MC13783_BUTTON_DBNC_30MS 1
178#define MC13783_BUTTON_DBNC_150MS 2 177#define MC13783_BUTTON_DBNC_150MS 2
@@ -180,6 +179,8 @@ struct mc13xxx_buttons_platform_data {
180#define MC13783_BUTTON_ENABLE (1 << 2) 179#define MC13783_BUTTON_ENABLE (1 << 2)
181#define MC13783_BUTTON_POL_INVERT (1 << 3) 180#define MC13783_BUTTON_POL_INVERT (1 << 3)
182#define MC13783_BUTTON_RESET_EN (1 << 4) 181#define MC13783_BUTTON_RESET_EN (1 << 4)
182
183struct mc13xxx_buttons_platform_data {
183 int b1on_flags; 184 int b1on_flags;
184 unsigned short b1on_key; 185 unsigned short b1on_key;
185 int b2on_flags; 186 int b2on_flags;
@@ -188,14 +189,14 @@ struct mc13xxx_buttons_platform_data {
188 unsigned short b3on_key; 189 unsigned short b3on_key;
189}; 190};
190 191
192#define MC13783_TS_ATO_FIRST false
193#define MC13783_TS_ATO_EACH true
194
191struct mc13xxx_ts_platform_data { 195struct mc13xxx_ts_platform_data {
192 /* Delay between Touchscreen polarization and ADC Conversion. 196 /* Delay between Touchscreen polarization and ADC Conversion.
193 * Given in clock ticks of a 32 kHz clock which gives a granularity of 197 * Given in clock ticks of a 32 kHz clock which gives a granularity of
194 * about 30.5ms */ 198 * about 30.5ms */
195 u8 ato; 199 u8 ato;
196
197#define MC13783_TS_ATO_FIRST false
198#define MC13783_TS_ATO_EACH true
199 /* Use the ATO delay only for the first conversion or for each one */ 200 /* Use the ATO delay only for the first conversion or for each one */
200 bool atox; 201 bool atox;
201}; 202};
@@ -210,11 +211,12 @@ struct mc13xxx_codec_platform_data {
210 enum mc13783_ssi_port dac_ssi_port; 211 enum mc13783_ssi_port dac_ssi_port;
211}; 212};
212 213
213struct mc13xxx_platform_data { 214#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
214#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
215#define MC13XXX_USE_CODEC (1 << 1) 215#define MC13XXX_USE_CODEC (1 << 1)
216#define MC13XXX_USE_ADC (1 << 2) 216#define MC13XXX_USE_ADC (1 << 2)
217#define MC13XXX_USE_RTC (1 << 3) 217#define MC13XXX_USE_RTC (1 << 3)
218
219struct mc13xxx_platform_data {
218 unsigned int flags; 220 unsigned int flags;
219 221
220 struct mc13xxx_regulator_platform_data regulators; 222 struct mc13xxx_regulator_platform_data regulators;
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index b8f87b704409..3420e09e2e20 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -482,10 +482,10 @@ enum usb_irq_events {
482 482
483/* helper macro to get correct slave number */ 483/* helper macro to get correct slave number */
484#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 484#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
485#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) 485#define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
486 486
487/* Base addresses of IP blocks in Palmas */ 487/* Base addresses of IP blocks in Palmas */
488#define PALMAS_SMPS_DVS_BASE 0x20 488#define PALMAS_SMPS_DVS_BASE 0x020
489#define PALMAS_RTC_BASE 0x100 489#define PALMAS_RTC_BASE 0x100
490#define PALMAS_VALIDITY_BASE 0x118 490#define PALMAS_VALIDITY_BASE 0x118
491#define PALMAS_SMPS_BASE 0x120 491#define PALMAS_SMPS_BASE 0x120
@@ -504,19 +504,19 @@ enum usb_irq_events {
504#define PALMAS_TRIM_GPADC_BASE 0x3CD 504#define PALMAS_TRIM_GPADC_BASE 0x3CD
505 505
506/* Registers for function RTC */ 506/* Registers for function RTC */
507#define PALMAS_SECONDS_REG 0x0 507#define PALMAS_SECONDS_REG 0x00
508#define PALMAS_MINUTES_REG 0x1 508#define PALMAS_MINUTES_REG 0x01
509#define PALMAS_HOURS_REG 0x2 509#define PALMAS_HOURS_REG 0x02
510#define PALMAS_DAYS_REG 0x3 510#define PALMAS_DAYS_REG 0x03
511#define PALMAS_MONTHS_REG 0x4 511#define PALMAS_MONTHS_REG 0x04
512#define PALMAS_YEARS_REG 0x5 512#define PALMAS_YEARS_REG 0x05
513#define PALMAS_WEEKS_REG 0x6 513#define PALMAS_WEEKS_REG 0x06
514#define PALMAS_ALARM_SECONDS_REG 0x8 514#define PALMAS_ALARM_SECONDS_REG 0x08
515#define PALMAS_ALARM_MINUTES_REG 0x9 515#define PALMAS_ALARM_MINUTES_REG 0x09
516#define PALMAS_ALARM_HOURS_REG 0xA 516#define PALMAS_ALARM_HOURS_REG 0x0A
517#define PALMAS_ALARM_DAYS_REG 0xB 517#define PALMAS_ALARM_DAYS_REG 0x0B
518#define PALMAS_ALARM_MONTHS_REG 0xC 518#define PALMAS_ALARM_MONTHS_REG 0x0C
519#define PALMAS_ALARM_YEARS_REG 0xD 519#define PALMAS_ALARM_YEARS_REG 0x0D
520#define PALMAS_RTC_CTRL_REG 0x10 520#define PALMAS_RTC_CTRL_REG 0x10
521#define PALMAS_RTC_STATUS_REG 0x11 521#define PALMAS_RTC_STATUS_REG 0x11
522#define PALMAS_RTC_INTERRUPTS_REG 0x12 522#define PALMAS_RTC_INTERRUPTS_REG 0x12
@@ -527,201 +527,201 @@ enum usb_irq_events {
527 527
528/* Bit definitions for SECONDS_REG */ 528/* Bit definitions for SECONDS_REG */
529#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 529#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
530#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 530#define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
531#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f 531#define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
532#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 532#define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
533 533
534/* Bit definitions for MINUTES_REG */ 534/* Bit definitions for MINUTES_REG */
535#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 535#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
536#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 536#define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
537#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f 537#define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
538#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 538#define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
539 539
540/* Bit definitions for HOURS_REG */ 540/* Bit definitions for HOURS_REG */
541#define PALMAS_HOURS_REG_PM_NAM 0x80 541#define PALMAS_HOURS_REG_PM_NAM 0x80
542#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 542#define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
543#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 543#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
544#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 544#define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
545#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f 545#define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
546#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 546#define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
547 547
548/* Bit definitions for DAYS_REG */ 548/* Bit definitions for DAYS_REG */
549#define PALMAS_DAYS_REG_DAY1_MASK 0x30 549#define PALMAS_DAYS_REG_DAY1_MASK 0x30
550#define PALMAS_DAYS_REG_DAY1_SHIFT 4 550#define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
551#define PALMAS_DAYS_REG_DAY0_MASK 0x0f 551#define PALMAS_DAYS_REG_DAY0_MASK 0x0F
552#define PALMAS_DAYS_REG_DAY0_SHIFT 0 552#define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
553 553
554/* Bit definitions for MONTHS_REG */ 554/* Bit definitions for MONTHS_REG */
555#define PALMAS_MONTHS_REG_MONTH1 0x10 555#define PALMAS_MONTHS_REG_MONTH1 0x10
556#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 556#define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
557#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f 557#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
558#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 558#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
559 559
560/* Bit definitions for YEARS_REG */ 560/* Bit definitions for YEARS_REG */
561#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 561#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
562#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 562#define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
563#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f 563#define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
564#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 564#define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
565 565
566/* Bit definitions for WEEKS_REG */ 566/* Bit definitions for WEEKS_REG */
567#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 567#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
568#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 568#define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
569 569
570/* Bit definitions for ALARM_SECONDS_REG */ 570/* Bit definitions for ALARM_SECONDS_REG */
571#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 571#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
572#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 572#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
573#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f 573#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
574#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 574#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
575 575
576/* Bit definitions for ALARM_MINUTES_REG */ 576/* Bit definitions for ALARM_MINUTES_REG */
577#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 577#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
578#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 578#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
579#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f 579#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
580#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 580#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
581 581
582/* Bit definitions for ALARM_HOURS_REG */ 582/* Bit definitions for ALARM_HOURS_REG */
583#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 583#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
584#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 584#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
585#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 585#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
586#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 586#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
587#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f 587#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
588#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 588#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
589 589
590/* Bit definitions for ALARM_DAYS_REG */ 590/* Bit definitions for ALARM_DAYS_REG */
591#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 591#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
592#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 592#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
593#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f 593#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
594#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 594#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
595 595
596/* Bit definitions for ALARM_MONTHS_REG */ 596/* Bit definitions for ALARM_MONTHS_REG */
597#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 597#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
598#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 598#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
599#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f 599#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
600#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 600#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
601 601
602/* Bit definitions for ALARM_YEARS_REG */ 602/* Bit definitions for ALARM_YEARS_REG */
603#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 603#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
604#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 604#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
605#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f 605#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
606#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 606#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
607 607
608/* Bit definitions for RTC_CTRL_REG */ 608/* Bit definitions for RTC_CTRL_REG */
609#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 609#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
610#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 610#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
611#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 611#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
612#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 612#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
613#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 613#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
614#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 614#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
615#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 615#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
616#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 616#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
617#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 617#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
618#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 618#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
619#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 619#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
620#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 620#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
621#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 621#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
622#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 622#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
623#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 623#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
624#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 624#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
625 625
626/* Bit definitions for RTC_STATUS_REG */ 626/* Bit definitions for RTC_STATUS_REG */
627#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 627#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
628#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 628#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
629#define PALMAS_RTC_STATUS_REG_ALARM 0x40 629#define PALMAS_RTC_STATUS_REG_ALARM 0x40
630#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 630#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
631#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 631#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
632#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 632#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
633#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 633#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
634#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 634#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
635#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 635#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
636#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 636#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
637#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 637#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
638#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 638#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
639#define PALMAS_RTC_STATUS_REG_RUN 0x02 639#define PALMAS_RTC_STATUS_REG_RUN 0x02
640#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 640#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
641 641
642/* Bit definitions for RTC_INTERRUPTS_REG */ 642/* Bit definitions for RTC_INTERRUPTS_REG */
643#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 643#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
644#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 644#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
645#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 645#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
646#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 646#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
647#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 647#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
648#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 648#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
649#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 649#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
650#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 650#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
651 651
652/* Bit definitions for RTC_COMP_LSB_REG */ 652/* Bit definitions for RTC_COMP_LSB_REG */
653#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff 653#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
654#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 654#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
655 655
656/* Bit definitions for RTC_COMP_MSB_REG */ 656/* Bit definitions for RTC_COMP_MSB_REG */
657#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff 657#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
658#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 658#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
659 659
660/* Bit definitions for RTC_RES_PROG_REG */ 660/* Bit definitions for RTC_RES_PROG_REG */
661#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f 661#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
662#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 662#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
663 663
664/* Bit definitions for RTC_RESET_STATUS_REG */ 664/* Bit definitions for RTC_RESET_STATUS_REG */
665#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 665#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
666#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 666#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
667 667
668/* Registers for function BACKUP */ 668/* Registers for function BACKUP */
669#define PALMAS_BACKUP0 0x0 669#define PALMAS_BACKUP0 0x00
670#define PALMAS_BACKUP1 0x1 670#define PALMAS_BACKUP1 0x01
671#define PALMAS_BACKUP2 0x2 671#define PALMAS_BACKUP2 0x02
672#define PALMAS_BACKUP3 0x3 672#define PALMAS_BACKUP3 0x03
673#define PALMAS_BACKUP4 0x4 673#define PALMAS_BACKUP4 0x04
674#define PALMAS_BACKUP5 0x5 674#define PALMAS_BACKUP5 0x05
675#define PALMAS_BACKUP6 0x6 675#define PALMAS_BACKUP6 0x06
676#define PALMAS_BACKUP7 0x7 676#define PALMAS_BACKUP7 0x07
677 677
678/* Bit definitions for BACKUP0 */ 678/* Bit definitions for BACKUP0 */
679#define PALMAS_BACKUP0_BACKUP_MASK 0xff 679#define PALMAS_BACKUP0_BACKUP_MASK 0xFF
680#define PALMAS_BACKUP0_BACKUP_SHIFT 0 680#define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
681 681
682/* Bit definitions for BACKUP1 */ 682/* Bit definitions for BACKUP1 */
683#define PALMAS_BACKUP1_BACKUP_MASK 0xff 683#define PALMAS_BACKUP1_BACKUP_MASK 0xFF
684#define PALMAS_BACKUP1_BACKUP_SHIFT 0 684#define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
685 685
686/* Bit definitions for BACKUP2 */ 686/* Bit definitions for BACKUP2 */
687#define PALMAS_BACKUP2_BACKUP_MASK 0xff 687#define PALMAS_BACKUP2_BACKUP_MASK 0xFF
688#define PALMAS_BACKUP2_BACKUP_SHIFT 0 688#define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
689 689
690/* Bit definitions for BACKUP3 */ 690/* Bit definitions for BACKUP3 */
691#define PALMAS_BACKUP3_BACKUP_MASK 0xff 691#define PALMAS_BACKUP3_BACKUP_MASK 0xFF
692#define PALMAS_BACKUP3_BACKUP_SHIFT 0 692#define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
693 693
694/* Bit definitions for BACKUP4 */ 694/* Bit definitions for BACKUP4 */
695#define PALMAS_BACKUP4_BACKUP_MASK 0xff 695#define PALMAS_BACKUP4_BACKUP_MASK 0xFF
696#define PALMAS_BACKUP4_BACKUP_SHIFT 0 696#define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
697 697
698/* Bit definitions for BACKUP5 */ 698/* Bit definitions for BACKUP5 */
699#define PALMAS_BACKUP5_BACKUP_MASK 0xff 699#define PALMAS_BACKUP5_BACKUP_MASK 0xFF
700#define PALMAS_BACKUP5_BACKUP_SHIFT 0 700#define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
701 701
702/* Bit definitions for BACKUP6 */ 702/* Bit definitions for BACKUP6 */
703#define PALMAS_BACKUP6_BACKUP_MASK 0xff 703#define PALMAS_BACKUP6_BACKUP_MASK 0xFF
704#define PALMAS_BACKUP6_BACKUP_SHIFT 0 704#define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
705 705
706/* Bit definitions for BACKUP7 */ 706/* Bit definitions for BACKUP7 */
707#define PALMAS_BACKUP7_BACKUP_MASK 0xff 707#define PALMAS_BACKUP7_BACKUP_MASK 0xFF
708#define PALMAS_BACKUP7_BACKUP_SHIFT 0 708#define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
709 709
710/* Registers for function SMPS */ 710/* Registers for function SMPS */
711#define PALMAS_SMPS12_CTRL 0x0 711#define PALMAS_SMPS12_CTRL 0x00
712#define PALMAS_SMPS12_TSTEP 0x1 712#define PALMAS_SMPS12_TSTEP 0x01
713#define PALMAS_SMPS12_FORCE 0x2 713#define PALMAS_SMPS12_FORCE 0x02
714#define PALMAS_SMPS12_VOLTAGE 0x3 714#define PALMAS_SMPS12_VOLTAGE 0x03
715#define PALMAS_SMPS3_CTRL 0x4 715#define PALMAS_SMPS3_CTRL 0x04
716#define PALMAS_SMPS3_VOLTAGE 0x7 716#define PALMAS_SMPS3_VOLTAGE 0x07
717#define PALMAS_SMPS45_CTRL 0x8 717#define PALMAS_SMPS45_CTRL 0x08
718#define PALMAS_SMPS45_TSTEP 0x9 718#define PALMAS_SMPS45_TSTEP 0x09
719#define PALMAS_SMPS45_FORCE 0xA 719#define PALMAS_SMPS45_FORCE 0x0A
720#define PALMAS_SMPS45_VOLTAGE 0xB 720#define PALMAS_SMPS45_VOLTAGE 0x0B
721#define PALMAS_SMPS6_CTRL 0xC 721#define PALMAS_SMPS6_CTRL 0x0C
722#define PALMAS_SMPS6_TSTEP 0xD 722#define PALMAS_SMPS6_TSTEP 0x0D
723#define PALMAS_SMPS6_FORCE 0xE 723#define PALMAS_SMPS6_FORCE 0x0E
724#define PALMAS_SMPS6_VOLTAGE 0xF 724#define PALMAS_SMPS6_VOLTAGE 0x0F
725#define PALMAS_SMPS7_CTRL 0x10 725#define PALMAS_SMPS7_CTRL 0x10
726#define PALMAS_SMPS7_VOLTAGE 0x13 726#define PALMAS_SMPS7_VOLTAGE 0x13
727#define PALMAS_SMPS8_CTRL 0x14 727#define PALMAS_SMPS8_CTRL 0x14
@@ -744,303 +744,303 @@ enum usb_irq_events {
744 744
745/* Bit definitions for SMPS12_CTRL */ 745/* Bit definitions for SMPS12_CTRL */
746#define PALMAS_SMPS12_CTRL_WR_S 0x80 746#define PALMAS_SMPS12_CTRL_WR_S 0x80
747#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 747#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
748#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 748#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
749#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 749#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
750#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 750#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
751#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 751#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
752#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 752#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
753#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 753#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
754#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 754#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
755#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 755#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
756 756
757/* Bit definitions for SMPS12_TSTEP */ 757/* Bit definitions for SMPS12_TSTEP */
758#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 758#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
759#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 759#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
760 760
761/* Bit definitions for SMPS12_FORCE */ 761/* Bit definitions for SMPS12_FORCE */
762#define PALMAS_SMPS12_FORCE_CMD 0x80 762#define PALMAS_SMPS12_FORCE_CMD 0x80
763#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 763#define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
764#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f 764#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
765#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 765#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
766 766
767/* Bit definitions for SMPS12_VOLTAGE */ 767/* Bit definitions for SMPS12_VOLTAGE */
768#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 768#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
769#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 769#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
770#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f 770#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
771#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 771#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
772 772
773/* Bit definitions for SMPS3_CTRL */ 773/* Bit definitions for SMPS3_CTRL */
774#define PALMAS_SMPS3_CTRL_WR_S 0x80 774#define PALMAS_SMPS3_CTRL_WR_S 0x80
775#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 775#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
776#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 776#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
777#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 777#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
778#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 778#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
779#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 779#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
780#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 780#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
781#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 781#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
782 782
783/* Bit definitions for SMPS3_VOLTAGE */ 783/* Bit definitions for SMPS3_VOLTAGE */
784#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 784#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
785#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 785#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
786#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f 786#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
787#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 787#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
788 788
789/* Bit definitions for SMPS45_CTRL */ 789/* Bit definitions for SMPS45_CTRL */
790#define PALMAS_SMPS45_CTRL_WR_S 0x80 790#define PALMAS_SMPS45_CTRL_WR_S 0x80
791#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 791#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
792#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 792#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
793#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 793#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
794#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 794#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
795#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 795#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
796#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 796#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
797#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 797#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
798#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 798#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
799#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 799#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
800 800
801/* Bit definitions for SMPS45_TSTEP */ 801/* Bit definitions for SMPS45_TSTEP */
802#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 802#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
803#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 803#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
804 804
805/* Bit definitions for SMPS45_FORCE */ 805/* Bit definitions for SMPS45_FORCE */
806#define PALMAS_SMPS45_FORCE_CMD 0x80 806#define PALMAS_SMPS45_FORCE_CMD 0x80
807#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 807#define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
808#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f 808#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
809#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 809#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
810 810
811/* Bit definitions for SMPS45_VOLTAGE */ 811/* Bit definitions for SMPS45_VOLTAGE */
812#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 812#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
813#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 813#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
814#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f 814#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
815#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 815#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
816 816
817/* Bit definitions for SMPS6_CTRL */ 817/* Bit definitions for SMPS6_CTRL */
818#define PALMAS_SMPS6_CTRL_WR_S 0x80 818#define PALMAS_SMPS6_CTRL_WR_S 0x80
819#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 819#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
820#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 820#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
821#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 821#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
822#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 822#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
823#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 823#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
824#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 824#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
825#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 825#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
826#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 826#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
827#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 827#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
828 828
829/* Bit definitions for SMPS6_TSTEP */ 829/* Bit definitions for SMPS6_TSTEP */
830#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 830#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
831#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 831#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
832 832
833/* Bit definitions for SMPS6_FORCE */ 833/* Bit definitions for SMPS6_FORCE */
834#define PALMAS_SMPS6_FORCE_CMD 0x80 834#define PALMAS_SMPS6_FORCE_CMD 0x80
835#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 835#define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
836#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f 836#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
837#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 837#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
838 838
839/* Bit definitions for SMPS6_VOLTAGE */ 839/* Bit definitions for SMPS6_VOLTAGE */
840#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 840#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
841#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 841#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
842#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f 842#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
843#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 843#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
844 844
845/* Bit definitions for SMPS7_CTRL */ 845/* Bit definitions for SMPS7_CTRL */
846#define PALMAS_SMPS7_CTRL_WR_S 0x80 846#define PALMAS_SMPS7_CTRL_WR_S 0x80
847#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 847#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
848#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 848#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
849#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 849#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
850#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 850#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
851#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 851#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
852#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 852#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
853#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 853#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
854 854
855/* Bit definitions for SMPS7_VOLTAGE */ 855/* Bit definitions for SMPS7_VOLTAGE */
856#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 856#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
857#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 857#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
858#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f 858#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
859#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 859#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
860 860
861/* Bit definitions for SMPS8_CTRL */ 861/* Bit definitions for SMPS8_CTRL */
862#define PALMAS_SMPS8_CTRL_WR_S 0x80 862#define PALMAS_SMPS8_CTRL_WR_S 0x80
863#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 863#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
864#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 864#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
865#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 865#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
866#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 866#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
867#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 867#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
868#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 868#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
869#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 869#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
870#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 870#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
871#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 871#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
872 872
873/* Bit definitions for SMPS8_TSTEP */ 873/* Bit definitions for SMPS8_TSTEP */
874#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 874#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
875#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 875#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
876 876
877/* Bit definitions for SMPS8_FORCE */ 877/* Bit definitions for SMPS8_FORCE */
878#define PALMAS_SMPS8_FORCE_CMD 0x80 878#define PALMAS_SMPS8_FORCE_CMD 0x80
879#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 879#define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
880#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f 880#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
881#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 881#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
882 882
883/* Bit definitions for SMPS8_VOLTAGE */ 883/* Bit definitions for SMPS8_VOLTAGE */
884#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 884#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
885#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 885#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
886#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f 886#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
887#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 887#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
888 888
889/* Bit definitions for SMPS9_CTRL */ 889/* Bit definitions for SMPS9_CTRL */
890#define PALMAS_SMPS9_CTRL_WR_S 0x80 890#define PALMAS_SMPS9_CTRL_WR_S 0x80
891#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 891#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
892#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 892#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
893#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 893#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
894#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 894#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
895#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 895#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
896#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 896#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
897#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 897#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
898 898
899/* Bit definitions for SMPS9_VOLTAGE */ 899/* Bit definitions for SMPS9_VOLTAGE */
900#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 900#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
901#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 901#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
902#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f 902#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
903#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 903#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
904 904
905/* Bit definitions for SMPS10_CTRL */ 905/* Bit definitions for SMPS10_CTRL */
906#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 906#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
907#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 907#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
908#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f 908#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
909#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 909#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
910 910
911/* Bit definitions for SMPS10_STATUS */ 911/* Bit definitions for SMPS10_STATUS */
912#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f 912#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
913#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 913#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
914 914
915/* Bit definitions for SMPS_CTRL */ 915/* Bit definitions for SMPS_CTRL */
916#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 916#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
917#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 917#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
918#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 918#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
919#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 919#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
920#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 920#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
921#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 921#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
922#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 922#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
923#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 923#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
924 924
925/* Bit definitions for SMPS_PD_CTRL */ 925/* Bit definitions for SMPS_PD_CTRL */
926#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 926#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
927#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 927#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
928#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 928#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
929#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 929#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
930#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 930#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
931#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 931#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
932#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 932#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
933#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 933#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
934#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 934#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
935#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 935#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
936#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 936#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
937#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 937#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
938#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 938#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
939#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 939#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
940 940
941/* Bit definitions for SMPS_THERMAL_EN */ 941/* Bit definitions for SMPS_THERMAL_EN */
942#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 942#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
943#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 943#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
944#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 944#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
945#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 945#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
946#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 946#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
947#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 947#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
948#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 948#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
949#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 949#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
950#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 950#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
951#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 951#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
952 952
953/* Bit definitions for SMPS_THERMAL_STATUS */ 953/* Bit definitions for SMPS_THERMAL_STATUS */
954#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 954#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
955#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 955#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
956#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 956#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
957#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 957#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
958#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 958#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
959#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 959#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
960#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 960#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
961#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 961#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
962#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 962#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
963#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 963#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
964 964
965/* Bit definitions for SMPS_SHORT_STATUS */ 965/* Bit definitions for SMPS_SHORT_STATUS */
966#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 966#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
967#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 967#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
968#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 968#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
969#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 969#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
970#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 970#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
971#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 971#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
972#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 972#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
973#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 973#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
974#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 974#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
975#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 975#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
976#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 976#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
977#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 977#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
978#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 978#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
979#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 979#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
980#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 980#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
981#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 981#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
982 982
983/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 983/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
984#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 984#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
985#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 985#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
986#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 986#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
987#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 987#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
988#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 988#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
989#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 989#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
990#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 990#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
991#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 991#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
992#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 992#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
993#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 993#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
994#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 994#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
995#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 995#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
996#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 996#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
997#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 997#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
998 998
999/* Bit definitions for SMPS_POWERGOOD_MASK1 */ 999/* Bit definitions for SMPS_POWERGOOD_MASK1 */
1000#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 1000#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1001#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 1001#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1002#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 1002#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1003#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 1003#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1004#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 1004#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1005#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 1005#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1006#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 1006#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1007#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 1007#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1008#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 1008#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1009#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 1009#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1010#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 1010#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1011#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 1011#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1012#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 1012#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1013#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 1013#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1014#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 1014#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1015#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 1015#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1016 1016
1017/* Bit definitions for SMPS_POWERGOOD_MASK2 */ 1017/* Bit definitions for SMPS_POWERGOOD_MASK2 */
1018#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 1018#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1019#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 1019#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1020#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 1020#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1021#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 1021#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1022#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 1022#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1023#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 1023#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1024#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 1024#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1025#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 1025#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1026 1026
1027/* Registers for function LDO */ 1027/* Registers for function LDO */
1028#define PALMAS_LDO1_CTRL 0x0 1028#define PALMAS_LDO1_CTRL 0x00
1029#define PALMAS_LDO1_VOLTAGE 0x1 1029#define PALMAS_LDO1_VOLTAGE 0x01
1030#define PALMAS_LDO2_CTRL 0x2 1030#define PALMAS_LDO2_CTRL 0x02
1031#define PALMAS_LDO2_VOLTAGE 0x3 1031#define PALMAS_LDO2_VOLTAGE 0x03
1032#define PALMAS_LDO3_CTRL 0x4 1032#define PALMAS_LDO3_CTRL 0x04
1033#define PALMAS_LDO3_VOLTAGE 0x5 1033#define PALMAS_LDO3_VOLTAGE 0x05
1034#define PALMAS_LDO4_CTRL 0x6 1034#define PALMAS_LDO4_CTRL 0x06
1035#define PALMAS_LDO4_VOLTAGE 0x7 1035#define PALMAS_LDO4_VOLTAGE 0x07
1036#define PALMAS_LDO5_CTRL 0x8 1036#define PALMAS_LDO5_CTRL 0x08
1037#define PALMAS_LDO5_VOLTAGE 0x9 1037#define PALMAS_LDO5_VOLTAGE 0x09
1038#define PALMAS_LDO6_CTRL 0xA 1038#define PALMAS_LDO6_CTRL 0x0A
1039#define PALMAS_LDO6_VOLTAGE 0xB 1039#define PALMAS_LDO6_VOLTAGE 0x0B
1040#define PALMAS_LDO7_CTRL 0xC 1040#define PALMAS_LDO7_CTRL 0x0C
1041#define PALMAS_LDO7_VOLTAGE 0xD 1041#define PALMAS_LDO7_VOLTAGE 0x0D
1042#define PALMAS_LDO8_CTRL 0xE 1042#define PALMAS_LDO8_CTRL 0x0E
1043#define PALMAS_LDO8_VOLTAGE 0xF 1043#define PALMAS_LDO8_VOLTAGE 0x0F
1044#define PALMAS_LDO9_CTRL 0x10 1044#define PALMAS_LDO9_CTRL 0x10
1045#define PALMAS_LDO9_VOLTAGE 0x11 1045#define PALMAS_LDO9_VOLTAGE 0x11
1046#define PALMAS_LDOLN_CTRL 0x12 1046#define PALMAS_LDOLN_CTRL 0x12
@@ -1055,236 +1055,236 @@ enum usb_irq_events {
1055 1055
1056/* Bit definitions for LDO1_CTRL */ 1056/* Bit definitions for LDO1_CTRL */
1057#define PALMAS_LDO1_CTRL_WR_S 0x80 1057#define PALMAS_LDO1_CTRL_WR_S 0x80
1058#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 1058#define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1059#define PALMAS_LDO1_CTRL_STATUS 0x10 1059#define PALMAS_LDO1_CTRL_STATUS 0x10
1060#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 1060#define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1061#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1061#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1062#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 1062#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1063#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1063#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1064#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 1064#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1065 1065
1066/* Bit definitions for LDO1_VOLTAGE */ 1066/* Bit definitions for LDO1_VOLTAGE */
1067#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f 1067#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1068#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 1068#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1069 1069
1070/* Bit definitions for LDO2_CTRL */ 1070/* Bit definitions for LDO2_CTRL */
1071#define PALMAS_LDO2_CTRL_WR_S 0x80 1071#define PALMAS_LDO2_CTRL_WR_S 0x80
1072#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 1072#define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1073#define PALMAS_LDO2_CTRL_STATUS 0x10 1073#define PALMAS_LDO2_CTRL_STATUS 0x10
1074#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 1074#define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1075#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1075#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1076#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 1076#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1077#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1077#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1078#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 1078#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1079 1079
1080/* Bit definitions for LDO2_VOLTAGE */ 1080/* Bit definitions for LDO2_VOLTAGE */
1081#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f 1081#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1082#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 1082#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1083 1083
1084/* Bit definitions for LDO3_CTRL */ 1084/* Bit definitions for LDO3_CTRL */
1085#define PALMAS_LDO3_CTRL_WR_S 0x80 1085#define PALMAS_LDO3_CTRL_WR_S 0x80
1086#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 1086#define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1087#define PALMAS_LDO3_CTRL_STATUS 0x10 1087#define PALMAS_LDO3_CTRL_STATUS 0x10
1088#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 1088#define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1089#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1089#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1090#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 1090#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1091#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1091#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1092#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 1092#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1093 1093
1094/* Bit definitions for LDO3_VOLTAGE */ 1094/* Bit definitions for LDO3_VOLTAGE */
1095#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f 1095#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1096#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 1096#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1097 1097
1098/* Bit definitions for LDO4_CTRL */ 1098/* Bit definitions for LDO4_CTRL */
1099#define PALMAS_LDO4_CTRL_WR_S 0x80 1099#define PALMAS_LDO4_CTRL_WR_S 0x80
1100#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 1100#define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1101#define PALMAS_LDO4_CTRL_STATUS 0x10 1101#define PALMAS_LDO4_CTRL_STATUS 0x10
1102#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 1102#define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1103#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1103#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1104#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 1104#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1105#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1105#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1106#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 1106#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1107 1107
1108/* Bit definitions for LDO4_VOLTAGE */ 1108/* Bit definitions for LDO4_VOLTAGE */
1109#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f 1109#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1110#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 1110#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1111 1111
1112/* Bit definitions for LDO5_CTRL */ 1112/* Bit definitions for LDO5_CTRL */
1113#define PALMAS_LDO5_CTRL_WR_S 0x80 1113#define PALMAS_LDO5_CTRL_WR_S 0x80
1114#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 1114#define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1115#define PALMAS_LDO5_CTRL_STATUS 0x10 1115#define PALMAS_LDO5_CTRL_STATUS 0x10
1116#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 1116#define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1117#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1117#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1118#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 1118#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1119#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1119#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1120#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 1120#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1121 1121
1122/* Bit definitions for LDO5_VOLTAGE */ 1122/* Bit definitions for LDO5_VOLTAGE */
1123#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f 1123#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1124#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 1124#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1125 1125
1126/* Bit definitions for LDO6_CTRL */ 1126/* Bit definitions for LDO6_CTRL */
1127#define PALMAS_LDO6_CTRL_WR_S 0x80 1127#define PALMAS_LDO6_CTRL_WR_S 0x80
1128#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 1128#define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1129#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1129#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1130#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 1130#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1131#define PALMAS_LDO6_CTRL_STATUS 0x10 1131#define PALMAS_LDO6_CTRL_STATUS 0x10
1132#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 1132#define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1133#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1133#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1134#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 1134#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1135#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1135#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1136#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 1136#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1137 1137
1138/* Bit definitions for LDO6_VOLTAGE */ 1138/* Bit definitions for LDO6_VOLTAGE */
1139#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f 1139#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1140#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 1140#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1141 1141
1142/* Bit definitions for LDO7_CTRL */ 1142/* Bit definitions for LDO7_CTRL */
1143#define PALMAS_LDO7_CTRL_WR_S 0x80 1143#define PALMAS_LDO7_CTRL_WR_S 0x80
1144#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 1144#define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1145#define PALMAS_LDO7_CTRL_STATUS 0x10 1145#define PALMAS_LDO7_CTRL_STATUS 0x10
1146#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 1146#define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1147#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1147#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1148#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 1148#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1149#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1149#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1150#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 1150#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1151 1151
1152/* Bit definitions for LDO7_VOLTAGE */ 1152/* Bit definitions for LDO7_VOLTAGE */
1153#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f 1153#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1154#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 1154#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1155 1155
1156/* Bit definitions for LDO8_CTRL */ 1156/* Bit definitions for LDO8_CTRL */
1157#define PALMAS_LDO8_CTRL_WR_S 0x80 1157#define PALMAS_LDO8_CTRL_WR_S 0x80
1158#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 1158#define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1159#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1159#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1160#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 1160#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1161#define PALMAS_LDO8_CTRL_STATUS 0x10 1161#define PALMAS_LDO8_CTRL_STATUS 0x10
1162#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 1162#define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1163#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1163#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1164#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 1164#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1165#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1165#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1166#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 1166#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1167 1167
1168/* Bit definitions for LDO8_VOLTAGE */ 1168/* Bit definitions for LDO8_VOLTAGE */
1169#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f 1169#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1170#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 1170#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1171 1171
1172/* Bit definitions for LDO9_CTRL */ 1172/* Bit definitions for LDO9_CTRL */
1173#define PALMAS_LDO9_CTRL_WR_S 0x80 1173#define PALMAS_LDO9_CTRL_WR_S 0x80
1174#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 1174#define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1175#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1175#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1176#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 1176#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1177#define PALMAS_LDO9_CTRL_STATUS 0x10 1177#define PALMAS_LDO9_CTRL_STATUS 0x10
1178#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 1178#define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1179#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1179#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1180#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 1180#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1181#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1181#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1182#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 1182#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1183 1183
1184/* Bit definitions for LDO9_VOLTAGE */ 1184/* Bit definitions for LDO9_VOLTAGE */
1185#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f 1185#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1186#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 1186#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1187 1187
1188/* Bit definitions for LDOLN_CTRL */ 1188/* Bit definitions for LDOLN_CTRL */
1189#define PALMAS_LDOLN_CTRL_WR_S 0x80 1189#define PALMAS_LDOLN_CTRL_WR_S 0x80
1190#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 1190#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1191#define PALMAS_LDOLN_CTRL_STATUS 0x10 1191#define PALMAS_LDOLN_CTRL_STATUS 0x10
1192#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 1192#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1193#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1193#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1194#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 1194#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1195#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1195#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1196#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 1196#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1197 1197
1198/* Bit definitions for LDOLN_VOLTAGE */ 1198/* Bit definitions for LDOLN_VOLTAGE */
1199#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f 1199#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1200#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 1200#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1201 1201
1202/* Bit definitions for LDOUSB_CTRL */ 1202/* Bit definitions for LDOUSB_CTRL */
1203#define PALMAS_LDOUSB_CTRL_WR_S 0x80 1203#define PALMAS_LDOUSB_CTRL_WR_S 0x80
1204#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 1204#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1205#define PALMAS_LDOUSB_CTRL_STATUS 0x10 1205#define PALMAS_LDOUSB_CTRL_STATUS 0x10
1206#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 1206#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1207#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1207#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1208#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 1208#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1209#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1209#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1210#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 1210#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1211 1211
1212/* Bit definitions for LDOUSB_VOLTAGE */ 1212/* Bit definitions for LDOUSB_VOLTAGE */
1213#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f 1213#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1214#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 1214#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1215 1215
1216/* Bit definitions for LDO_CTRL */ 1216/* Bit definitions for LDO_CTRL */
1217#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1217#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1218#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 1218#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1219 1219
1220/* Bit definitions for LDO_PD_CTRL1 */ 1220/* Bit definitions for LDO_PD_CTRL1 */
1221#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1221#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1222#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 1222#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1223#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1223#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1224#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 1224#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1225#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1225#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1226#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 1226#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1227#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1227#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1228#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 1228#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1229#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1229#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1230#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 1230#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1231#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1231#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1232#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 1232#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1233#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1233#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1234#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 1234#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1235#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1235#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1236#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 1236#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1237 1237
1238/* Bit definitions for LDO_PD_CTRL2 */ 1238/* Bit definitions for LDO_PD_CTRL2 */
1239#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1239#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1240#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 1240#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1241#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1241#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1242#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 1242#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1243#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1243#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1244#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 1244#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1245 1245
1246/* Bit definitions for LDO_SHORT_STATUS1 */ 1246/* Bit definitions for LDO_SHORT_STATUS1 */
1247#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1247#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1248#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 1248#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1249#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1249#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1250#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 1250#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1251#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1251#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1252#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 1252#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1253#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1253#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1254#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 1254#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1255#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1255#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1256#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 1256#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1257#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1257#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1258#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 1258#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1259#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1259#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1260#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 1260#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1261#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1261#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1262#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 1262#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1263 1263
1264/* Bit definitions for LDO_SHORT_STATUS2 */ 1264/* Bit definitions for LDO_SHORT_STATUS2 */
1265#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1265#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1266#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 1266#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1267#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1267#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1268#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 1268#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1269#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1269#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1270#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 1270#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1271#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1271#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1272#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 1272#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1273 1273
1274/* Registers for function PMU_CONTROL */ 1274/* Registers for function PMU_CONTROL */
1275#define PALMAS_DEV_CTRL 0x0 1275#define PALMAS_DEV_CTRL 0x00
1276#define PALMAS_POWER_CTRL 0x1 1276#define PALMAS_POWER_CTRL 0x01
1277#define PALMAS_VSYS_LO 0x2 1277#define PALMAS_VSYS_LO 0x02
1278#define PALMAS_VSYS_MON 0x3 1278#define PALMAS_VSYS_MON 0x03
1279#define PALMAS_VBAT_MON 0x4 1279#define PALMAS_VBAT_MON 0x04
1280#define PALMAS_WATCHDOG 0x5 1280#define PALMAS_WATCHDOG 0x05
1281#define PALMAS_BOOT_STATUS 0x6 1281#define PALMAS_BOOT_STATUS 0x06
1282#define PALMAS_BATTERY_BOUNCE 0x7 1282#define PALMAS_BATTERY_BOUNCE 0x07
1283#define PALMAS_BACKUP_BATTERY_CTRL 0x8 1283#define PALMAS_BACKUP_BATTERY_CTRL 0x08
1284#define PALMAS_LONG_PRESS_KEY 0x9 1284#define PALMAS_LONG_PRESS_KEY 0x09
1285#define PALMAS_OSC_THERM_CTRL 0xA 1285#define PALMAS_OSC_THERM_CTRL 0x0A
1286#define PALMAS_BATDEBOUNCING 0xB 1286#define PALMAS_BATDEBOUNCING 0x0B
1287#define PALMAS_SWOFF_HWRST 0xF 1287#define PALMAS_SWOFF_HWRST 0x0F
1288#define PALMAS_SWOFF_COLDRST 0x10 1288#define PALMAS_SWOFF_COLDRST 0x10
1289#define PALMAS_SWOFF_STATUS 0x11 1289#define PALMAS_SWOFF_STATUS 0x11
1290#define PALMAS_PMU_CONFIG 0x12 1290#define PALMAS_PMU_CONFIG 0x12
@@ -1296,668 +1296,668 @@ enum usb_irq_events {
1296 1296
1297/* Bit definitions for DEV_CTRL */ 1297/* Bit definitions for DEV_CTRL */
1298#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1298#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1299#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 1299#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1300#define PALMAS_DEV_CTRL_SW_RST 0x02 1300#define PALMAS_DEV_CTRL_SW_RST 0x02
1301#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 1301#define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1302#define PALMAS_DEV_CTRL_DEV_ON 0x01 1302#define PALMAS_DEV_CTRL_DEV_ON 0x01
1303#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 1303#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1304 1304
1305/* Bit definitions for POWER_CTRL */ 1305/* Bit definitions for POWER_CTRL */
1306#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1306#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1307#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 1307#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1308#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1308#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1309#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 1309#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1310#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1310#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1311#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 1311#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1312 1312
1313/* Bit definitions for VSYS_LO */ 1313/* Bit definitions for VSYS_LO */
1314#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f 1314#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1315#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 1315#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1316 1316
1317/* Bit definitions for VSYS_MON */ 1317/* Bit definitions for VSYS_MON */
1318#define PALMAS_VSYS_MON_ENABLE 0x80 1318#define PALMAS_VSYS_MON_ENABLE 0x80
1319#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 1319#define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1320#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f 1320#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1321#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 1321#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1322 1322
1323/* Bit definitions for VBAT_MON */ 1323/* Bit definitions for VBAT_MON */
1324#define PALMAS_VBAT_MON_ENABLE 0x80 1324#define PALMAS_VBAT_MON_ENABLE 0x80
1325#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 1325#define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1326#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f 1326#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1327#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 1327#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1328 1328
1329/* Bit definitions for WATCHDOG */ 1329/* Bit definitions for WATCHDOG */
1330#define PALMAS_WATCHDOG_LOCK 0x20 1330#define PALMAS_WATCHDOG_LOCK 0x20
1331#define PALMAS_WATCHDOG_LOCK_SHIFT 5 1331#define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1332#define PALMAS_WATCHDOG_ENABLE 0x10 1332#define PALMAS_WATCHDOG_ENABLE 0x10
1333#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 1333#define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1334#define PALMAS_WATCHDOG_MODE 0x08 1334#define PALMAS_WATCHDOG_MODE 0x08
1335#define PALMAS_WATCHDOG_MODE_SHIFT 3 1335#define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1336#define PALMAS_WATCHDOG_TIMER_MASK 0x07 1336#define PALMAS_WATCHDOG_TIMER_MASK 0x07
1337#define PALMAS_WATCHDOG_TIMER_SHIFT 0 1337#define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1338 1338
1339/* Bit definitions for BOOT_STATUS */ 1339/* Bit definitions for BOOT_STATUS */
1340#define PALMAS_BOOT_STATUS_BOOT1 0x02 1340#define PALMAS_BOOT_STATUS_BOOT1 0x02
1341#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 1341#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1342#define PALMAS_BOOT_STATUS_BOOT0 0x01 1342#define PALMAS_BOOT_STATUS_BOOT0 0x01
1343#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 1343#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1344 1344
1345/* Bit definitions for BATTERY_BOUNCE */ 1345/* Bit definitions for BATTERY_BOUNCE */
1346#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f 1346#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1347#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 1347#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1348 1348
1349/* Bit definitions for BACKUP_BATTERY_CTRL */ 1349/* Bit definitions for BACKUP_BATTERY_CTRL */
1350#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1350#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1351#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 1351#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1352#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1352#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1353#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 1353#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1354#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1354#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1355#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 1355#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1356#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1356#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1357#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 1357#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1358#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1358#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1359#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 1359#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1360#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1360#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1361#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 1361#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1362#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1362#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1363#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 1363#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1364 1364
1365/* Bit definitions for LONG_PRESS_KEY */ 1365/* Bit definitions for LONG_PRESS_KEY */
1366#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1366#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1367#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 1367#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1368#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1368#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1369#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 1369#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1370#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1370#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1371#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 1371#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1372#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1372#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1373#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 1373#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1374 1374
1375/* Bit definitions for OSC_THERM_CTRL */ 1375/* Bit definitions for OSC_THERM_CTRL */
1376#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1376#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1377#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 1377#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1378#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1378#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1379#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 1379#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1380#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1380#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1381#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 1381#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1382#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1382#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1383#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 1383#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1384#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1384#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1385#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 1385#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1386#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1386#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1387#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 1387#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1388#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1388#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1389#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 1389#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1390 1390
1391/* Bit definitions for BATDEBOUNCING */ 1391/* Bit definitions for BATDEBOUNCING */
1392#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1392#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1393#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 1393#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1394#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1394#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1395#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 1395#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1396#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1396#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1397#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 1397#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1398 1398
1399/* Bit definitions for SWOFF_HWRST */ 1399/* Bit definitions for SWOFF_HWRST */
1400#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1400#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1401#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 1401#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1402#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1402#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1403#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 1403#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1404#define PALMAS_SWOFF_HWRST_WTD 0x20 1404#define PALMAS_SWOFF_HWRST_WTD 0x20
1405#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 1405#define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1406#define PALMAS_SWOFF_HWRST_TSHUT 0x10 1406#define PALMAS_SWOFF_HWRST_TSHUT 0x10
1407#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 1407#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1408#define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1408#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1409#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 1409#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1410#define PALMAS_SWOFF_HWRST_SW_RST 0x04 1410#define PALMAS_SWOFF_HWRST_SW_RST 0x04
1411#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 1411#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1412#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1412#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1413#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 1413#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1414#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1414#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1415#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 1415#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1416 1416
1417/* Bit definitions for SWOFF_COLDRST */ 1417/* Bit definitions for SWOFF_COLDRST */
1418#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1418#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1419#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 1419#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1420#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1420#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1421#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 1421#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1422#define PALMAS_SWOFF_COLDRST_WTD 0x20 1422#define PALMAS_SWOFF_COLDRST_WTD 0x20
1423#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 1423#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1424#define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1424#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1425#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 1425#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1426#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1426#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1427#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 1427#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1428#define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1428#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1429#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 1429#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1430#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1430#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1431#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 1431#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1432#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1432#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1433#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 1433#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1434 1434
1435/* Bit definitions for SWOFF_STATUS */ 1435/* Bit definitions for SWOFF_STATUS */
1436#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1436#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1437#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 1437#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1438#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1438#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1439#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 1439#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1440#define PALMAS_SWOFF_STATUS_WTD 0x20 1440#define PALMAS_SWOFF_STATUS_WTD 0x20
1441#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 1441#define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1442#define PALMAS_SWOFF_STATUS_TSHUT 0x10 1442#define PALMAS_SWOFF_STATUS_TSHUT 0x10
1443#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 1443#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1444#define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1444#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1445#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 1445#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1446#define PALMAS_SWOFF_STATUS_SW_RST 0x04 1446#define PALMAS_SWOFF_STATUS_SW_RST 0x04
1447#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 1447#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1448#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1448#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1449#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 1449#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1450#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1450#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1451#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 1451#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1452 1452
1453/* Bit definitions for PMU_CONFIG */ 1453/* Bit definitions for PMU_CONFIG */
1454#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1454#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1455#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 1455#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1456#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1456#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1457#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 1457#define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1458#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1458#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1459#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 1459#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1460#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1460#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1461#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 1461#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1462#define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1462#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1463#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 1463#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1464 1464
1465/* Bit definitions for SPARE */ 1465/* Bit definitions for SPARE */
1466#define PALMAS_SPARE_SPARE_MASK 0xf8 1466#define PALMAS_SPARE_SPARE_MASK 0xf8
1467#define PALMAS_SPARE_SPARE_SHIFT 3 1467#define PALMAS_SPARE_SPARE_SHIFT 0x03
1468#define PALMAS_SPARE_REGEN3_OD 0x04 1468#define PALMAS_SPARE_REGEN3_OD 0x04
1469#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 1469#define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1470#define PALMAS_SPARE_REGEN2_OD 0x02 1470#define PALMAS_SPARE_REGEN2_OD 0x02
1471#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 1471#define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1472#define PALMAS_SPARE_REGEN1_OD 0x01 1472#define PALMAS_SPARE_REGEN1_OD 0x01
1473#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 1473#define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1474 1474
1475/* Bit definitions for PMU_SECONDARY_INT */ 1475/* Bit definitions for PMU_SECONDARY_INT */
1476#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1476#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1477#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 1477#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1478#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1478#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1479#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 1479#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1480#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1480#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1481#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 1481#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1482#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1482#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1483#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 1483#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1484#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1484#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1485#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 1485#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1486#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1486#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1487#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 1487#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1488#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1488#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1489#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 1489#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1490#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1490#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1491#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 1491#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1492 1492
1493/* Bit definitions for SW_REVISION */ 1493/* Bit definitions for SW_REVISION */
1494#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff 1494#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1495#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 1495#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1496 1496
1497/* Bit definitions for EXT_CHRG_CTRL */ 1497/* Bit definitions for EXT_CHRG_CTRL */
1498#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1498#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1499#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 1499#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1500#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1500#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1501#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 1501#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1502#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1502#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1503#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 1503#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1504#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1504#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1505#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 1505#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1506#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1506#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1507#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 1507#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1508#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1508#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1509#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 1509#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1510 1510
1511/* Bit definitions for PMU_SECONDARY_INT2 */ 1511/* Bit definitions for PMU_SECONDARY_INT2 */
1512#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1512#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1513#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 1513#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1514#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1514#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1515#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 1515#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1516#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1516#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1517#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 1517#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1518#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1518#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1519#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 1519#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1520 1520
1521/* Registers for function RESOURCE */ 1521/* Registers for function RESOURCE */
1522#define PALMAS_CLK32KG_CTRL 0x0 1522#define PALMAS_CLK32KG_CTRL 0x00
1523#define PALMAS_CLK32KGAUDIO_CTRL 0x1 1523#define PALMAS_CLK32KGAUDIO_CTRL 0x01
1524#define PALMAS_REGEN1_CTRL 0x2 1524#define PALMAS_REGEN1_CTRL 0x02
1525#define PALMAS_REGEN2_CTRL 0x3 1525#define PALMAS_REGEN2_CTRL 0x03
1526#define PALMAS_SYSEN1_CTRL 0x4 1526#define PALMAS_SYSEN1_CTRL 0x04
1527#define PALMAS_SYSEN2_CTRL 0x5 1527#define PALMAS_SYSEN2_CTRL 0x05
1528#define PALMAS_NSLEEP_RES_ASSIGN 0x6 1528#define PALMAS_NSLEEP_RES_ASSIGN 0x06
1529#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 1529#define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1530#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 1530#define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1531#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 1531#define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1532#define PALMAS_ENABLE1_RES_ASSIGN 0xA 1532#define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1533#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB 1533#define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1534#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC 1534#define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1535#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD 1535#define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1536#define PALMAS_ENABLE2_RES_ASSIGN 0xE 1536#define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1537#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF 1537#define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1538#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1538#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1539#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1539#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1540#define PALMAS_REGEN3_CTRL 0x12 1540#define PALMAS_REGEN3_CTRL 0x12
1541 1541
1542/* Bit definitions for CLK32KG_CTRL */ 1542/* Bit definitions for CLK32KG_CTRL */
1543#define PALMAS_CLK32KG_CTRL_STATUS 0x10 1543#define PALMAS_CLK32KG_CTRL_STATUS 0x10
1544#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 1544#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1545#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1545#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1546#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 1546#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1547#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1547#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1548#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 1548#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1549 1549
1550/* Bit definitions for CLK32KGAUDIO_CTRL */ 1550/* Bit definitions for CLK32KGAUDIO_CTRL */
1551#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1551#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1552#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 1552#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1553#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1553#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1554#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 1554#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1555#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1555#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1556#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 1556#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1557#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1557#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1558#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 1558#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1559 1559
1560/* Bit definitions for REGEN1_CTRL */ 1560/* Bit definitions for REGEN1_CTRL */
1561#define PALMAS_REGEN1_CTRL_STATUS 0x10 1561#define PALMAS_REGEN1_CTRL_STATUS 0x10
1562#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 1562#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1563#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1563#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1564#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 1564#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1565#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1565#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1566#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 1566#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1567 1567
1568/* Bit definitions for REGEN2_CTRL */ 1568/* Bit definitions for REGEN2_CTRL */
1569#define PALMAS_REGEN2_CTRL_STATUS 0x10 1569#define PALMAS_REGEN2_CTRL_STATUS 0x10
1570#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 1570#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1571#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1571#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1572#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 1572#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1573#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1573#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1574#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 1574#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1575 1575
1576/* Bit definitions for SYSEN1_CTRL */ 1576/* Bit definitions for SYSEN1_CTRL */
1577#define PALMAS_SYSEN1_CTRL_STATUS 0x10 1577#define PALMAS_SYSEN1_CTRL_STATUS 0x10
1578#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 1578#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1579#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1579#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1580#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 1580#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1581#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1581#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1582#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 1582#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1583 1583
1584/* Bit definitions for SYSEN2_CTRL */ 1584/* Bit definitions for SYSEN2_CTRL */
1585#define PALMAS_SYSEN2_CTRL_STATUS 0x10 1585#define PALMAS_SYSEN2_CTRL_STATUS 0x10
1586#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 1586#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1587#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1587#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1588#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 1588#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1589#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1589#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1590#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 1590#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1591 1591
1592/* Bit definitions for NSLEEP_RES_ASSIGN */ 1592/* Bit definitions for NSLEEP_RES_ASSIGN */
1593#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1593#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1594#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 1594#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1595#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1595#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1596#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1596#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1597#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1597#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1598#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 1598#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1599#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1599#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1600#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 1600#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1601#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1601#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1602#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 1602#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1603#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1603#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1604#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 1604#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1605#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1605#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1606#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 1606#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1607 1607
1608/* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1608/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1609#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1609#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1610#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 1610#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1611#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1611#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1612#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 1612#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1613#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1613#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1614#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 1614#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1615#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1615#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1616#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 1616#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1617#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1617#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1618#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 1618#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1619#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1619#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1620#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 1620#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1621#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1621#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1622#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 1622#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1623#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1623#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1624#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 1624#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1625 1625
1626/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1626/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1627#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1627#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1628#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 1628#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1629#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1629#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1630#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 1630#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1631#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1631#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1632#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 1632#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1633#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1633#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1634#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 1634#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1635#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1635#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1636#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 1636#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1637#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1637#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1638#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 1638#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1639#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1639#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1640#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 1640#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1641#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1641#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1642#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 1642#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1643 1643
1644/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1644/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1645#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1645#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1646#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 1646#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1647#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1647#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1648#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 1648#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1649#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1649#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1650#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 1650#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1651 1651
1652/* Bit definitions for ENABLE1_RES_ASSIGN */ 1652/* Bit definitions for ENABLE1_RES_ASSIGN */
1653#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1653#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1654#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 1654#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1655#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1655#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1656#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1656#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1657#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1657#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1658#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 1658#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1659#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1659#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1660#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 1660#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1661#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1661#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1662#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 1662#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1663#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1663#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1664#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 1664#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1665#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1665#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1666#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 1666#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1667 1667
1668/* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1668/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1669#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1669#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1670#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 1670#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1671#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1671#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1672#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 1672#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1673#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1673#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1674#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 1674#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1675#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1675#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1676#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 1676#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1677#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1677#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1678#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 1678#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1679#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1679#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1680#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 1680#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1681#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1681#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1682#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 1682#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1683#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1683#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1684#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 1684#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1685 1685
1686/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1686/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1687#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1687#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1688#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 1688#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1689#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1689#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1690#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 1690#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1691#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1691#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1692#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 1692#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1693#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1693#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1694#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 1694#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1695#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1695#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1696#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 1696#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1697#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1697#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1698#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 1698#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1699#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1699#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1700#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 1700#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1701#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1701#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1702#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 1702#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1703 1703
1704/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1704/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1705#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1705#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1706#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 1706#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1707#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1707#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1708#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 1708#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1709#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1709#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1710#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 1710#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1711 1711
1712/* Bit definitions for ENABLE2_RES_ASSIGN */ 1712/* Bit definitions for ENABLE2_RES_ASSIGN */
1713#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1713#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1714#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 1714#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1715#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1715#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1716#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1716#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1717#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1717#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1718#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 1718#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1719#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1719#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1720#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 1720#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1721#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1721#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1722#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 1722#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1723#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1723#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1724#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 1724#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1725#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1725#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1726#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 1726#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1727 1727
1728/* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1728/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1729#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1729#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1730#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 1730#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1731#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1731#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1732#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 1732#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1733#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1733#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1734#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 1734#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1735#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1735#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1736#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 1736#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1737#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1737#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1738#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 1738#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1739#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1739#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1740#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 1740#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1741#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1741#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1742#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 1742#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1743#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1743#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1744#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 1744#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1745 1745
1746/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1746/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1747#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1747#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1748#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 1748#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1749#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1749#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1750#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 1750#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1751#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1751#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1752#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 1752#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1753#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1753#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1754#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 1754#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1755#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1755#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1756#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 1756#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1757#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1757#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1758#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 1758#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1759#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1759#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1760#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 1760#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1761#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1761#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1762#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 1762#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1763 1763
1764/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1764/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1765#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1765#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1766#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 1766#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1767#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1767#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1768#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 1768#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1769#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1769#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1770#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 1770#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1771 1771
1772/* Bit definitions for REGEN3_CTRL */ 1772/* Bit definitions for REGEN3_CTRL */
1773#define PALMAS_REGEN3_CTRL_STATUS 0x10 1773#define PALMAS_REGEN3_CTRL_STATUS 0x10
1774#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 1774#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1775#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1775#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1776#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 1776#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1777#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1777#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1778#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1778#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1779 1779
1780/* Registers for function PAD_CONTROL */ 1780/* Registers for function PAD_CONTROL */
1781#define PALMAS_OD_OUTPUT_CTRL2 0x2 1781#define PALMAS_OD_OUTPUT_CTRL2 0x02
1782#define PALMAS_POLARITY_CTRL2 0x3 1782#define PALMAS_POLARITY_CTRL2 0x03
1783#define PALMAS_PU_PD_INPUT_CTRL1 0x4 1783#define PALMAS_PU_PD_INPUT_CTRL1 0x04
1784#define PALMAS_PU_PD_INPUT_CTRL2 0x5 1784#define PALMAS_PU_PD_INPUT_CTRL2 0x05
1785#define PALMAS_PU_PD_INPUT_CTRL3 0x6 1785#define PALMAS_PU_PD_INPUT_CTRL3 0x06
1786#define PALMAS_PU_PD_INPUT_CTRL5 0x7 1786#define PALMAS_PU_PD_INPUT_CTRL5 0x07
1787#define PALMAS_OD_OUTPUT_CTRL 0x8 1787#define PALMAS_OD_OUTPUT_CTRL 0x08
1788#define PALMAS_POLARITY_CTRL 0x9 1788#define PALMAS_POLARITY_CTRL 0x09
1789#define PALMAS_PRIMARY_SECONDARY_PAD1 0xA 1789#define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1790#define PALMAS_PRIMARY_SECONDARY_PAD2 0xB 1790#define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1791#define PALMAS_I2C_SPI 0xC 1791#define PALMAS_I2C_SPI 0x0C
1792#define PALMAS_PU_PD_INPUT_CTRL4 0xD 1792#define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1793#define PALMAS_PRIMARY_SECONDARY_PAD3 0xE 1793#define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1794#define PALMAS_PRIMARY_SECONDARY_PAD4 0xF 1794#define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1795 1795
1796/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1796/* Bit definitions for PU_PD_INPUT_CTRL1 */
1797#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1797#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1798#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 1798#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1799#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1799#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1800#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 1800#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1801#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1801#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1802#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 1802#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1803#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1803#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1804#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 1804#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1805#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1805#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1806#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 1806#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1807 1807
1808/* Bit definitions for PU_PD_INPUT_CTRL2 */ 1808/* Bit definitions for PU_PD_INPUT_CTRL2 */
1809#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1809#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1810#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 1810#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1811#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1811#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1812#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 1812#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1813#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1813#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1814#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 1814#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1815#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1815#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1816#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 1816#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1817#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1817#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1818#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 1818#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1819#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1819#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1820#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 1820#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1821 1821
1822/* Bit definitions for PU_PD_INPUT_CTRL3 */ 1822/* Bit definitions for PU_PD_INPUT_CTRL3 */
1823#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1823#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1824#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 1824#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1825#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1825#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1826#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 1826#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1827#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1827#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1828#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 1828#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1829#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1829#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1830#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 1830#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1831 1831
1832/* Bit definitions for OD_OUTPUT_CTRL */ 1832/* Bit definitions for OD_OUTPUT_CTRL */
1833#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1833#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1834#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 1834#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
1835#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1835#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1836#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 1836#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
1837#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1837#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1838#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 1838#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
1839#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1839#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1840#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 1840#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
1841 1841
1842/* Bit definitions for POLARITY_CTRL */ 1842/* Bit definitions for POLARITY_CTRL */
1843#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1843#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1844#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 1844#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
1845#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1845#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1846#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 1846#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
1847#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1847#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1848#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 1848#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
1849#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1849#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1850#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 1850#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
1851#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1851#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1852#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 1852#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
1853#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1853#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1854#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 1854#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
1855#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1855#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1856#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 1856#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
1857#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1857#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1858#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 1858#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
1859 1859
1860/* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1860/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1861#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1861#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1862#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 1862#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
1863#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1863#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1864#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 1864#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
1865#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1865#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1866#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 1866#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
1867#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1867#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1868#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 1868#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
1869#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1869#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1870#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 1870#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
1871#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 1871#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1872#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 1872#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
1873 1873
1874/* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 1874/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1875#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 1875#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1876#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 1876#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
1877#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 1877#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1878#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 1878#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
1879#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 1879#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1880#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 1880#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
1881#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 1881#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1882#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 1882#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
1883 1883
1884/* Bit definitions for I2C_SPI */ 1884/* Bit definitions for I2C_SPI */
1885#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 1885#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1886#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 1886#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
1887#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 1887#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1888#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 1888#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
1889#define PALMAS_I2C_SPI_ID_I2C2 0x20 1889#define PALMAS_I2C_SPI_ID_I2C2 0x20
1890#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 1890#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
1891#define PALMAS_I2C_SPI_I2C_SPI 0x10 1891#define PALMAS_I2C_SPI_I2C_SPI 0x10
1892#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 1892#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
1893#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f 1893#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
1894#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 1894#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
1895 1895
1896/* Bit definitions for PU_PD_INPUT_CTRL4 */ 1896/* Bit definitions for PU_PD_INPUT_CTRL4 */
1897#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 1897#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1898#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 1898#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
1899#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 1899#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1900#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 1900#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
1901#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 1901#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1902#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 1902#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
1903#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 1903#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1904#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 1904#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
1905 1905
1906/* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 1906/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1907#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 1907#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1908#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 1908#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
1909#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 1909#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1910#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 1910#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
1911 1911
1912/* Registers for function LED_PWM */ 1912/* Registers for function LED_PWM */
1913#define PALMAS_LED_PERIOD_CTRL 0x0 1913#define PALMAS_LED_PERIOD_CTRL 0x00
1914#define PALMAS_LED_CTRL 0x1 1914#define PALMAS_LED_CTRL 0x01
1915#define PALMAS_PWM_CTRL1 0x2 1915#define PALMAS_PWM_CTRL1 0x02
1916#define PALMAS_PWM_CTRL2 0x3 1916#define PALMAS_PWM_CTRL2 0x03
1917 1917
1918/* Bit definitions for LED_PERIOD_CTRL */ 1918/* Bit definitions for LED_PERIOD_CTRL */
1919#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 1919#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1920#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 1920#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
1921#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 1921#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1922#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 1922#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
1923 1923
1924/* Bit definitions for LED_CTRL */ 1924/* Bit definitions for LED_CTRL */
1925#define PALMAS_LED_CTRL_LED_2_SEQ 0x20 1925#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1926#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 1926#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
1927#define PALMAS_LED_CTRL_LED_1_SEQ 0x10 1927#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1928#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 1928#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
1929#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 1929#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1930#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 1930#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
1931#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 1931#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1932#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 1932#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
1933 1933
1934/* Bit definitions for PWM_CTRL1 */ 1934/* Bit definitions for PWM_CTRL1 */
1935#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 1935#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1936#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 1936#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
1937#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 1937#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1938#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 1938#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
1939 1939
1940/* Bit definitions for PWM_CTRL2 */ 1940/* Bit definitions for PWM_CTRL2 */
1941#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff 1941#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
1942#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 1942#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
1943 1943
1944/* Registers for function INTERRUPT */ 1944/* Registers for function INTERRUPT */
1945#define PALMAS_INT1_STATUS 0x0 1945#define PALMAS_INT1_STATUS 0x00
1946#define PALMAS_INT1_MASK 0x1 1946#define PALMAS_INT1_MASK 0x01
1947#define PALMAS_INT1_LINE_STATE 0x2 1947#define PALMAS_INT1_LINE_STATE 0x02
1948#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 1948#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
1949#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 1949#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
1950#define PALMAS_INT2_STATUS 0x5 1950#define PALMAS_INT2_STATUS 0x05
1951#define PALMAS_INT2_MASK 0x6 1951#define PALMAS_INT2_MASK 0x06
1952#define PALMAS_INT2_LINE_STATE 0x7 1952#define PALMAS_INT2_LINE_STATE 0x07
1953#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 1953#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
1954#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 1954#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
1955#define PALMAS_INT3_STATUS 0xA 1955#define PALMAS_INT3_STATUS 0x0A
1956#define PALMAS_INT3_MASK 0xB 1956#define PALMAS_INT3_MASK 0x0B
1957#define PALMAS_INT3_LINE_STATE 0xC 1957#define PALMAS_INT3_LINE_STATE 0x0C
1958#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD 1958#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
1959#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE 1959#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
1960#define PALMAS_INT4_STATUS 0xF 1960#define PALMAS_INT4_STATUS 0x0F
1961#define PALMAS_INT4_MASK 0x10 1961#define PALMAS_INT4_MASK 0x10
1962#define PALMAS_INT4_LINE_STATE 0x11 1962#define PALMAS_INT4_LINE_STATE 0x11
1963#define PALMAS_INT4_EDGE_DETECT1 0x12 1963#define PALMAS_INT4_EDGE_DETECT1 0x12
@@ -1966,276 +1966,276 @@ enum usb_irq_events {
1966 1966
1967/* Bit definitions for INT1_STATUS */ 1967/* Bit definitions for INT1_STATUS */
1968#define PALMAS_INT1_STATUS_VBAT_MON 0x80 1968#define PALMAS_INT1_STATUS_VBAT_MON 0x80
1969#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 1969#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
1970#define PALMAS_INT1_STATUS_VSYS_MON 0x40 1970#define PALMAS_INT1_STATUS_VSYS_MON 0x40
1971#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 1971#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
1972#define PALMAS_INT1_STATUS_HOTDIE 0x20 1972#define PALMAS_INT1_STATUS_HOTDIE 0x20
1973#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 1973#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
1974#define PALMAS_INT1_STATUS_PWRDOWN 0x10 1974#define PALMAS_INT1_STATUS_PWRDOWN 0x10
1975#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 1975#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
1976#define PALMAS_INT1_STATUS_RPWRON 0x08 1976#define PALMAS_INT1_STATUS_RPWRON 0x08
1977#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 1977#define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
1978#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 1978#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1979#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 1979#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
1980#define PALMAS_INT1_STATUS_PWRON 0x02 1980#define PALMAS_INT1_STATUS_PWRON 0x02
1981#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 1981#define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
1982#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 1982#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1983#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 1983#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
1984 1984
1985/* Bit definitions for INT1_MASK */ 1985/* Bit definitions for INT1_MASK */
1986#define PALMAS_INT1_MASK_VBAT_MON 0x80 1986#define PALMAS_INT1_MASK_VBAT_MON 0x80
1987#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 1987#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
1988#define PALMAS_INT1_MASK_VSYS_MON 0x40 1988#define PALMAS_INT1_MASK_VSYS_MON 0x40
1989#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 1989#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
1990#define PALMAS_INT1_MASK_HOTDIE 0x20 1990#define PALMAS_INT1_MASK_HOTDIE 0x20
1991#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 1991#define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
1992#define PALMAS_INT1_MASK_PWRDOWN 0x10 1992#define PALMAS_INT1_MASK_PWRDOWN 0x10
1993#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 1993#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
1994#define PALMAS_INT1_MASK_RPWRON 0x08 1994#define PALMAS_INT1_MASK_RPWRON 0x08
1995#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 1995#define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
1996#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 1996#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1997#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 1997#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
1998#define PALMAS_INT1_MASK_PWRON 0x02 1998#define PALMAS_INT1_MASK_PWRON 0x02
1999#define PALMAS_INT1_MASK_PWRON_SHIFT 1 1999#define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2000#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 2000#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2001#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 2001#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2002 2002
2003/* Bit definitions for INT1_LINE_STATE */ 2003/* Bit definitions for INT1_LINE_STATE */
2004#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 2004#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2005#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 2005#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2006#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 2006#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2007#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 2007#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2008#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 2008#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2009#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 2009#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2010#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 2010#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2011#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 2011#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2012#define PALMAS_INT1_LINE_STATE_RPWRON 0x08 2012#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2013#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 2013#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2014#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 2014#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2015#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 2015#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2016#define PALMAS_INT1_LINE_STATE_PWRON 0x02 2016#define PALMAS_INT1_LINE_STATE_PWRON 0x02
2017#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 2017#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2018#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 2018#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2019#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 2019#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2020 2020
2021/* Bit definitions for INT2_STATUS */ 2021/* Bit definitions for INT2_STATUS */
2022#define PALMAS_INT2_STATUS_VAC_ACOK 0x80 2022#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2023#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 2023#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2024#define PALMAS_INT2_STATUS_SHORT 0x40 2024#define PALMAS_INT2_STATUS_SHORT 0x40
2025#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 2025#define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2026#define PALMAS_INT2_STATUS_FBI_BB 0x20 2026#define PALMAS_INT2_STATUS_FBI_BB 0x20
2027#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 2027#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2028#define PALMAS_INT2_STATUS_RESET_IN 0x10 2028#define PALMAS_INT2_STATUS_RESET_IN 0x10
2029#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 2029#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2030#define PALMAS_INT2_STATUS_BATREMOVAL 0x08 2030#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2031#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 2031#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2032#define PALMAS_INT2_STATUS_WDT 0x04 2032#define PALMAS_INT2_STATUS_WDT 0x04
2033#define PALMAS_INT2_STATUS_WDT_SHIFT 2 2033#define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2034#define PALMAS_INT2_STATUS_RTC_TIMER 0x02 2034#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2035#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 2035#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2036#define PALMAS_INT2_STATUS_RTC_ALARM 0x01 2036#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2037#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 2037#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2038 2038
2039/* Bit definitions for INT2_MASK */ 2039/* Bit definitions for INT2_MASK */
2040#define PALMAS_INT2_MASK_VAC_ACOK 0x80 2040#define PALMAS_INT2_MASK_VAC_ACOK 0x80
2041#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 2041#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2042#define PALMAS_INT2_MASK_SHORT 0x40 2042#define PALMAS_INT2_MASK_SHORT 0x40
2043#define PALMAS_INT2_MASK_SHORT_SHIFT 6 2043#define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2044#define PALMAS_INT2_MASK_FBI_BB 0x20 2044#define PALMAS_INT2_MASK_FBI_BB 0x20
2045#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 2045#define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2046#define PALMAS_INT2_MASK_RESET_IN 0x10 2046#define PALMAS_INT2_MASK_RESET_IN 0x10
2047#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 2047#define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2048#define PALMAS_INT2_MASK_BATREMOVAL 0x08 2048#define PALMAS_INT2_MASK_BATREMOVAL 0x08
2049#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 2049#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2050#define PALMAS_INT2_MASK_WDT 0x04 2050#define PALMAS_INT2_MASK_WDT 0x04
2051#define PALMAS_INT2_MASK_WDT_SHIFT 2 2051#define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2052#define PALMAS_INT2_MASK_RTC_TIMER 0x02 2052#define PALMAS_INT2_MASK_RTC_TIMER 0x02
2053#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 2053#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2054#define PALMAS_INT2_MASK_RTC_ALARM 0x01 2054#define PALMAS_INT2_MASK_RTC_ALARM 0x01
2055#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 2055#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2056 2056
2057/* Bit definitions for INT2_LINE_STATE */ 2057/* Bit definitions for INT2_LINE_STATE */
2058#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 2058#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2059#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 2059#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2060#define PALMAS_INT2_LINE_STATE_SHORT 0x40 2060#define PALMAS_INT2_LINE_STATE_SHORT 0x40
2061#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 2061#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2062#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 2062#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2063#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 2063#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2064#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2064#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2065#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 2065#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2066#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2066#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2067#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 2067#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2068#define PALMAS_INT2_LINE_STATE_WDT 0x04 2068#define PALMAS_INT2_LINE_STATE_WDT 0x04
2069#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 2069#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2070#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2070#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2071#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 2071#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2072#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2072#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2073#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 2073#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2074 2074
2075/* Bit definitions for INT3_STATUS */ 2075/* Bit definitions for INT3_STATUS */
2076#define PALMAS_INT3_STATUS_VBUS 0x80 2076#define PALMAS_INT3_STATUS_VBUS 0x80
2077#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 2077#define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2078#define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2078#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2079#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 2079#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2080#define PALMAS_INT3_STATUS_ID 0x20 2080#define PALMAS_INT3_STATUS_ID 0x20
2081#define PALMAS_INT3_STATUS_ID_SHIFT 5 2081#define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2082#define PALMAS_INT3_STATUS_ID_OTG 0x10 2082#define PALMAS_INT3_STATUS_ID_OTG 0x10
2083#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 2083#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2084#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2084#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2085#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 2085#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2086#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2086#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2087#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 2087#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2088#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2088#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2089#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 2089#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2090#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2090#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2091#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 2091#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2092 2092
2093/* Bit definitions for INT3_MASK */ 2093/* Bit definitions for INT3_MASK */
2094#define PALMAS_INT3_MASK_VBUS 0x80 2094#define PALMAS_INT3_MASK_VBUS 0x80
2095#define PALMAS_INT3_MASK_VBUS_SHIFT 7 2095#define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2096#define PALMAS_INT3_MASK_VBUS_OTG 0x40 2096#define PALMAS_INT3_MASK_VBUS_OTG 0x40
2097#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 2097#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2098#define PALMAS_INT3_MASK_ID 0x20 2098#define PALMAS_INT3_MASK_ID 0x20
2099#define PALMAS_INT3_MASK_ID_SHIFT 5 2099#define PALMAS_INT3_MASK_ID_SHIFT 0x05
2100#define PALMAS_INT3_MASK_ID_OTG 0x10 2100#define PALMAS_INT3_MASK_ID_OTG 0x10
2101#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 2101#define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2102#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2102#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2103#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 2103#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2104#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2104#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2105#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 2105#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2106#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2106#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2107#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 2107#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2108#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2108#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2109#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 2109#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2110 2110
2111/* Bit definitions for INT3_LINE_STATE */ 2111/* Bit definitions for INT3_LINE_STATE */
2112#define PALMAS_INT3_LINE_STATE_VBUS 0x80 2112#define PALMAS_INT3_LINE_STATE_VBUS 0x80
2113#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 2113#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2114#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2114#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2115#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 2115#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2116#define PALMAS_INT3_LINE_STATE_ID 0x20 2116#define PALMAS_INT3_LINE_STATE_ID 0x20
2117#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 2117#define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2118#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2118#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2119#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 2119#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2120#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2120#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2121#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 2121#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2122#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2122#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2123#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 2123#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2124#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2124#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2125#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 2125#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2126#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2126#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2127#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 2127#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2128 2128
2129/* Bit definitions for INT4_STATUS */ 2129/* Bit definitions for INT4_STATUS */
2130#define PALMAS_INT4_STATUS_GPIO_7 0x80 2130#define PALMAS_INT4_STATUS_GPIO_7 0x80
2131#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 2131#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2132#define PALMAS_INT4_STATUS_GPIO_6 0x40 2132#define PALMAS_INT4_STATUS_GPIO_6 0x40
2133#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 2133#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2134#define PALMAS_INT4_STATUS_GPIO_5 0x20 2134#define PALMAS_INT4_STATUS_GPIO_5 0x20
2135#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 2135#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2136#define PALMAS_INT4_STATUS_GPIO_4 0x10 2136#define PALMAS_INT4_STATUS_GPIO_4 0x10
2137#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 2137#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2138#define PALMAS_INT4_STATUS_GPIO_3 0x08 2138#define PALMAS_INT4_STATUS_GPIO_3 0x08
2139#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 2139#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2140#define PALMAS_INT4_STATUS_GPIO_2 0x04 2140#define PALMAS_INT4_STATUS_GPIO_2 0x04
2141#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 2141#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2142#define PALMAS_INT4_STATUS_GPIO_1 0x02 2142#define PALMAS_INT4_STATUS_GPIO_1 0x02
2143#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 2143#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2144#define PALMAS_INT4_STATUS_GPIO_0 0x01 2144#define PALMAS_INT4_STATUS_GPIO_0 0x01
2145#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 2145#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2146 2146
2147/* Bit definitions for INT4_MASK */ 2147/* Bit definitions for INT4_MASK */
2148#define PALMAS_INT4_MASK_GPIO_7 0x80 2148#define PALMAS_INT4_MASK_GPIO_7 0x80
2149#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 2149#define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2150#define PALMAS_INT4_MASK_GPIO_6 0x40 2150#define PALMAS_INT4_MASK_GPIO_6 0x40
2151#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 2151#define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2152#define PALMAS_INT4_MASK_GPIO_5 0x20 2152#define PALMAS_INT4_MASK_GPIO_5 0x20
2153#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 2153#define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2154#define PALMAS_INT4_MASK_GPIO_4 0x10 2154#define PALMAS_INT4_MASK_GPIO_4 0x10
2155#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 2155#define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2156#define PALMAS_INT4_MASK_GPIO_3 0x08 2156#define PALMAS_INT4_MASK_GPIO_3 0x08
2157#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 2157#define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2158#define PALMAS_INT4_MASK_GPIO_2 0x04 2158#define PALMAS_INT4_MASK_GPIO_2 0x04
2159#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 2159#define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2160#define PALMAS_INT4_MASK_GPIO_1 0x02 2160#define PALMAS_INT4_MASK_GPIO_1 0x02
2161#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 2161#define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2162#define PALMAS_INT4_MASK_GPIO_0 0x01 2162#define PALMAS_INT4_MASK_GPIO_0 0x01
2163#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 2163#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2164 2164
2165/* Bit definitions for INT4_LINE_STATE */ 2165/* Bit definitions for INT4_LINE_STATE */
2166#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2166#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2167#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 2167#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2168#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2168#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2169#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 2169#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2170#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2170#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2171#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 2171#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2172#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2172#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2173#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 2173#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2174#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2174#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2175#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 2175#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2176#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2176#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2177#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 2177#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2178#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2178#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2179#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 2179#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2180#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2180#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2181#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 2181#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2182 2182
2183/* Bit definitions for INT4_EDGE_DETECT1 */ 2183/* Bit definitions for INT4_EDGE_DETECT1 */
2184#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2184#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2185#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 2185#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2186#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2186#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2187#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 2187#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2188#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2188#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2189#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 2189#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2190#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2190#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2191#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 2191#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2192#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2192#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2193#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 2193#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2194#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2194#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2195#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 2195#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2196#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2196#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2197#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 2197#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2198#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2198#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2199#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 2199#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2200 2200
2201/* Bit definitions for INT4_EDGE_DETECT2 */ 2201/* Bit definitions for INT4_EDGE_DETECT2 */
2202#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2202#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2203#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 2203#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2204#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2204#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2205#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 2205#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2206#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2206#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2207#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 2207#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2208#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2208#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2209#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 2209#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2210#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2210#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2211#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 2211#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2212#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2212#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2213#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 2213#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2214#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2214#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2215#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 2215#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2216#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2216#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2217#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 2217#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2218 2218
2219/* Bit definitions for INT_CTRL */ 2219/* Bit definitions for INT_CTRL */
2220#define PALMAS_INT_CTRL_INT_PENDING 0x04 2220#define PALMAS_INT_CTRL_INT_PENDING 0x04
2221#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 2221#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2222#define PALMAS_INT_CTRL_INT_CLEAR 0x01 2222#define PALMAS_INT_CTRL_INT_CLEAR 0x01
2223#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 2223#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2224 2224
2225/* Registers for function USB_OTG */ 2225/* Registers for function USB_OTG */
2226#define PALMAS_USB_WAKEUP 0x3 2226#define PALMAS_USB_WAKEUP 0x03
2227#define PALMAS_USB_VBUS_CTRL_SET 0x4 2227#define PALMAS_USB_VBUS_CTRL_SET 0x04
2228#define PALMAS_USB_VBUS_CTRL_CLR 0x5 2228#define PALMAS_USB_VBUS_CTRL_CLR 0x05
2229#define PALMAS_USB_ID_CTRL_SET 0x6 2229#define PALMAS_USB_ID_CTRL_SET 0x06
2230#define PALMAS_USB_ID_CTRL_CLEAR 0x7 2230#define PALMAS_USB_ID_CTRL_CLEAR 0x07
2231#define PALMAS_USB_VBUS_INT_SRC 0x8 2231#define PALMAS_USB_VBUS_INT_SRC 0x08
2232#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 2232#define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2233#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA 2233#define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2234#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB 2234#define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2235#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC 2235#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2236#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD 2236#define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2237#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE 2237#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2238#define PALMAS_USB_ID_INT_SRC 0xF 2238#define PALMAS_USB_ID_INT_SRC 0x0F
2239#define PALMAS_USB_ID_INT_LATCH_SET 0x10 2239#define PALMAS_USB_ID_INT_LATCH_SET 0x10
2240#define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2240#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2241#define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2241#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
@@ -2250,306 +2250,306 @@ enum usb_irq_events {
2250 2250
2251/* Bit definitions for USB_WAKEUP */ 2251/* Bit definitions for USB_WAKEUP */
2252#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2252#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2253#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 2253#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2254 2254
2255/* Bit definitions for USB_VBUS_CTRL_SET */ 2255/* Bit definitions for USB_VBUS_CTRL_SET */
2256#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2256#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2257#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 2257#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2258#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2258#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2259#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 2259#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2260#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2260#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2261#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 2261#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2262#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2262#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2263#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 2263#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2264#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2264#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2265#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 2265#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2266 2266
2267/* Bit definitions for USB_VBUS_CTRL_CLR */ 2267/* Bit definitions for USB_VBUS_CTRL_CLR */
2268#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2268#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2269#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 2269#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2270#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2270#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2271#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 2271#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2272#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2272#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2273#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 2273#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2274#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2274#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2275#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 2275#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2276#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2276#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2277#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 2277#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2278 2278
2279/* Bit definitions for USB_ID_CTRL_SET */ 2279/* Bit definitions for USB_ID_CTRL_SET */
2280#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2280#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2281#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 2281#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2282#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2282#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2283#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 2283#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2284#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2284#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2285#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 2285#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2286#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2286#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2287#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 2287#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2288#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2288#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2289#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 2289#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2290#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2290#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2291#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 2291#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2292 2292
2293/* Bit definitions for USB_ID_CTRL_CLEAR */ 2293/* Bit definitions for USB_ID_CTRL_CLEAR */
2294#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2294#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2295#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 2295#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2296#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2296#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2297#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 2297#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2298#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2298#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2299#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 2299#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2300#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2300#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2301#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 2301#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2302#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2302#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2303#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 2303#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2304#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2304#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2305#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 2305#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2306 2306
2307/* Bit definitions for USB_VBUS_INT_SRC */ 2307/* Bit definitions for USB_VBUS_INT_SRC */
2308#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2308#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2309#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 2309#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2310#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2310#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2311#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 2311#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2312#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2312#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2313#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 2313#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2314#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2314#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2315#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 2315#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2316#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2316#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2317#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 2317#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2318#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2318#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2319#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 2319#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2320#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2320#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2321#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 2321#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2322 2322
2323/* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2323/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2324#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2324#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2325#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 2325#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2326#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2326#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2327#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 2327#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2328#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2328#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2329#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 2329#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2330#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2330#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2331#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 2331#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2332#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2332#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2333#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 2333#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2334#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2334#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2335#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 2335#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2336#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2336#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2337#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 2337#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2338#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2338#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2339#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 2339#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2340 2340
2341/* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2341/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2342#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2342#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2343#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 2343#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2344#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2344#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2345#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 2345#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2346#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2346#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2347#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 2347#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2348#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2348#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2349#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 2349#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2350#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2350#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2351#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 2351#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2352#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2352#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2353#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 2353#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2354#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2354#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2355#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 2355#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2356#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2356#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2357#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 2357#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2358 2358
2359/* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2359/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2360#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2360#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2361#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 2361#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2362#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2362#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2363#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 2363#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2364#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2364#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2365#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 2365#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2366#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2366#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2367#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 2367#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2368#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2368#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2369#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 2369#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2370#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2370#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2371#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 2371#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2372#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2372#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2373#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 2373#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2374 2374
2375/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2375/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2376#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2376#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2377#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 2377#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2378#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2378#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2379#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 2379#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2380#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2380#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2381#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 2381#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2382#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2382#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2383#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 2383#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2384#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2384#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2385#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 2385#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2386#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2386#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2387#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 2387#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2388#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2388#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2389#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 2389#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2390 2390
2391/* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2391/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2392#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2392#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2393#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 2393#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2394#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2394#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2395#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 2395#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2396#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2396#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2397#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 2397#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2398#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2398#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2399#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 2399#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2400#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2400#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2401#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 2401#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2402#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2402#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2403#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 2403#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2404#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2404#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2405#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 2405#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2406#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2406#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2407#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 2407#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2408 2408
2409/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2409/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2410#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2410#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2411#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 2411#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2412#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2412#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2413#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 2413#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2414#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2414#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2415#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 2415#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2416#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2416#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2417#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 2417#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2418#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2418#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2419#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 2419#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2420#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2420#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2421#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 2421#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2422#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2422#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2423#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 2423#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2424#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2424#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2425#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 2425#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2426 2426
2427/* Bit definitions for USB_ID_INT_SRC */ 2427/* Bit definitions for USB_ID_INT_SRC */
2428#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2428#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2429#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 2429#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2430#define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2430#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2431#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 2431#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2432#define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2432#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2433#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 2433#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2434#define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2434#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2435#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 2435#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2436#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2436#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2437#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 2437#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2438 2438
2439/* Bit definitions for USB_ID_INT_LATCH_SET */ 2439/* Bit definitions for USB_ID_INT_LATCH_SET */
2440#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2440#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2441#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 2441#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2442#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2442#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2443#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 2443#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2444#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2444#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2445#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 2445#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2446#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2446#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2447#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 2447#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2448#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2448#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2449#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 2449#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2450 2450
2451/* Bit definitions for USB_ID_INT_LATCH_CLR */ 2451/* Bit definitions for USB_ID_INT_LATCH_CLR */
2452#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2452#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2453#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 2453#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2454#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2454#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2455#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 2455#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2456#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2456#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2457#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 2457#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2458#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2458#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2459#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 2459#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2460#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2460#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2461#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 2461#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2462 2462
2463/* Bit definitions for USB_ID_INT_EN_LO_SET */ 2463/* Bit definitions for USB_ID_INT_EN_LO_SET */
2464#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2464#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2465#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 2465#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2466#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2466#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2467#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 2467#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2468#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2468#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2469#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 2469#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2470#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2470#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2471#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 2471#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2472#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2472#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2473#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 2473#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2474 2474
2475/* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2475/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2476#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2476#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2477#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 2477#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2478#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2478#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2479#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 2479#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2480#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2480#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2481#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 2481#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2482#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2482#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2483#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 2483#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2484#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2484#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2485#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 2485#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2486 2486
2487/* Bit definitions for USB_ID_INT_EN_HI_SET */ 2487/* Bit definitions for USB_ID_INT_EN_HI_SET */
2488#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2488#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2489#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 2489#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2490#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2490#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2491#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 2491#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2492#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2492#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2493#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 2493#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2494#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2494#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2495#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 2495#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2496#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2496#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2497#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 2497#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2498 2498
2499/* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2499/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2500#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2500#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2501#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 2501#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2502#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2502#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2503#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 2503#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2504#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2504#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2505#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 2505#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2506#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2506#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2507#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 2507#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2508#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2508#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2509#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 2509#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2510 2510
2511/* Bit definitions for USB_OTG_ADP_CTRL */ 2511/* Bit definitions for USB_OTG_ADP_CTRL */
2512#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2512#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2513#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 2513#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2514#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2514#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2515#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 2515#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2516 2516
2517/* Bit definitions for USB_OTG_ADP_HIGH */ 2517/* Bit definitions for USB_OTG_ADP_HIGH */
2518#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff 2518#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2519#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 2519#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2520 2520
2521/* Bit definitions for USB_OTG_ADP_LOW */ 2521/* Bit definitions for USB_OTG_ADP_LOW */
2522#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff 2522#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2523#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 2523#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2524 2524
2525/* Bit definitions for USB_OTG_ADP_RISE */ 2525/* Bit definitions for USB_OTG_ADP_RISE */
2526#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff 2526#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2527#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 2527#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2528 2528
2529/* Bit definitions for USB_OTG_REVISION */ 2529/* Bit definitions for USB_OTG_REVISION */
2530#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2530#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2531#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 2531#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2532 2532
2533/* Registers for function VIBRATOR */ 2533/* Registers for function VIBRATOR */
2534#define PALMAS_VIBRA_CTRL 0x0 2534#define PALMAS_VIBRA_CTRL 0x00
2535 2535
2536/* Bit definitions for VIBRA_CTRL */ 2536/* Bit definitions for VIBRA_CTRL */
2537#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2537#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2538#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 2538#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2539#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2539#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2540#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 2540#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2541 2541
2542/* Registers for function GPIO */ 2542/* Registers for function GPIO */
2543#define PALMAS_GPIO_DATA_IN 0x0 2543#define PALMAS_GPIO_DATA_IN 0x00
2544#define PALMAS_GPIO_DATA_DIR 0x1 2544#define PALMAS_GPIO_DATA_DIR 0x01
2545#define PALMAS_GPIO_DATA_OUT 0x2 2545#define PALMAS_GPIO_DATA_OUT 0x02
2546#define PALMAS_GPIO_DEBOUNCE_EN 0x3 2546#define PALMAS_GPIO_DEBOUNCE_EN 0x03
2547#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 2547#define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2548#define PALMAS_GPIO_SET_DATA_OUT 0x5 2548#define PALMAS_GPIO_SET_DATA_OUT 0x05
2549#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2549#define PALMAS_PU_PD_GPIO_CTRL1 0x06
2550#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2550#define PALMAS_PU_PD_GPIO_CTRL2 0x07
2551#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2551#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2552#define PALMAS_GPIO_DATA_IN2 0x9 2552#define PALMAS_GPIO_DATA_IN2 0x09
2553#define PALMAS_GPIO_DATA_DIR2 0x0A 2553#define PALMAS_GPIO_DATA_DIR2 0x0A
2554#define PALMAS_GPIO_DATA_OUT2 0x0B 2554#define PALMAS_GPIO_DATA_OUT2 0x0B
2555#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C 2555#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
@@ -2561,167 +2561,167 @@ enum usb_irq_events {
2561 2561
2562/* Bit definitions for GPIO_DATA_IN */ 2562/* Bit definitions for GPIO_DATA_IN */
2563#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2563#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2564#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 2564#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2565#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2565#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2566#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 2566#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2567#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2567#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2568#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 2568#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2569#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2569#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2570#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 2570#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2571#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2571#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2572#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 2572#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2573#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2573#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2574#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 2574#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2575#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2575#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2576#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 2576#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2577#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2577#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2578#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 2578#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2579 2579
2580/* Bit definitions for GPIO_DATA_DIR */ 2580/* Bit definitions for GPIO_DATA_DIR */
2581#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2581#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2582#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 2582#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2583#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2583#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2584#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 2584#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2585#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2585#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2586#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 2586#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2587#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2587#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2588#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 2588#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2589#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2589#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2590#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 2590#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2591#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2591#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2592#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 2592#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2593#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2593#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2594#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 2594#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2595#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2595#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2596#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 2596#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2597 2597
2598/* Bit definitions for GPIO_DATA_OUT */ 2598/* Bit definitions for GPIO_DATA_OUT */
2599#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2599#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2600#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 2600#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2601#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2601#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2602#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 2602#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2603#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2603#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2604#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 2604#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2605#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2605#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2606#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 2606#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2607#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2607#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2608#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 2608#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2609#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2609#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2610#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 2610#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2611#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2611#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2612#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 2612#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2613#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2613#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2614#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 2614#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2615 2615
2616/* Bit definitions for GPIO_DEBOUNCE_EN */ 2616/* Bit definitions for GPIO_DEBOUNCE_EN */
2617#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2617#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2618#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 2618#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2619#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2619#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2620#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 2620#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2621#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2621#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2622#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 2622#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2623#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2623#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2624#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 2624#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2625#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2625#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2626#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 2626#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2627#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2627#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2628#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 2628#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2629#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2629#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2630#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 2630#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2631#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2631#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2632#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 2632#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2633 2633
2634/* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2634/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2635#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2635#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2636#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 2636#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2637#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2637#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2638#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 2638#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2639#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2639#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2640#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 2640#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2641#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2641#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2642#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 2642#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2643#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2643#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2644#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 2644#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2645#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2645#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2646#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 2646#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2647#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2647#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2648#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 2648#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2649#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2649#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2650#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 2650#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2651 2651
2652/* Bit definitions for GPIO_SET_DATA_OUT */ 2652/* Bit definitions for GPIO_SET_DATA_OUT */
2653#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2653#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2654#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 2654#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2655#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2655#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2656#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 2656#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2657#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2657#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2658#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 2658#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2659#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2659#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2660#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 2660#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2661#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2661#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2662#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 2662#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2663#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2663#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2664#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 2664#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2665#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2665#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2666#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 2666#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2667#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2667#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2668#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 2668#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2669 2669
2670/* Bit definitions for PU_PD_GPIO_CTRL1 */ 2670/* Bit definitions for PU_PD_GPIO_CTRL1 */
2671#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2671#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2672#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 2672#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2673#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2673#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2674#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 2674#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2675#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2675#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2676#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 2676#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2677#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2677#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2678#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 2678#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2679#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2679#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2680#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 2680#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2681#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2681#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2682#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 2682#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2683 2683
2684/* Bit definitions for PU_PD_GPIO_CTRL2 */ 2684/* Bit definitions for PU_PD_GPIO_CTRL2 */
2685#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2685#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2686#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 2686#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2687#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2687#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2688#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 2688#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2689#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2689#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2690#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 2690#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2691#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2691#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2692#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 2692#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2693#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2693#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2694#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 2694#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2695#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2695#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2696#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 2696#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2697#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2697#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2698#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 2698#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2699 2699
2700/* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2700/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2701#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2701#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2702#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 2702#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2703#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2703#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2704#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 2704#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2705#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2705#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2706#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 2706#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2707 2707
2708/* Registers for function GPADC */ 2708/* Registers for function GPADC */
2709#define PALMAS_GPADC_CTRL1 0x0 2709#define PALMAS_GPADC_CTRL1 0x00
2710#define PALMAS_GPADC_CTRL2 0x1 2710#define PALMAS_GPADC_CTRL2 0x01
2711#define PALMAS_GPADC_RT_CTRL 0x2 2711#define PALMAS_GPADC_RT_CTRL 0x02
2712#define PALMAS_GPADC_AUTO_CTRL 0x3 2712#define PALMAS_GPADC_AUTO_CTRL 0x03
2713#define PALMAS_GPADC_STATUS 0x4 2713#define PALMAS_GPADC_STATUS 0x04
2714#define PALMAS_GPADC_RT_SELECT 0x5 2714#define PALMAS_GPADC_RT_SELECT 0x05
2715#define PALMAS_GPADC_RT_CONV0_LSB 0x6 2715#define PALMAS_GPADC_RT_CONV0_LSB 0x06
2716#define PALMAS_GPADC_RT_CONV0_MSB 0x7 2716#define PALMAS_GPADC_RT_CONV0_MSB 0x07
2717#define PALMAS_GPADC_AUTO_SELECT 0x8 2717#define PALMAS_GPADC_AUTO_SELECT 0x08
2718#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 2718#define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2719#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA 2719#define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2720#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB 2720#define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2721#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC 2721#define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2722#define PALMAS_GPADC_SW_SELECT 0xD 2722#define PALMAS_GPADC_SW_SELECT 0x0D
2723#define PALMAS_GPADC_SW_CONV0_LSB 0xE 2723#define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2724#define PALMAS_GPADC_SW_CONV0_MSB 0xF 2724#define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2725#define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2725#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2726#define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2726#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2727#define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2727#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
@@ -2731,150 +2731,150 @@ enum usb_irq_events {
2731 2731
2732/* Bit definitions for GPADC_CTRL1 */ 2732/* Bit definitions for GPADC_CTRL1 */
2733#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2733#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2734#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 2734#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2735#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2735#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2736#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 2736#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2737#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2737#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2738#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 2738#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2739#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2739#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2740#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 2740#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2741#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2741#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2742#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 2742#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2743 2743
2744/* Bit definitions for GPADC_CTRL2 */ 2744/* Bit definitions for GPADC_CTRL2 */
2745#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2745#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2746#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 2746#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2747 2747
2748/* Bit definitions for GPADC_RT_CTRL */ 2748/* Bit definitions for GPADC_RT_CTRL */
2749#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2749#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2750#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 2750#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2751#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2751#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2752#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 2752#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2753 2753
2754/* Bit definitions for GPADC_AUTO_CTRL */ 2754/* Bit definitions for GPADC_AUTO_CTRL */
2755#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2755#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2756#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 2756#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2757#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2757#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2758#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 2758#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2759#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2759#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2760#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 2760#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2761#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2761#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2762#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 2762#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2763#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f 2763#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2764#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 2764#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2765 2765
2766/* Bit definitions for GPADC_STATUS */ 2766/* Bit definitions for GPADC_STATUS */
2767#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2767#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2768#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 2768#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2769 2769
2770/* Bit definitions for GPADC_RT_SELECT */ 2770/* Bit definitions for GPADC_RT_SELECT */
2771#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2771#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2772#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 2772#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2773#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f 2773#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2774#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 2774#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2775 2775
2776/* Bit definitions for GPADC_RT_CONV0_LSB */ 2776/* Bit definitions for GPADC_RT_CONV0_LSB */
2777#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff 2777#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2778#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 2778#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2779 2779
2780/* Bit definitions for GPADC_RT_CONV0_MSB */ 2780/* Bit definitions for GPADC_RT_CONV0_MSB */
2781#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f 2781#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2782#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 2782#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2783 2783
2784/* Bit definitions for GPADC_AUTO_SELECT */ 2784/* Bit definitions for GPADC_AUTO_SELECT */
2785#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 2785#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2786#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 2786#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2787#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f 2787#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2788#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 2788#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2789 2789
2790/* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2790/* Bit definitions for GPADC_AUTO_CONV0_LSB */
2791#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff 2791#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2792#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 2792#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2793 2793
2794/* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2794/* Bit definitions for GPADC_AUTO_CONV0_MSB */
2795#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f 2795#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2796#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 2796#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2797 2797
2798/* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2798/* Bit definitions for GPADC_AUTO_CONV1_LSB */
2799#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff 2799#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2800#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 2800#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2801 2801
2802/* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2802/* Bit definitions for GPADC_AUTO_CONV1_MSB */
2803#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f 2803#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2804#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 2804#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2805 2805
2806/* Bit definitions for GPADC_SW_SELECT */ 2806/* Bit definitions for GPADC_SW_SELECT */
2807#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2807#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2808#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 2808#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2809#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2809#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2810#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 2810#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2811#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f 2811#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2812#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 2812#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2813 2813
2814/* Bit definitions for GPADC_SW_CONV0_LSB */ 2814/* Bit definitions for GPADC_SW_CONV0_LSB */
2815#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff 2815#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2816#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 2816#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2817 2817
2818/* Bit definitions for GPADC_SW_CONV0_MSB */ 2818/* Bit definitions for GPADC_SW_CONV0_MSB */
2819#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f 2819#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2820#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 2820#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2821 2821
2822/* Bit definitions for GPADC_THRES_CONV0_LSB */ 2822/* Bit definitions for GPADC_THRES_CONV0_LSB */
2823#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff 2823#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2824#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 2824#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2825 2825
2826/* Bit definitions for GPADC_THRES_CONV0_MSB */ 2826/* Bit definitions for GPADC_THRES_CONV0_MSB */
2827#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2827#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2828#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 2828#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2829#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f 2829#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2830#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 2830#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2831 2831
2832/* Bit definitions for GPADC_THRES_CONV1_LSB */ 2832/* Bit definitions for GPADC_THRES_CONV1_LSB */
2833#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff 2833#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2834#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 2834#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2835 2835
2836/* Bit definitions for GPADC_THRES_CONV1_MSB */ 2836/* Bit definitions for GPADC_THRES_CONV1_MSB */
2837#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2837#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2838#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 2838#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2839#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f 2839#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2840#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 2840#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2841 2841
2842/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2842/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2843#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2843#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2844#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 2844#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2845#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2845#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2846#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 2846#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
2847#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f 2847#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
2848#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 2848#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
2849 2849
2850/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2850/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2851#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2851#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2852#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 2852#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
2853#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f 2853#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
2854#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 2854#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
2855 2855
2856/* Registers for function GPADC */ 2856/* Registers for function GPADC */
2857#define PALMAS_GPADC_TRIM1 0x0 2857#define PALMAS_GPADC_TRIM1 0x00
2858#define PALMAS_GPADC_TRIM2 0x1 2858#define PALMAS_GPADC_TRIM2 0x01
2859#define PALMAS_GPADC_TRIM3 0x2 2859#define PALMAS_GPADC_TRIM3 0x02
2860#define PALMAS_GPADC_TRIM4 0x3 2860#define PALMAS_GPADC_TRIM4 0x03
2861#define PALMAS_GPADC_TRIM5 0x4 2861#define PALMAS_GPADC_TRIM5 0x04
2862#define PALMAS_GPADC_TRIM6 0x5 2862#define PALMAS_GPADC_TRIM6 0x05
2863#define PALMAS_GPADC_TRIM7 0x6 2863#define PALMAS_GPADC_TRIM7 0x06
2864#define PALMAS_GPADC_TRIM8 0x7 2864#define PALMAS_GPADC_TRIM8 0x07
2865#define PALMAS_GPADC_TRIM9 0x8 2865#define PALMAS_GPADC_TRIM9 0x08
2866#define PALMAS_GPADC_TRIM10 0x9 2866#define PALMAS_GPADC_TRIM10 0x09
2867#define PALMAS_GPADC_TRIM11 0xA 2867#define PALMAS_GPADC_TRIM11 0x0A
2868#define PALMAS_GPADC_TRIM12 0xB 2868#define PALMAS_GPADC_TRIM12 0x0B
2869#define PALMAS_GPADC_TRIM13 0xC 2869#define PALMAS_GPADC_TRIM13 0x0C
2870#define PALMAS_GPADC_TRIM14 0xD 2870#define PALMAS_GPADC_TRIM14 0x0D
2871#define PALMAS_GPADC_TRIM15 0xE 2871#define PALMAS_GPADC_TRIM15 0x0E
2872#define PALMAS_GPADC_TRIM16 0xF 2872#define PALMAS_GPADC_TRIM16 0x0F
2873 2873
2874static inline int palmas_read(struct palmas *palmas, unsigned int base, 2874static inline int palmas_read(struct palmas *palmas, unsigned int base,
2875 unsigned int reg, unsigned int *val) 2875 unsigned int reg, unsigned int *val)
2876{ 2876{
2877 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2877 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2878 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2878 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2879 2879
2880 return regmap_read(palmas->regmap[slave_id], addr, val); 2880 return regmap_read(palmas->regmap[slave_id], addr, val);
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
deleted file mode 100644
index bd2f4f64e931..000000000000
--- a/include/linux/mfd/pm8xxx/core.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/*
14 * Qualcomm PMIC 8xxx driver header file
15 *
16 */
17
18#ifndef __MFD_PM8XXX_CORE_H
19#define __MFD_PM8XXX_CORE_H
20
21#include <linux/mfd/core.h>
22
23struct pm8xxx_drvdata {
24 int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
25 int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
26 int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
27 int n);
28 int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
29 int n);
30 int (*pmic_read_irq_stat) (const struct device *dev, int irq);
31 void *pm_chip_data;
32};
33
34static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
35{
36 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
37
38 if (!dd)
39 return -EINVAL;
40 return dd->pmic_readb(dev, addr, val);
41}
42
43static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
44{
45 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
46
47 if (!dd)
48 return -EINVAL;
49 return dd->pmic_writeb(dev, addr, val);
50}
51
52static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
53 int n)
54{
55 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
56
57 if (!dd)
58 return -EINVAL;
59 return dd->pmic_read_buf(dev, addr, buf, n);
60}
61
62static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
63 int n)
64{
65 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
66
67 if (!dd)
68 return -EINVAL;
69 return dd->pmic_write_buf(dev, addr, buf, n);
70}
71
72static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
73{
74 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
75
76 if (!dd)
77 return -EINVAL;
78 return dd->pmic_read_irq_stat(dev, irq);
79}
80
81#endif
diff --git a/include/linux/mfd/rdc321x.h b/include/linux/mfd/rdc321x.h
index 4bdf19c8eedf..442743a8f915 100644
--- a/include/linux/mfd/rdc321x.h
+++ b/include/linux/mfd/rdc321x.h
@@ -12,7 +12,7 @@
12#define RDC321X_GPIO_CTRL_REG2 0x84 12#define RDC321X_GPIO_CTRL_REG2 0x84
13#define RDC321X_GPIO_DATA_REG2 0x88 13#define RDC321X_GPIO_DATA_REG2 0x88
14 14
15#define RDC321X_MAX_GPIO 58 15#define RDC321X_NUM_GPIO 59
16 16
17struct rdc321x_gpio_pdata { 17struct rdc321x_gpio_pdata {
18 struct pci_dev *sb_pdev; 18 struct pci_dev *sb_pdev;
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
index 157e32b6ca28..47d84242940b 100644
--- a/include/linux/mfd/samsung/core.h
+++ b/include/linux/mfd/samsung/core.h
@@ -24,35 +24,36 @@ enum sec_device_type {
24}; 24};
25 25
26/** 26/**
27 * struct sec_pmic_dev - s5m87xx master device for sub-drivers 27 * struct sec_pmic_dev - s2m/s5m master device for sub-drivers
28 * @dev: master device of the chip (can be used to access platform data) 28 * @dev: Master device of the chip
29 * @pdata: pointer to private data used to pass platform data to child 29 * @pdata: Platform data populated with data from DTS
30 * @i2c: i2c client private data for regulator 30 * or board files
31 * @rtc: i2c client private data for rtc 31 * @regmap_pmic: Regmap associated with PMIC's I2C address
32 * @iolock: mutex for serializing io access 32 * @i2c: I2C client of the main driver
33 * @irqlock: mutex for buslock 33 * @device_type: Type of device, matches enum sec_device_type
34 * @irq_base: base IRQ number for sec-pmic, required for IRQs 34 * @irq_base: Base IRQ number for device, required for IRQs
35 * @irq: generic IRQ number for s5m87xx 35 * @irq: Generic IRQ number for device
36 * @ono: power onoff IRQ number for s5m87xx 36 * @irq_data: Runtime data structure for IRQ controller
37 * @irq_masks_cur: currently active value 37 * @ono: Power onoff IRQ number for s5m87xx
38 * @irq_masks_cache: cached hardware value 38 * @wakeup: Whether or not this is a wakeup device
39 * @type: indicate which s5m87xx "variant" is used 39 * @wtsr_smpl: Whether or not to enable in RTC driver the Watchdog
40 * Timer Software Reset (registers set to default value
41 * after PWRHOLD falling) and Sudden Momentary Power Loss
42 * (PMIC will enter power on sequence after short drop in
43 * VBATT voltage).
40 */ 44 */
41struct sec_pmic_dev { 45struct sec_pmic_dev {
42 struct device *dev; 46 struct device *dev;
43 struct sec_platform_data *pdata; 47 struct sec_platform_data *pdata;
44 struct regmap *regmap_pmic; 48 struct regmap *regmap_pmic;
45 struct regmap *regmap_rtc;
46 struct i2c_client *i2c; 49 struct i2c_client *i2c;
47 struct i2c_client *rtc;
48 50
49 int device_type; 51 unsigned long device_type;
50 int irq_base; 52 int irq_base;
51 int irq; 53 int irq;
52 struct regmap_irq_chip_data *irq_data; 54 struct regmap_irq_chip_data *irq_data;
53 55
54 int ono; 56 int ono;
55 unsigned long type;
56 bool wakeup; 57 bool wakeup;
57 bool wtsr_smpl; 58 bool wtsr_smpl;
58}; 59};
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index 48395a69a7e9..575a86c7fcbd 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -11,6 +11,7 @@
11#include <linux/mutex.h> 11#include <linux/mutex.h>
12 12
13struct device; 13struct device;
14struct regulator;
14 15
15enum stmpe_block { 16enum stmpe_block {
16 STMPE_BLOCK_GPIO = 1 << 0, 17 STMPE_BLOCK_GPIO = 1 << 0,
@@ -62,6 +63,8 @@ struct stmpe_client_info;
62 63
63/** 64/**
64 * struct stmpe - STMPE MFD structure 65 * struct stmpe - STMPE MFD structure
66 * @vcc: optional VCC regulator
67 * @vio: optional VIO regulator
65 * @lock: lock protecting I/O operations 68 * @lock: lock protecting I/O operations
66 * @irq_lock: IRQ bus lock 69 * @irq_lock: IRQ bus lock
67 * @dev: device, mostly for dev_dbg() 70 * @dev: device, mostly for dev_dbg()
@@ -73,13 +76,14 @@ struct stmpe_client_info;
73 * @regs: list of addresses of registers which are at different addresses on 76 * @regs: list of addresses of registers which are at different addresses on
74 * different variants. Indexed by one of STMPE_IDX_*. 77 * different variants. Indexed by one of STMPE_IDX_*.
75 * @irq: irq number for stmpe 78 * @irq: irq number for stmpe
76 * @irq_base: starting IRQ number for internal IRQs
77 * @num_gpios: number of gpios, differs for variants 79 * @num_gpios: number of gpios, differs for variants
78 * @ier: cache of IER registers for bus_lock 80 * @ier: cache of IER registers for bus_lock
79 * @oldier: cache of IER registers for bus_lock 81 * @oldier: cache of IER registers for bus_lock
80 * @pdata: platform data 82 * @pdata: platform data
81 */ 83 */
82struct stmpe { 84struct stmpe {
85 struct regulator *vcc;
86 struct regulator *vio;
83 struct mutex lock; 87 struct mutex lock;
84 struct mutex irq_lock; 88 struct mutex irq_lock;
85 struct device *dev; 89 struct device *dev;
@@ -91,7 +95,6 @@ struct stmpe {
91 const u8 *regs; 95 const u8 *regs;
92 96
93 int irq; 97 int irq;
94 int irq_base;
95 int num_gpios; 98 int num_gpios;
96 u8 ier[2]; 99 u8 ier[2];
97 u8 oldier[2]; 100 u8 oldier[2];
@@ -132,8 +135,6 @@ struct stmpe_keypad_platform_data {
132 135
133/** 136/**
134 * struct stmpe_gpio_platform_data - STMPE GPIO platform data 137 * struct stmpe_gpio_platform_data - STMPE GPIO platform data
135 * @gpio_base: first gpio number assigned. A maximum of
136 * %STMPE_NR_GPIOS GPIOs will be allocated.
137 * @norequest_mask: bitmask specifying which GPIOs should _not_ be 138 * @norequest_mask: bitmask specifying which GPIOs should _not_ be
138 * requestable due to different usage (e.g. touch, keypad) 139 * requestable due to different usage (e.g. touch, keypad)
139 * STMPE_GPIO_NOREQ_* macros can be used here. 140 * STMPE_GPIO_NOREQ_* macros can be used here.
@@ -141,7 +142,6 @@ struct stmpe_keypad_platform_data {
141 * @remove: board specific remove callback 142 * @remove: board specific remove callback
142 */ 143 */
143struct stmpe_gpio_platform_data { 144struct stmpe_gpio_platform_data {
144 int gpio_base;
145 unsigned norequest_mask; 145 unsigned norequest_mask;
146 void (*setup)(struct stmpe *stmpe, unsigned gpio_base); 146 void (*setup)(struct stmpe *stmpe, unsigned gpio_base);
147 void (*remove)(struct stmpe *stmpe, unsigned gpio_base); 147 void (*remove)(struct stmpe *stmpe, unsigned gpio_base);
@@ -195,8 +195,6 @@ struct stmpe_ts_platform_data {
195 * @irq_trigger: IRQ trigger to use for the interrupt to the host 195 * @irq_trigger: IRQ trigger to use for the interrupt to the host
196 * @autosleep: bool to enable/disable stmpe autosleep 196 * @autosleep: bool to enable/disable stmpe autosleep
197 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 197 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
198 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
199 * %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used.
200 * @irq_over_gpio: true if gpio is used to get irq 198 * @irq_over_gpio: true if gpio is used to get irq
201 * @irq_gpio: gpio number over which irq will be requested (significant only if 199 * @irq_gpio: gpio number over which irq will be requested (significant only if
202 * irq_over_gpio is true) 200 * irq_over_gpio is true)
@@ -207,7 +205,6 @@ struct stmpe_ts_platform_data {
207struct stmpe_platform_data { 205struct stmpe_platform_data {
208 int id; 206 int id;
209 unsigned int blocks; 207 unsigned int blocks;
210 int irq_base;
211 unsigned int irq_trigger; 208 unsigned int irq_trigger;
212 bool autosleep; 209 bool autosleep;
213 bool irq_over_gpio; 210 bool irq_over_gpio;
@@ -219,10 +216,4 @@ struct stmpe_platform_data {
219 struct stmpe_ts_platform_data *ts; 216 struct stmpe_ts_platform_data *ts;
220}; 217};
221 218
222#define STMPE_NR_INTERNAL_IRQS 9
223#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x))
224
225#define STMPE_NR_GPIOS 24
226#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS)
227
228#endif 219#endif
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
index 8789fa3c7fd9..75e543b78f53 100644
--- a/include/linux/mfd/syscon.h
+++ b/include/linux/mfd/syscon.h
@@ -15,6 +15,8 @@
15#ifndef __LINUX_MFD_SYSCON_H__ 15#ifndef __LINUX_MFD_SYSCON_H__
16#define __LINUX_MFD_SYSCON_H__ 16#define __LINUX_MFD_SYSCON_H__
17 17
18#include <linux/err.h>
19
18struct device_node; 20struct device_node;
19 21
20#ifdef CONFIG_MFD_SYSCON 22#ifdef CONFIG_MFD_SYSCON
diff --git a/include/linux/mfd/tps65218.h b/include/linux/mfd/tps65218.h
index d2e357df5a0e..2f9b593246ee 100644
--- a/include/linux/mfd/tps65218.h
+++ b/include/linux/mfd/tps65218.h
@@ -267,7 +267,6 @@ struct tps65218 {
267 u32 irq_mask; 267 u32 irq_mask;
268 struct regmap_irq_chip_data *irq_data; 268 struct regmap_irq_chip_data *irq_data;
269 struct regulator_desc desc[TPS65218_NUM_REGULATOR]; 269 struct regulator_desc desc[TPS65218_NUM_REGULATOR];
270 struct regulator_dev *rdev[TPS65218_NUM_REGULATOR];
271 struct tps_info *info[TPS65218_NUM_REGULATOR]; 270 struct tps_info *info[TPS65218_NUM_REGULATOR];
272 struct regmap *regmap; 271 struct regmap *regmap;
273}; 272};
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index 81f639bc1ae6..8f9fc3d26e6d 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -28,6 +28,7 @@
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/mfd/core.h> 29#include <linux/mfd/core.h>
30#include <linux/regulator/consumer.h> 30#include <linux/regulator/consumer.h>
31#include <linux/clk.h>
31 32
32#define TWL6040_REG_ASICID 0x01 33#define TWL6040_REG_ASICID 0x01
33#define TWL6040_REG_ASICREV 0x02 34#define TWL6040_REG_ASICREV 0x02
@@ -157,6 +158,7 @@
157#define TWL6040_I2CSEL 0x01 158#define TWL6040_I2CSEL 0x01
158#define TWL6040_RESETSPLIT 0x04 159#define TWL6040_RESETSPLIT 0x04
159#define TWL6040_INTCLRMODE 0x08 160#define TWL6040_INTCLRMODE 0x08
161#define TWL6040_I2CMODE(x) ((x & 0x3) << 4)
160 162
161/* STATUS (0x2E) fields */ 163/* STATUS (0x2E) fields */
162 164
@@ -222,6 +224,7 @@ struct twl6040 {
222 struct regmap *regmap; 224 struct regmap *regmap;
223 struct regmap_irq_chip_data *irq_data; 225 struct regmap_irq_chip_data *irq_data;
224 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */ 226 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
227 struct clk *clk32k;
225 struct mutex mutex; 228 struct mutex mutex;
226 struct mutex irq_mutex; 229 struct mutex irq_mutex;
227 struct mfd_cell cells[TWL6040_CELLS]; 230 struct mfd_cell cells[TWL6040_CELLS];
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 07:26:41 -0400