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authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-06 15:08:39 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-06 15:08:39 -0400
commit1fe9eb184721132c7254d76d9ef31c96edad8870 (patch)
treec055ffb7f201bc2370714ebe186a922d0eb39d0d
parent0bb464624140bfdd8389d4c5464ba134b2856049 (diff)
parent89abd4df28c6f85645e32f37ffab6426f800e4a1 (diff)
Merge tag 'mfd-for-linus-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into next
Pull MFD updates from Lee Jones: "Changes to existing drivers: - increase DT coverage: arizona, mc13xxx, stmpe-i2c, syscon, sun6i-prcm - regmap use of and/or clean-up: tps65090, twl6040 - basic renaming: max14577 - use new cpufreq helpers: db8500-prcmu - increase regulator support: stmpe, arizona, wm5102 - reduce legacy GPIO overhead: stmpe - provide necessary remove path: bcm590xx - expand sysfs presence: kempld - move driver specific code out to drivers: rtc-s5m, arizona - clk handling: twl6040 - use managed (devm_*) resources: ipaq-micro - clean-up/remove unused/duplicated code: tps65218, sec, pm8921, abx500-core, db8500-prcmu, menelaus - build/boot/sematic bug fixes: rtsx_usb, stmpe, bcm590xx, abx500, mc13xxx, rdc321x-southbridge, mfd-core, sec, max14577, syscon, cros_ec_spi - constify stuff: sm501, tps65910, tps6507x, tps6586x, max77686, max8997, kempld, max77693, max8907, rtsx_usb, db8500-prcmu, max8998, wm8400, sec, lp3943, max14577, as3711, omap-usb-host, ipaq-micro Support for new devices: - add support for max77836 into max14577 - add support for tps658640 into tps6586x - add support for cros-ec-i2c-tunnel into cros_ec - add new driver for rtsx_usb_sdmmc and rtsx_usb_ms - add new driver for axp20x - add new driver for sun6i-prcm - add new driver for ipaq-micro" * tag 'mfd-for-linus-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (77 commits) mfd: wm5102: Correct default for LDO Control 2 register mfd: menelaus: Use module_i2c_driver mfd: tps65218: Terminate of match table mfd: db8500-prcmu: Remove check for CONFIG_DBX500_PRCMU_DEBUG mfd: ti-keystone-devctrl: Add bindings for device state control mfd: palmas: Format the header file mfd: abx500-core: Remove unused function abx500_dump_all_banks() mfd: arizona: Correct addresses of always-on trigger registers mfd: max14577: Cast to architecture agnostic data type i2c: ChromeOS EC tunnel driver mfd: cros_ec: Sync to the latest cros_ec_commands.h from EC sources mfd: cros_ec: spi: Increase cros_ec_spi deadline from 5ms to 100ms mfd: cros_ec: spi: Make the cros_ec_spi timeout more reliable mfd: cros_ec: spi: Add mutex to cros_ec_spi mfd: cros_ec: spi: Calculate delay between transfers correctly mfd: arizona: Correct error message for addition of main IRQ chip mfd: wm8997: Add registers for high power mode mfd: arizona: Add MICVDD to mapped regulators mfd: ipaq-micro: Make mfd_cell array const mfd: ipaq-micro: Use devm_ioremap_resource() ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt39
-rw-r--r--Documentation/devicetree/bindings/mfd/sun6i-prcm.txt59
-rw-r--r--Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt19
-rw-r--r--Documentation/devicetree/bindings/mfd/twl6040.txt2
-rw-r--r--drivers/gpio/gpio-stmpe.c18
-rw-r--r--drivers/i2c/busses/Kconfig9
-rw-r--r--drivers/i2c/busses/Makefile1
-rw-r--r--drivers/i2c/busses/i2c-cros-ec-tunnel.c318
-rw-r--r--drivers/memstick/host/Kconfig10
-rw-r--r--drivers/memstick/host/Makefile1
-rw-r--r--drivers/memstick/host/rtsx_usb_ms.c839
-rw-r--r--drivers/mfd/Kconfig31
-rw-r--r--drivers/mfd/Makefile3
-rw-r--r--drivers/mfd/abx500-core.c16
-rw-r--r--drivers/mfd/arizona-core.c1
-rw-r--r--drivers/mfd/arizona-irq.c2
-rw-r--r--drivers/mfd/as3711.c2
-rw-r--r--drivers/mfd/axp20x.c258
-rw-r--r--drivers/mfd/bcm590xx.c9
-rw-r--r--drivers/mfd/cros_ec.c10
-rw-r--r--drivers/mfd/cros_ec_spi.c67
-rw-r--r--drivers/mfd/db8500-prcmu.c5
-rw-r--r--drivers/mfd/ipaq-micro.c482
-rw-r--r--drivers/mfd/kempld-core.c129
-rw-r--r--drivers/mfd/lp3943.c2
-rw-r--r--drivers/mfd/lpc_ich.c1
-rw-r--r--drivers/mfd/max14577.c40
-rw-r--r--drivers/mfd/max77686.c2
-rw-r--r--drivers/mfd/max77693.c2
-rw-r--r--drivers/mfd/max8907.c2
-rw-r--r--drivers/mfd/max8997.c2
-rw-r--r--drivers/mfd/max8998.c2
-rw-r--r--drivers/mfd/mc13xxx-core.c26
-rw-r--r--drivers/mfd/menelaus.c23
-rw-r--r--drivers/mfd/mfd-core.c11
-rw-r--r--drivers/mfd/omap-usb-host.c2
-rw-r--r--drivers/mfd/pm8921-core.c123
-rw-r--r--drivers/mfd/rdc321x-southbridge.c2
-rw-r--r--drivers/mfd/rtsx_usb.c16
-rw-r--r--drivers/mfd/sec-core.c88
-rw-r--r--drivers/mfd/sec-irq.c2
-rw-r--r--drivers/mfd/sm501.c2
-rw-r--r--drivers/mfd/stmpe-i2c.c30
-rw-r--r--drivers/mfd/stmpe.c33
-rw-r--r--drivers/mfd/stmpe.h2
-rw-r--r--drivers/mfd/sun6i-prcm.c134
-rw-r--r--drivers/mfd/syscon.c6
-rw-r--r--drivers/mfd/tps6507x.c2
-rw-r--r--drivers/mfd/tps65218.c1
-rw-r--r--drivers/mfd/tps6586x.c2
-rw-r--r--drivers/mfd/tps65910.c2
-rw-r--r--drivers/mfd/twl6040.c42
-rw-r--r--drivers/mfd/wm5102-tables.c4
-rw-r--r--drivers/mfd/wm5110-tables.c14
-rw-r--r--drivers/mfd/wm8400-core.c2
-rw-r--r--drivers/mfd/wm8997-tables.c14
-rw-r--r--drivers/mmc/host/Kconfig7
-rw-r--r--drivers/mmc/host/Makefile1
-rw-r--r--drivers/mmc/host/rtsx_usb_sdmmc.c1455
-rw-r--r--drivers/rtc/rtc-s5m.c75
-rw-r--r--include/linux/mfd/abx500.h1
-rw-r--r--include/linux/mfd/arizona/registers.h14
-rw-r--r--include/linux/mfd/axp20x.h180
-rw-r--r--include/linux/mfd/cros_ec.h4
-rw-r--r--include/linux/mfd/cros_ec_commands.h1128
-rw-r--r--include/linux/mfd/ipaq-micro.h148
-rw-r--r--include/linux/mfd/kempld.h4
-rw-r--r--include/linux/mfd/mc13xxx.h22
-rw-r--r--include/linux/mfd/palmas.h2166
-rw-r--r--include/linux/mfd/pm8xxx/core.h81
-rw-r--r--include/linux/mfd/rdc321x.h2
-rw-r--r--include/linux/mfd/samsung/core.h35
-rw-r--r--include/linux/mfd/stmpe.h19
-rw-r--r--include/linux/mfd/syscon.h2
-rw-r--r--include/linux/mfd/tps65218.h1
-rw-r--r--include/linux/mfd/twl6040.h3
76 files changed, 6641 insertions, 1673 deletions
diff --git a/Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt b/Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt
new file mode 100644
index 000000000000..898f030eba62
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt
@@ -0,0 +1,39 @@
1I2C bus that tunnels through the ChromeOS EC (cros-ec)
2======================================================
3On some ChromeOS board designs we've got a connection to the EC (embedded
4controller) but no direct connection to some devices on the other side of
5the EC (like a battery and PMIC). To get access to those devices we need
6to tunnel our i2c commands through the EC.
7
8The node for this device should be under a cros-ec node like google,cros-ec-spi
9or google,cros-ec-i2c.
10
11
12Required properties:
13- compatible: google,cros-ec-i2c-tunnel
14- google,remote-bus: The EC bus we'd like to talk to.
15
16Optional child nodes:
17- One node per I2C device connected to the tunnelled I2C bus.
18
19
20Example:
21 cros-ec@0 {
22 compatible = "google,cros-ec-spi";
23
24 ...
25
26 i2c-tunnel {
27 compatible = "google,cros-ec-i2c-tunnel";
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 google,remote-bus = <0>;
32
33 battery: sbs-battery@b {
34 compatible = "sbs,sbs-battery";
35 reg = <0xb>;
36 sbs,poll-retry-count = <1>;
37 };
38 };
39 }
diff --git a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
new file mode 100644
index 000000000000..1f5a31fef907
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
@@ -0,0 +1,59 @@
1* Allwinner PRCM (Power/Reset/Clock Management) Multi-Functional Device
2
3PRCM is an MFD device exposing several Power Management related devices
4(like clks and reset controllers).
5
6Required properties:
7 - compatible: "allwinner,sun6i-a31-prcm"
8 - reg: The PRCM registers range
9
10The prcm node may contain several subdevices definitions:
11 - see Documentation/devicetree/clk/sunxi.txt for clock devices
12 - see Documentation/devicetree/reset/allwinner,sunxi-clock-reset.txt for reset
13 controller devices
14
15
16Example:
17
18 prcm: prcm@01f01400 {
19 compatible = "allwinner,sun6i-a31-prcm";
20 reg = <0x01f01400 0x200>;
21
22 /* Put subdevices here */
23 ar100: ar100_clk {
24 compatible = "allwinner,sun6i-a31-ar100-clk";
25 #clock-cells = <0>;
26 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
27 };
28
29 ahb0: ahb0_clk {
30 compatible = "fixed-factor-clock";
31 #clock-cells = <0>;
32 clock-div = <1>;
33 clock-mult = <1>;
34 clocks = <&ar100_div>;
35 clock-output-names = "ahb0";
36 };
37
38 apb0: apb0_clk {
39 compatible = "allwinner,sun6i-a31-apb0-clk";
40 #clock-cells = <0>;
41 clocks = <&ahb0>;
42 clock-output-names = "apb0";
43 };
44
45 apb0_gates: apb0_gates_clk {
46 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
47 #clock-cells = <1>;
48 clocks = <&apb0>;
49 clock-output-names = "apb0_pio", "apb0_ir",
50 "apb0_timer01", "apb0_p2wi",
51 "apb0_uart", "apb0_1wire",
52 "apb0_i2c";
53 };
54
55 apb0_rst: apb0_rst {
56 compatible = "allwinner,sun6i-a31-clock-reset";
57 #reset-cells = <1>;
58 };
59 };
diff --git a/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt b/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt
new file mode 100644
index 000000000000..20963c76b4bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt
@@ -0,0 +1,19 @@
1* Device tree bindings for Texas Instruments keystone device state control
2
3The Keystone II devices have a set of registers that are used to control
4the status of its peripherals. This node is intended to allow access to
5this functionality.
6
7Required properties:
8
9- compatible: "ti,keystone-devctrl", "syscon"
10
11- reg: contains offset/length value for device state control
12 registers space.
13
14Example:
15
16devctrl: device-state-control@0x02620000 {
17 compatible = "ti,keystone-devctrl", "syscon";
18 reg = <0x02620000 0x1000>;
19};
diff --git a/Documentation/devicetree/bindings/mfd/twl6040.txt b/Documentation/devicetree/bindings/mfd/twl6040.txt
index 0f5dd709d752..a41157b5d930 100644
--- a/Documentation/devicetree/bindings/mfd/twl6040.txt
+++ b/Documentation/devicetree/bindings/mfd/twl6040.txt
@@ -19,6 +19,8 @@ Required properties:
19 19
20Optional properties, nodes: 20Optional properties, nodes:
21- enable-active-high: To power on the twl6040 during boot. 21- enable-active-high: To power on the twl6040 during boot.
22- clocks: phandle to the clk32k clock provider
23- clock-names: Must be "clk32k"
22 24
23Vibra functionality 25Vibra functionality
24Required properties: 26Required properties:
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 2776a09bee58..628b58494294 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -23,7 +23,8 @@
23enum { REG_RE, REG_FE, REG_IE }; 23enum { REG_RE, REG_FE, REG_IE };
24 24
25#define CACHE_NR_REGS 3 25#define CACHE_NR_REGS 3
26#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8) 26/* No variant has more than 24 GPIOs */
27#define CACHE_NR_BANKS (24 / 8)
27 28
28struct stmpe_gpio { 29struct stmpe_gpio {
29 struct gpio_chip chip; 30 struct gpio_chip chip;
@@ -31,8 +32,6 @@ struct stmpe_gpio {
31 struct device *dev; 32 struct device *dev;
32 struct mutex irq_lock; 33 struct mutex irq_lock;
33 struct irq_domain *domain; 34 struct irq_domain *domain;
34
35 int irq_base;
36 unsigned norequest_mask; 35 unsigned norequest_mask;
37 36
38 /* Caches of interrupt control registers for bus_lock */ 37 /* Caches of interrupt control registers for bus_lock */
@@ -311,13 +310,8 @@ static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
311static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio, 310static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
312 struct device_node *np) 311 struct device_node *np)
313{ 312{
314 int base = 0;
315
316 if (!np)
317 base = stmpe_gpio->irq_base;
318
319 stmpe_gpio->domain = irq_domain_add_simple(np, 313 stmpe_gpio->domain = irq_domain_add_simple(np,
320 stmpe_gpio->chip.ngpio, base, 314 stmpe_gpio->chip.ngpio, 0,
321 &stmpe_gpio_irq_simple_ops, stmpe_gpio); 315 &stmpe_gpio_irq_simple_ops, stmpe_gpio);
322 if (!stmpe_gpio->domain) { 316 if (!stmpe_gpio->domain) {
323 dev_err(stmpe_gpio->dev, "failed to create irqdomain\n"); 317 dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
@@ -354,7 +348,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
354#ifdef CONFIG_OF 348#ifdef CONFIG_OF
355 stmpe_gpio->chip.of_node = np; 349 stmpe_gpio->chip.of_node = np;
356#endif 350#endif
357 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1; 351 stmpe_gpio->chip.base = -1;
358 352
359 if (pdata) 353 if (pdata)
360 stmpe_gpio->norequest_mask = pdata->norequest_mask; 354 stmpe_gpio->norequest_mask = pdata->norequest_mask;
@@ -362,9 +356,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
362 of_property_read_u32(np, "st,norequest-mask", 356 of_property_read_u32(np, "st,norequest-mask",
363 &stmpe_gpio->norequest_mask); 357 &stmpe_gpio->norequest_mask);
364 358
365 if (irq >= 0) 359 if (irq < 0)
366 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
367 else
368 dev_info(&pdev->dev, 360 dev_info(&pdev->dev,
369 "device configured in no-irq mode; " 361 "device configured in no-irq mode; "
370 "irqs are not available\n"); 362 "irqs are not available\n");
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index c94db1c5e353..9a0a6cc7f4ba 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -993,6 +993,15 @@ config I2C_SIBYTE
993 help 993 help
994 Supports the SiByte SOC on-chip I2C interfaces (2 channels). 994 Supports the SiByte SOC on-chip I2C interfaces (2 channels).
995 995
996config I2C_CROS_EC_TUNNEL
997 tristate "ChromeOS EC tunnel I2C bus"
998 depends on MFD_CROS_EC
999 help
1000 If you say yes here you get an I2C bus that will tunnel i2c commands
1001 through to the other side of the ChromeOS EC to the i2c bus
1002 connected there. This will work whatever the interface used to
1003 talk to the EC (SPI, I2C or LPC).
1004
996config SCx200_I2C 1005config SCx200_I2C
997 tristate "NatSemi SCx200 I2C using GPIO pins (DEPRECATED)" 1006 tristate "NatSemi SCx200 I2C using GPIO pins (DEPRECATED)"
998 depends on SCx200_GPIO 1007 depends on SCx200_GPIO
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 18d18ff9db93..e110ca932918 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o
95# Other I2C/SMBus bus drivers 95# Other I2C/SMBus bus drivers
96obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o 96obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o
97obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o 97obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o
98obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o
98obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o 99obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
99obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o 100obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
100obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o 101obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
diff --git a/drivers/i2c/busses/i2c-cros-ec-tunnel.c b/drivers/i2c/busses/i2c-cros-ec-tunnel.c
new file mode 100644
index 000000000000..8e7a71487bb1
--- /dev/null
+++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c
@@ -0,0 +1,318 @@
1/*
2 * Copyright (C) 2013 Google, Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * Expose an I2C passthrough to the ChromeOS EC.
10 */
11
12#include <linux/module.h>
13#include <linux/i2c.h>
14#include <linux/mfd/cros_ec.h>
15#include <linux/mfd/cros_ec_commands.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18
19/**
20 * struct ec_i2c_device - Driver data for I2C tunnel
21 *
22 * @dev: Device node
23 * @adap: I2C adapter
24 * @ec: Pointer to EC device
25 * @remote_bus: The EC bus number we tunnel to on the other side.
26 * @request_buf: Buffer for transmitting data; we expect most transfers to fit.
27 * @response_buf: Buffer for receiving data; we expect most transfers to fit.
28 */
29
30struct ec_i2c_device {
31 struct device *dev;
32 struct i2c_adapter adap;
33 struct cros_ec_device *ec;
34
35 u16 remote_bus;
36
37 u8 request_buf[256];
38 u8 response_buf[256];
39};
40
41/**
42 * ec_i2c_count_message - Count bytes needed for ec_i2c_construct_message
43 *
44 * @i2c_msgs: The i2c messages to read
45 * @num: The number of i2c messages.
46 *
47 * Returns the number of bytes the messages will take up.
48 */
49static int ec_i2c_count_message(const struct i2c_msg i2c_msgs[], int num)
50{
51 int i;
52 int size;
53
54 size = sizeof(struct ec_params_i2c_passthru);
55 size += num * sizeof(struct ec_params_i2c_passthru_msg);
56 for (i = 0; i < num; i++)
57 if (!(i2c_msgs[i].flags & I2C_M_RD))
58 size += i2c_msgs[i].len;
59
60 return size;
61}
62
63/**
64 * ec_i2c_construct_message - construct a message to go to the EC
65 *
66 * This function effectively stuffs the standard i2c_msg format of Linux into
67 * a format that the EC understands.
68 *
69 * @buf: The buffer to fill. We assume that the buffer is big enough.
70 * @i2c_msgs: The i2c messages to read.
71 * @num: The number of i2c messages.
72 * @bus_num: The remote bus number we want to talk to.
73 *
74 * Returns 0 or a negative error number.
75 */
76static int ec_i2c_construct_message(u8 *buf, const struct i2c_msg i2c_msgs[],
77 int num, u16 bus_num)
78{
79 struct ec_params_i2c_passthru *params;
80 u8 *out_data;
81 int i;
82
83 out_data = buf + sizeof(struct ec_params_i2c_passthru) +
84 num * sizeof(struct ec_params_i2c_passthru_msg);
85
86 params = (struct ec_params_i2c_passthru *)buf;
87 params->port = bus_num;
88 params->num_msgs = num;
89 for (i = 0; i < num; i++) {
90 const struct i2c_msg *i2c_msg = &i2c_msgs[i];
91 struct ec_params_i2c_passthru_msg *msg = &params->msg[i];
92
93 msg->len = i2c_msg->len;
94 msg->addr_flags = i2c_msg->addr;
95
96 if (i2c_msg->flags & I2C_M_TEN)
97 msg->addr_flags |= EC_I2C_FLAG_10BIT;
98
99 if (i2c_msg->flags & I2C_M_RD) {
100 msg->addr_flags |= EC_I2C_FLAG_READ;
101 } else {
102 memcpy(out_data, i2c_msg->buf, msg->len);
103 out_data += msg->len;
104 }
105 }
106
107 return 0;
108}
109
110/**
111 * ec_i2c_count_response - Count bytes needed for ec_i2c_parse_response
112 *
113 * @i2c_msgs: The i2c messages to to fill up.
114 * @num: The number of i2c messages expected.
115 *
116 * Returns the number of response bytes expeced.
117 */
118static int ec_i2c_count_response(struct i2c_msg i2c_msgs[], int num)
119{
120 int size;
121 int i;
122
123 size = sizeof(struct ec_response_i2c_passthru);
124 for (i = 0; i < num; i++)
125 if (i2c_msgs[i].flags & I2C_M_RD)
126 size += i2c_msgs[i].len;
127
128 return size;
129}
130
131/**
132 * ec_i2c_parse_response - Parse a response from the EC
133 *
134 * We'll take the EC's response and copy it back into msgs.
135 *
136 * @buf: The buffer to parse.
137 * @i2c_msgs: The i2c messages to to fill up.
138 * @num: The number of i2c messages; will be modified to include the actual
139 * number received.
140 *
141 * Returns 0 or a negative error number.
142 */
143static int ec_i2c_parse_response(const u8 *buf, struct i2c_msg i2c_msgs[],
144 int *num)
145{
146 const struct ec_response_i2c_passthru *resp;
147 const u8 *in_data;
148 int i;
149
150 in_data = buf + sizeof(struct ec_response_i2c_passthru);
151
152 resp = (const struct ec_response_i2c_passthru *)buf;
153 if (resp->i2c_status & EC_I2C_STATUS_TIMEOUT)
154 return -ETIMEDOUT;
155 else if (resp->i2c_status & EC_I2C_STATUS_ERROR)
156 return -EREMOTEIO;
157
158 /* Other side could send us back fewer messages, but not more */
159 if (resp->num_msgs > *num)
160 return -EPROTO;
161 *num = resp->num_msgs;
162
163 for (i = 0; i < *num; i++) {
164 struct i2c_msg *i2c_msg = &i2c_msgs[i];
165
166 if (i2c_msgs[i].flags & I2C_M_RD) {
167 memcpy(i2c_msg->buf, in_data, i2c_msg->len);
168 in_data += i2c_msg->len;
169 }
170 }
171
172 return 0;
173}
174
175static int ec_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg i2c_msgs[],
176 int num)
177{
178 struct ec_i2c_device *bus = adap->algo_data;
179 struct device *dev = bus->dev;
180 const u16 bus_num = bus->remote_bus;
181 int request_len;
182 int response_len;
183 u8 *request = NULL;
184 u8 *response = NULL;
185 int result;
186
187 request_len = ec_i2c_count_message(i2c_msgs, num);
188 if (request_len < 0) {
189 dev_warn(dev, "Error constructing message %d\n", request_len);
190 result = request_len;
191 goto exit;
192 }
193 response_len = ec_i2c_count_response(i2c_msgs, num);
194 if (response_len < 0) {
195 /* Unexpected; no errors should come when NULL response */
196 dev_warn(dev, "Error preparing response %d\n", response_len);
197 result = response_len;
198 goto exit;
199 }
200
201 if (request_len <= ARRAY_SIZE(bus->request_buf)) {
202 request = bus->request_buf;
203 } else {
204 request = kzalloc(request_len, GFP_KERNEL);
205 if (request == NULL) {
206 result = -ENOMEM;
207 goto exit;
208 }
209 }
210 if (response_len <= ARRAY_SIZE(bus->response_buf)) {
211 response = bus->response_buf;
212 } else {
213 response = kzalloc(response_len, GFP_KERNEL);
214 if (response == NULL) {
215 result = -ENOMEM;
216 goto exit;
217 }
218 }
219
220 ec_i2c_construct_message(request, i2c_msgs, num, bus_num);
221 result = bus->ec->command_sendrecv(bus->ec, EC_CMD_I2C_PASSTHRU,
222 request, request_len,
223 response, response_len);
224 if (result)
225 goto exit;
226
227 result = ec_i2c_parse_response(response, i2c_msgs, &num);
228 if (result < 0)
229 goto exit;
230
231 /* Indicate success by saying how many messages were sent */
232 result = num;
233exit:
234 if (request != bus->request_buf)
235 kfree(request);
236 if (response != bus->response_buf)
237 kfree(response);
238
239 return result;
240}
241
242static u32 ec_i2c_functionality(struct i2c_adapter *adap)
243{
244 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
245}
246
247static const struct i2c_algorithm ec_i2c_algorithm = {
248 .master_xfer = ec_i2c_xfer,
249 .functionality = ec_i2c_functionality,
250};
251
252static int ec_i2c_probe(struct platform_device *pdev)
253{
254 struct device_node *np = pdev->dev.of_node;
255 struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
256 struct device *dev = &pdev->dev;
257 struct ec_i2c_device *bus = NULL;
258 u32 remote_bus;
259 int err;
260
261 if (!ec->command_sendrecv) {
262 dev_err(dev, "Missing sendrecv\n");
263 return -EINVAL;
264 }
265
266 bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
267 if (bus == NULL)
268 return -ENOMEM;
269
270 err = of_property_read_u32(np, "google,remote-bus", &remote_bus);
271 if (err) {
272 dev_err(dev, "Couldn't read remote-bus property\n");
273 return err;
274 }
275 bus->remote_bus = remote_bus;
276
277 bus->ec = ec;
278 bus->dev = dev;
279
280 bus->adap.owner = THIS_MODULE;
281 strlcpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name));
282 bus->adap.algo = &ec_i2c_algorithm;
283 bus->adap.algo_data = bus;
284 bus->adap.dev.parent = &pdev->dev;
285 bus->adap.dev.of_node = np;
286
287 err = i2c_add_adapter(&bus->adap);
288 if (err) {
289 dev_err(dev, "cannot register i2c adapter\n");
290 return err;
291 }
292 platform_set_drvdata(pdev, bus);
293
294 return err;
295}
296
297static int ec_i2c_remove(struct platform_device *dev)
298{
299 struct ec_i2c_device *bus = platform_get_drvdata(dev);
300
301 i2c_del_adapter(&bus->adap);
302
303 return 0;
304}
305
306static struct platform_driver ec_i2c_tunnel_driver = {
307 .probe = ec_i2c_probe,
308 .remove = ec_i2c_remove,
309 .driver = {
310 .name = "cros-ec-i2c-tunnel",
311 },
312};
313
314module_platform_driver(ec_i2c_tunnel_driver);
315
316MODULE_LICENSE("GPL");
317MODULE_DESCRIPTION("EC I2C tunnel driver");
318MODULE_ALIAS("platform:cros-ec-i2c-tunnel");
diff --git a/drivers/memstick/host/Kconfig b/drivers/memstick/host/Kconfig
index 1b37cf8cd204..7310e32b5991 100644
--- a/drivers/memstick/host/Kconfig
+++ b/drivers/memstick/host/Kconfig
@@ -52,3 +52,13 @@ config MEMSTICK_REALTEK_PCI
52 52
53 To compile this driver as a module, choose M here: the module will 53 To compile this driver as a module, choose M here: the module will
54 be called rtsx_pci_ms. 54 be called rtsx_pci_ms.
55
56config MEMSTICK_REALTEK_USB
57 tristate "Realtek USB Memstick Card Interface Driver"
58 depends on MFD_RTSX_USB
59 help
60 Say Y here to include driver code to support Memstick card interface
61 of Realtek RTS5129/39 series USB card reader
62
63 To compile this driver as a module, choose M here: the module will
64 be called rts5139_ms.
diff --git a/drivers/memstick/host/Makefile b/drivers/memstick/host/Makefile
index af3459d7686e..491c9557441d 100644
--- a/drivers/memstick/host/Makefile
+++ b/drivers/memstick/host/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_MEMSTICK_TIFM_MS) += tifm_ms.o
6obj-$(CONFIG_MEMSTICK_JMICRON_38X) += jmb38x_ms.o 6obj-$(CONFIG_MEMSTICK_JMICRON_38X) += jmb38x_ms.o
7obj-$(CONFIG_MEMSTICK_R592) += r592.o 7obj-$(CONFIG_MEMSTICK_R592) += r592.o
8obj-$(CONFIG_MEMSTICK_REALTEK_PCI) += rtsx_pci_ms.o 8obj-$(CONFIG_MEMSTICK_REALTEK_PCI) += rtsx_pci_ms.o
9obj-$(CONFIG_MEMSTICK_REALTEK_USB) += rtsx_usb_ms.o
diff --git a/drivers/memstick/host/rtsx_usb_ms.c b/drivers/memstick/host/rtsx_usb_ms.c
new file mode 100644
index 000000000000..a7282b7d4de8
--- /dev/null
+++ b/drivers/memstick/host/rtsx_usb_ms.c
@@ -0,0 +1,839 @@
1/* Realtek USB Memstick Card Interface driver
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
16 *
17 * Author:
18 * Roger Tseng <rogerable@realtek.com>
19 */
20
21#include <linux/module.h>
22#include <linux/highmem.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/workqueue.h>
26#include <linux/memstick.h>
27#include <linux/kthread.h>
28#include <linux/mfd/rtsx_usb.h>
29#include <linux/pm_runtime.h>
30#include <linux/mutex.h>
31#include <linux/sched.h>
32#include <linux/completion.h>
33#include <asm/unaligned.h>
34
35struct rtsx_usb_ms {
36 struct platform_device *pdev;
37 struct rtsx_ucr *ucr;
38 struct memstick_host *msh;
39 struct memstick_request *req;
40
41 struct mutex host_mutex;
42 struct work_struct handle_req;
43
44 struct task_struct *detect_ms;
45 struct completion detect_ms_exit;
46
47 u8 ssc_depth;
48 unsigned int clock;
49 int power_mode;
50 unsigned char ifmode;
51 bool eject;
52};
53
54static inline struct device *ms_dev(struct rtsx_usb_ms *host)
55{
56 return &(host->pdev->dev);
57}
58
59static inline void ms_clear_error(struct rtsx_usb_ms *host)
60{
61 struct rtsx_ucr *ucr = host->ucr;
62 rtsx_usb_ep0_write_register(ucr, CARD_STOP,
63 MS_STOP | MS_CLR_ERR,
64 MS_STOP | MS_CLR_ERR);
65
66 rtsx_usb_clear_dma_err(ucr);
67 rtsx_usb_clear_fsm_err(ucr);
68}
69
70#ifdef DEBUG
71
72static void ms_print_debug_regs(struct rtsx_usb_ms *host)
73{
74 struct rtsx_ucr *ucr = host->ucr;
75 u16 i;
76 u8 *ptr;
77
78 /* Print MS host internal registers */
79 rtsx_usb_init_cmd(ucr);
80
81 /* MS_CFG to MS_INT_REG */
82 for (i = 0xFD40; i <= 0xFD44; i++)
83 rtsx_usb_add_cmd(ucr, READ_REG_CMD, i, 0, 0);
84
85 /* CARD_SHARE_MODE to CARD_GPIO */
86 for (i = 0xFD51; i <= 0xFD56; i++)
87 rtsx_usb_add_cmd(ucr, READ_REG_CMD, i, 0, 0);
88
89 /* CARD_PULL_CTLx */
90 for (i = 0xFD60; i <= 0xFD65; i++)
91 rtsx_usb_add_cmd(ucr, READ_REG_CMD, i, 0, 0);
92
93 /* CARD_DATA_SOURCE, CARD_SELECT, CARD_CLK_EN, CARD_PWR_CTL */
94 rtsx_usb_add_cmd(ucr, READ_REG_CMD, CARD_DATA_SOURCE, 0, 0);
95 rtsx_usb_add_cmd(ucr, READ_REG_CMD, CARD_SELECT, 0, 0);
96 rtsx_usb_add_cmd(ucr, READ_REG_CMD, CARD_CLK_EN, 0, 0);
97 rtsx_usb_add_cmd(ucr, READ_REG_CMD, CARD_PWR_CTL, 0, 0);
98
99 rtsx_usb_send_cmd(ucr, MODE_CR, 100);
100 rtsx_usb_get_rsp(ucr, 21, 100);
101
102 ptr = ucr->rsp_buf;
103 for (i = 0xFD40; i <= 0xFD44; i++)
104 dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
105 for (i = 0xFD51; i <= 0xFD56; i++)
106 dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
107 for (i = 0xFD60; i <= 0xFD65; i++)
108 dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
109
110 dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", CARD_DATA_SOURCE, *(ptr++));
111 dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", CARD_SELECT, *(ptr++));
112 dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", CARD_CLK_EN, *(ptr++));
113 dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", CARD_PWR_CTL, *(ptr++));
114}
115
116#else
117
118static void ms_print_debug_regs(struct rtsx_usb_ms *host)
119{
120}
121
122#endif
123
124static int ms_pull_ctl_disable_lqfp48(struct rtsx_ucr *ucr)
125{
126 rtsx_usb_init_cmd(ucr);
127
128 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
129 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
130 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
131 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
132 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
133 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
134
135 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
136}
137
138static int ms_pull_ctl_disable_qfn24(struct rtsx_ucr *ucr)
139{
140 rtsx_usb_init_cmd(ucr);
141
142 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
143 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
144 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
145 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
146 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
147 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
148
149 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
150}
151
152static int ms_pull_ctl_enable_lqfp48(struct rtsx_ucr *ucr)
153{
154 rtsx_usb_init_cmd(ucr);
155
156 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
157 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
158 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
159 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
160 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
161 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
162
163 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
164}
165
166static int ms_pull_ctl_enable_qfn24(struct rtsx_ucr *ucr)
167{
168 rtsx_usb_init_cmd(ucr);
169
170 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
171 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
172 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
173 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
174 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
175 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
176
177 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
178}
179
180static int ms_power_on(struct rtsx_usb_ms *host)
181{
182 struct rtsx_ucr *ucr = host->ucr;
183 int err;
184
185 dev_dbg(ms_dev(host), "%s\n", __func__);
186
187 rtsx_usb_init_cmd(ucr);
188 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_SELECT, 0x07, MS_MOD_SEL);
189 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_SHARE_MODE,
190 CARD_SHARE_MASK, CARD_SHARE_MS);
191 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_CLK_EN,
192 MS_CLK_EN, MS_CLK_EN);
193 err = rtsx_usb_send_cmd(ucr, MODE_C, 100);
194 if (err < 0)
195 return err;
196
197 if (CHECK_PKG(ucr, LQFP48))
198 err = ms_pull_ctl_enable_lqfp48(ucr);
199 else
200 err = ms_pull_ctl_enable_qfn24(ucr);
201 if (err < 0)
202 return err;
203
204 err = rtsx_usb_write_register(ucr, CARD_PWR_CTL,
205 POWER_MASK, PARTIAL_POWER_ON);
206 if (err)
207 return err;
208
209 usleep_range(800, 1000);
210
211 rtsx_usb_init_cmd(ucr);
212 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PWR_CTL,
213 POWER_MASK, POWER_ON);
214 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_OE,
215 MS_OUTPUT_EN, MS_OUTPUT_EN);
216
217 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
218}
219
220static int ms_power_off(struct rtsx_usb_ms *host)
221{
222 struct rtsx_ucr *ucr = host->ucr;
223 int err;
224
225 dev_dbg(ms_dev(host), "%s\n", __func__);
226
227 rtsx_usb_init_cmd(ucr);
228
229 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
230 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
231
232 err = rtsx_usb_send_cmd(ucr, MODE_C, 100);
233 if (err < 0)
234 return err;
235
236 if (CHECK_PKG(ucr, LQFP48))
237 return ms_pull_ctl_disable_lqfp48(ucr);
238
239 return ms_pull_ctl_disable_qfn24(ucr);
240}
241
242static int ms_transfer_data(struct rtsx_usb_ms *host, unsigned char data_dir,
243 u8 tpc, u8 cfg, struct scatterlist *sg)
244{
245 struct rtsx_ucr *ucr = host->ucr;
246 int err;
247 unsigned int length = sg->length;
248 u16 sec_cnt = (u16)(length / 512);
249 u8 trans_mode, dma_dir, flag;
250 unsigned int pipe;
251 struct memstick_dev *card = host->msh->card;
252
253 dev_dbg(ms_dev(host), "%s: tpc = 0x%02x, data_dir = %s, length = %d\n",
254 __func__, tpc, (data_dir == READ) ? "READ" : "WRITE",
255 length);
256
257 if (data_dir == READ) {
258 flag = MODE_CDIR;
259 dma_dir = DMA_DIR_FROM_CARD;
260 if (card->id.type != MEMSTICK_TYPE_PRO)
261 trans_mode = MS_TM_NORMAL_READ;
262 else
263 trans_mode = MS_TM_AUTO_READ;
264 pipe = usb_rcvbulkpipe(ucr->pusb_dev, EP_BULK_IN);
265 } else {
266 flag = MODE_CDOR;
267 dma_dir = DMA_DIR_TO_CARD;
268 if (card->id.type != MEMSTICK_TYPE_PRO)
269 trans_mode = MS_TM_NORMAL_WRITE;
270 else
271 trans_mode = MS_TM_AUTO_WRITE;
272 pipe = usb_sndbulkpipe(ucr->pusb_dev, EP_BULK_OUT);
273 }
274
275 rtsx_usb_init_cmd(ucr);
276
277 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
278 if (card->id.type == MEMSTICK_TYPE_PRO) {
279 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_SECTOR_CNT_H,
280 0xFF, (u8)(sec_cnt >> 8));
281 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_SECTOR_CNT_L,
282 0xFF, (u8)sec_cnt);
283 }
284 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
285
286 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_TC3,
287 0xFF, (u8)(length >> 24));
288 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_TC2,
289 0xFF, (u8)(length >> 16));
290 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_TC1,
291 0xFF, (u8)(length >> 8));
292 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_TC0, 0xFF,
293 (u8)length);
294 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_CTL,
295 0x03 | DMA_PACK_SIZE_MASK, dma_dir | DMA_EN | DMA_512);
296 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_DATA_SOURCE,
297 0x01, RING_BUFFER);
298
299 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TRANSFER,
300 0xFF, MS_TRANSFER_START | trans_mode);
301 rtsx_usb_add_cmd(ucr, CHECK_REG_CMD, MS_TRANSFER,
302 MS_TRANSFER_END, MS_TRANSFER_END);
303
304 err = rtsx_usb_send_cmd(ucr, flag | STAGE_MS_STATUS, 100);
305 if (err)
306 return err;
307
308 err = rtsx_usb_transfer_data(ucr, pipe, sg, length,
309 1, NULL, 10000);
310 if (err)
311 goto err_out;
312
313 err = rtsx_usb_get_rsp(ucr, 3, 15000);
314 if (err)
315 goto err_out;
316
317 if (ucr->rsp_buf[0] & MS_TRANSFER_ERR ||
318 ucr->rsp_buf[1] & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
319 err = -EIO;
320 goto err_out;
321 }
322 return 0;
323err_out:
324 ms_clear_error(host);
325 return err;
326}
327
328static int ms_write_bytes(struct rtsx_usb_ms *host, u8 tpc,
329 u8 cfg, u8 cnt, u8 *data, u8 *int_reg)
330{
331 struct rtsx_ucr *ucr = host->ucr;
332 int err, i;
333
334 dev_dbg(ms_dev(host), "%s: tpc = 0x%02x\n", __func__, tpc);
335
336 rtsx_usb_init_cmd(ucr);
337
338 for (i = 0; i < cnt; i++)
339 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
340 PPBUF_BASE2 + i, 0xFF, data[i]);
341
342 if (cnt % 2)
343 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
344 PPBUF_BASE2 + i, 0xFF, 0xFF);
345
346 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
347 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
348 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
349 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_DATA_SOURCE,
350 0x01, PINGPONG_BUFFER);
351
352 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TRANSFER,
353 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
354 rtsx_usb_add_cmd(ucr, CHECK_REG_CMD, MS_TRANSFER,
355 MS_TRANSFER_END, MS_TRANSFER_END);
356 rtsx_usb_add_cmd(ucr, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
357
358 err = rtsx_usb_send_cmd(ucr, MODE_CR, 100);
359 if (err)
360 return err;
361
362 err = rtsx_usb_get_rsp(ucr, 2, 5000);
363 if (err || (ucr->rsp_buf[0] & MS_TRANSFER_ERR)) {
364 u8 val;
365
366 rtsx_usb_ep0_read_register(ucr, MS_TRANS_CFG, &val);
367 dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val);
368
369 if (int_reg)
370 *int_reg = val & 0x0F;
371
372 ms_print_debug_regs(host);
373
374 ms_clear_error(host);
375
376 if (!(tpc & 0x08)) {
377 if (val & MS_CRC16_ERR)
378 return -EIO;
379 } else {
380 if (!(val & 0x80)) {
381 if (val & (MS_INT_ERR | MS_INT_CMDNK))
382 return -EIO;
383 }
384 }
385
386 return -ETIMEDOUT;
387 }
388
389 if (int_reg)
390 *int_reg = ucr->rsp_buf[1] & 0x0F;
391
392 return 0;
393}
394
395static int ms_read_bytes(struct rtsx_usb_ms *host, u8 tpc,
396 u8 cfg, u8 cnt, u8 *data, u8 *int_reg)
397{
398 struct rtsx_ucr *ucr = host->ucr;
399 int err, i;
400 u8 *ptr;
401
402 dev_dbg(ms_dev(host), "%s: tpc = 0x%02x\n", __func__, tpc);
403
404 rtsx_usb_init_cmd(ucr);
405
406 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
407 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
408 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
409 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_DATA_SOURCE,
410 0x01, PINGPONG_BUFFER);
411
412 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MS_TRANSFER,
413 0xFF, MS_TRANSFER_START | MS_TM_READ_BYTES);
414 rtsx_usb_add_cmd(ucr, CHECK_REG_CMD, MS_TRANSFER,
415 MS_TRANSFER_END, MS_TRANSFER_END);
416 for (i = 0; i < cnt - 1; i++)
417 rtsx_usb_add_cmd(ucr, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
418 if (cnt % 2)
419 rtsx_usb_add_cmd(ucr, READ_REG_CMD, PPBUF_BASE2 + cnt, 0, 0);
420 else
421 rtsx_usb_add_cmd(ucr, READ_REG_CMD,
422 PPBUF_BASE2 + cnt - 1, 0, 0);
423
424 rtsx_usb_add_cmd(ucr, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
425
426 err = rtsx_usb_send_cmd(ucr, MODE_CR, 100);
427 if (err)
428 return err;
429
430 err = rtsx_usb_get_rsp(ucr, cnt + 2, 5000);
431 if (err || (ucr->rsp_buf[0] & MS_TRANSFER_ERR)) {
432 u8 val;
433
434 rtsx_usb_ep0_read_register(ucr, MS_TRANS_CFG, &val);
435 dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val);
436
437 if (int_reg && (host->ifmode != MEMSTICK_SERIAL))
438 *int_reg = val & 0x0F;
439
440 ms_print_debug_regs(host);
441
442 ms_clear_error(host);
443
444 if (!(tpc & 0x08)) {
445 if (val & MS_CRC16_ERR)
446 return -EIO;
447 } else {
448 if (!(val & 0x80)) {
449 if (val & (MS_INT_ERR | MS_INT_CMDNK))
450 return -EIO;
451 }
452 }
453
454 return -ETIMEDOUT;
455 }
456
457 ptr = ucr->rsp_buf + 1;
458 for (i = 0; i < cnt; i++)
459 data[i] = *ptr++;
460
461
462 if (int_reg && (host->ifmode != MEMSTICK_SERIAL))
463 *int_reg = *ptr & 0x0F;
464
465 return 0;
466}
467
468static int rtsx_usb_ms_issue_cmd(struct rtsx_usb_ms *host)
469{
470 struct memstick_request *req = host->req;
471 int err = 0;
472 u8 cfg = 0, int_reg;
473
474 dev_dbg(ms_dev(host), "%s\n", __func__);
475
476 if (req->need_card_int) {
477 if (host->ifmode != MEMSTICK_SERIAL)
478 cfg = WAIT_INT;
479 }
480
481 if (req->long_data) {
482 err = ms_transfer_data(host, req->data_dir,
483 req->tpc, cfg, &(req->sg));
484 } else {
485 if (req->data_dir == READ)
486 err = ms_read_bytes(host, req->tpc, cfg,
487 req->data_len, req->data, &int_reg);
488 else
489 err = ms_write_bytes(host, req->tpc, cfg,
490 req->data_len, req->data, &int_reg);
491 }
492 if (err < 0)
493 return err;
494
495 if (req->need_card_int) {
496 if (host->ifmode == MEMSTICK_SERIAL) {
497 err = ms_read_bytes(host, MS_TPC_GET_INT,
498 NO_WAIT_INT, 1, &req->int_reg, NULL);
499 if (err < 0)
500 return err;
501 } else {
502
503 if (int_reg & MS_INT_CMDNK)
504 req->int_reg |= MEMSTICK_INT_CMDNAK;
505 if (int_reg & MS_INT_BREQ)
506 req->int_reg |= MEMSTICK_INT_BREQ;
507 if (int_reg & MS_INT_ERR)
508 req->int_reg |= MEMSTICK_INT_ERR;
509 if (int_reg & MS_INT_CED)
510 req->int_reg |= MEMSTICK_INT_CED;
511 }
512 dev_dbg(ms_dev(host), "int_reg: 0x%02x\n", req->int_reg);
513 }
514
515 return 0;
516}
517
518static void rtsx_usb_ms_handle_req(struct work_struct *work)
519{
520 struct rtsx_usb_ms *host = container_of(work,
521 struct rtsx_usb_ms, handle_req);
522 struct rtsx_ucr *ucr = host->ucr;
523 struct memstick_host *msh = host->msh;
524 int rc;
525
526 if (!host->req) {
527 do {
528 rc = memstick_next_req(msh, &host->req);
529 dev_dbg(ms_dev(host), "next req %d\n", rc);
530
531 if (!rc) {
532 mutex_lock(&ucr->dev_mutex);
533
534 if (rtsx_usb_card_exclusive_check(ucr,
535 RTSX_USB_MS_CARD))
536 host->req->error = -EIO;
537 else
538 host->req->error =
539 rtsx_usb_ms_issue_cmd(host);
540
541 mutex_unlock(&ucr->dev_mutex);
542
543 dev_dbg(ms_dev(host), "req result %d\n",
544 host->req->error);
545 }
546 } while (!rc);
547 }
548
549}
550
551static void rtsx_usb_ms_request(struct memstick_host *msh)
552{
553 struct rtsx_usb_ms *host = memstick_priv(msh);
554
555 dev_dbg(ms_dev(host), "--> %s\n", __func__);
556
557 if (!host->eject)
558 schedule_work(&host->handle_req);
559}
560
561static int rtsx_usb_ms_set_param(struct memstick_host *msh,
562 enum memstick_param param, int value)
563{
564 struct rtsx_usb_ms *host = memstick_priv(msh);
565 struct rtsx_ucr *ucr = host->ucr;
566 unsigned int clock = 0;
567 u8 ssc_depth = 0;
568 int err;
569
570 dev_dbg(ms_dev(host), "%s: param = %d, value = %d\n",
571 __func__, param, value);
572
573 mutex_lock(&ucr->dev_mutex);
574
575 err = rtsx_usb_card_exclusive_check(ucr, RTSX_USB_MS_CARD);
576 if (err)
577 goto out;
578
579 switch (param) {
580 case MEMSTICK_POWER:
581 if (value == host->power_mode)
582 break;
583
584 if (value == MEMSTICK_POWER_ON) {
585 pm_runtime_get_sync(ms_dev(host));
586 err = ms_power_on(host);
587 } else if (value == MEMSTICK_POWER_OFF) {
588 err = ms_power_off(host);
589 if (host->msh->card)
590 pm_runtime_put_noidle(ms_dev(host));
591 else
592 pm_runtime_put(ms_dev(host));
593 } else
594 err = -EINVAL;
595 if (!err)
596 host->power_mode = value;
597 break;
598
599 case MEMSTICK_INTERFACE:
600 if (value == MEMSTICK_SERIAL) {
601 clock = 19000000;
602 ssc_depth = SSC_DEPTH_512K;
603 err = rtsx_usb_write_register(ucr, MS_CFG, 0x5A,
604 MS_BUS_WIDTH_1 | PUSH_TIME_DEFAULT);
605 if (err < 0)
606 break;
607 } else if (value == MEMSTICK_PAR4) {
608 clock = 39000000;
609 ssc_depth = SSC_DEPTH_1M;
610
611 err = rtsx_usb_write_register(ucr, MS_CFG, 0x5A,
612 MS_BUS_WIDTH_4 | PUSH_TIME_ODD |
613 MS_NO_CHECK_INT);
614 if (err < 0)
615 break;
616 } else {
617 err = -EINVAL;
618 break;
619 }
620
621 err = rtsx_usb_switch_clock(ucr, clock,
622 ssc_depth, false, true, false);
623 if (err < 0) {
624 dev_dbg(ms_dev(host), "switch clock failed\n");
625 break;
626 }
627
628 host->ssc_depth = ssc_depth;
629 host->clock = clock;
630 host->ifmode = value;
631 break;
632 default:
633 err = -EINVAL;
634 break;
635 }
636out:
637 mutex_unlock(&ucr->dev_mutex);
638
639 /* power-on delay */
640 if (param == MEMSTICK_POWER && value == MEMSTICK_POWER_ON)
641 usleep_range(10000, 12000);
642
643 dev_dbg(ms_dev(host), "%s: return = %d\n", __func__, err);
644 return err;
645}
646
647#ifdef CONFIG_PM_SLEEP
648static int rtsx_usb_ms_suspend(struct device *dev)
649{
650 struct rtsx_usb_ms *host = dev_get_drvdata(dev);
651 struct memstick_host *msh = host->msh;
652
653 dev_dbg(ms_dev(host), "--> %s\n", __func__);
654
655 memstick_suspend_host(msh);
656 return 0;
657}
658
659static int rtsx_usb_ms_resume(struct device *dev)
660{
661 struct rtsx_usb_ms *host = dev_get_drvdata(dev);
662 struct memstick_host *msh = host->msh;
663
664 dev_dbg(ms_dev(host), "--> %s\n", __func__);
665
666 memstick_resume_host(msh);
667 return 0;
668}
669#endif /* CONFIG_PM_SLEEP */
670
671/*
672 * Thread function of ms card slot detection. The thread starts right after
673 * successful host addition. It stops while the driver removal function sets
674 * host->eject true.
675 */
676static int rtsx_usb_detect_ms_card(void *__host)
677{
678 struct rtsx_usb_ms *host = (struct rtsx_usb_ms *)__host;
679 struct rtsx_ucr *ucr = host->ucr;
680 u8 val = 0;
681 int err;
682
683 for (;;) {
684 mutex_lock(&ucr->dev_mutex);
685
686 /* Check pending MS card changes */
687 err = rtsx_usb_read_register(ucr, CARD_INT_PEND, &val);
688 if (err) {
689 mutex_unlock(&ucr->dev_mutex);
690 goto poll_again;
691 }
692
693 /* Clear the pending */
694 rtsx_usb_write_register(ucr, CARD_INT_PEND,
695 XD_INT | MS_INT | SD_INT,
696 XD_INT | MS_INT | SD_INT);
697
698 mutex_unlock(&ucr->dev_mutex);
699
700 if (val & MS_INT) {
701 dev_dbg(ms_dev(host), "MS slot change detected\n");
702 memstick_detect_change(host->msh);
703 }
704
705poll_again:
706 if (host->eject)
707 break;
708
709 msleep(1000);
710 }
711
712 complete(&host->detect_ms_exit);
713 return 0;
714}
715
716static int rtsx_usb_ms_drv_probe(struct platform_device *pdev)
717{
718 struct memstick_host *msh;
719 struct rtsx_usb_ms *host;
720 struct rtsx_ucr *ucr;
721 int err;
722
723 ucr = usb_get_intfdata(to_usb_interface(pdev->dev.parent));
724 if (!ucr)
725 return -ENXIO;
726
727 dev_dbg(&(pdev->dev),
728 "Realtek USB Memstick controller found\n");
729
730 msh = memstick_alloc_host(sizeof(*host), &pdev->dev);
731 if (!msh)
732 return -ENOMEM;
733
734 host = memstick_priv(msh);
735 host->ucr = ucr;
736 host->msh = msh;
737 host->pdev = pdev;
738 host->power_mode = MEMSTICK_POWER_OFF;
739 platform_set_drvdata(pdev, host);
740
741 mutex_init(&host->host_mutex);
742 INIT_WORK(&host->handle_req, rtsx_usb_ms_handle_req);
743
744 init_completion(&host->detect_ms_exit);
745 host->detect_ms = kthread_create(rtsx_usb_detect_ms_card, host,
746 "rtsx_usb_ms_%d", pdev->id);
747 if (IS_ERR(host->detect_ms)) {
748 dev_dbg(&(pdev->dev),
749 "Unable to create polling thread.\n");
750 err = PTR_ERR(host->detect_ms);
751 goto err_out;
752 }
753
754 msh->request = rtsx_usb_ms_request;
755 msh->set_param = rtsx_usb_ms_set_param;
756 msh->caps = MEMSTICK_CAP_PAR4;
757
758 pm_runtime_enable(&pdev->dev);
759 err = memstick_add_host(msh);
760 if (err)
761 goto err_out;
762
763 wake_up_process(host->detect_ms);
764 return 0;
765err_out:
766 memstick_free_host(msh);
767 return err;
768}
769
770static int rtsx_usb_ms_drv_remove(struct platform_device *pdev)
771{
772 struct rtsx_usb_ms *host = platform_get_drvdata(pdev);
773 struct memstick_host *msh;
774 int err;
775
776 msh = host->msh;
777 host->eject = true;
778 cancel_work_sync(&host->handle_req);
779
780 mutex_lock(&host->host_mutex);
781 if (host->req) {
782 dev_dbg(&(pdev->dev),
783 "%s: Controller removed during transfer\n",
784 dev_name(&msh->dev));
785 host->req->error = -ENOMEDIUM;
786 do {
787 err = memstick_next_req(msh, &host->req);
788 if (!err)
789 host->req->error = -ENOMEDIUM;
790 } while (!err);
791 }
792 mutex_unlock(&host->host_mutex);
793
794 wait_for_completion(&host->detect_ms_exit);
795 memstick_remove_host(msh);
796 memstick_free_host(msh);
797
798 /* Balance possible unbalanced usage count
799 * e.g. unconditional module removal
800 */
801 if (pm_runtime_active(ms_dev(host)))
802 pm_runtime_put(ms_dev(host));
803
804 pm_runtime_disable(&pdev->dev);
805 platform_set_drvdata(pdev, NULL);
806
807 dev_dbg(&(pdev->dev),
808 ": Realtek USB Memstick controller has been removed\n");
809
810 return 0;
811}
812
813static SIMPLE_DEV_PM_OPS(rtsx_usb_ms_pm_ops,
814 rtsx_usb_ms_suspend, rtsx_usb_ms_resume);
815
816static struct platform_device_id rtsx_usb_ms_ids[] = {
817 {
818 .name = "rtsx_usb_ms",
819 }, {
820 /* sentinel */
821 }
822};
823MODULE_DEVICE_TABLE(platform, rtsx_usb_ms_ids);
824
825static struct platform_driver rtsx_usb_ms_driver = {
826 .probe = rtsx_usb_ms_drv_probe,
827 .remove = rtsx_usb_ms_drv_remove,
828 .id_table = rtsx_usb_ms_ids,
829 .driver = {
830 .owner = THIS_MODULE,
831 .name = "rtsx_usb_ms",
832 .pm = &rtsx_usb_ms_pm_ops,
833 },
834};
835module_platform_driver(rtsx_usb_ms_driver);
836
837MODULE_LICENSE("GPL v2");
838MODULE_AUTHOR("Roger Tseng <rogerable@realtek.com>");
839MODULE_DESCRIPTION("Realtek USB Memstick Card Host Driver");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 6deb8a11c12f..ee8204cc31e9 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -67,6 +67,18 @@ config MFD_BCM590XX
67 help 67 help
68 Support for the BCM590xx PMUs from Broadcom 68 Support for the BCM590xx PMUs from Broadcom
69 69
70config MFD_AXP20X
71 bool "X-Powers AXP20X"
72 select MFD_CORE
73 select REGMAP_I2C
74 select REGMAP_IRQ
75 depends on I2C=y
76 help
77 If you say Y here you get support for the X-Powers AXP202 and AXP209.
78 This driver include only the core APIs. You have to select individual
79 components like regulators or the PEK (Power Enable Key) under the
80 corresponding menus.
81
70config MFD_CROS_EC 82config MFD_CROS_EC
71 tristate "ChromeOS Embedded Controller" 83 tristate "ChromeOS Embedded Controller"
72 select MFD_CORE 84 select MFD_CORE
@@ -250,6 +262,16 @@ config MFD_INTEL_MSIC
250 Passage) chip. This chip embeds audio, battery, GPIO, etc. 262 Passage) chip. This chip embeds audio, battery, GPIO, etc.
251 devices used in Intel Medfield platforms. 263 devices used in Intel Medfield platforms.
252 264
265config MFD_IPAQ_MICRO
266 bool "Atmel Micro ASIC (iPAQ h3100/h3600/h3700) Support"
267 depends on SA1100_H3100 || SA1100_H3600
268 select MFD_CORE
269 help
270 Select this to get support for the Microcontroller found in
271 the Compaq iPAQ handheld computers. This is an Atmel
272 AT90LS8535 microcontroller flashed with a special iPAQ
273 firmware using the custom protocol implemented in this driver.
274
253config MFD_JANZ_CMODIO 275config MFD_JANZ_CMODIO
254 tristate "Janz CMOD-IO PCI MODULbus Carrier Board" 276 tristate "Janz CMOD-IO PCI MODULbus Carrier Board"
255 select MFD_CORE 277 select MFD_CORE
@@ -675,6 +697,7 @@ config MFD_DB8500_PRCMU
675config MFD_STMPE 697config MFD_STMPE
676 bool "STMicroelectronics STMPE" 698 bool "STMicroelectronics STMPE"
677 depends on (I2C=y || SPI_MASTER=y) 699 depends on (I2C=y || SPI_MASTER=y)
700 depends on OF
678 select MFD_CORE 701 select MFD_CORE
679 help 702 help
680 Support for the STMPE family of I/O Expanders from 703 Support for the STMPE family of I/O Expanders from
@@ -719,6 +742,14 @@ config MFD_STA2X11
719 select MFD_CORE 742 select MFD_CORE
720 select REGMAP_MMIO 743 select REGMAP_MMIO
721 744
745config MFD_SUN6I_PRCM
746 bool "Allwinner A31 PRCM controller"
747 depends on ARCH_SUNXI
748 select MFD_CORE
749 help
750 Support for the PRCM (Power/Reset/Clock Management) unit available
751 in A31 SoC.
752
722config MFD_SYSCON 753config MFD_SYSCON
723 bool "System Controller Register R/W Based on Regmap" 754 bool "System Controller Register R/W Based on Regmap"
724 select REGMAP_MMIO 755 select REGMAP_MMIO
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index cec3487b539e..8afedba535c7 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_MFD_STA2X11) += sta2x11-mfd.o
29obj-$(CONFIG_MFD_STMPE) += stmpe.o 29obj-$(CONFIG_MFD_STMPE) += stmpe.o
30obj-$(CONFIG_STMPE_I2C) += stmpe-i2c.o 30obj-$(CONFIG_STMPE_I2C) += stmpe-i2c.o
31obj-$(CONFIG_STMPE_SPI) += stmpe-spi.o 31obj-$(CONFIG_STMPE_SPI) += stmpe-spi.o
32obj-$(CONFIG_MFD_SUN6I_PRCM) += sun6i-prcm.o
32obj-$(CONFIG_MFD_TC3589X) += tc3589x.o 33obj-$(CONFIG_MFD_TC3589X) += tc3589x.o
33obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o 34obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o
34obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o 35obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o
@@ -102,6 +103,7 @@ obj-$(CONFIG_PMIC_DA9052) += da9052-irq.o
102obj-$(CONFIG_PMIC_DA9052) += da9052-core.o 103obj-$(CONFIG_PMIC_DA9052) += da9052-core.o
103obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o 104obj-$(CONFIG_MFD_DA9052_SPI) += da9052-spi.o
104obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o 105obj-$(CONFIG_MFD_DA9052_I2C) += da9052-i2c.o
106obj-$(CONFIG_MFD_AXP20X) += axp20x.o
105 107
106obj-$(CONFIG_MFD_LP3943) += lp3943.o 108obj-$(CONFIG_MFD_LP3943) += lp3943.o
107obj-$(CONFIG_MFD_LP8788) += lp8788.o lp8788-irq.o 109obj-$(CONFIG_MFD_LP8788) += lp8788.o lp8788-irq.o
@@ -166,3 +168,4 @@ obj-$(CONFIG_MFD_RETU) += retu-mfd.o
166obj-$(CONFIG_MFD_AS3711) += as3711.o 168obj-$(CONFIG_MFD_AS3711) += as3711.o
167obj-$(CONFIG_MFD_AS3722) += as3722.o 169obj-$(CONFIG_MFD_AS3722) += as3722.o
168obj-$(CONFIG_MFD_STW481X) += stw481x.o 170obj-$(CONFIG_MFD_STW481X) += stw481x.o
171obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
diff --git a/drivers/mfd/abx500-core.c b/drivers/mfd/abx500-core.c
index f3a15aa54d7b..fe418995108c 100644
--- a/drivers/mfd/abx500-core.c
+++ b/drivers/mfd/abx500-core.c
@@ -151,22 +151,6 @@ int abx500_startup_irq_enabled(struct device *dev, unsigned int irq)
151} 151}
152EXPORT_SYMBOL(abx500_startup_irq_enabled); 152EXPORT_SYMBOL(abx500_startup_irq_enabled);
153 153
154void abx500_dump_all_banks(void)
155{
156 struct abx500_ops *ops;
157 struct device dummy_child = {NULL};
158 struct abx500_device_entry *dev_entry;
159
160 list_for_each_entry(dev_entry, &abx500_list, list) {
161 dummy_child.parent = dev_entry->dev;
162 ops = &dev_entry->ops;
163
164 if ((ops != NULL) && (ops->dump_all_banks != NULL))
165 ops->dump_all_banks(&dummy_child);
166 }
167}
168EXPORT_SYMBOL(abx500_dump_all_banks);
169
170MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>"); 154MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>");
171MODULE_DESCRIPTION("ABX500 core driver"); 155MODULE_DESCRIPTION("ABX500 core driver");
172MODULE_LICENSE("GPL"); 156MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
index 07e6e27be23c..cfc191abae4a 100644
--- a/drivers/mfd/arizona-core.c
+++ b/drivers/mfd/arizona-core.c
@@ -583,6 +583,7 @@ static const char *wm5102_supplies[] = {
583 "CPVDD", 583 "CPVDD",
584 "SPKVDDL", 584 "SPKVDDL",
585 "SPKVDDR", 585 "SPKVDDR",
586 "MICVDD",
586}; 587};
587 588
588static const struct mfd_cell wm5102_devs[] = { 589static const struct mfd_cell wm5102_devs[] = {
diff --git a/drivers/mfd/arizona-irq.c b/drivers/mfd/arizona-irq.c
index 88758ab9402b..17102f589100 100644
--- a/drivers/mfd/arizona-irq.c
+++ b/drivers/mfd/arizona-irq.c
@@ -285,7 +285,7 @@ int arizona_irq_init(struct arizona *arizona)
285 IRQF_ONESHOT, -1, irq, 285 IRQF_ONESHOT, -1, irq,
286 &arizona->irq_chip); 286 &arizona->irq_chip);
287 if (ret != 0) { 287 if (ret != 0) {
288 dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", ret); 288 dev_err(arizona->dev, "Failed to add main IRQs: %d\n", ret);
289 goto err_aod; 289 goto err_aod;
290 } 290 }
291 291
diff --git a/drivers/mfd/as3711.c b/drivers/mfd/as3711.c
index ec684fcedb42..d9706ede8d39 100644
--- a/drivers/mfd/as3711.c
+++ b/drivers/mfd/as3711.c
@@ -114,7 +114,7 @@ static const struct regmap_config as3711_regmap_config = {
114}; 114};
115 115
116#ifdef CONFIG_OF 116#ifdef CONFIG_OF
117static struct of_device_id as3711_of_match[] = { 117static const struct of_device_id as3711_of_match[] = {
118 {.compatible = "ams,as3711",}, 118 {.compatible = "ams,as3711",},
119 {} 119 {}
120}; 120};
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
new file mode 100644
index 000000000000..dee653989e3a
--- /dev/null
+++ b/drivers/mfd/axp20x.c
@@ -0,0 +1,258 @@
1/*
2 * axp20x.c - MFD core driver for the X-Powers AXP202 and AXP209
3 *
4 * AXP20x comprises an adaptive USB-Compatible PWM charger, 2 BUCK DC-DC
5 * converters, 5 LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as 4 configurable GPIOs.
7 *
8 * Author: Carlo Caione <carlo@caione.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/err.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23#include <linux/regulator/consumer.h>
24#include <linux/mfd/axp20x.h>
25#include <linux/mfd/core.h>
26#include <linux/of_device.h>
27#include <linux/of_irq.h>
28
29#define AXP20X_OFF 0x80
30
31static const struct regmap_range axp20x_writeable_ranges[] = {
32 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
33 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
34};
35
36static const struct regmap_range axp20x_volatile_ranges[] = {
37 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
38};
39
40static const struct regmap_access_table axp20x_writeable_table = {
41 .yes_ranges = axp20x_writeable_ranges,
42 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
43};
44
45static const struct regmap_access_table axp20x_volatile_table = {
46 .yes_ranges = axp20x_volatile_ranges,
47 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
48};
49
50static struct resource axp20x_pek_resources[] = {
51 {
52 .name = "PEK_DBR",
53 .start = AXP20X_IRQ_PEK_RIS_EDGE,
54 .end = AXP20X_IRQ_PEK_RIS_EDGE,
55 .flags = IORESOURCE_IRQ,
56 }, {
57 .name = "PEK_DBF",
58 .start = AXP20X_IRQ_PEK_FAL_EDGE,
59 .end = AXP20X_IRQ_PEK_FAL_EDGE,
60 .flags = IORESOURCE_IRQ,
61 },
62};
63
64static const struct regmap_config axp20x_regmap_config = {
65 .reg_bits = 8,
66 .val_bits = 8,
67 .wr_table = &axp20x_writeable_table,
68 .volatile_table = &axp20x_volatile_table,
69 .max_register = AXP20X_FG_RES,
70 .cache_type = REGCACHE_RBTREE,
71};
72
73#define AXP20X_IRQ(_irq, _off, _mask) \
74 [AXP20X_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
75
76static const struct regmap_irq axp20x_regmap_irqs[] = {
77 AXP20X_IRQ(ACIN_OVER_V, 0, 7),
78 AXP20X_IRQ(ACIN_PLUGIN, 0, 6),
79 AXP20X_IRQ(ACIN_REMOVAL, 0, 5),
80 AXP20X_IRQ(VBUS_OVER_V, 0, 4),
81 AXP20X_IRQ(VBUS_PLUGIN, 0, 3),
82 AXP20X_IRQ(VBUS_REMOVAL, 0, 2),
83 AXP20X_IRQ(VBUS_V_LOW, 0, 1),
84 AXP20X_IRQ(BATT_PLUGIN, 1, 7),
85 AXP20X_IRQ(BATT_REMOVAL, 1, 6),
86 AXP20X_IRQ(BATT_ENT_ACT_MODE, 1, 5),
87 AXP20X_IRQ(BATT_EXIT_ACT_MODE, 1, 4),
88 AXP20X_IRQ(CHARG, 1, 3),
89 AXP20X_IRQ(CHARG_DONE, 1, 2),
90 AXP20X_IRQ(BATT_TEMP_HIGH, 1, 1),
91 AXP20X_IRQ(BATT_TEMP_LOW, 1, 0),
92 AXP20X_IRQ(DIE_TEMP_HIGH, 2, 7),
93 AXP20X_IRQ(CHARG_I_LOW, 2, 6),
94 AXP20X_IRQ(DCDC1_V_LONG, 2, 5),
95 AXP20X_IRQ(DCDC2_V_LONG, 2, 4),
96 AXP20X_IRQ(DCDC3_V_LONG, 2, 3),
97 AXP20X_IRQ(PEK_SHORT, 2, 1),
98 AXP20X_IRQ(PEK_LONG, 2, 0),
99 AXP20X_IRQ(N_OE_PWR_ON, 3, 7),
100 AXP20X_IRQ(N_OE_PWR_OFF, 3, 6),
101 AXP20X_IRQ(VBUS_VALID, 3, 5),
102 AXP20X_IRQ(VBUS_NOT_VALID, 3, 4),
103 AXP20X_IRQ(VBUS_SESS_VALID, 3, 3),
104 AXP20X_IRQ(VBUS_SESS_END, 3, 2),
105 AXP20X_IRQ(LOW_PWR_LVL1, 3, 1),
106 AXP20X_IRQ(LOW_PWR_LVL2, 3, 0),
107 AXP20X_IRQ(TIMER, 4, 7),
108 AXP20X_IRQ(PEK_RIS_EDGE, 4, 6),
109 AXP20X_IRQ(PEK_FAL_EDGE, 4, 5),
110 AXP20X_IRQ(GPIO3_INPUT, 4, 3),
111 AXP20X_IRQ(GPIO2_INPUT, 4, 2),
112 AXP20X_IRQ(GPIO1_INPUT, 4, 1),
113 AXP20X_IRQ(GPIO0_INPUT, 4, 0),
114};
115
116static const struct of_device_id axp20x_of_match[] = {
117 { .compatible = "x-powers,axp202", .data = (void *) AXP202_ID },
118 { .compatible = "x-powers,axp209", .data = (void *) AXP209_ID },
119 { },
120};
121MODULE_DEVICE_TABLE(of, axp20x_of_match);
122
123/*
124 * This is useless for OF-enabled devices, but it is needed by I2C subsystem
125 */
126static const struct i2c_device_id axp20x_i2c_id[] = {
127 { },
128};
129MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id);
130
131static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
132 .name = "axp20x_irq_chip",
133 .status_base = AXP20X_IRQ1_STATE,
134 .ack_base = AXP20X_IRQ1_STATE,
135 .mask_base = AXP20X_IRQ1_EN,
136 .num_regs = 5,
137 .irqs = axp20x_regmap_irqs,
138 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
139 .mask_invert = true,
140 .init_ack_masked = true,
141};
142
143static const char * const axp20x_supplies[] = {
144 "acin",
145 "vin2",
146 "vin3",
147 "ldo24in",
148 "ldo3in",
149 "ldo5in",
150};
151
152static struct mfd_cell axp20x_cells[] = {
153 {
154 .name = "axp20x-pek",
155 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
156 .resources = axp20x_pek_resources,
157 }, {
158 .name = "axp20x-regulator",
159 .parent_supplies = axp20x_supplies,
160 .num_parent_supplies = ARRAY_SIZE(axp20x_supplies),
161 },
162};
163
164static struct axp20x_dev *axp20x_pm_power_off;
165static void axp20x_power_off(void)
166{
167 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
168 AXP20X_OFF);
169}
170
171static int axp20x_i2c_probe(struct i2c_client *i2c,
172 const struct i2c_device_id *id)
173{
174 struct axp20x_dev *axp20x;
175 const struct of_device_id *of_id;
176 int ret;
177
178 axp20x = devm_kzalloc(&i2c->dev, sizeof(*axp20x), GFP_KERNEL);
179 if (!axp20x)
180 return -ENOMEM;
181
182 of_id = of_match_device(axp20x_of_match, &i2c->dev);
183 if (!of_id) {
184 dev_err(&i2c->dev, "Unable to setup AXP20X data\n");
185 return -ENODEV;
186 }
187 axp20x->variant = (long) of_id->data;
188
189 axp20x->i2c_client = i2c;
190 axp20x->dev = &i2c->dev;
191 dev_set_drvdata(axp20x->dev, axp20x);
192
193 axp20x->regmap = devm_regmap_init_i2c(i2c, &axp20x_regmap_config);
194 if (IS_ERR(axp20x->regmap)) {
195 ret = PTR_ERR(axp20x->regmap);
196 dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
197 return ret;
198 }
199
200 ret = regmap_add_irq_chip(axp20x->regmap, i2c->irq,
201 IRQF_ONESHOT | IRQF_SHARED, -1,
202 &axp20x_regmap_irq_chip,
203 &axp20x->regmap_irqc);
204 if (ret) {
205 dev_err(&i2c->dev, "failed to add irq chip: %d\n", ret);
206 return ret;
207 }
208
209 ret = mfd_add_devices(axp20x->dev, -1, axp20x_cells,
210 ARRAY_SIZE(axp20x_cells), NULL, 0, NULL);
211
212 if (ret) {
213 dev_err(&i2c->dev, "failed to add MFD devices: %d\n", ret);
214 regmap_del_irq_chip(i2c->irq, axp20x->regmap_irqc);
215 return ret;
216 }
217
218 if (!pm_power_off) {
219 axp20x_pm_power_off = axp20x;
220 pm_power_off = axp20x_power_off;
221 }
222
223 dev_info(&i2c->dev, "AXP20X driver loaded\n");
224
225 return 0;
226}
227
228static int axp20x_i2c_remove(struct i2c_client *i2c)
229{
230 struct axp20x_dev *axp20x = i2c_get_clientdata(i2c);
231
232 if (axp20x == axp20x_pm_power_off) {
233 axp20x_pm_power_off = NULL;
234 pm_power_off = NULL;
235 }
236
237 mfd_remove_devices(axp20x->dev);
238 regmap_del_irq_chip(axp20x->i2c_client->irq, axp20x->regmap_irqc);
239
240 return 0;
241}
242
243static struct i2c_driver axp20x_i2c_driver = {
244 .driver = {
245 .name = "axp20x",
246 .owner = THIS_MODULE,
247 .of_match_table = of_match_ptr(axp20x_of_match),
248 },
249 .probe = axp20x_i2c_probe,
250 .remove = axp20x_i2c_remove,
251 .id_table = axp20x_i2c_id,
252};
253
254module_i2c_driver(axp20x_i2c_driver);
255
256MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
257MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
258MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/bcm590xx.c b/drivers/mfd/bcm590xx.c
index 43cba1a1973c..e334de000e8c 100644
--- a/drivers/mfd/bcm590xx.c
+++ b/drivers/mfd/bcm590xx.c
@@ -96,6 +96,12 @@ err:
96 return ret; 96 return ret;
97} 97}
98 98
99static int bcm590xx_i2c_remove(struct i2c_client *i2c)
100{
101 mfd_remove_devices(&i2c->dev);
102 return 0;
103}
104
99static const struct of_device_id bcm590xx_of_match[] = { 105static const struct of_device_id bcm590xx_of_match[] = {
100 { .compatible = "brcm,bcm59056" }, 106 { .compatible = "brcm,bcm59056" },
101 { } 107 { }
@@ -115,6 +121,7 @@ static struct i2c_driver bcm590xx_i2c_driver = {
115 .of_match_table = of_match_ptr(bcm590xx_of_match), 121 .of_match_table = of_match_ptr(bcm590xx_of_match),
116 }, 122 },
117 .probe = bcm590xx_i2c_probe, 123 .probe = bcm590xx_i2c_probe,
124 .remove = bcm590xx_i2c_remove,
118 .id_table = bcm590xx_i2c_id, 125 .id_table = bcm590xx_i2c_id,
119}; 126};
120module_i2c_driver(bcm590xx_i2c_driver); 127module_i2c_driver(bcm590xx_i2c_driver);
@@ -122,4 +129,4 @@ module_i2c_driver(bcm590xx_i2c_driver);
122MODULE_AUTHOR("Matt Porter <mporter@linaro.org>"); 129MODULE_AUTHOR("Matt Porter <mporter@linaro.org>");
123MODULE_DESCRIPTION("BCM590xx multi-function driver"); 130MODULE_DESCRIPTION("BCM590xx multi-function driver");
124MODULE_LICENSE("GPL v2"); 131MODULE_LICENSE("GPL v2");
125MODULE_ALIAS("platform:bcm590xx"); 132MODULE_ALIAS("i2c:bcm590xx");
diff --git a/drivers/mfd/cros_ec.c b/drivers/mfd/cros_ec.c
index 783fe2e73e1e..38fe9bf0d169 100644
--- a/drivers/mfd/cros_ec.c
+++ b/drivers/mfd/cros_ec.c
@@ -30,7 +30,7 @@ int cros_ec_prepare_tx(struct cros_ec_device *ec_dev,
30 uint8_t *out; 30 uint8_t *out;
31 int csum, i; 31 int csum, i;
32 32
33 BUG_ON(msg->out_len > EC_HOST_PARAM_SIZE); 33 BUG_ON(msg->out_len > EC_PROTO2_MAX_PARAM_SIZE);
34 out = ec_dev->dout; 34 out = ec_dev->dout;
35 out[0] = EC_CMD_VERSION0 + msg->version; 35 out[0] = EC_CMD_VERSION0 + msg->version;
36 out[1] = msg->cmd; 36 out[1] = msg->cmd;
@@ -90,6 +90,11 @@ static const struct mfd_cell cros_devs[] = {
90 .id = 1, 90 .id = 1,
91 .of_compatible = "google,cros-ec-keyb", 91 .of_compatible = "google,cros-ec-keyb",
92 }, 92 },
93 {
94 .name = "cros-ec-i2c-tunnel",
95 .id = 2,
96 .of_compatible = "google,cros-ec-i2c-tunnel",
97 },
93}; 98};
94 99
95int cros_ec_register(struct cros_ec_device *ec_dev) 100int cros_ec_register(struct cros_ec_device *ec_dev)
@@ -184,3 +189,6 @@ int cros_ec_resume(struct cros_ec_device *ec_dev)
184EXPORT_SYMBOL(cros_ec_resume); 189EXPORT_SYMBOL(cros_ec_resume);
185 190
186#endif 191#endif
192
193MODULE_LICENSE("GPL");
194MODULE_DESCRIPTION("ChromeOS EC core driver");
diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c
index 84af8d7a4295..0b8d32829166 100644
--- a/drivers/mfd/cros_ec_spi.c
+++ b/drivers/mfd/cros_ec_spi.c
@@ -39,14 +39,22 @@
39#define EC_MSG_PREAMBLE_COUNT 32 39#define EC_MSG_PREAMBLE_COUNT 32
40 40
41/* 41/*
42 * We must get a response from the EC in 5ms. This is a very long 42 * Allow for a long time for the EC to respond. We support i2c
43 * time, but the flash write command can take 2-3ms. The EC command 43 * tunneling and support fairly long messages for the tunnel (249
44 * processing is currently not very fast (about 500us). We could 44 * bytes long at the moment). If we're talking to a 100 kHz device
45 * look at speeding this up and making the flash write command a 45 * on the other end and need to transfer ~256 bytes, then we need:
46 * 'slow' command, requiring a GET_STATUS wait loop, like flash 46 * 10 us/bit * ~10 bits/byte * ~256 bytes = ~25ms
47 * erase. 47 *
48 */ 48 * We'll wait 4 times that to handle clock stretching and other
49#define EC_MSG_DEADLINE_MS 5 49 * paranoia.
50 *
51 * It's pretty unlikely that we'll really see a 249 byte tunnel in
52 * anything other than testing. If this was more common we might
53 * consider having slow commands like this require a GET_STATUS
54 * wait loop. The 'flash write' command would be another candidate
55 * for this, clocking in at 2-3ms.
56 */
57#define EC_MSG_DEADLINE_MS 100
50 58
51/* 59/*
52 * Time between raising the SPI chip select (for the end of a 60 * Time between raising the SPI chip select (for the end of a
@@ -65,11 +73,13 @@
65 * if no record 73 * if no record
66 * @end_of_msg_delay: used to set the delay_usecs on the spi_transfer that 74 * @end_of_msg_delay: used to set the delay_usecs on the spi_transfer that
67 * is sent when we want to turn off CS at the end of a transaction. 75 * is sent when we want to turn off CS at the end of a transaction.
76 * @lock: mutex to ensure only one user of cros_ec_command_spi_xfer at a time
68 */ 77 */
69struct cros_ec_spi { 78struct cros_ec_spi {
70 struct spi_device *spi; 79 struct spi_device *spi;
71 s64 last_transfer_ns; 80 s64 last_transfer_ns;
72 unsigned int end_of_msg_delay; 81 unsigned int end_of_msg_delay;
82 struct mutex lock;
73}; 83};
74 84
75static void debug_packet(struct device *dev, const char *name, u8 *ptr, 85static void debug_packet(struct device *dev, const char *name, u8 *ptr,
@@ -111,7 +121,9 @@ static int cros_ec_spi_receive_response(struct cros_ec_device *ec_dev,
111 121
112 /* Receive data until we see the header byte */ 122 /* Receive data until we see the header byte */
113 deadline = jiffies + msecs_to_jiffies(EC_MSG_DEADLINE_MS); 123 deadline = jiffies + msecs_to_jiffies(EC_MSG_DEADLINE_MS);
114 do { 124 while (true) {
125 unsigned long start_jiffies = jiffies;
126
115 memset(&trans, 0, sizeof(trans)); 127 memset(&trans, 0, sizeof(trans));
116 trans.cs_change = 1; 128 trans.cs_change = 1;
117 trans.rx_buf = ptr = ec_dev->din; 129 trans.rx_buf = ptr = ec_dev->din;
@@ -132,12 +144,19 @@ static int cros_ec_spi_receive_response(struct cros_ec_device *ec_dev,
132 break; 144 break;
133 } 145 }
134 } 146 }
147 if (ptr != end)
148 break;
135 149
136 if (time_after(jiffies, deadline)) { 150 /*
151 * Use the time at the start of the loop as a timeout. This
152 * gives us one last shot at getting the transfer and is useful
153 * in case we got context switched out for a while.
154 */
155 if (time_after(start_jiffies, deadline)) {
137 dev_warn(ec_dev->dev, "EC failed to respond in time\n"); 156 dev_warn(ec_dev->dev, "EC failed to respond in time\n");
138 return -ETIMEDOUT; 157 return -ETIMEDOUT;
139 } 158 }
140 } while (ptr == end); 159 }
141 160
142 /* 161 /*
143 * ptr now points to the header byte. Copy any valid data to the 162 * ptr now points to the header byte. Copy any valid data to the
@@ -208,6 +227,13 @@ static int cros_ec_command_spi_xfer(struct cros_ec_device *ec_dev,
208 int ret = 0, final_ret; 227 int ret = 0, final_ret;
209 struct timespec ts; 228 struct timespec ts;
210 229
230 /*
231 * We have the shared ec_dev buffer plus we do lots of separate spi_sync
232 * calls, so we need to make sure only one person is using this at a
233 * time.
234 */
235 mutex_lock(&ec_spi->lock);
236
211 len = cros_ec_prepare_tx(ec_dev, ec_msg); 237 len = cros_ec_prepare_tx(ec_dev, ec_msg);
212 dev_dbg(ec_dev->dev, "prepared, len=%d\n", len); 238 dev_dbg(ec_dev->dev, "prepared, len=%d\n", len);
213 239
@@ -219,7 +245,7 @@ static int cros_ec_command_spi_xfer(struct cros_ec_device *ec_dev,
219 ktime_get_ts(&ts); 245 ktime_get_ts(&ts);
220 delay = timespec_to_ns(&ts) - ec_spi->last_transfer_ns; 246 delay = timespec_to_ns(&ts) - ec_spi->last_transfer_ns;
221 if (delay < EC_SPI_RECOVERY_TIME_NS) 247 if (delay < EC_SPI_RECOVERY_TIME_NS)
222 ndelay(delay); 248 ndelay(EC_SPI_RECOVERY_TIME_NS - delay);
223 } 249 }
224 250
225 /* Transmit phase - send our message */ 251 /* Transmit phase - send our message */
@@ -260,7 +286,7 @@ static int cros_ec_command_spi_xfer(struct cros_ec_device *ec_dev,
260 ret = final_ret; 286 ret = final_ret;
261 if (ret < 0) { 287 if (ret < 0) {
262 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret); 288 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
263 return ret; 289 goto exit;
264 } 290 }
265 291
266 /* check response error code */ 292 /* check response error code */
@@ -269,14 +295,16 @@ static int cros_ec_command_spi_xfer(struct cros_ec_device *ec_dev,
269 dev_warn(ec_dev->dev, "command 0x%02x returned an error %d\n", 295 dev_warn(ec_dev->dev, "command 0x%02x returned an error %d\n",
270 ec_msg->cmd, ptr[0]); 296 ec_msg->cmd, ptr[0]);
271 debug_packet(ec_dev->dev, "in_err", ptr, len); 297 debug_packet(ec_dev->dev, "in_err", ptr, len);
272 return -EINVAL; 298 ret = -EINVAL;
299 goto exit;
273 } 300 }
274 len = ptr[1]; 301 len = ptr[1];
275 sum = ptr[0] + ptr[1]; 302 sum = ptr[0] + ptr[1];
276 if (len > ec_msg->in_len) { 303 if (len > ec_msg->in_len) {
277 dev_err(ec_dev->dev, "packet too long (%d bytes, expected %d)", 304 dev_err(ec_dev->dev, "packet too long (%d bytes, expected %d)",
278 len, ec_msg->in_len); 305 len, ec_msg->in_len);
279 return -ENOSPC; 306 ret = -ENOSPC;
307 goto exit;
280 } 308 }
281 309
282 /* copy response packet payload and compute checksum */ 310 /* copy response packet payload and compute checksum */
@@ -293,10 +321,14 @@ static int cros_ec_command_spi_xfer(struct cros_ec_device *ec_dev,
293 dev_err(ec_dev->dev, 321 dev_err(ec_dev->dev,
294 "bad packet checksum, expected %02x, got %02x\n", 322 "bad packet checksum, expected %02x, got %02x\n",
295 sum, ptr[len + 2]); 323 sum, ptr[len + 2]);
296 return -EBADMSG; 324 ret = -EBADMSG;
325 goto exit;
297 } 326 }
298 327
299 return 0; 328 ret = 0;
329exit:
330 mutex_unlock(&ec_spi->lock);
331 return ret;
300} 332}
301 333
302static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device *dev) 334static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device *dev)
@@ -327,6 +359,7 @@ static int cros_ec_spi_probe(struct spi_device *spi)
327 if (ec_spi == NULL) 359 if (ec_spi == NULL)
328 return -ENOMEM; 360 return -ENOMEM;
329 ec_spi->spi = spi; 361 ec_spi->spi = spi;
362 mutex_init(&ec_spi->lock);
330 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL); 363 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL);
331 if (!ec_dev) 364 if (!ec_dev)
332 return -ENOMEM; 365 return -ENOMEM;
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index b11fdd63eecd..193cf168ba84 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -2300,9 +2300,6 @@ int prcmu_ac_wake_req(void)
2300 2300
2301 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2301 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2302 msecs_to_jiffies(5000))) { 2302 msecs_to_jiffies(5000))) {
2303#if defined(CONFIG_DBX500_PRCMU_DEBUG)
2304 db8500_prcmu_debug_dump(__func__, true, true);
2305#endif
2306 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2303 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2307 __func__); 2304 __func__);
2308 ret = -EFAULT; 2305 ret = -EFAULT;
@@ -3112,7 +3109,7 @@ static int db8500_prcmu_register_ab8500(struct device *parent,
3112{ 3109{
3113 struct device_node *np; 3110 struct device_node *np;
3114 struct resource ab8500_resource; 3111 struct resource ab8500_resource;
3115 struct mfd_cell ab8500_cell = { 3112 const struct mfd_cell ab8500_cell = {
3116 .name = "ab8500-core", 3113 .name = "ab8500-core",
3117 .of_compatible = "stericsson,ab8500", 3114 .of_compatible = "stericsson,ab8500",
3118 .id = AB8500_VERSION_AB8500, 3115 .id = AB8500_VERSION_AB8500,
diff --git a/drivers/mfd/ipaq-micro.c b/drivers/mfd/ipaq-micro.c
new file mode 100644
index 000000000000..7e50fe0118e3
--- /dev/null
+++ b/drivers/mfd/ipaq-micro.c
@@ -0,0 +1,482 @@
1/*
2 * Compaq iPAQ h3xxx Atmel microcontroller companion support
3 *
4 * This is an Atmel AT90LS8535 with a special flashed-in firmware that
5 * implements the special protocol used by this driver.
6 *
7 * based on previous kernel 2.4 version by Andrew Christian
8 * Author : Alessandro Gardich <gremlin@gremlin.it>
9 * Author : Dmitry Artamonow <mad_soft@inbox.ru>
10 * Author : Linus Walleij <linus.walleij@linaro.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/pm.h>
21#include <linux/delay.h>
22#include <linux/device.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25#include <linux/mfd/core.h>
26#include <linux/mfd/ipaq-micro.h>
27#include <linux/string.h>
28#include <linux/random.h>
29#include <linux/slab.h>
30#include <linux/list.h>
31
32#include <mach/hardware.h>
33
34static void ipaq_micro_trigger_tx(struct ipaq_micro *micro)
35{
36 struct ipaq_micro_txdev *tx = &micro->tx;
37 struct ipaq_micro_msg *msg = micro->msg;
38 int i, bp;
39 u8 checksum;
40 u32 val;
41
42 bp = 0;
43 tx->buf[bp++] = CHAR_SOF;
44
45 checksum = ((msg->id & 0x0f) << 4) | (msg->tx_len & 0x0f);
46 tx->buf[bp++] = checksum;
47
48 for (i = 0; i < msg->tx_len; i++) {
49 tx->buf[bp++] = msg->tx_data[i];
50 checksum += msg->tx_data[i];
51 }
52
53 tx->buf[bp++] = checksum;
54 tx->len = bp;
55 tx->index = 0;
56 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
57 tx->buf, tx->len, true);
58
59 /* Enable interrupt */
60 val = readl(micro->base + UTCR3);
61 val |= UTCR3_TIE;
62 writel(val, micro->base + UTCR3);
63}
64
65int ipaq_micro_tx_msg(struct ipaq_micro *micro, struct ipaq_micro_msg *msg)
66{
67 unsigned long flags;
68
69 dev_dbg(micro->dev, "TX msg: %02x, %d bytes\n", msg->id, msg->tx_len);
70
71 spin_lock_irqsave(&micro->lock, flags);
72 if (micro->msg) {
73 list_add_tail(&msg->node, &micro->queue);
74 spin_unlock_irqrestore(&micro->lock, flags);
75 return 0;
76 }
77 micro->msg = msg;
78 ipaq_micro_trigger_tx(micro);
79 spin_unlock_irqrestore(&micro->lock, flags);
80 return 0;
81}
82EXPORT_SYMBOL(ipaq_micro_tx_msg);
83
84static void micro_rx_msg(struct ipaq_micro *micro, u8 id, int len, u8 *data)
85{
86 int i;
87
88 dev_dbg(micro->dev, "RX msg: %02x, %d bytes\n", id, len);
89
90 spin_lock(&micro->lock);
91 switch (id) {
92 case MSG_VERSION:
93 case MSG_EEPROM_READ:
94 case MSG_EEPROM_WRITE:
95 case MSG_BACKLIGHT:
96 case MSG_NOTIFY_LED:
97 case MSG_THERMAL_SENSOR:
98 case MSG_BATTERY:
99 /* Handle synchronous messages */
100 if (micro->msg && micro->msg->id == id) {
101 struct ipaq_micro_msg *msg = micro->msg;
102
103 memcpy(msg->rx_data, data, len);
104 msg->rx_len = len;
105 complete(&micro->msg->ack);
106 if (!list_empty(&micro->queue)) {
107 micro->msg = list_entry(micro->queue.next,
108 struct ipaq_micro_msg,
109 node);
110 list_del_init(&micro->msg->node);
111 ipaq_micro_trigger_tx(micro);
112 } else
113 micro->msg = NULL;
114 dev_dbg(micro->dev, "OK RX message 0x%02x\n", id);
115 } else {
116 dev_err(micro->dev,
117 "out of band RX message 0x%02x\n", id);
118 if(!micro->msg)
119 dev_info(micro->dev, "no message queued\n");
120 else
121 dev_info(micro->dev, "expected message %02x\n",
122 micro->msg->id);
123 }
124 break;
125 case MSG_KEYBOARD:
126 if (micro->key)
127 micro->key(micro->key_data, len, data);
128 else
129 dev_dbg(micro->dev, "key message ignored, no handle \n");
130 break;
131 case MSG_TOUCHSCREEN:
132 if (micro->ts)
133 micro->ts(micro->ts_data, len, data);
134 else
135 dev_dbg(micro->dev, "touchscreen message ignored, no handle \n");
136 break;
137 default:
138 dev_err(micro->dev,
139 "unknown msg %d [%d] ", id, len);
140 for (i = 0; i < len; ++i)
141 pr_cont("0x%02x ", data[i]);
142 pr_cont("\n");
143 }
144 spin_unlock(&micro->lock);
145}
146
147static void micro_process_char(struct ipaq_micro *micro, u8 ch)
148{
149 struct ipaq_micro_rxdev *rx = &micro->rx;
150
151 switch (rx->state) {
152 case STATE_SOF: /* Looking for SOF */
153 if (ch == CHAR_SOF)
154 rx->state = STATE_ID; /* Next byte is the id and len */
155 break;
156 case STATE_ID: /* Looking for id and len byte */
157 rx->id = (ch & 0xf0) >> 4 ;
158 rx->len = (ch & 0x0f);
159 rx->index = 0;
160 rx->chksum = ch;
161 rx->state = (rx->len > 0) ? STATE_DATA : STATE_CHKSUM;
162 break;
163 case STATE_DATA: /* Looking for 'len' data bytes */
164 rx->chksum += ch;
165 rx->buf[rx->index] = ch;
166 if (++rx->index == rx->len)
167 rx->state = STATE_CHKSUM;
168 break;
169 case STATE_CHKSUM: /* Looking for the checksum */
170 if (ch == rx->chksum)
171 micro_rx_msg(micro, rx->id, rx->len, rx->buf);
172 rx->state = STATE_SOF;
173 break;
174 }
175}
176
177static void micro_rx_chars(struct ipaq_micro *micro)
178{
179 u32 status, ch;
180
181 while ((status = readl(micro->base + UTSR1)) & UTSR1_RNE) {
182 ch = readl(micro->base + UTDR);
183 if (status & UTSR1_PRE)
184 dev_err(micro->dev, "rx: parity error\n");
185 else if (status & UTSR1_FRE)
186 dev_err(micro->dev, "rx: framing error\n");
187 else if (status & UTSR1_ROR)
188 dev_err(micro->dev, "rx: overrun error\n");
189 micro_process_char(micro, ch);
190 }
191}
192
193static void ipaq_micro_get_version(struct ipaq_micro *micro)
194{
195 struct ipaq_micro_msg msg = {
196 .id = MSG_VERSION,
197 };
198
199 ipaq_micro_tx_msg_sync(micro, &msg);
200 if (msg.rx_len == 4) {
201 memcpy(micro->version, msg.rx_data, 4);
202 micro->version[4] = '\0';
203 } else if (msg.rx_len == 9) {
204 memcpy(micro->version, msg.rx_data, 4);
205 micro->version[4] = '\0';
206 /* Bytes 4-7 are "pack", byte 8 is "boot type" */
207 } else {
208 dev_err(micro->dev,
209 "illegal version message %d bytes\n", msg.rx_len);
210 }
211}
212
213static void ipaq_micro_eeprom_read(struct ipaq_micro *micro,
214 u8 address, u8 len, u8 *data)
215{
216 struct ipaq_micro_msg msg = {
217 .id = MSG_EEPROM_READ,
218 };
219 u8 i;
220
221 for (i = 0; i < len; i++) {
222 msg.tx_data[0] = address + i;
223 msg.tx_data[1] = 1;
224 msg.tx_len = 2;
225 ipaq_micro_tx_msg_sync(micro, &msg);
226 memcpy(data + (i * 2), msg.rx_data, 2);
227 }
228}
229
230static char *ipaq_micro_str(u8 *wchar, u8 len)
231{
232 char retstr[256];
233 u8 i;
234
235 for (i = 0; i < len / 2; i++)
236 retstr[i] = wchar[i * 2];
237 return kstrdup(retstr, GFP_KERNEL);
238}
239
240static u16 ipaq_micro_to_u16(u8 *data)
241{
242 return data[1] << 8 | data[0];
243}
244
245static void ipaq_micro_eeprom_dump(struct ipaq_micro *micro)
246{
247 u8 dump[256];
248 char *str;
249
250 ipaq_micro_eeprom_read(micro, 0, 128, dump);
251 str = ipaq_micro_str(dump, 10);
252 if (str) {
253 dev_info(micro->dev, "HM version %s\n", str);
254 kfree(str);
255 }
256 str = ipaq_micro_str(dump+10, 40);
257 if (str) {
258 dev_info(micro->dev, "serial number: %s\n", str);
259 /* Feed the random pool with this */
260 add_device_randomness(str, strlen(str));
261 kfree(str);
262 }
263 str = ipaq_micro_str(dump+50, 20);
264 if (str) {
265 dev_info(micro->dev, "module ID: %s\n", str);
266 kfree(str);
267 }
268 str = ipaq_micro_str(dump+70, 10);
269 if (str) {
270 dev_info(micro->dev, "product revision: %s\n", str);
271 kfree(str);
272 }
273 dev_info(micro->dev, "product ID: %u\n", ipaq_micro_to_u16(dump+80));
274 dev_info(micro->dev, "frame rate: %u fps\n",
275 ipaq_micro_to_u16(dump+82));
276 dev_info(micro->dev, "page mode: %u\n", ipaq_micro_to_u16(dump+84));
277 dev_info(micro->dev, "country ID: %u\n", ipaq_micro_to_u16(dump+86));
278 dev_info(micro->dev, "color display: %s\n",
279 ipaq_micro_to_u16(dump+88) ? "yes" : "no");
280 dev_info(micro->dev, "ROM size: %u MiB\n", ipaq_micro_to_u16(dump+90));
281 dev_info(micro->dev, "RAM size: %u KiB\n", ipaq_micro_to_u16(dump+92));
282 dev_info(micro->dev, "screen: %u x %u\n",
283 ipaq_micro_to_u16(dump+94), ipaq_micro_to_u16(dump+96));
284 print_hex_dump(KERN_DEBUG, "eeprom: ", DUMP_PREFIX_OFFSET, 16, 1,
285 dump, 256, true);
286
287}
288
289static void micro_tx_chars(struct ipaq_micro *micro)
290{
291 struct ipaq_micro_txdev *tx = &micro->tx;
292 u32 val;
293
294 while ((tx->index < tx->len) &&
295 (readl(micro->base + UTSR1) & UTSR1_TNF)) {
296 writel(tx->buf[tx->index], micro->base + UTDR);
297 tx->index++;
298 }
299
300 /* Stop interrupts */
301 val = readl(micro->base + UTCR3);
302 val &= ~UTCR3_TIE;
303 writel(val, micro->base + UTCR3);
304}
305
306static void micro_reset_comm(struct ipaq_micro *micro)
307{
308 struct ipaq_micro_rxdev *rx = &micro->rx;
309 u32 val;
310
311 if (micro->msg)
312 complete(&micro->msg->ack);
313
314 /* Initialize Serial channel protocol frame */
315 rx->state = STATE_SOF; /* Reset the state machine */
316
317 /* Set up interrupts */
318 writel(0x01, micro->sdlc + 0x0); /* Select UART mode */
319
320 /* Clean up CR3 */
321 writel(0x0, micro->base + UTCR3);
322
323 /* Format: 8N1 */
324 writel(UTCR0_8BitData | UTCR0_1StpBit, micro->base + UTCR0);
325
326 /* Baud rate: 115200 */
327 writel(0x0, micro->base + UTCR1);
328 writel(0x1, micro->base + UTCR2);
329
330 /* Clear SR0 */
331 writel(0xff, micro->base + UTSR0);
332
333 /* Enable RX int, disable TX int */
334 writel(UTCR3_TXE | UTCR3_RXE | UTCR3_RIE, micro->base + UTCR3);
335 val = readl(micro->base + UTCR3);
336 val &= ~UTCR3_TIE;
337 writel(val, micro->base + UTCR3);
338}
339
340static irqreturn_t micro_serial_isr(int irq, void *dev_id)
341{
342 struct ipaq_micro *micro = dev_id;
343 struct ipaq_micro_txdev *tx = &micro->tx;
344 u32 status;
345
346 status = readl(micro->base + UTSR0);
347 do {
348 if (status & (UTSR0_RID | UTSR0_RFS)) {
349 if (status & UTSR0_RID)
350 /* Clear the Receiver IDLE bit */
351 writel(UTSR0_RID, micro->base + UTSR0);
352 micro_rx_chars(micro);
353 }
354
355 /* Clear break bits */
356 if (status & (UTSR0_RBB | UTSR0_REB))
357 writel(status & (UTSR0_RBB | UTSR0_REB),
358 micro->base + UTSR0);
359
360 if (status & UTSR0_TFS)
361 micro_tx_chars(micro);
362
363 status = readl(micro->base + UTSR0);
364
365 } while (((tx->index < tx->len) && (status & UTSR0_TFS)) ||
366 (status & (UTSR0_RFS | UTSR0_RID)));
367
368 return IRQ_HANDLED;
369}
370
371static const struct mfd_cell micro_cells[] = {
372 { .name = "ipaq-micro-backlight", },
373 { .name = "ipaq-micro-battery", },
374 { .name = "ipaq-micro-keys", },
375 { .name = "ipaq-micro-ts", },
376 { .name = "ipaq-micro-leds", },
377};
378
379static int micro_resume(struct device *dev)
380{
381 struct ipaq_micro *micro = dev_get_drvdata(dev);
382
383 micro_reset_comm(micro);
384 mdelay(10);
385
386 return 0;
387}
388
389static int micro_probe(struct platform_device *pdev)
390{
391 struct ipaq_micro *micro;
392 struct resource *res;
393 int ret;
394 int irq;
395
396 micro = devm_kzalloc(&pdev->dev, sizeof(*micro), GFP_KERNEL);
397 if (!micro)
398 return -ENOMEM;
399
400 micro->dev = &pdev->dev;
401
402 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 if (!res)
404 return -EINVAL;
405
406 micro->base = devm_ioremap_resource(&pdev->dev, res);
407 if (IS_ERR(micro->base))
408 return PTR_ERR(micro->base);
409
410 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
411 if (!res)
412 return -EINVAL;
413
414 micro->sdlc = devm_ioremap_resource(&pdev->dev, res);
415 if (IS_ERR(micro->sdlc))
416 return PTR_ERR(micro->sdlc);
417
418 micro_reset_comm(micro);
419
420 irq = platform_get_irq(pdev, 0);
421 if (!irq)
422 return -EINVAL;
423 ret = devm_request_irq(&pdev->dev, irq, micro_serial_isr,
424 IRQF_SHARED, "ipaq-micro",
425 micro);
426 if (ret) {
427 dev_err(&pdev->dev, "unable to grab serial port IRQ\n");
428 return ret;
429 } else
430 dev_info(&pdev->dev, "grabbed serial port IRQ\n");
431
432 spin_lock_init(&micro->lock);
433 INIT_LIST_HEAD(&micro->queue);
434 platform_set_drvdata(pdev, micro);
435
436 ret = mfd_add_devices(&pdev->dev, pdev->id, micro_cells,
437 ARRAY_SIZE(micro_cells), NULL, 0, NULL);
438 if (ret) {
439 dev_err(&pdev->dev, "error adding MFD cells");
440 return ret;
441 }
442
443 /* Check version */
444 ipaq_micro_get_version(micro);
445 dev_info(&pdev->dev, "Atmel micro ASIC version %s\n", micro->version);
446 ipaq_micro_eeprom_dump(micro);
447
448 return 0;
449}
450
451static int micro_remove(struct platform_device *pdev)
452{
453 struct ipaq_micro *micro = platform_get_drvdata(pdev);
454 u32 val;
455
456 mfd_remove_devices(&pdev->dev);
457
458 val = readl(micro->base + UTCR3);
459 val &= ~(UTCR3_RXE | UTCR3_RIE); /* disable receive interrupt */
460 val &= ~(UTCR3_TXE | UTCR3_TIE); /* disable transmit interrupt */
461 writel(val, micro->base + UTCR3);
462
463 return 0;
464}
465
466static const struct dev_pm_ops micro_dev_pm_ops = {
467 SET_SYSTEM_SLEEP_PM_OPS(NULL, micro_resume)
468};
469
470static struct platform_driver micro_device_driver = {
471 .driver = {
472 .name = "ipaq-h3xxx-micro",
473 .pm = &micro_dev_pm_ops,
474 },
475 .probe = micro_probe,
476 .remove = micro_remove,
477 /* .shutdown = micro_suspend, // FIXME */
478};
479module_platform_driver(micro_device_driver);
480
481MODULE_LICENSE("GPL");
482MODULE_DESCRIPTION("driver for iPAQ Atmel micro core and backlight");
diff --git a/drivers/mfd/kempld-core.c b/drivers/mfd/kempld-core.c
index 07692604e119..f7ff0188603d 100644
--- a/drivers/mfd/kempld-core.c
+++ b/drivers/mfd/kempld-core.c
@@ -86,7 +86,7 @@ enum kempld_cells {
86 KEMPLD_UART, 86 KEMPLD_UART,
87}; 87};
88 88
89static struct mfd_cell kempld_devs[] = { 89static const struct mfd_cell kempld_devs[] = {
90 [KEMPLD_I2C] = { 90 [KEMPLD_I2C] = {
91 .name = "kempld-i2c", 91 .name = "kempld-i2c",
92 }, 92 },
@@ -288,9 +288,38 @@ EXPORT_SYMBOL_GPL(kempld_release_mutex);
288 */ 288 */
289static int kempld_get_info(struct kempld_device_data *pld) 289static int kempld_get_info(struct kempld_device_data *pld)
290{ 290{
291 int ret;
291 struct kempld_platform_data *pdata = dev_get_platdata(pld->dev); 292 struct kempld_platform_data *pdata = dev_get_platdata(pld->dev);
293 char major, minor;
294
295 ret = pdata->get_info(pld);
296 if (ret)
297 return ret;
298
299 /* The Kontron PLD firmware version string has the following format:
300 * Pwxy.zzzz
301 * P: Fixed
302 * w: PLD number - 1 hex digit
303 * x: Major version - 1 alphanumerical digit (0-9A-V)
304 * y: Minor version - 1 alphanumerical digit (0-9A-V)
305 * zzzz: Build number - 4 zero padded hex digits */
292 306
293 return pdata->get_info(pld); 307 if (pld->info.major < 10)
308 major = pld->info.major + '0';
309 else
310 major = (pld->info.major - 10) + 'A';
311 if (pld->info.minor < 10)
312 minor = pld->info.minor + '0';
313 else
314 minor = (pld->info.minor - 10) + 'A';
315
316 ret = scnprintf(pld->info.version, sizeof(pld->info.version),
317 "P%X%c%c.%04X", pld->info.number, major, minor,
318 pld->info.buildnr);
319 if (ret < 0)
320 return ret;
321
322 return 0;
294} 323}
295 324
296/* 325/*
@@ -307,9 +336,71 @@ static int kempld_register_cells(struct kempld_device_data *pld)
307 return pdata->register_cells(pld); 336 return pdata->register_cells(pld);
308} 337}
309 338
339static const char *kempld_get_type_string(struct kempld_device_data *pld)
340{
341 const char *version_type;
342
343 switch (pld->info.type) {
344 case 0:
345 version_type = "release";
346 break;
347 case 1:
348 version_type = "debug";
349 break;
350 case 2:
351 version_type = "custom";
352 break;
353 default:
354 version_type = "unspecified";
355 break;
356 }
357
358 return version_type;
359}
360
361static ssize_t kempld_version_show(struct device *dev,
362 struct device_attribute *attr, char *buf)
363{
364 struct kempld_device_data *pld = dev_get_drvdata(dev);
365
366 return scnprintf(buf, PAGE_SIZE, "%s\n", pld->info.version);
367}
368
369static ssize_t kempld_specification_show(struct device *dev,
370 struct device_attribute *attr, char *buf)
371{
372 struct kempld_device_data *pld = dev_get_drvdata(dev);
373
374 return scnprintf(buf, PAGE_SIZE, "%d.%d\n", pld->info.spec_major,
375 pld->info.spec_minor);
376}
377
378static ssize_t kempld_type_show(struct device *dev,
379 struct device_attribute *attr, char *buf)
380{
381 struct kempld_device_data *pld = dev_get_drvdata(dev);
382
383 return scnprintf(buf, PAGE_SIZE, "%s\n", kempld_get_type_string(pld));
384}
385
386static DEVICE_ATTR(pld_version, S_IRUGO, kempld_version_show, NULL);
387static DEVICE_ATTR(pld_specification, S_IRUGO, kempld_specification_show,
388 NULL);
389static DEVICE_ATTR(pld_type, S_IRUGO, kempld_type_show, NULL);
390
391static struct attribute *pld_attributes[] = {
392 &dev_attr_pld_version.attr,
393 &dev_attr_pld_specification.attr,
394 &dev_attr_pld_type.attr,
395 NULL
396};
397
398static const struct attribute_group pld_attr_group = {
399 .attrs = pld_attributes,
400};
401
310static int kempld_detect_device(struct kempld_device_data *pld) 402static int kempld_detect_device(struct kempld_device_data *pld)
311{ 403{
312 char *version_type;
313 u8 index_reg; 404 u8 index_reg;
314 int ret; 405 int ret;
315 406
@@ -335,27 +426,19 @@ static int kempld_detect_device(struct kempld_device_data *pld)
335 if (ret) 426 if (ret)
336 return ret; 427 return ret;
337 428
338 switch (pld->info.type) { 429 dev_info(pld->dev, "Found Kontron PLD - %s (%s), spec %d.%d\n",
339 case 0: 430 pld->info.version, kempld_get_type_string(pld),
340 version_type = "release"; 431 pld->info.spec_major, pld->info.spec_minor);
341 break; 432
342 case 1: 433 ret = sysfs_create_group(&pld->dev->kobj, &pld_attr_group);
343 version_type = "debug"; 434 if (ret)
344 break; 435 return ret;
345 case 2:
346 version_type = "custom";
347 break;
348 default:
349 version_type = "unspecified";
350 }
351 436
352 dev_info(pld->dev, "Found Kontron PLD %d\n", pld->info.number); 437 ret = kempld_register_cells(pld);
353 dev_info(pld->dev, "%s version %d.%d build %d, specification %d.%d\n", 438 if (ret)
354 version_type, pld->info.major, pld->info.minor, 439 sysfs_remove_group(&pld->dev->kobj, &pld_attr_group);
355 pld->info.buildnr, pld->info.spec_major,
356 pld->info.spec_minor);
357 440
358 return kempld_register_cells(pld); 441 return ret;
359} 442}
360 443
361static int kempld_probe(struct platform_device *pdev) 444static int kempld_probe(struct platform_device *pdev)
@@ -399,6 +482,8 @@ static int kempld_remove(struct platform_device *pdev)
399 struct kempld_device_data *pld = platform_get_drvdata(pdev); 482 struct kempld_device_data *pld = platform_get_drvdata(pdev);
400 struct kempld_platform_data *pdata = dev_get_platdata(pld->dev); 483 struct kempld_platform_data *pdata = dev_get_platdata(pld->dev);
401 484
485 sysfs_remove_group(&pld->dev->kobj, &pld_attr_group);
486
402 mfd_remove_devices(&pdev->dev); 487 mfd_remove_devices(&pdev->dev);
403 pdata->release_hardware_mutex(pld); 488 pdata->release_hardware_mutex(pld);
404 489
diff --git a/drivers/mfd/lp3943.c b/drivers/mfd/lp3943.c
index e32226836fb4..335b930112b2 100644
--- a/drivers/mfd/lp3943.c
+++ b/drivers/mfd/lp3943.c
@@ -62,7 +62,7 @@ static const struct lp3943_reg_cfg lp3943_mux_cfg[] = {
62 { LP3943_REG_MUX3, 0xC0, 6 }, 62 { LP3943_REG_MUX3, 0xC0, 6 },
63}; 63};
64 64
65static struct mfd_cell lp3943_devs[] = { 65static const struct mfd_cell lp3943_devs[] = {
66 { 66 {
67 .name = "lp3943-pwm", 67 .name = "lp3943-pwm",
68 .of_compatible = "ti,lp3943-pwm", 68 .of_compatible = "ti,lp3943-pwm",
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
index 3f10ea3f45d1..7d8482ff5868 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich.c
@@ -488,6 +488,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
488 [LPC_PPT] = { 488 [LPC_PPT] = {
489 .name = "Panther Point", 489 .name = "Panther Point",
490 .iTCO_version = 2, 490 .iTCO_version = 2,
491 .gpio_version = ICH_V5_GPIO,
491 }, 492 },
492 [LPC_LPT] = { 493 [LPC_LPT] = {
493 .name = "Lynx Point", 494 .name = "Lynx Point",
diff --git a/drivers/mfd/max14577.c b/drivers/mfd/max14577.c
index 484d372a4892..4a5e885383f8 100644
--- a/drivers/mfd/max14577.c
+++ b/drivers/mfd/max14577.c
@@ -26,7 +26,7 @@
26#include <linux/mfd/max14577.h> 26#include <linux/mfd/max14577.h>
27#include <linux/mfd/max14577-private.h> 27#include <linux/mfd/max14577-private.h>
28 28
29static struct mfd_cell max14577_devs[] = { 29static const struct mfd_cell max14577_devs[] = {
30 { 30 {
31 .name = "max14577-muic", 31 .name = "max14577-muic",
32 .of_compatible = "maxim,max14577-muic", 32 .of_compatible = "maxim,max14577-muic",
@@ -38,7 +38,7 @@ static struct mfd_cell max14577_devs[] = {
38 { .name = "max14577-charger", }, 38 { .name = "max14577-charger", },
39}; 39};
40 40
41static struct mfd_cell max77836_devs[] = { 41static const struct mfd_cell max77836_devs[] = {
42 { 42 {
43 .name = "max77836-muic", 43 .name = "max77836-muic",
44 .of_compatible = "maxim,max77836-muic", 44 .of_compatible = "maxim,max77836-muic",
@@ -57,7 +57,7 @@ static struct mfd_cell max77836_devs[] = {
57 }, 57 },
58}; 58};
59 59
60static struct of_device_id max14577_dt_match[] = { 60static const struct of_device_id max14577_dt_match[] = {
61 { 61 {
62 .compatible = "maxim,max14577", 62 .compatible = "maxim,max14577",
63 .data = (void *)MAXIM_DEVICE_TYPE_MAX14577, 63 .data = (void *)MAXIM_DEVICE_TYPE_MAX14577,
@@ -292,7 +292,7 @@ static int max14577_i2c_probe(struct i2c_client *i2c,
292 struct device_node *np = i2c->dev.of_node; 292 struct device_node *np = i2c->dev.of_node;
293 int ret = 0; 293 int ret = 0;
294 const struct regmap_irq_chip *irq_chip; 294 const struct regmap_irq_chip *irq_chip;
295 struct mfd_cell *mfd_devs; 295 const struct mfd_cell *mfd_devs;
296 unsigned int mfd_devs_size; 296 unsigned int mfd_devs_size;
297 int irq_flags; 297 int irq_flags;
298 298
@@ -331,7 +331,8 @@ static int max14577_i2c_probe(struct i2c_client *i2c,
331 331
332 of_id = of_match_device(max14577_dt_match, &i2c->dev); 332 of_id = of_match_device(max14577_dt_match, &i2c->dev);
333 if (of_id) 333 if (of_id)
334 max14577->dev_type = (unsigned int)of_id->data; 334 max14577->dev_type =
335 (enum maxim_device_type)of_id->data;
335 } else { 336 } else {
336 max14577->dev_type = id->driver_data; 337 max14577->dev_type = id->driver_data;
337 } 338 }
@@ -414,20 +415,18 @@ static int max14577_suspend(struct device *dev)
414 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 415 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
415 struct max14577 *max14577 = i2c_get_clientdata(i2c); 416 struct max14577 *max14577 = i2c_get_clientdata(i2c);
416 417
417 if (device_may_wakeup(dev)) { 418 if (device_may_wakeup(dev))
418 enable_irq_wake(max14577->irq); 419 enable_irq_wake(max14577->irq);
419 /* 420 /*
420 * MUIC IRQ must be disabled during suspend if this is 421 * MUIC IRQ must be disabled during suspend because if it happens
421 * a wake up source because it will be handled before 422 * while suspended it will be handled before resuming I2C.
422 * resuming I2C. 423 *
423 * 424 * When device is woken up from suspend (e.g. by ADC change),
424 * When device is woken up from suspend (e.g. by ADC change), 425 * an interrupt occurs before resuming I2C bus controller.
425 * an interrupt occurs before resuming I2C bus controller. 426 * Interrupt handler tries to read registers but this read
426 * Interrupt handler tries to read registers but this read 427 * will fail because I2C is still suspended.
427 * will fail because I2C is still suspended. 428 */
428 */ 429 disable_irq(max14577->irq);
429 disable_irq(max14577->irq);
430 }
431 430
432 return 0; 431 return 0;
433} 432}
@@ -437,10 +436,9 @@ static int max14577_resume(struct device *dev)
437 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 436 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
438 struct max14577 *max14577 = i2c_get_clientdata(i2c); 437 struct max14577 *max14577 = i2c_get_clientdata(i2c);
439 438
440 if (device_may_wakeup(dev)) { 439 if (device_may_wakeup(dev))
441 disable_irq_wake(max14577->irq); 440 disable_irq_wake(max14577->irq);
442 enable_irq(max14577->irq); 441 enable_irq(max14577->irq);
443 }
444 442
445 return 0; 443 return 0;
446} 444}
diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
index e5fce765accb..ce869acf27ae 100644
--- a/drivers/mfd/max77686.c
+++ b/drivers/mfd/max77686.c
@@ -47,7 +47,7 @@ static struct regmap_config max77686_regmap_config = {
47}; 47};
48 48
49#ifdef CONFIG_OF 49#ifdef CONFIG_OF
50static struct of_device_id max77686_pmic_dt_match[] = { 50static const struct of_device_id max77686_pmic_dt_match[] = {
51 {.compatible = "maxim,max77686", .data = NULL}, 51 {.compatible = "maxim,max77686", .data = NULL},
52 {}, 52 {},
53}; 53};
diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c
index c5535f018466..7e05428c756d 100644
--- a/drivers/mfd/max77693.c
+++ b/drivers/mfd/max77693.c
@@ -243,7 +243,7 @@ static const struct dev_pm_ops max77693_pm = {
243}; 243};
244 244
245#ifdef CONFIG_OF 245#ifdef CONFIG_OF
246static struct of_device_id max77693_dt_match[] = { 246static const struct of_device_id max77693_dt_match[] = {
247 { .compatible = "maxim,max77693" }, 247 { .compatible = "maxim,max77693" },
248 {}, 248 {},
249}; 249};
diff --git a/drivers/mfd/max8907.c b/drivers/mfd/max8907.c
index 07740314b29d..232749c8813d 100644
--- a/drivers/mfd/max8907.c
+++ b/drivers/mfd/max8907.c
@@ -305,7 +305,7 @@ static int max8907_i2c_remove(struct i2c_client *i2c)
305} 305}
306 306
307#ifdef CONFIG_OF 307#ifdef CONFIG_OF
308static struct of_device_id max8907_of_match[] = { 308static const struct of_device_id max8907_of_match[] = {
309 { .compatible = "maxim,max8907" }, 309 { .compatible = "maxim,max8907" },
310 { }, 310 { },
311}; 311};
diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
index 8cf7a015cfe5..595364ee178a 100644
--- a/drivers/mfd/max8997.c
+++ b/drivers/mfd/max8997.c
@@ -51,7 +51,7 @@ static const struct mfd_cell max8997_devs[] = {
51}; 51};
52 52
53#ifdef CONFIG_OF 53#ifdef CONFIG_OF
54static struct of_device_id max8997_pmic_dt_match[] = { 54static const struct of_device_id max8997_pmic_dt_match[] = {
55 { .compatible = "maxim,max8997-pmic", .data = (void *)TYPE_MAX8997 }, 55 { .compatible = "maxim,max8997-pmic", .data = (void *)TYPE_MAX8997 },
56 {}, 56 {},
57}; 57};
diff --git a/drivers/mfd/max8998.c b/drivers/mfd/max8998.c
index 592db06098e6..a37cb7444b6e 100644
--- a/drivers/mfd/max8998.c
+++ b/drivers/mfd/max8998.c
@@ -132,7 +132,7 @@ int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask)
132EXPORT_SYMBOL(max8998_update_reg); 132EXPORT_SYMBOL(max8998_update_reg);
133 133
134#ifdef CONFIG_OF 134#ifdef CONFIG_OF
135static struct of_device_id max8998_dt_match[] = { 135static const struct of_device_id max8998_dt_match[] = {
136 { .compatible = "maxim,max8998", .data = (void *)TYPE_MAX8998 }, 136 { .compatible = "maxim,max8998", .data = (void *)TYPE_MAX8998 },
137 { .compatible = "national,lp3974", .data = (void *)TYPE_LP3974 }, 137 { .compatible = "national,lp3974", .data = (void *)TYPE_LP3974 },
138 { .compatible = "ti,lp3974", .data = (void *)TYPE_LP3974 }, 138 { .compatible = "ti,lp3974", .data = (void *)TYPE_LP3974 },
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 0c6c21c5b1a8..acf5dd712eb2 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -660,34 +660,22 @@ int mc13xxx_common_init(struct device *dev)
660 if (ret) 660 if (ret)
661 return ret; 661 return ret;
662 662
663 mutex_init(&mc13xxx->lock);
664
663 ret = request_threaded_irq(mc13xxx->irq, NULL, mc13xxx_irq_thread, 665 ret = request_threaded_irq(mc13xxx->irq, NULL, mc13xxx_irq_thread,
664 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx); 666 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
665 if (ret) 667 if (ret)
666 return ret; 668 return ret;
667 669
668 mutex_init(&mc13xxx->lock);
669
670 if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata) 670 if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
671 mc13xxx->flags = pdata->flags; 671 mc13xxx->flags = pdata->flags;
672 672
673 if (mc13xxx->flags & MC13XXX_USE_ADC) 673 if (mc13xxx->flags & MC13XXX_USE_ADC)
674 mc13xxx_add_subdevice(mc13xxx, "%s-adc"); 674 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
675 675
676 if (mc13xxx->flags & MC13XXX_USE_CODEC) {
677 if (pdata)
678 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
679 pdata->codec, sizeof(*pdata->codec));
680 else
681 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
682 }
683
684 if (mc13xxx->flags & MC13XXX_USE_RTC) 676 if (mc13xxx->flags & MC13XXX_USE_RTC)
685 mc13xxx_add_subdevice(mc13xxx, "%s-rtc"); 677 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
686 678
687 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
688 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
689 &pdata->touch, sizeof(pdata->touch));
690
691 if (pdata) { 679 if (pdata) {
692 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator", 680 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
693 &pdata->regulators, sizeof(pdata->regulators)); 681 &pdata->regulators, sizeof(pdata->regulators));
@@ -695,10 +683,20 @@ int mc13xxx_common_init(struct device *dev)
695 pdata->leds, sizeof(*pdata->leds)); 683 pdata->leds, sizeof(*pdata->leds));
696 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton", 684 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
697 pdata->buttons, sizeof(*pdata->buttons)); 685 pdata->buttons, sizeof(*pdata->buttons));
686 if (mc13xxx->flags & MC13XXX_USE_CODEC)
687 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
688 pdata->codec, sizeof(*pdata->codec));
689 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
690 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
691 &pdata->touch, sizeof(pdata->touch));
698 } else { 692 } else {
699 mc13xxx_add_subdevice(mc13xxx, "%s-regulator"); 693 mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
700 mc13xxx_add_subdevice(mc13xxx, "%s-led"); 694 mc13xxx_add_subdevice(mc13xxx, "%s-led");
701 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton"); 695 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
696 if (mc13xxx->flags & MC13XXX_USE_CODEC)
697 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
698 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
699 mc13xxx_add_subdevice(mc13xxx, "%s-ts");
702 } 700 }
703 701
704 return 0; 702 return 0;
diff --git a/drivers/mfd/menelaus.c b/drivers/mfd/menelaus.c
index ad25bfa3fb02..5e2667afe2bc 100644
--- a/drivers/mfd/menelaus.c
+++ b/drivers/mfd/menelaus.c
@@ -1287,29 +1287,8 @@ static struct i2c_driver menelaus_i2c_driver = {
1287 .id_table = menelaus_id, 1287 .id_table = menelaus_id,
1288}; 1288};
1289 1289
1290static int __init menelaus_init(void) 1290module_i2c_driver(menelaus_i2c_driver);
1291{
1292 int res;
1293
1294 res = i2c_add_driver(&menelaus_i2c_driver);
1295 if (res < 0) {
1296 pr_err(DRIVER_NAME ": driver registration failed\n");
1297 return res;
1298 }
1299
1300 return 0;
1301}
1302
1303static void __exit menelaus_exit(void)
1304{
1305 i2c_del_driver(&menelaus_i2c_driver);
1306
1307 /* FIXME: Shutdown menelaus parts that can be shut down */
1308}
1309 1291
1310MODULE_AUTHOR("Texas Instruments, Inc. (and others)"); 1292MODULE_AUTHOR("Texas Instruments, Inc. (and others)");
1311MODULE_DESCRIPTION("I2C interface for Menelaus."); 1293MODULE_DESCRIPTION("I2C interface for Menelaus.");
1312MODULE_LICENSE("GPL"); 1294MODULE_LICENSE("GPL");
1313
1314module_init(menelaus_init);
1315module_exit(menelaus_exit);
diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 267649244737..892d343193ad 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -102,7 +102,7 @@ static int mfd_add_device(struct device *parent, int id,
102 pdev->dev.dma_mask = parent->dma_mask; 102 pdev->dev.dma_mask = parent->dma_mask;
103 pdev->dev.dma_parms = parent->dma_parms; 103 pdev->dev.dma_parms = parent->dma_parms;
104 104
105 ret = devm_regulator_bulk_register_supply_alias( 105 ret = regulator_bulk_register_supply_alias(
106 &pdev->dev, cell->parent_supplies, 106 &pdev->dev, cell->parent_supplies,
107 parent, cell->parent_supplies, 107 parent, cell->parent_supplies,
108 cell->num_parent_supplies); 108 cell->num_parent_supplies);
@@ -182,9 +182,9 @@ static int mfd_add_device(struct device *parent, int id,
182 return 0; 182 return 0;
183 183
184fail_alias: 184fail_alias:
185 devm_regulator_bulk_unregister_supply_alias(&pdev->dev, 185 regulator_bulk_unregister_supply_alias(&pdev->dev,
186 cell->parent_supplies, 186 cell->parent_supplies,
187 cell->num_parent_supplies); 187 cell->num_parent_supplies);
188fail_res: 188fail_res:
189 kfree(res); 189 kfree(res);
190fail_device: 190fail_device:
@@ -238,6 +238,9 @@ static int mfd_remove_devices_fn(struct device *dev, void *c)
238 pdev = to_platform_device(dev); 238 pdev = to_platform_device(dev);
239 cell = mfd_get_cell(pdev); 239 cell = mfd_get_cell(pdev);
240 240
241 regulator_bulk_unregister_supply_alias(dev, cell->parent_supplies,
242 cell->num_parent_supplies);
243
241 /* find the base address of usage_count pointers (for freeing) */ 244 /* find the base address of usage_count pointers (for freeing) */
242 if (!*usage_count || (cell->usage_count < *usage_count)) 245 if (!*usage_count || (cell->usage_count < *usage_count))
243 *usage_count = cell->usage_count; 246 *usage_count = cell->usage_count;
diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 651e249287dc..b48d80c367f9 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -557,7 +557,7 @@ static int usbhs_omap_get_dt_pdata(struct device *dev,
557 return 0; 557 return 0;
558} 558}
559 559
560static struct of_device_id usbhs_child_match_table[] = { 560static const struct of_device_id usbhs_child_match_table[] = {
561 { .compatible = "ti,omap-ehci", }, 561 { .compatible = "ti,omap-ehci", },
562 { .compatible = "ti,omap-ohci", }, 562 { .compatible = "ti,omap-ohci", },
563 { } 563 { }
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index b97a97187ae9..959513803542 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -26,7 +26,6 @@
26#include <linux/regmap.h> 26#include <linux/regmap.h>
27#include <linux/of_platform.h> 27#include <linux/of_platform.h>
28#include <linux/mfd/core.h> 28#include <linux/mfd/core.h>
29#include <linux/mfd/pm8xxx/core.h>
30 29
31#define SSBI_REG_ADDR_IRQ_BASE 0x1BB 30#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
32 31
@@ -57,7 +56,6 @@
57#define PM8921_NR_IRQS 256 56#define PM8921_NR_IRQS 256
58 57
59struct pm_irq_chip { 58struct pm_irq_chip {
60 struct device *dev;
61 struct regmap *regmap; 59 struct regmap *regmap;
62 spinlock_t pm_irq_lock; 60 spinlock_t pm_irq_lock;
63 struct irq_domain *irqdomain; 61 struct irq_domain *irqdomain;
@@ -67,11 +65,6 @@ struct pm_irq_chip {
67 u8 config[0]; 65 u8 config[0];
68}; 66};
69 67
70struct pm8921 {
71 struct device *dev;
72 struct pm_irq_chip *irq_chip;
73};
74
75static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp, 68static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
76 unsigned int *ip) 69 unsigned int *ip)
77{ 70{
@@ -255,55 +248,6 @@ static struct irq_chip pm8xxx_irq_chip = {
255 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, 248 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
256}; 249};
257 250
258/**
259 * pm8xxx_get_irq_stat - get the status of the irq line
260 * @chip: pointer to identify a pmic irq controller
261 * @irq: the irq number
262 *
263 * The pm8xxx gpio and mpp rely on the interrupt block to read
264 * the values on their pins. This function is to facilitate reading
265 * the status of a gpio or an mpp line. The caller has to convert the
266 * gpio number to irq number.
267 *
268 * RETURNS:
269 * an int indicating the value read on that line
270 */
271static int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
272{
273 int pmirq, rc;
274 unsigned int block, bits, bit;
275 unsigned long flags;
276 struct irq_data *irq_data = irq_get_irq_data(irq);
277
278 pmirq = irq_data->hwirq;
279
280 block = pmirq / 8;
281 bit = pmirq % 8;
282
283 spin_lock_irqsave(&chip->pm_irq_lock, flags);
284
285 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
286 if (rc) {
287 pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
288 irq, pmirq, block, rc);
289 goto bail_out;
290 }
291
292 rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
293 if (rc) {
294 pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
295 irq, pmirq, block, rc);
296 goto bail_out;
297 }
298
299 rc = (bits & (1 << bit)) ? 1 : 0;
300
301bail_out:
302 spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
303
304 return rc;
305}
306
307static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq, 251static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
308 irq_hw_number_t hwirq) 252 irq_hw_number_t hwirq)
309{ 253{
@@ -324,56 +268,6 @@ static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
324 .map = pm8xxx_irq_domain_map, 268 .map = pm8xxx_irq_domain_map,
325}; 269};
326 270
327static int pm8921_readb(const struct device *dev, u16 addr, u8 *val)
328{
329 const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
330 const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
331
332 return ssbi_read(pmic->dev->parent, addr, val, 1);
333}
334
335static int pm8921_writeb(const struct device *dev, u16 addr, u8 val)
336{
337 const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
338 const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
339
340 return ssbi_write(pmic->dev->parent, addr, &val, 1);
341}
342
343static int pm8921_read_buf(const struct device *dev, u16 addr, u8 *buf,
344 int cnt)
345{
346 const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
347 const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
348
349 return ssbi_read(pmic->dev->parent, addr, buf, cnt);
350}
351
352static int pm8921_write_buf(const struct device *dev, u16 addr, u8 *buf,
353 int cnt)
354{
355 const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
356 const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
357
358 return ssbi_write(pmic->dev->parent, addr, buf, cnt);
359}
360
361static int pm8921_read_irq_stat(const struct device *dev, int irq)
362{
363 const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
364 const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
365
366 return pm8xxx_get_irq_stat(pmic->irq_chip, irq);
367}
368
369static struct pm8xxx_drvdata pm8921_drvdata = {
370 .pmic_readb = pm8921_readb,
371 .pmic_writeb = pm8921_writeb,
372 .pmic_read_buf = pm8921_read_buf,
373 .pmic_write_buf = pm8921_write_buf,
374 .pmic_read_irq_stat = pm8921_read_irq_stat,
375};
376
377static const struct regmap_config ssbi_regmap_config = { 271static const struct regmap_config ssbi_regmap_config = {
378 .reg_bits = 16, 272 .reg_bits = 16,
379 .val_bits = 8, 273 .val_bits = 8,
@@ -392,7 +286,6 @@ MODULE_DEVICE_TABLE(of, pm8921_id_table);
392 286
393static int pm8921_probe(struct platform_device *pdev) 287static int pm8921_probe(struct platform_device *pdev)
394{ 288{
395 struct pm8921 *pmic;
396 struct regmap *regmap; 289 struct regmap *regmap;
397 int irq, rc; 290 int irq, rc;
398 unsigned int val; 291 unsigned int val;
@@ -404,12 +297,6 @@ static int pm8921_probe(struct platform_device *pdev)
404 if (irq < 0) 297 if (irq < 0)
405 return irq; 298 return irq;
406 299
407 pmic = devm_kzalloc(&pdev->dev, sizeof(struct pm8921), GFP_KERNEL);
408 if (!pmic) {
409 pr_err("Cannot alloc pm8921 struct\n");
410 return -ENOMEM;
411 }
412
413 regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent, 300 regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
414 &ssbi_regmap_config); 301 &ssbi_regmap_config);
415 if (IS_ERR(regmap)) 302 if (IS_ERR(regmap))
@@ -434,18 +321,13 @@ static int pm8921_probe(struct platform_device *pdev)
434 pr_info("PMIC revision 2: %02X\n", val); 321 pr_info("PMIC revision 2: %02X\n", val);
435 rev |= val << BITS_PER_BYTE; 322 rev |= val << BITS_PER_BYTE;
436 323
437 pmic->dev = &pdev->dev;
438 pm8921_drvdata.pm_chip_data = pmic;
439 platform_set_drvdata(pdev, &pm8921_drvdata);
440
441 chip = devm_kzalloc(&pdev->dev, sizeof(*chip) + 324 chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
442 sizeof(chip->config[0]) * nirqs, 325 sizeof(chip->config[0]) * nirqs,
443 GFP_KERNEL); 326 GFP_KERNEL);
444 if (!chip) 327 if (!chip)
445 return -ENOMEM; 328 return -ENOMEM;
446 329
447 pmic->irq_chip = chip; 330 platform_set_drvdata(pdev, chip);
448 chip->dev = &pdev->dev;
449 chip->regmap = regmap; 331 chip->regmap = regmap;
450 chip->num_irqs = nirqs; 332 chip->num_irqs = nirqs;
451 chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8); 333 chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
@@ -481,8 +363,7 @@ static int pm8921_remove_child(struct device *dev, void *unused)
481static int pm8921_remove(struct platform_device *pdev) 363static int pm8921_remove(struct platform_device *pdev)
482{ 364{
483 int irq = platform_get_irq(pdev, 0); 365 int irq = platform_get_irq(pdev, 0);
484 struct pm8921 *pmic = pm8921_drvdata.pm_chip_data; 366 struct pm_irq_chip *chip = platform_get_drvdata(pdev);
485 struct pm_irq_chip *chip = pmic->irq_chip;
486 367
487 device_for_each_child(&pdev->dev, NULL, pm8921_remove_child); 368 device_for_each_child(&pdev->dev, NULL, pm8921_remove_child);
488 irq_set_chained_handler(irq, NULL); 369 irq_set_chained_handler(irq, NULL);
diff --git a/drivers/mfd/rdc321x-southbridge.c b/drivers/mfd/rdc321x-southbridge.c
index c79569750be9..6575585f1d1f 100644
--- a/drivers/mfd/rdc321x-southbridge.c
+++ b/drivers/mfd/rdc321x-southbridge.c
@@ -38,7 +38,7 @@ static struct resource rdc321x_wdt_resource[] = {
38}; 38};
39 39
40static struct rdc321x_gpio_pdata rdc321x_gpio_pdata = { 40static struct rdc321x_gpio_pdata rdc321x_gpio_pdata = {
41 .max_gpios = RDC321X_MAX_GPIO, 41 .max_gpios = RDC321X_NUM_GPIO,
42}; 42};
43 43
44static struct resource rdc321x_gpio_resources[] = { 44static struct resource rdc321x_gpio_resources[] = {
diff --git a/drivers/mfd/rtsx_usb.c b/drivers/mfd/rtsx_usb.c
index b53b9d46cc45..6352bec8419a 100644
--- a/drivers/mfd/rtsx_usb.c
+++ b/drivers/mfd/rtsx_usb.c
@@ -29,7 +29,7 @@ static int polling_pipe = 1;
29module_param(polling_pipe, int, S_IRUGO | S_IWUSR); 29module_param(polling_pipe, int, S_IRUGO | S_IWUSR);
30MODULE_PARM_DESC(polling_pipe, "polling pipe (0: ctl, 1: bulk)"); 30MODULE_PARM_DESC(polling_pipe, "polling pipe (0: ctl, 1: bulk)");
31 31
32static struct mfd_cell rtsx_usb_cells[] = { 32static const struct mfd_cell rtsx_usb_cells[] = {
33 [RTSX_USB_SD_CARD] = { 33 [RTSX_USB_SD_CARD] = {
34 .name = "rtsx_usb_sdmmc", 34 .name = "rtsx_usb_sdmmc",
35 .pdata_size = 0, 35 .pdata_size = 0,
@@ -67,7 +67,7 @@ static int rtsx_usb_bulk_transfer_sglist(struct rtsx_ucr *ucr,
67 ucr->sg_timer.expires = jiffies + msecs_to_jiffies(timeout); 67 ucr->sg_timer.expires = jiffies + msecs_to_jiffies(timeout);
68 add_timer(&ucr->sg_timer); 68 add_timer(&ucr->sg_timer);
69 usb_sg_wait(&ucr->current_sg); 69 usb_sg_wait(&ucr->current_sg);
70 del_timer(&ucr->sg_timer); 70 del_timer_sync(&ucr->sg_timer);
71 71
72 if (act_len) 72 if (act_len)
73 *act_len = ucr->current_sg.bytes; 73 *act_len = ucr->current_sg.bytes;
@@ -644,14 +644,14 @@ static int rtsx_usb_probe(struct usb_interface *intf,
644 if (ret) 644 if (ret)
645 goto out_init_fail; 645 goto out_init_fail;
646 646
647 /* initialize USB SG transfer timer */
648 setup_timer(&ucr->sg_timer, rtsx_usb_sg_timed_out, (unsigned long) ucr);
649
647 ret = mfd_add_devices(&intf->dev, usb_dev->devnum, rtsx_usb_cells, 650 ret = mfd_add_devices(&intf->dev, usb_dev->devnum, rtsx_usb_cells,
648 ARRAY_SIZE(rtsx_usb_cells), NULL, 0, NULL); 651 ARRAY_SIZE(rtsx_usb_cells), NULL, 0, NULL);
649 if (ret) 652 if (ret)
650 goto out_init_fail; 653 goto out_init_fail;
651 654
652 /* initialize USB SG transfer timer */
653 init_timer(&ucr->sg_timer);
654 setup_timer(&ucr->sg_timer, rtsx_usb_sg_timed_out, (unsigned long) ucr);
655#ifdef CONFIG_PM 655#ifdef CONFIG_PM
656 intf->needs_remote_wakeup = 1; 656 intf->needs_remote_wakeup = 1;
657 usb_enable_autosuspend(usb_dev); 657 usb_enable_autosuspend(usb_dev);
@@ -687,9 +687,15 @@ static int rtsx_usb_suspend(struct usb_interface *intf, pm_message_t message)
687 dev_dbg(&intf->dev, "%s called with pm message 0x%04u\n", 687 dev_dbg(&intf->dev, "%s called with pm message 0x%04u\n",
688 __func__, message.event); 688 __func__, message.event);
689 689
690 /*
691 * Call to make sure LED is off during suspend to save more power.
692 * It is NOT a permanent state and could be turned on anytime later.
693 * Thus no need to call turn_on when resunming.
694 */
690 mutex_lock(&ucr->dev_mutex); 695 mutex_lock(&ucr->dev_mutex);
691 rtsx_usb_turn_off_led(ucr); 696 rtsx_usb_turn_off_led(ucr);
692 mutex_unlock(&ucr->dev_mutex); 697 mutex_unlock(&ucr->dev_mutex);
698
693 return 0; 699 return 0;
694} 700}
695 701
diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
index 1cf27521fff4..be06d0abbf19 100644
--- a/drivers/mfd/sec-core.c
+++ b/drivers/mfd/sec-core.c
@@ -25,7 +25,6 @@
25#include <linux/mfd/core.h> 25#include <linux/mfd/core.h>
26#include <linux/mfd/samsung/core.h> 26#include <linux/mfd/samsung/core.h>
27#include <linux/mfd/samsung/irq.h> 27#include <linux/mfd/samsung/irq.h>
28#include <linux/mfd/samsung/rtc.h>
29#include <linux/mfd/samsung/s2mpa01.h> 28#include <linux/mfd/samsung/s2mpa01.h>
30#include <linux/mfd/samsung/s2mps11.h> 29#include <linux/mfd/samsung/s2mps11.h>
31#include <linux/mfd/samsung/s2mps14.h> 30#include <linux/mfd/samsung/s2mps14.h>
@@ -91,7 +90,7 @@ static const struct mfd_cell s2mpa01_devs[] = {
91}; 90};
92 91
93#ifdef CONFIG_OF 92#ifdef CONFIG_OF
94static struct of_device_id sec_dt_match[] = { 93static const struct of_device_id sec_dt_match[] = {
95 { .compatible = "samsung,s5m8767-pmic", 94 { .compatible = "samsung,s5m8767-pmic",
96 .data = (void *)S5M8767X, 95 .data = (void *)S5M8767X,
97 }, { 96 }, {
@@ -196,20 +195,6 @@ static const struct regmap_config s5m8767_regmap_config = {
196 .cache_type = REGCACHE_FLAT, 195 .cache_type = REGCACHE_FLAT,
197}; 196};
198 197
199static const struct regmap_config s5m_rtc_regmap_config = {
200 .reg_bits = 8,
201 .val_bits = 8,
202
203 .max_register = SEC_RTC_REG_MAX,
204};
205
206static const struct regmap_config s2mps14_rtc_regmap_config = {
207 .reg_bits = 8,
208 .val_bits = 8,
209
210 .max_register = S2MPS_RTC_REG_MAX,
211};
212
213#ifdef CONFIG_OF 198#ifdef CONFIG_OF
214/* 199/*
215 * Only the common platform data elements for s5m8767 are parsed here from the 200 * Only the common platform data elements for s5m8767 are parsed here from the
@@ -264,8 +249,9 @@ static int sec_pmic_probe(struct i2c_client *i2c,
264 const struct i2c_device_id *id) 249 const struct i2c_device_id *id)
265{ 250{
266 struct sec_platform_data *pdata = dev_get_platdata(&i2c->dev); 251 struct sec_platform_data *pdata = dev_get_platdata(&i2c->dev);
267 const struct regmap_config *regmap, *regmap_rtc; 252 const struct regmap_config *regmap;
268 struct sec_pmic_dev *sec_pmic; 253 struct sec_pmic_dev *sec_pmic;
254 unsigned long device_type;
269 int ret; 255 int ret;
270 256
271 sec_pmic = devm_kzalloc(&i2c->dev, sizeof(struct sec_pmic_dev), 257 sec_pmic = devm_kzalloc(&i2c->dev, sizeof(struct sec_pmic_dev),
@@ -277,7 +263,7 @@ static int sec_pmic_probe(struct i2c_client *i2c,
277 sec_pmic->dev = &i2c->dev; 263 sec_pmic->dev = &i2c->dev;
278 sec_pmic->i2c = i2c; 264 sec_pmic->i2c = i2c;
279 sec_pmic->irq = i2c->irq; 265 sec_pmic->irq = i2c->irq;
280 sec_pmic->type = sec_i2c_get_driver_data(i2c, id); 266 device_type = sec_i2c_get_driver_data(i2c, id);
281 267
282 if (sec_pmic->dev->of_node) { 268 if (sec_pmic->dev->of_node) {
283 pdata = sec_pmic_i2c_parse_dt_pdata(sec_pmic->dev); 269 pdata = sec_pmic_i2c_parse_dt_pdata(sec_pmic->dev);
@@ -285,7 +271,7 @@ static int sec_pmic_probe(struct i2c_client *i2c,
285 ret = PTR_ERR(pdata); 271 ret = PTR_ERR(pdata);
286 return ret; 272 return ret;
287 } 273 }
288 pdata->device_type = sec_pmic->type; 274 pdata->device_type = device_type;
289 } 275 }
290 if (pdata) { 276 if (pdata) {
291 sec_pmic->device_type = pdata->device_type; 277 sec_pmic->device_type = pdata->device_type;
@@ -298,39 +284,21 @@ static int sec_pmic_probe(struct i2c_client *i2c,
298 switch (sec_pmic->device_type) { 284 switch (sec_pmic->device_type) {
299 case S2MPA01: 285 case S2MPA01:
300 regmap = &s2mpa01_regmap_config; 286 regmap = &s2mpa01_regmap_config;
301 /*
302 * The rtc-s5m driver does not support S2MPA01 and there
303 * is no mfd_cell for S2MPA01 RTC device.
304 * However we must pass something to devm_regmap_init_i2c()
305 * so use S5M-like regmap config even though it wouldn't work.
306 */
307 regmap_rtc = &s5m_rtc_regmap_config;
308 break; 287 break;
309 case S2MPS11X: 288 case S2MPS11X:
310 regmap = &s2mps11_regmap_config; 289 regmap = &s2mps11_regmap_config;
311 /*
312 * The rtc-s5m driver does not support S2MPS11 and there
313 * is no mfd_cell for S2MPS11 RTC device.
314 * However we must pass something to devm_regmap_init_i2c()
315 * so use S5M-like regmap config even though it wouldn't work.
316 */
317 regmap_rtc = &s5m_rtc_regmap_config;
318 break; 290 break;
319 case S2MPS14X: 291 case S2MPS14X:
320 regmap = &s2mps14_regmap_config; 292 regmap = &s2mps14_regmap_config;
321 regmap_rtc = &s2mps14_rtc_regmap_config;
322 break; 293 break;
323 case S5M8763X: 294 case S5M8763X:
324 regmap = &s5m8763_regmap_config; 295 regmap = &s5m8763_regmap_config;
325 regmap_rtc = &s5m_rtc_regmap_config;
326 break; 296 break;
327 case S5M8767X: 297 case S5M8767X:
328 regmap = &s5m8767_regmap_config; 298 regmap = &s5m8767_regmap_config;
329 regmap_rtc = &s5m_rtc_regmap_config;
330 break; 299 break;
331 default: 300 default:
332 regmap = &sec_regmap_config; 301 regmap = &sec_regmap_config;
333 regmap_rtc = &s5m_rtc_regmap_config;
334 break; 302 break;
335 } 303 }
336 304
@@ -342,21 +310,6 @@ static int sec_pmic_probe(struct i2c_client *i2c,
342 return ret; 310 return ret;
343 } 311 }
344 312
345 sec_pmic->rtc = i2c_new_dummy(i2c->adapter, RTC_I2C_ADDR);
346 if (!sec_pmic->rtc) {
347 dev_err(&i2c->dev, "Failed to allocate I2C for RTC\n");
348 return -ENODEV;
349 }
350 i2c_set_clientdata(sec_pmic->rtc, sec_pmic);
351
352 sec_pmic->regmap_rtc = devm_regmap_init_i2c(sec_pmic->rtc, regmap_rtc);
353 if (IS_ERR(sec_pmic->regmap_rtc)) {
354 ret = PTR_ERR(sec_pmic->regmap_rtc);
355 dev_err(&i2c->dev, "Failed to allocate RTC register map: %d\n",
356 ret);
357 goto err_regmap_rtc;
358 }
359
360 if (pdata && pdata->cfg_pmic_irq) 313 if (pdata && pdata->cfg_pmic_irq)
361 pdata->cfg_pmic_irq(); 314 pdata->cfg_pmic_irq();
362 315
@@ -403,8 +356,6 @@ static int sec_pmic_probe(struct i2c_client *i2c,
403 356
404err_mfd: 357err_mfd:
405 sec_irq_exit(sec_pmic); 358 sec_irq_exit(sec_pmic);
406err_regmap_rtc:
407 i2c_unregister_device(sec_pmic->rtc);
408 return ret; 359 return ret;
409} 360}
410 361
@@ -414,7 +365,6 @@ static int sec_pmic_remove(struct i2c_client *i2c)
414 365
415 mfd_remove_devices(sec_pmic->dev); 366 mfd_remove_devices(sec_pmic->dev);
416 sec_irq_exit(sec_pmic); 367 sec_irq_exit(sec_pmic);
417 i2c_unregister_device(sec_pmic->rtc);
418 return 0; 368 return 0;
419} 369}
420 370
@@ -424,19 +374,18 @@ static int sec_pmic_suspend(struct device *dev)
424 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 374 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
425 struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c); 375 struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c);
426 376
427 if (device_may_wakeup(dev)) { 377 if (device_may_wakeup(dev))
428 enable_irq_wake(sec_pmic->irq); 378 enable_irq_wake(sec_pmic->irq);
429 /* 379 /*
430 * PMIC IRQ must be disabled during suspend for RTC alarm 380 * PMIC IRQ must be disabled during suspend for RTC alarm
431 * to work properly. 381 * to work properly.
432 * When device is woken up from suspend by RTC Alarm, an 382 * When device is woken up from suspend, an
433 * interrupt occurs before resuming I2C bus controller. 383 * interrupt occurs before resuming I2C bus controller.
434 * The interrupt is handled by regmap_irq_thread which tries 384 * The interrupt is handled by regmap_irq_thread which tries
435 * to read RTC registers. This read fails (I2C is still 385 * to read RTC registers. This read fails (I2C is still
436 * suspended) and RTC Alarm interrupt is disabled. 386 * suspended) and RTC Alarm interrupt is disabled.
437 */ 387 */
438 disable_irq(sec_pmic->irq); 388 disable_irq(sec_pmic->irq);
439 }
440 389
441 return 0; 390 return 0;
442} 391}
@@ -446,10 +395,9 @@ static int sec_pmic_resume(struct device *dev)
446 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 395 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
447 struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c); 396 struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c);
448 397
449 if (device_may_wakeup(dev)) { 398 if (device_may_wakeup(dev))
450 disable_irq_wake(sec_pmic->irq); 399 disable_irq_wake(sec_pmic->irq);
451 enable_irq(sec_pmic->irq); 400 enable_irq(sec_pmic->irq);
452 }
453 401
454 return 0; 402 return 0;
455} 403}
diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c
index 64e7913aadc6..654e2c1dbf7a 100644
--- a/drivers/mfd/sec-irq.c
+++ b/drivers/mfd/sec-irq.c
@@ -385,7 +385,7 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
385 &sec_pmic->irq_data); 385 &sec_pmic->irq_data);
386 break; 386 break;
387 default: 387 default:
388 dev_err(sec_pmic->dev, "Unknown device type %d\n", 388 dev_err(sec_pmic->dev, "Unknown device type %lu\n",
389 sec_pmic->device_type); 389 sec_pmic->device_type);
390 return -EINVAL; 390 return -EINVAL;
391 } 391 }
diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
index e7dc441a8f8a..81e6d0932bf0 100644
--- a/drivers/mfd/sm501.c
+++ b/drivers/mfd/sm501.c
@@ -1726,7 +1726,7 @@ static struct pci_driver sm501_pci_driver = {
1726 1726
1727MODULE_ALIAS("platform:sm501"); 1727MODULE_ALIAS("platform:sm501");
1728 1728
1729static struct of_device_id of_sm501_match_tbl[] = { 1729static const struct of_device_id of_sm501_match_tbl[] = {
1730 { .compatible = "smi,sm501", }, 1730 { .compatible = "smi,sm501", },
1731 { /* end */ } 1731 { /* end */ }
1732}; 1732};
diff --git a/drivers/mfd/stmpe-i2c.c b/drivers/mfd/stmpe-i2c.c
index 0da02e11d58e..a45f9c0a330a 100644
--- a/drivers/mfd/stmpe-i2c.c
+++ b/drivers/mfd/stmpe-i2c.c
@@ -14,6 +14,7 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/of_device.h>
17#include "stmpe.h" 18#include "stmpe.h"
18 19
19static int i2c_reg_read(struct stmpe *stmpe, u8 reg) 20static int i2c_reg_read(struct stmpe *stmpe, u8 reg)
@@ -52,15 +53,41 @@ static struct stmpe_client_info i2c_ci = {
52 .write_block = i2c_block_write, 53 .write_block = i2c_block_write,
53}; 54};
54 55
56static const struct of_device_id stmpe_of_match[] = {
57 { .compatible = "st,stmpe610", .data = (void *)STMPE610, },
58 { .compatible = "st,stmpe801", .data = (void *)STMPE801, },
59 { .compatible = "st,stmpe811", .data = (void *)STMPE811, },
60 { .compatible = "st,stmpe1601", .data = (void *)STMPE1601, },
61 { .compatible = "st,stmpe1801", .data = (void *)STMPE1801, },
62 { .compatible = "st,stmpe2401", .data = (void *)STMPE2401, },
63 { .compatible = "st,stmpe2403", .data = (void *)STMPE2403, },
64 {},
65};
66MODULE_DEVICE_TABLE(of, stmpe_of_match);
67
55static int 68static int
56stmpe_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) 69stmpe_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
57{ 70{
71 int partnum;
72 const struct of_device_id *of_id;
73
58 i2c_ci.data = (void *)id; 74 i2c_ci.data = (void *)id;
59 i2c_ci.irq = i2c->irq; 75 i2c_ci.irq = i2c->irq;
60 i2c_ci.client = i2c; 76 i2c_ci.client = i2c;
61 i2c_ci.dev = &i2c->dev; 77 i2c_ci.dev = &i2c->dev;
62 78
63 return stmpe_probe(&i2c_ci, id->driver_data); 79 of_id = of_match_device(stmpe_of_match, &i2c->dev);
80 if (!of_id) {
81 /*
82 * This happens when the I2C ID matches the node name
83 * but no real compatible string has been given.
84 */
85 dev_info(&i2c->dev, "matching on node name, compatible is preferred\n");
86 partnum = id->driver_data;
87 } else
88 partnum = (int)of_id->data;
89
90 return stmpe_probe(&i2c_ci, partnum);
64} 91}
65 92
66static int stmpe_i2c_remove(struct i2c_client *i2c) 93static int stmpe_i2c_remove(struct i2c_client *i2c)
@@ -89,6 +116,7 @@ static struct i2c_driver stmpe_i2c_driver = {
89#ifdef CONFIG_PM 116#ifdef CONFIG_PM
90 .pm = &stmpe_dev_pm_ops, 117 .pm = &stmpe_dev_pm_ops,
91#endif 118#endif
119 .of_match_table = stmpe_of_match,
92 }, 120 },
93 .probe = stmpe_i2c_probe, 121 .probe = stmpe_i2c_probe,
94 .remove = stmpe_i2c_remove, 122 .remove = stmpe_i2c_remove,
diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c
index 4a91f6771fb8..3b6bfa7184ad 100644
--- a/drivers/mfd/stmpe.c
+++ b/drivers/mfd/stmpe.c
@@ -20,6 +20,7 @@
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include <linux/mfd/core.h> 21#include <linux/mfd/core.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/regulator/consumer.h>
23#include "stmpe.h" 24#include "stmpe.h"
24 25
25static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 26static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
@@ -605,9 +606,18 @@ static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
605 606
606 if (blocks & STMPE_BLOCK_GPIO) 607 if (blocks & STMPE_BLOCK_GPIO)
607 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO; 608 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
609 else
610 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO;
608 611
609 if (blocks & STMPE_BLOCK_KEYPAD) 612 if (blocks & STMPE_BLOCK_KEYPAD)
610 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC; 613 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
614 else
615 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC;
616
617 if (blocks & STMPE_BLOCK_PWM)
618 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM;
619 else
620 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
611 621
612 return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL, mask, 622 return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL, mask,
613 enable ? mask : 0); 623 enable ? mask : 0);
@@ -986,9 +996,6 @@ static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np)
986 int base = 0; 996 int base = 0;
987 int num_irqs = stmpe->variant->num_irqs; 997 int num_irqs = stmpe->variant->num_irqs;
988 998
989 if (!np)
990 base = stmpe->irq_base;
991
992 stmpe->domain = irq_domain_add_simple(np, num_irqs, base, 999 stmpe->domain = irq_domain_add_simple(np, num_irqs, base,
993 &stmpe_irq_ops, stmpe); 1000 &stmpe_irq_ops, stmpe);
994 if (!stmpe->domain) { 1001 if (!stmpe->domain) {
@@ -1067,7 +1074,7 @@ static int stmpe_chip_init(struct stmpe *stmpe)
1067static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell) 1074static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
1068{ 1075{
1069 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1, 1076 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
1070 NULL, stmpe->irq_base, stmpe->domain); 1077 NULL, 0, stmpe->domain);
1071} 1078}
1072 1079
1073static int stmpe_devices_init(struct stmpe *stmpe) 1080static int stmpe_devices_init(struct stmpe *stmpe)
@@ -1171,12 +1178,23 @@ int stmpe_probe(struct stmpe_client_info *ci, int partnum)
1171 stmpe->dev = ci->dev; 1178 stmpe->dev = ci->dev;
1172 stmpe->client = ci->client; 1179 stmpe->client = ci->client;
1173 stmpe->pdata = pdata; 1180 stmpe->pdata = pdata;
1174 stmpe->irq_base = pdata->irq_base;
1175 stmpe->ci = ci; 1181 stmpe->ci = ci;
1176 stmpe->partnum = partnum; 1182 stmpe->partnum = partnum;
1177 stmpe->variant = stmpe_variant_info[partnum]; 1183 stmpe->variant = stmpe_variant_info[partnum];
1178 stmpe->regs = stmpe->variant->regs; 1184 stmpe->regs = stmpe->variant->regs;
1179 stmpe->num_gpios = stmpe->variant->num_gpios; 1185 stmpe->num_gpios = stmpe->variant->num_gpios;
1186 stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc");
1187 if (!IS_ERR(stmpe->vcc)) {
1188 ret = regulator_enable(stmpe->vcc);
1189 if (ret)
1190 dev_warn(ci->dev, "failed to enable VCC supply\n");
1191 }
1192 stmpe->vio = devm_regulator_get_optional(ci->dev, "vio");
1193 if (!IS_ERR(stmpe->vio)) {
1194 ret = regulator_enable(stmpe->vio);
1195 if (ret)
1196 dev_warn(ci->dev, "failed to enable VIO supply\n");
1197 }
1180 dev_set_drvdata(stmpe->dev, stmpe); 1198 dev_set_drvdata(stmpe->dev, stmpe);
1181 1199
1182 if (ci->init) 1200 if (ci->init)
@@ -1243,6 +1261,11 @@ int stmpe_probe(struct stmpe_client_info *ci, int partnum)
1243 1261
1244int stmpe_remove(struct stmpe *stmpe) 1262int stmpe_remove(struct stmpe *stmpe)
1245{ 1263{
1264 if (!IS_ERR(stmpe->vio))
1265 regulator_disable(stmpe->vio);
1266 if (!IS_ERR(stmpe->vcc))
1267 regulator_disable(stmpe->vcc);
1268
1246 mfd_remove_devices(stmpe->dev); 1269 mfd_remove_devices(stmpe->dev);
1247 1270
1248 return 0; 1271 return 0;
diff --git a/drivers/mfd/stmpe.h b/drivers/mfd/stmpe.h
index 6639f1b0fef5..9e4d21d37a11 100644
--- a/drivers/mfd/stmpe.h
+++ b/drivers/mfd/stmpe.h
@@ -192,7 +192,7 @@ int stmpe_remove(struct stmpe *stmpe);
192 192
193#define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3) 193#define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)
194#define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1) 194#define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1)
195#define STMPE1601_SYSCON_ENABLE_SPWM (1 << 0) 195#define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)
196 196
197/* The 1601/2403 share the same masks */ 197/* The 1601/2403 share the same masks */
198#define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7) 198#define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
new file mode 100644
index 000000000000..718fc4d2adc0
--- /dev/null
+++ b/drivers/mfd/sun6i-prcm.c
@@ -0,0 +1,134 @@
1/*
2 * Copyright (C) 2014 Free Electrons
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6 *
7 * Allwinner PRCM (Power/Reset/Clock Management) driver
8 *
9 */
10
11#include <linux/mfd/core.h>
12#include <linux/module.h>
13#include <linux/of.h>
14
15struct prcm_data {
16 int nsubdevs;
17 const struct mfd_cell *subdevs;
18};
19
20static const struct resource sun6i_a31_ar100_clk_res[] = {
21 {
22 .start = 0x0,
23 .end = 0x3,
24 .flags = IORESOURCE_MEM,
25 },
26};
27
28static const struct resource sun6i_a31_apb0_clk_res[] = {
29 {
30 .start = 0xc,
31 .end = 0xf,
32 .flags = IORESOURCE_MEM,
33 },
34};
35
36static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
37 {
38 .start = 0x28,
39 .end = 0x2b,
40 .flags = IORESOURCE_MEM,
41 },
42};
43
44static const struct resource sun6i_a31_apb0_rstc_res[] = {
45 {
46 .start = 0xb0,
47 .end = 0xb3,
48 .flags = IORESOURCE_MEM,
49 },
50};
51
52static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
53 {
54 .name = "sun6i-a31-ar100-clk",
55 .of_compatible = "allwinner,sun6i-a31-ar100-clk",
56 .num_resources = ARRAY_SIZE(sun6i_a31_ar100_clk_res),
57 .resources = sun6i_a31_ar100_clk_res,
58 },
59 {
60 .name = "sun6i-a31-apb0-clk",
61 .of_compatible = "allwinner,sun6i-a31-apb0-clk",
62 .num_resources = ARRAY_SIZE(sun6i_a31_apb0_clk_res),
63 .resources = sun6i_a31_apb0_clk_res,
64 },
65 {
66 .name = "sun6i-a31-apb0-gates-clk",
67 .of_compatible = "allwinner,sun6i-a31-apb0-gates-clk",
68 .num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
69 .resources = sun6i_a31_apb0_gates_clk_res,
70 },
71 {
72 .name = "sun6i-a31-apb0-clock-reset",
73 .of_compatible = "allwinner,sun6i-a31-clock-reset",
74 .num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
75 .resources = sun6i_a31_apb0_rstc_res,
76 },
77};
78
79static const struct prcm_data sun6i_a31_prcm_data = {
80 .nsubdevs = ARRAY_SIZE(sun6i_a31_prcm_subdevs),
81 .subdevs = sun6i_a31_prcm_subdevs,
82};
83
84static const struct of_device_id sun6i_prcm_dt_ids[] = {
85 {
86 .compatible = "allwinner,sun6i-a31-prcm",
87 .data = &sun6i_a31_prcm_data,
88 },
89 { /* sentinel */ },
90};
91
92static int sun6i_prcm_probe(struct platform_device *pdev)
93{
94 struct device_node *np = pdev->dev.of_node;
95 const struct of_device_id *match;
96 const struct prcm_data *data;
97 struct resource *res;
98 int ret;
99
100 match = of_match_node(sun6i_prcm_dt_ids, np);
101 if (!match)
102 return -EINVAL;
103
104 data = match->data;
105
106 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
107 if (!res) {
108 dev_err(&pdev->dev, "no prcm memory region provided\n");
109 return -ENOENT;
110 }
111
112 ret = mfd_add_devices(&pdev->dev, 0, data->subdevs, data->nsubdevs,
113 res, -1, NULL);
114 if (ret) {
115 dev_err(&pdev->dev, "failed to add subdevices\n");
116 return ret;
117 }
118
119 return 0;
120}
121
122static struct platform_driver sun6i_prcm_driver = {
123 .driver = {
124 .name = "sun6i-prcm",
125 .owner = THIS_MODULE,
126 .of_match_table = sun6i_prcm_dt_ids,
127 },
128 .probe = sun6i_prcm_probe,
129};
130module_platform_driver(sun6i_prcm_driver);
131
132MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
133MODULE_DESCRIPTION("Allwinner sun6i PRCM driver");
134MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index e2a04bb8bc1e..ca15878ce5c0 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -95,7 +95,11 @@ struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
95 struct device_node *syscon_np; 95 struct device_node *syscon_np;
96 struct regmap *regmap; 96 struct regmap *regmap;
97 97
98 syscon_np = of_parse_phandle(np, property, 0); 98 if (property)
99 syscon_np = of_parse_phandle(np, property, 0);
100 else
101 syscon_np = np;
102
99 if (!syscon_np) 103 if (!syscon_np)
100 return ERR_PTR(-ENODEV); 104 return ERR_PTR(-ENODEV);
101 105
diff --git a/drivers/mfd/tps6507x.c b/drivers/mfd/tps6507x.c
index 3b27482a174f..a2e1990c9de7 100644
--- a/drivers/mfd/tps6507x.c
+++ b/drivers/mfd/tps6507x.c
@@ -119,7 +119,7 @@ static const struct i2c_device_id tps6507x_i2c_id[] = {
119MODULE_DEVICE_TABLE(i2c, tps6507x_i2c_id); 119MODULE_DEVICE_TABLE(i2c, tps6507x_i2c_id);
120 120
121#ifdef CONFIG_OF 121#ifdef CONFIG_OF
122static struct of_device_id tps6507x_of_match[] = { 122static const struct of_device_id tps6507x_of_match[] = {
123 {.compatible = "ti,tps6507x", }, 123 {.compatible = "ti,tps6507x", },
124 {}, 124 {},
125}; 125};
diff --git a/drivers/mfd/tps65218.c b/drivers/mfd/tps65218.c
index a74bfb59f18f..0d256cb002eb 100644
--- a/drivers/mfd/tps65218.c
+++ b/drivers/mfd/tps65218.c
@@ -197,6 +197,7 @@ static struct regmap_irq_chip tps65218_irq_chip = {
197 197
198static const struct of_device_id of_tps65218_match_table[] = { 198static const struct of_device_id of_tps65218_match_table[] = {
199 { .compatible = "ti,tps65218", }, 199 { .compatible = "ti,tps65218", },
200 {}
200}; 201};
201 202
202static int tps65218_probe(struct i2c_client *client, 203static int tps65218_probe(struct i2c_client *client,
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index 835e5549ecdd..8e1dbc469580 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -444,7 +444,7 @@ static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *clien
444 return pdata; 444 return pdata;
445} 445}
446 446
447static struct of_device_id tps6586x_of_match[] = { 447static const struct of_device_id tps6586x_of_match[] = {
448 { .compatible = "ti,tps6586x", }, 448 { .compatible = "ti,tps6586x", },
449 { }, 449 { },
450}; 450};
diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c
index 460a014ca629..f9e42ea1cb1a 100644
--- a/drivers/mfd/tps65910.c
+++ b/drivers/mfd/tps65910.c
@@ -379,7 +379,7 @@ err_sleep_init:
379} 379}
380 380
381#ifdef CONFIG_OF 381#ifdef CONFIG_OF
382static struct of_device_id tps65910_of_match[] = { 382static const struct of_device_id tps65910_of_match[] = {
383 { .compatible = "ti,tps65910", .data = (void *)TPS65910}, 383 { .compatible = "ti,tps65910", .data = (void *)TPS65910},
384 { .compatible = "ti,tps65911", .data = (void *)TPS65911}, 384 { .compatible = "ti,tps65911", .data = (void *)TPS65911},
385 { }, 385 { },
diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c
index 6e88f25832fb..ae26d84b3a59 100644
--- a/drivers/mfd/twl6040.c
+++ b/drivers/mfd/twl6040.c
@@ -87,8 +87,13 @@ static struct reg_default twl6040_defaults[] = {
87}; 87};
88 88
89static struct reg_default twl6040_patch[] = { 89static struct reg_default twl6040_patch[] = {
90 /* Select I2C bus access to dual access registers */ 90 /*
91 { TWL6040_REG_ACCCTL, 0x09 }, 91 * Select I2C bus access to dual access registers
92 * Interrupt register is cleared on read
93 * Select fast mode for i2c (400KHz)
94 */
95 { TWL6040_REG_ACCCTL,
96 TWL6040_I2CSEL | TWL6040_INTCLRMODE | TWL6040_I2CMODE(1) },
92}; 97};
93 98
94 99
@@ -286,6 +291,8 @@ int twl6040_power(struct twl6040 *twl6040, int on)
286 if (twl6040->power_count++) 291 if (twl6040->power_count++)
287 goto out; 292 goto out;
288 293
294 clk_prepare_enable(twl6040->clk32k);
295
289 /* Allow writes to the chip */ 296 /* Allow writes to the chip */
290 regcache_cache_only(twl6040->regmap, false); 297 regcache_cache_only(twl6040->regmap, false);
291 298
@@ -341,6 +348,8 @@ int twl6040_power(struct twl6040 *twl6040, int on)
341 348
342 twl6040->sysclk = 0; 349 twl6040->sysclk = 0;
343 twl6040->mclk = 0; 350 twl6040->mclk = 0;
351
352 clk_disable_unprepare(twl6040->clk32k);
344 } 353 }
345 354
346out: 355out:
@@ -432,12 +441,9 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
432 TWL6040_HPLLENA; 441 TWL6040_HPLLENA;
433 break; 442 break;
434 case 19200000: 443 case 19200000:
435 /* 444 /* PLL enabled, bypass mode */
436 * PLL disabled 445 hppllctl |= TWL6040_MCLK_19200KHZ |
437 * (enable PLL if MCLK jitter quality 446 TWL6040_HPLLBP | TWL6040_HPLLENA;
438 * doesn't meet specification)
439 */
440 hppllctl |= TWL6040_MCLK_19200KHZ;
441 break; 447 break;
442 case 26000000: 448 case 26000000:
443 /* PLL enabled, active mode */ 449 /* PLL enabled, active mode */
@@ -445,9 +451,9 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
445 TWL6040_HPLLENA; 451 TWL6040_HPLLENA;
446 break; 452 break;
447 case 38400000: 453 case 38400000:
448 /* PLL enabled, active mode */ 454 /* PLL enabled, bypass mode */
449 hppllctl |= TWL6040_MCLK_38400KHZ | 455 hppllctl |= TWL6040_MCLK_38400KHZ |
450 TWL6040_HPLLENA; 456 TWL6040_HPLLBP | TWL6040_HPLLENA;
451 break; 457 break;
452 default: 458 default:
453 dev_err(twl6040->dev, 459 dev_err(twl6040->dev,
@@ -639,6 +645,12 @@ static int twl6040_probe(struct i2c_client *client,
639 645
640 i2c_set_clientdata(client, twl6040); 646 i2c_set_clientdata(client, twl6040);
641 647
648 twl6040->clk32k = devm_clk_get(&client->dev, "clk32k");
649 if (IS_ERR(twl6040->clk32k)) {
650 dev_info(&client->dev, "clk32k is not handled\n");
651 twl6040->clk32k = NULL;
652 }
653
642 twl6040->supplies[0].supply = "vio"; 654 twl6040->supplies[0].supply = "vio";
643 twl6040->supplies[1].supply = "v2v1"; 655 twl6040->supplies[1].supply = "v2v1";
644 ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES, 656 ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
@@ -660,6 +672,9 @@ static int twl6040_probe(struct i2c_client *client,
660 mutex_init(&twl6040->mutex); 672 mutex_init(&twl6040->mutex);
661 init_completion(&twl6040->ready); 673 init_completion(&twl6040->ready);
662 674
675 regmap_register_patch(twl6040->regmap, twl6040_patch,
676 ARRAY_SIZE(twl6040_patch));
677
663 twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV); 678 twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
664 if (twl6040->rev < 0) { 679 if (twl6040->rev < 0) {
665 dev_err(&client->dev, "Failed to read revision register: %d\n", 680 dev_err(&client->dev, "Failed to read revision register: %d\n",
@@ -679,6 +694,9 @@ static int twl6040_probe(struct i2c_client *client,
679 GPIOF_OUT_INIT_LOW, "audpwron"); 694 GPIOF_OUT_INIT_LOW, "audpwron");
680 if (ret) 695 if (ret)
681 goto gpio_err; 696 goto gpio_err;
697
698 /* Clear any pending interrupt */
699 twl6040_reg_read(twl6040, TWL6040_REG_INTID);
682 } 700 }
683 701
684 ret = regmap_add_irq_chip(twl6040->regmap, twl6040->irq, IRQF_ONESHOT, 702 ret = regmap_add_irq_chip(twl6040->regmap, twl6040->irq, IRQF_ONESHOT,
@@ -707,10 +725,6 @@ static int twl6040_probe(struct i2c_client *client,
707 goto readyirq_err; 725 goto readyirq_err;
708 } 726 }
709 727
710 /* dual-access registers controlled by I2C only */
711 regmap_register_patch(twl6040->regmap, twl6040_patch,
712 ARRAY_SIZE(twl6040_patch));
713
714 /* 728 /*
715 * The main functionality of twl6040 to provide audio on OMAP4+ systems. 729 * The main functionality of twl6040 to provide audio on OMAP4+ systems.
716 * We can add the ASoC codec child whenever this driver has been loaded. 730 * We can add the ASoC codec child whenever this driver has been loaded.
diff --git a/drivers/mfd/wm5102-tables.c b/drivers/mfd/wm5102-tables.c
index 070f8cfbbd7a..c8a993bd17ae 100644
--- a/drivers/mfd/wm5102-tables.c
+++ b/drivers/mfd/wm5102-tables.c
@@ -333,7 +333,7 @@ static const struct reg_default wm5102_reg_default[] = {
333 { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */ 333 { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */
334 { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */ 334 { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
335 { 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */ 335 { 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */
336 { 0x00000212, 0x0001 }, /* R530 - LDO1 Control 2 */ 336 { 0x00000212, 0x0000 }, /* R530 - LDO1 Control 2 */
337 { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */ 337 { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */
338 { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */ 338 { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */
339 { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */ 339 { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */
@@ -1037,6 +1037,8 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg)
1037 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: 1037 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
1038 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5: 1038 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
1039 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6: 1039 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
1040 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_7:
1041 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_8:
1040 case ARIZONA_COMFORT_NOISE_GENERATOR: 1042 case ARIZONA_COMFORT_NOISE_GENERATOR:
1041 case ARIZONA_HAPTICS_CONTROL_1: 1043 case ARIZONA_HAPTICS_CONTROL_1:
1042 case ARIZONA_HAPTICS_CONTROL_2: 1044 case ARIZONA_HAPTICS_CONTROL_2:
diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c
index 1942b6f231da..41a7f6fb7802 100644
--- a/drivers/mfd/wm5110-tables.c
+++ b/drivers/mfd/wm5110-tables.c
@@ -468,10 +468,12 @@ static const struct reg_default wm5110_reg_default[] = {
468 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */ 468 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
469 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */ 469 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
470 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */ 470 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
471 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 1 */ 471 { 0x00000066, 0x01FF }, /* R102 - Always On Triggers Sequence Select 1 */
472 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 2 */ 472 { 0x00000067, 0x01FF }, /* R103 - Always On Triggers Sequence Select 2 */
473 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 3 */ 473 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */
474 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 4 */ 474 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */
475 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */
476 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */
475 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */ 477 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
476 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */ 478 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
477 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */ 479 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
@@ -549,6 +551,7 @@ static const struct reg_default wm5110_reg_default[] = {
549 { 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */ 551 { 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */
550 { 0x000002A9, 0x300A }, /* R681 - Mic Detect Level 4 */ 552 { 0x000002A9, 0x300A }, /* R681 - Mic Detect Level 4 */
551 { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */ 553 { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
554 { 0x000002CB, 0x0000 }, /* R715 - Isolation control */
552 { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */ 555 { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
553 { 0x00000300, 0x0000 }, /* R768 - Input Enables */ 556 { 0x00000300, 0x0000 }, /* R768 - Input Enables */
554 { 0x00000308, 0x0000 }, /* R776 - Input Rate */ 557 { 0x00000308, 0x0000 }, /* R776 - Input Rate */
@@ -1498,6 +1501,8 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1498 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2: 1501 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
1499 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3: 1502 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
1500 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: 1503 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
1504 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
1505 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
1501 case ARIZONA_COMFORT_NOISE_GENERATOR: 1506 case ARIZONA_COMFORT_NOISE_GENERATOR:
1502 case ARIZONA_HAPTICS_CONTROL_1: 1507 case ARIZONA_HAPTICS_CONTROL_1:
1503 case ARIZONA_HAPTICS_CONTROL_2: 1508 case ARIZONA_HAPTICS_CONTROL_2:
@@ -1580,6 +1585,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1580 case ARIZONA_MIC_DETECT_LEVEL_3: 1585 case ARIZONA_MIC_DETECT_LEVEL_3:
1581 case ARIZONA_MIC_DETECT_LEVEL_4: 1586 case ARIZONA_MIC_DETECT_LEVEL_4:
1582 case ARIZONA_MIC_NOISE_MIX_CONTROL_1: 1587 case ARIZONA_MIC_NOISE_MIX_CONTROL_1:
1588 case ARIZONA_ISOLATION_CONTROL:
1583 case ARIZONA_JACK_DETECT_ANALOGUE: 1589 case ARIZONA_JACK_DETECT_ANALOGUE:
1584 case ARIZONA_INPUT_ENABLES: 1590 case ARIZONA_INPUT_ENABLES:
1585 case ARIZONA_INPUT_ENABLES_STATUS: 1591 case ARIZONA_INPUT_ENABLES_STATUS:
diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
index e5eae751aa1b..c6fb5d16ca09 100644
--- a/drivers/mfd/wm8400-core.c
+++ b/drivers/mfd/wm8400-core.c
@@ -64,7 +64,7 @@ EXPORT_SYMBOL_GPL(wm8400_block_read);
64 64
65static int wm8400_register_codec(struct wm8400 *wm8400) 65static int wm8400_register_codec(struct wm8400 *wm8400)
66{ 66{
67 struct mfd_cell cell = { 67 const struct mfd_cell cell = {
68 .name = "wm8400-codec", 68 .name = "wm8400-codec",
69 .platform_data = wm8400, 69 .platform_data = wm8400,
70 .pdata_size = sizeof(*wm8400), 70 .pdata_size = sizeof(*wm8400),
diff --git a/drivers/mfd/wm8997-tables.c b/drivers/mfd/wm8997-tables.c
index 5aa807687777..c7a81da64ee1 100644
--- a/drivers/mfd/wm8997-tables.c
+++ b/drivers/mfd/wm8997-tables.c
@@ -174,10 +174,10 @@ static const struct reg_default wm8997_reg_default[] = {
174 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */ 174 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
175 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */ 175 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
176 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */ 176 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
177 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 1 */ 177 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */
178 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 2 */ 178 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */
179 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 3 */ 179 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */
180 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 4 */ 180 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */
181 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */ 181 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
182 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */ 182 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
183 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */ 183 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
@@ -814,10 +814,10 @@ static bool wm8997_readable_register(struct device *dev, unsigned int reg)
814 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: 814 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
815 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: 815 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
816 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4: 816 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
817 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
818 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
819 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3: 817 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
820 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: 818 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
819 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
820 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
821 case ARIZONA_COMFORT_NOISE_GENERATOR: 821 case ARIZONA_COMFORT_NOISE_GENERATOR:
822 case ARIZONA_HAPTICS_CONTROL_1: 822 case ARIZONA_HAPTICS_CONTROL_1:
823 case ARIZONA_HAPTICS_CONTROL_2: 823 case ARIZONA_HAPTICS_CONTROL_2:
@@ -846,6 +846,7 @@ static bool wm8997_readable_register(struct device *dev, unsigned int reg)
846 case ARIZONA_RATE_ESTIMATOR_3: 846 case ARIZONA_RATE_ESTIMATOR_3:
847 case ARIZONA_RATE_ESTIMATOR_4: 847 case ARIZONA_RATE_ESTIMATOR_4:
848 case ARIZONA_RATE_ESTIMATOR_5: 848 case ARIZONA_RATE_ESTIMATOR_5:
849 case ARIZONA_DYNAMIC_FREQUENCY_SCALING_1:
849 case ARIZONA_FLL1_CONTROL_1: 850 case ARIZONA_FLL1_CONTROL_1:
850 case ARIZONA_FLL1_CONTROL_2: 851 case ARIZONA_FLL1_CONTROL_2:
851 case ARIZONA_FLL1_CONTROL_3: 852 case ARIZONA_FLL1_CONTROL_3:
@@ -880,6 +881,7 @@ static bool wm8997_readable_register(struct device *dev, unsigned int reg)
880 case ARIZONA_FLL2_GPIO_CLOCK: 881 case ARIZONA_FLL2_GPIO_CLOCK:
881 case ARIZONA_MIC_CHARGE_PUMP_1: 882 case ARIZONA_MIC_CHARGE_PUMP_1:
882 case ARIZONA_LDO1_CONTROL_1: 883 case ARIZONA_LDO1_CONTROL_1:
884 case ARIZONA_LDO1_CONTROL_2:
883 case ARIZONA_LDO2_CONTROL_1: 885 case ARIZONA_LDO2_CONTROL_1:
884 case ARIZONA_MIC_BIAS_CTRL_1: 886 case ARIZONA_MIC_BIAS_CTRL_1:
885 case ARIZONA_MIC_BIAS_CTRL_2: 887 case ARIZONA_MIC_BIAS_CTRL_2:
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 8aaf8c1f3f63..b675882307e4 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -694,3 +694,10 @@ config MMC_REALTEK_PCI
694 help 694 help
695 Say Y here to include driver code to support SD/MMC card interface 695 Say Y here to include driver code to support SD/MMC card interface
696 of Realtek PCI-E card reader 696 of Realtek PCI-E card reader
697
698config MMC_REALTEK_USB
699 tristate "Realtek USB SD/MMC Card Interface Driver"
700 depends on MFD_RTSX_USB
701 help
702 Say Y here to include driver code to support SD/MMC card interface
703 of Realtek RTS5129/39 series card reader
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 0c8aa5e1e304..3eb48b656f25 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_MMC_USHC) += ushc.o
52obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o 52obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
53 53
54obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o 54obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
55obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
55 56
56obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o 57obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
57obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o 58obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
diff --git a/drivers/mmc/host/rtsx_usb_sdmmc.c b/drivers/mmc/host/rtsx_usb_sdmmc.c
new file mode 100644
index 000000000000..e11fafa6fc6b
--- /dev/null
+++ b/drivers/mmc/host/rtsx_usb_sdmmc.c
@@ -0,0 +1,1455 @@
1/* Realtek USB SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
16 *
17 * Author:
18 * Roger Tseng <rogerable@realtek.com>
19 */
20
21#include <linux/module.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/usb.h>
26#include <linux/mmc/host.h>
27#include <linux/mmc/mmc.h>
28#include <linux/mmc/sd.h>
29#include <linux/mmc/sdio.h>
30#include <linux/mmc/card.h>
31#include <linux/scatterlist.h>
32#include <linux/pm_runtime.h>
33
34#include <linux/mfd/rtsx_usb.h>
35#include <asm/unaligned.h>
36
37#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
38#include <linux/leds.h>
39#include <linux/workqueue.h>
40#define RTSX_USB_USE_LEDS_CLASS
41#endif
42
43struct rtsx_usb_sdmmc {
44 struct platform_device *pdev;
45 struct rtsx_ucr *ucr;
46 struct mmc_host *mmc;
47 struct mmc_request *mrq;
48
49 struct mutex host_mutex;
50
51 u8 ssc_depth;
52 unsigned int clock;
53 bool vpclk;
54 bool double_clk;
55 bool host_removal;
56 bool card_exist;
57 bool initial_mode;
58 bool ddr_mode;
59
60 unsigned char power_mode;
61
62#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
63 struct led_classdev led;
64 char led_name[32];
65 struct work_struct led_work;
66#endif
67};
68
69static inline struct device *sdmmc_dev(struct rtsx_usb_sdmmc *host)
70{
71 return &(host->pdev->dev);
72}
73
74static inline void sd_clear_error(struct rtsx_usb_sdmmc *host)
75{
76 struct rtsx_ucr *ucr = host->ucr;
77 rtsx_usb_ep0_write_register(ucr, CARD_STOP,
78 SD_STOP | SD_CLR_ERR,
79 SD_STOP | SD_CLR_ERR);
80
81 rtsx_usb_clear_dma_err(ucr);
82 rtsx_usb_clear_fsm_err(ucr);
83}
84
85#ifdef DEBUG
86static void sd_print_debug_regs(struct rtsx_usb_sdmmc *host)
87{
88 struct rtsx_ucr *ucr = host->ucr;
89 u8 val = 0;
90
91 rtsx_usb_ep0_read_register(ucr, SD_STAT1, &val);
92 dev_dbg(sdmmc_dev(host), "SD_STAT1: 0x%x\n", val);
93 rtsx_usb_ep0_read_register(ucr, SD_STAT2, &val);
94 dev_dbg(sdmmc_dev(host), "SD_STAT2: 0x%x\n", val);
95 rtsx_usb_ep0_read_register(ucr, SD_BUS_STAT, &val);
96 dev_dbg(sdmmc_dev(host), "SD_BUS_STAT: 0x%x\n", val);
97}
98#else
99#define sd_print_debug_regs(host)
100#endif /* DEBUG */
101
102static int sd_read_data(struct rtsx_usb_sdmmc *host, struct mmc_command *cmd,
103 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
104{
105 struct rtsx_ucr *ucr = host->ucr;
106 int err;
107 u8 trans_mode;
108
109 if (!buf)
110 buf_len = 0;
111
112 rtsx_usb_init_cmd(ucr);
113 if (cmd != NULL) {
114 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__
115 , cmd->opcode);
116 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
117 trans_mode = SD_TM_AUTO_TUNING;
118 else
119 trans_mode = SD_TM_NORMAL_READ;
120
121 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
122 SD_CMD0, 0xFF, (u8)(cmd->opcode) | 0x40);
123 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
124 SD_CMD1, 0xFF, (u8)(cmd->arg >> 24));
125 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
126 SD_CMD2, 0xFF, (u8)(cmd->arg >> 16));
127 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
128 SD_CMD3, 0xFF, (u8)(cmd->arg >> 8));
129 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
130 SD_CMD4, 0xFF, (u8)cmd->arg);
131 } else {
132 trans_mode = SD_TM_AUTO_READ_3;
133 }
134
135 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
136 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BYTE_CNT_H,
137 0xFF, (u8)(byte_cnt >> 8));
138 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
139 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
140
141 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG2, 0xFF,
142 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
143 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
144 if (trans_mode != SD_TM_AUTO_TUNING)
145 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
146 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
147
148 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_TRANSFER,
149 0xFF, trans_mode | SD_TRANSFER_START);
150 rtsx_usb_add_cmd(ucr, CHECK_REG_CMD, SD_TRANSFER,
151 SD_TRANSFER_END, SD_TRANSFER_END);
152
153 if (cmd != NULL) {
154 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_CMD1, 0, 0);
155 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_CMD2, 0, 0);
156 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_CMD3, 0, 0);
157 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_CMD4, 0, 0);
158 }
159
160 err = rtsx_usb_send_cmd(ucr, MODE_CR, timeout);
161 if (err) {
162 dev_dbg(sdmmc_dev(host),
163 "rtsx_usb_send_cmd failed (err = %d)\n", err);
164 return err;
165 }
166
167 err = rtsx_usb_get_rsp(ucr, !cmd ? 1 : 5, timeout);
168 if (err || (ucr->rsp_buf[0] & SD_TRANSFER_ERR)) {
169 sd_print_debug_regs(host);
170
171 if (!err) {
172 dev_dbg(sdmmc_dev(host),
173 "Transfer failed (SD_TRANSFER = %02x)\n",
174 ucr->rsp_buf[0]);
175 err = -EIO;
176 } else {
177 dev_dbg(sdmmc_dev(host),
178 "rtsx_usb_get_rsp failed (err = %d)\n", err);
179 }
180
181 return err;
182 }
183
184 if (cmd != NULL) {
185 cmd->resp[0] = get_unaligned_be32(ucr->rsp_buf + 1);
186 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
187 cmd->resp[0]);
188 }
189
190 if (buf && buf_len) {
191 /* 2-byte aligned part */
192 err = rtsx_usb_read_ppbuf(ucr, buf, byte_cnt - (byte_cnt % 2));
193 if (err) {
194 dev_dbg(sdmmc_dev(host),
195 "rtsx_usb_read_ppbuf failed (err = %d)\n", err);
196 return err;
197 }
198
199 /* unaligned byte */
200 if (byte_cnt % 2)
201 return rtsx_usb_read_register(ucr,
202 PPBUF_BASE2 + byte_cnt,
203 buf + byte_cnt - 1);
204 }
205
206 return 0;
207}
208
209static int sd_write_data(struct rtsx_usb_sdmmc *host, struct mmc_command *cmd,
210 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
211{
212 struct rtsx_ucr *ucr = host->ucr;
213 int err;
214 u8 trans_mode;
215
216 if (!buf)
217 buf_len = 0;
218
219 if (buf && buf_len) {
220 err = rtsx_usb_write_ppbuf(ucr, buf, buf_len);
221 if (err) {
222 dev_dbg(sdmmc_dev(host),
223 "rtsx_usb_write_ppbuf failed (err = %d)\n",
224 err);
225 return err;
226 }
227 }
228
229 trans_mode = (cmd != NULL) ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
230 rtsx_usb_init_cmd(ucr);
231
232 if (cmd != NULL) {
233 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__,
234 cmd->opcode);
235 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
236 SD_CMD0, 0xFF, (u8)(cmd->opcode) | 0x40);
237 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
238 SD_CMD1, 0xFF, (u8)(cmd->arg >> 24));
239 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
240 SD_CMD2, 0xFF, (u8)(cmd->arg >> 16));
241 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
242 SD_CMD3, 0xFF, (u8)(cmd->arg >> 8));
243 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
244 SD_CMD4, 0xFF, (u8)cmd->arg);
245 }
246
247 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
248 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BYTE_CNT_H,
249 0xFF, (u8)(byte_cnt >> 8));
250 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
251 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
252
253 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG2, 0xFF,
254 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
255 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
256 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
257 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
258
259 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
260 trans_mode | SD_TRANSFER_START);
261 rtsx_usb_add_cmd(ucr, CHECK_REG_CMD, SD_TRANSFER,
262 SD_TRANSFER_END, SD_TRANSFER_END);
263
264 if (cmd != NULL) {
265 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_CMD1, 0, 0);
266 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_CMD2, 0, 0);
267 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_CMD3, 0, 0);
268 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_CMD4, 0, 0);
269 }
270
271 err = rtsx_usb_send_cmd(ucr, MODE_CR, timeout);
272 if (err) {
273 dev_dbg(sdmmc_dev(host),
274 "rtsx_usb_send_cmd failed (err = %d)\n", err);
275 return err;
276 }
277
278 err = rtsx_usb_get_rsp(ucr, !cmd ? 1 : 5, timeout);
279 if (err) {
280 sd_print_debug_regs(host);
281 dev_dbg(sdmmc_dev(host),
282 "rtsx_usb_get_rsp failed (err = %d)\n", err);
283 return err;
284 }
285
286 if (cmd != NULL) {
287 cmd->resp[0] = get_unaligned_be32(ucr->rsp_buf + 1);
288 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
289 cmd->resp[0]);
290 }
291
292 return 0;
293}
294
295static void sd_send_cmd_get_rsp(struct rtsx_usb_sdmmc *host,
296 struct mmc_command *cmd)
297{
298 struct rtsx_ucr *ucr = host->ucr;
299 u8 cmd_idx = (u8)cmd->opcode;
300 u32 arg = cmd->arg;
301 int err = 0;
302 int timeout = 100;
303 int i;
304 u8 *ptr;
305 int stat_idx = 0;
306 int len = 2;
307 u8 rsp_type;
308
309 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
310 __func__, cmd_idx, arg);
311
312 /* Response type:
313 * R0
314 * R1, R5, R6, R7
315 * R1b
316 * R2
317 * R3, R4
318 */
319 switch (mmc_resp_type(cmd)) {
320 case MMC_RSP_NONE:
321 rsp_type = SD_RSP_TYPE_R0;
322 break;
323 case MMC_RSP_R1:
324 rsp_type = SD_RSP_TYPE_R1;
325 break;
326 case MMC_RSP_R1 & ~MMC_RSP_CRC:
327 rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
328 break;
329 case MMC_RSP_R1B:
330 rsp_type = SD_RSP_TYPE_R1b;
331 break;
332 case MMC_RSP_R2:
333 rsp_type = SD_RSP_TYPE_R2;
334 break;
335 case MMC_RSP_R3:
336 rsp_type = SD_RSP_TYPE_R3;
337 break;
338 default:
339 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
340 err = -EINVAL;
341 goto out;
342 }
343
344 if (rsp_type == SD_RSP_TYPE_R1b)
345 timeout = 3000;
346
347 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
348 err = rtsx_usb_write_register(ucr, SD_BUS_STAT,
349 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
350 SD_CLK_TOGGLE_EN);
351 if (err)
352 goto out;
353 }
354
355 rtsx_usb_init_cmd(ucr);
356
357 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
358 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
359 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
360 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
361 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
362
363 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
364 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_DATA_SOURCE,
365 0x01, PINGPONG_BUFFER);
366 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_TRANSFER,
367 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
368 rtsx_usb_add_cmd(ucr, CHECK_REG_CMD, SD_TRANSFER,
369 SD_TRANSFER_END | SD_STAT_IDLE,
370 SD_TRANSFER_END | SD_STAT_IDLE);
371
372 if (rsp_type == SD_RSP_TYPE_R2) {
373 /* Read data from ping-pong buffer */
374 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
375 rtsx_usb_add_cmd(ucr, READ_REG_CMD, (u16)i, 0, 0);
376 stat_idx = 16;
377 } else if (rsp_type != SD_RSP_TYPE_R0) {
378 /* Read data from SD_CMDx registers */
379 for (i = SD_CMD0; i <= SD_CMD4; i++)
380 rtsx_usb_add_cmd(ucr, READ_REG_CMD, (u16)i, 0, 0);
381 stat_idx = 5;
382 }
383 len += stat_idx;
384
385 rtsx_usb_add_cmd(ucr, READ_REG_CMD, SD_STAT1, 0, 0);
386
387 err = rtsx_usb_send_cmd(ucr, MODE_CR, 100);
388 if (err) {
389 dev_dbg(sdmmc_dev(host),
390 "rtsx_usb_send_cmd error (err = %d)\n", err);
391 goto out;
392 }
393
394 err = rtsx_usb_get_rsp(ucr, len, timeout);
395 if (err || (ucr->rsp_buf[0] & SD_TRANSFER_ERR)) {
396 sd_print_debug_regs(host);
397 sd_clear_error(host);
398
399 if (!err) {
400 dev_dbg(sdmmc_dev(host),
401 "Transfer failed (SD_TRANSFER = %02x)\n",
402 ucr->rsp_buf[0]);
403 err = -EIO;
404 } else {
405 dev_dbg(sdmmc_dev(host),
406 "rtsx_usb_get_rsp failed (err = %d)\n", err);
407 }
408
409 goto out;
410 }
411
412 if (rsp_type == SD_RSP_TYPE_R0) {
413 err = 0;
414 goto out;
415 }
416
417 /* Skip result of CHECK_REG_CMD */
418 ptr = ucr->rsp_buf + 1;
419
420 /* Check (Start,Transmission) bit of Response */
421 if ((ptr[0] & 0xC0) != 0) {
422 err = -EILSEQ;
423 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
424 goto out;
425 }
426
427 /* Check CRC7 */
428 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
429 if (ptr[stat_idx] & SD_CRC7_ERR) {
430 err = -EILSEQ;
431 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
432 goto out;
433 }
434 }
435
436 if (rsp_type == SD_RSP_TYPE_R2) {
437 for (i = 0; i < 4; i++) {
438 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
439 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
440 i, cmd->resp[i]);
441 }
442 } else {
443 cmd->resp[0] = get_unaligned_be32(ptr + 1);
444 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
445 cmd->resp[0]);
446 }
447
448out:
449 cmd->error = err;
450}
451
452static int sd_rw_multi(struct rtsx_usb_sdmmc *host, struct mmc_request *mrq)
453{
454 struct rtsx_ucr *ucr = host->ucr;
455 struct mmc_data *data = mrq->data;
456 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
457 u8 cfg2, trans_mode;
458 int err;
459 u8 flag;
460 size_t data_len = data->blksz * data->blocks;
461 unsigned int pipe;
462
463 if (read) {
464 dev_dbg(sdmmc_dev(host), "%s: read %zu bytes\n",
465 __func__, data_len);
466 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
467 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
468 trans_mode = SD_TM_AUTO_READ_3;
469 } else {
470 dev_dbg(sdmmc_dev(host), "%s: write %zu bytes\n",
471 __func__, data_len);
472 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
473 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
474 trans_mode = SD_TM_AUTO_WRITE_3;
475 }
476
477 rtsx_usb_init_cmd(ucr);
478
479 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
480 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
481 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
482 0xFF, (u8)data->blocks);
483 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
484 0xFF, (u8)(data->blocks >> 8));
485
486 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_DATA_SOURCE,
487 0x01, RING_BUFFER);
488
489 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_TC3,
490 0xFF, (u8)(data_len >> 24));
491 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_TC2,
492 0xFF, (u8)(data_len >> 16));
493 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_TC1,
494 0xFF, (u8)(data_len >> 8));
495 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_TC0,
496 0xFF, (u8)data_len);
497 if (read) {
498 flag = MODE_CDIR;
499 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_CTL,
500 0x03 | DMA_PACK_SIZE_MASK,
501 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
502 } else {
503 flag = MODE_CDOR;
504 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, MC_DMA_CTL,
505 0x03 | DMA_PACK_SIZE_MASK,
506 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
507 }
508
509 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
510 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
511 trans_mode | SD_TRANSFER_START);
512 rtsx_usb_add_cmd(ucr, CHECK_REG_CMD, SD_TRANSFER,
513 SD_TRANSFER_END, SD_TRANSFER_END);
514
515 err = rtsx_usb_send_cmd(ucr, flag, 100);
516 if (err)
517 return err;
518
519 if (read)
520 pipe = usb_rcvbulkpipe(ucr->pusb_dev, EP_BULK_IN);
521 else
522 pipe = usb_sndbulkpipe(ucr->pusb_dev, EP_BULK_OUT);
523
524 err = rtsx_usb_transfer_data(ucr, pipe, data->sg, data_len,
525 data->sg_len, NULL, 10000);
526 if (err) {
527 dev_dbg(sdmmc_dev(host), "rtsx_usb_transfer_data error %d\n"
528 , err);
529 sd_clear_error(host);
530 return err;
531 }
532
533 return rtsx_usb_get_rsp(ucr, 1, 2000);
534}
535
536static inline void sd_enable_initial_mode(struct rtsx_usb_sdmmc *host)
537{
538 rtsx_usb_write_register(host->ucr, SD_CFG1,
539 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
540}
541
542static inline void sd_disable_initial_mode(struct rtsx_usb_sdmmc *host)
543{
544 rtsx_usb_write_register(host->ucr, SD_CFG1,
545 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
546}
547
548static void sd_normal_rw(struct rtsx_usb_sdmmc *host,
549 struct mmc_request *mrq)
550{
551 struct mmc_command *cmd = mrq->cmd;
552 struct mmc_data *data = mrq->data;
553 u8 *buf;
554
555 buf = kzalloc(data->blksz, GFP_NOIO);
556 if (!buf) {
557 cmd->error = -ENOMEM;
558 return;
559 }
560
561 if (data->flags & MMC_DATA_READ) {
562 if (host->initial_mode)
563 sd_disable_initial_mode(host);
564
565 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
566 data->blksz, 200);
567
568 if (host->initial_mode)
569 sd_enable_initial_mode(host);
570
571 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
572 } else {
573 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
574
575 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
576 data->blksz, 200);
577 }
578
579 kfree(buf);
580}
581
582static int sd_change_phase(struct rtsx_usb_sdmmc *host, u8 sample_point, int tx)
583{
584 struct rtsx_ucr *ucr = host->ucr;
585 int err;
586
587 dev_dbg(sdmmc_dev(host), "%s: %s sample_point = %d\n",
588 __func__, tx ? "TX" : "RX", sample_point);
589
590 rtsx_usb_init_cmd(ucr);
591
592 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
593
594 if (tx)
595 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL,
596 0x0F, sample_point);
597 else
598 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK1_CTL,
599 0x0F, sample_point);
600
601 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
602 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL,
603 PHASE_NOT_RESET, PHASE_NOT_RESET);
604 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0);
605 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_RST, 0);
606
607 err = rtsx_usb_send_cmd(ucr, MODE_C, 100);
608 if (err)
609 return err;
610
611 return 0;
612}
613
614static inline u32 get_phase_point(u32 phase_map, unsigned int idx)
615{
616 idx &= MAX_PHASE;
617 return phase_map & (1 << idx);
618}
619
620static int get_phase_len(u32 phase_map, unsigned int idx)
621{
622 int i;
623
624 for (i = 0; i < MAX_PHASE + 1; i++) {
625 if (get_phase_point(phase_map, idx + i) == 0)
626 return i;
627 }
628 return MAX_PHASE + 1;
629}
630
631static u8 sd_search_final_phase(struct rtsx_usb_sdmmc *host, u32 phase_map)
632{
633 int start = 0, len = 0;
634 int start_final = 0, len_final = 0;
635 u8 final_phase = 0xFF;
636
637 if (phase_map == 0) {
638 dev_dbg(sdmmc_dev(host), "Phase: [map:%x]\n", phase_map);
639 return final_phase;
640 }
641
642 while (start < MAX_PHASE + 1) {
643 len = get_phase_len(phase_map, start);
644 if (len_final < len) {
645 start_final = start;
646 len_final = len;
647 }
648 start += len ? len : 1;
649 }
650
651 final_phase = (start_final + len_final / 2) & MAX_PHASE;
652 dev_dbg(sdmmc_dev(host), "Phase: [map:%x] [maxlen:%d] [final:%d]\n",
653 phase_map, len_final, final_phase);
654
655 return final_phase;
656}
657
658static void sd_wait_data_idle(struct rtsx_usb_sdmmc *host)
659{
660 int err, i;
661 u8 val = 0;
662
663 for (i = 0; i < 100; i++) {
664 err = rtsx_usb_ep0_read_register(host->ucr,
665 SD_DATA_STATE, &val);
666 if (val & SD_DATA_IDLE)
667 return;
668
669 usleep_range(100, 1000);
670 }
671}
672
673static int sd_tuning_rx_cmd(struct rtsx_usb_sdmmc *host,
674 u8 opcode, u8 sample_point)
675{
676 int err;
677 struct mmc_command cmd = {0};
678
679 err = sd_change_phase(host, sample_point, 0);
680 if (err)
681 return err;
682
683 cmd.opcode = MMC_SEND_TUNING_BLOCK;
684 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
685 if (err) {
686 /* Wait till SD DATA IDLE */
687 sd_wait_data_idle(host);
688 sd_clear_error(host);
689 return err;
690 }
691
692 return 0;
693}
694
695static void sd_tuning_phase(struct rtsx_usb_sdmmc *host,
696 u8 opcode, u16 *phase_map)
697{
698 int err, i;
699 u16 raw_phase_map = 0;
700
701 for (i = MAX_PHASE; i >= 0; i--) {
702 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
703 if (!err)
704 raw_phase_map |= 1 << i;
705 }
706
707 if (phase_map)
708 *phase_map = raw_phase_map;
709}
710
711static int sd_tuning_rx(struct rtsx_usb_sdmmc *host, u8 opcode)
712{
713 int err, i;
714 u16 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
715 u8 final_phase;
716
717 /* setting fixed default TX phase */
718 err = sd_change_phase(host, 0x01, 1);
719 if (err) {
720 dev_dbg(sdmmc_dev(host), "TX phase setting failed\n");
721 return err;
722 }
723
724 /* tuning RX phase */
725 for (i = 0; i < RX_TUNING_CNT; i++) {
726 sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
727
728 if (raw_phase_map[i] == 0)
729 break;
730 }
731
732 phase_map = 0xFFFF;
733 for (i = 0; i < RX_TUNING_CNT; i++) {
734 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%04x\n",
735 i, raw_phase_map[i]);
736 phase_map &= raw_phase_map[i];
737 }
738 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%04x\n", phase_map);
739
740 if (phase_map) {
741 final_phase = sd_search_final_phase(host, phase_map);
742 if (final_phase == 0xFF)
743 return -EINVAL;
744
745 err = sd_change_phase(host, final_phase, 0);
746 if (err)
747 return err;
748 } else {
749 return -EINVAL;
750 }
751
752 return 0;
753}
754
755static int sdmmc_get_ro(struct mmc_host *mmc)
756{
757 struct rtsx_usb_sdmmc *host = mmc_priv(mmc);
758 struct rtsx_ucr *ucr = host->ucr;
759 int err;
760 u16 val;
761
762 if (host->host_removal)
763 return -ENOMEDIUM;
764
765 mutex_lock(&ucr->dev_mutex);
766
767 /* Check SD card detect */
768 err = rtsx_usb_get_card_status(ucr, &val);
769
770 mutex_unlock(&ucr->dev_mutex);
771
772
773 /* Treat failed detection as non-ro */
774 if (err)
775 return 0;
776
777 if (val & SD_WP)
778 return 1;
779
780 return 0;
781}
782
783static int sdmmc_get_cd(struct mmc_host *mmc)
784{
785 struct rtsx_usb_sdmmc *host = mmc_priv(mmc);
786 struct rtsx_ucr *ucr = host->ucr;
787 int err;
788 u16 val;
789
790 if (host->host_removal)
791 return -ENOMEDIUM;
792
793 mutex_lock(&ucr->dev_mutex);
794
795 /* Check SD card detect */
796 err = rtsx_usb_get_card_status(ucr, &val);
797
798 mutex_unlock(&ucr->dev_mutex);
799
800 /* Treat failed detection as non-exist */
801 if (err)
802 goto no_card;
803
804 if (val & SD_CD) {
805 host->card_exist = true;
806 return 1;
807 }
808
809no_card:
810 host->card_exist = false;
811 return 0;
812}
813
814static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
815{
816 struct rtsx_usb_sdmmc *host = mmc_priv(mmc);
817 struct rtsx_ucr *ucr = host->ucr;
818 struct mmc_command *cmd = mrq->cmd;
819 struct mmc_data *data = mrq->data;
820 unsigned int data_size = 0;
821
822 dev_dbg(sdmmc_dev(host), "%s\n", __func__);
823
824 if (host->host_removal) {
825 cmd->error = -ENOMEDIUM;
826 goto finish;
827 }
828
829 if ((!host->card_exist)) {
830 cmd->error = -ENOMEDIUM;
831 goto finish_detect_card;
832 }
833
834 /*
835 * Reject SDIO CMDs to speed up card identification
836 * since unsupported
837 */
838 if (cmd->opcode == SD_IO_SEND_OP_COND ||
839 cmd->opcode == SD_IO_RW_DIRECT ||
840 cmd->opcode == SD_IO_RW_EXTENDED) {
841 cmd->error = -EINVAL;
842 goto finish;
843 }
844
845 mutex_lock(&ucr->dev_mutex);
846
847 mutex_lock(&host->host_mutex);
848 host->mrq = mrq;
849 mutex_unlock(&host->host_mutex);
850
851 if (mrq->data)
852 data_size = data->blocks * data->blksz;
853
854 if (!data_size) {
855 sd_send_cmd_get_rsp(host, cmd);
856 } else if ((!(data_size % 512) && cmd->opcode != MMC_SEND_EXT_CSD) ||
857 mmc_op_multi(cmd->opcode)) {
858 sd_send_cmd_get_rsp(host, cmd);
859
860 if (!cmd->error) {
861 sd_rw_multi(host, mrq);
862
863 if (mmc_op_multi(cmd->opcode) && mrq->stop) {
864 sd_send_cmd_get_rsp(host, mrq->stop);
865 rtsx_usb_write_register(ucr, MC_FIFO_CTL,
866 FIFO_FLUSH, FIFO_FLUSH);
867 }
868 }
869 } else {
870 sd_normal_rw(host, mrq);
871 }
872
873 if (mrq->data) {
874 if (cmd->error || data->error)
875 data->bytes_xfered = 0;
876 else
877 data->bytes_xfered = data->blocks * data->blksz;
878 }
879
880 mutex_unlock(&ucr->dev_mutex);
881
882finish_detect_card:
883 if (cmd->error) {
884 /*
885 * detect card when fail to update card existence state and
886 * speed up card removal when retry
887 */
888 sdmmc_get_cd(mmc);
889 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
890 }
891
892finish:
893 mutex_lock(&host->host_mutex);
894 host->mrq = NULL;
895 mutex_unlock(&host->host_mutex);
896
897 mmc_request_done(mmc, mrq);
898}
899
900static int sd_set_bus_width(struct rtsx_usb_sdmmc *host,
901 unsigned char bus_width)
902{
903 int err = 0;
904 u8 width[] = {
905 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
906 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
907 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
908 };
909
910 if (bus_width <= MMC_BUS_WIDTH_8)
911 err = rtsx_usb_write_register(host->ucr, SD_CFG1,
912 0x03, width[bus_width]);
913
914 return err;
915}
916
917static int sd_pull_ctl_disable_lqfp48(struct rtsx_ucr *ucr)
918{
919 rtsx_usb_init_cmd(ucr);
920
921 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
922 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
923 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
924 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
925 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
926 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
927
928 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
929}
930
931static int sd_pull_ctl_disable_qfn24(struct rtsx_ucr *ucr)
932{
933 rtsx_usb_init_cmd(ucr);
934
935 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
936 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
937 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
938 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
939 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
940 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
941
942 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
943}
944
945static int sd_pull_ctl_enable_lqfp48(struct rtsx_ucr *ucr)
946{
947 rtsx_usb_init_cmd(ucr);
948
949 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
950 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
951 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xA9);
952 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
953 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
954 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
955
956 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
957}
958
959static int sd_pull_ctl_enable_qfn24(struct rtsx_ucr *ucr)
960{
961 rtsx_usb_init_cmd(ucr);
962
963 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA5);
964 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x9A);
965 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xA5);
966 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x9A);
967 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x65);
968 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x5A);
969
970 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
971}
972
973static int sd_power_on(struct rtsx_usb_sdmmc *host)
974{
975 struct rtsx_ucr *ucr = host->ucr;
976 int err;
977
978 dev_dbg(sdmmc_dev(host), "%s\n", __func__);
979 rtsx_usb_init_cmd(ucr);
980 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
981 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_SHARE_MODE,
982 CARD_SHARE_MASK, CARD_SHARE_SD);
983 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_CLK_EN,
984 SD_CLK_EN, SD_CLK_EN);
985 err = rtsx_usb_send_cmd(ucr, MODE_C, 100);
986 if (err)
987 return err;
988
989 if (CHECK_PKG(ucr, LQFP48))
990 err = sd_pull_ctl_enable_lqfp48(ucr);
991 else
992 err = sd_pull_ctl_enable_qfn24(ucr);
993 if (err)
994 return err;
995
996 err = rtsx_usb_write_register(ucr, CARD_PWR_CTL,
997 POWER_MASK, PARTIAL_POWER_ON);
998 if (err)
999 return err;
1000
1001 usleep_range(800, 1000);
1002
1003 rtsx_usb_init_cmd(ucr);
1004 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PWR_CTL,
1005 POWER_MASK|LDO3318_PWR_MASK, POWER_ON|LDO_ON);
1006 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_OE,
1007 SD_OUTPUT_EN, SD_OUTPUT_EN);
1008
1009 return rtsx_usb_send_cmd(ucr, MODE_C, 100);
1010}
1011
1012static int sd_power_off(struct rtsx_usb_sdmmc *host)
1013{
1014 struct rtsx_ucr *ucr = host->ucr;
1015 int err;
1016
1017 dev_dbg(sdmmc_dev(host), "%s\n", __func__);
1018 rtsx_usb_init_cmd(ucr);
1019
1020 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
1021 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
1022 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PWR_CTL,
1023 POWER_MASK, POWER_OFF);
1024 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_PWR_CTL,
1025 POWER_MASK|LDO3318_PWR_MASK, POWER_OFF|LDO_SUSPEND);
1026
1027 err = rtsx_usb_send_cmd(ucr, MODE_C, 100);
1028 if (err)
1029 return err;
1030
1031 if (CHECK_PKG(ucr, LQFP48))
1032 return sd_pull_ctl_disable_lqfp48(ucr);
1033 return sd_pull_ctl_disable_qfn24(ucr);
1034}
1035
1036static int sd_set_power_mode(struct rtsx_usb_sdmmc *host,
1037 unsigned char power_mode)
1038{
1039 int err;
1040
1041 if (power_mode != MMC_POWER_OFF)
1042 power_mode = MMC_POWER_ON;
1043
1044 if (power_mode == host->power_mode)
1045 return 0;
1046
1047 if (power_mode == MMC_POWER_OFF) {
1048 err = sd_power_off(host);
1049 pm_runtime_put(sdmmc_dev(host));
1050 } else {
1051 pm_runtime_get_sync(sdmmc_dev(host));
1052 err = sd_power_on(host);
1053 }
1054
1055 if (!err)
1056 host->power_mode = power_mode;
1057
1058 return err;
1059}
1060
1061static int sd_set_timing(struct rtsx_usb_sdmmc *host,
1062 unsigned char timing, bool *ddr_mode)
1063{
1064 struct rtsx_ucr *ucr = host->ucr;
1065 int err;
1066
1067 *ddr_mode = false;
1068
1069 rtsx_usb_init_cmd(ucr);
1070
1071 switch (timing) {
1072 case MMC_TIMING_UHS_SDR104:
1073 case MMC_TIMING_UHS_SDR50:
1074 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG1,
1075 0x0C | SD_ASYNC_FIFO_RST,
1076 SD_30_MODE | SD_ASYNC_FIFO_RST);
1077 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1078 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1079 break;
1080
1081 case MMC_TIMING_UHS_DDR50:
1082 *ddr_mode = true;
1083
1084 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG1,
1085 0x0C | SD_ASYNC_FIFO_RST,
1086 SD_DDR_MODE | SD_ASYNC_FIFO_RST);
1087 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1088 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1089 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1090 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1091 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1092 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1093 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1094 break;
1095
1096 case MMC_TIMING_MMC_HS:
1097 case MMC_TIMING_SD_HS:
1098 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG1,
1099 0x0C, SD_20_MODE);
1100 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1101 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1102 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1103 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1104 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1105 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1106 break;
1107
1108 default:
1109 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
1110 SD_CFG1, 0x0C, SD_20_MODE);
1111 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1112 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1113 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD,
1114 SD_PUSH_POINT_CTL, 0xFF, 0);
1115 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1116 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1117 break;
1118 }
1119
1120 err = rtsx_usb_send_cmd(ucr, MODE_C, 100);
1121
1122 return err;
1123}
1124
1125static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1126{
1127 struct rtsx_usb_sdmmc *host = mmc_priv(mmc);
1128 struct rtsx_ucr *ucr = host->ucr;
1129
1130 dev_dbg(sdmmc_dev(host), "%s\n", __func__);
1131 mutex_lock(&ucr->dev_mutex);
1132
1133 if (rtsx_usb_card_exclusive_check(ucr, RTSX_USB_SD_CARD)) {
1134 mutex_unlock(&ucr->dev_mutex);
1135 return;
1136 }
1137
1138 sd_set_power_mode(host, ios->power_mode);
1139 sd_set_bus_width(host, ios->bus_width);
1140 sd_set_timing(host, ios->timing, &host->ddr_mode);
1141
1142 host->vpclk = false;
1143 host->double_clk = true;
1144
1145 switch (ios->timing) {
1146 case MMC_TIMING_UHS_SDR104:
1147 case MMC_TIMING_UHS_SDR50:
1148 host->ssc_depth = SSC_DEPTH_2M;
1149 host->vpclk = true;
1150 host->double_clk = false;
1151 break;
1152 case MMC_TIMING_UHS_DDR50:
1153 case MMC_TIMING_UHS_SDR25:
1154 host->ssc_depth = SSC_DEPTH_1M;
1155 break;
1156 default:
1157 host->ssc_depth = SSC_DEPTH_512K;
1158 break;
1159 }
1160
1161 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1162 host->clock = ios->clock;
1163
1164 rtsx_usb_switch_clock(host->ucr, host->clock, host->ssc_depth,
1165 host->initial_mode, host->double_clk, host->vpclk);
1166
1167 mutex_unlock(&ucr->dev_mutex);
1168 dev_dbg(sdmmc_dev(host), "%s end\n", __func__);
1169}
1170
1171static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1172{
1173 struct rtsx_usb_sdmmc *host = mmc_priv(mmc);
1174 struct rtsx_ucr *ucr = host->ucr;
1175 int err = 0;
1176
1177 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1178 __func__, ios->signal_voltage);
1179
1180 if (host->host_removal)
1181 return -ENOMEDIUM;
1182
1183 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_120)
1184 return -EPERM;
1185
1186 mutex_lock(&ucr->dev_mutex);
1187
1188 err = rtsx_usb_card_exclusive_check(ucr, RTSX_USB_SD_CARD);
1189 if (err) {
1190 mutex_unlock(&ucr->dev_mutex);
1191 return err;
1192 }
1193
1194 /* Let mmc core do the busy checking, simply stop the forced-toggle
1195 * clock(while issuing CMD11) and switch voltage.
1196 */
1197 rtsx_usb_init_cmd(ucr);
1198
1199 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1200 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_PAD_CTL,
1201 SD_IO_USING_1V8, SD_IO_USING_3V3);
1202 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, LDO_POWER_CFG,
1203 TUNE_SD18_MASK, TUNE_SD18_3V3);
1204 } else {
1205 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_BUS_STAT,
1206 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
1207 SD_CLK_FORCE_STOP);
1208 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_PAD_CTL,
1209 SD_IO_USING_1V8, SD_IO_USING_1V8);
1210 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, LDO_POWER_CFG,
1211 TUNE_SD18_MASK, TUNE_SD18_1V8);
1212 }
1213
1214 err = rtsx_usb_send_cmd(ucr, MODE_C, 100);
1215 mutex_unlock(&ucr->dev_mutex);
1216
1217 return err;
1218}
1219
1220static int sdmmc_card_busy(struct mmc_host *mmc)
1221{
1222 struct rtsx_usb_sdmmc *host = mmc_priv(mmc);
1223 struct rtsx_ucr *ucr = host->ucr;
1224 int err;
1225 u8 stat;
1226 u8 mask = SD_DAT3_STATUS | SD_DAT2_STATUS | SD_DAT1_STATUS
1227 | SD_DAT0_STATUS;
1228
1229 dev_dbg(sdmmc_dev(host), "%s\n", __func__);
1230
1231 mutex_lock(&ucr->dev_mutex);
1232
1233 err = rtsx_usb_write_register(ucr, SD_BUS_STAT,
1234 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
1235 SD_CLK_TOGGLE_EN);
1236 if (err)
1237 goto out;
1238
1239 mdelay(1);
1240
1241 err = rtsx_usb_read_register(ucr, SD_BUS_STAT, &stat);
1242 if (err)
1243 goto out;
1244
1245 err = rtsx_usb_write_register(ucr, SD_BUS_STAT,
1246 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1247out:
1248 mutex_unlock(&ucr->dev_mutex);
1249
1250 if (err)
1251 return err;
1252
1253 /* check if any pin between dat[0:3] is low */
1254 if ((stat & mask) != mask)
1255 return 1;
1256 else
1257 return 0;
1258}
1259
1260static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1261{
1262 struct rtsx_usb_sdmmc *host = mmc_priv(mmc);
1263 struct rtsx_ucr *ucr = host->ucr;
1264 int err = 0;
1265
1266 if (host->host_removal)
1267 return -ENOMEDIUM;
1268
1269 mutex_lock(&ucr->dev_mutex);
1270
1271 if (!host->ddr_mode)
1272 err = sd_tuning_rx(host, MMC_SEND_TUNING_BLOCK);
1273
1274 mutex_unlock(&ucr->dev_mutex);
1275
1276 return err;
1277}
1278
1279static const struct mmc_host_ops rtsx_usb_sdmmc_ops = {
1280 .request = sdmmc_request,
1281 .set_ios = sdmmc_set_ios,
1282 .get_ro = sdmmc_get_ro,
1283 .get_cd = sdmmc_get_cd,
1284 .start_signal_voltage_switch = sdmmc_switch_voltage,
1285 .card_busy = sdmmc_card_busy,
1286 .execute_tuning = sdmmc_execute_tuning,
1287};
1288
1289#ifdef RTSX_USB_USE_LEDS_CLASS
1290static void rtsx_usb_led_control(struct led_classdev *led,
1291 enum led_brightness brightness)
1292{
1293 struct rtsx_usb_sdmmc *host = container_of(led,
1294 struct rtsx_usb_sdmmc, led);
1295
1296 if (host->host_removal)
1297 return;
1298
1299 host->led.brightness = brightness;
1300 schedule_work(&host->led_work);
1301}
1302
1303static void rtsx_usb_update_led(struct work_struct *work)
1304{
1305 struct rtsx_usb_sdmmc *host =
1306 container_of(work, struct rtsx_usb_sdmmc, led_work);
1307 struct rtsx_ucr *ucr = host->ucr;
1308
1309 mutex_lock(&ucr->dev_mutex);
1310
1311 if (host->led.brightness == LED_OFF)
1312 rtsx_usb_turn_off_led(ucr);
1313 else
1314 rtsx_usb_turn_on_led(ucr);
1315
1316 mutex_unlock(&ucr->dev_mutex);
1317}
1318#endif
1319
1320static void rtsx_usb_init_host(struct rtsx_usb_sdmmc *host)
1321{
1322 struct mmc_host *mmc = host->mmc;
1323
1324 mmc->f_min = 250000;
1325 mmc->f_max = 208000000;
1326 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1327 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1328 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1329 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
1330 MMC_CAP_NEEDS_POLL;
1331
1332 mmc->max_current_330 = 400;
1333 mmc->max_current_180 = 800;
1334 mmc->ops = &rtsx_usb_sdmmc_ops;
1335 mmc->max_segs = 256;
1336 mmc->max_seg_size = 65536;
1337 mmc->max_blk_size = 512;
1338 mmc->max_blk_count = 65535;
1339 mmc->max_req_size = 524288;
1340
1341 host->power_mode = MMC_POWER_OFF;
1342}
1343
1344static int rtsx_usb_sdmmc_drv_probe(struct platform_device *pdev)
1345{
1346 struct mmc_host *mmc;
1347 struct rtsx_usb_sdmmc *host;
1348 struct rtsx_ucr *ucr;
1349#ifdef RTSX_USB_USE_LEDS_CLASS
1350 int err;
1351#endif
1352
1353 ucr = usb_get_intfdata(to_usb_interface(pdev->dev.parent));
1354 if (!ucr)
1355 return -ENXIO;
1356
1357 dev_dbg(&(pdev->dev), ": Realtek USB SD/MMC controller found\n");
1358
1359 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1360 if (!mmc)
1361 return -ENOMEM;
1362
1363 host = mmc_priv(mmc);
1364 host->ucr = ucr;
1365 host->mmc = mmc;
1366 host->pdev = pdev;
1367 platform_set_drvdata(pdev, host);
1368
1369 mutex_init(&host->host_mutex);
1370 rtsx_usb_init_host(host);
1371 pm_runtime_enable(&pdev->dev);
1372
1373#ifdef RTSX_USB_USE_LEDS_CLASS
1374 snprintf(host->led_name, sizeof(host->led_name),
1375 "%s::", mmc_hostname(mmc));
1376 host->led.name = host->led_name;
1377 host->led.brightness = LED_OFF;
1378 host->led.default_trigger = mmc_hostname(mmc);
1379 host->led.brightness_set = rtsx_usb_led_control;
1380
1381 err = led_classdev_register(mmc_dev(mmc), &host->led);
1382 if (err)
1383 dev_err(&(pdev->dev),
1384 "Failed to register LED device: %d\n", err);
1385 INIT_WORK(&host->led_work, rtsx_usb_update_led);
1386
1387#endif
1388 mmc_add_host(mmc);
1389
1390 return 0;
1391}
1392
1393static int rtsx_usb_sdmmc_drv_remove(struct platform_device *pdev)
1394{
1395 struct rtsx_usb_sdmmc *host = platform_get_drvdata(pdev);
1396 struct mmc_host *mmc;
1397
1398 if (!host)
1399 return 0;
1400
1401 mmc = host->mmc;
1402 host->host_removal = true;
1403
1404 mutex_lock(&host->host_mutex);
1405 if (host->mrq) {
1406 dev_dbg(&(pdev->dev),
1407 "%s: Controller removed during transfer\n",
1408 mmc_hostname(mmc));
1409 host->mrq->cmd->error = -ENOMEDIUM;
1410 if (host->mrq->stop)
1411 host->mrq->stop->error = -ENOMEDIUM;
1412 mmc_request_done(mmc, host->mrq);
1413 }
1414 mutex_unlock(&host->host_mutex);
1415
1416 mmc_remove_host(mmc);
1417
1418#ifdef RTSX_USB_USE_LEDS_CLASS
1419 cancel_work_sync(&host->led_work);
1420 led_classdev_unregister(&host->led);
1421#endif
1422
1423 mmc_free_host(mmc);
1424 pm_runtime_disable(&pdev->dev);
1425 platform_set_drvdata(pdev, NULL);
1426
1427 dev_dbg(&(pdev->dev),
1428 ": Realtek USB SD/MMC module has been removed\n");
1429
1430 return 0;
1431}
1432
1433static struct platform_device_id rtsx_usb_sdmmc_ids[] = {
1434 {
1435 .name = "rtsx_usb_sdmmc",
1436 }, {
1437 /* sentinel */
1438 }
1439};
1440MODULE_DEVICE_TABLE(platform, rtsx_usb_sdmmc_ids);
1441
1442static struct platform_driver rtsx_usb_sdmmc_driver = {
1443 .probe = rtsx_usb_sdmmc_drv_probe,
1444 .remove = rtsx_usb_sdmmc_drv_remove,
1445 .id_table = rtsx_usb_sdmmc_ids,
1446 .driver = {
1447 .owner = THIS_MODULE,
1448 .name = "rtsx_usb_sdmmc",
1449 },
1450};
1451module_platform_driver(rtsx_usb_sdmmc_driver);
1452
1453MODULE_LICENSE("GPL v2");
1454MODULE_AUTHOR("Roger Tseng <rogerable@realtek.com>");
1455MODULE_DESCRIPTION("Realtek USB SD/MMC Card Host Driver");
diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c
index 476af93543f6..8ec2d6a1dbe1 100644
--- a/drivers/rtc/rtc-s5m.c
+++ b/drivers/rtc/rtc-s5m.c
@@ -40,6 +40,7 @@
40 40
41struct s5m_rtc_info { 41struct s5m_rtc_info {
42 struct device *dev; 42 struct device *dev;
43 struct i2c_client *i2c;
43 struct sec_pmic_dev *s5m87xx; 44 struct sec_pmic_dev *s5m87xx;
44 struct regmap *regmap; 45 struct regmap *regmap;
45 struct rtc_device *rtc_dev; 46 struct rtc_device *rtc_dev;
@@ -49,6 +50,20 @@ struct s5m_rtc_info {
49 bool wtsr_smpl; 50 bool wtsr_smpl;
50}; 51};
51 52
53static const struct regmap_config s5m_rtc_regmap_config = {
54 .reg_bits = 8,
55 .val_bits = 8,
56
57 .max_register = SEC_RTC_REG_MAX,
58};
59
60static const struct regmap_config s2mps14_rtc_regmap_config = {
61 .reg_bits = 8,
62 .val_bits = 8,
63
64 .max_register = S2MPS_RTC_REG_MAX,
65};
66
52static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm, 67static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm,
53 int rtc_24hr_mode) 68 int rtc_24hr_mode)
54{ 69{
@@ -554,6 +569,7 @@ static int s5m_rtc_probe(struct platform_device *pdev)
554 struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent); 569 struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent);
555 struct sec_platform_data *pdata = s5m87xx->pdata; 570 struct sec_platform_data *pdata = s5m87xx->pdata;
556 struct s5m_rtc_info *info; 571 struct s5m_rtc_info *info;
572 const struct regmap_config *regmap_cfg;
557 int ret; 573 int ret;
558 574
559 if (!pdata) { 575 if (!pdata) {
@@ -565,9 +581,37 @@ static int s5m_rtc_probe(struct platform_device *pdev)
565 if (!info) 581 if (!info)
566 return -ENOMEM; 582 return -ENOMEM;
567 583
584 switch (pdata->device_type) {
585 case S2MPS14X:
586 regmap_cfg = &s2mps14_rtc_regmap_config;
587 break;
588 case S5M8763X:
589 regmap_cfg = &s5m_rtc_regmap_config;
590 break;
591 case S5M8767X:
592 regmap_cfg = &s5m_rtc_regmap_config;
593 break;
594 default:
595 dev_err(&pdev->dev, "Device type is not supported by RTC driver\n");
596 return -ENODEV;
597 }
598
599 info->i2c = i2c_new_dummy(s5m87xx->i2c->adapter, RTC_I2C_ADDR);
600 if (!info->i2c) {
601 dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n");
602 return -ENODEV;
603 }
604
605 info->regmap = devm_regmap_init_i2c(info->i2c, regmap_cfg);
606 if (IS_ERR(info->regmap)) {
607 ret = PTR_ERR(info->regmap);
608 dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n",
609 ret);
610 goto err;
611 }
612
568 info->dev = &pdev->dev; 613 info->dev = &pdev->dev;
569 info->s5m87xx = s5m87xx; 614 info->s5m87xx = s5m87xx;
570 info->regmap = s5m87xx->regmap_rtc;
571 info->device_type = s5m87xx->device_type; 615 info->device_type = s5m87xx->device_type;
572 info->wtsr_smpl = s5m87xx->wtsr_smpl; 616 info->wtsr_smpl = s5m87xx->wtsr_smpl;
573 617
@@ -585,7 +629,7 @@ static int s5m_rtc_probe(struct platform_device *pdev)
585 default: 629 default:
586 ret = -EINVAL; 630 ret = -EINVAL;
587 dev_err(&pdev->dev, "Unsupported device type: %d\n", ret); 631 dev_err(&pdev->dev, "Unsupported device type: %d\n", ret);
588 return ret; 632 goto err;
589 } 633 }
590 634
591 platform_set_drvdata(pdev, info); 635 platform_set_drvdata(pdev, info);
@@ -602,15 +646,24 @@ static int s5m_rtc_probe(struct platform_device *pdev)
602 info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s5m-rtc", 646 info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s5m-rtc",
603 &s5m_rtc_ops, THIS_MODULE); 647 &s5m_rtc_ops, THIS_MODULE);
604 648
605 if (IS_ERR(info->rtc_dev)) 649 if (IS_ERR(info->rtc_dev)) {
606 return PTR_ERR(info->rtc_dev); 650 ret = PTR_ERR(info->rtc_dev);
651 goto err;
652 }
607 653
608 ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL, 654 ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL,
609 s5m_rtc_alarm_irq, 0, "rtc-alarm0", 655 s5m_rtc_alarm_irq, 0, "rtc-alarm0",
610 info); 656 info);
611 if (ret < 0) 657 if (ret < 0) {
612 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", 658 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
613 info->irq, ret); 659 info->irq, ret);
660 goto err;
661 }
662
663 return 0;
664
665err:
666 i2c_unregister_device(info->i2c);
614 667
615 return ret; 668 return ret;
616} 669}
@@ -639,6 +692,17 @@ static void s5m_rtc_shutdown(struct platform_device *pdev)
639 s5m_rtc_enable_smpl(info, false); 692 s5m_rtc_enable_smpl(info, false);
640} 693}
641 694
695static int s5m_rtc_remove(struct platform_device *pdev)
696{
697 struct s5m_rtc_info *info = platform_get_drvdata(pdev);
698
699 /* Perform also all shutdown steps when removing */
700 s5m_rtc_shutdown(pdev);
701 i2c_unregister_device(info->i2c);
702
703 return 0;
704}
705
642#ifdef CONFIG_PM_SLEEP 706#ifdef CONFIG_PM_SLEEP
643static int s5m_rtc_resume(struct device *dev) 707static int s5m_rtc_resume(struct device *dev)
644{ 708{
@@ -676,6 +740,7 @@ static struct platform_driver s5m_rtc_driver = {
676 .pm = &s5m_rtc_pm_ops, 740 .pm = &s5m_rtc_pm_ops,
677 }, 741 },
678 .probe = s5m_rtc_probe, 742 .probe = s5m_rtc_probe,
743 .remove = s5m_rtc_remove,
679 .shutdown = s5m_rtc_shutdown, 744 .shutdown = s5m_rtc_shutdown,
680 .id_table = s5m_rtc_id, 745 .id_table = s5m_rtc_id,
681}; 746};
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 3301b2031c8d..552cc1d61cc7 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -330,7 +330,6 @@ int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
330int abx500_get_chip_id(struct device *dev); 330int abx500_get_chip_id(struct device *dev);
331int abx500_event_registers_startup_state_get(struct device *dev, u8 *event); 331int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
332int abx500_startup_irq_enabled(struct device *dev, unsigned int irq); 332int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
333void abx500_dump_all_banks(void);
334 333
335struct abx500_ops { 334struct abx500_ops {
336 int (*get_chip_id) (struct device *); 335 int (*get_chip_id) (struct device *);
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 7b35c21170d5..7204d8138b24 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -42,12 +42,14 @@
42#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62 42#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62
43#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63 43#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63
44#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64 44#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64
45#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68 45#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x66
46#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69 46#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x67
47#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A 47#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x68
48#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B 48#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x69
49#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C 49#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6A
50#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D 50#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6B
51#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_7 0x6C
52#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_8 0x6D
51#define ARIZONA_COMFORT_NOISE_GENERATOR 0x70 53#define ARIZONA_COMFORT_NOISE_GENERATOR 0x70
52#define ARIZONA_HAPTICS_CONTROL_1 0x90 54#define ARIZONA_HAPTICS_CONTROL_1 0x90
53#define ARIZONA_HAPTICS_CONTROL_2 0x91 55#define ARIZONA_HAPTICS_CONTROL_2 0x91
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
new file mode 100644
index 000000000000..d0e31a2287ac
--- /dev/null
+++ b/include/linux/mfd/axp20x.h
@@ -0,0 +1,180 @@
1/*
2 * Functions and registers to access AXP20X power management chip.
3 *
4 * Copyright (C) 2013, Carlo Caione <carlo@caione.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_MFD_AXP20X_H
12#define __LINUX_MFD_AXP20X_H
13
14enum {
15 AXP202_ID = 0,
16 AXP209_ID,
17};
18
19#define AXP20X_DATACACHE(m) (0x04 + (m))
20
21/* Power supply */
22#define AXP20X_PWR_INPUT_STATUS 0x00
23#define AXP20X_PWR_OP_MODE 0x01
24#define AXP20X_USB_OTG_STATUS 0x02
25#define AXP20X_PWR_OUT_CTRL 0x12
26#define AXP20X_DCDC2_V_OUT 0x23
27#define AXP20X_DCDC2_LDO3_V_SCAL 0x25
28#define AXP20X_DCDC3_V_OUT 0x27
29#define AXP20X_LDO24_V_OUT 0x28
30#define AXP20X_LDO3_V_OUT 0x29
31#define AXP20X_VBUS_IPSOUT_MGMT 0x30
32#define AXP20X_V_OFF 0x31
33#define AXP20X_OFF_CTRL 0x32
34#define AXP20X_CHRG_CTRL1 0x33
35#define AXP20X_CHRG_CTRL2 0x34
36#define AXP20X_CHRG_BAK_CTRL 0x35
37#define AXP20X_PEK_KEY 0x36
38#define AXP20X_DCDC_FREQ 0x37
39#define AXP20X_V_LTF_CHRG 0x38
40#define AXP20X_V_HTF_CHRG 0x39
41#define AXP20X_APS_WARN_L1 0x3a
42#define AXP20X_APS_WARN_L2 0x3b
43#define AXP20X_V_LTF_DISCHRG 0x3c
44#define AXP20X_V_HTF_DISCHRG 0x3d
45
46/* Interrupt */
47#define AXP20X_IRQ1_EN 0x40
48#define AXP20X_IRQ2_EN 0x41
49#define AXP20X_IRQ3_EN 0x42
50#define AXP20X_IRQ4_EN 0x43
51#define AXP20X_IRQ5_EN 0x44
52#define AXP20X_IRQ1_STATE 0x48
53#define AXP20X_IRQ2_STATE 0x49
54#define AXP20X_IRQ3_STATE 0x4a
55#define AXP20X_IRQ4_STATE 0x4b
56#define AXP20X_IRQ5_STATE 0x4c
57
58/* ADC */
59#define AXP20X_ACIN_V_ADC_H 0x56
60#define AXP20X_ACIN_V_ADC_L 0x57
61#define AXP20X_ACIN_I_ADC_H 0x58
62#define AXP20X_ACIN_I_ADC_L 0x59
63#define AXP20X_VBUS_V_ADC_H 0x5a
64#define AXP20X_VBUS_V_ADC_L 0x5b
65#define AXP20X_VBUS_I_ADC_H 0x5c
66#define AXP20X_VBUS_I_ADC_L 0x5d
67#define AXP20X_TEMP_ADC_H 0x5e
68#define AXP20X_TEMP_ADC_L 0x5f
69#define AXP20X_TS_IN_H 0x62
70#define AXP20X_TS_IN_L 0x63
71#define AXP20X_GPIO0_V_ADC_H 0x64
72#define AXP20X_GPIO0_V_ADC_L 0x65
73#define AXP20X_GPIO1_V_ADC_H 0x66
74#define AXP20X_GPIO1_V_ADC_L 0x67
75#define AXP20X_PWR_BATT_H 0x70
76#define AXP20X_PWR_BATT_M 0x71
77#define AXP20X_PWR_BATT_L 0x72
78#define AXP20X_BATT_V_H 0x78
79#define AXP20X_BATT_V_L 0x79
80#define AXP20X_BATT_CHRG_I_H 0x7a
81#define AXP20X_BATT_CHRG_I_L 0x7b
82#define AXP20X_BATT_DISCHRG_I_H 0x7c
83#define AXP20X_BATT_DISCHRG_I_L 0x7d
84#define AXP20X_IPSOUT_V_HIGH_H 0x7e
85#define AXP20X_IPSOUT_V_HIGH_L 0x7f
86
87/* Power supply */
88#define AXP20X_DCDC_MODE 0x80
89#define AXP20X_ADC_EN1 0x82
90#define AXP20X_ADC_EN2 0x83
91#define AXP20X_ADC_RATE 0x84
92#define AXP20X_GPIO10_IN_RANGE 0x85
93#define AXP20X_GPIO1_ADC_IRQ_RIS 0x86
94#define AXP20X_GPIO1_ADC_IRQ_FAL 0x87
95#define AXP20X_TIMER_CTRL 0x8a
96#define AXP20X_VBUS_MON 0x8b
97#define AXP20X_OVER_TMP 0x8f
98
99/* GPIO */
100#define AXP20X_GPIO0_CTRL 0x90
101#define AXP20X_LDO5_V_OUT 0x91
102#define AXP20X_GPIO1_CTRL 0x92
103#define AXP20X_GPIO2_CTRL 0x93
104#define AXP20X_GPIO20_SS 0x94
105#define AXP20X_GPIO3_CTRL 0x95
106
107/* Battery */
108#define AXP20X_CHRG_CC_31_24 0xb0
109#define AXP20X_CHRG_CC_23_16 0xb1
110#define AXP20X_CHRG_CC_15_8 0xb2
111#define AXP20X_CHRG_CC_7_0 0xb3
112#define AXP20X_DISCHRG_CC_31_24 0xb4
113#define AXP20X_DISCHRG_CC_23_16 0xb5
114#define AXP20X_DISCHRG_CC_15_8 0xb6
115#define AXP20X_DISCHRG_CC_7_0 0xb7
116#define AXP20X_CC_CTRL 0xb8
117#define AXP20X_FG_RES 0xb9
118
119/* Regulators IDs */
120enum {
121 AXP20X_LDO1 = 0,
122 AXP20X_LDO2,
123 AXP20X_LDO3,
124 AXP20X_LDO4,
125 AXP20X_LDO5,
126 AXP20X_DCDC2,
127 AXP20X_DCDC3,
128 AXP20X_REG_ID_MAX,
129};
130
131/* IRQs */
132enum {
133 AXP20X_IRQ_ACIN_OVER_V = 1,
134 AXP20X_IRQ_ACIN_PLUGIN,
135 AXP20X_IRQ_ACIN_REMOVAL,
136 AXP20X_IRQ_VBUS_OVER_V,
137 AXP20X_IRQ_VBUS_PLUGIN,
138 AXP20X_IRQ_VBUS_REMOVAL,
139 AXP20X_IRQ_VBUS_V_LOW,
140 AXP20X_IRQ_BATT_PLUGIN,
141 AXP20X_IRQ_BATT_REMOVAL,
142 AXP20X_IRQ_BATT_ENT_ACT_MODE,
143 AXP20X_IRQ_BATT_EXIT_ACT_MODE,
144 AXP20X_IRQ_CHARG,
145 AXP20X_IRQ_CHARG_DONE,
146 AXP20X_IRQ_BATT_TEMP_HIGH,
147 AXP20X_IRQ_BATT_TEMP_LOW,
148 AXP20X_IRQ_DIE_TEMP_HIGH,
149 AXP20X_IRQ_CHARG_I_LOW,
150 AXP20X_IRQ_DCDC1_V_LONG,
151 AXP20X_IRQ_DCDC2_V_LONG,
152 AXP20X_IRQ_DCDC3_V_LONG,
153 AXP20X_IRQ_PEK_SHORT = 22,
154 AXP20X_IRQ_PEK_LONG,
155 AXP20X_IRQ_N_OE_PWR_ON,
156 AXP20X_IRQ_N_OE_PWR_OFF,
157 AXP20X_IRQ_VBUS_VALID,
158 AXP20X_IRQ_VBUS_NOT_VALID,
159 AXP20X_IRQ_VBUS_SESS_VALID,
160 AXP20X_IRQ_VBUS_SESS_END,
161 AXP20X_IRQ_LOW_PWR_LVL1,
162 AXP20X_IRQ_LOW_PWR_LVL2,
163 AXP20X_IRQ_TIMER,
164 AXP20X_IRQ_PEK_RIS_EDGE,
165 AXP20X_IRQ_PEK_FAL_EDGE,
166 AXP20X_IRQ_GPIO3_INPUT,
167 AXP20X_IRQ_GPIO2_INPUT,
168 AXP20X_IRQ_GPIO1_INPUT,
169 AXP20X_IRQ_GPIO0_INPUT,
170};
171
172struct axp20x_dev {
173 struct device *dev;
174 struct i2c_client *i2c_client;
175 struct regmap *regmap;
176 struct regmap_irq_chip_data *regmap_irqc;
177 long variant;
178};
179
180#endif /* __LINUX_MFD_AXP20X_H */
diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h
index 032af7fc5b2e..887ef4f7bef7 100644
--- a/include/linux/mfd/cros_ec.h
+++ b/include/linux/mfd/cros_ec.h
@@ -29,8 +29,8 @@ enum {
29 EC_MSG_RX_PROTO_BYTES = 3, 29 EC_MSG_RX_PROTO_BYTES = 3,
30 30
31 /* Max length of messages */ 31 /* Max length of messages */
32 EC_MSG_BYTES = EC_HOST_PARAM_SIZE + EC_MSG_TX_PROTO_BYTES, 32 EC_MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE +
33 33 EC_MSG_TX_PROTO_BYTES,
34}; 34};
35 35
36/** 36/**
diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h
index 86fd06953bcd..7853a6410d14 100644
--- a/include/linux/mfd/cros_ec_commands.h
+++ b/include/linux/mfd/cros_ec_commands.h
@@ -24,25 +24,12 @@
24#define __CROS_EC_COMMANDS_H 24#define __CROS_EC_COMMANDS_H
25 25
26/* 26/*
27 * Protocol overview 27 * Current version of this protocol
28 * 28 *
29 * request: CMD [ P0 P1 P2 ... Pn S ] 29 * TODO(crosbug.com/p/11223): This is effectively useless; protocol is
30 * response: ERR [ P0 P1 P2 ... Pn S ] 30 * determined in other ways. Remove this once the kernel code no longer
31 * 31 * depends on it.
32 * where the bytes are defined as follow :
33 * - CMD is the command code. (defined by EC_CMD_ constants)
34 * - ERR is the error code. (defined by EC_RES_ constants)
35 * - Px is the optional payload.
36 * it is not sent if the error code is not success.
37 * (defined by ec_params_ and ec_response_ structures)
38 * - S is the checksum which is the sum of all payload bytes.
39 *
40 * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD
41 * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM.
42 * On I2C, all bytes are sent serially in the same message.
43 */ 32 */
44
45/* Current version of this protocol */
46#define EC_PROTO_VERSION 0x00000002 33#define EC_PROTO_VERSION 0x00000002
47 34
48/* Command version mask */ 35/* Command version mask */
@@ -57,13 +44,19 @@
57#define EC_LPC_ADDR_HOST_CMD 0x204 44#define EC_LPC_ADDR_HOST_CMD 0x204
58 45
59/* I/O addresses for host command args and params */ 46/* I/O addresses for host command args and params */
60#define EC_LPC_ADDR_HOST_ARGS 0x800 47/* Protocol version 2 */
61#define EC_LPC_ADDR_HOST_PARAM 0x804 48#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */
62#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */ 49#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is
63 50 * EC_PROTO2_MAX_PARAM_SIZE */
64/* I/O addresses for host command params, old interface */ 51/* Protocol version 3 */
65#define EC_LPC_ADDR_OLD_PARAM 0x880 52#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
66#define EC_OLD_PARAM_SIZE 0x080 /* Size of param area in bytes */ 53#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
54
55/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
56 * and they tell the kernel that so we have to think of it as two parts. */
57#define EC_HOST_CMD_REGION0 0x800
58#define EC_HOST_CMD_REGION1 0x880
59#define EC_HOST_CMD_REGION_SIZE 0x80
67 60
68/* EC command register bit functions */ 61/* EC command register bit functions */
69#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ 62#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */
@@ -79,18 +72,22 @@
79#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ 72#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
80 73
81/* The offset address of each type of data in mapped memory. */ 74/* The offset address of each type of data in mapped memory. */
82#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors */ 75#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
83#define EC_MEMMAP_FAN 0x10 /* Fan speeds */ 76#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
84#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* Temp sensors (second set) */ 77#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */
85#define EC_MEMMAP_ID 0x20 /* 'E' 'C' */ 78#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */
86#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ 79#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
87#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ 80#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
88#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ 81#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
89#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ 82#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
90#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ 83#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */
91#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host command interface flags */ 84#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */
92#define EC_MEMMAP_SWITCHES 0x30 85/* Unused 0x28 - 0x2f */
93#define EC_MEMMAP_HOST_EVENTS 0x34 86#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */
87/* Unused 0x31 - 0x33 */
88#define EC_MEMMAP_HOST_EVENTS 0x34 /* 32 bits */
89/* Reserve 0x38 - 0x3f for additional host event-related stuff */
90/* Battery values are all 32 bits */
94#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ 91#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */
95#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ 92#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */
96#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ 93#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */
@@ -99,10 +96,24 @@
99#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ 96#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */
100#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ 97#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */
101#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ 98#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */
99/* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */
102#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ 100#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */
103#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ 101#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */
104#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ 102#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */
105#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ 103#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
104#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */
105/* Unused 0x84 - 0x8f */
106#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/
107/* Unused 0x91 */
108#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometer data 0x92 - 0x9f */
109#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */
110/* Unused 0xa6 - 0xfe (remember, 0xff is NOT part of the memmap region) */
111
112
113/* Define the format of the accelerometer mapped memory status byte. */
114#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
115#define EC_MEMMAP_ACC_STATUS_BUSY_BIT (1 << 4)
116#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT (1 << 7)
106 117
107/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ 118/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
108#define EC_TEMP_SENSOR_ENTRIES 16 119#define EC_TEMP_SENSOR_ENTRIES 16
@@ -112,6 +123,8 @@
112 * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. 123 * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
113 */ 124 */
114#define EC_TEMP_SENSOR_B_ENTRIES 8 125#define EC_TEMP_SENSOR_B_ENTRIES 8
126
127/* Special values for mapped temperature sensors */
115#define EC_TEMP_SENSOR_NOT_PRESENT 0xff 128#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
116#define EC_TEMP_SENSOR_ERROR 0xfe 129#define EC_TEMP_SENSOR_ERROR 0xfe
117#define EC_TEMP_SENSOR_NOT_POWERED 0xfd 130#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
@@ -122,6 +135,18 @@
122 */ 135 */
123#define EC_TEMP_SENSOR_OFFSET 200 136#define EC_TEMP_SENSOR_OFFSET 200
124 137
138/*
139 * Number of ALS readings at EC_MEMMAP_ALS
140 */
141#define EC_ALS_ENTRIES 2
142
143/*
144 * The default value a temperature sensor will return when it is present but
145 * has not been read this boot. This is a reasonable number to avoid
146 * triggering alarms on the host.
147 */
148#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
149
125#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ 150#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */
126#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ 151#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */
127#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ 152#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */
@@ -137,8 +162,8 @@
137#define EC_SWITCH_LID_OPEN 0x01 162#define EC_SWITCH_LID_OPEN 0x01
138#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 163#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
139#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 164#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
140/* Recovery requested via keyboard */ 165/* Was recovery requested via keyboard; now unused. */
141#define EC_SWITCH_KEYBOARD_RECOVERY 0x08 166#define EC_SWITCH_IGNORE1 0x08
142/* Recovery requested via dedicated signal (from servo board) */ 167/* Recovery requested via dedicated signal (from servo board) */
143#define EC_SWITCH_DEDICATED_RECOVERY 0x10 168#define EC_SWITCH_DEDICATED_RECOVERY 0x10
144/* Was fake developer mode switch; now unused. Remove in next refactor. */ 169/* Was fake developer mode switch; now unused. Remove in next refactor. */
@@ -147,10 +172,15 @@
147/* Host command interface flags */ 172/* Host command interface flags */
148/* Host command interface supports LPC args (LPC interface only) */ 173/* Host command interface supports LPC args (LPC interface only) */
149#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 174#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
175/* Host command interface supports version 3 protocol */
176#define EC_HOST_CMD_FLAG_VERSION_3 0x02
150 177
151/* Wireless switch flags */ 178/* Wireless switch flags */
152#define EC_WIRELESS_SWITCH_WLAN 0x01 179#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */
153#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 180#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */
181#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */
182#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */
183#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */
154 184
155/* 185/*
156 * This header file is used in coreboot both in C and ACPI code. The ACPI code 186 * This header file is used in coreboot both in C and ACPI code. The ACPI code
@@ -159,6 +189,14 @@
159 */ 189 */
160#ifndef __ACPI__ 190#ifndef __ACPI__
161 191
192/*
193 * Define __packed if someone hasn't beat us to it. Linux kernel style
194 * checking prefers __packed over __attribute__((packed)).
195 */
196#ifndef __packed
197#define __packed __attribute__((packed))
198#endif
199
162/* LPC command status byte masks */ 200/* LPC command status byte masks */
163/* EC has written a byte in the data register and host hasn't read it yet */ 201/* EC has written a byte in the data register and host hasn't read it yet */
164#define EC_LPC_STATUS_TO_HOST 0x01 202#define EC_LPC_STATUS_TO_HOST 0x01
@@ -198,6 +236,9 @@ enum ec_status {
198 EC_RES_UNAVAILABLE = 9, /* No response available */ 236 EC_RES_UNAVAILABLE = 9, /* No response available */
199 EC_RES_TIMEOUT = 10, /* We got a timeout */ 237 EC_RES_TIMEOUT = 10, /* We got a timeout */
200 EC_RES_OVERFLOW = 11, /* Table / data overflow */ 238 EC_RES_OVERFLOW = 11, /* Table / data overflow */
239 EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */
240 EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */
241 EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */
201}; 242};
202 243
203/* 244/*
@@ -235,6 +276,16 @@ enum host_event_code {
235 /* Shutdown due to battery level too low */ 276 /* Shutdown due to battery level too low */
236 EC_HOST_EVENT_BATTERY_SHUTDOWN = 17, 277 EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
237 278
279 /* Suggest that the AP throttle itself */
280 EC_HOST_EVENT_THROTTLE_START = 18,
281 /* Suggest that the AP resume normal speed */
282 EC_HOST_EVENT_THROTTLE_STOP = 19,
283
284 /* Hang detect logic detected a hang and host event timeout expired */
285 EC_HOST_EVENT_HANG_DETECT = 20,
286 /* Hang detect logic detected a hang and warm rebooted the AP */
287 EC_HOST_EVENT_HANG_REBOOT = 21,
288
238 /* 289 /*
239 * The high bit of the event mask is not used as a host event code. If 290 * The high bit of the event mask is not used as a host event code. If
240 * it reads back as set, then the entire event mask should be 291 * it reads back as set, then the entire event mask should be
@@ -279,6 +330,188 @@ struct ec_lpc_host_args {
279 */ 330 */
280#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 331#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
281 332
333/*****************************************************************************/
334/*
335 * Byte codes returned by EC over SPI interface.
336 *
337 * These can be used by the AP to debug the EC interface, and to determine
338 * when the EC is not in a state where it will ever get around to responding
339 * to the AP.
340 *
341 * Example of sequence of bytes read from EC for a current good transfer:
342 * 1. - - AP asserts chip select (CS#)
343 * 2. EC_SPI_OLD_READY - AP sends first byte(s) of request
344 * 3. - - EC starts handling CS# interrupt
345 * 4. EC_SPI_RECEIVING - AP sends remaining byte(s) of request
346 * 5. EC_SPI_PROCESSING - EC starts processing request; AP is clocking in
347 * bytes looking for EC_SPI_FRAME_START
348 * 6. - - EC finishes processing and sets up response
349 * 7. EC_SPI_FRAME_START - AP reads frame byte
350 * 8. (response packet) - AP reads response packet
351 * 9. EC_SPI_PAST_END - Any additional bytes read by AP
352 * 10 - - AP deasserts chip select
353 * 11 - - EC processes CS# interrupt and sets up DMA for
354 * next request
355 *
356 * If the AP is waiting for EC_SPI_FRAME_START and sees any value other than
357 * the following byte values:
358 * EC_SPI_OLD_READY
359 * EC_SPI_RX_READY
360 * EC_SPI_RECEIVING
361 * EC_SPI_PROCESSING
362 *
363 * Then the EC found an error in the request, or was not ready for the request
364 * and lost data. The AP should give up waiting for EC_SPI_FRAME_START,
365 * because the EC is unable to tell when the AP is done sending its request.
366 */
367
368/*
369 * Framing byte which precedes a response packet from the EC. After sending a
370 * request, the AP will clock in bytes until it sees the framing byte, then
371 * clock in the response packet.
372 */
373#define EC_SPI_FRAME_START 0xec
374
375/*
376 * Padding bytes which are clocked out after the end of a response packet.
377 */
378#define EC_SPI_PAST_END 0xed
379
380/*
381 * EC is ready to receive, and has ignored the byte sent by the AP. EC expects
382 * that the AP will send a valid packet header (starting with
383 * EC_COMMAND_PROTOCOL_3) in the next 32 bytes.
384 */
385#define EC_SPI_RX_READY 0xf8
386
387/*
388 * EC has started receiving the request from the AP, but hasn't started
389 * processing it yet.
390 */
391#define EC_SPI_RECEIVING 0xf9
392
393/* EC has received the entire request from the AP and is processing it. */
394#define EC_SPI_PROCESSING 0xfa
395
396/*
397 * EC received bad data from the AP, such as a packet header with an invalid
398 * length. EC will ignore all data until chip select deasserts.
399 */
400#define EC_SPI_RX_BAD_DATA 0xfb
401
402/*
403 * EC received data from the AP before it was ready. That is, the AP asserted
404 * chip select and started clocking data before the EC was ready to receive it.
405 * EC will ignore all data until chip select deasserts.
406 */
407#define EC_SPI_NOT_READY 0xfc
408
409/*
410 * EC was ready to receive a request from the AP. EC has treated the byte sent
411 * by the AP as part of a request packet, or (for old-style ECs) is processing
412 * a fully received packet but is not ready to respond yet.
413 */
414#define EC_SPI_OLD_READY 0xfd
415
416/*****************************************************************************/
417
418/*
419 * Protocol version 2 for I2C and SPI send a request this way:
420 *
421 * 0 EC_CMD_VERSION0 + (command version)
422 * 1 Command number
423 * 2 Length of params = N
424 * 3..N+2 Params, if any
425 * N+3 8-bit checksum of bytes 0..N+2
426 *
427 * The corresponding response is:
428 *
429 * 0 Result code (EC_RES_*)
430 * 1 Length of params = M
431 * 2..M+1 Params, if any
432 * M+2 8-bit checksum of bytes 0..M+1
433 */
434#define EC_PROTO2_REQUEST_HEADER_BYTES 3
435#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
436#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \
437 EC_PROTO2_REQUEST_TRAILER_BYTES)
438
439#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
440#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
441#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \
442 EC_PROTO2_RESPONSE_TRAILER_BYTES)
443
444/* Parameter length was limited by the LPC interface */
445#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
446
447/* Maximum request and response packet sizes for protocol version 2 */
448#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \
449 EC_PROTO2_MAX_PARAM_SIZE)
450#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \
451 EC_PROTO2_MAX_PARAM_SIZE)
452
453/*****************************************************************************/
454
455/*
456 * Value written to legacy command port / prefix byte to indicate protocol
457 * 3+ structs are being used. Usage is bus-dependent.
458 */
459#define EC_COMMAND_PROTOCOL_3 0xda
460
461#define EC_HOST_REQUEST_VERSION 3
462
463/* Version 3 request from host */
464struct ec_host_request {
465 /* Struct version (=3)
466 *
467 * EC will return EC_RES_INVALID_HEADER if it receives a header with a
468 * version it doesn't know how to parse.
469 */
470 uint8_t struct_version;
471
472 /*
473 * Checksum of request and data; sum of all bytes including checksum
474 * should total to 0.
475 */
476 uint8_t checksum;
477
478 /* Command code */
479 uint16_t command;
480
481 /* Command version */
482 uint8_t command_version;
483
484 /* Unused byte in current protocol version; set to 0 */
485 uint8_t reserved;
486
487 /* Length of data which follows this header */
488 uint16_t data_len;
489} __packed;
490
491#define EC_HOST_RESPONSE_VERSION 3
492
493/* Version 3 response from EC */
494struct ec_host_response {
495 /* Struct version (=3) */
496 uint8_t struct_version;
497
498 /*
499 * Checksum of response and data; sum of all bytes including checksum
500 * should total to 0.
501 */
502 uint8_t checksum;
503
504 /* Result code (EC_RES_*) */
505 uint16_t result;
506
507 /* Length of data which follows this header */
508 uint16_t data_len;
509
510 /* Unused bytes in current protocol version; set to 0 */
511 uint16_t reserved;
512} __packed;
513
514/*****************************************************************************/
282/* 515/*
283 * Notes on commands: 516 * Notes on commands:
284 * 517 *
@@ -418,6 +651,68 @@ struct ec_response_get_comms_status {
418 uint32_t flags; /* Mask of enum ec_comms_status */ 651 uint32_t flags; /* Mask of enum ec_comms_status */
419} __packed; 652} __packed;
420 653
654/* Fake a variety of responses, purely for testing purposes. */
655#define EC_CMD_TEST_PROTOCOL 0x0a
656
657/* Tell the EC what to send back to us. */
658struct ec_params_test_protocol {
659 uint32_t ec_result;
660 uint32_t ret_len;
661 uint8_t buf[32];
662} __packed;
663
664/* Here it comes... */
665struct ec_response_test_protocol {
666 uint8_t buf[32];
667} __packed;
668
669/* Get prococol information */
670#define EC_CMD_GET_PROTOCOL_INFO 0x0b
671
672/* Flags for ec_response_get_protocol_info.flags */
673/* EC_RES_IN_PROGRESS may be returned if a command is slow */
674#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0)
675
676struct ec_response_get_protocol_info {
677 /* Fields which exist if at least protocol version 3 supported */
678
679 /* Bitmask of protocol versions supported (1 << n means version n)*/
680 uint32_t protocol_versions;
681
682 /* Maximum request packet size, in bytes */
683 uint16_t max_request_packet_size;
684
685 /* Maximum response packet size, in bytes */
686 uint16_t max_response_packet_size;
687
688 /* Flags; see EC_PROTOCOL_INFO_* */
689 uint32_t flags;
690} __packed;
691
692
693/*****************************************************************************/
694/* Get/Set miscellaneous values */
695
696/* The upper byte of .flags tells what to do (nothing means "get") */
697#define EC_GSV_SET 0x80000000
698
699/* The lower three bytes of .flags identifies the parameter, if that has
700 meaning for an individual command. */
701#define EC_GSV_PARAM_MASK 0x00ffffff
702
703struct ec_params_get_set_value {
704 uint32_t flags;
705 uint32_t value;
706} __packed;
707
708struct ec_response_get_set_value {
709 uint32_t flags;
710 uint32_t value;
711} __packed;
712
713/* More than one command can use these structs to get/set paramters. */
714#define EC_CMD_GSV_PAUSE_IN_S5 0x0c
715
421 716
422/*****************************************************************************/ 717/*****************************************************************************/
423/* Flash commands */ 718/* Flash commands */
@@ -425,6 +720,7 @@ struct ec_response_get_comms_status {
425/* Get flash info */ 720/* Get flash info */
426#define EC_CMD_FLASH_INFO 0x10 721#define EC_CMD_FLASH_INFO 0x10
427 722
723/* Version 0 returns these fields */
428struct ec_response_flash_info { 724struct ec_response_flash_info {
429 /* Usable flash size, in bytes */ 725 /* Usable flash size, in bytes */
430 uint32_t flash_size; 726 uint32_t flash_size;
@@ -445,6 +741,37 @@ struct ec_response_flash_info {
445 uint32_t protect_block_size; 741 uint32_t protect_block_size;
446} __packed; 742} __packed;
447 743
744/* Flags for version 1+ flash info command */
745/* EC flash erases bits to 0 instead of 1 */
746#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0)
747
748/*
749 * Version 1 returns the same initial fields as version 0, with additional
750 * fields following.
751 *
752 * gcc anonymous structs don't seem to get along with the __packed directive;
753 * if they did we'd define the version 0 struct as a sub-struct of this one.
754 */
755struct ec_response_flash_info_1 {
756 /* Version 0 fields; see above for description */
757 uint32_t flash_size;
758 uint32_t write_block_size;
759 uint32_t erase_block_size;
760 uint32_t protect_block_size;
761
762 /* Version 1 adds these fields: */
763 /*
764 * Ideal write size in bytes. Writes will be fastest if size is
765 * exactly this and offset is a multiple of this. For example, an EC
766 * may have a write buffer which can do half-page operations if data is
767 * aligned, and a slower word-at-a-time write mode.
768 */
769 uint32_t write_ideal_size;
770
771 /* Flags; see EC_FLASH_INFO_* */
772 uint32_t flags;
773} __packed;
774
448/* 775/*
449 * Read flash 776 * Read flash
450 * 777 *
@@ -459,15 +786,15 @@ struct ec_params_flash_read {
459 786
460/* Write flash */ 787/* Write flash */
461#define EC_CMD_FLASH_WRITE 0x12 788#define EC_CMD_FLASH_WRITE 0x12
789#define EC_VER_FLASH_WRITE 1
790
791/* Version 0 of the flash command supported only 64 bytes of data */
792#define EC_FLASH_WRITE_VER0_SIZE 64
462 793
463struct ec_params_flash_write { 794struct ec_params_flash_write {
464 uint32_t offset; /* Byte offset to write */ 795 uint32_t offset; /* Byte offset to write */
465 uint32_t size; /* Size to write in bytes */ 796 uint32_t size; /* Size to write in bytes */
466 /* 797 /* Followed by data to write */
467 * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to
468 * use a power of 2 so writes stay aligned.
469 */
470 uint8_t data[64];
471} __packed; 798} __packed;
472 799
473/* Erase flash */ 800/* Erase flash */
@@ -543,7 +870,7 @@ struct ec_response_flash_protect {
543 870
544enum ec_flash_region { 871enum ec_flash_region {
545 /* Region which holds read-only EC image */ 872 /* Region which holds read-only EC image */
546 EC_FLASH_REGION_RO, 873 EC_FLASH_REGION_RO = 0,
547 /* Region which holds rewritable EC image */ 874 /* Region which holds rewritable EC image */
548 EC_FLASH_REGION_RW, 875 EC_FLASH_REGION_RW,
549 /* 876 /*
@@ -551,6 +878,8 @@ enum ec_flash_region {
551 * EC_FLASH_REGION_RO) 878 * EC_FLASH_REGION_RO)
552 */ 879 */
553 EC_FLASH_REGION_WP_RO, 880 EC_FLASH_REGION_WP_RO,
881 /* Number of regions */
882 EC_FLASH_REGION_COUNT,
554}; 883};
555 884
556struct ec_params_flash_region_info { 885struct ec_params_flash_region_info {
@@ -639,15 +968,15 @@ struct rgb_s {
639 */ 968 */
640struct lightbar_params { 969struct lightbar_params {
641 /* Timing */ 970 /* Timing */
642 int google_ramp_up; 971 int32_t google_ramp_up;
643 int google_ramp_down; 972 int32_t google_ramp_down;
644 int s3s0_ramp_up; 973 int32_t s3s0_ramp_up;
645 int s0_tick_delay[2]; /* AC=0/1 */ 974 int32_t s0_tick_delay[2]; /* AC=0/1 */
646 int s0a_tick_delay[2]; /* AC=0/1 */ 975 int32_t s0a_tick_delay[2]; /* AC=0/1 */
647 int s0s3_ramp_down; 976 int32_t s0s3_ramp_down;
648 int s3_sleep_for; 977 int32_t s3_sleep_for;
649 int s3_ramp_up; 978 int32_t s3_ramp_up;
650 int s3_ramp_down; 979 int32_t s3_ramp_down;
651 980
652 /* Oscillation */ 981 /* Oscillation */
653 uint8_t new_s0; 982 uint8_t new_s0;
@@ -676,7 +1005,7 @@ struct ec_params_lightbar {
676 union { 1005 union {
677 struct { 1006 struct {
678 /* no args */ 1007 /* no args */
679 } dump, off, on, init, get_seq, get_params; 1008 } dump, off, on, init, get_seq, get_params, version;
680 1009
681 struct num { 1010 struct num {
682 uint8_t num; 1011 uint8_t num;
@@ -710,6 +1039,11 @@ struct ec_response_lightbar {
710 1039
711 struct lightbar_params get_params; 1040 struct lightbar_params get_params;
712 1041
1042 struct version {
1043 uint32_t num;
1044 uint32_t flags;
1045 } version;
1046
713 struct { 1047 struct {
714 /* no return params */ 1048 /* no return params */
715 } off, on, init, brightness, seq, reg, rgb, demo, set_params; 1049 } off, on, init, brightness, seq, reg, rgb, demo, set_params;
@@ -730,10 +1064,62 @@ enum lightbar_command {
730 LIGHTBAR_CMD_DEMO = 9, 1064 LIGHTBAR_CMD_DEMO = 9,
731 LIGHTBAR_CMD_GET_PARAMS = 10, 1065 LIGHTBAR_CMD_GET_PARAMS = 10,
732 LIGHTBAR_CMD_SET_PARAMS = 11, 1066 LIGHTBAR_CMD_SET_PARAMS = 11,
1067 LIGHTBAR_CMD_VERSION = 12,
733 LIGHTBAR_NUM_CMDS 1068 LIGHTBAR_NUM_CMDS
734}; 1069};
735 1070
736/*****************************************************************************/ 1071/*****************************************************************************/
1072/* LED control commands */
1073
1074#define EC_CMD_LED_CONTROL 0x29
1075
1076enum ec_led_id {
1077 /* LED to indicate battery state of charge */
1078 EC_LED_ID_BATTERY_LED = 0,
1079 /*
1080 * LED to indicate system power state (on or in suspend).
1081 * May be on power button or on C-panel.
1082 */
1083 EC_LED_ID_POWER_LED,
1084 /* LED on power adapter or its plug */
1085 EC_LED_ID_ADAPTER_LED,
1086
1087 EC_LED_ID_COUNT
1088};
1089
1090/* LED control flags */
1091#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
1092#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */
1093
1094enum ec_led_colors {
1095 EC_LED_COLOR_RED = 0,
1096 EC_LED_COLOR_GREEN,
1097 EC_LED_COLOR_BLUE,
1098 EC_LED_COLOR_YELLOW,
1099 EC_LED_COLOR_WHITE,
1100
1101 EC_LED_COLOR_COUNT
1102};
1103
1104struct ec_params_led_control {
1105 uint8_t led_id; /* Which LED to control */
1106 uint8_t flags; /* Control flags */
1107
1108 uint8_t brightness[EC_LED_COLOR_COUNT];
1109} __packed;
1110
1111struct ec_response_led_control {
1112 /*
1113 * Available brightness value range.
1114 *
1115 * Range 0 means color channel not present.
1116 * Range 1 means on/off control.
1117 * Other values means the LED is control by PWM.
1118 */
1119 uint8_t brightness_range[EC_LED_COLOR_COUNT];
1120} __packed;
1121
1122/*****************************************************************************/
737/* Verified boot commands */ 1123/* Verified boot commands */
738 1124
739/* 1125/*
@@ -790,6 +1176,181 @@ enum ec_vboot_hash_status {
790#define EC_VBOOT_HASH_OFFSET_RW 0xfffffffd 1176#define EC_VBOOT_HASH_OFFSET_RW 0xfffffffd
791 1177
792/*****************************************************************************/ 1178/*****************************************************************************/
1179/*
1180 * Motion sense commands. We'll make separate structs for sub-commands with
1181 * different input args, so that we know how much to expect.
1182 */
1183#define EC_CMD_MOTION_SENSE_CMD 0x2B
1184
1185/* Motion sense commands */
1186enum motionsense_command {
1187 /*
1188 * Dump command returns all motion sensor data including motion sense
1189 * module flags and individual sensor flags.
1190 */
1191 MOTIONSENSE_CMD_DUMP = 0,
1192
1193 /*
1194 * Info command returns data describing the details of a given sensor,
1195 * including enum motionsensor_type, enum motionsensor_location, and
1196 * enum motionsensor_chip.
1197 */
1198 MOTIONSENSE_CMD_INFO = 1,
1199
1200 /*
1201 * EC Rate command is a setter/getter command for the EC sampling rate
1202 * of all motion sensors in milliseconds.
1203 */
1204 MOTIONSENSE_CMD_EC_RATE = 2,
1205
1206 /*
1207 * Sensor ODR command is a setter/getter command for the output data
1208 * rate of a specific motion sensor in millihertz.
1209 */
1210 MOTIONSENSE_CMD_SENSOR_ODR = 3,
1211
1212 /*
1213 * Sensor range command is a setter/getter command for the range of
1214 * a specified motion sensor in +/-G's or +/- deg/s.
1215 */
1216 MOTIONSENSE_CMD_SENSOR_RANGE = 4,
1217
1218 /*
1219 * Setter/getter command for the keyboard wake angle. When the lid
1220 * angle is greater than this value, keyboard wake is disabled in S3,
1221 * and when the lid angle goes less than this value, keyboard wake is
1222 * enabled. Note, the lid angle measurement is an approximate,
1223 * un-calibrated value, hence the wake angle isn't exact.
1224 */
1225 MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5,
1226
1227 /* Number of motionsense sub-commands. */
1228 MOTIONSENSE_NUM_CMDS
1229};
1230
1231enum motionsensor_id {
1232 EC_MOTION_SENSOR_ACCEL_BASE = 0,
1233 EC_MOTION_SENSOR_ACCEL_LID = 1,
1234 EC_MOTION_SENSOR_GYRO = 2,
1235
1236 /*
1237 * Note, if more sensors are added and this count changes, the padding
1238 * in ec_response_motion_sense dump command must be modified.
1239 */
1240 EC_MOTION_SENSOR_COUNT = 3
1241};
1242
1243/* List of motion sensor types. */
1244enum motionsensor_type {
1245 MOTIONSENSE_TYPE_ACCEL = 0,
1246 MOTIONSENSE_TYPE_GYRO = 1,
1247};
1248
1249/* List of motion sensor locations. */
1250enum motionsensor_location {
1251 MOTIONSENSE_LOC_BASE = 0,
1252 MOTIONSENSE_LOC_LID = 1,
1253};
1254
1255/* List of motion sensor chips. */
1256enum motionsensor_chip {
1257 MOTIONSENSE_CHIP_KXCJ9 = 0,
1258};
1259
1260/* Module flag masks used for the dump sub-command. */
1261#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0)
1262
1263/* Sensor flag masks used for the dump sub-command. */
1264#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0)
1265
1266/*
1267 * Send this value for the data element to only perform a read. If you
1268 * send any other value, the EC will interpret it as data to set and will
1269 * return the actual value set.
1270 */
1271#define EC_MOTION_SENSE_NO_VALUE -1
1272
1273struct ec_params_motion_sense {
1274 uint8_t cmd;
1275 union {
1276 /* Used for MOTIONSENSE_CMD_DUMP. */
1277 struct {
1278 /* no args */
1279 } dump;
1280
1281 /*
1282 * Used for MOTIONSENSE_CMD_EC_RATE and
1283 * MOTIONSENSE_CMD_KB_WAKE_ANGLE.
1284 */
1285 struct {
1286 /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */
1287 int16_t data;
1288 } ec_rate, kb_wake_angle;
1289
1290 /* Used for MOTIONSENSE_CMD_INFO. */
1291 struct {
1292 /* Should be element of enum motionsensor_id. */
1293 uint8_t sensor_num;
1294 } info;
1295
1296 /*
1297 * Used for MOTIONSENSE_CMD_SENSOR_ODR and
1298 * MOTIONSENSE_CMD_SENSOR_RANGE.
1299 */
1300 struct {
1301 /* Should be element of enum motionsensor_id. */
1302 uint8_t sensor_num;
1303
1304 /* Rounding flag, true for round-up, false for down. */
1305 uint8_t roundup;
1306
1307 uint16_t reserved;
1308
1309 /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */
1310 int32_t data;
1311 } sensor_odr, sensor_range;
1312 };
1313} __packed;
1314
1315struct ec_response_motion_sense {
1316 union {
1317 /* Used for MOTIONSENSE_CMD_DUMP. */
1318 struct {
1319 /* Flags representing the motion sensor module. */
1320 uint8_t module_flags;
1321
1322 /* Flags for each sensor in enum motionsensor_id. */
1323 uint8_t sensor_flags[EC_MOTION_SENSOR_COUNT];
1324
1325 /* Array of all sensor data. Each sensor is 3-axis. */
1326 int16_t data[3*EC_MOTION_SENSOR_COUNT];
1327 } dump;
1328
1329 /* Used for MOTIONSENSE_CMD_INFO. */
1330 struct {
1331 /* Should be element of enum motionsensor_type. */
1332 uint8_t type;
1333
1334 /* Should be element of enum motionsensor_location. */
1335 uint8_t location;
1336
1337 /* Should be element of enum motionsensor_chip. */
1338 uint8_t chip;
1339 } info;
1340
1341 /*
1342 * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR,
1343 * MOTIONSENSE_CMD_SENSOR_RANGE, and
1344 * MOTIONSENSE_CMD_KB_WAKE_ANGLE.
1345 */
1346 struct {
1347 /* Current value of the parameter queried. */
1348 int32_t ret;
1349 } ec_rate, sensor_odr, sensor_range, kb_wake_angle;
1350 };
1351} __packed;
1352
1353/*****************************************************************************/
793/* USB charging control commands */ 1354/* USB charging control commands */
794 1355
795/* Set USB port charging mode */ 1356/* Set USB port charging mode */
@@ -868,20 +1429,27 @@ struct ec_response_port80_last_boot {
868} __packed; 1429} __packed;
869 1430
870/*****************************************************************************/ 1431/*****************************************************************************/
871/* Thermal engine commands */ 1432/* Thermal engine commands. Note that there are two implementations. We'll
1433 * reuse the command number, but the data and behavior is incompatible.
1434 * Version 0 is what originally shipped on Link.
1435 * Version 1 separates the CPU thermal limits from the fan control.
1436 */
872 1437
873/* Set thershold value */
874#define EC_CMD_THERMAL_SET_THRESHOLD 0x50 1438#define EC_CMD_THERMAL_SET_THRESHOLD 0x50
1439#define EC_CMD_THERMAL_GET_THRESHOLD 0x51
1440
1441/* The version 0 structs are opaque. You have to know what they are for
1442 * the get/set commands to make any sense.
1443 */
875 1444
1445/* Version 0 - set */
876struct ec_params_thermal_set_threshold { 1446struct ec_params_thermal_set_threshold {
877 uint8_t sensor_type; 1447 uint8_t sensor_type;
878 uint8_t threshold_id; 1448 uint8_t threshold_id;
879 uint16_t value; 1449 uint16_t value;
880} __packed; 1450} __packed;
881 1451
882/* Get threshold value */ 1452/* Version 0 - get */
883#define EC_CMD_THERMAL_GET_THRESHOLD 0x51
884
885struct ec_params_thermal_get_threshold { 1453struct ec_params_thermal_get_threshold {
886 uint8_t sensor_type; 1454 uint8_t sensor_type;
887 uint8_t threshold_id; 1455 uint8_t threshold_id;
@@ -891,6 +1459,41 @@ struct ec_response_thermal_get_threshold {
891 uint16_t value; 1459 uint16_t value;
892} __packed; 1460} __packed;
893 1461
1462
1463/* The version 1 structs are visible. */
1464enum ec_temp_thresholds {
1465 EC_TEMP_THRESH_WARN = 0,
1466 EC_TEMP_THRESH_HIGH,
1467 EC_TEMP_THRESH_HALT,
1468
1469 EC_TEMP_THRESH_COUNT
1470};
1471
1472/* Thermal configuration for one temperature sensor. Temps are in degrees K.
1473 * Zero values will be silently ignored by the thermal task.
1474 */
1475struct ec_thermal_config {
1476 uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */
1477 uint32_t temp_fan_off; /* no active cooling needed */
1478 uint32_t temp_fan_max; /* max active cooling needed */
1479} __packed;
1480
1481/* Version 1 - get config for one sensor. */
1482struct ec_params_thermal_get_threshold_v1 {
1483 uint32_t sensor_num;
1484} __packed;
1485/* This returns a struct ec_thermal_config */
1486
1487/* Version 1 - set config for one sensor.
1488 * Use read-modify-write for best results! */
1489struct ec_params_thermal_set_threshold_v1 {
1490 uint32_t sensor_num;
1491 struct ec_thermal_config cfg;
1492} __packed;
1493/* This returns no data */
1494
1495/****************************************************************************/
1496
894/* Toggle automatic fan control */ 1497/* Toggle automatic fan control */
895#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x52 1498#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x52
896 1499
@@ -920,6 +1523,18 @@ struct ec_params_tmp006_set_calibration {
920 float b2; 1523 float b2;
921} __packed; 1524} __packed;
922 1525
1526/* Read raw TMP006 data */
1527#define EC_CMD_TMP006_GET_RAW 0x55
1528
1529struct ec_params_tmp006_get_raw {
1530 uint8_t index;
1531} __packed;
1532
1533struct ec_response_tmp006_get_raw {
1534 int32_t t; /* In 1/100 K */
1535 int32_t v; /* In nV */
1536};
1537
923/*****************************************************************************/ 1538/*****************************************************************************/
924/* MKBP - Matrix KeyBoard Protocol */ 1539/* MKBP - Matrix KeyBoard Protocol */
925 1540
@@ -1118,11 +1733,41 @@ struct ec_params_switch_enable_backlight {
1118 1733
1119/* Enable/disable WLAN/Bluetooth */ 1734/* Enable/disable WLAN/Bluetooth */
1120#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x91 1735#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x91
1736#define EC_VER_SWITCH_ENABLE_WIRELESS 1
1121 1737
1122struct ec_params_switch_enable_wireless { 1738/* Version 0 params; no response */
1739struct ec_params_switch_enable_wireless_v0 {
1123 uint8_t enabled; 1740 uint8_t enabled;
1124} __packed; 1741} __packed;
1125 1742
1743/* Version 1 params */
1744struct ec_params_switch_enable_wireless_v1 {
1745 /* Flags to enable now */
1746 uint8_t now_flags;
1747
1748 /* Which flags to copy from now_flags */
1749 uint8_t now_mask;
1750
1751 /*
1752 * Flags to leave enabled in S3, if they're on at the S0->S3
1753 * transition. (Other flags will be disabled by the S0->S3
1754 * transition.)
1755 */
1756 uint8_t suspend_flags;
1757
1758 /* Which flags to copy from suspend_flags */
1759 uint8_t suspend_mask;
1760} __packed;
1761
1762/* Version 1 response */
1763struct ec_response_switch_enable_wireless_v1 {
1764 /* Flags to enable now */
1765 uint8_t now_flags;
1766
1767 /* Flags to leave enabled in S3 */
1768 uint8_t suspend_flags;
1769} __packed;
1770
1126/*****************************************************************************/ 1771/*****************************************************************************/
1127/* GPIO commands. Only available on EC if write protect has been disabled. */ 1772/* GPIO commands. Only available on EC if write protect has been disabled. */
1128 1773
@@ -1147,11 +1792,16 @@ struct ec_response_gpio_get {
1147/*****************************************************************************/ 1792/*****************************************************************************/
1148/* I2C commands. Only available when flash write protect is unlocked. */ 1793/* I2C commands. Only available when flash write protect is unlocked. */
1149 1794
1795/*
1796 * TODO(crosbug.com/p/23570): These commands are deprecated, and will be
1797 * removed soon. Use EC_CMD_I2C_XFER instead.
1798 */
1799
1150/* Read I2C bus */ 1800/* Read I2C bus */
1151#define EC_CMD_I2C_READ 0x94 1801#define EC_CMD_I2C_READ 0x94
1152 1802
1153struct ec_params_i2c_read { 1803struct ec_params_i2c_read {
1154 uint16_t addr; 1804 uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
1155 uint8_t read_size; /* Either 8 or 16. */ 1805 uint8_t read_size; /* Either 8 or 16. */
1156 uint8_t port; 1806 uint8_t port;
1157 uint8_t offset; 1807 uint8_t offset;
@@ -1165,7 +1815,7 @@ struct ec_response_i2c_read {
1165 1815
1166struct ec_params_i2c_write { 1816struct ec_params_i2c_write {
1167 uint16_t data; 1817 uint16_t data;
1168 uint16_t addr; 1818 uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
1169 uint8_t write_size; /* Either 8 or 16. */ 1819 uint8_t write_size; /* Either 8 or 16. */
1170 uint8_t port; 1820 uint8_t port;
1171 uint8_t offset; 1821 uint8_t offset;
@@ -1174,11 +1824,20 @@ struct ec_params_i2c_write {
1174/*****************************************************************************/ 1824/*****************************************************************************/
1175/* Charge state commands. Only available when flash write protect unlocked. */ 1825/* Charge state commands. Only available when flash write protect unlocked. */
1176 1826
1177/* Force charge state machine to stop in idle mode */ 1827/* Force charge state machine to stop charging the battery or force it to
1178#define EC_CMD_CHARGE_FORCE_IDLE 0x96 1828 * discharge the battery.
1829 */
1830#define EC_CMD_CHARGE_CONTROL 0x96
1831#define EC_VER_CHARGE_CONTROL 1
1179 1832
1180struct ec_params_force_idle { 1833enum ec_charge_control_mode {
1181 uint8_t enabled; 1834 CHARGE_CONTROL_NORMAL = 0,
1835 CHARGE_CONTROL_IDLE,
1836 CHARGE_CONTROL_DISCHARGE,
1837};
1838
1839struct ec_params_charge_control {
1840 uint32_t mode; /* enum charge_control_mode */
1182} __packed; 1841} __packed;
1183 1842
1184/*****************************************************************************/ 1843/*****************************************************************************/
@@ -1206,14 +1865,231 @@ struct ec_params_force_idle {
1206#define EC_CMD_BATTERY_CUT_OFF 0x99 1865#define EC_CMD_BATTERY_CUT_OFF 0x99
1207 1866
1208/*****************************************************************************/ 1867/*****************************************************************************/
1209/* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */ 1868/* USB port mux control. */
1210 1869
1211/* 1870/*
1212 * Dump charge state machine context. 1871 * Switch USB mux or return to automatic switching.
1213 * 1872 */
1214 * Response is a binary dump of charge state machine context. 1873#define EC_CMD_USB_MUX 0x9a
1874
1875struct ec_params_usb_mux {
1876 uint8_t mux;
1877} __packed;
1878
1879/*****************************************************************************/
1880/* LDOs / FETs control. */
1881
1882enum ec_ldo_state {
1883 EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */
1884 EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */
1885};
1886
1887/*
1888 * Switch on/off a LDO.
1889 */
1890#define EC_CMD_LDO_SET 0x9b
1891
1892struct ec_params_ldo_set {
1893 uint8_t index;
1894 uint8_t state;
1895} __packed;
1896
1897/*
1898 * Get LDO state.
1899 */
1900#define EC_CMD_LDO_GET 0x9c
1901
1902struct ec_params_ldo_get {
1903 uint8_t index;
1904} __packed;
1905
1906struct ec_response_ldo_get {
1907 uint8_t state;
1908} __packed;
1909
1910/*****************************************************************************/
1911/* Power info. */
1912
1913/*
1914 * Get power info.
1915 */
1916#define EC_CMD_POWER_INFO 0x9d
1917
1918struct ec_response_power_info {
1919 uint32_t usb_dev_type;
1920 uint16_t voltage_ac;
1921 uint16_t voltage_system;
1922 uint16_t current_system;
1923 uint16_t usb_current_limit;
1924} __packed;
1925
1926/*****************************************************************************/
1927/* I2C passthru command */
1928
1929#define EC_CMD_I2C_PASSTHRU 0x9e
1930
1931/* Slave address is 10 (not 7) bit */
1932#define EC_I2C_FLAG_10BIT (1 << 16)
1933
1934/* Read data; if not present, message is a write */
1935#define EC_I2C_FLAG_READ (1 << 15)
1936
1937/* Mask for address */
1938#define EC_I2C_ADDR_MASK 0x3ff
1939
1940#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */
1941#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */
1942
1943/* Any error */
1944#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
1945
1946struct ec_params_i2c_passthru_msg {
1947 uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */
1948 uint16_t len; /* Number of bytes to read or write */
1949} __packed;
1950
1951struct ec_params_i2c_passthru {
1952 uint8_t port; /* I2C port number */
1953 uint8_t num_msgs; /* Number of messages */
1954 struct ec_params_i2c_passthru_msg msg[];
1955 /* Data to write for all messages is concatenated here */
1956} __packed;
1957
1958struct ec_response_i2c_passthru {
1959 uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */
1960 uint8_t num_msgs; /* Number of messages processed */
1961 uint8_t data[]; /* Data read by messages concatenated here */
1962} __packed;
1963
1964/*****************************************************************************/
1965/* Power button hang detect */
1966
1967#define EC_CMD_HANG_DETECT 0x9f
1968
1969/* Reasons to start hang detection timer */
1970/* Power button pressed */
1971#define EC_HANG_START_ON_POWER_PRESS (1 << 0)
1972
1973/* Lid closed */
1974#define EC_HANG_START_ON_LID_CLOSE (1 << 1)
1975
1976 /* Lid opened */
1977#define EC_HANG_START_ON_LID_OPEN (1 << 2)
1978
1979/* Start of AP S3->S0 transition (booting or resuming from suspend) */
1980#define EC_HANG_START_ON_RESUME (1 << 3)
1981
1982/* Reasons to cancel hang detection */
1983
1984/* Power button released */
1985#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8)
1986
1987/* Any host command from AP received */
1988#define EC_HANG_STOP_ON_HOST_COMMAND (1 << 9)
1989
1990/* Stop on end of AP S0->S3 transition (suspending or shutting down) */
1991#define EC_HANG_STOP_ON_SUSPEND (1 << 10)
1992
1993/*
1994 * If this flag is set, all the other fields are ignored, and the hang detect
1995 * timer is started. This provides the AP a way to start the hang timer
1996 * without reconfiguring any of the other hang detect settings. Note that
1997 * you must previously have configured the timeouts.
1998 */
1999#define EC_HANG_START_NOW (1 << 30)
2000
2001/*
2002 * If this flag is set, all the other fields are ignored (including
2003 * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer
2004 * without reconfiguring any of the other hang detect settings.
1215 */ 2005 */
1216#define EC_CMD_CHARGE_DUMP 0xa0 2006#define EC_HANG_STOP_NOW (1 << 31)
2007
2008struct ec_params_hang_detect {
2009 /* Flags; see EC_HANG_* */
2010 uint32_t flags;
2011
2012 /* Timeout in msec before generating host event, if enabled */
2013 uint16_t host_event_timeout_msec;
2014
2015 /* Timeout in msec before generating warm reboot, if enabled */
2016 uint16_t warm_reboot_timeout_msec;
2017} __packed;
2018
2019/*****************************************************************************/
2020/* Commands for battery charging */
2021
2022/*
2023 * This is the single catch-all host command to exchange data regarding the
2024 * charge state machine (v2 and up).
2025 */
2026#define EC_CMD_CHARGE_STATE 0xa0
2027
2028/* Subcommands for this host command */
2029enum charge_state_command {
2030 CHARGE_STATE_CMD_GET_STATE,
2031 CHARGE_STATE_CMD_GET_PARAM,
2032 CHARGE_STATE_CMD_SET_PARAM,
2033 CHARGE_STATE_NUM_CMDS
2034};
2035
2036/*
2037 * Known param numbers are defined here. Ranges are reserved for board-specific
2038 * params, which are handled by the particular implementations.
2039 */
2040enum charge_state_params {
2041 CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */
2042 CS_PARAM_CHG_CURRENT, /* charger current limit */
2043 CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */
2044 CS_PARAM_CHG_STATUS, /* charger-specific status */
2045 CS_PARAM_CHG_OPTION, /* charger-specific options */
2046 /* How many so far? */
2047 CS_NUM_BASE_PARAMS,
2048
2049 /* Range for CONFIG_CHARGER_PROFILE_OVERRIDE params */
2050 CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000,
2051 CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff,
2052
2053 /* Other custom param ranges go here... */
2054};
2055
2056struct ec_params_charge_state {
2057 uint8_t cmd; /* enum charge_state_command */
2058 union {
2059 struct {
2060 /* no args */
2061 } get_state;
2062
2063 struct {
2064 uint32_t param; /* enum charge_state_param */
2065 } get_param;
2066
2067 struct {
2068 uint32_t param; /* param to set */
2069 uint32_t value; /* value to set */
2070 } set_param;
2071 };
2072} __packed;
2073
2074struct ec_response_charge_state {
2075 union {
2076 struct {
2077 int ac;
2078 int chg_voltage;
2079 int chg_current;
2080 int chg_input_current;
2081 int batt_state_of_charge;
2082 } get_state;
2083
2084 struct {
2085 uint32_t value;
2086 } get_param;
2087 struct {
2088 /* no return values */
2089 } set_param;
2090 };
2091} __packed;
2092
1217 2093
1218/* 2094/*
1219 * Set maximum battery charging current. 2095 * Set maximum battery charging current.
@@ -1221,15 +2097,59 @@ struct ec_params_force_idle {
1221#define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1 2097#define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1
1222 2098
1223struct ec_params_current_limit { 2099struct ec_params_current_limit {
1224 uint32_t limit; 2100 uint32_t limit; /* in mA */
2101} __packed;
2102
2103/*
2104 * Set maximum external power current.
2105 */
2106#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2
2107
2108struct ec_params_ext_power_current_limit {
2109 uint32_t limit; /* in mA */
2110} __packed;
2111
2112/*****************************************************************************/
2113/* Smart battery pass-through */
2114
2115/* Get / Set 16-bit smart battery registers */
2116#define EC_CMD_SB_READ_WORD 0xb0
2117#define EC_CMD_SB_WRITE_WORD 0xb1
2118
2119/* Get / Set string smart battery parameters
2120 * formatted as SMBUS "block".
2121 */
2122#define EC_CMD_SB_READ_BLOCK 0xb2
2123#define EC_CMD_SB_WRITE_BLOCK 0xb3
2124
2125struct ec_params_sb_rd {
2126 uint8_t reg;
2127} __packed;
2128
2129struct ec_response_sb_rd_word {
2130 uint16_t value;
2131} __packed;
2132
2133struct ec_params_sb_wr_word {
2134 uint8_t reg;
2135 uint16_t value;
2136} __packed;
2137
2138struct ec_response_sb_rd_block {
2139 uint8_t data[32];
2140} __packed;
2141
2142struct ec_params_sb_wr_block {
2143 uint8_t reg;
2144 uint16_t data[32];
1225} __packed; 2145} __packed;
1226 2146
1227/*****************************************************************************/ 2147/*****************************************************************************/
1228/* System commands */ 2148/* System commands */
1229 2149
1230/* 2150/*
1231 * TODO: this is a confusing name, since it doesn't necessarily reboot the EC. 2151 * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't
1232 * Rename to "set image" or something similar. 2152 * necessarily reboot the EC. Rename to "image" or something similar?
1233 */ 2153 */
1234#define EC_CMD_REBOOT_EC 0xd2 2154#define EC_CMD_REBOOT_EC 0xd2
1235 2155
@@ -1308,6 +2228,7 @@ struct ec_params_reboot_ec {
1308#define EC_CMD_ACPI_QUERY_EVENT 0x84 2228#define EC_CMD_ACPI_QUERY_EVENT 0x84
1309 2229
1310/* Valid addresses in ACPI memory space, for read/write commands */ 2230/* Valid addresses in ACPI memory space, for read/write commands */
2231
1311/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ 2232/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
1312#define EC_ACPI_MEM_VERSION 0x00 2233#define EC_ACPI_MEM_VERSION 0x00
1313/* 2234/*
@@ -1317,8 +2238,60 @@ struct ec_params_reboot_ec {
1317#define EC_ACPI_MEM_TEST 0x01 2238#define EC_ACPI_MEM_TEST 0x01
1318/* Test compliment; writes here are ignored. */ 2239/* Test compliment; writes here are ignored. */
1319#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 2240#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
2241
1320/* Keyboard backlight brightness percent (0 - 100) */ 2242/* Keyboard backlight brightness percent (0 - 100) */
1321#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 2243#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
2244/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */
2245#define EC_ACPI_MEM_FAN_DUTY 0x04
2246
2247/*
2248 * DPTF temp thresholds. Any of the EC's temp sensors can have up to two
2249 * independent thresholds attached to them. The current value of the ID
2250 * register determines which sensor is affected by the THRESHOLD and COMMIT
2251 * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme
2252 * as the memory-mapped sensors. The COMMIT register applies those settings.
2253 *
2254 * The spec does not mandate any way to read back the threshold settings
2255 * themselves, but when a threshold is crossed the AP needs a way to determine
2256 * which sensor(s) are responsible. Each reading of the ID register clears and
2257 * returns one sensor ID that has crossed one of its threshold (in either
2258 * direction) since the last read. A value of 0xFF means "no new thresholds
2259 * have tripped". Setting or enabling the thresholds for a sensor will clear
2260 * the unread event count for that sensor.
2261 */
2262#define EC_ACPI_MEM_TEMP_ID 0x05
2263#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
2264#define EC_ACPI_MEM_TEMP_COMMIT 0x07
2265/*
2266 * Here are the bits for the COMMIT register:
2267 * bit 0 selects the threshold index for the chosen sensor (0/1)
2268 * bit 1 enables/disables the selected threshold (0 = off, 1 = on)
2269 * Each write to the commit register affects one threshold.
2270 */
2271#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0)
2272#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1)
2273/*
2274 * Example:
2275 *
2276 * Set the thresholds for sensor 2 to 50 C and 60 C:
2277 * write 2 to [0x05] -- select temp sensor 2
2278 * write 0x7b to [0x06] -- C_TO_K(50) - EC_TEMP_SENSOR_OFFSET
2279 * write 0x2 to [0x07] -- enable threshold 0 with this value
2280 * write 0x85 to [0x06] -- C_TO_K(60) - EC_TEMP_SENSOR_OFFSET
2281 * write 0x3 to [0x07] -- enable threshold 1 with this value
2282 *
2283 * Disable the 60 C threshold, leaving the 50 C threshold unchanged:
2284 * write 2 to [0x05] -- select temp sensor 2
2285 * write 0x1 to [0x07] -- disable threshold 1
2286 */
2287
2288/* DPTF battery charging current limit */
2289#define EC_ACPI_MEM_CHARGING_LIMIT 0x08
2290
2291/* Charging limit is specified in 64 mA steps */
2292#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
2293/* Value to disable DPTF battery charging limit */
2294#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
1322 2295
1323/* Current version of ACPI memory address space */ 2296/* Current version of ACPI memory address space */
1324#define EC_ACPI_MEM_VERSION_CURRENT 1 2297#define EC_ACPI_MEM_VERSION_CURRENT 1
@@ -1360,10 +2333,21 @@ struct ec_params_reboot_ec {
1360 * Header bytes greater than this indicate a later version. For example, 2333 * Header bytes greater than this indicate a later version. For example,
1361 * EC_CMD_VERSION0 + 1 means we are using version 1. 2334 * EC_CMD_VERSION0 + 1 means we are using version 1.
1362 * 2335 *
1363 * The old EC interface must not use commands 0dc or higher. 2336 * The old EC interface must not use commands 0xdc or higher.
1364 */ 2337 */
1365#define EC_CMD_VERSION0 0xdc 2338#define EC_CMD_VERSION0 0xdc
1366 2339
1367#endif /* !__ACPI__ */ 2340#endif /* !__ACPI__ */
1368 2341
2342/*****************************************************************************/
2343/*
2344 * Deprecated constants. These constants have been renamed for clarity. The
2345 * meaning and size has not changed. Programs that use the old names should
2346 * switch to the new names soon, as the old names may not be carried forward
2347 * forever.
2348 */
2349#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
2350#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
2351#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
2352
1369#endif /* __CROS_EC_COMMANDS_H */ 2353#endif /* __CROS_EC_COMMANDS_H */
diff --git a/include/linux/mfd/ipaq-micro.h b/include/linux/mfd/ipaq-micro.h
new file mode 100644
index 000000000000..5c4d29f6674f
--- /dev/null
+++ b/include/linux/mfd/ipaq-micro.h
@@ -0,0 +1,148 @@
1/*
2 * Header file for the compaq Micro MFD
3 */
4
5#ifndef _MFD_IPAQ_MICRO_H_
6#define _MFD_IPAQ_MICRO_H_
7
8#include <linux/spinlock.h>
9#include <linux/completion.h>
10#include <linux/list.h>
11
12#define TX_BUF_SIZE 32
13#define RX_BUF_SIZE 16
14#define CHAR_SOF 0x02
15
16/*
17 * These are the different messages that can be sent to the microcontroller
18 * to control various aspects.
19 */
20#define MSG_VERSION 0x0
21#define MSG_KEYBOARD 0x2
22#define MSG_TOUCHSCREEN 0x3
23#define MSG_EEPROM_READ 0x4
24#define MSG_EEPROM_WRITE 0x5
25#define MSG_THERMAL_SENSOR 0x6
26#define MSG_NOTIFY_LED 0x8
27#define MSG_BATTERY 0x9
28#define MSG_SPI_READ 0xb
29#define MSG_SPI_WRITE 0xc
30#define MSG_BACKLIGHT 0xd /* H3600 only */
31#define MSG_CODEC_CTRL 0xe /* H3100 only */
32#define MSG_DISPLAY_CTRL 0xf /* H3100 only */
33
34/* state of receiver parser */
35enum rx_state {
36 STATE_SOF = 0, /* Next byte should be start of frame */
37 STATE_ID, /* Next byte is ID & message length */
38 STATE_DATA, /* Next byte is a data byte */
39 STATE_CHKSUM /* Next byte should be checksum */
40};
41
42/**
43 * struct ipaq_micro_txdev - TX state
44 * @len: length of message in TX buffer
45 * @index: current index into TX buffer
46 * @buf: TX buffer
47 */
48struct ipaq_micro_txdev {
49 u8 len;
50 u8 index;
51 u8 buf[TX_BUF_SIZE];
52};
53
54/**
55 * struct ipaq_micro_rxdev - RX state
56 * @state: context of RX state machine
57 * @chksum: calculated checksum
58 * @id: message ID from packet
59 * @len: RX buffer length
60 * @index: RX buffer index
61 * @buf: RX buffer
62 */
63struct ipaq_micro_rxdev {
64 enum rx_state state;
65 unsigned char chksum;
66 u8 id;
67 unsigned int len;
68 unsigned int index;
69 u8 buf[RX_BUF_SIZE];
70};
71
72/**
73 * struct ipaq_micro_msg - message to the iPAQ microcontroller
74 * @id: 4-bit ID of the message
75 * @tx_len: length of TX data
76 * @tx_data: TX data to send
77 * @rx_len: length of receieved RX data
78 * @rx_data: RX data to recieve
79 * @ack: a completion that will be completed when RX is complete
80 * @node: list node if message gets queued
81 */
82struct ipaq_micro_msg {
83 u8 id;
84 u8 tx_len;
85 u8 tx_data[TX_BUF_SIZE];
86 u8 rx_len;
87 u8 rx_data[RX_BUF_SIZE];
88 struct completion ack;
89 struct list_head node;
90};
91
92/**
93 * struct ipaq_micro - iPAQ microcontroller state
94 * @dev: corresponding platform device
95 * @base: virtual memory base for underlying serial device
96 * @sdlc: virtual memory base for Synchronous Data Link Controller
97 * @version: version string
98 * @tx: TX state
99 * @rx: RX state
100 * @lock: lock for this state container
101 * @msg: current message
102 * @queue: message queue
103 * @key: callback for asynchronous key events
104 * @key_data: data to pass along with key events
105 * @ts: callback for asynchronous touchscreen events
106 * @ts_data: data to pass along with key events
107 */
108struct ipaq_micro {
109 struct device *dev;
110 void __iomem *base;
111 void __iomem *sdlc;
112 char version[5];
113 struct ipaq_micro_txdev tx; /* transmit ISR state */
114 struct ipaq_micro_rxdev rx; /* receive ISR state */
115 spinlock_t lock;
116 struct ipaq_micro_msg *msg;
117 struct list_head queue;
118 void (*key) (void *data, int len, unsigned char *rxdata);
119 void *key_data;
120 void (*ts) (void *data, int len, unsigned char *rxdata);
121 void *ts_data;
122};
123
124extern int
125ipaq_micro_tx_msg(struct ipaq_micro *micro, struct ipaq_micro_msg *msg);
126
127static inline int
128ipaq_micro_tx_msg_sync(struct ipaq_micro *micro,
129 struct ipaq_micro_msg *msg)
130{
131 int ret;
132
133 init_completion(&msg->ack);
134 ret = ipaq_micro_tx_msg(micro, msg);
135 wait_for_completion(&msg->ack);
136
137 return ret;
138}
139
140static inline int
141ipaq_micro_tx_msg_async(struct ipaq_micro *micro,
142 struct ipaq_micro_msg *msg)
143{
144 init_completion(&msg->ack);
145 return ipaq_micro_tx_msg(micro, msg);
146}
147
148#endif /* _MFD_IPAQ_MICRO_H_ */
diff --git a/include/linux/mfd/kempld.h b/include/linux/mfd/kempld.h
index b911ef3add03..26e0b469e567 100644
--- a/include/linux/mfd/kempld.h
+++ b/include/linux/mfd/kempld.h
@@ -51,6 +51,8 @@
51#define KEMPLD_TYPE_DEBUG 0x1 51#define KEMPLD_TYPE_DEBUG 0x1
52#define KEMPLD_TYPE_CUSTOM 0x2 52#define KEMPLD_TYPE_CUSTOM 0x2
53 53
54#define KEMPLD_VERSION_LEN 10
55
54/** 56/**
55 * struct kempld_info - PLD device information structure 57 * struct kempld_info - PLD device information structure
56 * @major: PLD major revision 58 * @major: PLD major revision
@@ -60,6 +62,7 @@
60 * @type: PLD type 62 * @type: PLD type
61 * @spec_major: PLD FW specification major revision 63 * @spec_major: PLD FW specification major revision
62 * @spec_minor: PLD FW specification minor revision 64 * @spec_minor: PLD FW specification minor revision
65 * @version: PLD version string
63 */ 66 */
64struct kempld_info { 67struct kempld_info {
65 unsigned int major; 68 unsigned int major;
@@ -69,6 +72,7 @@ struct kempld_info {
69 unsigned int type; 72 unsigned int type;
70 unsigned int spec_major; 73 unsigned int spec_major;
71 unsigned int spec_minor; 74 unsigned int spec_minor;
75 char version[KEMPLD_VERSION_LEN];
72}; 76};
73 77
74/** 78/**
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index a326c850f046..d63b1d309106 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -117,10 +117,6 @@ struct mc13xxx_led_platform_data {
117 117
118#define MAX_LED_CONTROL_REGS 6 118#define MAX_LED_CONTROL_REGS 6
119 119
120struct mc13xxx_leds_platform_data {
121 struct mc13xxx_led_platform_data *led;
122 int num_leds;
123
124/* MC13783 LED Control 0 */ 120/* MC13783 LED Control 0 */
125#define MC13783_LED_C0_ENABLE (1 << 0) 121#define MC13783_LED_C0_ENABLE (1 << 0)
126#define MC13783_LED_C0_TRIODE_MD (1 << 7) 122#define MC13783_LED_C0_TRIODE_MD (1 << 7)
@@ -169,10 +165,13 @@ struct mc13xxx_leds_platform_data {
169/* MC34708 LED Control 0 */ 165/* MC34708 LED Control 0 */
170#define MC34708_LED_C0_CURRENT_R(x) (((x) & 0x3) << 9) 166#define MC34708_LED_C0_CURRENT_R(x) (((x) & 0x3) << 9)
171#define MC34708_LED_C0_CURRENT_G(x) (((x) & 0x3) << 21) 167#define MC34708_LED_C0_CURRENT_G(x) (((x) & 0x3) << 21)
168
169struct mc13xxx_leds_platform_data {
170 struct mc13xxx_led_platform_data *led;
171 int num_leds;
172 u32 led_control[MAX_LED_CONTROL_REGS]; 172 u32 led_control[MAX_LED_CONTROL_REGS];
173}; 173};
174 174
175struct mc13xxx_buttons_platform_data {
176#define MC13783_BUTTON_DBNC_0MS 0 175#define MC13783_BUTTON_DBNC_0MS 0
177#define MC13783_BUTTON_DBNC_30MS 1 176#define MC13783_BUTTON_DBNC_30MS 1
178#define MC13783_BUTTON_DBNC_150MS 2 177#define MC13783_BUTTON_DBNC_150MS 2
@@ -180,6 +179,8 @@ struct mc13xxx_buttons_platform_data {
180#define MC13783_BUTTON_ENABLE (1 << 2) 179#define MC13783_BUTTON_ENABLE (1 << 2)
181#define MC13783_BUTTON_POL_INVERT (1 << 3) 180#define MC13783_BUTTON_POL_INVERT (1 << 3)
182#define MC13783_BUTTON_RESET_EN (1 << 4) 181#define MC13783_BUTTON_RESET_EN (1 << 4)
182
183struct mc13xxx_buttons_platform_data {
183 int b1on_flags; 184 int b1on_flags;
184 unsigned short b1on_key; 185 unsigned short b1on_key;
185 int b2on_flags; 186 int b2on_flags;
@@ -188,14 +189,14 @@ struct mc13xxx_buttons_platform_data {
188 unsigned short b3on_key; 189 unsigned short b3on_key;
189}; 190};
190 191
192#define MC13783_TS_ATO_FIRST false
193#define MC13783_TS_ATO_EACH true
194
191struct mc13xxx_ts_platform_data { 195struct mc13xxx_ts_platform_data {
192 /* Delay between Touchscreen polarization and ADC Conversion. 196 /* Delay between Touchscreen polarization and ADC Conversion.
193 * Given in clock ticks of a 32 kHz clock which gives a granularity of 197 * Given in clock ticks of a 32 kHz clock which gives a granularity of
194 * about 30.5ms */ 198 * about 30.5ms */
195 u8 ato; 199 u8 ato;
196
197#define MC13783_TS_ATO_FIRST false
198#define MC13783_TS_ATO_EACH true
199 /* Use the ATO delay only for the first conversion or for each one */ 200 /* Use the ATO delay only for the first conversion or for each one */
200 bool atox; 201 bool atox;
201}; 202};
@@ -210,11 +211,12 @@ struct mc13xxx_codec_platform_data {
210 enum mc13783_ssi_port dac_ssi_port; 211 enum mc13783_ssi_port dac_ssi_port;
211}; 212};
212 213
213struct mc13xxx_platform_data { 214#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
214#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
215#define MC13XXX_USE_CODEC (1 << 1) 215#define MC13XXX_USE_CODEC (1 << 1)
216#define MC13XXX_USE_ADC (1 << 2) 216#define MC13XXX_USE_ADC (1 << 2)
217#define MC13XXX_USE_RTC (1 << 3) 217#define MC13XXX_USE_RTC (1 << 3)
218
219struct mc13xxx_platform_data {
218 unsigned int flags; 220 unsigned int flags;
219 221
220 struct mc13xxx_regulator_platform_data regulators; 222 struct mc13xxx_regulator_platform_data regulators;
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index b8f87b704409..3420e09e2e20 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -482,10 +482,10 @@ enum usb_irq_events {
482 482
483/* helper macro to get correct slave number */ 483/* helper macro to get correct slave number */
484#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 484#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
485#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) 485#define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
486 486
487/* Base addresses of IP blocks in Palmas */ 487/* Base addresses of IP blocks in Palmas */
488#define PALMAS_SMPS_DVS_BASE 0x20 488#define PALMAS_SMPS_DVS_BASE 0x020
489#define PALMAS_RTC_BASE 0x100 489#define PALMAS_RTC_BASE 0x100
490#define PALMAS_VALIDITY_BASE 0x118 490#define PALMAS_VALIDITY_BASE 0x118
491#define PALMAS_SMPS_BASE 0x120 491#define PALMAS_SMPS_BASE 0x120
@@ -504,19 +504,19 @@ enum usb_irq_events {
504#define PALMAS_TRIM_GPADC_BASE 0x3CD 504#define PALMAS_TRIM_GPADC_BASE 0x3CD
505 505
506/* Registers for function RTC */ 506/* Registers for function RTC */
507#define PALMAS_SECONDS_REG 0x0 507#define PALMAS_SECONDS_REG 0x00
508#define PALMAS_MINUTES_REG 0x1 508#define PALMAS_MINUTES_REG 0x01
509#define PALMAS_HOURS_REG 0x2 509#define PALMAS_HOURS_REG 0x02
510#define PALMAS_DAYS_REG 0x3 510#define PALMAS_DAYS_REG 0x03
511#define PALMAS_MONTHS_REG 0x4 511#define PALMAS_MONTHS_REG 0x04
512#define PALMAS_YEARS_REG 0x5 512#define PALMAS_YEARS_REG 0x05
513#define PALMAS_WEEKS_REG 0x6 513#define PALMAS_WEEKS_REG 0x06
514#define PALMAS_ALARM_SECONDS_REG 0x8 514#define PALMAS_ALARM_SECONDS_REG 0x08
515#define PALMAS_ALARM_MINUTES_REG 0x9 515#define PALMAS_ALARM_MINUTES_REG 0x09
516#define PALMAS_ALARM_HOURS_REG 0xA 516#define PALMAS_ALARM_HOURS_REG 0x0A
517#define PALMAS_ALARM_DAYS_REG 0xB 517#define PALMAS_ALARM_DAYS_REG 0x0B
518#define PALMAS_ALARM_MONTHS_REG 0xC 518#define PALMAS_ALARM_MONTHS_REG 0x0C
519#define PALMAS_ALARM_YEARS_REG 0xD 519#define PALMAS_ALARM_YEARS_REG 0x0D
520#define PALMAS_RTC_CTRL_REG 0x10 520#define PALMAS_RTC_CTRL_REG 0x10
521#define PALMAS_RTC_STATUS_REG 0x11 521#define PALMAS_RTC_STATUS_REG 0x11
522#define PALMAS_RTC_INTERRUPTS_REG 0x12 522#define PALMAS_RTC_INTERRUPTS_REG 0x12
@@ -527,201 +527,201 @@ enum usb_irq_events {
527 527
528/* Bit definitions for SECONDS_REG */ 528/* Bit definitions for SECONDS_REG */
529#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 529#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
530#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 530#define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
531#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f 531#define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
532#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 532#define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
533 533
534/* Bit definitions for MINUTES_REG */ 534/* Bit definitions for MINUTES_REG */
535#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 535#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
536#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 536#define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
537#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f 537#define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
538#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 538#define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
539 539
540/* Bit definitions for HOURS_REG */ 540/* Bit definitions for HOURS_REG */
541#define PALMAS_HOURS_REG_PM_NAM 0x80 541#define PALMAS_HOURS_REG_PM_NAM 0x80
542#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 542#define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
543#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 543#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
544#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 544#define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
545#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f 545#define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
546#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 546#define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
547 547
548/* Bit definitions for DAYS_REG */ 548/* Bit definitions for DAYS_REG */
549#define PALMAS_DAYS_REG_DAY1_MASK 0x30 549#define PALMAS_DAYS_REG_DAY1_MASK 0x30
550#define PALMAS_DAYS_REG_DAY1_SHIFT 4 550#define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
551#define PALMAS_DAYS_REG_DAY0_MASK 0x0f 551#define PALMAS_DAYS_REG_DAY0_MASK 0x0F
552#define PALMAS_DAYS_REG_DAY0_SHIFT 0 552#define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
553 553
554/* Bit definitions for MONTHS_REG */ 554/* Bit definitions for MONTHS_REG */
555#define PALMAS_MONTHS_REG_MONTH1 0x10 555#define PALMAS_MONTHS_REG_MONTH1 0x10
556#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 556#define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
557#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f 557#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
558#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 558#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
559 559
560/* Bit definitions for YEARS_REG */ 560/* Bit definitions for YEARS_REG */
561#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 561#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
562#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 562#define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
563#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f 563#define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
564#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 564#define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
565 565
566/* Bit definitions for WEEKS_REG */ 566/* Bit definitions for WEEKS_REG */
567#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 567#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
568#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 568#define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
569 569
570/* Bit definitions for ALARM_SECONDS_REG */ 570/* Bit definitions for ALARM_SECONDS_REG */
571#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 571#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
572#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 572#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
573#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f 573#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
574#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 574#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
575 575
576/* Bit definitions for ALARM_MINUTES_REG */ 576/* Bit definitions for ALARM_MINUTES_REG */
577#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 577#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
578#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 578#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
579#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f 579#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
580#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 580#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
581 581
582/* Bit definitions for ALARM_HOURS_REG */ 582/* Bit definitions for ALARM_HOURS_REG */
583#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 583#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
584#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 584#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
585#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 585#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
586#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 586#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
587#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f 587#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
588#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 588#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
589 589
590/* Bit definitions for ALARM_DAYS_REG */ 590/* Bit definitions for ALARM_DAYS_REG */
591#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 591#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
592#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 592#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
593#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f 593#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
594#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 594#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
595 595
596/* Bit definitions for ALARM_MONTHS_REG */ 596/* Bit definitions for ALARM_MONTHS_REG */
597#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 597#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
598#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 598#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
599#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f 599#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
600#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 600#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
601 601
602/* Bit definitions for ALARM_YEARS_REG */ 602/* Bit definitions for ALARM_YEARS_REG */
603#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 603#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
604#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 604#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
605#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f 605#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
606#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 606#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
607 607
608/* Bit definitions for RTC_CTRL_REG */ 608/* Bit definitions for RTC_CTRL_REG */
609#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 609#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
610#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 610#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
611#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 611#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
612#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 612#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
613#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 613#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
614#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 614#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
615#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 615#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
616#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 616#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
617#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 617#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
618#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 618#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
619#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 619#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
620#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 620#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
621#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 621#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
622#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 622#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
623#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 623#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
624#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 624#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
625 625
626/* Bit definitions for RTC_STATUS_REG */ 626/* Bit definitions for RTC_STATUS_REG */
627#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 627#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
628#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 628#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
629#define PALMAS_RTC_STATUS_REG_ALARM 0x40 629#define PALMAS_RTC_STATUS_REG_ALARM 0x40
630#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 630#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
631#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 631#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
632#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 632#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
633#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 633#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
634#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 634#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
635#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 635#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
636#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 636#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
637#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 637#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
638#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 638#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
639#define PALMAS_RTC_STATUS_REG_RUN 0x02 639#define PALMAS_RTC_STATUS_REG_RUN 0x02
640#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 640#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
641 641
642/* Bit definitions for RTC_INTERRUPTS_REG */ 642/* Bit definitions for RTC_INTERRUPTS_REG */
643#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 643#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
644#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 644#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
645#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 645#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
646#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 646#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
647#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 647#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
648#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 648#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
649#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 649#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
650#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 650#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
651 651
652/* Bit definitions for RTC_COMP_LSB_REG */ 652/* Bit definitions for RTC_COMP_LSB_REG */
653#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff 653#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
654#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 654#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
655 655
656/* Bit definitions for RTC_COMP_MSB_REG */ 656/* Bit definitions for RTC_COMP_MSB_REG */
657#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff 657#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
658#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 658#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
659 659
660/* Bit definitions for RTC_RES_PROG_REG */ 660/* Bit definitions for RTC_RES_PROG_REG */
661#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f 661#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
662#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 662#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
663 663
664/* Bit definitions for RTC_RESET_STATUS_REG */ 664/* Bit definitions for RTC_RESET_STATUS_REG */
665#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 665#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
666#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 666#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
667 667
668/* Registers for function BACKUP */ 668/* Registers for function BACKUP */
669#define PALMAS_BACKUP0 0x0 669#define PALMAS_BACKUP0 0x00
670#define PALMAS_BACKUP1 0x1 670#define PALMAS_BACKUP1 0x01
671#define PALMAS_BACKUP2 0x2 671#define PALMAS_BACKUP2 0x02
672#define PALMAS_BACKUP3 0x3 672#define PALMAS_BACKUP3 0x03
673#define PALMAS_BACKUP4 0x4 673#define PALMAS_BACKUP4 0x04
674#define PALMAS_BACKUP5 0x5 674#define PALMAS_BACKUP5 0x05
675#define PALMAS_BACKUP6 0x6 675#define PALMAS_BACKUP6 0x06
676#define PALMAS_BACKUP7 0x7 676#define PALMAS_BACKUP7 0x07
677 677
678/* Bit definitions for BACKUP0 */ 678/* Bit definitions for BACKUP0 */
679#define PALMAS_BACKUP0_BACKUP_MASK 0xff 679#define PALMAS_BACKUP0_BACKUP_MASK 0xFF
680#define PALMAS_BACKUP0_BACKUP_SHIFT 0 680#define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
681 681
682/* Bit definitions for BACKUP1 */ 682/* Bit definitions for BACKUP1 */
683#define PALMAS_BACKUP1_BACKUP_MASK 0xff 683#define PALMAS_BACKUP1_BACKUP_MASK 0xFF
684#define PALMAS_BACKUP1_BACKUP_SHIFT 0 684#define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
685 685
686/* Bit definitions for BACKUP2 */ 686/* Bit definitions for BACKUP2 */
687#define PALMAS_BACKUP2_BACKUP_MASK 0xff 687#define PALMAS_BACKUP2_BACKUP_MASK 0xFF
688#define PALMAS_BACKUP2_BACKUP_SHIFT 0 688#define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
689 689
690/* Bit definitions for BACKUP3 */ 690/* Bit definitions for BACKUP3 */
691#define PALMAS_BACKUP3_BACKUP_MASK 0xff 691#define PALMAS_BACKUP3_BACKUP_MASK 0xFF
692#define PALMAS_BACKUP3_BACKUP_SHIFT 0 692#define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
693 693
694/* Bit definitions for BACKUP4 */ 694/* Bit definitions for BACKUP4 */
695#define PALMAS_BACKUP4_BACKUP_MASK 0xff 695#define PALMAS_BACKUP4_BACKUP_MASK 0xFF
696#define PALMAS_BACKUP4_BACKUP_SHIFT 0 696#define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
697 697
698/* Bit definitions for BACKUP5 */ 698/* Bit definitions for BACKUP5 */
699#define PALMAS_BACKUP5_BACKUP_MASK 0xff 699#define PALMAS_BACKUP5_BACKUP_MASK 0xFF
700#define PALMAS_BACKUP5_BACKUP_SHIFT 0 700#define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
701 701
702/* Bit definitions for BACKUP6 */ 702/* Bit definitions for BACKUP6 */
703#define PALMAS_BACKUP6_BACKUP_MASK 0xff 703#define PALMAS_BACKUP6_BACKUP_MASK 0xFF
704#define PALMAS_BACKUP6_BACKUP_SHIFT 0 704#define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
705 705
706/* Bit definitions for BACKUP7 */ 706/* Bit definitions for BACKUP7 */
707#define PALMAS_BACKUP7_BACKUP_MASK 0xff 707#define PALMAS_BACKUP7_BACKUP_MASK 0xFF
708#define PALMAS_BACKUP7_BACKUP_SHIFT 0 708#define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
709 709
710/* Registers for function SMPS */ 710/* Registers for function SMPS */
711#define PALMAS_SMPS12_CTRL 0x0 711#define PALMAS_SMPS12_CTRL 0x00
712#define PALMAS_SMPS12_TSTEP 0x1 712#define PALMAS_SMPS12_TSTEP 0x01
713#define PALMAS_SMPS12_FORCE 0x2 713#define PALMAS_SMPS12_FORCE 0x02
714#define PALMAS_SMPS12_VOLTAGE 0x3 714#define PALMAS_SMPS12_VOLTAGE 0x03
715#define PALMAS_SMPS3_CTRL 0x4 715#define PALMAS_SMPS3_CTRL 0x04
716#define PALMAS_SMPS3_VOLTAGE 0x7 716#define PALMAS_SMPS3_VOLTAGE 0x07
717#define PALMAS_SMPS45_CTRL 0x8 717#define PALMAS_SMPS45_CTRL 0x08
718#define PALMAS_SMPS45_TSTEP 0x9 718#define PALMAS_SMPS45_TSTEP 0x09
719#define PALMAS_SMPS45_FORCE 0xA 719#define PALMAS_SMPS45_FORCE 0x0A
720#define PALMAS_SMPS45_VOLTAGE 0xB 720#define PALMAS_SMPS45_VOLTAGE 0x0B
721#define PALMAS_SMPS6_CTRL 0xC 721#define PALMAS_SMPS6_CTRL 0x0C
722#define PALMAS_SMPS6_TSTEP 0xD 722#define PALMAS_SMPS6_TSTEP 0x0D
723#define PALMAS_SMPS6_FORCE 0xE 723#define PALMAS_SMPS6_FORCE 0x0E
724#define PALMAS_SMPS6_VOLTAGE 0xF 724#define PALMAS_SMPS6_VOLTAGE 0x0F
725#define PALMAS_SMPS7_CTRL 0x10 725#define PALMAS_SMPS7_CTRL 0x10
726#define PALMAS_SMPS7_VOLTAGE 0x13 726#define PALMAS_SMPS7_VOLTAGE 0x13
727#define PALMAS_SMPS8_CTRL 0x14 727#define PALMAS_SMPS8_CTRL 0x14
@@ -744,303 +744,303 @@ enum usb_irq_events {
744 744
745/* Bit definitions for SMPS12_CTRL */ 745/* Bit definitions for SMPS12_CTRL */
746#define PALMAS_SMPS12_CTRL_WR_S 0x80 746#define PALMAS_SMPS12_CTRL_WR_S 0x80
747#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 747#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
748#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 748#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
749#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 749#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
750#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 750#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
751#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 751#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
752#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 752#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
753#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 753#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
754#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 754#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
755#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 755#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
756 756
757/* Bit definitions for SMPS12_TSTEP */ 757/* Bit definitions for SMPS12_TSTEP */
758#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 758#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
759#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 759#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
760 760
761/* Bit definitions for SMPS12_FORCE */ 761/* Bit definitions for SMPS12_FORCE */
762#define PALMAS_SMPS12_FORCE_CMD 0x80 762#define PALMAS_SMPS12_FORCE_CMD 0x80
763#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 763#define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
764#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f 764#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
765#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 765#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
766 766
767/* Bit definitions for SMPS12_VOLTAGE */ 767/* Bit definitions for SMPS12_VOLTAGE */
768#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 768#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
769#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 769#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
770#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f 770#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
771#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 771#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
772 772
773/* Bit definitions for SMPS3_CTRL */ 773/* Bit definitions for SMPS3_CTRL */
774#define PALMAS_SMPS3_CTRL_WR_S 0x80 774#define PALMAS_SMPS3_CTRL_WR_S 0x80
775#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 775#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
776#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 776#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
777#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 777#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
778#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 778#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
779#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 779#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
780#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 780#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
781#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 781#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
782 782
783/* Bit definitions for SMPS3_VOLTAGE */ 783/* Bit definitions for SMPS3_VOLTAGE */
784#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 784#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
785#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 785#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
786#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f 786#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
787#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 787#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
788 788
789/* Bit definitions for SMPS45_CTRL */ 789/* Bit definitions for SMPS45_CTRL */
790#define PALMAS_SMPS45_CTRL_WR_S 0x80 790#define PALMAS_SMPS45_CTRL_WR_S 0x80
791#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 791#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
792#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 792#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
793#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 793#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
794#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 794#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
795#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 795#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
796#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 796#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
797#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 797#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
798#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 798#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
799#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 799#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
800 800
801/* Bit definitions for SMPS45_TSTEP */ 801/* Bit definitions for SMPS45_TSTEP */
802#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 802#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
803#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 803#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
804 804
805/* Bit definitions for SMPS45_FORCE */ 805/* Bit definitions for SMPS45_FORCE */
806#define PALMAS_SMPS45_FORCE_CMD 0x80 806#define PALMAS_SMPS45_FORCE_CMD 0x80
807#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 807#define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
808#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f 808#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
809#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 809#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
810 810
811/* Bit definitions for SMPS45_VOLTAGE */ 811/* Bit definitions for SMPS45_VOLTAGE */
812#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 812#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
813#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 813#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
814#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f 814#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
815#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 815#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
816 816
817/* Bit definitions for SMPS6_CTRL */ 817/* Bit definitions for SMPS6_CTRL */
818#define PALMAS_SMPS6_CTRL_WR_S 0x80 818#define PALMAS_SMPS6_CTRL_WR_S 0x80
819#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 819#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
820#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 820#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
821#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 821#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
822#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 822#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
823#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 823#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
824#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 824#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
825#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 825#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
826#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 826#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
827#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 827#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
828 828
829/* Bit definitions for SMPS6_TSTEP */ 829/* Bit definitions for SMPS6_TSTEP */
830#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 830#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
831#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 831#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
832 832
833/* Bit definitions for SMPS6_FORCE */ 833/* Bit definitions for SMPS6_FORCE */
834#define PALMAS_SMPS6_FORCE_CMD 0x80 834#define PALMAS_SMPS6_FORCE_CMD 0x80
835#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 835#define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
836#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f 836#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
837#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 837#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
838 838
839/* Bit definitions for SMPS6_VOLTAGE */ 839/* Bit definitions for SMPS6_VOLTAGE */
840#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 840#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
841#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 841#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
842#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f 842#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
843#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 843#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
844 844
845/* Bit definitions for SMPS7_CTRL */ 845/* Bit definitions for SMPS7_CTRL */
846#define PALMAS_SMPS7_CTRL_WR_S 0x80 846#define PALMAS_SMPS7_CTRL_WR_S 0x80
847#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 847#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
848#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 848#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
849#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 849#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
850#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 850#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
851#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 851#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
852#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 852#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
853#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 853#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
854 854
855/* Bit definitions for SMPS7_VOLTAGE */ 855/* Bit definitions for SMPS7_VOLTAGE */
856#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 856#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
857#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 857#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
858#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f 858#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
859#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 859#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
860 860
861/* Bit definitions for SMPS8_CTRL */ 861/* Bit definitions for SMPS8_CTRL */
862#define PALMAS_SMPS8_CTRL_WR_S 0x80 862#define PALMAS_SMPS8_CTRL_WR_S 0x80
863#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 863#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
864#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 864#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
865#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 865#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
866#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 866#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
867#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 867#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
868#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 868#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
869#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 869#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
870#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 870#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
871#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 871#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
872 872
873/* Bit definitions for SMPS8_TSTEP */ 873/* Bit definitions for SMPS8_TSTEP */
874#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 874#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
875#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 875#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
876 876
877/* Bit definitions for SMPS8_FORCE */ 877/* Bit definitions for SMPS8_FORCE */
878#define PALMAS_SMPS8_FORCE_CMD 0x80 878#define PALMAS_SMPS8_FORCE_CMD 0x80
879#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 879#define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
880#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f 880#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
881#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 881#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
882 882
883/* Bit definitions for SMPS8_VOLTAGE */ 883/* Bit definitions for SMPS8_VOLTAGE */
884#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 884#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
885#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 885#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
886#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f 886#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
887#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 887#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
888 888
889/* Bit definitions for SMPS9_CTRL */ 889/* Bit definitions for SMPS9_CTRL */
890#define PALMAS_SMPS9_CTRL_WR_S 0x80 890#define PALMAS_SMPS9_CTRL_WR_S 0x80
891#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 891#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
892#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 892#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
893#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 893#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
894#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 894#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
895#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 895#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
896#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 896#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
897#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 897#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
898 898
899/* Bit definitions for SMPS9_VOLTAGE */ 899/* Bit definitions for SMPS9_VOLTAGE */
900#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 900#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
901#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 901#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
902#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f 902#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
903#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 903#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
904 904
905/* Bit definitions for SMPS10_CTRL */ 905/* Bit definitions for SMPS10_CTRL */
906#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 906#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
907#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 907#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
908#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f 908#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
909#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 909#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
910 910
911/* Bit definitions for SMPS10_STATUS */ 911/* Bit definitions for SMPS10_STATUS */
912#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f 912#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
913#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 913#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
914 914
915/* Bit definitions for SMPS_CTRL */ 915/* Bit definitions for SMPS_CTRL */
916#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 916#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
917#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 917#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
918#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 918#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
919#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 919#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
920#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 920#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
921#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 921#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
922#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 922#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
923#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 923#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
924 924
925/* Bit definitions for SMPS_PD_CTRL */ 925/* Bit definitions for SMPS_PD_CTRL */
926#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 926#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
927#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 927#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
928#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 928#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
929#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 929#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
930#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 930#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
931#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 931#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
932#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 932#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
933#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 933#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
934#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 934#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
935#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 935#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
936#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 936#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
937#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 937#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
938#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 938#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
939#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 939#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
940 940
941/* Bit definitions for SMPS_THERMAL_EN */ 941/* Bit definitions for SMPS_THERMAL_EN */
942#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 942#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
943#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 943#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
944#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 944#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
945#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 945#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
946#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 946#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
947#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 947#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
948#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 948#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
949#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 949#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
950#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 950#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
951#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 951#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
952 952
953/* Bit definitions for SMPS_THERMAL_STATUS */ 953/* Bit definitions for SMPS_THERMAL_STATUS */
954#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 954#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
955#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 955#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
956#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 956#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
957#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 957#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
958#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 958#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
959#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 959#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
960#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 960#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
961#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 961#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
962#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 962#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
963#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 963#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
964 964
965/* Bit definitions for SMPS_SHORT_STATUS */ 965/* Bit definitions for SMPS_SHORT_STATUS */
966#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 966#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
967#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 967#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
968#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 968#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
969#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 969#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
970#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 970#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
971#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 971#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
972#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 972#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
973#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 973#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
974#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 974#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
975#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 975#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
976#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 976#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
977#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 977#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
978#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 978#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
979#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 979#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
980#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 980#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
981#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 981#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
982 982
983/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 983/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
984#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 984#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
985#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 985#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
986#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 986#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
987#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 987#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
988#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 988#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
989#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 989#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
990#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 990#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
991#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 991#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
992#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 992#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
993#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 993#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
994#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 994#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
995#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 995#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
996#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 996#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
997#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 997#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
998 998
999/* Bit definitions for SMPS_POWERGOOD_MASK1 */ 999/* Bit definitions for SMPS_POWERGOOD_MASK1 */
1000#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 1000#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1001#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 1001#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1002#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 1002#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1003#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 1003#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1004#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 1004#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1005#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 1005#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1006#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 1006#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1007#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 1007#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1008#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 1008#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1009#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 1009#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1010#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 1010#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1011#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 1011#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1012#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 1012#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1013#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 1013#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1014#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 1014#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1015#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 1015#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1016 1016
1017/* Bit definitions for SMPS_POWERGOOD_MASK2 */ 1017/* Bit definitions for SMPS_POWERGOOD_MASK2 */
1018#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 1018#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1019#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 1019#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1020#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 1020#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1021#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 1021#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1022#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 1022#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1023#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 1023#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1024#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 1024#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1025#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 1025#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1026 1026
1027/* Registers for function LDO */ 1027/* Registers for function LDO */
1028#define PALMAS_LDO1_CTRL 0x0 1028#define PALMAS_LDO1_CTRL 0x00
1029#define PALMAS_LDO1_VOLTAGE 0x1 1029#define PALMAS_LDO1_VOLTAGE 0x01
1030#define PALMAS_LDO2_CTRL 0x2 1030#define PALMAS_LDO2_CTRL 0x02
1031#define PALMAS_LDO2_VOLTAGE 0x3 1031#define PALMAS_LDO2_VOLTAGE 0x03
1032#define PALMAS_LDO3_CTRL 0x4 1032#define PALMAS_LDO3_CTRL 0x04
1033#define PALMAS_LDO3_VOLTAGE 0x5 1033#define PALMAS_LDO3_VOLTAGE 0x05
1034#define PALMAS_LDO4_CTRL 0x6 1034#define PALMAS_LDO4_CTRL 0x06
1035#define PALMAS_LDO4_VOLTAGE 0x7 1035#define PALMAS_LDO4_VOLTAGE 0x07
1036#define PALMAS_LDO5_CTRL 0x8 1036#define PALMAS_LDO5_CTRL 0x08
1037#define PALMAS_LDO5_VOLTAGE 0x9 1037#define PALMAS_LDO5_VOLTAGE 0x09
1038#define PALMAS_LDO6_CTRL 0xA 1038#define PALMAS_LDO6_CTRL 0x0A
1039#define PALMAS_LDO6_VOLTAGE 0xB 1039#define PALMAS_LDO6_VOLTAGE 0x0B
1040#define PALMAS_LDO7_CTRL 0xC 1040#define PALMAS_LDO7_CTRL 0x0C
1041#define PALMAS_LDO7_VOLTAGE 0xD 1041#define PALMAS_LDO7_VOLTAGE 0x0D
1042#define PALMAS_LDO8_CTRL 0xE 1042#define PALMAS_LDO8_CTRL 0x0E
1043#define PALMAS_LDO8_VOLTAGE 0xF 1043#define PALMAS_LDO8_VOLTAGE 0x0F
1044#define PALMAS_LDO9_CTRL 0x10 1044#define PALMAS_LDO9_CTRL 0x10
1045#define PALMAS_LDO9_VOLTAGE 0x11 1045#define PALMAS_LDO9_VOLTAGE 0x11
1046#define PALMAS_LDOLN_CTRL 0x12 1046#define PALMAS_LDOLN_CTRL 0x12
@@ -1055,236 +1055,236 @@ enum usb_irq_events {
1055 1055
1056/* Bit definitions for LDO1_CTRL */ 1056/* Bit definitions for LDO1_CTRL */
1057#define PALMAS_LDO1_CTRL_WR_S 0x80 1057#define PALMAS_LDO1_CTRL_WR_S 0x80
1058#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 1058#define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1059#define PALMAS_LDO1_CTRL_STATUS 0x10 1059#define PALMAS_LDO1_CTRL_STATUS 0x10
1060#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 1060#define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1061#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1061#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1062#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 1062#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1063#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1063#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1064#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 1064#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1065 1065
1066/* Bit definitions for LDO1_VOLTAGE */ 1066/* Bit definitions for LDO1_VOLTAGE */
1067#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f 1067#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1068#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 1068#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1069 1069
1070/* Bit definitions for LDO2_CTRL */ 1070/* Bit definitions for LDO2_CTRL */
1071#define PALMAS_LDO2_CTRL_WR_S 0x80 1071#define PALMAS_LDO2_CTRL_WR_S 0x80
1072#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 1072#define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1073#define PALMAS_LDO2_CTRL_STATUS 0x10 1073#define PALMAS_LDO2_CTRL_STATUS 0x10
1074#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 1074#define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1075#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1075#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1076#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 1076#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1077#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1077#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1078#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 1078#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1079 1079
1080/* Bit definitions for LDO2_VOLTAGE */ 1080/* Bit definitions for LDO2_VOLTAGE */
1081#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f 1081#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1082#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 1082#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1083 1083
1084/* Bit definitions for LDO3_CTRL */ 1084/* Bit definitions for LDO3_CTRL */
1085#define PALMAS_LDO3_CTRL_WR_S 0x80 1085#define PALMAS_LDO3_CTRL_WR_S 0x80
1086#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 1086#define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1087#define PALMAS_LDO3_CTRL_STATUS 0x10 1087#define PALMAS_LDO3_CTRL_STATUS 0x10
1088#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 1088#define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1089#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1089#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1090#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 1090#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1091#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1091#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1092#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 1092#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1093 1093
1094/* Bit definitions for LDO3_VOLTAGE */ 1094/* Bit definitions for LDO3_VOLTAGE */
1095#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f 1095#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1096#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 1096#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1097 1097
1098/* Bit definitions for LDO4_CTRL */ 1098/* Bit definitions for LDO4_CTRL */
1099#define PALMAS_LDO4_CTRL_WR_S 0x80 1099#define PALMAS_LDO4_CTRL_WR_S 0x80
1100#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 1100#define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1101#define PALMAS_LDO4_CTRL_STATUS 0x10 1101#define PALMAS_LDO4_CTRL_STATUS 0x10
1102#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 1102#define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1103#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1103#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1104#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 1104#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1105#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1105#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1106#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 1106#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1107 1107
1108/* Bit definitions for LDO4_VOLTAGE */ 1108/* Bit definitions for LDO4_VOLTAGE */
1109#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f 1109#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1110#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 1110#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1111 1111
1112/* Bit definitions for LDO5_CTRL */ 1112/* Bit definitions for LDO5_CTRL */
1113#define PALMAS_LDO5_CTRL_WR_S 0x80 1113#define PALMAS_LDO5_CTRL_WR_S 0x80
1114#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 1114#define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1115#define PALMAS_LDO5_CTRL_STATUS 0x10 1115#define PALMAS_LDO5_CTRL_STATUS 0x10
1116#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 1116#define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1117#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1117#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1118#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 1118#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1119#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1119#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1120#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 1120#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1121 1121
1122/* Bit definitions for LDO5_VOLTAGE */ 1122/* Bit definitions for LDO5_VOLTAGE */
1123#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f 1123#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1124#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 1124#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1125 1125
1126/* Bit definitions for LDO6_CTRL */ 1126/* Bit definitions for LDO6_CTRL */
1127#define PALMAS_LDO6_CTRL_WR_S 0x80 1127#define PALMAS_LDO6_CTRL_WR_S 0x80
1128#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 1128#define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1129#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1129#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1130#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 1130#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1131#define PALMAS_LDO6_CTRL_STATUS 0x10 1131#define PALMAS_LDO6_CTRL_STATUS 0x10
1132#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 1132#define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1133#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1133#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1134#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 1134#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1135#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1135#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1136#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 1136#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1137 1137
1138/* Bit definitions for LDO6_VOLTAGE */ 1138/* Bit definitions for LDO6_VOLTAGE */
1139#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f 1139#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1140#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 1140#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1141 1141
1142/* Bit definitions for LDO7_CTRL */ 1142/* Bit definitions for LDO7_CTRL */
1143#define PALMAS_LDO7_CTRL_WR_S 0x80 1143#define PALMAS_LDO7_CTRL_WR_S 0x80
1144#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 1144#define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1145#define PALMAS_LDO7_CTRL_STATUS 0x10 1145#define PALMAS_LDO7_CTRL_STATUS 0x10
1146#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 1146#define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1147#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1147#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1148#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 1148#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1149#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1149#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1150#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 1150#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1151 1151
1152/* Bit definitions for LDO7_VOLTAGE */ 1152/* Bit definitions for LDO7_VOLTAGE */
1153#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f 1153#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1154#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 1154#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1155 1155
1156/* Bit definitions for LDO8_CTRL */ 1156/* Bit definitions for LDO8_CTRL */
1157#define PALMAS_LDO8_CTRL_WR_S 0x80 1157#define PALMAS_LDO8_CTRL_WR_S 0x80
1158#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 1158#define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1159#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1159#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1160#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 1160#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1161#define PALMAS_LDO8_CTRL_STATUS 0x10 1161#define PALMAS_LDO8_CTRL_STATUS 0x10
1162#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 1162#define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1163#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1163#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1164#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 1164#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1165#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1165#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1166#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 1166#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1167 1167
1168/* Bit definitions for LDO8_VOLTAGE */ 1168/* Bit definitions for LDO8_VOLTAGE */
1169#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f 1169#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1170#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 1170#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1171 1171
1172/* Bit definitions for LDO9_CTRL */ 1172/* Bit definitions for LDO9_CTRL */
1173#define PALMAS_LDO9_CTRL_WR_S 0x80 1173#define PALMAS_LDO9_CTRL_WR_S 0x80
1174#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 1174#define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1175#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1175#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1176#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 1176#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1177#define PALMAS_LDO9_CTRL_STATUS 0x10 1177#define PALMAS_LDO9_CTRL_STATUS 0x10
1178#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 1178#define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1179#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1179#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1180#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 1180#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1181#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1181#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1182#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 1182#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1183 1183
1184/* Bit definitions for LDO9_VOLTAGE */ 1184/* Bit definitions for LDO9_VOLTAGE */
1185#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f 1185#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1186#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 1186#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1187 1187
1188/* Bit definitions for LDOLN_CTRL */ 1188/* Bit definitions for LDOLN_CTRL */
1189#define PALMAS_LDOLN_CTRL_WR_S 0x80 1189#define PALMAS_LDOLN_CTRL_WR_S 0x80
1190#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 1190#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1191#define PALMAS_LDOLN_CTRL_STATUS 0x10 1191#define PALMAS_LDOLN_CTRL_STATUS 0x10
1192#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 1192#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1193#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1193#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1194#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 1194#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1195#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1195#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1196#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 1196#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1197 1197
1198/* Bit definitions for LDOLN_VOLTAGE */ 1198/* Bit definitions for LDOLN_VOLTAGE */
1199#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f 1199#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1200#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 1200#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1201 1201
1202/* Bit definitions for LDOUSB_CTRL */ 1202/* Bit definitions for LDOUSB_CTRL */
1203#define PALMAS_LDOUSB_CTRL_WR_S 0x80 1203#define PALMAS_LDOUSB_CTRL_WR_S 0x80
1204#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 1204#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1205#define PALMAS_LDOUSB_CTRL_STATUS 0x10 1205#define PALMAS_LDOUSB_CTRL_STATUS 0x10
1206#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 1206#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1207#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1207#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1208#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 1208#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1209#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1209#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1210#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 1210#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1211 1211
1212/* Bit definitions for LDOUSB_VOLTAGE */ 1212/* Bit definitions for LDOUSB_VOLTAGE */
1213#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f 1213#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1214#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 1214#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1215 1215
1216/* Bit definitions for LDO_CTRL */ 1216/* Bit definitions for LDO_CTRL */
1217#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1217#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1218#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 1218#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1219 1219
1220/* Bit definitions for LDO_PD_CTRL1 */ 1220/* Bit definitions for LDO_PD_CTRL1 */
1221#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1221#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1222#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 1222#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1223#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1223#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1224#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 1224#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1225#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1225#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1226#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 1226#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1227#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1227#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1228#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 1228#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1229#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1229#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1230#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 1230#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1231#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1231#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1232#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 1232#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1233#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1233#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1234#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 1234#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1235#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1235#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1236#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 1236#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1237 1237
1238/* Bit definitions for LDO_PD_CTRL2 */ 1238/* Bit definitions for LDO_PD_CTRL2 */
1239#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1239#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1240#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 1240#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1241#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1241#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1242#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 1242#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1243#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1243#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1244#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 1244#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1245 1245
1246/* Bit definitions for LDO_SHORT_STATUS1 */ 1246/* Bit definitions for LDO_SHORT_STATUS1 */
1247#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1247#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1248#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 1248#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1249#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1249#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1250#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 1250#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1251#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1251#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1252#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 1252#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1253#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1253#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1254#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 1254#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1255#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1255#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1256#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 1256#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1257#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1257#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1258#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 1258#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1259#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1259#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1260#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 1260#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1261#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1261#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1262#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 1262#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1263 1263
1264/* Bit definitions for LDO_SHORT_STATUS2 */ 1264/* Bit definitions for LDO_SHORT_STATUS2 */
1265#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1265#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1266#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 1266#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1267#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1267#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1268#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 1268#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1269#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1269#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1270#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 1270#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1271#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1271#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1272#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 1272#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1273 1273
1274/* Registers for function PMU_CONTROL */ 1274/* Registers for function PMU_CONTROL */
1275#define PALMAS_DEV_CTRL 0x0 1275#define PALMAS_DEV_CTRL 0x00
1276#define PALMAS_POWER_CTRL 0x1 1276#define PALMAS_POWER_CTRL 0x01
1277#define PALMAS_VSYS_LO 0x2 1277#define PALMAS_VSYS_LO 0x02
1278#define PALMAS_VSYS_MON 0x3 1278#define PALMAS_VSYS_MON 0x03
1279#define PALMAS_VBAT_MON 0x4 1279#define PALMAS_VBAT_MON 0x04
1280#define PALMAS_WATCHDOG 0x5 1280#define PALMAS_WATCHDOG 0x05
1281#define PALMAS_BOOT_STATUS 0x6 1281#define PALMAS_BOOT_STATUS 0x06
1282#define PALMAS_BATTERY_BOUNCE 0x7 1282#define PALMAS_BATTERY_BOUNCE 0x07
1283#define PALMAS_BACKUP_BATTERY_CTRL 0x8 1283#define PALMAS_BACKUP_BATTERY_CTRL 0x08
1284#define PALMAS_LONG_PRESS_KEY 0x9 1284#define PALMAS_LONG_PRESS_KEY 0x09
1285#define PALMAS_OSC_THERM_CTRL 0xA 1285#define PALMAS_OSC_THERM_CTRL 0x0A
1286#define PALMAS_BATDEBOUNCING 0xB 1286#define PALMAS_BATDEBOUNCING 0x0B
1287#define PALMAS_SWOFF_HWRST 0xF 1287#define PALMAS_SWOFF_HWRST 0x0F
1288#define PALMAS_SWOFF_COLDRST 0x10 1288#define PALMAS_SWOFF_COLDRST 0x10
1289#define PALMAS_SWOFF_STATUS 0x11 1289#define PALMAS_SWOFF_STATUS 0x11
1290#define PALMAS_PMU_CONFIG 0x12 1290#define PALMAS_PMU_CONFIG 0x12
@@ -1296,668 +1296,668 @@ enum usb_irq_events {
1296 1296
1297/* Bit definitions for DEV_CTRL */ 1297/* Bit definitions for DEV_CTRL */
1298#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1298#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1299#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 1299#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1300#define PALMAS_DEV_CTRL_SW_RST 0x02 1300#define PALMAS_DEV_CTRL_SW_RST 0x02
1301#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 1301#define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1302#define PALMAS_DEV_CTRL_DEV_ON 0x01 1302#define PALMAS_DEV_CTRL_DEV_ON 0x01
1303#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 1303#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1304 1304
1305/* Bit definitions for POWER_CTRL */ 1305/* Bit definitions for POWER_CTRL */
1306#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1306#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1307#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 1307#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1308#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1308#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1309#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 1309#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1310#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1310#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1311#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 1311#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1312 1312
1313/* Bit definitions for VSYS_LO */ 1313/* Bit definitions for VSYS_LO */
1314#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f 1314#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1315#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 1315#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1316 1316
1317/* Bit definitions for VSYS_MON */ 1317/* Bit definitions for VSYS_MON */
1318#define PALMAS_VSYS_MON_ENABLE 0x80 1318#define PALMAS_VSYS_MON_ENABLE 0x80
1319#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 1319#define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1320#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f 1320#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1321#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 1321#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1322 1322
1323/* Bit definitions for VBAT_MON */ 1323/* Bit definitions for VBAT_MON */
1324#define PALMAS_VBAT_MON_ENABLE 0x80 1324#define PALMAS_VBAT_MON_ENABLE 0x80
1325#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 1325#define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1326#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f 1326#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1327#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 1327#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1328 1328
1329/* Bit definitions for WATCHDOG */ 1329/* Bit definitions for WATCHDOG */
1330#define PALMAS_WATCHDOG_LOCK 0x20 1330#define PALMAS_WATCHDOG_LOCK 0x20
1331#define PALMAS_WATCHDOG_LOCK_SHIFT 5 1331#define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1332#define PALMAS_WATCHDOG_ENABLE 0x10 1332#define PALMAS_WATCHDOG_ENABLE 0x10
1333#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 1333#define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1334#define PALMAS_WATCHDOG_MODE 0x08 1334#define PALMAS_WATCHDOG_MODE 0x08
1335#define PALMAS_WATCHDOG_MODE_SHIFT 3 1335#define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1336#define PALMAS_WATCHDOG_TIMER_MASK 0x07 1336#define PALMAS_WATCHDOG_TIMER_MASK 0x07
1337#define PALMAS_WATCHDOG_TIMER_SHIFT 0 1337#define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1338 1338
1339/* Bit definitions for BOOT_STATUS */ 1339/* Bit definitions for BOOT_STATUS */
1340#define PALMAS_BOOT_STATUS_BOOT1 0x02 1340#define PALMAS_BOOT_STATUS_BOOT1 0x02
1341#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 1341#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1342#define PALMAS_BOOT_STATUS_BOOT0 0x01 1342#define PALMAS_BOOT_STATUS_BOOT0 0x01
1343#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 1343#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1344 1344
1345/* Bit definitions for BATTERY_BOUNCE */ 1345/* Bit definitions for BATTERY_BOUNCE */
1346#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f 1346#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1347#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 1347#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1348 1348
1349/* Bit definitions for BACKUP_BATTERY_CTRL */ 1349/* Bit definitions for BACKUP_BATTERY_CTRL */
1350#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1350#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1351#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 1351#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1352#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1352#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1353#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 1353#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1354#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1354#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1355#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 1355#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1356#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1356#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1357#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 1357#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1358#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1358#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1359#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 1359#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1360#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1360#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1361#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 1361#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1362#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1362#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1363#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 1363#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1364 1364
1365/* Bit definitions for LONG_PRESS_KEY */ 1365/* Bit definitions for LONG_PRESS_KEY */
1366#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1366#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1367#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 1367#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1368#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1368#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1369#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 1369#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1370#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1370#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1371#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 1371#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1372#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1372#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1373#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 1373#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1374 1374
1375/* Bit definitions for OSC_THERM_CTRL */ 1375/* Bit definitions for OSC_THERM_CTRL */
1376#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1376#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1377#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 1377#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1378#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1378#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1379#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 1379#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1380#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1380#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1381#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 1381#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1382#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1382#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1383#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 1383#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1384#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1384#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1385#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 1385#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1386#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1386#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1387#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 1387#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1388#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1388#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1389#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 1389#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1390 1390
1391/* Bit definitions for BATDEBOUNCING */ 1391/* Bit definitions for BATDEBOUNCING */
1392#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1392#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1393#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 1393#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1394#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1394#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1395#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 1395#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1396#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1396#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1397#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 1397#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1398 1398
1399/* Bit definitions for SWOFF_HWRST */ 1399/* Bit definitions for SWOFF_HWRST */
1400#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1400#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1401#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 1401#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1402#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1402#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1403#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 1403#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1404#define PALMAS_SWOFF_HWRST_WTD 0x20 1404#define PALMAS_SWOFF_HWRST_WTD 0x20
1405#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 1405#define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1406#define PALMAS_SWOFF_HWRST_TSHUT 0x10 1406#define PALMAS_SWOFF_HWRST_TSHUT 0x10
1407#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 1407#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1408#define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1408#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1409#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 1409#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1410#define PALMAS_SWOFF_HWRST_SW_RST 0x04 1410#define PALMAS_SWOFF_HWRST_SW_RST 0x04
1411#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 1411#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1412#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1412#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1413#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 1413#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1414#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1414#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1415#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 1415#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1416 1416
1417/* Bit definitions for SWOFF_COLDRST */ 1417/* Bit definitions for SWOFF_COLDRST */
1418#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1418#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1419#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 1419#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1420#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1420#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1421#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 1421#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1422#define PALMAS_SWOFF_COLDRST_WTD 0x20 1422#define PALMAS_SWOFF_COLDRST_WTD 0x20
1423#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 1423#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1424#define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1424#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1425#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 1425#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1426#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1426#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1427#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 1427#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1428#define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1428#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1429#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 1429#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1430#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1430#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1431#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 1431#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1432#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1432#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1433#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 1433#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1434 1434
1435/* Bit definitions for SWOFF_STATUS */ 1435/* Bit definitions for SWOFF_STATUS */
1436#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1436#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1437#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 1437#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1438#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1438#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1439#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 1439#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1440#define PALMAS_SWOFF_STATUS_WTD 0x20 1440#define PALMAS_SWOFF_STATUS_WTD 0x20
1441#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 1441#define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1442#define PALMAS_SWOFF_STATUS_TSHUT 0x10 1442#define PALMAS_SWOFF_STATUS_TSHUT 0x10
1443#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 1443#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1444#define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1444#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1445#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 1445#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1446#define PALMAS_SWOFF_STATUS_SW_RST 0x04 1446#define PALMAS_SWOFF_STATUS_SW_RST 0x04
1447#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 1447#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1448#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1448#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1449#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 1449#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1450#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1450#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1451#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 1451#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1452 1452
1453/* Bit definitions for PMU_CONFIG */ 1453/* Bit definitions for PMU_CONFIG */
1454#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1454#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1455#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 1455#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1456#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1456#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1457#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 1457#define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1458#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1458#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1459#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 1459#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1460#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1460#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1461#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 1461#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1462#define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1462#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1463#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 1463#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1464 1464
1465/* Bit definitions for SPARE */ 1465/* Bit definitions for SPARE */
1466#define PALMAS_SPARE_SPARE_MASK 0xf8 1466#define PALMAS_SPARE_SPARE_MASK 0xf8
1467#define PALMAS_SPARE_SPARE_SHIFT 3 1467#define PALMAS_SPARE_SPARE_SHIFT 0x03
1468#define PALMAS_SPARE_REGEN3_OD 0x04 1468#define PALMAS_SPARE_REGEN3_OD 0x04
1469#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 1469#define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1470#define PALMAS_SPARE_REGEN2_OD 0x02 1470#define PALMAS_SPARE_REGEN2_OD 0x02
1471#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 1471#define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1472#define PALMAS_SPARE_REGEN1_OD 0x01 1472#define PALMAS_SPARE_REGEN1_OD 0x01
1473#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 1473#define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1474 1474
1475/* Bit definitions for PMU_SECONDARY_INT */ 1475/* Bit definitions for PMU_SECONDARY_INT */
1476#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1476#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1477#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 1477#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1478#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1478#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1479#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 1479#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1480#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1480#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1481#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 1481#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1482#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1482#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1483#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 1483#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1484#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1484#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1485#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 1485#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1486#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1486#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1487#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 1487#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1488#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1488#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1489#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 1489#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1490#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1490#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1491#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 1491#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1492 1492
1493/* Bit definitions for SW_REVISION */ 1493/* Bit definitions for SW_REVISION */
1494#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff 1494#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1495#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 1495#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1496 1496
1497/* Bit definitions for EXT_CHRG_CTRL */ 1497/* Bit definitions for EXT_CHRG_CTRL */
1498#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1498#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1499#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 1499#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1500#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1500#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1501#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 1501#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1502#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1502#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1503#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 1503#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1504#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1504#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1505#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 1505#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1506#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1506#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1507#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 1507#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1508#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1508#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1509#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 1509#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1510 1510
1511/* Bit definitions for PMU_SECONDARY_INT2 */ 1511/* Bit definitions for PMU_SECONDARY_INT2 */
1512#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1512#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1513#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 1513#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1514#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1514#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1515#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 1515#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1516#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1516#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1517#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 1517#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1518#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1518#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1519#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 1519#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1520 1520
1521/* Registers for function RESOURCE */ 1521/* Registers for function RESOURCE */
1522#define PALMAS_CLK32KG_CTRL 0x0 1522#define PALMAS_CLK32KG_CTRL 0x00
1523#define PALMAS_CLK32KGAUDIO_CTRL 0x1 1523#define PALMAS_CLK32KGAUDIO_CTRL 0x01
1524#define PALMAS_REGEN1_CTRL 0x2 1524#define PALMAS_REGEN1_CTRL 0x02
1525#define PALMAS_REGEN2_CTRL 0x3 1525#define PALMAS_REGEN2_CTRL 0x03
1526#define PALMAS_SYSEN1_CTRL 0x4 1526#define PALMAS_SYSEN1_CTRL 0x04
1527#define PALMAS_SYSEN2_CTRL 0x5 1527#define PALMAS_SYSEN2_CTRL 0x05
1528#define PALMAS_NSLEEP_RES_ASSIGN 0x6 1528#define PALMAS_NSLEEP_RES_ASSIGN 0x06
1529#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 1529#define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1530#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 1530#define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1531#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 1531#define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1532#define PALMAS_ENABLE1_RES_ASSIGN 0xA 1532#define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1533#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB 1533#define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1534#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC 1534#define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1535#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD 1535#define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1536#define PALMAS_ENABLE2_RES_ASSIGN 0xE 1536#define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1537#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF 1537#define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1538#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1538#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1539#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1539#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1540#define PALMAS_REGEN3_CTRL 0x12 1540#define PALMAS_REGEN3_CTRL 0x12
1541 1541
1542/* Bit definitions for CLK32KG_CTRL */ 1542/* Bit definitions for CLK32KG_CTRL */
1543#define PALMAS_CLK32KG_CTRL_STATUS 0x10 1543#define PALMAS_CLK32KG_CTRL_STATUS 0x10
1544#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 1544#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1545#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1545#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1546#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 1546#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1547#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1547#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1548#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 1548#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1549 1549
1550/* Bit definitions for CLK32KGAUDIO_CTRL */ 1550/* Bit definitions for CLK32KGAUDIO_CTRL */
1551#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1551#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1552#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 1552#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1553#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1553#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1554#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 1554#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1555#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1555#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1556#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 1556#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1557#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1557#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1558#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 1558#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1559 1559
1560/* Bit definitions for REGEN1_CTRL */ 1560/* Bit definitions for REGEN1_CTRL */
1561#define PALMAS_REGEN1_CTRL_STATUS 0x10 1561#define PALMAS_REGEN1_CTRL_STATUS 0x10
1562#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 1562#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1563#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1563#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1564#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 1564#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1565#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1565#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1566#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 1566#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1567 1567
1568/* Bit definitions for REGEN2_CTRL */ 1568/* Bit definitions for REGEN2_CTRL */
1569#define PALMAS_REGEN2_CTRL_STATUS 0x10 1569#define PALMAS_REGEN2_CTRL_STATUS 0x10
1570#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 1570#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1571#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1571#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1572#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 1572#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1573#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1573#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1574#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 1574#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1575 1575
1576/* Bit definitions for SYSEN1_CTRL */ 1576/* Bit definitions for SYSEN1_CTRL */
1577#define PALMAS_SYSEN1_CTRL_STATUS 0x10 1577#define PALMAS_SYSEN1_CTRL_STATUS 0x10
1578#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 1578#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1579#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1579#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1580#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 1580#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1581#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1581#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1582#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 1582#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1583 1583
1584/* Bit definitions for SYSEN2_CTRL */ 1584/* Bit definitions for SYSEN2_CTRL */
1585#define PALMAS_SYSEN2_CTRL_STATUS 0x10 1585#define PALMAS_SYSEN2_CTRL_STATUS 0x10
1586#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 1586#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1587#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1587#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1588#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 1588#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1589#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1589#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1590#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 1590#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1591 1591
1592/* Bit definitions for NSLEEP_RES_ASSIGN */ 1592/* Bit definitions for NSLEEP_RES_ASSIGN */
1593#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1593#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1594#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 1594#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1595#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1595#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1596#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1596#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1597#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1597#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1598#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 1598#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1599#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1599#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1600#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 1600#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1601#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1601#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1602#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 1602#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1603#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1603#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1604#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 1604#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1605#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1605#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1606#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 1606#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1607 1607
1608/* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1608/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1609#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1609#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1610#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 1610#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1611#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1611#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1612#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 1612#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1613#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1613#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1614#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 1614#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1615#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1615#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1616#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 1616#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1617#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1617#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1618#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 1618#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1619#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1619#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1620#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 1620#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1621#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1621#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1622#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 1622#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1623#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1623#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1624#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 1624#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1625 1625
1626/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1626/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1627#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1627#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1628#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 1628#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1629#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1629#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1630#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 1630#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1631#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1631#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1632#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 1632#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1633#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1633#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1634#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 1634#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1635#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1635#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1636#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 1636#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1637#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1637#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1638#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 1638#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1639#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1639#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1640#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 1640#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1641#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1641#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1642#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 1642#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1643 1643
1644/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1644/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1645#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1645#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1646#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 1646#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1647#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1647#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1648#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 1648#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1649#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1649#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1650#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 1650#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1651 1651
1652/* Bit definitions for ENABLE1_RES_ASSIGN */ 1652/* Bit definitions for ENABLE1_RES_ASSIGN */
1653#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1653#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1654#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 1654#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1655#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1655#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1656#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1656#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1657#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1657#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1658#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 1658#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1659#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1659#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1660#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 1660#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1661#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1661#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1662#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 1662#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1663#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1663#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1664#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 1664#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1665#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1665#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1666#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 1666#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1667 1667
1668/* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1668/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1669#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1669#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1670#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 1670#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1671#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1671#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1672#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 1672#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1673#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1673#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1674#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 1674#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1675#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1675#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1676#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 1676#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1677#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1677#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1678#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 1678#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1679#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1679#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1680#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 1680#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1681#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1681#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1682#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 1682#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1683#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1683#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1684#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 1684#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1685 1685
1686/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1686/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1687#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1687#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1688#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 1688#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1689#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1689#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1690#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 1690#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1691#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1691#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1692#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 1692#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1693#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1693#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1694#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 1694#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1695#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1695#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1696#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 1696#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1697#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1697#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1698#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 1698#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1699#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1699#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1700#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 1700#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1701#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1701#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1702#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 1702#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1703 1703
1704/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1704/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1705#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1705#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1706#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 1706#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1707#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1707#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1708#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 1708#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1709#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1709#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1710#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 1710#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1711 1711
1712/* Bit definitions for ENABLE2_RES_ASSIGN */ 1712/* Bit definitions for ENABLE2_RES_ASSIGN */
1713#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1713#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1714#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 1714#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1715#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1715#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1716#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1716#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1717#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1717#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1718#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 1718#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1719#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1719#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1720#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 1720#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1721#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1721#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1722#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 1722#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1723#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1723#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1724#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 1724#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1725#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1725#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1726#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 1726#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1727 1727
1728/* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1728/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1729#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1729#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1730#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 1730#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1731#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1731#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1732#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 1732#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1733#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1733#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1734#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 1734#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1735#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1735#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1736#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 1736#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1737#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1737#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1738#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 1738#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1739#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1739#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1740#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 1740#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1741#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1741#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1742#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 1742#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1743#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1743#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1744#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 1744#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1745 1745
1746/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1746/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1747#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1747#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1748#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 1748#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1749#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1749#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1750#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 1750#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1751#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1751#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1752#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 1752#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1753#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1753#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1754#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 1754#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1755#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1755#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1756#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 1756#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1757#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1757#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1758#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 1758#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1759#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1759#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1760#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 1760#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1761#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1761#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1762#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 1762#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1763 1763
1764/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1764/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1765#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1765#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1766#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 1766#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1767#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1767#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1768#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 1768#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1769#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1769#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1770#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 1770#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1771 1771
1772/* Bit definitions for REGEN3_CTRL */ 1772/* Bit definitions for REGEN3_CTRL */
1773#define PALMAS_REGEN3_CTRL_STATUS 0x10 1773#define PALMAS_REGEN3_CTRL_STATUS 0x10
1774#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 1774#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1775#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1775#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1776#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 1776#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1777#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1777#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1778#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1778#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1779 1779
1780/* Registers for function PAD_CONTROL */ 1780/* Registers for function PAD_CONTROL */
1781#define PALMAS_OD_OUTPUT_CTRL2 0x2 1781#define PALMAS_OD_OUTPUT_CTRL2 0x02
1782#define PALMAS_POLARITY_CTRL2 0x3 1782#define PALMAS_POLARITY_CTRL2 0x03
1783#define PALMAS_PU_PD_INPUT_CTRL1 0x4 1783#define PALMAS_PU_PD_INPUT_CTRL1 0x04
1784#define PALMAS_PU_PD_INPUT_CTRL2 0x5 1784#define PALMAS_PU_PD_INPUT_CTRL2 0x05
1785#define PALMAS_PU_PD_INPUT_CTRL3 0x6 1785#define PALMAS_PU_PD_INPUT_CTRL3 0x06
1786#define PALMAS_PU_PD_INPUT_CTRL5 0x7 1786#define PALMAS_PU_PD_INPUT_CTRL5 0x07
1787#define PALMAS_OD_OUTPUT_CTRL 0x8 1787#define PALMAS_OD_OUTPUT_CTRL 0x08
1788#define PALMAS_POLARITY_CTRL 0x9 1788#define PALMAS_POLARITY_CTRL 0x09
1789#define PALMAS_PRIMARY_SECONDARY_PAD1 0xA 1789#define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1790#define PALMAS_PRIMARY_SECONDARY_PAD2 0xB 1790#define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1791#define PALMAS_I2C_SPI 0xC 1791#define PALMAS_I2C_SPI 0x0C
1792#define PALMAS_PU_PD_INPUT_CTRL4 0xD 1792#define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1793#define PALMAS_PRIMARY_SECONDARY_PAD3 0xE 1793#define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1794#define PALMAS_PRIMARY_SECONDARY_PAD4 0xF 1794#define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1795 1795
1796/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1796/* Bit definitions for PU_PD_INPUT_CTRL1 */
1797#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1797#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1798#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 1798#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1799#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1799#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1800#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 1800#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1801#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1801#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1802#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 1802#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1803#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1803#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1804#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 1804#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1805#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1805#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1806#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 1806#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1807 1807
1808/* Bit definitions for PU_PD_INPUT_CTRL2 */ 1808/* Bit definitions for PU_PD_INPUT_CTRL2 */
1809#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1809#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1810#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 1810#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1811#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1811#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1812#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 1812#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1813#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1813#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1814#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 1814#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1815#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1815#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1816#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 1816#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1817#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1817#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1818#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 1818#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1819#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1819#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1820#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 1820#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1821 1821
1822/* Bit definitions for PU_PD_INPUT_CTRL3 */ 1822/* Bit definitions for PU_PD_INPUT_CTRL3 */
1823#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1823#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1824#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 1824#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1825#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1825#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1826#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 1826#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1827#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1827#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1828#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 1828#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1829#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1829#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1830#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 1830#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1831 1831
1832/* Bit definitions for OD_OUTPUT_CTRL */ 1832/* Bit definitions for OD_OUTPUT_CTRL */
1833#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1833#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1834#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 1834#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
1835#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1835#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1836#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 1836#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
1837#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1837#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1838#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 1838#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
1839#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1839#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1840#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 1840#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
1841 1841
1842/* Bit definitions for POLARITY_CTRL */ 1842/* Bit definitions for POLARITY_CTRL */
1843#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1843#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1844#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 1844#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
1845#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1845#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1846#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 1846#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
1847#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1847#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1848#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 1848#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
1849#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1849#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1850#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 1850#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
1851#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1851#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1852#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 1852#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
1853#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1853#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1854#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 1854#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
1855#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1855#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1856#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 1856#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
1857#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1857#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1858#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 1858#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
1859 1859
1860/* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1860/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1861#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1861#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1862#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 1862#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
1863#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1863#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1864#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 1864#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
1865#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1865#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1866#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 1866#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
1867#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1867#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1868#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 1868#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
1869#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1869#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1870#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 1870#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
1871#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 1871#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1872#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 1872#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
1873 1873
1874/* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 1874/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1875#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 1875#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1876#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 1876#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
1877#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 1877#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1878#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 1878#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
1879#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 1879#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1880#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 1880#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
1881#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 1881#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1882#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 1882#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
1883 1883
1884/* Bit definitions for I2C_SPI */ 1884/* Bit definitions for I2C_SPI */
1885#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 1885#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1886#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 1886#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
1887#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 1887#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1888#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 1888#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
1889#define PALMAS_I2C_SPI_ID_I2C2 0x20 1889#define PALMAS_I2C_SPI_ID_I2C2 0x20
1890#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 1890#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
1891#define PALMAS_I2C_SPI_I2C_SPI 0x10 1891#define PALMAS_I2C_SPI_I2C_SPI 0x10
1892#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 1892#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
1893#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f 1893#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
1894#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 1894#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
1895 1895
1896/* Bit definitions for PU_PD_INPUT_CTRL4 */ 1896/* Bit definitions for PU_PD_INPUT_CTRL4 */
1897#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 1897#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1898#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 1898#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
1899#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 1899#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1900#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 1900#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
1901#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 1901#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1902#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 1902#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
1903#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 1903#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1904#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 1904#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
1905 1905
1906/* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 1906/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1907#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 1907#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1908#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 1908#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
1909#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 1909#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1910#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 1910#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
1911 1911
1912/* Registers for function LED_PWM */ 1912/* Registers for function LED_PWM */
1913#define PALMAS_LED_PERIOD_CTRL 0x0 1913#define PALMAS_LED_PERIOD_CTRL 0x00
1914#define PALMAS_LED_CTRL 0x1 1914#define PALMAS_LED_CTRL 0x01
1915#define PALMAS_PWM_CTRL1 0x2 1915#define PALMAS_PWM_CTRL1 0x02
1916#define PALMAS_PWM_CTRL2 0x3 1916#define PALMAS_PWM_CTRL2 0x03
1917 1917
1918/* Bit definitions for LED_PERIOD_CTRL */ 1918/* Bit definitions for LED_PERIOD_CTRL */
1919#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 1919#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1920#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 1920#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
1921#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 1921#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1922#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 1922#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
1923 1923
1924/* Bit definitions for LED_CTRL */ 1924/* Bit definitions for LED_CTRL */
1925#define PALMAS_LED_CTRL_LED_2_SEQ 0x20 1925#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1926#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 1926#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
1927#define PALMAS_LED_CTRL_LED_1_SEQ 0x10 1927#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1928#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 1928#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
1929#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 1929#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1930#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 1930#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
1931#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 1931#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1932#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 1932#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
1933 1933
1934/* Bit definitions for PWM_CTRL1 */ 1934/* Bit definitions for PWM_CTRL1 */
1935#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 1935#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1936#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 1936#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
1937#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 1937#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1938#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 1938#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
1939 1939
1940/* Bit definitions for PWM_CTRL2 */ 1940/* Bit definitions for PWM_CTRL2 */
1941#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff 1941#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
1942#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 1942#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
1943 1943
1944/* Registers for function INTERRUPT */ 1944/* Registers for function INTERRUPT */
1945#define PALMAS_INT1_STATUS 0x0 1945#define PALMAS_INT1_STATUS 0x00
1946#define PALMAS_INT1_MASK 0x1 1946#define PALMAS_INT1_MASK 0x01
1947#define PALMAS_INT1_LINE_STATE 0x2 1947#define PALMAS_INT1_LINE_STATE 0x02
1948#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 1948#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
1949#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 1949#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
1950#define PALMAS_INT2_STATUS 0x5 1950#define PALMAS_INT2_STATUS 0x05
1951#define PALMAS_INT2_MASK 0x6 1951#define PALMAS_INT2_MASK 0x06
1952#define PALMAS_INT2_LINE_STATE 0x7 1952#define PALMAS_INT2_LINE_STATE 0x07
1953#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 1953#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
1954#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 1954#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
1955#define PALMAS_INT3_STATUS 0xA 1955#define PALMAS_INT3_STATUS 0x0A
1956#define PALMAS_INT3_MASK 0xB 1956#define PALMAS_INT3_MASK 0x0B
1957#define PALMAS_INT3_LINE_STATE 0xC 1957#define PALMAS_INT3_LINE_STATE 0x0C
1958#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD 1958#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
1959#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE 1959#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
1960#define PALMAS_INT4_STATUS 0xF 1960#define PALMAS_INT4_STATUS 0x0F
1961#define PALMAS_INT4_MASK 0x10 1961#define PALMAS_INT4_MASK 0x10
1962#define PALMAS_INT4_LINE_STATE 0x11 1962#define PALMAS_INT4_LINE_STATE 0x11
1963#define PALMAS_INT4_EDGE_DETECT1 0x12 1963#define PALMAS_INT4_EDGE_DETECT1 0x12
@@ -1966,276 +1966,276 @@ enum usb_irq_events {
1966 1966
1967/* Bit definitions for INT1_STATUS */ 1967/* Bit definitions for INT1_STATUS */
1968#define PALMAS_INT1_STATUS_VBAT_MON 0x80 1968#define PALMAS_INT1_STATUS_VBAT_MON 0x80
1969#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 1969#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
1970#define PALMAS_INT1_STATUS_VSYS_MON 0x40 1970#define PALMAS_INT1_STATUS_VSYS_MON 0x40
1971#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 1971#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
1972#define PALMAS_INT1_STATUS_HOTDIE 0x20 1972#define PALMAS_INT1_STATUS_HOTDIE 0x20
1973#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 1973#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
1974#define PALMAS_INT1_STATUS_PWRDOWN 0x10 1974#define PALMAS_INT1_STATUS_PWRDOWN 0x10
1975#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 1975#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
1976#define PALMAS_INT1_STATUS_RPWRON 0x08 1976#define PALMAS_INT1_STATUS_RPWRON 0x08
1977#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 1977#define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
1978#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 1978#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1979#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 1979#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
1980#define PALMAS_INT1_STATUS_PWRON 0x02 1980#define PALMAS_INT1_STATUS_PWRON 0x02
1981#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 1981#define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
1982#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 1982#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1983#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 1983#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
1984 1984
1985/* Bit definitions for INT1_MASK */ 1985/* Bit definitions for INT1_MASK */
1986#define PALMAS_INT1_MASK_VBAT_MON 0x80 1986#define PALMAS_INT1_MASK_VBAT_MON 0x80
1987#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 1987#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
1988#define PALMAS_INT1_MASK_VSYS_MON 0x40 1988#define PALMAS_INT1_MASK_VSYS_MON 0x40
1989#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 1989#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
1990#define PALMAS_INT1_MASK_HOTDIE 0x20 1990#define PALMAS_INT1_MASK_HOTDIE 0x20
1991#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 1991#define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
1992#define PALMAS_INT1_MASK_PWRDOWN 0x10 1992#define PALMAS_INT1_MASK_PWRDOWN 0x10
1993#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 1993#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
1994#define PALMAS_INT1_MASK_RPWRON 0x08 1994#define PALMAS_INT1_MASK_RPWRON 0x08
1995#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 1995#define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
1996#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 1996#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1997#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 1997#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
1998#define PALMAS_INT1_MASK_PWRON 0x02 1998#define PALMAS_INT1_MASK_PWRON 0x02
1999#define PALMAS_INT1_MASK_PWRON_SHIFT 1 1999#define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2000#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 2000#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2001#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 2001#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2002 2002
2003/* Bit definitions for INT1_LINE_STATE */ 2003/* Bit definitions for INT1_LINE_STATE */
2004#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 2004#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2005#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 2005#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2006#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 2006#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2007#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 2007#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2008#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 2008#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2009#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 2009#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2010#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 2010#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2011#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 2011#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2012#define PALMAS_INT1_LINE_STATE_RPWRON 0x08 2012#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2013#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 2013#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2014#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 2014#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2015#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 2015#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2016#define PALMAS_INT1_LINE_STATE_PWRON 0x02 2016#define PALMAS_INT1_LINE_STATE_PWRON 0x02
2017#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 2017#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2018#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 2018#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2019#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 2019#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2020 2020
2021/* Bit definitions for INT2_STATUS */ 2021/* Bit definitions for INT2_STATUS */
2022#define PALMAS_INT2_STATUS_VAC_ACOK 0x80 2022#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2023#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 2023#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2024#define PALMAS_INT2_STATUS_SHORT 0x40 2024#define PALMAS_INT2_STATUS_SHORT 0x40
2025#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 2025#define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2026#define PALMAS_INT2_STATUS_FBI_BB 0x20 2026#define PALMAS_INT2_STATUS_FBI_BB 0x20
2027#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 2027#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2028#define PALMAS_INT2_STATUS_RESET_IN 0x10 2028#define PALMAS_INT2_STATUS_RESET_IN 0x10
2029#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 2029#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2030#define PALMAS_INT2_STATUS_BATREMOVAL 0x08 2030#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2031#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 2031#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2032#define PALMAS_INT2_STATUS_WDT 0x04 2032#define PALMAS_INT2_STATUS_WDT 0x04
2033#define PALMAS_INT2_STATUS_WDT_SHIFT 2 2033#define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2034#define PALMAS_INT2_STATUS_RTC_TIMER 0x02 2034#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2035#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 2035#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2036#define PALMAS_INT2_STATUS_RTC_ALARM 0x01 2036#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2037#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 2037#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2038 2038
2039/* Bit definitions for INT2_MASK */ 2039/* Bit definitions for INT2_MASK */
2040#define PALMAS_INT2_MASK_VAC_ACOK 0x80 2040#define PALMAS_INT2_MASK_VAC_ACOK 0x80
2041#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 2041#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2042#define PALMAS_INT2_MASK_SHORT 0x40 2042#define PALMAS_INT2_MASK_SHORT 0x40
2043#define PALMAS_INT2_MASK_SHORT_SHIFT 6 2043#define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2044#define PALMAS_INT2_MASK_FBI_BB 0x20 2044#define PALMAS_INT2_MASK_FBI_BB 0x20
2045#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 2045#define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2046#define PALMAS_INT2_MASK_RESET_IN 0x10 2046#define PALMAS_INT2_MASK_RESET_IN 0x10
2047#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 2047#define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2048#define PALMAS_INT2_MASK_BATREMOVAL 0x08 2048#define PALMAS_INT2_MASK_BATREMOVAL 0x08
2049#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 2049#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2050#define PALMAS_INT2_MASK_WDT 0x04 2050#define PALMAS_INT2_MASK_WDT 0x04
2051#define PALMAS_INT2_MASK_WDT_SHIFT 2 2051#define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2052#define PALMAS_INT2_MASK_RTC_TIMER 0x02 2052#define PALMAS_INT2_MASK_RTC_TIMER 0x02
2053#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 2053#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2054#define PALMAS_INT2_MASK_RTC_ALARM 0x01 2054#define PALMAS_INT2_MASK_RTC_ALARM 0x01
2055#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 2055#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2056 2056
2057/* Bit definitions for INT2_LINE_STATE */ 2057/* Bit definitions for INT2_LINE_STATE */
2058#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 2058#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2059#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 2059#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2060#define PALMAS_INT2_LINE_STATE_SHORT 0x40 2060#define PALMAS_INT2_LINE_STATE_SHORT 0x40
2061#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 2061#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2062#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 2062#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2063#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 2063#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2064#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2064#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2065#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 2065#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2066#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2066#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2067#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 2067#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2068#define PALMAS_INT2_LINE_STATE_WDT 0x04 2068#define PALMAS_INT2_LINE_STATE_WDT 0x04
2069#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 2069#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2070#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2070#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2071#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 2071#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2072#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2072#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2073#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 2073#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2074 2074
2075/* Bit definitions for INT3_STATUS */ 2075/* Bit definitions for INT3_STATUS */
2076#define PALMAS_INT3_STATUS_VBUS 0x80 2076#define PALMAS_INT3_STATUS_VBUS 0x80
2077#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 2077#define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2078#define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2078#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2079#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 2079#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2080#define PALMAS_INT3_STATUS_ID 0x20 2080#define PALMAS_INT3_STATUS_ID 0x20
2081#define PALMAS_INT3_STATUS_ID_SHIFT 5 2081#define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2082#define PALMAS_INT3_STATUS_ID_OTG 0x10 2082#define PALMAS_INT3_STATUS_ID_OTG 0x10
2083#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 2083#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2084#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2084#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2085#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 2085#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2086#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2086#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2087#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 2087#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2088#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2088#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2089#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 2089#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2090#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2090#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2091#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 2091#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2092 2092
2093/* Bit definitions for INT3_MASK */ 2093/* Bit definitions for INT3_MASK */
2094#define PALMAS_INT3_MASK_VBUS 0x80 2094#define PALMAS_INT3_MASK_VBUS 0x80
2095#define PALMAS_INT3_MASK_VBUS_SHIFT 7 2095#define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2096#define PALMAS_INT3_MASK_VBUS_OTG 0x40 2096#define PALMAS_INT3_MASK_VBUS_OTG 0x40
2097#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 2097#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2098#define PALMAS_INT3_MASK_ID 0x20 2098#define PALMAS_INT3_MASK_ID 0x20
2099#define PALMAS_INT3_MASK_ID_SHIFT 5 2099#define PALMAS_INT3_MASK_ID_SHIFT 0x05
2100#define PALMAS_INT3_MASK_ID_OTG 0x10 2100#define PALMAS_INT3_MASK_ID_OTG 0x10
2101#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 2101#define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2102#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2102#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2103#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 2103#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2104#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2104#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2105#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 2105#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2106#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2106#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2107#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 2107#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2108#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2108#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2109#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 2109#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2110 2110
2111/* Bit definitions for INT3_LINE_STATE */ 2111/* Bit definitions for INT3_LINE_STATE */
2112#define PALMAS_INT3_LINE_STATE_VBUS 0x80 2112#define PALMAS_INT3_LINE_STATE_VBUS 0x80
2113#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 2113#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2114#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2114#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2115#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 2115#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2116#define PALMAS_INT3_LINE_STATE_ID 0x20 2116#define PALMAS_INT3_LINE_STATE_ID 0x20
2117#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 2117#define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2118#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2118#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2119#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 2119#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2120#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2120#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2121#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 2121#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2122#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2122#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2123#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 2123#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2124#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2124#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2125#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 2125#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2126#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2126#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2127#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 2127#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2128 2128
2129/* Bit definitions for INT4_STATUS */ 2129/* Bit definitions for INT4_STATUS */
2130#define PALMAS_INT4_STATUS_GPIO_7 0x80 2130#define PALMAS_INT4_STATUS_GPIO_7 0x80
2131#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 2131#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2132#define PALMAS_INT4_STATUS_GPIO_6 0x40 2132#define PALMAS_INT4_STATUS_GPIO_6 0x40
2133#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 2133#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2134#define PALMAS_INT4_STATUS_GPIO_5 0x20 2134#define PALMAS_INT4_STATUS_GPIO_5 0x20
2135#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 2135#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2136#define PALMAS_INT4_STATUS_GPIO_4 0x10 2136#define PALMAS_INT4_STATUS_GPIO_4 0x10
2137#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 2137#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2138#define PALMAS_INT4_STATUS_GPIO_3 0x08 2138#define PALMAS_INT4_STATUS_GPIO_3 0x08
2139#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 2139#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2140#define PALMAS_INT4_STATUS_GPIO_2 0x04 2140#define PALMAS_INT4_STATUS_GPIO_2 0x04
2141#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 2141#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2142#define PALMAS_INT4_STATUS_GPIO_1 0x02 2142#define PALMAS_INT4_STATUS_GPIO_1 0x02
2143#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 2143#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2144#define PALMAS_INT4_STATUS_GPIO_0 0x01 2144#define PALMAS_INT4_STATUS_GPIO_0 0x01
2145#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 2145#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2146 2146
2147/* Bit definitions for INT4_MASK */ 2147/* Bit definitions for INT4_MASK */
2148#define PALMAS_INT4_MASK_GPIO_7 0x80 2148#define PALMAS_INT4_MASK_GPIO_7 0x80
2149#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 2149#define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2150#define PALMAS_INT4_MASK_GPIO_6 0x40 2150#define PALMAS_INT4_MASK_GPIO_6 0x40
2151#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 2151#define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2152#define PALMAS_INT4_MASK_GPIO_5 0x20 2152#define PALMAS_INT4_MASK_GPIO_5 0x20
2153#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 2153#define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2154#define PALMAS_INT4_MASK_GPIO_4 0x10 2154#define PALMAS_INT4_MASK_GPIO_4 0x10
2155#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 2155#define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2156#define PALMAS_INT4_MASK_GPIO_3 0x08 2156#define PALMAS_INT4_MASK_GPIO_3 0x08
2157#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 2157#define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2158#define PALMAS_INT4_MASK_GPIO_2 0x04 2158#define PALMAS_INT4_MASK_GPIO_2 0x04
2159#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 2159#define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2160#define PALMAS_INT4_MASK_GPIO_1 0x02 2160#define PALMAS_INT4_MASK_GPIO_1 0x02
2161#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 2161#define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2162#define PALMAS_INT4_MASK_GPIO_0 0x01 2162#define PALMAS_INT4_MASK_GPIO_0 0x01
2163#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 2163#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2164 2164
2165/* Bit definitions for INT4_LINE_STATE */ 2165/* Bit definitions for INT4_LINE_STATE */
2166#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2166#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2167#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 2167#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2168#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2168#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2169#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 2169#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2170#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2170#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2171#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 2171#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2172#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2172#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2173#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 2173#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2174#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2174#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2175#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 2175#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2176#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2176#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2177#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 2177#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2178#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2178#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2179#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 2179#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2180#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2180#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2181#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 2181#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2182 2182
2183/* Bit definitions for INT4_EDGE_DETECT1 */ 2183/* Bit definitions for INT4_EDGE_DETECT1 */
2184#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2184#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2185#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 2185#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2186#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2186#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2187#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 2187#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2188#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2188#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2189#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 2189#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2190#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2190#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2191#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 2191#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2192#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2192#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2193#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 2193#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2194#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2194#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2195#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 2195#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2196#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2196#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2197#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 2197#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2198#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2198#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2199#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 2199#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2200 2200
2201/* Bit definitions for INT4_EDGE_DETECT2 */ 2201/* Bit definitions for INT4_EDGE_DETECT2 */
2202#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2202#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2203#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 2203#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2204#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2204#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2205#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 2205#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2206#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2206#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2207#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 2207#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2208#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2208#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2209#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 2209#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2210#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2210#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2211#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 2211#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2212#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2212#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2213#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 2213#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2214#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2214#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2215#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 2215#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2216#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2216#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2217#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 2217#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2218 2218
2219/* Bit definitions for INT_CTRL */ 2219/* Bit definitions for INT_CTRL */
2220#define PALMAS_INT_CTRL_INT_PENDING 0x04 2220#define PALMAS_INT_CTRL_INT_PENDING 0x04
2221#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 2221#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2222#define PALMAS_INT_CTRL_INT_CLEAR 0x01 2222#define PALMAS_INT_CTRL_INT_CLEAR 0x01
2223#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 2223#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2224 2224
2225/* Registers for function USB_OTG */ 2225/* Registers for function USB_OTG */
2226#define PALMAS_USB_WAKEUP 0x3 2226#define PALMAS_USB_WAKEUP 0x03
2227#define PALMAS_USB_VBUS_CTRL_SET 0x4 2227#define PALMAS_USB_VBUS_CTRL_SET 0x04
2228#define PALMAS_USB_VBUS_CTRL_CLR 0x5 2228#define PALMAS_USB_VBUS_CTRL_CLR 0x05
2229#define PALMAS_USB_ID_CTRL_SET 0x6 2229#define PALMAS_USB_ID_CTRL_SET 0x06
2230#define PALMAS_USB_ID_CTRL_CLEAR 0x7 2230#define PALMAS_USB_ID_CTRL_CLEAR 0x07
2231#define PALMAS_USB_VBUS_INT_SRC 0x8 2231#define PALMAS_USB_VBUS_INT_SRC 0x08
2232#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 2232#define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2233#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA 2233#define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2234#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB 2234#define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2235#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC 2235#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2236#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD 2236#define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2237#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE 2237#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2238#define PALMAS_USB_ID_INT_SRC 0xF 2238#define PALMAS_USB_ID_INT_SRC 0x0F
2239#define PALMAS_USB_ID_INT_LATCH_SET 0x10 2239#define PALMAS_USB_ID_INT_LATCH_SET 0x10
2240#define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2240#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2241#define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2241#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
@@ -2250,306 +2250,306 @@ enum usb_irq_events {
2250 2250
2251/* Bit definitions for USB_WAKEUP */ 2251/* Bit definitions for USB_WAKEUP */
2252#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2252#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2253#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 2253#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2254 2254
2255/* Bit definitions for USB_VBUS_CTRL_SET */ 2255/* Bit definitions for USB_VBUS_CTRL_SET */
2256#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2256#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2257#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 2257#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2258#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2258#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2259#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 2259#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2260#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2260#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2261#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 2261#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2262#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2262#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2263#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 2263#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2264#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2264#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2265#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 2265#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2266 2266
2267/* Bit definitions for USB_VBUS_CTRL_CLR */ 2267/* Bit definitions for USB_VBUS_CTRL_CLR */
2268#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2268#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2269#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 2269#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2270#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2270#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2271#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 2271#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2272#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2272#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2273#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 2273#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2274#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2274#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2275#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 2275#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2276#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2276#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2277#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 2277#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2278 2278
2279/* Bit definitions for USB_ID_CTRL_SET */ 2279/* Bit definitions for USB_ID_CTRL_SET */
2280#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2280#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2281#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 2281#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2282#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2282#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2283#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 2283#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2284#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2284#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2285#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 2285#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2286#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2286#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2287#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 2287#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2288#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2288#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2289#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 2289#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2290#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2290#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2291#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 2291#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2292 2292
2293/* Bit definitions for USB_ID_CTRL_CLEAR */ 2293/* Bit definitions for USB_ID_CTRL_CLEAR */
2294#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2294#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2295#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 2295#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2296#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2296#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2297#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 2297#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2298#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2298#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2299#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 2299#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2300#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2300#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2301#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 2301#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2302#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2302#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2303#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 2303#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2304#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2304#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2305#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 2305#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2306 2306
2307/* Bit definitions for USB_VBUS_INT_SRC */ 2307/* Bit definitions for USB_VBUS_INT_SRC */
2308#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2308#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2309#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 2309#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2310#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2310#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2311#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 2311#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2312#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2312#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2313#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 2313#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2314#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2314#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2315#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 2315#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2316#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2316#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2317#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 2317#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2318#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2318#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2319#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 2319#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2320#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2320#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2321#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 2321#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2322 2322
2323/* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2323/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2324#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2324#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2325#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 2325#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2326#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2326#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2327#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 2327#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2328#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2328#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2329#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 2329#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2330#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2330#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2331#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 2331#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2332#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2332#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2333#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 2333#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2334#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2334#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2335#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 2335#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2336#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2336#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2337#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 2337#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2338#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2338#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2339#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 2339#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2340 2340
2341/* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2341/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2342#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2342#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2343#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 2343#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2344#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2344#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2345#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 2345#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2346#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2346#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2347#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 2347#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2348#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2348#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2349#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 2349#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2350#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2350#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2351#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 2351#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2352#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2352#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2353#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 2353#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2354#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2354#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2355#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 2355#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2356#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2356#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2357#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 2357#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2358 2358
2359/* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2359/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2360#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2360#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2361#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 2361#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2362#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2362#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2363#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 2363#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2364#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2364#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2365#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 2365#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2366#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2366#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2367#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 2367#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2368#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2368#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2369#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 2369#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2370#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2370#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2371#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 2371#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2372#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2372#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2373#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 2373#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2374 2374
2375/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2375/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2376#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2376#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2377#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 2377#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2378#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2378#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2379#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 2379#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2380#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2380#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2381#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 2381#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2382#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2382#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2383#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 2383#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2384#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2384#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2385#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 2385#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2386#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2386#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2387#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 2387#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2388#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2388#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2389#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 2389#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2390 2390
2391/* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2391/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2392#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2392#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2393#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 2393#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2394#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2394#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2395#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 2395#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2396#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2396#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2397#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 2397#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2398#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2398#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2399#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 2399#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2400#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2400#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2401#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 2401#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2402#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2402#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2403#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 2403#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2404#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2404#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2405#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 2405#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2406#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2406#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2407#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 2407#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2408 2408
2409/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2409/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2410#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2410#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2411#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 2411#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2412#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2412#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2413#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 2413#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2414#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2414#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2415#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 2415#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2416#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2416#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2417#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 2417#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2418#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2418#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2419#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 2419#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2420#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2420#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2421#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 2421#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2422#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2422#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2423#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 2423#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2424#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2424#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2425#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 2425#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2426 2426
2427/* Bit definitions for USB_ID_INT_SRC */ 2427/* Bit definitions for USB_ID_INT_SRC */
2428#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2428#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2429#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 2429#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2430#define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2430#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2431#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 2431#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2432#define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2432#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2433#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 2433#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2434#define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2434#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2435#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 2435#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2436#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2436#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2437#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 2437#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2438 2438
2439/* Bit definitions for USB_ID_INT_LATCH_SET */ 2439/* Bit definitions for USB_ID_INT_LATCH_SET */
2440#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2440#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2441#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 2441#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2442#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2442#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2443#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 2443#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2444#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2444#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2445#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 2445#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2446#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2446#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2447#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 2447#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2448#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2448#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2449#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 2449#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2450 2450
2451/* Bit definitions for USB_ID_INT_LATCH_CLR */ 2451/* Bit definitions for USB_ID_INT_LATCH_CLR */
2452#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2452#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2453#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 2453#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2454#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2454#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2455#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 2455#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2456#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2456#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2457#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 2457#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2458#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2458#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2459#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 2459#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2460#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2460#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2461#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 2461#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2462 2462
2463/* Bit definitions for USB_ID_INT_EN_LO_SET */ 2463/* Bit definitions for USB_ID_INT_EN_LO_SET */
2464#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2464#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2465#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 2465#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2466#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2466#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2467#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 2467#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2468#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2468#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2469#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 2469#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2470#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2470#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2471#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 2471#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2472#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2472#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2473#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 2473#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2474 2474
2475/* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2475/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2476#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2476#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2477#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 2477#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2478#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2478#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2479#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 2479#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2480#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2480#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2481#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 2481#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2482#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2482#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2483#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 2483#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2484#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2484#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2485#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 2485#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2486 2486
2487/* Bit definitions for USB_ID_INT_EN_HI_SET */ 2487/* Bit definitions for USB_ID_INT_EN_HI_SET */
2488#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2488#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2489#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 2489#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2490#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2490#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2491#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 2491#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2492#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2492#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2493#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 2493#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2494#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2494#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2495#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 2495#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2496#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2496#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2497#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 2497#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2498 2498
2499/* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2499/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2500#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2500#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2501#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 2501#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2502#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2502#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2503#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 2503#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2504#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2504#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2505#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 2505#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2506#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2506#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2507#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 2507#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2508#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2508#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2509#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 2509#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2510 2510
2511/* Bit definitions for USB_OTG_ADP_CTRL */ 2511/* Bit definitions for USB_OTG_ADP_CTRL */
2512#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2512#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2513#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 2513#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2514#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2514#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2515#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 2515#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2516 2516
2517/* Bit definitions for USB_OTG_ADP_HIGH */ 2517/* Bit definitions for USB_OTG_ADP_HIGH */
2518#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff 2518#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2519#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 2519#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2520 2520
2521/* Bit definitions for USB_OTG_ADP_LOW */ 2521/* Bit definitions for USB_OTG_ADP_LOW */
2522#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff 2522#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2523#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 2523#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2524 2524
2525/* Bit definitions for USB_OTG_ADP_RISE */ 2525/* Bit definitions for USB_OTG_ADP_RISE */
2526#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff 2526#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2527#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 2527#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2528 2528
2529/* Bit definitions for USB_OTG_REVISION */ 2529/* Bit definitions for USB_OTG_REVISION */
2530#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2530#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2531#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 2531#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2532 2532
2533/* Registers for function VIBRATOR */ 2533/* Registers for function VIBRATOR */
2534#define PALMAS_VIBRA_CTRL 0x0 2534#define PALMAS_VIBRA_CTRL 0x00
2535 2535
2536/* Bit definitions for VIBRA_CTRL */ 2536/* Bit definitions for VIBRA_CTRL */
2537#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2537#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2538#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 2538#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2539#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2539#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2540#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 2540#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2541 2541
2542/* Registers for function GPIO */ 2542/* Registers for function GPIO */
2543#define PALMAS_GPIO_DATA_IN 0x0 2543#define PALMAS_GPIO_DATA_IN 0x00
2544#define PALMAS_GPIO_DATA_DIR 0x1 2544#define PALMAS_GPIO_DATA_DIR 0x01
2545#define PALMAS_GPIO_DATA_OUT 0x2 2545#define PALMAS_GPIO_DATA_OUT 0x02
2546#define PALMAS_GPIO_DEBOUNCE_EN 0x3 2546#define PALMAS_GPIO_DEBOUNCE_EN 0x03
2547#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 2547#define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2548#define PALMAS_GPIO_SET_DATA_OUT 0x5 2548#define PALMAS_GPIO_SET_DATA_OUT 0x05
2549#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2549#define PALMAS_PU_PD_GPIO_CTRL1 0x06
2550#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2550#define PALMAS_PU_PD_GPIO_CTRL2 0x07
2551#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2551#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2552#define PALMAS_GPIO_DATA_IN2 0x9 2552#define PALMAS_GPIO_DATA_IN2 0x09
2553#define PALMAS_GPIO_DATA_DIR2 0x0A 2553#define PALMAS_GPIO_DATA_DIR2 0x0A
2554#define PALMAS_GPIO_DATA_OUT2 0x0B 2554#define PALMAS_GPIO_DATA_OUT2 0x0B
2555#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C 2555#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
@@ -2561,167 +2561,167 @@ enum usb_irq_events {
2561 2561
2562/* Bit definitions for GPIO_DATA_IN */ 2562/* Bit definitions for GPIO_DATA_IN */
2563#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2563#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2564#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 2564#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2565#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2565#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2566#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 2566#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2567#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2567#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2568#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 2568#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2569#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2569#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2570#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 2570#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2571#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2571#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2572#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 2572#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2573#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2573#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2574#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 2574#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2575#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2575#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2576#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 2576#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2577#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2577#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2578#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 2578#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2579 2579
2580/* Bit definitions for GPIO_DATA_DIR */ 2580/* Bit definitions for GPIO_DATA_DIR */
2581#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2581#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2582#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 2582#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2583#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2583#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2584#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 2584#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2585#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2585#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2586#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 2586#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2587#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2587#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2588#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 2588#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2589#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2589#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2590#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 2590#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2591#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2591#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2592#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 2592#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2593#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2593#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2594#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 2594#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2595#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2595#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2596#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 2596#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2597 2597
2598/* Bit definitions for GPIO_DATA_OUT */ 2598/* Bit definitions for GPIO_DATA_OUT */
2599#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2599#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2600#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 2600#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2601#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2601#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2602#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 2602#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2603#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2603#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2604#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 2604#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2605#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2605#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2606#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 2606#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2607#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2607#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2608#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 2608#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2609#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2609#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2610#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 2610#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2611#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2611#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2612#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 2612#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2613#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2613#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2614#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 2614#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2615 2615
2616/* Bit definitions for GPIO_DEBOUNCE_EN */ 2616/* Bit definitions for GPIO_DEBOUNCE_EN */
2617#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2617#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2618#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 2618#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2619#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2619#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2620#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 2620#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2621#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2621#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2622#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 2622#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2623#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2623#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2624#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 2624#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2625#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2625#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2626#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 2626#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2627#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2627#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2628#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 2628#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2629#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2629#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2630#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 2630#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2631#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2631#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2632#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 2632#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2633 2633
2634/* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2634/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2635#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2635#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2636#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 2636#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2637#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2637#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2638#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 2638#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2639#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2639#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2640#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 2640#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2641#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2641#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2642#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 2642#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2643#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2643#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2644#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 2644#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2645#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2645#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2646#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 2646#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2647#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2647#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2648#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 2648#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2649#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2649#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2650#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 2650#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2651 2651
2652/* Bit definitions for GPIO_SET_DATA_OUT */ 2652/* Bit definitions for GPIO_SET_DATA_OUT */
2653#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2653#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2654#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 2654#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2655#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2655#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2656#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 2656#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2657#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2657#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2658#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 2658#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2659#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2659#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2660#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 2660#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2661#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2661#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2662#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 2662#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2663#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2663#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2664#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 2664#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2665#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2665#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2666#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 2666#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2667#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2667#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2668#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 2668#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2669 2669
2670/* Bit definitions for PU_PD_GPIO_CTRL1 */ 2670/* Bit definitions for PU_PD_GPIO_CTRL1 */
2671#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2671#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2672#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 2672#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2673#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2673#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2674#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 2674#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2675#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2675#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2676#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 2676#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2677#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2677#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2678#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 2678#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2679#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2679#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2680#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 2680#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2681#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2681#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2682#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 2682#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2683 2683
2684/* Bit definitions for PU_PD_GPIO_CTRL2 */ 2684/* Bit definitions for PU_PD_GPIO_CTRL2 */
2685#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2685#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2686#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 2686#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2687#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2687#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2688#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 2688#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2689#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2689#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2690#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 2690#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2691#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2691#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2692#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 2692#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2693#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2693#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2694#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 2694#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2695#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2695#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2696#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 2696#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2697#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2697#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2698#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 2698#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2699 2699
2700/* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2700/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2701#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2701#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2702#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 2702#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2703#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2703#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2704#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 2704#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2705#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2705#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2706#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 2706#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2707 2707
2708/* Registers for function GPADC */ 2708/* Registers for function GPADC */
2709#define PALMAS_GPADC_CTRL1 0x0 2709#define PALMAS_GPADC_CTRL1 0x00
2710#define PALMAS_GPADC_CTRL2 0x1 2710#define PALMAS_GPADC_CTRL2 0x01
2711#define PALMAS_GPADC_RT_CTRL 0x2 2711#define PALMAS_GPADC_RT_CTRL 0x02
2712#define PALMAS_GPADC_AUTO_CTRL 0x3 2712#define PALMAS_GPADC_AUTO_CTRL 0x03
2713#define PALMAS_GPADC_STATUS 0x4 2713#define PALMAS_GPADC_STATUS 0x04
2714#define PALMAS_GPADC_RT_SELECT 0x5 2714#define PALMAS_GPADC_RT_SELECT 0x05
2715#define PALMAS_GPADC_RT_CONV0_LSB 0x6 2715#define PALMAS_GPADC_RT_CONV0_LSB 0x06
2716#define PALMAS_GPADC_RT_CONV0_MSB 0x7 2716#define PALMAS_GPADC_RT_CONV0_MSB 0x07
2717#define PALMAS_GPADC_AUTO_SELECT 0x8 2717#define PALMAS_GPADC_AUTO_SELECT 0x08
2718#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 2718#define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2719#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA 2719#define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2720#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB 2720#define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2721#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC 2721#define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2722#define PALMAS_GPADC_SW_SELECT 0xD 2722#define PALMAS_GPADC_SW_SELECT 0x0D
2723#define PALMAS_GPADC_SW_CONV0_LSB 0xE 2723#define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2724#define PALMAS_GPADC_SW_CONV0_MSB 0xF 2724#define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2725#define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2725#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2726#define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2726#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2727#define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2727#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
@@ -2731,150 +2731,150 @@ enum usb_irq_events {
2731 2731
2732/* Bit definitions for GPADC_CTRL1 */ 2732/* Bit definitions for GPADC_CTRL1 */
2733#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2733#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2734#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 2734#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2735#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2735#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2736#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 2736#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2737#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2737#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2738#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 2738#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2739#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2739#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2740#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 2740#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2741#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2741#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2742#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 2742#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2743 2743
2744/* Bit definitions for GPADC_CTRL2 */ 2744/* Bit definitions for GPADC_CTRL2 */
2745#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2745#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2746#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 2746#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2747 2747
2748/* Bit definitions for GPADC_RT_CTRL */ 2748/* Bit definitions for GPADC_RT_CTRL */
2749#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2749#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2750#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 2750#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2751#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2751#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2752#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 2752#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2753 2753
2754/* Bit definitions for GPADC_AUTO_CTRL */ 2754/* Bit definitions for GPADC_AUTO_CTRL */
2755#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2755#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2756#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 2756#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2757#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2757#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2758#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 2758#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2759#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2759#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2760#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 2760#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2761#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2761#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2762#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 2762#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2763#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f 2763#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2764#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 2764#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2765 2765
2766/* Bit definitions for GPADC_STATUS */ 2766/* Bit definitions for GPADC_STATUS */
2767#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2767#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2768#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 2768#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2769 2769
2770/* Bit definitions for GPADC_RT_SELECT */ 2770/* Bit definitions for GPADC_RT_SELECT */
2771#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2771#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2772#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 2772#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2773#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f 2773#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2774#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 2774#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2775 2775
2776/* Bit definitions for GPADC_RT_CONV0_LSB */ 2776/* Bit definitions for GPADC_RT_CONV0_LSB */
2777#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff 2777#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2778#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 2778#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2779 2779
2780/* Bit definitions for GPADC_RT_CONV0_MSB */ 2780/* Bit definitions for GPADC_RT_CONV0_MSB */
2781#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f 2781#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2782#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 2782#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2783 2783
2784/* Bit definitions for GPADC_AUTO_SELECT */ 2784/* Bit definitions for GPADC_AUTO_SELECT */
2785#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 2785#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2786#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 2786#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2787#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f 2787#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2788#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 2788#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2789 2789
2790/* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2790/* Bit definitions for GPADC_AUTO_CONV0_LSB */
2791#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff 2791#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2792#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 2792#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2793 2793
2794/* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2794/* Bit definitions for GPADC_AUTO_CONV0_MSB */
2795#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f 2795#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2796#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 2796#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2797 2797
2798/* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2798/* Bit definitions for GPADC_AUTO_CONV1_LSB */
2799#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff 2799#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2800#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 2800#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2801 2801
2802/* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2802/* Bit definitions for GPADC_AUTO_CONV1_MSB */
2803#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f 2803#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2804#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 2804#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2805 2805
2806/* Bit definitions for GPADC_SW_SELECT */ 2806/* Bit definitions for GPADC_SW_SELECT */
2807#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2807#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2808#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 2808#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2809#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2809#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2810#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 2810#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2811#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f 2811#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2812#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 2812#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2813 2813
2814/* Bit definitions for GPADC_SW_CONV0_LSB */ 2814/* Bit definitions for GPADC_SW_CONV0_LSB */
2815#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff 2815#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2816#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 2816#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2817 2817
2818/* Bit definitions for GPADC_SW_CONV0_MSB */ 2818/* Bit definitions for GPADC_SW_CONV0_MSB */
2819#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f 2819#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2820#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 2820#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2821 2821
2822/* Bit definitions for GPADC_THRES_CONV0_LSB */ 2822/* Bit definitions for GPADC_THRES_CONV0_LSB */
2823#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff 2823#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2824#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 2824#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2825 2825
2826/* Bit definitions for GPADC_THRES_CONV0_MSB */ 2826/* Bit definitions for GPADC_THRES_CONV0_MSB */
2827#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2827#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2828#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 2828#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2829#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f 2829#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2830#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 2830#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2831 2831
2832/* Bit definitions for GPADC_THRES_CONV1_LSB */ 2832/* Bit definitions for GPADC_THRES_CONV1_LSB */
2833#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff 2833#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2834#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 2834#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2835 2835
2836/* Bit definitions for GPADC_THRES_CONV1_MSB */ 2836/* Bit definitions for GPADC_THRES_CONV1_MSB */
2837#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2837#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2838#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 2838#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2839#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f 2839#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2840#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 2840#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2841 2841
2842/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2842/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2843#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2843#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2844#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 2844#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2845#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2845#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2846#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 2846#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
2847#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f 2847#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
2848#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 2848#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
2849 2849
2850/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2850/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2851#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2851#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2852#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 2852#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
2853#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f 2853#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
2854#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 2854#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
2855 2855
2856/* Registers for function GPADC */ 2856/* Registers for function GPADC */
2857#define PALMAS_GPADC_TRIM1 0x0 2857#define PALMAS_GPADC_TRIM1 0x00
2858#define PALMAS_GPADC_TRIM2 0x1 2858#define PALMAS_GPADC_TRIM2 0x01
2859#define PALMAS_GPADC_TRIM3 0x2 2859#define PALMAS_GPADC_TRIM3 0x02
2860#define PALMAS_GPADC_TRIM4 0x3 2860#define PALMAS_GPADC_TRIM4 0x03
2861#define PALMAS_GPADC_TRIM5 0x4 2861#define PALMAS_GPADC_TRIM5 0x04
2862#define PALMAS_GPADC_TRIM6 0x5 2862#define PALMAS_GPADC_TRIM6 0x05
2863#define PALMAS_GPADC_TRIM7 0x6 2863#define PALMAS_GPADC_TRIM7 0x06
2864#define PALMAS_GPADC_TRIM8 0x7 2864#define PALMAS_GPADC_TRIM8 0x07
2865#define PALMAS_GPADC_TRIM9 0x8 2865#define PALMAS_GPADC_TRIM9 0x08
2866#define PALMAS_GPADC_TRIM10 0x9 2866#define PALMAS_GPADC_TRIM10 0x09
2867#define PALMAS_GPADC_TRIM11 0xA 2867#define PALMAS_GPADC_TRIM11 0x0A
2868#define PALMAS_GPADC_TRIM12 0xB 2868#define PALMAS_GPADC_TRIM12 0x0B
2869#define PALMAS_GPADC_TRIM13 0xC 2869#define PALMAS_GPADC_TRIM13 0x0C
2870#define PALMAS_GPADC_TRIM14 0xD 2870#define PALMAS_GPADC_TRIM14 0x0D
2871#define PALMAS_GPADC_TRIM15 0xE 2871#define PALMAS_GPADC_TRIM15 0x0E
2872#define PALMAS_GPADC_TRIM16 0xF 2872#define PALMAS_GPADC_TRIM16 0x0F
2873 2873
2874static inline int palmas_read(struct palmas *palmas, unsigned int base, 2874static inline int palmas_read(struct palmas *palmas, unsigned int base,
2875 unsigned int reg, unsigned int *val) 2875 unsigned int reg, unsigned int *val)
2876{ 2876{
2877 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 2877 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2878 int slave_id = PALMAS_BASE_TO_SLAVE(base); 2878 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2879 2879
2880 return regmap_read(palmas->regmap[slave_id], addr, val); 2880 return regmap_read(palmas->regmap[slave_id], addr, val);
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
deleted file mode 100644
index bd2f4f64e931..000000000000
--- a/include/linux/mfd/pm8xxx/core.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/*
14 * Qualcomm PMIC 8xxx driver header file
15 *
16 */
17
18#ifndef __MFD_PM8XXX_CORE_H
19#define __MFD_PM8XXX_CORE_H
20
21#include <linux/mfd/core.h>
22
23struct pm8xxx_drvdata {
24 int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
25 int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
26 int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
27 int n);
28 int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
29 int n);
30 int (*pmic_read_irq_stat) (const struct device *dev, int irq);
31 void *pm_chip_data;
32};
33
34static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
35{
36 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
37
38 if (!dd)
39 return -EINVAL;
40 return dd->pmic_readb(dev, addr, val);
41}
42
43static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
44{
45 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
46
47 if (!dd)
48 return -EINVAL;
49 return dd->pmic_writeb(dev, addr, val);
50}
51
52static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
53 int n)
54{
55 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
56
57 if (!dd)
58 return -EINVAL;
59 return dd->pmic_read_buf(dev, addr, buf, n);
60}
61
62static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
63 int n)
64{
65 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
66
67 if (!dd)
68 return -EINVAL;
69 return dd->pmic_write_buf(dev, addr, buf, n);
70}
71
72static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
73{
74 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
75
76 if (!dd)
77 return -EINVAL;
78 return dd->pmic_read_irq_stat(dev, irq);
79}
80
81#endif
diff --git a/include/linux/mfd/rdc321x.h b/include/linux/mfd/rdc321x.h
index 4bdf19c8eedf..442743a8f915 100644
--- a/include/linux/mfd/rdc321x.h
+++ b/include/linux/mfd/rdc321x.h
@@ -12,7 +12,7 @@
12#define RDC321X_GPIO_CTRL_REG2 0x84 12#define RDC321X_GPIO_CTRL_REG2 0x84
13#define RDC321X_GPIO_DATA_REG2 0x88 13#define RDC321X_GPIO_DATA_REG2 0x88
14 14
15#define RDC321X_MAX_GPIO 58 15#define RDC321X_NUM_GPIO 59
16 16
17struct rdc321x_gpio_pdata { 17struct rdc321x_gpio_pdata {
18 struct pci_dev *sb_pdev; 18 struct pci_dev *sb_pdev;
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
index 157e32b6ca28..47d84242940b 100644
--- a/include/linux/mfd/samsung/core.h
+++ b/include/linux/mfd/samsung/core.h
@@ -24,35 +24,36 @@ enum sec_device_type {
24}; 24};
25 25
26/** 26/**
27 * struct sec_pmic_dev - s5m87xx master device for sub-drivers 27 * struct sec_pmic_dev - s2m/s5m master device for sub-drivers
28 * @dev: master device of the chip (can be used to access platform data) 28 * @dev: Master device of the chip
29 * @pdata: pointer to private data used to pass platform data to child 29 * @pdata: Platform data populated with data from DTS
30 * @i2c: i2c client private data for regulator 30 * or board files
31 * @rtc: i2c client private data for rtc 31 * @regmap_pmic: Regmap associated with PMIC's I2C address
32 * @iolock: mutex for serializing io access 32 * @i2c: I2C client of the main driver
33 * @irqlock: mutex for buslock 33 * @device_type: Type of device, matches enum sec_device_type
34 * @irq_base: base IRQ number for sec-pmic, required for IRQs 34 * @irq_base: Base IRQ number for device, required for IRQs
35 * @irq: generic IRQ number for s5m87xx 35 * @irq: Generic IRQ number for device
36 * @ono: power onoff IRQ number for s5m87xx 36 * @irq_data: Runtime data structure for IRQ controller
37 * @irq_masks_cur: currently active value 37 * @ono: Power onoff IRQ number for s5m87xx
38 * @irq_masks_cache: cached hardware value 38 * @wakeup: Whether or not this is a wakeup device
39 * @type: indicate which s5m87xx "variant" is used 39 * @wtsr_smpl: Whether or not to enable in RTC driver the Watchdog
40 * Timer Software Reset (registers set to default value
41 * after PWRHOLD falling) and Sudden Momentary Power Loss
42 * (PMIC will enter power on sequence after short drop in
43 * VBATT voltage).
40 */ 44 */
41struct sec_pmic_dev { 45struct sec_pmic_dev {
42 struct device *dev; 46 struct device *dev;
43 struct sec_platform_data *pdata; 47 struct sec_platform_data *pdata;
44 struct regmap *regmap_pmic; 48 struct regmap *regmap_pmic;
45 struct regmap *regmap_rtc;
46 struct i2c_client *i2c; 49 struct i2c_client *i2c;
47 struct i2c_client *rtc;
48 50
49 int device_type; 51 unsigned long device_type;
50 int irq_base; 52 int irq_base;
51 int irq; 53 int irq;
52 struct regmap_irq_chip_data *irq_data; 54 struct regmap_irq_chip_data *irq_data;
53 55
54 int ono; 56 int ono;
55 unsigned long type;
56 bool wakeup; 57 bool wakeup;
57 bool wtsr_smpl; 58 bool wtsr_smpl;
58}; 59};
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index 48395a69a7e9..575a86c7fcbd 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -11,6 +11,7 @@
11#include <linux/mutex.h> 11#include <linux/mutex.h>
12 12
13struct device; 13struct device;
14struct regulator;
14 15
15enum stmpe_block { 16enum stmpe_block {
16 STMPE_BLOCK_GPIO = 1 << 0, 17 STMPE_BLOCK_GPIO = 1 << 0,
@@ -62,6 +63,8 @@ struct stmpe_client_info;
62 63
63/** 64/**
64 * struct stmpe - STMPE MFD structure 65 * struct stmpe - STMPE MFD structure
66 * @vcc: optional VCC regulator
67 * @vio: optional VIO regulator
65 * @lock: lock protecting I/O operations 68 * @lock: lock protecting I/O operations
66 * @irq_lock: IRQ bus lock 69 * @irq_lock: IRQ bus lock
67 * @dev: device, mostly for dev_dbg() 70 * @dev: device, mostly for dev_dbg()
@@ -73,13 +76,14 @@ struct stmpe_client_info;
73 * @regs: list of addresses of registers which are at different addresses on 76 * @regs: list of addresses of registers which are at different addresses on
74 * different variants. Indexed by one of STMPE_IDX_*. 77 * different variants. Indexed by one of STMPE_IDX_*.
75 * @irq: irq number for stmpe 78 * @irq: irq number for stmpe
76 * @irq_base: starting IRQ number for internal IRQs
77 * @num_gpios: number of gpios, differs for variants 79 * @num_gpios: number of gpios, differs for variants
78 * @ier: cache of IER registers for bus_lock 80 * @ier: cache of IER registers for bus_lock
79 * @oldier: cache of IER registers for bus_lock 81 * @oldier: cache of IER registers for bus_lock
80 * @pdata: platform data 82 * @pdata: platform data
81 */ 83 */
82struct stmpe { 84struct stmpe {
85 struct regulator *vcc;
86 struct regulator *vio;
83 struct mutex lock; 87 struct mutex lock;
84 struct mutex irq_lock; 88 struct mutex irq_lock;
85 struct device *dev; 89 struct device *dev;
@@ -91,7 +95,6 @@ struct stmpe {
91 const u8 *regs; 95 const u8 *regs;
92 96
93 int irq; 97 int irq;
94 int irq_base;
95 int num_gpios; 98 int num_gpios;
96 u8 ier[2]; 99 u8 ier[2];
97 u8 oldier[2]; 100 u8 oldier[2];
@@ -132,8 +135,6 @@ struct stmpe_keypad_platform_data {
132 135
133/** 136/**
134 * struct stmpe_gpio_platform_data - STMPE GPIO platform data 137 * struct stmpe_gpio_platform_data - STMPE GPIO platform data
135 * @gpio_base: first gpio number assigned. A maximum of
136 * %STMPE_NR_GPIOS GPIOs will be allocated.
137 * @norequest_mask: bitmask specifying which GPIOs should _not_ be 138 * @norequest_mask: bitmask specifying which GPIOs should _not_ be
138 * requestable due to different usage (e.g. touch, keypad) 139 * requestable due to different usage (e.g. touch, keypad)
139 * STMPE_GPIO_NOREQ_* macros can be used here. 140 * STMPE_GPIO_NOREQ_* macros can be used here.
@@ -141,7 +142,6 @@ struct stmpe_keypad_platform_data {
141 * @remove: board specific remove callback 142 * @remove: board specific remove callback
142 */ 143 */
143struct stmpe_gpio_platform_data { 144struct stmpe_gpio_platform_data {
144 int gpio_base;
145 unsigned norequest_mask; 145 unsigned norequest_mask;
146 void (*setup)(struct stmpe *stmpe, unsigned gpio_base); 146 void (*setup)(struct stmpe *stmpe, unsigned gpio_base);
147 void (*remove)(struct stmpe *stmpe, unsigned gpio_base); 147 void (*remove)(struct stmpe *stmpe, unsigned gpio_base);
@@ -195,8 +195,6 @@ struct stmpe_ts_platform_data {
195 * @irq_trigger: IRQ trigger to use for the interrupt to the host 195 * @irq_trigger: IRQ trigger to use for the interrupt to the host
196 * @autosleep: bool to enable/disable stmpe autosleep 196 * @autosleep: bool to enable/disable stmpe autosleep
197 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 197 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
198 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
199 * %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used.
200 * @irq_over_gpio: true if gpio is used to get irq 198 * @irq_over_gpio: true if gpio is used to get irq
201 * @irq_gpio: gpio number over which irq will be requested (significant only if 199 * @irq_gpio: gpio number over which irq will be requested (significant only if
202 * irq_over_gpio is true) 200 * irq_over_gpio is true)
@@ -207,7 +205,6 @@ struct stmpe_ts_platform_data {
207struct stmpe_platform_data { 205struct stmpe_platform_data {
208 int id; 206 int id;
209 unsigned int blocks; 207 unsigned int blocks;
210 int irq_base;
211 unsigned int irq_trigger; 208 unsigned int irq_trigger;
212 bool autosleep; 209 bool autosleep;
213 bool irq_over_gpio; 210 bool irq_over_gpio;
@@ -219,10 +216,4 @@ struct stmpe_platform_data {
219 struct stmpe_ts_platform_data *ts; 216 struct stmpe_ts_platform_data *ts;
220}; 217};
221 218
222#define STMPE_NR_INTERNAL_IRQS 9
223#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x))
224
225#define STMPE_NR_GPIOS 24
226#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS)
227
228#endif 219#endif
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
index 8789fa3c7fd9..75e543b78f53 100644
--- a/include/linux/mfd/syscon.h
+++ b/include/linux/mfd/syscon.h
@@ -15,6 +15,8 @@
15#ifndef __LINUX_MFD_SYSCON_H__ 15#ifndef __LINUX_MFD_SYSCON_H__
16#define __LINUX_MFD_SYSCON_H__ 16#define __LINUX_MFD_SYSCON_H__
17 17
18#include <linux/err.h>
19
18struct device_node; 20struct device_node;
19 21
20#ifdef CONFIG_MFD_SYSCON 22#ifdef CONFIG_MFD_SYSCON
diff --git a/include/linux/mfd/tps65218.h b/include/linux/mfd/tps65218.h
index d2e357df5a0e..2f9b593246ee 100644
--- a/include/linux/mfd/tps65218.h
+++ b/include/linux/mfd/tps65218.h
@@ -267,7 +267,6 @@ struct tps65218 {
267 u32 irq_mask; 267 u32 irq_mask;
268 struct regmap_irq_chip_data *irq_data; 268 struct regmap_irq_chip_data *irq_data;
269 struct regulator_desc desc[TPS65218_NUM_REGULATOR]; 269 struct regulator_desc desc[TPS65218_NUM_REGULATOR];
270 struct regulator_dev *rdev[TPS65218_NUM_REGULATOR];
271 struct tps_info *info[TPS65218_NUM_REGULATOR]; 270 struct tps_info *info[TPS65218_NUM_REGULATOR];
272 struct regmap *regmap; 271 struct regmap *regmap;
273}; 272};
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index 81f639bc1ae6..8f9fc3d26e6d 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -28,6 +28,7 @@
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/mfd/core.h> 29#include <linux/mfd/core.h>
30#include <linux/regulator/consumer.h> 30#include <linux/regulator/consumer.h>
31#include <linux/clk.h>
31 32
32#define TWL6040_REG_ASICID 0x01 33#define TWL6040_REG_ASICID 0x01
33#define TWL6040_REG_ASICREV 0x02 34#define TWL6040_REG_ASICREV 0x02
@@ -157,6 +158,7 @@
157#define TWL6040_I2CSEL 0x01 158#define TWL6040_I2CSEL 0x01
158#define TWL6040_RESETSPLIT 0x04 159#define TWL6040_RESETSPLIT 0x04
159#define TWL6040_INTCLRMODE 0x08 160#define TWL6040_INTCLRMODE 0x08
161#define TWL6040_I2CMODE(x) ((x & 0x3) << 4)
160 162
161/* STATUS (0x2E) fields */ 163/* STATUS (0x2E) fields */
162 164
@@ -222,6 +224,7 @@ struct twl6040 {
222 struct regmap *regmap; 224 struct regmap *regmap;
223 struct regmap_irq_chip_data *irq_data; 225 struct regmap_irq_chip_data *irq_data;
224 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */ 226 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
227 struct clk *clk32k;
225 struct mutex mutex; 228 struct mutex mutex;
226 struct mutex irq_mutex; 229 struct mutex irq_mutex;
227 struct mfd_cell cells[TWL6040_CELLS]; 230 struct mfd_cell cells[TWL6040_CELLS];
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 22:38:39 -0400