From 9c9e321455fb806108f9dbb1872bacfd42c6002b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 8 May 2014 23:16:35 +0200 Subject: mfd: stmpe: add optional regulators The STMPE has VCC and VIO supply lines, and sometimes (as on Ux500) this comes from a software-controlled regulator. Make it possible to supply the STMPE with power from these regulators. Signed-off-by: Linus Walleij --- include/linux/mfd/stmpe.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h index 48395a69a7e9..980898620e57 100644 --- a/include/linux/mfd/stmpe.h +++ b/include/linux/mfd/stmpe.h @@ -11,6 +11,7 @@ #include struct device; +struct regulator; enum stmpe_block { STMPE_BLOCK_GPIO = 1 << 0, @@ -62,6 +63,8 @@ struct stmpe_client_info; /** * struct stmpe - STMPE MFD structure + * @vcc: optional VCC regulator + * @vio: optional VIO regulator * @lock: lock protecting I/O operations * @irq_lock: IRQ bus lock * @dev: device, mostly for dev_dbg() @@ -80,6 +83,8 @@ struct stmpe_client_info; * @pdata: platform data */ struct stmpe { + struct regulator *vcc; + struct regulator *vio; struct mutex lock; struct mutex irq_lock; struct device *dev; -- cgit v1.2.2 From 9e9dc7d9597bd6881b3e7ae6ae3d710319605c47 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 8 May 2014 23:16:34 +0200 Subject: mfd: stmpe: root out static GPIO and IRQ assignments The only platform using the STMPE expander now boots from device tree using all-dynamic GPIO and IRQ number assignments, so remove the mechanism to pass this from the device tree entirely. Signed-off-by: Linus Walleij --- include/linux/mfd/stmpe.h | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h index 980898620e57..575a86c7fcbd 100644 --- a/include/linux/mfd/stmpe.h +++ b/include/linux/mfd/stmpe.h @@ -76,7 +76,6 @@ struct stmpe_client_info; * @regs: list of addresses of registers which are at different addresses on * different variants. Indexed by one of STMPE_IDX_*. * @irq: irq number for stmpe - * @irq_base: starting IRQ number for internal IRQs * @num_gpios: number of gpios, differs for variants * @ier: cache of IER registers for bus_lock * @oldier: cache of IER registers for bus_lock @@ -96,7 +95,6 @@ struct stmpe { const u8 *regs; int irq; - int irq_base; int num_gpios; u8 ier[2]; u8 oldier[2]; @@ -137,8 +135,6 @@ struct stmpe_keypad_platform_data { /** * struct stmpe_gpio_platform_data - STMPE GPIO platform data - * @gpio_base: first gpio number assigned. A maximum of - * %STMPE_NR_GPIOS GPIOs will be allocated. * @norequest_mask: bitmask specifying which GPIOs should _not_ be * requestable due to different usage (e.g. touch, keypad) * STMPE_GPIO_NOREQ_* macros can be used here. @@ -146,7 +142,6 @@ struct stmpe_keypad_platform_data { * @remove: board specific remove callback */ struct stmpe_gpio_platform_data { - int gpio_base; unsigned norequest_mask; void (*setup)(struct stmpe *stmpe, unsigned gpio_base); void (*remove)(struct stmpe *stmpe, unsigned gpio_base); @@ -200,8 +195,6 @@ struct stmpe_ts_platform_data { * @irq_trigger: IRQ trigger to use for the interrupt to the host * @autosleep: bool to enable/disable stmpe autosleep * @autosleep_timeout: inactivity timeout in milliseconds for autosleep - * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or - * %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used. * @irq_over_gpio: true if gpio is used to get irq * @irq_gpio: gpio number over which irq will be requested (significant only if * irq_over_gpio is true) @@ -212,7 +205,6 @@ struct stmpe_ts_platform_data { struct stmpe_platform_data { int id; unsigned int blocks; - int irq_base; unsigned int irq_trigger; bool autosleep; bool irq_over_gpio; @@ -224,10 +216,4 @@ struct stmpe_platform_data { struct stmpe_ts_platform_data *ts; }; -#define STMPE_NR_INTERNAL_IRQS 9 -#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x)) - -#define STMPE_NR_GPIOS 24 -#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS) - #endif -- cgit v1.2.2 From 58a9e5b98360e8dcf9c958c0552fb35279e3933f Mon Sep 17 00:00:00 2001 From: Michael Brunner Date: Tue, 8 Apr 2014 08:21:06 +0200 Subject: mfd: Add sysfs attributes for Kontron PLD firmware revision This patch adds attributes to the Kontron PLD driver to allow applications to retrieve firmware information. Additionally the format has been changed to conform with the representation in other Kontron software. Signed-off-by: Michael Brunner Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- include/linux/mfd/kempld.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/kempld.h b/include/linux/mfd/kempld.h index b911ef3add03..26e0b469e567 100644 --- a/include/linux/mfd/kempld.h +++ b/include/linux/mfd/kempld.h @@ -51,6 +51,8 @@ #define KEMPLD_TYPE_DEBUG 0x1 #define KEMPLD_TYPE_CUSTOM 0x2 +#define KEMPLD_VERSION_LEN 10 + /** * struct kempld_info - PLD device information structure * @major: PLD major revision @@ -60,6 +62,7 @@ * @type: PLD type * @spec_major: PLD FW specification major revision * @spec_minor: PLD FW specification minor revision + * @version: PLD version string */ struct kempld_info { unsigned int major; @@ -69,6 +72,7 @@ struct kempld_info { unsigned int type; unsigned int spec_major; unsigned int spec_minor; + char version[KEMPLD_VERSION_LEN]; }; /** -- cgit v1.2.2 From 7abafa0a66414e385d122bcbc655a1d55ecbaecf Mon Sep 17 00:00:00 2001 From: Jay Aurabind Date: Wed, 21 May 2014 22:49:54 +0530 Subject: mfd: abx500-core: Fix compiler warning larger stack frame MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On systems with CONFIG_FRAME_WARN=1024, compiler warns the allocation of an object of struct device on stack. Make the allocation dynamically to fix the warning. Also change the caller's return type to int so as to account for error handling. drivers/mfd/abx500-core.c: In function ‘abx500_dump_all_banks’: drivers/mfd/abx500-core.c:167:1: warning: the frame size of 1032 bytes is larger than 1024 bytes [-Wframe-larger-than=] Signed-off-by: Aurabindo J Signed-off-by: Lee Jones --- include/linux/mfd/abx500.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index 3301b2031c8d..df2508f7f3d2 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -330,7 +330,7 @@ int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank, int abx500_get_chip_id(struct device *dev); int abx500_event_registers_startup_state_get(struct device *dev, u8 *event); int abx500_startup_irq_enabled(struct device *dev, unsigned int irq); -void abx500_dump_all_banks(void); +int abx500_dump_all_banks(void); struct abx500_ops { int (*get_chip_id) (struct device *); -- cgit v1.2.2 From d09b711a31ed891dc372039ccd347cdc8402da04 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 10:13:33 +0400 Subject: mfd: mc13xxx: Move definitions out of structures Signed-off-by: Alexander Shiyan Signed-off-by: Lee Jones --- include/linux/mfd/mc13xxx.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h index a326c850f046..d63b1d309106 100644 --- a/include/linux/mfd/mc13xxx.h +++ b/include/linux/mfd/mc13xxx.h @@ -117,10 +117,6 @@ struct mc13xxx_led_platform_data { #define MAX_LED_CONTROL_REGS 6 -struct mc13xxx_leds_platform_data { - struct mc13xxx_led_platform_data *led; - int num_leds; - /* MC13783 LED Control 0 */ #define MC13783_LED_C0_ENABLE (1 << 0) #define MC13783_LED_C0_TRIODE_MD (1 << 7) @@ -169,10 +165,13 @@ struct mc13xxx_leds_platform_data { /* MC34708 LED Control 0 */ #define MC34708_LED_C0_CURRENT_R(x) (((x) & 0x3) << 9) #define MC34708_LED_C0_CURRENT_G(x) (((x) & 0x3) << 21) + +struct mc13xxx_leds_platform_data { + struct mc13xxx_led_platform_data *led; + int num_leds; u32 led_control[MAX_LED_CONTROL_REGS]; }; -struct mc13xxx_buttons_platform_data { #define MC13783_BUTTON_DBNC_0MS 0 #define MC13783_BUTTON_DBNC_30MS 1 #define MC13783_BUTTON_DBNC_150MS 2 @@ -180,6 +179,8 @@ struct mc13xxx_buttons_platform_data { #define MC13783_BUTTON_ENABLE (1 << 2) #define MC13783_BUTTON_POL_INVERT (1 << 3) #define MC13783_BUTTON_RESET_EN (1 << 4) + +struct mc13xxx_buttons_platform_data { int b1on_flags; unsigned short b1on_key; int b2on_flags; @@ -188,14 +189,14 @@ struct mc13xxx_buttons_platform_data { unsigned short b3on_key; }; +#define MC13783_TS_ATO_FIRST false +#define MC13783_TS_ATO_EACH true + struct mc13xxx_ts_platform_data { /* Delay between Touchscreen polarization and ADC Conversion. * Given in clock ticks of a 32 kHz clock which gives a granularity of * about 30.5ms */ u8 ato; - -#define MC13783_TS_ATO_FIRST false -#define MC13783_TS_ATO_EACH true /* Use the ATO delay only for the first conversion or for each one */ bool atox; }; @@ -210,11 +211,12 @@ struct mc13xxx_codec_platform_data { enum mc13783_ssi_port dac_ssi_port; }; -struct mc13xxx_platform_data { -#define MC13XXX_USE_TOUCHSCREEN (1 << 0) +#define MC13XXX_USE_TOUCHSCREEN (1 << 0) #define MC13XXX_USE_CODEC (1 << 1) #define MC13XXX_USE_ADC (1 << 2) #define MC13XXX_USE_RTC (1 << 3) + +struct mc13xxx_platform_data { unsigned int flags; struct mc13xxx_regulator_platform_data regulators; -- cgit v1.2.2 From 3176a521922b8ebcf7a593063cc55344486d2cd7 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 15 Apr 2014 19:40:09 +0800 Subject: mfd: tps65218: Remove unused *rdev[] from struct tps65218 The *rdev[] is not used since commit 413be59e2f333 "regulator: tps65218: Remove unnecessary regulator_unregister call". Signed-off-by: Axel Lin Signed-off-by: Lee Jones --- include/linux/mfd/tps65218.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65218.h b/include/linux/mfd/tps65218.h index d2e357df5a0e..2f9b593246ee 100644 --- a/include/linux/mfd/tps65218.h +++ b/include/linux/mfd/tps65218.h @@ -267,7 +267,6 @@ struct tps65218 { u32 irq_mask; struct regmap_irq_chip_data *irq_data; struct regulator_desc desc[TPS65218_NUM_REGULATOR]; - struct regulator_dev *rdev[TPS65218_NUM_REGULATOR]; struct tps_info *info[TPS65218_NUM_REGULATOR]; struct regmap *regmap; }; -- cgit v1.2.2 From e349c910e2398cbff59d7c58851503191a8e9157 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 14 Apr 2014 09:40:45 +0200 Subject: mfd/rtc: s5m: Do not allocate RTC I2C dummy and regmap for unsupported chipsets The rtc-s5m driver does not support all of S2M and S5M chipsets supported by main MFD sec-core driver. For such chipsets unsupported by rtc-s5m, the MFD sec-core driver initialized regmap with default config. This config in such cases wouldn't work at all. The main MFD sec-core driver shouldn't initialize regmap for child drivers which is not used by them and even not valid. Move the allocation of RTC I2C dummy device and initialization of RTC regmap from main MFD sec-core driver to the rtc-s5m driver. The rtc-s5m driver will use proper regmap config for supported devices. Signed-off-by: Krzysztof Kozlowski Acked-by: Alessandro Zummo Signed-off-by: Lee Jones --- include/linux/mfd/samsung/core.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index 157e32b6ca28..84aaf6c25794 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -28,7 +28,6 @@ enum sec_device_type { * @dev: master device of the chip (can be used to access platform data) * @pdata: pointer to private data used to pass platform data to child * @i2c: i2c client private data for regulator - * @rtc: i2c client private data for rtc * @iolock: mutex for serializing io access * @irqlock: mutex for buslock * @irq_base: base IRQ number for sec-pmic, required for IRQs @@ -42,9 +41,7 @@ struct sec_pmic_dev { struct device *dev; struct sec_platform_data *pdata; struct regmap *regmap_pmic; - struct regmap *regmap_rtc; struct i2c_client *i2c; - struct i2c_client *rtc; int device_type; int irq_base; -- cgit v1.2.2 From 51f1f1cb24b870db44edcab56ffd89ecf8ce09e8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Apr 2014 10:05:38 +0200 Subject: mfd: sec-core: Update sec_pmic documentation Update the documentation for sec_pmic state container structure to reflect current code. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Lee Jones --- include/linux/mfd/samsung/core.h | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index 84aaf6c25794..1c66a6462887 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -24,18 +24,23 @@ enum sec_device_type { }; /** - * struct sec_pmic_dev - s5m87xx master device for sub-drivers - * @dev: master device of the chip (can be used to access platform data) - * @pdata: pointer to private data used to pass platform data to child - * @i2c: i2c client private data for regulator - * @iolock: mutex for serializing io access - * @irqlock: mutex for buslock - * @irq_base: base IRQ number for sec-pmic, required for IRQs - * @irq: generic IRQ number for s5m87xx - * @ono: power onoff IRQ number for s5m87xx - * @irq_masks_cur: currently active value - * @irq_masks_cache: cached hardware value - * @type: indicate which s5m87xx "variant" is used + * struct sec_pmic_dev - s2m/s5m master device for sub-drivers + * @dev: Master device of the chip + * @pdata: Platform data populated with data from DTS + * or board files + * @regmap_pmic: Regmap associated with PMIC's I2C address + * @i2c: I2C client of the main driver + * @device_type: Type of device, matches enum sec_device_type + * @irq_base: Base IRQ number for device, required for IRQs + * @irq: Generic IRQ number for device + * @irq_data: Runtime data structure for IRQ controller + * @ono: Power onoff IRQ number for s5m87xx + * @wakeup: Whether or not this is a wakeup device + * @wtsr_smpl: Whether or not to enable in RTC driver the Watchdog + * Timer Software Reset (registers set to default value + * after PWRHOLD falling) and Sudden Momentary Power Loss + * (PMIC will enter power on sequence after short drop in + * VBATT voltage). */ struct sec_pmic_dev { struct device *dev; -- cgit v1.2.2 From 1ec93b9b176b3c4e065c326ccf40458fcc01e6c0 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Fri, 25 Apr 2014 09:24:21 +0800 Subject: mfd: rdc321x: Fix off-by-one for ngpio setting The valid gpio is GPIO0 ~ GPIO58, so ngpio should be 59. This patch also renames RDC321X_MAX_GPIO to RDC321X_NUM_GPIO because it actually means the number of available GPIOs. Signed-off-by: Axel Lin Acked-by: Linus Walleij Signed-off-by: Lee Jones --- include/linux/mfd/rdc321x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/rdc321x.h b/include/linux/mfd/rdc321x.h index 4bdf19c8eedf..442743a8f915 100644 --- a/include/linux/mfd/rdc321x.h +++ b/include/linux/mfd/rdc321x.h @@ -12,7 +12,7 @@ #define RDC321X_GPIO_CTRL_REG2 0x84 #define RDC321X_GPIO_DATA_REG2 0x88 -#define RDC321X_MAX_GPIO 58 +#define RDC321X_NUM_GPIO 59 struct rdc321x_gpio_pdata { struct pci_dev *sb_pdev; -- cgit v1.2.2 From 11e38e11afcdd598d0978746924a001e3e7cb723 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 1 Apr 2014 16:44:59 +0300 Subject: mfd: twl6040: Select i2c fast mode as default with regmap patch All boards using twl6040 configures the i2c bus to 400KHz. While twl6040's defaults to normal mode (100KHz). So far twl6040 has no problem with i2c communication in this configuration it is safer to select fast i2c mode. Signed-off-by: Peter Ujfalusi Signed-off-by: Lee Jones --- include/linux/mfd/twl6040.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index 81f639bc1ae6..a69d16b30c18 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -157,6 +157,7 @@ #define TWL6040_I2CSEL 0x01 #define TWL6040_RESETSPLIT 0x04 #define TWL6040_INTCLRMODE 0x08 +#define TWL6040_I2CMODE(x) ((x & 0x3) << 4) /* STATUS (0x2E) fields */ -- cgit v1.2.2 From 68bab8662f49b9e158f1d32f11becd4e48c04079 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 3 Apr 2014 13:54:41 +0300 Subject: mfd: twl6040: Optional clk32k clock handling In certain boards the source for the clk32k clock can be gated. In these boards the clk32k clock can be provided to the driver and it is going to be enabled/disabled when it is needed. If the clk32k clock is not provided the driver will assume that it is always running. Signed-off-by: Peter Ujfalusi Signed-off-by: Lee Jones --- include/linux/mfd/twl6040.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index a69d16b30c18..8f9fc3d26e6d 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -28,6 +28,7 @@ #include #include #include +#include #define TWL6040_REG_ASICID 0x01 #define TWL6040_REG_ASICREV 0x02 @@ -223,6 +224,7 @@ struct twl6040 { struct regmap *regmap; struct regmap_irq_chip_data *irq_data; struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */ + struct clk *clk32k; struct mutex mutex; struct mutex irq_mutex; struct mfd_cell cells[TWL6040_CELLS]; -- cgit v1.2.2 From 9549b5ff001a8904372370d10be9a2f05e10eca5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 23 Apr 2014 16:13:05 +0200 Subject: mfd: sec-core: Remove duplicated device type from sec_pmic_dev The device type was stored in sec_pmic_dev state container twice: - unsigned long type (initialized from of_device_id or i2c_device_id) - int device_type (initialized as above or from board files when there is no DTS) The 'type' field was never used outside of probe so it can be safely removed. Change also the device_type in sec_pmic_dev and sec_platform_data to unsigned long to avoid any casts. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Lee Jones --- include/linux/mfd/samsung/core.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index 1c66a6462887..47d84242940b 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -48,13 +48,12 @@ struct sec_pmic_dev { struct regmap *regmap_pmic; struct i2c_client *i2c; - int device_type; + unsigned long device_type; int irq_base; int irq; struct regmap_irq_chip_data *irq_data; int ono; - unsigned long type; bool wakeup; bool wtsr_smpl; }; -- cgit v1.2.2 From 3e87933a68dce6a27bf1006964f8c850e13140b5 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 8 Apr 2014 17:14:15 -0700 Subject: mfd: pm8921: Remove pm8xxx API now that sub-devices use regmap The pm8xxx read/write wrappers are no longer necessary now that all the sub-device drivers are using the regmap API. Remove it. Signed-off-by: Stephen Boyd Signed-off-by: Lee Jones --- include/linux/mfd/pm8xxx/core.h | 81 ----------------------------------------- 1 file changed, 81 deletions(-) delete mode 100644 include/linux/mfd/pm8xxx/core.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h deleted file mode 100644 index bd2f4f64e931..000000000000 --- a/include/linux/mfd/pm8xxx/core.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/* - * Qualcomm PMIC 8xxx driver header file - * - */ - -#ifndef __MFD_PM8XXX_CORE_H -#define __MFD_PM8XXX_CORE_H - -#include - -struct pm8xxx_drvdata { - int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val); - int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val); - int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf, - int n); - int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf, - int n); - int (*pmic_read_irq_stat) (const struct device *dev, int irq); - void *pm_chip_data; -}; - -static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val) -{ - struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); - - if (!dd) - return -EINVAL; - return dd->pmic_readb(dev, addr, val); -} - -static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val) -{ - struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); - - if (!dd) - return -EINVAL; - return dd->pmic_writeb(dev, addr, val); -} - -static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf, - int n) -{ - struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); - - if (!dd) - return -EINVAL; - return dd->pmic_read_buf(dev, addr, buf, n); -} - -static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf, - int n) -{ - struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); - - if (!dd) - return -EINVAL; - return dd->pmic_write_buf(dev, addr, buf, n); -} - -static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq) -{ - struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); - - if (!dd) - return -EINVAL; - return dd->pmic_read_irq_stat(dev, irq); -} - -#endif -- cgit v1.2.2 From cfb61a419630a810033f2777aba724ab6b1272b3 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Thu, 1 May 2014 14:29:27 +0200 Subject: mfd: AXP20x: Add mfd driver for AXP20x PMIC This patch introduces the preliminary support for PMICs X-Powers AXP202 and AXP209. The AXP209 and AXP202 are the PMUs (Power Management Unit) used by A10, A13 and A20 SoCs and developed by X-Powers, a sister company of Allwinner. The core enables support for two subsystems: - PEK (Power Enable Key) - Regulators Signed-off-by: Carlo Caione Signed-off-by: Lee Jones --- include/linux/mfd/axp20x.h | 180 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) create mode 100644 include/linux/mfd/axp20x.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h new file mode 100644 index 000000000000..d0e31a2287ac --- /dev/null +++ b/include/linux/mfd/axp20x.h @@ -0,0 +1,180 @@ +/* + * Functions and registers to access AXP20X power management chip. + * + * Copyright (C) 2013, Carlo Caione + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MFD_AXP20X_H +#define __LINUX_MFD_AXP20X_H + +enum { + AXP202_ID = 0, + AXP209_ID, +}; + +#define AXP20X_DATACACHE(m) (0x04 + (m)) + +/* Power supply */ +#define AXP20X_PWR_INPUT_STATUS 0x00 +#define AXP20X_PWR_OP_MODE 0x01 +#define AXP20X_USB_OTG_STATUS 0x02 +#define AXP20X_PWR_OUT_CTRL 0x12 +#define AXP20X_DCDC2_V_OUT 0x23 +#define AXP20X_DCDC2_LDO3_V_SCAL 0x25 +#define AXP20X_DCDC3_V_OUT 0x27 +#define AXP20X_LDO24_V_OUT 0x28 +#define AXP20X_LDO3_V_OUT 0x29 +#define AXP20X_VBUS_IPSOUT_MGMT 0x30 +#define AXP20X_V_OFF 0x31 +#define AXP20X_OFF_CTRL 0x32 +#define AXP20X_CHRG_CTRL1 0x33 +#define AXP20X_CHRG_CTRL2 0x34 +#define AXP20X_CHRG_BAK_CTRL 0x35 +#define AXP20X_PEK_KEY 0x36 +#define AXP20X_DCDC_FREQ 0x37 +#define AXP20X_V_LTF_CHRG 0x38 +#define AXP20X_V_HTF_CHRG 0x39 +#define AXP20X_APS_WARN_L1 0x3a +#define AXP20X_APS_WARN_L2 0x3b +#define AXP20X_V_LTF_DISCHRG 0x3c +#define AXP20X_V_HTF_DISCHRG 0x3d + +/* Interrupt */ +#define AXP20X_IRQ1_EN 0x40 +#define AXP20X_IRQ2_EN 0x41 +#define AXP20X_IRQ3_EN 0x42 +#define AXP20X_IRQ4_EN 0x43 +#define AXP20X_IRQ5_EN 0x44 +#define AXP20X_IRQ1_STATE 0x48 +#define AXP20X_IRQ2_STATE 0x49 +#define AXP20X_IRQ3_STATE 0x4a +#define AXP20X_IRQ4_STATE 0x4b +#define AXP20X_IRQ5_STATE 0x4c + +/* ADC */ +#define AXP20X_ACIN_V_ADC_H 0x56 +#define AXP20X_ACIN_V_ADC_L 0x57 +#define AXP20X_ACIN_I_ADC_H 0x58 +#define AXP20X_ACIN_I_ADC_L 0x59 +#define AXP20X_VBUS_V_ADC_H 0x5a +#define AXP20X_VBUS_V_ADC_L 0x5b +#define AXP20X_VBUS_I_ADC_H 0x5c +#define AXP20X_VBUS_I_ADC_L 0x5d +#define AXP20X_TEMP_ADC_H 0x5e +#define AXP20X_TEMP_ADC_L 0x5f +#define AXP20X_TS_IN_H 0x62 +#define AXP20X_TS_IN_L 0x63 +#define AXP20X_GPIO0_V_ADC_H 0x64 +#define AXP20X_GPIO0_V_ADC_L 0x65 +#define AXP20X_GPIO1_V_ADC_H 0x66 +#define AXP20X_GPIO1_V_ADC_L 0x67 +#define AXP20X_PWR_BATT_H 0x70 +#define AXP20X_PWR_BATT_M 0x71 +#define AXP20X_PWR_BATT_L 0x72 +#define AXP20X_BATT_V_H 0x78 +#define AXP20X_BATT_V_L 0x79 +#define AXP20X_BATT_CHRG_I_H 0x7a +#define AXP20X_BATT_CHRG_I_L 0x7b +#define AXP20X_BATT_DISCHRG_I_H 0x7c +#define AXP20X_BATT_DISCHRG_I_L 0x7d +#define AXP20X_IPSOUT_V_HIGH_H 0x7e +#define AXP20X_IPSOUT_V_HIGH_L 0x7f + +/* Power supply */ +#define AXP20X_DCDC_MODE 0x80 +#define AXP20X_ADC_EN1 0x82 +#define AXP20X_ADC_EN2 0x83 +#define AXP20X_ADC_RATE 0x84 +#define AXP20X_GPIO10_IN_RANGE 0x85 +#define AXP20X_GPIO1_ADC_IRQ_RIS 0x86 +#define AXP20X_GPIO1_ADC_IRQ_FAL 0x87 +#define AXP20X_TIMER_CTRL 0x8a +#define AXP20X_VBUS_MON 0x8b +#define AXP20X_OVER_TMP 0x8f + +/* GPIO */ +#define AXP20X_GPIO0_CTRL 0x90 +#define AXP20X_LDO5_V_OUT 0x91 +#define AXP20X_GPIO1_CTRL 0x92 +#define AXP20X_GPIO2_CTRL 0x93 +#define AXP20X_GPIO20_SS 0x94 +#define AXP20X_GPIO3_CTRL 0x95 + +/* Battery */ +#define AXP20X_CHRG_CC_31_24 0xb0 +#define AXP20X_CHRG_CC_23_16 0xb1 +#define AXP20X_CHRG_CC_15_8 0xb2 +#define AXP20X_CHRG_CC_7_0 0xb3 +#define AXP20X_DISCHRG_CC_31_24 0xb4 +#define AXP20X_DISCHRG_CC_23_16 0xb5 +#define AXP20X_DISCHRG_CC_15_8 0xb6 +#define AXP20X_DISCHRG_CC_7_0 0xb7 +#define AXP20X_CC_CTRL 0xb8 +#define AXP20X_FG_RES 0xb9 + +/* Regulators IDs */ +enum { + AXP20X_LDO1 = 0, + AXP20X_LDO2, + AXP20X_LDO3, + AXP20X_LDO4, + AXP20X_LDO5, + AXP20X_DCDC2, + AXP20X_DCDC3, + AXP20X_REG_ID_MAX, +}; + +/* IRQs */ +enum { + AXP20X_IRQ_ACIN_OVER_V = 1, + AXP20X_IRQ_ACIN_PLUGIN, + AXP20X_IRQ_ACIN_REMOVAL, + AXP20X_IRQ_VBUS_OVER_V, + AXP20X_IRQ_VBUS_PLUGIN, + AXP20X_IRQ_VBUS_REMOVAL, + AXP20X_IRQ_VBUS_V_LOW, + AXP20X_IRQ_BATT_PLUGIN, + AXP20X_IRQ_BATT_REMOVAL, + AXP20X_IRQ_BATT_ENT_ACT_MODE, + AXP20X_IRQ_BATT_EXIT_ACT_MODE, + AXP20X_IRQ_CHARG, + AXP20X_IRQ_CHARG_DONE, + AXP20X_IRQ_BATT_TEMP_HIGH, + AXP20X_IRQ_BATT_TEMP_LOW, + AXP20X_IRQ_DIE_TEMP_HIGH, + AXP20X_IRQ_CHARG_I_LOW, + AXP20X_IRQ_DCDC1_V_LONG, + AXP20X_IRQ_DCDC2_V_LONG, + AXP20X_IRQ_DCDC3_V_LONG, + AXP20X_IRQ_PEK_SHORT = 22, + AXP20X_IRQ_PEK_LONG, + AXP20X_IRQ_N_OE_PWR_ON, + AXP20X_IRQ_N_OE_PWR_OFF, + AXP20X_IRQ_VBUS_VALID, + AXP20X_IRQ_VBUS_NOT_VALID, + AXP20X_IRQ_VBUS_SESS_VALID, + AXP20X_IRQ_VBUS_SESS_END, + AXP20X_IRQ_LOW_PWR_LVL1, + AXP20X_IRQ_LOW_PWR_LVL2, + AXP20X_IRQ_TIMER, + AXP20X_IRQ_PEK_RIS_EDGE, + AXP20X_IRQ_PEK_FAL_EDGE, + AXP20X_IRQ_GPIO3_INPUT, + AXP20X_IRQ_GPIO2_INPUT, + AXP20X_IRQ_GPIO1_INPUT, + AXP20X_IRQ_GPIO0_INPUT, +}; + +struct axp20x_dev { + struct device *dev; + struct i2c_client *i2c_client; + struct regmap *regmap; + struct regmap_irq_chip_data *regmap_irqc; + long variant; +}; + +#endif /* __LINUX_MFD_AXP20X_H */ -- cgit v1.2.2 From 3d2379909374ef2de6bc57ed8966c7ca8c9dfb82 Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Fri, 9 May 2014 16:37:40 +0530 Subject: mfd: syscon: Include linux/err.h to fix build error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit df73de9b0d412 ("mfd: syscon: Return -ENOSYS if CONFIG_MFD_SYSCON is not enabled") introduced fallbacks for APIs, but missed out on adding the header file. This would work only if linux/err.h is also included in the source code from where this file is included. It would be better to include linux/err.h in file to remove possible build errors. Without this patch, we get following and similar build errors if this header file is included in some source file and CONFIG_MFD_SYSCON is not enabled. include/linux/mfd/syscon.h: In function ‘syscon_node_to_regmap’: include/linux/mfd/syscon.h:30:2: error: implicit declaration of function ‘ERR_PTR’ [-Werror=implicit-function-declaration] return ERR_PTR(-ENOSYS); ^ include/linux/mfd/syscon.h:30:18: error: ‘ENOSYS’ undeclared (first use in this function) return ERR_PTR(-ENOSYS); ^ Signed-off-by: Tushar Behera Signed-off-by: Lee Jones --- include/linux/mfd/syscon.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h index 8789fa3c7fd9..75e543b78f53 100644 --- a/include/linux/mfd/syscon.h +++ b/include/linux/mfd/syscon.h @@ -15,6 +15,8 @@ #ifndef __LINUX_MFD_SYSCON_H__ #define __LINUX_MFD_SYSCON_H__ +#include + struct device_node; #ifdef CONFIG_MFD_SYSCON -- cgit v1.2.2 From dcc21cc09e3c22d0ede4e105afa8884eba293b58 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 3 Apr 2014 17:45:15 +0200 Subject: mfd: Add driver for Atmel Microcontroller on iPaq h3xxx This adds a driver for the Atmel Microcontroller found on the iPAQ h3xxx series. This device handles some keys, the touchscreen, and the battery monitoring. This is a port of a driver from handhelds.org 2.6.21 kernel, written by Alessandro Gardich based on Andrew Christians original HAL-driver. It has been heavily cleaned and converted to mfd-core by Dmitry Artamonow and rewritten again for the v3.x series kernels by Linus Walleij, bringing back some of the functionality lost from Andrew's original driver. Acked-by: Greg Kroah-Hartman Signed-off-by: Alessandro Gardich Signed-off-by: Dmitry Artamonow Signed-off-by: Linus Walleij Signed-off-by: Lee Jones --- include/linux/mfd/ipaq-micro.h | 148 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 include/linux/mfd/ipaq-micro.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/ipaq-micro.h b/include/linux/mfd/ipaq-micro.h new file mode 100644 index 000000000000..5c4d29f6674f --- /dev/null +++ b/include/linux/mfd/ipaq-micro.h @@ -0,0 +1,148 @@ +/* + * Header file for the compaq Micro MFD + */ + +#ifndef _MFD_IPAQ_MICRO_H_ +#define _MFD_IPAQ_MICRO_H_ + +#include +#include +#include + +#define TX_BUF_SIZE 32 +#define RX_BUF_SIZE 16 +#define CHAR_SOF 0x02 + +/* + * These are the different messages that can be sent to the microcontroller + * to control various aspects. + */ +#define MSG_VERSION 0x0 +#define MSG_KEYBOARD 0x2 +#define MSG_TOUCHSCREEN 0x3 +#define MSG_EEPROM_READ 0x4 +#define MSG_EEPROM_WRITE 0x5 +#define MSG_THERMAL_SENSOR 0x6 +#define MSG_NOTIFY_LED 0x8 +#define MSG_BATTERY 0x9 +#define MSG_SPI_READ 0xb +#define MSG_SPI_WRITE 0xc +#define MSG_BACKLIGHT 0xd /* H3600 only */ +#define MSG_CODEC_CTRL 0xe /* H3100 only */ +#define MSG_DISPLAY_CTRL 0xf /* H3100 only */ + +/* state of receiver parser */ +enum rx_state { + STATE_SOF = 0, /* Next byte should be start of frame */ + STATE_ID, /* Next byte is ID & message length */ + STATE_DATA, /* Next byte is a data byte */ + STATE_CHKSUM /* Next byte should be checksum */ +}; + +/** + * struct ipaq_micro_txdev - TX state + * @len: length of message in TX buffer + * @index: current index into TX buffer + * @buf: TX buffer + */ +struct ipaq_micro_txdev { + u8 len; + u8 index; + u8 buf[TX_BUF_SIZE]; +}; + +/** + * struct ipaq_micro_rxdev - RX state + * @state: context of RX state machine + * @chksum: calculated checksum + * @id: message ID from packet + * @len: RX buffer length + * @index: RX buffer index + * @buf: RX buffer + */ +struct ipaq_micro_rxdev { + enum rx_state state; + unsigned char chksum; + u8 id; + unsigned int len; + unsigned int index; + u8 buf[RX_BUF_SIZE]; +}; + +/** + * struct ipaq_micro_msg - message to the iPAQ microcontroller + * @id: 4-bit ID of the message + * @tx_len: length of TX data + * @tx_data: TX data to send + * @rx_len: length of receieved RX data + * @rx_data: RX data to recieve + * @ack: a completion that will be completed when RX is complete + * @node: list node if message gets queued + */ +struct ipaq_micro_msg { + u8 id; + u8 tx_len; + u8 tx_data[TX_BUF_SIZE]; + u8 rx_len; + u8 rx_data[RX_BUF_SIZE]; + struct completion ack; + struct list_head node; +}; + +/** + * struct ipaq_micro - iPAQ microcontroller state + * @dev: corresponding platform device + * @base: virtual memory base for underlying serial device + * @sdlc: virtual memory base for Synchronous Data Link Controller + * @version: version string + * @tx: TX state + * @rx: RX state + * @lock: lock for this state container + * @msg: current message + * @queue: message queue + * @key: callback for asynchronous key events + * @key_data: data to pass along with key events + * @ts: callback for asynchronous touchscreen events + * @ts_data: data to pass along with key events + */ +struct ipaq_micro { + struct device *dev; + void __iomem *base; + void __iomem *sdlc; + char version[5]; + struct ipaq_micro_txdev tx; /* transmit ISR state */ + struct ipaq_micro_rxdev rx; /* receive ISR state */ + spinlock_t lock; + struct ipaq_micro_msg *msg; + struct list_head queue; + void (*key) (void *data, int len, unsigned char *rxdata); + void *key_data; + void (*ts) (void *data, int len, unsigned char *rxdata); + void *ts_data; +}; + +extern int +ipaq_micro_tx_msg(struct ipaq_micro *micro, struct ipaq_micro_msg *msg); + +static inline int +ipaq_micro_tx_msg_sync(struct ipaq_micro *micro, + struct ipaq_micro_msg *msg) +{ + int ret; + + init_completion(&msg->ack); + ret = ipaq_micro_tx_msg(micro, msg); + wait_for_completion(&msg->ack); + + return ret; +} + +static inline int +ipaq_micro_tx_msg_async(struct ipaq_micro *micro, + struct ipaq_micro_msg *msg) +{ + init_completion(&msg->ack); + return ipaq_micro_tx_msg(micro, msg); +} + +#endif /* _MFD_IPAQ_MICRO_H_ */ -- cgit v1.2.2 From 5271db29d7199fe0ffb303ca4bbbb1485bba28c3 Mon Sep 17 00:00:00 2001 From: Bill Richardson Date: Wed, 30 Apr 2014 10:44:08 -0700 Subject: mfd: cros_ec: Sync to the latest cros_ec_commands.h from EC sources This just updates include/linux/mfd/cros_ec_commands.h to match the latest EC version (which is the One True Source for such things). See [dianders: took today's ToT version from the Chromium OS EC; deleted references to cros_ec_dev and cros_ec_lpc since those aren't upstream yet] Signed-off-by: Bill Richardson Signed-off-by: Doug Anderson Reviewed-by: Simon Glass Tested-by: Andrew Bresticker Tested-by: Stephen Warren Signed-off-by: Lee Jones --- include/linux/mfd/cros_ec.h | 4 +- include/linux/mfd/cros_ec_commands.h | 1128 +++++++++++++++++++++++++++++++--- 2 files changed, 1058 insertions(+), 74 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h index 032af7fc5b2e..887ef4f7bef7 100644 --- a/include/linux/mfd/cros_ec.h +++ b/include/linux/mfd/cros_ec.h @@ -29,8 +29,8 @@ enum { EC_MSG_RX_PROTO_BYTES = 3, /* Max length of messages */ - EC_MSG_BYTES = EC_HOST_PARAM_SIZE + EC_MSG_TX_PROTO_BYTES, - + EC_MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE + + EC_MSG_TX_PROTO_BYTES, }; /** diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h index 86fd06953bcd..7853a6410d14 100644 --- a/include/linux/mfd/cros_ec_commands.h +++ b/include/linux/mfd/cros_ec_commands.h @@ -24,25 +24,12 @@ #define __CROS_EC_COMMANDS_H /* - * Protocol overview + * Current version of this protocol * - * request: CMD [ P0 P1 P2 ... Pn S ] - * response: ERR [ P0 P1 P2 ... Pn S ] - * - * where the bytes are defined as follow : - * - CMD is the command code. (defined by EC_CMD_ constants) - * - ERR is the error code. (defined by EC_RES_ constants) - * - Px is the optional payload. - * it is not sent if the error code is not success. - * (defined by ec_params_ and ec_response_ structures) - * - S is the checksum which is the sum of all payload bytes. - * - * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD - * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM. - * On I2C, all bytes are sent serially in the same message. + * TODO(crosbug.com/p/11223): This is effectively useless; protocol is + * determined in other ways. Remove this once the kernel code no longer + * depends on it. */ - -/* Current version of this protocol */ #define EC_PROTO_VERSION 0x00000002 /* Command version mask */ @@ -57,13 +44,19 @@ #define EC_LPC_ADDR_HOST_CMD 0x204 /* I/O addresses for host command args and params */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 -#define EC_LPC_ADDR_HOST_PARAM 0x804 -#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */ - -/* I/O addresses for host command params, old interface */ -#define EC_LPC_ADDR_OLD_PARAM 0x880 -#define EC_OLD_PARAM_SIZE 0x080 /* Size of param area in bytes */ +/* Protocol version 2 */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is + * EC_PROTO2_MAX_PARAM_SIZE */ +/* Protocol version 3 */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ + +/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff + * and they tell the kernel that so we have to think of it as two parts. */ +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 +#define EC_HOST_CMD_REGION_SIZE 0x80 /* EC command register bit functions */ #define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ @@ -79,18 +72,22 @@ #define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ /* The offset address of each type of data in mapped memory. */ -#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors */ -#define EC_MEMMAP_FAN 0x10 /* Fan speeds */ -#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* Temp sensors (second set) */ -#define EC_MEMMAP_ID 0x20 /* 'E' 'C' */ +#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ +#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ +#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ +#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ #define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ #define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ #define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ #define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ -#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host command interface flags */ -#define EC_MEMMAP_SWITCHES 0x30 -#define EC_MEMMAP_HOST_EVENTS 0x34 +#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ +/* Unused 0x28 - 0x2f */ +#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ +/* Unused 0x31 - 0x33 */ +#define EC_MEMMAP_HOST_EVENTS 0x34 /* 32 bits */ +/* Reserve 0x38 - 0x3f for additional host event-related stuff */ +/* Battery values are all 32 bits */ #define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ #define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ #define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ @@ -99,10 +96,24 @@ #define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ #define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ #define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ +/* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */ #define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ #define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ #define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ #define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ +#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ +/* Unused 0x84 - 0x8f */ +#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ +/* Unused 0x91 */ +#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometer data 0x92 - 0x9f */ +#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ +/* Unused 0xa6 - 0xfe (remember, 0xff is NOT part of the memmap region) */ + + +/* Define the format of the accelerometer mapped memory status byte. */ +#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT (1 << 4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT (1 << 7) /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ #define EC_TEMP_SENSOR_ENTRIES 16 @@ -112,6 +123,8 @@ * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. */ #define EC_TEMP_SENSOR_B_ENTRIES 8 + +/* Special values for mapped temperature sensors */ #define EC_TEMP_SENSOR_NOT_PRESENT 0xff #define EC_TEMP_SENSOR_ERROR 0xfe #define EC_TEMP_SENSOR_NOT_POWERED 0xfd @@ -122,6 +135,18 @@ */ #define EC_TEMP_SENSOR_OFFSET 200 +/* + * Number of ALS readings at EC_MEMMAP_ALS + */ +#define EC_ALS_ENTRIES 2 + +/* + * The default value a temperature sensor will return when it is present but + * has not been read this boot. This is a reasonable number to avoid + * triggering alarms on the host. + */ +#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) + #define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ #define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ #define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ @@ -137,8 +162,8 @@ #define EC_SWITCH_LID_OPEN 0x01 #define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 -/* Recovery requested via keyboard */ -#define EC_SWITCH_KEYBOARD_RECOVERY 0x08 +/* Was recovery requested via keyboard; now unused. */ +#define EC_SWITCH_IGNORE1 0x08 /* Recovery requested via dedicated signal (from servo board) */ #define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ @@ -147,10 +172,15 @@ /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */ #define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +/* Host command interface supports version 3 protocol */ +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 /* Wireless switch flags */ -#define EC_WIRELESS_SWITCH_WLAN 0x01 -#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 +#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ +#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ +#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ +#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ /* * This header file is used in coreboot both in C and ACPI code. The ACPI code @@ -159,6 +189,14 @@ */ #ifndef __ACPI__ +/* + * Define __packed if someone hasn't beat us to it. Linux kernel style + * checking prefers __packed over __attribute__((packed)). + */ +#ifndef __packed +#define __packed __attribute__((packed)) +#endif + /* LPC command status byte masks */ /* EC has written a byte in the data register and host hasn't read it yet */ #define EC_LPC_STATUS_TO_HOST 0x01 @@ -198,6 +236,9 @@ enum ec_status { EC_RES_UNAVAILABLE = 9, /* No response available */ EC_RES_TIMEOUT = 10, /* We got a timeout */ EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */ }; /* @@ -235,6 +276,16 @@ enum host_event_code { /* Shutdown due to battery level too low */ EC_HOST_EVENT_BATTERY_SHUTDOWN = 17, + /* Suggest that the AP throttle itself */ + EC_HOST_EVENT_THROTTLE_START = 18, + /* Suggest that the AP resume normal speed */ + EC_HOST_EVENT_THROTTLE_STOP = 19, + + /* Hang detect logic detected a hang and host event timeout expired */ + EC_HOST_EVENT_HANG_DETECT = 20, + /* Hang detect logic detected a hang and warm rebooted the AP */ + EC_HOST_EVENT_HANG_REBOOT = 21, + /* * The high bit of the event mask is not used as a host event code. If * it reads back as set, then the entire event mask should be @@ -279,6 +330,188 @@ struct ec_lpc_host_args { */ #define EC_HOST_ARGS_FLAG_TO_HOST 0x02 +/*****************************************************************************/ +/* + * Byte codes returned by EC over SPI interface. + * + * These can be used by the AP to debug the EC interface, and to determine + * when the EC is not in a state where it will ever get around to responding + * to the AP. + * + * Example of sequence of bytes read from EC for a current good transfer: + * 1. - - AP asserts chip select (CS#) + * 2. EC_SPI_OLD_READY - AP sends first byte(s) of request + * 3. - - EC starts handling CS# interrupt + * 4. EC_SPI_RECEIVING - AP sends remaining byte(s) of request + * 5. EC_SPI_PROCESSING - EC starts processing request; AP is clocking in + * bytes looking for EC_SPI_FRAME_START + * 6. - - EC finishes processing and sets up response + * 7. EC_SPI_FRAME_START - AP reads frame byte + * 8. (response packet) - AP reads response packet + * 9. EC_SPI_PAST_END - Any additional bytes read by AP + * 10 - - AP deasserts chip select + * 11 - - EC processes CS# interrupt and sets up DMA for + * next request + * + * If the AP is waiting for EC_SPI_FRAME_START and sees any value other than + * the following byte values: + * EC_SPI_OLD_READY + * EC_SPI_RX_READY + * EC_SPI_RECEIVING + * EC_SPI_PROCESSING + * + * Then the EC found an error in the request, or was not ready for the request + * and lost data. The AP should give up waiting for EC_SPI_FRAME_START, + * because the EC is unable to tell when the AP is done sending its request. + */ + +/* + * Framing byte which precedes a response packet from the EC. After sending a + * request, the AP will clock in bytes until it sees the framing byte, then + * clock in the response packet. + */ +#define EC_SPI_FRAME_START 0xec + +/* + * Padding bytes which are clocked out after the end of a response packet. + */ +#define EC_SPI_PAST_END 0xed + +/* + * EC is ready to receive, and has ignored the byte sent by the AP. EC expects + * that the AP will send a valid packet header (starting with + * EC_COMMAND_PROTOCOL_3) in the next 32 bytes. + */ +#define EC_SPI_RX_READY 0xf8 + +/* + * EC has started receiving the request from the AP, but hasn't started + * processing it yet. + */ +#define EC_SPI_RECEIVING 0xf9 + +/* EC has received the entire request from the AP and is processing it. */ +#define EC_SPI_PROCESSING 0xfa + +/* + * EC received bad data from the AP, such as a packet header with an invalid + * length. EC will ignore all data until chip select deasserts. + */ +#define EC_SPI_RX_BAD_DATA 0xfb + +/* + * EC received data from the AP before it was ready. That is, the AP asserted + * chip select and started clocking data before the EC was ready to receive it. + * EC will ignore all data until chip select deasserts. + */ +#define EC_SPI_NOT_READY 0xfc + +/* + * EC was ready to receive a request from the AP. EC has treated the byte sent + * by the AP as part of a request packet, or (for old-style ECs) is processing + * a fully received packet but is not ready to respond yet. + */ +#define EC_SPI_OLD_READY 0xfd + +/*****************************************************************************/ + +/* + * Protocol version 2 for I2C and SPI send a request this way: + * + * 0 EC_CMD_VERSION0 + (command version) + * 1 Command number + * 2 Length of params = N + * 3..N+2 Params, if any + * N+3 8-bit checksum of bytes 0..N+2 + * + * The corresponding response is: + * + * 0 Result code (EC_RES_*) + * 1 Length of params = M + * 2..M+1 Params, if any + * M+2 8-bit checksum of bytes 0..M+1 + */ +#define EC_PROTO2_REQUEST_HEADER_BYTES 3 +#define EC_PROTO2_REQUEST_TRAILER_BYTES 1 +#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ + EC_PROTO2_REQUEST_TRAILER_BYTES) + +#define EC_PROTO2_RESPONSE_HEADER_BYTES 2 +#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 +#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ + EC_PROTO2_RESPONSE_TRAILER_BYTES) + +/* Parameter length was limited by the LPC interface */ +#define EC_PROTO2_MAX_PARAM_SIZE 0xfc + +/* Maximum request and response packet sizes for protocol version 2 */ +#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ + EC_PROTO2_MAX_PARAM_SIZE) + +/*****************************************************************************/ + +/* + * Value written to legacy command port / prefix byte to indicate protocol + * 3+ structs are being used. Usage is bus-dependent. + */ +#define EC_COMMAND_PROTOCOL_3 0xda + +#define EC_HOST_REQUEST_VERSION 3 + +/* Version 3 request from host */ +struct ec_host_request { + /* Struct version (=3) + * + * EC will return EC_RES_INVALID_HEADER if it receives a header with a + * version it doesn't know how to parse. + */ + uint8_t struct_version; + + /* + * Checksum of request and data; sum of all bytes including checksum + * should total to 0. + */ + uint8_t checksum; + + /* Command code */ + uint16_t command; + + /* Command version */ + uint8_t command_version; + + /* Unused byte in current protocol version; set to 0 */ + uint8_t reserved; + + /* Length of data which follows this header */ + uint16_t data_len; +} __packed; + +#define EC_HOST_RESPONSE_VERSION 3 + +/* Version 3 response from EC */ +struct ec_host_response { + /* Struct version (=3) */ + uint8_t struct_version; + + /* + * Checksum of response and data; sum of all bytes including checksum + * should total to 0. + */ + uint8_t checksum; + + /* Result code (EC_RES_*) */ + uint16_t result; + + /* Length of data which follows this header */ + uint16_t data_len; + + /* Unused bytes in current protocol version; set to 0 */ + uint16_t reserved; +} __packed; + +/*****************************************************************************/ /* * Notes on commands: * @@ -418,6 +651,68 @@ struct ec_response_get_comms_status { uint32_t flags; /* Mask of enum ec_comms_status */ } __packed; +/* Fake a variety of responses, purely for testing purposes. */ +#define EC_CMD_TEST_PROTOCOL 0x0a + +/* Tell the EC what to send back to us. */ +struct ec_params_test_protocol { + uint32_t ec_result; + uint32_t ret_len; + uint8_t buf[32]; +} __packed; + +/* Here it comes... */ +struct ec_response_test_protocol { + uint8_t buf[32]; +} __packed; + +/* Get prococol information */ +#define EC_CMD_GET_PROTOCOL_INFO 0x0b + +/* Flags for ec_response_get_protocol_info.flags */ +/* EC_RES_IN_PROGRESS may be returned if a command is slow */ +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) + +struct ec_response_get_protocol_info { + /* Fields which exist if at least protocol version 3 supported */ + + /* Bitmask of protocol versions supported (1 << n means version n)*/ + uint32_t protocol_versions; + + /* Maximum request packet size, in bytes */ + uint16_t max_request_packet_size; + + /* Maximum response packet size, in bytes */ + uint16_t max_response_packet_size; + + /* Flags; see EC_PROTOCOL_INFO_* */ + uint32_t flags; +} __packed; + + +/*****************************************************************************/ +/* Get/Set miscellaneous values */ + +/* The upper byte of .flags tells what to do (nothing means "get") */ +#define EC_GSV_SET 0x80000000 + +/* The lower three bytes of .flags identifies the parameter, if that has + meaning for an individual command. */ +#define EC_GSV_PARAM_MASK 0x00ffffff + +struct ec_params_get_set_value { + uint32_t flags; + uint32_t value; +} __packed; + +struct ec_response_get_set_value { + uint32_t flags; + uint32_t value; +} __packed; + +/* More than one command can use these structs to get/set paramters. */ +#define EC_CMD_GSV_PAUSE_IN_S5 0x0c + /*****************************************************************************/ /* Flash commands */ @@ -425,6 +720,7 @@ struct ec_response_get_comms_status { /* Get flash info */ #define EC_CMD_FLASH_INFO 0x10 +/* Version 0 returns these fields */ struct ec_response_flash_info { /* Usable flash size, in bytes */ uint32_t flash_size; @@ -445,6 +741,37 @@ struct ec_response_flash_info { uint32_t protect_block_size; } __packed; +/* Flags for version 1+ flash info command */ +/* EC flash erases bits to 0 instead of 1 */ +#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0) + +/* + * Version 1 returns the same initial fields as version 0, with additional + * fields following. + * + * gcc anonymous structs don't seem to get along with the __packed directive; + * if they did we'd define the version 0 struct as a sub-struct of this one. + */ +struct ec_response_flash_info_1 { + /* Version 0 fields; see above for description */ + uint32_t flash_size; + uint32_t write_block_size; + uint32_t erase_block_size; + uint32_t protect_block_size; + + /* Version 1 adds these fields: */ + /* + * Ideal write size in bytes. Writes will be fastest if size is + * exactly this and offset is a multiple of this. For example, an EC + * may have a write buffer which can do half-page operations if data is + * aligned, and a slower word-at-a-time write mode. + */ + uint32_t write_ideal_size; + + /* Flags; see EC_FLASH_INFO_* */ + uint32_t flags; +} __packed; + /* * Read flash * @@ -459,15 +786,15 @@ struct ec_params_flash_read { /* Write flash */ #define EC_CMD_FLASH_WRITE 0x12 +#define EC_VER_FLASH_WRITE 1 + +/* Version 0 of the flash command supported only 64 bytes of data */ +#define EC_FLASH_WRITE_VER0_SIZE 64 struct ec_params_flash_write { uint32_t offset; /* Byte offset to write */ uint32_t size; /* Size to write in bytes */ - /* - * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to - * use a power of 2 so writes stay aligned. - */ - uint8_t data[64]; + /* Followed by data to write */ } __packed; /* Erase flash */ @@ -543,7 +870,7 @@ struct ec_response_flash_protect { enum ec_flash_region { /* Region which holds read-only EC image */ - EC_FLASH_REGION_RO, + EC_FLASH_REGION_RO = 0, /* Region which holds rewritable EC image */ EC_FLASH_REGION_RW, /* @@ -551,6 +878,8 @@ enum ec_flash_region { * EC_FLASH_REGION_RO) */ EC_FLASH_REGION_WP_RO, + /* Number of regions */ + EC_FLASH_REGION_COUNT, }; struct ec_params_flash_region_info { @@ -639,15 +968,15 @@ struct rgb_s { */ struct lightbar_params { /* Timing */ - int google_ramp_up; - int google_ramp_down; - int s3s0_ramp_up; - int s0_tick_delay[2]; /* AC=0/1 */ - int s0a_tick_delay[2]; /* AC=0/1 */ - int s0s3_ramp_down; - int s3_sleep_for; - int s3_ramp_up; - int s3_ramp_down; + int32_t google_ramp_up; + int32_t google_ramp_down; + int32_t s3s0_ramp_up; + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0s3_ramp_down; + int32_t s3_sleep_for; + int32_t s3_ramp_up; + int32_t s3_ramp_down; /* Oscillation */ uint8_t new_s0; @@ -676,7 +1005,7 @@ struct ec_params_lightbar { union { struct { /* no args */ - } dump, off, on, init, get_seq, get_params; + } dump, off, on, init, get_seq, get_params, version; struct num { uint8_t num; @@ -710,6 +1039,11 @@ struct ec_response_lightbar { struct lightbar_params get_params; + struct version { + uint32_t num; + uint32_t flags; + } version; + struct { /* no return params */ } off, on, init, brightness, seq, reg, rgb, demo, set_params; @@ -730,9 +1064,61 @@ enum lightbar_command { LIGHTBAR_CMD_DEMO = 9, LIGHTBAR_CMD_GET_PARAMS = 10, LIGHTBAR_CMD_SET_PARAMS = 11, + LIGHTBAR_CMD_VERSION = 12, LIGHTBAR_NUM_CMDS }; +/*****************************************************************************/ +/* LED control commands */ + +#define EC_CMD_LED_CONTROL 0x29 + +enum ec_led_id { + /* LED to indicate battery state of charge */ + EC_LED_ID_BATTERY_LED = 0, + /* + * LED to indicate system power state (on or in suspend). + * May be on power button or on C-panel. + */ + EC_LED_ID_POWER_LED, + /* LED on power adapter or its plug */ + EC_LED_ID_ADAPTER_LED, + + EC_LED_ID_COUNT +}; + +/* LED control flags */ +#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ + +enum ec_led_colors { + EC_LED_COLOR_RED = 0, + EC_LED_COLOR_GREEN, + EC_LED_COLOR_BLUE, + EC_LED_COLOR_YELLOW, + EC_LED_COLOR_WHITE, + + EC_LED_COLOR_COUNT +}; + +struct ec_params_led_control { + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ + + uint8_t brightness[EC_LED_COLOR_COUNT]; +} __packed; + +struct ec_response_led_control { + /* + * Available brightness value range. + * + * Range 0 means color channel not present. + * Range 1 means on/off control. + * Other values means the LED is control by PWM. + */ + uint8_t brightness_range[EC_LED_COLOR_COUNT]; +} __packed; + /*****************************************************************************/ /* Verified boot commands */ @@ -789,6 +1175,181 @@ enum ec_vboot_hash_status { #define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe #define EC_VBOOT_HASH_OFFSET_RW 0xfffffffd +/*****************************************************************************/ +/* + * Motion sense commands. We'll make separate structs for sub-commands with + * different input args, so that we know how much to expect. + */ +#define EC_CMD_MOTION_SENSE_CMD 0x2B + +/* Motion sense commands */ +enum motionsense_command { + /* + * Dump command returns all motion sensor data including motion sense + * module flags and individual sensor flags. + */ + MOTIONSENSE_CMD_DUMP = 0, + + /* + * Info command returns data describing the details of a given sensor, + * including enum motionsensor_type, enum motionsensor_location, and + * enum motionsensor_chip. + */ + MOTIONSENSE_CMD_INFO = 1, + + /* + * EC Rate command is a setter/getter command for the EC sampling rate + * of all motion sensors in milliseconds. + */ + MOTIONSENSE_CMD_EC_RATE = 2, + + /* + * Sensor ODR command is a setter/getter command for the output data + * rate of a specific motion sensor in millihertz. + */ + MOTIONSENSE_CMD_SENSOR_ODR = 3, + + /* + * Sensor range command is a setter/getter command for the range of + * a specified motion sensor in +/-G's or +/- deg/s. + */ + MOTIONSENSE_CMD_SENSOR_RANGE = 4, + + /* + * Setter/getter command for the keyboard wake angle. When the lid + * angle is greater than this value, keyboard wake is disabled in S3, + * and when the lid angle goes less than this value, keyboard wake is + * enabled. Note, the lid angle measurement is an approximate, + * un-calibrated value, hence the wake angle isn't exact. + */ + MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5, + + /* Number of motionsense sub-commands. */ + MOTIONSENSE_NUM_CMDS +}; + +enum motionsensor_id { + EC_MOTION_SENSOR_ACCEL_BASE = 0, + EC_MOTION_SENSOR_ACCEL_LID = 1, + EC_MOTION_SENSOR_GYRO = 2, + + /* + * Note, if more sensors are added and this count changes, the padding + * in ec_response_motion_sense dump command must be modified. + */ + EC_MOTION_SENSOR_COUNT = 3 +}; + +/* List of motion sensor types. */ +enum motionsensor_type { + MOTIONSENSE_TYPE_ACCEL = 0, + MOTIONSENSE_TYPE_GYRO = 1, +}; + +/* List of motion sensor locations. */ +enum motionsensor_location { + MOTIONSENSE_LOC_BASE = 0, + MOTIONSENSE_LOC_LID = 1, +}; + +/* List of motion sensor chips. */ +enum motionsensor_chip { + MOTIONSENSE_CHIP_KXCJ9 = 0, +}; + +/* Module flag masks used for the dump sub-command. */ +#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0) + +/* Sensor flag masks used for the dump sub-command. */ +#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0) + +/* + * Send this value for the data element to only perform a read. If you + * send any other value, the EC will interpret it as data to set and will + * return the actual value set. + */ +#define EC_MOTION_SENSE_NO_VALUE -1 + +struct ec_params_motion_sense { + uint8_t cmd; + union { + /* Used for MOTIONSENSE_CMD_DUMP. */ + struct { + /* no args */ + } dump; + + /* + * Used for MOTIONSENSE_CMD_EC_RATE and + * MOTIONSENSE_CMD_KB_WAKE_ANGLE. + */ + struct { + /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */ + int16_t data; + } ec_rate, kb_wake_angle; + + /* Used for MOTIONSENSE_CMD_INFO. */ + struct { + /* Should be element of enum motionsensor_id. */ + uint8_t sensor_num; + } info; + + /* + * Used for MOTIONSENSE_CMD_SENSOR_ODR and + * MOTIONSENSE_CMD_SENSOR_RANGE. + */ + struct { + /* Should be element of enum motionsensor_id. */ + uint8_t sensor_num; + + /* Rounding flag, true for round-up, false for down. */ + uint8_t roundup; + + uint16_t reserved; + + /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */ + int32_t data; + } sensor_odr, sensor_range; + }; +} __packed; + +struct ec_response_motion_sense { + union { + /* Used for MOTIONSENSE_CMD_DUMP. */ + struct { + /* Flags representing the motion sensor module. */ + uint8_t module_flags; + + /* Flags for each sensor in enum motionsensor_id. */ + uint8_t sensor_flags[EC_MOTION_SENSOR_COUNT]; + + /* Array of all sensor data. Each sensor is 3-axis. */ + int16_t data[3*EC_MOTION_SENSOR_COUNT]; + } dump; + + /* Used for MOTIONSENSE_CMD_INFO. */ + struct { + /* Should be element of enum motionsensor_type. */ + uint8_t type; + + /* Should be element of enum motionsensor_location. */ + uint8_t location; + + /* Should be element of enum motionsensor_chip. */ + uint8_t chip; + } info; + + /* + * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR, + * MOTIONSENSE_CMD_SENSOR_RANGE, and + * MOTIONSENSE_CMD_KB_WAKE_ANGLE. + */ + struct { + /* Current value of the parameter queried. */ + int32_t ret; + } ec_rate, sensor_odr, sensor_range, kb_wake_angle; + }; +} __packed; + /*****************************************************************************/ /* USB charging control commands */ @@ -868,20 +1429,27 @@ struct ec_response_port80_last_boot { } __packed; /*****************************************************************************/ -/* Thermal engine commands */ +/* Thermal engine commands. Note that there are two implementations. We'll + * reuse the command number, but the data and behavior is incompatible. + * Version 0 is what originally shipped on Link. + * Version 1 separates the CPU thermal limits from the fan control. + */ -/* Set thershold value */ #define EC_CMD_THERMAL_SET_THRESHOLD 0x50 +#define EC_CMD_THERMAL_GET_THRESHOLD 0x51 + +/* The version 0 structs are opaque. You have to know what they are for + * the get/set commands to make any sense. + */ +/* Version 0 - set */ struct ec_params_thermal_set_threshold { uint8_t sensor_type; uint8_t threshold_id; uint16_t value; } __packed; -/* Get threshold value */ -#define EC_CMD_THERMAL_GET_THRESHOLD 0x51 - +/* Version 0 - get */ struct ec_params_thermal_get_threshold { uint8_t sensor_type; uint8_t threshold_id; @@ -891,6 +1459,41 @@ struct ec_response_thermal_get_threshold { uint16_t value; } __packed; + +/* The version 1 structs are visible. */ +enum ec_temp_thresholds { + EC_TEMP_THRESH_WARN = 0, + EC_TEMP_THRESH_HIGH, + EC_TEMP_THRESH_HALT, + + EC_TEMP_THRESH_COUNT +}; + +/* Thermal configuration for one temperature sensor. Temps are in degrees K. + * Zero values will be silently ignored by the thermal task. + */ +struct ec_thermal_config { + uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ + uint32_t temp_fan_off; /* no active cooling needed */ + uint32_t temp_fan_max; /* max active cooling needed */ +} __packed; + +/* Version 1 - get config for one sensor. */ +struct ec_params_thermal_get_threshold_v1 { + uint32_t sensor_num; +} __packed; +/* This returns a struct ec_thermal_config */ + +/* Version 1 - set config for one sensor. + * Use read-modify-write for best results! */ +struct ec_params_thermal_set_threshold_v1 { + uint32_t sensor_num; + struct ec_thermal_config cfg; +} __packed; +/* This returns no data */ + +/****************************************************************************/ + /* Toggle automatic fan control */ #define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x52 @@ -920,6 +1523,18 @@ struct ec_params_tmp006_set_calibration { float b2; } __packed; +/* Read raw TMP006 data */ +#define EC_CMD_TMP006_GET_RAW 0x55 + +struct ec_params_tmp006_get_raw { + uint8_t index; +} __packed; + +struct ec_response_tmp006_get_raw { + int32_t t; /* In 1/100 K */ + int32_t v; /* In nV */ +}; + /*****************************************************************************/ /* MKBP - Matrix KeyBoard Protocol */ @@ -1118,11 +1733,41 @@ struct ec_params_switch_enable_backlight { /* Enable/disable WLAN/Bluetooth */ #define EC_CMD_SWITCH_ENABLE_WIRELESS 0x91 +#define EC_VER_SWITCH_ENABLE_WIRELESS 1 -struct ec_params_switch_enable_wireless { +/* Version 0 params; no response */ +struct ec_params_switch_enable_wireless_v0 { uint8_t enabled; } __packed; +/* Version 1 params */ +struct ec_params_switch_enable_wireless_v1 { + /* Flags to enable now */ + uint8_t now_flags; + + /* Which flags to copy from now_flags */ + uint8_t now_mask; + + /* + * Flags to leave enabled in S3, if they're on at the S0->S3 + * transition. (Other flags will be disabled by the S0->S3 + * transition.) + */ + uint8_t suspend_flags; + + /* Which flags to copy from suspend_flags */ + uint8_t suspend_mask; +} __packed; + +/* Version 1 response */ +struct ec_response_switch_enable_wireless_v1 { + /* Flags to enable now */ + uint8_t now_flags; + + /* Flags to leave enabled in S3 */ + uint8_t suspend_flags; +} __packed; + /*****************************************************************************/ /* GPIO commands. Only available on EC if write protect has been disabled. */ @@ -1147,11 +1792,16 @@ struct ec_response_gpio_get { /*****************************************************************************/ /* I2C commands. Only available when flash write protect is unlocked. */ +/* + * TODO(crosbug.com/p/23570): These commands are deprecated, and will be + * removed soon. Use EC_CMD_I2C_XFER instead. + */ + /* Read I2C bus */ #define EC_CMD_I2C_READ 0x94 struct ec_params_i2c_read { - uint16_t addr; + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t read_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; @@ -1165,7 +1815,7 @@ struct ec_response_i2c_read { struct ec_params_i2c_write { uint16_t data; - uint16_t addr; + uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t write_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; @@ -1174,11 +1824,20 @@ struct ec_params_i2c_write { /*****************************************************************************/ /* Charge state commands. Only available when flash write protect unlocked. */ -/* Force charge state machine to stop in idle mode */ -#define EC_CMD_CHARGE_FORCE_IDLE 0x96 +/* Force charge state machine to stop charging the battery or force it to + * discharge the battery. + */ +#define EC_CMD_CHARGE_CONTROL 0x96 +#define EC_VER_CHARGE_CONTROL 1 -struct ec_params_force_idle { - uint8_t enabled; +enum ec_charge_control_mode { + CHARGE_CONTROL_NORMAL = 0, + CHARGE_CONTROL_IDLE, + CHARGE_CONTROL_DISCHARGE, +}; + +struct ec_params_charge_control { + uint32_t mode; /* enum charge_control_mode */ } __packed; /*****************************************************************************/ @@ -1206,14 +1865,231 @@ struct ec_params_force_idle { #define EC_CMD_BATTERY_CUT_OFF 0x99 /*****************************************************************************/ -/* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */ +/* USB port mux control. */ /* - * Dump charge state machine context. - * - * Response is a binary dump of charge state machine context. + * Switch USB mux or return to automatic switching. + */ +#define EC_CMD_USB_MUX 0x9a + +struct ec_params_usb_mux { + uint8_t mux; +} __packed; + +/*****************************************************************************/ +/* LDOs / FETs control. */ + +enum ec_ldo_state { + EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ + EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ +}; + +/* + * Switch on/off a LDO. + */ +#define EC_CMD_LDO_SET 0x9b + +struct ec_params_ldo_set { + uint8_t index; + uint8_t state; +} __packed; + +/* + * Get LDO state. + */ +#define EC_CMD_LDO_GET 0x9c + +struct ec_params_ldo_get { + uint8_t index; +} __packed; + +struct ec_response_ldo_get { + uint8_t state; +} __packed; + +/*****************************************************************************/ +/* Power info. */ + +/* + * Get power info. + */ +#define EC_CMD_POWER_INFO 0x9d + +struct ec_response_power_info { + uint32_t usb_dev_type; + uint16_t voltage_ac; + uint16_t voltage_system; + uint16_t current_system; + uint16_t usb_current_limit; +} __packed; + +/*****************************************************************************/ +/* I2C passthru command */ + +#define EC_CMD_I2C_PASSTHRU 0x9e + +/* Slave address is 10 (not 7) bit */ +#define EC_I2C_FLAG_10BIT (1 << 16) + +/* Read data; if not present, message is a write */ +#define EC_I2C_FLAG_READ (1 << 15) + +/* Mask for address */ +#define EC_I2C_ADDR_MASK 0x3ff + +#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ + +/* Any error */ +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) + +struct ec_params_i2c_passthru_msg { + uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ + uint16_t len; /* Number of bytes to read or write */ +} __packed; + +struct ec_params_i2c_passthru { + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ + struct ec_params_i2c_passthru_msg msg[]; + /* Data to write for all messages is concatenated here */ +} __packed; + +struct ec_response_i2c_passthru { + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + uint8_t data[]; /* Data read by messages concatenated here */ +} __packed; + +/*****************************************************************************/ +/* Power button hang detect */ + +#define EC_CMD_HANG_DETECT 0x9f + +/* Reasons to start hang detection timer */ +/* Power button pressed */ +#define EC_HANG_START_ON_POWER_PRESS (1 << 0) + +/* Lid closed */ +#define EC_HANG_START_ON_LID_CLOSE (1 << 1) + + /* Lid opened */ +#define EC_HANG_START_ON_LID_OPEN (1 << 2) + +/* Start of AP S3->S0 transition (booting or resuming from suspend) */ +#define EC_HANG_START_ON_RESUME (1 << 3) + +/* Reasons to cancel hang detection */ + +/* Power button released */ +#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8) + +/* Any host command from AP received */ +#define EC_HANG_STOP_ON_HOST_COMMAND (1 << 9) + +/* Stop on end of AP S0->S3 transition (suspending or shutting down) */ +#define EC_HANG_STOP_ON_SUSPEND (1 << 10) + +/* + * If this flag is set, all the other fields are ignored, and the hang detect + * timer is started. This provides the AP a way to start the hang timer + * without reconfiguring any of the other hang detect settings. Note that + * you must previously have configured the timeouts. + */ +#define EC_HANG_START_NOW (1 << 30) + +/* + * If this flag is set, all the other fields are ignored (including + * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer + * without reconfiguring any of the other hang detect settings. */ -#define EC_CMD_CHARGE_DUMP 0xa0 +#define EC_HANG_STOP_NOW (1 << 31) + +struct ec_params_hang_detect { + /* Flags; see EC_HANG_* */ + uint32_t flags; + + /* Timeout in msec before generating host event, if enabled */ + uint16_t host_event_timeout_msec; + + /* Timeout in msec before generating warm reboot, if enabled */ + uint16_t warm_reboot_timeout_msec; +} __packed; + +/*****************************************************************************/ +/* Commands for battery charging */ + +/* + * This is the single catch-all host command to exchange data regarding the + * charge state machine (v2 and up). + */ +#define EC_CMD_CHARGE_STATE 0xa0 + +/* Subcommands for this host command */ +enum charge_state_command { + CHARGE_STATE_CMD_GET_STATE, + CHARGE_STATE_CMD_GET_PARAM, + CHARGE_STATE_CMD_SET_PARAM, + CHARGE_STATE_NUM_CMDS +}; + +/* + * Known param numbers are defined here. Ranges are reserved for board-specific + * params, which are handled by the particular implementations. + */ +enum charge_state_params { + CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */ + CS_PARAM_CHG_CURRENT, /* charger current limit */ + CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ + CS_PARAM_CHG_STATUS, /* charger-specific status */ + CS_PARAM_CHG_OPTION, /* charger-specific options */ + /* How many so far? */ + CS_NUM_BASE_PARAMS, + + /* Range for CONFIG_CHARGER_PROFILE_OVERRIDE params */ + CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000, + CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff, + + /* Other custom param ranges go here... */ +}; + +struct ec_params_charge_state { + uint8_t cmd; /* enum charge_state_command */ + union { + struct { + /* no args */ + } get_state; + + struct { + uint32_t param; /* enum charge_state_param */ + } get_param; + + struct { + uint32_t param; /* param to set */ + uint32_t value; /* value to set */ + } set_param; + }; +} __packed; + +struct ec_response_charge_state { + union { + struct { + int ac; + int chg_voltage; + int chg_current; + int chg_input_current; + int batt_state_of_charge; + } get_state; + + struct { + uint32_t value; + } get_param; + struct { + /* no return values */ + } set_param; + }; +} __packed; + /* * Set maximum battery charging current. @@ -1221,15 +2097,59 @@ struct ec_params_force_idle { #define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1 struct ec_params_current_limit { - uint32_t limit; + uint32_t limit; /* in mA */ +} __packed; + +/* + * Set maximum external power current. + */ +#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2 + +struct ec_params_ext_power_current_limit { + uint32_t limit; /* in mA */ +} __packed; + +/*****************************************************************************/ +/* Smart battery pass-through */ + +/* Get / Set 16-bit smart battery registers */ +#define EC_CMD_SB_READ_WORD 0xb0 +#define EC_CMD_SB_WRITE_WORD 0xb1 + +/* Get / Set string smart battery parameters + * formatted as SMBUS "block". + */ +#define EC_CMD_SB_READ_BLOCK 0xb2 +#define EC_CMD_SB_WRITE_BLOCK 0xb3 + +struct ec_params_sb_rd { + uint8_t reg; +} __packed; + +struct ec_response_sb_rd_word { + uint16_t value; +} __packed; + +struct ec_params_sb_wr_word { + uint8_t reg; + uint16_t value; +} __packed; + +struct ec_response_sb_rd_block { + uint8_t data[32]; +} __packed; + +struct ec_params_sb_wr_block { + uint8_t reg; + uint16_t data[32]; } __packed; /*****************************************************************************/ /* System commands */ /* - * TODO: this is a confusing name, since it doesn't necessarily reboot the EC. - * Rename to "set image" or something similar. + * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't + * necessarily reboot the EC. Rename to "image" or something similar? */ #define EC_CMD_REBOOT_EC 0xd2 @@ -1308,6 +2228,7 @@ struct ec_params_reboot_ec { #define EC_CMD_ACPI_QUERY_EVENT 0x84 /* Valid addresses in ACPI memory space, for read/write commands */ + /* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ #define EC_ACPI_MEM_VERSION 0x00 /* @@ -1317,8 +2238,60 @@ struct ec_params_reboot_ec { #define EC_ACPI_MEM_TEST 0x01 /* Test compliment; writes here are ignored. */ #define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 + /* Keyboard backlight brightness percent (0 - 100) */ #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 +/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ +#define EC_ACPI_MEM_FAN_DUTY 0x04 + +/* + * DPTF temp thresholds. Any of the EC's temp sensors can have up to two + * independent thresholds attached to them. The current value of the ID + * register determines which sensor is affected by the THRESHOLD and COMMIT + * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme + * as the memory-mapped sensors. The COMMIT register applies those settings. + * + * The spec does not mandate any way to read back the threshold settings + * themselves, but when a threshold is crossed the AP needs a way to determine + * which sensor(s) are responsible. Each reading of the ID register clears and + * returns one sensor ID that has crossed one of its threshold (in either + * direction) since the last read. A value of 0xFF means "no new thresholds + * have tripped". Setting or enabling the thresholds for a sensor will clear + * the unread event count for that sensor. + */ +#define EC_ACPI_MEM_TEMP_ID 0x05 +#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 +#define EC_ACPI_MEM_TEMP_COMMIT 0x07 +/* + * Here are the bits for the COMMIT register: + * bit 0 selects the threshold index for the chosen sensor (0/1) + * bit 1 enables/disables the selected threshold (0 = off, 1 = on) + * Each write to the commit register affects one threshold. + */ +#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0) +#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1) +/* + * Example: + * + * Set the thresholds for sensor 2 to 50 C and 60 C: + * write 2 to [0x05] -- select temp sensor 2 + * write 0x7b to [0x06] -- C_TO_K(50) - EC_TEMP_SENSOR_OFFSET + * write 0x2 to [0x07] -- enable threshold 0 with this value + * write 0x85 to [0x06] -- C_TO_K(60) - EC_TEMP_SENSOR_OFFSET + * write 0x3 to [0x07] -- enable threshold 1 with this value + * + * Disable the 60 C threshold, leaving the 50 C threshold unchanged: + * write 2 to [0x05] -- select temp sensor 2 + * write 0x1 to [0x07] -- disable threshold 1 + */ + +/* DPTF battery charging current limit */ +#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 + +/* Charging limit is specified in 64 mA steps */ +#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 +/* Value to disable DPTF battery charging limit */ +#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff /* Current version of ACPI memory address space */ #define EC_ACPI_MEM_VERSION_CURRENT 1 @@ -1360,10 +2333,21 @@ struct ec_params_reboot_ec { * Header bytes greater than this indicate a later version. For example, * EC_CMD_VERSION0 + 1 means we are using version 1. * - * The old EC interface must not use commands 0dc or higher. + * The old EC interface must not use commands 0xdc or higher. */ #define EC_CMD_VERSION0 0xdc #endif /* !__ACPI__ */ +/*****************************************************************************/ +/* + * Deprecated constants. These constants have been renamed for clarity. The + * meaning and size has not changed. Programs that use the old names should + * switch to the new names soon, as the old names may not be carried forward + * forever. + */ +#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE +#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 +#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE + #endif /* __CROS_EC_COMMANDS_H */ -- cgit v1.2.2 From a9cd92acabcb8aca8431647005ed868b8c7644c9 Mon Sep 17 00:00:00 2001 From: Richard Fitzgerald Date: Tue, 20 May 2014 13:48:51 +0100 Subject: mfd: arizona: Correct addresses of always-on trigger registers Update the addresses and names to match current silicon. The WM8997 regmap tables have been adjusted to match the new names. Missing registers have been added to WM5110 default value table. Signed-off-by: Richard Fitzgerald Signed-off-by: Lee Jones --- include/linux/mfd/arizona/registers.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h index 7b35c21170d5..7204d8138b24 100644 --- a/include/linux/mfd/arizona/registers.h +++ b/include/linux/mfd/arizona/registers.h @@ -42,12 +42,14 @@ #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64 -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68 -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69 -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x66 +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x67 +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x68 +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x69 +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6A +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6B +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_7 0x6C +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_8 0x6D #define ARIZONA_COMFORT_NOISE_GENERATOR 0x70 #define ARIZONA_HAPTICS_CONTROL_1 0x90 #define ARIZONA_HAPTICS_CONTROL_2 0x91 -- cgit v1.2.2 From a22c514c6a8bf21663b2e0a5339cc461be2f01a2 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 22 May 2014 09:50:57 +0100 Subject: mfd: abx500-core: Remove unused function abx500_dump_all_banks() abx500_dump_all_banks() has no callers in the kernel, so it's probably safe to remove it. Cc: Linus Walleij Signed-off-by: Lee Jones --- include/linux/mfd/abx500.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index df2508f7f3d2..552cc1d61cc7 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -330,7 +330,6 @@ int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank, int abx500_get_chip_id(struct device *dev); int abx500_event_registers_startup_state_get(struct device *dev, u8 *event); int abx500_startup_irq_enabled(struct device *dev, unsigned int irq); -int abx500_dump_all_banks(void); struct abx500_ops { int (*get_chip_id) (struct device *); -- cgit v1.2.2 From 45ac60c0bc93f64c3fe64de8308c8e4bd67ac165 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Thu, 22 May 2014 14:48:30 +0530 Subject: mfd: palmas: Format the header file Formats the palmas header file. Convert all the offset values to hexadecimal. Signed-off-by: Keerthy Signed-off-by: Lee Jones --- include/linux/mfd/palmas.h | 2166 ++++++++++++++++++++++---------------------- 1 file changed, 1083 insertions(+), 1083 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h index 9974e387e483..ccbb21f718ed 100644 --- a/include/linux/mfd/palmas.h +++ b/include/linux/mfd/palmas.h @@ -482,10 +482,10 @@ enum usb_irq_events { /* helper macro to get correct slave number */ #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) -#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) +#define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y) /* Base addresses of IP blocks in Palmas */ -#define PALMAS_SMPS_DVS_BASE 0x20 +#define PALMAS_SMPS_DVS_BASE 0x020 #define PALMAS_RTC_BASE 0x100 #define PALMAS_VALIDITY_BASE 0x118 #define PALMAS_SMPS_BASE 0x120 @@ -504,19 +504,19 @@ enum usb_irq_events { #define PALMAS_TRIM_GPADC_BASE 0x3CD /* Registers for function RTC */ -#define PALMAS_SECONDS_REG 0x0 -#define PALMAS_MINUTES_REG 0x1 -#define PALMAS_HOURS_REG 0x2 -#define PALMAS_DAYS_REG 0x3 -#define PALMAS_MONTHS_REG 0x4 -#define PALMAS_YEARS_REG 0x5 -#define PALMAS_WEEKS_REG 0x6 -#define PALMAS_ALARM_SECONDS_REG 0x8 -#define PALMAS_ALARM_MINUTES_REG 0x9 -#define PALMAS_ALARM_HOURS_REG 0xA -#define PALMAS_ALARM_DAYS_REG 0xB -#define PALMAS_ALARM_MONTHS_REG 0xC -#define PALMAS_ALARM_YEARS_REG 0xD +#define PALMAS_SECONDS_REG 0x00 +#define PALMAS_MINUTES_REG 0x01 +#define PALMAS_HOURS_REG 0x02 +#define PALMAS_DAYS_REG 0x03 +#define PALMAS_MONTHS_REG 0x04 +#define PALMAS_YEARS_REG 0x05 +#define PALMAS_WEEKS_REG 0x06 +#define PALMAS_ALARM_SECONDS_REG 0x08 +#define PALMAS_ALARM_MINUTES_REG 0x09 +#define PALMAS_ALARM_HOURS_REG 0x0A +#define PALMAS_ALARM_DAYS_REG 0x0B +#define PALMAS_ALARM_MONTHS_REG 0x0C +#define PALMAS_ALARM_YEARS_REG 0x0D #define PALMAS_RTC_CTRL_REG 0x10 #define PALMAS_RTC_STATUS_REG 0x11 #define PALMAS_RTC_INTERRUPTS_REG 0x12 @@ -527,201 +527,201 @@ enum usb_irq_events { /* Bit definitions for SECONDS_REG */ #define PALMAS_SECONDS_REG_SEC1_MASK 0x70 -#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 -#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f -#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 +#define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04 +#define PALMAS_SECONDS_REG_SEC0_MASK 0x0F +#define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00 /* Bit definitions for MINUTES_REG */ #define PALMAS_MINUTES_REG_MIN1_MASK 0x70 -#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 -#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f -#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 +#define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04 +#define PALMAS_MINUTES_REG_MIN0_MASK 0x0F +#define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00 /* Bit definitions for HOURS_REG */ #define PALMAS_HOURS_REG_PM_NAM 0x80 -#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 +#define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30 -#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 -#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f -#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 +#define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04 +#define PALMAS_HOURS_REG_HOUR0_MASK 0x0F +#define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00 /* Bit definitions for DAYS_REG */ #define PALMAS_DAYS_REG_DAY1_MASK 0x30 -#define PALMAS_DAYS_REG_DAY1_SHIFT 4 -#define PALMAS_DAYS_REG_DAY0_MASK 0x0f -#define PALMAS_DAYS_REG_DAY0_SHIFT 0 +#define PALMAS_DAYS_REG_DAY1_SHIFT 0x04 +#define PALMAS_DAYS_REG_DAY0_MASK 0x0F +#define PALMAS_DAYS_REG_DAY0_SHIFT 0x00 /* Bit definitions for MONTHS_REG */ #define PALMAS_MONTHS_REG_MONTH1 0x10 -#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 -#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f -#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 +#define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04 +#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F +#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00 /* Bit definitions for YEARS_REG */ #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 -#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 -#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f -#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 +#define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04 +#define PALMAS_YEARS_REG_YEAR0_MASK 0x0F +#define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00 /* Bit definitions for WEEKS_REG */ #define PALMAS_WEEKS_REG_WEEK_MASK 0x07 -#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 +#define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00 /* Bit definitions for ALARM_SECONDS_REG */ #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 -#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 -#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f -#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04 +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F +#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00 /* Bit definitions for ALARM_MINUTES_REG */ #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 -#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 -#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f -#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04 +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F +#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00 /* Bit definitions for ALARM_HOURS_REG */ #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 -#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 +#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 -#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 -#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f -#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04 +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F +#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00 /* Bit definitions for ALARM_DAYS_REG */ #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 -#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 -#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f -#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04 +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F +#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00 /* Bit definitions for ALARM_MONTHS_REG */ #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 -#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 -#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f -#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04 +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F +#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00 /* Bit definitions for ALARM_YEARS_REG */ #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 -#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 -#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f -#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04 +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F +#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00 /* Bit definitions for RTC_CTRL_REG */ #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 -#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 +#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 -#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 +#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 -#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 +#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 -#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 +#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 -#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 +#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 -#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 +#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 -#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 +#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 -#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 +#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00 /* Bit definitions for RTC_STATUS_REG */ #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 -#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 +#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07 #define PALMAS_RTC_STATUS_REG_ALARM 0x40 -#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 +#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 -#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 +#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 -#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 +#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 -#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 +#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 -#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 +#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02 #define PALMAS_RTC_STATUS_REG_RUN 0x02 -#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 +#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01 /* Bit definitions for RTC_INTERRUPTS_REG */ #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 -#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 +#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 -#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 +#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 -#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 +#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 -#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 +#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00 /* Bit definitions for RTC_COMP_LSB_REG */ -#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff -#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 +#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF +#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00 /* Bit definitions for RTC_COMP_MSB_REG */ -#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff -#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 +#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF +#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00 /* Bit definitions for RTC_RES_PROG_REG */ -#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f -#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 +#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F +#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00 /* Bit definitions for RTC_RESET_STATUS_REG */ #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 -#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 +#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00 /* Registers for function BACKUP */ -#define PALMAS_BACKUP0 0x0 -#define PALMAS_BACKUP1 0x1 -#define PALMAS_BACKUP2 0x2 -#define PALMAS_BACKUP3 0x3 -#define PALMAS_BACKUP4 0x4 -#define PALMAS_BACKUP5 0x5 -#define PALMAS_BACKUP6 0x6 -#define PALMAS_BACKUP7 0x7 +#define PALMAS_BACKUP0 0x00 +#define PALMAS_BACKUP1 0x01 +#define PALMAS_BACKUP2 0x02 +#define PALMAS_BACKUP3 0x03 +#define PALMAS_BACKUP4 0x04 +#define PALMAS_BACKUP5 0x05 +#define PALMAS_BACKUP6 0x06 +#define PALMAS_BACKUP7 0x07 /* Bit definitions for BACKUP0 */ -#define PALMAS_BACKUP0_BACKUP_MASK 0xff -#define PALMAS_BACKUP0_BACKUP_SHIFT 0 +#define PALMAS_BACKUP0_BACKUP_MASK 0xFF +#define PALMAS_BACKUP0_BACKUP_SHIFT 0x00 /* Bit definitions for BACKUP1 */ -#define PALMAS_BACKUP1_BACKUP_MASK 0xff -#define PALMAS_BACKUP1_BACKUP_SHIFT 0 +#define PALMAS_BACKUP1_BACKUP_MASK 0xFF +#define PALMAS_BACKUP1_BACKUP_SHIFT 0x00 /* Bit definitions for BACKUP2 */ -#define PALMAS_BACKUP2_BACKUP_MASK 0xff -#define PALMAS_BACKUP2_BACKUP_SHIFT 0 +#define PALMAS_BACKUP2_BACKUP_MASK 0xFF +#define PALMAS_BACKUP2_BACKUP_SHIFT 0x00 /* Bit definitions for BACKUP3 */ -#define PALMAS_BACKUP3_BACKUP_MASK 0xff -#define PALMAS_BACKUP3_BACKUP_SHIFT 0 +#define PALMAS_BACKUP3_BACKUP_MASK 0xFF +#define PALMAS_BACKUP3_BACKUP_SHIFT 0x00 /* Bit definitions for BACKUP4 */ -#define PALMAS_BACKUP4_BACKUP_MASK 0xff -#define PALMAS_BACKUP4_BACKUP_SHIFT 0 +#define PALMAS_BACKUP4_BACKUP_MASK 0xFF +#define PALMAS_BACKUP4_BACKUP_SHIFT 0x00 /* Bit definitions for BACKUP5 */ -#define PALMAS_BACKUP5_BACKUP_MASK 0xff -#define PALMAS_BACKUP5_BACKUP_SHIFT 0 +#define PALMAS_BACKUP5_BACKUP_MASK 0xFF +#define PALMAS_BACKUP5_BACKUP_SHIFT 0x00 /* Bit definitions for BACKUP6 */ -#define PALMAS_BACKUP6_BACKUP_MASK 0xff -#define PALMAS_BACKUP6_BACKUP_SHIFT 0 +#define PALMAS_BACKUP6_BACKUP_MASK 0xFF +#define PALMAS_BACKUP6_BACKUP_SHIFT 0x00 /* Bit definitions for BACKUP7 */ -#define PALMAS_BACKUP7_BACKUP_MASK 0xff -#define PALMAS_BACKUP7_BACKUP_SHIFT 0 +#define PALMAS_BACKUP7_BACKUP_MASK 0xFF +#define PALMAS_BACKUP7_BACKUP_SHIFT 0x00 /* Registers for function SMPS */ -#define PALMAS_SMPS12_CTRL 0x0 -#define PALMAS_SMPS12_TSTEP 0x1 -#define PALMAS_SMPS12_FORCE 0x2 -#define PALMAS_SMPS12_VOLTAGE 0x3 -#define PALMAS_SMPS3_CTRL 0x4 -#define PALMAS_SMPS3_VOLTAGE 0x7 -#define PALMAS_SMPS45_CTRL 0x8 -#define PALMAS_SMPS45_TSTEP 0x9 -#define PALMAS_SMPS45_FORCE 0xA -#define PALMAS_SMPS45_VOLTAGE 0xB -#define PALMAS_SMPS6_CTRL 0xC -#define PALMAS_SMPS6_TSTEP 0xD -#define PALMAS_SMPS6_FORCE 0xE -#define PALMAS_SMPS6_VOLTAGE 0xF +#define PALMAS_SMPS12_CTRL 0x00 +#define PALMAS_SMPS12_TSTEP 0x01 +#define PALMAS_SMPS12_FORCE 0x02 +#define PALMAS_SMPS12_VOLTAGE 0x03 +#define PALMAS_SMPS3_CTRL 0x04 +#define PALMAS_SMPS3_VOLTAGE 0x07 +#define PALMAS_SMPS45_CTRL 0x08 +#define PALMAS_SMPS45_TSTEP 0x09 +#define PALMAS_SMPS45_FORCE 0x0A +#define PALMAS_SMPS45_VOLTAGE 0x0B +#define PALMAS_SMPS6_CTRL 0x0C +#define PALMAS_SMPS6_TSTEP 0x0D +#define PALMAS_SMPS6_FORCE 0x0E +#define PALMAS_SMPS6_VOLTAGE 0x0F #define PALMAS_SMPS7_CTRL 0x10 #define PALMAS_SMPS7_VOLTAGE 0x13 #define PALMAS_SMPS8_CTRL 0x14 @@ -744,303 +744,303 @@ enum usb_irq_events { /* Bit definitions for SMPS12_CTRL */ #define PALMAS_SMPS12_CTRL_WR_S 0x80 -#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 -#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 -#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c -#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 -#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SMPS12_TSTEP */ #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 -#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 +#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00 /* Bit definitions for SMPS12_FORCE */ #define PALMAS_SMPS12_FORCE_CMD 0x80 -#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 -#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f -#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 +#define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07 +#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F +#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS12_VOLTAGE */ #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 -#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 -#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f -#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07 +#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F +#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS3_CTRL */ #define PALMAS_SMPS3_CTRL_WR_S 0x80 -#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 -#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c -#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 -#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SMPS3_VOLTAGE */ #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 -#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 -#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f -#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 +#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F +#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS45_CTRL */ #define PALMAS_SMPS45_CTRL_WR_S 0x80 -#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 -#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 -#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c -#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 -#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SMPS45_TSTEP */ #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 -#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 +#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00 /* Bit definitions for SMPS45_FORCE */ #define PALMAS_SMPS45_FORCE_CMD 0x80 -#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 -#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f -#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 +#define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07 +#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F +#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS45_VOLTAGE */ #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 -#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 -#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f -#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07 +#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F +#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS6_CTRL */ #define PALMAS_SMPS6_CTRL_WR_S 0x80 -#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 -#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 -#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c -#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 -#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SMPS6_TSTEP */ #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 -#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 +#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00 /* Bit definitions for SMPS6_FORCE */ #define PALMAS_SMPS6_FORCE_CMD 0x80 -#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 -#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f -#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 +#define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07 +#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F +#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS6_VOLTAGE */ #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 -#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 -#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f -#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07 +#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F +#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS7_CTRL */ #define PALMAS_SMPS7_CTRL_WR_S 0x80 -#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 -#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c -#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 -#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SMPS7_VOLTAGE */ #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 -#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 -#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f -#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07 +#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F +#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS8_CTRL */ #define PALMAS_SMPS8_CTRL_WR_S 0x80 -#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 -#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 +#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 -#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c -#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 -#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SMPS8_TSTEP */ #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 -#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 +#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00 /* Bit definitions for SMPS8_FORCE */ #define PALMAS_SMPS8_FORCE_CMD 0x80 -#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 -#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f -#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 +#define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07 +#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F +#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS8_VOLTAGE */ #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 -#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 -#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f -#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07 +#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F +#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS9_CTRL */ #define PALMAS_SMPS9_CTRL_WR_S 0x80 -#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 +#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 -#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 +#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c -#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 -#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SMPS9_VOLTAGE */ #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 -#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 -#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f -#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07 +#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F +#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for SMPS10_CTRL */ #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 -#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 -#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f -#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04 +#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F +#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SMPS10_STATUS */ -#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f -#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 +#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F +#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00 /* Bit definitions for SMPS_CTRL */ #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 -#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 +#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 -#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 +#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c -#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 +#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 -#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 +#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00 /* Bit definitions for SMPS_PD_CTRL */ #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 -#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 +#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 -#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 +#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 -#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 +#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 -#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 +#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 -#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 +#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 -#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 +#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 -#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 +#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00 /* Bit definitions for SMPS_THERMAL_EN */ #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 -#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 +#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 -#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 +#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 -#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 +#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 -#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 +#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 -#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 +#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00 /* Bit definitions for SMPS_THERMAL_STATUS */ #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 -#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 -#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 -#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 -#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 -#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 +#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00 /* Bit definitions for SMPS_SHORT_STATUS */ #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 -#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 +#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 -#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 +#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 -#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 +#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 -#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 +#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 -#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 +#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 -#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 +#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 -#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 +#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 -#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 +#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 -#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 -#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 -#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 -#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 -#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 -#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 -#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 +#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00 /* Bit definitions for SMPS_POWERGOOD_MASK1 */ #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 -#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 -#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 -#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 -#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 -#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 -#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 -#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 -#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 +#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00 /* Bit definitions for SMPS_POWERGOOD_MASK2 */ #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 -#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 +#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 -#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 +#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 -#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 +#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 -#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 +#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00 /* Registers for function LDO */ -#define PALMAS_LDO1_CTRL 0x0 -#define PALMAS_LDO1_VOLTAGE 0x1 -#define PALMAS_LDO2_CTRL 0x2 -#define PALMAS_LDO2_VOLTAGE 0x3 -#define PALMAS_LDO3_CTRL 0x4 -#define PALMAS_LDO3_VOLTAGE 0x5 -#define PALMAS_LDO4_CTRL 0x6 -#define PALMAS_LDO4_VOLTAGE 0x7 -#define PALMAS_LDO5_CTRL 0x8 -#define PALMAS_LDO5_VOLTAGE 0x9 -#define PALMAS_LDO6_CTRL 0xA -#define PALMAS_LDO6_VOLTAGE 0xB -#define PALMAS_LDO7_CTRL 0xC -#define PALMAS_LDO7_VOLTAGE 0xD -#define PALMAS_LDO8_CTRL 0xE -#define PALMAS_LDO8_VOLTAGE 0xF +#define PALMAS_LDO1_CTRL 0x00 +#define PALMAS_LDO1_VOLTAGE 0x01 +#define PALMAS_LDO2_CTRL 0x02 +#define PALMAS_LDO2_VOLTAGE 0x03 +#define PALMAS_LDO3_CTRL 0x04 +#define PALMAS_LDO3_VOLTAGE 0x05 +#define PALMAS_LDO4_CTRL 0x06 +#define PALMAS_LDO4_VOLTAGE 0x07 +#define PALMAS_LDO5_CTRL 0x08 +#define PALMAS_LDO5_VOLTAGE 0x09 +#define PALMAS_LDO6_CTRL 0x0A +#define PALMAS_LDO6_VOLTAGE 0x0B +#define PALMAS_LDO7_CTRL 0x0C +#define PALMAS_LDO7_VOLTAGE 0x0D +#define PALMAS_LDO8_CTRL 0x0E +#define PALMAS_LDO8_VOLTAGE 0x0F #define PALMAS_LDO9_CTRL 0x10 #define PALMAS_LDO9_VOLTAGE 0x11 #define PALMAS_LDOLN_CTRL 0x12 @@ -1055,236 +1055,236 @@ enum usb_irq_events { /* Bit definitions for LDO1_CTRL */ #define PALMAS_LDO1_CTRL_WR_S 0x80 -#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO1_CTRL_STATUS 0x10 -#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO1_VOLTAGE */ -#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO2_CTRL */ #define PALMAS_LDO2_CTRL_WR_S 0x80 -#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO2_CTRL_STATUS 0x10 -#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO2_VOLTAGE */ -#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO3_CTRL */ #define PALMAS_LDO3_CTRL_WR_S 0x80 -#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO3_CTRL_STATUS 0x10 -#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO3_VOLTAGE */ -#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO4_CTRL */ #define PALMAS_LDO4_CTRL_WR_S 0x80 -#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO4_CTRL_STATUS 0x10 -#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO4_VOLTAGE */ -#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO5_CTRL */ #define PALMAS_LDO5_CTRL_WR_S 0x80 -#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO5_CTRL_STATUS 0x10 -#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO5_VOLTAGE */ -#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO6_CTRL */ #define PALMAS_LDO6_CTRL_WR_S 0x80 -#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 -#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 +#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06 #define PALMAS_LDO6_CTRL_STATUS 0x10 -#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO6_VOLTAGE */ -#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO7_CTRL */ #define PALMAS_LDO7_CTRL_WR_S 0x80 -#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO7_CTRL_STATUS 0x10 -#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO7_VOLTAGE */ -#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO8_CTRL */ #define PALMAS_LDO8_CTRL_WR_S 0x80 -#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 -#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 +#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06 #define PALMAS_LDO8_CTRL_STATUS 0x10 -#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO8_VOLTAGE */ -#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO9_CTRL */ #define PALMAS_LDO9_CTRL_WR_S 0x80 -#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 -#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 +#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06 #define PALMAS_LDO9_CTRL_STATUS 0x10 -#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDO9_VOLTAGE */ -#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDOLN_CTRL */ #define PALMAS_LDOLN_CTRL_WR_S 0x80 -#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDOLN_CTRL_STATUS 0x10 -#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDOLN_VOLTAGE */ -#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDOUSB_CTRL */ #define PALMAS_LDOUSB_CTRL_WR_S 0x80 -#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 +#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07 #define PALMAS_LDOUSB_CTRL_STATUS 0x10 -#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 +#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 -#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for LDOUSB_VOLTAGE */ -#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f -#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 +#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F +#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00 /* Bit definitions for LDO_CTRL */ #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 -#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 +#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00 /* Bit definitions for LDO_PD_CTRL1 */ #define PALMAS_LDO_PD_CTRL1_LDO8 0x80 -#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 +#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40 -#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 +#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20 -#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 +#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10 -#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 +#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08 -#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 +#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04 -#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 +#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02 -#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 +#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01 -#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 +#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00 /* Bit definitions for LDO_PD_CTRL2 */ #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 -#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 +#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 -#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 +#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01 -#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 +#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00 /* Bit definitions for LDO_SHORT_STATUS1 */ #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 -#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 +#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 -#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 +#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 -#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 +#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 -#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 +#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 -#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 +#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 -#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 +#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 -#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 +#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 -#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 +#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 /* Bit definitions for LDO_SHORT_STATUS2 */ #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 -#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 +#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 -#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 +#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 -#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 +#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 -#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 +#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00 /* Registers for function PMU_CONTROL */ -#define PALMAS_DEV_CTRL 0x0 -#define PALMAS_POWER_CTRL 0x1 -#define PALMAS_VSYS_LO 0x2 -#define PALMAS_VSYS_MON 0x3 -#define PALMAS_VBAT_MON 0x4 -#define PALMAS_WATCHDOG 0x5 -#define PALMAS_BOOT_STATUS 0x6 -#define PALMAS_BATTERY_BOUNCE 0x7 -#define PALMAS_BACKUP_BATTERY_CTRL 0x8 -#define PALMAS_LONG_PRESS_KEY 0x9 -#define PALMAS_OSC_THERM_CTRL 0xA -#define PALMAS_BATDEBOUNCING 0xB -#define PALMAS_SWOFF_HWRST 0xF +#define PALMAS_DEV_CTRL 0x00 +#define PALMAS_POWER_CTRL 0x01 +#define PALMAS_VSYS_LO 0x02 +#define PALMAS_VSYS_MON 0x03 +#define PALMAS_VBAT_MON 0x04 +#define PALMAS_WATCHDOG 0x05 +#define PALMAS_BOOT_STATUS 0x06 +#define PALMAS_BATTERY_BOUNCE 0x07 +#define PALMAS_BACKUP_BATTERY_CTRL 0x08 +#define PALMAS_LONG_PRESS_KEY 0x09 +#define PALMAS_OSC_THERM_CTRL 0x0A +#define PALMAS_BATDEBOUNCING 0x0B +#define PALMAS_SWOFF_HWRST 0x0F #define PALMAS_SWOFF_COLDRST 0x10 #define PALMAS_SWOFF_STATUS 0x11 #define PALMAS_PMU_CONFIG 0x12 @@ -1296,668 +1296,668 @@ enum usb_irq_events { /* Bit definitions for DEV_CTRL */ #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c -#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 +#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02 #define PALMAS_DEV_CTRL_SW_RST 0x02 -#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 +#define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01 #define PALMAS_DEV_CTRL_DEV_ON 0x01 -#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 +#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00 /* Bit definitions for POWER_CTRL */ #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 -#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 +#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 -#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 +#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 -#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 +#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00 /* Bit definitions for VSYS_LO */ -#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f -#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 +#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F +#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00 /* Bit definitions for VSYS_MON */ #define PALMAS_VSYS_MON_ENABLE 0x80 -#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 -#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f -#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 +#define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07 +#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F +#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00 /* Bit definitions for VBAT_MON */ #define PALMAS_VBAT_MON_ENABLE 0x80 -#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 -#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f -#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 +#define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07 +#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F +#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00 /* Bit definitions for WATCHDOG */ #define PALMAS_WATCHDOG_LOCK 0x20 -#define PALMAS_WATCHDOG_LOCK_SHIFT 5 +#define PALMAS_WATCHDOG_LOCK_SHIFT 0x05 #define PALMAS_WATCHDOG_ENABLE 0x10 -#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 +#define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04 #define PALMAS_WATCHDOG_MODE 0x08 -#define PALMAS_WATCHDOG_MODE_SHIFT 3 +#define PALMAS_WATCHDOG_MODE_SHIFT 0x03 #define PALMAS_WATCHDOG_TIMER_MASK 0x07 -#define PALMAS_WATCHDOG_TIMER_SHIFT 0 +#define PALMAS_WATCHDOG_TIMER_SHIFT 0x00 /* Bit definitions for BOOT_STATUS */ #define PALMAS_BOOT_STATUS_BOOT1 0x02 -#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 +#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01 #define PALMAS_BOOT_STATUS_BOOT0 0x01 -#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 +#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00 /* Bit definitions for BATTERY_BOUNCE */ -#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f -#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 +#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F +#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00 /* Bit definitions for BACKUP_BATTERY_CTRL */ #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 -#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 -#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 -#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 -#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 +#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 -#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 +#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 -#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 +#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 -#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 +#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00 /* Bit definitions for LONG_PRESS_KEY */ #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 -#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 +#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 -#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 +#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c -#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 +#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 -#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 +#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00 /* Bit definitions for OSC_THERM_CTRL */ #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 -#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 +#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 -#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 +#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 -#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 +#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 -#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 +#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c -#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 +#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 -#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 +#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 -#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 +#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00 /* Bit definitions for BATDEBOUNCING */ #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 -#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 +#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 -#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 +#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 -#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 +#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00 /* Bit definitions for SWOFF_HWRST */ #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 -#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 +#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 -#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 +#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06 #define PALMAS_SWOFF_HWRST_WTD 0x20 -#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 +#define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05 #define PALMAS_SWOFF_HWRST_TSHUT 0x10 -#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 +#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08 -#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 +#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03 #define PALMAS_SWOFF_HWRST_SW_RST 0x04 -#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 +#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 -#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 +#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 -#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 +#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00 /* Bit definitions for SWOFF_COLDRST */ #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 -#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 +#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 -#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 +#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06 #define PALMAS_SWOFF_COLDRST_WTD 0x20 -#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 +#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10 -#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 +#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 -#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 +#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04 -#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 +#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 -#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 +#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 -#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 +#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00 /* Bit definitions for SWOFF_STATUS */ #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 -#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 +#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 -#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 +#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06 #define PALMAS_SWOFF_STATUS_WTD 0x20 -#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 +#define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05 #define PALMAS_SWOFF_STATUS_TSHUT 0x10 -#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 +#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08 -#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 +#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03 #define PALMAS_SWOFF_STATUS_SW_RST 0x04 -#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 +#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 -#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 +#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 -#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 +#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00 /* Bit definitions for PMU_CONFIG */ #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 -#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 +#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 -#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 +#define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c -#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 +#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 -#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 +#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01 -#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 +#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00 /* Bit definitions for SPARE */ #define PALMAS_SPARE_SPARE_MASK 0xf8 -#define PALMAS_SPARE_SPARE_SHIFT 3 +#define PALMAS_SPARE_SPARE_SHIFT 0x03 #define PALMAS_SPARE_REGEN3_OD 0x04 -#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 +#define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02 #define PALMAS_SPARE_REGEN2_OD 0x02 -#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 +#define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01 #define PALMAS_SPARE_REGEN1_OD 0x01 -#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 +#define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00 /* Bit definitions for PMU_SECONDARY_INT */ #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 -#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 +#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 -#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 +#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 -#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 +#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 -#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 +#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 -#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 +#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 -#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 +#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 -#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 +#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 -#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 +#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00 /* Bit definitions for SW_REVISION */ -#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff -#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 +#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF +#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00 /* Bit definitions for EXT_CHRG_CTRL */ #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 -#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 +#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 -#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 +#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 -#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 +#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 -#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 +#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 -#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 +#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 -#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 +#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00 /* Bit definitions for PMU_SECONDARY_INT2 */ #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 -#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 +#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 -#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 +#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 -#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 +#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 -#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 +#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00 /* Registers for function RESOURCE */ -#define PALMAS_CLK32KG_CTRL 0x0 -#define PALMAS_CLK32KGAUDIO_CTRL 0x1 -#define PALMAS_REGEN1_CTRL 0x2 -#define PALMAS_REGEN2_CTRL 0x3 -#define PALMAS_SYSEN1_CTRL 0x4 -#define PALMAS_SYSEN2_CTRL 0x5 -#define PALMAS_NSLEEP_RES_ASSIGN 0x6 -#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 -#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 -#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 -#define PALMAS_ENABLE1_RES_ASSIGN 0xA -#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB -#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC -#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD -#define PALMAS_ENABLE2_RES_ASSIGN 0xE -#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF +#define PALMAS_CLK32KG_CTRL 0x00 +#define PALMAS_CLK32KGAUDIO_CTRL 0x01 +#define PALMAS_REGEN1_CTRL 0x02 +#define PALMAS_REGEN2_CTRL 0x03 +#define PALMAS_SYSEN1_CTRL 0x04 +#define PALMAS_SYSEN2_CTRL 0x05 +#define PALMAS_NSLEEP_RES_ASSIGN 0x06 +#define PALMAS_NSLEEP_SMPS_ASSIGN 0x07 +#define PALMAS_NSLEEP_LDO_ASSIGN1 0x08 +#define PALMAS_NSLEEP_LDO_ASSIGN2 0x09 +#define PALMAS_ENABLE1_RES_ASSIGN 0x0A +#define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B +#define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C +#define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D +#define PALMAS_ENABLE2_RES_ASSIGN 0x0E +#define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 #define PALMAS_REGEN3_CTRL 0x12 /* Bit definitions for CLK32KG_CTRL */ #define PALMAS_CLK32KG_CTRL_STATUS 0x10 -#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 +#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 -#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for CLK32KGAUDIO_CTRL */ #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 -#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 +#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 -#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 +#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 -#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for REGEN1_CTRL */ #define PALMAS_REGEN1_CTRL_STATUS 0x10 -#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 +#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 -#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for REGEN2_CTRL */ #define PALMAS_REGEN2_CTRL_STATUS 0x10 -#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 +#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 -#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SYSEN1_CTRL */ #define PALMAS_SYSEN1_CTRL_STATUS 0x10 -#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 +#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 -#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for SYSEN2_CTRL */ #define PALMAS_SYSEN2_CTRL_STATUS 0x10 -#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 +#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 -#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Bit definitions for NSLEEP_RES_ASSIGN */ #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 -#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 -#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 +#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 -#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 +#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 -#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 +#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 -#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 +#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 -#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 -#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 +#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 -#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 -#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 -#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 -#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 -#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 -#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 -#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 -#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 +#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 -#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 -#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 -#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 -#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 -#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 -#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 -#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 -#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 +#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 -#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 -#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 -#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 +#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00 /* Bit definitions for ENABLE1_RES_ASSIGN */ #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 -#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 -#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 +#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 -#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 +#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 -#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 +#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 -#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 +#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 -#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 -#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 +#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 -#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 -#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 -#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 -#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 -#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 -#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 -#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 -#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 +#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 -#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 -#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 -#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 -#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 -#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 -#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 -#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 -#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 +#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 -#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 -#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 -#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 +#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00 /* Bit definitions for ENABLE2_RES_ASSIGN */ #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 -#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 -#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 +#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 -#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 +#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 -#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 +#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 -#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 +#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 -#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 -#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 +#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 -#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 -#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 -#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 -#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 -#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 -#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 -#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 -#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 +#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 -#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 -#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 -#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 -#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 -#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 -#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 -#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 -#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 +#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 -#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 -#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 -#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 +#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00 /* Bit definitions for REGEN3_CTRL */ #define PALMAS_REGEN3_CTRL_STATUS 0x10 -#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 +#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 -#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 +#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 -#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 +#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 /* Registers for function PAD_CONTROL */ -#define PALMAS_OD_OUTPUT_CTRL2 0x2 -#define PALMAS_POLARITY_CTRL2 0x3 -#define PALMAS_PU_PD_INPUT_CTRL1 0x4 -#define PALMAS_PU_PD_INPUT_CTRL2 0x5 -#define PALMAS_PU_PD_INPUT_CTRL3 0x6 -#define PALMAS_PU_PD_INPUT_CTRL5 0x7 -#define PALMAS_OD_OUTPUT_CTRL 0x8 -#define PALMAS_POLARITY_CTRL 0x9 -#define PALMAS_PRIMARY_SECONDARY_PAD1 0xA -#define PALMAS_PRIMARY_SECONDARY_PAD2 0xB -#define PALMAS_I2C_SPI 0xC -#define PALMAS_PU_PD_INPUT_CTRL4 0xD -#define PALMAS_PRIMARY_SECONDARY_PAD3 0xE -#define PALMAS_PRIMARY_SECONDARY_PAD4 0xF +#define PALMAS_OD_OUTPUT_CTRL2 0x02 +#define PALMAS_POLARITY_CTRL2 0x03 +#define PALMAS_PU_PD_INPUT_CTRL1 0x04 +#define PALMAS_PU_PD_INPUT_CTRL2 0x05 +#define PALMAS_PU_PD_INPUT_CTRL3 0x06 +#define PALMAS_PU_PD_INPUT_CTRL5 0x07 +#define PALMAS_OD_OUTPUT_CTRL 0x08 +#define PALMAS_POLARITY_CTRL 0x09 +#define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A +#define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B +#define PALMAS_I2C_SPI 0x0C +#define PALMAS_PU_PD_INPUT_CTRL4 0x0D +#define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E +#define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F /* Bit definitions for PU_PD_INPUT_CTRL1 */ #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 -#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 +#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 -#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 +#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 -#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 +#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 -#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 +#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 -#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 +#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01 /* Bit definitions for PU_PD_INPUT_CTRL2 */ #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 -#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 -#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 -#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 -#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 +#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 -#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 +#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 -#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 +#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00 /* Bit definitions for PU_PD_INPUT_CTRL3 */ #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 -#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 +#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 -#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 +#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 -#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 +#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 -#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 +#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00 /* Bit definitions for OD_OUTPUT_CTRL */ #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 -#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 +#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 -#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 +#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 -#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 +#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 -#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 +#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03 /* Bit definitions for POLARITY_CTRL */ #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 -#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 +#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 -#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 +#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 -#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 +#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 -#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 +#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 -#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 +#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 -#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 +#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 -#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 +#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 -#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 +#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */ #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 -#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 -#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 -#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 -#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 +#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 -#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 +#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 -#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 +#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */ #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 -#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 -#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 -#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 -#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 +#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00 /* Bit definitions for I2C_SPI */ #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 -#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 +#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 -#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 +#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06 #define PALMAS_I2C_SPI_ID_I2C2 0x20 -#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 +#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05 #define PALMAS_I2C_SPI_I2C_SPI 0x10 -#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 -#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f -#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 +#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04 +#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F +#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00 /* Bit definitions for PU_PD_INPUT_CTRL4 */ #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 -#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 -#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 -#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 -#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 +#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */ #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 -#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 +#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 -#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 +#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00 /* Registers for function LED_PWM */ -#define PALMAS_LED_PERIOD_CTRL 0x0 -#define PALMAS_LED_CTRL 0x1 -#define PALMAS_PWM_CTRL1 0x2 -#define PALMAS_PWM_CTRL2 0x3 +#define PALMAS_LED_PERIOD_CTRL 0x00 +#define PALMAS_LED_CTRL 0x01 +#define PALMAS_PWM_CTRL1 0x02 +#define PALMAS_PWM_CTRL2 0x03 /* Bit definitions for LED_PERIOD_CTRL */ #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 -#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 +#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 -#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 +#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00 /* Bit definitions for LED_CTRL */ #define PALMAS_LED_CTRL_LED_2_SEQ 0x20 -#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 +#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10 -#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 +#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c -#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 +#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 -#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 +#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00 /* Bit definitions for PWM_CTRL1 */ #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 -#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 +#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 -#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 +#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00 /* Bit definitions for PWM_CTRL2 */ -#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff -#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 +#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF +#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00 /* Registers for function INTERRUPT */ -#define PALMAS_INT1_STATUS 0x0 -#define PALMAS_INT1_MASK 0x1 -#define PALMAS_INT1_LINE_STATE 0x2 -#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 -#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 -#define PALMAS_INT2_STATUS 0x5 -#define PALMAS_INT2_MASK 0x6 -#define PALMAS_INT2_LINE_STATE 0x7 -#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 -#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 -#define PALMAS_INT3_STATUS 0xA -#define PALMAS_INT3_MASK 0xB -#define PALMAS_INT3_LINE_STATE 0xC -#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD -#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE -#define PALMAS_INT4_STATUS 0xF +#define PALMAS_INT1_STATUS 0x00 +#define PALMAS_INT1_MASK 0x01 +#define PALMAS_INT1_LINE_STATE 0x02 +#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03 +#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04 +#define PALMAS_INT2_STATUS 0x05 +#define PALMAS_INT2_MASK 0x06 +#define PALMAS_INT2_LINE_STATE 0x07 +#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08 +#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09 +#define PALMAS_INT3_STATUS 0x0A +#define PALMAS_INT3_MASK 0x0B +#define PALMAS_INT3_LINE_STATE 0x0C +#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D +#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E +#define PALMAS_INT4_STATUS 0x0F #define PALMAS_INT4_MASK 0x10 #define PALMAS_INT4_LINE_STATE 0x11 #define PALMAS_INT4_EDGE_DETECT1 0x12 @@ -1966,276 +1966,276 @@ enum usb_irq_events { /* Bit definitions for INT1_STATUS */ #define PALMAS_INT1_STATUS_VBAT_MON 0x80 -#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 +#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07 #define PALMAS_INT1_STATUS_VSYS_MON 0x40 -#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 +#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06 #define PALMAS_INT1_STATUS_HOTDIE 0x20 -#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 +#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05 #define PALMAS_INT1_STATUS_PWRDOWN 0x10 -#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 +#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04 #define PALMAS_INT1_STATUS_RPWRON 0x08 -#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 +#define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 -#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 +#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 #define PALMAS_INT1_STATUS_PWRON 0x02 -#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 +#define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 -#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 +#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 /* Bit definitions for INT1_MASK */ #define PALMAS_INT1_MASK_VBAT_MON 0x80 -#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 +#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07 #define PALMAS_INT1_MASK_VSYS_MON 0x40 -#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 +#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06 #define PALMAS_INT1_MASK_HOTDIE 0x20 -#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 +#define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05 #define PALMAS_INT1_MASK_PWRDOWN 0x10 -#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 +#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04 #define PALMAS_INT1_MASK_RPWRON 0x08 -#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 +#define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 -#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 +#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 #define PALMAS_INT1_MASK_PWRON 0x02 -#define PALMAS_INT1_MASK_PWRON_SHIFT 1 +#define PALMAS_INT1_MASK_PWRON_SHIFT 0x01 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 -#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 +#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 /* Bit definitions for INT1_LINE_STATE */ #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 -#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 +#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 -#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 +#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 -#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 +#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 -#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 +#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08 -#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 +#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 -#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 +#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 #define PALMAS_INT1_LINE_STATE_PWRON 0x02 -#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 +#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 -#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 +#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 /* Bit definitions for INT2_STATUS */ #define PALMAS_INT2_STATUS_VAC_ACOK 0x80 -#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 +#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07 #define PALMAS_INT2_STATUS_SHORT 0x40 -#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 +#define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06 #define PALMAS_INT2_STATUS_FBI_BB 0x20 -#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 +#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05 #define PALMAS_INT2_STATUS_RESET_IN 0x10 -#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 +#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08 -#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 +#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03 #define PALMAS_INT2_STATUS_WDT 0x04 -#define PALMAS_INT2_STATUS_WDT_SHIFT 2 +#define PALMAS_INT2_STATUS_WDT_SHIFT 0x02 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02 -#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 +#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01 -#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 +#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00 /* Bit definitions for INT2_MASK */ #define PALMAS_INT2_MASK_VAC_ACOK 0x80 -#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 +#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07 #define PALMAS_INT2_MASK_SHORT 0x40 -#define PALMAS_INT2_MASK_SHORT_SHIFT 6 +#define PALMAS_INT2_MASK_SHORT_SHIFT 0x06 #define PALMAS_INT2_MASK_FBI_BB 0x20 -#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 +#define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05 #define PALMAS_INT2_MASK_RESET_IN 0x10 -#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 +#define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04 #define PALMAS_INT2_MASK_BATREMOVAL 0x08 -#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 +#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03 #define PALMAS_INT2_MASK_WDT 0x04 -#define PALMAS_INT2_MASK_WDT_SHIFT 2 +#define PALMAS_INT2_MASK_WDT_SHIFT 0x02 #define PALMAS_INT2_MASK_RTC_TIMER 0x02 -#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 +#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01 #define PALMAS_INT2_MASK_RTC_ALARM 0x01 -#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 +#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00 /* Bit definitions for INT2_LINE_STATE */ #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 -#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 +#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07 #define PALMAS_INT2_LINE_STATE_SHORT 0x40 -#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 +#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 -#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 +#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 -#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 +#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 -#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 +#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03 #define PALMAS_INT2_LINE_STATE_WDT 0x04 -#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 +#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 -#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 +#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 -#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 +#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00 /* Bit definitions for INT3_STATUS */ #define PALMAS_INT3_STATUS_VBUS 0x80 -#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 +#define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40 -#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 +#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06 #define PALMAS_INT3_STATUS_ID 0x20 -#define PALMAS_INT3_STATUS_ID_SHIFT 5 +#define PALMAS_INT3_STATUS_ID_SHIFT 0x05 #define PALMAS_INT3_STATUS_ID_OTG 0x10 -#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 +#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 -#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 +#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 -#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 +#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 -#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 +#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 -#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 +#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 /* Bit definitions for INT3_MASK */ #define PALMAS_INT3_MASK_VBUS 0x80 -#define PALMAS_INT3_MASK_VBUS_SHIFT 7 +#define PALMAS_INT3_MASK_VBUS_SHIFT 0x07 #define PALMAS_INT3_MASK_VBUS_OTG 0x40 -#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 +#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06 #define PALMAS_INT3_MASK_ID 0x20 -#define PALMAS_INT3_MASK_ID_SHIFT 5 +#define PALMAS_INT3_MASK_ID_SHIFT 0x05 #define PALMAS_INT3_MASK_ID_OTG 0x10 -#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 +#define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 -#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 +#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 -#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 +#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 -#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 +#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 -#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 +#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 /* Bit definitions for INT3_LINE_STATE */ #define PALMAS_INT3_LINE_STATE_VBUS 0x80 -#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 +#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 -#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 +#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06 #define PALMAS_INT3_LINE_STATE_ID 0x20 -#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 +#define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 -#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 +#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 -#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 +#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 -#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 +#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 -#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 +#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 -#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 +#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 /* Bit definitions for INT4_STATUS */ #define PALMAS_INT4_STATUS_GPIO_7 0x80 -#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 +#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07 #define PALMAS_INT4_STATUS_GPIO_6 0x40 -#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 +#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06 #define PALMAS_INT4_STATUS_GPIO_5 0x20 -#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 +#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05 #define PALMAS_INT4_STATUS_GPIO_4 0x10 -#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 +#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04 #define PALMAS_INT4_STATUS_GPIO_3 0x08 -#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 +#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03 #define PALMAS_INT4_STATUS_GPIO_2 0x04 -#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 +#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02 #define PALMAS_INT4_STATUS_GPIO_1 0x02 -#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 +#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01 #define PALMAS_INT4_STATUS_GPIO_0 0x01 -#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 +#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00 /* Bit definitions for INT4_MASK */ #define PALMAS_INT4_MASK_GPIO_7 0x80 -#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 +#define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07 #define PALMAS_INT4_MASK_GPIO_6 0x40 -#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 +#define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06 #define PALMAS_INT4_MASK_GPIO_5 0x20 -#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 +#define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05 #define PALMAS_INT4_MASK_GPIO_4 0x10 -#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 +#define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04 #define PALMAS_INT4_MASK_GPIO_3 0x08 -#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 +#define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03 #define PALMAS_INT4_MASK_GPIO_2 0x04 -#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 +#define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02 #define PALMAS_INT4_MASK_GPIO_1 0x02 -#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 +#define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01 #define PALMAS_INT4_MASK_GPIO_0 0x01 -#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 +#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00 /* Bit definitions for INT4_LINE_STATE */ #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 -#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 +#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 -#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 +#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 -#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 +#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 -#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 +#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 -#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 +#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 -#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 +#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 -#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 +#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 -#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 +#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 /* Bit definitions for INT4_EDGE_DETECT1 */ #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 -#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 -#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 -#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 -#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 -#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 -#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 -#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 -#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 +#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 /* Bit definitions for INT4_EDGE_DETECT2 */ #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 -#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 -#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 -#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 -#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 -#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 -#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 -#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 -#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 +#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 /* Bit definitions for INT_CTRL */ #define PALMAS_INT_CTRL_INT_PENDING 0x04 -#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 +#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02 #define PALMAS_INT_CTRL_INT_CLEAR 0x01 -#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 +#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00 /* Registers for function USB_OTG */ -#define PALMAS_USB_WAKEUP 0x3 -#define PALMAS_USB_VBUS_CTRL_SET 0x4 -#define PALMAS_USB_VBUS_CTRL_CLR 0x5 -#define PALMAS_USB_ID_CTRL_SET 0x6 -#define PALMAS_USB_ID_CTRL_CLEAR 0x7 -#define PALMAS_USB_VBUS_INT_SRC 0x8 -#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 -#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA -#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB -#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC -#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD -#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE -#define PALMAS_USB_ID_INT_SRC 0xF +#define PALMAS_USB_WAKEUP 0x03 +#define PALMAS_USB_VBUS_CTRL_SET 0x04 +#define PALMAS_USB_VBUS_CTRL_CLR 0x05 +#define PALMAS_USB_ID_CTRL_SET 0x06 +#define PALMAS_USB_ID_CTRL_CLEAR 0x07 +#define PALMAS_USB_VBUS_INT_SRC 0x08 +#define PALMAS_USB_VBUS_INT_LATCH_SET 0x09 +#define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A +#define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B +#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C +#define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D +#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E +#define PALMAS_USB_ID_INT_SRC 0x0F #define PALMAS_USB_ID_INT_LATCH_SET 0x10 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12 @@ -2250,306 +2250,306 @@ enum usb_irq_events { /* Bit definitions for USB_WAKEUP */ #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 -#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 +#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00 /* Bit definitions for USB_VBUS_CTRL_SET */ #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 -#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 -#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 -#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 -#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 -#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 +#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02 /* Bit definitions for USB_VBUS_CTRL_CLR */ #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 -#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 -#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 -#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 -#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 -#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 +#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02 /* Bit definitions for USB_ID_CTRL_SET */ #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 -#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 +#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 -#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 +#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 -#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 +#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 -#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 +#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 -#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 +#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 -#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 +#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02 /* Bit definitions for USB_ID_CTRL_CLEAR */ #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 -#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 -#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 -#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 -#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 -#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 -#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 +#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02 /* Bit definitions for USB_VBUS_INT_SRC */ #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 -#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 -#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 -#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 -#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 -#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 -#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 -#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 +#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00 /* Bit definitions for USB_VBUS_INT_LATCH_SET */ #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 -#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 -#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 -#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 -#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 +#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 -#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 -#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 -#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 -#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 +#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */ #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 -#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 -#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 -#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 -#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 -#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 -#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 -#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 -#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 +#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */ #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 -#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 -#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 -#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 -#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 -#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 -#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 -#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 +#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 -#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 -#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 -#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 -#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 -#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 -#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 -#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 +#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */ #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 -#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 -#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 -#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 -#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 -#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 -#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 -#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 -#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 +#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 -#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 -#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 -#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 -#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 -#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 -#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 -#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 -#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 +#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00 /* Bit definitions for USB_ID_INT_SRC */ #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 -#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08 -#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04 -#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02 -#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 -#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 +#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00 /* Bit definitions for USB_ID_INT_LATCH_SET */ #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 -#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 -#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 -#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 -#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 -#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 +#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00 /* Bit definitions for USB_ID_INT_LATCH_CLR */ #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 -#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 -#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 -#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 -#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 -#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 +#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00 /* Bit definitions for USB_ID_INT_EN_LO_SET */ #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 -#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 -#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 -#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 -#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 -#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 +#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00 /* Bit definitions for USB_ID_INT_EN_LO_CLR */ #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 -#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 -#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 -#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 -#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 -#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 +#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00 /* Bit definitions for USB_ID_INT_EN_HI_SET */ #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 -#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 -#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 -#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 -#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 -#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 +#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00 /* Bit definitions for USB_ID_INT_EN_HI_CLR */ #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 -#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 -#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 -#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 -#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 -#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 +#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00 /* Bit definitions for USB_OTG_ADP_CTRL */ #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 -#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 +#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 -#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 +#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00 /* Bit definitions for USB_OTG_ADP_HIGH */ -#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff -#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 +#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF +#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00 /* Bit definitions for USB_OTG_ADP_LOW */ -#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff -#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 +#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF +#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00 /* Bit definitions for USB_OTG_ADP_RISE */ -#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff -#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 +#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF +#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00 /* Bit definitions for USB_OTG_REVISION */ #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 -#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 +#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00 /* Registers for function VIBRATOR */ -#define PALMAS_VIBRA_CTRL 0x0 +#define PALMAS_VIBRA_CTRL 0x00 /* Bit definitions for VIBRA_CTRL */ #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 -#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 +#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 -#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 +#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00 /* Registers for function GPIO */ -#define PALMAS_GPIO_DATA_IN 0x0 -#define PALMAS_GPIO_DATA_DIR 0x1 -#define PALMAS_GPIO_DATA_OUT 0x2 -#define PALMAS_GPIO_DEBOUNCE_EN 0x3 -#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 -#define PALMAS_GPIO_SET_DATA_OUT 0x5 -#define PALMAS_PU_PD_GPIO_CTRL1 0x6 -#define PALMAS_PU_PD_GPIO_CTRL2 0x7 -#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 -#define PALMAS_GPIO_DATA_IN2 0x9 +#define PALMAS_GPIO_DATA_IN 0x00 +#define PALMAS_GPIO_DATA_DIR 0x01 +#define PALMAS_GPIO_DATA_OUT 0x02 +#define PALMAS_GPIO_DEBOUNCE_EN 0x03 +#define PALMAS_GPIO_CLEAR_DATA_OUT 0x04 +#define PALMAS_GPIO_SET_DATA_OUT 0x05 +#define PALMAS_PU_PD_GPIO_CTRL1 0x06 +#define PALMAS_PU_PD_GPIO_CTRL2 0x07 +#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08 +#define PALMAS_GPIO_DATA_IN2 0x09 #define PALMAS_GPIO_DATA_DIR2 0x0A #define PALMAS_GPIO_DATA_OUT2 0x0B #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C @@ -2561,167 +2561,167 @@ enum usb_irq_events { /* Bit definitions for GPIO_DATA_IN */ #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 -#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 +#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 -#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 +#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 -#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 +#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 -#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 +#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 -#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 +#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 -#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 +#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 -#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 +#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 -#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 +#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00 /* Bit definitions for GPIO_DATA_DIR */ #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 -#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 +#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 -#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 +#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 -#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 +#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 -#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 +#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 -#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 +#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 -#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 +#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 -#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 +#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 -#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 +#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00 /* Bit definitions for GPIO_DATA_OUT */ #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 -#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 +#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 -#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 +#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 -#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 +#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 -#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 +#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 -#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 +#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 -#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 +#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 -#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 +#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 -#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 +#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00 /* Bit definitions for GPIO_DEBOUNCE_EN */ #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 -#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 -#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 -#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 -#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 -#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 -#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 -#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 -#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 +#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00 /* Bit definitions for GPIO_CLEAR_DATA_OUT */ #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 -#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 -#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 -#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 -#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 -#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 -#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 -#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 -#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 +#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00 /* Bit definitions for GPIO_SET_DATA_OUT */ #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 -#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 -#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 -#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 -#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 -#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 -#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 -#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 -#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 +#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00 /* Bit definitions for PU_PD_GPIO_CTRL1 */ #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 -#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 -#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 -#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 -#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 -#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 -#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 +#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00 /* Bit definitions for PU_PD_GPIO_CTRL2 */ #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 -#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 -#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 -#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 -#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 -#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 -#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 -#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 +#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */ #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 -#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 -#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 -#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 +#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01 /* Registers for function GPADC */ -#define PALMAS_GPADC_CTRL1 0x0 -#define PALMAS_GPADC_CTRL2 0x1 -#define PALMAS_GPADC_RT_CTRL 0x2 -#define PALMAS_GPADC_AUTO_CTRL 0x3 -#define PALMAS_GPADC_STATUS 0x4 -#define PALMAS_GPADC_RT_SELECT 0x5 -#define PALMAS_GPADC_RT_CONV0_LSB 0x6 -#define PALMAS_GPADC_RT_CONV0_MSB 0x7 -#define PALMAS_GPADC_AUTO_SELECT 0x8 -#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 -#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA -#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB -#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC -#define PALMAS_GPADC_SW_SELECT 0xD -#define PALMAS_GPADC_SW_CONV0_LSB 0xE -#define PALMAS_GPADC_SW_CONV0_MSB 0xF +#define PALMAS_GPADC_CTRL1 0x00 +#define PALMAS_GPADC_CTRL2 0x01 +#define PALMAS_GPADC_RT_CTRL 0x02 +#define PALMAS_GPADC_AUTO_CTRL 0x03 +#define PALMAS_GPADC_STATUS 0x04 +#define PALMAS_GPADC_RT_SELECT 0x05 +#define PALMAS_GPADC_RT_CONV0_LSB 0x06 +#define PALMAS_GPADC_RT_CONV0_MSB 0x07 +#define PALMAS_GPADC_AUTO_SELECT 0x08 +#define PALMAS_GPADC_AUTO_CONV0_LSB 0x09 +#define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A +#define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B +#define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C +#define PALMAS_GPADC_SW_SELECT 0x0D +#define PALMAS_GPADC_SW_CONV0_LSB 0x0E +#define PALMAS_GPADC_SW_CONV0_MSB 0x0F #define PALMAS_GPADC_THRES_CONV0_LSB 0x10 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12 @@ -2731,150 +2731,150 @@ enum usb_irq_events { /* Bit definitions for GPADC_CTRL1 */ #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 -#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 +#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 -#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 +#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c -#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 +#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 -#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 +#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 -#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 +#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00 /* Bit definitions for GPADC_CTRL2 */ #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 -#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 +#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01 /* Bit definitions for GPADC_RT_CTRL */ #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 -#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 +#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 -#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 +#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00 /* Bit definitions for GPADC_AUTO_CTRL */ #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 -#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 +#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 -#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 +#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 -#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 +#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 -#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 -#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f -#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 +#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04 +#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F +#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00 /* Bit definitions for GPADC_STATUS */ #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 -#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 +#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04 /* Bit definitions for GPADC_RT_SELECT */ #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 -#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 -#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f -#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 +#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07 +#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F +#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00 /* Bit definitions for GPADC_RT_CONV0_LSB */ -#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff -#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 +#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF +#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00 /* Bit definitions for GPADC_RT_CONV0_MSB */ -#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f -#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 +#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F +#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00 /* Bit definitions for GPADC_AUTO_SELECT */ -#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 -#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 -#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f -#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 +#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0 +#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04 +#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F +#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00 /* Bit definitions for GPADC_AUTO_CONV0_LSB */ -#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff -#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 +#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF +#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00 /* Bit definitions for GPADC_AUTO_CONV0_MSB */ -#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f -#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 +#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F +#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00 /* Bit definitions for GPADC_AUTO_CONV1_LSB */ -#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff -#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 +#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF +#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00 /* Bit definitions for GPADC_AUTO_CONV1_MSB */ -#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f -#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 +#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F +#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00 /* Bit definitions for GPADC_SW_SELECT */ #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 -#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 +#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 -#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 -#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f -#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 +#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04 +#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F +#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00 /* Bit definitions for GPADC_SW_CONV0_LSB */ -#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff -#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 +#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF +#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00 /* Bit definitions for GPADC_SW_CONV0_MSB */ -#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f -#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 +#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F +#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00 /* Bit definitions for GPADC_THRES_CONV0_LSB */ -#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff -#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 +#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF +#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00 /* Bit definitions for GPADC_THRES_CONV0_MSB */ #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 -#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 -#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f -#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 +#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07 +#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F +#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00 /* Bit definitions for GPADC_THRES_CONV1_LSB */ -#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff -#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 +#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF +#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00 /* Bit definitions for GPADC_THRES_CONV1_MSB */ #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 -#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 -#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f -#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 +#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07 +#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F +#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 -#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 -#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 -#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f -#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04 +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F +#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 -#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 -#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f -#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 +#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07 +#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F +#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00 /* Registers for function GPADC */ -#define PALMAS_GPADC_TRIM1 0x0 -#define PALMAS_GPADC_TRIM2 0x1 -#define PALMAS_GPADC_TRIM3 0x2 -#define PALMAS_GPADC_TRIM4 0x3 -#define PALMAS_GPADC_TRIM5 0x4 -#define PALMAS_GPADC_TRIM6 0x5 -#define PALMAS_GPADC_TRIM7 0x6 -#define PALMAS_GPADC_TRIM8 0x7 -#define PALMAS_GPADC_TRIM9 0x8 -#define PALMAS_GPADC_TRIM10 0x9 -#define PALMAS_GPADC_TRIM11 0xA -#define PALMAS_GPADC_TRIM12 0xB -#define PALMAS_GPADC_TRIM13 0xC -#define PALMAS_GPADC_TRIM14 0xD -#define PALMAS_GPADC_TRIM15 0xE -#define PALMAS_GPADC_TRIM16 0xF +#define PALMAS_GPADC_TRIM1 0x00 +#define PALMAS_GPADC_TRIM2 0x01 +#define PALMAS_GPADC_TRIM3 0x02 +#define PALMAS_GPADC_TRIM4 0x03 +#define PALMAS_GPADC_TRIM5 0x04 +#define PALMAS_GPADC_TRIM6 0x05 +#define PALMAS_GPADC_TRIM7 0x06 +#define PALMAS_GPADC_TRIM8 0x07 +#define PALMAS_GPADC_TRIM9 0x08 +#define PALMAS_GPADC_TRIM10 0x09 +#define PALMAS_GPADC_TRIM11 0x0A +#define PALMAS_GPADC_TRIM12 0x0B +#define PALMAS_GPADC_TRIM13 0x0C +#define PALMAS_GPADC_TRIM14 0x0D +#define PALMAS_GPADC_TRIM15 0x0E +#define PALMAS_GPADC_TRIM16 0x0F static inline int palmas_read(struct palmas *palmas, unsigned int base, unsigned int reg, unsigned int *val) { - unsigned int addr = PALMAS_BASE_TO_REG(base, reg); + unsigned int addr = PALMAS_BASE_TO_REG(base, reg); int slave_id = PALMAS_BASE_TO_SLAVE(base); return regmap_read(palmas->regmap[slave_id], addr, val); -- cgit v1.2.2