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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-07 20:20:53 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-07 20:20:53 -0400
commite0b8b78651350e8dcf9cc60a959ccbcfc5bc3061 (patch)
tree87cf0ed233021bb5c7486b35c2e34f1ea98b81c2 /drivers/pinctrl
parent54c72d5987ff9f3cf59529d5d4f5cf19eae3f695 (diff)
parente1ee5c578fb1fa24b7ccaf1a11237a2bd70b6f9a (diff)
Merge tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl updates from Linus Walleij: "This is the bulk pin control changes for the v3.17 merge development cycle: - get rid of the .disable() callback from the driver callback vtable. This callback was abused and counterintuitive since a pin or group of pins can be said to always be in some setting, and never really disabled. We now only enable a certain muxing, and move between some certain muxings, we never "disable" a mux setting - some janitorial moving the MSM, Samsung and Nomadik and drivers to their own subdirectories for a clearer view in the subsystem. This will continue - kill off the use of the return value from gpiochip_remove(), this will be done in parallel in the GPIO subsystem and hopefully not trigger too many unchecked return value warnings before we get rid of this altogether - a huge set of changes and improvements to the Allwinner sunxi drivers especially for their latest A23 and A31 SoCs, and some ground work for the new sun8i platform family - a large set of Rockchip driver improvements adding support for the RK3288 SoC - advances in migration of older Freescale platforms to pin control, especially i.MX1 - Samsung and Exynos improvements - support for the Qualcomm MSM8960 SoC - use the gpiolib irqchip helpers for the ST SPEAr and Intel Baytrail drivers - a bunch of nice janitorial work done with cppcheck" * tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (61 commits) pinctrl: baytrail: Convert to use gpiolib irqchip pinctrl: sunxi: number gpio ranges starting from 0 pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ pinctrl: rockchip: add drive-strength control for rk3288 pinctrl: rockchip: add separate type for rk3288 pinctrl: rockchip: set is_generic in pinconf_ops pinctrl: msm: drop negativity check on unsigned value pinctrl: remove all usage of gpio_remove ret val in driver/pinctl pinctrl: qcom: Make muxing of gpio function explicit pinctrl: nomadik: move all Nomadik drivers to subdir pinctrl: samsung: Group all drivers in a sub-dir sh-pfc: sh73a0: Introduce the use of devm_regulator_register sh-pfc: Add renesas,pfc-r8a7791 to binding documentation pinctrl: msm: move all qualcomm drivers to subdir pinctrl: msm: Add msm8960 definitions pinctrl: samsung: Allow pin value to be initialized using pinfunc pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes pinctrl: exynos: Consolidate irq_chips of GPIO and WKUP EINTs pinctrl: samsung: Handle GPIO request and free using pinctrl helpers pinctrl: samsung: Decouple direction setting from pinctrl ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig117
-rw-r--r--drivers/pinctrl/Makefile24
-rw-r--r--drivers/pinctrl/core.c24
-rw-r--r--drivers/pinctrl/nomadik/Kconfig51
-rw-r--r--drivers/pinctrl/nomadik/Makefile10
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab8500.c (renamed from drivers/pinctrl/pinctrl-ab8500.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab8505.c (renamed from drivers/pinctrl/pinctrl-ab8505.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab8540.c (renamed from drivers/pinctrl/pinctrl-ab8540.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab9540.c (renamed from drivers/pinctrl/pinctrl-ab9540.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.c (renamed from drivers/pinctrl/pinctrl-abx500.c)19
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.h (renamed from drivers/pinctrl/pinctrl-abx500.h)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c (renamed from drivers/pinctrl/pinctrl-nomadik-db8500.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c (renamed from drivers/pinctrl/pinctrl-nomadik-db8540.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c (renamed from drivers/pinctrl/pinctrl-nomadik-stn8815.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.c (renamed from drivers/pinctrl/pinctrl-nomadik.c)18
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.h (renamed from drivers/pinctrl/pinctrl-nomadik.h)0
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c41
-rw-r--r--drivers/pinctrl/pinctrl-as3722.c11
-rw-r--r--drivers/pinctrl/pinctrl-at91.c27
-rw-r--r--drivers/pinctrl/pinctrl-baytrail.c103
-rw-r--r--drivers/pinctrl/pinctrl-bcm281xx.c2
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c11
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c10
-rw-r--r--drivers/pinctrl/pinctrl-imx.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx1-core.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx1.c279
-rw-r--r--drivers/pinctrl/pinctrl-imx27.c52
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c401
-rw-r--r--drivers/pinctrl/pinctrl-single.c61
-rw-r--r--drivers/pinctrl/pinctrl-st.c15
-rw-r--r--drivers/pinctrl/pinctrl-tb10x.c17
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c13
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c28
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c58
-rw-r--r--drivers/pinctrl/pinctrl-u300.c14
-rw-r--r--drivers/pinctrl/pinmux.c4
-rw-r--r--drivers/pinctrl/qcom/Kconfig42
-rw-r--r--drivers/pinctrl/qcom/Makefile6
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8064.c (renamed from drivers/pinctrl/pinctrl-apq8064.c)19
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq8064.c (renamed from drivers/pinctrl/pinctrl-ipq8064.c)17
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c (renamed from drivers/pinctrl/pinctrl-msm.c)42
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.h (renamed from drivers/pinctrl/pinctrl-msm.h)0
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8960.c1282
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8x74.c (renamed from drivers/pinctrl/pinctrl-msm8x74.c)29
-rw-r--r--drivers/pinctrl/samsung/Kconfig28
-rw-r--r--drivers/pinctrl/samsung/Makefile7
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c (renamed from drivers/pinctrl/pinctrl-exynos.c)307
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.h (renamed from drivers/pinctrl/pinctrl-exynos.h)0
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c (renamed from drivers/pinctrl/pinctrl-exynos5440.c)10
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c24xx.c (renamed from drivers/pinctrl/pinctrl-s3c24xx.c)0
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c64xx.c (renamed from drivers/pinctrl/pinctrl-s3c64xx.c)0
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c (renamed from drivers/pinctrl/pinctrl-samsung.c)728
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.h (renamed from drivers/pinctrl/pinctrl-samsung.h)18
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c9
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c417
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c11
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c22
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c10
-rw-r--r--drivers/pinctrl/spear/Kconfig1
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c84
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c7
-rw-r--r--drivers/pinctrl/sunxi/Kconfig24
-rw-r--r--drivers/pinctrl/sunxi/Makefile2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c4
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c217
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c142
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c593
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c187
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h44
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wmt.c21
74 files changed, 4198 insertions, 1550 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 0042ccb46b9a..4e3231ad03cd 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -11,10 +11,10 @@ menu "Pin controllers"
11 depends on PINCTRL 11 depends on PINCTRL
12 12
13config PINMUX 13config PINMUX
14 bool "Support pin multiplexing controllers" 14 bool "Support pin multiplexing controllers" if COMPILE_TEST
15 15
16config PINCONF 16config PINCONF
17 bool "Support pin configuration controllers" 17 bool "Support pin configuration controllers" if COMPILE_TEST
18 18
19config GENERIC_PINCONF 19config GENERIC_PINCONF
20 bool 20 bool
@@ -26,29 +26,6 @@ config DEBUG_PINCTRL
26 help 26 help
27 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28 28
29config PINCTRL_ABX500
30 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
31 depends on AB8500_CORE
32 select GENERIC_PINCONF
33 help
34 Select this to enable the ABx500 family IC GPIO driver
35
36config PINCTRL_AB8500
37 bool "AB8500 pin controller driver"
38 depends on PINCTRL_ABX500 && ARCH_U8500
39
40config PINCTRL_AB8540
41 bool "AB8540 pin controller driver"
42 depends on PINCTRL_ABX500 && ARCH_U8500
43
44config PINCTRL_AB9540
45 bool "AB9540 pin controller driver"
46 depends on PINCTRL_ABX500 && ARCH_U8500
47
48config PINCTRL_AB8505
49 bool "AB8505 pin controller driver"
50 depends on PINCTRL_ABX500 && ARCH_U8500
51
52config PINCTRL_ADI2 29config PINCTRL_ADI2
53 bool "ADI pin controller driver" 30 bool "ADI pin controller driver"
54 depends on BLACKFIN 31 depends on BLACKFIN
@@ -93,7 +70,7 @@ config PINCTRL_AT91
93config PINCTRL_BAYTRAIL 70config PINCTRL_BAYTRAIL
94 bool "Intel Baytrail GPIO pin control" 71 bool "Intel Baytrail GPIO pin control"
95 depends on GPIOLIB && ACPI && X86 72 depends on GPIOLIB && ACPI && X86
96 select IRQ_DOMAIN 73 select GPIOLIB_IRQCHIP
97 help 74 help
98 driver for memory mapped GPIO functionality on Intel Baytrail 75 driver for memory mapped GPIO functionality on Intel Baytrail
99 platforms. Supports 3 banks with 102, 28 and 44 gpios. 76 platforms. Supports 3 banks with 102, 28 and 44 gpios.
@@ -130,6 +107,13 @@ config PINCTRL_IMX1_CORE
130 select PINMUX 107 select PINMUX
131 select PINCONF 108 select PINCONF
132 109
110config PINCTRL_IMX1
111 bool "IMX1 pinctrl driver"
112 depends on SOC_IMX1
113 select PINCTRL_IMX1_CORE
114 help
115 Say Y here to enable the imx1 pinctrl driver
116
133config PINCTRL_IMX27 117config PINCTRL_IMX27
134 bool "IMX27 pinctrl driver" 118 bool "IMX27 pinctrl driver"
135 depends on SOC_IMX27 119 depends on SOC_IMX27
@@ -226,58 +210,6 @@ config PINCTRL_IMX28
226 bool 210 bool
227 select PINCTRL_MXS 211 select PINCTRL_MXS
228 212
229config PINCTRL_MSM
230 bool
231 select PINMUX
232 select PINCONF
233 select GENERIC_PINCONF
234 select GPIOLIB_IRQCHIP
235
236config PINCTRL_APQ8064
237 tristate "Qualcomm APQ8064 pin controller driver"
238 depends on GPIOLIB && OF
239 select PINCTRL_MSM
240 help
241 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
242 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
243
244config PINCTRL_IPQ8064
245 tristate "Qualcomm IPQ8064 pin controller driver"
246 depends on GPIOLIB && OF
247 select PINCTRL_MSM
248 help
249 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
250 Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
251
252config PINCTRL_MSM8X74
253 tristate "Qualcomm 8x74 pin controller driver"
254 depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST)
255 select PINCTRL_MSM
256 help
257 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
258 Qualcomm TLMM block found in the Qualcomm 8974 platform.
259
260config PINCTRL_NOMADIK
261 bool "Nomadik pin controller driver"
262 depends on ARCH_U8500 || ARCH_NOMADIK
263 select PINMUX
264 select PINCONF
265 select GPIOLIB
266 select OF_GPIO
267 select GPIOLIB_IRQCHIP
268
269config PINCTRL_STN8815
270 bool "STN8815 pin controller driver"
271 depends on PINCTRL_NOMADIK && ARCH_NOMADIK
272
273config PINCTRL_DB8500
274 bool "DB8500 pin controller driver"
275 depends on PINCTRL_NOMADIK && ARCH_U8500
276
277config PINCTRL_DB8540
278 bool "DB8540 pin controller driver"
279 depends on PINCTRL_NOMADIK && ARCH_U8500
280
281config PINCTRL_ROCKCHIP 213config PINCTRL_ROCKCHIP
282 bool 214 bool
283 select PINMUX 215 select PINMUX
@@ -356,22 +288,6 @@ config PINCTRL_COH901
356 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 288 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
357 ports of 8 GPIO pins each. 289 ports of 8 GPIO pins each.
358 290
359config PINCTRL_SAMSUNG
360 bool
361 select PINMUX
362 select PINCONF
363
364config PINCTRL_EXYNOS
365 bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
366 depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
367 select PINCTRL_SAMSUNG
368
369config PINCTRL_EXYNOS5440
370 bool "Samsung EXYNOS5440 SoC pinctrl driver"
371 depends on SOC_EXYNOS5440
372 select PINMUX
373 select PINCONF
374
375config PINCTRL_PALMAS 291config PINCTRL_PALMAS
376 bool "Pinctrl driver for the PALMAS Series MFD devices" 292 bool "Pinctrl driver for the PALMAS Series MFD devices"
377 depends on OF && MFD_PALMAS 293 depends on OF && MFD_PALMAS
@@ -383,18 +299,11 @@ config PINCTRL_PALMAS
383 open drain configuration for the Palmas series devices like 299 open drain configuration for the Palmas series devices like
384 TPS65913, TPS80036 etc. 300 TPS65913, TPS80036 etc.
385 301
386config PINCTRL_S3C24XX
387 bool "Samsung S3C24XX SoC pinctrl driver"
388 depends on ARCH_S3C24XX
389 select PINCTRL_SAMSUNG
390
391config PINCTRL_S3C64XX
392 bool "Samsung S3C64XX SoC pinctrl driver"
393 depends on ARCH_S3C64XX
394 select PINCTRL_SAMSUNG
395
396source "drivers/pinctrl/berlin/Kconfig" 302source "drivers/pinctrl/berlin/Kconfig"
397source "drivers/pinctrl/mvebu/Kconfig" 303source "drivers/pinctrl/mvebu/Kconfig"
304source "drivers/pinctrl/nomadik/Kconfig"
305source "drivers/pinctrl/qcom/Kconfig"
306source "drivers/pinctrl/samsung/Kconfig"
398source "drivers/pinctrl/sh-pfc/Kconfig" 307source "drivers/pinctrl/sh-pfc/Kconfig"
399source "drivers/pinctrl/spear/Kconfig" 308source "drivers/pinctrl/spear/Kconfig"
400source "drivers/pinctrl/sunxi/Kconfig" 309source "drivers/pinctrl/sunxi/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index c4b5d405b8f5..e90817c1f584 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,11 +9,6 @@ ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o 9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif 10endif
11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
13obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
14obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
15obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
17obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o 12obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
18obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o 13obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
19obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o 14obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
@@ -24,6 +19,7 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
24obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o 19obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
25obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o 20obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
26obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o 21obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
22obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
27obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o 23obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
28obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o 24obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
29obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o 25obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
@@ -38,14 +34,6 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
38obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 34obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
39obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o 35obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
40obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o 36obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
41obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
42obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
43obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
44obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
45obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
46obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
47obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
48obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
49obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o 37obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
50obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o 38obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
51obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 39obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
@@ -59,11 +47,6 @@ obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
59obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o 47obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
60obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o 48obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
61obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 49obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
62obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
63obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
64obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
65obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o
66obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
67obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o 50obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
68obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 51obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
69obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o 52obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
@@ -72,8 +55,11 @@ obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
72 55
73obj-$(CONFIG_ARCH_BERLIN) += berlin/ 56obj-$(CONFIG_ARCH_BERLIN) += berlin/
74obj-$(CONFIG_PLAT_ORION) += mvebu/ 57obj-$(CONFIG_PLAT_ORION) += mvebu/
58obj-y += nomadik/
59obj-$(CONFIG_ARCH_QCOM) += qcom/
60obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
75obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ 61obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
76obj-$(CONFIG_SUPERH) += sh-pfc/ 62obj-$(CONFIG_SUPERH) += sh-pfc/
77obj-$(CONFIG_PLAT_SPEAR) += spear/ 63obj-$(CONFIG_PLAT_SPEAR) += spear/
78obj-$(CONFIG_ARCH_VT8500) += vt8500/
79obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 64obj-$(CONFIG_ARCH_SUNXI) += sunxi/
65obj-$(CONFIG_ARCH_VT8500) += vt8500/
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index e09474ecde23..e4f65510c87e 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -992,29 +992,15 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
992 992
993 if (p->state) { 993 if (p->state) {
994 /* 994 /*
995 * The set of groups with a mux configuration in the old state 995 * For each pinmux setting in the old state, forget SW's record
996 * may not be identical to the set of groups with a mux setting 996 * of mux owner for that pingroup. Any pingroups which are
997 * in the new state. While this might be unusual, it's entirely 997 * still owned by the new state will be re-acquired by the call
998 * possible for the "user"-supplied mapping table to be written 998 * to pinmux_enable_setting() in the loop below.
999 * that way. For each group that was configured in the old state
1000 * but not in the new state, this code puts that group into a
1001 * safe/disabled state.
1002 */ 999 */
1003 list_for_each_entry(setting, &p->state->settings, node) { 1000 list_for_each_entry(setting, &p->state->settings, node) {
1004 bool found = false;
1005 if (setting->type != PIN_MAP_TYPE_MUX_GROUP) 1001 if (setting->type != PIN_MAP_TYPE_MUX_GROUP)
1006 continue; 1002 continue;
1007 list_for_each_entry(setting2, &state->settings, node) { 1003 pinmux_disable_setting(setting);
1008 if (setting2->type != PIN_MAP_TYPE_MUX_GROUP)
1009 continue;
1010 if (setting2->data.mux.group ==
1011 setting->data.mux.group) {
1012 found = true;
1013 break;
1014 }
1015 }
1016 if (!found)
1017 pinmux_disable_setting(setting);
1018 } 1004 }
1019 } 1005 }
1020 1006
diff --git a/drivers/pinctrl/nomadik/Kconfig b/drivers/pinctrl/nomadik/Kconfig
new file mode 100644
index 000000000000..d48a5aa24a29
--- /dev/null
+++ b/drivers/pinctrl/nomadik/Kconfig
@@ -0,0 +1,51 @@
1if ARCH_U8500
2
3config PINCTRL_ABX500
4 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
5 depends on AB8500_CORE
6 select GENERIC_PINCONF
7 help
8 Select this to enable the ABx500 family IC GPIO driver
9
10config PINCTRL_AB8500
11 bool "AB8500 pin controller driver"
12 depends on PINCTRL_ABX500 && ARCH_U8500
13
14config PINCTRL_AB8540
15 bool "AB8540 pin controller driver"
16 depends on PINCTRL_ABX500 && ARCH_U8500
17
18config PINCTRL_AB9540
19 bool "AB9540 pin controller driver"
20 depends on PINCTRL_ABX500 && ARCH_U8500
21
22config PINCTRL_AB8505
23 bool "AB8505 pin controller driver"
24 depends on PINCTRL_ABX500 && ARCH_U8500
25
26endif
27
28if (ARCH_U8500 || ARCH_NOMADIK)
29
30config PINCTRL_NOMADIK
31 bool "Nomadik pin controller driver"
32 depends on ARCH_U8500 || ARCH_NOMADIK
33 select PINMUX
34 select PINCONF
35 select GPIOLIB
36 select OF_GPIO
37 select GPIOLIB_IRQCHIP
38
39config PINCTRL_STN8815
40 bool "STN8815 pin controller driver"
41 depends on PINCTRL_NOMADIK && ARCH_NOMADIK
42
43config PINCTRL_DB8500
44 bool "DB8500 pin controller driver"
45 depends on PINCTRL_NOMADIK && ARCH_U8500
46
47config PINCTRL_DB8540
48 bool "DB8540 pin controller driver"
49 depends on PINCTRL_NOMADIK && ARCH_U8500
50
51endif
diff --git a/drivers/pinctrl/nomadik/Makefile b/drivers/pinctrl/nomadik/Makefile
new file mode 100644
index 000000000000..30b27f18cd52
--- /dev/null
+++ b/drivers/pinctrl/nomadik/Makefile
@@ -0,0 +1,10 @@
1# Nomadik family pin control drivers
2obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
3obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
4obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
5obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
6obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
7obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
8obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
9obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
10obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
diff --git a/drivers/pinctrl/pinctrl-ab8500.c b/drivers/pinctrl/nomadik/pinctrl-ab8500.c
index 2ac2d0ad3025..2ac2d0ad3025 100644
--- a/drivers/pinctrl/pinctrl-ab8500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-ab8500.c
diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c
index bf0ef4ac376f..bf0ef4ac376f 100644
--- a/drivers/pinctrl/pinctrl-ab8505.c
+++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c
diff --git a/drivers/pinctrl/pinctrl-ab8540.c b/drivers/pinctrl/nomadik/pinctrl-ab8540.c
index 9867535d49c1..9867535d49c1 100644
--- a/drivers/pinctrl/pinctrl-ab8540.c
+++ b/drivers/pinctrl/nomadik/pinctrl-ab8540.c
diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/nomadik/pinctrl-ab9540.c
index 1a281ca95dac..1a281ca95dac 100644
--- a/drivers/pinctrl/pinctrl-ab9540.c
+++ b/drivers/pinctrl/nomadik/pinctrl-ab9540.c
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index 163da9c3ea0e..a53a689a2bfa 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -32,8 +32,8 @@
32#include <linux/pinctrl/machine.h> 32#include <linux/pinctrl/machine.h>
33 33
34#include "pinctrl-abx500.h" 34#include "pinctrl-abx500.h"
35#include "core.h" 35#include "../core.h"
36#include "pinconf.h" 36#include "../pinconf.h"
37 37
38/* 38/*
39 * The AB9540 and AB8540 GPIO support are extended versions 39 * The AB9540 and AB8540 GPIO support are extended versions
@@ -737,20 +737,6 @@ static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
737 return ret; 737 return ret;
738} 738}
739 739
740static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
741 unsigned function, unsigned group)
742{
743 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
744 const struct abx500_pingroup *g;
745
746 g = &pct->soc->groups[group];
747 if (g->altsetting < 0)
748 return;
749
750 /* FIXME: poke out the mux, set the pin to some default state? */
751 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
752}
753
754static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, 740static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
755 struct pinctrl_gpio_range *range, 741 struct pinctrl_gpio_range *range,
756 unsigned offset) 742 unsigned offset)
@@ -799,7 +785,6 @@ static const struct pinmux_ops abx500_pinmux_ops = {
799 .get_function_name = abx500_pmx_get_func_name, 785 .get_function_name = abx500_pmx_get_func_name,
800 .get_function_groups = abx500_pmx_get_func_groups, 786 .get_function_groups = abx500_pmx_get_func_groups,
801 .enable = abx500_pmx_enable, 787 .enable = abx500_pmx_enable,
802 .disable = abx500_pmx_disable,
803 .gpio_request_enable = abx500_gpio_request_enable, 788 .gpio_request_enable = abx500_gpio_request_enable,
804 .gpio_disable_free = abx500_gpio_disable_free, 789 .gpio_disable_free = abx500_gpio_disable_free,
805}; 790};
diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/nomadik/pinctrl-abx500.h
index 2beef3bfe9ca..2beef3bfe9ca 100644
--- a/drivers/pinctrl/pinctrl-abx500.h
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.h
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
index c74840729648..c74840729648 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
index d7ba5443bae0..d7ba5443bae0 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8540.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
diff --git a/drivers/pinctrl/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
index ed39dcafd4f8..ed39dcafd4f8 100644
--- a/drivers/pinctrl/pinctrl-nomadik-stn8815.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index 8f6f16ef73f3..e7cab07eef47 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -31,7 +31,7 @@
31/* Since we request GPIOs from ourself */ 31/* Since we request GPIOs from ourself */
32#include <linux/pinctrl/consumer.h> 32#include <linux/pinctrl/consumer.h>
33#include "pinctrl-nomadik.h" 33#include "pinctrl-nomadik.h"
34#include "core.h" 34#include "../core.h"
35 35
36/* 36/*
37 * The GPIO module in the Nomadik family of Systems-on-Chip is an 37 * The GPIO module in the Nomadik family of Systems-on-Chip is an
@@ -1765,21 +1765,6 @@ out_glitch:
1765 return ret; 1765 return ret;
1766} 1766}
1767 1767
1768static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1769 unsigned function, unsigned group)
1770{
1771 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1772 const struct nmk_pingroup *g;
1773
1774 g = &npct->soc->groups[group];
1775
1776 if (g->altsetting < 0)
1777 return;
1778
1779 /* Poke out the mux, set the pin to some default state? */
1780 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1781}
1782
1783static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1768static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1784 struct pinctrl_gpio_range *range, 1769 struct pinctrl_gpio_range *range,
1785 unsigned offset) 1770 unsigned offset)
@@ -1826,7 +1811,6 @@ static const struct pinmux_ops nmk_pinmux_ops = {
1826 .get_function_name = nmk_pmx_get_func_name, 1811 .get_function_name = nmk_pmx_get_func_name,
1827 .get_function_groups = nmk_pmx_get_func_groups, 1812 .get_function_groups = nmk_pmx_get_func_groups,
1828 .enable = nmk_pmx_enable, 1813 .enable = nmk_pmx_enable,
1829 .disable = nmk_pmx_disable,
1830 .gpio_request_enable = nmk_gpio_request_enable, 1814 .gpio_request_enable = nmk_gpio_request_enable,
1831 .gpio_disable_free = nmk_gpio_disable_free, 1815 .gpio_disable_free = nmk_gpio_disable_free,
1832}; 1816};
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/nomadik/pinctrl-nomadik.h
index d8215f1e70c7..d8215f1e70c7 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.h
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
index 5c44feb54ebb..b092b93c67a1 100644
--- a/drivers/pinctrl/pinctrl-adi2.c
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -401,7 +401,7 @@ static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
401 401
402 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 402 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
403 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 403 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
404 snprintf(buf, 16, "gpio-irq%d", irq); 404 snprintf(buf, 16, "gpio-irq%u", irq);
405 port_setup(port, d->hwirq, true); 405 port_setup(port, d->hwirq, true);
406 } else 406 } else
407 goto out; 407 goto out;
@@ -652,35 +652,6 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id,
652 return 0; 652 return 0;
653} 653}
654 654
655static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id,
656 unsigned group_id)
657{
658 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
659 struct gpio_port *port;
660 struct pinctrl_gpio_range *range;
661 unsigned long flags;
662 unsigned short *mux, pin;
663
664 mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
665
666 while (*mux) {
667 pin = P_IDENT(*mux);
668
669 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
670 if (range == NULL) /* should not happen */
671 return;
672
673 port = container_of(range->gc, struct gpio_port, chip);
674
675 spin_lock_irqsave(&port->lock, flags);
676
677 port_setup(port, pin_to_offset(range, pin), true);
678 mux++;
679
680 spin_unlock_irqrestore(&port->lock, flags);
681 }
682}
683
684static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) 655static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
685{ 656{
686 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); 657 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -728,7 +699,6 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
728 699
729static struct pinmux_ops adi_pinmux_ops = { 700static struct pinmux_ops adi_pinmux_ops = {
730 .enable = adi_pinmux_enable, 701 .enable = adi_pinmux_enable,
731 .disable = adi_pinmux_disable,
732 .get_functions_count = adi_pinmux_get_funcs_count, 702 .get_functions_count = adi_pinmux_get_funcs_count,
733 .get_function_name = adi_pinmux_get_func_name, 703 .get_function_name = adi_pinmux_get_func_name,
734 .get_function_groups = adi_pinmux_get_groups, 704 .get_function_groups = adi_pinmux_get_groups,
@@ -979,7 +949,7 @@ static int adi_gpio_probe(struct platform_device *pdev)
979 struct gpio_port *port; 949 struct gpio_port *port;
980 char pinctrl_devname[DEVNAME_SIZE]; 950 char pinctrl_devname[DEVNAME_SIZE];
981 static int gpio; 951 static int gpio;
982 int ret = 0, ret1; 952 int ret = 0;
983 953
984 pdata = dev->platform_data; 954 pdata = dev->platform_data;
985 if (!pdata) 955 if (!pdata)
@@ -1057,7 +1027,7 @@ static int adi_gpio_probe(struct platform_device *pdev)
1057 return 0; 1027 return 0;
1058 1028
1059out_remove_gpiochip: 1029out_remove_gpiochip:
1060 ret1 = gpiochip_remove(&port->chip); 1030 gpiochip_remove(&port->chip);
1061out_remove_domain: 1031out_remove_domain:
1062 if (port->pint) 1032 if (port->pint)
1063 irq_domain_remove(port->domain); 1033 irq_domain_remove(port->domain);
@@ -1068,12 +1038,11 @@ out_remove_domain:
1068static int adi_gpio_remove(struct platform_device *pdev) 1038static int adi_gpio_remove(struct platform_device *pdev)
1069{ 1039{
1070 struct gpio_port *port = platform_get_drvdata(pdev); 1040 struct gpio_port *port = platform_get_drvdata(pdev);
1071 int ret;
1072 u8 offset; 1041 u8 offset;
1073 1042
1074 list_del(&port->node); 1043 list_del(&port->node);
1075 gpiochip_remove_pin_ranges(&port->chip); 1044 gpiochip_remove_pin_ranges(&port->chip);
1076 ret = gpiochip_remove(&port->chip); 1045 gpiochip_remove(&port->chip);
1077 if (port->pint) { 1046 if (port->pint) {
1078 for (offset = 0; offset < port->width; offset++) 1047 for (offset = 0; offset < port->width; offset++)
1079 irq_dispose_mapping(irq_find_mapping(port->domain, 1048 irq_dispose_mapping(irq_find_mapping(port->domain,
@@ -1081,7 +1050,7 @@ static int adi_gpio_remove(struct platform_device *pdev)
1081 irq_domain_remove(port->domain); 1050 irq_domain_remove(port->domain);
1082 } 1051 }
1083 1052
1084 return ret; 1053 return 0;
1085} 1054}
1086 1055
1087static int adi_pinctrl_probe(struct platform_device *pdev) 1056static int adi_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
index c862f9c0e9ce..0e4ec91f4d49 100644
--- a/drivers/pinctrl/pinctrl-as3722.c
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -565,7 +565,6 @@ static int as3722_pinctrl_probe(struct platform_device *pdev)
565{ 565{
566 struct as3722_pctrl_info *as_pci; 566 struct as3722_pctrl_info *as_pci;
567 int ret; 567 int ret;
568 int tret;
569 568
570 as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL); 569 as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
571 if (!as_pci) 570 if (!as_pci)
@@ -611,10 +610,7 @@ static int as3722_pinctrl_probe(struct platform_device *pdev)
611 return 0; 610 return 0;
612 611
613fail_range_add: 612fail_range_add:
614 tret = gpiochip_remove(&as_pci->gpio_chip); 613 gpiochip_remove(&as_pci->gpio_chip);
615 if (tret < 0)
616 dev_warn(&pdev->dev, "Couldn't remove gpio chip, %d\n", tret);
617
618fail_chip_add: 614fail_chip_add:
619 pinctrl_unregister(as_pci->pctl); 615 pinctrl_unregister(as_pci->pctl);
620 return ret; 616 return ret;
@@ -623,11 +619,8 @@ fail_chip_add:
623static int as3722_pinctrl_remove(struct platform_device *pdev) 619static int as3722_pinctrl_remove(struct platform_device *pdev)
624{ 620{
625 struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev); 621 struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
626 int ret;
627 622
628 ret = gpiochip_remove(&as_pci->gpio_chip); 623 gpiochip_remove(&as_pci->gpio_chip);
629 if (ret < 0)
630 return ret;
631 pinctrl_unregister(as_pci->pctl); 624 pinctrl_unregister(as_pci->pctl);
632 return 0; 625 return 0;
633} 626}
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 421493cb490c..af1ba4fc150d 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -611,26 +611,6 @@ static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
611 return 0; 611 return 0;
612} 612}
613 613
614static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
615 unsigned group)
616{
617 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
618 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
619 const struct at91_pmx_pin *pin;
620 uint32_t npins = info->groups[group].npins;
621 int i;
622 unsigned mask;
623 void __iomem *pio;
624
625 for (i = 0; i < npins; i++) {
626 pin = &pins_conf[i];
627 at91_pin_dbg(info->dev, pin);
628 pio = pin_to_controller(info, pin->bank);
629 mask = pin_to_mask(pin->pin);
630 at91_mux_gpio_enable(pio, mask, 1);
631 }
632}
633
634static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 614static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
635{ 615{
636 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 616 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
@@ -705,7 +685,6 @@ static const struct pinmux_ops at91_pmx_ops = {
705 .get_function_name = at91_pmx_get_func_name, 685 .get_function_name = at91_pmx_get_func_name,
706 .get_function_groups = at91_pmx_get_groups, 686 .get_function_groups = at91_pmx_get_groups,
707 .enable = at91_pmx_enable, 687 .enable = at91_pmx_enable,
708 .disable = at91_pmx_disable,
709 .gpio_request_enable = at91_gpio_request_enable, 688 .gpio_request_enable = at91_gpio_request_enable,
710 .gpio_disable_free = at91_gpio_disable_free, 689 .gpio_disable_free = at91_gpio_disable_free,
711}; 690};
@@ -793,9 +772,9 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
793 struct seq_file *s, unsigned pin_id) 772 struct seq_file *s, unsigned pin_id)
794{ 773{
795 unsigned long config; 774 unsigned long config;
796 int ret, val, num_conf = 0; 775 int val, num_conf = 0;
797 776
798 ret = at91_pinconf_get(pctldev, pin_id, &config); 777 at91_pinconf_get(pctldev, pin_id, &config);
799 778
800 DBG_SHOW_FLAG(MULTI_DRIVE); 779 DBG_SHOW_FLAG(MULTI_DRIVE);
801 DBG_SHOW_FLAG(PULL_UP); 780 DBG_SHOW_FLAG(PULL_UP);
@@ -945,7 +924,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np,
945 /* Initialise function */ 924 /* Initialise function */
946 func->name = np->name; 925 func->name = np->name;
947 func->ngroups = of_get_child_count(np); 926 func->ngroups = of_get_child_count(np);
948 if (func->ngroups <= 0) { 927 if (func->ngroups == 0) {
949 dev_err(info->dev, "no groups defined\n"); 928 dev_err(info->dev, "no groups defined\n");
950 return -EINVAL; 929 return -EINVAL;
951 } 930 }
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
index 975572e2f260..9ca59a018743 100644
--- a/drivers/pinctrl/pinctrl-baytrail.c
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -25,9 +25,7 @@
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/bitops.h> 26#include <linux/bitops.h>
27#include <linux/interrupt.h> 27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/gpio.h> 28#include <linux/gpio.h>
30#include <linux/irqdomain.h>
31#include <linux/acpi.h> 29#include <linux/acpi.h>
32#include <linux/platform_device.h> 30#include <linux/platform_device.h>
33#include <linux/seq_file.h> 31#include <linux/seq_file.h>
@@ -44,6 +42,7 @@
44 42
45/* BYT_CONF0_REG register bits */ 43/* BYT_CONF0_REG register bits */
46#define BYT_IODEN BIT(31) 44#define BYT_IODEN BIT(31)
45#define BYT_DIRECT_IRQ_EN BIT(27)
47#define BYT_TRIG_NEG BIT(26) 46#define BYT_TRIG_NEG BIT(26)
48#define BYT_TRIG_POS BIT(25) 47#define BYT_TRIG_POS BIT(25)
49#define BYT_TRIG_LVL BIT(24) 48#define BYT_TRIG_LVL BIT(24)
@@ -137,7 +136,6 @@ static struct pinctrl_gpio_range byt_ranges[] = {
137 136
138struct byt_gpio { 137struct byt_gpio {
139 struct gpio_chip chip; 138 struct gpio_chip chip;
140 struct irq_domain *domain;
141 struct platform_device *pdev; 139 struct platform_device *pdev;
142 spinlock_t lock; 140 spinlock_t lock;
143 void __iomem *reg_base; 141 void __iomem *reg_base;
@@ -217,7 +215,7 @@ static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
217 215
218static int byt_irq_type(struct irq_data *d, unsigned type) 216static int byt_irq_type(struct irq_data *d, unsigned type)
219{ 217{
220 struct byt_gpio *vg = irq_data_get_irq_chip_data(d); 218 struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
221 u32 offset = irqd_to_hwirq(d); 219 u32 offset = irqd_to_hwirq(d);
222 u32 value; 220 u32 value;
223 unsigned long flags; 221 unsigned long flags;
@@ -303,12 +301,22 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
303 unsigned gpio, int value) 301 unsigned gpio, int value)
304{ 302{
305 struct byt_gpio *vg = to_byt_gpio(chip); 303 struct byt_gpio *vg = to_byt_gpio(chip);
304 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
306 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); 305 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
307 unsigned long flags; 306 unsigned long flags;
308 u32 reg_val; 307 u32 reg_val;
309 308
310 spin_lock_irqsave(&vg->lock, flags); 309 spin_lock_irqsave(&vg->lock, flags);
311 310
311 /*
312 * Before making any direction modifications, do a check if gpio
313 * is set for direct IRQ. On baytrail, setting GPIO to output does
314 * not make sense, so let's at least warn the caller before they shoot
315 * themselves in the foot.
316 */
317 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
318 "Potential Error: Setting GPIO with direct_irq_en to output");
319
312 reg_val = readl(reg) | BYT_DIR_MASK; 320 reg_val = readl(reg) | BYT_DIR_MASK;
313 reg_val &= ~BYT_OUTPUT_EN; 321 reg_val &= ~BYT_OUTPUT_EN;
314 322
@@ -393,16 +401,10 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
393 spin_unlock_irqrestore(&vg->lock, flags); 401 spin_unlock_irqrestore(&vg->lock, flags);
394} 402}
395 403
396static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
397{
398 struct byt_gpio *vg = to_byt_gpio(chip);
399 return irq_create_mapping(vg->domain, offset);
400}
401
402static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 404static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
403{ 405{
404 struct irq_data *data = irq_desc_get_irq_data(desc); 406 struct irq_data *data = irq_desc_get_irq_data(desc);
405 struct byt_gpio *vg = irq_data_get_irq_handler_data(data); 407 struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
406 struct irq_chip *chip = irq_data_get_irq_chip(data); 408 struct irq_chip *chip = irq_data_get_irq_chip(data);
407 u32 base, pin, mask; 409 u32 base, pin, mask;
408 void __iomem *reg; 410 void __iomem *reg;
@@ -421,7 +423,7 @@ static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
421 /* Clear before handling so we can't lose an edge */ 423 /* Clear before handling so we can't lose an edge */
422 writel(mask, reg); 424 writel(mask, reg);
423 425
424 virq = irq_find_mapping(vg->domain, base + pin); 426 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
425 generic_handle_irq(virq); 427 generic_handle_irq(virq);
426 428
427 /* In case bios or user sets triggering incorretly a pin 429 /* In case bios or user sets triggering incorretly a pin
@@ -454,33 +456,11 @@ static void byt_irq_mask(struct irq_data *d)
454{ 456{
455} 457}
456 458
457static int byt_irq_reqres(struct irq_data *d)
458{
459 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
460
461 if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
462 dev_err(vg->chip.dev,
463 "unable to lock HW IRQ %lu for IRQ\n",
464 irqd_to_hwirq(d));
465 return -EINVAL;
466 }
467 return 0;
468}
469
470static void byt_irq_relres(struct irq_data *d)
471{
472 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
473
474 gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
475}
476
477static struct irq_chip byt_irqchip = { 459static struct irq_chip byt_irqchip = {
478 .name = "BYT-GPIO", 460 .name = "BYT-GPIO",
479 .irq_mask = byt_irq_mask, 461 .irq_mask = byt_irq_mask,
480 .irq_unmask = byt_irq_unmask, 462 .irq_unmask = byt_irq_unmask,
481 .irq_set_type = byt_irq_type, 463 .irq_set_type = byt_irq_type,
482 .irq_request_resources = byt_irq_reqres,
483 .irq_release_resources = byt_irq_relres,
484}; 464};
485 465
486static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 466static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
@@ -501,23 +481,6 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
501 } 481 }
502} 482}
503 483
504static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
505 irq_hw_number_t hw)
506{
507 struct byt_gpio *vg = d->host_data;
508
509 irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
510 "demux");
511 irq_set_chip_data(virq, vg);
512 irq_set_irq_type(virq, IRQ_TYPE_NONE);
513
514 return 0;
515}
516
517static const struct irq_domain_ops byt_gpio_irq_ops = {
518 .map = byt_gpio_irq_map,
519};
520
521static int byt_gpio_probe(struct platform_device *pdev) 484static int byt_gpio_probe(struct platform_device *pdev)
522{ 485{
523 struct byt_gpio *vg; 486 struct byt_gpio *vg;
@@ -527,7 +490,6 @@ static int byt_gpio_probe(struct platform_device *pdev)
527 struct acpi_device *acpi_dev; 490 struct acpi_device *acpi_dev;
528 struct pinctrl_gpio_range *range; 491 struct pinctrl_gpio_range *range;
529 acpi_handle handle = ACPI_HANDLE(dev); 492 acpi_handle handle = ACPI_HANDLE(dev);
530 unsigned hwirq;
531 int ret; 493 int ret;
532 494
533 if (acpi_bus_get_device(handle, &acpi_dev)) 495 if (acpi_bus_get_device(handle, &acpi_dev))
@@ -574,27 +536,27 @@ static int byt_gpio_probe(struct platform_device *pdev)
574 gc->can_sleep = false; 536 gc->can_sleep = false;
575 gc->dev = dev; 537 gc->dev = dev;
576 538
539 ret = gpiochip_add(gc);
540 if (ret) {
541 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
542 return ret;
543 }
544
577 /* set up interrupts */ 545 /* set up interrupts */
578 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 546 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
579 if (irq_rc && irq_rc->start) { 547 if (irq_rc && irq_rc->start) {
580 hwirq = irq_rc->start;
581 gc->to_irq = byt_gpio_to_irq;
582
583 vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
584 &byt_gpio_irq_ops, vg);
585 if (!vg->domain)
586 return -ENXIO;
587
588 byt_gpio_irq_init_hw(vg); 548 byt_gpio_irq_init_hw(vg);
549 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
550 handle_simple_irq, IRQ_TYPE_NONE);
551 if (ret) {
552 dev_err(dev, "failed to add irqchip\n");
553 gpiochip_remove(gc);
554 return ret;
555 }
589 556
590 irq_set_handler_data(hwirq, vg); 557 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
591 irq_set_chained_handler(hwirq, byt_gpio_irq_handler); 558 (unsigned)irq_rc->start,
592 } 559 byt_gpio_irq_handler);
593
594 ret = gpiochip_add(gc);
595 if (ret) {
596 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
597 return ret;
598 } 560 }
599 561
600 pm_runtime_enable(dev); 562 pm_runtime_enable(dev);
@@ -627,12 +589,9 @@ MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
627static int byt_gpio_remove(struct platform_device *pdev) 589static int byt_gpio_remove(struct platform_device *pdev)
628{ 590{
629 struct byt_gpio *vg = platform_get_drvdata(pdev); 591 struct byt_gpio *vg = platform_get_drvdata(pdev);
630 int err;
631 592
632 pm_runtime_disable(&pdev->dev); 593 pm_runtime_disable(&pdev->dev);
633 err = gpiochip_remove(&vg->chip); 594 gpiochip_remove(&vg->chip);
634 if (err)
635 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
636 595
637 return 0; 596 return 0;
638} 597}
diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/pinctrl-bcm281xx.c
index 3bed792b2c03..c5ca9e633fff 100644
--- a/drivers/pinctrl/pinctrl-bcm281xx.c
+++ b/drivers/pinctrl/pinctrl-bcm281xx.c
@@ -1396,7 +1396,7 @@ static struct pinctrl_desc bcm281xx_pinctrl_desc = {
1396 .owner = THIS_MODULE, 1396 .owner = THIS_MODULE,
1397}; 1397};
1398 1398
1399int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) 1399static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1400{ 1400{
1401 struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl; 1401 struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
1402 struct resource *res; 1402 struct resource *res;
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index 3d907de9bc91..5bcfd7ace0cd 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -841,16 +841,6 @@ static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
841 return 0; 841 return 0;
842} 842}
843 843
844static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev,
845 unsigned func_selector,
846 unsigned group_selector)
847{
848 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
849
850 /* disable by setting to GPIO_IN */
851 bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN);
852}
853
854static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 844static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
855 struct pinctrl_gpio_range *range, 845 struct pinctrl_gpio_range *range,
856 unsigned offset) 846 unsigned offset)
@@ -880,7 +870,6 @@ static const struct pinmux_ops bcm2835_pmx_ops = {
880 .get_function_name = bcm2835_pmx_get_function_name, 870 .get_function_name = bcm2835_pmx_get_function_name,
881 .get_function_groups = bcm2835_pmx_get_function_groups, 871 .get_function_groups = bcm2835_pmx_get_function_groups,
882 .enable = bcm2835_pmx_enable, 872 .enable = bcm2835_pmx_enable,
883 .disable = bcm2835_pmx_disable,
884 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 873 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
885 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 874 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
886}; 875};
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index d182fdd2e715..29cbbab8c3a6 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -756,8 +756,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
756 756
757err_no_range: 757err_no_range:
758err_no_irqchip: 758err_no_irqchip:
759 if (gpiochip_remove(&gpio->chip)) 759 gpiochip_remove(&gpio->chip);
760 dev_err(&pdev->dev, "failed to remove gpio chip\n");
761err_no_chip: 760err_no_chip:
762 clk_disable_unprepare(gpio->clk); 761 clk_disable_unprepare(gpio->clk);
763 dev_err(&pdev->dev, "module ERROR:%d\n", err); 762 dev_err(&pdev->dev, "module ERROR:%d\n", err);
@@ -767,16 +766,11 @@ err_no_chip:
767static int __exit u300_gpio_remove(struct platform_device *pdev) 766static int __exit u300_gpio_remove(struct platform_device *pdev)
768{ 767{
769 struct u300_gpio *gpio = platform_get_drvdata(pdev); 768 struct u300_gpio *gpio = platform_get_drvdata(pdev);
770 int err;
771 769
772 /* Turn off the GPIO block */ 770 /* Turn off the GPIO block */
773 writel(0x00000000U, gpio->base + U300_GPIO_CR); 771 writel(0x00000000U, gpio->base + U300_GPIO_CR);
774 772
775 err = gpiochip_remove(&gpio->chip); 773 gpiochip_remove(&gpio->chip);
776 if (err < 0) {
777 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
778 return err;
779 }
780 clk_disable_unprepare(gpio->clk); 774 clk_disable_unprepare(gpio->clk);
781 return 0; 775 return 0;
782} 776}
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index a24448e5d399..946d594a64dd 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -515,7 +515,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
515 /* Initialise function */ 515 /* Initialise function */
516 func->name = np->name; 516 func->name = np->name;
517 func->num_groups = of_get_child_count(np); 517 func->num_groups = of_get_child_count(np);
518 if (func->num_groups <= 0) { 518 if (func->num_groups == 0) {
519 dev_err(info->dev, "no groups defined in %s\n", np->full_name); 519 dev_err(info->dev, "no groups defined in %s\n", np->full_name);
520 return -EINVAL; 520 return -EINVAL;
521 } 521 }
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c
index 815384b377b5..483420757c9f 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -526,7 +526,7 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
526 /* Initialise function */ 526 /* Initialise function */
527 func->name = np->name; 527 func->name = np->name;
528 func->num_groups = of_get_child_count(np); 528 func->num_groups = of_get_child_count(np);
529 if (func->num_groups <= 0) 529 if (func->num_groups == 0)
530 return -EINVAL; 530 return -EINVAL;
531 531
532 func->groups = devm_kzalloc(info->dev, 532 func->groups = devm_kzalloc(info->dev,
diff --git a/drivers/pinctrl/pinctrl-imx1.c b/drivers/pinctrl/pinctrl-imx1.c
new file mode 100644
index 000000000000..533a6e519648
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx1.c
@@ -0,0 +1,279 @@
1/*
2 * i.MX1 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx1.h"
18
19#define PAD_ID(port, pin) ((port) * 32 + (pin))
20#define PA 0
21#define PB 1
22#define PC 2
23#define PD 3
24
25enum imx1_pads {
26 MX1_PAD_A24 = PAD_ID(PA, 0),
27 MX1_PAD_TIN = PAD_ID(PA, 1),
28 MX1_PAD_PWMO = PAD_ID(PA, 2),
29 MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
30 MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
31 MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
32 MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
33 MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
34 MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
35 MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
36 MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
37 MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
38 MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
39 MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
40 MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
41 MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
42 MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
43 MX1_PAD_DTACK = PAD_ID(PA, 17),
44 MX1_PAD_BCLK = PAD_ID(PA, 18),
45 MX1_PAD_LBA = PAD_ID(PA, 19),
46 MX1_PAD_ECB = PAD_ID(PA, 20),
47 MX1_PAD_A0 = PAD_ID(PA, 21),
48 MX1_PAD_CS4 = PAD_ID(PA, 22),
49 MX1_PAD_CS5 = PAD_ID(PA, 23),
50 MX1_PAD_A16 = PAD_ID(PA, 24),
51 MX1_PAD_A17 = PAD_ID(PA, 25),
52 MX1_PAD_A18 = PAD_ID(PA, 26),
53 MX1_PAD_A19 = PAD_ID(PA, 27),
54 MX1_PAD_A20 = PAD_ID(PA, 28),
55 MX1_PAD_A21 = PAD_ID(PA, 29),
56 MX1_PAD_A22 = PAD_ID(PA, 30),
57 MX1_PAD_A23 = PAD_ID(PA, 31),
58 MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
59 MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
60 MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
61 MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
62 MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
63 MX1_PAD_SD_CMD = PAD_ID(PB, 13),
64 MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
65 MX1_PAD_SIM_PD = PAD_ID(PB, 15),
66 MX1_PAD_SIM_TX = PAD_ID(PB, 16),
67 MX1_PAD_SIM_RX = PAD_ID(PB, 17),
68 MX1_PAD_SIM_RST = PAD_ID(PB, 18),
69 MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
70 MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
71 MX1_PAD_USBD_OE = PAD_ID(PB, 21),
72 MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
73 MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
74 MX1_PAD_USBD_VP = PAD_ID(PB, 24),
75 MX1_PAD_USBD_VM = PAD_ID(PB, 25),
76 MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
77 MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
78 MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
79 MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
80 MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
81 MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
82 MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
83 MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
84 MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
85 MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
86 MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
87 MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
88 MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
89 MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
90 MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
91 MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
92 MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
93 MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
94 MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
95 MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
96 MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
97 MX1_PAD_BT13 = PAD_ID(PC, 19),
98 MX1_PAD_BT12 = PAD_ID(PC, 20),
99 MX1_PAD_BT11 = PAD_ID(PC, 21),
100 MX1_PAD_BT10 = PAD_ID(PC, 22),
101 MX1_PAD_BT9 = PAD_ID(PC, 23),
102 MX1_PAD_BT8 = PAD_ID(PC, 24),
103 MX1_PAD_BT7 = PAD_ID(PC, 25),
104 MX1_PAD_BT6 = PAD_ID(PC, 26),
105 MX1_PAD_BT5 = PAD_ID(PC, 27),
106 MX1_PAD_BT4 = PAD_ID(PC, 28),
107 MX1_PAD_BT3 = PAD_ID(PC, 29),
108 MX1_PAD_BT2 = PAD_ID(PC, 30),
109 MX1_PAD_BT1 = PAD_ID(PC, 31),
110 MX1_PAD_LSCLK = PAD_ID(PD, 6),
111 MX1_PAD_REV = PAD_ID(PD, 7),
112 MX1_PAD_CLS = PAD_ID(PD, 8),
113 MX1_PAD_PS = PAD_ID(PD, 9),
114 MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
115 MX1_PAD_CONTRAST = PAD_ID(PD, 11),
116 MX1_PAD_ACD_OE = PAD_ID(PD, 12),
117 MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
118 MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
119 MX1_PAD_LD0 = PAD_ID(PD, 15),
120 MX1_PAD_LD1 = PAD_ID(PD, 16),
121 MX1_PAD_LD2 = PAD_ID(PD, 17),
122 MX1_PAD_LD3 = PAD_ID(PD, 18),
123 MX1_PAD_LD4 = PAD_ID(PD, 19),
124 MX1_PAD_LD5 = PAD_ID(PD, 20),
125 MX1_PAD_LD6 = PAD_ID(PD, 21),
126 MX1_PAD_LD7 = PAD_ID(PD, 22),
127 MX1_PAD_LD8 = PAD_ID(PD, 23),
128 MX1_PAD_LD9 = PAD_ID(PD, 24),
129 MX1_PAD_LD10 = PAD_ID(PD, 25),
130 MX1_PAD_LD11 = PAD_ID(PD, 26),
131 MX1_PAD_LD12 = PAD_ID(PD, 27),
132 MX1_PAD_LD13 = PAD_ID(PD, 28),
133 MX1_PAD_LD14 = PAD_ID(PD, 29),
134 MX1_PAD_LD15 = PAD_ID(PD, 30),
135 MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
136};
137
138/* Pad names for the pinmux subsystem */
139static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
140 IMX_PINCTRL_PIN(MX1_PAD_A24),
141 IMX_PINCTRL_PIN(MX1_PAD_TIN),
142 IMX_PINCTRL_PIN(MX1_PAD_PWMO),
143 IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
144 IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
145 IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
146 IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
147 IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
148 IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
149 IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
150 IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
151 IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
152 IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
153 IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
154 IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
155 IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
156 IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
157 IMX_PINCTRL_PIN(MX1_PAD_DTACK),
158 IMX_PINCTRL_PIN(MX1_PAD_BCLK),
159 IMX_PINCTRL_PIN(MX1_PAD_LBA),
160 IMX_PINCTRL_PIN(MX1_PAD_ECB),
161 IMX_PINCTRL_PIN(MX1_PAD_A0),
162 IMX_PINCTRL_PIN(MX1_PAD_CS4),
163 IMX_PINCTRL_PIN(MX1_PAD_CS5),
164 IMX_PINCTRL_PIN(MX1_PAD_A16),
165 IMX_PINCTRL_PIN(MX1_PAD_A17),
166 IMX_PINCTRL_PIN(MX1_PAD_A18),
167 IMX_PINCTRL_PIN(MX1_PAD_A19),
168 IMX_PINCTRL_PIN(MX1_PAD_A20),
169 IMX_PINCTRL_PIN(MX1_PAD_A21),
170 IMX_PINCTRL_PIN(MX1_PAD_A22),
171 IMX_PINCTRL_PIN(MX1_PAD_A23),
172 IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
173 IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
174 IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
175 IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
176 IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
177 IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
178 IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
179 IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
180 IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
181 IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
182 IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
183 IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
184 IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
185 IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
186 IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
187 IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
188 IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
189 IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
190 IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
191 IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
192 IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
193 IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
194 IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
195 IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
196 IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
197 IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
198 IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
199 IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
200 IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
201 IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
202 IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
203 IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
204 IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
205 IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
206 IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
207 IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
208 IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
209 IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
210 IMX_PINCTRL_PIN(MX1_PAD_BT13),
211 IMX_PINCTRL_PIN(MX1_PAD_BT12),
212 IMX_PINCTRL_PIN(MX1_PAD_BT11),
213 IMX_PINCTRL_PIN(MX1_PAD_BT10),
214 IMX_PINCTRL_PIN(MX1_PAD_BT9),
215 IMX_PINCTRL_PIN(MX1_PAD_BT8),
216 IMX_PINCTRL_PIN(MX1_PAD_BT7),
217 IMX_PINCTRL_PIN(MX1_PAD_BT6),
218 IMX_PINCTRL_PIN(MX1_PAD_BT5),
219 IMX_PINCTRL_PIN(MX1_PAD_BT4),
220 IMX_PINCTRL_PIN(MX1_PAD_BT3),
221 IMX_PINCTRL_PIN(MX1_PAD_BT2),
222 IMX_PINCTRL_PIN(MX1_PAD_BT1),
223 IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
224 IMX_PINCTRL_PIN(MX1_PAD_REV),
225 IMX_PINCTRL_PIN(MX1_PAD_CLS),
226 IMX_PINCTRL_PIN(MX1_PAD_PS),
227 IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
228 IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
229 IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
230 IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
231 IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
232 IMX_PINCTRL_PIN(MX1_PAD_LD0),
233 IMX_PINCTRL_PIN(MX1_PAD_LD1),
234 IMX_PINCTRL_PIN(MX1_PAD_LD2),
235 IMX_PINCTRL_PIN(MX1_PAD_LD3),
236 IMX_PINCTRL_PIN(MX1_PAD_LD4),
237 IMX_PINCTRL_PIN(MX1_PAD_LD5),
238 IMX_PINCTRL_PIN(MX1_PAD_LD6),
239 IMX_PINCTRL_PIN(MX1_PAD_LD7),
240 IMX_PINCTRL_PIN(MX1_PAD_LD8),
241 IMX_PINCTRL_PIN(MX1_PAD_LD9),
242 IMX_PINCTRL_PIN(MX1_PAD_LD10),
243 IMX_PINCTRL_PIN(MX1_PAD_LD11),
244 IMX_PINCTRL_PIN(MX1_PAD_LD12),
245 IMX_PINCTRL_PIN(MX1_PAD_LD13),
246 IMX_PINCTRL_PIN(MX1_PAD_LD14),
247 IMX_PINCTRL_PIN(MX1_PAD_LD15),
248 IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
249};
250
251static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
252 .pins = imx1_pinctrl_pads,
253 .npins = ARRAY_SIZE(imx1_pinctrl_pads),
254};
255
256static int __init imx1_pinctrl_probe(struct platform_device *pdev)
257{
258 return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
259}
260
261static const struct of_device_id imx1_pinctrl_of_match[] = {
262 { .compatible = "fsl,imx1-iomuxc", },
263 { }
264};
265MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match);
266
267static struct platform_driver imx1_pinctrl_driver = {
268 .driver = {
269 .name = "imx1-pinctrl",
270 .owner = THIS_MODULE,
271 .of_match_table = imx1_pinctrl_of_match,
272 },
273 .remove = imx1_pinctrl_core_remove,
274};
275module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
276
277MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
278MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver");
279MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c
index 417c99205bc2..f8dfefb69968 100644
--- a/drivers/pinctrl/pinctrl-imx27.c
+++ b/drivers/pinctrl/pinctrl-imx27.c
@@ -63,10 +63,6 @@ enum imx27_pads {
63 MX27_PAD_CONTRAST = PAD_ID(PA, 30), 63 MX27_PAD_CONTRAST = PAD_ID(PA, 30),
64 MX27_PAD_OE_ACD = PAD_ID(PA, 31), 64 MX27_PAD_OE_ACD = PAD_ID(PA, 31),
65 65
66 MX27_PAD_UNUSED0 = PAD_ID(PB, 0),
67 MX27_PAD_UNUSED1 = PAD_ID(PB, 1),
68 MX27_PAD_UNUSED2 = PAD_ID(PB, 2),
69 MX27_PAD_UNUSED3 = PAD_ID(PB, 3),
70 MX27_PAD_SD2_D0 = PAD_ID(PB, 4), 66 MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
71 MX27_PAD_SD2_D1 = PAD_ID(PB, 5), 67 MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
72 MX27_PAD_SD2_D2 = PAD_ID(PB, 6), 68 MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
@@ -96,11 +92,6 @@ enum imx27_pads {
96 MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), 92 MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
97 MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), 93 MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
98 94
99 MX27_PAD_UNUSED4 = PAD_ID(PC, 0),
100 MX27_PAD_UNUSED5 = PAD_ID(PC, 1),
101 MX27_PAD_UNUSED6 = PAD_ID(PC, 2),
102 MX27_PAD_UNUSED7 = PAD_ID(PC, 3),
103 MX27_PAD_UNUSED8 = PAD_ID(PC, 4),
104 MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), 95 MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
105 MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), 96 MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
106 MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), 97 MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
@@ -188,12 +179,6 @@ enum imx27_pads {
188 MX27_PAD_SD1_CLK = PAD_ID(PE, 23), 179 MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
189 MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), 180 MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
190 MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), 181 MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
191 MX27_PAD_UNUSED9 = PAD_ID(PE, 26),
192 MX27_PAD_UNUSED10 = PAD_ID(PE, 27),
193 MX27_PAD_UNUSED11 = PAD_ID(PE, 28),
194 MX27_PAD_UNUSED12 = PAD_ID(PE, 29),
195 MX27_PAD_UNUSED13 = PAD_ID(PE, 30),
196 MX27_PAD_UNUSED14 = PAD_ID(PE, 31),
197 182
198 MX27_PAD_NFRB = PAD_ID(PF, 0), 183 MX27_PAD_NFRB = PAD_ID(PF, 0),
199 MX27_PAD_NFCLE = PAD_ID(PF, 1), 184 MX27_PAD_NFCLE = PAD_ID(PF, 1),
@@ -219,14 +204,6 @@ enum imx27_pads {
219 MX27_PAD_CS4_B = PAD_ID(PF, 21), 204 MX27_PAD_CS4_B = PAD_ID(PF, 21),
220 MX27_PAD_CS5_B = PAD_ID(PF, 22), 205 MX27_PAD_CS5_B = PAD_ID(PF, 22),
221 MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), 206 MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
222 MX27_PAD_UNUSED15 = PAD_ID(PF, 24),
223 MX27_PAD_UNUSED16 = PAD_ID(PF, 25),
224 MX27_PAD_UNUSED17 = PAD_ID(PF, 26),
225 MX27_PAD_UNUSED18 = PAD_ID(PF, 27),
226 MX27_PAD_UNUSED19 = PAD_ID(PF, 28),
227 MX27_PAD_UNUSED20 = PAD_ID(PF, 29),
228 MX27_PAD_UNUSED21 = PAD_ID(PF, 30),
229 MX27_PAD_UNUSED22 = PAD_ID(PF, 31),
230}; 207};
231 208
232/* Pad names for the pinmux subsystem */ 209/* Pad names for the pinmux subsystem */
@@ -264,10 +241,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
264 IMX_PINCTRL_PIN(MX27_PAD_CONTRAST), 241 IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
265 IMX_PINCTRL_PIN(MX27_PAD_OE_ACD), 242 IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
266 243
267 IMX_PINCTRL_PIN(MX27_PAD_UNUSED0),
268 IMX_PINCTRL_PIN(MX27_PAD_UNUSED1),
269 IMX_PINCTRL_PIN(MX27_PAD_UNUSED2),
270 IMX_PINCTRL_PIN(MX27_PAD_UNUSED3),
271 IMX_PINCTRL_PIN(MX27_PAD_SD2_D0), 244 IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
272 IMX_PINCTRL_PIN(MX27_PAD_SD2_D1), 245 IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
273 IMX_PINCTRL_PIN(MX27_PAD_SD2_D2), 246 IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
@@ -297,11 +270,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
297 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM), 270 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
298 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP), 271 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
299 272
300 IMX_PINCTRL_PIN(MX27_PAD_UNUSED4),
301 IMX_PINCTRL_PIN(MX27_PAD_UNUSED5),
302 IMX_PINCTRL_PIN(MX27_PAD_UNUSED6),
303 IMX_PINCTRL_PIN(MX27_PAD_UNUSED7),
304 IMX_PINCTRL_PIN(MX27_PAD_UNUSED8),
305 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA), 273 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
306 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL), 274 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
307 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5), 275 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
@@ -389,12 +357,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
389 IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK), 357 IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
390 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK), 358 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
391 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7), 359 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
392 IMX_PINCTRL_PIN(MX27_PAD_UNUSED9),
393 IMX_PINCTRL_PIN(MX27_PAD_UNUSED10),
394 IMX_PINCTRL_PIN(MX27_PAD_UNUSED11),
395 IMX_PINCTRL_PIN(MX27_PAD_UNUSED12),
396 IMX_PINCTRL_PIN(MX27_PAD_UNUSED13),
397 IMX_PINCTRL_PIN(MX27_PAD_UNUSED14),
398 360
399 IMX_PINCTRL_PIN(MX27_PAD_NFRB), 361 IMX_PINCTRL_PIN(MX27_PAD_NFRB),
400 IMX_PINCTRL_PIN(MX27_PAD_NFCLE), 362 IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
@@ -420,14 +382,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
420 IMX_PINCTRL_PIN(MX27_PAD_CS4_B), 382 IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
421 IMX_PINCTRL_PIN(MX27_PAD_CS5_B), 383 IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
422 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15), 384 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
423 IMX_PINCTRL_PIN(MX27_PAD_UNUSED15),
424 IMX_PINCTRL_PIN(MX27_PAD_UNUSED16),
425 IMX_PINCTRL_PIN(MX27_PAD_UNUSED17),
426 IMX_PINCTRL_PIN(MX27_PAD_UNUSED18),
427 IMX_PINCTRL_PIN(MX27_PAD_UNUSED19),
428 IMX_PINCTRL_PIN(MX27_PAD_UNUSED20),
429 IMX_PINCTRL_PIN(MX27_PAD_UNUSED21),
430 IMX_PINCTRL_PIN(MX27_PAD_UNUSED22),
431}; 385};
432 386
433static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { 387static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
@@ -440,12 +394,6 @@ static struct of_device_id imx27_pinctrl_of_match[] = {
440 { /* sentinel */ } 394 { /* sentinel */ }
441}; 395};
442 396
443struct imx27_pinctrl_private {
444 int num_gpio_childs;
445 struct platform_device **gpio_dev;
446 struct mxc_gpio_platform_data *gpio_pdata;
447};
448
449static int imx27_pinctrl_probe(struct platform_device *pdev) 397static int imx27_pinctrl_probe(struct platform_device *pdev)
450{ 398{
451 return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info); 399 return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index bb805d5e9ff0..5e8b2e04cd7a 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -62,11 +62,26 @@ enum rockchip_pinctrl_type {
62 RK2928, 62 RK2928,
63 RK3066B, 63 RK3066B,
64 RK3188, 64 RK3188,
65 RK3288,
65}; 66};
66 67
67enum rockchip_pin_bank_type { 68/**
68 COMMON_BANK, 69 * Encode variants of iomux registers into a type variable
69 RK3188_BANK0, 70 */
71#define IOMUX_GPIO_ONLY BIT(0)
72#define IOMUX_WIDTH_4BIT BIT(1)
73#define IOMUX_SOURCE_PMU BIT(2)
74#define IOMUX_UNROUTED BIT(3)
75
76/**
77 * @type: iomux variant using IOMUX_* constants
78 * @offset: if initialized to -1 it will be autocalculated, by specifying
79 * an initial offset value the relevant source offset can be reset
80 * to a new value for autocalculating the following iomux registers.
81 */
82struct rockchip_iomux {
83 int type;
84 int offset;
70}; 85};
71 86
72/** 87/**
@@ -78,6 +93,7 @@ enum rockchip_pin_bank_type {
78 * @nr_pins: number of pins in this bank 93 * @nr_pins: number of pins in this bank
79 * @name: name of the bank 94 * @name: name of the bank
80 * @bank_num: number of the bank, to account for holes 95 * @bank_num: number of the bank, to account for holes
96 * @iomux: array describing the 4 iomux sources of the bank
81 * @valid: are all necessary informations present 97 * @valid: are all necessary informations present
82 * @of_node: dt node of this bank 98 * @of_node: dt node of this bank
83 * @drvdata: common pinctrl basedata 99 * @drvdata: common pinctrl basedata
@@ -95,7 +111,7 @@ struct rockchip_pin_bank {
95 u8 nr_pins; 111 u8 nr_pins;
96 char *name; 112 char *name;
97 u8 bank_num; 113 u8 bank_num;
98 enum rockchip_pin_bank_type bank_type; 114 struct rockchip_iomux iomux[4];
99 bool valid; 115 bool valid;
100 struct device_node *of_node; 116 struct device_node *of_node;
101 struct rockchip_pinctrl *drvdata; 117 struct rockchip_pinctrl *drvdata;
@@ -111,6 +127,25 @@ struct rockchip_pin_bank {
111 .bank_num = id, \ 127 .bank_num = id, \
112 .nr_pins = pins, \ 128 .nr_pins = pins, \
113 .name = label, \ 129 .name = label, \
130 .iomux = { \
131 { .offset = -1 }, \
132 { .offset = -1 }, \
133 { .offset = -1 }, \
134 { .offset = -1 }, \
135 }, \
136 }
137
138#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
139 { \
140 .bank_num = id, \
141 .nr_pins = pins, \
142 .name = label, \
143 .iomux = { \
144 { .type = iom0, .offset = -1 }, \
145 { .type = iom1, .offset = -1 }, \
146 { .type = iom2, .offset = -1 }, \
147 { .type = iom3, .offset = -1 }, \
148 }, \
114 } 149 }
115 150
116/** 151/**
@@ -121,7 +156,8 @@ struct rockchip_pin_ctrl {
121 u32 nr_pins; 156 u32 nr_pins;
122 char *label; 157 char *label;
123 enum rockchip_pinctrl_type type; 158 enum rockchip_pinctrl_type type;
124 int mux_offset; 159 int grf_mux_offset;
160 int pmu_mux_offset;
125 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 161 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
126 int pin_num, struct regmap **regmap, 162 int pin_num, struct regmap **regmap,
127 int *reg, u8 *bit); 163 int *reg, u8 *bit);
@@ -343,24 +379,42 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
343static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 379static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
344{ 380{
345 struct rockchip_pinctrl *info = bank->drvdata; 381 struct rockchip_pinctrl *info = bank->drvdata;
382 int iomux_num = (pin / 8);
383 struct regmap *regmap;
346 unsigned int val; 384 unsigned int val;
347 int reg, ret; 385 int reg, ret, mask;
348 u8 bit; 386 u8 bit;
349 387
350 if (bank->bank_type == RK3188_BANK0 && pin < 16) 388 if (iomux_num > 3)
389 return -EINVAL;
390
391 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
392 dev_err(info->dev, "pin %d is unrouted\n", pin);
393 return -EINVAL;
394 }
395
396 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
351 return RK_FUNC_GPIO; 397 return RK_FUNC_GPIO;
352 398
399 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
400 ? info->regmap_pmu : info->regmap_base;
401
353 /* get basic quadrupel of mux registers and the correct reg inside */ 402 /* get basic quadrupel of mux registers and the correct reg inside */
354 reg = info->ctrl->mux_offset; 403 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
355 reg += bank->bank_num * 0x10; 404 reg = bank->iomux[iomux_num].offset;
356 reg += (pin / 8) * 4; 405 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
357 bit = (pin % 8) * 2; 406 if ((pin % 8) >= 4)
407 reg += 0x4;
408 bit = (pin % 4) * 4;
409 } else {
410 bit = (pin % 8) * 2;
411 }
358 412
359 ret = regmap_read(info->regmap_base, reg, &val); 413 ret = regmap_read(regmap, reg, &val);
360 if (ret) 414 if (ret)
361 return ret; 415 return ret;
362 416
363 return ((val >> bit) & 3); 417 return ((val >> bit) & mask);
364} 418}
365 419
366/* 420/*
@@ -379,16 +433,22 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
379static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 433static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
380{ 434{
381 struct rockchip_pinctrl *info = bank->drvdata; 435 struct rockchip_pinctrl *info = bank->drvdata;
382 int reg, ret; 436 int iomux_num = (pin / 8);
437 struct regmap *regmap;
438 int reg, ret, mask;
383 unsigned long flags; 439 unsigned long flags;
384 u8 bit; 440 u8 bit;
385 u32 data; 441 u32 data;
386 442
387 /* 443 if (iomux_num > 3)
388 * The first 16 pins of rk3188_bank0 are always gpios and do not have 444 return -EINVAL;
389 * a mux register at all. 445
390 */ 446 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
391 if (bank->bank_type == RK3188_BANK0 && pin < 16) { 447 dev_err(info->dev, "pin %d is unrouted\n", pin);
448 return -EINVAL;
449 }
450
451 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
392 if (mux != RK_FUNC_GPIO) { 452 if (mux != RK_FUNC_GPIO) {
393 dev_err(info->dev, 453 dev_err(info->dev,
394 "pin %d only supports a gpio mux\n", pin); 454 "pin %d only supports a gpio mux\n", pin);
@@ -401,17 +461,25 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
401 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 461 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
402 bank->bank_num, pin, mux); 462 bank->bank_num, pin, mux);
403 463
464 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
465 ? info->regmap_pmu : info->regmap_base;
466
404 /* get basic quadrupel of mux registers and the correct reg inside */ 467 /* get basic quadrupel of mux registers and the correct reg inside */
405 reg = info->ctrl->mux_offset; 468 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
406 reg += bank->bank_num * 0x10; 469 reg = bank->iomux[iomux_num].offset;
407 reg += (pin / 8) * 4; 470 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
408 bit = (pin % 8) * 2; 471 if ((pin % 8) >= 4)
472 reg += 0x4;
473 bit = (pin % 4) * 4;
474 } else {
475 bit = (pin % 8) * 2;
476 }
409 477
410 spin_lock_irqsave(&bank->slock, flags); 478 spin_lock_irqsave(&bank->slock, flags);
411 479
412 data = (3 << (bit + 16)); 480 data = (mask << (bit + 16));
413 data |= (mux & 3) << bit; 481 data |= (mux & mask) << bit;
414 ret = regmap_write(info->regmap_base, reg, data); 482 ret = regmap_write(regmap, reg, data);
415 483
416 spin_unlock_irqrestore(&bank->slock, flags); 484 spin_unlock_irqrestore(&bank->slock, flags);
417 485
@@ -449,7 +517,7 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
449 struct rockchip_pinctrl *info = bank->drvdata; 517 struct rockchip_pinctrl *info = bank->drvdata;
450 518
451 /* The first 12 pins of the first bank are located elsewhere */ 519 /* The first 12 pins of the first bank are located elsewhere */
452 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) { 520 if (bank->bank_num == 0 && pin_num < 12) {
453 *regmap = info->regmap_pmu ? info->regmap_pmu 521 *regmap = info->regmap_pmu ? info->regmap_pmu
454 : bank->regmap_pull; 522 : bank->regmap_pull;
455 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 523 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
@@ -476,6 +544,127 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
476 } 544 }
477} 545}
478 546
547#define RK3288_PULL_OFFSET 0x140
548static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
549 int pin_num, struct regmap **regmap,
550 int *reg, u8 *bit)
551{
552 struct rockchip_pinctrl *info = bank->drvdata;
553
554 /* The first 24 pins of the first bank are located in PMU */
555 if (bank->bank_num == 0) {
556 *regmap = info->regmap_pmu;
557 *reg = RK3188_PULL_PMU_OFFSET;
558
559 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
560 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
561 *bit *= RK3188_PULL_BITS_PER_PIN;
562 } else {
563 *regmap = info->regmap_base;
564 *reg = RK3288_PULL_OFFSET;
565
566 /* correct the offset, as we're starting with the 2nd bank */
567 *reg -= 0x10;
568 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
569 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
570
571 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
572 *bit *= RK3188_PULL_BITS_PER_PIN;
573 }
574}
575
576#define RK3288_DRV_PMU_OFFSET 0x70
577#define RK3288_DRV_GRF_OFFSET 0x1c0
578#define RK3288_DRV_BITS_PER_PIN 2
579#define RK3288_DRV_PINS_PER_REG 8
580#define RK3288_DRV_BANK_STRIDE 16
581static int rk3288_drv_list[] = { 2, 4, 8, 12 };
582
583static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
584 int pin_num, struct regmap **regmap,
585 int *reg, u8 *bit)
586{
587 struct rockchip_pinctrl *info = bank->drvdata;
588
589 /* The first 24 pins of the first bank are located in PMU */
590 if (bank->bank_num == 0) {
591 *regmap = info->regmap_pmu;
592 *reg = RK3288_DRV_PMU_OFFSET;
593
594 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
595 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
596 *bit *= RK3288_DRV_BITS_PER_PIN;
597 } else {
598 *regmap = info->regmap_base;
599 *reg = RK3288_DRV_GRF_OFFSET;
600
601 /* correct the offset, as we're starting with the 2nd bank */
602 *reg -= 0x10;
603 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
604 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
605
606 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
607 *bit *= RK3288_DRV_BITS_PER_PIN;
608 }
609}
610
611static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
612{
613 struct regmap *regmap;
614 int reg, ret;
615 u32 data;
616 u8 bit;
617
618 rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
619
620 ret = regmap_read(regmap, reg, &data);
621 if (ret)
622 return ret;
623
624 data >>= bit;
625 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
626
627 return rk3288_drv_list[data];
628}
629
630static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
631 int strength)
632{
633 struct rockchip_pinctrl *info = bank->drvdata;
634 struct regmap *regmap;
635 unsigned long flags;
636 int reg, ret, i;
637 u32 data;
638 u8 bit;
639
640 rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
641
642 ret = -EINVAL;
643 for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
644 if (rk3288_drv_list[i] == strength) {
645 ret = i;
646 break;
647 }
648 }
649
650 if (ret < 0) {
651 dev_err(info->dev, "unsupported driver strength %d\n",
652 strength);
653 return ret;
654 }
655
656 spin_lock_irqsave(&bank->slock, flags);
657
658 /* enable the write to the equivalent lower bits */
659 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
660 data |= (ret << bit);
661
662 ret = regmap_write(regmap, reg, data);
663 spin_unlock_irqrestore(&bank->slock, flags);
664
665 return ret;
666}
667
479static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 668static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
480{ 669{
481 struct rockchip_pinctrl *info = bank->drvdata; 670 struct rockchip_pinctrl *info = bank->drvdata;
@@ -501,6 +690,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
501 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 690 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
502 : PIN_CONFIG_BIAS_DISABLE; 691 : PIN_CONFIG_BIAS_DISABLE;
503 case RK3188: 692 case RK3188:
693 case RK3288:
504 data >>= bit; 694 data >>= bit;
505 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 695 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
506 696
@@ -555,6 +745,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
555 spin_unlock_irqrestore(&bank->slock, flags); 745 spin_unlock_irqrestore(&bank->slock, flags);
556 break; 746 break;
557 case RK3188: 747 case RK3188:
748 case RK3288:
558 spin_lock_irqsave(&bank->slock, flags); 749 spin_lock_irqsave(&bank->slock, flags);
559 750
560 /* enable the write to the equivalent lower bits */ 751 /* enable the write to the equivalent lower bits */
@@ -657,23 +848,6 @@ static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
657 return 0; 848 return 0;
658} 849}
659 850
660static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
661 unsigned selector, unsigned group)
662{
663 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
664 const unsigned int *pins = info->groups[group].pins;
665 struct rockchip_pin_bank *bank;
666 int cnt;
667
668 dev_dbg(info->dev, "disable function %s group %s\n",
669 info->functions[selector].name, info->groups[group].name);
670
671 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
672 bank = pin_to_bank(info, pins[cnt]);
673 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
674 }
675}
676
677/* 851/*
678 * The calls to gpio_direction_output() and gpio_direction_input() 852 * The calls to gpio_direction_output() and gpio_direction_input()
679 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 853 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
@@ -716,7 +890,6 @@ static const struct pinmux_ops rockchip_pmx_ops = {
716 .get_function_name = rockchip_pmx_get_func_name, 890 .get_function_name = rockchip_pmx_get_func_name,
717 .get_function_groups = rockchip_pmx_get_groups, 891 .get_function_groups = rockchip_pmx_get_groups,
718 .enable = rockchip_pmx_enable, 892 .enable = rockchip_pmx_enable,
719 .disable = rockchip_pmx_disable,
720 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 893 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
721}; 894};
722 895
@@ -734,6 +907,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
734 case RK3066B: 907 case RK3066B:
735 return pull ? false : true; 908 return pull ? false : true;
736 case RK3188: 909 case RK3188:
910 case RK3288:
737 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 911 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
738 } 912 }
739 913
@@ -788,6 +962,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
788 if (rc) 962 if (rc)
789 return rc; 963 return rc;
790 break; 964 break;
965 case PIN_CONFIG_DRIVE_STRENGTH:
966 /* rk3288 is the first with per-pin drive-strength */
967 if (info->ctrl->type != RK3288)
968 return -ENOTSUPP;
969
970 rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
971 if (rc < 0)
972 return rc;
973 break;
791 default: 974 default:
792 return -ENOTSUPP; 975 return -ENOTSUPP;
793 break; 976 break;
@@ -837,6 +1020,17 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
837 1020
838 arg = rc ? 1 : 0; 1021 arg = rc ? 1 : 0;
839 break; 1022 break;
1023 case PIN_CONFIG_DRIVE_STRENGTH:
1024 /* rk3288 is the first with per-pin drive-strength */
1025 if (info->ctrl->type != RK3288)
1026 return -ENOTSUPP;
1027
1028 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1029 if (rc < 0)
1030 return rc;
1031
1032 arg = rc;
1033 break;
840 default: 1034 default:
841 return -ENOTSUPP; 1035 return -ENOTSUPP;
842 break; 1036 break;
@@ -850,6 +1044,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
850static const struct pinconf_ops rockchip_pinconf_ops = { 1044static const struct pinconf_ops rockchip_pinconf_ops = {
851 .pin_config_get = rockchip_pinconf_get, 1045 .pin_config_get = rockchip_pinconf_get,
852 .pin_config_set = rockchip_pinconf_set, 1046 .pin_config_set = rockchip_pinconf_set,
1047 .is_generic = true,
853}; 1048};
854 1049
855static const struct of_device_id rockchip_bank_match[] = { 1050static const struct of_device_id rockchip_bank_match[] = {
@@ -1414,10 +1609,7 @@ fail:
1414 for (--i, --bank; i >= 0; --i, --bank) { 1609 for (--i, --bank; i >= 0; --i, --bank) {
1415 if (!bank->valid) 1610 if (!bank->valid)
1416 continue; 1611 continue;
1417 1612 gpiochip_remove(&bank->gpio_chip);
1418 if (gpiochip_remove(&bank->gpio_chip))
1419 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1420 bank->gpio_chip.label);
1421 } 1613 }
1422 return ret; 1614 return ret;
1423} 1615}
@@ -1427,20 +1619,15 @@ static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1427{ 1619{
1428 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1620 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1429 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1621 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1430 int ret = 0;
1431 int i; 1622 int i;
1432 1623
1433 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { 1624 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1434 if (!bank->valid) 1625 if (!bank->valid)
1435 continue; 1626 continue;
1436 1627 gpiochip_remove(&bank->gpio_chip);
1437 ret = gpiochip_remove(&bank->gpio_chip);
1438 } 1628 }
1439 1629
1440 if (ret) 1630 return 0;
1441 dev_err(&pdev->dev, "gpio chip remove failed\n");
1442
1443 return ret;
1444} 1631}
1445 1632
1446static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 1633static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
@@ -1466,8 +1653,6 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1466 "rockchip,rk3188-gpio-bank0")) { 1653 "rockchip,rk3188-gpio-bank0")) {
1467 struct device_node *node; 1654 struct device_node *node;
1468 1655
1469 bank->bank_type = RK3188_BANK0;
1470
1471 node = of_parse_phandle(bank->of_node->parent, 1656 node = of_parse_phandle(bank->of_node->parent,
1472 "rockchip,pmu", 0); 1657 "rockchip,pmu", 0);
1473 if (!node) { 1658 if (!node) {
@@ -1487,9 +1672,6 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1487 base, 1672 base,
1488 &rockchip_regmap_config); 1673 &rockchip_regmap_config);
1489 } 1674 }
1490
1491 } else {
1492 bank->bank_type = COMMON_BANK;
1493 } 1675 }
1494 1676
1495 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 1677 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
@@ -1513,7 +1695,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1513 struct device_node *np; 1695 struct device_node *np;
1514 struct rockchip_pin_ctrl *ctrl; 1696 struct rockchip_pin_ctrl *ctrl;
1515 struct rockchip_pin_bank *bank; 1697 struct rockchip_pin_bank *bank;
1516 int i; 1698 int grf_offs, pmu_offs, i, j;
1517 1699
1518 match = of_match_node(rockchip_pinctrl_dt_match, node); 1700 match = of_match_node(rockchip_pinctrl_dt_match, node);
1519 ctrl = (struct rockchip_pin_ctrl *)match->data; 1701 ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -1535,12 +1717,51 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1535 } 1717 }
1536 } 1718 }
1537 1719
1720 grf_offs = ctrl->grf_mux_offset;
1721 pmu_offs = ctrl->pmu_mux_offset;
1538 bank = ctrl->pin_banks; 1722 bank = ctrl->pin_banks;
1539 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1723 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1724 int bank_pins = 0;
1725
1540 spin_lock_init(&bank->slock); 1726 spin_lock_init(&bank->slock);
1541 bank->drvdata = d; 1727 bank->drvdata = d;
1542 bank->pin_base = ctrl->nr_pins; 1728 bank->pin_base = ctrl->nr_pins;
1543 ctrl->nr_pins += bank->nr_pins; 1729 ctrl->nr_pins += bank->nr_pins;
1730
1731 /* calculate iomux offsets */
1732 for (j = 0; j < 4; j++) {
1733 struct rockchip_iomux *iom = &bank->iomux[j];
1734 int inc;
1735
1736 if (bank_pins >= bank->nr_pins)
1737 break;
1738
1739 /* preset offset value, set new start value */
1740 if (iom->offset >= 0) {
1741 if (iom->type & IOMUX_SOURCE_PMU)
1742 pmu_offs = iom->offset;
1743 else
1744 grf_offs = iom->offset;
1745 } else { /* set current offset */
1746 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1747 pmu_offs : grf_offs;
1748 }
1749
1750 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1751 i, j, iom->offset);
1752
1753 /*
1754 * Increase offset according to iomux width.
1755 * 4bit iomux'es are spread over two registers.
1756 */
1757 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1758 if (iom->type & IOMUX_SOURCE_PMU)
1759 pmu_offs += inc;
1760 else
1761 grf_offs += inc;
1762
1763 bank_pins += 8;
1764 }
1544 } 1765 }
1545 1766
1546 return ctrl; 1767 return ctrl;
@@ -1644,7 +1865,7 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1644 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 1865 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1645 .label = "RK2928-GPIO", 1866 .label = "RK2928-GPIO",
1646 .type = RK2928, 1867 .type = RK2928,
1647 .mux_offset = 0xa8, 1868 .grf_mux_offset = 0xa8,
1648 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1869 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1649}; 1870};
1650 1871
@@ -1662,7 +1883,7 @@ static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1662 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 1883 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1663 .label = "RK3066a-GPIO", 1884 .label = "RK3066a-GPIO",
1664 .type = RK2928, 1885 .type = RK2928,
1665 .mux_offset = 0xa8, 1886 .grf_mux_offset = 0xa8,
1666 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1887 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1667}; 1888};
1668 1889
@@ -1678,11 +1899,11 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1678 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 1899 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1679 .label = "RK3066b-GPIO", 1900 .label = "RK3066b-GPIO",
1680 .type = RK3066B, 1901 .type = RK3066B,
1681 .mux_offset = 0x60, 1902 .grf_mux_offset = 0x60,
1682}; 1903};
1683 1904
1684static struct rockchip_pin_bank rk3188_pin_banks[] = { 1905static struct rockchip_pin_bank rk3188_pin_banks[] = {
1685 PIN_BANK(0, 32, "gpio0"), 1906 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
1686 PIN_BANK(1, 32, "gpio1"), 1907 PIN_BANK(1, 32, "gpio1"),
1687 PIN_BANK(2, 32, "gpio2"), 1908 PIN_BANK(2, 32, "gpio2"),
1688 PIN_BANK(3, 32, "gpio3"), 1909 PIN_BANK(3, 32, "gpio3"),
@@ -1693,10 +1914,52 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1693 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 1914 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1694 .label = "RK3188-GPIO", 1915 .label = "RK3188-GPIO",
1695 .type = RK3188, 1916 .type = RK3188,
1696 .mux_offset = 0x60, 1917 .grf_mux_offset = 0x60,
1697 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 1918 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
1698}; 1919};
1699 1920
1921static struct rockchip_pin_bank rk3288_pin_banks[] = {
1922 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
1923 IOMUX_SOURCE_PMU,
1924 IOMUX_SOURCE_PMU,
1925 IOMUX_UNROUTED
1926 ),
1927 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
1928 IOMUX_UNROUTED,
1929 IOMUX_UNROUTED,
1930 0
1931 ),
1932 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
1933 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
1934 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
1935 IOMUX_WIDTH_4BIT,
1936 0,
1937 0
1938 ),
1939 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
1940 0,
1941 0,
1942 IOMUX_UNROUTED
1943 ),
1944 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
1945 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
1946 0,
1947 IOMUX_WIDTH_4BIT,
1948 IOMUX_UNROUTED
1949 ),
1950 PIN_BANK(8, 16, "gpio8"),
1951};
1952
1953static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
1954 .pin_banks = rk3288_pin_banks,
1955 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
1956 .label = "RK3288-GPIO",
1957 .type = RK3288,
1958 .grf_mux_offset = 0x0,
1959 .pmu_mux_offset = 0x84,
1960 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
1961};
1962
1700static const struct of_device_id rockchip_pinctrl_dt_match[] = { 1963static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1701 { .compatible = "rockchip,rk2928-pinctrl", 1964 { .compatible = "rockchip,rk2928-pinctrl",
1702 .data = (void *)&rk2928_pin_ctrl }, 1965 .data = (void *)&rk2928_pin_ctrl },
@@ -1706,6 +1969,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1706 .data = (void *)&rk3066b_pin_ctrl }, 1969 .data = (void *)&rk3066b_pin_ctrl },
1707 { .compatible = "rockchip,rk3188-pinctrl", 1970 { .compatible = "rockchip,rk3188-pinctrl",
1708 .data = (void *)&rk3188_pin_ctrl }, 1971 .data = (void *)&rk3188_pin_ctrl },
1972 { .compatible = "rockchip,rk3288-pinctrl",
1973 .data = (void *)&rk3288_pin_ctrl },
1709 {}, 1974 {},
1710}; 1975};
1711MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 1976MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 2960557bfed9..95dd9cf55cb3 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -488,61 +488,6 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
488 return 0; 488 return 0;
489} 489}
490 490
491static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
492 unsigned group)
493{
494 struct pcs_device *pcs;
495 struct pcs_function *func;
496 int i;
497
498 pcs = pinctrl_dev_get_drvdata(pctldev);
499 /* If function mask is null, needn't disable it. */
500 if (!pcs->fmask)
501 return;
502
503 func = radix_tree_lookup(&pcs->ftree, fselector);
504 if (!func) {
505 dev_err(pcs->dev, "%s could not find function%i\n",
506 __func__, fselector);
507 return;
508 }
509
510 /*
511 * Ignore disable if function-off is not specified. Some hardware
512 * does not have clearly defined disable function. For pin specific
513 * off modes, you can use alternate named states as described in
514 * pinctrl-bindings.txt.
515 */
516 if (pcs->foff == PCS_OFF_DISABLED) {
517 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
518 func->name, fselector);
519 return;
520 }
521
522 dev_dbg(pcs->dev, "disabling function%i %s\n",
523 fselector, func->name);
524
525 for (i = 0; i < func->nvals; i++) {
526 struct pcs_func_vals *vals;
527 unsigned long flags;
528 unsigned val, mask;
529
530 vals = &func->vals[i];
531 raw_spin_lock_irqsave(&pcs->lock, flags);
532 val = pcs->read(vals->reg);
533
534 if (pcs->bits_per_mux)
535 mask = vals->mask;
536 else
537 mask = pcs->fmask;
538
539 val &= ~mask;
540 val |= pcs->foff << pcs->fshift;
541 pcs->write(val, vals->reg);
542 raw_spin_unlock_irqrestore(&pcs->lock, flags);
543 }
544}
545
546static int pcs_request_gpio(struct pinctrl_dev *pctldev, 491static int pcs_request_gpio(struct pinctrl_dev *pctldev,
547 struct pinctrl_gpio_range *range, unsigned pin) 492 struct pinctrl_gpio_range *range, unsigned pin)
548{ 493{
@@ -575,7 +520,6 @@ static const struct pinmux_ops pcs_pinmux_ops = {
575 .get_function_name = pcs_get_function_name, 520 .get_function_name = pcs_get_function_name,
576 .get_function_groups = pcs_get_function_groups, 521 .get_function_groups = pcs_get_function_groups,
577 .enable = pcs_enable, 522 .enable = pcs_enable,
578 .disable = pcs_disable,
579 .gpio_request_enable = pcs_request_gpio, 523 .gpio_request_enable = pcs_request_gpio,
580}; 524};
581 525
@@ -836,7 +780,7 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
836 780
837 pin = &pcs->pins.pa[i]; 781 pin = &pcs->pins.pa[i];
838 pn = &pcs->names[i]; 782 pn = &pcs->names[i];
839 sprintf(pn->name, "%lx.%d", 783 sprintf(pn->name, "%lx.%u",
840 (unsigned long)pcs->res->start + offset, pin_pos); 784 (unsigned long)pcs->res->start + offset, pin_pos);
841 pin->name = pn->name; 785 pin->name = pn->name;
842 pin->number = i; 786 pin->number = i;
@@ -1739,11 +1683,10 @@ static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1739{ 1683{
1740 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); 1684 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1741 struct irq_chip *chip; 1685 struct irq_chip *chip;
1742 int res;
1743 1686
1744 chip = irq_get_chip(irq); 1687 chip = irq_get_chip(irq);
1745 chained_irq_enter(chip, desc); 1688 chained_irq_enter(chip, desc);
1746 res = pcs_irq_handle(pcs_soc); 1689 pcs_irq_handle(pcs_soc);
1747 /* REVISIT: export and add handle_bad_irq(irq, desc)? */ 1690 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1748 chained_irq_exit(chip, desc); 1691 chained_irq_exit(chip, desc);
1749 1692
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 9f43916637ca..5475374d803f 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -930,11 +930,6 @@ static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector,
930 return 0; 930 return 0;
931} 931}
932 932
933static void st_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
934 unsigned group)
935{
936}
937
938static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 933static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
939 struct pinctrl_gpio_range *range, unsigned gpio, 934 struct pinctrl_gpio_range *range, unsigned gpio,
940 bool input) 935 bool input)
@@ -957,7 +952,6 @@ static struct pinmux_ops st_pmxops = {
957 .get_function_name = st_pmx_get_fname, 952 .get_function_name = st_pmx_get_fname,
958 .get_function_groups = st_pmx_get_groups, 953 .get_function_groups = st_pmx_get_groups,
959 .enable = st_pmx_enable, 954 .enable = st_pmx_enable,
960 .disable = st_pmx_disable,
961 .gpio_set_direction = st_pmx_set_gpio_direction, 955 .gpio_set_direction = st_pmx_set_gpio_direction,
962}; 956};
963 957
@@ -1178,9 +1172,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
1178 const __be32 *list; 1172 const __be32 *list;
1179 struct property *pp; 1173 struct property *pp;
1180 struct st_pinconf *conf; 1174 struct st_pinconf *conf;
1181 phandle phandle;
1182 struct device_node *pins; 1175 struct device_node *pins;
1183 u32 pin;
1184 int i = 0, npins = 0, nr_props; 1176 int i = 0, npins = 0, nr_props;
1185 1177
1186 pins = of_get_child_by_name(np, "st,pins"); 1178 pins = of_get_child_by_name(np, "st,pins");
@@ -1218,8 +1210,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
1218 conf = &grp->pin_conf[i]; 1210 conf = &grp->pin_conf[i];
1219 1211
1220 /* bank & offset */ 1212 /* bank & offset */
1221 phandle = be32_to_cpup(list++); 1213 be32_to_cpup(list++);
1222 pin = be32_to_cpup(list++); 1214 be32_to_cpup(list++);
1223 conf->pin = of_get_named_gpio(pins, pp->name, 0); 1215 conf->pin = of_get_named_gpio(pins, pp->name, 0);
1224 conf->name = pp->name; 1216 conf->name = pp->name;
1225 grp->pins[i] = conf->pin; 1217 grp->pins[i] = conf->pin;
@@ -1256,7 +1248,7 @@ static int st_pctl_parse_functions(struct device_node *np,
1256 func = &info->functions[index]; 1248 func = &info->functions[index];
1257 func->name = np->name; 1249 func->name = np->name;
1258 func->ngroups = of_get_child_count(np); 1250 func->ngroups = of_get_child_count(np);
1259 if (func->ngroups <= 0) { 1251 if (func->ngroups == 0) {
1260 dev_err(info->dev, "No groups defined\n"); 1252 dev_err(info->dev, "No groups defined\n");
1261 return -EINVAL; 1253 return -EINVAL;
1262 } 1254 }
@@ -1454,6 +1446,7 @@ static struct irq_chip st_gpio_irqchip = {
1454 .irq_mask = st_gpio_irq_mask, 1446 .irq_mask = st_gpio_irq_mask,
1455 .irq_unmask = st_gpio_irq_unmask, 1447 .irq_unmask = st_gpio_irq_unmask,
1456 .irq_set_type = st_gpio_irq_set_type, 1448 .irq_set_type = st_gpio_irq_set_type,
1449 .flags = IRQCHIP_SKIP_SET_WAKE,
1457}; 1450};
1458 1451
1459static int st_gpiolib_register_bank(struct st_pinctrl *info, 1452static int st_gpiolib_register_bank(struct st_pinctrl *info,
diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
index 26ca6855f478..71c5d4f0c538 100644
--- a/drivers/pinctrl/pinctrl-tb10x.c
+++ b/drivers/pinctrl/pinctrl-tb10x.c
@@ -738,22 +738,6 @@ static int tb10x_pctl_enable(struct pinctrl_dev *pctl,
738 return 0; 738 return 0;
739} 739}
740 740
741static void tb10x_pctl_disable(struct pinctrl_dev *pctl,
742 unsigned func_selector, unsigned group_selector)
743{
744 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
745 const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
746
747 if (grp->port < 0)
748 return;
749
750 mutex_lock(&state->mutex);
751
752 state->ports[grp->port].count--;
753
754 mutex_unlock(&state->mutex);
755}
756
757static struct pinmux_ops tb10x_pinmux_ops = { 741static struct pinmux_ops tb10x_pinmux_ops = {
758 .get_functions_count = tb10x_get_functions_count, 742 .get_functions_count = tb10x_get_functions_count,
759 .get_function_name = tb10x_get_function_name, 743 .get_function_name = tb10x_get_function_name,
@@ -761,7 +745,6 @@ static struct pinmux_ops tb10x_pinmux_ops = {
761 .gpio_request_enable = tb10x_gpio_request_enable, 745 .gpio_request_enable = tb10x_gpio_request_enable,
762 .gpio_disable_free = tb10x_gpio_disable_free, 746 .gpio_disable_free = tb10x_gpio_disable_free,
763 .enable = tb10x_pctl_enable, 747 .enable = tb10x_pctl_enable,
764 .disable = tb10x_pctl_disable,
765}; 748};
766 749
767static struct pinctrl_desc tb10x_pindesc = { 750static struct pinctrl_desc tb10x_pindesc = {
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 2d43bff74f59..150af5503c09 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -290,24 +290,11 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
290 return 0; 290 return 0;
291} 291}
292 292
293static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
294 unsigned function, unsigned group)
295{
296 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
297 const struct tegra_pingroup *g;
298
299 g = &pmx->soc->groups[group];
300
301 if (WARN_ON(g->mux_reg < 0))
302 return;
303}
304
305static const struct pinmux_ops tegra_pinmux_ops = { 293static const struct pinmux_ops tegra_pinmux_ops = {
306 .get_functions_count = tegra_pinctrl_get_funcs_count, 294 .get_functions_count = tegra_pinctrl_get_funcs_count,
307 .get_function_name = tegra_pinctrl_get_func_name, 295 .get_function_name = tegra_pinctrl_get_func_name,
308 .get_function_groups = tegra_pinctrl_get_func_groups, 296 .get_function_groups = tegra_pinctrl_get_func_groups,
309 .enable = tegra_pinctrl_enable, 297 .enable = tegra_pinctrl_enable,
310 .disable = tegra_pinctrl_disable,
311}; 298};
312 299
313static int tegra_pinconf_reg(struct tegra_pmx *pmx, 300static int tegra_pinconf_reg(struct tegra_pmx *pmx,
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
index 5bf01c28925e..41e81a35cabb 100644
--- a/drivers/pinctrl/pinctrl-tz1090-pdc.c
+++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c
@@ -574,33 +574,6 @@ static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev,
574 return 0; 574 return 0;
575} 575}
576 576
577static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev,
578 unsigned int function,
579 unsigned int group)
580{
581 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
582 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
583
584 dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
585 __func__,
586 function, tz1090_pdc_functions[function].name,
587 group, tz1090_pdc_groups[group].name);
588
589 /* is it even a mux? */
590 if (grp->drv)
591 return;
592
593 /* does this group even control the function? */
594 if (function != grp->func)
595 return;
596
597 /* record the pin being unmuxed and update mux bit */
598 spin_lock(&pmx->lock);
599 pmx->mux_en &= ~BIT(grp->pins[0]);
600 tz1090_pdc_pinctrl_mux(pmx, grp);
601 spin_unlock(&pmx->lock);
602}
603
604static const struct tz1090_pdc_pingroup *find_mux_group( 577static const struct tz1090_pdc_pingroup *find_mux_group(
605 struct tz1090_pdc_pmx *pmx, 578 struct tz1090_pdc_pmx *pmx,
606 unsigned int pin) 579 unsigned int pin)
@@ -662,7 +635,6 @@ static struct pinmux_ops tz1090_pdc_pinmux_ops = {
662 .get_function_name = tz1090_pdc_pinctrl_get_func_name, 635 .get_function_name = tz1090_pdc_pinctrl_get_func_name,
663 .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, 636 .get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
664 .enable = tz1090_pdc_pinctrl_enable, 637 .enable = tz1090_pdc_pinctrl_enable,
665 .disable = tz1090_pdc_pinctrl_disable,
666 .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, 638 .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
667 .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, 639 .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
668}; 640};
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
index bc9cd7a7602e..24082216842e 100644
--- a/drivers/pinctrl/pinctrl-tz1090.c
+++ b/drivers/pinctrl/pinctrl-tz1090.c
@@ -1479,63 +1479,6 @@ mux_pins:
1479} 1479}
1480 1480
1481/** 1481/**
1482 * tz1090_pinctrl_disable() - Disable a function on a pin group.
1483 * @pctldev: Pin control data
1484 * @function: Function index to disable
1485 * @group: Group index to disable
1486 *
1487 * Disable a particular function on a group of pins. The per GPIO pin pseudo pin
1488 * groups can be used (in which case the pin will be taken out of peripheral
1489 * mode. Some convenience pin groups can also be used in which case the effect
1490 * is the same as enabling the function on each individual pin in the group.
1491 */
1492static void tz1090_pinctrl_disable(struct pinctrl_dev *pctldev,
1493 unsigned int function, unsigned int group)
1494{
1495 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1496 struct tz1090_pingroup *grp;
1497 unsigned int pin_num, mux_group, i, npins;
1498 const unsigned int *pins;
1499
1500 /* group of pins? */
1501 if (group < ARRAY_SIZE(tz1090_groups)) {
1502 grp = &tz1090_groups[group];
1503 npins = grp->npins;
1504 pins = grp->pins;
1505 /*
1506 * All pins in the group must belong to the same mux group,
1507 * which allows us to just use the mux group of the first pin.
1508 * By explicitly listing permitted pingroups for each function
1509 * the pinmux core should ensure this is always the case.
1510 */
1511 } else {
1512 pin_num = group - ARRAY_SIZE(tz1090_groups);
1513 npins = 1;
1514 pins = &pin_num;
1515 }
1516 mux_group = tz1090_mux_pins[*pins];
1517
1518 /* no mux group, but can still be individually muxed to peripheral */
1519 if (mux_group >= TZ1090_MUX_GROUP_MAX) {
1520 if (function == TZ1090_MUX_PERIP)
1521 goto unmux_pins;
1522 return;
1523 }
1524
1525 /* mux group already set to a different function? */
1526 grp = &tz1090_mux_groups[mux_group];
1527 dev_dbg(pctldev->dev, "%s: unmuxing %u pin(s) in '%s' from '%s'\n",
1528 __func__, npins, grp->name, tz1090_functions[function].name);
1529
1530 /* subtract pins from ref count and unmux individually */
1531 WARN_ON(grp->func_count < npins);
1532 grp->func_count -= npins;
1533unmux_pins:
1534 for (i = 0; i < npins; ++i)
1535 tz1090_pinctrl_perip_select(pmx, pins[i], false);
1536}
1537
1538/**
1539 * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode. 1482 * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode.
1540 * @pctldev: Pin control data 1483 * @pctldev: Pin control data
1541 * @range: GPIO range 1484 * @range: GPIO range
@@ -1575,7 +1518,6 @@ static struct pinmux_ops tz1090_pinmux_ops = {
1575 .get_function_name = tz1090_pinctrl_get_func_name, 1518 .get_function_name = tz1090_pinctrl_get_func_name,
1576 .get_function_groups = tz1090_pinctrl_get_func_groups, 1519 .get_function_groups = tz1090_pinctrl_get_func_groups,
1577 .enable = tz1090_pinctrl_enable, 1520 .enable = tz1090_pinctrl_enable,
1578 .disable = tz1090_pinctrl_disable,
1579 .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, 1521 .gpio_request_enable = tz1090_pinctrl_gpio_request_enable,
1580 .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, 1522 .gpio_disable_free = tz1090_pinctrl_gpio_disable_free,
1581}; 1523};
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 209a01b8bd3b..0959bb36450f 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -970,19 +970,6 @@ static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
970 return 0; 970 return 0;
971} 971}
972 972
973static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
974 unsigned group)
975{
976 struct u300_pmx *upmx;
977
978 /* There is nothing to do with the power pins */
979 if (selector == 0)
980 return;
981
982 upmx = pinctrl_dev_get_drvdata(pctldev);
983 u300_pmx_endisable(upmx, selector, false);
984}
985
986static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 973static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
987{ 974{
988 return ARRAY_SIZE(u300_pmx_functions); 975 return ARRAY_SIZE(u300_pmx_functions);
@@ -1008,7 +995,6 @@ static const struct pinmux_ops u300_pmx_ops = {
1008 .get_function_name = u300_pmx_get_func_name, 995 .get_function_name = u300_pmx_get_func_name,
1009 .get_function_groups = u300_pmx_get_groups, 996 .get_function_groups = u300_pmx_get_groups,
1010 .enable = u300_pmx_enable, 997 .enable = u300_pmx_enable,
1011 .disable = u300_pmx_disable,
1012}; 998};
1013 999
1014static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1000static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 051e8592990e..c055daf9a80f 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -471,7 +471,6 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
471{ 471{
472 struct pinctrl_dev *pctldev = setting->pctldev; 472 struct pinctrl_dev *pctldev = setting->pctldev;
473 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 473 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
474 const struct pinmux_ops *ops = pctldev->desc->pmxops;
475 int ret = 0; 474 int ret = 0;
476 const unsigned *pins = NULL; 475 const unsigned *pins = NULL;
477 unsigned num_pins = 0; 476 unsigned num_pins = 0;
@@ -518,9 +517,6 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
518 pins[i], desc->name, gname); 517 pins[i], desc->name, gname);
519 } 518 }
520 } 519 }
521
522 if (ops->disable)
523 ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group);
524} 520}
525 521
526#ifdef CONFIG_DEBUG_FS 522#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
new file mode 100644
index 000000000000..d160a710d704
--- /dev/null
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -0,0 +1,42 @@
1if (ARCH_QCOM || COMPILE_TEST)
2
3config PINCTRL_MSM
4 bool
5 select PINMUX
6 select PINCONF
7 select GENERIC_PINCONF
8 select GPIOLIB_IRQCHIP
9
10config PINCTRL_APQ8064
11 tristate "Qualcomm APQ8064 pin controller driver"
12 depends on GPIOLIB && OF
13 select PINCTRL_MSM
14 help
15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
16 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
17
18config PINCTRL_IPQ8064
19 tristate "Qualcomm IPQ8064 pin controller driver"
20 depends on GPIOLIB && OF
21 select PINCTRL_MSM
22 help
23 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
24 Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
25
26config PINCTRL_MSM8960
27 tristate "Qualcomm 8960 pin controller driver"
28 depends on GPIOLIB && OF
29 select PINCTRL_MSM
30 help
31 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
32 Qualcomm TLMM block found in the Qualcomm 8960 platform.
33
34config PINCTRL_MSM8X74
35 tristate "Qualcomm 8x74 pin controller driver"
36 depends on GPIOLIB && OF
37 select PINCTRL_MSM
38 help
39 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
40 Qualcomm TLMM block found in the Qualcomm 8974 platform.
41
42endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
new file mode 100644
index 000000000000..2a02602d715c
--- /dev/null
+++ b/drivers/pinctrl/qcom/Makefile
@@ -0,0 +1,6 @@
1# Qualcomm pin control drivers
2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
4obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
5obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
6obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c
index 519f7886b0f1..feb6f152f9b7 100644
--- a/drivers/pinctrl/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -230,7 +230,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
230 .pins = gpio##id##_pins, \ 230 .pins = gpio##id##_pins, \
231 .npins = ARRAY_SIZE(gpio##id##_pins), \ 231 .npins = ARRAY_SIZE(gpio##id##_pins), \
232 .funcs = (int[]){ \ 232 .funcs = (int[]){ \
233 APQ_MUX_NA, /* gpio mode */ \ 233 APQ_MUX_gpio, \
234 APQ_MUX_##f1, \ 234 APQ_MUX_##f1, \
235 APQ_MUX_##f2, \ 235 APQ_MUX_##f2, \
236 APQ_MUX_##f3, \ 236 APQ_MUX_##f3, \
@@ -293,6 +293,7 @@ enum apq8064_functions {
293 APQ_MUX_cam_mclk, 293 APQ_MUX_cam_mclk,
294 APQ_MUX_codec_mic_i2s, 294 APQ_MUX_codec_mic_i2s,
295 APQ_MUX_codec_spkr_i2s, 295 APQ_MUX_codec_spkr_i2s,
296 APQ_MUX_gpio,
296 APQ_MUX_gsbi1, 297 APQ_MUX_gsbi1,
297 APQ_MUX_gsbi2, 298 APQ_MUX_gsbi2,
298 APQ_MUX_gsbi3, 299 APQ_MUX_gsbi3,
@@ -335,6 +336,21 @@ static const char * const codec_mic_i2s_groups[] = {
335static const char * const codec_spkr_i2s_groups[] = { 336static const char * const codec_spkr_i2s_groups[] = {
336 "gpio39", "gpio40", "gpio41", "gpio42" 337 "gpio39", "gpio40", "gpio41", "gpio42"
337}; 338};
339static const char * const gpio_groups[] = {
340 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
341 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
342 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
343 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
344 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
345 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
346 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
347 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
348 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
349 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
350 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
351 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
352 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89"
353};
338static const char * const gsbi1_groups[] = { 354static const char * const gsbi1_groups[] = {
339 "gpio18", "gpio19", "gpio20", "gpio21" 355 "gpio18", "gpio19", "gpio20", "gpio21"
340}; 356};
@@ -430,6 +446,7 @@ static const struct msm_function apq8064_functions[] = {
430 FUNCTION(cam_mclk), 446 FUNCTION(cam_mclk),
431 FUNCTION(codec_mic_i2s), 447 FUNCTION(codec_mic_i2s),
432 FUNCTION(codec_spkr_i2s), 448 FUNCTION(codec_spkr_i2s),
449 FUNCTION(gpio),
433 FUNCTION(gsbi1), 450 FUNCTION(gsbi1),
434 FUNCTION(gsbi2), 451 FUNCTION(gsbi2),
435 FUNCTION(gsbi3), 452 FUNCTION(gsbi3),
diff --git a/drivers/pinctrl/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
index acafea4c3a33..767cf1120b20 100644
--- a/drivers/pinctrl/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -183,7 +183,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
183 .pins = gpio##id##_pins, \ 183 .pins = gpio##id##_pins, \
184 .npins = ARRAY_SIZE(gpio##id##_pins), \ 184 .npins = ARRAY_SIZE(gpio##id##_pins), \
185 .funcs = (int[]){ \ 185 .funcs = (int[]){ \
186 IPQ_MUX_NA, /* gpio mode */ \ 186 IPQ_MUX_gpio, \
187 IPQ_MUX_##f1, \ 187 IPQ_MUX_##f1, \
188 IPQ_MUX_##f2, \ 188 IPQ_MUX_##f2, \
189 IPQ_MUX_##f3, \ 189 IPQ_MUX_##f3, \
@@ -243,6 +243,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
243 } 243 }
244 244
245enum ipq8064_functions { 245enum ipq8064_functions {
246 IPQ_MUX_gpio,
246 IPQ_MUX_mdio, 247 IPQ_MUX_mdio,
247 IPQ_MUX_mi2s, 248 IPQ_MUX_mi2s,
248 IPQ_MUX_pdm, 249 IPQ_MUX_pdm,
@@ -291,6 +292,19 @@ enum ipq8064_functions {
291 IPQ_MUX_NA, 292 IPQ_MUX_NA,
292}; 293};
293 294
295static const char * const gpio_groups[] = {
296 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
297 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
298 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
299 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
300 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
301 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
302 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
303 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
304 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
305 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
306};
307
294static const char * const mdio_groups[] = { 308static const char * const mdio_groups[] = {
295 "gpio0", "gpio1", "gpio10", "gpio11", 309 "gpio0", "gpio1", "gpio10", "gpio11",
296}; 310};
@@ -481,6 +495,7 @@ static const char * const ps_hold_groups[] = {
481}; 495};
482 496
483static const struct msm_function ipq8064_functions[] = { 497static const struct msm_function ipq8064_functions[] = {
498 FUNCTION(gpio),
484 FUNCTION(mdio), 499 FUNCTION(mdio),
485 FUNCTION(ssbi), 500 FUNCTION(ssbi),
486 FUNCTION(spmi), 501 FUNCTION(spmi),
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index df6dda4ce803..2738108caff2 100644
--- a/drivers/pinctrl/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -27,10 +27,10 @@
27#include <linux/interrupt.h> 27#include <linux/interrupt.h>
28#include <linux/spinlock.h> 28#include <linux/spinlock.h>
29 29
30#include "core.h" 30#include "../core.h"
31#include "pinconf.h" 31#include "../pinconf.h"
32#include "pinctrl-msm.h" 32#include "pinctrl-msm.h"
33#include "pinctrl-utils.h" 33#include "../pinctrl-utils.h"
34 34
35#define MAX_NR_GPIO 300 35#define MAX_NR_GPIO 300
36 36
@@ -142,9 +142,6 @@ static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
142 142
143 g = &pctrl->soc->groups[group]; 143 g = &pctrl->soc->groups[group];
144 144
145 if (WARN_ON(g->mux_bit < 0))
146 return -EINVAL;
147
148 for (i = 0; i < g->nfuncs; i++) { 145 for (i = 0; i < g->nfuncs; i++) {
149 if (g->funcs[i] == function) 146 if (g->funcs[i] == function)
150 break; 147 break;
@@ -165,36 +162,11 @@ static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
165 return 0; 162 return 0;
166} 163}
167 164
168static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
169 unsigned function,
170 unsigned group)
171{
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
173 const struct msm_pingroup *g;
174 unsigned long flags;
175 u32 val;
176
177 g = &pctrl->soc->groups[group];
178
179 if (WARN_ON(g->mux_bit < 0))
180 return;
181
182 spin_lock_irqsave(&pctrl->lock, flags);
183
184 /* Clear the mux bits to select gpio mode */
185 val = readl(pctrl->regs + g->ctl_reg);
186 val &= ~(0x7 << g->mux_bit);
187 writel(val, pctrl->regs + g->ctl_reg);
188
189 spin_unlock_irqrestore(&pctrl->lock, flags);
190}
191
192static const struct pinmux_ops msm_pinmux_ops = { 165static const struct pinmux_ops msm_pinmux_ops = {
193 .get_functions_count = msm_get_functions_count, 166 .get_functions_count = msm_get_functions_count,
194 .get_function_name = msm_get_function_name, 167 .get_function_name = msm_get_function_name,
195 .get_function_groups = msm_get_function_groups, 168 .get_function_groups = msm_get_function_groups,
196 .enable = msm_pinmux_enable, 169 .enable = msm_pinmux_enable,
197 .disable = msm_pinmux_disable,
198}; 170};
199 171
200static int msm_config_reg(struct msm_pinctrl *pctrl, 172static int msm_config_reg(struct msm_pinctrl *pctrl,
@@ -206,6 +178,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
206 switch (param) { 178 switch (param) {
207 case PIN_CONFIG_BIAS_DISABLE: 179 case PIN_CONFIG_BIAS_DISABLE:
208 case PIN_CONFIG_BIAS_PULL_DOWN: 180 case PIN_CONFIG_BIAS_PULL_DOWN:
181 case PIN_CONFIG_BIAS_BUS_HOLD:
209 case PIN_CONFIG_BIAS_PULL_UP: 182 case PIN_CONFIG_BIAS_PULL_UP:
210 *bit = g->pull_bit; 183 *bit = g->pull_bit;
211 *mask = 3; 184 *mask = 3;
@@ -243,6 +216,7 @@ static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
243 216
244#define MSM_NO_PULL 0 217#define MSM_NO_PULL 0
245#define MSM_PULL_DOWN 1 218#define MSM_PULL_DOWN 1
219#define MSM_KEEPER 2
246#define MSM_PULL_UP 3 220#define MSM_PULL_UP 3
247 221
248static unsigned msm_regval_to_drive(u32 val) 222static unsigned msm_regval_to_drive(u32 val)
@@ -280,6 +254,9 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
280 case PIN_CONFIG_BIAS_PULL_DOWN: 254 case PIN_CONFIG_BIAS_PULL_DOWN:
281 arg = arg == MSM_PULL_DOWN; 255 arg = arg == MSM_PULL_DOWN;
282 break; 256 break;
257 case PIN_CONFIG_BIAS_BUS_HOLD:
258 arg = arg == MSM_KEEPER;
259 break;
283 case PIN_CONFIG_BIAS_PULL_UP: 260 case PIN_CONFIG_BIAS_PULL_UP:
284 arg = arg == MSM_PULL_UP; 261 arg = arg == MSM_PULL_UP;
285 break; 262 break;
@@ -339,6 +316,9 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
339 case PIN_CONFIG_BIAS_PULL_DOWN: 316 case PIN_CONFIG_BIAS_PULL_DOWN:
340 arg = MSM_PULL_DOWN; 317 arg = MSM_PULL_DOWN;
341 break; 318 break;
319 case PIN_CONFIG_BIAS_BUS_HOLD:
320 arg = MSM_KEEPER;
321 break;
342 case PIN_CONFIG_BIAS_PULL_UP: 322 case PIN_CONFIG_BIAS_PULL_UP:
343 arg = MSM_PULL_UP; 323 arg = MSM_PULL_UP;
344 break; 324 break;
diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 7b2a227a590a..7b2a227a590a 100644
--- a/drivers/pinctrl/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c
new file mode 100644
index 000000000000..35047036a053
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
@@ -0,0 +1,1282 @@
1/*
2 * Copyright (c) 2014, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc msm8960_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92 PINCTRL_PIN(69, "GPIO_69"),
93 PINCTRL_PIN(70, "GPIO_70"),
94 PINCTRL_PIN(71, "GPIO_71"),
95 PINCTRL_PIN(72, "GPIO_72"),
96 PINCTRL_PIN(73, "GPIO_73"),
97 PINCTRL_PIN(74, "GPIO_74"),
98 PINCTRL_PIN(75, "GPIO_75"),
99 PINCTRL_PIN(76, "GPIO_76"),
100 PINCTRL_PIN(77, "GPIO_77"),
101 PINCTRL_PIN(78, "GPIO_78"),
102 PINCTRL_PIN(79, "GPIO_79"),
103 PINCTRL_PIN(80, "GPIO_80"),
104 PINCTRL_PIN(81, "GPIO_81"),
105 PINCTRL_PIN(82, "GPIO_82"),
106 PINCTRL_PIN(83, "GPIO_83"),
107 PINCTRL_PIN(84, "GPIO_84"),
108 PINCTRL_PIN(85, "GPIO_85"),
109 PINCTRL_PIN(86, "GPIO_86"),
110 PINCTRL_PIN(87, "GPIO_87"),
111 PINCTRL_PIN(88, "GPIO_88"),
112 PINCTRL_PIN(89, "GPIO_89"),
113 PINCTRL_PIN(90, "GPIO_90"),
114 PINCTRL_PIN(91, "GPIO_91"),
115 PINCTRL_PIN(92, "GPIO_92"),
116 PINCTRL_PIN(93, "GPIO_93"),
117 PINCTRL_PIN(94, "GPIO_94"),
118 PINCTRL_PIN(95, "GPIO_95"),
119 PINCTRL_PIN(96, "GPIO_96"),
120 PINCTRL_PIN(97, "GPIO_97"),
121 PINCTRL_PIN(98, "GPIO_98"),
122 PINCTRL_PIN(99, "GPIO_99"),
123 PINCTRL_PIN(100, "GPIO_100"),
124 PINCTRL_PIN(101, "GPIO_101"),
125 PINCTRL_PIN(102, "GPIO_102"),
126 PINCTRL_PIN(103, "GPIO_103"),
127 PINCTRL_PIN(104, "GPIO_104"),
128 PINCTRL_PIN(105, "GPIO_105"),
129 PINCTRL_PIN(106, "GPIO_106"),
130 PINCTRL_PIN(107, "GPIO_107"),
131 PINCTRL_PIN(108, "GPIO_108"),
132 PINCTRL_PIN(109, "GPIO_109"),
133 PINCTRL_PIN(110, "GPIO_110"),
134 PINCTRL_PIN(111, "GPIO_111"),
135 PINCTRL_PIN(112, "GPIO_112"),
136 PINCTRL_PIN(113, "GPIO_113"),
137 PINCTRL_PIN(114, "GPIO_114"),
138 PINCTRL_PIN(115, "GPIO_115"),
139 PINCTRL_PIN(116, "GPIO_116"),
140 PINCTRL_PIN(117, "GPIO_117"),
141 PINCTRL_PIN(118, "GPIO_118"),
142 PINCTRL_PIN(119, "GPIO_119"),
143 PINCTRL_PIN(120, "GPIO_120"),
144 PINCTRL_PIN(121, "GPIO_121"),
145 PINCTRL_PIN(122, "GPIO_122"),
146 PINCTRL_PIN(123, "GPIO_123"),
147 PINCTRL_PIN(124, "GPIO_124"),
148 PINCTRL_PIN(125, "GPIO_125"),
149 PINCTRL_PIN(126, "GPIO_126"),
150 PINCTRL_PIN(127, "GPIO_127"),
151 PINCTRL_PIN(128, "GPIO_128"),
152 PINCTRL_PIN(129, "GPIO_129"),
153 PINCTRL_PIN(130, "GPIO_130"),
154 PINCTRL_PIN(131, "GPIO_131"),
155 PINCTRL_PIN(132, "GPIO_132"),
156 PINCTRL_PIN(133, "GPIO_133"),
157 PINCTRL_PIN(134, "GPIO_134"),
158 PINCTRL_PIN(135, "GPIO_135"),
159 PINCTRL_PIN(136, "GPIO_136"),
160 PINCTRL_PIN(137, "GPIO_137"),
161 PINCTRL_PIN(138, "GPIO_138"),
162 PINCTRL_PIN(139, "GPIO_139"),
163 PINCTRL_PIN(140, "GPIO_140"),
164 PINCTRL_PIN(141, "GPIO_141"),
165 PINCTRL_PIN(142, "GPIO_142"),
166 PINCTRL_PIN(143, "GPIO_143"),
167 PINCTRL_PIN(144, "GPIO_144"),
168 PINCTRL_PIN(145, "GPIO_145"),
169 PINCTRL_PIN(146, "GPIO_146"),
170 PINCTRL_PIN(147, "GPIO_147"),
171 PINCTRL_PIN(148, "GPIO_148"),
172 PINCTRL_PIN(149, "GPIO_149"),
173 PINCTRL_PIN(150, "GPIO_150"),
174 PINCTRL_PIN(151, "GPIO_151"),
175
176 PINCTRL_PIN(152, "SDC1_CLK"),
177 PINCTRL_PIN(153, "SDC1_CMD"),
178 PINCTRL_PIN(154, "SDC1_DATA"),
179 PINCTRL_PIN(155, "SDC3_CLK"),
180 PINCTRL_PIN(156, "SDC3_CMD"),
181 PINCTRL_PIN(157, "SDC3_DATA"),
182};
183
184#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
185DECLARE_MSM_GPIO_PINS(0);
186DECLARE_MSM_GPIO_PINS(1);
187DECLARE_MSM_GPIO_PINS(2);
188DECLARE_MSM_GPIO_PINS(3);
189DECLARE_MSM_GPIO_PINS(4);
190DECLARE_MSM_GPIO_PINS(5);
191DECLARE_MSM_GPIO_PINS(6);
192DECLARE_MSM_GPIO_PINS(7);
193DECLARE_MSM_GPIO_PINS(8);
194DECLARE_MSM_GPIO_PINS(9);
195DECLARE_MSM_GPIO_PINS(10);
196DECLARE_MSM_GPIO_PINS(11);
197DECLARE_MSM_GPIO_PINS(12);
198DECLARE_MSM_GPIO_PINS(13);
199DECLARE_MSM_GPIO_PINS(14);
200DECLARE_MSM_GPIO_PINS(15);
201DECLARE_MSM_GPIO_PINS(16);
202DECLARE_MSM_GPIO_PINS(17);
203DECLARE_MSM_GPIO_PINS(18);
204DECLARE_MSM_GPIO_PINS(19);
205DECLARE_MSM_GPIO_PINS(20);
206DECLARE_MSM_GPIO_PINS(21);
207DECLARE_MSM_GPIO_PINS(22);
208DECLARE_MSM_GPIO_PINS(23);
209DECLARE_MSM_GPIO_PINS(24);
210DECLARE_MSM_GPIO_PINS(25);
211DECLARE_MSM_GPIO_PINS(26);
212DECLARE_MSM_GPIO_PINS(27);
213DECLARE_MSM_GPIO_PINS(28);
214DECLARE_MSM_GPIO_PINS(29);
215DECLARE_MSM_GPIO_PINS(30);
216DECLARE_MSM_GPIO_PINS(31);
217DECLARE_MSM_GPIO_PINS(32);
218DECLARE_MSM_GPIO_PINS(33);
219DECLARE_MSM_GPIO_PINS(34);
220DECLARE_MSM_GPIO_PINS(35);
221DECLARE_MSM_GPIO_PINS(36);
222DECLARE_MSM_GPIO_PINS(37);
223DECLARE_MSM_GPIO_PINS(38);
224DECLARE_MSM_GPIO_PINS(39);
225DECLARE_MSM_GPIO_PINS(40);
226DECLARE_MSM_GPIO_PINS(41);
227DECLARE_MSM_GPIO_PINS(42);
228DECLARE_MSM_GPIO_PINS(43);
229DECLARE_MSM_GPIO_PINS(44);
230DECLARE_MSM_GPIO_PINS(45);
231DECLARE_MSM_GPIO_PINS(46);
232DECLARE_MSM_GPIO_PINS(47);
233DECLARE_MSM_GPIO_PINS(48);
234DECLARE_MSM_GPIO_PINS(49);
235DECLARE_MSM_GPIO_PINS(50);
236DECLARE_MSM_GPIO_PINS(51);
237DECLARE_MSM_GPIO_PINS(52);
238DECLARE_MSM_GPIO_PINS(53);
239DECLARE_MSM_GPIO_PINS(54);
240DECLARE_MSM_GPIO_PINS(55);
241DECLARE_MSM_GPIO_PINS(56);
242DECLARE_MSM_GPIO_PINS(57);
243DECLARE_MSM_GPIO_PINS(58);
244DECLARE_MSM_GPIO_PINS(59);
245DECLARE_MSM_GPIO_PINS(60);
246DECLARE_MSM_GPIO_PINS(61);
247DECLARE_MSM_GPIO_PINS(62);
248DECLARE_MSM_GPIO_PINS(63);
249DECLARE_MSM_GPIO_PINS(64);
250DECLARE_MSM_GPIO_PINS(65);
251DECLARE_MSM_GPIO_PINS(66);
252DECLARE_MSM_GPIO_PINS(67);
253DECLARE_MSM_GPIO_PINS(68);
254DECLARE_MSM_GPIO_PINS(69);
255DECLARE_MSM_GPIO_PINS(70);
256DECLARE_MSM_GPIO_PINS(71);
257DECLARE_MSM_GPIO_PINS(72);
258DECLARE_MSM_GPIO_PINS(73);
259DECLARE_MSM_GPIO_PINS(74);
260DECLARE_MSM_GPIO_PINS(75);
261DECLARE_MSM_GPIO_PINS(76);
262DECLARE_MSM_GPIO_PINS(77);
263DECLARE_MSM_GPIO_PINS(78);
264DECLARE_MSM_GPIO_PINS(79);
265DECLARE_MSM_GPIO_PINS(80);
266DECLARE_MSM_GPIO_PINS(81);
267DECLARE_MSM_GPIO_PINS(82);
268DECLARE_MSM_GPIO_PINS(83);
269DECLARE_MSM_GPIO_PINS(84);
270DECLARE_MSM_GPIO_PINS(85);
271DECLARE_MSM_GPIO_PINS(86);
272DECLARE_MSM_GPIO_PINS(87);
273DECLARE_MSM_GPIO_PINS(88);
274DECLARE_MSM_GPIO_PINS(89);
275DECLARE_MSM_GPIO_PINS(90);
276DECLARE_MSM_GPIO_PINS(91);
277DECLARE_MSM_GPIO_PINS(92);
278DECLARE_MSM_GPIO_PINS(93);
279DECLARE_MSM_GPIO_PINS(94);
280DECLARE_MSM_GPIO_PINS(95);
281DECLARE_MSM_GPIO_PINS(96);
282DECLARE_MSM_GPIO_PINS(97);
283DECLARE_MSM_GPIO_PINS(98);
284DECLARE_MSM_GPIO_PINS(99);
285DECLARE_MSM_GPIO_PINS(100);
286DECLARE_MSM_GPIO_PINS(101);
287DECLARE_MSM_GPIO_PINS(102);
288DECLARE_MSM_GPIO_PINS(103);
289DECLARE_MSM_GPIO_PINS(104);
290DECLARE_MSM_GPIO_PINS(105);
291DECLARE_MSM_GPIO_PINS(106);
292DECLARE_MSM_GPIO_PINS(107);
293DECLARE_MSM_GPIO_PINS(108);
294DECLARE_MSM_GPIO_PINS(109);
295DECLARE_MSM_GPIO_PINS(110);
296DECLARE_MSM_GPIO_PINS(111);
297DECLARE_MSM_GPIO_PINS(112);
298DECLARE_MSM_GPIO_PINS(113);
299DECLARE_MSM_GPIO_PINS(114);
300DECLARE_MSM_GPIO_PINS(115);
301DECLARE_MSM_GPIO_PINS(116);
302DECLARE_MSM_GPIO_PINS(117);
303DECLARE_MSM_GPIO_PINS(118);
304DECLARE_MSM_GPIO_PINS(119);
305DECLARE_MSM_GPIO_PINS(120);
306DECLARE_MSM_GPIO_PINS(121);
307DECLARE_MSM_GPIO_PINS(122);
308DECLARE_MSM_GPIO_PINS(123);
309DECLARE_MSM_GPIO_PINS(124);
310DECLARE_MSM_GPIO_PINS(125);
311DECLARE_MSM_GPIO_PINS(126);
312DECLARE_MSM_GPIO_PINS(127);
313DECLARE_MSM_GPIO_PINS(128);
314DECLARE_MSM_GPIO_PINS(129);
315DECLARE_MSM_GPIO_PINS(130);
316DECLARE_MSM_GPIO_PINS(131);
317DECLARE_MSM_GPIO_PINS(132);
318DECLARE_MSM_GPIO_PINS(133);
319DECLARE_MSM_GPIO_PINS(134);
320DECLARE_MSM_GPIO_PINS(135);
321DECLARE_MSM_GPIO_PINS(136);
322DECLARE_MSM_GPIO_PINS(137);
323DECLARE_MSM_GPIO_PINS(138);
324DECLARE_MSM_GPIO_PINS(139);
325DECLARE_MSM_GPIO_PINS(140);
326DECLARE_MSM_GPIO_PINS(141);
327DECLARE_MSM_GPIO_PINS(142);
328DECLARE_MSM_GPIO_PINS(143);
329DECLARE_MSM_GPIO_PINS(144);
330DECLARE_MSM_GPIO_PINS(145);
331DECLARE_MSM_GPIO_PINS(146);
332DECLARE_MSM_GPIO_PINS(147);
333DECLARE_MSM_GPIO_PINS(148);
334DECLARE_MSM_GPIO_PINS(149);
335DECLARE_MSM_GPIO_PINS(150);
336DECLARE_MSM_GPIO_PINS(151);
337
338static const unsigned int sdc1_clk_pins[] = { 152 };
339static const unsigned int sdc1_cmd_pins[] = { 153 };
340static const unsigned int sdc1_data_pins[] = { 154 };
341static const unsigned int sdc3_clk_pins[] = { 155 };
342static const unsigned int sdc3_cmd_pins[] = { 156 };
343static const unsigned int sdc3_data_pins[] = { 157 };
344
345#define FUNCTION(fname) \
346 [MSM_MUX_##fname] = { \
347 .name = #fname, \
348 .groups = fname##_groups, \
349 .ngroups = ARRAY_SIZE(fname##_groups), \
350 }
351
352#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
353 { \
354 .name = "gpio" #id, \
355 .pins = gpio##id##_pins, \
356 .npins = ARRAY_SIZE(gpio##id##_pins), \
357 .funcs = (int[]){ \
358 MSM_MUX_gpio, \
359 MSM_MUX_##f1, \
360 MSM_MUX_##f2, \
361 MSM_MUX_##f3, \
362 MSM_MUX_##f4, \
363 MSM_MUX_##f5, \
364 MSM_MUX_##f6, \
365 MSM_MUX_##f7, \
366 MSM_MUX_##f8, \
367 MSM_MUX_##f9, \
368 MSM_MUX_##f10, \
369 MSM_MUX_##f11 \
370 }, \
371 .nfuncs = 12, \
372 .ctl_reg = 0x1000 + 0x10 * id, \
373 .io_reg = 0x1004 + 0x10 * id, \
374 .intr_cfg_reg = 0x1008 + 0x10 * id, \
375 .intr_status_reg = 0x100c + 0x10 * id, \
376 .intr_target_reg = 0x400 + 0x4 * id, \
377 .mux_bit = 2, \
378 .pull_bit = 0, \
379 .drv_bit = 6, \
380 .oe_bit = 9, \
381 .in_bit = 0, \
382 .out_bit = 1, \
383 .intr_enable_bit = 0, \
384 .intr_status_bit = 0, \
385 .intr_ack_high = 1, \
386 .intr_target_bit = 0, \
387 .intr_raw_status_bit = 3, \
388 .intr_polarity_bit = 1, \
389 .intr_detection_bit = 2, \
390 .intr_detection_width = 1, \
391 }
392
393#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
394 { \
395 .name = #pg_name, \
396 .pins = pg_name##_pins, \
397 .npins = ARRAY_SIZE(pg_name##_pins), \
398 .ctl_reg = ctl, \
399 .io_reg = 0, \
400 .intr_cfg_reg = 0, \
401 .intr_status_reg = 0, \
402 .intr_target_reg = 0, \
403 .mux_bit = -1, \
404 .pull_bit = pull, \
405 .drv_bit = drv, \
406 .oe_bit = -1, \
407 .in_bit = -1, \
408 .out_bit = -1, \
409 .intr_enable_bit = -1, \
410 .intr_status_bit = -1, \
411 .intr_target_bit = -1, \
412 .intr_raw_status_bit = -1, \
413 .intr_polarity_bit = -1, \
414 .intr_detection_bit = -1, \
415 .intr_detection_width = -1, \
416 }
417
418enum msm8960_functions {
419 MSM_MUX_audio_pcm,
420 MSM_MUX_bt,
421 MSM_MUX_cam_mclk0,
422 MSM_MUX_cam_mclk1,
423 MSM_MUX_cam_mclk2,
424 MSM_MUX_codec_mic_i2s,
425 MSM_MUX_codec_spkr_i2s,
426 MSM_MUX_ext_gps,
427 MSM_MUX_fm,
428 MSM_MUX_gps_blanking,
429 MSM_MUX_gps_pps_in,
430 MSM_MUX_gps_pps_out,
431 MSM_MUX_gp_clk_0a,
432 MSM_MUX_gp_clk_0b,
433 MSM_MUX_gp_clk_1a,
434 MSM_MUX_gp_clk_1b,
435 MSM_MUX_gp_clk_2a,
436 MSM_MUX_gp_clk_2b,
437 MSM_MUX_gp_mn,
438 MSM_MUX_gp_pdm_0a,
439 MSM_MUX_gp_pdm_0b,
440 MSM_MUX_gp_pdm_1a,
441 MSM_MUX_gp_pdm_1b,
442 MSM_MUX_gp_pdm_2a,
443 MSM_MUX_gp_pdm_2b,
444 MSM_MUX_gpio,
445 MSM_MUX_gsbi1,
446 MSM_MUX_gsbi1_spi_cs1_n,
447 MSM_MUX_gsbi1_spi_cs2a_n,
448 MSM_MUX_gsbi1_spi_cs2b_n,
449 MSM_MUX_gsbi1_spi_cs3_n,
450 MSM_MUX_gsbi2,
451 MSM_MUX_gsbi2_spi_cs1_n,
452 MSM_MUX_gsbi2_spi_cs2_n,
453 MSM_MUX_gsbi2_spi_cs3_n,
454 MSM_MUX_gsbi3,
455 MSM_MUX_gsbi4,
456 MSM_MUX_gsbi4_3d_cam_i2c_l,
457 MSM_MUX_gsbi4_3d_cam_i2c_r,
458 MSM_MUX_gsbi5,
459 MSM_MUX_gsbi5_3d_cam_i2c_l,
460 MSM_MUX_gsbi5_3d_cam_i2c_r,
461 MSM_MUX_gsbi6,
462 MSM_MUX_gsbi7,
463 MSM_MUX_gsbi8,
464 MSM_MUX_gsbi9,
465 MSM_MUX_gsbi10,
466 MSM_MUX_gsbi11,
467 MSM_MUX_gsbi11_spi_cs1a_n,
468 MSM_MUX_gsbi11_spi_cs1b_n,
469 MSM_MUX_gsbi11_spi_cs2a_n,
470 MSM_MUX_gsbi11_spi_cs2b_n,
471 MSM_MUX_gsbi11_spi_cs3_n,
472 MSM_MUX_gsbi12,
473 MSM_MUX_hdmi_cec,
474 MSM_MUX_hdmi_ddc_clock,
475 MSM_MUX_hdmi_ddc_data,
476 MSM_MUX_hdmi_hot_plug_detect,
477 MSM_MUX_hsic,
478 MSM_MUX_mdp_vsync,
479 MSM_MUX_mi2s,
480 MSM_MUX_mic_i2s,
481 MSM_MUX_pmb_clk,
482 MSM_MUX_pmb_ext_ctrl,
483 MSM_MUX_ps_hold,
484 MSM_MUX_rpm_wdog,
485 MSM_MUX_sdc2,
486 MSM_MUX_sdc4,
487 MSM_MUX_sdc5,
488 MSM_MUX_slimbus1,
489 MSM_MUX_slimbus2,
490 MSM_MUX_spkr_i2s,
491 MSM_MUX_ssbi1,
492 MSM_MUX_ssbi2,
493 MSM_MUX_ssbi_ext_gps,
494 MSM_MUX_ssbi_pmic2,
495 MSM_MUX_ssbi_qpa1,
496 MSM_MUX_ssbi_ts,
497 MSM_MUX_tsif1,
498 MSM_MUX_tsif2,
499 MSM_MUX_ts_eoc,
500 MSM_MUX_usb_fs1,
501 MSM_MUX_usb_fs1_oe,
502 MSM_MUX_usb_fs1_oe_n,
503 MSM_MUX_usb_fs2,
504 MSM_MUX_usb_fs2_oe,
505 MSM_MUX_usb_fs2_oe_n,
506 MSM_MUX_vfe_camif_timer1_a,
507 MSM_MUX_vfe_camif_timer1_b,
508 MSM_MUX_vfe_camif_timer2,
509 MSM_MUX_vfe_camif_timer3_a,
510 MSM_MUX_vfe_camif_timer3_b,
511 MSM_MUX_vfe_camif_timer4_a,
512 MSM_MUX_vfe_camif_timer4_b,
513 MSM_MUX_vfe_camif_timer4_c,
514 MSM_MUX_vfe_camif_timer5_a,
515 MSM_MUX_vfe_camif_timer5_b,
516 MSM_MUX_vfe_camif_timer6_a,
517 MSM_MUX_vfe_camif_timer6_b,
518 MSM_MUX_vfe_camif_timer6_c,
519 MSM_MUX_vfe_camif_timer7_a,
520 MSM_MUX_vfe_camif_timer7_b,
521 MSM_MUX_vfe_camif_timer7_c,
522 MSM_MUX_wlan,
523 MSM_MUX_NA,
524};
525
526static const char * const audio_pcm_groups[] = {
527 "gpio63", "gpio64", "gpio65", "gpio66"
528};
529
530static const char * const bt_groups[] = {
531 "gpio28", "gpio29", "gpio83"
532};
533
534static const char * const cam_mclk0_groups[] = {
535 "gpio5"
536};
537
538static const char * const cam_mclk1_groups[] = {
539 "gpio4"
540};
541
542static const char * const cam_mclk2_groups[] = {
543 "gpio2"
544};
545
546static const char * const codec_mic_i2s_groups[] = {
547 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58"
548};
549
550static const char * const codec_spkr_i2s_groups[] = {
551 "gpio59", "gpio60", "gpio61", "gpio62"
552};
553
554static const char * const ext_gps_groups[] = {
555 "gpio22", "gpio23", "gpio24", "gpio25"
556};
557
558static const char * const fm_groups[] = {
559 "gpio26", "gpio27"
560};
561
562static const char * const gps_blanking_groups[] = {
563 "gpio137"
564};
565
566static const char * const gps_pps_in_groups[] = {
567 "gpio37"
568};
569
570static const char * const gps_pps_out_groups[] = {
571 "gpio37"
572};
573
574static const char * const gp_clk_0a_groups[] = {
575 "gpio3"
576};
577
578static const char * const gp_clk_0b_groups[] = {
579 "gpio54"
580};
581
582static const char * const gp_clk_1a_groups[] = {
583 "gpio4"
584};
585
586static const char * const gp_clk_1b_groups[] = {
587 "gpio70"
588};
589
590static const char * const gp_clk_2a_groups[] = {
591 "gpio52"
592};
593
594static const char * const gp_clk_2b_groups[] = {
595 "gpio37"
596};
597
598static const char * const gp_mn_groups[] = {
599 "gpio2"
600};
601
602static const char * const gp_pdm_0a_groups[] = {
603 "gpio58"
604};
605
606static const char * const gp_pdm_0b_groups[] = {
607 "gpio39"
608};
609
610static const char * const gp_pdm_1a_groups[] = {
611 "gpio94"
612};
613
614static const char * const gp_pdm_1b_groups[] = {
615 "gpio64"
616};
617
618static const char * const gp_pdm_2a_groups[] = {
619 "gpio69"
620};
621
622static const char * const gp_pdm_2b_groups[] = {
623 "gpio53"
624};
625
626static const char * const gpio_groups[] = {
627 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
628 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
629 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
630 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
631 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
632 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
633 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
634 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
635 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
636 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
637 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
638 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
639 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
640 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
641 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
642 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
643 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
644 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
645 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
646 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
647 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
648 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
649 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151"
650};
651
652static const char * const gsbi1_groups[] = {
653 "gpio6", "gpio7", "gpio8", "gpio9"
654};
655
656static const char * const gsbi1_spi_cs1_n_groups[] = {
657 "gpio14"
658};
659
660static const char * const gsbi1_spi_cs2a_n_groups[] = {
661 "gpio15"
662};
663
664static const char * const gsbi1_spi_cs2b_n_groups[] = {
665 "gpio17"
666};
667
668static const char * const gsbi1_spi_cs3_n_groups[] = {
669 "gpio16"
670};
671
672static const char * const gsbi2_groups[] = {
673 "gpio10", "gpio11", "gpio12", "gpio13"
674};
675
676static const char * const gsbi2_spi_cs1_n_groups[] = {
677 "gpio52"
678};
679
680static const char * const gsbi2_spi_cs2_n_groups[] = {
681 "gpio68"
682};
683
684static const char * const gsbi2_spi_cs3_n_groups[] = {
685 "gpio56"
686};
687
688static const char * const gsbi3_groups[] = {
689 "gpio14", "gpio15", "gpio16", "gpio17"
690};
691
692static const char * const gsbi4_groups[] = {
693 "gpio18", "gpio19", "gpio20", "gpio21"
694};
695
696static const char * const gsbi4_3d_cam_i2c_l_groups[] = {
697 "gpio18", "gpio19"
698};
699
700static const char * const gsbi4_3d_cam_i2c_r_groups[] = {
701 "gpio20", "gpio21"
702};
703
704static const char * const gsbi5_groups[] = {
705 "gpio22", "gpio23", "gpio24", "gpio25"
706};
707
708static const char * const gsbi5_3d_cam_i2c_l_groups[] = {
709 "gpio22", "gpio23"
710};
711
712static const char * const gsbi5_3d_cam_i2c_r_groups[] = {
713 "gpio24", "gpio25"
714};
715
716static const char * const gsbi6_groups[] = {
717 "gpio26", "gpio27", "gpio28", "gpio29"
718};
719
720static const char * const gsbi7_groups[] = {
721 "gpio30", "gpio31", "gpio32", "gpio33"
722};
723
724static const char * const gsbi8_groups[] = {
725 "gpio34", "gpio35", "gpio36", "gpio37"
726};
727
728static const char * const gsbi9_groups[] = {
729 "gpio93", "gpio94", "gpio95", "gpio96"
730};
731
732static const char * const gsbi10_groups[] = {
733 "gpio71", "gpio72", "gpio73", "gpio74"
734};
735
736static const char * const gsbi11_groups[] = {
737 "gpio38", "gpio39", "gpio40", "gpio41"
738};
739
740static const char * const gsbi11_spi_cs1a_n_groups[] = {
741 "gpio36"
742};
743
744static const char * const gsbi11_spi_cs1b_n_groups[] = {
745 "gpio18"
746};
747
748static const char * const gsbi11_spi_cs2a_n_groups[] = {
749 "gpio37"
750};
751
752static const char * const gsbi11_spi_cs2b_n_groups[] = {
753 "gpio19"
754};
755
756static const char * const gsbi11_spi_cs3_n_groups[] = {
757 "gpio76"
758};
759
760static const char * const gsbi12_groups[] = {
761 "gpio42", "gpio43", "gpio44", "gpio45"
762};
763
764static const char * const hdmi_cec_groups[] = {
765 "gpio99"
766};
767
768static const char * const hdmi_ddc_clock_groups[] = {
769 "gpio100"
770};
771
772static const char * const hdmi_ddc_data_groups[] = {
773 "gpio101"
774};
775
776static const char * const hdmi_hot_plug_detect_groups[] = {
777 "gpio102"
778};
779
780static const char * const hsic_groups[] = {
781 "gpio150", "gpio151"
782};
783
784static const char * const mdp_vsync_groups[] = {
785 "gpio0", "gpio1", "gpio19"
786};
787
788static const char * const mi2s_groups[] = {
789 "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53"
790};
791
792static const char * const mic_i2s_groups[] = {
793 "gpio71", "gpio72", "gpio73", "gpio74"
794};
795
796static const char * const pmb_clk_groups[] = {
797 "gpio21", "gpio86", "gpio112"
798};
799
800static const char * const pmb_ext_ctrl_groups[] = {
801 "gpio4", "gpio5"
802};
803
804static const char * const ps_hold_groups[] = {
805 "gpio108"
806};
807
808static const char * const rpm_wdog_groups[] = {
809 "gpio12"
810};
811
812static const char * const sdc2_groups[] = {
813 "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
814 "gpio96", "gpio97", "gpio98"
815};
816
817static const char * const sdc4_groups[] = {
818 "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88"
819};
820
821static const char * const sdc5_groups[] = {
822 "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82"
823};
824
825static const char * const slimbus1_groups[] = {
826 "gpio50", "gpio51", "gpio60", "gpio61"
827};
828
829static const char * const slimbus2_groups[] = {
830 "gpio42", "gpio43"
831};
832
833static const char * const spkr_i2s_groups[] = {
834 "gpio67", "gpio68", "gpio69", "gpio70"
835};
836
837static const char * const ssbi1_groups[] = {
838 "gpio141", "gpio143"
839};
840
841static const char * const ssbi2_groups[] = {
842 "gpio140", "gpio142"
843};
844
845static const char * const ssbi_ext_gps_groups[] = {
846 "gpio23"
847};
848
849static const char * const ssbi_pmic2_groups[] = {
850 "gpio149"
851};
852
853static const char * const ssbi_qpa1_groups[] = {
854 "gpio131"
855};
856
857static const char * const ssbi_ts_groups[] = {
858 "gpio10"
859};
860
861static const char * const tsif1_groups[] = {
862 "gpio75", "gpio76", "gpio77", "gpio82"
863};
864
865static const char * const tsif2_groups[] = {
866 "gpio78", "gpio79", "gpio80", "gpio81"
867};
868
869static const char * const ts_eoc_groups[] = {
870 "gpio11"
871};
872
873static const char * const usb_fs1_groups[] = {
874 "gpio32", "gpio33"
875};
876
877static const char * const usb_fs1_oe_groups[] = {
878 "gpio31"
879};
880
881static const char * const usb_fs1_oe_n_groups[] = {
882 "gpio31"
883};
884
885static const char * const usb_fs2_groups[] = {
886 "gpio34", "gpio35"
887};
888
889static const char * const usb_fs2_oe_groups[] = {
890 "gpio36"
891};
892
893static const char * const usb_fs2_oe_n_groups[] = {
894 "gpio36"
895};
896
897static const char * const vfe_camif_timer1_a_groups[] = {
898 "gpio2"
899};
900
901static const char * const vfe_camif_timer1_b_groups[] = {
902 "gpio38"
903};
904
905static const char * const vfe_camif_timer2_groups[] = {
906 "gpio3"
907};
908
909static const char * const vfe_camif_timer3_a_groups[] = {
910 "gpio4"
911};
912
913static const char * const vfe_camif_timer3_b_groups[] = {
914 "gpio151"
915};
916
917static const char * const vfe_camif_timer4_a_groups[] = {
918 "gpio65"
919};
920
921static const char * const vfe_camif_timer4_b_groups[] = {
922 "gpio150"
923};
924
925static const char * const vfe_camif_timer4_c_groups[] = {
926 "gpio10"
927};
928
929static const char * const vfe_camif_timer5_a_groups[] = {
930 "gpio66"
931};
932
933static const char * const vfe_camif_timer5_b_groups[] = {
934 "gpio39"
935};
936
937static const char * const vfe_camif_timer6_a_groups[] = {
938 "gpio71"
939};
940
941static const char * const vfe_camif_timer6_b_groups[] = {
942 "gpio0"
943};
944
945static const char * const vfe_camif_timer6_c_groups[] = {
946 "gpio18"
947};
948
949static const char * const vfe_camif_timer7_a_groups[] = {
950 "gpio67"
951};
952
953static const char * const vfe_camif_timer7_b_groups[] = {
954 "gpio1"
955};
956
957static const char * const vfe_camif_timer7_c_groups[] = {
958 "gpio19"
959};
960
961static const char * const wlan_groups[] = {
962 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88"
963};
964
965static const struct msm_function msm8960_functions[] = {
966 FUNCTION(audio_pcm),
967 FUNCTION(bt),
968 FUNCTION(cam_mclk0),
969 FUNCTION(cam_mclk1),
970 FUNCTION(cam_mclk2),
971 FUNCTION(codec_mic_i2s),
972 FUNCTION(codec_spkr_i2s),
973 FUNCTION(ext_gps),
974 FUNCTION(fm),
975 FUNCTION(gps_blanking),
976 FUNCTION(gps_pps_in),
977 FUNCTION(gps_pps_out),
978 FUNCTION(gp_clk_0a),
979 FUNCTION(gp_clk_0b),
980 FUNCTION(gp_clk_1a),
981 FUNCTION(gp_clk_1b),
982 FUNCTION(gp_clk_2a),
983 FUNCTION(gp_clk_2b),
984 FUNCTION(gp_mn),
985 FUNCTION(gp_pdm_0a),
986 FUNCTION(gp_pdm_0b),
987 FUNCTION(gp_pdm_1a),
988 FUNCTION(gp_pdm_1b),
989 FUNCTION(gp_pdm_2a),
990 FUNCTION(gp_pdm_2b),
991 FUNCTION(gpio),
992 FUNCTION(gsbi1),
993 FUNCTION(gsbi1_spi_cs1_n),
994 FUNCTION(gsbi1_spi_cs2a_n),
995 FUNCTION(gsbi1_spi_cs2b_n),
996 FUNCTION(gsbi1_spi_cs3_n),
997 FUNCTION(gsbi2),
998 FUNCTION(gsbi2_spi_cs1_n),
999 FUNCTION(gsbi2_spi_cs2_n),
1000 FUNCTION(gsbi2_spi_cs3_n),
1001 FUNCTION(gsbi3),
1002 FUNCTION(gsbi4),
1003 FUNCTION(gsbi4_3d_cam_i2c_l),
1004 FUNCTION(gsbi4_3d_cam_i2c_r),
1005 FUNCTION(gsbi5),
1006 FUNCTION(gsbi5_3d_cam_i2c_l),
1007 FUNCTION(gsbi5_3d_cam_i2c_r),
1008 FUNCTION(gsbi6),
1009 FUNCTION(gsbi7),
1010 FUNCTION(gsbi8),
1011 FUNCTION(gsbi9),
1012 FUNCTION(gsbi10),
1013 FUNCTION(gsbi11),
1014 FUNCTION(gsbi11_spi_cs1a_n),
1015 FUNCTION(gsbi11_spi_cs1b_n),
1016 FUNCTION(gsbi11_spi_cs2a_n),
1017 FUNCTION(gsbi11_spi_cs2b_n),
1018 FUNCTION(gsbi11_spi_cs3_n),
1019 FUNCTION(gsbi12),
1020 FUNCTION(hdmi_cec),
1021 FUNCTION(hdmi_ddc_clock),
1022 FUNCTION(hdmi_ddc_data),
1023 FUNCTION(hdmi_hot_plug_detect),
1024 FUNCTION(hsic),
1025 FUNCTION(mdp_vsync),
1026 FUNCTION(mi2s),
1027 FUNCTION(mic_i2s),
1028 FUNCTION(pmb_clk),
1029 FUNCTION(pmb_ext_ctrl),
1030 FUNCTION(ps_hold),
1031 FUNCTION(rpm_wdog),
1032 FUNCTION(sdc2),
1033 FUNCTION(sdc4),
1034 FUNCTION(sdc5),
1035 FUNCTION(slimbus1),
1036 FUNCTION(slimbus2),
1037 FUNCTION(spkr_i2s),
1038 FUNCTION(ssbi1),
1039 FUNCTION(ssbi2),
1040 FUNCTION(ssbi_ext_gps),
1041 FUNCTION(ssbi_pmic2),
1042 FUNCTION(ssbi_qpa1),
1043 FUNCTION(ssbi_ts),
1044 FUNCTION(tsif1),
1045 FUNCTION(tsif2),
1046 FUNCTION(ts_eoc),
1047 FUNCTION(usb_fs1),
1048 FUNCTION(usb_fs1_oe),
1049 FUNCTION(usb_fs1_oe_n),
1050 FUNCTION(usb_fs2),
1051 FUNCTION(usb_fs2_oe),
1052 FUNCTION(usb_fs2_oe_n),
1053 FUNCTION(vfe_camif_timer1_a),
1054 FUNCTION(vfe_camif_timer1_b),
1055 FUNCTION(vfe_camif_timer2),
1056 FUNCTION(vfe_camif_timer3_a),
1057 FUNCTION(vfe_camif_timer3_b),
1058 FUNCTION(vfe_camif_timer4_a),
1059 FUNCTION(vfe_camif_timer4_b),
1060 FUNCTION(vfe_camif_timer4_c),
1061 FUNCTION(vfe_camif_timer5_a),
1062 FUNCTION(vfe_camif_timer5_b),
1063 FUNCTION(vfe_camif_timer6_a),
1064 FUNCTION(vfe_camif_timer6_b),
1065 FUNCTION(vfe_camif_timer6_c),
1066 FUNCTION(vfe_camif_timer7_a),
1067 FUNCTION(vfe_camif_timer7_b),
1068 FUNCTION(vfe_camif_timer7_c),
1069 FUNCTION(wlan),
1070};
1071
1072static const struct msm_pingroup msm8960_groups[] = {
1073 PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1074 PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1075 PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA),
1076 PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1077 PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA),
1078 PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1079 PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1080 PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1081 PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1082 PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1083 PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA),
1084 PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1085 PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1086 PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1087 PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1088 PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1089 PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1090 PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1091 PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA),
1092 PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA),
1093 PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1094 PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA),
1095 PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA),
1096 PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA),
1097 PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA),
1098 PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA),
1099 PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1100 PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1101 PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1102 PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1103 PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1104 PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA),
1105 PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1106 PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1107 PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1108 PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1109 PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA),
1110 PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA),
1111 PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA),
1112 PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b),
1113 PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1114 PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1115 PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1116 PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1117 PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1118 PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1119 PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1120 PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1121 PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1122 PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1123 PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1124 PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1125 PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA),
1126 PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1127 PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1128 PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1129 PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1130 PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1131 PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1132 PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1133 PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1134 PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1135 PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1136 PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1137 PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1138 PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1139 PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1140 PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1141 PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1142 PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1143 PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1144 PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA),
1145 PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1146 PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1147 PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1148 PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1149 PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1150 PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1151 PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1152 PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1153 PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1154 PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1155 PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1156 PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1157 PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1158 PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1159 PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA),
1160 PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1161 PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1162 PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1163 PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1164 PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1165 PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1166 PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1167 PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA),
1168 PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1169 PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1170 PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1171 PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1172 PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1173 PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1174 PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1175 PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1176 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1177 PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1178 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1179 PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1180 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1181 PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1182 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1183 PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1184 PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1185 PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1186 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1187 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1188 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1189 PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1190 PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1191 PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1192 PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1193 PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1194 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1195 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1196 PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1197 PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1198 PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1199 PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1200 PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1201 PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1202 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1203 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1204 PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1205 PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1206 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1207 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1208 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1209 PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1210 PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1211 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1212 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1213 PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1214 PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1215 PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1216 PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1217 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1218 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1219 PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1220 PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1221 PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1222 PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1223 PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA),
1224 PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA),
1225
1226 SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6),
1227 SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3),
1228 SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0),
1229
1230 SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6),
1231 SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3),
1232 SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0),
1233};
1234
1235#define NUM_GPIO_PINGROUPS 152
1236
1237static const struct msm_pinctrl_soc_data msm8960_pinctrl = {
1238 .pins = msm8960_pins,
1239 .npins = ARRAY_SIZE(msm8960_pins),
1240 .functions = msm8960_functions,
1241 .nfunctions = ARRAY_SIZE(msm8960_functions),
1242 .groups = msm8960_groups,
1243 .ngroups = ARRAY_SIZE(msm8960_groups),
1244 .ngpios = NUM_GPIO_PINGROUPS,
1245};
1246
1247static int msm8960_pinctrl_probe(struct platform_device *pdev)
1248{
1249 return msm_pinctrl_probe(pdev, &msm8960_pinctrl);
1250}
1251
1252static const struct of_device_id msm8960_pinctrl_of_match[] = {
1253 { .compatible = "qcom,msm8960-pinctrl", },
1254 { },
1255};
1256
1257static struct platform_driver msm8960_pinctrl_driver = {
1258 .driver = {
1259 .name = "msm8960-pinctrl",
1260 .owner = THIS_MODULE,
1261 .of_match_table = msm8960_pinctrl_of_match,
1262 },
1263 .probe = msm8960_pinctrl_probe,
1264 .remove = msm_pinctrl_remove,
1265};
1266
1267static int __init msm8960_pinctrl_init(void)
1268{
1269 return platform_driver_register(&msm8960_pinctrl_driver);
1270}
1271arch_initcall(msm8960_pinctrl_init);
1272
1273static void __exit msm8960_pinctrl_exit(void)
1274{
1275 platform_driver_unregister(&msm8960_pinctrl_driver);
1276}
1277module_exit(msm8960_pinctrl_exit);
1278
1279MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
1280MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver");
1281MODULE_LICENSE("GPL v2");
1282MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
index 418306911a6f..8c9720154d1e 100644
--- a/drivers/pinctrl/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
@@ -342,7 +342,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
342 .pins = gpio##id##_pins, \ 342 .pins = gpio##id##_pins, \
343 .npins = ARRAY_SIZE(gpio##id##_pins), \ 343 .npins = ARRAY_SIZE(gpio##id##_pins), \
344 .funcs = (int[]){ \ 344 .funcs = (int[]){ \
345 MSM_MUX_NA, /* gpio mode */ \ 345 MSM_MUX_gpio, \
346 MSM_MUX_##f1, \ 346 MSM_MUX_##f1, \
347 MSM_MUX_##f2, \ 347 MSM_MUX_##f2, \
348 MSM_MUX_##f3, \ 348 MSM_MUX_##f3, \
@@ -402,6 +402,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
402 * the pingroup table below. 402 * the pingroup table below.
403 */ 403 */
404enum msm8x74_functions { 404enum msm8x74_functions {
405 MSM_MUX_gpio,
405 MSM_MUX_cci_i2c0, 406 MSM_MUX_cci_i2c0,
406 MSM_MUX_cci_i2c1, 407 MSM_MUX_cci_i2c1,
407 MSM_MUX_blsp_i2c1, 408 MSM_MUX_blsp_i2c1,
@@ -509,6 +510,31 @@ enum msm8x74_functions {
509 MSM_MUX_NA, 510 MSM_MUX_NA,
510}; 511};
511 512
513static const char * const gpio_groups[] = {
514 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
515 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
516 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
517 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
518 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
519 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
520 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
521 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
522 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
523 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
524 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
525 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
526 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
527 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
528 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
529 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
530 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
531 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
532 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
533 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
534 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
535 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145"
536};
537
512static const char * const blsp_uart1_groups[] = { 538static const char * const blsp_uart1_groups[] = {
513 "gpio0", "gpio1", "gpio2", "gpio3" 539 "gpio0", "gpio1", "gpio2", "gpio3"
514}; 540};
@@ -728,6 +754,7 @@ static const char * const wlan_groups[] = {
728static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; 754static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
729 755
730static const struct msm_function msm8x74_functions[] = { 756static const struct msm_function msm8x74_functions[] = {
757 FUNCTION(gpio),
731 FUNCTION(cci_i2c0), 758 FUNCTION(cci_i2c0),
732 FUNCTION(cci_i2c1), 759 FUNCTION(cci_i2c1),
733 FUNCTION(uim1), 760 FUNCTION(uim1),
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
new file mode 100644
index 000000000000..d0461cd5d707
--- /dev/null
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -0,0 +1,28 @@
1#
2# Samsung Pin control drivers
3#
4config PINCTRL_SAMSUNG
5 bool
6 select PINMUX
7 select PINCONF
8
9config PINCTRL_EXYNOS
10 bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
11 depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
12 select PINCTRL_SAMSUNG
13
14config PINCTRL_EXYNOS5440
15 bool "Samsung EXYNOS5440 SoC pinctrl driver"
16 depends on SOC_EXYNOS5440
17 select PINMUX
18 select PINCONF
19
20config PINCTRL_S3C24XX
21 bool "Samsung S3C24XX SoC pinctrl driver"
22 depends on ARCH_S3C24XX
23 select PINCTRL_SAMSUNG
24
25config PINCTRL_S3C64XX
26 bool "Samsung S3C64XX SoC pinctrl driver"
27 depends on ARCH_S3C64XX
28 select PINCTRL_SAMSUNG
diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile
new file mode 100644
index 000000000000..70160c059edd
--- /dev/null
+++ b/drivers/pinctrl/samsung/Makefile
@@ -0,0 +1,7 @@
1# Samsung pin control drivers
2
3obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
4obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
5obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
6obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o
7obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 9609c23834ce..003bfd874a61 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -33,6 +33,18 @@
33#include "pinctrl-samsung.h" 33#include "pinctrl-samsung.h"
34#include "pinctrl-exynos.h" 34#include "pinctrl-exynos.h"
35 35
36struct exynos_irq_chip {
37 struct irq_chip chip;
38
39 u32 eint_con;
40 u32 eint_mask;
41 u32 eint_pend;
42};
43
44static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
45{
46 return container_of(chip, struct exynos_irq_chip, chip);
47}
36 48
37static struct samsung_pin_bank_type bank_type_off = { 49static struct samsung_pin_bank_type bank_type_off = {
38 .fld_width = { 4, 1, 2, 2, 2, 2, }, 50 .fld_width = { 4, 1, 2, 2, 2, 2, },
@@ -50,11 +62,13 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
50 { } 62 { }
51}; 63};
52 64
53static void exynos_gpio_irq_mask(struct irq_data *irqd) 65static void exynos_irq_mask(struct irq_data *irqd)
54{ 66{
67 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
68 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
55 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 69 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
56 struct samsung_pinctrl_drv_data *d = bank->drvdata; 70 struct samsung_pinctrl_drv_data *d = bank->drvdata;
57 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; 71 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
58 unsigned long mask; 72 unsigned long mask;
59 unsigned long flags; 73 unsigned long flags;
60 74
@@ -67,20 +81,24 @@ static void exynos_gpio_irq_mask(struct irq_data *irqd)
67 spin_unlock_irqrestore(&bank->slock, flags); 81 spin_unlock_irqrestore(&bank->slock, flags);
68} 82}
69 83
70static void exynos_gpio_irq_ack(struct irq_data *irqd) 84static void exynos_irq_ack(struct irq_data *irqd)
71{ 85{
86 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
87 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 88 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
73 struct samsung_pinctrl_drv_data *d = bank->drvdata; 89 struct samsung_pinctrl_drv_data *d = bank->drvdata;
74 unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; 90 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
75 91
76 writel(1 << irqd->hwirq, d->virt_base + reg_pend); 92 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
77} 93}
78 94
79static void exynos_gpio_irq_unmask(struct irq_data *irqd) 95static void exynos_irq_unmask(struct irq_data *irqd)
80{ 96{
97 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
98 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
81 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 99 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
82 struct samsung_pinctrl_drv_data *d = bank->drvdata; 100 struct samsung_pinctrl_drv_data *d = bank->drvdata;
83 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; 101 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
84 unsigned long mask; 102 unsigned long mask;
85 unsigned long flags; 103 unsigned long flags;
86 104
@@ -93,7 +111,7 @@ static void exynos_gpio_irq_unmask(struct irq_data *irqd)
93 * masked. 111 * masked.
94 */ 112 */
95 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 113 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
96 exynos_gpio_irq_ack(irqd); 114 exynos_irq_ack(irqd);
97 115
98 spin_lock_irqsave(&bank->slock, flags); 116 spin_lock_irqsave(&bank->slock, flags);
99 117
@@ -104,16 +122,17 @@ static void exynos_gpio_irq_unmask(struct irq_data *irqd)
104 spin_unlock_irqrestore(&bank->slock, flags); 122 spin_unlock_irqrestore(&bank->slock, flags);
105} 123}
106 124
107static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 125static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
108{ 126{
127 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
128 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
109 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 129 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
110 struct samsung_pin_bank_type *bank_type = bank->type; 130 struct samsung_pin_bank_type *bank_type = bank->type;
111 struct samsung_pinctrl_drv_data *d = bank->drvdata; 131 struct samsung_pinctrl_drv_data *d = bank->drvdata;
112 struct samsung_pin_ctrl *ctrl = d->ctrl;
113 unsigned int pin = irqd->hwirq; 132 unsigned int pin = irqd->hwirq;
114 unsigned int shift = EXYNOS_EINT_CON_LEN * pin; 133 unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
115 unsigned int con, trig_type; 134 unsigned int con, trig_type;
116 unsigned long reg_con = ctrl->geint_con + bank->eint_offset; 135 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
117 unsigned long flags; 136 unsigned long flags;
118 unsigned int mask; 137 unsigned int mask;
119 138
@@ -167,12 +186,17 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
167/* 186/*
168 * irq_chip for gpio interrupts. 187 * irq_chip for gpio interrupts.
169 */ 188 */
170static struct irq_chip exynos_gpio_irq_chip = { 189static struct exynos_irq_chip exynos_gpio_irq_chip = {
171 .name = "exynos_gpio_irq_chip", 190 .chip = {
172 .irq_unmask = exynos_gpio_irq_unmask, 191 .name = "exynos_gpio_irq_chip",
173 .irq_mask = exynos_gpio_irq_mask, 192 .irq_unmask = exynos_irq_unmask,
174 .irq_ack = exynos_gpio_irq_ack, 193 .irq_mask = exynos_irq_mask,
175 .irq_set_type = exynos_gpio_irq_set_type, 194 .irq_ack = exynos_irq_ack,
195 .irq_set_type = exynos_irq_set_type,
196 },
197 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
198 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
199 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
176}; 200};
177 201
178static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, 202static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
@@ -181,7 +205,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
181 struct samsung_pin_bank *b = h->host_data; 205 struct samsung_pin_bank *b = h->host_data;
182 206
183 irq_set_chip_data(virq, b); 207 irq_set_chip_data(virq, b);
184 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, 208 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
185 handle_level_irq); 209 handle_level_irq);
186 set_irq_flags(virq, IRQF_VALID); 210 set_irq_flags(virq, IRQF_VALID);
187 return 0; 211 return 0;
@@ -202,7 +226,7 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
202 struct samsung_pin_bank *bank = ctrl->pin_banks; 226 struct samsung_pin_bank *bank = ctrl->pin_banks;
203 unsigned int svc, group, pin, virq; 227 unsigned int svc, group, pin, virq;
204 228
205 svc = readl(d->virt_base + ctrl->svc); 229 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
206 group = EXYNOS_SVC_GROUP(svc); 230 group = EXYNOS_SVC_GROUP(svc);
207 pin = svc & EXYNOS_SVC_NUM_MASK; 231 pin = svc & EXYNOS_SVC_NUM_MASK;
208 232
@@ -279,119 +303,6 @@ err_domains:
279 return ret; 303 return ret;
280} 304}
281 305
282static void exynos_wkup_irq_mask(struct irq_data *irqd)
283{
284 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
285 struct samsung_pinctrl_drv_data *d = b->drvdata;
286 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
287 unsigned long mask;
288 unsigned long flags;
289
290 spin_lock_irqsave(&b->slock, flags);
291
292 mask = readl(d->virt_base + reg_mask);
293 mask |= 1 << irqd->hwirq;
294 writel(mask, d->virt_base + reg_mask);
295
296 spin_unlock_irqrestore(&b->slock, flags);
297}
298
299static void exynos_wkup_irq_ack(struct irq_data *irqd)
300{
301 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
302 struct samsung_pinctrl_drv_data *d = b->drvdata;
303 unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
304
305 writel(1 << irqd->hwirq, d->virt_base + pend);
306}
307
308static void exynos_wkup_irq_unmask(struct irq_data *irqd)
309{
310 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
311 struct samsung_pinctrl_drv_data *d = b->drvdata;
312 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
313 unsigned long mask;
314 unsigned long flags;
315
316 /*
317 * Ack level interrupts right before unmask
318 *
319 * If we don't do this we'll get a double-interrupt. Level triggered
320 * interrupts must not fire an interrupt if the level is not
321 * _currently_ active, even if it was active while the interrupt was
322 * masked.
323 */
324 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
325 exynos_wkup_irq_ack(irqd);
326
327 spin_lock_irqsave(&b->slock, flags);
328
329 mask = readl(d->virt_base + reg_mask);
330 mask &= ~(1 << irqd->hwirq);
331 writel(mask, d->virt_base + reg_mask);
332
333 spin_unlock_irqrestore(&b->slock, flags);
334}
335
336static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
337{
338 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
339 struct samsung_pin_bank_type *bank_type = bank->type;
340 struct samsung_pinctrl_drv_data *d = bank->drvdata;
341 unsigned int pin = irqd->hwirq;
342 unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
343 unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
344 unsigned long con, trig_type;
345 unsigned long flags;
346 unsigned int mask;
347
348 switch (type) {
349 case IRQ_TYPE_EDGE_RISING:
350 trig_type = EXYNOS_EINT_EDGE_RISING;
351 break;
352 case IRQ_TYPE_EDGE_FALLING:
353 trig_type = EXYNOS_EINT_EDGE_FALLING;
354 break;
355 case IRQ_TYPE_EDGE_BOTH:
356 trig_type = EXYNOS_EINT_EDGE_BOTH;
357 break;
358 case IRQ_TYPE_LEVEL_HIGH:
359 trig_type = EXYNOS_EINT_LEVEL_HIGH;
360 break;
361 case IRQ_TYPE_LEVEL_LOW:
362 trig_type = EXYNOS_EINT_LEVEL_LOW;
363 break;
364 default:
365 pr_err("unsupported external interrupt type\n");
366 return -EINVAL;
367 }
368
369 if (type & IRQ_TYPE_EDGE_BOTH)
370 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
371 else
372 __irq_set_handler_locked(irqd->irq, handle_level_irq);
373
374 con = readl(d->virt_base + reg_con);
375 con &= ~(EXYNOS_EINT_CON_MASK << shift);
376 con |= trig_type << shift;
377 writel(con, d->virt_base + reg_con);
378
379 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
380 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
381 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
382
383 spin_lock_irqsave(&bank->slock, flags);
384
385 con = readl(d->virt_base + reg_con);
386 con &= ~(mask << shift);
387 con |= EXYNOS_EINT_FUNC << shift;
388 writel(con, d->virt_base + reg_con);
389
390 spin_unlock_irqrestore(&bank->slock, flags);
391
392 return 0;
393}
394
395static u32 exynos_eint_wake_mask = 0xffffffff; 306static u32 exynos_eint_wake_mask = 0xffffffff;
396 307
397u32 exynos_get_eint_wake_mask(void) 308u32 exynos_get_eint_wake_mask(void)
@@ -417,13 +328,18 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
417/* 328/*
418 * irq_chip for wakeup interrupts 329 * irq_chip for wakeup interrupts
419 */ 330 */
420static struct irq_chip exynos_wkup_irq_chip = { 331static struct exynos_irq_chip exynos_wkup_irq_chip = {
421 .name = "exynos_wkup_irq_chip", 332 .chip = {
422 .irq_unmask = exynos_wkup_irq_unmask, 333 .name = "exynos_wkup_irq_chip",
423 .irq_mask = exynos_wkup_irq_mask, 334 .irq_unmask = exynos_irq_unmask,
424 .irq_ack = exynos_wkup_irq_ack, 335 .irq_mask = exynos_irq_mask,
425 .irq_set_type = exynos_wkup_irq_set_type, 336 .irq_ack = exynos_irq_ack,
426 .irq_set_wake = exynos_wkup_irq_set_wake, 337 .irq_set_type = exynos_irq_set_type,
338 .irq_set_wake = exynos_wkup_irq_set_wake,
339 },
340 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
341 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
342 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
427}; 343};
428 344
429/* interrupt handler for wakeup interrupts 0..15 */ 345/* interrupt handler for wakeup interrupts 0..15 */
@@ -464,7 +380,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
464 struct irq_chip *chip = irq_get_chip(irq); 380 struct irq_chip *chip = irq_get_chip(irq);
465 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); 381 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
466 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; 382 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
467 struct samsung_pin_ctrl *ctrl = d->ctrl;
468 unsigned long pend; 383 unsigned long pend;
469 unsigned long mask; 384 unsigned long mask;
470 int i; 385 int i;
@@ -473,8 +388,10 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
473 388
474 for (i = 0; i < eintd->nr_banks; ++i) { 389 for (i = 0; i < eintd->nr_banks; ++i) {
475 struct samsung_pin_bank *b = eintd->banks[i]; 390 struct samsung_pin_bank *b = eintd->banks[i];
476 pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset); 391 pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
477 mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset); 392 + b->eint_offset);
393 mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
394 + b->eint_offset);
478 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 395 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
479 } 396 }
480 397
@@ -484,7 +401,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
484static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, 401static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
485 irq_hw_number_t hw) 402 irq_hw_number_t hw)
486{ 403{
487 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); 404 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
405 handle_level_irq);
488 irq_set_chip_data(virq, h->host_data); 406 irq_set_chip_data(virq, h->host_data);
489 set_irq_flags(virq, IRQF_VALID); 407 set_irq_flags(virq, IRQF_VALID);
490 return 0; 408 return 0;
@@ -703,13 +621,6 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
703 /* pin-controller instance 0 data */ 621 /* pin-controller instance 0 data */
704 .pin_banks = s5pv210_pin_bank, 622 .pin_banks = s5pv210_pin_bank,
705 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), 623 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
706 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
707 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
708 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
709 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
710 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
711 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
712 .svc = EXYNOS_SVC_OFFSET,
713 .eint_gpio_init = exynos_eint_gpio_init, 624 .eint_gpio_init = exynos_eint_gpio_init,
714 .eint_wkup_init = exynos_eint_wkup_init, 625 .eint_wkup_init = exynos_eint_wkup_init,
715 .suspend = exynos_pinctrl_suspend, 626 .suspend = exynos_pinctrl_suspend,
@@ -758,10 +669,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
758 /* pin-controller instance 0 data */ 669 /* pin-controller instance 0 data */
759 .pin_banks = exynos3250_pin_banks0, 670 .pin_banks = exynos3250_pin_banks0,
760 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), 671 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
761 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
762 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
763 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
764 .svc = EXYNOS_SVC_OFFSET,
765 .eint_gpio_init = exynos_eint_gpio_init, 672 .eint_gpio_init = exynos_eint_gpio_init,
766 .suspend = exynos_pinctrl_suspend, 673 .suspend = exynos_pinctrl_suspend,
767 .resume = exynos_pinctrl_resume, 674 .resume = exynos_pinctrl_resume,
@@ -770,13 +677,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
770 /* pin-controller instance 1 data */ 677 /* pin-controller instance 1 data */
771 .pin_banks = exynos3250_pin_banks1, 678 .pin_banks = exynos3250_pin_banks1,
772 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), 679 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
773 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
774 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
775 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
776 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
777 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
778 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
779 .svc = EXYNOS_SVC_OFFSET,
780 .eint_gpio_init = exynos_eint_gpio_init, 680 .eint_gpio_init = exynos_eint_gpio_init,
781 .eint_wkup_init = exynos_eint_wkup_init, 681 .eint_wkup_init = exynos_eint_wkup_init,
782 .suspend = exynos_pinctrl_suspend, 682 .suspend = exynos_pinctrl_suspend,
@@ -843,10 +743,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
843 /* pin-controller instance 0 data */ 743 /* pin-controller instance 0 data */
844 .pin_banks = exynos4210_pin_banks0, 744 .pin_banks = exynos4210_pin_banks0,
845 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 745 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
846 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
847 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
848 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
849 .svc = EXYNOS_SVC_OFFSET,
850 .eint_gpio_init = exynos_eint_gpio_init, 746 .eint_gpio_init = exynos_eint_gpio_init,
851 .suspend = exynos_pinctrl_suspend, 747 .suspend = exynos_pinctrl_suspend,
852 .resume = exynos_pinctrl_resume, 748 .resume = exynos_pinctrl_resume,
@@ -855,13 +751,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
855 /* pin-controller instance 1 data */ 751 /* pin-controller instance 1 data */
856 .pin_banks = exynos4210_pin_banks1, 752 .pin_banks = exynos4210_pin_banks1,
857 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 753 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
858 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
859 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
860 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
861 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
862 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
863 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
864 .svc = EXYNOS_SVC_OFFSET,
865 .eint_gpio_init = exynos_eint_gpio_init, 754 .eint_gpio_init = exynos_eint_gpio_init,
866 .eint_wkup_init = exynos_eint_wkup_init, 755 .eint_wkup_init = exynos_eint_wkup_init,
867 .suspend = exynos_pinctrl_suspend, 756 .suspend = exynos_pinctrl_suspend,
@@ -942,10 +831,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
942 /* pin-controller instance 0 data */ 831 /* pin-controller instance 0 data */
943 .pin_banks = exynos4x12_pin_banks0, 832 .pin_banks = exynos4x12_pin_banks0,
944 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), 833 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
945 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
946 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
947 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
948 .svc = EXYNOS_SVC_OFFSET,
949 .eint_gpio_init = exynos_eint_gpio_init, 834 .eint_gpio_init = exynos_eint_gpio_init,
950 .suspend = exynos_pinctrl_suspend, 835 .suspend = exynos_pinctrl_suspend,
951 .resume = exynos_pinctrl_resume, 836 .resume = exynos_pinctrl_resume,
@@ -954,13 +839,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
954 /* pin-controller instance 1 data */ 839 /* pin-controller instance 1 data */
955 .pin_banks = exynos4x12_pin_banks1, 840 .pin_banks = exynos4x12_pin_banks1,
956 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), 841 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
957 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
958 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
959 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
960 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
961 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
962 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
963 .svc = EXYNOS_SVC_OFFSET,
964 .eint_gpio_init = exynos_eint_gpio_init, 842 .eint_gpio_init = exynos_eint_gpio_init,
965 .eint_wkup_init = exynos_eint_wkup_init, 843 .eint_wkup_init = exynos_eint_wkup_init,
966 .suspend = exynos_pinctrl_suspend, 844 .suspend = exynos_pinctrl_suspend,
@@ -970,10 +848,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
970 /* pin-controller instance 2 data */ 848 /* pin-controller instance 2 data */
971 .pin_banks = exynos4x12_pin_banks2, 849 .pin_banks = exynos4x12_pin_banks2,
972 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), 850 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
973 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
974 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
975 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
976 .svc = EXYNOS_SVC_OFFSET,
977 .eint_gpio_init = exynos_eint_gpio_init, 851 .eint_gpio_init = exynos_eint_gpio_init,
978 .suspend = exynos_pinctrl_suspend, 852 .suspend = exynos_pinctrl_suspend,
979 .resume = exynos_pinctrl_resume, 853 .resume = exynos_pinctrl_resume,
@@ -982,10 +856,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
982 /* pin-controller instance 3 data */ 856 /* pin-controller instance 3 data */
983 .pin_banks = exynos4x12_pin_banks3, 857 .pin_banks = exynos4x12_pin_banks3,
984 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), 858 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
985 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
986 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
987 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
988 .svc = EXYNOS_SVC_OFFSET,
989 .eint_gpio_init = exynos_eint_gpio_init, 859 .eint_gpio_init = exynos_eint_gpio_init,
990 .suspend = exynos_pinctrl_suspend, 860 .suspend = exynos_pinctrl_suspend,
991 .resume = exynos_pinctrl_resume, 861 .resume = exynos_pinctrl_resume,
@@ -1058,13 +928,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1058 /* pin-controller instance 0 data */ 928 /* pin-controller instance 0 data */
1059 .pin_banks = exynos5250_pin_banks0, 929 .pin_banks = exynos5250_pin_banks0,
1060 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), 930 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
1061 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1062 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1063 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1064 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1065 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1066 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1067 .svc = EXYNOS_SVC_OFFSET,
1068 .eint_gpio_init = exynos_eint_gpio_init, 931 .eint_gpio_init = exynos_eint_gpio_init,
1069 .eint_wkup_init = exynos_eint_wkup_init, 932 .eint_wkup_init = exynos_eint_wkup_init,
1070 .suspend = exynos_pinctrl_suspend, 933 .suspend = exynos_pinctrl_suspend,
@@ -1074,10 +937,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1074 /* pin-controller instance 1 data */ 937 /* pin-controller instance 1 data */
1075 .pin_banks = exynos5250_pin_banks1, 938 .pin_banks = exynos5250_pin_banks1,
1076 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), 939 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
1077 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1078 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1079 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1080 .svc = EXYNOS_SVC_OFFSET,
1081 .eint_gpio_init = exynos_eint_gpio_init, 940 .eint_gpio_init = exynos_eint_gpio_init,
1082 .suspend = exynos_pinctrl_suspend, 941 .suspend = exynos_pinctrl_suspend,
1083 .resume = exynos_pinctrl_resume, 942 .resume = exynos_pinctrl_resume,
@@ -1086,10 +945,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1086 /* pin-controller instance 2 data */ 945 /* pin-controller instance 2 data */
1087 .pin_banks = exynos5250_pin_banks2, 946 .pin_banks = exynos5250_pin_banks2,
1088 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), 947 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
1089 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1090 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1091 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1092 .svc = EXYNOS_SVC_OFFSET,
1093 .eint_gpio_init = exynos_eint_gpio_init, 948 .eint_gpio_init = exynos_eint_gpio_init,
1094 .suspend = exynos_pinctrl_suspend, 949 .suspend = exynos_pinctrl_suspend,
1095 .resume = exynos_pinctrl_resume, 950 .resume = exynos_pinctrl_resume,
@@ -1098,10 +953,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1098 /* pin-controller instance 3 data */ 953 /* pin-controller instance 3 data */
1099 .pin_banks = exynos5250_pin_banks3, 954 .pin_banks = exynos5250_pin_banks3,
1100 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), 955 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
1101 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1102 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1103 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1104 .svc = EXYNOS_SVC_OFFSET,
1105 .eint_gpio_init = exynos_eint_gpio_init, 956 .eint_gpio_init = exynos_eint_gpio_init,
1106 .suspend = exynos_pinctrl_suspend, 957 .suspend = exynos_pinctrl_suspend,
1107 .resume = exynos_pinctrl_resume, 958 .resume = exynos_pinctrl_resume,
@@ -1158,13 +1009,6 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1158 /* pin-controller instance 0 data */ 1009 /* pin-controller instance 0 data */
1159 .pin_banks = exynos5260_pin_banks0, 1010 .pin_banks = exynos5260_pin_banks0,
1160 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 1011 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
1161 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1162 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1163 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1164 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1165 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1166 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1167 .svc = EXYNOS_SVC_OFFSET,
1168 .eint_gpio_init = exynos_eint_gpio_init, 1012 .eint_gpio_init = exynos_eint_gpio_init,
1169 .eint_wkup_init = exynos_eint_wkup_init, 1013 .eint_wkup_init = exynos_eint_wkup_init,
1170 .label = "exynos5260-gpio-ctrl0", 1014 .label = "exynos5260-gpio-ctrl0",
@@ -1172,20 +1016,12 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1172 /* pin-controller instance 1 data */ 1016 /* pin-controller instance 1 data */
1173 .pin_banks = exynos5260_pin_banks1, 1017 .pin_banks = exynos5260_pin_banks1,
1174 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 1018 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
1175 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1176 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1177 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1178 .svc = EXYNOS_SVC_OFFSET,
1179 .eint_gpio_init = exynos_eint_gpio_init, 1019 .eint_gpio_init = exynos_eint_gpio_init,
1180 .label = "exynos5260-gpio-ctrl1", 1020 .label = "exynos5260-gpio-ctrl1",
1181 }, { 1021 }, {
1182 /* pin-controller instance 2 data */ 1022 /* pin-controller instance 2 data */
1183 .pin_banks = exynos5260_pin_banks2, 1023 .pin_banks = exynos5260_pin_banks2,
1184 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 1024 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
1185 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1186 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1187 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1188 .svc = EXYNOS_SVC_OFFSET,
1189 .eint_gpio_init = exynos_eint_gpio_init, 1025 .eint_gpio_init = exynos_eint_gpio_init,
1190 .label = "exynos5260-gpio-ctrl2", 1026 .label = "exynos5260-gpio-ctrl2",
1191 }, 1027 },
@@ -1256,13 +1092,6 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1256 /* pin-controller instance 0 data */ 1092 /* pin-controller instance 0 data */
1257 .pin_banks = exynos5420_pin_banks0, 1093 .pin_banks = exynos5420_pin_banks0,
1258 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 1094 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
1259 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1260 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1261 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1262 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1263 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1264 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1265 .svc = EXYNOS_SVC_OFFSET,
1266 .eint_gpio_init = exynos_eint_gpio_init, 1095 .eint_gpio_init = exynos_eint_gpio_init,
1267 .eint_wkup_init = exynos_eint_wkup_init, 1096 .eint_wkup_init = exynos_eint_wkup_init,
1268 .label = "exynos5420-gpio-ctrl0", 1097 .label = "exynos5420-gpio-ctrl0",
@@ -1270,40 +1099,24 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1270 /* pin-controller instance 1 data */ 1099 /* pin-controller instance 1 data */
1271 .pin_banks = exynos5420_pin_banks1, 1100 .pin_banks = exynos5420_pin_banks1,
1272 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 1101 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
1273 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1274 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1275 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1276 .svc = EXYNOS_SVC_OFFSET,
1277 .eint_gpio_init = exynos_eint_gpio_init, 1102 .eint_gpio_init = exynos_eint_gpio_init,
1278 .label = "exynos5420-gpio-ctrl1", 1103 .label = "exynos5420-gpio-ctrl1",
1279 }, { 1104 }, {
1280 /* pin-controller instance 2 data */ 1105 /* pin-controller instance 2 data */
1281 .pin_banks = exynos5420_pin_banks2, 1106 .pin_banks = exynos5420_pin_banks2,
1282 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 1107 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
1283 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1284 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1285 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1286 .svc = EXYNOS_SVC_OFFSET,
1287 .eint_gpio_init = exynos_eint_gpio_init, 1108 .eint_gpio_init = exynos_eint_gpio_init,
1288 .label = "exynos5420-gpio-ctrl2", 1109 .label = "exynos5420-gpio-ctrl2",
1289 }, { 1110 }, {
1290 /* pin-controller instance 3 data */ 1111 /* pin-controller instance 3 data */
1291 .pin_banks = exynos5420_pin_banks3, 1112 .pin_banks = exynos5420_pin_banks3,
1292 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 1113 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
1293 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1294 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1295 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1296 .svc = EXYNOS_SVC_OFFSET,
1297 .eint_gpio_init = exynos_eint_gpio_init, 1114 .eint_gpio_init = exynos_eint_gpio_init,
1298 .label = "exynos5420-gpio-ctrl3", 1115 .label = "exynos5420-gpio-ctrl3",
1299 }, { 1116 }, {
1300 /* pin-controller instance 4 data */ 1117 /* pin-controller instance 4 data */
1301 .pin_banks = exynos5420_pin_banks4, 1118 .pin_banks = exynos5420_pin_banks4,
1302 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 1119 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
1303 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1304 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1305 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1306 .svc = EXYNOS_SVC_OFFSET,
1307 .eint_gpio_init = exynos_eint_gpio_init, 1120 .eint_gpio_init = exynos_eint_gpio_init,
1308 .label = "exynos5420-gpio-ctrl4", 1121 .label = "exynos5420-gpio-ctrl4",
1309 }, 1122 },
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 3c91c357792f..3c91c357792f 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
index 8fe2ab0a7698..603da2f9dd95 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -23,7 +23,7 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irqdomain.h> 24#include <linux/irqdomain.h>
25#include <linux/of_irq.h> 25#include <linux/of_irq.h>
26#include "core.h" 26#include "../core.h"
27 27
28/* EXYNOS5440 GPIO and Pinctrl register offsets */ 28/* EXYNOS5440 GPIO and Pinctrl register offsets */
29#define GPIO_MUX 0x00 29#define GPIO_MUX 0x00
@@ -371,13 +371,6 @@ static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned select
371 return 0; 371 return 0;
372} 372}
373 373
374/* disable a specified pinmux by writing to registers */
375static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
376 unsigned selector, unsigned group)
377{
378 exynos5440_pinmux_setup(pctldev, selector, group, false);
379}
380
381/* 374/*
382 * The calls to gpio_direction_output() and gpio_direction_input() 375 * The calls to gpio_direction_output() and gpio_direction_input()
383 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 376 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
@@ -395,7 +388,6 @@ static const struct pinmux_ops exynos5440_pinmux_ops = {
395 .get_function_name = exynos5440_pinmux_get_fname, 388 .get_function_name = exynos5440_pinmux_get_fname,
396 .get_function_groups = exynos5440_pinmux_get_groups, 389 .get_function_groups = exynos5440_pinmux_get_groups,
397 .enable = exynos5440_pinmux_enable, 390 .enable = exynos5440_pinmux_enable,
398 .disable = exynos5440_pinmux_disable,
399 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, 391 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
400}; 392};
401 393
diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index ad3eaad17001..ad3eaad17001 100644
--- a/drivers/pinctrl/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
diff --git a/drivers/pinctrl/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index 89143c903000..89143c903000 100644
--- a/drivers/pinctrl/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 3e61d0f8f146..b07406da333c 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -30,7 +30,7 @@
30#include <linux/spinlock.h> 30#include <linux/spinlock.h>
31#include <linux/syscore_ops.h> 31#include <linux/syscore_ops.h>
32 32
33#include "core.h" 33#include "../core.h"
34#include "pinctrl-samsung.h" 34#include "pinctrl-samsung.h"
35 35
36#define GROUP_SUFFIX "-grp" 36#define GROUP_SUFFIX "-grp"
@@ -40,13 +40,14 @@
40 40
41/* list of all possible config options supported */ 41/* list of all possible config options supported */
42static struct pin_config { 42static struct pin_config {
43 char *prop_cfg; 43 const char *property;
44 unsigned int cfg_type; 44 enum pincfg_type param;
45} pcfgs[] = { 45} cfg_params[] = {
46 { "samsung,pin-pud", PINCFG_TYPE_PUD }, 46 { "samsung,pin-pud", PINCFG_TYPE_PUD },
47 { "samsung,pin-drv", PINCFG_TYPE_DRV }, 47 { "samsung,pin-drv", PINCFG_TYPE_DRV },
48 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN }, 48 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
49 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, 49 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
50 { "samsung,pin-val", PINCFG_TYPE_DAT },
50}; 51};
51 52
52/* Global list of devices (struct samsung_pinctrl_drv_data) */ 53/* Global list of devices (struct samsung_pinctrl_drv_data) */
@@ -59,163 +60,242 @@ static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
59 return container_of(gc, struct samsung_pin_bank, gpio_chip); 60 return container_of(gc, struct samsung_pin_bank, gpio_chip);
60} 61}
61 62
62/* check if the selector is a valid pin group selector */
63static int samsung_get_group_count(struct pinctrl_dev *pctldev) 63static int samsung_get_group_count(struct pinctrl_dev *pctldev)
64{ 64{
65 struct samsung_pinctrl_drv_data *drvdata; 65 struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev);
66 66
67 drvdata = pinctrl_dev_get_drvdata(pctldev); 67 return pmx->nr_groups;
68 return drvdata->nr_groups;
69} 68}
70 69
71/* return the name of the group selected by the group selector */
72static const char *samsung_get_group_name(struct pinctrl_dev *pctldev, 70static const char *samsung_get_group_name(struct pinctrl_dev *pctldev,
73 unsigned selector) 71 unsigned group)
74{ 72{
75 struct samsung_pinctrl_drv_data *drvdata; 73 struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev);
76 74
77 drvdata = pinctrl_dev_get_drvdata(pctldev); 75 return pmx->pin_groups[group].name;
78 return drvdata->pin_groups[selector].name;
79} 76}
80 77
81/* return the pin numbers associated with the specified group */
82static int samsung_get_group_pins(struct pinctrl_dev *pctldev, 78static int samsung_get_group_pins(struct pinctrl_dev *pctldev,
83 unsigned selector, const unsigned **pins, unsigned *num_pins) 79 unsigned group,
80 const unsigned **pins,
81 unsigned *num_pins)
84{ 82{
85 struct samsung_pinctrl_drv_data *drvdata; 83 struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev);
84
85 *pins = pmx->pin_groups[group].pins;
86 *num_pins = pmx->pin_groups[group].num_pins;
86 87
87 drvdata = pinctrl_dev_get_drvdata(pctldev);
88 *pins = drvdata->pin_groups[selector].pins;
89 *num_pins = drvdata->pin_groups[selector].num_pins;
90 return 0; 88 return 0;
91} 89}
92 90
93/* create pinctrl_map entries by parsing device tree nodes */ 91static int reserve_map(struct device *dev, struct pinctrl_map **map,
94static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, 92 unsigned *reserved_maps, unsigned *num_maps,
95 struct device_node *np, struct pinctrl_map **maps, 93 unsigned reserve)
96 unsigned *nmaps)
97{ 94{
98 struct device *dev = pctldev->dev; 95 unsigned old_num = *reserved_maps;
99 struct pinctrl_map *map; 96 unsigned new_num = *num_maps + reserve;
100 unsigned long *cfg = NULL; 97 struct pinctrl_map *new_map;
101 char *gname, *fname;
102 int cfg_cnt = 0, map_cnt = 0, idx = 0;
103
104 /* count the number of config options specfied in the node */
105 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
106 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
107 cfg_cnt++;
108 }
109 98
110 /* 99 if (old_num >= new_num)
111 * Find out the number of map entries to create. All the config options 100 return 0;
112 * can be accomadated into a single config map entry.
113 */
114 if (cfg_cnt)
115 map_cnt = 1;
116 if (of_find_property(np, "samsung,pin-function", NULL))
117 map_cnt++;
118 if (!map_cnt) {
119 dev_err(dev, "node %s does not have either config or function "
120 "configurations\n", np->name);
121 return -EINVAL;
122 }
123 101
124 /* Allocate memory for pin-map entries */ 102 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
125 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); 103 if (!new_map) {
126 if (!map) { 104 dev_err(dev, "krealloc(map) failed\n");
127 dev_err(dev, "could not alloc memory for pin-maps\n");
128 return -ENOMEM; 105 return -ENOMEM;
129 } 106 }
130 *nmaps = 0;
131 107
132 /* 108 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
133 * Allocate memory for pin group name. The pin group name is derived 109
134 * from the node name from which these map entries are be created. 110 *map = new_map;
135 */ 111 *reserved_maps = new_num;
136 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); 112
137 if (!gname) { 113 return 0;
138 dev_err(dev, "failed to alloc memory for group name\n"); 114}
139 goto free_map; 115
116static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
117 unsigned *num_maps, const char *group,
118 const char *function)
119{
120 if (WARN_ON(*num_maps == *reserved_maps))
121 return -ENOSPC;
122
123 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
124 (*map)[*num_maps].data.mux.group = group;
125 (*map)[*num_maps].data.mux.function = function;
126 (*num_maps)++;
127
128 return 0;
129}
130
131static int add_map_configs(struct device *dev, struct pinctrl_map **map,
132 unsigned *reserved_maps, unsigned *num_maps,
133 const char *group, unsigned long *configs,
134 unsigned num_configs)
135{
136 unsigned long *dup_configs;
137
138 if (WARN_ON(*num_maps == *reserved_maps))
139 return -ENOSPC;
140
141 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
142 GFP_KERNEL);
143 if (!dup_configs) {
144 dev_err(dev, "kmemdup(configs) failed\n");
145 return -ENOMEM;
140 } 146 }
141 sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
142 147
143 /* 148 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
144 * don't have config options? then skip over to creating function 149 (*map)[*num_maps].data.configs.group_or_pin = group;
145 * map entries. 150 (*map)[*num_maps].data.configs.configs = dup_configs;
146 */ 151 (*map)[*num_maps].data.configs.num_configs = num_configs;
147 if (!cfg_cnt) 152 (*num_maps)++;
148 goto skip_cfgs; 153
149 154 return 0;
150 /* Allocate memory for config entries */ 155}
151 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); 156
152 if (!cfg) { 157static int add_config(struct device *dev, unsigned long **configs,
153 dev_err(dev, "failed to alloc memory for configs\n"); 158 unsigned *num_configs, unsigned long config)
154 goto free_gname; 159{
160 unsigned old_num = *num_configs;
161 unsigned new_num = old_num + 1;
162 unsigned long *new_configs;
163
164 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
165 GFP_KERNEL);
166 if (!new_configs) {
167 dev_err(dev, "krealloc(configs) failed\n");
168 return -ENOMEM;
155 } 169 }
156 170
157 /* Prepare a list of config settings */ 171 new_configs[old_num] = config;
158 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { 172
159 u32 value; 173 *configs = new_configs;
160 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value)) 174 *num_configs = new_num;
161 cfg[cfg_cnt++] = 175
162 PINCFG_PACK(pcfgs[idx].cfg_type, value); 176 return 0;
177}
178
179static void samsung_dt_free_map(struct pinctrl_dev *pctldev,
180 struct pinctrl_map *map,
181 unsigned num_maps)
182{
183 int i;
184
185 for (i = 0; i < num_maps; i++)
186 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
187 kfree(map[i].data.configs.configs);
188
189 kfree(map);
190}
191
192static int samsung_dt_subnode_to_map(struct samsung_pinctrl_drv_data *drvdata,
193 struct device *dev,
194 struct device_node *np,
195 struct pinctrl_map **map,
196 unsigned *reserved_maps,
197 unsigned *num_maps)
198{
199 int ret, i;
200 u32 val;
201 unsigned long config;
202 unsigned long *configs = NULL;
203 unsigned num_configs = 0;
204 unsigned reserve;
205 struct property *prop;
206 const char *group;
207 bool has_func = false;
208
209 ret = of_property_read_u32(np, "samsung,pin-function", &val);
210 if (!ret)
211 has_func = true;
212
213 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
214 ret = of_property_read_u32(np, cfg_params[i].property, &val);
215 if (!ret) {
216 config = PINCFG_PACK(cfg_params[i].param, val);
217 ret = add_config(dev, &configs, &num_configs, config);
218 if (ret < 0)
219 goto exit;
220 /* EINVAL=missing, which is fine since it's optional */
221 } else if (ret != -EINVAL) {
222 dev_err(dev, "could not parse property %s\n",
223 cfg_params[i].property);
224 }
163 } 225 }
164 226
165 /* create the config map entry */ 227 reserve = 0;
166 map[*nmaps].data.configs.group_or_pin = gname; 228 if (has_func)
167 map[*nmaps].data.configs.configs = cfg; 229 reserve++;
168 map[*nmaps].data.configs.num_configs = cfg_cnt; 230 if (num_configs)
169 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 231 reserve++;
170 *nmaps += 1; 232 ret = of_property_count_strings(np, "samsung,pins");
171 233 if (ret < 0) {
172skip_cfgs: 234 dev_err(dev, "could not parse property samsung,pins\n");
173 /* create the function map entry */ 235 goto exit;
174 if (of_find_property(np, "samsung,pin-function", NULL)) { 236 }
175 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); 237 reserve *= ret;
176 if (!fname) { 238
177 dev_err(dev, "failed to alloc memory for func name\n"); 239 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
178 goto free_cfg; 240 if (ret < 0)
241 goto exit;
242
243 of_property_for_each_string(np, "samsung,pins", prop, group) {
244 if (has_func) {
245 ret = add_map_mux(map, reserved_maps,
246 num_maps, group, np->full_name);
247 if (ret < 0)
248 goto exit;
179 } 249 }
180 sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
181 250
182 map[*nmaps].data.mux.group = gname; 251 if (num_configs) {
183 map[*nmaps].data.mux.function = fname; 252 ret = add_map_configs(dev, map, reserved_maps,
184 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 253 num_maps, group, configs,
185 *nmaps += 1; 254 num_configs);
255 if (ret < 0)
256 goto exit;
257 }
186 } 258 }
187 259
188 *maps = map; 260 ret = 0;
189 return 0;
190 261
191free_cfg: 262exit:
192 kfree(cfg); 263 kfree(configs);
193free_gname: 264 return ret;
194 kfree(gname);
195free_map:
196 kfree(map);
197 return -ENOMEM;
198} 265}
199 266
200/* free the memory allocated to hold the pin-map table */ 267static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
201static void samsung_dt_free_map(struct pinctrl_dev *pctldev, 268 struct device_node *np_config,
202 struct pinctrl_map *map, unsigned num_maps) 269 struct pinctrl_map **map,
270 unsigned *num_maps)
203{ 271{
204 int idx; 272 struct samsung_pinctrl_drv_data *drvdata;
205 273 unsigned reserved_maps;
206 for (idx = 0; idx < num_maps; idx++) { 274 struct device_node *np;
207 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) { 275 int ret;
208 kfree(map[idx].data.mux.function); 276
209 if (!idx) 277 drvdata = pinctrl_dev_get_drvdata(pctldev);
210 kfree(map[idx].data.mux.group); 278
211 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) { 279 reserved_maps = 0;
212 kfree(map[idx].data.configs.configs); 280 *map = NULL;
213 if (!idx) 281 *num_maps = 0;
214 kfree(map[idx].data.configs.group_or_pin); 282
283 if (!of_get_child_count(np_config))
284 return samsung_dt_subnode_to_map(drvdata, pctldev->dev,
285 np_config, map,
286 &reserved_maps,
287 num_maps);
288
289 for_each_child_of_node(np_config, np) {
290 ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map,
291 &reserved_maps, num_maps);
292 if (ret < 0) {
293 samsung_dt_free_map(pctldev, *map, *num_maps);
294 return ret;
215 } 295 }
216 }; 296 }
217 297
218 kfree(map); 298 return 0;
219} 299}
220 300
221/* list of pinctrl callbacks for the pinctrl core */ 301/* list of pinctrl callbacks for the pinctrl core */
@@ -286,83 +366,21 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
286 unsigned group, bool enable) 366 unsigned group, bool enable)
287{ 367{
288 struct samsung_pinctrl_drv_data *drvdata; 368 struct samsung_pinctrl_drv_data *drvdata;
289 const unsigned int *pins;
290 struct samsung_pin_bank *bank;
291 void __iomem *reg;
292 u32 mask, shift, data, pin_offset, cnt;
293 unsigned long flags;
294
295 drvdata = pinctrl_dev_get_drvdata(pctldev);
296 pins = drvdata->pin_groups[group].pins;
297
298 /*
299 * for each pin in the pin group selected, program the correspoding pin
300 * pin function number in the config register.
301 */
302 for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) {
303 struct samsung_pin_bank_type *type;
304
305 pin_to_reg_bank(drvdata, pins[cnt] - drvdata->ctrl->base,
306 &reg, &pin_offset, &bank);
307 type = bank->type;
308 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
309 shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC];
310 if (shift >= 32) {
311 /* Some banks have two config registers */
312 shift -= 32;
313 reg += 4;
314 }
315
316 spin_lock_irqsave(&bank->slock, flags);
317
318 data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
319 data &= ~(mask << shift);
320 if (enable)
321 data |= drvdata->pin_groups[group].func << shift;
322 writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
323
324 spin_unlock_irqrestore(&bank->slock, flags);
325 }
326}
327
328/* enable a specified pinmux by writing to registers */
329static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
330 unsigned group)
331{
332 samsung_pinmux_setup(pctldev, selector, group, true);
333 return 0;
334}
335
336/* disable a specified pinmux by writing to registers */
337static void samsung_pinmux_disable(struct pinctrl_dev *pctldev,
338 unsigned selector, unsigned group)
339{
340 samsung_pinmux_setup(pctldev, selector, group, false);
341}
342
343/*
344 * The calls to gpio_direction_output() and gpio_direction_input()
345 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
346 * function called from the gpiolib interface).
347 */
348static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
349 struct pinctrl_gpio_range *range, unsigned offset, bool input)
350{
351 struct samsung_pin_bank_type *type; 369 struct samsung_pin_bank_type *type;
352 struct samsung_pin_bank *bank; 370 struct samsung_pin_bank *bank;
353 struct samsung_pinctrl_drv_data *drvdata;
354 void __iomem *reg; 371 void __iomem *reg;
355 u32 data, pin_offset, mask, shift; 372 u32 mask, shift, data, pin_offset;
356 unsigned long flags; 373 unsigned long flags;
374 const struct samsung_pmx_func *func;
375 const struct samsung_pin_group *grp;
357 376
358 bank = gc_to_pin_bank(range->gc);
359 type = bank->type;
360 drvdata = pinctrl_dev_get_drvdata(pctldev); 377 drvdata = pinctrl_dev_get_drvdata(pctldev);
378 func = &drvdata->pmx_functions[selector];
379 grp = &drvdata->pin_groups[group];
361 380
362 pin_offset = offset - bank->pin_base; 381 pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->ctrl->base,
363 reg = drvdata->virt_base + bank->pctl_offset + 382 &reg, &pin_offset, &bank);
364 type->reg_offset[PINCFG_TYPE_FUNC]; 383 type = bank->type;
365
366 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; 384 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
367 shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; 385 shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC];
368 if (shift >= 32) { 386 if (shift >= 32) {
@@ -373,14 +391,20 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
373 391
374 spin_lock_irqsave(&bank->slock, flags); 392 spin_lock_irqsave(&bank->slock, flags);
375 393
376 data = readl(reg); 394 data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
377 data &= ~(mask << shift); 395 data &= ~(mask << shift);
378 if (!input) 396 if (enable)
379 data |= FUNC_OUTPUT << shift; 397 data |= func->val << shift;
380 writel(data, reg); 398 writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
381 399
382 spin_unlock_irqrestore(&bank->slock, flags); 400 spin_unlock_irqrestore(&bank->slock, flags);
401}
383 402
403/* enable a specified pinmux by writing to registers */
404static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
405 unsigned group)
406{
407 samsung_pinmux_setup(pctldev, selector, group, true);
384 return 0; 408 return 0;
385} 409}
386 410
@@ -390,8 +414,6 @@ static const struct pinmux_ops samsung_pinmux_ops = {
390 .get_function_name = samsung_pinmux_get_fname, 414 .get_function_name = samsung_pinmux_get_fname,
391 .get_function_groups = samsung_pinmux_get_groups, 415 .get_function_groups = samsung_pinmux_get_groups,
392 .enable = samsung_pinmux_enable, 416 .enable = samsung_pinmux_enable,
393 .disable = samsung_pinmux_disable,
394 .gpio_set_direction = samsung_pinmux_gpio_set_direction,
395}; 417};
396 418
397/* set or get the pin config settings for a specified pin */ 419/* set or get the pin config settings for a specified pin */
@@ -540,25 +562,59 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
540} 562}
541 563
542/* 564/*
543 * gpiolib gpio_direction_input callback function. The setting of the pin 565 * The calls to gpio_direction_output() and gpio_direction_input()
544 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 566 * leads to this function call.
545 * interface.
546 */ 567 */
568static int samsung_gpio_set_direction(struct gpio_chip *gc,
569 unsigned offset, bool input)
570{
571 struct samsung_pin_bank_type *type;
572 struct samsung_pin_bank *bank;
573 struct samsung_pinctrl_drv_data *drvdata;
574 void __iomem *reg;
575 u32 data, mask, shift;
576 unsigned long flags;
577
578 bank = gc_to_pin_bank(gc);
579 type = bank->type;
580 drvdata = bank->drvdata;
581
582 reg = drvdata->virt_base + bank->pctl_offset +
583 type->reg_offset[PINCFG_TYPE_FUNC];
584
585 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
586 shift = offset * type->fld_width[PINCFG_TYPE_FUNC];
587 if (shift >= 32) {
588 /* Some banks have two config registers */
589 shift -= 32;
590 reg += 4;
591 }
592
593 spin_lock_irqsave(&bank->slock, flags);
594
595 data = readl(reg);
596 data &= ~(mask << shift);
597 if (!input)
598 data |= FUNC_OUTPUT << shift;
599 writel(data, reg);
600
601 spin_unlock_irqrestore(&bank->slock, flags);
602
603 return 0;
604}
605
606/* gpiolib gpio_direction_input callback function. */
547static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 607static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
548{ 608{
549 return pinctrl_gpio_direction_input(gc->base + offset); 609 return samsung_gpio_set_direction(gc, offset, true);
550} 610}
551 611
552/* 612/* gpiolib gpio_direction_output callback function. */
553 * gpiolib gpio_direction_output callback function. The setting of the pin
554 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
555 * interface.
556 */
557static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 613static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
558 int value) 614 int value)
559{ 615{
560 samsung_gpio_set(gc, offset, value); 616 samsung_gpio_set(gc, offset, value);
561 return pinctrl_gpio_direction_output(gc->base + offset); 617 return samsung_gpio_set_direction(gc, offset, false);
562} 618}
563 619
564/* 620/*
@@ -578,87 +634,115 @@ static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
578 return (virq) ? : -ENXIO; 634 return (virq) ? : -ENXIO;
579} 635}
580 636
581/* 637static struct samsung_pin_group *samsung_pinctrl_create_groups(
582 * Parse the pin names listed in the 'samsung,pins' property and convert it 638 struct device *dev,
583 * into a list of gpio numbers are create a pin group from it. 639 struct samsung_pinctrl_drv_data *drvdata,
584 */ 640 unsigned int *cnt)
585static int samsung_pinctrl_parse_dt_pins(struct platform_device *pdev,
586 struct device_node *cfg_np,
587 struct pinctrl_desc *pctl,
588 unsigned int **pin_list,
589 unsigned int *npins)
590{ 641{
591 struct device *dev = &pdev->dev; 642 struct pinctrl_desc *ctrldesc = &drvdata->pctl;
592 struct property *prop; 643 struct samsung_pin_group *groups, *grp;
593 struct pinctrl_pin_desc const *pdesc = pctl->pins; 644 const struct pinctrl_pin_desc *pdesc;
594 unsigned int idx = 0, cnt; 645 int i;
595 const char *pin_name;
596 646
597 *npins = of_property_count_strings(cfg_np, "samsung,pins"); 647 groups = devm_kzalloc(dev, ctrldesc->npins * sizeof(*groups),
598 if (IS_ERR_VALUE(*npins)) { 648 GFP_KERNEL);
599 dev_err(dev, "invalid pin list in %s node", cfg_np->name); 649 if (!groups)
650 return ERR_PTR(-EINVAL);
651 grp = groups;
652
653 pdesc = ctrldesc->pins;
654 for (i = 0; i < ctrldesc->npins; ++i, ++pdesc, ++grp) {
655 grp->name = pdesc->name;
656 grp->pins = &pdesc->number;
657 grp->num_pins = 1;
658 }
659
660 *cnt = ctrldesc->npins;
661 return groups;
662}
663
664static int samsung_pinctrl_create_function(struct device *dev,
665 struct samsung_pinctrl_drv_data *drvdata,
666 struct device_node *func_np,
667 struct samsung_pmx_func *func)
668{
669 int npins;
670 int ret;
671 int i;
672
673 if (of_property_read_u32(func_np, "samsung,pin-function", &func->val))
674 return 0;
675
676 npins = of_property_count_strings(func_np, "samsung,pins");
677 if (npins < 1) {
678 dev_err(dev, "invalid pin list in %s node", func_np->name);
600 return -EINVAL; 679 return -EINVAL;
601 } 680 }
602 681
603 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); 682 func->name = func_np->full_name;
604 if (!*pin_list) { 683
605 dev_err(dev, "failed to allocate memory for pin list\n"); 684 func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL);
685 if (!func->groups)
606 return -ENOMEM; 686 return -ENOMEM;
607 }
608 687
609 of_property_for_each_string(cfg_np, "samsung,pins", prop, pin_name) { 688 for (i = 0; i < npins; ++i) {
610 for (cnt = 0; cnt < pctl->npins; cnt++) { 689 const char *gname;
611 if (pdesc[cnt].name) { 690
612 if (!strcmp(pin_name, pdesc[cnt].name)) { 691 ret = of_property_read_string_index(func_np, "samsung,pins",
613 (*pin_list)[idx++] = pdesc[cnt].number; 692 i, &gname);
614 break; 693 if (ret) {
615 } 694 dev_err(dev,
616 } 695 "failed to read pin name %d from %s node\n",
617 } 696 i, func_np->name);
618 if (cnt == pctl->npins) { 697 return ret;
619 dev_err(dev, "pin %s not valid in %s node\n",
620 pin_name, cfg_np->name);
621 devm_kfree(dev, *pin_list);
622 return -EINVAL;
623 } 698 }
699
700 func->groups[i] = gname;
624 } 701 }
625 702
626 return 0; 703 func->num_groups = npins;
704 return 1;
627} 705}
628 706
629/* 707static struct samsung_pmx_func *samsung_pinctrl_create_functions(
630 * Parse the information about all the available pin groups and pin functions 708 struct device *dev,
631 * from device node of the pin-controller. A pin group is formed with all 709 struct samsung_pinctrl_drv_data *drvdata,
632 * the pins listed in the "samsung,pins" property. 710 unsigned int *cnt)
633 */
634static int samsung_pinctrl_parse_dt(struct platform_device *pdev,
635 struct samsung_pinctrl_drv_data *drvdata)
636{ 711{
637 struct device *dev = &pdev->dev; 712 struct samsung_pmx_func *functions, *func;
638 struct device_node *dev_np = dev->of_node; 713 struct device_node *dev_np = dev->of_node;
639 struct device_node *cfg_np; 714 struct device_node *cfg_np;
640 struct samsung_pin_group *groups, *grp; 715 unsigned int func_cnt = 0;
641 struct samsung_pmx_func *functions, *func;
642 unsigned *pin_list;
643 unsigned int npins, grp_cnt, func_idx = 0;
644 char *gname, *fname;
645 int ret; 716 int ret;
646 717
647 grp_cnt = of_get_child_count(dev_np); 718 /*
648 if (!grp_cnt) 719 * Iterate over all the child nodes of the pin controller node
649 return -EINVAL; 720 * and create pin groups and pin function lists.
721 */
722 for_each_child_of_node(dev_np, cfg_np) {
723 struct device_node *func_np;
650 724
651 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); 725 if (!of_get_child_count(cfg_np)) {
652 if (!groups) { 726 if (!of_find_property(cfg_np,
653 dev_err(dev, "failed allocate memory for ping group list\n"); 727 "samsung,pin-function", NULL))
654 return -EINVAL; 728 continue;
729 ++func_cnt;
730 continue;
731 }
732
733 for_each_child_of_node(cfg_np, func_np) {
734 if (!of_find_property(func_np,
735 "samsung,pin-function", NULL))
736 continue;
737 ++func_cnt;
738 }
655 } 739 }
656 grp = groups;
657 740
658 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); 741 functions = devm_kzalloc(dev, func_cnt * sizeof(*functions),
742 GFP_KERNEL);
659 if (!functions) { 743 if (!functions) {
660 dev_err(dev, "failed to allocate memory for function list\n"); 744 dev_err(dev, "failed to allocate memory for function list\n");
661 return -EINVAL; 745 return ERR_PTR(-EINVAL);
662 } 746 }
663 func = functions; 747 func = functions;
664 748
@@ -666,61 +750,68 @@ static int samsung_pinctrl_parse_dt(struct platform_device *pdev,
666 * Iterate over all the child nodes of the pin controller node 750 * Iterate over all the child nodes of the pin controller node
667 * and create pin groups and pin function lists. 751 * and create pin groups and pin function lists.
668 */ 752 */
753 func_cnt = 0;
669 for_each_child_of_node(dev_np, cfg_np) { 754 for_each_child_of_node(dev_np, cfg_np) {
670 u32 function; 755 struct device_node *func_np;
671 if (!of_find_property(cfg_np, "samsung,pins", NULL)) 756
757 if (!of_get_child_count(cfg_np)) {
758 ret = samsung_pinctrl_create_function(dev, drvdata,
759 cfg_np, func);
760 if (ret < 0)
761 return ERR_PTR(ret);
762 if (ret > 0) {
763 ++func;
764 ++func_cnt;
765 }
672 continue; 766 continue;
767 }
673 768
674 ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np, 769 for_each_child_of_node(cfg_np, func_np) {
675 &drvdata->pctl, &pin_list, &npins); 770 ret = samsung_pinctrl_create_function(dev, drvdata,
676 if (ret) 771 func_np, func);
677 return ret; 772 if (ret < 0)
678 773 return ERR_PTR(ret);
679 /* derive pin group name from the node name */ 774 if (ret > 0) {
680 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, 775 ++func;
681 GFP_KERNEL); 776 ++func_cnt;
682 if (!gname) { 777 }
683 dev_err(dev, "failed to alloc memory for group name\n");
684 return -ENOMEM;
685 } 778 }
686 sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX); 779 }
687 780
688 grp->name = gname; 781 *cnt = func_cnt;
689 grp->pins = pin_list; 782 return functions;
690 grp->num_pins = npins; 783}
691 of_property_read_u32(cfg_np, "samsung,pin-function", &function);
692 grp->func = function;
693 grp++;
694 784
695 if (!of_find_property(cfg_np, "samsung,pin-function", NULL)) 785/*
696 continue; 786 * Parse the information about all the available pin groups and pin functions
787 * from device node of the pin-controller. A pin group is formed with all
788 * the pins listed in the "samsung,pins" property.
789 */
697 790
698 /* derive function name from the node name */ 791static int samsung_pinctrl_parse_dt(struct platform_device *pdev,
699 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, 792 struct samsung_pinctrl_drv_data *drvdata)
700 GFP_KERNEL); 793{
701 if (!fname) { 794 struct device *dev = &pdev->dev;
702 dev_err(dev, "failed to alloc memory for func name\n"); 795 struct samsung_pin_group *groups;
703 return -ENOMEM; 796 struct samsung_pmx_func *functions;
704 } 797 unsigned int grp_cnt = 0, func_cnt = 0;
705 sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX); 798
706 799 groups = samsung_pinctrl_create_groups(dev, drvdata, &grp_cnt);
707 func->name = fname; 800 if (IS_ERR(groups)) {
708 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 801 dev_err(dev, "failed to parse pin groups\n");
709 if (!func->groups) { 802 return PTR_ERR(groups);
710 dev_err(dev, "failed to alloc memory for group list " 803 }
711 "in pin function"); 804
712 return -ENOMEM; 805 functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt);
713 } 806 if (IS_ERR(functions)) {
714 func->groups[0] = gname; 807 dev_err(dev, "failed to parse pin functions\n");
715 func->num_groups = 1; 808 return PTR_ERR(groups);
716 func++;
717 func_idx++;
718 } 809 }
719 810
720 drvdata->pin_groups = groups; 811 drvdata->pin_groups = groups;
721 drvdata->nr_groups = grp_cnt; 812 drvdata->nr_groups = grp_cnt;
722 drvdata->pmx_functions = functions; 813 drvdata->pmx_functions = functions;
723 drvdata->nr_functions = func_idx; 814 drvdata->nr_functions = func_cnt;
724 815
725 return 0; 816 return 0;
726} 817}
@@ -790,7 +881,8 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
790 pin_bank = &drvdata->ctrl->pin_banks[bank]; 881 pin_bank = &drvdata->ctrl->pin_banks[bank];
791 pin_bank->grange.name = pin_bank->name; 882 pin_bank->grange.name = pin_bank->name;
792 pin_bank->grange.id = bank; 883 pin_bank->grange.id = bank;
793 pin_bank->grange.pin_base = pin_bank->pin_base; 884 pin_bank->grange.pin_base = drvdata->ctrl->base
885 + pin_bank->pin_base;
794 pin_bank->grange.base = pin_bank->gpio_chip.base; 886 pin_bank->grange.base = pin_bank->gpio_chip.base;
795 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 887 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
796 pin_bank->grange.gc = &pin_bank->gpio_chip; 888 pin_bank->grange.gc = &pin_bank->gpio_chip;
@@ -800,7 +892,19 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
800 return 0; 892 return 0;
801} 893}
802 894
895static int samsung_gpio_request(struct gpio_chip *chip, unsigned offset)
896{
897 return pinctrl_request_gpio(chip->base + offset);
898}
899
900static void samsung_gpio_free(struct gpio_chip *chip, unsigned offset)
901{
902 pinctrl_free_gpio(chip->base + offset);
903}
904
803static const struct gpio_chip samsung_gpiolib_chip = { 905static const struct gpio_chip samsung_gpiolib_chip = {
906 .request = samsung_gpio_request,
907 .free = samsung_gpio_free,
804 .set = samsung_gpio_set, 908 .set = samsung_gpio_set,
805 .get = samsung_gpio_get, 909 .get = samsung_gpio_get,
806 .direction_input = samsung_gpio_direction_input, 910 .direction_input = samsung_gpio_direction_input,
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index b3e41fa5798b..2b882320e8e9 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -156,13 +156,6 @@ struct samsung_pin_bank {
156 * @nr_banks: number of pin banks. 156 * @nr_banks: number of pin banks.
157 * @base: starting system wide pin number. 157 * @base: starting system wide pin number.
158 * @nr_pins: number of pins supported by the controller. 158 * @nr_pins: number of pins supported by the controller.
159 * @geint_con: offset of the ext-gpio controller registers.
160 * @geint_mask: offset of the ext-gpio interrupt mask registers.
161 * @geint_pend: offset of the ext-gpio interrupt pending registers.
162 * @weint_con: offset of the ext-wakeup controller registers.
163 * @weint_mask: offset of the ext-wakeup interrupt mask registers.
164 * @weint_pend: offset of the ext-wakeup interrupt pending registers.
165 * @svc: offset of the interrupt service register.
166 * @eint_gpio_init: platform specific callback to setup the external gpio 159 * @eint_gpio_init: platform specific callback to setup the external gpio
167 * interrupts for the controller. 160 * interrupts for the controller.
168 * @eint_wkup_init: platform specific callback to setup the external wakeup 161 * @eint_wkup_init: platform specific callback to setup the external wakeup
@@ -176,16 +169,6 @@ struct samsung_pin_ctrl {
176 u32 base; 169 u32 base;
177 u32 nr_pins; 170 u32 nr_pins;
178 171
179 u32 geint_con;
180 u32 geint_mask;
181 u32 geint_pend;
182
183 u32 weint_con;
184 u32 weint_mask;
185 u32 weint_pend;
186
187 u32 svc;
188
189 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 172 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
190 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); 173 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
191 void (*suspend)(struct samsung_pinctrl_drv_data *); 174 void (*suspend)(struct samsung_pinctrl_drv_data *);
@@ -248,6 +231,7 @@ struct samsung_pmx_func {
248 const char *name; 231 const char *name;
249 const char **groups; 232 const char **groups;
250 u8 num_groups; 233 u8 num_groups;
234 u32 val;
251}; 235};
252 236
253/* list of all exported SoC specific data */ 237/* list of all exported SoC specific data */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index a9288ab01f7b..80f641ee4dea 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -409,11 +409,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
409 409
410int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) 410int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
411{ 411{
412 int err; 412 gpiochip_remove(&pfc->gpio->gpio_chip);
413 int ret; 413 gpiochip_remove(&pfc->func->gpio_chip);
414
415 ret = gpiochip_remove(&pfc->gpio->gpio_chip);
416 err = gpiochip_remove(&pfc->func->gpio_chip);
417 414
418 return ret < 0 ? ret : err; 415 return 0;
419} 416}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 2e688dc4a3c8..576d41b459e9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1726,6 +1726,133 @@ static const unsigned int audio_clkout_mux[] = {
1726 AUDIO_CLKOUT_MARK, 1726 AUDIO_CLKOUT_MARK,
1727}; 1727};
1728 1728
1729/* - CAN -------------------------------------------------------------------- */
1730
1731static const unsigned int can0_data_pins[] = {
1732 /* TX, RX */
1733 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1734};
1735
1736static const unsigned int can0_data_mux[] = {
1737 CAN0_TX_MARK, CAN0_RX_MARK,
1738};
1739
1740static const unsigned int can0_data_b_pins[] = {
1741 /* TX, RX */
1742 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1743};
1744
1745static const unsigned int can0_data_b_mux[] = {
1746 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1747};
1748
1749static const unsigned int can0_data_c_pins[] = {
1750 /* TX, RX */
1751 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1752};
1753
1754static const unsigned int can0_data_c_mux[] = {
1755 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1756};
1757
1758static const unsigned int can0_data_d_pins[] = {
1759 /* TX, RX */
1760 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1761};
1762
1763static const unsigned int can0_data_d_mux[] = {
1764 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1765};
1766
1767static const unsigned int can0_data_e_pins[] = {
1768 /* TX, RX */
1769 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1770};
1771
1772static const unsigned int can0_data_e_mux[] = {
1773 CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1774};
1775
1776static const unsigned int can0_data_f_pins[] = {
1777 /* TX, RX */
1778 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1779};
1780
1781static const unsigned int can0_data_f_mux[] = {
1782 CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1783};
1784
1785static const unsigned int can1_data_pins[] = {
1786 /* TX, RX */
1787 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1788};
1789
1790static const unsigned int can1_data_mux[] = {
1791 CAN1_TX_MARK, CAN1_RX_MARK,
1792};
1793
1794static const unsigned int can1_data_b_pins[] = {
1795 /* TX, RX */
1796 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1797};
1798
1799static const unsigned int can1_data_b_mux[] = {
1800 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1801};
1802
1803static const unsigned int can1_data_c_pins[] = {
1804 /* TX, RX */
1805 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1806};
1807
1808static const unsigned int can1_data_c_mux[] = {
1809 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1810};
1811
1812static const unsigned int can1_data_d_pins[] = {
1813 /* TX, RX */
1814 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1815};
1816
1817static const unsigned int can1_data_d_mux[] = {
1818 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1819};
1820
1821static const unsigned int can_clk_pins[] = {
1822 /* CLK */
1823 RCAR_GP_PIN(7, 2),
1824};
1825
1826static const unsigned int can_clk_mux[] = {
1827 CAN_CLK_MARK,
1828};
1829
1830static const unsigned int can_clk_b_pins[] = {
1831 /* CLK */
1832 RCAR_GP_PIN(5, 21),
1833};
1834
1835static const unsigned int can_clk_b_mux[] = {
1836 CAN_CLK_B_MARK,
1837};
1838
1839static const unsigned int can_clk_c_pins[] = {
1840 /* CLK */
1841 RCAR_GP_PIN(4, 30),
1842};
1843
1844static const unsigned int can_clk_c_mux[] = {
1845 CAN_CLK_C_MARK,
1846};
1847
1848static const unsigned int can_clk_d_pins[] = {
1849 /* CLK */
1850 RCAR_GP_PIN(7, 19),
1851};
1852
1853static const unsigned int can_clk_d_mux[] = {
1854 CAN_CLK_D_MARK,
1855};
1729 1856
1730/* - DU --------------------------------------------------------------------- */ 1857/* - DU --------------------------------------------------------------------- */
1731static const unsigned int du_rgb666_pins[] = { 1858static const unsigned int du_rgb666_pins[] = {
@@ -1867,6 +1994,192 @@ static const unsigned int eth_rmii_mux[] = {
1867 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 1994 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1868 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 1995 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1869}; 1996};
1997
1998/* - HSCIF0 ----------------------------------------------------------------- */
1999static const unsigned int hscif0_data_pins[] = {
2000 /* RX, TX */
2001 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2002};
2003static const unsigned int hscif0_data_mux[] = {
2004 HRX0_MARK, HTX0_MARK,
2005};
2006static const unsigned int hscif0_clk_pins[] = {
2007 /* SCK */
2008 RCAR_GP_PIN(7, 2),
2009};
2010static const unsigned int hscif0_clk_mux[] = {
2011 HSCK0_MARK,
2012};
2013static const unsigned int hscif0_ctrl_pins[] = {
2014 /* RTS, CTS */
2015 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2016};
2017static const unsigned int hscif0_ctrl_mux[] = {
2018 HRTS0_N_MARK, HCTS0_N_MARK,
2019};
2020static const unsigned int hscif0_data_b_pins[] = {
2021 /* RX, TX */
2022 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2023};
2024static const unsigned int hscif0_data_b_mux[] = {
2025 HRX0_B_MARK, HTX0_B_MARK,
2026};
2027static const unsigned int hscif0_ctrl_b_pins[] = {
2028 /* RTS, CTS */
2029 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2030};
2031static const unsigned int hscif0_ctrl_b_mux[] = {
2032 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2033};
2034static const unsigned int hscif0_data_c_pins[] = {
2035 /* RX, TX */
2036 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2037};
2038static const unsigned int hscif0_data_c_mux[] = {
2039 HRX0_C_MARK, HTX0_C_MARK,
2040};
2041static const unsigned int hscif0_clk_c_pins[] = {
2042 /* SCK */
2043 RCAR_GP_PIN(5, 31),
2044};
2045static const unsigned int hscif0_clk_c_mux[] = {
2046 HSCK0_C_MARK,
2047};
2048/* - HSCIF1 ----------------------------------------------------------------- */
2049static const unsigned int hscif1_data_pins[] = {
2050 /* RX, TX */
2051 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2052};
2053static const unsigned int hscif1_data_mux[] = {
2054 HRX1_MARK, HTX1_MARK,
2055};
2056static const unsigned int hscif1_clk_pins[] = {
2057 /* SCK */
2058 RCAR_GP_PIN(7, 7),
2059};
2060static const unsigned int hscif1_clk_mux[] = {
2061 HSCK1_MARK,
2062};
2063static const unsigned int hscif1_ctrl_pins[] = {
2064 /* RTS, CTS */
2065 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2066};
2067static const unsigned int hscif1_ctrl_mux[] = {
2068 HRTS1_N_MARK, HCTS1_N_MARK,
2069};
2070static const unsigned int hscif1_data_b_pins[] = {
2071 /* RX, TX */
2072 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2073};
2074static const unsigned int hscif1_data_b_mux[] = {
2075 HRX1_B_MARK, HTX1_B_MARK,
2076};
2077static const unsigned int hscif1_data_c_pins[] = {
2078 /* RX, TX */
2079 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2080};
2081static const unsigned int hscif1_data_c_mux[] = {
2082 HRX1_C_MARK, HTX1_C_MARK,
2083};
2084static const unsigned int hscif1_clk_c_pins[] = {
2085 /* SCK */
2086 RCAR_GP_PIN(7, 16),
2087};
2088static const unsigned int hscif1_clk_c_mux[] = {
2089 HSCK1_C_MARK,
2090};
2091static const unsigned int hscif1_ctrl_c_pins[] = {
2092 /* RTS, CTS */
2093 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2094};
2095static const unsigned int hscif1_ctrl_c_mux[] = {
2096 HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2097};
2098static const unsigned int hscif1_data_d_pins[] = {
2099 /* RX, TX */
2100 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2101};
2102static const unsigned int hscif1_data_d_mux[] = {
2103 HRX1_D_MARK, HTX1_D_MARK,
2104};
2105static const unsigned int hscif1_data_e_pins[] = {
2106 /* RX, TX */
2107 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2108};
2109static const unsigned int hscif1_data_e_mux[] = {
2110 HRX1_C_MARK, HTX1_C_MARK,
2111};
2112static const unsigned int hscif1_clk_e_pins[] = {
2113 /* SCK */
2114 RCAR_GP_PIN(2, 6),
2115};
2116static const unsigned int hscif1_clk_e_mux[] = {
2117 HSCK1_E_MARK,
2118};
2119static const unsigned int hscif1_ctrl_e_pins[] = {
2120 /* RTS, CTS */
2121 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2122};
2123static const unsigned int hscif1_ctrl_e_mux[] = {
2124 HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2125};
2126/* - HSCIF2 ----------------------------------------------------------------- */
2127static const unsigned int hscif2_data_pins[] = {
2128 /* RX, TX */
2129 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2130};
2131static const unsigned int hscif2_data_mux[] = {
2132 HRX2_MARK, HTX2_MARK,
2133};
2134static const unsigned int hscif2_clk_pins[] = {
2135 /* SCK */
2136 RCAR_GP_PIN(4, 15),
2137};
2138static const unsigned int hscif2_clk_mux[] = {
2139 HSCK2_MARK,
2140};
2141static const unsigned int hscif2_ctrl_pins[] = {
2142 /* RTS, CTS */
2143 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2144};
2145static const unsigned int hscif2_ctrl_mux[] = {
2146 HRTS2_N_MARK, HCTS2_N_MARK,
2147};
2148static const unsigned int hscif2_data_b_pins[] = {
2149 /* RX, TX */
2150 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2151};
2152static const unsigned int hscif2_data_b_mux[] = {
2153 HRX2_B_MARK, HTX2_B_MARK,
2154};
2155static const unsigned int hscif2_ctrl_b_pins[] = {
2156 /* RTS, CTS */
2157 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2158};
2159static const unsigned int hscif2_ctrl_b_mux[] = {
2160 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2161};
2162static const unsigned int hscif2_data_c_pins[] = {
2163 /* RX, TX */
2164 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2165};
2166static const unsigned int hscif2_data_c_mux[] = {
2167 HRX2_C_MARK, HTX2_C_MARK,
2168};
2169static const unsigned int hscif2_clk_c_pins[] = {
2170 /* SCK */
2171 RCAR_GP_PIN(5, 31),
2172};
2173static const unsigned int hscif2_clk_c_mux[] = {
2174 HSCK2_C_MARK,
2175};
2176static const unsigned int hscif2_data_d_pins[] = {
2177 /* RX, TX */
2178 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2179};
2180static const unsigned int hscif2_data_d_mux[] = {
2181 HRX2_B_MARK, HTX2_D_MARK,
2182};
1870/* - I2C0 ------------------------------------------------------------------- */ 2183/* - I2C0 ------------------------------------------------------------------- */
1871static const unsigned int i2c0_pins[] = { 2184static const unsigned int i2c0_pins[] = {
1872 /* SCL, SDA */ 2185 /* SCL, SDA */
@@ -3869,6 +4182,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3869 SH_PFC_PIN_GROUP(audio_clk_b_b), 4182 SH_PFC_PIN_GROUP(audio_clk_b_b),
3870 SH_PFC_PIN_GROUP(audio_clk_c), 4183 SH_PFC_PIN_GROUP(audio_clk_c),
3871 SH_PFC_PIN_GROUP(audio_clkout), 4184 SH_PFC_PIN_GROUP(audio_clkout),
4185 SH_PFC_PIN_GROUP(can0_data),
4186 SH_PFC_PIN_GROUP(can0_data_b),
4187 SH_PFC_PIN_GROUP(can0_data_c),
4188 SH_PFC_PIN_GROUP(can0_data_d),
4189 SH_PFC_PIN_GROUP(can0_data_e),
4190 SH_PFC_PIN_GROUP(can0_data_f),
4191 SH_PFC_PIN_GROUP(can1_data),
4192 SH_PFC_PIN_GROUP(can1_data_b),
4193 SH_PFC_PIN_GROUP(can1_data_c),
4194 SH_PFC_PIN_GROUP(can1_data_d),
4195 SH_PFC_PIN_GROUP(can_clk),
4196 SH_PFC_PIN_GROUP(can_clk_b),
4197 SH_PFC_PIN_GROUP(can_clk_c),
4198 SH_PFC_PIN_GROUP(can_clk_d),
3872 SH_PFC_PIN_GROUP(du_rgb666), 4199 SH_PFC_PIN_GROUP(du_rgb666),
3873 SH_PFC_PIN_GROUP(du_rgb888), 4200 SH_PFC_PIN_GROUP(du_rgb888),
3874 SH_PFC_PIN_GROUP(du_clk_out_0), 4201 SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -3885,6 +4212,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3885 SH_PFC_PIN_GROUP(eth_magic), 4212 SH_PFC_PIN_GROUP(eth_magic),
3886 SH_PFC_PIN_GROUP(eth_mdio), 4213 SH_PFC_PIN_GROUP(eth_mdio),
3887 SH_PFC_PIN_GROUP(eth_rmii), 4214 SH_PFC_PIN_GROUP(eth_rmii),
4215 SH_PFC_PIN_GROUP(hscif0_data),
4216 SH_PFC_PIN_GROUP(hscif0_clk),
4217 SH_PFC_PIN_GROUP(hscif0_ctrl),
4218 SH_PFC_PIN_GROUP(hscif0_data_b),
4219 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4220 SH_PFC_PIN_GROUP(hscif0_data_c),
4221 SH_PFC_PIN_GROUP(hscif0_clk_c),
4222 SH_PFC_PIN_GROUP(hscif1_data),
4223 SH_PFC_PIN_GROUP(hscif1_clk),
4224 SH_PFC_PIN_GROUP(hscif1_ctrl),
4225 SH_PFC_PIN_GROUP(hscif1_data_b),
4226 SH_PFC_PIN_GROUP(hscif1_data_c),
4227 SH_PFC_PIN_GROUP(hscif1_clk_c),
4228 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4229 SH_PFC_PIN_GROUP(hscif1_data_d),
4230 SH_PFC_PIN_GROUP(hscif1_data_e),
4231 SH_PFC_PIN_GROUP(hscif1_clk_e),
4232 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4233 SH_PFC_PIN_GROUP(hscif2_data),
4234 SH_PFC_PIN_GROUP(hscif2_clk),
4235 SH_PFC_PIN_GROUP(hscif2_ctrl),
4236 SH_PFC_PIN_GROUP(hscif2_data_b),
4237 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4238 SH_PFC_PIN_GROUP(hscif2_data_c),
4239 SH_PFC_PIN_GROUP(hscif2_clk_c),
4240 SH_PFC_PIN_GROUP(hscif2_data_d),
3888 SH_PFC_PIN_GROUP(i2c0), 4241 SH_PFC_PIN_GROUP(i2c0),
3889 SH_PFC_PIN_GROUP(i2c0_b), 4242 SH_PFC_PIN_GROUP(i2c0_b),
3890 SH_PFC_PIN_GROUP(i2c0_c), 4243 SH_PFC_PIN_GROUP(i2c0_c),
@@ -4155,6 +4508,30 @@ static const char * const audio_clk_groups[] = {
4155 "audio_clkout", 4508 "audio_clkout",
4156}; 4509};
4157 4510
4511static const char * const can0_groups[] = {
4512 "can0_data_a",
4513 "can0_data_b",
4514 "can0_data_c",
4515 "can0_data_d",
4516 "can0_data_e",
4517 "can0_data_f",
4518 "can_clk_a",
4519 "can_clk_b",
4520 "can_clk_c",
4521 "can_clk_d",
4522};
4523
4524static const char * const can1_groups[] = {
4525 "can1_data_a",
4526 "can1_data_b",
4527 "can1_data_c",
4528 "can1_data_d",
4529 "can_clk_a",
4530 "can_clk_b",
4531 "can_clk_c",
4532 "can_clk_d",
4533};
4534
4158static const char * const du_groups[] = { 4535static const char * const du_groups[] = {
4159 "du_rgb666", 4536 "du_rgb666",
4160 "du_rgb888", 4537 "du_rgb888",
@@ -4183,6 +4560,41 @@ static const char * const eth_groups[] = {
4183 "eth_rmii", 4560 "eth_rmii",
4184}; 4561};
4185 4562
4563static const char * const hscif0_groups[] = {
4564 "hscif0_data",
4565 "hscif0_clk",
4566 "hscif0_ctrl",
4567 "hscif0_data_b",
4568 "hscif0_ctrl_b",
4569 "hscif0_data_c",
4570 "hscif0_clk_c",
4571};
4572
4573static const char * const hscif1_groups[] = {
4574 "hscif1_data",
4575 "hscif1_clk",
4576 "hscif1_ctrl",
4577 "hscif1_data_b",
4578 "hscif1_data_c",
4579 "hscif1_clk_c",
4580 "hscif1_ctrl_c",
4581 "hscif1_data_d",
4582 "hscif1_data_e",
4583 "hscif1_clk_e",
4584 "hscif1_ctrl_e",
4585};
4586
4587static const char * const hscif2_groups[] = {
4588 "hscif2_data",
4589 "hscif2_clk",
4590 "hscif2_ctrl",
4591 "hscif2_data_b",
4592 "hscif2_ctrl_b",
4593 "hscif2_data_c",
4594 "hscif2_clk_c",
4595 "hscif2_data_d",
4596};
4597
4186static const char * const i2c0_groups[] = { 4598static const char * const i2c0_groups[] = {
4187 "i2c0", 4599 "i2c0",
4188 "i2c0_b", 4600 "i2c0_b",
@@ -4543,10 +4955,15 @@ static const char * const vin2_groups[] = {
4543 4955
4544static const struct sh_pfc_function pinmux_functions[] = { 4956static const struct sh_pfc_function pinmux_functions[] = {
4545 SH_PFC_FUNCTION(audio_clk), 4957 SH_PFC_FUNCTION(audio_clk),
4958 SH_PFC_FUNCTION(can0),
4959 SH_PFC_FUNCTION(can1),
4546 SH_PFC_FUNCTION(du), 4960 SH_PFC_FUNCTION(du),
4547 SH_PFC_FUNCTION(du0), 4961 SH_PFC_FUNCTION(du0),
4548 SH_PFC_FUNCTION(du1), 4962 SH_PFC_FUNCTION(du1),
4549 SH_PFC_FUNCTION(eth), 4963 SH_PFC_FUNCTION(eth),
4964 SH_PFC_FUNCTION(hscif0),
4965 SH_PFC_FUNCTION(hscif1),
4966 SH_PFC_FUNCTION(hscif2),
4550 SH_PFC_FUNCTION(i2c0), 4967 SH_PFC_FUNCTION(i2c0),
4551 SH_PFC_FUNCTION(i2c1), 4968 SH_PFC_FUNCTION(i2c1),
4552 SH_PFC_FUNCTION(i2c2), 4969 SH_PFC_FUNCTION(i2c2),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index ee370de4609a..0bd8f4401b42 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3842,7 +3842,8 @@ static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
3842 cfg.init_data = &sh73a0_vccq_mc0_init_data; 3842 cfg.init_data = &sh73a0_vccq_mc0_init_data;
3843 cfg.driver_data = pfc; 3843 cfg.driver_data = pfc;
3844 3844
3845 data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg); 3845 data->vccq_mc0 = devm_regulator_register(pfc->dev,
3846 &sh73a0_vccq_mc0_desc, &cfg);
3846 if (IS_ERR(data->vccq_mc0)) { 3847 if (IS_ERR(data->vccq_mc0)) {
3847 ret = PTR_ERR(data->vccq_mc0); 3848 ret = PTR_ERR(data->vccq_mc0);
3848 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", 3849 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
@@ -3855,16 +3856,8 @@ static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
3855 return 0; 3856 return 0;
3856} 3857}
3857 3858
3858static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
3859{
3860 struct sh73a0_pinmux_data *data = pfc->soc_data;
3861
3862 regulator_unregister(data->vccq_mc0);
3863}
3864
3865static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { 3859static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
3866 .init = sh73a0_pinmux_soc_init, 3860 .init = sh73a0_pinmux_soc_init,
3867 .exit = sh73a0_pinmux_soc_exit,
3868 .get_bias = sh73a0_pinmux_get_bias, 3861 .get_bias = sh73a0_pinmux_get_bias,
3869 .set_bias = sh73a0_pinmux_set_bias, 3862 .set_bias = sh73a0_pinmux_set_bias,
3870}; 3863};
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index e758af95c209..11db3ee39d40 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -345,27 +345,6 @@ done:
345 return ret; 345 return ret;
346} 346}
347 347
348static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
349 unsigned group)
350{
351 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
352 struct sh_pfc *pfc = pmx->pfc;
353 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
354 unsigned long flags;
355 unsigned int i;
356
357 spin_lock_irqsave(&pfc->lock, flags);
358
359 for (i = 0; i < grp->nr_pins; ++i) {
360 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
361 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
362
363 cfg->type = PINMUX_TYPE_NONE;
364 }
365
366 spin_unlock_irqrestore(&pfc->lock, flags);
367}
368
369static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, 348static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
370 struct pinctrl_gpio_range *range, 349 struct pinctrl_gpio_range *range,
371 unsigned offset) 350 unsigned offset)
@@ -464,7 +443,6 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = {
464 .get_function_name = sh_pfc_get_function_name, 443 .get_function_name = sh_pfc_get_function_name,
465 .get_function_groups = sh_pfc_get_function_groups, 444 .get_function_groups = sh_pfc_get_function_groups,
466 .enable = sh_pfc_func_enable, 445 .enable = sh_pfc_func_enable,
467 .disable = sh_pfc_func_disable,
468 .gpio_request_enable = sh_pfc_gpio_request_enable, 446 .gpio_request_enable = sh_pfc_gpio_request_enable,
469 .gpio_disable_free = sh_pfc_gpio_disable_free, 447 .gpio_disable_free = sh_pfc_gpio_disable_free,
470 .gpio_set_direction = sh_pfc_gpio_set_direction, 448 .gpio_set_direction = sh_pfc_gpio_set_direction,
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 014f5b1fee55..4c1d7c68666d 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -186,15 +186,6 @@ static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
186 return 0; 186 return 0;
187} 187}
188 188
189static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
190 unsigned group)
191{
192 struct sirfsoc_pmx *spmx;
193
194 spmx = pinctrl_dev_get_drvdata(pmxdev);
195 sirfsoc_pinmux_endisable(spmx, selector, false);
196}
197
198static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) 189static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
199{ 190{
200 return sirfsoc_pmxfunc_cnt; 191 return sirfsoc_pmxfunc_cnt;
@@ -240,7 +231,6 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
240 231
241static struct pinmux_ops sirfsoc_pinmux_ops = { 232static struct pinmux_ops sirfsoc_pinmux_ops = {
242 .enable = sirfsoc_pinmux_enable, 233 .enable = sirfsoc_pinmux_enable,
243 .disable = sirfsoc_pinmux_disable,
244 .get_functions_count = sirfsoc_pinmux_get_funcs_count, 234 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
245 .get_function_name = sirfsoc_pinmux_get_func_name, 235 .get_function_name = sirfsoc_pinmux_get_func_name,
246 .get_function_groups = sirfsoc_pinmux_get_groups, 236 .get_function_groups = sirfsoc_pinmux_get_groups,
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
index 04d93e602674..9ef18eb958e1 100644
--- a/drivers/pinctrl/spear/Kconfig
+++ b/drivers/pinctrl/spear/Kconfig
@@ -48,6 +48,7 @@ config PINCTRL_SPEAR1340
48config PINCTRL_SPEAR_PLGPIO 48config PINCTRL_SPEAR_PLGPIO
49 bool "SPEAr SoC PLGPIO Controller" 49 bool "SPEAr SoC PLGPIO Controller"
50 depends on GPIOLIB && PINCTRL_SPEAR 50 depends on GPIOLIB && PINCTRL_SPEAR
51 select GPIOLIB_IRQCHIP
51 help 52 help
52 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr 53 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
53 SoCs. 54 SoCs.
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index ff2940e9f2a7..bddb79105d67 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -11,12 +11,11 @@
11 11
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/err.h> 13#include <linux/err.h>
14#include <linux/gpio.h> 14#include <linux/gpio/driver.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_platform.h>
20#include <linux/pinctrl/consumer.h> 19#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h> 20#include <linux/platform_device.h>
22#include <linux/pm.h> 21#include <linux/pm.h>
@@ -54,7 +53,6 @@ struct plgpio_regs {
54 * 53 *
55 * lock: lock for guarding gpio registers 54 * lock: lock for guarding gpio registers
56 * base: base address of plgpio block 55 * base: base address of plgpio block
57 * irq_base: irq number of plgpio0
58 * chip: gpio framework specific chip information structure 56 * chip: gpio framework specific chip information structure
59 * p2o: function ptr for pin to offset conversion. This is required only for 57 * p2o: function ptr for pin to offset conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1. 58 * machines where mapping b/w pin and offset is not 1-to-1.
@@ -68,8 +66,6 @@ struct plgpio {
68 spinlock_t lock; 66 spinlock_t lock;
69 void __iomem *base; 67 void __iomem *base;
70 struct clk *clk; 68 struct clk *clk;
71 unsigned irq_base;
72 struct irq_domain *irq_domain;
73 struct gpio_chip chip; 69 struct gpio_chip chip;
74 int (*p2o)(int pin); /* pin_to_offset */ 70 int (*p2o)(int pin); /* pin_to_offset */
75 int (*o2p)(int offset); /* offset_to_pin */ 71 int (*o2p)(int offset); /* offset_to_pin */
@@ -280,21 +276,12 @@ disable_clk:
280 pinctrl_free_gpio(gpio); 276 pinctrl_free_gpio(gpio);
281} 277}
282 278
283static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
284{
285 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
286
287 if (IS_ERR_VALUE(plgpio->irq_base))
288 return -EINVAL;
289
290 return irq_find_mapping(plgpio->irq_domain, offset);
291}
292
293/* PLGPIO IRQ */ 279/* PLGPIO IRQ */
294static void plgpio_irq_disable(struct irq_data *d) 280static void plgpio_irq_disable(struct irq_data *d)
295{ 281{
296 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 282 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
297 int offset = d->irq - plgpio->irq_base; 283 struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
284 int offset = d->hwirq;
298 unsigned long flags; 285 unsigned long flags;
299 286
300 /* get correct offset for "offset" pin */ 287 /* get correct offset for "offset" pin */
@@ -311,8 +298,9 @@ static void plgpio_irq_disable(struct irq_data *d)
311 298
312static void plgpio_irq_enable(struct irq_data *d) 299static void plgpio_irq_enable(struct irq_data *d)
313{ 300{
314 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 301 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
315 int offset = d->irq - plgpio->irq_base; 302 struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
303 int offset = d->hwirq;
316 unsigned long flags; 304 unsigned long flags;
317 305
318 /* get correct offset for "offset" pin */ 306 /* get correct offset for "offset" pin */
@@ -329,8 +317,9 @@ static void plgpio_irq_enable(struct irq_data *d)
329 317
330static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) 318static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
331{ 319{
332 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 320 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
333 int offset = d->irq - plgpio->irq_base; 321 struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
322 int offset = d->hwirq;
334 void __iomem *reg_off; 323 void __iomem *reg_off;
335 unsigned int supported_type = 0, val; 324 unsigned int supported_type = 0, val;
336 325
@@ -369,7 +358,8 @@ static struct irq_chip plgpio_irqchip = {
369 358
370static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc) 359static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
371{ 360{
372 struct plgpio *plgpio = irq_get_handler_data(irq); 361 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
362 struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
373 struct irq_chip *irqchip = irq_desc_get_chip(desc); 363 struct irq_chip *irqchip = irq_desc_get_chip(desc);
374 int regs_count, count, pin, offset, i = 0; 364 int regs_count, count, pin, offset, i = 0;
375 unsigned long pending; 365 unsigned long pending;
@@ -410,7 +400,8 @@ static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
410 400
411 /* get correct irq line number */ 401 /* get correct irq line number */
412 pin = i * MAX_GPIO_PER_REG + pin; 402 pin = i * MAX_GPIO_PER_REG + pin;
413 generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin)); 403 generic_handle_irq(
404 irq_find_mapping(gc->irqdomain, pin));
414 } 405 }
415 } 406 }
416 chained_irq_exit(irqchip, desc); 407 chained_irq_exit(irqchip, desc);
@@ -523,10 +514,9 @@ end:
523} 514}
524static int plgpio_probe(struct platform_device *pdev) 515static int plgpio_probe(struct platform_device *pdev)
525{ 516{
526 struct device_node *np = pdev->dev.of_node;
527 struct plgpio *plgpio; 517 struct plgpio *plgpio;
528 struct resource *res; 518 struct resource *res;
529 int ret, irq, i; 519 int ret, irq;
530 520
531 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); 521 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
532 if (!plgpio) { 522 if (!plgpio) {
@@ -563,7 +553,6 @@ static int plgpio_probe(struct platform_device *pdev)
563 platform_set_drvdata(pdev, plgpio); 553 platform_set_drvdata(pdev, plgpio);
564 spin_lock_init(&plgpio->lock); 554 spin_lock_init(&plgpio->lock);
565 555
566 plgpio->irq_base = -1;
567 plgpio->chip.base = -1; 556 plgpio->chip.base = -1;
568 plgpio->chip.request = plgpio_request; 557 plgpio->chip.request = plgpio_request;
569 plgpio->chip.free = plgpio_free; 558 plgpio->chip.free = plgpio_free;
@@ -571,10 +560,10 @@ static int plgpio_probe(struct platform_device *pdev)
571 plgpio->chip.direction_output = plgpio_direction_output; 560 plgpio->chip.direction_output = plgpio_direction_output;
572 plgpio->chip.get = plgpio_get_value; 561 plgpio->chip.get = plgpio_get_value;
573 plgpio->chip.set = plgpio_set_value; 562 plgpio->chip.set = plgpio_set_value;
574 plgpio->chip.to_irq = plgpio_to_irq;
575 plgpio->chip.label = dev_name(&pdev->dev); 563 plgpio->chip.label = dev_name(&pdev->dev);
576 plgpio->chip.dev = &pdev->dev; 564 plgpio->chip.dev = &pdev->dev;
577 plgpio->chip.owner = THIS_MODULE; 565 plgpio->chip.owner = THIS_MODULE;
566 plgpio->chip.of_node = pdev->dev.of_node;
578 567
579 if (!IS_ERR(plgpio->clk)) { 568 if (!IS_ERR(plgpio->clk)) {
580 ret = clk_prepare(plgpio->clk); 569 ret = clk_prepare(plgpio->clk);
@@ -592,43 +581,32 @@ static int plgpio_probe(struct platform_device *pdev)
592 581
593 irq = platform_get_irq(pdev, 0); 582 irq = platform_get_irq(pdev, 0);
594 if (irq < 0) { 583 if (irq < 0) {
595 dev_info(&pdev->dev, "irqs not supported\n"); 584 dev_info(&pdev->dev, "PLGPIO registered without IRQs\n");
596 return 0;
597 }
598
599 plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0);
600 if (IS_ERR_VALUE(plgpio->irq_base)) {
601 /* we would not support irq for gpio */
602 dev_warn(&pdev->dev, "couldn't allocate irq base\n");
603 return 0; 585 return 0;
604 } 586 }
605 587
606 plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio, 588 ret = gpiochip_irqchip_add(&plgpio->chip,
607 plgpio->irq_base, 0, &irq_domain_simple_ops, NULL); 589 &plgpio_irqchip,
608 if (WARN_ON(!plgpio->irq_domain)) { 590 0,
609 dev_err(&pdev->dev, "irq domain init failed\n"); 591 handle_simple_irq,
610 irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio); 592 IRQ_TYPE_NONE);
611 ret = -ENXIO; 593 if (ret) {
594 dev_err(&pdev->dev, "failed to add irqchip to gpiochip\n");
612 goto remove_gpiochip; 595 goto remove_gpiochip;
613 } 596 }
614 597
615 irq_set_chained_handler(irq, plgpio_irq_handler); 598 gpiochip_set_chained_irqchip(&plgpio->chip,
616 for (i = 0; i < plgpio->chip.ngpio; i++) { 599 &plgpio_irqchip,
617 irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip, 600 irq,
618 handle_simple_irq); 601 plgpio_irq_handler);
619 set_irq_flags(i + plgpio->irq_base, IRQF_VALID);
620 irq_set_chip_data(i + plgpio->irq_base, plgpio);
621 }
622 602
623 irq_set_handler_data(irq, plgpio);
624 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n"); 603 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
625 604
626 return 0; 605 return 0;
627 606
628remove_gpiochip: 607remove_gpiochip:
629 dev_info(&pdev->dev, "Remove gpiochip\n"); 608 dev_info(&pdev->dev, "Remove gpiochip\n");
630 if (gpiochip_remove(&plgpio->chip)) 609 gpiochip_remove(&plgpio->chip);
631 dev_err(&pdev->dev, "unable to remove gpiochip\n");
632unprepare_clk: 610unprepare_clk:
633 if (!IS_ERR(plgpio->clk)) 611 if (!IS_ERR(plgpio->clk))
634 clk_unprepare(plgpio->clk); 612 clk_unprepare(plgpio->clk);
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index 58bf6867aa17..f72cc4e192bd 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -274,12 +274,6 @@ static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
274 return spear_pinctrl_endisable(pctldev, function, group, true); 274 return spear_pinctrl_endisable(pctldev, function, group, true);
275} 275}
276 276
277static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
278 unsigned function, unsigned group)
279{
280 spear_pinctrl_endisable(pctldev, function, group, false);
281}
282
283/* gpio with pinmux */ 277/* gpio with pinmux */
284static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx, 278static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,
285 unsigned pin) 279 unsigned pin)
@@ -345,7 +339,6 @@ static const struct pinmux_ops spear_pinmux_ops = {
345 .get_function_name = spear_pinctrl_get_func_name, 339 .get_function_name = spear_pinctrl_get_func_name,
346 .get_function_groups = spear_pinctrl_get_func_groups, 340 .get_function_groups = spear_pinctrl_get_func_groups,
347 .enable = spear_pinctrl_enable, 341 .enable = spear_pinctrl_enable,
348 .disable = spear_pinctrl_disable,
349 .gpio_request_enable = gpio_request_enable, 342 .gpio_request_enable = gpio_request_enable,
350 .gpio_disable_free = gpio_disable_free, 343 .gpio_disable_free = gpio_disable_free,
351}; 344};
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 73e0a305ea13..a5e10f777ed2 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -1,36 +1,42 @@
1if ARCH_SUNXI 1if ARCH_SUNXI
2 2
3config PINCTRL_SUNXI
4 bool
5
6config PINCTRL_SUNXI_COMMON 3config PINCTRL_SUNXI_COMMON
7 bool 4 bool
8 select PINMUX 5 select PINMUX
9 select GENERIC_PINCONF 6 select GENERIC_PINCONF
10 7
11config PINCTRL_SUN4I_A10 8config PINCTRL_SUN4I_A10
12 def_bool PINCTRL_SUNXI || MACH_SUN4I 9 def_bool MACH_SUN4I
13 select PINCTRL_SUNXI_COMMON 10 select PINCTRL_SUNXI_COMMON
14 11
15config PINCTRL_SUN5I_A10S 12config PINCTRL_SUN5I_A10S
16 def_bool PINCTRL_SUNXI || MACH_SUN5I 13 def_bool MACH_SUN5I
17 select PINCTRL_SUNXI_COMMON 14 select PINCTRL_SUNXI_COMMON
18 15
19config PINCTRL_SUN5I_A13 16config PINCTRL_SUN5I_A13
20 def_bool PINCTRL_SUNXI || MACH_SUN5I 17 def_bool MACH_SUN5I
21 select PINCTRL_SUNXI_COMMON 18 select PINCTRL_SUNXI_COMMON
22 19
23config PINCTRL_SUN6I_A31 20config PINCTRL_SUN6I_A31
24 def_bool PINCTRL_SUNXI || MACH_SUN6I 21 def_bool MACH_SUN6I
25 select PINCTRL_SUNXI_COMMON 22 select PINCTRL_SUNXI_COMMON
26 23
27config PINCTRL_SUN6I_A31_R 24config PINCTRL_SUN6I_A31_R
28 def_bool PINCTRL_SUNXI || MACH_SUN6I 25 def_bool MACH_SUN6I
29 depends on RESET_CONTROLLER 26 depends on RESET_CONTROLLER
30 select PINCTRL_SUNXI_COMMON 27 select PINCTRL_SUNXI_COMMON
31 28
32config PINCTRL_SUN7I_A20 29config PINCTRL_SUN7I_A20
33 def_bool PINCTRL_SUNXI || MACH_SUN7I 30 def_bool MACH_SUN7I
31 select PINCTRL_SUNXI_COMMON
32
33config PINCTRL_SUN8I_A23
34 def_bool MACH_SUN8I
35 select PINCTRL_SUNXI_COMMON
36
37config PINCTRL_SUN8I_A23_R
38 def_bool MACH_SUN8I
39 depends on RESET_CONTROLLER
34 select PINCTRL_SUNXI_COMMON 40 select PINCTRL_SUNXI_COMMON
35 41
36endif 42endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 0f4461cbe11d..e797efb02901 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o 8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o 9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o 10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
11obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
12obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index fa1ff7c7e357..86b608bedca6 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -1010,6 +1010,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
1010static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 1010static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1011 .pins = sun4i_a10_pins, 1011 .pins = sun4i_a10_pins,
1012 .npins = ARRAY_SIZE(sun4i_a10_pins), 1012 .npins = ARRAY_SIZE(sun4i_a10_pins),
1013 .irq_banks = 1,
1013}; 1014};
1014 1015
1015static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) 1016static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
index 164d743f526c..2fa7430cabaf 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
@@ -661,6 +661,7 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = { 661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
662 .pins = sun5i_a10s_pins, 662 .pins = sun5i_a10s_pins,
663 .npins = ARRAY_SIZE(sun5i_a10s_pins), 663 .npins = ARRAY_SIZE(sun5i_a10s_pins),
664 .irq_banks = 1,
664}; 665};
665 666
666static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev) 667static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
index 1188a2b7b988..e47c33dbae3a 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
@@ -330,15 +330,12 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
330 /* Hole */ 330 /* Hole */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
332 SUNXI_FUNCTION(0x0, "gpio_in"), 332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ 333 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
335 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 334 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
336 SUNXI_FUNCTION(0x0, "gpio_in"), 335 SUNXI_FUNCTION(0x0, "gpio_in"),
337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ 336 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 337 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
340 SUNXI_FUNCTION(0x0, "gpio_in"), 338 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ 339 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 340 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
344 SUNXI_FUNCTION(0x0, "gpio_in"), 341 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -382,6 +379,7 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
382static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { 379static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
383 .pins = sun5i_a13_pins, 380 .pins = sun5i_a13_pins,
384 .npins = ARRAY_SIZE(sun5i_a13_pins), 381 .npins = ARRAY_SIZE(sun5i_a13_pins),
382 .irq_banks = 1,
385}; 383};
386 384
387static int sun5i_a13_pinctrl_probe(struct platform_device *pdev) 385static int sun5i_a13_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index 8fcba48e0a42..9a2517b65113 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -93,6 +93,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
93 .pins = sun6i_a31_r_pins, 93 .pins = sun6i_a31_r_pins,
94 .npins = ARRAY_SIZE(sun6i_a31_r_pins), 94 .npins = ARRAY_SIZE(sun6i_a31_r_pins),
95 .pin_base = PL_BASE, 95 .pin_base = PL_BASE,
96 .irq_banks = 2,
96}; 97};
97 98
98static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) 99static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index 8dea5856458b..a2b4b85c5ad5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -24,208 +24,244 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
24 SUNXI_FUNCTION(0x1, "gpio_out"), 24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ 25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */ 26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
27 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 27 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"), 30 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"), 31 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ 32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
32 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */ 33 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
33 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 34 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
35 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"), 37 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"), 38 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ 39 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
38 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */ 40 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
39 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 41 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"), 44 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"), 45 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ 46 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
44 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */ 47 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
45 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 48 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"), 51 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"), 52 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ 53 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
50 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */ 54 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
51 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 55 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
56 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 57 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"), 58 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"), 59 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ 60 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
56 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */ 61 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
57 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 62 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
63 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"), 65 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"), 66 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ 67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
62 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */ 68 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
63 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 69 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
70 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"), 72 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"), 73 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ 74 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
68 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */ 75 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
69 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 76 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"), 79 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"), 80 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ 81 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
74 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */ 82 SUNXI_FUNCTION(0x3, "lcd1"), /* D8 */
83 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"), 85 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"), 86 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ 87 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
79 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */ 88 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
80 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ 89 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
81 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */ 90 SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
83 SUNXI_FUNCTION(0x0, "gpio_in"), 93 SUNXI_FUNCTION(0x0, "gpio_in"),
84 SUNXI_FUNCTION(0x1, "gpio_out"), 94 SUNXI_FUNCTION(0x1, "gpio_out"),
85 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ 95 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
86 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */ 96 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
87 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ 97 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
88 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */ 98 SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
99 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 100 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
90 SUNXI_FUNCTION(0x0, "gpio_in"), 101 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"), 102 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ 103 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
93 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */ 104 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
94 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ 105 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
95 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */ 106 SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
107 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 108 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
97 SUNXI_FUNCTION(0x0, "gpio_in"), 109 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"), 110 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ 111 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
100 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */ 112 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
101 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ 113 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
102 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */ 114 SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
115 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), 116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
104 SUNXI_FUNCTION(0x0, "gpio_in"), 117 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out"), 118 SUNXI_FUNCTION(0x1, "gpio_out"),
106 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ 119 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
107 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */ 120 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
108 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ 121 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
109 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */ 122 SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
123 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), 124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
111 SUNXI_FUNCTION(0x0, "gpio_in"), 125 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"), 126 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ 127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
114 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */ 128 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
115 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ 129 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
116 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */ 130 SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
131 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), 132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
118 SUNXI_FUNCTION(0x0, "gpio_in"), 133 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"), 134 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ 135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
121 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */ 136 SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
137 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), 138 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
123 SUNXI_FUNCTION(0x0, "gpio_in"), 139 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"), 140 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ 141 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
126 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */ 142 SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
143 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), 144 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
128 SUNXI_FUNCTION(0x0, "gpio_in"), 145 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"), 146 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ 147 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
131 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */ 148 SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
149 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), 150 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
133 SUNXI_FUNCTION(0x0, "gpio_in"), 151 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"), 152 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ 153 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
136 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */ 154 SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
155 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), 156 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
138 SUNXI_FUNCTION(0x0, "gpio_in"), 157 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"), 158 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ 159 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
141 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */ 160 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
142 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */ 161 SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
162 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), 163 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
144 SUNXI_FUNCTION(0x0, "gpio_in"), 164 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"), 165 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ 166 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
147 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */ 167 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
148 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */ 168 SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
169 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), 170 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
150 SUNXI_FUNCTION(0x0, "gpio_in"), 171 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"), 172 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ 173 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
153 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */ 174 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
154 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */ 175 SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
176 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22), 177 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
156 SUNXI_FUNCTION(0x0, "gpio_in"), 178 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"), 179 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ 180 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
159 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */ 181 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
160 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */ 182 SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
183 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
161 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23), 184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
162 SUNXI_FUNCTION(0x0, "gpio_in"), 185 SUNXI_FUNCTION(0x0, "gpio_in"),
163 SUNXI_FUNCTION(0x1, "gpio_out"), 186 SUNXI_FUNCTION(0x1, "gpio_out"),
164 SUNXI_FUNCTION(0x2, "gmac"), /* COL */ 187 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
165 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */ 188 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
166 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */ 189 SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
190 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24), 191 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
168 SUNXI_FUNCTION(0x0, "gpio_in"), 192 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"), 193 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ 194 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
171 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */ 195 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
172 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */ 196 SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
197 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25), 198 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
174 SUNXI_FUNCTION(0x0, "gpio_in"), 199 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"), 200 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ 201 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
177 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */ 202 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
178 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */ 203 SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
204 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26), 205 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
180 SUNXI_FUNCTION(0x0, "gpio_in"), 206 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"), 207 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ 208 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
183 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */ 209 SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
210 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), 211 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
185 SUNXI_FUNCTION(0x0, "gpio_in"), 212 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"), 213 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ 214 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
188 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */ 215 SUNXI_FUNCTION(0x3, "lcd1"), /* VSYNC */
216 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
189 /* Hole */ 217 /* Hole */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 218 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
191 SUNXI_FUNCTION(0x0, "gpio_in"), 219 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"), 220 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ 221 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
194 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 222 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
195 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */ 223 SUNXI_FUNCTION(0x4, "csi"), /* MCLK1 */
224 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
197 SUNXI_FUNCTION(0x0, "gpio_in"), 226 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"), 227 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */ 228 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
229 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
201 SUNXI_FUNCTION(0x0, "gpio_in"), 231 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"), 232 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */ 233 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
234 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 235 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
205 SUNXI_FUNCTION(0x0, "gpio_in"), 236 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"), 237 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */ 238 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
239 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 240 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
209 SUNXI_FUNCTION(0x0, "gpio_in"), 241 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"), 242 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ 243 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
212 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ 244 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
245 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
214 SUNXI_FUNCTION(0x0, "gpio_in"), 247 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"), 248 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ 249 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
217 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 250 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
218 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */ 251 SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
252 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
219 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 253 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
220 SUNXI_FUNCTION(0x0, "gpio_in"), 254 SUNXI_FUNCTION(0x0, "gpio_in"),
221 SUNXI_FUNCTION(0x1, "gpio_out"), 255 SUNXI_FUNCTION(0x1, "gpio_out"),
222 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ 256 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
223 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 257 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
224 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */ 258 SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
259 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 260 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
226 SUNXI_FUNCTION(0x0, "gpio_in"), 261 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"), 262 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */ 263 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
264 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
229 /* Hole */ 265 /* Hole */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 266 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
231 SUNXI_FUNCTION(0x0, "gpio_in"), 267 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -510,86 +546,103 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
510 SUNXI_FUNCTION(0x0, "gpio_in"), 546 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"), 547 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 548 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
513 SUNXI_FUNCTION(0x3, "ts")), /* CLK */ 549 SUNXI_FUNCTION(0x3, "ts"), /* CLK */
550 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 551 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
515 SUNXI_FUNCTION(0x0, "gpio_in"), 552 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"), 553 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 554 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
518 SUNXI_FUNCTION(0x3, "ts")), /* ERR */ 555 SUNXI_FUNCTION(0x3, "ts"), /* ERR */
556 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
520 SUNXI_FUNCTION(0x0, "gpio_in"), 558 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"), 559 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 560 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
523 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ 561 SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
562 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 563 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
525 SUNXI_FUNCTION(0x0, "gpio_in"), 564 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"), 565 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 566 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
528 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ 567 SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
568 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
530 SUNXI_FUNCTION(0x0, "gpio_in"), 570 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"), 571 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 572 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
533 SUNXI_FUNCTION(0x3, "uart5")), /* TX */ 573 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
574 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 575 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
535 SUNXI_FUNCTION(0x0, "gpio_in"), 576 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"), 577 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 578 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
538 SUNXI_FUNCTION(0x3, "uart5")), /* RX */ 579 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
580 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 581 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
540 SUNXI_FUNCTION(0x0, "gpio_in"), 582 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"), 583 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 584 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
543 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */ 585 SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
586 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 587 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
545 SUNXI_FUNCTION(0x0, "gpio_in"), 588 SUNXI_FUNCTION(0x0, "gpio_in"),
546 SUNXI_FUNCTION(0x1, "gpio_out"), 589 SUNXI_FUNCTION(0x1, "gpio_out"),
547 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 590 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
548 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */ 591 SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
592 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
549 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 593 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
550 SUNXI_FUNCTION(0x0, "gpio_in"), 594 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out"), 595 SUNXI_FUNCTION(0x1, "gpio_out"),
552 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 596 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
553 SUNXI_FUNCTION(0x3, "ts")), /* D0 */ 597 SUNXI_FUNCTION(0x3, "ts"), /* D0 */
598 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
554 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 599 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
555 SUNXI_FUNCTION(0x0, "gpio_in"), 600 SUNXI_FUNCTION(0x0, "gpio_in"),
556 SUNXI_FUNCTION(0x1, "gpio_out"), 601 SUNXI_FUNCTION(0x1, "gpio_out"),
557 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 602 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
558 SUNXI_FUNCTION(0x3, "ts")), /* D1 */ 603 SUNXI_FUNCTION(0x3, "ts"), /* D1 */
604 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
559 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 605 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
560 SUNXI_FUNCTION(0x0, "gpio_in"), 606 SUNXI_FUNCTION(0x0, "gpio_in"),
561 SUNXI_FUNCTION(0x1, "gpio_out"), 607 SUNXI_FUNCTION(0x1, "gpio_out"),
562 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 608 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
563 SUNXI_FUNCTION(0x3, "ts")), /* D2 */ 609 SUNXI_FUNCTION(0x3, "ts"), /* D2 */
610 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 611 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
565 SUNXI_FUNCTION(0x0, "gpio_in"), 612 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"), 613 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 614 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
568 SUNXI_FUNCTION(0x3, "ts")), /* D3 */ 615 SUNXI_FUNCTION(0x3, "ts"), /* D3 */
616 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 617 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
570 SUNXI_FUNCTION(0x0, "gpio_in"), 618 SUNXI_FUNCTION(0x0, "gpio_in"),
571 SUNXI_FUNCTION(0x1, "gpio_out"), 619 SUNXI_FUNCTION(0x1, "gpio_out"),
572 SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 620 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
573 SUNXI_FUNCTION(0x3, "ts")), /* D4 */ 621 SUNXI_FUNCTION(0x3, "ts"), /* D4 */
622 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 623 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
575 SUNXI_FUNCTION(0x0, "gpio_in"), 624 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"), 625 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 626 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
578 SUNXI_FUNCTION(0x3, "ts")), /* D5 */ 627 SUNXI_FUNCTION(0x3, "ts"), /* D5 */
628 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 629 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
580 SUNXI_FUNCTION(0x0, "gpio_in"), 630 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"), 631 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 632 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
583 SUNXI_FUNCTION(0x3, "ts")), /* D6 */ 633 SUNXI_FUNCTION(0x3, "ts"), /* D6 */
634 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
584 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 635 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
585 SUNXI_FUNCTION(0x0, "gpio_in"), 636 SUNXI_FUNCTION(0x0, "gpio_in"),
586 SUNXI_FUNCTION(0x1, "gpio_out"), 637 SUNXI_FUNCTION(0x1, "gpio_out"),
587 SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 638 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
588 SUNXI_FUNCTION(0x3, "ts")), /* D7 */ 639 SUNXI_FUNCTION(0x3, "ts"), /* D7 */
640 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
589 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 641 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
590 SUNXI_FUNCTION(0x0, "gpio_in"), 642 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out"), 643 SUNXI_FUNCTION(0x1, "gpio_out"),
592 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */ 644 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
645 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
593 /* Hole */ 646 /* Hole */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 647 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
595 SUNXI_FUNCTION(0x0, "gpio_in"), 648 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -625,86 +678,105 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
625 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 678 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
626 SUNXI_FUNCTION(0x0, "gpio_in"), 679 SUNXI_FUNCTION(0x0, "gpio_in"),
627 SUNXI_FUNCTION(0x1, "gpio_out"), 680 SUNXI_FUNCTION(0x1, "gpio_out"),
628 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */ 681 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
682 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
629 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 683 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
630 SUNXI_FUNCTION(0x0, "gpio_in"), 684 SUNXI_FUNCTION(0x0, "gpio_in"),
631 SUNXI_FUNCTION(0x1, "gpio_out"), 685 SUNXI_FUNCTION(0x1, "gpio_out"),
632 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */ 686 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
687 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 688 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
634 SUNXI_FUNCTION(0x0, "gpio_in"), 689 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"), 690 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */ 691 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
692 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
637 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 693 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
638 SUNXI_FUNCTION(0x0, "gpio_in"), 694 SUNXI_FUNCTION(0x0, "gpio_in"),
639 SUNXI_FUNCTION(0x1, "gpio_out"), 695 SUNXI_FUNCTION(0x1, "gpio_out"),
640 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */ 696 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
697 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
641 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 698 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
642 SUNXI_FUNCTION(0x0, "gpio_in"), 699 SUNXI_FUNCTION(0x0, "gpio_in"),
643 SUNXI_FUNCTION(0x1, "gpio_out"), 700 SUNXI_FUNCTION(0x1, "gpio_out"),
644 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */ 701 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
702 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
645 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 703 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
646 SUNXI_FUNCTION(0x0, "gpio_in"), 704 SUNXI_FUNCTION(0x0, "gpio_in"),
647 SUNXI_FUNCTION(0x1, "gpio_out"), 705 SUNXI_FUNCTION(0x1, "gpio_out"),
648 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */ 706 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
707 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 708 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
650 SUNXI_FUNCTION(0x0, "gpio_in"), 709 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"), 710 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "uart2")), /* TX */ 711 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
712 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
653 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 713 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
654 SUNXI_FUNCTION(0x0, "gpio_in"), 714 SUNXI_FUNCTION(0x0, "gpio_in"),
655 SUNXI_FUNCTION(0x1, "gpio_out"), 715 SUNXI_FUNCTION(0x1, "gpio_out"),
656 SUNXI_FUNCTION(0x2, "uart2")), /* RX */ 716 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
717 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 718 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
658 SUNXI_FUNCTION(0x0, "gpio_in"), 719 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"), 720 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */ 721 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
722 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 723 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
662 SUNXI_FUNCTION(0x0, "gpio_in"), 724 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"), 725 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */ 726 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
727 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 728 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
666 SUNXI_FUNCTION(0x0, "gpio_in"), 729 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"), 730 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ 731 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
669 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */ 732 SUNXI_FUNCTION(0x3, "usb"), /* DP3 */
733 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
670 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 734 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
671 SUNXI_FUNCTION(0x0, "gpio_in"), 735 SUNXI_FUNCTION(0x0, "gpio_in"),
672 SUNXI_FUNCTION(0x1, "gpio_out"), 736 SUNXI_FUNCTION(0x1, "gpio_out"),
673 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ 737 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
674 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */ 738 SUNXI_FUNCTION(0x3, "usb"), /* DM3 */
739 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 740 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
676 SUNXI_FUNCTION(0x0, "gpio_in"), 741 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out"), 742 SUNXI_FUNCTION(0x1, "gpio_out"),
678 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 743 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
679 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */ 744 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
745 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
680 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 746 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
681 SUNXI_FUNCTION(0x0, "gpio_in"), 747 SUNXI_FUNCTION(0x0, "gpio_in"),
682 SUNXI_FUNCTION(0x1, "gpio_out"), 748 SUNXI_FUNCTION(0x1, "gpio_out"),
683 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 749 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
684 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */ 750 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
751 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
685 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), 752 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
686 SUNXI_FUNCTION(0x0, "gpio_in"), 753 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out"), 754 SUNXI_FUNCTION(0x1, "gpio_out"),
688 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 755 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
689 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */ 756 SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
757 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
690 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), 758 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
691 SUNXI_FUNCTION(0x0, "gpio_in"), 759 SUNXI_FUNCTION(0x0, "gpio_in"),
692 SUNXI_FUNCTION(0x1, "gpio_out"), 760 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 761 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
694 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */ 762 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
763 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
695 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), 764 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
696 SUNXI_FUNCTION(0x0, "gpio_in"), 765 SUNXI_FUNCTION(0x0, "gpio_in"),
697 SUNXI_FUNCTION(0x1, "gpio_out"), 766 SUNXI_FUNCTION(0x1, "gpio_out"),
698 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 767 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
699 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */ 768 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
769 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
700 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), 770 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
701 SUNXI_FUNCTION(0x0, "gpio_in"), 771 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out"), 772 SUNXI_FUNCTION(0x1, "gpio_out"),
703 SUNXI_FUNCTION(0x2, "uart4")), /* TX */ 773 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
774 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), 775 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
705 SUNXI_FUNCTION(0x0, "gpio_in"), 776 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out"), 777 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "uart4")), /* RX */ 778 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
779 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
708 /* Hole */ 780 /* Hole */
709 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), 781 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
710 SUNXI_FUNCTION(0x0, "gpio_in"), 782 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -836,6 +908,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
836static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { 908static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
837 .pins = sun6i_a31_pins, 909 .pins = sun6i_a31_pins,
838 .npins = ARRAY_SIZE(sun6i_a31_pins), 910 .npins = ARRAY_SIZE(sun6i_a31_pins),
911 .irq_banks = 4,
839}; 912};
840 913
841static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) 914static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index d8577ce5f1a4..dac99e02bfdb 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -1036,6 +1036,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = { 1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
1037 .pins = sun7i_a20_pins, 1037 .pins = sun7i_a20_pins,
1038 .npins = ARRAY_SIZE(sun7i_a20_pins), 1038 .npins = ARRAY_SIZE(sun7i_a20_pins),
1039 .irq_banks = 1,
1039}; 1040};
1040 1041
1041static int sun7i_a20_pinctrl_probe(struct platform_device *pdev) 1042static int sun7i_a20_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
new file mode 100644
index 000000000000..90f3b3a7c51e
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
@@ -0,0 +1,142 @@
1/*
2 * Allwinner A23 SoCs special pins pinctrl driver.
3 *
4 * Copyright (C) 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
6 *
7 * Copyright (C) 2014 Boris Brezillon
8 * Boris Brezillon <boris.brezillon@free-electrons.com>
9 *
10 * Copyright (C) 2014 Maxime Ripard
11 * Maxime Ripard <maxime.ripard@free-electrons.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/reset.h>
24
25#include "pinctrl-sunxi.h"
26
27static const struct sunxi_desc_pin sun8i_a23_r_pins[] = {
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
32 SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
33 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
38 SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
39 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
44 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PL_EINT2 */
45 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
46 SUNXI_FUNCTION(0x0, "gpio_in"),
47 SUNXI_FUNCTION(0x1, "gpio_out"),
48 SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
49 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PL_EINT3 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */
54 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PL_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */
59 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PL_EINT5 */
60 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
61 SUNXI_FUNCTION(0x0, "gpio_in"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */
64 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PL_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */
69 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PL_EINT7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
74 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 8)), /* PL_EINT8 */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
79 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 9)), /* PL_EINT9 */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "s_pwm"),
84 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 10)), /* PL_EINT10 */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 11)), /* PL_EINT11 */
89};
90
91static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {
92 .pins = sun8i_a23_r_pins,
93 .npins = ARRAY_SIZE(sun8i_a23_r_pins),
94 .pin_base = PL_BASE,
95 .irq_banks = 1,
96};
97
98static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
99{
100 struct reset_control *rstc;
101 int ret;
102
103 rstc = devm_reset_control_get(&pdev->dev, NULL);
104 if (IS_ERR(rstc)) {
105 dev_err(&pdev->dev, "Reset controller missing\n");
106 return PTR_ERR(rstc);
107 }
108
109 ret = reset_control_deassert(rstc);
110 if (ret)
111 return ret;
112
113 ret = sunxi_pinctrl_init(pdev,
114 &sun8i_a23_r_pinctrl_data);
115
116 if (ret)
117 reset_control_assert(rstc);
118
119 return ret;
120}
121
122static struct of_device_id sun8i_a23_r_pinctrl_match[] = {
123 { .compatible = "allwinner,sun8i-a23-r-pinctrl", },
124 {}
125};
126MODULE_DEVICE_TABLE(of, sun8i_a23_r_pinctrl_match);
127
128static struct platform_driver sun8i_a23_r_pinctrl_driver = {
129 .probe = sun8i_a23_r_pinctrl_probe,
130 .driver = {
131 .name = "sun8i-a23-r-pinctrl",
132 .owner = THIS_MODULE,
133 .of_match_table = sun8i_a23_r_pinctrl_match,
134 },
135};
136module_platform_driver(sun8i_a23_r_pinctrl_driver);
137
138MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
139MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
140MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
141MODULE_DESCRIPTION("Allwinner A23 R_PIO pinctrl driver");
142MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
new file mode 100644
index 000000000000..ac71e8c5901b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
@@ -0,0 +1,593 @@
1/*
2 * Allwinner A23 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Chen-Yu Tsai
5 *
6 * Chen-Yu Tsai <wens@csie.org>
7 *
8 * Copyright (C) 2014 Maxime Ripard
9 *
10 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-sunxi.h"
24
25static const struct sunxi_desc_pin sun8i_a23_pins[] = {
26 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
27 SUNXI_FUNCTION(0x0, "gpio_in"),
28 SUNXI_FUNCTION(0x1, "gpio_out"),
29 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
30 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
31 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PA_EINT0 */
32 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
33 SUNXI_FUNCTION(0x0, "gpio_in"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
35 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
36 SUNXI_FUNCTION(0x3, "jtag"), /* CKO */
37 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PA_EINT1 */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
39 SUNXI_FUNCTION(0x0, "gpio_in"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
41 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
42 SUNXI_FUNCTION(0x3, "jtag"), /* DOO */
43 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PA_EINT2 */
44 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
45 SUNXI_FUNCTION(0x0, "gpio_in"),
46 SUNXI_FUNCTION(0x1, "gpio_out"),
47 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
48 SUNXI_FUNCTION(0x3, "jtag"), /* DIO */
49 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PA_EINT3 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
54 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PA_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
59 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PA_EINT5 */
60 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
61 SUNXI_FUNCTION(0x0, "gpio_in"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
64 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PA_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
69 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PA_EINT7 */
70 /* Hole */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
75 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PB_EINT0 */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
80 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PB_EINT1 */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
85 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PB_EINT2 */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
90 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PB_EINT3 */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
95 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PB_EINT4 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
97 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
100 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PB_EINT5 */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
105 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PB_EINT6 */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
110 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PB_EINT7 */
111 /* Hole */
112 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
113 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out"),
115 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
116 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
121 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
123 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
126 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
131 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
140 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
141 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
142 SUNXI_FUNCTION(0x0, "gpio_in"),
143 SUNXI_FUNCTION(0x1, "gpio_out"),
144 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
145 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
154 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
159 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
164 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
165 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
166 SUNXI_FUNCTION(0x0, "gpio_in"),
167 SUNXI_FUNCTION(0x1, "gpio_out"),
168 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
169 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
170 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
171 SUNXI_FUNCTION(0x0, "gpio_in"),
172 SUNXI_FUNCTION(0x1, "gpio_out"),
173 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
174 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
179 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
184 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
189 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
194 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
203 /* Hole */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
216 SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
221 SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
226 SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
231 SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
232 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
233 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out"),
235 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
236 SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
241 SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
246 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
251 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
252 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
253 SUNXI_FUNCTION(0x0, "gpio_in"),
254 SUNXI_FUNCTION(0x1, "gpio_out"),
255 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
256 SUNXI_FUNCTION(0x3, "uart1")), /* TX */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
261 SUNXI_FUNCTION(0x3, "uart1")), /* RX */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
266 SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
267 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
271 SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
276 SUNXI_FUNCTION(0x3, "i2s1")), /* SYNC */
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
281 SUNXI_FUNCTION(0x3, "i2s1")), /* CLK */
282 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
283 SUNXI_FUNCTION(0x0, "gpio_in"),
284 SUNXI_FUNCTION(0x1, "gpio_out"),
285 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
286 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
291 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
296 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
301 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
303 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out"),
305 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
306 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
307 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
308 SUNXI_FUNCTION(0x0, "gpio_in"),
309 SUNXI_FUNCTION(0x1, "gpio_out"),
310 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
311 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
316 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
321 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
326 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
327 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
328 SUNXI_FUNCTION(0x0, "gpio_in"),
329 SUNXI_FUNCTION(0x1, "gpio_out"),
330 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
331 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
336 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
341 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
342 /* Hole */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
344 SUNXI_FUNCTION(0x0, "gpio_in"),
345 SUNXI_FUNCTION(0x1, "gpio_out"),
346 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out"),
354 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
359 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
360 SUNXI_FUNCTION(0x0, "gpio_in"),
361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "csi")), /* D2 */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "csi")), /* D3 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "csi")), /* D4 */
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "csi")), /* D5 */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "csi")), /* D6 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "csi")), /* D7 */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out"),
394 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
395 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
396 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
397 SUNXI_FUNCTION(0x0, "gpio_in"),
398 SUNXI_FUNCTION(0x1, "gpio_out"),
399 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
400 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
401 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
402 SUNXI_FUNCTION(0x0, "gpio_in"),
403 SUNXI_FUNCTION(0x1, "gpio_out")),
404 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
405 SUNXI_FUNCTION(0x0, "gpio_in"),
406 SUNXI_FUNCTION(0x1, "gpio_out")),
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out")),
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out")),
413 /* Hole */
414 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
415 SUNXI_FUNCTION(0x0, "gpio_in"),
416 SUNXI_FUNCTION(0x1, "gpio_out"),
417 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
418 SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
419 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
420 SUNXI_FUNCTION(0x0, "gpio_in"),
421 SUNXI_FUNCTION(0x1, "gpio_out"),
422 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
423 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
424 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
425 SUNXI_FUNCTION(0x0, "gpio_in"),
426 SUNXI_FUNCTION(0x1, "gpio_out"),
427 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
428 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
429 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
430 SUNXI_FUNCTION(0x0, "gpio_in"),
431 SUNXI_FUNCTION(0x1, "gpio_out"),
432 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
433 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
434 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
435 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out"),
437 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
438 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
439 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
440 SUNXI_FUNCTION(0x0, "gpio_in"),
441 SUNXI_FUNCTION(0x1, "gpio_out"),
442 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
443 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
444 /* Hole */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
449 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 0)), /* PG_EINT0 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
454 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 1)), /* PG_EINT1 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
459 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 2)), /* PG_EINT2 */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
464 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 3)), /* PG_EINT3 */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
469 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 4)), /* PG_EINT4 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
474 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 5)), /* PG_EINT5 */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
479 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 6)), /* PG_EINT6 */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
484 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 7)), /* PG_EINT7 */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
489 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)), /* PG_EINT8 */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
494 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)), /* PG_EINT9 */
495 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
496 SUNXI_FUNCTION(0x0, "gpio_in"),
497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
499 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 10)), /* PG_EINT10 */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
504 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 11)), /* PG_EINT11 */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
509 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 12)), /* PG_EINT12 */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
514 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 13)), /* PG_EINT13 */
515 /* Hole */
516 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "pwm0")),
520 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
521 SUNXI_FUNCTION(0x0, "gpio_in"),
522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "pwm1")),
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
528 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
529 SUNXI_FUNCTION(0x0, "gpio_in"),
530 SUNXI_FUNCTION(0x1, "gpio_out"),
531 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
536 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
537 SUNXI_FUNCTION(0x0, "gpio_in"),
538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
541 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out"),
543 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
544 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
549 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
554 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
559 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
560};
561
562static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = {
563 .pins = sun8i_a23_pins,
564 .npins = ARRAY_SIZE(sun8i_a23_pins),
565 .irq_banks = 3,
566};
567
568static int sun8i_a23_pinctrl_probe(struct platform_device *pdev)
569{
570 return sunxi_pinctrl_init(pdev,
571 &sun8i_a23_pinctrl_data);
572}
573
574static struct of_device_id sun8i_a23_pinctrl_match[] = {
575 { .compatible = "allwinner,sun8i-a23-pinctrl", },
576 {}
577};
578MODULE_DEVICE_TABLE(of, sun8i_a23_pinctrl_match);
579
580static struct platform_driver sun8i_a23_pinctrl_driver = {
581 .probe = sun8i_a23_pinctrl_probe,
582 .driver = {
583 .name = "sun8i-a23-pinctrl",
584 .owner = THIS_MODULE,
585 .of_match_table = sun8i_a23_pinctrl_match,
586 },
587};
588module_platform_driver(sun8i_a23_pinctrl_driver);
589
590MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
591MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
592MODULE_DESCRIPTION("Allwinner A23 pinctrl driver");
593MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 5f38c7f67834..3df66e366c87 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -31,6 +31,9 @@
31#include "../core.h" 31#include "../core.h"
32#include "pinctrl-sunxi.h" 32#include "pinctrl-sunxi.h"
33 33
34static struct irq_chip sunxi_pinctrl_edge_irq_chip;
35static struct irq_chip sunxi_pinctrl_level_irq_chip;
36
34static struct sunxi_pinctrl_group * 37static struct sunxi_pinctrl_group *
35sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 38sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
36{ 39{
@@ -508,7 +511,7 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
508 base = PINS_PER_BANK * gpiospec->args[0]; 511 base = PINS_PER_BANK * gpiospec->args[0];
509 pin = base + gpiospec->args[1]; 512 pin = base + gpiospec->args[1];
510 513
511 if (pin > (gc->base + gc->ngpio)) 514 if (pin > gc->ngpio)
512 return -EINVAL; 515 return -EINVAL;
513 516
514 if (flags) 517 if (flags)
@@ -521,25 +524,61 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
521{ 524{
522 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 525 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
523 struct sunxi_desc_function *desc; 526 struct sunxi_desc_function *desc;
527 unsigned pinnum = pctl->desc->pin_base + offset;
528 unsigned irqnum;
524 529
525 if (offset >= chip->ngpio) 530 if (offset >= chip->ngpio)
526 return -ENXIO; 531 return -ENXIO;
527 532
528 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); 533 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
529 if (!desc) 534 if (!desc)
530 return -EINVAL; 535 return -EINVAL;
531 536
537 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
538
532 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 539 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
533 chip->label, offset + chip->base, desc->irqnum); 540 chip->label, offset + chip->base, irqnum);
534 541
535 return irq_find_mapping(pctl->domain, desc->irqnum); 542 return irq_find_mapping(pctl->domain, irqnum);
536} 543}
537 544
545static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
546{
547 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
548 struct sunxi_desc_function *func;
549 int ret;
550
551 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
552 pctl->irq_array[d->hwirq], "irq");
553 if (!func)
554 return -EINVAL;
555
556 ret = gpio_lock_as_irq(pctl->chip,
557 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
558 if (ret) {
559 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
560 irqd_to_hwirq(d));
561 return ret;
562 }
563
564 /* Change muxing to INT mode */
565 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
538 566
539static int sunxi_pinctrl_irq_set_type(struct irq_data *d, 567 return 0;
540 unsigned int type) 568}
569
570static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
571{
572 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
573
574 gpio_unlock_as_irq(pctl->chip,
575 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
576}
577
578static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
541{ 579{
542 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 580 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
581 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
543 u32 reg = sunxi_irq_cfg_reg(d->hwirq); 582 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
544 u8 index = sunxi_irq_cfg_offset(d->hwirq); 583 u8 index = sunxi_irq_cfg_offset(d->hwirq);
545 unsigned long flags; 584 unsigned long flags;
@@ -566,6 +605,14 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
566 return -EINVAL; 605 return -EINVAL;
567 } 606 }
568 607
608 if (type & IRQ_TYPE_LEVEL_MASK) {
609 d->chip = &sunxi_pinctrl_level_irq_chip;
610 desc->handle_irq = handle_fasteoi_irq;
611 } else {
612 d->chip = &sunxi_pinctrl_edge_irq_chip;
613 desc->handle_irq = handle_edge_irq;
614 }
615
569 spin_lock_irqsave(&pctl->lock, flags); 616 spin_lock_irqsave(&pctl->lock, flags);
570 617
571 regval = readl(pctl->membase + reg); 618 regval = readl(pctl->membase + reg);
@@ -577,26 +624,14 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
577 return 0; 624 return 0;
578} 625}
579 626
580static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) 627static void sunxi_pinctrl_irq_ack(struct irq_data *d)
581{ 628{
582 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 629 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
583 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
584 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
585 u32 status_reg = sunxi_irq_status_reg(d->hwirq); 630 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
586 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 631 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
587 unsigned long flags;
588 u32 val;
589
590 spin_lock_irqsave(&pctl->lock, flags);
591
592 /* Mask the IRQ */
593 val = readl(pctl->membase + ctrl_reg);
594 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
595 632
596 /* Clear the IRQ */ 633 /* Clear the IRQ */
597 writel(1 << status_idx, pctl->membase + status_reg); 634 writel(1 << status_idx, pctl->membase + status_reg);
598
599 spin_unlock_irqrestore(&pctl->lock, flags);
600} 635}
601 636
602static void sunxi_pinctrl_irq_mask(struct irq_data *d) 637static void sunxi_pinctrl_irq_mask(struct irq_data *d)
@@ -619,19 +654,11 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
619static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 654static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
620{ 655{
621 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 656 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
622 struct sunxi_desc_function *func;
623 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 657 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
624 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 658 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
625 unsigned long flags; 659 unsigned long flags;
626 u32 val; 660 u32 val;
627 661
628 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
629 pctl->irq_array[d->hwirq],
630 "irq");
631
632 /* Change muxing to INT mode */
633 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
634
635 spin_lock_irqsave(&pctl->lock, flags); 662 spin_lock_irqsave(&pctl->lock, flags);
636 663
637 /* Unmask the IRQ */ 664 /* Unmask the IRQ */
@@ -641,28 +668,60 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
641 spin_unlock_irqrestore(&pctl->lock, flags); 668 spin_unlock_irqrestore(&pctl->lock, flags);
642} 669}
643 670
644static struct irq_chip sunxi_pinctrl_irq_chip = { 671static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
672{
673 sunxi_pinctrl_irq_ack(d);
674 sunxi_pinctrl_irq_unmask(d);
675}
676
677static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
678 .irq_ack = sunxi_pinctrl_irq_ack,
679 .irq_mask = sunxi_pinctrl_irq_mask,
680 .irq_unmask = sunxi_pinctrl_irq_unmask,
681 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
682 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
683 .irq_set_type = sunxi_pinctrl_irq_set_type,
684 .flags = IRQCHIP_SKIP_SET_WAKE,
685};
686
687static struct irq_chip sunxi_pinctrl_level_irq_chip = {
688 .irq_eoi = sunxi_pinctrl_irq_ack,
645 .irq_mask = sunxi_pinctrl_irq_mask, 689 .irq_mask = sunxi_pinctrl_irq_mask,
646 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
647 .irq_unmask = sunxi_pinctrl_irq_unmask, 690 .irq_unmask = sunxi_pinctrl_irq_unmask,
691 /* Define irq_enable / disable to avoid spurious irqs for drivers
692 * using these to suppress irqs while they clear the irq source */
693 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
694 .irq_disable = sunxi_pinctrl_irq_mask,
695 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
696 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
648 .irq_set_type = sunxi_pinctrl_irq_set_type, 697 .irq_set_type = sunxi_pinctrl_irq_set_type,
698 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
699 IRQCHIP_EOI_IF_HANDLED,
649}; 700};
650 701
651static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) 702static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
652{ 703{
653 struct irq_chip *chip = irq_get_chip(irq); 704 struct irq_chip *chip = irq_get_chip(irq);
654 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); 705 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
655 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); 706 unsigned long bank, reg, val;
707
708 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
709 if (irq == pctl->irq[bank])
710 break;
711
712 if (bank == pctl->desc->irq_banks)
713 return;
656 714
657 /* Clear all interrupts */ 715 reg = sunxi_irq_status_reg_from_bank(bank);
658 writel(reg, pctl->membase + IRQ_STATUS_REG); 716 val = readl(pctl->membase + reg);
659 717
660 if (reg) { 718 if (val) {
661 int irqoffset; 719 int irqoffset;
662 720
663 chained_irq_enter(chip, desc); 721 chained_irq_enter(chip, desc);
664 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) { 722 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
665 int pin_irq = irq_find_mapping(pctl->domain, irqoffset); 723 int pin_irq = irq_find_mapping(pctl->domain,
724 bank * IRQ_PER_BANK + irqoffset);
666 generic_handle_irq(pin_irq); 725 generic_handle_irq(pin_irq);
667 } 726 }
668 chained_irq_exit(chip, desc); 727 chained_irq_exit(chip, desc);
@@ -730,8 +789,11 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev)
730 789
731 while (func->name) { 790 while (func->name) {
732 /* Create interrupt mapping while we're at it */ 791 /* Create interrupt mapping while we're at it */
733 if (!strcmp(func->name, "irq")) 792 if (!strcmp(func->name, "irq")) {
734 pctl->irq_array[func->irqnum] = pin->pin.number; 793 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
794 pctl->irq_array[irqnum] = pin->pin.number;
795 }
796
735 sunxi_pinctrl_add_function(pctl, func->name); 797 sunxi_pinctrl_add_function(pctl, func->name);
736 func++; 798 func++;
737 } 799 }
@@ -801,6 +863,13 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
801 pctl->dev = &pdev->dev; 863 pctl->dev = &pdev->dev;
802 pctl->desc = desc; 864 pctl->desc = desc;
803 865
866 pctl->irq_array = devm_kcalloc(&pdev->dev,
867 IRQ_PER_BANK * pctl->desc->irq_banks,
868 sizeof(*pctl->irq_array),
869 GFP_KERNEL);
870 if (!pctl->irq_array)
871 return -ENOMEM;
872
804 ret = sunxi_pinctrl_build_state(pdev); 873 ret = sunxi_pinctrl_build_state(pdev);
805 if (ret) { 874 if (ret) {
806 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 875 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
@@ -869,7 +938,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
869 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 938 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
870 939
871 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 940 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
872 pin->pin.number, 941 pin->pin.number - pctl->desc->pin_base,
873 pin->pin.number, 1); 942 pin->pin.number, 1);
874 if (ret) 943 if (ret)
875 goto gpiochip_error; 944 goto gpiochip_error;
@@ -885,30 +954,51 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
885 if (ret) 954 if (ret)
886 goto gpiochip_error; 955 goto gpiochip_error;
887 956
888 pctl->irq = irq_of_parse_and_map(node, 0); 957 pctl->irq = devm_kcalloc(&pdev->dev,
958 pctl->desc->irq_banks,
959 sizeof(*pctl->irq),
960 GFP_KERNEL);
889 if (!pctl->irq) { 961 if (!pctl->irq) {
890 ret = -EINVAL; 962 ret = -ENOMEM;
891 goto clk_error; 963 goto clk_error;
892 } 964 }
893 965
894 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, 966 for (i = 0; i < pctl->desc->irq_banks; i++) {
895 &irq_domain_simple_ops, NULL); 967 pctl->irq[i] = platform_get_irq(pdev, i);
968 if (pctl->irq[i] < 0) {
969 ret = pctl->irq[i];
970 goto clk_error;
971 }
972 }
973
974 pctl->domain = irq_domain_add_linear(node,
975 pctl->desc->irq_banks * IRQ_PER_BANK,
976 &irq_domain_simple_ops,
977 NULL);
896 if (!pctl->domain) { 978 if (!pctl->domain) {
897 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 979 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
898 ret = -ENOMEM; 980 ret = -ENOMEM;
899 goto clk_error; 981 goto clk_error;
900 } 982 }
901 983
902 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { 984 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
903 int irqno = irq_create_mapping(pctl->domain, i); 985 int irqno = irq_create_mapping(pctl->domain, i);
904 986
905 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, 987 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
906 handle_simple_irq); 988 handle_edge_irq);
907 irq_set_chip_data(irqno, pctl); 989 irq_set_chip_data(irqno, pctl);
908 }; 990 };
909 991
910 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); 992 for (i = 0; i < pctl->desc->irq_banks; i++) {
911 irq_set_handler_data(pctl->irq, pctl); 993 /* Mask and clear all IRQs before registering a handler */
994 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i));
995 writel(0xffffffff,
996 pctl->membase + sunxi_irq_status_reg_from_bank(i));
997
998 irq_set_chained_handler(pctl->irq[i],
999 sunxi_pinctrl_irq_handler);
1000 irq_set_handler_data(pctl->irq[i], pctl);
1001 }
912 1002
913 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1003 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
914 1004
@@ -917,8 +1007,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
917clk_error: 1007clk_error:
918 clk_disable_unprepare(clk); 1008 clk_disable_unprepare(clk);
919gpiochip_error: 1009gpiochip_error:
920 if (gpiochip_remove(pctl->chip)) 1010 gpiochip_remove(pctl->chip);
921 dev_err(&pdev->dev, "failed to remove gpio chip\n");
922pinctrl_error: 1011pinctrl_error:
923 pinctrl_unregister(pctl->pctl_dev); 1012 pinctrl_unregister(pctl->pctl_dev);
924 return ret; 1013 return ret;
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 8169ba598876..4245b96c7996 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -53,7 +53,7 @@
53#define PULL_PINS_BITS 2 53#define PULL_PINS_BITS 2
54#define PULL_PINS_MASK 0x03 54#define PULL_PINS_MASK 0x03
55 55
56#define SUNXI_IRQ_NUMBER 32 56#define IRQ_PER_BANK 32
57 57
58#define IRQ_CFG_REG 0x200 58#define IRQ_CFG_REG 0x200
59#define IRQ_CFG_IRQ_PER_REG 8 59#define IRQ_CFG_IRQ_PER_REG 8
@@ -68,6 +68,8 @@
68#define IRQ_STATUS_IRQ_BITS 1 68#define IRQ_STATUS_IRQ_BITS 1
69#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 69#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
70 70
71#define IRQ_MEM_SIZE 0x20
72
71#define IRQ_EDGE_RISING 0x00 73#define IRQ_EDGE_RISING 0x00
72#define IRQ_EDGE_FALLING 0x01 74#define IRQ_EDGE_FALLING 0x01
73#define IRQ_LEVEL_HIGH 0x02 75#define IRQ_LEVEL_HIGH 0x02
@@ -77,6 +79,7 @@
77struct sunxi_desc_function { 79struct sunxi_desc_function {
78 const char *name; 80 const char *name;
79 u8 muxval; 81 u8 muxval;
82 u8 irqbank;
80 u8 irqnum; 83 u8 irqnum;
81}; 84};
82 85
@@ -89,6 +92,7 @@ struct sunxi_pinctrl_desc {
89 const struct sunxi_desc_pin *pins; 92 const struct sunxi_desc_pin *pins;
90 int npins; 93 int npins;
91 unsigned pin_base; 94 unsigned pin_base;
95 unsigned irq_banks;
92}; 96};
93 97
94struct sunxi_pinctrl_function { 98struct sunxi_pinctrl_function {
@@ -113,8 +117,8 @@ struct sunxi_pinctrl {
113 unsigned nfunctions; 117 unsigned nfunctions;
114 struct sunxi_pinctrl_group *groups; 118 struct sunxi_pinctrl_group *groups;
115 unsigned ngroups; 119 unsigned ngroups;
116 int irq; 120 int *irq;
117 int irq_array[SUNXI_IRQ_NUMBER]; 121 unsigned *irq_array;
118 spinlock_t lock; 122 spinlock_t lock;
119 struct pinctrl_dev *pctl_dev; 123 struct pinctrl_dev *pctl_dev;
120}; 124};
@@ -139,6 +143,14 @@ struct sunxi_pinctrl {
139 .irqnum = _irq, \ 143 .irqnum = _irq, \
140 } 144 }
141 145
146#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
147 { \
148 .name = "irq", \
149 .muxval = _val, \
150 .irqbank = _bank, \
151 .irqnum = _irq, \
152 }
153
142/* 154/*
143 * The sunXi PIO registers are organized as is: 155 * The sunXi PIO registers are organized as is:
144 * 0x00 - 0x0c Muxing values. 156 * 0x00 - 0x0c Muxing values.
@@ -218,8 +230,10 @@ static inline u32 sunxi_pull_offset(u16 pin)
218 230
219static inline u32 sunxi_irq_cfg_reg(u16 irq) 231static inline u32 sunxi_irq_cfg_reg(u16 irq)
220{ 232{
221 u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04; 233 u8 bank = irq / IRQ_PER_BANK;
222 return reg + IRQ_CFG_REG; 234 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
235
236 return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
223} 237}
224 238
225static inline u32 sunxi_irq_cfg_offset(u16 irq) 239static inline u32 sunxi_irq_cfg_offset(u16 irq)
@@ -228,10 +242,16 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
228 return irq_num * IRQ_CFG_IRQ_BITS; 242 return irq_num * IRQ_CFG_IRQ_BITS;
229} 243}
230 244
245static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
246{
247 return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
248}
249
231static inline u32 sunxi_irq_ctrl_reg(u16 irq) 250static inline u32 sunxi_irq_ctrl_reg(u16 irq)
232{ 251{
233 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04; 252 u8 bank = irq / IRQ_PER_BANK;
234 return reg + IRQ_CTRL_REG; 253
254 return sunxi_irq_ctrl_reg_from_bank(bank);
235} 255}
236 256
237static inline u32 sunxi_irq_ctrl_offset(u16 irq) 257static inline u32 sunxi_irq_ctrl_offset(u16 irq)
@@ -240,10 +260,16 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
240 return irq_num * IRQ_CTRL_IRQ_BITS; 260 return irq_num * IRQ_CTRL_IRQ_BITS;
241} 261}
242 262
263static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
264{
265 return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
266}
267
243static inline u32 sunxi_irq_status_reg(u16 irq) 268static inline u32 sunxi_irq_status_reg(u16 irq)
244{ 269{
245 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04; 270 u8 bank = irq / IRQ_PER_BANK;
246 return reg + IRQ_STATUS_REG; 271
272 return sunxi_irq_status_reg_from_bank(bank);
247} 273}
248 274
249static inline u32 sunxi_irq_status_offset(u16 irq) 275static inline u32 sunxi_irq_status_offset(u16 irq)
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index 2c61281bebd7..8cea355f9a81 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -141,17 +141,6 @@ static int wmt_pmx_enable(struct pinctrl_dev *pctldev,
141 return wmt_set_pinmux(data, func_selector, pinnum); 141 return wmt_set_pinmux(data, func_selector, pinnum);
142} 142}
143 143
144static void wmt_pmx_disable(struct pinctrl_dev *pctldev,
145 unsigned func_selector,
146 unsigned group_selector)
147{
148 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
149 u32 pinnum = data->pins[group_selector].number;
150
151 /* disable by setting GPIO_IN */
152 wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, pinnum);
153}
154
155static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 144static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
156 struct pinctrl_gpio_range *range, 145 struct pinctrl_gpio_range *range,
157 unsigned offset) 146 unsigned offset)
@@ -180,7 +169,6 @@ static struct pinmux_ops wmt_pinmux_ops = {
180 .get_function_name = wmt_pmx_get_function_name, 169 .get_function_name = wmt_pmx_get_function_name,
181 .get_function_groups = wmt_pmx_get_function_groups, 170 .get_function_groups = wmt_pmx_get_function_groups,
182 .enable = wmt_pmx_enable, 171 .enable = wmt_pmx_enable,
183 .disable = wmt_pmx_disable,
184 .gpio_disable_free = wmt_pmx_gpio_disable_free, 172 .gpio_disable_free = wmt_pmx_gpio_disable_free,
185 .gpio_set_direction = wmt_pmx_gpio_set_direction, 173 .gpio_set_direction = wmt_pmx_gpio_set_direction,
186}; 174};
@@ -627,8 +615,7 @@ int wmt_pinctrl_probe(struct platform_device *pdev,
627 return 0; 615 return 0;
628 616
629fail_range: 617fail_range:
630 if (gpiochip_remove(&data->gpio_chip)) 618 gpiochip_remove(&data->gpio_chip);
631 dev_err(&pdev->dev, "failed to remove gpio chip\n");
632fail_gpio: 619fail_gpio:
633 pinctrl_unregister(data->pctl_dev); 620 pinctrl_unregister(data->pctl_dev);
634 return err; 621 return err;
@@ -637,12 +624,8 @@ fail_gpio:
637int wmt_pinctrl_remove(struct platform_device *pdev) 624int wmt_pinctrl_remove(struct platform_device *pdev)
638{ 625{
639 struct wmt_pinctrl_data *data = platform_get_drvdata(pdev); 626 struct wmt_pinctrl_data *data = platform_get_drvdata(pdev);
640 int err;
641
642 err = gpiochip_remove(&data->gpio_chip);
643 if (err)
644 dev_err(&pdev->dev, "failed to remove gpio chip\n");
645 627
628 gpiochip_remove(&data->gpio_chip);
646 pinctrl_unregister(data->pctl_dev); 629 pinctrl_unregister(data->pctl_dev);
647 630
648 return 0; 631 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 23:55:30 -0500