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path: root/drivers/pinctrl/samsung/pinctrl-exynos5440.c
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Diffstat (limited to 'drivers/pinctrl/samsung/pinctrl-exynos5440.c')
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c1061
1 files changed, 1061 insertions, 0 deletions
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
new file mode 100644
index 000000000000..603da2f9dd95
--- /dev/null
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -0,0 +1,1061 @@
1/*
2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/interrupt.h>
24#include <linux/irqdomain.h>
25#include <linux/of_irq.h>
26#include "../core.h"
27
28/* EXYNOS5440 GPIO and Pinctrl register offsets */
29#define GPIO_MUX 0x00
30#define GPIO_IE 0x04
31#define GPIO_INT 0x08
32#define GPIO_TYPE 0x0C
33#define GPIO_VAL 0x10
34#define GPIO_OE 0x14
35#define GPIO_IN 0x18
36#define GPIO_PE 0x1C
37#define GPIO_PS 0x20
38#define GPIO_SR 0x24
39#define GPIO_DS0 0x28
40#define GPIO_DS1 0x2C
41
42#define EXYNOS5440_MAX_PINS 23
43#define EXYNOS5440_MAX_GPIO_INT 8
44#define PIN_NAME_LENGTH 10
45
46#define GROUP_SUFFIX "-grp"
47#define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
48#define FUNCTION_SUFFIX "-mux"
49#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
50
51/*
52 * pin configuration type and its value are packed together into a 16-bits.
53 * The upper 8-bits represent the configuration type and the lower 8-bits
54 * hold the value of the configuration type.
55 */
56#define PINCFG_TYPE_MASK 0xFF
57#define PINCFG_VALUE_SHIFT 8
58#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
59#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
60#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
61#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
62 PINCFG_VALUE_SHIFT)
63
64/**
65 * enum pincfg_type - possible pin configuration types supported.
66 * @PINCFG_TYPE_PUD: Pull up/down configuration.
67 * @PINCFG_TYPE_DRV: Drive strength configuration.
68 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
69 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
70 */
71enum pincfg_type {
72 PINCFG_TYPE_PUD,
73 PINCFG_TYPE_DRV,
74 PINCFG_TYPE_SKEW_RATE,
75 PINCFG_TYPE_INPUT_TYPE
76};
77
78/**
79 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
80 * @name: name of the pin group, used to lookup the group.
81 * @pins: the pins included in this group.
82 * @num_pins: number of pins included in this group.
83 */
84struct exynos5440_pin_group {
85 const char *name;
86 const unsigned int *pins;
87 u8 num_pins;
88};
89
90/**
91 * struct exynos5440_pmx_func: represent a pin function.
92 * @name: name of the pin function, used to lookup the function.
93 * @groups: one or more names of pin groups that provide this function.
94 * @num_groups: number of groups included in @groups.
95 * @function: the function number to be programmed when selected.
96 */
97struct exynos5440_pmx_func {
98 const char *name;
99 const char **groups;
100 u8 num_groups;
101 unsigned long function;
102};
103
104/**
105 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
106 * @reg_base: ioremapped based address of the register space.
107 * @gc: gpio chip registered with gpiolib.
108 * @pin_groups: list of pin groups parsed from device tree.
109 * @nr_groups: number of pin groups available.
110 * @pmx_functions: list of pin functions parsed from device tree.
111 * @nr_functions: number of pin functions available.
112 */
113struct exynos5440_pinctrl_priv_data {
114 void __iomem *reg_base;
115 struct gpio_chip *gc;
116 struct irq_domain *irq_domain;
117
118 const struct exynos5440_pin_group *pin_groups;
119 unsigned int nr_groups;
120 const struct exynos5440_pmx_func *pmx_functions;
121 unsigned int nr_functions;
122};
123
124/**
125 * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
126 * @priv: driver's private runtime data.
127 * @gpio_int: gpio interrupt number.
128 */
129struct exynos5440_gpio_intr_data {
130 struct exynos5440_pinctrl_priv_data *priv;
131 unsigned int gpio_int;
132};
133
134/* list of all possible config options supported */
135static struct pin_config {
136 char *prop_cfg;
137 unsigned int cfg_type;
138} pcfgs[] = {
139 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
140 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
141 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
142 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
143};
144
145/* check if the selector is a valid pin group selector */
146static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
147{
148 struct exynos5440_pinctrl_priv_data *priv;
149
150 priv = pinctrl_dev_get_drvdata(pctldev);
151 return priv->nr_groups;
152}
153
154/* return the name of the group selected by the group selector */
155static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
156 unsigned selector)
157{
158 struct exynos5440_pinctrl_priv_data *priv;
159
160 priv = pinctrl_dev_get_drvdata(pctldev);
161 return priv->pin_groups[selector].name;
162}
163
164/* return the pin numbers associated with the specified group */
165static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
166 unsigned selector, const unsigned **pins, unsigned *num_pins)
167{
168 struct exynos5440_pinctrl_priv_data *priv;
169
170 priv = pinctrl_dev_get_drvdata(pctldev);
171 *pins = priv->pin_groups[selector].pins;
172 *num_pins = priv->pin_groups[selector].num_pins;
173 return 0;
174}
175
176/* create pinctrl_map entries by parsing device tree nodes */
177static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
178 struct device_node *np, struct pinctrl_map **maps,
179 unsigned *nmaps)
180{
181 struct device *dev = pctldev->dev;
182 struct pinctrl_map *map;
183 unsigned long *cfg = NULL;
184 char *gname, *fname;
185 int cfg_cnt = 0, map_cnt = 0, idx = 0;
186
187 /* count the number of config options specfied in the node */
188 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
189 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
190 cfg_cnt++;
191
192 /*
193 * Find out the number of map entries to create. All the config options
194 * can be accomadated into a single config map entry.
195 */
196 if (cfg_cnt)
197 map_cnt = 1;
198 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
199 map_cnt++;
200 if (!map_cnt) {
201 dev_err(dev, "node %s does not have either config or function "
202 "configurations\n", np->name);
203 return -EINVAL;
204 }
205
206 /* Allocate memory for pin-map entries */
207 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
208 if (!map) {
209 dev_err(dev, "could not alloc memory for pin-maps\n");
210 return -ENOMEM;
211 }
212 *nmaps = 0;
213
214 /*
215 * Allocate memory for pin group name. The pin group name is derived
216 * from the node name from which these map entries are be created.
217 */
218 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
219 if (!gname) {
220 dev_err(dev, "failed to alloc memory for group name\n");
221 goto free_map;
222 }
223 snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX);
224
225 /*
226 * don't have config options? then skip over to creating function
227 * map entries.
228 */
229 if (!cfg_cnt)
230 goto skip_cfgs;
231
232 /* Allocate memory for config entries */
233 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
234 if (!cfg) {
235 dev_err(dev, "failed to alloc memory for configs\n");
236 goto free_gname;
237 }
238
239 /* Prepare a list of config settings */
240 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
241 u32 value;
242 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
243 cfg[cfg_cnt++] =
244 PINCFG_PACK(pcfgs[idx].cfg_type, value);
245 }
246
247 /* create the config map entry */
248 map[*nmaps].data.configs.group_or_pin = gname;
249 map[*nmaps].data.configs.configs = cfg;
250 map[*nmaps].data.configs.num_configs = cfg_cnt;
251 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
252 *nmaps += 1;
253
254skip_cfgs:
255 /* create the function map entry */
256 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
257 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL);
258 if (!fname) {
259 dev_err(dev, "failed to alloc memory for func name\n");
260 goto free_cfg;
261 }
262 snprintf(fname, strlen(np->name) + 4, "%s%s", np->name,
263 FUNCTION_SUFFIX);
264
265 map[*nmaps].data.mux.group = gname;
266 map[*nmaps].data.mux.function = fname;
267 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
268 *nmaps += 1;
269 }
270
271 *maps = map;
272 return 0;
273
274free_cfg:
275 kfree(cfg);
276free_gname:
277 kfree(gname);
278free_map:
279 kfree(map);
280 return -ENOMEM;
281}
282
283/* free the memory allocated to hold the pin-map table */
284static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
285 struct pinctrl_map *map, unsigned num_maps)
286{
287 int idx;
288
289 for (idx = 0; idx < num_maps; idx++) {
290 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
291 kfree(map[idx].data.mux.function);
292 if (!idx)
293 kfree(map[idx].data.mux.group);
294 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
295 kfree(map[idx].data.configs.configs);
296 if (!idx)
297 kfree(map[idx].data.configs.group_or_pin);
298 }
299 };
300
301 kfree(map);
302}
303
304/* list of pinctrl callbacks for the pinctrl core */
305static const struct pinctrl_ops exynos5440_pctrl_ops = {
306 .get_groups_count = exynos5440_get_group_count,
307 .get_group_name = exynos5440_get_group_name,
308 .get_group_pins = exynos5440_get_group_pins,
309 .dt_node_to_map = exynos5440_dt_node_to_map,
310 .dt_free_map = exynos5440_dt_free_map,
311};
312
313/* check if the selector is a valid pin function selector */
314static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
315{
316 struct exynos5440_pinctrl_priv_data *priv;
317
318 priv = pinctrl_dev_get_drvdata(pctldev);
319 return priv->nr_functions;
320}
321
322/* return the name of the pin function specified */
323static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
324 unsigned selector)
325{
326 struct exynos5440_pinctrl_priv_data *priv;
327
328 priv = pinctrl_dev_get_drvdata(pctldev);
329 return priv->pmx_functions[selector].name;
330}
331
332/* return the groups associated for the specified function selector */
333static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
334 unsigned selector, const char * const **groups,
335 unsigned * const num_groups)
336{
337 struct exynos5440_pinctrl_priv_data *priv;
338
339 priv = pinctrl_dev_get_drvdata(pctldev);
340 *groups = priv->pmx_functions[selector].groups;
341 *num_groups = priv->pmx_functions[selector].num_groups;
342 return 0;
343}
344
345/* enable or disable a pinmux function */
346static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
347 unsigned group, bool enable)
348{
349 struct exynos5440_pinctrl_priv_data *priv;
350 void __iomem *base;
351 u32 function;
352 u32 data;
353
354 priv = pinctrl_dev_get_drvdata(pctldev);
355 base = priv->reg_base;
356 function = priv->pmx_functions[selector].function;
357
358 data = readl(base + GPIO_MUX);
359 if (enable)
360 data |= (1 << function);
361 else
362 data &= ~(1 << function);
363 writel(data, base + GPIO_MUX);
364}
365
366/* enable a specified pinmux by writing to registers */
367static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
368 unsigned group)
369{
370 exynos5440_pinmux_setup(pctldev, selector, group, true);
371 return 0;
372}
373
374/*
375 * The calls to gpio_direction_output() and gpio_direction_input()
376 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
377 * function called from the gpiolib interface).
378 */
379static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
380 struct pinctrl_gpio_range *range, unsigned offset, bool input)
381{
382 return 0;
383}
384
385/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
386static const struct pinmux_ops exynos5440_pinmux_ops = {
387 .get_functions_count = exynos5440_get_functions_count,
388 .get_function_name = exynos5440_pinmux_get_fname,
389 .get_function_groups = exynos5440_pinmux_get_groups,
390 .enable = exynos5440_pinmux_enable,
391 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
392};
393
394/* set the pin config settings for a specified pin */
395static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
396 unsigned long *configs,
397 unsigned num_configs)
398{
399 struct exynos5440_pinctrl_priv_data *priv;
400 void __iomem *base;
401 enum pincfg_type cfg_type;
402 u32 cfg_value;
403 u32 data;
404 int i;
405
406 priv = pinctrl_dev_get_drvdata(pctldev);
407 base = priv->reg_base;
408
409 for (i = 0; i < num_configs; i++) {
410 cfg_type = PINCFG_UNPACK_TYPE(configs[i]);
411 cfg_value = PINCFG_UNPACK_VALUE(configs[i]);
412
413 switch (cfg_type) {
414 case PINCFG_TYPE_PUD:
415 /* first set pull enable/disable bit */
416 data = readl(base + GPIO_PE);
417 data &= ~(1 << pin);
418 if (cfg_value)
419 data |= (1 << pin);
420 writel(data, base + GPIO_PE);
421
422 /* then set pull up/down bit */
423 data = readl(base + GPIO_PS);
424 data &= ~(1 << pin);
425 if (cfg_value == 2)
426 data |= (1 << pin);
427 writel(data, base + GPIO_PS);
428 break;
429
430 case PINCFG_TYPE_DRV:
431 /* set the first bit of the drive strength */
432 data = readl(base + GPIO_DS0);
433 data &= ~(1 << pin);
434 data |= ((cfg_value & 1) << pin);
435 writel(data, base + GPIO_DS0);
436 cfg_value >>= 1;
437
438 /* set the second bit of the driver strength */
439 data = readl(base + GPIO_DS1);
440 data &= ~(1 << pin);
441 data |= ((cfg_value & 1) << pin);
442 writel(data, base + GPIO_DS1);
443 break;
444 case PINCFG_TYPE_SKEW_RATE:
445 data = readl(base + GPIO_SR);
446 data &= ~(1 << pin);
447 data |= ((cfg_value & 1) << pin);
448 writel(data, base + GPIO_SR);
449 break;
450 case PINCFG_TYPE_INPUT_TYPE:
451 data = readl(base + GPIO_TYPE);
452 data &= ~(1 << pin);
453 data |= ((cfg_value & 1) << pin);
454 writel(data, base + GPIO_TYPE);
455 break;
456 default:
457 WARN_ON(1);
458 return -EINVAL;
459 }
460 } /* for each config */
461
462 return 0;
463}
464
465/* get the pin config settings for a specified pin */
466static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
467 unsigned long *config)
468{
469 struct exynos5440_pinctrl_priv_data *priv;
470 void __iomem *base;
471 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
472 u32 data;
473
474 priv = pinctrl_dev_get_drvdata(pctldev);
475 base = priv->reg_base;
476
477 switch (cfg_type) {
478 case PINCFG_TYPE_PUD:
479 data = readl(base + GPIO_PE);
480 data = (data >> pin) & 1;
481 if (!data)
482 *config = 0;
483 else
484 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
485 break;
486 case PINCFG_TYPE_DRV:
487 data = readl(base + GPIO_DS0);
488 data = (data >> pin) & 1;
489 *config = data;
490 data = readl(base + GPIO_DS1);
491 data = (data >> pin) & 1;
492 *config |= (data << 1);
493 break;
494 case PINCFG_TYPE_SKEW_RATE:
495 data = readl(base + GPIO_SR);
496 *config = (data >> pin) & 1;
497 break;
498 case PINCFG_TYPE_INPUT_TYPE:
499 data = readl(base + GPIO_TYPE);
500 *config = (data >> pin) & 1;
501 break;
502 default:
503 WARN_ON(1);
504 return -EINVAL;
505 }
506
507 return 0;
508}
509
510/* set the pin config settings for a specified pin group */
511static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
512 unsigned group, unsigned long *configs,
513 unsigned num_configs)
514{
515 struct exynos5440_pinctrl_priv_data *priv;
516 const unsigned int *pins;
517 unsigned int cnt;
518
519 priv = pinctrl_dev_get_drvdata(pctldev);
520 pins = priv->pin_groups[group].pins;
521
522 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
523 exynos5440_pinconf_set(pctldev, pins[cnt], configs,
524 num_configs);
525
526 return 0;
527}
528
529/* get the pin config settings for a specified pin group */
530static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
531 unsigned int group, unsigned long *config)
532{
533 struct exynos5440_pinctrl_priv_data *priv;
534 const unsigned int *pins;
535
536 priv = pinctrl_dev_get_drvdata(pctldev);
537 pins = priv->pin_groups[group].pins;
538 exynos5440_pinconf_get(pctldev, pins[0], config);
539 return 0;
540}
541
542/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
543static const struct pinconf_ops exynos5440_pinconf_ops = {
544 .pin_config_get = exynos5440_pinconf_get,
545 .pin_config_set = exynos5440_pinconf_set,
546 .pin_config_group_get = exynos5440_pinconf_group_get,
547 .pin_config_group_set = exynos5440_pinconf_group_set,
548};
549
550/* gpiolib gpio_set callback function */
551static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
552{
553 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
554 void __iomem *base = priv->reg_base;
555 u32 data;
556
557 data = readl(base + GPIO_VAL);
558 data &= ~(1 << offset);
559 if (value)
560 data |= 1 << offset;
561 writel(data, base + GPIO_VAL);
562}
563
564/* gpiolib gpio_get callback function */
565static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
566{
567 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
568 void __iomem *base = priv->reg_base;
569 u32 data;
570
571 data = readl(base + GPIO_IN);
572 data >>= offset;
573 data &= 1;
574 return data;
575}
576
577/* gpiolib gpio_direction_input callback function */
578static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
579{
580 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
581 void __iomem *base = priv->reg_base;
582 u32 data;
583
584 /* first disable the data output enable on this pin */
585 data = readl(base + GPIO_OE);
586 data &= ~(1 << offset);
587 writel(data, base + GPIO_OE);
588
589 /* now enable input on this pin */
590 data = readl(base + GPIO_IE);
591 data |= 1 << offset;
592 writel(data, base + GPIO_IE);
593 return 0;
594}
595
596/* gpiolib gpio_direction_output callback function */
597static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
598 int value)
599{
600 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
601 void __iomem *base = priv->reg_base;
602 u32 data;
603
604 exynos5440_gpio_set(gc, offset, value);
605
606 /* first disable the data input enable on this pin */
607 data = readl(base + GPIO_IE);
608 data &= ~(1 << offset);
609 writel(data, base + GPIO_IE);
610
611 /* now enable output on this pin */
612 data = readl(base + GPIO_OE);
613 data |= 1 << offset;
614 writel(data, base + GPIO_OE);
615 return 0;
616}
617
618/* gpiolib gpio_to_irq callback function */
619static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
620{
621 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
622 unsigned int virq;
623
624 if (offset < 16 || offset > 23)
625 return -ENXIO;
626
627 if (!priv->irq_domain)
628 return -ENXIO;
629
630 virq = irq_create_mapping(priv->irq_domain, offset - 16);
631 return virq ? : -ENXIO;
632}
633
634/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
635static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
636 struct device_node *cfg_np, unsigned int **pin_list,
637 unsigned int *npins)
638{
639 struct device *dev = &pdev->dev;
640 struct property *prop;
641
642 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
643 if (!prop)
644 return -ENOENT;
645
646 *npins = prop->length / sizeof(unsigned long);
647 if (!*npins) {
648 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
649 return -EINVAL;
650 }
651
652 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
653 if (!*pin_list) {
654 dev_err(dev, "failed to allocate memory for pin list\n");
655 return -ENOMEM;
656 }
657
658 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
659 *pin_list, *npins);
660}
661
662/*
663 * Parse the information about all the available pin groups and pin functions
664 * from device node of the pin-controller.
665 */
666static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
667 struct exynos5440_pinctrl_priv_data *priv)
668{
669 struct device *dev = &pdev->dev;
670 struct device_node *dev_np = dev->of_node;
671 struct device_node *cfg_np;
672 struct exynos5440_pin_group *groups, *grp;
673 struct exynos5440_pmx_func *functions, *func;
674 unsigned *pin_list;
675 unsigned int npins, grp_cnt, func_idx = 0;
676 char *gname, *fname;
677 int ret;
678
679 grp_cnt = of_get_child_count(dev_np);
680 if (!grp_cnt)
681 return -EINVAL;
682
683 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
684 if (!groups) {
685 dev_err(dev, "failed allocate memory for ping group list\n");
686 return -EINVAL;
687 }
688 grp = groups;
689
690 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
691 if (!functions) {
692 dev_err(dev, "failed to allocate memory for function list\n");
693 return -EINVAL;
694 }
695 func = functions;
696
697 /*
698 * Iterate over all the child nodes of the pin controller node
699 * and create pin groups and pin function lists.
700 */
701 for_each_child_of_node(dev_np, cfg_np) {
702 u32 function;
703
704 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
705 &pin_list, &npins);
706 if (ret) {
707 gname = NULL;
708 goto skip_to_pin_function;
709 }
710
711 /* derive pin group name from the node name */
712 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
713 GFP_KERNEL);
714 if (!gname) {
715 dev_err(dev, "failed to alloc memory for group name\n");
716 return -ENOMEM;
717 }
718 snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
719 GROUP_SUFFIX);
720
721 grp->name = gname;
722 grp->pins = pin_list;
723 grp->num_pins = npins;
724 grp++;
725
726skip_to_pin_function:
727 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
728 &function);
729 if (ret)
730 continue;
731
732 /* derive function name from the node name */
733 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
734 GFP_KERNEL);
735 if (!fname) {
736 dev_err(dev, "failed to alloc memory for func name\n");
737 return -ENOMEM;
738 }
739 snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
740 FUNCTION_SUFFIX);
741
742 func->name = fname;
743 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
744 if (!func->groups) {
745 dev_err(dev, "failed to alloc memory for group list "
746 "in pin function");
747 return -ENOMEM;
748 }
749 func->groups[0] = gname;
750 func->num_groups = gname ? 1 : 0;
751 func->function = function;
752 func++;
753 func_idx++;
754 }
755
756 priv->pin_groups = groups;
757 priv->nr_groups = grp_cnt;
758 priv->pmx_functions = functions;
759 priv->nr_functions = func_idx;
760 return 0;
761}
762
763/* register the pinctrl interface with the pinctrl subsystem */
764static int exynos5440_pinctrl_register(struct platform_device *pdev,
765 struct exynos5440_pinctrl_priv_data *priv)
766{
767 struct device *dev = &pdev->dev;
768 struct pinctrl_desc *ctrldesc;
769 struct pinctrl_dev *pctl_dev;
770 struct pinctrl_pin_desc *pindesc, *pdesc;
771 struct pinctrl_gpio_range grange;
772 char *pin_names;
773 int pin, ret;
774
775 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
776 if (!ctrldesc) {
777 dev_err(dev, "could not allocate memory for pinctrl desc\n");
778 return -ENOMEM;
779 }
780
781 ctrldesc->name = "exynos5440-pinctrl";
782 ctrldesc->owner = THIS_MODULE;
783 ctrldesc->pctlops = &exynos5440_pctrl_ops;
784 ctrldesc->pmxops = &exynos5440_pinmux_ops;
785 ctrldesc->confops = &exynos5440_pinconf_ops;
786
787 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
788 EXYNOS5440_MAX_PINS, GFP_KERNEL);
789 if (!pindesc) {
790 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
791 return -ENOMEM;
792 }
793 ctrldesc->pins = pindesc;
794 ctrldesc->npins = EXYNOS5440_MAX_PINS;
795
796 /* dynamically populate the pin number and pin name for pindesc */
797 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
798 pdesc->number = pin;
799
800 /*
801 * allocate space for storing the dynamically generated names for all
802 * the pins which belong to this pin-controller.
803 */
804 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
805 ctrldesc->npins, GFP_KERNEL);
806 if (!pin_names) {
807 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
808 return -ENOMEM;
809 }
810
811 /* for each pin, set the name of the pin */
812 for (pin = 0; pin < ctrldesc->npins; pin++) {
813 snprintf(pin_names, 6, "gpio%02d", pin);
814 pdesc = pindesc + pin;
815 pdesc->name = pin_names;
816 pin_names += PIN_NAME_LENGTH;
817 }
818
819 ret = exynos5440_pinctrl_parse_dt(pdev, priv);
820 if (ret)
821 return ret;
822
823 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
824 if (!pctl_dev) {
825 dev_err(&pdev->dev, "could not register pinctrl driver\n");
826 return -EINVAL;
827 }
828
829 grange.name = "exynos5440-pctrl-gpio-range";
830 grange.id = 0;
831 grange.base = 0;
832 grange.npins = EXYNOS5440_MAX_PINS;
833 grange.gc = priv->gc;
834 pinctrl_add_gpio_range(pctl_dev, &grange);
835 return 0;
836}
837
838/* register the gpiolib interface with the gpiolib subsystem */
839static int exynos5440_gpiolib_register(struct platform_device *pdev,
840 struct exynos5440_pinctrl_priv_data *priv)
841{
842 struct gpio_chip *gc;
843 int ret;
844
845 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
846 if (!gc) {
847 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
848 return -ENOMEM;
849 }
850
851 priv->gc = gc;
852 gc->base = 0;
853 gc->ngpio = EXYNOS5440_MAX_PINS;
854 gc->dev = &pdev->dev;
855 gc->set = exynos5440_gpio_set;
856 gc->get = exynos5440_gpio_get;
857 gc->direction_input = exynos5440_gpio_direction_input;
858 gc->direction_output = exynos5440_gpio_direction_output;
859 gc->to_irq = exynos5440_gpio_to_irq;
860 gc->label = "gpiolib-exynos5440";
861 gc->owner = THIS_MODULE;
862 ret = gpiochip_add(gc);
863 if (ret) {
864 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
865 "code: %d\n", gc->label, ret);
866 return ret;
867 }
868
869 return 0;
870}
871
872/* unregister the gpiolib interface with the gpiolib subsystem */
873static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
874 struct exynos5440_pinctrl_priv_data *priv)
875{
876 int ret = gpiochip_remove(priv->gc);
877 if (ret) {
878 dev_err(&pdev->dev, "gpio chip remove failed\n");
879 return ret;
880 }
881 return 0;
882}
883
884static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
885{
886 struct exynos5440_pinctrl_priv_data *d;
887 unsigned long gpio_int;
888
889 d = irq_data_get_irq_chip_data(irqd);
890 gpio_int = readl(d->reg_base + GPIO_INT);
891 gpio_int |= 1 << irqd->hwirq;
892 writel(gpio_int, d->reg_base + GPIO_INT);
893}
894
895static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
896{
897 struct exynos5440_pinctrl_priv_data *d;
898 unsigned long gpio_int;
899
900 d = irq_data_get_irq_chip_data(irqd);
901 gpio_int = readl(d->reg_base + GPIO_INT);
902 gpio_int &= ~(1 << irqd->hwirq);
903 writel(gpio_int, d->reg_base + GPIO_INT);
904}
905
906/* irq_chip for gpio interrupts */
907static struct irq_chip exynos5440_gpio_irq_chip = {
908 .name = "exynos5440_gpio_irq_chip",
909 .irq_unmask = exynos5440_gpio_irq_unmask,
910 .irq_mask = exynos5440_gpio_irq_mask,
911};
912
913/* interrupt handler for GPIO interrupts 0..7 */
914static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
915{
916 struct exynos5440_gpio_intr_data *intd = data;
917 struct exynos5440_pinctrl_priv_data *d = intd->priv;
918 int virq;
919
920 virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
921 if (!virq)
922 return IRQ_NONE;
923 generic_handle_irq(virq);
924 return IRQ_HANDLED;
925}
926
927static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
928 irq_hw_number_t hw)
929{
930 struct exynos5440_pinctrl_priv_data *d = h->host_data;
931
932 irq_set_chip_data(virq, d);
933 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
934 handle_level_irq);
935 set_irq_flags(virq, IRQF_VALID);
936 return 0;
937}
938
939/* irq domain callbacks for gpio interrupt controller */
940static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
941 .map = exynos5440_gpio_irq_map,
942 .xlate = irq_domain_xlate_twocell,
943};
944
945/* setup handling of gpio interrupts */
946static int exynos5440_gpio_irq_init(struct platform_device *pdev,
947 struct exynos5440_pinctrl_priv_data *priv)
948{
949 struct device *dev = &pdev->dev;
950 struct exynos5440_gpio_intr_data *intd;
951 int i, irq, ret;
952
953 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
954 GFP_KERNEL);
955 if (!intd) {
956 dev_err(dev, "failed to allocate memory for gpio intr data\n");
957 return -ENOMEM;
958 }
959
960 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
961 irq = irq_of_parse_and_map(dev->of_node, i);
962 if (irq <= 0) {
963 dev_err(dev, "irq parsing failed\n");
964 return -EINVAL;
965 }
966
967 intd->gpio_int = i;
968 intd->priv = priv;
969 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
970 0, dev_name(dev), intd++);
971 if (ret) {
972 dev_err(dev, "irq request failed\n");
973 return -ENXIO;
974 }
975 }
976
977 priv->irq_domain = irq_domain_add_linear(dev->of_node,
978 EXYNOS5440_MAX_GPIO_INT,
979 &exynos5440_gpio_irqd_ops, priv);
980 if (!priv->irq_domain) {
981 dev_err(dev, "failed to create irq domain\n");
982 return -ENXIO;
983 }
984
985 return 0;
986}
987
988static int exynos5440_pinctrl_probe(struct platform_device *pdev)
989{
990 struct device *dev = &pdev->dev;
991 struct exynos5440_pinctrl_priv_data *priv;
992 struct resource *res;
993 int ret;
994
995 if (!dev->of_node) {
996 dev_err(dev, "device tree node not found\n");
997 return -ENODEV;
998 }
999
1000 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1001 if (!priv) {
1002 dev_err(dev, "could not allocate memory for private data\n");
1003 return -ENOMEM;
1004 }
1005
1006 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1007 priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
1008 if (IS_ERR(priv->reg_base))
1009 return PTR_ERR(priv->reg_base);
1010
1011 ret = exynos5440_gpiolib_register(pdev, priv);
1012 if (ret)
1013 return ret;
1014
1015 ret = exynos5440_pinctrl_register(pdev, priv);
1016 if (ret) {
1017 exynos5440_gpiolib_unregister(pdev, priv);
1018 return ret;
1019 }
1020
1021 ret = exynos5440_gpio_irq_init(pdev, priv);
1022 if (ret) {
1023 dev_err(dev, "failed to setup gpio interrupts\n");
1024 return ret;
1025 }
1026
1027 platform_set_drvdata(pdev, priv);
1028 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
1029 return 0;
1030}
1031
1032static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
1033 { .compatible = "samsung,exynos5440-pinctrl" },
1034 {},
1035};
1036MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
1037
1038static struct platform_driver exynos5440_pinctrl_driver = {
1039 .probe = exynos5440_pinctrl_probe,
1040 .driver = {
1041 .name = "exynos5440-pinctrl",
1042 .owner = THIS_MODULE,
1043 .of_match_table = exynos5440_pinctrl_dt_match,
1044 },
1045};
1046
1047static int __init exynos5440_pinctrl_drv_register(void)
1048{
1049 return platform_driver_register(&exynos5440_pinctrl_driver);
1050}
1051postcore_initcall(exynos5440_pinctrl_drv_register);
1052
1053static void __exit exynos5440_pinctrl_drv_unregister(void)
1054{
1055 platform_driver_unregister(&exynos5440_pinctrl_driver);
1056}
1057module_exit(exynos5440_pinctrl_drv_unregister);
1058
1059MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1060MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
1061MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 14:19:52 -0500