1 files changed, 333 insertions, 68 deletions

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index bb805d5e9ff0..5e8b2e04cd7a 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -62,11 +62,26 @@ enum rockchip_pinctrl_type {
         RK2928,
         RK3066B,
         RK3188,
+        RK3288,
 };
 
-enum rockchip_pin_bank_type {
-        COMMON_BANK,
-        RK3188_BANK0,
+/**
+ * Encode variants of iomux registers into a type variable
+ */
+#define IOMUX_GPIO_ONLY         BIT(0)
+#define IOMUX_WIDTH_4BIT        BIT(1)
+#define IOMUX_SOURCE_PMU        BIT(2)
+#define IOMUX_UNROUTED          BIT(3)
+
+/**
+ * @type: iomux variant using IOMUX_* constants
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ *          an initial offset value the relevant source offset can be reset
+ *          to a new value for autocalculating the following iomux registers.
+ */
+struct rockchip_iomux {
+        int                             type;
+        int                             offset;
 };
 
 /**
@@ -78,6 +93,7 @@ enum rockchip_pin_bank_type {
  * @nr_pins: number of pins in this bank
  * @name: name of the bank
  * @bank_num: number of the bank, to account for holes
+ * @iomux: array describing the 4 iomux sources of the bank
  * @valid: are all necessary informations present
  * @of_node: dt node of this bank
  * @drvdata: common pinctrl basedata
@@ -95,7 +111,7 @@ struct rockchip_pin_bank {
         u8                              nr_pins;
         char                            *name;
         u8                              bank_num;
-        enum rockchip_pin_bank_type     bank_type;
+        struct rockchip_iomux           iomux[4];
         bool                            valid;
         struct device_node              *of_node;
         struct rockchip_pinctrl         *drvdata;
@@ -111,6 +127,25 @@ struct rockchip_pin_bank {
                 .bank_num       = id,                   \
                 .nr_pins        = pins,                 \
                 .name           = label,                \
+                .iomux          = {                     \
+                        { .offset = -1 },               \
+                        { .offset = -1 },               \
+                        { .offset = -1 },               \
+                        { .offset = -1 },               \
+                },                                      \
+        }
+
+#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
+        {                                                               \
+                .bank_num       = id,                                   \
+                .nr_pins        = pins,                                 \
+                .name           = label,                                \
+                .iomux          = {                                     \
+                        { .type = iom0, .offset = -1 },                 \
+                        { .type = iom1, .offset = -1 },                 \
+                        { .type = iom2, .offset = -1 },                 \
+                        { .type = iom3, .offset = -1 },                 \
+                },                                                      \
         }
 
 /**
@@ -121,7 +156,8 @@ struct rockchip_pin_ctrl {
         u32                             nr_pins;
         char                            *label;
         enum rockchip_pinctrl_type      type;
-        int                             mux_offset;
+        int                             grf_mux_offset;
+        int                             pmu_mux_offset;
         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
                                     int pin_num, struct regmap **regmap,
                                     int *reg, u8 *bit);
@@ -343,24 +379,42 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 {
         struct rockchip_pinctrl *info = bank->drvdata;
+        int iomux_num = (pin / 8);
+        struct regmap *regmap;
         unsigned int val;
-        int reg, ret;
+        int reg, ret, mask;
         u8 bit;
 
-        if (bank->bank_type == RK3188_BANK0 && pin < 16)
+        if (iomux_num > 3)
+                return -EINVAL;
+
+        if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
+                dev_err(info->dev, "pin %d is unrouted\n", pin);
+                return -EINVAL;
+        }
+
+        if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
                 return RK_FUNC_GPIO;
 
+        regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+                                ? info->regmap_pmu : info->regmap_base;
+
         /* get basic quadrupel of mux registers and the correct reg inside */
-        reg = info->ctrl->mux_offset;
-        reg += bank->bank_num * 0x10;
-        reg += (pin / 8) * 4;
-        bit = (pin % 8) * 2;
+        mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
+        reg = bank->iomux[iomux_num].offset;
+        if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
+                if ((pin % 8) >= 4)
+                        reg += 0x4;
+                bit = (pin % 4) * 4;
+        } else {
+                bit = (pin % 8) * 2;
+        }
 
-        ret = regmap_read(info->regmap_base, reg, &val);
+        ret = regmap_read(regmap, reg, &val);
         if (ret)
                 return ret;
 
-        return ((val >> bit) & 3);
+        return ((val >> bit) & mask);
 }
 
 /*
@@ -379,16 +433,22 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 {
         struct rockchip_pinctrl *info = bank->drvdata;
-        int reg, ret;
+        int iomux_num = (pin / 8);
+        struct regmap *regmap;
+        int reg, ret, mask;
         unsigned long flags;
         u8 bit;
         u32 data;
 
-        /*
-         * The first 16 pins of rk3188_bank0 are always gpios and do not have
-         * a mux register at all.
-         */
-        if (bank->bank_type == RK3188_BANK0 && pin < 16) {
+        if (iomux_num > 3)
+                return -EINVAL;
+
+        if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
+                dev_err(info->dev, "pin %d is unrouted\n", pin);
+                return -EINVAL;
+        }
+
+        if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
                 if (mux != RK_FUNC_GPIO) {
                         dev_err(info->dev,
                                 "pin %d only supports a gpio mux\n", pin);
@@ -401,17 +461,25 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
                                                 bank->bank_num, pin, mux);
 
+        regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+                                ? info->regmap_pmu : info->regmap_base;
+
         /* get basic quadrupel of mux registers and the correct reg inside */
-        reg = info->ctrl->mux_offset;
-        reg += bank->bank_num * 0x10;
-        reg += (pin / 8) * 4;
-        bit = (pin % 8) * 2;
+        mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
+        reg = bank->iomux[iomux_num].offset;
+        if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
+                if ((pin % 8) >= 4)
+                        reg += 0x4;
+                bit = (pin % 4) * 4;
+        } else {
+                bit = (pin % 8) * 2;
+        }
 
         spin_lock_irqsave(&bank->slock, flags);
 
-        data = (3 << (bit + 16));
-        data |= (mux & 3) << bit;
-        ret = regmap_write(info->regmap_base, reg, data);
+        data = (mask << (bit + 16));
+        data |= (mux & mask) << bit;
+        ret = regmap_write(regmap, reg, data);
 
         spin_unlock_irqrestore(&bank->slock, flags);
 
@@ -449,7 +517,7 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
         struct rockchip_pinctrl *info = bank->drvdata;
 
         /* The first 12 pins of the first bank are located elsewhere */
-        if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
+        if (bank->bank_num == 0 && pin_num < 12) {
                 *regmap = info->regmap_pmu ? info->regmap_pmu
                                            : bank->regmap_pull;
                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
@@ -476,6 +544,127 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
         }
 }
 
+#define RK3288_PULL_OFFSET              0x140
+static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+                                    int pin_num, struct regmap **regmap,
+                                    int *reg, u8 *bit)
+{
+        struct rockchip_pinctrl *info = bank->drvdata;
+
+        /* The first 24 pins of the first bank are located in PMU */
+        if (bank->bank_num == 0) {
+                *regmap = info->regmap_pmu;
+                *reg = RK3188_PULL_PMU_OFFSET;
+
+                *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+                *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+                *bit *= RK3188_PULL_BITS_PER_PIN;
+        } else {
+                *regmap = info->regmap_base;
+                *reg = RK3288_PULL_OFFSET;
+
+                /* correct the offset, as we're starting with the 2nd bank */
+                *reg -= 0x10;
+                *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+                *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+                *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+                *bit *= RK3188_PULL_BITS_PER_PIN;
+        }
+}
+
+#define RK3288_DRV_PMU_OFFSET           0x70
+#define RK3288_DRV_GRF_OFFSET           0x1c0
+#define RK3288_DRV_BITS_PER_PIN         2
+#define RK3288_DRV_PINS_PER_REG         8
+#define RK3288_DRV_BANK_STRIDE          16
+static int rk3288_drv_list[] = { 2, 4, 8, 12 };
+
+static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+                                    int pin_num, struct regmap **regmap,
+                                    int *reg, u8 *bit)
+{
+        struct rockchip_pinctrl *info = bank->drvdata;
+
+        /* The first 24 pins of the first bank are located in PMU */
+        if (bank->bank_num == 0) {
+                *regmap = info->regmap_pmu;
+                *reg = RK3288_DRV_PMU_OFFSET;
+
+                *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+                *bit = pin_num % RK3288_DRV_PINS_PER_REG;
+                *bit *= RK3288_DRV_BITS_PER_PIN;
+        } else {
+                *regmap = info->regmap_base;
+                *reg = RK3288_DRV_GRF_OFFSET;
+
+                /* correct the offset, as we're starting with the 2nd bank */
+                *reg -= 0x10;
+                *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
+                *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+
+                *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
+                *bit *= RK3288_DRV_BITS_PER_PIN;
+        }
+}
+
+static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
+{
+        struct regmap *regmap;
+        int reg, ret;
+        u32 data;
+        u8 bit;
+
+        rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+        ret = regmap_read(regmap, reg, &data);
+        if (ret)
+                return ret;
+
+        data >>= bit;
+        data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
+
+        return rk3288_drv_list[data];
+}
+
+static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
+                            int strength)
+{
+        struct rockchip_pinctrl *info = bank->drvdata;
+        struct regmap *regmap;
+        unsigned long flags;
+        int reg, ret, i;
+        u32 data;
+        u8 bit;
+
+        rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+        ret = -EINVAL;
+        for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
+                if (rk3288_drv_list[i] == strength) {
+                        ret = i;
+                        break;
+                }
+        }
+
+        if (ret < 0) {
+                dev_err(info->dev, "unsupported driver strength %d\n",
+                        strength);
+                return ret;
+        }
+
+        spin_lock_irqsave(&bank->slock, flags);
+
+        /* enable the write to the equivalent lower bits */
+        data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+        data |= (ret << bit);
+
+        ret = regmap_write(regmap, reg, data);
+        spin_unlock_irqrestore(&bank->slock, flags);
+
+        return ret;
+}
+
 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 {
         struct rockchip_pinctrl *info = bank->drvdata;
@@ -501,6 +690,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
                                 : PIN_CONFIG_BIAS_DISABLE;
         case RK3188:
+        case RK3288:
                 data >>= bit;
                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 
@@ -555,6 +745,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
                 spin_unlock_irqrestore(&bank->slock, flags);
                 break;
         case RK3188:
+        case RK3288:
                 spin_lock_irqsave(&bank->slock, flags);
 
                 /* enable the write to the equivalent lower bits */
@@ -657,23 +848,6 @@ static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
         return 0;
 }
 
-static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
-                                        unsigned selector, unsigned group)
-{
-        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
-        const unsigned int *pins = info->groups[group].pins;
-        struct rockchip_pin_bank *bank;
-        int cnt;
-
-        dev_dbg(info->dev, "disable function %s group %s\n",
-                info->functions[selector].name, info->groups[group].name);
-
-        for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
-                bank = pin_to_bank(info, pins[cnt]);
-                rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
-        }
-}
-
 /*
  * The calls to gpio_direction_output() and gpio_direction_input()
  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
@@ -716,7 +890,6 @@ static const struct pinmux_ops rockchip_pmx_ops = {
         .get_function_name      = rockchip_pmx_get_func_name,
         .get_function_groups    = rockchip_pmx_get_groups,
         .enable                 = rockchip_pmx_enable,
-        .disable                = rockchip_pmx_disable,
         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 };
 
@@ -734,6 +907,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
         case RK3066B:
                 return pull ? false : true;
         case RK3188:
+        case RK3288:
                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
         }
 
@@ -788,6 +962,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
                         if (rc)
                                 return rc;
                         break;
+                case PIN_CONFIG_DRIVE_STRENGTH:
+                        /* rk3288 is the first with per-pin drive-strength */
+                        if (info->ctrl->type != RK3288)
+                                return -ENOTSUPP;
+
+                        rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
+                        if (rc < 0)
+                                return rc;
+                        break;
                 default:
                         return -ENOTSUPP;
                         break;
@@ -837,6 +1020,17 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 
                 arg = rc ? 1 : 0;
                 break;
+        case PIN_CONFIG_DRIVE_STRENGTH:
+                /* rk3288 is the first with per-pin drive-strength */
+                if (info->ctrl->type != RK3288)
+                        return -ENOTSUPP;
+
+                rc = rk3288_get_drive(bank, pin - bank->pin_base);
+                if (rc < 0)
+                        return rc;
+
+                arg = rc;
+                break;
         default:
                 return -ENOTSUPP;
                 break;
@@ -850,6 +1044,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 static const struct pinconf_ops rockchip_pinconf_ops = {
         .pin_config_get                 = rockchip_pinconf_get,
         .pin_config_set                 = rockchip_pinconf_set,
+        .is_generic                     = true,
 };
 
 static const struct of_device_id rockchip_bank_match[] = {
@@ -1414,10 +1609,7 @@ fail:
         for (--i, --bank; i >= 0; --i, --bank) {
                 if (!bank->valid)
                         continue;
-
-                if (gpiochip_remove(&bank->gpio_chip))
-                        dev_err(&pdev->dev, "gpio chip %s remove failed\n",
-                                                        bank->gpio_chip.label);
+                gpiochip_remove(&bank->gpio_chip);
         }
         return ret;
 }
@@ -1427,20 +1619,15 @@ static int rockchip_gpiolib_unregister(struct platform_device *pdev,
 {
         struct rockchip_pin_ctrl *ctrl = info->ctrl;
         struct rockchip_pin_bank *bank = ctrl->pin_banks;
-        int ret = 0;
         int i;
 
-        for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
+        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
                 if (!bank->valid)
                         continue;
-
-                ret = gpiochip_remove(&bank->gpio_chip);
+                gpiochip_remove(&bank->gpio_chip);
         }
 
-        if (ret)
-                dev_err(&pdev->dev, "gpio chip remove failed\n");
-
-        return ret;
+        return 0;
 }
 
 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
@@ -1466,8 +1653,6 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
                                     "rockchip,rk3188-gpio-bank0")) {
                 struct device_node *node;
 
-                bank->bank_type = RK3188_BANK0;
-
                 node = of_parse_phandle(bank->of_node->parent,
                                         "rockchip,pmu", 0);
                 if (!node) {
@@ -1487,9 +1672,6 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
                                                     base,
                                                     &rockchip_regmap_config);
                 }
-
-        } else {
-                bank->bank_type = COMMON_BANK;
         }
 
         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
@@ -1513,7 +1695,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
         struct device_node *np;
         struct rockchip_pin_ctrl *ctrl;
         struct rockchip_pin_bank *bank;
-        int i;
+        int grf_offs, pmu_offs, i, j;
 
         match = of_match_node(rockchip_pinctrl_dt_match, node);
         ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -1535,12 +1717,51 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
                 }
         }
 
+        grf_offs = ctrl->grf_mux_offset;
+        pmu_offs = ctrl->pmu_mux_offset;
         bank = ctrl->pin_banks;
         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+                int bank_pins = 0;
+
                 spin_lock_init(&bank->slock);
                 bank->drvdata = d;
                 bank->pin_base = ctrl->nr_pins;
                 ctrl->nr_pins += bank->nr_pins;
+
+                /* calculate iomux offsets */
+                for (j = 0; j < 4; j++) {
+                        struct rockchip_iomux *iom = &bank->iomux[j];
+                        int inc;
+
+                        if (bank_pins >= bank->nr_pins)
+                                break;
+
+                        /* preset offset value, set new start value */
+                        if (iom->offset >= 0) {
+                                if (iom->type & IOMUX_SOURCE_PMU)
+                                        pmu_offs = iom->offset;
+                                else
+                                        grf_offs = iom->offset;
+                        } else { /* set current offset */
+                                iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+                                                        pmu_offs : grf_offs;
+                        }
+
+                        dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
+                                 i, j, iom->offset);
+
+                        /*
+                         * Increase offset according to iomux width.
+                         * 4bit iomux'es are spread over two registers.
+                         */
+                        inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
+                        if (iom->type & IOMUX_SOURCE_PMU)
+                                pmu_offs += inc;
+                        else
+                                grf_offs += inc;
+
+                        bank_pins += 8;
+                }
         }
 
         return ctrl;
@@ -1644,7 +1865,7 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
                 .label                  = "RK2928-GPIO",
                 .type                   = RK2928,
-                .mux_offset             = 0xa8,
+                .grf_mux_offset         = 0xa8,
                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
 };
 
@@ -1662,7 +1883,7 @@ static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
                 .label                  = "RK3066a-GPIO",
                 .type                   = RK2928,
-                .mux_offset             = 0xa8,
+                .grf_mux_offset         = 0xa8,
                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
 };
 
@@ -1678,11 +1899,11 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
                 .label          = "RK3066b-GPIO",
                 .type           = RK3066B,
-                .mux_offset     = 0x60,
+                .grf_mux_offset = 0x60,
 };
 
 static struct rockchip_pin_bank rk3188_pin_banks[] = {
-        PIN_BANK(0, 32, "gpio0"),
+        PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
         PIN_BANK(1, 32, "gpio1"),
         PIN_BANK(2, 32, "gpio2"),
         PIN_BANK(3, 32, "gpio3"),
@@ -1693,10 +1914,52 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
                 .label                  = "RK3188-GPIO",
                 .type                   = RK3188,
-                .mux_offset             = 0x60,
+                .grf_mux_offset         = 0x60,
                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
 };
 
+static struct rockchip_pin_bank rk3288_pin_banks[] = {
+        PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
+                                             IOMUX_SOURCE_PMU,
+                                             IOMUX_SOURCE_PMU,
+                                             IOMUX_UNROUTED
+                            ),
+        PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
+                                             IOMUX_UNROUTED,
+                                             IOMUX_UNROUTED,
+                                             0
+                            ),
+        PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
+        PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
+        PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT,
+                                             0,
+                                             0
+                            ),
+        PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
+                                             0,
+                                             0,
+                                             IOMUX_UNROUTED
+                            ),
+        PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
+        PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
+                                             0,
+                                             IOMUX_WIDTH_4BIT,
+                                             IOMUX_UNROUTED
+                            ),
+        PIN_BANK(8, 16, "gpio8"),
+};
+
+static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
+                .pin_banks              = rk3288_pin_banks,
+                .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
+                .label                  = "RK3288-GPIO",
+                .type                   = RK3288,
+                .grf_mux_offset         = 0x0,
+                .pmu_mux_offset         = 0x84,
+                .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
+};
+
 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
         { .compatible = "rockchip,rk2928-pinctrl",
                 .data = (void *)&rk2928_pin_ctrl },
@@ -1706,6 +1969,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
                 .data = (void *)&rk3066b_pin_ctrl },
         { .compatible = "rockchip,rk3188-pinctrl",
                 .data = (void *)&rk3188_pin_ctrl },
+        { .compatible = "rockchip,rk3288-pinctrl",
+                .data = (void *)&rk3288_pin_ctrl },
         {},
 };
 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);