dw_dmac: Pass Channel Priority from platform_data

In Synopsys designware, channel priority is programmable. This patch adds
support for passing channel priority through platform data. By default Ascending
channel priority will be followed, i.e. channel 0 will get highest priority and
channel 7 will get lowest.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

1 files changed, 10 insertions, 1 deletions

diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index f413e123405a..318a342fc7ec 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -901,8 +901,11 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 
                 cfghi = dws->cfg_hi;
-                cfglo = dws->cfg_lo;
+                cfglo = dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
         }
+
+        cfglo |= DWC_CFGL_CH_PRIOR(dwc->priority);
+
         channel_writel(dwc, CFG_LO, cfglo);
         channel_writel(dwc, CFG_HI, cfghi);
 
@@ -1325,6 +1328,12 @@ static int __init dw_probe(struct platform_device *pdev)
                 else
                         list_add(&dwc->chan.device_node, &dw->dma.channels);
 
+                /* 7 is highest priority & 0 is lowest. */
+                if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
+                        dwc->priority = 7 - i;
+                else
+                        dwc->priority = i;
+
                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
                 spin_lock_init(&dwc->lock);
                 dwc->mask = 1 << i;