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-rw-r--r--drivers/dma/dw_dmac.c11
-rw-r--r--drivers/dma/dw_dmac_regs.h3
-rw-r--r--include/linux/dw_dmac.h4
3 files changed, 16 insertions, 2 deletions
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index f413e123405a..318a342fc7ec 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -901,8 +901,11 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
901 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); 901 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
902 902
903 cfghi = dws->cfg_hi; 903 cfghi = dws->cfg_hi;
904 cfglo = dws->cfg_lo; 904 cfglo = dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
905 } 905 }
906
907 cfglo |= DWC_CFGL_CH_PRIOR(dwc->priority);
908
906 channel_writel(dwc, CFG_LO, cfglo); 909 channel_writel(dwc, CFG_LO, cfglo);
907 channel_writel(dwc, CFG_HI, cfghi); 910 channel_writel(dwc, CFG_HI, cfghi);
908 911
@@ -1325,6 +1328,12 @@ static int __init dw_probe(struct platform_device *pdev)
1325 else 1328 else
1326 list_add(&dwc->chan.device_node, &dw->dma.channels); 1329 list_add(&dwc->chan.device_node, &dw->dma.channels);
1327 1330
1331 /* 7 is highest priority & 0 is lowest. */
1332 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1333 dwc->priority = 7 - i;
1334 else
1335 dwc->priority = i;
1336
1328 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; 1337 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1329 spin_lock_init(&dwc->lock); 1338 spin_lock_init(&dwc->lock);
1330 dwc->mask = 1 << i; 1339 dwc->mask = 1 << i;
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index d9a939f67f46..6a8e6d35f359 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -101,6 +101,8 @@ struct dw_dma_regs {
101#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff 101#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
102 102
103/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */ 103/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
104#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
105#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
104#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ 106#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
105#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ 107#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
106#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ 108#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
@@ -134,6 +136,7 @@ struct dw_dma_chan {
134 struct dma_chan chan; 136 struct dma_chan chan;
135 void __iomem *ch_regs; 137 void __iomem *ch_regs;
136 u8 mask; 138 u8 mask;
139 u8 priority;
137 140
138 spinlock_t lock; 141 spinlock_t lock;
139 142
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index a18c498984d9..64c76da571ef 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -25,6 +25,9 @@ struct dw_dma_platform_data {
25#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 25#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
26#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 26#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
27 unsigned char chan_allocation_order; 27 unsigned char chan_allocation_order;
28#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
29#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
30 unsigned char chan_priority;
28}; 31};
29 32
30/** 33/**
@@ -70,7 +73,6 @@ struct dw_dma_slave {
70#define DWC_CFGH_DST_PER(x) ((x) << 11) 73#define DWC_CFGH_DST_PER(x) ((x) << 11)
71 74
72/* Platform-configurable bits in CFG_LO */ 75/* Platform-configurable bits in CFG_LO */
73#define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */
74#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ 76#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
75#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) 77#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
76#define DWC_CFGL_LOCK_CH_XACT (2 << 12) 78#define DWC_CFGL_LOCK_CH_XACT (2 << 12)