dw_dmac: Pass Channel Priority from platform_data

In Synopsys designware, channel priority is programmable. This patch adds
support for passing channel priority through platform data. By default Ascending
channel priority will be followed, i.e. channel 0 will get highest priority and
channel 7 will get lowest.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

2 files changed, 13 insertions, 1 deletions

diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index f413e123405a..318a342fc7ec 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -901,8 +901,11 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 
                 cfghi = dws->cfg_hi;
-                cfglo = dws->cfg_lo;
+                cfglo = dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
         }
+
+        cfglo |= DWC_CFGL_CH_PRIOR(dwc->priority);
+
         channel_writel(dwc, CFG_LO, cfglo);
         channel_writel(dwc, CFG_HI, cfghi);
 
@@ -1325,6 +1328,12 @@ static int __init dw_probe(struct platform_device *pdev)
                 else
                         list_add(&dwc->chan.device_node, &dw->dma.channels);
 
+                /* 7 is highest priority & 0 is lowest. */
+                if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
+                        dwc->priority = 7 - i;
+                else
+                        dwc->priority = i;
+
                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
                 spin_lock_init(&dwc->lock);
                 dwc->mask = 1 << i;
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index d9a939f67f46..6a8e6d35f359 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -101,6 +101,8 @@ struct dw_dma_regs {
 #define DWC_CTLH_BLOCK_TS_MASK  0x00000fff
 
 /* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
+#define DWC_CFGL_CH_PRIOR_MASK  (0x7 << 5)      /* priority mask */
+#define DWC_CFGL_CH_PRIOR(x)    ((x) << 5)      /* priority */
 #define DWC_CFGL_CH_SUSP        (1 << 8)        /* pause xfer */
 #define DWC_CFGL_FIFO_EMPTY     (1 << 9)        /* pause xfer */
 #define DWC_CFGL_HS_DST         (1 << 10)       /* handshake w/dst */
@@ -134,6 +136,7 @@ struct dw_dma_chan {
         struct dma_chan         chan;
         void __iomem            *ch_regs;
         u8                      mask;
+        u8                      priority;
 
         spinlock_t              lock;