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authorChris Metcalf <cmetcalf@tilera.com>2013-07-23 17:32:04 -0400
committerChris Metcalf <cmetcalf@tilera.com>2013-07-31 11:51:19 -0400
commitdd78bc11fb2050b6a3990d0421feca4c68ca4335 (patch)
tree7147fe5e0b3815443eea608d3dd0950ba53bb47d /arch/tile/include/asm
parent7d937719e3c5c6c9ad00584f6b62230d2ef7f9f1 (diff)
tile: convert uses of "inv" to "finv"
The "inv" (invalidate) instruction is generally less safe than "finv" (flush and invalidate), as it will drop dirty data from the cache. It turns out we have almost no need for "inv" (other than for the older 32-bit architecture in some limited cases), so convert to "finv" where possible and delete the extra "inv" infrastructure. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm')
-rw-r--r--arch/tile/include/asm/cacheflush.h44
-rw-r--r--arch/tile/include/asm/uaccess.h31
2 files changed, 20 insertions, 55 deletions
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
index 0fc63c488edf..92ee4c8a4f76 100644
--- a/arch/tile/include/asm/cacheflush.h
+++ b/arch/tile/include/asm/cacheflush.h
@@ -75,23 +75,6 @@ static inline void copy_to_user_page(struct vm_area_struct *vma,
75#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 75#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
76 memcpy((dst), (src), (len)) 76 memcpy((dst), (src), (len))
77 77
78/*
79 * Invalidate a VA range; pads to L2 cacheline boundaries.
80 *
81 * Note that on TILE64, __inv_buffer() actually flushes modified
82 * cache lines in addition to invalidating them, i.e., it's the
83 * same as __finv_buffer().
84 */
85static inline void __inv_buffer(void *buffer, size_t size)
86{
87 char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
88 char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
89 while (next < finish) {
90 __insn_inv(next);
91 next += CHIP_INV_STRIDE();
92 }
93}
94
95/* Flush a VA range; pads to L2 cacheline boundaries. */ 78/* Flush a VA range; pads to L2 cacheline boundaries. */
96static inline void __flush_buffer(void *buffer, size_t size) 79static inline void __flush_buffer(void *buffer, size_t size)
97{ 80{
@@ -115,13 +98,6 @@ static inline void __finv_buffer(void *buffer, size_t size)
115} 98}
116 99
117 100
118/* Invalidate a VA range and wait for it to be complete. */
119static inline void inv_buffer(void *buffer, size_t size)
120{
121 __inv_buffer(buffer, size);
122 mb();
123}
124
125/* 101/*
126 * Flush a locally-homecached VA range and wait for the evicted 102 * Flush a locally-homecached VA range and wait for the evicted
127 * cachelines to hit memory. 103 * cachelines to hit memory.
@@ -142,6 +118,26 @@ static inline void finv_buffer_local(void *buffer, size_t size)
142 mb_incoherent(); 118 mb_incoherent();
143} 119}
144 120
121#ifdef __tilepro__
122/* Invalidate a VA range; pads to L2 cacheline boundaries. */
123static inline void __inv_buffer(void *buffer, size_t size)
124{
125 char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
126 char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
127 while (next < finish) {
128 __insn_inv(next);
129 next += CHIP_INV_STRIDE();
130 }
131}
132
133/* Invalidate a VA range and wait for it to be complete. */
134static inline void inv_buffer(void *buffer, size_t size)
135{
136 __inv_buffer(buffer, size);
137 mb();
138}
139#endif
140
145/* 141/*
146 * Flush and invalidate a VA range that is homed remotely, waiting 142 * Flush and invalidate a VA range that is homed remotely, waiting
147 * until the memory controller holds the flushed values. If "hfh" is 143 * until the memory controller holds the flushed values. If "hfh" is
diff --git a/arch/tile/include/asm/uaccess.h b/arch/tile/include/asm/uaccess.h
index e4d44bd7df27..f68503f8e0aa 100644
--- a/arch/tile/include/asm/uaccess.h
+++ b/arch/tile/include/asm/uaccess.h
@@ -567,37 +567,6 @@ static inline unsigned long __must_check flush_user(
567} 567}
568 568
569/** 569/**
570 * inv_user: - Invalidate a block of memory in user space from cache.
571 * @mem: Destination address, in user space.
572 * @len: Number of bytes to invalidate.
573 *
574 * Returns number of bytes that could not be invalidated.
575 * On success, this will be zero.
576 *
577 * Note that on Tile64, the "inv" operation is in fact a
578 * "flush and invalidate", so cache write-backs will occur prior
579 * to the cache being marked invalid.
580 */
581extern unsigned long inv_user_asm(void __user *mem, unsigned long len);
582static inline unsigned long __must_check __inv_user(
583 void __user *mem, unsigned long len)
584{
585 int retval;
586
587 might_fault();
588 retval = inv_user_asm(mem, len);
589 mb_incoherent();
590 return retval;
591}
592static inline unsigned long __must_check inv_user(
593 void __user *mem, unsigned long len)
594{
595 if (access_ok(VERIFY_WRITE, mem, len))
596 return __inv_user(mem, len);
597 return len;
598}
599
600/**
601 * finv_user: - Flush-inval a block of memory in user space from cache. 570 * finv_user: - Flush-inval a block of memory in user space from cache.
602 * @mem: Destination address, in user space. 571 * @mem: Destination address, in user space.
603 * @len: Number of bytes to invalidate. 572 * @len: Number of bytes to invalidate.