diff options
Diffstat (limited to 'arch/tile/include/asm/cacheflush.h')
-rw-r--r-- | arch/tile/include/asm/cacheflush.h | 44 |
1 files changed, 20 insertions, 24 deletions
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h index 0fc63c488edf..92ee4c8a4f76 100644 --- a/arch/tile/include/asm/cacheflush.h +++ b/arch/tile/include/asm/cacheflush.h | |||
@@ -75,23 +75,6 @@ static inline void copy_to_user_page(struct vm_area_struct *vma, | |||
75 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | 75 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
76 | memcpy((dst), (src), (len)) | 76 | memcpy((dst), (src), (len)) |
77 | 77 | ||
78 | /* | ||
79 | * Invalidate a VA range; pads to L2 cacheline boundaries. | ||
80 | * | ||
81 | * Note that on TILE64, __inv_buffer() actually flushes modified | ||
82 | * cache lines in addition to invalidating them, i.e., it's the | ||
83 | * same as __finv_buffer(). | ||
84 | */ | ||
85 | static inline void __inv_buffer(void *buffer, size_t size) | ||
86 | { | ||
87 | char *next = (char *)((long)buffer & -L2_CACHE_BYTES); | ||
88 | char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size); | ||
89 | while (next < finish) { | ||
90 | __insn_inv(next); | ||
91 | next += CHIP_INV_STRIDE(); | ||
92 | } | ||
93 | } | ||
94 | |||
95 | /* Flush a VA range; pads to L2 cacheline boundaries. */ | 78 | /* Flush a VA range; pads to L2 cacheline boundaries. */ |
96 | static inline void __flush_buffer(void *buffer, size_t size) | 79 | static inline void __flush_buffer(void *buffer, size_t size) |
97 | { | 80 | { |
@@ -115,13 +98,6 @@ static inline void __finv_buffer(void *buffer, size_t size) | |||
115 | } | 98 | } |
116 | 99 | ||
117 | 100 | ||
118 | /* Invalidate a VA range and wait for it to be complete. */ | ||
119 | static inline void inv_buffer(void *buffer, size_t size) | ||
120 | { | ||
121 | __inv_buffer(buffer, size); | ||
122 | mb(); | ||
123 | } | ||
124 | |||
125 | /* | 101 | /* |
126 | * Flush a locally-homecached VA range and wait for the evicted | 102 | * Flush a locally-homecached VA range and wait for the evicted |
127 | * cachelines to hit memory. | 103 | * cachelines to hit memory. |
@@ -142,6 +118,26 @@ static inline void finv_buffer_local(void *buffer, size_t size) | |||
142 | mb_incoherent(); | 118 | mb_incoherent(); |
143 | } | 119 | } |
144 | 120 | ||
121 | #ifdef __tilepro__ | ||
122 | /* Invalidate a VA range; pads to L2 cacheline boundaries. */ | ||
123 | static inline void __inv_buffer(void *buffer, size_t size) | ||
124 | { | ||
125 | char *next = (char *)((long)buffer & -L2_CACHE_BYTES); | ||
126 | char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size); | ||
127 | while (next < finish) { | ||
128 | __insn_inv(next); | ||
129 | next += CHIP_INV_STRIDE(); | ||
130 | } | ||
131 | } | ||
132 | |||
133 | /* Invalidate a VA range and wait for it to be complete. */ | ||
134 | static inline void inv_buffer(void *buffer, size_t size) | ||
135 | { | ||
136 | __inv_buffer(buffer, size); | ||
137 | mb(); | ||
138 | } | ||
139 | #endif | ||
140 | |||
145 | /* | 141 | /* |
146 | * Flush and invalidate a VA range that is homed remotely, waiting | 142 | * Flush and invalidate a VA range that is homed remotely, waiting |
147 | * until the memory controller holds the flushed values. If "hfh" is | 143 | * until the memory controller holds the flushed values. If "hfh" is |