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authorPaul Mackerras <paulus@samba.org>2008-06-09 00:01:46 -0400
committerPaul Mackerras <paulus@samba.org>2008-06-10 07:40:22 -0400
commit917f0af9e5a9ceecf9e72537fabb501254ba321d (patch)
tree1ef207755c6d83ce4af93ef2b5e4645eebd65886 /arch/ppc/platforms
parent0f3d6bcd391b058c619fc30e8022e8a29fbf4bef (diff)
powerpc: Remove arch/ppc and include/asm-ppc
All the maintained platforms are now in arch/powerpc, so the old arch/ppc stuff can now go away. Acked-by: Adrian Bunk <bunk@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Jochen Friedrich <jochen@scram.de> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Sean MacLennan <smaclennan@pikatech.com> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/4xx/Kconfig285
-rw-r--r--arch/ppc/platforms/4xx/Makefile31
-rw-r--r--arch/ppc/platforms/4xx/bamboo.c442
-rw-r--r--arch/ppc/platforms/4xx/bamboo.h133
-rw-r--r--arch/ppc/platforms/4xx/bubinga.c265
-rw-r--r--arch/ppc/platforms/4xx/bubinga.h54
-rw-r--r--arch/ppc/platforms/4xx/cpci405.c201
-rw-r--r--arch/ppc/platforms/4xx/cpci405.h28
-rw-r--r--arch/ppc/platforms/4xx/ebony.c334
-rw-r--r--arch/ppc/platforms/4xx/ebony.h97
-rw-r--r--arch/ppc/platforms/4xx/ep405.c196
-rw-r--r--arch/ppc/platforms/4xx/ep405.h52
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.c141
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.h145
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.c120
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.h148
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.c115
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.h148
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.c220
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.h73
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.c163
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.h63
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.c231
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.h71
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.c129
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.h61
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.c170
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.h154
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.c122
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.h235
-rw-r--r--arch/ppc/platforms/4xx/ibmstbx25.c66
-rw-r--r--arch/ppc/platforms/4xx/ibmstbx25.h258
-rw-r--r--arch/ppc/platforms/4xx/luan.c371
-rw-r--r--arch/ppc/platforms/4xx/luan.h77
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c350
-rw-r--r--arch/ppc/platforms/4xx/ocotea.h94
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.c146
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.h63
-rw-r--r--arch/ppc/platforms/4xx/redwood5.c120
-rw-r--r--arch/ppc/platforms/4xx/redwood5.h52
-rw-r--r--arch/ppc/platforms/4xx/redwood6.c156
-rw-r--r--arch/ppc/platforms/4xx/redwood6.h53
-rw-r--r--arch/ppc/platforms/4xx/sycamore.c272
-rw-r--r--arch/ppc/platforms/4xx/sycamore.h49
-rw-r--r--arch/ppc/platforms/4xx/taishan.c395
-rw-r--r--arch/ppc/platforms/4xx/taishan.h67
-rw-r--r--arch/ppc/platforms/4xx/virtex.h35
-rw-r--r--arch/ppc/platforms/4xx/walnut.c246
-rw-r--r--arch/ppc/platforms/4xx/walnut.h52
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml300.c118
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml403.c120
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters.h104
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h310
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h243
-rw-r--r--arch/ppc/platforms/4xx/yucca.c393
-rw-r--r--arch/ppc/platforms/4xx/yucca.h108
-rw-r--r--arch/ppc/platforms/Makefile25
-rw-r--r--arch/ppc/platforms/bseip.h38
-rw-r--r--arch/ppc/platforms/ccm.h27
-rw-r--r--arch/ppc/platforms/chestnut.c574
-rw-r--r--arch/ppc/platforms/chestnut.h127
-rw-r--r--arch/ppc/platforms/cpci690.c453
-rw-r--r--arch/ppc/platforms/cpci690.h74
-rw-r--r--arch/ppc/platforms/est8260.h35
-rw-r--r--arch/ppc/platforms/ev64260.c649
-rw-r--r--arch/ppc/platforms/ev64260.h126
-rw-r--r--arch/ppc/platforms/ev64360.c517
-rw-r--r--arch/ppc/platforms/ev64360.h114
-rw-r--r--arch/ppc/platforms/fads.h130
-rw-r--r--arch/ppc/platforms/hdpu.c1015
-rw-r--r--arch/ppc/platforms/hdpu.h80
-rw-r--r--arch/ppc/platforms/hermes.h26
-rw-r--r--arch/ppc/platforms/ip860.h35
-rw-r--r--arch/ppc/platforms/ivms8.h55
-rw-r--r--arch/ppc/platforms/katana.c902
-rw-r--r--arch/ppc/platforms/katana.h253
-rw-r--r--arch/ppc/platforms/lantec.h20
-rw-r--r--arch/ppc/platforms/lite5200.c245
-rw-r--r--arch/ppc/platforms/lite5200.h21
-rw-r--r--arch/ppc/platforms/lopec.c310
-rw-r--r--arch/ppc/platforms/lopec.h39
-rw-r--r--arch/ppc/platforms/lwmon.h59
-rw-r--r--arch/ppc/platforms/mbx.h117
-rw-r--r--arch/ppc/platforms/mpc866ads_setup.c413
-rw-r--r--arch/ppc/platforms/mvme5100.c340
-rw-r--r--arch/ppc/platforms/mvme5100.h91
-rw-r--r--arch/ppc/platforms/pal4.h40
-rw-r--r--arch/ppc/platforms/pal4_pci.c75
-rw-r--r--arch/ppc/platforms/pal4_serial.h37
-rw-r--r--arch/ppc/platforms/pal4_setup.c173
-rw-r--r--arch/ppc/platforms/pcu_e.h27
-rw-r--r--arch/ppc/platforms/powerpmc250.c378
-rw-r--r--arch/ppc/platforms/powerpmc250.h52
-rw-r--r--arch/ppc/platforms/pplus.c844
-rw-r--r--arch/ppc/platforms/pplus.h65
-rw-r--r--arch/ppc/platforms/prep_pci.c1339
-rw-r--r--arch/ppc/platforms/prep_setup.c1043
-rw-r--r--arch/ppc/platforms/prpmc750.c360
-rw-r--r--arch/ppc/platforms/prpmc750.h95
-rw-r--r--arch/ppc/platforms/prpmc800.c472
-rw-r--r--arch/ppc/platforms/prpmc800.h82
-rw-r--r--arch/ppc/platforms/radstone_ppc7d.c1492
-rw-r--r--arch/ppc/platforms/radstone_ppc7d.h433
-rw-r--r--arch/ppc/platforms/residual.c1034
-rw-r--r--arch/ppc/platforms/rpx8260.h81
-rw-r--r--arch/ppc/platforms/rpxclassic.h114
-rw-r--r--arch/ppc/platforms/rpxlite.h91
-rw-r--r--arch/ppc/platforms/sandpoint.c651
-rw-r--r--arch/ppc/platforms/sandpoint.h75
-rw-r--r--arch/ppc/platforms/sbc82xx.c256
-rw-r--r--arch/ppc/platforms/sbc82xx.h36
-rw-r--r--arch/ppc/platforms/sbs8260.h28
-rw-r--r--arch/ppc/platforms/spruce.c322
-rw-r--r--arch/ppc/platforms/spruce.h71
-rw-r--r--arch/ppc/platforms/tqm8260.h22
-rw-r--r--arch/ppc/platforms/tqm8260_setup.c42
-rw-r--r--arch/ppc/platforms/tqm8xx.h155
117 files changed, 0 insertions, 25840 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
deleted file mode 100644
index 76551b679030..000000000000
--- a/arch/ppc/platforms/4xx/Kconfig
+++ /dev/null
@@ -1,285 +0,0 @@
1config 4xx
2 bool
3 depends on 40x || 44x
4 default y
5
6config WANT_EARLY_SERIAL
7 bool
8 select SERIAL_8250
9 default n
10
11menu "IBM 4xx options"
12 depends on 4xx
13
14choice
15 prompt "Machine Type"
16 depends on 40x
17 default WALNUT
18
19config BUBINGA
20 bool "Bubinga"
21 select WANT_EARLY_SERIAL
22 help
23 This option enables support for the IBM 405EP evaluation board.
24
25config CPCI405
26 bool "CPCI405"
27 help
28 This option enables support for the CPCI405 board.
29
30config EP405
31 bool "EP405/EP405PC"
32 select EMBEDDEDBOOT
33 help
34 This option enables support for the EP405/EP405PC boards.
35
36config REDWOOD_5
37 bool "Redwood-5"
38 help
39 This option enables support for the IBM STB04 evaluation board.
40
41config REDWOOD_6
42 bool "Redwood-6"
43 help
44 This option enables support for the IBM STBx25xx evaluation board.
45
46config SYCAMORE
47 bool "Sycamore"
48 help
49 This option enables support for the IBM PPC405GPr evaluation board.
50
51config WALNUT
52 bool "Walnut"
53 help
54 This option enables support for the IBM PPC405GP evaluation board.
55
56config XILINX_ML300
57 bool "Xilinx-ML300"
58 select XILINX_VIRTEX_II_PRO
59 select EMBEDDEDBOOT
60 help
61 This option enables support for the Xilinx ML300 evaluation board.
62
63config XILINX_ML403
64 bool "Xilinx-ML403"
65 select XILINX_VIRTEX_4_FX
66 select EMBEDDEDBOOT
67 help
68 This option enables support for the Xilinx ML403 evaluation board.
69endchoice
70
71choice
72 prompt "Machine Type"
73 depends on 44x
74 default EBONY
75
76config BAMBOO
77 bool "Bamboo"
78 select WANT_EARLY_SERIAL
79 help
80 This option enables support for the IBM PPC440EP evaluation board.
81
82config EBONY
83 bool "Ebony"
84 select WANT_EARLY_SERIAL
85 help
86 This option enables support for the IBM PPC440GP evaluation board.
87
88config LUAN
89 bool "Luan"
90 select WANT_EARLY_SERIAL
91 help
92 This option enables support for the IBM PPC440SP evaluation board.
93
94config YUCCA
95 bool "Yucca"
96 select WANT_EARLY_SERIAL
97 help
98 This option enables support for the AMCC PPC440SPe evaluation board.
99
100config OCOTEA
101 bool "Ocotea"
102 select WANT_EARLY_SERIAL
103 help
104 This option enables support for the IBM PPC440GX evaluation board.
105
106config TAISHAN
107 bool "Taishan"
108 select WANT_EARLY_SERIAL
109 help
110 This option enables support for the AMCC PPC440GX evaluation board.
111
112endchoice
113
114config EP405PC
115 bool "EP405PC Support"
116 depends on EP405
117
118
119# It's often necessary to know the specific 4xx processor type.
120# Fortunately, it is impled (so far) from the board type, so we
121# don't need to ask more redundant questions.
122config NP405H
123 bool
124 depends on ASH
125 default y
126
127config 440EP
128 bool
129 depends on BAMBOO
130 select PPC_FPU
131 default y
132
133config 440GP
134 bool
135 depends on EBONY
136 default y
137
138config 440GX
139 bool
140 depends on OCOTEA || TAISHAN
141 default y
142
143config 440SP
144 bool
145 depends on LUAN
146 default y
147
148config 440SPE
149 bool
150 depends on YUCCA
151 default y
152
153config 440
154 bool
155 depends on 440GP || 440SP || 440SPE || 440EP
156 default y
157
158config 440A
159 bool
160 depends on 440GX
161 default y
162
163config IBM440EP_ERR42
164 bool
165 depends on 440EP
166 default y
167
168# All 405-based cores up until the 405GPR and 405EP have this errata.
169config IBM405_ERR77
170 bool
171 depends on 40x && !403GCX && !405GPR && !405EP
172 default y
173
174# All 40x-based cores, up until the 405GPR and 405EP have this errata.
175config IBM405_ERR51
176 bool
177 depends on 40x && !405GPR && !405EP
178 default y
179
180config BOOKE
181 bool
182 depends on 44x
183 default y
184
185config IBM_OCP
186 bool
187 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT
188 default y
189
190config IBM_EMAC4
191 bool
192 depends on 440GX || 440SP || 440SPE
193 default y
194
195config BIOS_FIXUP
196 bool
197 depends on BUBINGA || EP405 || SYCAMORE || WALNUT || CPCI405
198 default y
199
200# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
201config 403GCX
202 bool
203 depends on OAK
204 default y
205
206config 405EP
207 bool
208 depends on BUBINGA
209 default y
210
211config 405GP
212 bool
213 depends on CPCI405 || EP405 || WALNUT
214 default y
215
216config 405GPR
217 bool
218 depends on SYCAMORE
219 default y
220
221config XILINX_VIRTEX_II_PRO
222 bool
223 select XILINX_VIRTEX
224
225config XILINX_VIRTEX_4_FX
226 bool
227 select XILINX_VIRTEX
228
229config XILINX_VIRTEX
230 bool
231
232config STB03xxx
233 bool
234 depends on REDWOOD_5 || REDWOOD_6
235 default y
236
237config EMBEDDEDBOOT
238 bool
239
240config IBM_OPENBIOS
241 bool
242 depends on ASH || REDWOOD_5 || REDWOOD_6
243 default y
244
245config PPC4xx_DMA
246 bool "PPC4xx DMA controller support"
247 depends on 4xx
248
249config PPC4xx_EDMA
250 bool
251 depends on !STB03xxx && PPC4xx_DMA
252 default y
253
254config PPC_GEN550
255 bool
256 depends on 4xx
257 default y
258
259choice
260 prompt "TTYS0 device and default console"
261 depends on 40x
262 default UART0_TTYS0
263
264config UART0_TTYS0
265 bool "UART0"
266
267config UART0_TTYS1
268 bool "UART1"
269
270endchoice
271
272config SERIAL_SICC
273 bool "SICC Serial port support"
274 depends on STB03xxx
275
276config UART1_DFLT_CONSOLE
277 bool
278 depends on SERIAL_SICC && UART0_TTYS1
279 default y
280
281config SERIAL_SICC_CONSOLE
282 bool
283 depends on SERIAL_SICC && UART0_TTYS1
284 default y
285endmenu
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
deleted file mode 100644
index 723ad7985cc6..000000000000
--- a/arch/ppc/platforms/4xx/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
1#
2# Makefile for the PowerPC 4xx linux kernel.
3
4obj-$(CONFIG_BAMBOO) += bamboo.o
5obj-$(CONFIG_CPCI405) += cpci405.o
6obj-$(CONFIG_EBONY) += ebony.o
7obj-$(CONFIG_EP405) += ep405.o
8obj-$(CONFIG_BUBINGA) += bubinga.o
9obj-$(CONFIG_LUAN) += luan.o
10obj-$(CONFIG_YUCCA) += yucca.o
11obj-$(CONFIG_OCOTEA) += ocotea.o
12obj-$(CONFIG_REDWOOD_5) += redwood5.o
13obj-$(CONFIG_REDWOOD_6) += redwood6.o
14obj-$(CONFIG_SYCAMORE) += sycamore.o
15obj-$(CONFIG_TAISHAN) += taishan.o
16obj-$(CONFIG_WALNUT) += walnut.o
17obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
18obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o
19
20obj-$(CONFIG_405GP) += ibm405gp.o
21obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
22obj-$(CONFIG_NP405H) += ibmnp405h.o
23obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
24obj-$(CONFIG_440EP) += ibm440ep.o
25obj-$(CONFIG_440GP) += ibm440gp.o
26obj-$(CONFIG_440GX) += ibm440gx.o
27obj-$(CONFIG_440SP) += ibm440sp.o
28obj-$(CONFIG_440SPE) += ppc440spe.o
29obj-$(CONFIG_405EP) += ibm405ep.o
30obj-$(CONFIG_405GPR) += ibm405gpr.o
31
diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c
deleted file mode 100644
index 01f20f4c14fe..000000000000
--- a/arch/ppc/platforms/4xx/bamboo.c
+++ /dev/null
@@ -1,442 +0,0 @@
1/*
2 * Bamboo board specific routines
3 *
4 * Wade Farnsworth <wfarnsworth@mvista.com>
5 * Copyright 2004 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/stddef.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/reboot.h>
18#include <linux/pci.h>
19#include <linux/kdev_t.h>
20#include <linux/types.h>
21#include <linux/major.h>
22#include <linux/blkdev.h>
23#include <linux/console.h>
24#include <linux/delay.h>
25#include <linux/initrd.h>
26#include <linux/seq_file.h>
27#include <linux/root_dev.h>
28#include <linux/tty.h>
29#include <linux/serial.h>
30#include <linux/serial_core.h>
31#include <linux/serial_8250.h>
32#include <linux/ethtool.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/dma.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/ocp.h>
41#include <asm/pci-bridge.h>
42#include <asm/time.h>
43#include <asm/todc.h>
44#include <asm/bootinfo.h>
45#include <asm/ppc4xx_pic.h>
46#include <asm/ppcboot.h>
47
48#include <syslib/gen550.h>
49#include <syslib/ibm440gx_common.h>
50
51extern bd_t __res;
52
53static struct ibm44x_clocks clocks __initdata;
54
55/*
56 * Bamboo external IRQ triggering/polarity settings
57 */
58unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
65 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
69};
70
71static void __init
72bamboo_calibrate_decr(void)
73{
74 unsigned int freq;
75
76 if (mfspr(SPRN_CCR1) & CCR1_TCS)
77 freq = BAMBOO_TMRCLK;
78 else
79 freq = clocks.cpu;
80
81 ibm44x_calibrate_decr(freq);
82
83}
84
85static int
86bamboo_show_cpuinfo(struct seq_file *m)
87{
88 seq_printf(m, "vendor\t\t: IBM\n");
89 seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
90
91 return 0;
92}
93
94static inline int
95bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
96{
97 static char pci_irq_table[][4] =
98 /*
99 * PCI IDSEL/INTPIN->INTLINE
100 * A B C D
101 */
102 {
103 { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
104 { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
105 { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
106 { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
107 };
108
109 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
110 return PCI_IRQ_TABLE_LOOKUP;
111}
112
113static void __init bamboo_set_emacdata(void)
114{
115 u8 * base_addr;
116 struct ocp_def *def;
117 struct ocp_func_emac_data *emacdata;
118 u8 val;
119 int mode;
120 u32 excluded = 0;
121
122 base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
123 val = readb(base_addr);
124 iounmap((void *) base_addr);
125 if (BAMBOO_SEL_MII(val))
126 mode = PHY_MODE_MII;
127 else if (BAMBOO_SEL_RMII(val))
128 mode = PHY_MODE_RMII;
129 else
130 mode = PHY_MODE_SMII;
131
132 /*
133 * SW2 on the Bamboo is used for ethernet configuration and is accessed
134 * via the CONFIG2 register in the FPGA. If the ANEG pin is set,
135 * overwrite the supported features with the settings in SW2.
136 *
137 * This is used as a workaround for the improperly biased RJ-45 sockets
138 * on the Rev. 0 Bamboo. By default only 10baseT is functional.
139 * Removing inductors L17 and L18 from the board allows 100baseT, but
140 * disables 10baseT. The Rev. 1 has no such limitations.
141 */
142
143 base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
144 val = readb(base_addr);
145 iounmap((void *) base_addr);
146 if (!BAMBOO_AUTONEGOTIATE(val)) {
147 excluded |= SUPPORTED_Autoneg;
148 if (BAMBOO_FORCE_100Mbps(val)) {
149 excluded |= SUPPORTED_10baseT_Full;
150 excluded |= SUPPORTED_10baseT_Half;
151 if (BAMBOO_FULL_DUPLEX_EN(val))
152 excluded |= SUPPORTED_100baseT_Half;
153 else
154 excluded |= SUPPORTED_100baseT_Full;
155 } else {
156 excluded |= SUPPORTED_100baseT_Full;
157 excluded |= SUPPORTED_100baseT_Half;
158 if (BAMBOO_FULL_DUPLEX_EN(val))
159 excluded |= SUPPORTED_10baseT_Half;
160 else
161 excluded |= SUPPORTED_10baseT_Full;
162 }
163 }
164
165 /* Set mac_addr, phy mode and unsupported phy features for each EMAC */
166
167 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
168 emacdata = def->additions;
169 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
170 emacdata->phy_mode = mode;
171 emacdata->phy_feat_exc = excluded;
172
173 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
174 emacdata = def->additions;
175 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
176 emacdata->phy_mode = mode;
177 emacdata->phy_feat_exc = excluded;
178}
179
180static int
181bamboo_exclude_device(unsigned char bus, unsigned char devfn)
182{
183 return (bus == 0 && devfn == 0);
184}
185
186#define PCI_READW(offset) \
187 (readw((void *)((u32)pci_reg_base+offset)))
188
189#define PCI_WRITEW(value, offset) \
190 (writew(value, (void *)((u32)pci_reg_base+offset)))
191
192#define PCI_WRITEL(value, offset) \
193 (writel(value, (void *)((u32)pci_reg_base+offset)))
194
195static void __init
196bamboo_setup_pci(void)
197{
198 void *pci_reg_base;
199 unsigned long memory_size;
200 memory_size = ppc_md.find_end_of_memory();
201
202 pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
203
204 /* Enable PCI I/O, Mem, and Busmaster cycles */
205 PCI_WRITEW(PCI_READW(PCI_COMMAND) |
206 PCI_COMMAND_MEMORY |
207 PCI_COMMAND_MASTER, PCI_COMMAND);
208
209 /* Disable region first */
210 PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
211
212 /* PLB starting addr: 0x00000000A0000000 */
213 PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
214
215 /* PCI start addr, 0xA0000000 (PCI Address) */
216 PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
217 PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
218
219 /* Enable no pre-fetch, enable region */
220 PCI_WRITEL(((0xffffffff -
221 (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
222 BAMBOO_PCIL0_PMM0MA);
223
224 /* Disable region one */
225 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
226 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
227 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
228 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
229 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
230
231 /* Disable region two */
232 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
233 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
234 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
235 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
236 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
237
238 /* Now configure the PCI->PLB windows, we only use PTM1
239 *
240 * For Inbound flow, set the window size to all available memory
241 * This is required because if size is smaller,
242 * then Eth/PCI DD would fail as PCI card not able to access
243 * the memory allocated by DD.
244 */
245
246 PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
247 PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
248
249 memory_size = 1 << fls(memory_size - 1);
250
251 /* Size low + Enabled */
252 PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
253
254 eieio();
255 iounmap(pci_reg_base);
256}
257
258static void __init
259bamboo_setup_hose(void)
260{
261 unsigned int bar_response, bar;
262 struct pci_controller *hose;
263
264 bamboo_setup_pci();
265
266 hose = pcibios_alloc_controller();
267
268 if (!hose)
269 return;
270
271 hose->first_busno = 0;
272 hose->last_busno = 0xff;
273
274 hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
275
276 pci_init_resource(&hose->io_resource,
277 BAMBOO_PCI_LOWER_IO,
278 BAMBOO_PCI_UPPER_IO,
279 IORESOURCE_IO,
280 "PCI host bridge");
281
282 pci_init_resource(&hose->mem_resources[0],
283 BAMBOO_PCI_LOWER_MEM,
284 BAMBOO_PCI_UPPER_MEM,
285 IORESOURCE_MEM,
286 "PCI host bridge");
287
288 ppc_md.pci_exclude_device = bamboo_exclude_device;
289
290 hose->io_space.start = BAMBOO_PCI_LOWER_IO;
291 hose->io_space.end = BAMBOO_PCI_UPPER_IO;
292 hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
293 hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
294 isa_io_base =
295 (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
296 hose->io_base_virt = (void *)isa_io_base;
297
298 setup_indirect_pci(hose,
299 BAMBOO_PCI_CFGA_PLB32,
300 BAMBOO_PCI_CFGD_PLB32);
301 hose->set_cfg_type = 1;
302
303 /* Zero config bars */
304 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
305 early_write_config_dword(hose, hose->first_busno,
306 PCI_FUNC(hose->first_busno), bar,
307 0x00000000);
308 early_read_config_dword(hose, hose->first_busno,
309 PCI_FUNC(hose->first_busno), bar,
310 &bar_response);
311 }
312
313 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
314
315 ppc_md.pci_swizzle = common_swizzle;
316 ppc_md.pci_map_irq = bamboo_map_irq;
317}
318
319TODC_ALLOC();
320
321static void __init
322bamboo_early_serial_map(void)
323{
324 struct uart_port port;
325
326 /* Setup ioremapped serial port access */
327 memset(&port, 0, sizeof(port));
328 port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
329 port.irq = 0;
330 port.uartclk = clocks.uart0;
331 port.regshift = 0;
332 port.iotype = UPIO_MEM;
333 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
334 port.line = 0;
335
336 if (early_serial_setup(&port) != 0) {
337 printk("Early serial init of port 0 failed\n");
338 }
339
340#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
341 /* Configure debug serial access */
342 gen550_init(0, &port);
343#endif
344
345 port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
346 port.irq = 1;
347 port.uartclk = clocks.uart1;
348 port.line = 1;
349
350 if (early_serial_setup(&port) != 0) {
351 printk("Early serial init of port 1 failed\n");
352 }
353
354#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
355 /* Configure debug serial access */
356 gen550_init(1, &port);
357#endif
358
359 port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
360 port.irq = 3;
361 port.uartclk = clocks.uart2;
362 port.line = 2;
363
364 if (early_serial_setup(&port) != 0) {
365 printk("Early serial init of port 2 failed\n");
366 }
367
368#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
369 /* Configure debug serial access */
370 gen550_init(2, &port);
371#endif
372
373 port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
374 port.irq = 4;
375 port.uartclk = clocks.uart3;
376 port.line = 3;
377
378 if (early_serial_setup(&port) != 0) {
379 printk("Early serial init of port 3 failed\n");
380 }
381}
382
383static void __init
384bamboo_setup_arch(void)
385{
386
387 bamboo_set_emacdata();
388
389 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
390 ocp_sys_info.opb_bus_freq = clocks.opb;
391
392 /* Setup TODC access */
393 TODC_INIT(TODC_TYPE_DS1743,
394 0,
395 0,
396 ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
397 8);
398
399 /* init to some ~sane value until calibrate_delay() runs */
400 loops_per_jiffy = 50000000/HZ;
401
402 /* Setup PCI host bridge */
403 bamboo_setup_hose();
404
405#ifdef CONFIG_BLK_DEV_INITRD
406 if (initrd_start)
407 ROOT_DEV = Root_RAM0;
408 else
409#endif
410#ifdef CONFIG_ROOT_NFS
411 ROOT_DEV = Root_NFS;
412#else
413 ROOT_DEV = Root_HDA1;
414#endif
415
416 bamboo_early_serial_map();
417
418 /* Identify the system */
419 printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
420}
421
422void __init platform_init(unsigned long r3, unsigned long r4,
423 unsigned long r5, unsigned long r6, unsigned long r7)
424{
425 ibm44x_platform_init(r3, r4, r5, r6, r7);
426
427 ppc_md.setup_arch = bamboo_setup_arch;
428 ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
429 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
430
431 ppc_md.calibrate_decr = bamboo_calibrate_decr;
432 ppc_md.time_init = todc_time_init;
433 ppc_md.set_rtc_time = todc_set_rtc_time;
434 ppc_md.get_rtc_time = todc_get_rtc_time;
435
436 ppc_md.nvram_read_val = todc_direct_read_val;
437 ppc_md.nvram_write_val = todc_direct_write_val;
438#ifdef CONFIG_KGDB
439 ppc_md.early_serial_map = bamboo_early_serial_map;
440#endif
441}
442
diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h
deleted file mode 100644
index dcd3d09a0a71..000000000000
--- a/arch/ppc/platforms/4xx/bamboo.h
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Bamboo board definitions
3 *
4 * Wade Farnsworth <wfarnsworth@mvista.com>
5 *
6 * Copyright 2004 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_BAMBOO_H__
16#define __ASM_BAMBOO_H__
17
18#include <platforms/4xx/ibm440ep.h>
19
20/* F/W TLB mapping used in bootloader glue to reset EMAC */
21#define PPC44x_EMAC0_MR0 0x0EF600E00
22
23/* Location of MAC addresses in PIBS image */
24#define PIBS_FLASH_BASE 0xfff00000
25#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400)
26#define PIBS_MAC_SIZE 0x200
27#define PIBS_MAC_OFFSET 0x100
28
29/* Default clock rate */
30#define BAMBOO_TMRCLK 25000000
31
32/* RTC/NVRAM location */
33#define BAMBOO_RTC_ADDR 0x080000000ULL
34#define BAMBOO_RTC_SIZE 0x2000
35
36/* FPGA Registers */
37#define BAMBOO_FPGA_ADDR 0x080002000ULL
38
39#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1)
40#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x08)
41#define BAMBOO_FORCE_100Mbps(x) (x & 0x04)
42#define BAMBOO_AUTONEGOTIATE(x) (x & 0x02)
43
44#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3)
45#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80))
46#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40))
47#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20))
48
49#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
50#define BAMBOO_SEL_MII(x) (x & 0x80)
51#define BAMBOO_SEL_RMII(x) (x & 0x40)
52#define BAMBOO_SEL_SMII(x) (x & 0x20)
53
54/* Flash */
55#define BAMBOO_SMALL_FLASH_LOW 0x087f00000ULL
56#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000ULL
57#define BAMBOO_SMALL_FLASH_SIZE 0x100000
58#define BAMBOO_LARGE_FLASH_LOW 0x087800000ULL
59#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000ULL
60#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000ULL
61#define BAMBOO_LARGE_FLASH_SIZE 0x400000
62#define BAMBOO_SRAM_LOW 0x087f00000ULL
63#define BAMBOO_SRAM_HIGH1 0x0fff00000ULL
64#define BAMBOO_SRAM_HIGH2 0x0ff800000ULL
65#define BAMBOO_SRAM_SIZE 0x100000
66#define BAMBOO_NAND_FLASH_REG_ADDR 0x090000000ULL
67#define BAMBOO_NAND_FLASH_REG_SIZE 0x2000
68
69/*
70 * Serial port defines
71 */
72#define RS_TABLE_SIZE 4
73
74#define UART0_IO_BASE 0xEF600300
75#define UART1_IO_BASE 0xEF600400
76#define UART2_IO_BASE 0xEF600500
77#define UART3_IO_BASE 0xEF600600
78
79#define BASE_BAUD 33177600/3/16
80#define UART0_INT 0
81#define UART1_INT 1
82#define UART2_INT 3
83#define UART3_INT 4
84
85#define STD_UART_OP(num) \
86 { 0, BASE_BAUD, 0, UART##num##_INT, \
87 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
88 iomem_base: (void*)UART##num##_IO_BASE, \
89 io_type: SERIAL_IO_MEM},
90
91#define SERIAL_PORT_DFNS \
92 STD_UART_OP(0) \
93 STD_UART_OP(1) \
94 STD_UART_OP(2) \
95 STD_UART_OP(3)
96
97/* PCI support */
98#define BAMBOO_PCI_CFGA_PLB32 0xeec00000
99#define BAMBOO_PCI_CFGD_PLB32 0xeec00004
100
101#define BAMBOO_PCI_IO_BASE 0x00000000e8000000ULL
102#define BAMBOO_PCI_IO_SIZE 0x00010000
103#define BAMBOO_PCI_MEM_OFFSET 0x00000000
104#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000a0000000ULL
105
106#define BAMBOO_PCI_LOWER_IO 0x00000000
107#define BAMBOO_PCI_UPPER_IO 0x0000ffff
108#define BAMBOO_PCI_LOWER_MEM 0xa0000000
109#define BAMBOO_PCI_UPPER_MEM 0xafffffff
110#define BAMBOO_PCI_MEM_BASE 0xa0000000
111
112#define BAMBOO_PCIL0_BASE 0x00000000ef400000ULL
113#define BAMBOO_PCIL0_SIZE 0x40
114
115#define BAMBOO_PCIL0_PMM0LA 0x000
116#define BAMBOO_PCIL0_PMM0MA 0x004
117#define BAMBOO_PCIL0_PMM0PCILA 0x008
118#define BAMBOO_PCIL0_PMM0PCIHA 0x00C
119#define BAMBOO_PCIL0_PMM1LA 0x010
120#define BAMBOO_PCIL0_PMM1MA 0x014
121#define BAMBOO_PCIL0_PMM1PCILA 0x018
122#define BAMBOO_PCIL0_PMM1PCIHA 0x01C
123#define BAMBOO_PCIL0_PMM2LA 0x020
124#define BAMBOO_PCIL0_PMM2MA 0x024
125#define BAMBOO_PCIL0_PMM2PCILA 0x028
126#define BAMBOO_PCIL0_PMM2PCIHA 0x02C
127#define BAMBOO_PCIL0_PTM1MS 0x030
128#define BAMBOO_PCIL0_PTM1LA 0x034
129#define BAMBOO_PCIL0_PTM2MS 0x038
130#define BAMBOO_PCIL0_PTM2LA 0x03C
131
132#endif /* __ASM_BAMBOO_H__ */
133#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c
deleted file mode 100644
index cd696be55aca..000000000000
--- a/arch/ppc/platforms/4xx/bubinga.c
+++ /dev/null
@@ -1,265 +0,0 @@
1/*
2 * Support for IBM PPC 405EP evaluation board (Bubinga).
3 *
4 * Author: SAW (IBM), derived from walnut.c.
5 * Maintained by MontaVista Software <source@mvista.com>
6 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/threads.h>
16#include <linux/param.h>
17#include <linux/string.h>
18#include <linux/blkdev.h>
19#include <linux/pci.h>
20#include <linux/rtc.h>
21#include <linux/tty.h>
22#include <linux/serial.h>
23#include <linux/serial_core.h>
24#include <linux/serial_8250.h>
25
26#include <asm/system.h>
27#include <asm/pci-bridge.h>
28#include <asm/processor.h>
29#include <asm/machdep.h>
30#include <asm/page.h>
31#include <asm/time.h>
32#include <asm/io.h>
33#include <asm/todc.h>
34#include <asm/kgdb.h>
35#include <asm/ocp.h>
36#include <asm/ibm_ocp_pci.h>
37
38#include <platforms/4xx/ibm405ep.h>
39
40#undef DEBUG
41
42#ifdef DEBUG
43#define DBG(x...) printk(x)
44#else
45#define DBG(x...)
46#endif
47
48extern bd_t __res;
49
50void *bubinga_rtc_base;
51
52/* Some IRQs unique to the board
53 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
54 */
55int __init
56ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
57{
58 static char pci_irq_table[][4] =
59 /*
60 * PCI IDSEL/INTPIN->INTLINE
61 * A B C D
62 */
63 {
64 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
65 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
66 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
67 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
68 };
69
70 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
71 return PCI_IRQ_TABLE_LOOKUP;
72};
73
74/* The serial clock for the chip is an internal clock determined by
75 * different clock speeds/dividers.
76 * Calculate the proper input baud rate and setup the serial driver.
77 */
78static void __init
79bubinga_early_serial_map(void)
80{
81 u32 uart_div;
82 int uart_clock;
83 struct uart_port port;
84
85 /* Calculate the serial clock input frequency
86 *
87 * The base baud is the PLL OUTA (provided in the board info
88 * structure) divided by the external UART Divisor, divided
89 * by 16.
90 */
91 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
92 uart_clock = __res.bi_procfreq / uart_div;
93
94 /* Setup serial port access */
95 memset(&port, 0, sizeof(port));
96 port.membase = (void*)ACTING_UART0_IO_BASE;
97 port.irq = ACTING_UART0_INT;
98 port.uartclk = uart_clock;
99 port.regshift = 0;
100 port.iotype = UPIO_MEM;
101 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
102 port.line = 0;
103
104 if (early_serial_setup(&port) != 0) {
105 printk("Early serial init of port 0 failed\n");
106 }
107
108 port.membase = (void*)ACTING_UART1_IO_BASE;
109 port.irq = ACTING_UART1_INT;
110 port.line = 1;
111
112 if (early_serial_setup(&port) != 0) {
113 printk("Early serial init of port 1 failed\n");
114 }
115}
116
117void __init
118bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
119{
120#ifdef CONFIG_PCI
121
122 unsigned int bar_response, bar;
123 /*
124 * Expected PCI mapping:
125 *
126 * PLB addr PCI memory addr
127 * --------------------- ---------------------
128 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
129 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
130 *
131 * PLB addr PCI io addr
132 * --------------------- ---------------------
133 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
134 *
135 * The following code is simplified by assuming that the bootrom
136 * has been well behaved in following this mapping.
137 */
138
139#ifdef DEBUG
140 int i;
141
142 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
143 printk("PCI bridge regs before fixup \n");
144 for (i = 0; i <= 3; i++) {
145 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
146 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
147 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
148 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
149 }
150 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
151 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
152 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
153 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
154
155#endif
156
157 /* added for IBM boot rom version 1.15 bios bar changes -AK */
158
159 /* Disable region first */
160 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
161 /* PLB starting addr, PCI: 0x80000000 */
162 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
163 /* PCI start addr, 0x80000000 */
164 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
165 /* 512MB range of PLB to PCI */
166 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
167 /* Enable no pre-fetch, enable region */
168 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
169 (PPC405_PCI_UPPER_MEM -
170 PPC405_PCI_MEM_BASE)) | 0x01));
171
172 /* Disable region one */
173 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
174 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
175 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
176 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
177 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
178 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
179
180 /* Disable region two */
181 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
182 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
183 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
184 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
185 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
186 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
187 out_le32((void *) &(pcip->ptm2la), 0x00000000);
188
189 /* Zero config bars */
190 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
191 early_write_config_dword(hose, hose->first_busno,
192 PCI_FUNC(hose->first_busno), bar,
193 0x00000000);
194 early_read_config_dword(hose, hose->first_busno,
195 PCI_FUNC(hose->first_busno), bar,
196 &bar_response);
197 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
198 hose->first_busno, PCI_SLOT(hose->first_busno),
199 PCI_FUNC(hose->first_busno), bar, bar_response);
200 }
201 /* end workaround */
202
203#ifdef DEBUG
204 printk("PCI bridge regs after fixup \n");
205 for (i = 0; i <= 3; i++) {
206 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
207 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
208 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
209 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
210 }
211 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
212 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
213 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
214 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
215
216#endif
217#endif
218}
219
220void __init
221bubinga_setup_arch(void)
222{
223 ppc4xx_setup_arch();
224
225 ibm_ocp_set_emac(0, 1);
226
227 bubinga_early_serial_map();
228
229 /* RTC step for the evb405ep */
230 bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
231 TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
232 bubinga_rtc_base, 8);
233 /* Identify the system */
234 printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
235}
236
237void __init
238bubinga_map_io(void)
239{
240 ppc4xx_map_io();
241 io_block_mapping(BUBINGA_RTC_VADDR,
242 BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
243}
244
245void __init
246platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
247 unsigned long r6, unsigned long r7)
248{
249 ppc4xx_init(r3, r4, r5, r6, r7);
250
251 ppc_md.setup_arch = bubinga_setup_arch;
252 ppc_md.setup_io_mappings = bubinga_map_io;
253
254#ifdef CONFIG_GEN_RTC
255 ppc_md.time_init = todc_time_init;
256 ppc_md.set_rtc_time = todc_set_rtc_time;
257 ppc_md.get_rtc_time = todc_get_rtc_time;
258 ppc_md.nvram_read_val = todc_direct_read_val;
259 ppc_md.nvram_write_val = todc_direct_write_val;
260#endif
261#ifdef CONFIG_KGDB
262 ppc_md.early_serial_map = bubinga_early_serial_map;
263#endif
264}
265
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h
deleted file mode 100644
index 5c408060eb35..000000000000
--- a/arch/ppc/platforms/4xx/bubinga.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Bubinga board definitions
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * SAW (IBM)
9 * 2003 (c) MontaVista Softare Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifdef __KERNEL__
19#ifndef __BUBINGA_H__
20#define __BUBINGA_H__
21
22#include <platforms/4xx/ibm405ep.h>
23#include <asm/ppcboot.h>
24
25/* Memory map for the Bubinga board.
26 * Generic 4xx plus RTC.
27 */
28
29#define BUBINGA_RTC_PADDR ((uint)0xf0000000)
30#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR
31#define BUBINGA_RTC_SIZE ((uint)8*1024)
32
33/* The UART clock is based off an internal clock -
34 * define BASE_BAUD based on the internal clock and divider(s).
35 * Since BASE_BAUD must be a constant, we will initialize it
36 * using clock/divider values which OpenBIOS initializes
37 * for typical configurations at various CPU speeds.
38 * The base baud is calculated as (FWDA / EXT UART DIV / 16)
39 */
40#define BASE_BAUD 0
41
42/* Flash */
43#define PPC40x_FPGA_BASE 0xF0300000
44#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */
45#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
46#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
47#define PPC40x_FLASH_LOW 0xFFF00000
48#define PPC40x_FLASH_HIGH 0xFFF80000
49#define PPC40x_FLASH_SIZE 0x80000
50
51#define PPC4xx_MACHINE_NAME "IBM Bubinga"
52
53#endif /* __BUBINGA_H__ */
54#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c
deleted file mode 100644
index 2e7e25dd84cb..000000000000
--- a/arch/ppc/platforms/4xx/cpci405.c
+++ /dev/null
@@ -1,201 +0,0 @@
1/*
2 * Board setup routines for the esd CPCI-405 cPCI Board.
3 *
4 * Copyright 2001-2006 esd electronic system design - hannover germany
5 *
6 * Authors: Matthias Fuchs
7 * matthias.fuchs@esd-electronics.com
8 * Stefan Roese
9 * stefan.roese@esd-electronics.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <asm/system.h>
21#include <asm/pci-bridge.h>
22#include <asm/machdep.h>
23#include <asm/todc.h>
24#include <linux/serial.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <asm/ocp.h>
28#include <asm/ibm_ocp_pci.h>
29#include <platforms/4xx/ibm405gp.h>
30
31#ifdef CONFIG_GEN_RTC
32void *cpci405_nvram;
33#endif
34
35extern bd_t __res;
36
37/*
38 * Some IRQs unique to CPCI-405.
39 */
40int __init
41ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
42{
43 static char pci_irq_table[][4] =
44 /*
45 * PCI IDSEL/INTPIN->INTLINE
46 * A B C D
47 */
48 {
49 {28, 29, 30, 27}, /* IDSEL 15 - cPCI slot 8 */
50 {29, 30, 27, 28}, /* IDSEL 16 - cPCI slot 7 */
51 {30, 27, 28, 29}, /* IDSEL 17 - cPCI slot 6 */
52 {27, 28, 29, 30}, /* IDSEL 18 - cPCI slot 5 */
53 {28, 29, 30, 27}, /* IDSEL 19 - cPCI slot 4 */
54 {29, 30, 27, 28}, /* IDSEL 20 - cPCI slot 3 */
55 {30, 27, 28, 29}, /* IDSEL 21 - cPCI slot 2 */
56 };
57 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
58 return PCI_IRQ_TABLE_LOOKUP;
59};
60
61/* The serial clock for the chip is an internal clock determined by
62 * different clock speeds/dividers.
63 * Calculate the proper input baud rate and setup the serial driver.
64 */
65static void __init
66cpci405_early_serial_map(void)
67{
68 u32 uart_div;
69 int uart_clock;
70 struct uart_port port;
71
72 /* Calculate the serial clock input frequency
73 *
74 * The uart clock is the cpu frequency (provided in the board info
75 * structure) divided by the external UART Divisor.
76 */
77 uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
78 uart_clock = __res.bi_procfreq / uart_div;
79
80 /* Setup serial port access */
81 memset(&port, 0, sizeof(port));
82#if defined(CONFIG_UART0_TTYS0)
83 port.membase = (void*)UART0_IO_BASE;
84 port.irq = UART0_INT;
85#else
86 port.membase = (void*)UART1_IO_BASE;
87 port.irq = UART1_INT;
88#endif
89 port.uartclk = uart_clock;
90 port.regshift = 0;
91 port.iotype = UPIO_MEM;
92 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
93 port.line = 0;
94
95 if (early_serial_setup(&port) != 0) {
96 printk("Early serial init of port 0 failed\n");
97 }
98#if defined(CONFIG_UART0_TTYS0)
99 port.membase = (void*)UART1_IO_BASE;
100 port.irq = UART1_INT;
101#else
102 port.membase = (void*)UART0_IO_BASE;
103 port.irq = UART0_INT;
104#endif
105 port.line = 1;
106
107 if (early_serial_setup(&port) != 0) {
108 printk("Early serial init of port 1 failed\n");
109 }
110}
111
112void __init
113cpci405_setup_arch(void)
114{
115 ppc4xx_setup_arch();
116
117 ibm_ocp_set_emac(0, 0);
118
119 cpci405_early_serial_map();
120
121#ifdef CONFIG_GEN_RTC
122 TODC_INIT(TODC_TYPE_MK48T35,
123 cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
124#endif
125}
126
127void __init
128bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
129{
130#ifdef CONFIG_PCI
131 unsigned int bar_response, bar;
132
133 /* Disable region first */
134 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
135 /* PLB starting addr, PCI: 0x80000000 */
136 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
137 /* PCI start addr, 0x80000000 */
138 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
139 /* 512MB range of PLB to PCI */
140 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
141 /* Enable no pre-fetch, enable region */
142 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
143 (PPC405_PCI_UPPER_MEM -
144 PPC405_PCI_MEM_BASE)) | 0x01));
145
146 /* Disable region one */
147 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
148 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
149 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
150 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
151 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
152 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
153
154 /* Disable region two */
155 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
156 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
157 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
158 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
159 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
160 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
161 out_le32((void *) &(pcip->ptm2la), 0x00000000);
162
163 /* Zero config bars */
164 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
165 early_write_config_dword(hose, hose->first_busno,
166 PCI_FUNC(hose->first_busno), bar,
167 0x00000000);
168 early_read_config_dword(hose, hose->first_busno,
169 PCI_FUNC(hose->first_busno), bar,
170 &bar_response);
171 }
172#endif
173}
174
175void __init
176cpci405_map_io(void)
177{
178 ppc4xx_map_io();
179
180#ifdef CONFIG_GEN_RTC
181 cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
182#endif
183}
184
185void __init
186platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
187 unsigned long r6, unsigned long r7)
188{
189 ppc4xx_init(r3, r4, r5, r6, r7);
190
191 ppc_md.setup_arch = cpci405_setup_arch;
192 ppc_md.setup_io_mappings = cpci405_map_io;
193
194#ifdef CONFIG_GEN_RTC
195 ppc_md.time_init = todc_time_init;
196 ppc_md.set_rtc_time = todc_set_rtc_time;
197 ppc_md.get_rtc_time = todc_get_rtc_time;
198 ppc_md.nvram_read_val = todc_direct_read_val;
199 ppc_md.nvram_write_val = todc_direct_write_val;
200#endif
201}
diff --git a/arch/ppc/platforms/4xx/cpci405.h b/arch/ppc/platforms/4xx/cpci405.h
deleted file mode 100644
index a6c0a138b0d7..000000000000
--- a/arch/ppc/platforms/4xx/cpci405.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * CPCI-405 board specific definitions
3 *
4 * Copyright 2001-2006 esd electronic system design - hannover germany
5 *
6 * Authors: Matthias Fuchs
7 * matthias.fuchs@esd-electronics.com
8 * Stefan Roese
9 * stefan.roese@esd-electronics.com
10 */
11
12#ifdef __KERNEL__
13#ifndef __CPCI405_H__
14#define __CPCI405_H__
15
16#include <platforms/4xx/ibm405gp.h>
17#include <asm/ppcboot.h>
18
19/* Map for the NVRAM space */
20#define CPCI405_NVRAM_PADDR ((uint)0xf0200000)
21#define CPCI405_NVRAM_SIZE ((uint)32*1024)
22
23#define BASE_BAUD 0
24
25#define PPC4xx_MACHINE_NAME "esd CPCI-405"
26
27#endif /* __CPCI405_H__ */
28#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
deleted file mode 100644
index 8027a36fc5bb..000000000000
--- a/arch/ppc/platforms/4xx/ebony.c
+++ /dev/null
@@ -1,334 +0,0 @@
1/*
2 * Ebony board specific routines
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 * Copyright 2002-2005 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003-2005 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/reboot.h>
21#include <linux/pci.h>
22#include <linux/kdev_t.h>
23#include <linux/types.h>
24#include <linux/major.h>
25#include <linux/blkdev.h>
26#include <linux/console.h>
27#include <linux/delay.h>
28#include <linux/initrd.h>
29#include <linux/seq_file.h>
30#include <linux/root_dev.h>
31#include <linux/tty.h>
32#include <linux/serial.h>
33#include <linux/serial_core.h>
34#include <linux/serial_8250.h>
35
36#include <asm/system.h>
37#include <asm/pgtable.h>
38#include <asm/page.h>
39#include <asm/dma.h>
40#include <asm/io.h>
41#include <asm/machdep.h>
42#include <asm/ocp.h>
43#include <asm/pci-bridge.h>
44#include <asm/time.h>
45#include <asm/todc.h>
46#include <asm/bootinfo.h>
47#include <asm/ppc4xx_pic.h>
48#include <asm/ppcboot.h>
49#include <asm/tlbflush.h>
50
51#include <syslib/gen550.h>
52#include <syslib/ibm440gp_common.h>
53
54extern bd_t __res;
55
56static struct ibm44x_clocks clocks __initdata;
57
58/*
59 * Ebony external IRQ triggering/polarity settings
60 */
61unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
67 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
75};
76
77static void __init
78ebony_calibrate_decr(void)
79{
80 unsigned int freq;
81
82 /*
83 * Determine system clock speed
84 *
85 * If we are on Rev. B silicon, then use
86 * default external system clock. If we are
87 * on Rev. C silicon then errata forces us to
88 * use the internal clock.
89 */
90 if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0)
91 freq = EBONY_440GP_RB_SYSCLK;
92 else
93 freq = EBONY_440GP_RC_SYSCLK;
94
95 ibm44x_calibrate_decr(freq);
96}
97
98static int
99ebony_show_cpuinfo(struct seq_file *m)
100{
101 seq_printf(m, "vendor\t\t: IBM\n");
102 seq_printf(m, "machine\t\t: Ebony\n");
103
104 return 0;
105}
106
107static inline int
108ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
109{
110 static char pci_irq_table[][4] =
111 /*
112 * PCI IDSEL/INTPIN->INTLINE
113 * A B C D
114 */
115 {
116 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
117 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
118 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
119 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
120 };
121
122 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
123 return PCI_IRQ_TABLE_LOOKUP;
124}
125
126#define PCIX_WRITEL(value, offset) \
127 (writel(value, pcix_reg_base + offset))
128
129/*
130 * FIXME: This is only here to "make it work". This will move
131 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
132 * configuration library. -Matt
133 */
134static void __init
135ebony_setup_pcix(void)
136{
137 void __iomem *pcix_reg_base;
138
139 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
140
141 /* Disable all windows */
142 PCIX_WRITEL(0, PCIX0_POM0SA);
143 PCIX_WRITEL(0, PCIX0_POM1SA);
144 PCIX_WRITEL(0, PCIX0_POM2SA);
145 PCIX_WRITEL(0, PCIX0_PIM0SA);
146 PCIX_WRITEL(0, PCIX0_PIM1SA);
147 PCIX_WRITEL(0, PCIX0_PIM2SA);
148
149 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
150 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
151 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
152 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
153 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
154 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
155
156 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
157 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
158 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
159 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
160
161 eieio();
162}
163
164static void __init
165ebony_setup_hose(void)
166{
167 struct pci_controller *hose;
168
169 /* Configure windows on the PCI-X host bridge */
170 ebony_setup_pcix();
171
172 hose = pcibios_alloc_controller();
173
174 if (!hose)
175 return;
176
177 hose->first_busno = 0;
178 hose->last_busno = 0xff;
179
180 hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
181
182 pci_init_resource(&hose->io_resource,
183 EBONY_PCI_LOWER_IO,
184 EBONY_PCI_UPPER_IO,
185 IORESOURCE_IO,
186 "PCI host bridge");
187
188 pci_init_resource(&hose->mem_resources[0],
189 EBONY_PCI_LOWER_MEM,
190 EBONY_PCI_UPPER_MEM,
191 IORESOURCE_MEM,
192 "PCI host bridge");
193
194 hose->io_space.start = EBONY_PCI_LOWER_IO;
195 hose->io_space.end = EBONY_PCI_UPPER_IO;
196 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
197 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
198 hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
199 isa_io_base = (unsigned long)hose->io_base_virt;
200
201 setup_indirect_pci(hose,
202 EBONY_PCI_CFGA_PLB32,
203 EBONY_PCI_CFGD_PLB32);
204 hose->set_cfg_type = 1;
205
206 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
207
208 ppc_md.pci_swizzle = common_swizzle;
209 ppc_md.pci_map_irq = ebony_map_irq;
210}
211
212TODC_ALLOC();
213
214static void __init
215ebony_early_serial_map(void)
216{
217 struct uart_port port;
218
219 /* Setup ioremapped serial port access */
220 memset(&port, 0, sizeof(port));
221 port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
222 port.irq = 0;
223 port.uartclk = clocks.uart0;
224 port.regshift = 0;
225 port.iotype = UPIO_MEM;
226 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
227 port.line = 0;
228
229 if (early_serial_setup(&port) != 0) {
230 printk("Early serial init of port 0 failed\n");
231 }
232
233#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
234 /* Configure debug serial access */
235 gen550_init(0, &port);
236
237 /* Purge TLB entry added in head_44x.S for early serial access */
238 _tlbie(UART0_IO_BASE, 0);
239#endif
240
241 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
242 port.irq = 1;
243 port.uartclk = clocks.uart1;
244 port.line = 1;
245
246 if (early_serial_setup(&port) != 0) {
247 printk("Early serial init of port 1 failed\n");
248 }
249
250#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
251 /* Configure debug serial access */
252 gen550_init(1, &port);
253#endif
254}
255
256static void __init
257ebony_setup_arch(void)
258{
259 struct ocp_def *def;
260 struct ocp_func_emac_data *emacdata;
261
262 /* Set mac_addr for each EMAC */
263 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
264 emacdata = def->additions;
265 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
266 emacdata->phy_mode = PHY_MODE_RMII;
267 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
268
269 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
270 emacdata = def->additions;
271 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
272 emacdata->phy_mode = PHY_MODE_RMII;
273 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
274
275 /*
276 * Determine various clocks.
277 * To be completely correct we should get SysClk
278 * from FPGA, because it can be changed by on-board switches
279 * --ebs
280 */
281 ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
282 ocp_sys_info.opb_bus_freq = clocks.opb;
283
284 /* Setup TODC access */
285 TODC_INIT(TODC_TYPE_DS1743,
286 0,
287 0,
288 ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
289 8);
290
291 /* init to some ~sane value until calibrate_delay() runs */
292 loops_per_jiffy = 50000000/HZ;
293
294 /* Setup PCI host bridge */
295 ebony_setup_hose();
296
297#ifdef CONFIG_BLK_DEV_INITRD
298 if (initrd_start)
299 ROOT_DEV = Root_RAM0;
300 else
301#endif
302#ifdef CONFIG_ROOT_NFS
303 ROOT_DEV = Root_NFS;
304#else
305 ROOT_DEV = Root_HDA1;
306#endif
307
308 ebony_early_serial_map();
309
310 /* Identify the system */
311 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
312}
313
314void __init platform_init(unsigned long r3, unsigned long r4,
315 unsigned long r5, unsigned long r6, unsigned long r7)
316{
317 ibm44x_platform_init(r3, r4, r5, r6, r7);
318
319 ppc_md.setup_arch = ebony_setup_arch;
320 ppc_md.show_cpuinfo = ebony_show_cpuinfo;
321 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
322
323 ppc_md.calibrate_decr = ebony_calibrate_decr;
324 ppc_md.time_init = todc_time_init;
325 ppc_md.set_rtc_time = todc_set_rtc_time;
326 ppc_md.get_rtc_time = todc_get_rtc_time;
327
328 ppc_md.nvram_read_val = todc_direct_read_val;
329 ppc_md.nvram_write_val = todc_direct_write_val;
330#ifdef CONFIG_KGDB
331 ppc_md.early_serial_map = ebony_early_serial_map;
332#endif
333}
334
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
deleted file mode 100644
index f40e33d39d76..000000000000
--- a/arch/ppc/platforms/4xx/ebony.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * Ebony board definitions
3 *
4 * Matt Porter <mporter@mvista.com>
5 *
6 * Copyright 2002 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_EBONY_H__
16#define __ASM_EBONY_H__
17
18#include <platforms/4xx/ibm440gp.h>
19
20/* F/W TLB mapping used in bootloader glue to reset EMAC */
21#define PPC44x_EMAC0_MR0 0xE0000800
22
23/* Where to find the MAC info */
24#define OPENBIOS_MAC_BASE 0xfffffe0c
25#define OPENBIOS_MAC_OFFSET 0x0c
26
27/* Default clock rates for Rev. B and Rev. C silicon */
28#define EBONY_440GP_RB_SYSCLK 33000000
29#define EBONY_440GP_RC_SYSCLK 400000000
30
31/* RTC/NVRAM location */
32#define EBONY_RTC_ADDR 0x0000000148000000ULL
33#define EBONY_RTC_SIZE 0x2000
34
35/* Flash */
36#define EBONY_FPGA_ADDR 0x0000000148300000ULL
37#define EBONY_BOOT_SMALL_FLASH(x) (x & 0x20)
38#define EBONY_ONBRD_FLASH_EN(x) (x & 0x02)
39#define EBONY_FLASH_SEL(x) (x & 0x01)
40#define EBONY_SMALL_FLASH_LOW1 0x00000001ff800000ULL
41#define EBONY_SMALL_FLASH_LOW2 0x00000001ff880000ULL
42#define EBONY_SMALL_FLASH_HIGH1 0x00000001fff00000ULL
43#define EBONY_SMALL_FLASH_HIGH2 0x00000001fff80000ULL
44#define EBONY_SMALL_FLASH_SIZE 0x80000
45#define EBONY_LARGE_FLASH_LOW 0x00000001ff800000ULL
46#define EBONY_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
47#define EBONY_LARGE_FLASH_SIZE 0x400000
48
49#define EBONY_SMALL_FLASH_BASE 0x00000001fff80000ULL
50#define EBONY_LARGE_FLASH_BASE 0x00000001ff800000ULL
51
52/*
53 * Serial port defines
54 */
55
56#if defined(__BOOTER__)
57/* OpenBIOS defined UART mappings, used by bootloader shim */
58#define UART0_IO_BASE 0xE0000200
59#define UART1_IO_BASE 0xE0000300
60#else
61/* head_44x.S created UART mapping, used before early_serial_setup.
62 * We cannot use default OpenBIOS UART mappings because they
63 * don't work for configurations with more than 512M RAM. --ebs
64 */
65#define UART0_IO_BASE 0xF0000200
66#define UART1_IO_BASE 0xF0000300
67#endif
68
69/* external Epson SG-615P */
70#define BASE_BAUD 691200
71
72#define STD_UART_OP(num) \
73 { 0, BASE_BAUD, 0, UART##num##_INT, \
74 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
75 iomem_base: (void*)UART##num##_IO_BASE, \
76 io_type: SERIAL_IO_MEM},
77
78#define SERIAL_PORT_DFNS \
79 STD_UART_OP(0) \
80 STD_UART_OP(1)
81
82/* PCI support */
83#define EBONY_PCI_LOWER_IO 0x00000000
84#define EBONY_PCI_UPPER_IO 0x0000ffff
85#define EBONY_PCI_LOWER_MEM 0x80002000
86#define EBONY_PCI_UPPER_MEM 0xffffefff
87
88#define EBONY_PCI_CFGREGS_BASE 0x000000020ec00000
89#define EBONY_PCI_CFGA_PLB32 0x0ec00000
90#define EBONY_PCI_CFGD_PLB32 0x0ec00004
91
92#define EBONY_PCI_IO_BASE 0x0000000208000000ULL
93#define EBONY_PCI_IO_SIZE 0x00010000
94#define EBONY_PCI_MEM_OFFSET 0x00000000
95
96#endif /* __ASM_EBONY_H__ */
97#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ep405.c b/arch/ppc/platforms/4xx/ep405.c
deleted file mode 100644
index 5aa295022804..000000000000
--- a/arch/ppc/platforms/4xx/ep405.c
+++ /dev/null
@@ -1,196 +0,0 @@
1/*
2 * Embedded Planet 405GP board
3 * http://www.embeddedplanet.com
4 *
5 * Author: Matthew Locke <mlocke@mvista.com>
6 *
7 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/pci.h>
14#include <asm/system.h>
15#include <asm/pci-bridge.h>
16#include <asm/machdep.h>
17#include <asm/todc.h>
18#include <asm/ocp.h>
19#include <asm/ibm_ocp_pci.h>
20
21#undef DEBUG
22#ifdef DEBUG
23#define DBG(x...) printk(x)
24#else
25#define DBG(x...)
26#endif
27
28u8 *ep405_bcsr;
29u8 *ep405_nvram;
30
31static struct {
32 u8 cpld_xirq_select;
33 int pci_idsel;
34 int irq;
35} ep405_devtable[] = {
36#ifdef CONFIG_EP405PC
37 {0x07, 0x0E, 25}, /* EP405PC: USB */
38#endif
39};
40
41int __init
42ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
43{
44 int i;
45
46 /* AFAICT this is only called a few times during PCI setup, so
47 performance is not critical */
48 for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
49 if (idsel == ep405_devtable[i].pci_idsel)
50 return ep405_devtable[i].irq;
51 }
52 return -1;
53};
54
55void __init
56ep405_setup_arch(void)
57{
58 ppc4xx_setup_arch();
59
60 ibm_ocp_set_emac(0, 0);
61
62 if (__res.bi_nvramsize == 512*1024) {
63 /* FIXME: we should properly handle NVRTCs of different sizes */
64 TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
65 }
66}
67
68void __init
69bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
70{
71#ifdef CONFIG_PCI
72 unsigned int bar_response, bar;
73 /*
74 * Expected PCI mapping:
75 *
76 * PLB addr PCI memory addr
77 * --------------------- ---------------------
78 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
79 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
80 *
81 * PLB addr PCI io addr
82 * --------------------- ---------------------
83 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
84 *
85 */
86
87 /* Disable region zero first */
88 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
89 /* PLB starting addr, PCI: 0x80000000 */
90 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
91 /* PCI start addr, 0x80000000 */
92 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
93 /* 512MB range of PLB to PCI */
94 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
95 /* Enable no pre-fetch, enable region */
96 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
97 (PPC405_PCI_UPPER_MEM -
98 PPC405_PCI_MEM_BASE)) | 0x01));
99
100 /* Disable region one */
101 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
102 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
103 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
104 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
105 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
106 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
107
108 /* Disable region two */
109 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
110 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
111 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
112 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
113 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
114 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
115
116 /* Configure PTM (PCI->PLB) region 1 */
117 out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
118 /* Disable PTM region 2 */
119 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
120
121 /* Zero config bars */
122 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
123 early_write_config_dword(hose, hose->first_busno,
124 PCI_FUNC(hose->first_busno), bar,
125 0x00000000);
126 early_read_config_dword(hose, hose->first_busno,
127 PCI_FUNC(hose->first_busno), bar,
128 &bar_response);
129 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
130 hose->first_busno, PCI_SLOT(hose->first_busno),
131 PCI_FUNC(hose->first_busno), bar, bar_response);
132 }
133 /* end workaround */
134#endif
135}
136
137void __init
138ep405_map_io(void)
139{
140 bd_t *bip = &__res;
141
142 ppc4xx_map_io();
143
144 ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
145
146 if (bip->bi_nvramsize > 0) {
147 ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
148 }
149}
150
151void __init
152ep405_init_IRQ(void)
153{
154 int i;
155
156 ppc4xx_init_IRQ();
157
158 /* Workaround for a bug in the firmware it incorrectly sets
159 the IRQ polarities for XIRQ0 and XIRQ1 */
160 mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
161 mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
162
163 /* Activate the XIRQs from the CPLD */
164 writeb(0xf0, ep405_bcsr+10);
165
166 /* Set up IRQ routing */
167 for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
168 if ( (ep405_devtable[i].irq >= 25)
169 && (ep405_devtable[i].irq) <= 31) {
170 writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
171 writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
172 }
173 }
174}
175
176void __init
177platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
178 unsigned long r6, unsigned long r7)
179{
180 ppc4xx_init(r3, r4, r5, r6, r7);
181
182 ppc_md.setup_arch = ep405_setup_arch;
183 ppc_md.setup_io_mappings = ep405_map_io;
184 ppc_md.init_IRQ = ep405_init_IRQ;
185
186 ppc_md.nvram_read_val = todc_direct_read_val;
187 ppc_md.nvram_write_val = todc_direct_write_val;
188
189 if (__res.bi_nvramsize == 512*1024) {
190 ppc_md.time_init = todc_time_init;
191 ppc_md.set_rtc_time = todc_set_rtc_time;
192 ppc_md.get_rtc_time = todc_get_rtc_time;
193 } else {
194 printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n");
195 }
196}
diff --git a/arch/ppc/platforms/4xx/ep405.h b/arch/ppc/platforms/4xx/ep405.h
deleted file mode 100644
index 9814fc431725..000000000000
--- a/arch/ppc/platforms/4xx/ep405.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Embedded Planet 405GP board
3 * http://www.embeddedplanet.com
4 *
5 * Author: Matthew Locke <mlocke@mvista.com>
6 *
7 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __ASM_EP405_H__
15#define __ASM_EP405_H__
16
17/* We have a 405GP core */
18#include <platforms/4xx/ibm405gp.h>
19
20#ifndef __ASSEMBLY__
21
22#include <linux/types.h>
23
24typedef struct board_info {
25 unsigned int bi_memsize; /* DRAM installed, in bytes */
26 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
27 unsigned int bi_intfreq; /* Processor speed, in Hz */
28 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
29 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
30 unsigned int bi_nvramsize; /* Size of the NVRAM/RTC */
31} bd_t;
32
33/* Some 4xx parts use a different timebase frequency from the internal clock.
34*/
35#define bi_tbfreq bi_intfreq
36
37extern u8 *ep405_bcsr;
38extern u8 *ep405_nvram;
39
40/* Map for the BCSR and NVRAM space */
41#define EP405_BCSR_PADDR ((uint)0xf4000000)
42#define EP405_BCSR_SIZE ((uint)16)
43#define EP405_NVRAM_PADDR ((uint)0xf4200000)
44
45/* serial defines */
46#define BASE_BAUD 399193
47
48#define PPC4xx_MACHINE_NAME "Embedded Planet 405GP"
49
50#endif /* !__ASSEMBLY__ */
51#endif /* __ASM_EP405_H__ */
52#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c
deleted file mode 100644
index fb3630a1608d..000000000000
--- a/arch/ppc/platforms/4xx/ibm405ep.c
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * Support for IBM PPC 405EP processors.
3 *
4 * Author: SAW (IBM), derived from ibmnp405l.c.
5 * Maintained by MontaVista Software <source@mvista.com>
6 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/threads.h>
16#include <linux/param.h>
17#include <linux/string.h>
18
19#include <asm/ibm4xx.h>
20#include <asm/ocp.h>
21#include <asm/ppc4xx_pic.h>
22
23#include <platforms/4xx/ibm405ep.h>
24
25static struct ocp_func_mal_data ibm405ep_mal0_def = {
26 .num_tx_chans = 4, /* Number of TX channels */
27 .num_rx_chans = 2, /* Number of RX channels */
28 .txeob_irq = 11, /* TX End Of Buffer IRQ */
29 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
30 .txde_irq = 13, /* TX Descriptor Error IRQ */
31 .rxde_irq = 14, /* RX Descriptor Error IRQ */
32 .serr_irq = 10, /* MAL System Error IRQ */
33 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
34};
35OCP_SYSFS_MAL_DATA()
36
37static struct ocp_func_emac_data ibm405ep_emac0_def = {
38 .rgmii_idx = -1, /* No RGMII */
39 .rgmii_mux = -1, /* No RGMII */
40 .zmii_idx = -1, /* ZMII device index */
41 .zmii_mux = 0, /* ZMII input of this EMAC */
42 .mal_idx = 0, /* MAL device index */
43 .mal_rx_chan = 0, /* MAL rx channel number */
44 .mal_tx_chan = 0, /* MAL tx channel number */
45 .wol_irq = 9, /* WOL interrupt number */
46 .mdio_idx = 0, /* MDIO via EMAC0 */
47 .tah_idx = -1, /* No TAH */
48};
49
50static struct ocp_func_emac_data ibm405ep_emac1_def = {
51 .rgmii_idx = -1, /* No RGMII */
52 .rgmii_mux = -1, /* No RGMII */
53 .zmii_idx = -1, /* ZMII device index */
54 .zmii_mux = 0, /* ZMII input of this EMAC */
55 .mal_idx = 0, /* MAL device index */
56 .mal_rx_chan = 1, /* MAL rx channel number */
57 .mal_tx_chan = 2, /* MAL tx channel number */
58 .wol_irq = 9, /* WOL interrupt number */
59 .mdio_idx = 0, /* MDIO via EMAC0 */
60 .tah_idx = -1, /* No TAH */
61};
62OCP_SYSFS_EMAC_DATA()
63
64static struct ocp_func_iic_data ibm405ep_iic0_def = {
65 .fast_mode = 0, /* Use standad mode (100Khz) */
66};
67OCP_SYSFS_IIC_DATA()
68
69struct ocp_def core_ocp[] = {
70 { .vendor = OCP_VENDOR_IBM,
71 .function = OCP_FUNC_OPB,
72 .index = 0,
73 .paddr = 0xEF600000,
74 .irq = OCP_IRQ_NA,
75 .pm = OCP_CPM_NA,
76 },
77 { .vendor = OCP_VENDOR_IBM,
78 .function = OCP_FUNC_16550,
79 .index = 0,
80 .paddr = UART0_IO_BASE,
81 .irq = UART0_INT,
82 .pm = IBM_CPM_UART0
83 },
84 { .vendor = OCP_VENDOR_IBM,
85 .function = OCP_FUNC_16550,
86 .index = 1,
87 .paddr = UART1_IO_BASE,
88 .irq = UART1_INT,
89 .pm = IBM_CPM_UART1
90 },
91 { .vendor = OCP_VENDOR_IBM,
92 .function = OCP_FUNC_IIC,
93 .paddr = 0xEF600500,
94 .irq = 2,
95 .pm = IBM_CPM_IIC0,
96 .additions = &ibm405ep_iic0_def,
97 .show = &ocp_show_iic_data
98 },
99 { .vendor = OCP_VENDOR_IBM,
100 .function = OCP_FUNC_GPIO,
101 .paddr = 0xEF600700,
102 .irq = OCP_IRQ_NA,
103 .pm = IBM_CPM_GPIO0
104 },
105 { .vendor = OCP_VENDOR_IBM,
106 .function = OCP_FUNC_MAL,
107 .paddr = OCP_PADDR_NA,
108 .irq = OCP_IRQ_NA,
109 .pm = OCP_CPM_NA,
110 .additions = &ibm405ep_mal0_def,
111 .show = &ocp_show_mal_data
112 },
113 { .vendor = OCP_VENDOR_IBM,
114 .function = OCP_FUNC_EMAC,
115 .index = 0,
116 .paddr = EMAC0_BASE,
117 .irq = 15,
118 .pm = OCP_CPM_NA,
119 .additions = &ibm405ep_emac0_def,
120 .show = &ocp_show_emac_data
121 },
122 { .vendor = OCP_VENDOR_IBM,
123 .function = OCP_FUNC_EMAC,
124 .index = 1,
125 .paddr = 0xEF600900,
126 .irq = 17,
127 .pm = OCP_CPM_NA,
128 .additions = &ibm405ep_emac1_def,
129 .show = &ocp_show_emac_data
130 },
131 { .vendor = OCP_VENDOR_INVALID
132 }
133};
134
135/* Polarity and triggering settings for internal interrupt sources */
136struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
137 { .polarity = 0xffff7f80,
138 .triggering = 0x00000000,
139 .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
140 }
141};
diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h
deleted file mode 100644
index 3ef20a547080..000000000000
--- a/arch/ppc/platforms/4xx/ibm405ep.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * IBM PPC 405EP processor defines.
3 *
4 * Author: SAW (IBM), derived from ibm405gp.h.
5 * Maintained by MontaVista Software <source@mvista.com>
6 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __ASM_IBM405EP_H__
15#define __ASM_IBM405EP_H__
16
17
18/* ibm405.h at bottom of this file */
19
20/* PCI
21 * PCI Bridge config reg definitions
22 * see 17-19 of manual
23 */
24
25#define PPC405_PCI_CONFIG_ADDR 0xeec00000
26#define PPC405_PCI_CONFIG_DATA 0xeec00004
27
28#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
29 /* setbat */
30#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
31#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
32#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
33
34#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
35#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
36#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
37#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
38
39#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
40
41#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
42#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
43#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
44#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
45#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
46#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
47#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
48#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
49#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
50#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
51#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
52#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
53
54/* serial port defines */
55#define RS_TABLE_SIZE 2
56
57#define UART0_INT 0
58#define UART1_INT 1
59
60#define PCIL0_BASE 0xEF400000
61#define UART0_IO_BASE 0xEF600300
62#define UART1_IO_BASE 0xEF600400
63#define EMAC0_BASE 0xEF600800
64
65#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
66
67#if defined(CONFIG_UART0_TTYS0)
68#define ACTING_UART0_IO_BASE UART0_IO_BASE
69#define ACTING_UART1_IO_BASE UART1_IO_BASE
70#define ACTING_UART0_INT UART0_INT
71#define ACTING_UART1_INT UART1_INT
72#else
73#define ACTING_UART0_IO_BASE UART1_IO_BASE
74#define ACTING_UART1_IO_BASE UART0_IO_BASE
75#define ACTING_UART0_INT UART1_INT
76#define ACTING_UART1_INT UART0_INT
77#endif
78
79#define STD_UART_OP(num) \
80 { 0, BASE_BAUD, 0, ACTING_UART##num##_INT, \
81 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
82 iomem_base: (u8 *)ACTING_UART##num##_IO_BASE, \
83 io_type: SERIAL_IO_MEM},
84
85#define SERIAL_DEBUG_IO_BASE ACTING_UART0_IO_BASE
86#define SERIAL_PORT_DFNS \
87 STD_UART_OP(0) \
88 STD_UART_OP(1)
89
90/* DCR defines */
91#define DCRN_CPMSR_BASE 0x0BA
92#define DCRN_CPMFR_BASE 0x0B9
93
94#define DCRN_CPC0_PLLMR0_BASE 0x0F0
95#define DCRN_CPC0_BOOT_BASE 0x0F1
96#define DCRN_CPC0_CR1_BASE 0x0F2
97#define DCRN_CPC0_EPRCSR_BASE 0x0F3
98#define DCRN_CPC0_PLLMR1_BASE 0x0F4
99#define DCRN_CPC0_UCR_BASE 0x0F5
100#define DCRN_CPC0_UCR_U0DIV 0x07F
101#define DCRN_CPC0_SRR_BASE 0x0F6
102#define DCRN_CPC0_JTAGID_BASE 0x0F7
103#define DCRN_CPC0_SPARE_BASE 0x0F8
104#define DCRN_CPC0_PCI_BASE 0x0F9
105
106
107#define IBM_CPM_GPT 0x80000000 /* GPT interface */
108#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
109#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */
110#define IBM_CPM_CPU 0x00008000 /* processor core */
111#define IBM_CPM_EBC 0x00002000 /* EBC controller */
112#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */
113#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */
114#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
115#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
116#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
117#define IBM_CPM_DMA 0x00000040 /* DMA controller */
118#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
119#define IBM_CPM_UART1 0x00000002 /* serial port 0 */
120#define IBM_CPM_UART0 0x00000001 /* serial port 1 */
121#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
122 | IBM_CPM_OPB | IBM_CPM_EBC \
123 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
124 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
125#define DCRN_DMA0_BASE 0x100
126#define DCRN_DMA1_BASE 0x108
127#define DCRN_DMA2_BASE 0x110
128#define DCRN_DMA3_BASE 0x118
129#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
130#define DCRN_DMASR_BASE 0x120
131#define DCRN_EBC_BASE 0x012
132#define DCRN_DCP0_BASE 0x014
133#define DCRN_MAL_BASE 0x180
134#define DCRN_OCM0_BASE 0x018
135#define DCRN_PLB0_BASE 0x084
136#define DCRN_PLLMR_BASE 0x0B0
137#define DCRN_POB0_BASE 0x0A0
138#define DCRN_SDRAM0_BASE 0x010
139#define DCRN_UIC0_BASE 0x0C0
140#define UIC0 DCRN_UIC0_BASE
141
142#include <asm/ibm405.h>
143
144#endif /* __ASM_IBM405EP_H__ */
145#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c
deleted file mode 100644
index 2ac67a2f0ba6..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gp.c
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 *
3 * Copyright 2000-2001 MontaVista Software Inc.
4 * Original author: Armin Kuster akuster@mvista.com
5 *
6 * Module name: ibm405gp.c
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/smp.h>
18#include <linux/threads.h>
19#include <linux/param.h>
20#include <linux/string.h>
21#include <platforms/4xx/ibm405gp.h>
22#include <asm/ibm4xx.h>
23#include <asm/ocp.h>
24#include <asm/ppc4xx_pic.h>
25
26static struct ocp_func_emac_data ibm405gp_emac0_def = {
27 .rgmii_idx = -1, /* No RGMII */
28 .rgmii_mux = -1, /* No RGMII */
29 .zmii_idx = -1, /* ZMII device index */
30 .zmii_mux = 0, /* ZMII input of this EMAC */
31 .mal_idx = 0, /* MAL device index */
32 .mal_rx_chan = 0, /* MAL rx channel number */
33 .mal_tx_chan = 0, /* MAL tx channel number */
34 .wol_irq = 9, /* WOL interrupt number */
35 .mdio_idx = -1, /* No shared MDIO */
36 .tah_idx = -1, /* No TAH */
37};
38OCP_SYSFS_EMAC_DATA()
39
40static struct ocp_func_mal_data ibm405gp_mal0_def = {
41 .num_tx_chans = 1, /* Number of TX channels */
42 .num_rx_chans = 1, /* Number of RX channels */
43 .txeob_irq = 11, /* TX End Of Buffer IRQ */
44 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
45 .txde_irq = 13, /* TX Descriptor Error IRQ */
46 .rxde_irq = 14, /* RX Descriptor Error IRQ */
47 .serr_irq = 10, /* MAL System Error IRQ */
48 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
49};
50OCP_SYSFS_MAL_DATA()
51
52static struct ocp_func_iic_data ibm405gp_iic0_def = {
53 .fast_mode = 0, /* Use standad mode (100Khz) */
54};
55OCP_SYSFS_IIC_DATA()
56
57struct ocp_def core_ocp[] = {
58 { .vendor = OCP_VENDOR_IBM,
59 .function = OCP_FUNC_OPB,
60 .index = 0,
61 .paddr = 0xEF600000,
62 .irq = OCP_IRQ_NA,
63 .pm = OCP_CPM_NA,
64 },
65 { .vendor = OCP_VENDOR_IBM,
66 .function = OCP_FUNC_16550,
67 .index = 0,
68 .paddr = UART0_IO_BASE,
69 .irq = UART0_INT,
70 .pm = IBM_CPM_UART0
71 },
72 { .vendor = OCP_VENDOR_IBM,
73 .function = OCP_FUNC_16550,
74 .index = 1,
75 .paddr = UART1_IO_BASE,
76 .irq = UART1_INT,
77 .pm = IBM_CPM_UART1
78 },
79 { .vendor = OCP_VENDOR_IBM,
80 .function = OCP_FUNC_IIC,
81 .paddr = 0xEF600500,
82 .irq = 2,
83 .pm = IBM_CPM_IIC0,
84 .additions = &ibm405gp_iic0_def,
85 .show = &ocp_show_iic_data,
86 },
87 { .vendor = OCP_VENDOR_IBM,
88 .function = OCP_FUNC_GPIO,
89 .paddr = 0xEF600700,
90 .irq = OCP_IRQ_NA,
91 .pm = IBM_CPM_GPIO0
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_MAL,
95 .paddr = OCP_PADDR_NA,
96 .irq = OCP_IRQ_NA,
97 .pm = OCP_CPM_NA,
98 .additions = &ibm405gp_mal0_def,
99 .show = &ocp_show_mal_data,
100 },
101 { .vendor = OCP_VENDOR_IBM,
102 .function = OCP_FUNC_EMAC,
103 .index = 0,
104 .paddr = EMAC0_BASE,
105 .irq = 15,
106 .pm = IBM_CPM_EMAC0,
107 .additions = &ibm405gp_emac0_def,
108 .show = &ocp_show_emac_data,
109 },
110 { .vendor = OCP_VENDOR_INVALID
111 }
112};
113
114/* Polarity and triggering settings for internal interrupt sources */
115struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
116 { .polarity = 0xffffff80,
117 .triggering = 0x10000000,
118 .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
119 }
120};
diff --git a/arch/ppc/platforms/4xx/ibm405gp.h b/arch/ppc/platforms/4xx/ibm405gp.h
deleted file mode 100644
index 9f15e5518719..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gp.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Author: Armin Kuster akuster@mvista.com
3 *
4 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBM405GP_H__
12#define __ASM_IBM405GP_H__
13
14
15/* ibm405.h at bottom of this file */
16
17/* PCI
18 * PCI Bridge config reg definitions
19 * see 17-19 of manual
20 */
21
22#define PPC405_PCI_CONFIG_ADDR 0xeec00000
23#define PPC405_PCI_CONFIG_DATA 0xeec00004
24
25#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
26 /* setbat */
27#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
28#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
29#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
30
31#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
32#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
33#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
34#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
35
36#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
37
38#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
39#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
40#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
41#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
42#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
43#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
44#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
45#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
46#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
47#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
48#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
49#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
50
51/* serial port defines */
52#define RS_TABLE_SIZE 2
53
54#define UART0_INT 0
55#define UART1_INT 1
56
57#define PCIL0_BASE 0xEF400000
58#define UART0_IO_BASE 0xEF600300
59#define UART1_IO_BASE 0xEF600400
60#define EMAC0_BASE 0xEF600800
61
62#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
63
64#define STD_UART_OP(num) \
65 { 0, BASE_BAUD, 0, UART##num##_INT, \
66 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
67 iomem_base: (u8 *)UART##num##_IO_BASE, \
68 io_type: SERIAL_IO_MEM},
69
70#if defined(CONFIG_UART0_TTYS0)
71#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
72#define SERIAL_PORT_DFNS \
73 STD_UART_OP(0) \
74 STD_UART_OP(1)
75#endif
76
77#if defined(CONFIG_UART0_TTYS1)
78#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
79#define SERIAL_PORT_DFNS \
80 STD_UART_OP(1) \
81 STD_UART_OP(0)
82#endif
83
84/* DCR defines */
85#define DCRN_CHCR_BASE 0x0B1
86#define DCRN_CHPSR_BASE 0x0B4
87#define DCRN_CPMSR_BASE 0x0B8
88#define DCRN_CPMFR_BASE 0x0BA
89
90#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
91#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
92#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
93#define CHR1_CETE 0x00800000 /* CPU external timer enable */
94
95#define DCRN_CHPSR_BASE 0x0B4
96#define PSR_PLL_FWD_MASK 0xC0000000
97#define PSR_PLL_FDBACK_MASK 0x30000000
98#define PSR_PLL_TUNING_MASK 0x0E000000
99#define PSR_PLB_CPU_MASK 0x01800000
100#define PSR_OPB_PLB_MASK 0x00600000
101#define PSR_PCI_PLB_MASK 0x00180000
102#define PSR_EB_PLB_MASK 0x00060000
103#define PSR_ROM_WIDTH_MASK 0x00018000
104#define PSR_ROM_LOC 0x00004000
105#define PSR_PCI_ASYNC_EN 0x00001000
106#define PSR_PCI_ARBIT_EN 0x00000400
107
108#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
109#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
110#define IBM_CPM_CPU 0x20000000 /* processor core */
111#define IBM_CPM_DMA 0x10000000 /* DMA controller */
112#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
113#define IBM_CPM_DCP 0x04000000 /* CodePack */
114#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
115#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
116#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
117#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
118#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
119#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
120#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
121#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
122#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
123#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
124 | IBM_CPM_OPB | IBM_CPM_EBC \
125 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
126 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
127
128#define DCRN_DMA0_BASE 0x100
129#define DCRN_DMA1_BASE 0x108
130#define DCRN_DMA2_BASE 0x110
131#define DCRN_DMA3_BASE 0x118
132#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
133#define DCRN_DMASR_BASE 0x120
134#define DCRN_EBC_BASE 0x012
135#define DCRN_DCP0_BASE 0x014
136#define DCRN_MAL_BASE 0x180
137#define DCRN_OCM0_BASE 0x018
138#define DCRN_PLB0_BASE 0x084
139#define DCRN_PLLMR_BASE 0x0B0
140#define DCRN_POB0_BASE 0x0A0
141#define DCRN_SDRAM0_BASE 0x010
142#define DCRN_UIC0_BASE 0x0C0
143#define UIC0 DCRN_UIC0_BASE
144
145#include <asm/ibm405.h>
146
147#endif /* __ASM_IBM405GP_H__ */
148#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c
deleted file mode 100644
index 9f4dacffdbb3..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gpr.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <linux/smp.h>
12#include <linux/threads.h>
13#include <linux/param.h>
14#include <linux/string.h>
15#include <platforms/4xx/ibm405gpr.h>
16#include <asm/ibm4xx.h>
17#include <asm/ocp.h>
18#include <asm/ppc4xx_pic.h>
19
20static struct ocp_func_emac_data ibm405gpr_emac0_def = {
21 .rgmii_idx = -1, /* No RGMII */
22 .rgmii_mux = -1, /* No RGMII */
23 .zmii_idx = -1, /* ZMII device index */
24 .zmii_mux = 0, /* ZMII input of this EMAC */
25 .mal_idx = 0, /* MAL device index */
26 .mal_rx_chan = 0, /* MAL rx channel number */
27 .mal_tx_chan = 0, /* MAL tx channel number */
28 .wol_irq = 9, /* WOL interrupt number */
29 .mdio_idx = -1, /* No shared MDIO */
30 .tah_idx = -1, /* No TAH */
31};
32OCP_SYSFS_EMAC_DATA()
33
34static struct ocp_func_mal_data ibm405gpr_mal0_def = {
35 .num_tx_chans = 1, /* Number of TX channels */
36 .num_rx_chans = 1, /* Number of RX channels */
37 .txeob_irq = 11, /* TX End Of Buffer IRQ */
38 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
39 .txde_irq = 13, /* TX Descriptor Error IRQ */
40 .rxde_irq = 14, /* RX Descriptor Error IRQ */
41 .serr_irq = 10, /* MAL System Error IRQ */
42 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
43};
44OCP_SYSFS_MAL_DATA()
45
46static struct ocp_func_iic_data ibm405gpr_iic0_def = {
47 .fast_mode = 0, /* Use standad mode (100Khz) */
48};
49
50OCP_SYSFS_IIC_DATA()
51
52struct ocp_def core_ocp[] = {
53 { .vendor = OCP_VENDOR_IBM,
54 .function = OCP_FUNC_OPB,
55 .index = 0,
56 .paddr = 0xEF600000,
57 .irq = OCP_IRQ_NA,
58 .pm = OCP_CPM_NA,
59 },
60 { .vendor = OCP_VENDOR_IBM,
61 .function = OCP_FUNC_16550,
62 .index = 0,
63 .paddr = UART0_IO_BASE,
64 .irq = UART0_INT,
65 .pm = IBM_CPM_UART0
66 },
67 { .vendor = OCP_VENDOR_IBM,
68 .function = OCP_FUNC_16550,
69 .index = 1,
70 .paddr = UART1_IO_BASE,
71 .irq = UART1_INT,
72 .pm = IBM_CPM_UART1
73 },
74 { .vendor = OCP_VENDOR_IBM,
75 .function = OCP_FUNC_IIC,
76 .paddr = 0xEF600500,
77 .irq = 2,
78 .pm = IBM_CPM_IIC0,
79 .additions = &ibm405gpr_iic0_def,
80 .show = &ocp_show_iic_data,
81 },
82 { .vendor = OCP_VENDOR_IBM,
83 .function = OCP_FUNC_GPIO,
84 .paddr = 0xEF600700,
85 .irq = OCP_IRQ_NA,
86 .pm = IBM_CPM_GPIO0
87 },
88 { .vendor = OCP_VENDOR_IBM,
89 .function = OCP_FUNC_MAL,
90 .paddr = OCP_PADDR_NA,
91 .irq = OCP_IRQ_NA,
92 .pm = OCP_CPM_NA,
93 .additions = &ibm405gpr_mal0_def,
94 .show = &ocp_show_mal_data,
95 },
96 { .vendor = OCP_VENDOR_IBM,
97 .function = OCP_FUNC_EMAC,
98 .index = 0,
99 .paddr = EMAC0_BASE,
100 .irq = 15,
101 .pm = IBM_CPM_EMAC0,
102 .additions = &ibm405gpr_emac0_def,
103 .show = &ocp_show_emac_data,
104 },
105 { .vendor = OCP_VENDOR_INVALID
106 }
107};
108
109/* Polarity and triggering settings for internal interrupt sources */
110struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
111 { .polarity = 0xffffe000,
112 .triggering = 0x10000000,
113 .ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */
114 }
115};
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.h b/arch/ppc/platforms/4xx/ibm405gpr.h
deleted file mode 100644
index 9e01f1515de3..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gpr.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBM405GPR_H__
12#define __ASM_IBM405GPR_H__
13
14
15/* ibm405.h at bottom of this file */
16
17/* PCI
18 * PCI Bridge config reg definitions
19 * see 17-19 of manual
20 */
21
22#define PPC405_PCI_CONFIG_ADDR 0xeec00000
23#define PPC405_PCI_CONFIG_DATA 0xeec00004
24
25#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
26 /* setbat */
27#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
28#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
29#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
30
31#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
32#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
33#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
34#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
35
36#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
37
38#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
39#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
40#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
41#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
42#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
43#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
44#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
45#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
46#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
47#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
48#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
49#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
50
51/* serial port defines */
52#define RS_TABLE_SIZE 2
53
54#define UART0_INT 0
55#define UART1_INT 1
56
57#define PCIL0_BASE 0xEF400000
58#define UART0_IO_BASE 0xEF600300
59#define UART1_IO_BASE 0xEF600400
60#define EMAC0_BASE 0xEF600800
61
62#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
63
64#define STD_UART_OP(num) \
65 { 0, BASE_BAUD, 0, UART##num##_INT, \
66 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
67 iomem_base: (u8 *)UART##num##_IO_BASE, \
68 io_type: SERIAL_IO_MEM},
69
70#if defined(CONFIG_UART0_TTYS0)
71#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
72#define SERIAL_PORT_DFNS \
73 STD_UART_OP(0) \
74 STD_UART_OP(1)
75#endif
76
77#if defined(CONFIG_UART0_TTYS1)
78#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
79#define SERIAL_PORT_DFNS \
80 STD_UART_OP(1) \
81 STD_UART_OP(0)
82#endif
83
84/* DCR defines */
85#define DCRN_CHCR_BASE 0x0B1
86#define DCRN_CHPSR_BASE 0x0B4
87#define DCRN_CPMSR_BASE 0x0B8
88#define DCRN_CPMFR_BASE 0x0BA
89
90#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
91#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
92#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
93#define CHR1_CETE 0x00800000 /* CPU external timer enable */
94
95#define DCRN_CHPSR_BASE 0x0B4
96#define PSR_PLL_FWD_MASK 0xC0000000
97#define PSR_PLL_FDBACK_MASK 0x30000000
98#define PSR_PLL_TUNING_MASK 0x0E000000
99#define PSR_PLB_CPU_MASK 0x01800000
100#define PSR_OPB_PLB_MASK 0x00600000
101#define PSR_PCI_PLB_MASK 0x00180000
102#define PSR_EB_PLB_MASK 0x00060000
103#define PSR_ROM_WIDTH_MASK 0x00018000
104#define PSR_ROM_LOC 0x00004000
105#define PSR_PCI_ASYNC_EN 0x00001000
106#define PSR_PCI_ARBIT_EN 0x00000400
107
108#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
109#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
110#define IBM_CPM_CPU 0x20000000 /* processor core */
111#define IBM_CPM_DMA 0x10000000 /* DMA controller */
112#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
113#define IBM_CPM_DCP 0x04000000 /* CodePack */
114#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
115#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
116#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
117#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
118#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
119#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
120#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
121#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
122#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
123#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
124 | IBM_CPM_OPB | IBM_CPM_EBC \
125 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
126 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
127
128#define DCRN_DMA0_BASE 0x100
129#define DCRN_DMA1_BASE 0x108
130#define DCRN_DMA2_BASE 0x110
131#define DCRN_DMA3_BASE 0x118
132#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
133#define DCRN_DMASR_BASE 0x120
134#define DCRN_EBC_BASE 0x012
135#define DCRN_DCP0_BASE 0x014
136#define DCRN_MAL_BASE 0x180
137#define DCRN_OCM0_BASE 0x018
138#define DCRN_PLB0_BASE 0x084
139#define DCRN_PLLMR_BASE 0x0B0
140#define DCRN_POB0_BASE 0x0A0
141#define DCRN_SDRAM0_BASE 0x010
142#define DCRN_UIC0_BASE 0x0C0
143#define UIC0 DCRN_UIC0_BASE
144
145#include <asm/ibm405.h>
146
147#endif /* __ASM_IBM405GPR_H__ */
148#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
deleted file mode 100644
index 0de91532aabb..000000000000
--- a/arch/ppc/platforms/4xx/ibm440ep.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * PPC440EP I/O descriptions
3 *
4 * Wade Farnsworth <wfarnsworth@mvista.com>
5 * Copyright 2004 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <platforms/4xx/ibm440ep.h>
17#include <asm/ocp.h>
18#include <asm/ppc4xx_pic.h>
19
20static struct ocp_func_emac_data ibm440ep_emac0_def = {
21 .rgmii_idx = -1, /* No RGMII */
22 .rgmii_mux = -1, /* No RGMII */
23 .zmii_idx = 0, /* ZMII device index */
24 .zmii_mux = 0, /* ZMII input of this EMAC */
25 .mal_idx = 0, /* MAL device index */
26 .mal_rx_chan = 0, /* MAL rx channel number */
27 .mal_tx_chan = 0, /* MAL tx channel number */
28 .wol_irq = 61, /* WOL interrupt number */
29 .mdio_idx = -1, /* No shared MDIO */
30 .tah_idx = -1, /* No TAH */
31};
32
33static struct ocp_func_emac_data ibm440ep_emac1_def = {
34 .rgmii_idx = -1, /* No RGMII */
35 .rgmii_mux = -1, /* No RGMII */
36 .zmii_idx = 0, /* ZMII device index */
37 .zmii_mux = 1, /* ZMII input of this EMAC */
38 .mal_idx = 0, /* MAL device index */
39 .mal_rx_chan = 1, /* MAL rx channel number */
40 .mal_tx_chan = 2, /* MAL tx channel number */
41 .wol_irq = 63, /* WOL interrupt number */
42 .mdio_idx = -1, /* No shared MDIO */
43 .tah_idx = -1, /* No TAH */
44};
45OCP_SYSFS_EMAC_DATA()
46
47static struct ocp_func_mal_data ibm440ep_mal0_def = {
48 .num_tx_chans = 4, /* Number of TX channels */
49 .num_rx_chans = 2, /* Number of RX channels */
50 .txeob_irq = 10, /* TX End Of Buffer IRQ */
51 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
52 .txde_irq = 33, /* TX Descriptor Error IRQ */
53 .rxde_irq = 34, /* RX Descriptor Error IRQ */
54 .serr_irq = 32, /* MAL System Error IRQ */
55 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
56};
57OCP_SYSFS_MAL_DATA()
58
59static struct ocp_func_iic_data ibm440ep_iic0_def = {
60 .fast_mode = 0, /* Use standad mode (100Khz) */
61};
62
63static struct ocp_func_iic_data ibm440ep_iic1_def = {
64 .fast_mode = 0, /* Use standad mode (100Khz) */
65};
66OCP_SYSFS_IIC_DATA()
67
68struct ocp_def core_ocp[] = {
69 { .vendor = OCP_VENDOR_IBM,
70 .function = OCP_FUNC_OPB,
71 .index = 0,
72 .paddr = 0x0EF600000ULL,
73 .irq = OCP_IRQ_NA,
74 .pm = OCP_CPM_NA,
75 },
76 { .vendor = OCP_VENDOR_IBM,
77 .function = OCP_FUNC_16550,
78 .index = 0,
79 .paddr = PPC440EP_UART0_ADDR,
80 .irq = UART0_INT,
81 .pm = IBM_CPM_UART0,
82 },
83 { .vendor = OCP_VENDOR_IBM,
84 .function = OCP_FUNC_16550,
85 .index = 1,
86 .paddr = PPC440EP_UART1_ADDR,
87 .irq = UART1_INT,
88 .pm = IBM_CPM_UART1,
89 },
90 { .vendor = OCP_VENDOR_IBM,
91 .function = OCP_FUNC_16550,
92 .index = 2,
93 .paddr = PPC440EP_UART2_ADDR,
94 .irq = UART2_INT,
95 .pm = IBM_CPM_UART2,
96 },
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_16550,
99 .index = 3,
100 .paddr = PPC440EP_UART3_ADDR,
101 .irq = UART3_INT,
102 .pm = IBM_CPM_UART3,
103 },
104 { .vendor = OCP_VENDOR_IBM,
105 .function = OCP_FUNC_IIC,
106 .index = 0,
107 .paddr = 0x0EF600700ULL,
108 .irq = 2,
109 .pm = IBM_CPM_IIC0,
110 .additions = &ibm440ep_iic0_def,
111 .show = &ocp_show_iic_data
112 },
113 { .vendor = OCP_VENDOR_IBM,
114 .function = OCP_FUNC_IIC,
115 .index = 1,
116 .paddr = 0x0EF600800ULL,
117 .irq = 7,
118 .pm = IBM_CPM_IIC1,
119 .additions = &ibm440ep_iic1_def,
120 .show = &ocp_show_iic_data
121 },
122 { .vendor = OCP_VENDOR_IBM,
123 .function = OCP_FUNC_GPIO,
124 .index = 0,
125 .paddr = 0x0EF600B00ULL,
126 .irq = OCP_IRQ_NA,
127 .pm = IBM_CPM_GPIO0,
128 },
129 { .vendor = OCP_VENDOR_IBM,
130 .function = OCP_FUNC_GPIO,
131 .index = 1,
132 .paddr = 0x0EF600C00ULL,
133 .irq = OCP_IRQ_NA,
134 .pm = OCP_CPM_NA,
135 },
136 { .vendor = OCP_VENDOR_IBM,
137 .function = OCP_FUNC_MAL,
138 .paddr = OCP_PADDR_NA,
139 .irq = OCP_IRQ_NA,
140 .pm = OCP_CPM_NA,
141 .additions = &ibm440ep_mal0_def,
142 .show = &ocp_show_mal_data,
143 },
144 { .vendor = OCP_VENDOR_IBM,
145 .function = OCP_FUNC_EMAC,
146 .index = 0,
147 .paddr = 0x0EF600E00ULL,
148 .irq = 60,
149 .pm = OCP_CPM_NA,
150 .additions = &ibm440ep_emac0_def,
151 .show = &ocp_show_emac_data,
152 },
153 { .vendor = OCP_VENDOR_IBM,
154 .function = OCP_FUNC_EMAC,
155 .index = 1,
156 .paddr = 0x0EF600F00ULL,
157 .irq = 62,
158 .pm = OCP_CPM_NA,
159 .additions = &ibm440ep_emac1_def,
160 .show = &ocp_show_emac_data,
161 },
162 { .vendor = OCP_VENDOR_IBM,
163 .function = OCP_FUNC_ZMII,
164 .paddr = 0x0EF600D00ULL,
165 .irq = OCP_IRQ_NA,
166 .pm = OCP_CPM_NA,
167 },
168 { .vendor = OCP_VENDOR_INVALID
169 }
170};
171
172/* Polarity and triggering settings for internal interrupt sources */
173struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
174 { .polarity = 0xffbffe03,
175 .triggering = 0x00000000,
176 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
177 },
178 { .polarity = 0xffffc6af,
179 .triggering = 0x06000140,
180 .ext_irq_mask = 0x00003800, /* IRQ7 - IRQ9 */
181 },
182};
183
184static struct resource usb_gadget_resources[] = {
185 [0] = {
186 .start = 0x050000100ULL,
187 .end = 0x05000017FULL,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = 55,
192 .end = 55,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
197static u64 dma_mask = 0xffffffffULL;
198
199static struct platform_device usb_gadget_device = {
200 .name = "musbhsfc",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(usb_gadget_resources),
203 .resource = usb_gadget_resources,
204 .dev = {
205 .dma_mask = &dma_mask,
206 .coherent_dma_mask = 0xffffffffULL,
207 }
208};
209
210static struct platform_device *ibm440ep_devs[] __initdata = {
211 &usb_gadget_device,
212};
213
214static int __init
215ibm440ep_platform_add_devices(void)
216{
217 return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
218}
219arch_initcall(ibm440ep_platform_add_devices);
220
diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h
deleted file mode 100644
index d92572727d20..000000000000
--- a/arch/ppc/platforms/4xx/ibm440ep.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * PPC440EP definitions
3 *
4 * Wade Farnsworth <wfarnsworth@mvista.com>
5 *
6 * Copyright 2002 Roland Dreier
7 * Copyright 2004 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifdef __KERNEL__
17#ifndef __PPC_PLATFORMS_IBM440EP_H
18#define __PPC_PLATFORMS_IBM440EP_H
19
20#include <asm/ibm44x.h>
21
22/* UART */
23#define PPC440EP_UART0_ADDR 0x0EF600300
24#define PPC440EP_UART1_ADDR 0x0EF600400
25#define PPC440EP_UART2_ADDR 0x0EF600500
26#define PPC440EP_UART3_ADDR 0x0EF600600
27#define UART0_INT 0
28#define UART1_INT 1
29#define UART2_INT 3
30#define UART3_INT 4
31
32/* Clock and Power Management */
33#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
34#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
35#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
36#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
37#define IBM_CPM_FPU 0x04000000 /* floating point unit */
38#define IBM_CPM_CPU 0x02000000 /* processor core */
39#define IBM_CPM_DMA 0x01000000 /* DMA controller */
40#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
41#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
42#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
43#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
44#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
45#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
46#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
47#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
48#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
49#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
50#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
51#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
52#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
53#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
54#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
55#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
56#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
57#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
58#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
59#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
60#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
61#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
62#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
63
64#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
65 | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
66 | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
67 | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
68 | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
69 | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
70
71
72#endif /* __PPC_PLATFORMS_IBM440EP_H */
73#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c
deleted file mode 100644
index b67a72e5c6fe..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gp.c
+++ /dev/null
@@ -1,163 +0,0 @@
1/*
2 * PPC440GP I/O descriptions
3 *
4 * Matt Porter <mporter@mvista.com>
5 * Copyright 2002-2004 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003, 2004 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/init.h>
17#include <linux/module.h>
18#include <platforms/4xx/ibm440gp.h>
19#include <asm/ocp.h>
20#include <asm/ppc4xx_pic.h>
21
22static struct ocp_func_emac_data ibm440gp_emac0_def = {
23 .rgmii_idx = -1, /* No RGMII */
24 .rgmii_mux = -1, /* No RGMII */
25 .zmii_idx = 0, /* ZMII device index */
26 .zmii_mux = 0, /* ZMII input of this EMAC */
27 .mal_idx = 0, /* MAL device index */
28 .mal_rx_chan = 0, /* MAL rx channel number */
29 .mal_tx_chan = 0, /* MAL tx channel number */
30 .wol_irq = 61, /* WOL interrupt number */
31 .mdio_idx = -1, /* No shared MDIO */
32 .tah_idx = -1, /* No TAH */
33};
34
35static struct ocp_func_emac_data ibm440gp_emac1_def = {
36 .rgmii_idx = -1, /* No RGMII */
37 .rgmii_mux = -1, /* No RGMII */
38 .zmii_idx = 0, /* ZMII device index */
39 .zmii_mux = 1, /* ZMII input of this EMAC */
40 .mal_idx = 0, /* MAL device index */
41 .mal_rx_chan = 1, /* MAL rx channel number */
42 .mal_tx_chan = 2, /* MAL tx channel number */
43 .wol_irq = 63, /* WOL interrupt number */
44 .mdio_idx = -1, /* No shared MDIO */
45 .tah_idx = -1, /* No TAH */
46};
47OCP_SYSFS_EMAC_DATA()
48
49static struct ocp_func_mal_data ibm440gp_mal0_def = {
50 .num_tx_chans = 4, /* Number of TX channels */
51 .num_rx_chans = 2, /* Number of RX channels */
52 .txeob_irq = 10, /* TX End Of Buffer IRQ */
53 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
54 .txde_irq = 33, /* TX Descriptor Error IRQ */
55 .rxde_irq = 34, /* RX Descriptor Error IRQ */
56 .serr_irq = 32, /* MAL System Error IRQ */
57 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
58};
59OCP_SYSFS_MAL_DATA()
60
61static struct ocp_func_iic_data ibm440gp_iic0_def = {
62 .fast_mode = 0, /* Use standad mode (100Khz) */
63};
64
65static struct ocp_func_iic_data ibm440gp_iic1_def = {
66 .fast_mode = 0, /* Use standad mode (100Khz) */
67};
68OCP_SYSFS_IIC_DATA()
69
70struct ocp_def core_ocp[] = {
71 { .vendor = OCP_VENDOR_IBM,
72 .function = OCP_FUNC_OPB,
73 .index = 0,
74 .paddr = 0x0000000140000000ULL,
75 .irq = OCP_IRQ_NA,
76 .pm = OCP_CPM_NA,
77 },
78 { .vendor = OCP_VENDOR_IBM,
79 .function = OCP_FUNC_16550,
80 .index = 0,
81 .paddr = PPC440GP_UART0_ADDR,
82 .irq = UART0_INT,
83 .pm = IBM_CPM_UART0,
84 },
85 { .vendor = OCP_VENDOR_IBM,
86 .function = OCP_FUNC_16550,
87 .index = 1,
88 .paddr = PPC440GP_UART1_ADDR,
89 .irq = UART1_INT,
90 .pm = IBM_CPM_UART1,
91 },
92 { .vendor = OCP_VENDOR_IBM,
93 .function = OCP_FUNC_IIC,
94 .index = 0,
95 .paddr = 0x0000000140000400ULL,
96 .irq = 2,
97 .pm = IBM_CPM_IIC0,
98 .additions = &ibm440gp_iic0_def,
99 .show = &ocp_show_iic_data
100 },
101 { .vendor = OCP_VENDOR_IBM,
102 .function = OCP_FUNC_IIC,
103 .index = 1,
104 .paddr = 0x0000000140000500ULL,
105 .irq = 3,
106 .pm = IBM_CPM_IIC1,
107 .additions = &ibm440gp_iic1_def,
108 .show = &ocp_show_iic_data
109 },
110 { .vendor = OCP_VENDOR_IBM,
111 .function = OCP_FUNC_GPIO,
112 .index = 0,
113 .paddr = 0x0000000140000700ULL,
114 .irq = OCP_IRQ_NA,
115 .pm = IBM_CPM_GPIO0,
116 },
117 { .vendor = OCP_VENDOR_IBM,
118 .function = OCP_FUNC_MAL,
119 .paddr = OCP_PADDR_NA,
120 .irq = OCP_IRQ_NA,
121 .pm = OCP_CPM_NA,
122 .additions = &ibm440gp_mal0_def,
123 .show = &ocp_show_mal_data,
124 },
125 { .vendor = OCP_VENDOR_IBM,
126 .function = OCP_FUNC_EMAC,
127 .index = 0,
128 .paddr = 0x0000000140000800ULL,
129 .irq = 60,
130 .pm = OCP_CPM_NA,
131 .additions = &ibm440gp_emac0_def,
132 .show = &ocp_show_emac_data,
133 },
134 { .vendor = OCP_VENDOR_IBM,
135 .function = OCP_FUNC_EMAC,
136 .index = 1,
137 .paddr = 0x0000000140000900ULL,
138 .irq = 62,
139 .pm = OCP_CPM_NA,
140 .additions = &ibm440gp_emac1_def,
141 .show = &ocp_show_emac_data,
142 },
143 { .vendor = OCP_VENDOR_IBM,
144 .function = OCP_FUNC_ZMII,
145 .paddr = 0x0000000140000780ULL,
146 .irq = OCP_IRQ_NA,
147 .pm = OCP_CPM_NA,
148 },
149 { .vendor = OCP_VENDOR_INVALID
150 }
151};
152
153/* Polarity and triggering settings for internal interrupt sources */
154struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
155 { .polarity = 0xfffffe03,
156 .triggering = 0x01c00000,
157 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
158 },
159 { .polarity = 0xffffc0ff,
160 .triggering = 0x00ff8000,
161 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
162 },
163};
diff --git a/arch/ppc/platforms/4xx/ibm440gp.h b/arch/ppc/platforms/4xx/ibm440gp.h
deleted file mode 100644
index 391c90e1f5ea..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gp.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * PPC440GP definitions
3 *
4 * Roland Dreier <roland@digitalvampire.org>
5 *
6 * Copyright 2002 Roland Dreier
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This file contains code that was originally in the files ibm44x.h
14 * and ebony.h, which were written by Matt Porter of MontaVista Software Inc.
15 */
16
17#ifdef __KERNEL__
18#ifndef __PPC_PLATFORMS_IBM440GP_H
19#define __PPC_PLATFORMS_IBM440GP_H
20
21
22/* UART */
23#define PPC440GP_UART0_ADDR 0x0000000140000200ULL
24#define PPC440GP_UART1_ADDR 0x0000000140000300ULL
25#define UART0_INT 0
26#define UART1_INT 1
27
28/* Clock and Power Management */
29#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
30#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
31#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
32#define IBM_CPM_CPU 0x02000000 /* processor core */
33#define IBM_CPM_DMA 0x01000000 /* DMA controller */
34#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
35#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
36#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
37#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
38#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
39#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
40#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
41#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
42#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
43#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
44#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
45#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
46#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
47#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
48#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
49
50#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
51 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
52 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
53 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI)
54/*
55 * Serial port defines
56 */
57#define RS_TABLE_SIZE 2
58
59#include <asm/ibm44x.h>
60#include <syslib/ibm440gp_common.h>
61
62#endif /* __PPC_PLATFORMS_IBM440GP_H */
63#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
deleted file mode 100644
index 685abffcb6ce..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gx.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * PPC440GX I/O descriptions
3 *
4 * Matt Porter <mporter@mvista.com>
5 * Copyright 2002-2004 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003, 2004 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/init.h>
17#include <linux/module.h>
18#include <platforms/4xx/ibm440gx.h>
19#include <asm/ocp.h>
20#include <asm/ppc4xx_pic.h>
21
22static struct ocp_func_emac_data ibm440gx_emac0_def = {
23 .rgmii_idx = -1, /* No RGMII */
24 .rgmii_mux = -1, /* No RGMII */
25 .zmii_idx = 0, /* ZMII device index */
26 .zmii_mux = 0, /* ZMII input of this EMAC */
27 .mal_idx = 0, /* MAL device index */
28 .mal_rx_chan = 0, /* MAL rx channel number */
29 .mal_tx_chan = 0, /* MAL tx channel number */
30 .wol_irq = 61, /* WOL interrupt number */
31 .mdio_idx = -1, /* No shared MDIO */
32 .tah_idx = -1, /* No TAH */
33};
34
35static struct ocp_func_emac_data ibm440gx_emac1_def = {
36 .rgmii_idx = -1, /* No RGMII */
37 .rgmii_mux = -1, /* No RGMII */
38 .zmii_idx = 0, /* ZMII device index */
39 .zmii_mux = 1, /* ZMII input of this EMAC */
40 .mal_idx = 0, /* MAL device index */
41 .mal_rx_chan = 1, /* MAL rx channel number */
42 .mal_tx_chan = 1, /* MAL tx channel number */
43 .wol_irq = 63, /* WOL interrupt number */
44 .mdio_idx = -1, /* No shared MDIO */
45 .tah_idx = -1, /* No TAH */
46};
47
48static struct ocp_func_emac_data ibm440gx_emac2_def = {
49 .rgmii_idx = 0, /* RGMII device index */
50 .rgmii_mux = 0, /* RGMII input of this EMAC */
51 .zmii_idx = 0, /* ZMII device index */
52 .zmii_mux = 2, /* ZMII input of this EMAC */
53 .mal_idx = 0, /* MAL device index */
54 .mal_rx_chan = 2, /* MAL rx channel number */
55 .mal_tx_chan = 2, /* MAL tx channel number */
56 .wol_irq = 65, /* WOL interrupt number */
57 .mdio_idx = -1, /* No shared MDIO */
58 .tah_idx = 0, /* TAH device index */
59};
60
61static struct ocp_func_emac_data ibm440gx_emac3_def = {
62 .rgmii_idx = 0, /* RGMII device index */
63 .rgmii_mux = 1, /* RGMII input of this EMAC */
64 .zmii_idx = 0, /* ZMII device index */
65 .zmii_mux = 3, /* ZMII input of this EMAC */
66 .mal_idx = 0, /* MAL device index */
67 .mal_rx_chan = 3, /* MAL rx channel number */
68 .mal_tx_chan = 3, /* MAL tx channel number */
69 .wol_irq = 67, /* WOL interrupt number */
70 .mdio_idx = -1, /* No shared MDIO */
71 .tah_idx = 1, /* TAH device index */
72};
73OCP_SYSFS_EMAC_DATA()
74
75static struct ocp_func_mal_data ibm440gx_mal0_def = {
76 .num_tx_chans = 4, /* Number of TX channels */
77 .num_rx_chans = 4, /* Number of RX channels */
78 .txeob_irq = 10, /* TX End Of Buffer IRQ */
79 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
80 .txde_irq = 33, /* TX Descriptor Error IRQ */
81 .rxde_irq = 34, /* RX Descriptor Error IRQ */
82 .serr_irq = 32, /* MAL System Error IRQ */
83 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
84};
85OCP_SYSFS_MAL_DATA()
86
87static struct ocp_func_iic_data ibm440gx_iic0_def = {
88 .fast_mode = 0, /* Use standad mode (100Khz) */
89};
90
91static struct ocp_func_iic_data ibm440gx_iic1_def = {
92 .fast_mode = 0, /* Use standad mode (100Khz) */
93};
94OCP_SYSFS_IIC_DATA()
95
96struct ocp_def core_ocp[] = {
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_OPB,
99 .index = 0,
100 .paddr = 0x0000000140000000ULL,
101 .irq = OCP_IRQ_NA,
102 .pm = OCP_CPM_NA,
103 },
104 { .vendor = OCP_VENDOR_IBM,
105 .function = OCP_FUNC_16550,
106 .index = 0,
107 .paddr = PPC440GX_UART0_ADDR,
108 .irq = UART0_INT,
109 .pm = IBM_CPM_UART0,
110 },
111 { .vendor = OCP_VENDOR_IBM,
112 .function = OCP_FUNC_16550,
113 .index = 1,
114 .paddr = PPC440GX_UART1_ADDR,
115 .irq = UART1_INT,
116 .pm = IBM_CPM_UART1,
117 },
118 { .vendor = OCP_VENDOR_IBM,
119 .function = OCP_FUNC_IIC,
120 .index = 0,
121 .paddr = 0x0000000140000400ULL,
122 .irq = 2,
123 .pm = IBM_CPM_IIC0,
124 .additions = &ibm440gx_iic0_def,
125 .show = &ocp_show_iic_data
126 },
127 { .vendor = OCP_VENDOR_IBM,
128 .function = OCP_FUNC_IIC,
129 .index = 1,
130 .paddr = 0x0000000140000500ULL,
131 .irq = 3,
132 .pm = IBM_CPM_IIC1,
133 .additions = &ibm440gx_iic1_def,
134 .show = &ocp_show_iic_data
135 },
136 { .vendor = OCP_VENDOR_IBM,
137 .function = OCP_FUNC_GPIO,
138 .index = 0,
139 .paddr = 0x0000000140000700ULL,
140 .irq = OCP_IRQ_NA,
141 .pm = IBM_CPM_GPIO0,
142 },
143 { .vendor = OCP_VENDOR_IBM,
144 .function = OCP_FUNC_MAL,
145 .paddr = OCP_PADDR_NA,
146 .irq = OCP_IRQ_NA,
147 .pm = OCP_CPM_NA,
148 .additions = &ibm440gx_mal0_def,
149 .show = &ocp_show_mal_data,
150 },
151 { .vendor = OCP_VENDOR_IBM,
152 .function = OCP_FUNC_EMAC,
153 .index = 0,
154 .paddr = 0x0000000140000800ULL,
155 .irq = 60,
156 .pm = OCP_CPM_NA,
157 .additions = &ibm440gx_emac0_def,
158 .show = &ocp_show_emac_data,
159 },
160 { .vendor = OCP_VENDOR_IBM,
161 .function = OCP_FUNC_EMAC,
162 .index = 1,
163 .paddr = 0x0000000140000900ULL,
164 .irq = 62,
165 .pm = OCP_CPM_NA,
166 .additions = &ibm440gx_emac1_def,
167 .show = &ocp_show_emac_data,
168 },
169 { .vendor = OCP_VENDOR_IBM,
170 .function = OCP_FUNC_EMAC,
171 .index = 2,
172 .paddr = 0x0000000140000C00ULL,
173 .irq = 64,
174 .pm = OCP_CPM_NA,
175 .additions = &ibm440gx_emac2_def,
176 .show = &ocp_show_emac_data,
177 },
178 { .vendor = OCP_VENDOR_IBM,
179 .function = OCP_FUNC_EMAC,
180 .index = 3,
181 .paddr = 0x0000000140000E00ULL,
182 .irq = 66,
183 .pm = OCP_CPM_NA,
184 .additions = &ibm440gx_emac3_def,
185 .show = &ocp_show_emac_data,
186 },
187 { .vendor = OCP_VENDOR_IBM,
188 .function = OCP_FUNC_RGMII,
189 .paddr = 0x0000000140000790ULL,
190 .irq = OCP_IRQ_NA,
191 .pm = OCP_CPM_NA,
192 },
193 { .vendor = OCP_VENDOR_IBM,
194 .function = OCP_FUNC_ZMII,
195 .paddr = 0x0000000140000780ULL,
196 .irq = OCP_IRQ_NA,
197 .pm = OCP_CPM_NA,
198 },
199 { .vendor = OCP_VENDOR_IBM,
200 .function = OCP_FUNC_TAH,
201 .index = 0,
202 .paddr = 0x0000000140000b50ULL,
203 .irq = 68,
204 .pm = OCP_CPM_NA,
205 },
206 { .vendor = OCP_VENDOR_IBM,
207 .function = OCP_FUNC_TAH,
208 .index = 1,
209 .paddr = 0x0000000140000d50ULL,
210 .irq = 69,
211 .pm = OCP_CPM_NA,
212 },
213 { .vendor = OCP_VENDOR_INVALID
214 }
215};
216
217/* Polarity and triggering settings for internal interrupt sources */
218struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
219 { .polarity = 0xfffffe03,
220 .triggering = 0x01c00000,
221 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
222 },
223 { .polarity = 0xffffc0ff,
224 .triggering = 0x00ff8000,
225 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
226 },
227 { .polarity = 0xffff83ff,
228 .triggering = 0x000f83c0,
229 .ext_irq_mask = 0x00007c00, /* IRQ13 - IRQ17 */
230 },
231};
diff --git a/arch/ppc/platforms/4xx/ibm440gx.h b/arch/ppc/platforms/4xx/ibm440gx.h
deleted file mode 100644
index 599c4289b9c2..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gx.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * PPC440GX definitions
3 *
4 * Matt Porter <mporter@mvista.com>
5 *
6 * Copyright 2002 Roland Dreier
7 * Copyright 2003 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifdef __KERNEL__
17#ifndef __PPC_PLATFORMS_IBM440GX_H
18#define __PPC_PLATFORMS_IBM440GX_H
19
20
21#include <asm/ibm44x.h>
22
23/* UART */
24#define PPC440GX_UART0_ADDR 0x0000000140000200ULL
25#define PPC440GX_UART1_ADDR 0x0000000140000300ULL
26#define UART0_INT 0
27#define UART1_INT 1
28
29/* Clock and Power Management */
30#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
31#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
32#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
33#define IBM_CPM_RGMII 0x10000000 /* RGMII */
34#define IBM_CPM_TAHOE0 0x08000000 /* TAHOE 0 */
35#define IBM_CPM_TAHOE1 0x04000000 /* TAHOE 1 */
36#define IBM_CPM_CPU 0x02000000 /* processor core */
37#define IBM_CPM_DMA 0x01000000 /* DMA controller */
38#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
39#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
40#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
41#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
42#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
43#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
44#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
45#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
46#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
47#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
48#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
49#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
50#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
51#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
52#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
53#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
54#define IBM_CPM_EMAC1 0x00000010 /* EMAC 1 */
55#define IBM_CPM_EMAC2 0x00000008 /* EMAC 2 */
56#define IBM_CPM_EMAC3 0x00000004 /* EMAC 3 */
57
58#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
59 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
60 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
61 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
62 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
63 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
64 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
65/*
66 * Serial port defines
67 */
68#define RS_TABLE_SIZE 2
69
70#endif /* __PPC_PLATFORMS_IBM440GX_H */
71#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
deleted file mode 100644
index de8f7ac5623c..000000000000
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * PPC440SP I/O descriptions
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 * Copyright 2002-2005 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003, 2004 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/init.h>
17#include <linux/module.h>
18#include <platforms/4xx/ibm440sp.h>
19#include <asm/ocp.h>
20
21static struct ocp_func_emac_data ibm440sp_emac0_def = {
22 .rgmii_idx = -1, /* No RGMII */
23 .rgmii_mux = -1, /* No RGMII */
24 .zmii_idx = -1, /* No ZMII */
25 .zmii_mux = -1, /* No ZMII */
26 .mal_idx = 0, /* MAL device index */
27 .mal_rx_chan = 0, /* MAL rx channel number */
28 .mal_tx_chan = 0, /* MAL tx channel number */
29 .wol_irq = 61, /* WOL interrupt number */
30 .mdio_idx = -1, /* No shared MDIO */
31 .tah_idx = -1, /* No TAH */
32};
33OCP_SYSFS_EMAC_DATA()
34
35static struct ocp_func_mal_data ibm440sp_mal0_def = {
36 .num_tx_chans = 1, /* Number of TX channels */
37 .num_rx_chans = 1, /* Number of RX channels */
38 .txeob_irq = 38, /* TX End Of Buffer IRQ */
39 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
40 .txde_irq = 34, /* TX Descriptor Error IRQ */
41 .rxde_irq = 35, /* RX Descriptor Error IRQ */
42 .serr_irq = 33, /* MAL System Error IRQ */
43 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
44};
45OCP_SYSFS_MAL_DATA()
46
47static struct ocp_func_iic_data ibm440sp_iic0_def = {
48 .fast_mode = 0, /* Use standad mode (100Khz) */
49};
50
51static struct ocp_func_iic_data ibm440sp_iic1_def = {
52 .fast_mode = 0, /* Use standad mode (100Khz) */
53};
54OCP_SYSFS_IIC_DATA()
55
56struct ocp_def core_ocp[] = {
57 { .vendor = OCP_VENDOR_IBM,
58 .function = OCP_FUNC_OPB,
59 .index = 0,
60 .paddr = 0x0000000140000000ULL,
61 .irq = OCP_IRQ_NA,
62 .pm = OCP_CPM_NA,
63 },
64 { .vendor = OCP_VENDOR_IBM,
65 .function = OCP_FUNC_16550,
66 .index = 0,
67 .paddr = PPC440SP_UART0_ADDR,
68 .irq = UART0_INT,
69 .pm = IBM_CPM_UART0,
70 },
71 { .vendor = OCP_VENDOR_IBM,
72 .function = OCP_FUNC_16550,
73 .index = 1,
74 .paddr = PPC440SP_UART1_ADDR,
75 .irq = UART1_INT,
76 .pm = IBM_CPM_UART1,
77 },
78 { .vendor = OCP_VENDOR_IBM,
79 .function = OCP_FUNC_16550,
80 .index = 2,
81 .paddr = PPC440SP_UART2_ADDR,
82 .irq = UART2_INT,
83 .pm = IBM_CPM_UART2,
84 },
85 { .vendor = OCP_VENDOR_IBM,
86 .function = OCP_FUNC_IIC,
87 .index = 0,
88 .paddr = 0x00000001f0000400ULL,
89 .irq = 2,
90 .pm = IBM_CPM_IIC0,
91 .additions = &ibm440sp_iic0_def,
92 .show = &ocp_show_iic_data
93 },
94 { .vendor = OCP_VENDOR_IBM,
95 .function = OCP_FUNC_IIC,
96 .index = 1,
97 .paddr = 0x00000001f0000500ULL,
98 .irq = 3,
99 .pm = IBM_CPM_IIC1,
100 .additions = &ibm440sp_iic1_def,
101 .show = &ocp_show_iic_data
102 },
103 { .vendor = OCP_VENDOR_IBM,
104 .function = OCP_FUNC_GPIO,
105 .index = 0,
106 .paddr = 0x00000001f0000700ULL,
107 .irq = OCP_IRQ_NA,
108 .pm = IBM_CPM_GPIO0,
109 },
110 { .vendor = OCP_VENDOR_IBM,
111 .function = OCP_FUNC_MAL,
112 .paddr = OCP_PADDR_NA,
113 .irq = OCP_IRQ_NA,
114 .pm = OCP_CPM_NA,
115 .additions = &ibm440sp_mal0_def,
116 .show = &ocp_show_mal_data,
117 },
118 { .vendor = OCP_VENDOR_IBM,
119 .function = OCP_FUNC_EMAC,
120 .index = 0,
121 .paddr = 0x00000001f0000800ULL,
122 .irq = 60,
123 .pm = OCP_CPM_NA,
124 .additions = &ibm440sp_emac0_def,
125 .show = &ocp_show_emac_data,
126 },
127 { .vendor = OCP_VENDOR_INVALID
128 }
129};
diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h
deleted file mode 100644
index 2978682f1720..000000000000
--- a/arch/ppc/platforms/4xx/ibm440sp.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * PPC440SP definitions
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2004-2005 MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __PPC_PLATFORMS_IBM440SP_H
16#define __PPC_PLATFORMS_IBM440SP_H
17
18
19#include <asm/ibm44x.h>
20
21/* UART */
22#define PPC440SP_UART0_ADDR 0x00000001f0000200ULL
23#define PPC440SP_UART1_ADDR 0x00000001f0000300ULL
24#define PPC440SP_UART2_ADDR 0x00000001f0000600ULL
25#define UART0_INT 0
26#define UART1_INT 1
27#define UART2_INT 2
28
29/* Clock and Power Management */
30#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
31#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
32#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
33#define IBM_CPM_CPU 0x02000000 /* processor core */
34#define IBM_CPM_DMA 0x01000000 /* DMA controller */
35#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
36#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
37#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
38#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
39#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
40#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
41#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
42#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
43#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
44#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
45#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
46#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
47#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
48#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
49#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
50#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
51#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
52
53#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
54 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
55 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
56 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
57 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
58 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
59 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
60#endif /* __PPC_PLATFORMS_IBM440SP_H */
61#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c
deleted file mode 100644
index 1afc3642e5b1..000000000000
--- a/arch/ppc/platforms/4xx/ibmnp405h.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <asm/ocp.h>
12#include <platforms/4xx/ibmnp405h.h>
13
14static struct ocp_func_emac_data ibmnp405h_emac0_def = {
15 .rgmii_idx = -1, /* No RGMII */
16 .rgmii_mux = -1, /* No RGMII */
17 .zmii_idx = 0, /* ZMII device index */
18 .zmii_mux = 0, /* ZMII input of this EMAC */
19 .mal_idx = 0, /* MAL device index */
20 .mal_rx_chan = 0, /* MAL rx channel number */
21 .mal_tx_chan = 0, /* MAL tx channel number */
22 .wol_irq = 41, /* WOL interrupt number */
23 .mdio_idx = -1, /* No shared MDIO */
24 .tah_idx = -1, /* No TAH */
25};
26
27static struct ocp_func_emac_data ibmnp405h_emac1_def = {
28 .rgmii_idx = -1, /* No RGMII */
29 .rgmii_mux = -1, /* No RGMII */
30 .zmii_idx = 0, /* ZMII device index */
31 .zmii_mux = 1, /* ZMII input of this EMAC */
32 .mal_idx = 0, /* MAL device index */
33 .mal_rx_chan = 1, /* MAL rx channel number */
34 .mal_tx_chan = 2, /* MAL tx channel number */
35 .wol_irq = 41, /* WOL interrupt number */
36 .mdio_idx = -1, /* No shared MDIO */
37 .tah_idx = -1, /* No TAH */
38};
39static struct ocp_func_emac_data ibmnp405h_emac2_def = {
40 .rgmii_idx = -1, /* No RGMII */
41 .rgmii_mux = -1, /* No RGMII */
42 .zmii_idx = 0, /* ZMII device index */
43 .zmii_mux = 2, /* ZMII input of this EMAC */
44 .mal_idx = 0, /* MAL device index */
45 .mal_rx_chan = 2, /* MAL rx channel number */
46 .mal_tx_chan = 4, /* MAL tx channel number */
47 .wol_irq = 41, /* WOL interrupt number */
48 .mdio_idx = -1, /* No shared MDIO */
49 .tah_idx = -1, /* No TAH */
50};
51static struct ocp_func_emac_data ibmnp405h_emac3_def = {
52 .rgmii_idx = -1, /* No RGMII */
53 .rgmii_mux = -1, /* No RGMII */
54 .zmii_idx = 0, /* ZMII device index */
55 .zmii_mux = 3, /* ZMII input of this EMAC */
56 .mal_idx = 0, /* MAL device index */
57 .mal_rx_chan = 3, /* MAL rx channel number */
58 .mal_tx_chan = 6, /* MAL tx channel number */
59 .wol_irq = 41, /* WOL interrupt number */
60 .mdio_idx = -1, /* No shared MDIO */
61 .tah_idx = -1, /* No TAH */
62};
63OCP_SYSFS_EMAC_DATA()
64
65static struct ocp_func_mal_data ibmnp405h_mal0_def = {
66 .num_tx_chans = 8, /* Number of TX channels */
67 .num_rx_chans = 4, /* Number of RX channels */
68 .txeob_irq = 17, /* TX End Of Buffer IRQ */
69 .rxeob_irq = 18, /* RX End Of Buffer IRQ */
70 .txde_irq = 46, /* TX Descriptor Error IRQ */
71 .rxde_irq = 47, /* RX Descriptor Error IRQ */
72 .serr_irq = 45, /* MAL System Error IRQ */
73 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
74};
75OCP_SYSFS_MAL_DATA()
76
77static struct ocp_func_iic_data ibmnp405h_iic0_def = {
78 .fast_mode = 0, /* Use standad mode (100Khz) */
79};
80OCP_SYSFS_IIC_DATA()
81
82struct ocp_def core_ocp[] = {
83 { .vendor = OCP_VENDOR_IBM,
84 .function = OCP_FUNC_OPB,
85 .index = 0,
86 .paddr = 0xEF600000,
87 .irq = OCP_IRQ_NA,
88 .pm = OCP_CPM_NA,
89 },
90 { .vendor = OCP_VENDOR_IBM,
91 .function = OCP_FUNC_16550,
92 .index = 0,
93 .paddr = UART0_IO_BASE,
94 .irq = UART0_INT,
95 .pm = IBM_CPM_UART0
96 },
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_16550,
99 .index = 1,
100 .paddr = UART1_IO_BASE,
101 .irq = UART1_INT,
102 .pm = IBM_CPM_UART1
103 },
104 { .vendor = OCP_VENDOR_IBM,
105 .function = OCP_FUNC_IIC,
106 .paddr = 0xEF600500,
107 .irq = 2,
108 .pm = IBM_CPM_IIC0,
109 .additions = &ibmnp405h_iic0_def,
110 .show = &ocp_show_iic_data
111 },
112 { .vendor = OCP_VENDOR_IBM,
113 .function = OCP_FUNC_GPIO,
114 .paddr = 0xEF600700,
115 .irq = OCP_IRQ_NA,
116 .pm = IBM_CPM_GPIO0
117 },
118 { .vendor = OCP_VENDOR_IBM,
119 .function = OCP_FUNC_MAL,
120 .paddr = OCP_PADDR_NA,
121 .irq = OCP_IRQ_NA,
122 .pm = OCP_CPM_NA,
123 .additions = &ibmnp405h_mal0_def,
124 .show = &ocp_show_mal_data,
125 },
126 { .vendor = OCP_VENDOR_IBM,
127 .function = OCP_FUNC_EMAC,
128 .index = 0,
129 .paddr = EMAC0_BASE,
130 .irq = 37,
131 .pm = IBM_CPM_EMAC0,
132 .additions = &ibmnp405h_emac0_def,
133 .show = &ocp_show_emac_data,
134 },
135 { .vendor = OCP_VENDOR_IBM,
136 .function = OCP_FUNC_EMAC,
137 .index = 1,
138 .paddr = 0xEF600900,
139 .irq = 38,
140 .pm = IBM_CPM_EMAC1,
141 .additions = &ibmnp405h_emac1_def,
142 .show = &ocp_show_emac_data,
143 },
144 { .vendor = OCP_VENDOR_IBM,
145 .function = OCP_FUNC_EMAC,
146 .index = 2,
147 .paddr = 0xEF600a00,
148 .irq = 39,
149 .pm = IBM_CPM_EMAC2,
150 .additions = &ibmnp405h_emac2_def,
151 .show = &ocp_show_emac_data,
152 },
153 { .vendor = OCP_VENDOR_IBM,
154 .function = OCP_FUNC_EMAC,
155 .index = 3,
156 .paddr = 0xEF600b00,
157 .irq = 40,
158 .pm = IBM_CPM_EMAC3,
159 .additions = &ibmnp405h_emac3_def,
160 .show = &ocp_show_emac_data,
161 },
162 { .vendor = OCP_VENDOR_IBM,
163 .function = OCP_FUNC_ZMII,
164 .paddr = 0xEF600C10,
165 .irq = OCP_IRQ_NA,
166 .pm = OCP_CPM_NA,
167 },
168 { .vendor = OCP_VENDOR_INVALID
169 }
170};
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h
deleted file mode 100644
index 08a6a7791903..000000000000
--- a/arch/ppc/platforms/4xx/ibmnp405h.h
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBMNP405H_H__
12#define __ASM_IBMNP405H_H__
13
14
15/* ibm405.h at bottom of this file */
16
17#define PPC405_PCI_CONFIG_ADDR 0xeec00000
18#define PPC405_PCI_CONFIG_DATA 0xeec00004
19#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
20 /* setbat */
21#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
22#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
23#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
24
25#define PPC405_PCI_LOWER_MEM 0x00000000 /* hose_a->mem_space.start */
26#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
27#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
28#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
29
30#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
31
32#define PPC4xx_PCI_IO_ADDR ((uint)PPC405_PCI_PHY_IO_BASE)
33#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
34#define PPC4xx_PCI_CFG_ADDR ((uint)PPC405_PCI_CONFIG_ADDR)
35#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
36#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000)
37#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
38#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000)
39#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
40
41/* serial port defines */
42#define RS_TABLE_SIZE 4
43
44#define UART0_INT 0
45#define UART1_INT 1
46#define PCIL0_BASE 0xEF400000
47#define UART0_IO_BASE 0xEF600300
48#define UART1_IO_BASE 0xEF600400
49#define OPB0_BASE 0xEF600600
50#define EMAC0_BASE 0xEF600800
51
52#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
53
54#define STD_UART_OP(num) \
55 { 0, BASE_BAUD, 0, UART##num##_INT, \
56 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
57 iomem_base:(u8 *) UART##num##_IO_BASE, \
58 io_type: SERIAL_IO_MEM},
59
60#if defined(CONFIG_UART0_TTYS0)
61#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
62#define SERIAL_PORT_DFNS \
63 STD_UART_OP(0) \
64 STD_UART_OP(1)
65#endif
66
67#if defined(CONFIG_UART0_TTYS1)
68#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
69#define SERIAL_PORT_DFNS \
70 STD_UART_OP(1) \
71 STD_UART_OP(0)
72#endif
73
74/* DCR defines */
75/* ------------------------------------------------------------------------- */
76
77#define DCRN_CHCR_BASE 0x0F1
78#define DCRN_CHPSR_BASE 0x0B4
79#define DCRN_CPMSR_BASE 0x0BA
80#define DCRN_CPMFR_BASE 0x0B9
81#define DCRN_CPMER_BASE 0x0B8
82
83/* CPM Clocking & Power Management defines */
84#define IBM_CPM_PCI 0x40000000 /* PCI */
85#define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */
86#define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */
87#define IBM_CPM_EMAC0 0x00800000 /* EMAC 0 MII */
88#define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */
89#define IBM_CPM_EMMII 0 /* Shift value for MII */
90#define IBM_CPM_EMRX 1 /* Shift value for recv */
91#define IBM_CPM_EMTX 2 /* Shift value for MAC */
92#define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */
93#define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */
94#define IBM_CPM_CPU 0x00008000 /* processor core */
95#define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */
96#define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */
97#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */
98#define IBM_CPM_HDLC 0x00000800 /* HDCL */
99#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
100#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
101#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
102#define IBM_CPM_DMA 0x00000040 /* DMA controller */
103#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
104#define IBM_CPM_UART0 0x00000002 /* serial port 0 */
105#define IBM_CPM_UART1 0x00000001 /* serial port 1 */
106/* this is the default setting for devices put to sleep when booting */
107
108#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
109 | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
110 | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \
111 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \
112 | IBM_CPM_EMAC3 | IBM_CPM_PCI)
113
114#define DCRN_DMA0_BASE 0x100
115#define DCRN_DMA1_BASE 0x108
116#define DCRN_DMA2_BASE 0x110
117#define DCRN_DMA3_BASE 0x118
118#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
119#define DCRN_DMASR_BASE 0x120
120#define DCRN_EBC_BASE 0x012
121#define DCRN_DCP0_BASE 0x014
122#define DCRN_MAL_BASE 0x180
123#define DCRN_OCM0_BASE 0x018
124#define DCRN_PLB0_BASE 0x084
125#define DCRN_PLLMR_BASE 0x0B0
126#define DCRN_POB0_BASE 0x0A0
127#define DCRN_SDRAM0_BASE 0x010
128#define DCRN_UIC0_BASE 0x0C0
129#define DCRN_UIC1_BASE 0x0D0
130#define DCRN_CPC0_EPRCSR 0x0F3
131
132#define UIC0_UIC1NC 0x00000002
133
134#define CHR1_CETE 0x00000004 /* CPU external timer enable */
135#define UIC0 DCRN_UIC0_BASE
136#define UIC1 DCRN_UIC1_BASE
137
138#undef NR_UICS
139#define NR_UICS 2
140
141/* EMAC DCRN's FIXME: armin */
142#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
143#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
144#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
145#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
146#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
147#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
148#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
149#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
150
151#include <asm/ibm405.h>
152
153#endif /* __ASM_IBMNP405H_H__ */
154#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c
deleted file mode 100644
index 799a2eccccc3..000000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <asm/ocp.h>
13#include <asm/ppc4xx_pic.h>
14#include <platforms/4xx/ibmstb4.h>
15
16static struct ocp_func_iic_data ibmstb4_iic0_def = {
17 .fast_mode = 0, /* Use standad mode (100Khz) */
18};
19
20static struct ocp_func_iic_data ibmstb4_iic1_def = {
21 .fast_mode = 0, /* Use standad mode (100Khz) */
22};
23OCP_SYSFS_IIC_DATA()
24
25struct ocp_def core_ocp[] __initdata = {
26 { .vendor = OCP_VENDOR_IBM,
27 .function = OCP_FUNC_16550,
28 .index = 0,
29 .paddr = UART0_IO_BASE,
30 .irq = UART0_INT,
31 .pm = IBM_CPM_UART0,
32 },
33 { .vendor = OCP_VENDOR_IBM,
34 .function = OCP_FUNC_16550,
35 .index = 1,
36 .paddr = UART1_IO_BASE,
37 .irq = UART1_INT,
38 .pm = IBM_CPM_UART1,
39 },
40 { .vendor = OCP_VENDOR_IBM,
41 .function = OCP_FUNC_16550,
42 .index = 2,
43 .paddr = UART2_IO_BASE,
44 .irq = UART2_INT,
45 .pm = IBM_CPM_UART2,
46 },
47 { .vendor = OCP_VENDOR_IBM,
48 .function = OCP_FUNC_IIC,
49 .paddr = IIC0_BASE,
50 .irq = IIC0_IRQ,
51 .pm = IBM_CPM_IIC0,
52 .additions = &ibmstb4_iic0_def,
53 .show = &ocp_show_iic_data
54 },
55 { .vendor = OCP_VENDOR_IBM,
56 .function = OCP_FUNC_IIC,
57 .paddr = IIC1_BASE,
58 .irq = IIC1_IRQ,
59 .pm = IBM_CPM_IIC1,
60 .additions = &ibmstb4_iic1_def,
61 .show = &ocp_show_iic_data
62 },
63 { .vendor = OCP_VENDOR_IBM,
64 .function = OCP_FUNC_GPIO,
65 .paddr = GPIO0_BASE,
66 .irq = OCP_IRQ_NA,
67 .pm = IBM_CPM_GPIO0,
68 },
69 { .vendor = OCP_VENDOR_IBM,
70 .function = OCP_FUNC_IDE,
71 .paddr = IDE0_BASE,
72 .irq = IDE0_IRQ,
73 .pm = OCP_CPM_NA,
74 },
75 { .vendor = OCP_VENDOR_INVALID,
76 }
77};
78
79/* Polarity and triggering settings for internal interrupt sources */
80struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
81 { .polarity = 0x7fffff01,
82 .triggering = 0x00000000,
83 .ext_irq_mask = 0x0000007e, /* IRQ0 - IRQ5 */
84 }
85};
86
87static struct resource ohci_usb_resources[] = {
88 [0] = {
89 .start = USB0_BASE,
90 .end = USB0_BASE + USB0_SIZE - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = USB0_IRQ,
95 .end = USB0_IRQ,
96 .flags = IORESOURCE_IRQ,
97 },
98};
99
100static u64 dma_mask = 0xffffffffULL;
101
102static struct platform_device ohci_usb_device = {
103 .name = "ppc-soc-ohci",
104 .id = 0,
105 .num_resources = ARRAY_SIZE(ohci_usb_resources),
106 .resource = ohci_usb_resources,
107 .dev = {
108 .dma_mask = &dma_mask,
109 .coherent_dma_mask = 0xffffffffULL,
110 }
111};
112
113static struct platform_device *ibmstb4_devs[] __initdata = {
114 &ohci_usb_device,
115};
116
117static int __init
118ibmstb4_platform_add_devices(void)
119{
120 return platform_add_devices(ibmstb4_devs, ARRAY_SIZE(ibmstb4_devs));
121}
122arch_initcall(ibmstb4_platform_add_devices);
diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h
deleted file mode 100644
index 31a08abaa4a2..000000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.h
+++ /dev/null
@@ -1,235 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBMSTB4_H__
12#define __ASM_IBMSTB4_H__
13
14
15/* serial port defines */
16#define STB04xxx_IO_BASE ((uint)0xe0000000)
17#define PPC4xx_PCI_IO_ADDR STB04xxx_IO_BASE
18#define PPC4xx_ONB_IO_PADDR STB04xxx_IO_BASE
19#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
20#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
21
22/*
23 * map STB04xxx internal i/o address (0x400x00xx) to an address
24 * which is below the 2GB limit...
25 *
26 * 4000 000x uart1 -> 0xe000 000x
27 * 4001 00xx ppu
28 * 4002 00xx smart card
29 * 4003 000x iic
30 * 4004 000x uart0
31 * 4005 0xxx timer
32 * 4006 00xx gpio
33 * 4007 00xx smart card
34 * 400b 000x iic
35 * 400c 000x scp
36 * 400d 000x modem
37 * 400e 000x uart2
38*/
39#define STB04xxx_MAP_IO_ADDR(a) (((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000))
40
41#define RS_TABLE_SIZE 3
42#define UART0_INT 20
43
44#ifdef __BOOTER__
45#define UART0_IO_BASE 0x40040000
46#else
47#define UART0_IO_BASE 0xe0040000
48#endif
49
50#define UART1_INT 21
51
52#ifdef __BOOTER__
53#define UART1_IO_BASE 0x40000000
54#else
55#define UART1_IO_BASE 0xe0000000
56#endif
57
58#define UART2_INT 31
59#ifdef __BOOTER__
60#define UART2_IO_BASE 0x400e0000
61#else
62#define UART2_IO_BASE 0xe00e0000
63#endif
64
65#define IDE0_BASE 0x400F0000
66#define IDE0_SIZE 0x200
67#define IDE0_IRQ 25
68#define IIC0_BASE 0x40030000
69#define IIC1_BASE 0x400b0000
70#define OPB0_BASE 0x40000000
71#define GPIO0_BASE 0x40060000
72
73#define USB0_BASE 0x40010000
74#define USB0_SIZE 0xA0
75#define USB0_IRQ 18
76
77#define IIC_NUMS 2
78#define UART_NUMS 3
79#define IIC0_IRQ 9
80#define IIC1_IRQ 10
81#define IIC_OWN 0x55
82#define IIC_CLOCK 50
83
84#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
85
86#define STD_UART_OP(num) \
87 { 0, BASE_BAUD, 0, UART##num##_INT, \
88 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
89 iomem_base: (u8 *)UART##num##_IO_BASE, \
90 io_type: SERIAL_IO_MEM},
91
92#if defined(CONFIG_UART0_TTYS0)
93#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
94#define SERIAL_PORT_DFNS \
95 STD_UART_OP(0) \
96 STD_UART_OP(1) \
97 STD_UART_OP(2)
98#endif
99
100#if defined(CONFIG_UART0_TTYS1)
101#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
102#define SERIAL_PORT_DFNS \
103 STD_UART_OP(1) \
104 STD_UART_OP(0) \
105 STD_UART_OP(2)
106#endif
107
108#if defined(CONFIG_UART0_TTYS2)
109#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
110#define SERIAL_PORT_DFNS \
111 STD_UART_OP(2) \
112 STD_UART_OP(0) \
113 STD_UART_OP(1)
114#endif
115
116#define DCRN_BE_BASE 0x090
117#define DCRN_DMA0_BASE 0x0C0
118#define DCRN_DMA1_BASE 0x0C8
119#define DCRN_DMA2_BASE 0x0D0
120#define DCRN_DMA3_BASE 0x0D8
121#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
122#define DCRN_DMASR_BASE 0x0E0
123#define DCRN_PLB0_BASE 0x054
124#define DCRN_PLB1_BASE 0x064
125#define DCRN_POB0_BASE 0x0B0
126#define DCRN_SCCR_BASE 0x120
127#define DCRN_UIC0_BASE 0x040
128#define DCRN_BE_BASE 0x090
129#define DCRN_DMA0_BASE 0x0C0
130#define DCRN_DMA1_BASE 0x0C8
131#define DCRN_DMA2_BASE 0x0D0
132#define DCRN_DMA3_BASE 0x0D8
133#define DCRN_CIC_BASE 0x030
134#define DCRN_DMASR_BASE 0x0E0
135#define DCRN_EBIMC_BASE 0x070
136#define DCRN_DCRX_BASE 0x020
137#define DCRN_CPMFR_BASE 0x102
138#define DCRN_SCCR_BASE 0x120
139#define UIC0 DCRN_UIC0_BASE
140
141#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
142#define IBM_CPM_USB0 0x40000000 /* IEEE-1284 */
143#define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */
144#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
145#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
146#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
147#define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */
148#define IBM_CPM_DMA 0x01000000 /* DMA controller */
149#define IBM_CPM_DMA1 0x00800000 /* reserved */
150#define IBM_CPM_XPT1 0x00400000 /* reserved */
151#define IBM_CPM_XPT2 0x00200000 /* reserved */
152#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
153#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
154#define IBM_CPM_EPI 0x00040000 /* DCR Extension */
155#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
156#define IBM_CPM_VID 0x00010000 /* reserved */
157#define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */
158#define IBM_CPM_USBSDRA 0x00004000 /* SDRAM 0 memory controller */
159#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
160#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
161#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
162#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
163#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
164#define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */
165#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
166#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
167#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
168#define IBM_CPM_UART2 0x00000008 /* Serial Control Port */
169#define IBM_CPM_DDIO 0x00000004 /* Descrambler */
170#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
171
172#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
173 | IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
174 | IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
175 | IBM_CPM_XPT27 | IBM_CPM_UIC )
176
177#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
178#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
179/* DCRN_BESR */
180#define BESR_DSES 0x80000000 /* Data-Side Error Status */
181#define BESR_DMES 0x40000000 /* DMA Error Status */
182#define BESR_RWS 0x20000000 /* Read/Write Status */
183#define BESR_ETMASK 0x1C000000 /* Error Type */
184#define ET_PROT 0
185#define ET_PARITY 1
186#define ET_NCFG 2
187#define ET_BUSERR 4
188#define ET_BUSTO 6
189
190#define CHR1_CETE 0x00800000 /* CPU external timer enable */
191#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
192
193#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
194#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
195#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
196#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
197#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
198#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
199#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
200#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
201#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
202
203#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
204#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
205#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
206#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
207#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
208#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
209#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
210#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
211
212#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
213#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
214#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
215#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
216#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
217#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
218#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
219#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
220#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
221#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
222#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
223#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
224#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
225#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
226#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
227#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
228#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
229#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
230#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
231
232#include <asm/ibm405.h>
233
234#endif /* __ASM_IBMSTB4_H__ */
235#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c
deleted file mode 100644
index 090ddcbecc5e..000000000000
--- a/arch/ppc/platforms/4xx/ibmstbx25.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <asm/ocp.h>
12#include <platforms/4xx/ibmstbx25.h>
13#include <asm/ppc4xx_pic.h>
14
15static struct ocp_func_iic_data ibmstbx25_iic0_def = {
16 .fast_mode = 0, /* Use standad mode (100Khz) */
17};
18OCP_SYSFS_IIC_DATA()
19
20struct ocp_def core_ocp[] __initdata = {
21 { .vendor = OCP_VENDOR_IBM,
22 .function = OCP_FUNC_16550,
23 .index = 0,
24 .paddr = UART0_IO_BASE,
25 .irq = UART0_INT,
26 .pm = IBM_CPM_UART0,
27 },
28 { .vendor = OCP_VENDOR_IBM,
29 .function = OCP_FUNC_16550,
30 .index = 1,
31 .paddr = UART1_IO_BASE,
32 .irq = UART1_INT,
33 .pm = IBM_CPM_UART1,
34 },
35 { .vendor = OCP_VENDOR_IBM,
36 .function = OCP_FUNC_16550,
37 .index = 2,
38 .paddr = UART2_IO_BASE,
39 .irq = UART2_INT,
40 .pm = IBM_CPM_UART2,
41 },
42 { .vendor = OCP_VENDOR_IBM,
43 .function = OCP_FUNC_IIC,
44 .paddr = IIC0_BASE,
45 .irq = IIC0_IRQ,
46 .pm = IBM_CPM_IIC0,
47 .additions = &ibmstbx25_iic0_def,
48 .show = &ocp_show_iic_data
49 },
50 { .vendor = OCP_VENDOR_IBM,
51 .function = OCP_FUNC_GPIO,
52 .paddr = GPIO0_BASE,
53 .irq = OCP_IRQ_NA,
54 .pm = IBM_CPM_GPIO0,
55 },
56 { .vendor = OCP_VENDOR_INVALID
57 }
58};
59
60/* Polarity and triggering settings for internal interrupt sources */
61struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
62 { .polarity = 0xffff8f80,
63 .triggering = 0x00000000,
64 .ext_irq_mask = 0x0000707f, /* IRQ7 - IRQ9, IRQ0 - IRQ6 */
65 }
66};
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h
deleted file mode 100644
index 31b63343e641..000000000000
--- a/arch/ppc/platforms/4xx/ibmstbx25.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#ifdef __KERNEL__
11#ifndef __ASM_IBMSTBX25_H__
12#define __ASM_IBMSTBX25_H__
13
14
15/* serial port defines */
16#define STBx25xx_IO_BASE ((uint)0xe0000000)
17#define PPC4xx_ONB_IO_PADDR STBx25xx_IO_BASE
18#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
19#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
20
21/*
22 * map STBxxxx internal i/o address (0x400x00xx) to an address
23 * which is below the 2GB limit...
24 *
25 * 4000 000x uart1 -> 0xe000 000x
26 * 4001 00xx uart2
27 * 4002 00xx smart card
28 * 4003 000x iic
29 * 4004 000x uart0
30 * 4005 0xxx timer
31 * 4006 00xx gpio
32 * 4007 00xx smart card
33 * 400b 000x iic
34 * 400c 000x scp
35 * 400d 000x modem
36 * 400e 000x uart2
37*/
38#define STBx25xx_MAP_IO_ADDR(a) (((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000))
39
40#define RS_TABLE_SIZE 3
41
42#define OPB_BASE_START 0x40000000
43#define EBIU_BASE_START 0xF0100000
44#define DCR_BASE_START 0x0000
45
46#ifdef __BOOTER__
47#define UART1_IO_BASE 0x40000000
48#define UART2_IO_BASE 0x40010000
49#else
50#define UART1_IO_BASE 0xe0000000
51#define UART2_IO_BASE 0xe0010000
52#endif
53#define SC0_BASE 0x40020000 /* smart card #0 */
54#define IIC0_BASE 0x40030000
55#ifdef __BOOTER__
56#define UART0_IO_BASE 0x40040000
57#else
58#define UART0_IO_BASE 0xe0040000
59#endif
60#define SCC0_BASE 0x40040000 /* Serial 0 controller IrdA */
61#define GPT0_BASE 0x40050000 /* General purpose timers */
62#define GPIO0_BASE 0x40060000
63#define SC1_BASE 0x40070000 /* smart card #1 */
64#define SCP0_BASE 0x400C0000 /* Serial Controller Port */
65#define SSP0_BASE 0x400D0000 /* Sync serial port */
66
67#define IDE0_BASE 0xf0100000
68#define REDWOOD_IDE_CTRL 0xf1100000
69
70#define RTCFPC_IRQ 0
71#define XPORT_IRQ 1
72#define AUD_IRQ 2
73#define AID_IRQ 3
74#define DMA0 4
75#define DMA1_IRQ 5
76#define DMA2_IRQ 6
77#define DMA3_IRQ 7
78#define SC0_IRQ 8
79#define IIC0_IRQ 9
80#define IIR0_IRQ 10
81#define GPT0_IRQ 11
82#define GPT1_IRQ 12
83#define SCP0_IRQ 13
84#define SSP0_IRQ 14
85#define GPT2_IRQ 15 /* count down timer */
86#define SC1_IRQ 16
87/* IRQ 17 - 19 external */
88#define UART0_INT 20
89#define UART1_INT 21
90#define UART2_INT 22
91#define XPTDMA_IRQ 23
92#define DCRIDE_IRQ 24
93/* IRQ 25 - 30 external */
94#define IDE0_IRQ 26
95
96#define IIC_NUMS 1
97#define UART_NUMS 3
98#define IIC_OWN 0x55
99#define IIC_CLOCK 50
100
101#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
102
103#define STD_UART_OP(num) \
104 { 0, BASE_BAUD, 0, UART##num##_INT, \
105 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
106 iomem_base: (u8 *)UART##num##_IO_BASE, \
107 io_type: SERIAL_IO_MEM},
108
109#if defined(CONFIG_UART0_TTYS0)
110#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
111#define SERIAL_PORT_DFNS \
112 STD_UART_OP(0) \
113 STD_UART_OP(1) \
114 STD_UART_OP(2)
115#endif
116
117#if defined(CONFIG_UART0_TTYS1)
118#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
119#define SERIAL_PORT_DFNS \
120 STD_UART_OP(1) \
121 STD_UART_OP(0) \
122 STD_UART_OP(2)
123#endif
124
125#if defined(CONFIG_UART0_TTYS2)
126#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
127#define SERIAL_PORT_DFNS \
128 STD_UART_OP(2) \
129 STD_UART_OP(0) \
130 STD_UART_OP(1)
131#endif
132
133#define DCRN_BE_BASE 0x090
134#define DCRN_DMA0_BASE 0x0C0
135#define DCRN_DMA1_BASE 0x0C8
136#define DCRN_DMA2_BASE 0x0D0
137#define DCRN_DMA3_BASE 0x0D8
138#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
139#define DCRN_DMASR_BASE 0x0E0
140#define DCRN_PLB0_BASE 0x054
141#define DCRN_PLB1_BASE 0x064
142#define DCRN_POB0_BASE 0x0B0
143#define DCRN_SCCR_BASE 0x120
144#define DCRN_UIC0_BASE 0x040
145#define DCRN_BE_BASE 0x090
146#define DCRN_DMA0_BASE 0x0C0
147#define DCRN_DMA1_BASE 0x0C8
148#define DCRN_DMA2_BASE 0x0D0
149#define DCRN_DMA3_BASE 0x0D8
150#define DCRN_CIC_BASE 0x030
151#define DCRN_DMASR_BASE 0x0E0
152#define DCRN_EBIMC_BASE 0x070
153#define DCRN_DCRX_BASE 0x020
154#define DCRN_CPMFR_BASE 0x102
155#define DCRN_SCCR_BASE 0x120
156#define DCRN_RTCFP_BASE 0x310
157
158#define UIC0 DCRN_UIC0_BASE
159
160#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
161#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
162#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
163#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
164#define IBM_CPM_IRR 0x02000000 /* Infrared receiver */
165#define IBM_CPM_DMA 0x01000000 /* DMA controller */
166#define IBM_CPM_UART2 0x00200000 /* Serial Control Port */
167#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
168#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
169#define IBM_PM_DCRIDE 0x00040000 /* DCR timeout & IDE line Mode clock */
170#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
171#define IBM_CPM_VID 0x00010000 /* reserved */
172#define IBM_CPM_SC1 0x00008000 /* Smart Card 0 */
173#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
174#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
175#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
176#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
177#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
178#define IBM_CPM_C405T 0x00000100 /* CPU timers */
179#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
180#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
181#define IBM_CPM_RTCFPC 0x00000020 /* Realtime clock and front panel */
182#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
183#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
184#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA \
185 | IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T \
186 | IBM_CPM_XPT27 | IBM_CPM_UIC)
187
188#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
189#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
190/* DCRN_BESR */
191#define BESR_DSES 0x80000000 /* Data-Side Error Status */
192#define BESR_DMES 0x40000000 /* DMA Error Status */
193#define BESR_RWS 0x20000000 /* Read/Write Status */
194#define BESR_ETMASK 0x1C000000 /* Error Type */
195#define ET_PROT 0
196#define ET_PARITY 1
197#define ET_NCFG 2
198#define ET_BUSERR 4
199#define ET_BUSTO 6
200
201#define CHR1_CETE 0x00800000 /* CPU external timer enable */
202#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
203
204#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
205#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
206#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
207#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
208#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
209#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
210#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
211#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
212#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
213
214#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
215#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
216#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
217#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
218#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
219#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
220#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
221#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
222
223#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
224#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
225#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
226#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
227#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
228#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
229#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
230#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
231#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
232#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
233#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
234#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
235#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
236#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
237#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
238#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
239#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
240#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
241#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
242
243#define DCRN_RTC_FPC0_CNTL (DCRN_RTCFP_BASE + 0x00) /* RTC cntl */
244#define DCRN_RTC_FPC0_INT (DCRN_RTCFP_BASE + 0x01) /* RTC Interrupt */
245#define DCRN_RTC_FPC0_TIME (DCRN_RTCFP_BASE + 0x02) /* RTC time reg */
246#define DCRN_RTC_FPC0_ALRM (DCRN_RTCFP_BASE + 0x03) /* RTC Alarm reg */
247#define DCRN_RTC_FPC0_D1 (DCRN_RTCFP_BASE + 0x04) /* LED Data 1 */
248#define DCRN_RTC_FPC0_D2 (DCRN_RTCFP_BASE + 0x05) /* LED Data 2 */
249#define DCRN_RTC_FPC0_D3 (DCRN_RTCFP_BASE + 0x06) /* LED Data 3 */
250#define DCRN_RTC_FPC0_D4 (DCRN_RTCFP_BASE + 0x07) /* LED Data 4 */
251#define DCRN_RTC_FPC0_D5 (DCRN_RTCFP_BASE + 0x08) /* LED Data 5 */
252#define DCRN_RTC_FPC0_FCNTL (DCRN_RTCFP_BASE + 0x09) /* LED control */
253#define DCRN_RTC_FPC0_BRT (DCRN_RTCFP_BASE + 0x0A) /* Brightness cntl */
254
255#include <asm/ibm405.h>
256
257#endif /* __ASM_IBMSTBX25_H__ */
258#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
deleted file mode 100644
index f6d8c2e8b6b7..000000000000
--- a/arch/ppc/platforms/4xx/luan.c
+++ /dev/null
@@ -1,371 +0,0 @@
1/*
2 * Luan board specific routines
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2004-2005 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/types.h>
22#include <linux/major.h>
23#include <linux/blkdev.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/initrd.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29#include <linux/tty.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/dma.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/ocp.h>
41#include <asm/pci-bridge.h>
42#include <asm/time.h>
43#include <asm/todc.h>
44#include <asm/bootinfo.h>
45#include <asm/ppc4xx_pic.h>
46#include <asm/ppcboot.h>
47
48#include <syslib/ibm44x_common.h>
49#include <syslib/ibm440gx_common.h>
50#include <syslib/ibm440sp_common.h>
51
52extern bd_t __res;
53
54static struct ibm44x_clocks clocks __initdata;
55
56static void __init
57luan_calibrate_decr(void)
58{
59 unsigned int freq;
60
61 if (mfspr(SPRN_CCR1) & CCR1_TCS)
62 freq = LUAN_TMR_CLK;
63 else
64 freq = clocks.cpu;
65
66 ibm44x_calibrate_decr(freq);
67}
68
69static int
70luan_show_cpuinfo(struct seq_file *m)
71{
72 seq_printf(m, "vendor\t\t: IBM\n");
73 seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
74
75 return 0;
76}
77
78static inline int
79luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
80{
81 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
82
83 /* PCIX0 in adapter mode, no host interrupt routing */
84
85 /* PCIX1 */
86 if (hose->index == 0) {
87 static char pci_irq_table[][4] =
88 /*
89 * PCI IDSEL/INTPIN->INTLINE
90 * A B C D
91 */
92 {
93 { 49, 49, 49, 49 }, /* IDSEL 1 - PCIX1 Slot 0 */
94 { 49, 49, 49, 49 }, /* IDSEL 2 - PCIX1 Slot 1 */
95 { 49, 49, 49, 49 }, /* IDSEL 3 - PCIX1 Slot 2 */
96 { 49, 49, 49, 49 }, /* IDSEL 4 - PCIX1 Slot 3 */
97 };
98 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
99 return PCI_IRQ_TABLE_LOOKUP;
100 /* PCIX2 */
101 } else if (hose->index == 1) {
102 static char pci_irq_table[][4] =
103 /*
104 * PCI IDSEL/INTPIN->INTLINE
105 * A B C D
106 */
107 {
108 { 50, 50, 50, 50 }, /* IDSEL 1 - PCIX2 Slot 0 */
109 { 50, 50, 50, 50 }, /* IDSEL 2 - PCIX2 Slot 1 */
110 { 50, 50, 50, 50 }, /* IDSEL 3 - PCIX2 Slot 2 */
111 { 50, 50, 50, 50 }, /* IDSEL 4 - PCIX2 Slot 3 */
112 };
113 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
114 return PCI_IRQ_TABLE_LOOKUP;
115 }
116 return -1;
117}
118
119static void __init luan_set_emacdata(void)
120{
121 struct ocp_def *def;
122 struct ocp_func_emac_data *emacdata;
123
124 /* Set phy_map, phy_mode, and mac_addr for the EMAC */
125 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
126 emacdata = def->additions;
127 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
128 emacdata->phy_mode = PHY_MODE_GMII;
129 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
130}
131
132#define PCIX_READW(offset) \
133 (readw((void *)((u32)pcix_reg_base+offset)))
134
135#define PCIX_WRITEW(value, offset) \
136 (writew(value, (void *)((u32)pcix_reg_base+offset)))
137
138#define PCIX_WRITEL(value, offset) \
139 (writel(value, (void *)((u32)pcix_reg_base+offset)))
140
141static void __init
142luan_setup_pcix(void)
143{
144 int i;
145 void *pcix_reg_base;
146
147 for (i=0;i<3;i++) {
148 pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
149
150 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
151 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
152
153 /* Disable all windows */
154 PCIX_WRITEL(0, PCIX0_POM0SA);
155 PCIX_WRITEL(0, PCIX0_POM1SA);
156 PCIX_WRITEL(0, PCIX0_POM2SA);
157 PCIX_WRITEL(0, PCIX0_PIM0SA);
158 PCIX_WRITEL(0, PCIX0_PIM0SAH);
159 PCIX_WRITEL(0, PCIX0_PIM1SA);
160 PCIX_WRITEL(0, PCIX0_PIM2SA);
161 PCIX_WRITEL(0, PCIX0_PIM2SAH);
162
163 /*
164 * Setup 512MB PLB->PCI outbound mem window
165 * (a_n000_0000->0_n000_0000)
166 * */
167 PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
168 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
169 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
170 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
171 PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
172
173 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
174 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
175 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
176 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
177 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
178
179 iounmap(pcix_reg_base);
180 }
181
182 eieio();
183}
184
185static void __init
186luan_setup_hose(struct pci_controller *hose,
187 int lower_mem,
188 int upper_mem,
189 int cfga,
190 int cfgd,
191 u64 pcix_io_base)
192{
193 char name[20];
194
195 sprintf(name, "PCIX%d host bridge", hose->index);
196
197 hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
198
199 pci_init_resource(&hose->io_resource,
200 LUAN_PCIX_LOWER_IO,
201 LUAN_PCIX_UPPER_IO,
202 IORESOURCE_IO,
203 name);
204
205 pci_init_resource(&hose->mem_resources[0],
206 lower_mem,
207 upper_mem,
208 IORESOURCE_MEM,
209 name);
210
211 hose->io_space.start = LUAN_PCIX_LOWER_IO;
212 hose->io_space.end = LUAN_PCIX_UPPER_IO;
213 hose->mem_space.start = lower_mem;
214 hose->mem_space.end = upper_mem;
215 hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
216 isa_io_base = (unsigned long) hose->io_base_virt;
217
218 setup_indirect_pci(hose, cfga, cfgd);
219 hose->set_cfg_type = 1;
220}
221
222static void __init
223luan_setup_hoses(void)
224{
225 struct pci_controller *hose1, *hose2;
226
227 /* Configure windows on the PCI-X host bridge */
228 luan_setup_pcix();
229
230 /* Allocate hoses for PCIX1 and PCIX2 */
231 hose1 = pcibios_alloc_controller();
232 if (!hose1)
233 return;
234
235 hose2 = pcibios_alloc_controller();
236 if (!hose2) {
237 pcibios_free_controller(hose1);
238 return;
239 }
240
241 /* Setup PCIX1 */
242 hose1->first_busno = 0;
243 hose1->last_busno = 0xff;
244
245 luan_setup_hose(hose1,
246 LUAN_PCIX1_LOWER_MEM,
247 LUAN_PCIX1_UPPER_MEM,
248 PCIX1_CFGA,
249 PCIX1_CFGD,
250 PCIX1_IO_BASE);
251
252 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
253
254 /* Setup PCIX2 */
255 hose2->first_busno = hose1->last_busno + 1;
256 hose2->last_busno = 0xff;
257
258 luan_setup_hose(hose2,
259 LUAN_PCIX2_LOWER_MEM,
260 LUAN_PCIX2_UPPER_MEM,
261 PCIX2_CFGA,
262 PCIX2_CFGD,
263 PCIX2_IO_BASE);
264
265 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
266
267 ppc_md.pci_swizzle = common_swizzle;
268 ppc_md.pci_map_irq = luan_map_irq;
269}
270
271TODC_ALLOC();
272
273static void __init
274luan_early_serial_map(void)
275{
276 struct uart_port port;
277
278 /* Setup ioremapped serial port access */
279 memset(&port, 0, sizeof(port));
280 port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
281 port.irq = UART0_INT;
282 port.uartclk = clocks.uart0;
283 port.regshift = 0;
284 port.iotype = UPIO_MEM;
285 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
286 port.line = 0;
287
288 if (early_serial_setup(&port) != 0) {
289 printk("Early serial init of port 0 failed\n");
290 }
291
292 port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
293 port.irq = UART1_INT;
294 port.uartclk = clocks.uart1;
295 port.line = 1;
296
297 if (early_serial_setup(&port) != 0) {
298 printk("Early serial init of port 1 failed\n");
299 }
300
301 port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
302 port.irq = UART2_INT;
303 port.uartclk = BASE_BAUD;
304 port.line = 2;
305
306 if (early_serial_setup(&port) != 0) {
307 printk("Early serial init of port 2 failed\n");
308 }
309}
310
311static void __init
312luan_setup_arch(void)
313{
314 luan_set_emacdata();
315
316#if !defined(CONFIG_BDI_SWITCH)
317 /*
318 * The Abatron BDI JTAG debugger does not tolerate others
319 * mucking with the debug registers.
320 */
321 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
322#endif
323
324 /*
325 * Determine various clocks.
326 * To be completely correct we should get SysClk
327 * from FPGA, because it can be changed by on-board switches
328 * --ebs
329 */
330 /* 440GX and 440SP clocking is the same -mdp */
331 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
332 ocp_sys_info.opb_bus_freq = clocks.opb;
333
334 /* init to some ~sane value until calibrate_delay() runs */
335 loops_per_jiffy = 50000000/HZ;
336
337 /* Setup PCIXn host bridges */
338 luan_setup_hoses();
339
340#ifdef CONFIG_BLK_DEV_INITRD
341 if (initrd_start)
342 ROOT_DEV = Root_RAM0;
343 else
344#endif
345#ifdef CONFIG_ROOT_NFS
346 ROOT_DEV = Root_NFS;
347#else
348 ROOT_DEV = Root_HDA1;
349#endif
350
351 luan_early_serial_map();
352
353 /* Identify the system */
354 printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
355}
356
357void __init platform_init(unsigned long r3, unsigned long r4,
358 unsigned long r5, unsigned long r6, unsigned long r7)
359{
360 ibm44x_platform_init(r3, r4, r5, r6, r7);
361
362 ppc_md.setup_arch = luan_setup_arch;
363 ppc_md.show_cpuinfo = luan_show_cpuinfo;
364 ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
365 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
366
367 ppc_md.calibrate_decr = luan_calibrate_decr;
368#ifdef CONFIG_KGDB
369 ppc_md.early_serial_map = luan_early_serial_map;
370#endif
371}
diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h
deleted file mode 100644
index 68dd46b0a5c4..000000000000
--- a/arch/ppc/platforms/4xx/luan.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * Luan board definitions
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2004-2005 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_LUAN_H__
17#define __ASM_LUAN_H__
18
19#include <platforms/4xx/ibm440sp.h>
20
21/* F/W TLB mapping used in bootloader glue to reset EMAC */
22#define PPC44x_EMAC0_MR0 0xa0000800
23
24/* Location of MAC addresses in PIBS image */
25#define PIBS_FLASH_BASE 0xffe00000
26#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
27
28/* External timer clock frequency */
29#define LUAN_TMR_CLK 25000000
30
31/* Flash */
32#define LUAN_FPGA_REG_0 0x0000000148300000ULL
33#define LUAN_BOOT_LARGE_FLASH(x) (x & 0x40)
34#define LUAN_SMALL_FLASH_LOW 0x00000001ff900000ULL
35#define LUAN_SMALL_FLASH_HIGH 0x00000001ffe00000ULL
36#define LUAN_SMALL_FLASH_SIZE 0x100000
37#define LUAN_LARGE_FLASH_LOW 0x00000001ff800000ULL
38#define LUAN_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
39#define LUAN_LARGE_FLASH_SIZE 0x400000
40
41/*
42 * Serial port defines
43 */
44#define RS_TABLE_SIZE 3
45
46/* PIBS defined UART mappings, used before early_serial_setup */
47#define UART0_IO_BASE 0xa0000200
48#define UART1_IO_BASE 0xa0000300
49#define UART2_IO_BASE 0xa0000600
50
51#define BASE_BAUD 11059200
52#define STD_UART_OP(num) \
53 { 0, BASE_BAUD, 0, UART##num##_INT, \
54 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
55 iomem_base: (void*)UART##num##_IO_BASE, \
56 io_type: SERIAL_IO_MEM},
57
58#define SERIAL_PORT_DFNS \
59 STD_UART_OP(0) \
60 STD_UART_OP(1) \
61 STD_UART_OP(2)
62
63/* PCI support */
64#define LUAN_PCIX_LOWER_IO 0x00000000
65#define LUAN_PCIX_UPPER_IO 0x0000ffff
66#define LUAN_PCIX0_LOWER_MEM 0x80000000
67#define LUAN_PCIX0_UPPER_MEM 0x9fffffff
68#define LUAN_PCIX1_LOWER_MEM 0xa0000000
69#define LUAN_PCIX1_UPPER_MEM 0xbfffffff
70#define LUAN_PCIX2_LOWER_MEM 0xc0000000
71#define LUAN_PCIX2_UPPER_MEM 0xdfffffff
72
73#define LUAN_PCIX_MEM_SIZE 0x20000000
74#define LUAN_PCIX_MEM_OFFSET 0x00000000
75
76#endif /* __ASM_LUAN_H__ */
77#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
deleted file mode 100644
index 308386ef6f77..000000000000
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ /dev/null
@@ -1,350 +0,0 @@
1/*
2 * Ocotea board specific routines
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2003-2005 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/types.h>
22#include <linux/major.h>
23#include <linux/blkdev.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/initrd.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29#include <linux/tty.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/dma.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/ocp.h>
41#include <asm/pci-bridge.h>
42#include <asm/time.h>
43#include <asm/todc.h>
44#include <asm/bootinfo.h>
45#include <asm/ppc4xx_pic.h>
46#include <asm/ppcboot.h>
47#include <asm/tlbflush.h>
48
49#include <syslib/gen550.h>
50#include <syslib/ibm440gx_common.h>
51
52extern bd_t __res;
53
54static struct ibm44x_clocks clocks __initdata;
55
56static void __init
57ocotea_calibrate_decr(void)
58{
59 unsigned int freq;
60
61 if (mfspr(SPRN_CCR1) & CCR1_TCS)
62 freq = OCOTEA_TMR_CLK;
63 else
64 freq = clocks.cpu;
65
66 ibm44x_calibrate_decr(freq);
67}
68
69static int
70ocotea_show_cpuinfo(struct seq_file *m)
71{
72 seq_printf(m, "vendor\t\t: IBM\n");
73 seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
74 ibm440gx_show_cpuinfo(m);
75 return 0;
76}
77
78static inline int
79ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
80{
81 static char pci_irq_table[][4] =
82 /*
83 * PCI IDSEL/INTPIN->INTLINE
84 * A B C D
85 */
86 {
87 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
88 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
89 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
90 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
91 };
92
93 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
94 return PCI_IRQ_TABLE_LOOKUP;
95}
96
97static void __init ocotea_set_emacdata(void)
98{
99 struct ocp_def *def;
100 struct ocp_func_emac_data *emacdata;
101 int i;
102
103 /*
104 * Note: Current rev. board only operates in Group 4a
105 * mode, so we always set EMAC0-1 for SMII and EMAC2-3
106 * for RGMII (though these could run in RTBI just the same).
107 *
108 * The FPGA reg 3 information isn't even suitable for
109 * determining the phy_mode, so if the board becomes
110 * usable in !4a, it will be necessary to parse an environment
111 * variable from the firmware or similar to properly configure
112 * the phy_map/phy_mode.
113 */
114 /* Set phy_map, phy_mode, and mac_addr for each EMAC */
115 for (i=0; i<4; i++) {
116 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
117 emacdata = def->additions;
118 if (i < 2) {
119 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
120 emacdata->phy_mode = PHY_MODE_SMII;
121 }
122 else {
123 emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
124 emacdata->phy_mode = PHY_MODE_RGMII;
125 }
126 if (i == 0)
127 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
128 else if (i == 1)
129 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
130 else if (i == 2)
131 memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
132 else if (i == 3)
133 memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
134 }
135}
136
137#define PCIX_READW(offset) \
138 (readw(pcix_reg_base+offset))
139
140#define PCIX_WRITEW(value, offset) \
141 (writew(value, pcix_reg_base+offset))
142
143#define PCIX_WRITEL(value, offset) \
144 (writel(value, pcix_reg_base+offset))
145
146/*
147 * FIXME: This is only here to "make it work". This will move
148 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
149 * configuration library. -Matt
150 */
151static void __init
152ocotea_setup_pcix(void)
153{
154 void *pcix_reg_base;
155
156 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
157
158 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
159 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
160
161 /* Disable all windows */
162 PCIX_WRITEL(0, PCIX0_POM0SA);
163 PCIX_WRITEL(0, PCIX0_POM1SA);
164 PCIX_WRITEL(0, PCIX0_POM2SA);
165 PCIX_WRITEL(0, PCIX0_PIM0SA);
166 PCIX_WRITEL(0, PCIX0_PIM0SAH);
167 PCIX_WRITEL(0, PCIX0_PIM1SA);
168 PCIX_WRITEL(0, PCIX0_PIM2SA);
169 PCIX_WRITEL(0, PCIX0_PIM2SAH);
170
171 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
172 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
173 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
174 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
175 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
176 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
177
178 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
179 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
180 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
181 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
182
183 eieio();
184}
185
186static void __init
187ocotea_setup_hose(void)
188{
189 struct pci_controller *hose;
190
191 /* Configure windows on the PCI-X host bridge */
192 ocotea_setup_pcix();
193
194 hose = pcibios_alloc_controller();
195
196 if (!hose)
197 return;
198
199 hose->first_busno = 0;
200 hose->last_busno = 0xff;
201
202 hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
203
204 pci_init_resource(&hose->io_resource,
205 OCOTEA_PCI_LOWER_IO,
206 OCOTEA_PCI_UPPER_IO,
207 IORESOURCE_IO,
208 "PCI host bridge");
209
210 pci_init_resource(&hose->mem_resources[0],
211 OCOTEA_PCI_LOWER_MEM,
212 OCOTEA_PCI_UPPER_MEM,
213 IORESOURCE_MEM,
214 "PCI host bridge");
215
216 hose->io_space.start = OCOTEA_PCI_LOWER_IO;
217 hose->io_space.end = OCOTEA_PCI_UPPER_IO;
218 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
219 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
220 hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
221 isa_io_base = (unsigned long) hose->io_base_virt;
222
223 setup_indirect_pci(hose,
224 OCOTEA_PCI_CFGA_PLB32,
225 OCOTEA_PCI_CFGD_PLB32);
226 hose->set_cfg_type = 1;
227
228 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
229
230 ppc_md.pci_swizzle = common_swizzle;
231 ppc_md.pci_map_irq = ocotea_map_irq;
232}
233
234
235TODC_ALLOC();
236
237static void __init
238ocotea_early_serial_map(void)
239{
240 struct uart_port port;
241
242 /* Setup ioremapped serial port access */
243 memset(&port, 0, sizeof(port));
244 port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
245 port.irq = UART0_INT;
246 port.uartclk = clocks.uart0;
247 port.regshift = 0;
248 port.iotype = UPIO_MEM;
249 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
250 port.line = 0;
251
252 if (early_serial_setup(&port) != 0) {
253 printk("Early serial init of port 0 failed\n");
254 }
255
256#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
257 /* Configure debug serial access */
258 gen550_init(0, &port);
259
260 /* Purge TLB entry added in head_44x.S for early serial access */
261 _tlbie(UART0_IO_BASE, 0);
262#endif
263
264 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
265 port.irq = UART1_INT;
266 port.uartclk = clocks.uart1;
267 port.line = 1;
268
269 if (early_serial_setup(&port) != 0) {
270 printk("Early serial init of port 1 failed\n");
271 }
272
273#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
274 /* Configure debug serial access */
275 gen550_init(1, &port);
276#endif
277}
278
279static void __init
280ocotea_setup_arch(void)
281{
282 ocotea_set_emacdata();
283
284 ibm440gx_tah_enable();
285
286 /*
287 * Determine various clocks.
288 * To be completely correct we should get SysClk
289 * from FPGA, because it can be changed by on-board switches
290 * --ebs
291 */
292 ibm440gx_get_clocks(&clocks, 33300000, 6 * 1843200);
293 ocp_sys_info.opb_bus_freq = clocks.opb;
294
295 /* Setup TODC access */
296 TODC_INIT(TODC_TYPE_DS1743,
297 0,
298 0,
299 ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
300 8);
301
302 /* init to some ~sane value until calibrate_delay() runs */
303 loops_per_jiffy = 50000000/HZ;
304
305 /* Setup PCI host bridge */
306 ocotea_setup_hose();
307
308#ifdef CONFIG_BLK_DEV_INITRD
309 if (initrd_start)
310 ROOT_DEV = Root_RAM0;
311 else
312#endif
313#ifdef CONFIG_ROOT_NFS
314 ROOT_DEV = Root_NFS;
315#else
316 ROOT_DEV = Root_HDA1;
317#endif
318
319 ocotea_early_serial_map();
320
321 /* Identify the system */
322 printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
323}
324
325static void __init ocotea_init(void)
326{
327 ibm440gx_l2c_setup(&clocks);
328}
329
330void __init platform_init(unsigned long r3, unsigned long r4,
331 unsigned long r5, unsigned long r6, unsigned long r7)
332{
333 ibm440gx_platform_init(r3, r4, r5, r6, r7);
334
335 ppc_md.setup_arch = ocotea_setup_arch;
336 ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
337 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
338
339 ppc_md.calibrate_decr = ocotea_calibrate_decr;
340 ppc_md.time_init = todc_time_init;
341 ppc_md.set_rtc_time = todc_set_rtc_time;
342 ppc_md.get_rtc_time = todc_get_rtc_time;
343
344 ppc_md.nvram_read_val = todc_direct_read_val;
345 ppc_md.nvram_write_val = todc_direct_write_val;
346#ifdef CONFIG_KGDB
347 ppc_md.early_serial_map = ocotea_early_serial_map;
348#endif
349 ppc_md.init = ocotea_init;
350}
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
deleted file mode 100644
index 89730ce2322c..000000000000
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Ocotea board definitions
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 *
6 * Copyright 2003-2005 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_OCOTEA_H__
17#define __ASM_OCOTEA_H__
18
19#include <platforms/4xx/ibm440gx.h>
20
21/* F/W TLB mapping used in bootloader glue to reset EMAC */
22#define PPC44x_EMAC0_MR0 0xe0000800
23
24/* Location of MAC addresses in PIBS image */
25#define PIBS_FLASH_BASE 0xfff00000
26#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xb0500)
27#define PIBS_MAC_SIZE 0x200
28#define PIBS_MAC_OFFSET 0x100
29
30/* External timer clock frequency */
31#define OCOTEA_TMR_CLK 25000000
32
33/* RTC/NVRAM location */
34#define OCOTEA_RTC_ADDR 0x0000000148000000ULL
35#define OCOTEA_RTC_SIZE 0x2000
36
37/* Flash */
38#define OCOTEA_FPGA_REG_0 0x0000000148300000ULL
39#define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40)
40#define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL
41#define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL
42#define OCOTEA_SMALL_FLASH_SIZE 0x100000
43#define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL
44#define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
45#define OCOTEA_LARGE_FLASH_SIZE 0x400000
46
47/* FPGA_REG_3 (Ethernet Groups) */
48#define OCOTEA_FPGA_REG_3 0x0000000148300003ULL
49
50/*
51 * Serial port defines
52 */
53#define RS_TABLE_SIZE 2
54
55#if defined(__BOOTER__)
56/* OpenBIOS defined UART mappings, used by bootloader shim */
57#define UART0_IO_BASE 0xE0000200
58#define UART1_IO_BASE 0xE0000300
59#else
60/* head_44x.S created UART mapping, used before early_serial_setup.
61 * We cannot use default OpenBIOS UART mappings because they
62 * don't work for configurations with more than 512M RAM. --ebs
63 */
64#define UART0_IO_BASE 0xF0000200
65#define UART1_IO_BASE 0xF0000300
66#endif
67
68#define BASE_BAUD 11059200/16
69#define STD_UART_OP(num) \
70 { 0, BASE_BAUD, 0, UART##num##_INT, \
71 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
72 iomem_base: (void*)UART##num##_IO_BASE, \
73 io_type: SERIAL_IO_MEM},
74
75#define SERIAL_PORT_DFNS \
76 STD_UART_OP(0) \
77 STD_UART_OP(1)
78
79/* PCI support */
80#define OCOTEA_PCI_LOWER_IO 0x00000000
81#define OCOTEA_PCI_UPPER_IO 0x0000ffff
82#define OCOTEA_PCI_LOWER_MEM 0x80000000
83#define OCOTEA_PCI_UPPER_MEM 0xffffefff
84
85#define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL
86#define OCOTEA_PCI_CFGA_PLB32 0x0ec00000
87#define OCOTEA_PCI_CFGD_PLB32 0x0ec00004
88
89#define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL
90#define OCOTEA_PCI_IO_SIZE 0x00010000
91#define OCOTEA_PCI_MEM_OFFSET 0x00000000
92
93#endif /* __ASM_OCOTEA_H__ */
94#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c
deleted file mode 100644
index 1be5d1c8e266..000000000000
--- a/arch/ppc/platforms/4xx/ppc440spe.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/*
2 * PPC440SPe I/O descriptions
3 *
4 * Roland Dreier <rolandd@cisco.com>
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 *
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
11 * Copyright (c) 2003, 2004 Zultys Technologies
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/init.h>
20#include <linux/module.h>
21#include <platforms/4xx/ppc440spe.h>
22#include <asm/ocp.h>
23#include <asm/ppc4xx_pic.h>
24
25static struct ocp_func_emac_data ppc440spe_emac0_def = {
26 .rgmii_idx = -1, /* No RGMII */
27 .rgmii_mux = -1, /* No RGMII */
28 .zmii_idx = -1, /* No ZMII */
29 .zmii_mux = -1, /* No ZMII */
30 .mal_idx = 0, /* MAL device index */
31 .mal_rx_chan = 0, /* MAL rx channel number */
32 .mal_tx_chan = 0, /* MAL tx channel number */
33 .wol_irq = 61, /* WOL interrupt number */
34 .mdio_idx = -1, /* No shared MDIO */
35 .tah_idx = -1, /* No TAH */
36};
37OCP_SYSFS_EMAC_DATA()
38
39static struct ocp_func_mal_data ppc440spe_mal0_def = {
40 .num_tx_chans = 1, /* Number of TX channels */
41 .num_rx_chans = 1, /* Number of RX channels */
42 .txeob_irq = 38, /* TX End Of Buffer IRQ */
43 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
44 .txde_irq = 34, /* TX Descriptor Error IRQ */
45 .rxde_irq = 35, /* RX Descriptor Error IRQ */
46 .serr_irq = 33, /* MAL System Error IRQ */
47 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
48};
49OCP_SYSFS_MAL_DATA()
50
51static struct ocp_func_iic_data ppc440spe_iic0_def = {
52 .fast_mode = 0, /* Use standad mode (100Khz) */
53};
54
55static struct ocp_func_iic_data ppc440spe_iic1_def = {
56 .fast_mode = 0, /* Use standad mode (100Khz) */
57};
58OCP_SYSFS_IIC_DATA()
59
60struct ocp_def core_ocp[] = {
61 { .vendor = OCP_VENDOR_IBM,
62 .function = OCP_FUNC_16550,
63 .index = 0,
64 .paddr = PPC440SPE_UART0_ADDR,
65 .irq = UART0_INT,
66 .pm = IBM_CPM_UART0,
67 },
68 { .vendor = OCP_VENDOR_IBM,
69 .function = OCP_FUNC_16550,
70 .index = 1,
71 .paddr = PPC440SPE_UART1_ADDR,
72 .irq = UART1_INT,
73 .pm = IBM_CPM_UART1,
74 },
75 { .vendor = OCP_VENDOR_IBM,
76 .function = OCP_FUNC_16550,
77 .index = 2,
78 .paddr = PPC440SPE_UART2_ADDR,
79 .irq = UART2_INT,
80 .pm = IBM_CPM_UART2,
81 },
82 { .vendor = OCP_VENDOR_IBM,
83 .function = OCP_FUNC_IIC,
84 .index = 0,
85 .paddr = 0x00000004f0000400ULL,
86 .irq = 2,
87 .pm = IBM_CPM_IIC0,
88 .additions = &ppc440spe_iic0_def,
89 .show = &ocp_show_iic_data
90 },
91 { .vendor = OCP_VENDOR_IBM,
92 .function = OCP_FUNC_IIC,
93 .index = 1,
94 .paddr = 0x00000004f0000500ULL,
95 .irq = 3,
96 .pm = IBM_CPM_IIC1,
97 .additions = &ppc440spe_iic1_def,
98 .show = &ocp_show_iic_data
99 },
100 { .vendor = OCP_VENDOR_IBM,
101 .function = OCP_FUNC_GPIO,
102 .index = 0,
103 .paddr = 0x00000004f0000700ULL,
104 .irq = OCP_IRQ_NA,
105 .pm = IBM_CPM_GPIO0,
106 },
107 { .vendor = OCP_VENDOR_IBM,
108 .function = OCP_FUNC_MAL,
109 .paddr = OCP_PADDR_NA,
110 .irq = OCP_IRQ_NA,
111 .pm = OCP_CPM_NA,
112 .additions = &ppc440spe_mal0_def,
113 .show = &ocp_show_mal_data,
114 },
115 { .vendor = OCP_VENDOR_IBM,
116 .function = OCP_FUNC_EMAC,
117 .index = 0,
118 .paddr = 0x00000004f0000800ULL,
119 .irq = 60,
120 .pm = OCP_CPM_NA,
121 .additions = &ppc440spe_emac0_def,
122 .show = &ocp_show_emac_data,
123 },
124 { .vendor = OCP_VENDOR_INVALID
125 }
126};
127
128/* Polarity and triggering settings for internal interrupt sources */
129struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
130 { .polarity = 0xffffffff,
131 .triggering = 0x010f0004,
132 .ext_irq_mask = 0x00000000,
133 },
134 { .polarity = 0xffffffff,
135 .triggering = 0x001f8040,
136 .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
137 },
138 { .polarity = 0xffffffff,
139 .triggering = 0x00000000,
140 .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */
141 },
142 { .polarity = 0xffffffff,
143 .triggering = 0x00000000,
144 .ext_irq_mask = 0x00000000,
145 },
146};
diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h
deleted file mode 100644
index f1e867c4c9fc..000000000000
--- a/arch/ppc/platforms/4xx/ppc440spe.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * PPC440SPe definitions
3 *
4 * Roland Dreier <rolandd@cisco.com>
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 *
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2004-2005 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __PPC_PLATFORMS_PPC440SPE_H
18#define __PPC_PLATFORMS_PPC440SPE_H
19
20
21#include <asm/ibm44x.h>
22
23/* UART */
24#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL
25#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL
26#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL
27#define UART0_INT 0
28#define UART1_INT 1
29#define UART2_INT 37
30
31/* Clock and Power Management */
32#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
33#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
34#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
35#define IBM_CPM_CPU 0x02000000 /* processor core */
36#define IBM_CPM_DMA 0x01000000 /* DMA controller */
37#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
38#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
39#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
40#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
41#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
42#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
43#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
44#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
45#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
46#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
47#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
48#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
49#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
50#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
51#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
52#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
53#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
54
55#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
56 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
57 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
58 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
59 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
60 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
61 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
62#endif /* __PPC_PLATFORMS_PPC440SP_H */
63#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c
deleted file mode 100644
index edf4d37d1a52..000000000000
--- a/arch/ppc/platforms/4xx/redwood5.c
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Support for the IBM redwood5 eval board file
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/pagemap.h>
14#include <linux/platform_device.h>
15#include <linux/ioport.h>
16#include <asm/io.h>
17#include <asm/machdep.h>
18#include <asm/ppc4xx_pic.h>
19
20/*
21 * Define external IRQ senses and polarities.
22 */
23unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
24 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
25 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
26 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
27 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
28 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
29 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
30};
31
32static struct resource smc91x_resources[] = {
33 [0] = {
34 .start = SMC91111_BASE_ADDR,
35 .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
36 .flags = IORESOURCE_MEM,
37 },
38 [1] = {
39 .start = SMC91111_IRQ,
40 .end = SMC91111_IRQ,
41 .flags = IORESOURCE_IRQ,
42 },
43};
44
45static struct platform_device smc91x_device = {
46 .name = "smc91x",
47 .id = 0,
48 .num_resources = ARRAY_SIZE(smc91x_resources),
49 .resource = smc91x_resources,
50};
51
52static struct platform_device *redwood5_devs[] __initdata = {
53 &smc91x_device,
54};
55
56static int __init
57redwood5_platform_add_devices(void)
58{
59 return platform_add_devices(redwood5_devs, ARRAY_SIZE(redwood5_devs));
60}
61
62void __init
63redwood5_setup_arch(void)
64{
65 ppc4xx_setup_arch();
66
67#ifdef CONFIG_DEBUG_BRINGUP
68 printk("\n");
69 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
70 printk("\n");
71 printk("bi_s_version\t %s\n", bip->bi_s_version);
72 printk("bi_r_version\t %s\n", bip->bi_r_version);
73 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,bip->bi_memsize/(1024*1000));
74 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
75 bip->bi_enetaddr[0], bip->bi_enetaddr[1],
76 bip->bi_enetaddr[2], bip->bi_enetaddr[3],
77 bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
78
79 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
80 bip->bi_intfreq, bip->bi_intfreq/ 1000000);
81
82 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
83 bip->bi_busfreq, bip->bi_busfreq / 1000000 );
84 printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
85 bip->bi_tbfreq, bip->bi_tbfreq/1000000);
86
87 printk("\n");
88#endif
89 device_initcall(redwood5_platform_add_devices);
90}
91
92void __init
93redwood5_map_io(void)
94{
95 int i;
96
97 ppc4xx_map_io();
98 for (i = 0; i < 16; i++) {
99 unsigned long v, p;
100
101 /* 0x400x0000 -> 0xe00x0000 */
102 p = 0x40000000 | (i << 16);
103 v = STB04xxx_IO_BASE | (i << 16);
104
105 io_block_mapping(v, p, PAGE_SIZE,
106 _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) | _PAGE_GUARDED);
107 }
108
109
110}
111
112void __init
113platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
114 unsigned long r6, unsigned long r7)
115{
116 ppc4xx_init(r3, r4, r5, r6, r7);
117
118 ppc_md.setup_arch = redwood5_setup_arch;
119 ppc_md.setup_io_mappings = redwood5_map_io;
120}
diff --git a/arch/ppc/platforms/4xx/redwood5.h b/arch/ppc/platforms/4xx/redwood5.h
deleted file mode 100644
index 49edd4818970..000000000000
--- a/arch/ppc/platforms/4xx/redwood5.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Macros, definitions, and data structures specific to the IBM PowerPC
3 * STB03xxx "Redwood" evaluation board.
4 *
5 * Author: Armin Kuster <akuster@mvista.com>
6 *
7 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __ASM_REDWOOD5_H__
15#define __ASM_REDWOOD5_H__
16
17/* Redwood5 has an STB04xxx core */
18#include <platforms/4xx/ibmstb4.h>
19
20#ifndef __ASSEMBLY__
21typedef struct board_info {
22 unsigned char bi_s_version[4]; /* Version of this structure */
23 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
24 unsigned int bi_memsize; /* DRAM installed, in bytes */
25 unsigned int bi_dummy; /* field shouldn't exist */
26 unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
27 unsigned int bi_intfreq; /* Processor speed, in Hz */
28 unsigned int bi_busfreq; /* Bus speed, in Hz */
29 unsigned int bi_tbfreq; /* Software timebase freq */
30} bd_t;
31#endif /* !__ASSEMBLY__ */
32
33
34#define SMC91111_BASE_ADDR 0xf2000300
35#define SMC91111_REG_SIZE 16
36#define SMC91111_IRQ 28
37
38#ifdef MAX_HWIFS
39#undef MAX_HWIFS
40#endif
41#define MAX_HWIFS 1
42
43#define _IO_BASE 0
44#define _ISA_MEM_BASE 0
45#define PCI_DRAM_OFFSET 0
46
47#define BASE_BAUD (378000000 / 18 / 16)
48
49#define PPC4xx_MACHINE_NAME "IBM Redwood5"
50
51#endif /* __ASM_REDWOOD5_H__ */
52#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c
deleted file mode 100644
index 006e29f83a1a..000000000000
--- a/arch/ppc/platforms/4xx/redwood6.c
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <linux/pagemap.h>
12#include <linux/platform_device.h>
13#include <linux/ioport.h>
14#include <asm/io.h>
15#include <asm/ppc4xx_pic.h>
16#include <linux/delay.h>
17#include <asm/machdep.h>
18
19/*
20 * Define external IRQ senses and polarities.
21 */
22unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
23 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
24 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
25 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
26 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
27 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
28 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
29 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
30 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
31 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
32 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
33};
34
35static struct resource smc91x_resources[] = {
36 [0] = {
37 .start = SMC91111_BASE_ADDR,
38 .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 [1] = {
42 .start = SMC91111_IRQ,
43 .end = SMC91111_IRQ,
44 .flags = IORESOURCE_IRQ,
45 },
46};
47
48static struct platform_device smc91x_device = {
49 .name = "smc91x",
50 .id = 0,
51 .num_resources = ARRAY_SIZE(smc91x_resources),
52 .resource = smc91x_resources,
53};
54
55static struct platform_device *redwood6_devs[] __initdata = {
56 &smc91x_device,
57};
58
59static int __init
60redwood6_platform_add_devices(void)
61{
62 return platform_add_devices(redwood6_devs, ARRAY_SIZE(redwood6_devs));
63}
64
65
66void __init
67redwood6_setup_arch(void)
68{
69#ifdef CONFIG_IDE
70 void *xilinx, *xilinx_1, *xilinx_2;
71 unsigned short us_reg5;
72#endif
73
74 ppc4xx_setup_arch();
75
76#ifdef CONFIG_IDE
77 xilinx = (unsigned long) ioremap(IDE_XLINUX_MUX_BASE, 0x10);
78 /* init xilinx control registers - enable ide mux, clear reset bit */
79 if (!xilinx) {
80 printk(KERN_CRIT
81 "redwood6_setup_arch() xilinxi ioremap failed\n");
82 return;
83 }
84 xilinx_1 = xilinx + 0xa;
85 xilinx_2 = xilinx + 0xe;
86
87 us_reg5 = readb(xilinx_1);
88 writeb(0x01d1, xilinx_1);
89 writeb(0x0008, xilinx_2);
90
91 udelay(10 * 1000);
92
93 writeb(0x01d1, xilinx_1);
94 writeb(0x0008, xilinx_2);
95#endif
96
97#ifdef DEBUG_BRINGUP
98 bd_t *bip = (bd_t *) __res;
99 printk("\n");
100 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
101 printk("\n");
102 printk("bi_s_version\t %s\n", bip->bi_s_version);
103 printk("bi_r_version\t %s\n", bip->bi_r_version);
104 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
105 bip->bi_memsize / (1024 * 1000));
106 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
107 bip->bi_enetaddr[0], bip->bi_enetaddr[1], bip->bi_enetaddr[2],
108 bip->bi_enetaddr[3], bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
109
110 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
111 bip->bi_intfreq, bip->bi_intfreq / 1000000);
112
113 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
114 bip->bi_busfreq, bip->bi_busfreq / 1000000);
115 printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
116 bip->bi_tbfreq, bip->bi_tbfreq / 1000000);
117
118 printk("\n");
119#endif
120
121 /* Identify the system */
122 printk(KERN_INFO "IBM Redwood6 (STBx25XX) Platform\n");
123 printk(KERN_INFO
124 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
125
126 device_initcall(redwood6_platform_add_devices);
127}
128
129void __init
130redwood6_map_io(void)
131{
132 int i;
133
134 ppc4xx_map_io();
135 for (i = 0; i < 16; i++) {
136 unsigned long v, p;
137
138 /* 0x400x0000 -> 0xe00x0000 */
139 p = 0x40000000 | (i << 16);
140 v = STBx25xx_IO_BASE | (i << 16);
141
142 io_block_mapping(v, p, PAGE_SIZE,
143 _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) |
144 _PAGE_GUARDED);
145 }
146}
147
148void __init
149platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
150 unsigned long r6, unsigned long r7)
151{
152 ppc4xx_init(r3, r4, r5, r6, r7);
153
154 ppc_md.setup_arch = redwood6_setup_arch;
155 ppc_md.setup_io_mappings = redwood6_map_io;
156}
diff --git a/arch/ppc/platforms/4xx/redwood6.h b/arch/ppc/platforms/4xx/redwood6.h
deleted file mode 100644
index 1edcbe5c51c7..000000000000
--- a/arch/ppc/platforms/4xx/redwood6.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Macros, definitions, and data structures specific to the IBM PowerPC
3 * STBx25xx "Redwood6" evaluation board.
4 *
5 * Author: Armin Kuster <akuster@mvista.com>
6 *
7 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __ASM_REDWOOD5_H__
15#define __ASM_REDWOOD5_H__
16
17/* Redwood6 has an STBx25xx core */
18#include <platforms/4xx/ibmstbx25.h>
19
20#ifndef __ASSEMBLY__
21typedef struct board_info {
22 unsigned char bi_s_version[4]; /* Version of this structure */
23 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
24 unsigned int bi_memsize; /* DRAM installed, in bytes */
25 unsigned int bi_dummy; /* field shouldn't exist */
26 unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
27 unsigned int bi_intfreq; /* Processor speed, in Hz */
28 unsigned int bi_busfreq; /* Bus speed, in Hz */
29 unsigned int bi_tbfreq; /* Software timebase freq */
30} bd_t;
31#endif /* !__ASSEMBLY__ */
32
33#define SMC91111_BASE_ADDR 0xf2030300
34#define SMC91111_REG_SIZE 16
35#define SMC91111_IRQ 27
36#define IDE_XLINUX_MUX_BASE 0xf2040000
37#define IDE_DMA_ADDR 0xfce00000
38
39#ifdef MAX_HWIFS
40#undef MAX_HWIFS
41#endif
42#define MAX_HWIFS 1
43
44#define _IO_BASE 0
45#define _ISA_MEM_BASE 0
46#define PCI_DRAM_OFFSET 0
47
48#define BASE_BAUD (378000000 / 18 / 16)
49
50#define PPC4xx_MACHINE_NAME "IBM Redwood6"
51
52#endif /* __ASM_REDWOOD5_H__ */
53#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
deleted file mode 100644
index 8689f3e8ef3a..000000000000
--- a/arch/ppc/platforms/4xx/sycamore.c
+++ /dev/null
@@ -1,272 +0,0 @@
1/*
2 * Architecture- / platform-specific boot-time initialization code for
3 * IBM PowerPC 4xx based boards.
4 *
5 * Author: Armin Kuster <akuster@mvista.com>
6 *
7 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/smp.h>
14#include <linux/threads.h>
15#include <linux/param.h>
16#include <linux/string.h>
17#include <linux/pci.h>
18#include <linux/rtc.h>
19
20#include <asm/ocp.h>
21#include <asm/ppc4xx_pic.h>
22#include <asm/system.h>
23#include <asm/pci-bridge.h>
24#include <asm/machdep.h>
25#include <asm/page.h>
26#include <asm/time.h>
27#include <asm/io.h>
28#include <asm/ibm_ocp_pci.h>
29#include <asm/todc.h>
30
31#undef DEBUG
32
33#ifdef DEBUG
34#define DBG(x...) printk(x)
35#else
36#define DBG(x...)
37#endif
38
39void *kb_cs;
40void *kb_data;
41void *sycamore_rtc_base;
42
43/*
44 * Define external IRQ senses and polarities.
45 */
46unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
47 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
48 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
49 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 10 */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 11 */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 12 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
57 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
58 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
60};
61
62
63/* Some IRQs unique to Sycamore.
64 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
65 */
66int __init
67ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
68{
69 static char pci_irq_table[][4] =
70 /*
71 * PCI IDSEL/INTPIN->INTLINE
72 * A B C D
73 */
74 {
75 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
76 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
77 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
78 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
79 };
80
81 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
82 return PCI_IRQ_TABLE_LOOKUP;
83};
84
85void __init
86sycamore_setup_arch(void)
87{
88 void *fpga_brdc;
89 unsigned char fpga_brdc_data;
90 void *fpga_enable;
91 void *fpga_polarity;
92 void *fpga_status;
93 void *fpga_trigger;
94
95 ppc4xx_setup_arch();
96
97 ibm_ocp_set_emac(0, 0);
98
99 kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
100 if (!kb_data) {
101 printk(KERN_CRIT
102 "sycamore_setup_arch() kb_data ioremap failed\n");
103 return;
104 }
105
106 kb_cs = kb_data + 1;
107
108 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
109 if (!fpga_status) {
110 printk(KERN_CRIT
111 "sycamore_setup_arch() fpga_status ioremap failed\n");
112 return;
113 }
114
115 fpga_enable = fpga_status + 1;
116 fpga_polarity = fpga_status + 2;
117 fpga_trigger = fpga_status + 3;
118 fpga_brdc = fpga_status + 4;
119
120 /* split the keyboard and mouse interrupts */
121 fpga_brdc_data = readb(fpga_brdc);
122 fpga_brdc_data |= 0x80;
123 writeb(fpga_brdc_data, fpga_brdc);
124
125 writeb(0x3, fpga_enable);
126
127 writeb(0x3, fpga_polarity);
128
129 writeb(0x3, fpga_trigger);
130
131 /* RTC step for the sycamore */
132 sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
133 TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
134 sycamore_rtc_base, 8);
135
136 /* Identify the system */
137 printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
138 printk(KERN_INFO
139 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
140}
141
142void __init
143bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
144{
145#ifdef CONFIG_PCI
146 unsigned int bar_response, bar;
147 /*
148 * Expected PCI mapping:
149 *
150 * PLB addr PCI memory addr
151 * --------------------- ---------------------
152 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
153 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
154 *
155 * PLB addr PCI io addr
156 * --------------------- ---------------------
157 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
158 *
159 * The following code is simplified by assuming that the bootrom
160 * has been well behaved in following this mapping.
161 */
162
163#ifdef DEBUG
164 int i;
165
166 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
167 printk("PCI bridge regs before fixup \n");
168 for (i = 0; i <= 3; i++) {
169 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
170 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
171 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
172 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
173 }
174 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
175 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
176 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
177 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
178
179#endif
180
181 /* added for IBM boot rom version 1.15 bios bar changes -AK */
182
183 /* Disable region first */
184 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
185 /* PLB starting addr, PCI: 0x80000000 */
186 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
187 /* PCI start addr, 0x80000000 */
188 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
189 /* 512MB range of PLB to PCI */
190 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
191 /* Enable no pre-fetch, enable region */
192 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
193 (PPC405_PCI_UPPER_MEM -
194 PPC405_PCI_MEM_BASE)) | 0x01));
195
196 /* Enable inbound region one - 1GB size */
197 out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
198
199 /* Disable outbound region one */
200 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
201 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
202 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
203 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
204 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
205
206 /* Disable inbound region two */
207 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
208
209 /* Disable outbound region two */
210 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
211 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
212 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
213 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
214 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
215
216 /* Zero config bars */
217 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
218 early_write_config_dword(hose, hose->first_busno,
219 PCI_FUNC(hose->first_busno), bar,
220 0x00000000);
221 early_read_config_dword(hose, hose->first_busno,
222 PCI_FUNC(hose->first_busno), bar,
223 &bar_response);
224 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
225 hose->first_busno, PCI_SLOT(hose->first_busno),
226 PCI_FUNC(hose->first_busno), bar, bar_response);
227 }
228 /* end workaround */
229
230#ifdef DEBUG
231 printk("PCI bridge regs after fixup \n");
232 for (i = 0; i <= 3; i++) {
233 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
234 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
235 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
236 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
237 }
238 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
239 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
240 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
241 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
242
243#endif
244#endif
245
246}
247
248void __init
249sycamore_map_io(void)
250{
251 ppc4xx_map_io();
252 io_block_mapping(SYCAMORE_RTC_VADDR,
253 SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
254}
255
256void __init
257platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
258 unsigned long r6, unsigned long r7)
259{
260 ppc4xx_init(r3, r4, r5, r6, r7);
261
262 ppc_md.setup_arch = sycamore_setup_arch;
263 ppc_md.setup_io_mappings = sycamore_map_io;
264
265#ifdef CONFIG_GEN_RTC
266 ppc_md.time_init = todc_time_init;
267 ppc_md.set_rtc_time = todc_set_rtc_time;
268 ppc_md.get_rtc_time = todc_get_rtc_time;
269 ppc_md.nvram_read_val = todc_direct_read_val;
270 ppc_md.nvram_write_val = todc_direct_write_val;
271#endif
272}
diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h
deleted file mode 100644
index 69b169eac053..000000000000
--- a/arch/ppc/platforms/4xx/sycamore.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Sycamore board definitions
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * Armin Kuster <akuster@mvista.com>
9 * 2000 (c) MontaVista, Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifdef __KERNEL__
19#ifndef __ASM_SYCAMORE_H__
20#define __ASM_SYCAMORE_H__
21
22#include <platforms/4xx/ibm405gpr.h>
23#include <asm/ppcboot.h>
24
25/* Memory map for the IBM "Sycamore" 405GPr evaluation board.
26 * Generic 4xx plus RTC.
27 */
28
29#define SYCAMORE_RTC_PADDR ((uint)0xf0000000)
30#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR
31#define SYCAMORE_RTC_SIZE ((uint)8*1024)
32
33#define BASE_BAUD 691200
34
35#define SYCAMORE_PS2_BASE 0xF0100000
36
37/* Flash */
38#define PPC40x_FPGA_BASE 0xF0300000
39#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
40#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
41#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
42#define PPC40x_FLASH_LOW 0xFFF00000
43#define PPC40x_FLASH_HIGH 0xFFF80000
44#define PPC40x_FLASH_SIZE 0x80000
45
46#define PPC4xx_MACHINE_NAME "IBM Sycamore"
47
48#endif /* __ASM_SYCAMORE_H__ */
49#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
deleted file mode 100644
index 115694275083..000000000000
--- a/arch/ppc/platforms/4xx/taishan.c
+++ /dev/null
@@ -1,395 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/taishan.c
3 *
4 * AMCC Taishan board specific routines
5 *
6 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/types.h>
22#include <linux/major.h>
23#include <linux/blkdev.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/initrd.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29#include <linux/tty.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33#include <linux/platform_device.h>
34#include <linux/mtd/partitions.h>
35#include <linux/mtd/nand.h>
36#include <linux/mtd/ndfc.h>
37#include <linux/mtd/physmap.h>
38
39#include <asm/machdep.h>
40#include <asm/ocp.h>
41#include <asm/bootinfo.h>
42#include <asm/ppcboot.h>
43
44#include <syslib/gen550.h>
45#include <syslib/ibm440gx_common.h>
46
47extern bd_t __res;
48
49static struct ibm44x_clocks clocks __initdata;
50
51/*
52 * NOR FLASH configuration (using mtd physmap driver)
53 */
54
55/* start will be added dynamically, end is always fixed */
56static struct resource taishan_nor_resource = {
57 .start = TAISHAN_FLASH_ADDR,
58 .end = 0x1ffffffffULL,
59 .flags = IORESOURCE_MEM,
60};
61
62#define RW_PART0_OF 0
63#define RW_PART0_SZ 0x180000
64#define RW_PART1_SZ 0x200000
65/* Partition 2 will be autosized dynamically... */
66#define RW_PART3_SZ 0x80000
67#define RW_PART4_SZ 0x40000
68
69static struct mtd_partition taishan_nor_parts[] = {
70 {
71 .name = "kernel",
72 .offset = 0,
73 .size = RW_PART0_SZ
74 },
75 {
76 .name = "root",
77 .offset = MTDPART_OFS_APPEND,
78 .size = RW_PART1_SZ,
79 },
80 {
81 .name = "user",
82 .offset = MTDPART_OFS_APPEND,
83/* .size = RW_PART2_SZ */ /* will be adjusted dynamically */
84 },
85 {
86 .name = "env",
87 .offset = MTDPART_OFS_APPEND,
88 .size = RW_PART3_SZ,
89 },
90 {
91 .name = "u-boot",
92 .offset = MTDPART_OFS_APPEND,
93 .size = RW_PART4_SZ,
94 }
95};
96
97static struct physmap_flash_data taishan_nor_data = {
98 .width = 4,
99 .parts = taishan_nor_parts,
100 .nr_parts = ARRAY_SIZE(taishan_nor_parts),
101};
102
103static struct platform_device taishan_nor_device = {
104 .name = "physmap-flash",
105 .id = 0,
106 .dev = {
107 .platform_data = &taishan_nor_data,
108 },
109 .num_resources = 1,
110 .resource = &taishan_nor_resource,
111};
112
113static int taishan_setup_flash(void)
114{
115 /*
116 * Adjust partition 2 to flash size
117 */
118 taishan_nor_parts[2].size = __res.bi_flashsize -
119 RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ;
120
121 platform_device_register(&taishan_nor_device);
122
123 return 0;
124}
125arch_initcall(taishan_setup_flash);
126
127static void __init
128taishan_calibrate_decr(void)
129{
130 unsigned int freq;
131
132 if (mfspr(SPRN_CCR1) & CCR1_TCS)
133 freq = TAISHAN_TMR_CLK;
134 else
135 freq = clocks.cpu;
136
137 ibm44x_calibrate_decr(freq);
138}
139
140static int
141taishan_show_cpuinfo(struct seq_file *m)
142{
143 seq_printf(m, "vendor\t\t: AMCC\n");
144 seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n");
145 ibm440gx_show_cpuinfo(m);
146 return 0;
147}
148
149static inline int
150taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
151{
152 static char pci_irq_table[][4] =
153 /*
154 * PCI IDSEL/INTPIN->INTLINE
155 * A B C D
156 */
157 {
158 { 23, 24, 25, 26 }, /* IDSEL 1 - PCI Slot 0 */
159 { 24, 25, 26, 23 }, /* IDSEL 2 - PCI Slot 1 */
160 };
161
162 const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
163 return PCI_IRQ_TABLE_LOOKUP;
164}
165
166static void __init taishan_set_emacdata(void)
167{
168 struct ocp_def *def;
169 struct ocp_func_emac_data *emacdata;
170 int i;
171
172 /* Set phy_map, phy_mode, and mac_addr for each EMAC */
173 for (i=2; i<4; i++) {
174 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
175 emacdata = def->additions;
176 if (i < 2) {
177 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
178 emacdata->phy_mode = PHY_MODE_SMII;
179 } else {
180 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
181 emacdata->phy_mode = PHY_MODE_RGMII;
182 }
183 if (i == 0)
184 memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
185 else if (i == 1)
186 memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
187 else if (i == 2)
188 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
189 else if (i == 3)
190 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
191 }
192}
193
194#define PCIX_READW(offset) \
195 (readw(pcix_reg_base+offset))
196
197#define PCIX_WRITEW(value, offset) \
198 (writew(value, pcix_reg_base+offset))
199
200#define PCIX_WRITEL(value, offset) \
201 (writel(value, pcix_reg_base+offset))
202
203/*
204 * FIXME: This is only here to "make it work". This will move
205 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
206 * configuration library. -Matt
207 */
208static void __init
209taishan_setup_pcix(void)
210{
211 void *pcix_reg_base;
212
213 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
214
215 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
216 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
217
218 /* Disable all windows */
219 PCIX_WRITEL(0, PCIX0_POM0SA);
220 PCIX_WRITEL(0, PCIX0_POM1SA);
221 PCIX_WRITEL(0, PCIX0_POM2SA);
222 PCIX_WRITEL(0, PCIX0_PIM0SA);
223 PCIX_WRITEL(0, PCIX0_PIM0SAH);
224 PCIX_WRITEL(0, PCIX0_PIM1SA);
225 PCIX_WRITEL(0, PCIX0_PIM2SA);
226 PCIX_WRITEL(0, PCIX0_PIM2SAH);
227
228 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
229 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
230 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
231 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
232 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
233 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
234
235 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
236 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
237 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
238 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
239 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
240
241 iounmap(pcix_reg_base);
242
243 eieio();
244}
245
246static void __init
247taishan_setup_hose(void)
248{
249 struct pci_controller *hose;
250
251 /* Configure windows on the PCI-X host bridge */
252 taishan_setup_pcix();
253
254 hose = pcibios_alloc_controller();
255
256 if (!hose)
257 return;
258
259 hose->first_busno = 0;
260 hose->last_busno = 0xff;
261
262 hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET;
263
264 pci_init_resource(&hose->io_resource,
265 TAISHAN_PCI_LOWER_IO,
266 TAISHAN_PCI_UPPER_IO,
267 IORESOURCE_IO,
268 "PCI host bridge");
269
270 pci_init_resource(&hose->mem_resources[0],
271 TAISHAN_PCI_LOWER_MEM,
272 TAISHAN_PCI_UPPER_MEM,
273 IORESOURCE_MEM,
274 "PCI host bridge");
275
276 hose->io_space.start = TAISHAN_PCI_LOWER_IO;
277 hose->io_space.end = TAISHAN_PCI_UPPER_IO;
278 hose->mem_space.start = TAISHAN_PCI_LOWER_MEM;
279 hose->mem_space.end = TAISHAN_PCI_UPPER_MEM;
280 hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE);
281 isa_io_base = (unsigned long) hose->io_base_virt;
282
283 setup_indirect_pci(hose,
284 TAISHAN_PCI_CFGA_PLB32,
285 TAISHAN_PCI_CFGD_PLB32);
286 hose->set_cfg_type = 1;
287
288 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
289
290 ppc_md.pci_swizzle = common_swizzle;
291 ppc_md.pci_map_irq = taishan_map_irq;
292}
293
294
295static void __init
296taishan_early_serial_map(void)
297{
298 struct uart_port port;
299
300 /* Setup ioremapped serial port access */
301 memset(&port, 0, sizeof(port));
302 port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
303 port.irq = UART0_INT;
304 port.uartclk = clocks.uart0;
305 port.regshift = 0;
306 port.iotype = UPIO_MEM;
307 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
308 port.line = 0;
309
310 if (early_serial_setup(&port) != 0)
311 printk("Early serial init of port 0 failed\n");
312
313#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
314 /* Configure debug serial access */
315 gen550_init(0, &port);
316
317 /* Purge TLB entry added in head_44x.S for early serial access */
318 _tlbie(UART0_IO_BASE, 0);
319#endif
320
321 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
322 port.irq = UART1_INT;
323 port.uartclk = clocks.uart1;
324 port.line = 1;
325
326 if (early_serial_setup(&port) != 0)
327 printk("Early serial init of port 1 failed\n");
328
329#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
330 /* Configure debug serial access */
331 gen550_init(1, &port);
332#endif
333}
334
335static void __init
336taishan_setup_arch(void)
337{
338 taishan_set_emacdata();
339
340 ibm440gx_tah_enable();
341
342 /*
343 * Determine various clocks.
344 * To be completely correct we should get SysClk
345 * from FPGA, because it can be changed by on-board switches
346 * --ebs
347 */
348 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
349 ocp_sys_info.opb_bus_freq = clocks.opb;
350
351 /* init to some ~sane value until calibrate_delay() runs */
352 loops_per_jiffy = 50000000/HZ;
353
354 /* Setup PCI host bridge */
355 taishan_setup_hose();
356
357#ifdef CONFIG_BLK_DEV_INITRD
358 if (initrd_start)
359 ROOT_DEV = Root_RAM0;
360 else
361#endif
362#ifdef CONFIG_ROOT_NFS
363 ROOT_DEV = Root_NFS;
364#else
365 ROOT_DEV = Root_HDA1;
366#endif
367
368 taishan_early_serial_map();
369
370 /* Identify the system */
371 printk("AMCC PowerPC 440GX Taishan Platform\n");
372}
373
374static void __init taishan_init(void)
375{
376 ibm440gx_l2c_setup(&clocks);
377}
378
379void __init platform_init(unsigned long r3, unsigned long r4,
380 unsigned long r5, unsigned long r6, unsigned long r7)
381{
382 ibm44x_platform_init(r3, r4, r5, r6, r7);
383
384 ppc_md.setup_arch = taishan_setup_arch;
385 ppc_md.show_cpuinfo = taishan_show_cpuinfo;
386 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
387
388 ppc_md.calibrate_decr = taishan_calibrate_decr;
389
390#ifdef CONFIG_KGDB
391 ppc_md.early_serial_map = taishan_early_serial_map;
392#endif
393 ppc_md.init = taishan_init;
394}
395
diff --git a/arch/ppc/platforms/4xx/taishan.h b/arch/ppc/platforms/4xx/taishan.h
deleted file mode 100644
index ea7561a80457..000000000000
--- a/arch/ppc/platforms/4xx/taishan.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/taishan.h
3 *
4 * AMCC Taishan board definitions
5 *
6 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_TAISHAN_H__
17#define __ASM_TAISHAN_H__
18
19#include <platforms/4xx/ibm440gx.h>
20
21/* External timer clock frequency */
22#define TAISHAN_TMR_CLK 25000000
23
24/* Flash */
25#define TAISHAN_FPGA_ADDR 0x0000000141000000ULL
26#define TAISHAN_LCM_ADDR 0x0000000142000000ULL
27#define TAISHAN_FLASH_ADDR 0x00000001fc000000ULL
28#define TAISHAN_FLASH_SIZE 0x4000000
29
30/*
31 * Serial port defines
32 */
33#define RS_TABLE_SIZE 2
34
35/* head_44x.S created UART mapping, used before early_serial_setup.
36 * We cannot use default OpenBIOS UART mappings because they
37 * don't work for configurations with more than 512M RAM. --ebs
38 */
39#define UART0_IO_BASE 0xF0000200
40#define UART1_IO_BASE 0xF0000300
41
42#define BASE_BAUD 11059200/16
43#define STD_UART_OP(num) \
44 { 0, BASE_BAUD, 0, UART##num##_INT, \
45 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
46 iomem_base: (void*)UART##num##_IO_BASE, \
47 io_type: SERIAL_IO_MEM},
48
49#define SERIAL_PORT_DFNS \
50 STD_UART_OP(0) \
51 STD_UART_OP(1)
52
53/* PCI support */
54#define TAISHAN_PCI_LOWER_IO 0x00000000
55#define TAISHAN_PCI_UPPER_IO 0x0000ffff
56#define TAISHAN_PCI_LOWER_MEM 0x80000000
57#define TAISHAN_PCI_UPPER_MEM 0xffffefff
58
59#define TAISHAN_PCI_CFGA_PLB32 0x0ec00000
60#define TAISHAN_PCI_CFGD_PLB32 0x0ec00004
61
62#define TAISHAN_PCI_IO_BASE 0x0000000208000000ULL
63#define TAISHAN_PCI_IO_SIZE 0x00010000
64#define TAISHAN_PCI_MEM_OFFSET 0x00000000
65
66#endif /* __ASM_TAISHAN_H__ */
67#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h
deleted file mode 100644
index 738280420be5..000000000000
--- a/arch/ppc/platforms/4xx/virtex.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Basic Virtex platform defines, included by <asm/ibm4xx.h>
3 *
4 * 2005-2007 (c) Secret Lab Technologies Ltd.
5 * 2002-2004 (c) MontaVista Software, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#ifdef __KERNEL__
13#ifndef __ASM_VIRTEX_H__
14#define __ASM_VIRTEX_H__
15
16#include <asm/ibm405.h>
17#include <asm/ppcboot.h>
18
19/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */
20#if !defined(BASE_BAUD)
21 #define BASE_BAUD (0) /* dummy value; not used */
22#endif
23
24#ifndef __ASSEMBLY__
25extern const char* virtex_machine_name;
26#define PPC4xx_MACHINE_NAME (virtex_machine_name)
27#endif /* !__ASSEMBLY__ */
28
29/* We don't need anything mapped. Size of zero will accomplish that. */
30#define PPC4xx_ONB_IO_PADDR 0u
31#define PPC4xx_ONB_IO_VADDR 0u
32#define PPC4xx_ONB_IO_SIZE 0u
33
34#endif /* __ASM_VIRTEX_H__ */
35#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c
deleted file mode 100644
index 2f9772340854..000000000000
--- a/arch/ppc/platforms/4xx/walnut.c
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * Architecture- / platform-specific boot-time initialization code for
3 * IBM PowerPC 4xx based boards. Adapted from original
4 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
5 * <dan@net4x.com>.
6 *
7 * Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
8 *
9 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/init.h>
15#include <linux/smp.h>
16#include <linux/threads.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/pci.h>
20#include <linux/rtc.h>
21
22#include <asm/system.h>
23#include <asm/pci-bridge.h>
24#include <asm/machdep.h>
25#include <asm/page.h>
26#include <asm/time.h>
27#include <asm/io.h>
28#include <asm/ocp.h>
29#include <asm/ibm_ocp_pci.h>
30#include <asm/todc.h>
31
32#undef DEBUG
33
34#ifdef DEBUG
35#define DBG(x...) printk(x)
36#else
37#define DBG(x...)
38#endif
39
40void *kb_cs;
41void *kb_data;
42void *walnut_rtc_base;
43
44/* Some IRQs unique to Walnut.
45 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
46 */
47int __init
48ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
49{
50 static char pci_irq_table[][4] =
51 /*
52 * PCI IDSEL/INTPIN->INTLINE
53 * A B C D
54 */
55 {
56 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
57 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
58 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
59 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
60 };
61
62 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
63 return PCI_IRQ_TABLE_LOOKUP;
64};
65
66void __init
67walnut_setup_arch(void)
68{
69
70 void *fpga_brdc;
71 unsigned char fpga_brdc_data;
72 void *fpga_enable;
73 void *fpga_polarity;
74 void *fpga_status;
75 void *fpga_trigger;
76
77 ppc4xx_setup_arch();
78
79 ibm_ocp_set_emac(0, 0);
80
81 kb_data = ioremap(WALNUT_PS2_BASE, 8);
82 if (!kb_data) {
83 printk(KERN_CRIT
84 "walnut_setup_arch() kb_data ioremap failed\n");
85 return;
86 }
87
88 kb_cs = kb_data + 1;
89
90 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
91 if (!fpga_status) {
92 printk(KERN_CRIT
93 "walnut_setup_arch() fpga_status ioremap failed\n");
94 return;
95 }
96
97 fpga_enable = fpga_status + 1;
98 fpga_polarity = fpga_status + 2;
99 fpga_trigger = fpga_status + 3;
100 fpga_brdc = fpga_status + 4;
101
102 /* split the keyboard and mouse interrupts */
103 fpga_brdc_data = readb(fpga_brdc);
104 fpga_brdc_data |= 0x80;
105 writeb(fpga_brdc_data, fpga_brdc);
106
107 writeb(0x3, fpga_enable);
108
109 writeb(0x3, fpga_polarity);
110
111 writeb(0x3, fpga_trigger);
112
113 /* RTC step for the walnut */
114 walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
115 TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
116 walnut_rtc_base, 8);
117 /* Identify the system */
118 printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n");
119}
120
121void __init
122bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
123{
124#ifdef CONFIG_PCI
125 unsigned int bar_response, bar;
126 /*
127 * Expected PCI mapping:
128 *
129 * PLB addr PCI memory addr
130 * --------------------- ---------------------
131 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
132 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
133 *
134 * PLB addr PCI io addr
135 * --------------------- ---------------------
136 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
137 *
138 * The following code is simplified by assuming that the bootrom
139 * has been well behaved in following this mapping.
140 */
141
142#ifdef DEBUG
143 int i;
144
145 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
146 printk("PCI bridge regs before fixup \n");
147 for (i = 0; i <= 3; i++) {
148 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
149 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
150 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
151 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
152 }
153 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
154 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
155 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
156 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
157
158#endif
159
160 /* added for IBM boot rom version 1.15 bios bar changes -AK */
161
162 /* Disable region first */
163 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
164 /* PLB starting addr, PCI: 0x80000000 */
165 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
166 /* PCI start addr, 0x80000000 */
167 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
168 /* 512MB range of PLB to PCI */
169 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
170 /* Enable no pre-fetch, enable region */
171 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
172 (PPC405_PCI_UPPER_MEM -
173 PPC405_PCI_MEM_BASE)) | 0x01));
174
175 /* Disable region one */
176 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
177 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
178 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
179 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
180 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
181 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
182
183 /* Disable region two */
184 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
185 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
186 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
187 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
188 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
189 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
190
191 /* Zero config bars */
192 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
193 early_write_config_dword(hose, hose->first_busno,
194 PCI_FUNC(hose->first_busno), bar,
195 0x00000000);
196 early_read_config_dword(hose, hose->first_busno,
197 PCI_FUNC(hose->first_busno), bar,
198 &bar_response);
199 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
200 hose->first_busno, PCI_SLOT(hose->first_busno),
201 PCI_FUNC(hose->first_busno), bar, bar_response);
202 }
203 /* end work around */
204
205#ifdef DEBUG
206 printk("PCI bridge regs after fixup \n");
207 for (i = 0; i <= 3; i++) {
208 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
209 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
210 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
211 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
212 }
213 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
214 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
215 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
216 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
217
218#endif
219#endif
220}
221
222void __init
223walnut_map_io(void)
224{
225 ppc4xx_map_io();
226 io_block_mapping(WALNUT_RTC_VADDR,
227 WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
228}
229
230void __init
231platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
232 unsigned long r6, unsigned long r7)
233{
234 ppc4xx_init(r3, r4, r5, r6, r7);
235
236 ppc_md.setup_arch = walnut_setup_arch;
237 ppc_md.setup_io_mappings = walnut_map_io;
238
239#ifdef CONFIG_GEN_RTC
240 ppc_md.time_init = todc_time_init;
241 ppc_md.set_rtc_time = todc_set_rtc_time;
242 ppc_md.get_rtc_time = todc_get_rtc_time;
243 ppc_md.nvram_read_val = todc_direct_read_val;
244 ppc_md.nvram_write_val = todc_direct_write_val;
245#endif
246}
diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h
deleted file mode 100644
index d9c4eb788940..000000000000
--- a/arch/ppc/platforms/4xx/walnut.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Walnut board definitions
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
9 * Frank Rowand <frank_rowand@mvista.com>
10 * Debbie Chu <debbie_chu@mvista.com>
11 * 2000 (c) MontaVista, Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#ifdef __KERNEL__
21#ifndef __ASM_WALNUT_H__
22#define __ASM_WALNUT_H__
23
24#include <platforms/4xx/ibm405gp.h>
25#include <asm/ppcboot.h>
26
27/* Memory map for the IBM "Walnut" 405GP evaluation board.
28 * Generic 4xx plus RTC.
29 */
30
31#define WALNUT_RTC_PADDR ((uint)0xf0000000)
32#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR
33#define WALNUT_RTC_SIZE ((uint)8*1024)
34
35#define BASE_BAUD 691200
36
37#define WALNUT_PS2_BASE 0xF0100000
38
39/* Flash */
40#define PPC40x_FPGA_BASE 0xF0300000
41#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
42#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
43#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
44#define PPC40x_FLASH_LOW 0xFFF00000
45#define PPC40x_FLASH_HIGH 0xFFF80000
46#define PPC40x_FLASH_SIZE 0x80000
47#define WALNUT_FPGA_BASE PPC40x_FPGA_BASE
48
49#define PPC4xx_MACHINE_NAME "IBM Walnut"
50
51#endif /* __ASM_WALNUT_H__ */
52#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c
deleted file mode 100644
index 6e522fefc26f..000000000000
--- a/arch/ppc/platforms/4xx/xilinx_ml300.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * Xilinx ML300 evaluation board initialization
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is licensed
9 * "as is" without any warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/tty.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/serial_8250.h>
18#include <linux/serialP.h>
19#include <asm/io.h>
20#include <asm/machdep.h>
21
22#include <syslib/gen550.h>
23#include <syslib/virtex_devices.h>
24#include <platforms/4xx/xparameters/xparameters.h>
25
26/*
27 * As an overview of how the following functions (platform_init,
28 * ml300_map_io, ml300_setup_arch and ml300_init_IRQ) fit into the
29 * kernel startup procedure, here's a call tree:
30 *
31 * start_here arch/ppc/kernel/head_4xx.S
32 * early_init arch/ppc/kernel/setup.c
33 * machine_init arch/ppc/kernel/setup.c
34 * platform_init this file
35 * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c
36 * parse_bootinfo
37 * find_bootinfo
38 * "setup some default ppc_md pointers"
39 * MMU_init arch/ppc/mm/init.c
40 * *ppc_md.setup_io_mappings == ml300_map_io this file
41 * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c
42 * start_kernel init/main.c
43 * setup_arch arch/ppc/kernel/setup.c
44 * #if defined(CONFIG_KGDB)
45 * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
46 * #endif
47 * *ppc_md.setup_arch == ml300_setup_arch this file
48 * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c
49 * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c
50 * init_IRQ arch/ppc/kernel/irq.c
51 * *ppc_md.init_IRQ == ml300_init_IRQ this file
52 * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c
53 * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
54 */
55
56const char* virtex_machine_name = "ML300 Reference Design";
57
58#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
59static volatile unsigned *powerdown_base =
60 (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
61
62static void
63xilinx_power_off(void)
64{
65 local_irq_disable();
66 out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
67 while (1) ;
68}
69#endif
70
71void __init
72ml300_map_io(void)
73{
74 ppc4xx_map_io();
75
76#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
77 powerdown_base = ioremap((unsigned long) powerdown_base,
78 XPAR_POWER_0_POWERDOWN_HIGHADDR -
79 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
80#endif
81}
82
83void __init
84ml300_setup_arch(void)
85{
86 virtex_early_serial_map();
87 ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
88
89 /* Identify the system */
90 printk(KERN_INFO "Xilinx ML300 Reference System (Virtex-II Pro)\n");
91}
92
93/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
94void __init
95ml300_init_irq(void)
96{
97 ppc4xx_init_IRQ();
98}
99
100void __init
101platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
102 unsigned long r6, unsigned long r7)
103{
104 ppc4xx_init(r3, r4, r5, r6, r7);
105
106 ppc_md.setup_arch = ml300_setup_arch;
107 ppc_md.setup_io_mappings = ml300_map_io;
108 ppc_md.init_IRQ = ml300_init_irq;
109
110#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
111 ppc_md.power_off = xilinx_power_off;
112#endif
113
114#ifdef CONFIG_KGDB
115 ppc_md.early_serial_map = virtex_early_serial_map;
116#endif
117}
118
diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c
deleted file mode 100644
index bc3ace3762e7..000000000000
--- a/arch/ppc/platforms/4xx/xilinx_ml403.c
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Xilinx ML403 evaluation board initialization
3 *
4 * Author: Grant Likely <grant.likely@secretlab.ca>
5 *
6 * 2005-2007 (c) Secret Lab Technologies Ltd.
7 * 2002-2004 (c) MontaVista Software, Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/tty.h>
17#include <linux/serial.h>
18#include <linux/serial_core.h>
19#include <linux/serial_8250.h>
20#include <linux/serialP.h>
21#include <asm/io.h>
22#include <asm/machdep.h>
23
24#include <syslib/gen550.h>
25#include <syslib/virtex_devices.h>
26#include <platforms/4xx/xparameters/xparameters.h>
27
28/*
29 * As an overview of how the following functions (platform_init,
30 * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the
31 * kernel startup procedure, here's a call tree:
32 *
33 * start_here arch/ppc/kernel/head_4xx.S
34 * early_init arch/ppc/kernel/setup.c
35 * machine_init arch/ppc/kernel/setup.c
36 * platform_init this file
37 * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c
38 * parse_bootinfo
39 * find_bootinfo
40 * "setup some default ppc_md pointers"
41 * MMU_init arch/ppc/mm/init.c
42 * *ppc_md.setup_io_mappings == ml403_map_io this file
43 * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c
44 * start_kernel init/main.c
45 * setup_arch arch/ppc/kernel/setup.c
46 * #if defined(CONFIG_KGDB)
47 * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
48 * #endif
49 * *ppc_md.setup_arch == ml403_setup_arch this file
50 * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c
51 * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c
52 * init_IRQ arch/ppc/kernel/irq.c
53 * *ppc_md.init_IRQ == ml403_init_IRQ this file
54 * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c
55 * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
56 */
57
58const char* virtex_machine_name = "ML403 Reference Design";
59
60#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
61static volatile unsigned *powerdown_base =
62 (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
63
64static void
65xilinx_power_off(void)
66{
67 local_irq_disable();
68 out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
69 while (1) ;
70}
71#endif
72
73void __init
74ml403_map_io(void)
75{
76 ppc4xx_map_io();
77
78#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
79 powerdown_base = ioremap((unsigned long) powerdown_base,
80 XPAR_POWER_0_POWERDOWN_HIGHADDR -
81 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
82#endif
83}
84
85void __init
86ml403_setup_arch(void)
87{
88 virtex_early_serial_map();
89 ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
90
91 /* Identify the system */
92 printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n");
93}
94
95/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
96void __init
97ml403_init_irq(void)
98{
99 ppc4xx_init_IRQ();
100}
101
102void __init
103platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
104 unsigned long r6, unsigned long r7)
105{
106 ppc4xx_init(r3, r4, r5, r6, r7);
107
108 ppc_md.setup_arch = ml403_setup_arch;
109 ppc_md.setup_io_mappings = ml403_map_io;
110 ppc_md.init_IRQ = ml403_init_irq;
111
112#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
113 ppc_md.power_off = xilinx_power_off;
114#endif
115
116#ifdef CONFIG_KGDB
117 ppc_md.early_serial_map = virtex_early_serial_map;
118#endif
119}
120
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h
deleted file mode 100644
index 650888b00fb0..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/xparameters/xparameters.h
3 *
4 * This file includes the correct xparameters.h for the CONFIG'ed board plus
5 * fixups to translate board specific XPAR values to a common set of names
6 *
7 * Author: MontaVista Software, Inc.
8 * source@mvista.com
9 *
10 * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms
11 * of the GNU General Public License version 2. This program is licensed
12 * "as is" without any warranty of any kind, whether express or implied.
13 */
14
15
16#if defined(CONFIG_XILINX_ML300)
17 #include "xparameters_ml300.h"
18 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
19 XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
20 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
21 XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
22#elif defined(CONFIG_XILINX_ML403)
23 #include "xparameters_ml403.h"
24 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
25 XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
26 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
27 XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
28#else
29 /* Add other board xparameter includes here before the #else */
30 #error No xparameters_*.h file included
31#endif
32
33#ifndef SERIAL_PORT_DFNS
34 /* zImage serial port definitions */
35 #define RS_TABLE_SIZE 1
36 #define SERIAL_PORT_DFNS { \
37 .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \
38 .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \
39 .flags = ASYNC_BOOT_AUTOCONF, \
40 .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \
41 .iomem_reg_shift = 2, \
42 .io_type = SERIAL_IO_MEM, \
43 },
44#endif
45
46/*
47 * A few reasonable defaults for the #defines which could be missing depending
48 * on the IP version or variant (e.g. OPB vs PLB)
49 */
50
51#ifndef XPAR_EMAC_0_CAM_EXIST
52#define XPAR_EMAC_0_CAM_EXIST 0
53#endif
54#ifndef XPAR_EMAC_0_JUMBO_EXIST
55#define XPAR_EMAC_0_JUMBO_EXIST 0
56#endif
57#ifndef XPAR_EMAC_0_TX_DRE_TYPE
58#define XPAR_EMAC_0_TX_DRE_TYPE 0
59#endif
60#ifndef XPAR_EMAC_0_RX_DRE_TYPE
61#define XPAR_EMAC_0_RX_DRE_TYPE 0
62#endif
63#ifndef XPAR_EMAC_0_TX_INCLUDE_CSUM
64#define XPAR_EMAC_0_TX_INCLUDE_CSUM 0
65#endif
66#ifndef XPAR_EMAC_0_RX_INCLUDE_CSUM
67#define XPAR_EMAC_0_RX_INCLUDE_CSUM 0
68#endif
69
70#ifndef XPAR_EMAC_1_CAM_EXIST
71#define XPAR_EMAC_1_CAM_EXIST 0
72#endif
73#ifndef XPAR_EMAC_1_JUMBO_EXIST
74#define XPAR_EMAC_1_JUMBO_EXIST 0
75#endif
76#ifndef XPAR_EMAC_1_TX_DRE_TYPE
77#define XPAR_EMAC_1_TX_DRE_TYPE 0
78#endif
79#ifndef XPAR_EMAC_1_RX_DRE_TYPE
80#define XPAR_EMAC_1_RX_DRE_TYPE 0
81#endif
82#ifndef XPAR_EMAC_1_TX_INCLUDE_CSUM
83#define XPAR_EMAC_1_TX_INCLUDE_CSUM 0
84#endif
85#ifndef XPAR_EMAC_1_RX_INCLUDE_CSUM
86#define XPAR_EMAC_1_RX_INCLUDE_CSUM 0
87#endif
88
89#ifndef XPAR_GPIO_0_IS_DUAL
90#define XPAR_GPIO_0_IS_DUAL 0
91#endif
92#ifndef XPAR_GPIO_1_IS_DUAL
93#define XPAR_GPIO_1_IS_DUAL 0
94#endif
95#ifndef XPAR_GPIO_2_IS_DUAL
96#define XPAR_GPIO_2_IS_DUAL 0
97#endif
98#ifndef XPAR_GPIO_3_IS_DUAL
99#define XPAR_GPIO_3_IS_DUAL 0
100#endif
101#ifndef XPAR_GPIO_4_IS_DUAL
102#define XPAR_GPIO_4_IS_DUAL 0
103#endif
104
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
deleted file mode 100644
index 97e3f4d4bd54..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
+++ /dev/null
@@ -1,310 +0,0 @@
1/*******************************************************************
2*
3* Author: Xilinx, Inc.
4*
5*
6* This program is free software; you can redistribute it and/or modify it
7* under the terms of the GNU General Public License as published by the
8* Free Software Foundation; either version 2 of the License, or (at your
9* option) any later version.
10*
11*
12* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
13* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
14* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
15* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
16* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
17* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
18* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
19* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
20* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
21* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
22* FITNESS FOR A PARTICULAR PURPOSE.
23*
24*
25* Xilinx hardware products are not intended for use in life support
26* appliances, devices, or systems. Use in such applications is
27* expressly prohibited.
28*
29*
30* (c) Copyright 2002-2004 Xilinx Inc.
31* All rights reserved.
32*
33*
34* You should have received a copy of the GNU General Public License along
35* with this program; if not, write to the Free Software Foundation, Inc.,
36* 675 Mass Ave, Cambridge, MA 02139, USA.
37*
38* Description: Driver parameters
39*
40*******************************************************************/
41
42#define XPAR_XPCI_NUM_INSTANCES 1
43#define XPAR_XPCI_CLOCK_HZ 33333333
44#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
45#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
46#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
47#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
48#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
49#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
50#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
51#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
52#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
53#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
54
55/******************************************************************/
56
57#define XPAR_XEMAC_NUM_INSTANCES 1
58#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
59#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
60#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
61#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
62#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
63#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
64
65/******************************************************************/
66
67#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
68#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
69#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
70#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
71#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
72#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
73#define XPAR_XGPIO_NUM_INSTANCES 2
74
75/******************************************************************/
76
77#define XPAR_XIIC_NUM_INSTANCES 1
78#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
79#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
80#define XPAR_OPB_IIC_0_DEVICE_ID 0
81#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
82
83/******************************************************************/
84
85#define XPAR_XUARTNS550_NUM_INSTANCES 2
86#define XPAR_XUARTNS550_CLOCK_HZ 100000000
87#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
88#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
89#define XPAR_OPB_UART16550_0_DEVICE_ID 0
90#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
91#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
92#define XPAR_OPB_UART16550_1_DEVICE_ID 1
93
94/******************************************************************/
95
96#define XPAR_XSPI_NUM_INSTANCES 1
97#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
98#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
99#define XPAR_OPB_SPI_0_DEVICE_ID 0
100#define XPAR_OPB_SPI_0_FIFO_EXIST 1
101#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
102#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
103
104/******************************************************************/
105
106#define XPAR_XPS2_NUM_INSTANCES 2
107#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
108#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
109#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
110#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
111#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
112#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
113
114/******************************************************************/
115
116#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
117#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
118#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
119#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
120
121/******************************************************************/
122
123#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
124#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
125#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
126#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
127#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
128#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
129
130/******************************************************************/
131
132#define XPAR_XINTC_HAS_IPR 1
133#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
134#define XPAR_XINTC_USE_DCR 0
135#define XPAR_XINTC_NUM_INSTANCES 1
136#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
137#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
138#define XPAR_DCR_INTC_0_DEVICE_ID 0
139#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
140
141/******************************************************************/
142
143#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
144#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
145#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
146#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
147#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
148#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
149#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
150#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
151#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
152#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
153#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
154#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
155#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
156#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
157#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
158#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
159#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
160#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
161
162/******************************************************************/
163
164#define XPAR_XTFT_NUM_INSTANCES 1
165#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
166#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
167#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
168
169/******************************************************************/
170
171#define XPAR_XSYSACE_MEM_WIDTH 8
172#define XPAR_XSYSACE_NUM_INSTANCES 1
173#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
174#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
175#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
176#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
177
178/******************************************************************/
179
180#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
181
182/******************************************************************/
183
184/******************************************************************/
185
186/* Linux Redefines */
187
188/******************************************************************/
189
190#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
191#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
192#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
193#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
194#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
195#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
196#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
197#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
198
199/******************************************************************/
200
201#define XPAR_GPIO_0_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_0
202#define XPAR_GPIO_0_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_0
203#define XPAR_GPIO_0_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_0
204#define XPAR_GPIO_1_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_1
205#define XPAR_GPIO_1_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_1
206#define XPAR_GPIO_1_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_1
207
208/******************************************************************/
209
210#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
211#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
212#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
213#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
214
215/******************************************************************/
216
217#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
218#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
219#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
220
221/******************************************************************/
222
223#define XPAR_INTC_0_BASEADDR XPAR_DCR_INTC_0_BASEADDR
224#define XPAR_INTC_0_HIGHADDR XPAR_DCR_INTC_0_HIGHADDR
225#define XPAR_INTC_0_KIND_OF_INTR XPAR_DCR_INTC_0_KIND_OF_INTR
226#define XPAR_INTC_0_DEVICE_ID XPAR_DCR_INTC_0_DEVICE_ID
227
228/******************************************************************/
229
230#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
231#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
232#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
233#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
234#define XPAR_INTC_0_UARTNS550_1_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR
235#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
236#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
237#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR
238#define XPAR_INTC_0_TOUCHSCREEN_0_VEC_ID XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR
239#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
240#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
241#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
242#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
243
244/******************************************************************/
245
246#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
247#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
248#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
249#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
250#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
251#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
252
253/******************************************************************/
254
255#define XPAR_SPI_0_BASEADDR XPAR_OPB_SPI_0_BASEADDR
256#define XPAR_SPI_0_HIGHADDR XPAR_OPB_SPI_0_HIGHADDR
257#define XPAR_SPI_0_DEVICE_ID XPAR_OPB_SPI_0_DEVICE_ID
258
259/******************************************************************/
260
261#define XPAR_TOUCHSCREEN_0_BASEADDR XPAR_OPB_TSD_REF_0_BASEADDR
262#define XPAR_TOUCHSCREEN_0_HIGHADDR XPAR_OPB_TSD_REF_0_HIGHADDR
263#define XPAR_TOUCHSCREEN_0_DEVICE_ID XPAR_OPB_TSD_REF_0_DEVICE_ID
264
265/******************************************************************/
266
267#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
268
269/******************************************************************/
270
271#define XPAR_PCI_0_BASEADDR XPAR_OPB_PCI_REF_0_BASEADDR
272#define XPAR_PCI_0_HIGHADDR XPAR_OPB_PCI_REF_0_HIGHADDR
273#define XPAR_PCI_0_CONFIG_ADDR XPAR_OPB_PCI_REF_0_CONFIG_ADDR
274#define XPAR_PCI_0_CONFIG_DATA XPAR_OPB_PCI_REF_0_CONFIG_DATA
275#define XPAR_PCI_0_LCONFIG_ADDR XPAR_OPB_PCI_REF_0_LCONFIG_ADDR
276#define XPAR_PCI_0_MEM_BASEADDR XPAR_OPB_PCI_REF_0_MEM_BASEADDR
277#define XPAR_PCI_0_MEM_HIGHADDR XPAR_OPB_PCI_REF_0_MEM_HIGHADDR
278#define XPAR_PCI_0_IO_BASEADDR XPAR_OPB_PCI_REF_0_IO_BASEADDR
279#define XPAR_PCI_0_IO_HIGHADDR XPAR_OPB_PCI_REF_0_IO_HIGHADDR
280#define XPAR_PCI_0_CLOCK_FREQ_HZ XPAR_XPCI_CLOCK_HZ
281#define XPAR_PCI_0_DEVICE_ID XPAR_OPB_PCI_REF_0_DEVICE_ID
282
283/******************************************************************/
284
285#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
286#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
287#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
288#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
289#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
290#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
291
292/******************************************************************/
293
294#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
295#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
296#define XPAR_DDR_0_SIZE 0x08000000
297
298/******************************************************************/
299
300#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
301#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
302#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
303
304/******************************************************************/
305
306#define XPAR_POWER_0_POWERDOWN_BASEADDR 0x90000004
307#define XPAR_POWER_0_POWERDOWN_HIGHADDR 0x90000007
308#define XPAR_POWER_0_POWERDOWN_VALUE 0xFF
309
310/******************************************************************/
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
deleted file mode 100644
index 5cacdcb3964d..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
+++ /dev/null
@@ -1,243 +0,0 @@
1
2/*******************************************************************
3*
4* CAUTION: This file is automatically generated by libgen.
5* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
6* DO NOT EDIT.
7*
8* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
9*
10* Description: Driver parameters
11*
12*******************************************************************/
13
14#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
15#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
16
17/******************************************************************/
18
19#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000
20#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF
21#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000
22#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF
23#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
24#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
25#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000
26#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF
27#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000
28#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF
29
30/******************************************************************/
31
32#define XPAR_XEMAC_NUM_INSTANCES 1
33#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
34#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
35#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
36#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
37#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
38#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
39
40/******************************************************************/
41
42#define XPAR_XUARTNS550_NUM_INSTANCES 1
43#define XPAR_XUARTNS550_CLOCK_HZ 100000000
44#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
45#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
46#define XPAR_OPB_UART16550_0_DEVICE_ID 0
47
48/******************************************************************/
49
50#define XPAR_XGPIO_NUM_INSTANCES 3
51#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000
52#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF
53#define XPAR_OPB_GPIO_0_DEVICE_ID 0
54#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0
55#define XPAR_OPB_GPIO_0_IS_DUAL 1
56#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000
57#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF
58#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1
59#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0
60#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1
61#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000
62#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF
63#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2
64#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0
65#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0
66
67/******************************************************************/
68
69#define XPAR_XPS2_NUM_INSTANCES 2
70#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
71#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
72#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
73#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
74#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
75#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
76
77/******************************************************************/
78
79#define XPAR_XIIC_NUM_INSTANCES 1
80#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
81#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
82#define XPAR_OPB_IIC_0_DEVICE_ID 0
83#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
84#define XPAR_OPB_IIC_0_GPO_WIDTH 1
85
86/******************************************************************/
87
88#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10
89#define XPAR_XINTC_HAS_IPR 1
90#define XPAR_XINTC_USE_DCR 0
91#define XPAR_XINTC_NUM_INSTANCES 1
92#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0
93#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF
94#define XPAR_OPB_INTC_0_DEVICE_ID 0
95#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
96
97/******************************************************************/
98
99#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0
100#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF
101#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
102#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001
103#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0
104#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002
105#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1
106#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004
107#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2
108#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008
109#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3
110#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010
111#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4
112#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020
113#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5
114#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040
115#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6
116#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080
117#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7
118#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100
119#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
120#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200
121#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9
122
123/******************************************************************/
124
125#define XPAR_XTFT_NUM_INSTANCES 1
126#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
127#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
128#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
129
130/******************************************************************/
131
132#define XPAR_XSYSACE_MEM_WIDTH 16
133#define XPAR_XSYSACE_NUM_INSTANCES 1
134#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
135#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
136#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
137#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16
138
139/******************************************************************/
140
141#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
142
143/******************************************************************/
144
145
146/******************************************************************/
147
148/* Linux Redefines */
149
150/******************************************************************/
151
152#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
153#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
154#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
155#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
156
157/******************************************************************/
158
159#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
160#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
161#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
162#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
163
164/******************************************************************/
165
166#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
167#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
168#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
169#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
170#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
171#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
172
173/******************************************************************/
174
175#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
176
177/******************************************************************/
178
179#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
180#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
181#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
182#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
183#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
184#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
185
186/******************************************************************/
187
188#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0
189#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0
190#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0
191#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1
192#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1
193#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1
194#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0
195#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0
196#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0
197#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1
198#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1
199#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1
200#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR
201#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR
202#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID
203
204/******************************************************************/
205
206#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
207#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
208#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
209#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
210#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
211#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
212
213/******************************************************************/
214
215#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
216#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
217#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
218
219/******************************************************************/
220
221#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
222#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
223#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
224#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
225
226/******************************************************************/
227
228#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
229#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
230#define XPAR_DDR_0_SIZE 0x4000000
231
232/******************************************************************/
233
234#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
235#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
236#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
237
238/******************************************************************/
239
240#define XPAR_PCI_0_CLOCK_FREQ_HZ 0
241
242/******************************************************************/
243
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
deleted file mode 100644
index f6cfd44281fc..000000000000
--- a/arch/ppc/platforms/4xx/yucca.c
+++ /dev/null
@@ -1,393 +0,0 @@
1/*
2 * Yucca board specific routines
3 *
4 * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
5 *
6 * Copyright 2004-2005 MontaVista Software Inc.
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/stddef.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/reboot.h>
20#include <linux/pci.h>
21#include <linux/kdev_t.h>
22#include <linux/types.h>
23#include <linux/major.h>
24#include <linux/blkdev.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/initrd.h>
28#include <linux/seq_file.h>
29#include <linux/root_dev.h>
30#include <linux/tty.h>
31#include <linux/serial.h>
32#include <linux/serial_core.h>
33#include <linux/serial_8250.h>
34
35#include <asm/system.h>
36#include <asm/pgtable.h>
37#include <asm/page.h>
38#include <asm/dma.h>
39#include <asm/io.h>
40#include <asm/machdep.h>
41#include <asm/ocp.h>
42#include <asm/pci-bridge.h>
43#include <asm/time.h>
44#include <asm/todc.h>
45#include <asm/bootinfo.h>
46#include <asm/ppc4xx_pic.h>
47#include <asm/ppcboot.h>
48
49#include <syslib/ibm44x_common.h>
50#include <syslib/ibm440gx_common.h>
51#include <syslib/ibm440sp_common.h>
52#include <syslib/ppc440spe_pcie.h>
53
54extern bd_t __res;
55
56static struct ibm44x_clocks clocks __initdata;
57
58static void __init
59yucca_calibrate_decr(void)
60{
61 unsigned int freq;
62
63 if (mfspr(SPRN_CCR1) & CCR1_TCS)
64 freq = YUCCA_TMR_CLK;
65 else
66 freq = clocks.cpu;
67
68 ibm44x_calibrate_decr(freq);
69}
70
71static int
72yucca_show_cpuinfo(struct seq_file *m)
73{
74 seq_printf(m, "vendor\t\t: AMCC\n");
75 seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
76
77 return 0;
78}
79
80static enum {
81 HOSE_UNKNOWN,
82 HOSE_PCIX,
83 HOSE_PCIE0,
84 HOSE_PCIE1,
85 HOSE_PCIE2
86} hose_type[4];
87
88static inline int
89yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
90{
91 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
92
93 if (hose_type[hose->index] == HOSE_PCIX) {
94 static char pci_irq_table[][4] =
95 /*
96 * PCI IDSEL/INTPIN->INTLINE
97 * A B C D
98 */
99 {
100 { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */
101 };
102 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
103 return PCI_IRQ_TABLE_LOOKUP;
104 } else if (hose_type[hose->index] == HOSE_PCIE0) {
105 static char pci_irq_table[][4] =
106 /*
107 * PCI IDSEL/INTPIN->INTLINE
108 * A B C D
109 */
110 {
111 { 96, 97, 98, 99 },
112 };
113 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
114 return PCI_IRQ_TABLE_LOOKUP;
115 } else if (hose_type[hose->index] == HOSE_PCIE1) {
116 static char pci_irq_table[][4] =
117 /*
118 * PCI IDSEL/INTPIN->INTLINE
119 * A B C D
120 */
121 {
122 { 100, 101, 102, 103 },
123 };
124 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
125 return PCI_IRQ_TABLE_LOOKUP;
126 } else if (hose_type[hose->index] == HOSE_PCIE2) {
127 static char pci_irq_table[][4] =
128 /*
129 * PCI IDSEL/INTPIN->INTLINE
130 * A B C D
131 */
132 {
133 { 104, 105, 106, 107 },
134 };
135 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
136 return PCI_IRQ_TABLE_LOOKUP;
137 }
138 return -1;
139}
140
141static void __init yucca_set_emacdata(void)
142{
143 struct ocp_def *def;
144 struct ocp_func_emac_data *emacdata;
145
146 /* Set phy_map, phy_mode, and mac_addr for the EMAC */
147 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
148 emacdata = def->additions;
149 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
150 emacdata->phy_mode = PHY_MODE_GMII;
151 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
152}
153
154static int __init yucca_pcie_card_present(int port)
155{
156 void __iomem *pcie_fpga_base;
157 u16 reg;
158
159 pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
160 reg = in_be16(pcie_fpga_base + FPGA_REG1C);
161 iounmap(pcie_fpga_base);
162
163 switch(port) {
164 case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
165 case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
166 case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
167 default: return 0;
168 }
169}
170
171/*
172 * For the given slot, set rootpoint mode, send power to the slot,
173 * turn on the green LED and turn off the yellow LED, enable the clock
174 * and turn off reset.
175 */
176static void __init yucca_setup_pcie_fpga_rootpoint(int port)
177{
178 void __iomem *pcie_reg_fpga_base;
179 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
180
181 pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
182
183 switch(port) {
184 case 0:
185 rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
186 endpoint = 0;
187 power = FPGA_REG1A_PE0_PWRON;
188 green_led = FPGA_REG1A_PE0_GLED;
189 clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
190 yellow_led = FPGA_REG1A_PE0_YLED;
191 reset_off = FPGA_REG1C_PE0_PERST;
192 break;
193 case 1:
194 rootpoint = 0;
195 endpoint = FPGA_REG1C_PE1_ENDPOINT;
196 power = FPGA_REG1A_PE1_PWRON;
197 green_led = FPGA_REG1A_PE1_GLED;
198 clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
199 yellow_led = FPGA_REG1A_PE1_YLED;
200 reset_off = FPGA_REG1C_PE1_PERST;
201 break;
202 case 2:
203 rootpoint = 0;
204 endpoint = FPGA_REG1C_PE2_ENDPOINT;
205 power = FPGA_REG1A_PE2_PWRON;
206 green_led = FPGA_REG1A_PE2_GLED;
207 clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
208 yellow_led = FPGA_REG1A_PE2_YLED;
209 reset_off = FPGA_REG1C_PE2_PERST;
210 break;
211
212 default:
213 iounmap(pcie_reg_fpga_base);
214 return;
215 }
216
217 out_be16(pcie_reg_fpga_base + FPGA_REG1A,
218 ~(power | clock | green_led) &
219 (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
220 out_be16(pcie_reg_fpga_base + FPGA_REG1C,
221 ~(endpoint | reset_off) &
222 (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
223
224 /*
225 * Leave device in reset for a while after powering on the
226 * slot to give it a chance to initialize.
227 */
228 mdelay(250);
229
230 out_be16(pcie_reg_fpga_base + FPGA_REG1C,
231 reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
232
233 iounmap(pcie_reg_fpga_base);
234}
235
236static void __init
237yucca_setup_hoses(void)
238{
239 struct pci_controller *hose;
240 char name[20];
241 int i;
242
243 if (0 && ppc440spe_init_pcie()) {
244 printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
245 return;
246 }
247
248 for (i = 0; i <= 2; ++i) {
249 if (!yucca_pcie_card_present(i))
250 continue;
251
252 printk(KERN_INFO "PCIE%d: card present\n", i);
253 yucca_setup_pcie_fpga_rootpoint(i);
254 if (ppc440spe_init_pcie_rootport(i)) {
255 printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
256 continue;
257 }
258
259 hose = pcibios_alloc_controller();
260 if (!hose)
261 return;
262
263 sprintf(name, "PCIE%d host bridge", i);
264 pci_init_resource(&hose->io_resource,
265 YUCCA_PCIX_LOWER_IO,
266 YUCCA_PCIX_UPPER_IO,
267 IORESOURCE_IO,
268 name);
269
270 hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
271 i * YUCCA_PCIE_MEM_SIZE;
272 hose->mem_space.end = hose->mem_space.start +
273 YUCCA_PCIE_MEM_SIZE - 1;
274
275 pci_init_resource(&hose->mem_resources[0],
276 hose->mem_space.start,
277 hose->mem_space.end,
278 IORESOURCE_MEM,
279 name);
280
281 hose->first_busno = 0;
282 hose->last_busno = 15;
283 hose_type[hose->index] = HOSE_PCIE0 + i;
284
285 ppc440spe_setup_pcie(hose, i);
286 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
287 }
288
289 ppc_md.pci_swizzle = common_swizzle;
290 ppc_md.pci_map_irq = yucca_map_irq;
291}
292
293TODC_ALLOC();
294
295static void __init
296yucca_early_serial_map(void)
297{
298 struct uart_port port;
299
300 /* Setup ioremapped serial port access */
301 memset(&port, 0, sizeof(port));
302 port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
303 port.irq = UART0_INT;
304 port.uartclk = clocks.uart0;
305 port.regshift = 0;
306 port.iotype = UPIO_MEM;
307 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
308 port.line = 0;
309
310 if (early_serial_setup(&port) != 0) {
311 printk("Early serial init of port 0 failed\n");
312 }
313
314 port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
315 port.irq = UART1_INT;
316 port.uartclk = clocks.uart1;
317 port.line = 1;
318
319 if (early_serial_setup(&port) != 0) {
320 printk("Early serial init of port 1 failed\n");
321 }
322
323 port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
324 port.irq = UART2_INT;
325 port.uartclk = BASE_BAUD;
326 port.line = 2;
327
328 if (early_serial_setup(&port) != 0) {
329 printk("Early serial init of port 2 failed\n");
330 }
331}
332
333static void __init
334yucca_setup_arch(void)
335{
336 yucca_set_emacdata();
337
338#if !defined(CONFIG_BDI_SWITCH)
339 /*
340 * The Abatron BDI JTAG debugger does not tolerate others
341 * mucking with the debug registers.
342 */
343 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
344#endif
345
346 /*
347 * Determine various clocks.
348 * To be completely correct we should get SysClk
349 * from FPGA, because it can be changed by on-board switches
350 * --ebs
351 */
352 /* 440GX and 440SPe clocking is the same - rd */
353 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
354 ocp_sys_info.opb_bus_freq = clocks.opb;
355
356 /* init to some ~sane value until calibrate_delay() runs */
357 loops_per_jiffy = 50000000/HZ;
358
359 /* Setup PCIXn host bridges */
360 yucca_setup_hoses();
361
362#ifdef CONFIG_BLK_DEV_INITRD
363 if (initrd_start)
364 ROOT_DEV = Root_RAM0;
365 else
366#endif
367#ifdef CONFIG_ROOT_NFS
368 ROOT_DEV = Root_NFS;
369#else
370 ROOT_DEV = Root_HDA1;
371#endif
372
373 yucca_early_serial_map();
374
375 /* Identify the system */
376 printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
377}
378
379void __init platform_init(unsigned long r3, unsigned long r4,
380 unsigned long r5, unsigned long r6, unsigned long r7)
381{
382 ibm44x_platform_init(r3, r4, r5, r6, r7);
383
384 ppc_md.setup_arch = yucca_setup_arch;
385 ppc_md.show_cpuinfo = yucca_show_cpuinfo;
386 ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
387 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
388
389 ppc_md.calibrate_decr = yucca_calibrate_decr;
390#ifdef CONFIG_KGDB
391 ppc_md.early_serial_map = yucca_early_serial_map;
392#endif
393}
diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h
deleted file mode 100644
index bc9684e66a84..000000000000
--- a/arch/ppc/platforms/4xx/yucca.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * Yucca board definitions
3 *
4 * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
5 *
6 * Copyright 2004-2005 MontaVista Software Inc.
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_YUCCA_H__
18#define __ASM_YUCCA_H__
19
20#include <platforms/4xx/ppc440spe.h>
21
22/* F/W TLB mapping used in bootloader glue to reset EMAC */
23#define PPC44x_EMAC0_MR0 0xa0000800
24
25/* Location of MAC addresses in PIBS image */
26#define PIBS_FLASH_BASE 0xffe00000
27#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
28
29/* External timer clock frequency */
30#define YUCCA_TMR_CLK 25000000
31
32/*
33 * FPGA registers
34 */
35#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL
36#define YUCCA_FPGA_REG_SIZE 0x24
37
38#define FPGA_REG1A 0x1a
39
40#define FPGA_REG1A_PE0_GLED 0x8000
41#define FPGA_REG1A_PE1_GLED 0x4000
42#define FPGA_REG1A_PE2_GLED 0x2000
43#define FPGA_REG1A_PE0_YLED 0x1000
44#define FPGA_REG1A_PE1_YLED 0x0800
45#define FPGA_REG1A_PE2_YLED 0x0400
46#define FPGA_REG1A_PE0_PWRON 0x0200
47#define FPGA_REG1A_PE1_PWRON 0x0100
48#define FPGA_REG1A_PE2_PWRON 0x0080
49#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
50#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
51#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
52#define FPGA_REG1A_PE_SPREAD0 0x0008
53#define FPGA_REG1A_PE_SPREAD1 0x0004
54#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
55#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
56
57#define FPGA_REG1C 0x1c
58
59#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
60#define FPGA_REG1C_PE1_ENDPOINT 0x4000
61#define FPGA_REG1C_PE2_ENDPOINT 0x2000
62#define FPGA_REG1C_PE0_PRSNT 0x1000
63#define FPGA_REG1C_PE1_PRSNT 0x0800
64#define FPGA_REG1C_PE2_PRSNT 0x0400
65#define FPGA_REG1C_PE0_WAKE 0x0080
66#define FPGA_REG1C_PE1_WAKE 0x0040
67#define FPGA_REG1C_PE2_WAKE 0x0020
68#define FPGA_REG1C_PE0_PERST 0x0010
69#define FPGA_REG1C_PE1_PERST 0x0008
70#define FPGA_REG1C_PE2_PERST 0x0004
71
72/*
73 * Serial port defines
74 */
75#define RS_TABLE_SIZE 3
76
77/* PIBS defined UART mappings, used before early_serial_setup */
78#define UART0_IO_BASE 0xa0000200
79#define UART1_IO_BASE 0xa0000300
80#define UART2_IO_BASE 0xa0000600
81
82#define BASE_BAUD 11059200
83#define STD_UART_OP(num) \
84 { 0, BASE_BAUD, 0, UART##num##_INT, \
85 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
86 iomem_base: (void*)UART##num##_IO_BASE, \
87 io_type: SERIAL_IO_MEM},
88
89#define SERIAL_PORT_DFNS \
90 STD_UART_OP(0) \
91 STD_UART_OP(1) \
92 STD_UART_OP(2)
93
94/* PCI support */
95#define YUCCA_PCIX_LOWER_IO 0x00000000
96#define YUCCA_PCIX_UPPER_IO 0x0000ffff
97#define YUCCA_PCIX_LOWER_MEM 0x80000000
98#define YUCCA_PCIX_UPPER_MEM 0x8fffffff
99#define YUCCA_PCIE_LOWER_MEM 0x90000000
100#define YUCCA_PCIE_MEM_SIZE 0x10000000
101
102#define YUCCA_PCIX_MEM_SIZE 0x10000000
103#define YUCCA_PCIX_MEM_OFFSET 0x00000000
104#define YUCCA_PCIE_MEM_SIZE 0x10000000
105#define YUCCA_PCIE_MEM_OFFSET 0x00000000
106
107#endif /* __ASM_YUCCA_H__ */
108#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
deleted file mode 100644
index 6260231987cb..000000000000
--- a/arch/ppc/platforms/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
6obj-$(CONFIG_PREP_RESIDUAL) += residual.o
7obj-$(CONFIG_TQM8260) += tqm8260_setup.o
8obj-$(CONFIG_CPCI690) += cpci690.o
9obj-$(CONFIG_EV64260) += ev64260.o
10obj-$(CONFIG_CHESTNUT) += chestnut.o
11obj-$(CONFIG_LOPEC) += lopec.o
12obj-$(CONFIG_KATANA) += katana.o
13obj-$(CONFIG_HDPU) += hdpu.o
14obj-$(CONFIG_MVME5100) += mvme5100.o
15obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o
16obj-$(CONFIG_POWERPMC250) += powerpmc250.o
17obj-$(CONFIG_PPLUS) += pplus.o
18obj-$(CONFIG_PRPMC750) += prpmc750.o
19obj-$(CONFIG_PRPMC800) += prpmc800.o
20obj-$(CONFIG_RADSTONE_PPC7D) += radstone_ppc7d.o
21obj-$(CONFIG_SANDPOINT) += sandpoint.o
22obj-$(CONFIG_SBC82xx) += sbc82xx.o
23obj-$(CONFIG_SPRUCE) += spruce.o
24obj-$(CONFIG_LITE5200) += lite5200.o
25obj-$(CONFIG_EV64360) += ev64360.o
diff --git a/arch/ppc/platforms/bseip.h b/arch/ppc/platforms/bseip.h
deleted file mode 100644
index 691f4a52b0a5..000000000000
--- a/arch/ppc/platforms/bseip.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the Bright Star Engineering ip-Engine board. Copied from the MBX stuff.
4 *
5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
6 */
7#ifndef __MACH_BSEIP_DEFS
8#define __MACH_BSEIP_DEFS
9
10#ifndef __ASSEMBLY__
11/* A Board Information structure that is given to a program when
12 * prom starts it up.
13 */
14typedef struct bd_info {
15 unsigned int bi_memstart; /* Memory start address */
16 unsigned int bi_memsize; /* Memory (end) size in bytes */
17 unsigned int bi_intfreq; /* Internal Freq, in Hz */
18 unsigned int bi_busfreq; /* Bus Freq, in Hz */
19 unsigned char bi_enetaddr[6];
20 unsigned int bi_baudrate;
21} bd_t;
22
23extern bd_t m8xx_board_info;
24
25/* Memory map is configured by the PROM startup.
26 * All we need to get started is the IMMR.
27 */
28#define IMAP_ADDR ((uint)0xff000000)
29#define IMAP_SIZE ((uint)(64 * 1024))
30#define PCMCIA_MEM_ADDR ((uint)0x04000000)
31#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
32#endif /* !__ASSEMBLY__ */
33
34/* We don't use the 8259.
35*/
36#define NR_8259_INTS 0
37
38#endif
diff --git a/arch/ppc/platforms/ccm.h b/arch/ppc/platforms/ccm.h
deleted file mode 100644
index 69000b1c7a4c..000000000000
--- a/arch/ppc/platforms/ccm.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Siemens Card Controller Module specific definitions
3 *
4 * Copyright (C) 2001-2002 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifndef __MACH_CCM_H
8#define __MACH_CCM_H
9
10
11#include <asm/ppcboot.h>
12
13#define CCM_IMMR_BASE 0xF0000000 /* phys. addr of IMMR */
14#define CCM_IMAP_SIZE (64 * 1024) /* size of mapped area */
15
16#define IMAP_ADDR CCM_IMMR_BASE /* physical base address of IMMR area */
17#define IMAP_SIZE CCM_IMAP_SIZE /* mapped size of IMMR area */
18
19#define FEC_INTERRUPT 13 /* = SIU_LEVEL6 */
20#define DEC_INTERRUPT 11 /* = SIU_LEVEL5 */
21#define CPM_INTERRUPT 9 /* = SIU_LEVEL4 */
22
23/* We don't use the 8259.
24*/
25#define NR_8259_INTS 0
26
27#endif /* __MACH_CCM_H */
diff --git a/arch/ppc/platforms/chestnut.c b/arch/ppc/platforms/chestnut.c
deleted file mode 100644
index 27c140f218ed..000000000000
--- a/arch/ppc/platforms/chestnut.c
+++ /dev/null
@@ -1,574 +0,0 @@
1/*
2 * Board setup routines for IBM Chestnut
3 *
4 * Author: <source@mvista.com>
5 *
6 * <2004> (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/kdev_t.h>
18#include <linux/major.h>
19#include <linux/blkdev.h>
20#include <linux/console.h>
21#include <linux/root_dev.h>
22#include <linux/initrd.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/serial.h>
26#include <linux/serial_core.h>
27#include <linux/serial_8250.h>
28#include <linux/mtd/physmap.h>
29#include <asm/system.h>
30#include <asm/pgtable.h>
31#include <asm/page.h>
32#include <asm/time.h>
33#include <asm/dma.h>
34#include <asm/io.h>
35#include <asm/hw_irq.h>
36#include <asm/machdep.h>
37#include <asm/kgdb.h>
38#include <asm/bootinfo.h>
39#include <asm/mv64x60.h>
40#include <platforms/chestnut.h>
41
42static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
43static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
44
45static mv64x60_handle_t bh;
46
47extern void gen550_progress(char *, unsigned short);
48extern void gen550_init(int, struct uart_port *);
49extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
50
51#define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
52 BIT(MV64x60_CPU2DEV_1_WIN) | \
53 BIT(MV64x60_CPU2DEV_2_WIN) | \
54 BIT(MV64x60_CPU2DEV_3_WIN) | \
55 BIT(MV64x60_CPU2BOOT_WIN))
56/**************************************************************************
57 * FUNCTION: chestnut_calibrate_decr
58 *
59 * DESCRIPTION: initialize decrementer interrupt frequency (used as system
60 * timer)
61 *
62 ****/
63static void __init
64chestnut_calibrate_decr(void)
65{
66 ulong freq;
67
68 freq = CHESTNUT_BUS_SPEED / 4;
69
70 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
71 freq/1000000, freq%1000000);
72
73 tb_ticks_per_jiffy = freq / HZ;
74 tb_to_us = mulhwu_scale_factor(freq, 1000000);
75}
76
77static int
78chestnut_show_cpuinfo(struct seq_file *m)
79{
80 seq_printf(m, "vendor\t\t: IBM\n");
81 seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
82
83 return 0;
84}
85
86/**************************************************************************
87 * FUNCTION: chestnut_find_end_of_memory
88 *
89 * DESCRIPTION: ppc_md memory size callback
90 *
91 ****/
92unsigned long __init
93chestnut_find_end_of_memory(void)
94{
95 static int mem_size = 0;
96
97 if (mem_size == 0) {
98 mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
99 MV64x60_TYPE_MV64460);
100 }
101 return mem_size;
102}
103
104#if defined(CONFIG_SERIAL_8250)
105static void __init
106chestnut_early_serial_map(void)
107{
108 struct uart_port port;
109
110 /* Setup serial port access */
111 memset(&port, 0, sizeof(port));
112 port.uartclk = BASE_BAUD * 16;
113 port.irq = UART0_INT;
114 port.flags = STD_COM_FLAGS | UPF_IOREMAP;
115 port.iotype = UPIO_MEM;
116 port.mapbase = CHESTNUT_UART0_IO_BASE;
117 port.regshift = 0;
118
119 if (early_serial_setup(&port) != 0)
120 printk("Early serial init of port 0 failed\n");
121
122 /* Assume early_serial_setup() doesn't modify serial_req */
123 port.line = 1;
124 port.irq = UART1_INT;
125 port.mapbase = CHESTNUT_UART1_IO_BASE;
126
127 if (early_serial_setup(&port) != 0)
128 printk("Early serial init of port 1 failed\n");
129}
130#endif
131
132/**************************************************************************
133 * FUNCTION: chestnut_map_irq
134 *
135 * DESCRIPTION: 0 return since PCI IRQs not needed
136 *
137 ****/
138static int __init
139chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
140{
141 static char pci_irq_table[][4] = {
142 {CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
143 CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
144 {CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
145 CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
146 {CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
147 CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
148 {CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
149 CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
150 };
151 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
152
153 return PCI_IRQ_TABLE_LOOKUP;
154}
155
156
157/**************************************************************************
158 * FUNCTION: chestnut_setup_bridge
159 *
160 * DESCRIPTION: initalize board-specific settings on the MV64360
161 *
162 ****/
163static void __init
164chestnut_setup_bridge(void)
165{
166 struct mv64x60_setup_info si;
167 int i;
168
169 if ( ppc_md.progress )
170 ppc_md.progress("chestnut_setup_bridge: enter", 0);
171
172 memset(&si, 0, sizeof(si));
173
174 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
175
176 /* setup only PCI bus 0 (bus 1 not used) */
177 si.pci_0.enable_bus = 1;
178 si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
179 si.pci_0.pci_io.pci_base_hi = 0;
180 si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
181 si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
182 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
183 si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
184 si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
185 si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
186 si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
187 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
188 si.pci_0.pci_cmd_bits = 0;
189 si.pci_0.latency_timer = 0x80;
190
191 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
192#if defined(CONFIG_NOT_COHERENT_CACHE)
193 si.cpu_prot_options[i] = 0;
194 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
195 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
196 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
197
198 si.pci_1.acc_cntl_options[i] =
199 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
200 MV64360_PCI_ACC_CNTL_SWAP_NONE |
201 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
202 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
203#else
204 si.cpu_prot_options[i] = 0;
205 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
206 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
207 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
208
209 si.pci_1.acc_cntl_options[i] =
210 MV64360_PCI_ACC_CNTL_SNOOP_WB |
211 MV64360_PCI_ACC_CNTL_SWAP_NONE |
212 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
213 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
214#endif
215 }
216
217 /* Lookup host bridge - on CPU 0 - no SMP support */
218 if (mv64x60_init(&bh, &si)) {
219 printk("\n\nPCI Bridge initialization failed!\n");
220 }
221
222 pci_dram_offset = 0;
223 ppc_md.pci_swizzle = common_swizzle;
224 ppc_md.pci_map_irq = chestnut_map_irq;
225 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
226
227 mv64x60_set_bus(&bh, 0, 0);
228 bh.hose_a->first_busno = 0;
229 bh.hose_a->last_busno = 0xff;
230 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
231}
232
233void __init
234chestnut_setup_peripherals(void)
235{
236 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
237 CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
238 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
239
240 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
241 CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
242 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
243
244 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
245 CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
246 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
247 cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
248
249 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
250 CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
251 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
252
253 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
254 CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
255 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
256
257 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
258 CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
259 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
260
261#ifdef CONFIG_NOT_COHERENT_CACHE
262 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
263#else
264 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
265#endif
266 sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
267 memset(sram_base, 0, MV64360_SRAM_SIZE);
268
269 /*
270 * Configure MPP pins for PCI DMA
271 *
272 * PCI Slot GNT pin REQ pin
273 * 0 MPP16 MPP17
274 * 1 MPP18 MPP19
275 * 2 MPP20 MPP21
276 * 3 MPP22 MPP23
277 */
278 mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
279 (0x1 << 0) | /* MPPSel16 PCI0_GNT[0] */
280 (0x1 << 4) | /* MPPSel17 PCI0_REQ[0] */
281 (0x1 << 8) | /* MPPSel18 PCI0_GNT[1] */
282 (0x1 << 12) | /* MPPSel19 PCI0_REQ[1] */
283 (0x1 << 16) | /* MPPSel20 PCI0_GNT[2] */
284 (0x1 << 20) | /* MPPSel21 PCI0_REQ[2] */
285 (0x1 << 24) | /* MPPSel22 PCI0_GNT[3] */
286 (0x1 << 28)); /* MPPSel23 PCI0_REQ[3] */
287 /*
288 * Set unused MPP pins for output, as per schematic note
289 *
290 * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
291 * MPP09, MPP10, MPP13, MPP14, MPP15
292 */
293 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
294 (0xf << 4) | /* MPPSel01 GPIO[1] */
295 (0xf << 8) | /* MPPSel02 GPIO[2] */
296 (0xf << 16) | /* MPPSel04 GPIO[4] */
297 (0xf << 20) | /* MPPSel05 GPIO[5] */
298 (0xf << 24)); /* MPPSel06 GPIO[6] */
299 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
300 (0xf << 4) | /* MPPSel09 GPIO[9] */
301 (0xf << 8) | /* MPPSel10 GPIO[10] */
302 (0xf << 20) | /* MPPSel13 GPIO[13] */
303 (0xf << 24) | /* MPPSel14 GPIO[14] */
304 (0xf << 28)); /* MPPSel15 GPIO[15] */
305 mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
306 BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) |
307 BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15));
308
309 /*
310 * Configure the following MPP pins to indicate a level
311 * triggered interrupt
312 *
313 * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
314 * MPP25 - UART A (high)
315 * MPP26 - UART B (high)
316 * MPP28 - PCI Slot 3 (low)
317 * MPP29 - PCI Slot 2 (low)
318 * MPP30 - PCI Slot 1 (low)
319 * MPP31 - PCI Slot 0 (low)
320 */
321 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
322 BIT(3) | BIT(2) | BIT(1) | BIT(0) | /* MPP 24 */
323 BIT(7) | BIT(6) | BIT(5) | BIT(4) | /* MPP 25 */
324 BIT(11) | BIT(10) | BIT(9) | BIT(8) | /* MPP 26 */
325 BIT(19) | BIT(18) | BIT(17) | BIT(16) | /* MPP 28 */
326 BIT(23) | BIT(22) | BIT(21) | BIT(20) | /* MPP 29 */
327 BIT(27) | BIT(26) | BIT(25) | BIT(24) | /* MPP 30 */
328 BIT(31) | BIT(30) | BIT(29) | BIT(28)); /* MPP 31 */
329
330 /*
331 * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
332 * 31 (low) interrupt polarity input signal and level triggered
333 */
334 mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
335 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
336 BIT(28) | BIT(29) | BIT(30) | BIT(31));
337 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
338 BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
339 BIT(31));
340
341 /* Config GPP interrupt controller to respond to level trigger */
342 mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
343
344 /*
345 * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
346 */
347 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
348 ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
349 BIT(31)));
350 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
351 BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
352 BIT(31));
353
354 /*
355 * Dismiss and then enable interrupt on CPU #0 high cause register
356 * BIT27 summarizes GPP interrupts 24-31
357 */
358 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
359
360 if (ppc_md.progress)
361 ppc_md.progress("chestnut_setup_bridge: exit", 0);
362}
363
364/**************************************************************************
365 * FUNCTION: chestnut_setup_arch
366 *
367 * DESCRIPTION: ppc_md machine configuration callback
368 *
369 ****/
370static void __init
371chestnut_setup_arch(void)
372{
373 if (ppc_md.progress)
374 ppc_md.progress("chestnut_setup_arch: enter", 0);
375
376 /* init to some ~sane value until calibrate_delay() runs */
377 loops_per_jiffy = 50000000 / HZ;
378
379 /* if the time base value is greater than bus freq/4 (the TB and
380 * decrementer tick rate) + signed integer rollover value, we
381 * can spend a fair amount of time waiting for the rollover to
382 * happen. To get around this, initialize the time base register
383 * to a "safe" value.
384 */
385 set_tb(0, 0);
386
387#ifdef CONFIG_BLK_DEV_INITRD
388 if (initrd_start)
389 ROOT_DEV = Root_RAM0;
390 else
391#endif
392#ifdef CONFIG_ROOT_NFS
393 ROOT_DEV = Root_NFS;
394#else
395 ROOT_DEV = Root_SDA2;
396#endif
397
398 /*
399 * Set up the L2CR register.
400 */
401 _set_L2CR(_get_L2CR() | L2CR_L2E);
402
403 chestnut_setup_bridge();
404 chestnut_setup_peripherals();
405
406#ifdef CONFIG_DUMMY_CONSOLE
407 conswitchp = &dummy_con;
408#endif
409
410#if defined(CONFIG_SERIAL_8250)
411 chestnut_early_serial_map();
412#endif
413
414 /* Identify the system */
415 printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
416 printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
417 " (source@mvista.com)\n");
418
419 if (ppc_md.progress)
420 ppc_md.progress("chestnut_setup_arch: exit", 0);
421}
422
423#ifdef CONFIG_MTD_PHYSMAP
424static struct mtd_partition ptbl;
425
426static int __init
427chestnut_setup_mtd(void)
428{
429 memset(&ptbl, 0, sizeof(ptbl));
430
431 ptbl.name = "User FS";
432 ptbl.size = CHESTNUT_32BIT_SIZE;
433
434 physmap_map.size = CHESTNUT_32BIT_SIZE;
435 physmap_set_partitions(&ptbl, 1);
436 return 0;
437}
438
439arch_initcall(chestnut_setup_mtd);
440#endif
441
442/**************************************************************************
443 * FUNCTION: chestnut_restart
444 *
445 * DESCRIPTION: ppc_md machine reset callback
446 * reset the board via the CPLD command register
447 *
448 ****/
449static void
450chestnut_restart(char *cmd)
451{
452 volatile ulong i = 10000000;
453
454 local_irq_disable();
455
456 /*
457 * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
458 *
459 * MPP24 - board reset
460 */
461 writeb(0x1, cpld_base + 3);
462
463 /* GPP pin tied to MPP earlier */
464 mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
465
466 while (i-- > 0);
467 panic("restart failed\n");
468}
469
470static void
471chestnut_halt(void)
472{
473 local_irq_disable();
474 for (;;);
475 /* NOTREACHED */
476}
477
478static void
479chestnut_power_off(void)
480{
481 chestnut_halt();
482 /* NOTREACHED */
483}
484
485/**************************************************************************
486 * FUNCTION: chestnut_map_io
487 *
488 * DESCRIPTION: configure fixed memory-mapped IO
489 *
490 ****/
491static void __init
492chestnut_map_io(void)
493{
494#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
495 io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
496 _PAGE_IO);
497#endif
498}
499
500/**************************************************************************
501 * FUNCTION: chestnut_set_bat
502 *
503 * DESCRIPTION: configures a (temporary) bat mapping for early access to
504 * device I/O
505 *
506 ****/
507static __inline__ void
508chestnut_set_bat(void)
509{
510 mb();
511 mtspr(SPRN_DBAT3U, 0xf0001ffe);
512 mtspr(SPRN_DBAT3L, 0xf000002a);
513 mb();
514}
515
516/**************************************************************************
517 * FUNCTION: platform_init
518 *
519 * DESCRIPTION: main entry point for configuring board-specific machine
520 * callbacks
521 *
522 ****/
523void __init
524platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
525 unsigned long r6, unsigned long r7)
526{
527 parse_bootinfo(find_bootinfo());
528
529 /* Copy the kernel command line arguments to a safe place. */
530
531 if (r6) {
532 *(char *) (r7 + KERNELBASE) = 0;
533 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
534 }
535
536 isa_mem_base = 0;
537
538 ppc_md.setup_arch = chestnut_setup_arch;
539 ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
540 ppc_md.init_IRQ = mv64360_init_irq;
541 ppc_md.get_irq = mv64360_get_irq;
542 ppc_md.init = NULL;
543
544 ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
545 ppc_md.setup_io_mappings = chestnut_map_io;
546
547 ppc_md.restart = chestnut_restart;
548 ppc_md.power_off = chestnut_power_off;
549 ppc_md.halt = chestnut_halt;
550
551 ppc_md.time_init = NULL;
552 ppc_md.set_rtc_time = NULL;
553 ppc_md.get_rtc_time = NULL;
554 ppc_md.calibrate_decr = chestnut_calibrate_decr;
555
556 ppc_md.nvram_read_val = NULL;
557 ppc_md.nvram_write_val = NULL;
558
559 ppc_md.heartbeat = NULL;
560
561 bh.p_base = CONFIG_MV64X60_NEW_BASE;
562
563 chestnut_set_bat();
564
565#if defined(CONFIG_SERIAL_TEXT_DEBUG)
566 ppc_md.progress = gen550_progress;
567#endif
568#if defined(CONFIG_KGDB)
569 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
570#endif
571
572 if (ppc_md.progress)
573 ppc_md.progress("chestnut_init(): exit", 0);
574}
diff --git a/arch/ppc/platforms/chestnut.h b/arch/ppc/platforms/chestnut.h
deleted file mode 100644
index e00fd9f8bbd0..000000000000
--- a/arch/ppc/platforms/chestnut.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/*
2 * Definitions for IBM 750FXGX Eval (Chestnut)
3 *
4 * Author: <source@mvista.com>
5 *
6 * Based on Artesyn Katana code done by Tim Montgomery <timm@artesyncp.com>
7 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
8 * Based on code done by Mark A. Greer <mgreer@mvista.com>
9 *
10 * <2004> (c) MontaVista Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16/*
17 * This is the CPU physical memory map (windows must be at least 1MB and start
18 * on a boundary that is a multiple of the window size):
19 *
20 * Seems on the IBM 750FXGX Eval board, the MV64460 Registers can be in
21 * only 2 places per switch U17 0x14000000 or 0xf1000000 easily - chose to
22 * implement at 0xf1000000 only at this time
23 *
24 * 0xfff00000-0xffffffff - 8 Flash
25 * 0xffe00000-0xffefffff - BOOT SRAM
26 * 0xffd00000-0xffd00004 - CPLD
27 * 0xffc00000-0xffc0000f - UART
28 * 0xffb00000-0xffb07fff - FRAM
29 * 0xff840000-0xffafffff - *** HOLE ***
30 * 0xff800000-0xff83ffff - MV64460 Integrated SRAM
31 * 0xfe000000-0xff8fffff - *** HOLE ***
32 * 0xfc000000-0xfdffffff - 32bit Flash
33 * 0xf1010000-0xfbffffff - *** HOLE ***
34 * 0xf1000000-0xf100ffff - MV64460 Registers
35 */
36
37#ifndef __PPC_PLATFORMS_CHESTNUT_H__
38#define __PPC_PLATFORMS_CHESTNUT_H__
39
40#define CHESTNUT_BOOT_8BIT_BASE 0xfff00000
41#define CHESTNUT_BOOT_8BIT_SIZE_ACTUAL (1024*1024)
42#define CHESTNUT_BOOT_SRAM_BASE 0xffe00000
43#define CHESTNUT_BOOT_SRAM_SIZE_ACTUAL (1024*1024)
44#define CHESTNUT_CPLD_BASE 0xffd00000
45#define CHESTNUT_CPLD_SIZE_ACTUAL 5
46#define CHESTNUT_CPLD_REG3 (CHESTNUT_CPLD_BASE+3)
47#define CHESTNUT_UART_BASE 0xffc00000
48#define CHESTNUT_UART_SIZE_ACTUAL 16
49#define CHESTNUT_FRAM_BASE 0xffb00000
50#define CHESTNUT_FRAM_SIZE_ACTUAL (32*1024)
51#define CHESTNUT_INTERNAL_SRAM_BASE 0xff800000
52#define CHESTNUT_32BIT_BASE 0xfc000000
53#define CHESTNUT_32BIT_SIZE (32*1024*1024)
54
55#define CHESTNUT_BOOT_8BIT_SIZE max(MV64360_WINDOW_SIZE_MIN, \
56 CHESTNUT_BOOT_8BIT_SIZE_ACTUAL)
57#define CHESTNUT_BOOT_SRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
58 CHESTNUT_BOOT_SRAM_SIZE_ACTUAL)
59#define CHESTNUT_CPLD_SIZE max(MV64360_WINDOW_SIZE_MIN, \
60 CHESTNUT_CPLD_SIZE_ACTUAL)
61#define CHESTNUT_UART_SIZE max(MV64360_WINDOW_SIZE_MIN, \
62 CHESTNUT_UART_SIZE_ACTUAL)
63#define CHESTNUT_FRAM_SIZE max(MV64360_WINDOW_SIZE_MIN, \
64 CHESTNUT_FRAM_SIZE_ACTUAL)
65
66#define CHESTNUT_BUS_SPEED 200000000
67#define CHESTNUT_PIBS_DATABASE 0xf0000 /* from PIBS src code */
68
69#define KATANA_ETH0_PHY_ADDR 12
70#define KATANA_ETH1_PHY_ADDR 11
71#define KATANA_ETH2_PHY_ADDR 4
72
73#define CHESTNUT_ETH_TX_QUEUE_SIZE 800
74#define CHESTNUT_ETH_RX_QUEUE_SIZE 400
75
76/*
77 * PCI windows
78 */
79
80#define CHESTNUT_PCI0_MEM_PROC_ADDR 0x80000000
81#define CHESTNUT_PCI0_MEM_PCI_HI_ADDR 0x00000000
82#define CHESTNUT_PCI0_MEM_PCI_LO_ADDR 0x80000000
83#define CHESTNUT_PCI0_MEM_SIZE 0x10000000
84#define CHESTNUT_PCI0_IO_PROC_ADDR 0xa0000000
85#define CHESTNUT_PCI0_IO_PCI_ADDR 0x00000000
86#define CHESTNUT_PCI0_IO_SIZE 0x01000000
87
88/*
89 * Board-specific IRQ info
90 */
91#define CHESTNUT_PCI_SLOT0_IRQ (64 + 31)
92#define CHESTNUT_PCI_SLOT1_IRQ (64 + 30)
93#define CHESTNUT_PCI_SLOT2_IRQ (64 + 29)
94#define CHESTNUT_PCI_SLOT3_IRQ (64 + 28)
95
96/* serial port definitions */
97#define CHESTNUT_UART0_IO_BASE (CHESTNUT_UART_BASE + 8)
98#define CHESTNUT_UART1_IO_BASE CHESTNUT_UART_BASE
99
100#define UART0_INT (64 + 25)
101#define UART1_INT (64 + 26)
102
103#ifdef CONFIG_SERIAL_MANY_PORTS
104#define RS_TABLE_SIZE 64
105#else
106#define RS_TABLE_SIZE 2
107#endif
108
109/* Rate for the 3.6864 Mhz clock for the onboard serial chip */
110#define BASE_BAUD (3686400 / 16)
111
112#ifdef CONFIG_SERIAL_DETECT_IRQ
113#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
114#else
115#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
116#endif
117
118#define STD_UART_OP(num) \
119 { 0, BASE_BAUD, 0, UART##num##_INT, STD_COM_FLAGS, \
120 iomem_base: (u8 *)CHESTNUT_UART##num##_IO_BASE, \
121 io_type: SERIAL_IO_MEM},
122
123#define SERIAL_PORT_DFNS \
124 STD_UART_OP(0) \
125 STD_UART_OP(1)
126
127#endif /* __PPC_PLATFORMS_CHESTNUT_H__ */
diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c
deleted file mode 100644
index 07f672d58767..000000000000
--- a/arch/ppc/platforms/cpci690.c
+++ /dev/null
@@ -1,453 +0,0 @@
1/*
2 * Board setup routines for the Force CPCI690 board.
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2003 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This programr
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/delay.h>
12#include <linux/pci.h>
13#include <linux/irq.h>
14#include <linux/fs.h>
15#include <linux/seq_file.h>
16#include <linux/console.h>
17#include <linux/initrd.h>
18#include <linux/root_dev.h>
19#include <linux/mv643xx.h>
20#include <linux/platform_device.h>
21#include <asm/bootinfo.h>
22#include <asm/machdep.h>
23#include <asm/todc.h>
24#include <asm/time.h>
25#include <asm/mv64x60.h>
26#include <platforms/cpci690.h>
27
28#define BOARD_VENDOR "Force"
29#define BOARD_MACHINE "CPCI690"
30
31/* Set IDE controllers into Native mode? */
32#define SET_PCI_IDE_NATIVE
33
34static struct mv64x60_handle bh;
35static void __iomem *cpci690_br_base;
36
37TODC_ALLOC();
38
39static int __init
40cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
41{
42 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
43
44 if (hose->index == 0) {
45 static char pci_irq_table[][4] =
46 /*
47 * PCI IDSEL/INTPIN->INTLINE
48 * A B C D
49 */
50 {
51 { 90, 91, 88, 89 }, /* IDSEL 30/20 - Sentinel */
52 };
53
54 const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
55 return PCI_IRQ_TABLE_LOOKUP;
56 } else {
57 static char pci_irq_table[][4] =
58 /*
59 * PCI IDSEL/INTPIN->INTLINE
60 * A B C D
61 */
62 {
63 { 93, 94, 95, 92 }, /* IDSEL 28/18 - PMC slot 2 */
64 { 0, 0, 0, 0 }, /* IDSEL 29/19 - Not used */
65 { 94, 95, 92, 93 }, /* IDSEL 30/20 - PMC slot 1 */
66 };
67
68 const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
69 return PCI_IRQ_TABLE_LOOKUP;
70 }
71}
72
73#define GB (1024UL * 1024UL * 1024UL)
74
75static u32
76cpci690_get_bus_freq(void)
77{
78 if (boot_mem_size >= (1*GB)) /* bus speed based on mem size */
79 return 100000000;
80 else
81 return 133333333;
82}
83
84static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
85 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
86 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/
87};
88
89static int
90cpci690_get_cpu_freq(void)
91{
92 unsigned long pll_cfg;
93
94 pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
95 return cpci690_get_bus_freq() * cpu_750xx[pll_cfg]/2;
96}
97
98static void __init
99cpci690_setup_bridge(void)
100{
101 struct mv64x60_setup_info si;
102 int i;
103
104 memset(&si, 0, sizeof(si));
105
106 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
107
108 si.pci_0.enable_bus = 1;
109 si.pci_0.pci_io.cpu_base = CPCI690_PCI0_IO_START_PROC_ADDR;
110 si.pci_0.pci_io.pci_base_hi = 0;
111 si.pci_0.pci_io.pci_base_lo = CPCI690_PCI0_IO_START_PCI_ADDR;
112 si.pci_0.pci_io.size = CPCI690_PCI0_IO_SIZE;
113 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
114 si.pci_0.pci_mem[0].cpu_base = CPCI690_PCI0_MEM_START_PROC_ADDR;
115 si.pci_0.pci_mem[0].pci_base_hi = CPCI690_PCI0_MEM_START_PCI_HI_ADDR;
116 si.pci_0.pci_mem[0].pci_base_lo = CPCI690_PCI0_MEM_START_PCI_LO_ADDR;
117 si.pci_0.pci_mem[0].size = CPCI690_PCI0_MEM_SIZE;
118 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
119 si.pci_0.pci_cmd_bits = 0;
120 si.pci_0.latency_timer = 0x80;
121
122 si.pci_1.enable_bus = 1;
123 si.pci_1.pci_io.cpu_base = CPCI690_PCI1_IO_START_PROC_ADDR;
124 si.pci_1.pci_io.pci_base_hi = 0;
125 si.pci_1.pci_io.pci_base_lo = CPCI690_PCI1_IO_START_PCI_ADDR;
126 si.pci_1.pci_io.size = CPCI690_PCI1_IO_SIZE;
127 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
128 si.pci_1.pci_mem[0].cpu_base = CPCI690_PCI1_MEM_START_PROC_ADDR;
129 si.pci_1.pci_mem[0].pci_base_hi = CPCI690_PCI1_MEM_START_PCI_HI_ADDR;
130 si.pci_1.pci_mem[0].pci_base_lo = CPCI690_PCI1_MEM_START_PCI_LO_ADDR;
131 si.pci_1.pci_mem[0].size = CPCI690_PCI1_MEM_SIZE;
132 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
133 si.pci_1.pci_cmd_bits = 0;
134 si.pci_1.latency_timer = 0x80;
135
136 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
137 si.cpu_prot_options[i] = 0;
138 si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
139 si.pci_0.acc_cntl_options[i] =
140 GT64260_PCI_ACC_CNTL_DREADEN |
141 GT64260_PCI_ACC_CNTL_RDPREFETCH |
142 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
143 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
144 GT64260_PCI_ACC_CNTL_SWAP_NONE |
145 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
146 si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
147 si.pci_1.acc_cntl_options[i] =
148 GT64260_PCI_ACC_CNTL_DREADEN |
149 GT64260_PCI_ACC_CNTL_RDPREFETCH |
150 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
151 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
152 GT64260_PCI_ACC_CNTL_SWAP_NONE |
153 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
154 si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
155 }
156
157 /* Lookup PCI host bridges */
158 if (mv64x60_init(&bh, &si))
159 printk(KERN_ERR "Bridge initialization failed.\n");
160
161 pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
162 ppc_md.pci_swizzle = common_swizzle;
163 ppc_md.pci_map_irq = cpci690_map_irq;
164 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
165
166 mv64x60_set_bus(&bh, 0, 0);
167 bh.hose_a->first_busno = 0;
168 bh.hose_a->last_busno = 0xff;
169 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
170
171 bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
172 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
173 bh.hose_b->last_busno = 0xff;
174 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
175 bh.hose_b->first_busno);
176}
177
178static void __init
179cpci690_setup_peripherals(void)
180{
181 /* Set up windows to CPLD, RTC/TODC, IPMI. */
182 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
183 CPCI690_BR_SIZE, 0);
184 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
185 cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
186
187 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
188 CPCI690_TODC_SIZE, 0);
189 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
190 TODC_INIT(TODC_TYPE_MK48T35, 0, 0,
191 ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8);
192
193 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE,
194 CPCI690_IPMI_SIZE, 0);
195 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
196
197 mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
198 mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
199
200 mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
201
202 /*
203 * Turn off timer/counters. Not turning off watchdog timer because
204 * can't read its reg on the 64260A so don't know if we'll be enabling
205 * or disabling.
206 */
207 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
208 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
209 mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
210 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
211
212 /*
213 * Set MPSC Multiplex RMII
214 * NOTE: ethernet driver modifies bit 0 and 1
215 */
216 mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
217
218#define GPP_EXTERNAL_INTERRUPTS \
219 ((1<<24) | (1<<25) | (1<<26) | (1<<27) | \
220 (1<<28) | (1<<29) | (1<<30) | (1<<31))
221 /* PCI interrupts are inputs */
222 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
223 /* PCI interrupts are active low */
224 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
225
226 /* Clear any pending interrupts for these inputs and enable them. */
227 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
228 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
229
230 /* Route MPP interrupt inputs to GPP */
231 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);
232 mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);
233}
234
235static void __init
236cpci690_setup_arch(void)
237{
238 if (ppc_md.progress)
239 ppc_md.progress("cpci690_setup_arch: enter", 0);
240#ifdef CONFIG_BLK_DEV_INITRD
241 if (initrd_start)
242 ROOT_DEV = Root_RAM0;
243 else
244#endif
245#ifdef CONFIG_ROOT_NFS
246 ROOT_DEV = Root_NFS;
247#else
248 ROOT_DEV = Root_SDA2;
249#endif
250
251 if (ppc_md.progress)
252 ppc_md.progress("cpci690_setup_arch: Enabling L2 cache", 0);
253
254 /* Enable L2 and L3 caches (if 745x) */
255 _set_L2CR(_get_L2CR() | L2CR_L2E);
256 _set_L3CR(_get_L3CR() | L3CR_L3E);
257
258 if (ppc_md.progress)
259 ppc_md.progress("cpci690_setup_arch: Initializing bridge", 0);
260
261 cpci690_setup_bridge(); /* set up PCI bridge(s) */
262 cpci690_setup_peripherals(); /* set up chip selects/GPP/MPP etc */
263
264 if (ppc_md.progress)
265 ppc_md.progress("cpci690_setup_arch: bridge init complete", 0);
266
267 printk(KERN_INFO "%s %s port (C) 2003 MontaVista Software, Inc. "
268 "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
269
270 if (ppc_md.progress)
271 ppc_md.progress("cpci690_setup_arch: exit", 0);
272}
273
274/* Platform device data fixup routines. */
275#if defined(CONFIG_SERIAL_MPSC)
276static void __init
277cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
278{
279 struct mpsc_pdata *pdata;
280
281 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
282
283 pdata->max_idle = 40;
284 pdata->default_baud = CPCI690_MPSC_BAUD;
285 pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
286 pdata->brg_clk_freq = cpci690_get_bus_freq();
287}
288
289static int
290cpci690_platform_notify(struct device *dev)
291{
292 static struct {
293 char *bus_id;
294 void ((*rtn)(struct platform_device *pdev));
295 } dev_map[] = {
296 { MPSC_CTLR_NAME ".0", cpci690_fixup_mpsc_pdata },
297 { MPSC_CTLR_NAME ".1", cpci690_fixup_mpsc_pdata },
298 };
299 struct platform_device *pdev;
300 int i;
301
302 if (dev && dev->bus_id)
303 for (i=0; i<ARRAY_SIZE(dev_map); i++)
304 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
305 BUS_ID_SIZE)) {
306
307 pdev = container_of(dev,
308 struct platform_device, dev);
309 dev_map[i].rtn(pdev);
310 }
311
312 return 0;
313}
314#endif
315
316static void
317cpci690_reset_board(void)
318{
319 u32 i = 10000;
320
321 local_irq_disable();
322 out_8((cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
323
324 while (i != 0) i++;
325 panic("restart failed\n");
326}
327
328static void
329cpci690_restart(char *cmd)
330{
331 cpci690_reset_board();
332}
333
334static void
335cpci690_halt(void)
336{
337 while (1);
338 /* NOTREACHED */
339}
340
341static void
342cpci690_power_off(void)
343{
344 cpci690_halt();
345 /* NOTREACHED */
346}
347
348static int
349cpci690_show_cpuinfo(struct seq_file *m)
350{
351 char *s;
352
353 seq_printf(m, "cpu MHz\t\t: %d\n",
354 (cpci690_get_cpu_freq() + 500000) / 1000000);
355 seq_printf(m, "bus MHz\t\t: %d\n",
356 (cpci690_get_bus_freq() + 500000) / 1000000);
357 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
358 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
359 seq_printf(m, "FPGA Revision\t: %d\n",
360 in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5);
361
362 switch(bh.type) {
363 case MV64x60_TYPE_GT64260A:
364 s = "gt64260a";
365 break;
366 case MV64x60_TYPE_GT64260B:
367 s = "gt64260b";
368 break;
369 case MV64x60_TYPE_MV64360:
370 s = "mv64360";
371 break;
372 case MV64x60_TYPE_MV64460:
373 s = "mv64460";
374 break;
375 default:
376 s = "Unknown";
377 }
378 seq_printf(m, "bridge type\t: %s\n", s);
379 seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
380#if defined(CONFIG_NOT_COHERENT_CACHE)
381 seq_printf(m, "coherency\t: %s\n", "off");
382#else
383 seq_printf(m, "coherency\t: %s\n", "on");
384#endif
385
386 return 0;
387}
388
389static void __init
390cpci690_calibrate_decr(void)
391{
392 ulong freq;
393
394 freq = cpci690_get_bus_freq() / 4;
395
396 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
397 freq/1000000, freq%1000000);
398
399 tb_ticks_per_jiffy = freq / HZ;
400 tb_to_us = mulhwu_scale_factor(freq, 1000000);
401}
402
403#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
404static void __init
405cpci690_map_io(void)
406{
407 io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
408 128 * 1024, _PAGE_IO);
409}
410#endif
411
412void __init
413platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
414 unsigned long r6, unsigned long r7)
415{
416 parse_bootinfo(find_bootinfo());
417
418#ifdef CONFIG_BLK_DEV_INITRD
419 /* take care of initrd if we have one */
420 if (r4) {
421 initrd_start = r4 + KERNELBASE;
422 initrd_end = r5 + KERNELBASE;
423 }
424#endif /* CONFIG_BLK_DEV_INITRD */
425
426 isa_mem_base = 0;
427
428 ppc_md.setup_arch = cpci690_setup_arch;
429 ppc_md.show_cpuinfo = cpci690_show_cpuinfo;
430 ppc_md.init_IRQ = gt64260_init_irq;
431 ppc_md.get_irq = gt64260_get_irq;
432 ppc_md.restart = cpci690_restart;
433 ppc_md.power_off = cpci690_power_off;
434 ppc_md.halt = cpci690_halt;
435 ppc_md.time_init = todc_time_init;
436 ppc_md.set_rtc_time = todc_set_rtc_time;
437 ppc_md.get_rtc_time = todc_get_rtc_time;
438 ppc_md.nvram_read_val = todc_direct_read_val;
439 ppc_md.nvram_write_val = todc_direct_write_val;
440 ppc_md.calibrate_decr = cpci690_calibrate_decr;
441
442#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
443 ppc_md.setup_io_mappings = cpci690_map_io;
444#ifdef CONFIG_SERIAL_TEXT_DEBUG
445 ppc_md.progress = mv64x60_mpsc_progress;
446 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
447#endif /* CONFIG_SERIAL_TEXT_DEBUG */
448#endif /* defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) */
449
450#if defined(CONFIG_SERIAL_MPSC)
451 platform_notify = cpci690_platform_notify;
452#endif
453}
diff --git a/arch/ppc/platforms/cpci690.h b/arch/ppc/platforms/cpci690.h
deleted file mode 100644
index 0fa5a4c31b67..000000000000
--- a/arch/ppc/platforms/cpci690.h
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * Definitions for Force CPCI690
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2003 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12/*
13 * The GT64260 has 2 PCI buses each with 1 window from the CPU bus to
14 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
15 */
16
17#ifndef __PPC_PLATFORMS_CPCI690_H
18#define __PPC_PLATFORMS_CPCI690_H
19
20/*
21 * Define bd_t to pass in the MAC addresses used by the GT64260's enet ctlrs.
22 */
23#define CPCI690_BI_MAGIC 0xFE8765DC
24
25typedef struct board_info {
26 u32 bi_magic;
27 u8 bi_enetaddr[3][6];
28} bd_t;
29
30/* PCI bus Resource setup */
31#define CPCI690_PCI0_MEM_START_PROC_ADDR 0x80000000
32#define CPCI690_PCI0_MEM_START_PCI_HI_ADDR 0x00000000
33#define CPCI690_PCI0_MEM_START_PCI_LO_ADDR 0x80000000
34#define CPCI690_PCI0_MEM_SIZE 0x10000000
35#define CPCI690_PCI0_IO_START_PROC_ADDR 0xa0000000
36#define CPCI690_PCI0_IO_START_PCI_ADDR 0x00000000
37#define CPCI690_PCI0_IO_SIZE 0x01000000
38
39#define CPCI690_PCI1_MEM_START_PROC_ADDR 0x90000000
40#define CPCI690_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
41#define CPCI690_PCI1_MEM_START_PCI_LO_ADDR 0x90000000
42#define CPCI690_PCI1_MEM_SIZE 0x10000000
43#define CPCI690_PCI1_IO_START_PROC_ADDR 0xa1000000
44#define CPCI690_PCI1_IO_START_PCI_ADDR 0x01000000
45#define CPCI690_PCI1_IO_SIZE 0x01000000
46
47/* Board Registers */
48#define CPCI690_BR_BASE 0xf0000000
49#define CPCI690_BR_SIZE_ACTUAL 0x8
50#define CPCI690_BR_SIZE max(GT64260_WINDOW_SIZE_MIN, \
51 CPCI690_BR_SIZE_ACTUAL)
52#define CPCI690_BR_LED_CNTL 0x00
53#define CPCI690_BR_SW_RESET 0x01
54#define CPCI690_BR_MISC_STATUS 0x02
55#define CPCI690_BR_SWITCH_STATUS 0x03
56#define CPCI690_BR_MEM_CTLR 0x04
57#define CPCI690_BR_LAST_RESET_1 0x05
58#define CPCI690_BR_LAST_RESET_2 0x06
59
60#define CPCI690_TODC_BASE 0xf0100000
61#define CPCI690_TODC_SIZE_ACTUAL 0x8000 /* Size or NVRAM + RTC */
62#define CPCI690_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \
63 CPCI690_TODC_SIZE_ACTUAL)
64#define CPCI690_MAC_OFFSET 0x7c10 /* MAC in RTC NVRAM */
65
66#define CPCI690_IPMI_BASE 0xf0200000
67#define CPCI690_IPMI_SIZE_ACTUAL 0x10 /* 16 bytes of IPMI */
68#define CPCI690_IPMI_SIZE max(GT64260_WINDOW_SIZE_MIN, \
69 CPCI690_IPMI_SIZE_ACTUAL)
70
71#define CPCI690_MPSC_BAUD 9600
72#define CPCI690_MPSC_CLK_SRC 8 /* TCLK */
73
74#endif /* __PPC_PLATFORMS_CPCI690_H */
diff --git a/arch/ppc/platforms/est8260.h b/arch/ppc/platforms/est8260.h
deleted file mode 100644
index adba68ecf57b..000000000000
--- a/arch/ppc/platforms/est8260.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/* Board information for the EST8260, which should be generic for
2 * all 8260 boards. The IMMR is now given to us so the hard define
3 * will soon be removed. All of the clock values are computed from
4 * the configuration SCMR and the Power-On-Reset word.
5 */
6#ifndef __EST8260_PLATFORM
7#define __EST8260_PLATFORM
8
9#define CPM_MAP_ADDR ((uint)0xf0000000)
10
11#define BOOTROM_RESTART_ADDR ((uint)0xff000104)
12
13/* For our show_cpuinfo hooks. */
14#define CPUINFO_VENDOR "EST Corporation"
15#define CPUINFO_MACHINE "SBC8260 PowerPC"
16
17/* A Board Information structure that is given to a program when
18 * prom starts it up.
19 */
20typedef struct bd_info {
21 unsigned int bi_memstart; /* Memory start address */
22 unsigned int bi_memsize; /* Memory (end) size in bytes */
23 unsigned int bi_intfreq; /* Internal Freq, in Hz */
24 unsigned int bi_busfreq; /* Bus Freq, in MHz */
25 unsigned int bi_cpmfreq; /* CPM Freq, in MHz */
26 unsigned int bi_brgfreq; /* BRG Freq, in MHz */
27 unsigned int bi_vco; /* VCO Out from PLL */
28 unsigned int bi_baudrate; /* Default console baud rate */
29 unsigned int bi_immr; /* IMMR when called from boot rom */
30 unsigned char bi_enetaddr[6];
31} bd_t;
32
33extern bd_t m8xx_board_info;
34
35#endif /* __EST8260_PLATFORM */
diff --git a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c
deleted file mode 100644
index f522b31c46d7..000000000000
--- a/arch/ppc/platforms/ev64260.c
+++ /dev/null
@@ -1,649 +0,0 @@
1/*
2 * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12/*
13 * The EV-64260-BP port is the result of hard work from many people from
14 * many companies. In particular, employees of Marvell/Galileo, Mission
15 * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
16 *
17 * Note: I have not been able to get *all* PCI slots to work reliably
18 * at 66 MHz. I recommend setting jumpers J15 & J16 to short pins 1&2
19 * so that 33 MHz is used. --MAG
20 * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK.
21 * At 100MHz, they are solid.
22 */
23
24#include <linux/delay.h>
25#include <linux/pci.h>
26#include <linux/irq.h>
27#include <linux/fs.h>
28#include <linux/seq_file.h>
29#include <linux/console.h>
30#include <linux/initrd.h>
31#include <linux/root_dev.h>
32#include <linux/platform_device.h>
33#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
34#include <linux/serial.h>
35#include <linux/tty.h>
36#include <linux/serial_core.h>
37#include <linux/serial_8250.h>
38#else
39#include <linux/mv643xx.h>
40#endif
41#include <asm/bootinfo.h>
42#include <asm/machdep.h>
43#include <asm/mv64x60.h>
44#include <asm/todc.h>
45#include <asm/time.h>
46
47#include <platforms/ev64260.h>
48
49#define BOARD_VENDOR "Marvell/Galileo"
50#define BOARD_MACHINE "EV-64260-BP"
51
52static struct mv64x60_handle bh;
53
54#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
55extern void gen550_progress(char *, unsigned short);
56extern void gen550_init(int, struct uart_port *);
57#endif
58
59static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
60 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
61};
62static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */
63 { 1, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 },
64 { 0, 30, 0, 2, 0, 26, 0, 18, 0, 22, 20, 24, 28, 32, 0, 0 }
65};
66
67
68TODC_ALLOC();
69
70static int
71ev64260_get_bus_speed(void)
72{
73 return 100000000;
74}
75
76static int
77ev64260_get_cpu_speed(void)
78{
79 unsigned long pvr, hid1, pll_ext;
80
81 pvr = PVR_VER(mfspr(SPRN_PVR));
82
83 if (pvr != PVR_VER(PVR_7450)) {
84 hid1 = mfspr(SPRN_HID1) >> 28;
85 return ev64260_get_bus_speed() * cpu_7xx[hid1]/2;
86 }
87 else {
88 hid1 = (mfspr(SPRN_HID1) & 0x0001e000) >> 13;
89 pll_ext = 0; /* No way to read; must get from schematic */
90 return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2;
91 }
92}
93
94unsigned long __init
95ev64260_find_end_of_memory(void)
96{
97 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
98 MV64x60_TYPE_GT64260A);
99}
100
101/*
102 * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
103 * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first
104 * PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ).
105 * This is the most IRQs you can get from one bus with this board, though.
106 */
107static int __init
108ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
109{
110 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
111
112 if (hose->index == 0) {
113 static char pci_irq_table[][4] =
114 /*
115 * PCI IDSEL/INTPIN->INTLINE
116 * A B C D
117 */
118 {
119 {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */
120 {EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */
121 };
122
123 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
124 return PCI_IRQ_TABLE_LOOKUP;
125 }
126 else {
127 static char pci_irq_table[][4] =
128 /*
129 * PCI IDSEL/INTPIN->INTLINE
130 * A B C D
131 */
132 {
133 { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */
134 { EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */
135 };
136
137 const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
138 return PCI_IRQ_TABLE_LOOKUP;
139 }
140}
141
142static void __init
143ev64260_setup_peripherals(void)
144{
145 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
146 EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0);
147 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
148 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
149 EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0);
150 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
151 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
152 EV64260_TODC_BASE, EV64260_TODC_SIZE, 0);
153 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
154 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
155 EV64260_UART_BASE, EV64260_UART_SIZE, 0);
156 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
157 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
158 EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0);
159 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
160
161 TODC_INIT(TODC_TYPE_DS1501, 0, 0,
162 ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8);
163
164 mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29)));
165 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27));
166
167 if (ev64260_get_bus_speed() > 100000000)
168 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23));
169
170 mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
171 mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
172
173 /*
174 * Enabling of PCI internal-vs-external arbitration
175 * is a platform- and errata-dependent decision.
176 */
177 if (bh.type == MV64x60_TYPE_GT64260A ) {
178 mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
179 mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
180 }
181
182 mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
183
184 /*
185 * Turn off timer/counters. Not turning off watchdog timer because
186 * can't read its reg on the 64260A so don't know if we'll be enabling
187 * or disabling.
188 */
189 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
190 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
191 mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
192 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
193
194 /*
195 * Set MPSC Multiplex RMII
196 * NOTE: ethernet driver modifies bit 0 and 1
197 */
198 mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
199
200 /*
201 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
202 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
203 * register). Need to route the MPP inputs to the GPP and set the
204 * polarity correctly.
205 *
206 * In MPP Control 2 Register
207 * MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0
208 * MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0
209 */
210 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) );
211
212 /*
213 * In MPP Control 3 Register
214 * MPP 26 -> GPP 26 (RTC INT) bits 8-11 -> 0
215 * MPP 27 -> GPP 27 (PCI 0 INTA) bits 12-15 -> 0
216 * MPP 29 -> GPP 29 (PCI 1 INTA) bits 20-23 -> 0
217 */
218 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20));
219
220#define GPP_EXTERNAL_INTERRUPTS \
221 ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
222 /* DUART & PCI interrupts are inputs */
223 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
224 /* DUART & PCI interrupts are active low */
225 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
226
227 /* Clear any pending interrupts for these inputs and enable them. */
228 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
229 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
230
231 return;
232}
233
234static void __init
235ev64260_setup_bridge(void)
236{
237 struct mv64x60_setup_info si;
238 int i;
239
240 memset(&si, 0, sizeof(si));
241
242 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
243
244 si.pci_0.enable_bus = 1;
245 si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE;
246 si.pci_0.pci_io.pci_base_hi = 0;
247 si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE;
248 si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE;
249 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
250 si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE;
251 si.pci_0.pci_mem[0].pci_base_hi = 0;
252 si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE;
253 si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE;
254 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
255 si.pci_0.pci_cmd_bits = 0;
256 si.pci_0.latency_timer = 0x8;
257
258 si.pci_1.enable_bus = 1;
259 si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE;
260 si.pci_1.pci_io.pci_base_hi = 0;
261 si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE;
262 si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE;
263 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
264 si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE;
265 si.pci_1.pci_mem[0].pci_base_hi = 0;
266 si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE;
267 si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE;
268 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
269 si.pci_1.pci_cmd_bits = 0;
270 si.pci_1.latency_timer = 0x8;
271
272 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
273 si.cpu_prot_options[i] = 0;
274 si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
275 si.pci_0.acc_cntl_options[i] =
276 GT64260_PCI_ACC_CNTL_DREADEN |
277 GT64260_PCI_ACC_CNTL_RDPREFETCH |
278 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
279 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
280 GT64260_PCI_ACC_CNTL_SWAP_NONE |
281 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
282 si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
283 si.pci_1.acc_cntl_options[i] =
284 GT64260_PCI_ACC_CNTL_DREADEN |
285 GT64260_PCI_ACC_CNTL_RDPREFETCH |
286 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
287 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
288 GT64260_PCI_ACC_CNTL_SWAP_NONE |
289 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
290 si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
291 }
292
293 /* Lookup PCI host bridges */
294 if (mv64x60_init(&bh, &si))
295 printk(KERN_ERR "Bridge initialization failed.\n");
296
297 pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
298 ppc_md.pci_swizzle = common_swizzle;
299 ppc_md.pci_map_irq = ev64260_map_irq;
300 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
301
302 mv64x60_set_bus(&bh, 0, 0);
303 bh.hose_a->first_busno = 0;
304 bh.hose_a->last_busno = 0xff;
305 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
306
307 bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
308 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
309 bh.hose_b->last_busno = 0xff;
310 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
311 bh.hose_b->first_busno);
312
313 return;
314}
315
316#if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE)
317static void __init
318ev64260_early_serial_map(void)
319{
320 struct uart_port port;
321 static char first_time = 1;
322
323 if (first_time) {
324 memset(&port, 0, sizeof(port));
325
326 port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE);
327 port.irq = EV64260_UART_0_IRQ;
328 port.uartclk = BASE_BAUD * 16;
329 port.regshift = 2;
330 port.iotype = UPIO_MEM;
331 port.flags = STD_COM_FLAGS;
332
333#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
334 gen550_init(0, &port);
335#endif
336
337 if (early_serial_setup(&port) != 0)
338 printk(KERN_WARNING "Early serial init of port 0 "
339 "failed\n");
340
341 first_time = 0;
342 }
343
344 return;
345}
346#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
347static void __init
348ev64260_early_serial_map(void)
349{
350}
351#endif
352
353static void __init
354ev64260_setup_arch(void)
355{
356 if (ppc_md.progress)
357 ppc_md.progress("ev64260_setup_arch: enter", 0);
358
359#ifdef CONFIG_BLK_DEV_INITRD
360 if (initrd_start)
361 ROOT_DEV = Root_RAM0;
362 else
363#endif
364#ifdef CONFIG_ROOT_NFS
365 ROOT_DEV = Root_NFS;
366#else
367 ROOT_DEV = Root_SDA2;
368#endif
369
370 if (ppc_md.progress)
371 ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0);
372
373 /* Enable L2 and L3 caches (if 745x) */
374 _set_L2CR(_get_L2CR() | L2CR_L2E);
375 _set_L3CR(_get_L3CR() | L3CR_L3E);
376
377 if (ppc_md.progress)
378 ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0);
379
380 ev64260_setup_bridge(); /* set up PCI bridge(s) */
381 ev64260_setup_peripherals(); /* set up chip selects/GPP/MPP etc */
382
383 if (ppc_md.progress)
384 ppc_md.progress("ev64260_setup_arch: bridge init complete", 0);
385
386#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
387 ev64260_early_serial_map();
388#endif
389
390 printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc. "
391 "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
392
393 if (ppc_md.progress)
394 ppc_md.progress("ev64260_setup_arch: exit", 0);
395
396 return;
397}
398
399/* Platform device data fixup routines. */
400#if defined(CONFIG_SERIAL_MPSC)
401static void __init
402ev64260_fixup_mpsc_pdata(struct platform_device *pdev)
403{
404 struct mpsc_pdata *pdata;
405
406 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
407
408 pdata->max_idle = 40;
409 pdata->default_baud = EV64260_DEFAULT_BAUD;
410 pdata->brg_clk_src = EV64260_MPSC_CLK_SRC;
411 pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
412
413 return;
414}
415
416static int
417ev64260_platform_notify(struct device *dev)
418{
419 static struct {
420 char *bus_id;
421 void ((*rtn)(struct platform_device *pdev));
422 } dev_map[] = {
423 { MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata },
424 { MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata },
425 };
426 struct platform_device *pdev;
427 int i;
428
429 if (dev && dev->bus_id)
430 for (i=0; i<ARRAY_SIZE(dev_map); i++)
431 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
432 BUS_ID_SIZE)) {
433
434 pdev = container_of(dev,
435 struct platform_device, dev);
436 dev_map[i].rtn(pdev);
437 }
438
439 return 0;
440}
441#endif
442
443static void
444ev64260_reset_board(void *addr)
445{
446 local_irq_disable();
447
448 /* disable and invalidate the L2 cache */
449 _set_L2CR(0);
450 _set_L2CR(0x200000);
451
452 /* flush and disable L1 I/D cache */
453 __asm__ __volatile__
454 ("mfspr 3,1008\n\t"
455 "ori 5,5,0xcc00\n\t"
456 "ori 4,3,0xc00\n\t"
457 "andc 5,3,5\n\t"
458 "sync\n\t"
459 "mtspr 1008,4\n\t"
460 "isync\n\t"
461 "sync\n\t"
462 "mtspr 1008,5\n\t"
463 "isync\n\t"
464 "sync\n\t");
465
466 /* unmap any other random cs's that might overlap with bootcs */
467 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0);
468 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
469 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0);
470 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
471 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0);
472 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
473 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0);
474 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
475
476 /* map bootrom back in to gt @ reset defaults */
477 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
478 0xff800000, 8*1024*1024, 0);
479 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
480
481 /* move reg base back to default, setup default pci0 */
482 mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE,
483 (1<<24) | CONFIG_MV64X60_BASE >> 20);
484
485 /* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped
486 * via BAT or MMU, and MSR IR/DR is ON */
487 /* SRR0 has system reset vector, SRR1 has default MSR value */
488 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
489 /* NOTE: assumes reset vector is at 0xfff00100 */
490 __asm__ __volatile__
491 ("mtspr 26, %0\n\t"
492 "li 4,(1<<6)\n\t"
493 "mtspr 27,4\n\t"
494 "rfi\n\t"
495 :: "r" (addr):"r4");
496
497 return;
498}
499
500static void
501ev64260_restart(char *cmd)
502{
503 volatile ulong i = 10000000;
504
505 ev64260_reset_board((void *)0xfff00100);
506
507 while (i-- > 0);
508 panic("restart failed\n");
509}
510
511static void
512ev64260_halt(void)
513{
514 local_irq_disable();
515 while (1);
516 /* NOTREACHED */
517}
518
519static void
520ev64260_power_off(void)
521{
522 ev64260_halt();
523 /* NOTREACHED */
524}
525
526static int
527ev64260_show_cpuinfo(struct seq_file *m)
528{
529 uint pvid;
530
531 pvid = mfspr(SPRN_PVR);
532 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
533 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
534 seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
535 seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
536
537 return 0;
538}
539
540/* DS1501 RTC has too much variation to use RTC for calibration */
541static void __init
542ev64260_calibrate_decr(void)
543{
544 ulong freq;
545
546 freq = ev64260_get_bus_speed()/4;
547
548 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
549 freq/1000000, freq%1000000);
550
551 tb_ticks_per_jiffy = freq / HZ;
552 tb_to_us = mulhwu_scale_factor(freq, 1000000);
553
554 return;
555}
556
557/*
558 * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space.
559 */
560static __inline__ void
561ev64260_set_bat(void)
562{
563 mb();
564 mtspr(SPRN_DBAT1U, 0xfb0001fe);
565 mtspr(SPRN_DBAT1L, 0xfb00002a);
566 mb();
567
568 return;
569}
570
571#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
572static void __init
573ev64260_map_io(void)
574{
575 io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO);
576}
577#endif
578
579void __init
580platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
581 unsigned long r6, unsigned long r7)
582{
583#ifdef CONFIG_BLK_DEV_INITRD
584 extern int initrd_below_start_ok;
585
586 initrd_start=initrd_end=0;
587 initrd_below_start_ok=0;
588#endif /* CONFIG_BLK_DEV_INITRD */
589
590 parse_bootinfo(find_bootinfo());
591
592 isa_mem_base = 0;
593 isa_io_base = EV64260_PCI0_IO_CPU_BASE;
594 pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE;
595
596 loops_per_jiffy = ev64260_get_cpu_speed() / HZ;
597
598 ppc_md.setup_arch = ev64260_setup_arch;
599 ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
600 ppc_md.init_IRQ = gt64260_init_irq;
601 ppc_md.get_irq = gt64260_get_irq;
602
603 ppc_md.restart = ev64260_restart;
604 ppc_md.power_off = ev64260_power_off;
605 ppc_md.halt = ev64260_halt;
606
607 ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
608
609 ppc_md.init = NULL;
610
611 ppc_md.time_init = todc_time_init;
612 ppc_md.set_rtc_time = todc_set_rtc_time;
613 ppc_md.get_rtc_time = todc_get_rtc_time;
614 ppc_md.nvram_read_val = todc_direct_read_val;
615 ppc_md.nvram_write_val = todc_direct_write_val;
616 ppc_md.calibrate_decr = ev64260_calibrate_decr;
617
618 bh.p_base = CONFIG_MV64X60_NEW_BASE;
619
620 ev64260_set_bat();
621
622#ifdef CONFIG_SERIAL_8250
623#if defined(CONFIG_SERIAL_TEXT_DEBUG)
624 ppc_md.setup_io_mappings = ev64260_map_io;
625 ppc_md.progress = gen550_progress;
626#endif
627#if defined(CONFIG_KGDB)
628 ppc_md.setup_io_mappings = ev64260_map_io;
629 ppc_md.early_serial_map = ev64260_early_serial_map;
630#endif
631#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
632#ifdef CONFIG_SERIAL_TEXT_DEBUG
633 ppc_md.setup_io_mappings = ev64260_map_io;
634 ppc_md.progress = mv64x60_mpsc_progress;
635 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
636#endif /* CONFIG_SERIAL_TEXT_DEBUG */
637#ifdef CONFIG_KGDB
638 ppc_md.setup_io_mappings = ev64260_map_io;
639 ppc_md.early_serial_map = ev64260_early_serial_map;
640#endif /* CONFIG_KGDB */
641
642#endif
643
644#if defined(CONFIG_SERIAL_MPSC)
645 platform_notify = ev64260_platform_notify;
646#endif
647
648 return;
649}
diff --git a/arch/ppc/platforms/ev64260.h b/arch/ppc/platforms/ev64260.h
deleted file mode 100644
index 44d90d56745a..000000000000
--- a/arch/ppc/platforms/ev64260.h
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * Definitions for Marvell/Galileo EV-64260-BP Evaluation Board.
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12/*
13 * The MV64x60 has 2 PCI buses each with 1 window from the CPU bus to
14 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
15 * We'll only use one PCI MEM window on each PCI bus.
16 *
17 * This is the CPU physical memory map (windows must be at least 1MB and start
18 * on a boundary that is a multiple of the window size):
19 *
20 * 0xfc000000-0xffffffff - External FLASH on device module
21 * 0xfbf00000-0xfbffffff - Embedded (on board) FLASH
22 * 0xfbe00000-0xfbefffff - GT64260 Registers (preferably)
23 * but really a config option
24 * 0xfbd00000-0xfbdfffff - External SRAM on device module
25 * 0xfbc00000-0xfbcfffff - TODC chip on device module
26 * 0xfbb00000-0xfbbfffff - External UART on device module
27 * 0xa2000000-0xfbafffff - <hole>
28 * 0xa1000000-0xa1ffffff - PCI 1 I/O (defined in gt64260.h)
29 * 0xa0000000-0xa0ffffff - PCI 0 I/O (defined in gt64260.h)
30 * 0x90000000-0x9fffffff - PCI 1 MEM (defined in gt64260.h)
31 * 0x80000000-0x8fffffff - PCI 0 MEM (defined in gt64260.h)
32 */
33
34#ifndef __PPC_PLATFORMS_EV64260_H
35#define __PPC_PLATFORMS_EV64260_H
36
37/* PCI mappings */
38#define EV64260_PCI0_IO_CPU_BASE 0xa0000000
39#define EV64260_PCI0_IO_PCI_BASE 0x00000000
40#define EV64260_PCI0_IO_SIZE 0x01000000
41
42#define EV64260_PCI0_MEM_CPU_BASE 0x80000000
43#define EV64260_PCI0_MEM_PCI_BASE 0x80000000
44#define EV64260_PCI0_MEM_SIZE 0x10000000
45
46#define EV64260_PCI1_IO_CPU_BASE (EV64260_PCI0_IO_CPU_BASE + \
47 EV64260_PCI0_IO_SIZE)
48#define EV64260_PCI1_IO_PCI_BASE (EV64260_PCI0_IO_PCI_BASE + \
49 EV64260_PCI0_IO_SIZE)
50#define EV64260_PCI1_IO_SIZE 0x01000000
51
52#define EV64260_PCI1_MEM_CPU_BASE (EV64260_PCI0_MEM_CPU_BASE + \
53 EV64260_PCI0_MEM_SIZE)
54#define EV64260_PCI1_MEM_PCI_BASE (EV64260_PCI0_MEM_PCI_BASE + \
55 EV64260_PCI0_MEM_SIZE)
56#define EV64260_PCI1_MEM_SIZE 0x10000000
57
58/* CPU Physical Memory Map setup (other than PCI) */
59#define EV64260_EXT_FLASH_BASE 0xfc000000
60#define EV64260_EMB_FLASH_BASE 0xfbf00000
61#define EV64260_EXT_SRAM_BASE 0xfbd00000
62#define EV64260_TODC_BASE 0xfbc00000
63#define EV64260_UART_BASE 0xfbb00000
64
65#define EV64260_EXT_FLASH_SIZE_ACTUAL 0x04000000 /* <= 64MB Extern FLASH */
66#define EV64260_EMB_FLASH_SIZE_ACTUAL 0x00080000 /* 512KB of Embed FLASH */
67#define EV64260_EXT_SRAM_SIZE_ACTUAL 0x00100000 /* 1MB SDRAM */
68#define EV64260_TODC_SIZE_ACTUAL 0x00000020 /* 32 bytes for TODC */
69#define EV64260_UART_SIZE_ACTUAL 0x00000040 /* 64 bytes for DUART */
70
71#define EV64260_EXT_FLASH_SIZE max(GT64260_WINDOW_SIZE_MIN, \
72 EV64260_EXT_FLASH_SIZE_ACTUAL)
73#define EV64260_EMB_FLASH_SIZE max(GT64260_WINDOW_SIZE_MIN, \
74 EV64260_EMB_FLASH_SIZE_ACTUAL)
75#define EV64260_EXT_SRAM_SIZE max(GT64260_WINDOW_SIZE_MIN, \
76 EV64260_EXT_SRAM_SIZE_ACTUAL)
77#define EV64260_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \
78 EV64260_TODC_SIZE_ACTUAL)
79/* Assembler in bootwrapper blows up if 'max' is used */
80#define EV64260_UART_SIZE GT64260_WINDOW_SIZE_MIN
81#define EV64260_UART_END ((EV64260_UART_BASE + \
82 EV64260_UART_SIZE - 1) & 0xfff00000)
83
84/* Board-specific IRQ info */
85#define EV64260_UART_0_IRQ 85
86#define EV64260_UART_1_IRQ 86
87#define EV64260_PCI_0_IRQ 91
88#define EV64260_PCI_1_IRQ 93
89
90/* Serial port setup */
91#define EV64260_DEFAULT_BAUD 115200
92
93#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
94#define SERIAL_PORT_DFNS
95
96#define EV64260_MPSC_CLK_SRC 8 /* TCLK */
97#define EV64260_MPSC_CLK_FREQ 100000000 /* 100MHz clk */
98#else
99#define EV64260_SERIAL_0 (EV64260_UART_BASE + 0x20)
100#define EV64260_SERIAL_1 EV64260_UART_BASE
101
102#define BASE_BAUD (EV64260_DEFAULT_BAUD * 2)
103
104#ifdef CONFIG_SERIAL_MANY_PORTS
105#define RS_TABLE_SIZE 64
106#else
107#define RS_TABLE_SIZE 2
108#endif
109
110#ifdef CONFIG_SERIAL_DETECT_IRQ
111#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
112#else
113#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
114#endif
115
116/* Required for bootloader's ns16550.c code */
117#define STD_SERIAL_PORT_DFNS \
118 { 0, BASE_BAUD, EV64260_SERIAL_0, EV64260_UART_0_IRQ, STD_COM_FLAGS, \
119 iomem_base: (u8 *)EV64260_SERIAL_0, /* ttyS0 */ \
120 iomem_reg_shift: 2, \
121 io_type: SERIAL_IO_MEM },
122
123#define SERIAL_PORT_DFNS \
124 STD_SERIAL_PORT_DFNS
125#endif
126#endif /* __PPC_PLATFORMS_EV64260_H */
diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c
deleted file mode 100644
index 6765676a5c6b..000000000000
--- a/arch/ppc/platforms/ev64360.c
+++ /dev/null
@@ -1,517 +0,0 @@
1/*
2 * Board setup routines for the Marvell EV-64360-BP Evaluation Board.
3 *
4 * Author: Lee Nicks <allinux@gmail.com>
5 *
6 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
7 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/console.h>
18#include <linux/initrd.h>
19#include <linux/root_dev.h>
20#include <linux/delay.h>
21#include <linux/seq_file.h>
22#include <linux/bootmem.h>
23#include <linux/mtd/physmap.h>
24#include <linux/mv643xx.h>
25#include <linux/platform_device.h>
26#include <asm/page.h>
27#include <asm/time.h>
28#include <asm/smp.h>
29#include <asm/todc.h>
30#include <asm/bootinfo.h>
31#include <asm/ppcboot.h>
32#include <asm/mv64x60.h>
33#include <asm/machdep.h>
34#include <platforms/ev64360.h>
35
36#define BOARD_VENDOR "Marvell"
37#define BOARD_MACHINE "EV-64360-BP"
38
39static struct mv64x60_handle bh;
40static void __iomem *sram_base;
41
42static u32 ev64360_flash_size_0;
43static u32 ev64360_flash_size_1;
44
45static u32 ev64360_bus_frequency;
46
47unsigned char __res[sizeof(bd_t)];
48
49TODC_ALLOC();
50
51static int __init
52ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
53{
54 return 0;
55}
56
57static void __init
58ev64360_setup_bridge(void)
59{
60 struct mv64x60_setup_info si;
61 int i;
62
63 memset(&si, 0, sizeof(si));
64
65 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
66
67 #ifdef CONFIG_PCI
68 si.pci_1.enable_bus = 1;
69 si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
70 si.pci_1.pci_io.pci_base_hi = 0;
71 si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
72 si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
73 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
74 si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
75 si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
76 si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
77 si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
78 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
79 si.pci_1.pci_cmd_bits = 0;
80 si.pci_1.latency_timer = 0x80;
81 #else
82 si.pci_0.enable_bus = 0;
83 si.pci_1.enable_bus = 0;
84 #endif
85
86 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
87#if defined(CONFIG_NOT_COHERENT_CACHE)
88 si.cpu_prot_options[i] = 0;
89 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
90 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
91 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
92
93 si.pci_1.acc_cntl_options[i] =
94 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
95 MV64360_PCI_ACC_CNTL_SWAP_NONE |
96 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
97 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
98#else
99 si.cpu_prot_options[i] = 0;
100 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
101 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
102 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
103
104 si.pci_1.acc_cntl_options[i] =
105 MV64360_PCI_ACC_CNTL_SNOOP_WB |
106 MV64360_PCI_ACC_CNTL_SWAP_NONE |
107 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
108 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
109#endif
110 }
111
112 if (mv64x60_init(&bh, &si))
113 printk(KERN_WARNING "Bridge initialization failed.\n");
114
115 #ifdef CONFIG_PCI
116 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
117 ppc_md.pci_swizzle = common_swizzle;
118 ppc_md.pci_map_irq = ev64360_map_irq;
119 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
120
121 mv64x60_set_bus(&bh, 1, 0);
122 bh.hose_b->first_busno = 0;
123 bh.hose_b->last_busno = 0xff;
124 #endif
125}
126
127/* Bridge & platform setup routines */
128void __init
129ev64360_intr_setup(void)
130{
131 /* MPP 8, 9, and 10 */
132 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
133
134 /*
135 * Define GPP 8,9,and 10 interrupt polarity as active low
136 * input signal and level triggered
137 */
138 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
139 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
140
141 /* Config GPP intr ctlr to respond to level trigger */
142 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
143
144 /* Erranum FEr PCI-#8 */
145 mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
146 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
147
148 /*
149 * Dismiss and then enable interrupt on GPP interrupt cause
150 * for CPU #0
151 */
152 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
153 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
154
155 /*
156 * Dismiss and then enable interrupt on CPU #0 high cause reg
157 * BIT25 summarizes GPP interrupts 8-15
158 */
159 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
160}
161
162void __init
163ev64360_setup_peripherals(void)
164{
165 u32 base;
166
167 /* Set up window for boot CS */
168 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
169 EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
170 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
171
172 /* We only use the 32-bit flash */
173 mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
174 &ev64360_flash_size_0);
175 ev64360_flash_size_1 = 0;
176
177 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
178 EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
179 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
180
181 TODC_INIT(TODC_TYPE_DS1501, 0, 0,
182 ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);
183
184 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
185 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
186 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
187 sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
188
189 /* Set up Enet->SRAM window */
190 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
191 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
192 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
193
194 /* Give enet r/w access to memory region */
195 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
196 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
197 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
198
199 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
200 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
201 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
202
203#if defined(CONFIG_NOT_COHERENT_CACHE)
204 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
205#else
206 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
207#endif
208
209 /*
210 * Setting the SRAM to 0. Note that this generates parity errors on
211 * internal data path in SRAM since it's first time accessing it
212 * while after reset it's not configured.
213 */
214 memset(sram_base, 0, MV64360_SRAM_SIZE);
215
216 /* set up PCI interrupt controller */
217 ev64360_intr_setup();
218}
219
220static void __init
221ev64360_setup_arch(void)
222{
223 if (ppc_md.progress)
224 ppc_md.progress("ev64360_setup_arch: enter", 0);
225
226 set_tb(0, 0);
227
228#ifdef CONFIG_BLK_DEV_INITRD
229 if (initrd_start)
230 ROOT_DEV = Root_RAM0;
231 else
232#endif
233#ifdef CONFIG_ROOT_NFS
234 ROOT_DEV = Root_NFS;
235#else
236 ROOT_DEV = Root_SDA2;
237#endif
238
239 /*
240 * Set up the L2CR register.
241 */
242 _set_L2CR(L2CR_L2E | L2CR_L2PE);
243
244 if (ppc_md.progress)
245 ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);
246
247 ev64360_setup_bridge();
248 ev64360_setup_peripherals();
249 ev64360_bus_frequency = ev64360_bus_freq();
250
251 printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
252 "(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
253 if (ppc_md.progress)
254 ppc_md.progress("ev64360_setup_arch: exit", 0);
255}
256
257/* Platform device data fixup routines. */
258#if defined(CONFIG_SERIAL_MPSC)
259static void __init
260ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
261{
262 struct mpsc_pdata *pdata;
263
264 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
265
266 pdata->max_idle = 40;
267 pdata->default_baud = EV64360_DEFAULT_BAUD;
268 pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
269 /*
270 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
271 * TCLK == SysCLK but on 64460, they are separate pins.
272 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
273 */
274 pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
275}
276#endif
277
278#if defined(CONFIG_MV643XX_ETH)
279static void __init
280ev64360_fixup_eth_pdata(struct platform_device *pdev)
281{
282 struct mv643xx_eth_platform_data *eth_pd;
283 static u16 phy_addr[] = {
284 EV64360_ETH0_PHY_ADDR,
285 EV64360_ETH1_PHY_ADDR,
286 EV64360_ETH2_PHY_ADDR,
287 };
288
289 eth_pd = pdev->dev.platform_data;
290 eth_pd->force_phy_addr = 1;
291 eth_pd->phy_addr = phy_addr[pdev->id];
292 eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
293 eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
294}
295#endif
296
297static int
298ev64360_platform_notify(struct device *dev)
299{
300 static struct {
301 char *bus_id;
302 void ((*rtn)(struct platform_device *pdev));
303 } dev_map[] = {
304#if defined(CONFIG_SERIAL_MPSC)
305 { MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
306 { MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
307#endif
308#if defined(CONFIG_MV643XX_ETH)
309 { MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
310 { MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
311 { MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
312#endif
313 };
314 struct platform_device *pdev;
315 int i;
316
317 if (dev && dev->bus_id)
318 for (i=0; i<ARRAY_SIZE(dev_map); i++)
319 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
320 BUS_ID_SIZE)) {
321
322 pdev = container_of(dev,
323 struct platform_device, dev);
324 dev_map[i].rtn(pdev);
325 }
326
327 return 0;
328}
329
330#ifdef CONFIG_MTD_PHYSMAP
331
332#ifndef MB
333#define MB (1 << 20)
334#endif
335
336/*
337 * MTD Layout.
338 *
339 * FLASH Amount: 0xff000000 - 0xffffffff
340 * ------------- -----------------------
341 * Reserved: 0xff000000 - 0xff03ffff
342 * JFFS2 file system: 0xff040000 - 0xffefffff
343 * U-boot: 0xfff00000 - 0xffffffff
344 */
345static int __init
346ev64360_setup_mtd(void)
347{
348 u32 size;
349 int ptbl_entries;
350 static struct mtd_partition *ptbl;
351
352 size = ev64360_flash_size_0 + ev64360_flash_size_1;
353 if (!size)
354 return -ENOMEM;
355
356 ptbl_entries = 3;
357
358 if ((ptbl = kzalloc(ptbl_entries * sizeof(struct mtd_partition),
359 GFP_KERNEL)) == NULL) {
360
361 printk(KERN_WARNING "Can't alloc MTD partition table\n");
362 return -ENOMEM;
363 }
364
365 ptbl[0].name = "reserved";
366 ptbl[0].offset = 0;
367 ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
368 ptbl[1].name = "jffs2";
369 ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
370 ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
371 ptbl[2].name = "U-BOOT";
372 ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
373 ptbl[2].size = EV64360_MTD_UBOOT_SIZE;
374
375 physmap_map.size = size;
376 physmap_set_partitions(ptbl, ptbl_entries);
377 return 0;
378}
379
380arch_initcall(ev64360_setup_mtd);
381#endif
382
383static void
384ev64360_restart(char *cmd)
385{
386 ulong i = 0xffffffff;
387 volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);
388
389 /* issue hard reset */
390 rtc_base[0xf] = 0x80;
391 rtc_base[0xc] = 0x00;
392 rtc_base[0xd] = 0x01;
393 rtc_base[0xf] = 0x83;
394
395 while (i-- > 0) ;
396 panic("restart failed\n");
397}
398
399static void
400ev64360_halt(void)
401{
402 while (1) ;
403 /* NOTREACHED */
404}
405
406static void
407ev64360_power_off(void)
408{
409 ev64360_halt();
410 /* NOTREACHED */
411}
412
413static int
414ev64360_show_cpuinfo(struct seq_file *m)
415{
416 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
417 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
418 seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);
419
420 return 0;
421}
422
423static void __init
424ev64360_calibrate_decr(void)
425{
426 u32 freq;
427
428 freq = ev64360_bus_frequency / 4;
429
430 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
431 (long)freq / 1000000, (long)freq % 1000000);
432
433 tb_ticks_per_jiffy = freq / HZ;
434 tb_to_us = mulhwu_scale_factor(freq, 1000000);
435}
436
437unsigned long __init
438ev64360_find_end_of_memory(void)
439{
440 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
441 MV64x60_TYPE_MV64360);
442}
443
444static inline void
445ev64360_set_bat(void)
446{
447 mb();
448 mtspr(SPRN_DBAT2U, 0xf0001ffe);
449 mtspr(SPRN_DBAT2L, 0xf000002a);
450 mb();
451}
452
453#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
454static void __init
455ev64360_map_io(void)
456{
457 io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
458 CONFIG_MV64X60_NEW_BASE, \
459 0x00020000, _PAGE_IO);
460}
461#endif
462
463void __init
464platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
465 unsigned long r6, unsigned long r7)
466{
467 parse_bootinfo(find_bootinfo());
468
469 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
470 * are non-zero, then we should use the board info from the bd_t
471 * structure and the cmdline pointed to by r6 instead of the
472 * information from birecs, if any. Otherwise, use the information
473 * from birecs as discovered by the preceding call to
474 * parse_bootinfo(). This rule should work with both PPCBoot, which
475 * uses a bd_t board info structure, and the kernel boot wrapper,
476 * which uses birecs.
477 */
478 if (r3 && r6) {
479 /* copy board info structure */
480 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
481 /* copy command line */
482 *(char *)(r7+KERNELBASE) = 0;
483 strcpy(cmd_line, (char *)(r6+KERNELBASE));
484 }
485 #ifdef CONFIG_ISA
486 isa_mem_base = 0;
487 #endif
488
489 ppc_md.setup_arch = ev64360_setup_arch;
490 ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
491 ppc_md.init_IRQ = mv64360_init_irq;
492 ppc_md.get_irq = mv64360_get_irq;
493 ppc_md.restart = ev64360_restart;
494 ppc_md.power_off = ev64360_power_off;
495 ppc_md.halt = ev64360_halt;
496 ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
497 ppc_md.init = NULL;
498
499 ppc_md.time_init = todc_time_init;
500 ppc_md.set_rtc_time = todc_set_rtc_time;
501 ppc_md.get_rtc_time = todc_get_rtc_time;
502 ppc_md.nvram_read_val = todc_direct_read_val;
503 ppc_md.nvram_write_val = todc_direct_write_val;
504 ppc_md.calibrate_decr = ev64360_calibrate_decr;
505
506#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
507 ppc_md.setup_io_mappings = ev64360_map_io;
508 ppc_md.progress = mv64x60_mpsc_progress;
509 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
510#endif
511
512#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
513 platform_notify = ev64360_platform_notify;
514#endif
515
516 ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
517}
diff --git a/arch/ppc/platforms/ev64360.h b/arch/ppc/platforms/ev64360.h
deleted file mode 100644
index b30f4722690a..000000000000
--- a/arch/ppc/platforms/ev64360.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * Definitions for Marvell EV-64360-BP Evaluation Board.
3 *
4 * Author: Lee Nicks <allinux@gmail.com>
5 *
6 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
7 * Based on code done by Mark A. Greer <mgreer@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/*
16 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
17 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
18 * We'll only use one PCI MEM window on each PCI bus.
19 *
20 * This is the CPU physical memory map (windows must be at least 64KB and start
21 * on a boundary that is a multiple of the window size):
22 *
23 * 0x42000000-0x4203ffff - Internal SRAM
24 * 0xf1000000-0xf100ffff - MV64360 Registers (CONFIG_MV64X60_NEW_BASE)
25 * 0xfc800000-0xfcffffff - RTC
26 * 0xff000000-0xffffffff - Boot window, 16 MB flash
27 * 0xc0000000-0xc3ffffff - PCI I/O (second hose)
28 * 0x80000000-0xbfffffff - PCI MEM (second hose)
29 */
30
31#ifndef __PPC_PLATFORMS_EV64360_H
32#define __PPC_PLATFORMS_EV64360_H
33
34/* CPU Physical Memory Map setup. */
35#define EV64360_BOOT_WINDOW_BASE 0xff000000
36#define EV64360_BOOT_WINDOW_SIZE 0x01000000 /* 16 MB */
37#define EV64360_INTERNAL_SRAM_BASE 0x42000000
38#define EV64360_RTC_WINDOW_BASE 0xfc800000
39#define EV64360_RTC_WINDOW_SIZE 0x00800000 /* 8 MB */
40
41#define EV64360_PCI1_MEM_START_PROC_ADDR 0x80000000
42#define EV64360_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
43#define EV64360_PCI1_MEM_START_PCI_LO_ADDR 0x80000000
44#define EV64360_PCI1_MEM_SIZE 0x40000000 /* 1 GB */
45#define EV64360_PCI1_IO_START_PROC_ADDR 0xc0000000
46#define EV64360_PCI1_IO_START_PCI_ADDR 0x00000000
47#define EV64360_PCI1_IO_SIZE 0x04000000 /* 64 MB */
48
49#define EV64360_DEFAULT_BAUD 115200
50#define EV64360_MPSC_CLK_SRC 8 /* TCLK */
51#define EV64360_MPSC_CLK_FREQ 133333333
52
53#define EV64360_MTD_RESERVED_SIZE 0x40000
54#define EV64360_MTD_JFFS2_SIZE 0xec0000
55#define EV64360_MTD_UBOOT_SIZE 0x100000
56
57#define EV64360_ETH0_PHY_ADDR 8
58#define EV64360_ETH1_PHY_ADDR 9
59#define EV64360_ETH2_PHY_ADDR 10
60
61#define EV64360_ETH_TX_QUEUE_SIZE 800
62#define EV64360_ETH_RX_QUEUE_SIZE 400
63
64#define EV64360_ETH_PORT_CONFIG_VALUE \
65 ETH_UNICAST_NORMAL_MODE | \
66 ETH_DEFAULT_RX_QUEUE_0 | \
67 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
68 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
69 ETH_RECEIVE_BC_IF_IP | \
70 ETH_RECEIVE_BC_IF_ARP | \
71 ETH_CAPTURE_TCP_FRAMES_DIS | \
72 ETH_CAPTURE_UDP_FRAMES_DIS | \
73 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
74 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
75 ETH_DEFAULT_RX_BPDU_QUEUE_0
76
77#define EV64360_ETH_PORT_CONFIG_EXTEND_VALUE \
78 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
79 ETH_PARTITION_DISABLE
80
81#define GT_ETH_IPG_INT_RX(value) \
82 ((value & 0x3fff) << 8)
83
84#define EV64360_ETH_PORT_SDMA_CONFIG_VALUE \
85 ETH_RX_BURST_SIZE_4_64BIT | \
86 GT_ETH_IPG_INT_RX(0) | \
87 ETH_TX_BURST_SIZE_4_64BIT
88
89#define EV64360_ETH_PORT_SERIAL_CONTROL_VALUE \
90 ETH_FORCE_LINK_PASS | \
91 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
92 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
93 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
94 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
95 ETH_FORCE_BP_MODE_NO_JAM | \
96 BIT9 | \
97 ETH_DO_NOT_FORCE_LINK_FAIL | \
98 ETH_RETRANSMIT_16_ATTEMPTS | \
99 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
100 ETH_DTE_ADV_0 | \
101 ETH_DISABLE_AUTO_NEG_BYPASS | \
102 ETH_AUTO_NEG_NO_CHANGE | \
103 ETH_MAX_RX_PACKET_9700BYTE | \
104 ETH_CLR_EXT_LOOPBACK | \
105 ETH_SET_FULL_DUPLEX_MODE | \
106 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
107
108static inline u32
109ev64360_bus_freq(void)
110{
111 return 133333333;
112}
113
114#endif /* __PPC_PLATFORMS_EV64360_H */
diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h
deleted file mode 100644
index 5219366667b3..000000000000
--- a/arch/ppc/platforms/fads.h
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 *
5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
6 *
7 * Added MPC86XADS support.
8 * The MPC86xADS manual says the board "is compatible with the MPC8xxFADS
9 * for SW point of view". This is 99% correct.
10 *
11 * Author: MontaVista Software, Inc.
12 * source@mvista.com
13 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
14 * terms of the GNU General Public License version 2. This program is licensed
15 * "as is" without any warranty of any kind, whether express or implied.
16 */
17
18#ifdef __KERNEL__
19#ifndef __ASM_FADS_H__
20#define __ASM_FADS_H__
21
22
23#include <asm/ppcboot.h>
24
25/* Memory map is configured by the PROM startup.
26 * I tried to follow the FADS manual, although the startup PROM
27 * dictates this and we simply have to move some of the physical
28 * addresses for Linux.
29 */
30#define BCSR_ADDR ((uint)0xff010000)
31
32/* PHY link change interrupt */
33#define PHY_INTERRUPT SIU_IRQ2
34
35#define BCSR_SIZE ((uint)(64 * 1024))
36#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
37#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
38#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
39#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
40#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
41
42#define IMAP_ADDR ((uint)0xff000000)
43#define IMAP_SIZE ((uint)(64 * 1024))
44
45#define PCMCIA_MEM_ADDR ((uint)0xff020000)
46#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
47
48/* Bits of interest in the BCSRs.
49 */
50#define BCSR1_ETHEN ((uint)0x20000000)
51#define BCSR1_IRDAEN ((uint)0x10000000)
52#define BCSR1_RS232EN_1 ((uint)0x01000000)
53#define BCSR1_PCCEN ((uint)0x00800000)
54#define BCSR1_PCCVCC0 ((uint)0x00400000)
55#define BCSR1_PCCVPP0 ((uint)0x00200000)
56#define BCSR1_PCCVPP1 ((uint)0x00100000)
57#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
58#define BCSR1_RS232EN_2 ((uint)0x00040000)
59#define BCSR1_PCCVCC1 ((uint)0x00010000)
60#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
61
62#define BCSR4_ETHLOOP ((uint)0x80000000) /* EEST Loopback */
63#define BCSR4_EEFDX ((uint)0x40000000) /* EEST FDX enable */
64#define BCSR4_FETH_EN ((uint)0x08000000) /* PHY enable */
65#define BCSR4_FETHCFG0 ((uint)0x04000000) /* PHY autoneg mode */
66#define BCSR4_FETHCFG1 ((uint)0x00400000) /* PHY autoneg mode */
67#define BCSR4_FETHFDE ((uint)0x02000000) /* PHY FDX advertise */
68#define BCSR4_FETHRST ((uint)0x00200000) /* PHY Reset */
69
70/* IO_BASE definition for pcmcia.
71 */
72#define _IO_BASE 0x80000000
73#define _IO_BASE_SIZE 0x1000
74
75#ifdef CONFIG_IDE
76#define MAX_HWIFS 1
77#endif
78
79/* Interrupt level assignments.
80 */
81#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
82
83/* We don't use the 8259.
84 */
85#define NR_8259_INTS 0
86
87/* CPM Ethernet through SCC1 or SCC2 */
88
89#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */
90/* Bits in parallel I/O port registers that have to be set/cleared
91 * to configure the pins for SCC1 use.
92 * TCLK - CLK1, RCLK - CLK2.
93 */
94#define PA_ENET_RXD ((ushort)0x0001)
95#define PA_ENET_TXD ((ushort)0x0002)
96#define PA_ENET_TCLK ((ushort)0x0100)
97#define PA_ENET_RCLK ((ushort)0x0200)
98#define PB_ENET_TENA ((uint)0x00001000)
99#define PC_ENET_CLSN ((ushort)0x0010)
100#define PC_ENET_RENA ((ushort)0x0020)
101
102/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
103 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
104 */
105#define SICR_ENET_MASK ((uint)0x000000ff)
106#define SICR_ENET_CLKRT ((uint)0x0000002c)
107#endif /* CONFIG_SCC1_ENET */
108
109#ifdef CONFIG_SCC2_ENET /* Probably 823/850 variant */
110/* Bits in parallel I/O port registers that have to be set/cleared
111 * to configure the pins for SCC1 use.
112 * TCLK - CLK1, RCLK - CLK2.
113 */
114#define PA_ENET_RXD ((ushort)0x0004)
115#define PA_ENET_TXD ((ushort)0x0008)
116#define PA_ENET_TCLK ((ushort)0x0400)
117#define PA_ENET_RCLK ((ushort)0x0200)
118#define PB_ENET_TENA ((uint)0x00002000)
119#define PC_ENET_CLSN ((ushort)0x0040)
120#define PC_ENET_RENA ((ushort)0x0080)
121
122/* Control bits in the SICR to route TCLK and RCLK to
123 * SCC2. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
124 */
125#define SICR_ENET_MASK ((uint)0x0000ff00)
126#define SICR_ENET_CLKRT ((uint)0x00002e00)
127#endif /* CONFIG_SCC2_ENET */
128
129#endif /* __ASM_FADS_H__ */
130#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c
deleted file mode 100644
index 904b518c152e..000000000000
--- a/arch/ppc/platforms/hdpu.c
+++ /dev/null
@@ -1,1015 +0,0 @@
1/*
2 * Board setup routines for the Sky Computers HDPU Compute Blade.
3 *
4 * Written by Brian Waite <waite@skycomputers.com>
5 *
6 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
7 * Rabeeh Khoury - rabeeh@galileo.co.il
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/irq.h>
19#include <linux/seq_file.h>
20#include <linux/platform_device.h>
21
22#include <linux/initrd.h>
23#include <linux/root_dev.h>
24#include <linux/smp.h>
25
26#include <asm/time.h>
27#include <asm/machdep.h>
28#include <asm/todc.h>
29#include <asm/mv64x60.h>
30#include <asm/ppcboot.h>
31#include <platforms/hdpu.h>
32#include <linux/mv643xx.h>
33#include <linux/hdpu_features.h>
34#include <linux/device.h>
35#include <linux/mtd/physmap.h>
36
37#define BOARD_VENDOR "Sky Computers"
38#define BOARD_MACHINE "HDPU-CB-A"
39
40bd_t ppcboot_bd;
41int ppcboot_bd_valid = 0;
42
43static mv64x60_handle_t bh;
44
45extern char cmd_line[];
46
47unsigned long hdpu_find_end_of_memory(void);
48void hdpu_mpsc_progress(char *s, unsigned short hex);
49void hdpu_heartbeat(void);
50
51static void parse_bootinfo(unsigned long r3,
52 unsigned long r4, unsigned long r5,
53 unsigned long r6, unsigned long r7);
54static void hdpu_set_l1pe(void);
55static void hdpu_cpustate_set(unsigned char new_state);
56#ifdef CONFIG_SMP
57static DEFINE_SPINLOCK(timebase_lock);
58static unsigned int timebase_upper = 0, timebase_lower = 0;
59extern int smp_tb_synchronized;
60
61void __devinit hdpu_tben_give(void);
62void __devinit hdpu_tben_take(void);
63#endif
64
65static int __init
66hdpu_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
67{
68 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
69
70 if (hose->index == 0) {
71 static char pci_irq_table[][4] = {
72 {HDPU_PCI_0_IRQ, 0, 0, 0},
73 {HDPU_PCI_0_IRQ, 0, 0, 0},
74 };
75
76 const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
77 return PCI_IRQ_TABLE_LOOKUP;
78 } else {
79 static char pci_irq_table[][4] = {
80 {HDPU_PCI_1_IRQ, 0, 0, 0},
81 };
82
83 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
84 return PCI_IRQ_TABLE_LOOKUP;
85 }
86}
87
88static void __init hdpu_intr_setup(void)
89{
90 mv64x60_write(&bh, MV64x60_GPP_IO_CNTL,
91 (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
92 (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
93 (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
94 (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
95 (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
96
97 /* XXXX Erranum FEr PCI-#8 */
98 mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1 << 5) | (1 << 9));
99 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1 << 5) | (1 << 9));
100
101 /*
102 * Dismiss and then enable interrupt on GPP interrupt cause
103 * for CPU #0
104 */
105 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~((1 << 8) | (1 << 13)));
106 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13));
107
108 /*
109 * Dismiss and then enable interrupt on CPU #0 high cause reg
110 * BIT25 summarizes GPP interrupts 8-15
111 */
112 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1 << 25));
113}
114
115static void __init hdpu_setup_peripherals(void)
116{
117 unsigned int val;
118
119 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
120 HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
121 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
122
123 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
124 HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0);
125 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
126
127 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
128 HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0);
129 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
130
131 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
132 HDPU_INTERNAL_SRAM_BASE,
133 HDPU_INTERNAL_SRAM_SIZE, 0);
134 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
135
136 bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
137 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0);
138
139 mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3));
140 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
141 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
142 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
143
144 /* Enable pipelining */
145 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
146 /* Enable Snoop Pipelining */
147 mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
148
149 /*
150 * Change DRAM read buffer assignment.
151 * Assign read buffer 0 dedicated only for CPU,
152 * and the rest read buffer 1.
153 */
154 val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG);
155 val = val & 0x03ffffff;
156 val = val | 0xf8000000;
157 mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val);
158
159 /*
160 * Configure internal SRAM -
161 * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
162 * Parity enabled.
163 * Parity error propagation
164 * Arbitration not parked for CPU only
165 * Other bits are reserved.
166 */
167#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
168 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
169#else
170 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
171#endif
172
173 hdpu_intr_setup();
174}
175
176static void __init hdpu_setup_bridge(void)
177{
178 struct mv64x60_setup_info si;
179 int i;
180
181 memset(&si, 0, sizeof(si));
182
183 si.phys_reg_base = HDPU_BRIDGE_REG_BASE;
184 si.pci_0.enable_bus = 1;
185 si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR;
186 si.pci_0.pci_io.pci_base_hi = 0;
187 si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR;
188 si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE;
189 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
190 si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR;
191 si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR;
192 si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR;
193 si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE;
194 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
195 si.pci_0.pci_cmd_bits = 0;
196 si.pci_0.latency_timer = 0x80;
197
198 si.pci_1.enable_bus = 1;
199 si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR;
200 si.pci_1.pci_io.pci_base_hi = 0;
201 si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR;
202 si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE;
203 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
204 si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR;
205 si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR;
206 si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR;
207 si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE;
208 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
209 si.pci_1.pci_cmd_bits = 0;
210 si.pci_1.latency_timer = 0x80;
211
212 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
213#if defined(CONFIG_NOT_COHERENT_CACHE)
214 si.cpu_prot_options[i] = 0;
215 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
216 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
217 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
218
219 si.pci_1.acc_cntl_options[i] =
220 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
221 MV64360_PCI_ACC_CNTL_SWAP_NONE |
222 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
223 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
224
225 si.pci_0.acc_cntl_options[i] =
226 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
227 MV64360_PCI_ACC_CNTL_SWAP_NONE |
228 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
229 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
230
231#else
232 si.cpu_prot_options[i] = 0;
233 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; /* errata */
234 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; /* errata */
235 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; /* errata */
236
237 si.pci_0.acc_cntl_options[i] =
238 MV64360_PCI_ACC_CNTL_SNOOP_WB |
239 MV64360_PCI_ACC_CNTL_SWAP_NONE |
240 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
241 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
242
243 si.pci_1.acc_cntl_options[i] =
244 MV64360_PCI_ACC_CNTL_SNOOP_WB |
245 MV64360_PCI_ACC_CNTL_SWAP_NONE |
246 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
247 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
248#endif
249 }
250
251 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
252
253 /* Lookup PCI host bridges */
254 mv64x60_init(&bh, &si);
255 pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
256 ppc_md.pci_swizzle = common_swizzle;
257 ppc_md.pci_map_irq = hdpu_map_irq;
258
259 mv64x60_set_bus(&bh, 0, 0);
260 bh.hose_a->first_busno = 0;
261 bh.hose_a->last_busno = 0xff;
262 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
263
264 bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
265 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
266 bh.hose_b->last_busno = 0xff;
267 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
268 bh.hose_b->first_busno);
269
270 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
271
272 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
273 /*
274 * Enabling of PCI internal-vs-external arbitration
275 * is a platform- and errata-dependent decision.
276 */
277 return;
278}
279
280#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
281static void __init hdpu_early_serial_map(void)
282{
283#ifdef CONFIG_KGDB
284 static char first_time = 1;
285
286#if defined(CONFIG_KGDB_TTYS0)
287#define KGDB_PORT 0
288#elif defined(CONFIG_KGDB_TTYS1)
289#define KGDB_PORT 1
290#else
291#error "Invalid kgdb_tty port"
292#endif
293
294 if (first_time) {
295 gt_early_mpsc_init(KGDB_PORT,
296 B9600 | CS8 | CREAD | HUPCL | CLOCAL);
297 first_time = 0;
298 }
299
300 return;
301#endif
302}
303#endif
304
305static void hdpu_init2(void)
306{
307 return;
308}
309
310#if defined(CONFIG_MV643XX_ETH)
311static void __init hdpu_fixup_eth_pdata(struct platform_device *pd)
312{
313
314 struct mv643xx_eth_platform_data *eth_pd;
315 eth_pd = pd->dev.platform_data;
316
317 eth_pd->force_phy_addr = 1;
318 eth_pd->phy_addr = pd->id;
319 eth_pd->speed = SPEED_100;
320 eth_pd->duplex = DUPLEX_FULL;
321 eth_pd->tx_queue_size = 400;
322 eth_pd->rx_queue_size = 800;
323}
324#endif
325
326static void __init hdpu_fixup_mpsc_pdata(struct platform_device *pd)
327{
328
329 struct mpsc_pdata *pdata;
330
331 pdata = (struct mpsc_pdata *)pd->dev.platform_data;
332
333 pdata->max_idle = 40;
334 if (ppcboot_bd_valid)
335 pdata->default_baud = ppcboot_bd.bi_baudrate;
336 else
337 pdata->default_baud = HDPU_DEFAULT_BAUD;
338 pdata->brg_clk_src = HDPU_MPSC_CLK_SRC;
339 pdata->brg_clk_freq = HDPU_MPSC_CLK_FREQ;
340}
341
342#if defined(CONFIG_HDPU_FEATURES)
343static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd)
344{
345 struct platform_device *pds[1];
346 pds[0] = pd;
347 mv64x60_pd_fixup(&bh, pds, 1);
348}
349#endif
350
351static int hdpu_platform_notify(struct device *dev)
352{
353 static struct {
354 char *bus_id;
355 void ((*rtn) (struct platform_device * pdev));
356 } dev_map[] = {
357 {
358 MPSC_CTLR_NAME ".0", hdpu_fixup_mpsc_pdata},
359#if defined(CONFIG_MV643XX_ETH)
360 {
361 MV643XX_ETH_NAME ".0", hdpu_fixup_eth_pdata},
362#endif
363#if defined(CONFIG_HDPU_FEATURES)
364 {
365 HDPU_CPUSTATE_NAME ".0", hdpu_fixup_cpustate_pdata},
366#endif
367 };
368 struct platform_device *pdev;
369 int i;
370
371 if (dev && dev->bus_id)
372 for (i = 0; i < ARRAY_SIZE(dev_map); i++)
373 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
374 BUS_ID_SIZE)) {
375
376 pdev = container_of(dev,
377 struct platform_device,
378 dev);
379 dev_map[i].rtn(pdev);
380 }
381
382 return 0;
383}
384
385static void __init hdpu_setup_arch(void)
386{
387 if (ppc_md.progress)
388 ppc_md.progress("hdpu_setup_arch: enter", 0);
389#ifdef CONFIG_BLK_DEV_INITRD
390 if (initrd_start)
391 ROOT_DEV = Root_RAM0;
392 else
393#endif
394#ifdef CONFIG_ROOT_NFS
395 ROOT_DEV = Root_NFS;
396#else
397 ROOT_DEV = Root_SDA2;
398#endif
399
400 ppc_md.heartbeat = hdpu_heartbeat;
401
402 ppc_md.heartbeat_reset = HZ;
403 ppc_md.heartbeat_count = 1;
404
405 if (ppc_md.progress)
406 ppc_md.progress("hdpu_setup_arch: Enabling L2 cache", 0);
407
408 /* Enable L1 Parity Bits */
409 hdpu_set_l1pe();
410
411 /* Enable L2 and L3 caches (if 745x) */
412 _set_L2CR(0x80080000);
413
414 if (ppc_md.progress)
415 ppc_md.progress("hdpu_setup_arch: enter", 0);
416
417 hdpu_setup_bridge();
418
419 hdpu_setup_peripherals();
420
421#ifdef CONFIG_SERIAL_MPSC_CONSOLE
422 hdpu_early_serial_map();
423#endif
424
425 printk("SKY HDPU Compute Blade \n");
426
427 if (ppc_md.progress)
428 ppc_md.progress("hdpu_setup_arch: exit", 0);
429
430 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK);
431 return;
432}
433static void __init hdpu_init_irq(void)
434{
435 mv64360_init_irq();
436}
437
438static void __init hdpu_set_l1pe()
439{
440 unsigned long ictrl;
441 asm volatile ("mfspr %0, 1011":"=r" (ictrl):);
442 ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP;
443 asm volatile ("mtspr 1011, %0"::"r" (ictrl));
444}
445
446/*
447 * Set BAT 1 to map 0xf1000000 to end of physical memory space.
448 */
449static __inline__ void hdpu_set_bat(void)
450{
451 mb();
452 mtspr(SPRN_DBAT1U, 0xf10001fe);
453 mtspr(SPRN_DBAT1L, 0xf100002a);
454 mb();
455
456 return;
457}
458
459unsigned long __init hdpu_find_end_of_memory(void)
460{
461 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
462 MV64x60_TYPE_MV64360);
463}
464
465static void hdpu_reset_board(void)
466{
467 volatile int infinite = 1;
468
469 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET);
470
471 local_irq_disable();
472
473 /* Clear all the LEDs */
474 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) |
475 (1 << 5) | (1 << 6)));
476
477 /* disable and invalidate the L2 cache */
478 _set_L2CR(0);
479 _set_L2CR(0x200000);
480
481 /* flush and disable L1 I/D cache */
482 __asm__ __volatile__
483 ("\n"
484 "mfspr 3,1008\n"
485 "ori 5,5,0xcc00\n"
486 "ori 4,3,0xc00\n"
487 "andc 5,3,5\n"
488 "sync\n"
489 "mtspr 1008,4\n"
490 "isync\n" "sync\n" "mtspr 1008,5\n" "isync\n" "sync\n");
491
492 /* Hit the reset bit */
493 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 3));
494
495 while (infinite)
496 infinite = infinite;
497
498 return;
499}
500
501static void hdpu_restart(char *cmd)
502{
503 volatile ulong i = 10000000;
504
505 hdpu_reset_board();
506
507 while (i-- > 0) ;
508 panic("restart failed\n");
509}
510
511static void hdpu_halt(void)
512{
513 local_irq_disable();
514
515 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT);
516
517 /* Clear all the LEDs */
518 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | (1 << 5) |
519 (1 << 6)));
520 while (1) ;
521 /* NOTREACHED */
522}
523
524static void hdpu_power_off(void)
525{
526 hdpu_halt();
527 /* NOTREACHED */
528}
529
530static int hdpu_show_cpuinfo(struct seq_file *m)
531{
532 uint pvid;
533
534 pvid = mfspr(SPRN_PVR);
535 seq_printf(m, "vendor\t\t: Sky Computers\n");
536 seq_printf(m, "machine\t\t: HDPU Compute Blade\n");
537 seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
538 pvid, (pvid & (1 << 15) ? "IBM" : "Motorola"));
539
540 return 0;
541}
542
543static void __init hdpu_calibrate_decr(void)
544{
545 ulong freq;
546
547 if (ppcboot_bd_valid)
548 freq = ppcboot_bd.bi_busfreq / 4;
549 else
550 freq = 133000000;
551
552 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
553 freq / 1000000, freq % 1000000);
554
555 tb_ticks_per_jiffy = freq / HZ;
556 tb_to_us = mulhwu_scale_factor(freq, 1000000);
557
558 return;
559}
560
561static void parse_bootinfo(unsigned long r3,
562 unsigned long r4, unsigned long r5,
563 unsigned long r6, unsigned long r7)
564{
565 bd_t *bd = NULL;
566 char *cmdline_start = NULL;
567 int cmdline_len = 0;
568
569 if (r3) {
570 if ((r3 & 0xf0000000) == 0)
571 r3 += KERNELBASE;
572 if ((r3 & 0xf0000000) == KERNELBASE) {
573 bd = (void *)r3;
574
575 memcpy(&ppcboot_bd, bd, sizeof(ppcboot_bd));
576 ppcboot_bd_valid = 1;
577 }
578 }
579#ifdef CONFIG_BLK_DEV_INITRD
580 if (r4 && r5 && r5 > r4) {
581 if ((r4 & 0xf0000000) == 0)
582 r4 += KERNELBASE;
583 if ((r5 & 0xf0000000) == 0)
584 r5 += KERNELBASE;
585 if ((r4 & 0xf0000000) == KERNELBASE) {
586 initrd_start = r4;
587 initrd_end = r5;
588 initrd_below_start_ok = 1;
589 }
590 }
591#endif /* CONFIG_BLK_DEV_INITRD */
592
593 if (r6 && r7 && r7 > r6) {
594 if ((r6 & 0xf0000000) == 0)
595 r6 += KERNELBASE;
596 if ((r7 & 0xf0000000) == 0)
597 r7 += KERNELBASE;
598 if ((r6 & 0xf0000000) == KERNELBASE) {
599 cmdline_start = (void *)r6;
600 cmdline_len = (r7 - r6);
601 strncpy(cmd_line, cmdline_start, cmdline_len);
602 }
603 }
604}
605
606void hdpu_heartbeat(void)
607{
608 if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5))
609 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 5));
610 else
611 mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, (1 << 5));
612
613 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
614
615}
616
617static void __init hdpu_map_io(void)
618{
619 io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO);
620}
621
622#ifdef CONFIG_SMP
623char hdpu_smp0[] = "SMP Cpu #0";
624char hdpu_smp1[] = "SMP Cpu #1";
625
626static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id)
627{
628 volatile unsigned int doorbell;
629
630 doorbell = mv64x60_read(&bh, MV64360_CPU0_DOORBELL);
631
632 /* Ack the doorbell interrupts */
633 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell);
634
635 if (doorbell & 1) {
636 smp_message_recv(0);
637 }
638 if (doorbell & 2) {
639 smp_message_recv(1);
640 }
641 if (doorbell & 4) {
642 smp_message_recv(2);
643 }
644 if (doorbell & 8) {
645 smp_message_recv(3);
646 }
647 return IRQ_HANDLED;
648}
649
650static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id)
651{
652 volatile unsigned int doorbell;
653
654 doorbell = mv64x60_read(&bh, MV64360_CPU1_DOORBELL);
655
656 /* Ack the doorbell interrupts */
657 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell);
658
659 if (doorbell & 1) {
660 smp_message_recv(0);
661 }
662 if (doorbell & 2) {
663 smp_message_recv(1);
664 }
665 if (doorbell & 4) {
666 smp_message_recv(2);
667 }
668 if (doorbell & 8) {
669 smp_message_recv(3);
670 }
671 return IRQ_HANDLED;
672}
673
674static void smp_hdpu_CPU_two(void)
675{
676 __asm__ __volatile__
677 ("\n"
678 "lis 3,0x0000\n"
679 "ori 3,3,0x00c0\n"
680 "mtspr 26, 3\n" "li 4,0\n" "mtspr 27,4\n" "rfi");
681
682}
683
684static int smp_hdpu_probe(void)
685{
686 int *cpu_count_reg;
687 int num_cpus = 0;
688
689 cpu_count_reg = ioremap(HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE);
690 if (cpu_count_reg) {
691 num_cpus = (*cpu_count_reg >> 20) & 0x3;
692 iounmap(cpu_count_reg);
693 }
694
695 /* Validate the bits in the CPLD. If we could not map the reg, return 2.
696 * If the register reported 0 or 3, return 2.
697 * Older CPLD revisions set these bits to all ones (val = 3).
698 */
699 if ((num_cpus < 1) || (num_cpus > 2)) {
700 printk
701 ("Unable to determine the number of processors %d . deafulting to 2.\n",
702 num_cpus);
703 num_cpus = 2;
704 }
705 return num_cpus;
706}
707
708static void
709smp_hdpu_message_pass(int target, int msg)
710{
711 if (msg > 0x3) {
712 printk("SMP %d: smp_message_pass: unknown msg %d\n",
713 smp_processor_id(), msg);
714 return;
715 }
716 switch (target) {
717 case MSG_ALL:
718 mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
719 mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
720 break;
721 case MSG_ALL_BUT_SELF:
722 if (smp_processor_id())
723 mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
724 else
725 mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
726 break;
727 default:
728 if (target == 0)
729 mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
730 else
731 mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
732 break;
733 }
734}
735
736static void smp_hdpu_kick_cpu(int nr)
737{
738 volatile unsigned int *bootaddr;
739
740 if (ppc_md.progress)
741 ppc_md.progress("smp_hdpu_kick_cpu", 0);
742
743 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK);
744
745 /* Disable BootCS. Must also reduce the windows size to zero. */
746 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
747 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0, 0, 0);
748
749 bootaddr = ioremap(HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE);
750 if (!bootaddr) {
751 if (ppc_md.progress)
752 ppc_md.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
753 return;
754 }
755
756 memcpy((void *)(bootaddr + 0x40), (void *)&smp_hdpu_CPU_two, 0x20);
757
758 /* map SRAM to 0xfff00000 */
759 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
760
761 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
762 0xfff00000, HDPU_INTERNAL_SRAM_SIZE, 0);
763 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
764
765 /* Enable CPU1 arbitration */
766 mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1 << 9));
767
768 /*
769 * Wait 100mSecond until other CPU has reached __secondary_start.
770 * When it reaches, it is permittable to rever the SRAM mapping etc...
771 */
772 mdelay(100);
773 *(unsigned long *)KERNELBASE = nr;
774 asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
775
776 iounmap(bootaddr);
777
778 /* Set up window for internal sram (256KByte insize) */
779 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
780 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
781 HDPU_INTERNAL_SRAM_BASE,
782 HDPU_INTERNAL_SRAM_SIZE, 0);
783 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
784 /*
785 * Set up windows for embedded FLASH (using boot CS window).
786 */
787
788 bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
789 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
790 HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
791 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
792}
793
794static void smp_hdpu_setup_cpu(int cpu_nr)
795{
796 if (cpu_nr == 0) {
797 if (ppc_md.progress)
798 ppc_md.progress("smp_hdpu_setup_cpu 0", 0);
799 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
800 mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
801 request_irq(60, hdpu_smp_cpu0_int_handler,
802 IRQF_DISABLED, hdpu_smp0, 0);
803 }
804
805 if (cpu_nr == 1) {
806 if (ppc_md.progress)
807 ppc_md.progress("smp_hdpu_setup_cpu 1", 0);
808
809 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR |
810 CPUSTATE_KERNEL_CPU1_OK);
811
812 /* Enable L1 Parity Bits */
813 hdpu_set_l1pe();
814
815 /* Enable L2 cache */
816 _set_L2CR(0);
817 _set_L2CR(0x80080000);
818
819 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
820 mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
821 request_irq(28, hdpu_smp_cpu1_int_handler,
822 IRQF_DISABLED, hdpu_smp1, 0);
823 }
824
825}
826
827void __devinit hdpu_tben_give()
828{
829 volatile unsigned long *val = 0;
830
831 /* By writing 0 to the TBEN_BASE, the timebases is frozen */
832 val = ioremap(HDPU_TBEN_BASE, 4);
833 *val = 0;
834 mb();
835
836 spin_lock(&timebase_lock);
837 timebase_upper = get_tbu();
838 timebase_lower = get_tbl();
839 spin_unlock(&timebase_lock);
840
841 while (timebase_upper || timebase_lower)
842 barrier();
843
844 /* By writing 1 to the TBEN_BASE, the timebases is thawed */
845 *val = 1;
846 mb();
847
848 iounmap(val);
849
850}
851
852void __devinit hdpu_tben_take()
853{
854 while (!(timebase_upper || timebase_lower))
855 barrier();
856
857 spin_lock(&timebase_lock);
858 set_tb(timebase_upper, timebase_lower);
859 timebase_upper = 0;
860 timebase_lower = 0;
861 spin_unlock(&timebase_lock);
862}
863
864static struct smp_ops_t hdpu_smp_ops = {
865 .message_pass = smp_hdpu_message_pass,
866 .probe = smp_hdpu_probe,
867 .kick_cpu = smp_hdpu_kick_cpu,
868 .setup_cpu = smp_hdpu_setup_cpu,
869 .give_timebase = hdpu_tben_give,
870 .take_timebase = hdpu_tben_take,
871};
872#endif /* CONFIG_SMP */
873
874void __init
875platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
876 unsigned long r6, unsigned long r7)
877{
878 parse_bootinfo(r3, r4, r5, r6, r7);
879
880 isa_mem_base = 0;
881
882 ppc_md.setup_arch = hdpu_setup_arch;
883 ppc_md.init = hdpu_init2;
884 ppc_md.show_cpuinfo = hdpu_show_cpuinfo;
885 ppc_md.init_IRQ = hdpu_init_irq;
886 ppc_md.get_irq = mv64360_get_irq;
887 ppc_md.restart = hdpu_restart;
888 ppc_md.power_off = hdpu_power_off;
889 ppc_md.halt = hdpu_halt;
890 ppc_md.find_end_of_memory = hdpu_find_end_of_memory;
891 ppc_md.calibrate_decr = hdpu_calibrate_decr;
892 ppc_md.setup_io_mappings = hdpu_map_io;
893
894 bh.p_base = CONFIG_MV64X60_NEW_BASE;
895 bh.v_base = (unsigned long *)bh.p_base;
896
897 hdpu_set_bat();
898
899#if defined(CONFIG_SERIAL_TEXT_DEBUG)
900 ppc_md.progress = hdpu_mpsc_progress; /* embedded UART */
901 mv64x60_progress_init(bh.p_base);
902#endif /* CONFIG_SERIAL_TEXT_DEBUG */
903
904#ifdef CONFIG_SMP
905 smp_ops = &hdpu_smp_ops;
906#endif /* CONFIG_SMP */
907
908#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
909 platform_notify = hdpu_platform_notify;
910#endif
911 return;
912}
913
914#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
915/* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
916void hdpu_mpsc_progress(char *s, unsigned short hex)
917{
918 while (mv64x60_read(&bh, MV64360_WHO_AM_I) !=
919 mv64x60_read(&bh, MV64360_SEMAPHORE_0)) {
920 }
921 mv64x60_mpsc_progress(s, hex);
922 mv64x60_write(&bh, MV64360_SEMAPHORE_0, 0xff);
923}
924#endif
925
926static void hdpu_cpustate_set(unsigned char new_state)
927{
928 unsigned int state = (new_state << 21);
929 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21));
930 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state);
931}
932
933#ifdef CONFIG_MTD_PHYSMAP
934static struct mtd_partition hdpu_partitions[] = {
935 {
936 .name = "Root FS",
937 .size = 0x03400000,
938 .offset = 0,
939 .mask_flags = 0,
940 },{
941 .name = "User FS",
942 .size = 0x00800000,
943 .offset = 0x03400000,
944 .mask_flags = 0,
945 },{
946 .name = "Kernel Image",
947 .size = 0x002C0000,
948 .offset = 0x03C00000,
949 .mask_flags = 0,
950 },{
951 .name = "bootEnv",
952 .size = 0x00040000,
953 .offset = 0x03EC0000,
954 .mask_flags = 0,
955 },{
956 .name = "bootROM",
957 .size = 0x00100000,
958 .offset = 0x03F00000,
959 .mask_flags = 0,
960 }
961};
962
963static int __init hdpu_setup_mtd(void)
964{
965
966 physmap_set_partitions(hdpu_partitions, 5);
967 return 0;
968}
969
970arch_initcall(hdpu_setup_mtd);
971#endif
972
973#ifdef CONFIG_HDPU_FEATURES
974
975static struct resource hdpu_cpustate_resources[] = {
976 [0] = {
977 .name = "addr base",
978 .start = MV64x60_GPP_VALUE_SET,
979 .end = MV64x60_GPP_VALUE_CLR + 1,
980 .flags = IORESOURCE_MEM,
981 },
982};
983
984static struct resource hdpu_nexus_resources[] = {
985 [0] = {
986 .name = "nexus register",
987 .start = HDPU_NEXUS_ID_BASE,
988 .end = HDPU_NEXUS_ID_BASE + HDPU_NEXUS_ID_SIZE,
989 .flags = IORESOURCE_MEM,
990 },
991};
992
993static struct platform_device hdpu_cpustate_device = {
994 .name = HDPU_CPUSTATE_NAME,
995 .id = 0,
996 .num_resources = ARRAY_SIZE(hdpu_cpustate_resources),
997 .resource = hdpu_cpustate_resources,
998};
999
1000static struct platform_device hdpu_nexus_device = {
1001 .name = HDPU_NEXUS_NAME,
1002 .id = 0,
1003 .num_resources = ARRAY_SIZE(hdpu_nexus_resources),
1004 .resource = hdpu_nexus_resources,
1005};
1006
1007static int __init hdpu_add_pds(void)
1008{
1009 platform_device_register(&hdpu_cpustate_device);
1010 platform_device_register(&hdpu_nexus_device);
1011 return 0;
1012}
1013
1014arch_initcall(hdpu_add_pds);
1015#endif
diff --git a/arch/ppc/platforms/hdpu.h b/arch/ppc/platforms/hdpu.h
deleted file mode 100644
index f9e020b6970c..000000000000
--- a/arch/ppc/platforms/hdpu.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Definitions for Sky Computers HDPU board.
3 *
4 * Brian Waite <waite@skycomputers.com>
5 *
6 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
7 * Based on code done by Mark A. Greer <mgreer@mvista.com>
8 * Based on code done by Tim Montgomery <timm@artesyncp.com>
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/*
18 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
19 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
20 * We'll only use one PCI MEM window on each PCI bus.
21 *
22 * This is the CPU physical memory map (windows must be at least 64K and start
23 * on a boundary that is a multiple of the window size):
24 *
25 * 0x80000000-0x8fffffff - PCI 0 MEM
26 * 0xa0000000-0xafffffff - PCI 1 MEM
27 * 0xc0000000-0xc0ffffff - PCI 0 I/O
28 * 0xc1000000-0xc1ffffff - PCI 1 I/O
29
30 * 0xf1000000-0xf100ffff - MV64360 Registers
31 * 0xf1010000-0xfb9fffff - HOLE
32 * 0xfbfa0000-0xfbfaffff - TBEN
33 * 0xfbf00000-0xfbfbffff - NEXUS
34 * 0xfbfc0000-0xfbffffff - Internal SRAM
35 * 0xfc000000-0xffffffff - Boot window
36 */
37
38#ifndef __PPC_PLATFORMS_HDPU_H
39#define __PPC_PLATFORMS_HDPU_H
40
41/* CPU Physical Memory Map setup. */
42#define HDPU_BRIDGE_REG_BASE 0xf1000000
43
44#define HDPU_TBEN_BASE 0xfbfa0000
45#define HDPU_TBEN_SIZE 0x00010000
46#define HDPU_NEXUS_ID_BASE 0xfbfb0000
47#define HDPU_NEXUS_ID_SIZE 0x00010000
48#define HDPU_INTERNAL_SRAM_BASE 0xfbfc0000
49#define HDPU_INTERNAL_SRAM_SIZE 0x00040000
50#define HDPU_EMB_FLASH_BASE 0xfc000000
51#define HDPU_EMB_FLASH_SIZE 0x04000000
52
53/* PCI Mappings */
54
55#define HDPU_PCI0_MEM_START_PROC_ADDR 0x80000000
56#define HDPU_PCI0_MEM_START_PCI_HI_ADDR 0x00000000
57#define HDPU_PCI0_MEM_START_PCI_LO_ADDR HDPU_PCI0_MEM_START_PROC_ADDR
58#define HDPU_PCI0_MEM_SIZE 0x10000000
59
60#define HDPU_PCI1_MEM_START_PROC_ADDR 0xc0000000
61#define HDPU_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
62#define HDPU_PCI1_MEM_START_PCI_LO_ADDR HDPU_PCI1_MEM_START_PROC_ADDR
63#define HDPU_PCI1_MEM_SIZE 0x20000000
64
65#define HDPU_PCI0_IO_START_PROC_ADDR 0xc0000000
66#define HDPU_PCI0_IO_START_PCI_ADDR 0x00000000
67#define HDPU_PCI0_IO_SIZE 0x01000000
68
69#define HDPU_PCI1_IO_START_PROC_ADDR 0xc1000000
70#define HDPU_PCI1_IO_START_PCI_ADDR 0x01000000
71#define HDPU_PCI1_IO_SIZE 0x01000000
72
73#define HDPU_DEFAULT_BAUD 115200
74#define HDPU_MPSC_CLK_SRC 8 /* TCLK */
75#define HDPU_MPSC_CLK_FREQ 133000000 /* 133 Mhz */
76
77#define HDPU_PCI_0_IRQ (8+64)
78#define HDPU_PCI_1_IRQ (13+64)
79
80#endif /* __PPC_PLATFORMS_HDPU_H */
diff --git a/arch/ppc/platforms/hermes.h b/arch/ppc/platforms/hermes.h
deleted file mode 100644
index de91afff8ca1..000000000000
--- a/arch/ppc/platforms/hermes.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Multidata HERMES-PRO ( / SL ) board specific definitions
3 *
4 * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifndef __MACH_HERMES_H
8#define __MACH_HERMES_H
9
10
11#include <asm/ppcboot.h>
12
13#define HERMES_IMMR_BASE 0xFF000000 /* phys. addr of IMMR */
14#define HERMES_IMAP_SIZE (64 * 1024) /* size of mapped area */
15
16#define IMAP_ADDR HERMES_IMMR_BASE /* physical base address of IMMR area */
17#define IMAP_SIZE HERMES_IMAP_SIZE /* mapped size of IMMR area */
18
19#define FEC_INTERRUPT 9 /* = SIU_LEVEL4 */
20#define CPM_INTERRUPT 11 /* = SIU_LEVEL5 (was: SIU_LEVEL2) */
21
22/* We don't use the 8259.
23*/
24#define NR_8259_INTS 0
25
26#endif /* __MACH_HERMES_H */
diff --git a/arch/ppc/platforms/ip860.h b/arch/ppc/platforms/ip860.h
deleted file mode 100644
index 2f1f86ce1447..000000000000
--- a/arch/ppc/platforms/ip860.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * MicroSys IP860 VMEBus board specific definitions
3 *
4 * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifndef __MACH_IP860_H
8#define __MACH_IP860_H
9
10
11#include <asm/ppcboot.h>
12
13#define IP860_IMMR_BASE 0xF1000000 /* phys. addr of IMMR */
14#define IP860_IMAP_SIZE (64 * 1024) /* size of mapped area */
15
16#define IMAP_ADDR IP860_IMMR_BASE /* physical base address of IMMR area */
17#define IMAP_SIZE IP860_IMAP_SIZE /* mapped size of IMMR area */
18
19/*
20 * MPC8xx Chip Select Usage
21 */
22#define IP860_BOOT_CS 0 /* Boot (VMEBus or Flash) Chip Select 0 */
23#define IP860_FLASH_CS 1 /* Flash is on Chip Select 1 */
24#define IP860_SDRAM_CS 2 /* SDRAM is on Chip Select 2 */
25#define IP860_SRAM_CS 3 /* SRAM is on Chip Select 3 */
26#define IP860_BCSR_CS 4 /* BCSR is on Chip Select 4 */
27#define IP860_IP_CS 5 /* IP Slots are on Chip Select 5 */
28#define IP860_VME_STD_CS 6 /* VME Standard I/O is on Chip Select 6 */
29#define IP860_VME_SHORT_CS 7 /* VME Short I/O is on Chip Select 7 */
30
31/* We don't use the 8259.
32*/
33#define NR_8259_INTS 0
34
35#endif /* __MACH_IP860_H */
diff --git a/arch/ppc/platforms/ivms8.h b/arch/ppc/platforms/ivms8.h
deleted file mode 100644
index 9109e684ad9b..000000000000
--- a/arch/ppc/platforms/ivms8.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Speech Design Integrated Voicemail board specific definitions
3 * - IVMS8 (small, 8 channels)
4 * - IVML24 (large, 24 channels)
5 *
6 * In 2.5 when we force a new bootloader, we can merge these two, and add
7 * in _MACH_'s for them. -- Tom
8 *
9 * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de)
10 */
11
12#ifdef __KERNEL__
13#ifndef __ASM_IVMS8_H__
14#define __ASM_IVMS8_H__
15
16
17#include <asm/ppcboot.h>
18
19#define IVMS_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */
20#define IVMS_IMAP_SIZE (64 * 1024) /* size of mapped area */
21
22#define IMAP_ADDR IVMS_IMMR_BASE /* phys. base address of IMMR area */
23#define IMAP_SIZE IVMS_IMAP_SIZE /* mapped size of IMMR area */
24
25#define PCMCIA_MEM_ADDR ((uint)0xFE100000)
26#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
27
28#define FEC_INTERRUPT 9 /* = SIU_LEVEL4 */
29#define IDE0_INTERRUPT 10 /* = IRQ5 */
30#define CPM_INTERRUPT 11 /* = SIU_LEVEL5 (was: SIU_LEVEL2) */
31#define PHY_INTERRUPT 12 /* = IRQ6 */
32
33/* override the default number of IDE hardware interfaces */
34#define MAX_HWIFS 1
35
36/*
37 * Definitions for IDE0 Interface
38 */
39#define IDE0_BASE_OFFSET 0x0000 /* Offset in PCMCIA memory */
40#define IDE0_DATA_REG_OFFSET 0x0000
41#define IDE0_ERROR_REG_OFFSET 0x0081
42#define IDE0_NSECTOR_REG_OFFSET 0x0082
43#define IDE0_SECTOR_REG_OFFSET 0x0083
44#define IDE0_LCYL_REG_OFFSET 0x0084
45#define IDE0_HCYL_REG_OFFSET 0x0085
46#define IDE0_SELECT_REG_OFFSET 0x0086
47#define IDE0_STATUS_REG_OFFSET 0x0087
48#define IDE0_CONTROL_REG_OFFSET 0x0106
49#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
50
51/* We don't use the 8259. */
52#define NR_8259_INTS 0
53
54#endif /* __ASM_IVMS8_H__ */
55#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c
deleted file mode 100644
index fe6e88cdb1cd..000000000000
--- a/arch/ppc/platforms/katana.c
+++ /dev/null
@@ -1,902 +0,0 @@
1/*
2 * Board setup routines for the Artesyn Katana cPCI boards.
3 *
4 * Author: Tim Montgomery <timm@artesyncp.com>
5 * Maintained by: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
8 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15/*
16 * Supports the Artesyn 750i, 752i, and 3750. The 752i is virtually identical
17 * to the 750i except that it has an mv64460 bridge.
18 */
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/kdev_t.h>
22#include <linux/console.h>
23#include <linux/initrd.h>
24#include <linux/root_dev.h>
25#include <linux/delay.h>
26#include <linux/seq_file.h>
27#include <linux/mtd/physmap.h>
28#include <linux/mv643xx.h>
29#include <linux/platform_device.h>
30#include <asm/io.h>
31#include <asm/unistd.h>
32#include <asm/page.h>
33#include <asm/time.h>
34#include <asm/smp.h>
35#include <asm/todc.h>
36#include <asm/bootinfo.h>
37#include <asm/ppcboot.h>
38#include <asm/mv64x60.h>
39#include <platforms/katana.h>
40#include <asm/machdep.h>
41
42static struct mv64x60_handle bh;
43static katana_id_t katana_id;
44static void __iomem *cpld_base;
45static void __iomem *sram_base;
46static u32 katana_flash_size_0;
47static u32 katana_flash_size_1;
48static u32 katana_bus_frequency;
49static struct pci_controller katana_hose_a;
50
51unsigned char __res[sizeof(bd_t)];
52
53/* PCI Interrupt routing */
54static int __init
55katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
56{
57 static char pci_irq_table[][4] = {
58 /*
59 * PCI IDSEL/INTPIN->INTLINE
60 * A B C D
61 */
62 /* IDSEL 4 (PMC 1) */
63 { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
64 KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
65 /* IDSEL 5 (PMC 2) */
66 { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
67 KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
68 /* IDSEL 6 (T8110) */
69 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
70 /* IDSEL 7 (unused) */
71 {0, 0, 0, 0 },
72 /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */
73 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
74 };
75 const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4;
76
77 return PCI_IRQ_TABLE_LOOKUP;
78}
79
80static int __init
81katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
82{
83 static char pci_irq_table[][4] = {
84 /*
85 * PCI IDSEL/INTPIN->INTLINE
86 * A B C D
87 */
88 { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */
89 { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/
90 { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/
91 };
92 const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
93
94 return PCI_IRQ_TABLE_LOOKUP;
95}
96
97static int __init
98katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
99{
100 switch (katana_id) {
101 case KATANA_ID_750I:
102 case KATANA_ID_752I:
103 return katana_irq_lookup_750i(idsel, pin);
104
105 case KATANA_ID_3750:
106 return katana_irq_lookup_3750(idsel, pin);
107
108 default:
109 printk(KERN_ERR "Bogus board ID\n");
110 return 0;
111 }
112}
113
114/* Board info retrieval routines */
115void __init
116katana_get_board_id(void)
117{
118 switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) {
119 case KATANA_PRODUCT_ID_3750:
120 katana_id = KATANA_ID_3750;
121 break;
122
123 case KATANA_PRODUCT_ID_750i:
124 katana_id = KATANA_ID_750I;
125 break;
126
127 case KATANA_PRODUCT_ID_752i:
128 katana_id = KATANA_ID_752I;
129 break;
130
131 default:
132 printk(KERN_ERR "Unsupported board\n");
133 }
134}
135
136int __init
137katana_get_proc_num(void)
138{
139 u16 val;
140 u8 save_exclude;
141 static int proc = -1;
142 static u8 first_time = 1;
143
144 if (first_time) {
145 if (katana_id != KATANA_ID_3750)
146 proc = 0;
147 else {
148 save_exclude = mv64x60_pci_exclude_bridge;
149 mv64x60_pci_exclude_bridge = 0;
150
151 early_read_config_word(bh.hose_b, 0,
152 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
153
154 mv64x60_pci_exclude_bridge = save_exclude;
155
156 switch(val) {
157 case PCI_DEVICE_ID_KATANA_3750_PROC0:
158 proc = 0;
159 break;
160
161 case PCI_DEVICE_ID_KATANA_3750_PROC1:
162 proc = 1;
163 break;
164
165 case PCI_DEVICE_ID_KATANA_3750_PROC2:
166 proc = 2;
167 break;
168
169 default:
170 printk(KERN_ERR "Bogus Device ID\n");
171 }
172 }
173
174 first_time = 0;
175 }
176
177 return proc;
178}
179
180static inline int
181katana_is_monarch(void)
182{
183 return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) &
184 KATANA_CPLD_BD_CFG_3_MONARCH;
185}
186
187static void __init
188katana_setup_bridge(void)
189{
190 struct pci_controller hose;
191 struct mv64x60_setup_info si;
192 void __iomem *vaddr;
193 int i;
194 u32 v;
195 u16 val, type;
196 u8 save_exclude;
197
198 /*
199 * Some versions of the Katana firmware mistakenly change the vendor
200 * & device id fields in the bridge's pci device (visible via pci
201 * config accesses). This breaks mv64x60_init() because those values
202 * are used to identify the type of bridge that's there. Artesyn
203 * claims that the subsystem vendor/device id's will have the correct
204 * Marvell values so this code puts back the correct values from there.
205 */
206 memset(&hose, 0, sizeof(hose));
207 vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
208 setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
209 vaddr + MV64x60_PCI0_CONFIG_DATA);
210 save_exclude = mv64x60_pci_exclude_bridge;
211 mv64x60_pci_exclude_bridge = 0;
212
213 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
214
215 if (val != PCI_VENDOR_ID_MARVELL) {
216 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
217 PCI_SUBSYSTEM_VENDOR_ID, &val);
218 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
219 PCI_VENDOR_ID, val);
220 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
221 PCI_SUBSYSTEM_ID, &val);
222 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
223 PCI_DEVICE_ID, val);
224 }
225
226 /*
227 * While we're in here, set the hotswap register correctly.
228 * Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
229 */
230 early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
231 MV64360_PCICFG_CPCI_HOTSWAP, &v);
232 v &= ~(1<<19);
233 v |= ((1<<17) | (1<<22) | (1<<23));
234 early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
235 MV64360_PCICFG_CPCI_HOTSWAP, v);
236
237 /* While we're at it, grab the bridge type for later */
238 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);
239
240 mv64x60_pci_exclude_bridge = save_exclude;
241 iounmap(vaddr);
242
243 memset(&si, 0, sizeof(si));
244
245 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
246
247 si.pci_1.enable_bus = 1;
248 si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
249 si.pci_1.pci_io.pci_base_hi = 0;
250 si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
251 si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
252 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
253 si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
254 si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
255 si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
256 si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
257 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
258 si.pci_1.pci_cmd_bits = 0;
259 si.pci_1.latency_timer = 0x80;
260
261 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
262#if defined(CONFIG_NOT_COHERENT_CACHE)
263 si.cpu_prot_options[i] = 0;
264 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
265 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
266 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
267
268 si.pci_1.acc_cntl_options[i] =
269 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
270 MV64360_PCI_ACC_CNTL_SWAP_NONE |
271 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
272 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
273#else
274 si.cpu_prot_options[i] = 0;
275 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
276 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
277 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
278
279 si.pci_1.acc_cntl_options[i] =
280 MV64360_PCI_ACC_CNTL_SNOOP_WB |
281 MV64360_PCI_ACC_CNTL_SWAP_NONE |
282 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
283 ((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
284 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
285 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
286#endif
287 }
288
289 /* Lookup PCI host bridges */
290 if (mv64x60_init(&bh, &si))
291 printk(KERN_WARNING "Bridge initialization failed.\n");
292
293 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
294 ppc_md.pci_swizzle = common_swizzle;
295 ppc_md.pci_map_irq = katana_map_irq;
296 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
297
298 mv64x60_set_bus(&bh, 1, 0);
299 bh.hose_b->first_busno = 0;
300 bh.hose_b->last_busno = 0xff;
301
302 /*
303 * Need to access hotswap reg which is in the pci config area of the
304 * bridge's hose 0. Note that pcibios_alloc_controller() can't be used
305 * to alloc hose_a b/c that would make hose 0 known to the generic
306 * pci code which we don't want.
307 */
308 bh.hose_a = &katana_hose_a;
309 setup_indirect_pci_nomap(bh.hose_a,
310 bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
311 bh.v_base + MV64x60_PCI0_CONFIG_DATA);
312}
313
314/* Bridge & platform setup routines */
315void __init
316katana_intr_setup(void)
317{
318 if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */
319 mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15);
320
321 /* MPP 8, 9, and 10 */
322 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
323
324 /* MPP 14 */
325 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
326 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
327
328 /*
329 * Define GPP 8,9,and 10 interrupt polarity as active low
330 * input signal and level triggered
331 */
332 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
333 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
334
335 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
336 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
337 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
338 }
339
340 /* Config GPP intr ctlr to respond to level trigger */
341 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
342
343 if (bh.type == MV64x60_TYPE_MV64360) {
344 /* Erratum FEr PCI-#9 */
345 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD,
346 (1<<4) | (1<<5) | (1<<6) | (1<<7));
347 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9));
348 } else {
349 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7));
350 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD,
351 (1<<4) | (1<<5) | (1<<8) | (1<<9));
352 }
353
354 /*
355 * Dismiss and then enable interrupt on GPP interrupt cause
356 * for CPU #0
357 */
358 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
359 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
360
361 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
362 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
363 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
364 }
365
366 /*
367 * Dismiss and then enable interrupt on CPU #0 high cause reg
368 * BIT25 summarizes GPP interrupts 8-15
369 */
370 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
371}
372
373void __init
374katana_setup_peripherals(void)
375{
376 u32 base;
377
378 /* Set up windows for boot CS, soldered & socketed flash, and CPLD */
379 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
380 KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
381 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
382
383 /* Assume firmware set up window sizes correctly for dev 0 & 1 */
384 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
385 &katana_flash_size_0);
386
387 if (katana_flash_size_0 > 0) {
388 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
389 KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
390 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
391 }
392
393 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
394 &katana_flash_size_1);
395
396 if (katana_flash_size_1 > 0) {
397 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
398 (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
399 katana_flash_size_1, 0);
400 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
401 }
402
403 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
404 KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
405 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
406
407 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
408 KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
409 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
410 cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
411
412 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
413 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
414 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
415 sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
416
417 /* Set up Enet->SRAM window */
418 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
419 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
420 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
421
422 /* Give enet r/w access to memory region */
423 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
424 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
425 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
426
427 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
428 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
429 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
430
431 /* Must wait until window set up before retrieving board id */
432 katana_get_board_id();
433
434 /* Enumerate pci bus (must know board id before getting proc number) */
435 if (katana_get_proc_num() == 0)
436 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
437
438#if defined(CONFIG_NOT_COHERENT_CACHE)
439 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
440#else
441 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
442#endif
443
444 /*
445 * Setting the SRAM to 0. Note that this generates parity errors on
446 * internal data path in SRAM since it's first time accessing it
447 * while after reset it's not configured.
448 */
449 memset(sram_base, 0, MV64360_SRAM_SIZE);
450
451 /* Only processor zero [on 3750] is an PCI interrupt controller */
452 if (katana_get_proc_num() == 0)
453 katana_intr_setup();
454}
455
456static void __init
457katana_enable_ipmi(void)
458{
459 u8 reset_out;
460
461 /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
462 reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
463 reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
464 out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
465}
466
467static void __init
468katana_setup_arch(void)
469{
470 if (ppc_md.progress)
471 ppc_md.progress("katana_setup_arch: enter", 0);
472
473 set_tb(0, 0);
474
475#ifdef CONFIG_BLK_DEV_INITRD
476 if (initrd_start)
477 ROOT_DEV = Root_RAM0;
478 else
479#endif
480#ifdef CONFIG_ROOT_NFS
481 ROOT_DEV = Root_NFS;
482#else
483 ROOT_DEV = Root_SDA2;
484#endif
485
486 /*
487 * Set up the L2CR register.
488 *
489 * 750FX has only L2E, L2PE (bits 2-8 are reserved)
490 * DD2.0 has bug that requires the L2 to be in WRT mode
491 * avoid dirty data in cache
492 */
493 if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) {
494 printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
495 "to Writethrough mode\n");
496 _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
497 } else
498 _set_L2CR(L2CR_L2E | L2CR_L2PE);
499
500 if (ppc_md.progress)
501 ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
502
503 katana_setup_bridge();
504 katana_setup_peripherals();
505 katana_enable_ipmi();
506
507 katana_bus_frequency = katana_bus_freq(cpld_base);
508
509 printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
510 if (ppc_md.progress)
511 ppc_md.progress("katana_setup_arch: exit", 0);
512}
513
514void
515katana_fixup_resources(struct pci_dev *dev)
516{
517 u16 v16;
518
519 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2);
520
521 pci_read_config_word(dev, PCI_COMMAND, &v16);
522 v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK;
523 pci_write_config_word(dev, PCI_COMMAND, v16);
524}
525
526static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
527 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
528 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/
529};
530
531static int
532katana_get_cpu_freq(void)
533{
534 unsigned long pll_cfg;
535
536 pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
537 return katana_bus_frequency * cpu_750xx[pll_cfg]/2;
538}
539
540/* Platform device data fixup routines. */
541#if defined(CONFIG_SERIAL_MPSC)
542static void __init
543katana_fixup_mpsc_pdata(struct platform_device *pdev)
544{
545 struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
546 bd_t *bdp = (bd_t *)__res;
547
548 if (bdp->bi_baudrate)
549 pdata->default_baud = bdp->bi_baudrate;
550 else
551 pdata->default_baud = KATANA_DEFAULT_BAUD;
552
553 pdata->max_idle = 40;
554 pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
555 /*
556 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
557 * TCLK == SysCLK but on 64460, they are separate pins.
558 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
559 */
560 pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
561}
562#endif
563
564#if defined(CONFIG_MV643XX_ETH)
565static void __init
566katana_fixup_eth_pdata(struct platform_device *pdev)
567{
568 struct mv643xx_eth_platform_data *eth_pd;
569 static u16 phy_addr[] = {
570 KATANA_ETH0_PHY_ADDR,
571 KATANA_ETH1_PHY_ADDR,
572 KATANA_ETH2_PHY_ADDR,
573 };
574
575 eth_pd = pdev->dev.platform_data;
576 eth_pd->force_phy_addr = 1;
577 eth_pd->phy_addr = phy_addr[pdev->id];
578 eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
579 eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
580}
581#endif
582
583#if defined(CONFIG_SYSFS)
584static void __init
585katana_fixup_mv64xxx_pdata(struct platform_device *pdev)
586{
587 struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *)
588 pdev->dev.platform_data;
589
590 /* Katana supports the mv64xxx hotswap register */
591 pdata->hs_reg_valid = 1;
592}
593#endif
594
595static int
596katana_platform_notify(struct device *dev)
597{
598 static struct {
599 char *bus_id;
600 void ((*rtn)(struct platform_device *pdev));
601 } dev_map[] = {
602#if defined(CONFIG_SERIAL_MPSC)
603 { MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata },
604 { MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata },
605#endif
606#if defined(CONFIG_MV643XX_ETH)
607 { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata },
608 { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
609 { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
610#endif
611#if defined(CONFIG_SYSFS)
612 { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata },
613#endif
614 };
615 struct platform_device *pdev;
616 int i;
617
618 if (dev && dev->bus_id)
619 for (i=0; i<ARRAY_SIZE(dev_map); i++)
620 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
621 BUS_ID_SIZE)) {
622 pdev = container_of(dev,
623 struct platform_device, dev);
624 dev_map[i].rtn(pdev);
625 }
626
627 return 0;
628}
629
630#ifdef CONFIG_MTD_PHYSMAP
631
632#ifndef MB
633#define MB (1 << 20)
634#endif
635
636/*
637 * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
638 *
639 * FLASH Amount: 128 64 32 16
640 * ------------- --- -- -- --
641 * Monitor: 1 1 1 1
642 * Primary Kernel: 1.5 1.5 1.5 1.5
643 * Primary fs: 30 30 <end> <end>
644 * Secondary Kernel: 1.5 1.5 N/A N/A
645 * Secondary fs: <end> <end> N/A N/A
646 * User: <overlays entire FLASH except for "Monitor" section>
647 */
648static int __init
649katana_setup_mtd(void)
650{
651 u32 size;
652 int ptbl_entries;
653 static struct mtd_partition *ptbl;
654
655 size = katana_flash_size_0 + katana_flash_size_1;
656 if (!size)
657 return -ENOMEM;
658
659 ptbl_entries = (size >= (64*MB)) ? 6 : 4;
660
661 if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition),
662 GFP_KERNEL)) == NULL) {
663 printk(KERN_WARNING "Can't alloc MTD partition table\n");
664 return -ENOMEM;
665 }
666
667 ptbl[0].name = "Monitor";
668 ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
669 ptbl[1].name = "Primary Kernel";
670 ptbl[1].offset = MTDPART_OFS_NXTBLK;
671 ptbl[1].size = 0x00180000; /* 1.5 MB */
672 ptbl[2].name = "Primary Filesystem";
673 ptbl[2].offset = MTDPART_OFS_APPEND;
674 ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
675 ptbl[ptbl_entries-1].name = "User FLASH";
676 ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
677 ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
678
679 if (size >= (64*MB)) {
680 ptbl[2].size = 30*MB;
681 ptbl[3].name = "Secondary Kernel";
682 ptbl[3].offset = MTDPART_OFS_NXTBLK;
683 ptbl[3].size = 0x00180000; /* 1.5 MB */
684 ptbl[4].name = "Secondary Filesystem";
685 ptbl[4].offset = MTDPART_OFS_APPEND;
686 ptbl[4].size = MTDPART_SIZ_FULL;
687 }
688
689 physmap_map.size = size;
690 physmap_set_partitions(ptbl, ptbl_entries);
691 return 0;
692}
693arch_initcall(katana_setup_mtd);
694#endif
695
696static void
697katana_restart(char *cmd)
698{
699 ulong i = 10000000;
700
701 /* issue hard reset to the reset command register */
702 out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR);
703
704 while (i-- > 0) ;
705 panic("restart failed\n");
706}
707
708static void
709katana_halt(void)
710{
711 u8 v;
712
713 /* Turn on blue LED to indicate its okay to remove */
714 if (katana_id == KATANA_ID_750I) {
715 u32 v;
716 u8 save_exclude;
717
718 /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */
719 save_exclude = mv64x60_pci_exclude_bridge;
720 mv64x60_pci_exclude_bridge = 0;
721 early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
722 MV64360_PCICFG_CPCI_HOTSWAP, &v);
723 v &= 0xff;
724 v |= (1 << 19);
725 early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
726 MV64360_PCICFG_CPCI_HOTSWAP, v);
727 mv64x60_pci_exclude_bridge = save_exclude;
728 } else if (katana_id == KATANA_ID_752I) {
729 v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF);
730 v |= HSL_PLD_HOT_SWAP_LED_BIT;
731 out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v);
732 }
733
734 while (1) ;
735 /* NOTREACHED */
736}
737
738static void
739katana_power_off(void)
740{
741 katana_halt();
742 /* NOTREACHED */
743}
744
745static int
746katana_show_cpuinfo(struct seq_file *m)
747{
748 char *s;
749
750 seq_printf(m, "cpu freq\t: %dMHz\n",
751 (katana_get_cpu_freq() + 500000) / 1000000);
752 seq_printf(m, "bus freq\t: %ldMHz\n",
753 ((long)katana_bus_frequency + 500000) / 1000000);
754 seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
755
756 seq_printf(m, "board\t\t: ");
757 switch (katana_id) {
758 case KATANA_ID_3750:
759 seq_printf(m, "Katana 3750");
760 break;
761
762 case KATANA_ID_750I:
763 seq_printf(m, "Katana 750i");
764 break;
765
766 case KATANA_ID_752I:
767 seq_printf(m, "Katana 752i");
768 break;
769
770 default:
771 seq_printf(m, "Unknown");
772 break;
773 }
774 seq_printf(m, " (product id: 0x%x)\n",
775 in_8(cpld_base + KATANA_CPLD_PRODUCT_ID));
776
777 seq_printf(m, "pci mode\t: %sMonarch\n",
778 katana_is_monarch()? "" : "Non-");
779 seq_printf(m, "hardware rev\t: 0x%x\n",
780 in_8(cpld_base+KATANA_CPLD_HARDWARE_VER));
781 seq_printf(m, "pld rev\t\t: 0x%x\n",
782 in_8(cpld_base + KATANA_CPLD_PLD_VER));
783
784 switch(bh.type) {
785 case MV64x60_TYPE_GT64260A:
786 s = "gt64260a";
787 break;
788 case MV64x60_TYPE_GT64260B:
789 s = "gt64260b";
790 break;
791 case MV64x60_TYPE_MV64360:
792 s = "mv64360";
793 break;
794 case MV64x60_TYPE_MV64460:
795 s = "mv64460";
796 break;
797 default:
798 s = "Unknown";
799 }
800 seq_printf(m, "bridge type\t: %s\n", s);
801 seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
802#if defined(CONFIG_NOT_COHERENT_CACHE)
803 seq_printf(m, "coherency\t: %s\n", "off");
804#else
805 seq_printf(m, "coherency\t: %s\n", "on");
806#endif
807
808 return 0;
809}
810
811static void __init
812katana_calibrate_decr(void)
813{
814 u32 freq;
815
816 freq = katana_bus_frequency / 4;
817
818 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
819 (long)freq / 1000000, (long)freq % 1000000);
820
821 tb_ticks_per_jiffy = freq / HZ;
822 tb_to_us = mulhwu_scale_factor(freq, 1000000);
823}
824
825/*
826 * The katana supports both uImage and zImage. If uImage, get the mem size
827 * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in
828 * the bi_rec data which is sucked out and put into boot_mem_size by
829 * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem
830 * size and not call this routine. The only way this will fail is when a uImage
831 * is used but the fw doesn't pass in a valid bi_memsize. This should never
832 * happen, though.
833 */
834unsigned long __init
835katana_find_end_of_memory(void)
836{
837 bd_t *bdp = (bd_t *)__res;
838 return bdp->bi_memsize;
839}
840
841#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
842static void __init
843katana_map_io(void)
844{
845 io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
846}
847#endif
848
849void __init
850platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
851 unsigned long r6, unsigned long r7)
852{
853 parse_bootinfo(find_bootinfo());
854
855 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
856 * are non-zero, then we should use the board info from the bd_t
857 * structure and the cmdline pointed to by r6 instead of the
858 * information from birecs, if any. Otherwise, use the information
859 * from birecs as discovered by the preceding call to
860 * parse_bootinfo(). This rule should work with both PPCBoot, which
861 * uses a bd_t board info structure, and the kernel boot wrapper,
862 * which uses birecs.
863 */
864 if (r3 && r6) {
865 /* copy board info structure */
866 memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t));
867 /* copy command line */
868 *(char *)(r7+KERNELBASE) = 0;
869 strcpy(cmd_line, (char *)(r6+KERNELBASE));
870 }
871
872#ifdef CONFIG_BLK_DEV_INITRD
873 /* take care of initrd if we have one */
874 if (r4) {
875 initrd_start = r4 + KERNELBASE;
876 initrd_end = r5 + KERNELBASE;
877 }
878#endif /* CONFIG_BLK_DEV_INITRD */
879
880 isa_mem_base = 0;
881
882 ppc_md.setup_arch = katana_setup_arch;
883 ppc_md.pcibios_fixup_resources = katana_fixup_resources;
884 ppc_md.show_cpuinfo = katana_show_cpuinfo;
885 ppc_md.init_IRQ = mv64360_init_irq;
886 ppc_md.get_irq = mv64360_get_irq;
887 ppc_md.restart = katana_restart;
888 ppc_md.power_off = katana_power_off;
889 ppc_md.halt = katana_halt;
890 ppc_md.find_end_of_memory = katana_find_end_of_memory;
891 ppc_md.calibrate_decr = katana_calibrate_decr;
892
893#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
894 ppc_md.setup_io_mappings = katana_map_io;
895 ppc_md.progress = mv64x60_mpsc_progress;
896 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
897#endif
898
899#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
900 platform_notify = katana_platform_notify;
901#endif
902}
diff --git a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h
deleted file mode 100644
index 0a9b036526b1..000000000000
--- a/arch/ppc/platforms/katana.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * Definitions for Artesyn Katana750i/3750 board.
3 *
4 * Author: Tim Montgomery <timm@artesyncp.com>
5 * Maintained by: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
8 * Based on code done by Mark A. Greer <mgreer@mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/*
17 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
18 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
19 * We'll only use one PCI MEM window on each PCI bus.
20 *
21 * This is the CPU physical memory map (windows must be at least 64 KB and start
22 * on a boundary that is a multiple of the window size):
23 *
24 * 0xff800000-0xffffffff - Boot window
25 * 0xf8400000-0xf843ffff - Internal SRAM
26 * 0xf8200000-0xf83fffff - CPLD
27 * 0xf8100000-0xf810ffff - MV64360 Registers (CONFIG_MV64X60_NEW_BASE)
28 * 0xf8000000-0xf80fffff - Socketed FLASH
29 * 0xe0000000-0xefffffff - Soldered FLASH
30 * 0xc0000000-0xc3ffffff - PCI I/O (second hose)
31 * 0x80000000-0xbfffffff - PCI MEM (second hose)
32 */
33
34#ifndef __PPC_PLATFORMS_KATANA_H
35#define __PPC_PLATFORMS_KATANA_H
36
37/* CPU Physical Memory Map setup. */
38#define KATANA_BOOT_WINDOW_BASE 0xff800000
39#define KATANA_BOOT_WINDOW_SIZE 0x00800000 /* 8 MB */
40#define KATANA_INTERNAL_SRAM_BASE 0xf8400000
41#define KATANA_CPLD_BASE 0xf8200000
42#define KATANA_CPLD_SIZE 0x00200000 /* 2 MB */
43#define KATANA_SOCKET_BASE 0xf8000000
44#define KATANA_SOCKETED_FLASH_SIZE 0x00100000 /* 1 MB */
45#define KATANA_SOLDERED_FLASH_BASE 0xe0000000
46#define KATANA_SOLDERED_FLASH_SIZE 0x10000000 /* 256 MB */
47
48#define KATANA_PCI1_MEM_START_PROC_ADDR 0x80000000
49#define KATANA_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
50#define KATANA_PCI1_MEM_START_PCI_LO_ADDR 0x80000000
51#define KATANA_PCI1_MEM_SIZE 0x40000000 /* 1 GB */
52#define KATANA_PCI1_IO_START_PROC_ADDR 0xc0000000
53#define KATANA_PCI1_IO_START_PCI_ADDR 0x00000000
54#define KATANA_PCI1_IO_SIZE 0x04000000 /* 64 MB */
55
56/* Board-specific IRQ info */
57#define KATANA_PCI_INTA_IRQ_3750 (64+8)
58#define KATANA_PCI_INTB_IRQ_3750 (64+9)
59#define KATANA_PCI_INTC_IRQ_3750 (64+10)
60
61#define KATANA_PCI_INTA_IRQ_750i (64+8)
62#define KATANA_PCI_INTB_IRQ_750i (64+9)
63#define KATANA_PCI_INTC_IRQ_750i (64+10)
64#define KATANA_PCI_INTD_IRQ_750i (64+14)
65
66#define KATANA_CPLD_RST_EVENT 0x00000000
67#define KATANA_CPLD_RST_CMD 0x00001000
68#define KATANA_CPLD_PCI_ERR_INT_EN 0x00002000
69#define KATANA_CPLD_PCI_ERR_INT_PEND 0x00003000
70#define KATANA_CPLD_PRODUCT_ID 0x00004000
71#define KATANA_CPLD_EREADY 0x00005000
72
73#define KATANA_CPLD_HARDWARE_VER 0x00007000
74#define KATANA_CPLD_PLD_VER 0x00008000
75#define KATANA_CPLD_BD_CFG_0 0x00009000
76#define KATANA_CPLD_BD_CFG_1 0x0000a000
77#define KATANA_CPLD_BD_CFG_3 0x0000c000
78#define KATANA_CPLD_LED 0x0000d000
79#define KATANA_CPLD_RESET_OUT 0x0000e000
80
81#define KATANA_CPLD_RST_EVENT_INITACT 0x80
82#define KATANA_CPLD_RST_EVENT_SW 0x40
83#define KATANA_CPLD_RST_EVENT_WD 0x20
84#define KATANA_CPLD_RST_EVENT_COPS 0x10
85#define KATANA_CPLD_RST_EVENT_COPH 0x08
86#define KATANA_CPLD_RST_EVENT_CPCI 0x02
87#define KATANA_CPLD_RST_EVENT_FP 0x01
88
89#define KATANA_CPLD_RST_CMD_SCL 0x80
90#define KATANA_CPLD_RST_CMD_SDA 0x40
91#define KATANA_CPLD_RST_CMD_I2C 0x10
92#define KATANA_CPLD_RST_CMD_FR 0x08
93#define KATANA_CPLD_RST_CMD_SR 0x04
94#define KATANA_CPLD_RST_CMD_HR 0x01
95
96#define KATANA_CPLD_BD_CFG_0_SYSCLK_MASK 0xc0
97#define KATANA_CPLD_BD_CFG_0_SYSCLK_200 0x00
98#define KATANA_CPLD_BD_CFG_0_SYSCLK_166 0x80
99#define KATANA_CPLD_BD_CFG_0_SYSCLK_133 0xc0
100#define KATANA_CPLD_BD_CFG_0_SYSCLK_100 0x40
101
102#define KATANA_CPLD_BD_CFG_1_FL_BANK_MASK 0x03
103#define KATANA_CPLD_BD_CFG_1_FL_BANK_16MB 0x00
104#define KATANA_CPLD_BD_CFG_1_FL_BANK_32MB 0x01
105#define KATANA_CPLD_BD_CFG_1_FL_BANK_64MB 0x02
106#define KATANA_CPLD_BD_CFG_1_FL_BANK_128MB 0x03
107
108#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_MASK 0x04
109#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_ONE 0x00
110#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_TWO 0x04
111
112#define KATANA_CPLD_BD_CFG_3_MONARCH 0x04
113
114#define KATANA_CPLD_RESET_OUT_PORTSEL 0x80
115#define KATANA_CPLD_RESET_OUT_WD 0x20
116#define KATANA_CPLD_RESET_OUT_COPH 0x08
117#define KATANA_CPLD_RESET_OUT_PCI_RST_PCI 0x02
118#define KATANA_CPLD_RESET_OUT_PCI_RST_FP 0x01
119
120#define KATANA_MBOX_RESET_REQUEST 0xC83A
121#define KATANA_MBOX_RESET_ACK 0xE430
122#define KATANA_MBOX_RESET_DONE 0x32E5
123
124#define HSL_PLD_BASE 0x00010000
125#define HSL_PLD_J4SGA_REG_OFF 0
126#define HSL_PLD_J4GA_REG_OFF 1
127#define HSL_PLD_J2GA_REG_OFF 2
128#define HSL_PLD_HOT_SWAP_OFF 6
129#define HSL_PLD_HOT_SWAP_LED_BIT 0x1
130#define GA_MASK 0x1f
131#define HSL_PLD_SIZE 0x1000
132#define K3750_GPP_GEO_ADDR_PINS 0xf8000000
133#define K3750_GPP_GEO_ADDR_SHIFT 27
134
135#define K3750_GPP_EVENT_PROC_0 (1 << 21)
136#define K3750_GPP_EVENT_PROC_1_2 (1 << 2)
137
138#define PCI_VENDOR_ID_ARTESYN 0x1223
139#define PCI_DEVICE_ID_KATANA_3750_PROC0 0x0041
140#define PCI_DEVICE_ID_KATANA_3750_PROC1 0x0042
141#define PCI_DEVICE_ID_KATANA_3750_PROC2 0x0043
142
143#define COPROC_MEM_FUNCTION 0
144#define COPROC_MEM_BAR 0
145#define COPROC_REGS_FUNCTION 0
146#define COPROC_REGS_BAR 4
147#define COPROC_FLASH_FUNCTION 2
148#define COPROC_FLASH_BAR 4
149
150#define KATANA_IPMB_LOCAL_I2C_ADDR 0x08
151
152#define KATANA_DEFAULT_BAUD 9600
153#define KATANA_MPSC_CLK_SRC 8 /* TCLK */
154
155#define KATANA_MTD_MONITOR_SIZE (1 << 20) /* 1 MB */
156
157#define KATANA_ETH0_PHY_ADDR 12
158#define KATANA_ETH1_PHY_ADDR 11
159#define KATANA_ETH2_PHY_ADDR 4
160
161#define KATANA_PRODUCT_ID_3750 0x01
162#define KATANA_PRODUCT_ID_750i 0x02
163#define KATANA_PRODUCT_ID_752i 0x04
164
165#define KATANA_ETH_TX_QUEUE_SIZE 800
166#define KATANA_ETH_RX_QUEUE_SIZE 400
167
168#define KATANA_ETH_PORT_CONFIG_VALUE \
169 ETH_UNICAST_NORMAL_MODE | \
170 ETH_DEFAULT_RX_QUEUE_0 | \
171 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
172 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
173 ETH_RECEIVE_BC_IF_IP | \
174 ETH_RECEIVE_BC_IF_ARP | \
175 ETH_CAPTURE_TCP_FRAMES_DIS | \
176 ETH_CAPTURE_UDP_FRAMES_DIS | \
177 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
178 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
179 ETH_DEFAULT_RX_BPDU_QUEUE_0
180
181#define KATANA_ETH_PORT_CONFIG_EXTEND_VALUE \
182 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
183 ETH_PARTITION_DISABLE
184
185#define GT_ETH_IPG_INT_RX(value) \
186 ((value & 0x3fff) << 8)
187
188#define KATANA_ETH_PORT_SDMA_CONFIG_VALUE \
189 ETH_RX_BURST_SIZE_4_64BIT | \
190 GT_ETH_IPG_INT_RX(0) | \
191 ETH_TX_BURST_SIZE_4_64BIT
192
193#define KATANA_ETH_PORT_SERIAL_CONTROL_VALUE \
194 ETH_FORCE_LINK_PASS | \
195 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
196 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
197 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
198 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
199 ETH_FORCE_BP_MODE_NO_JAM | \
200 BIT9 | \
201 ETH_DO_NOT_FORCE_LINK_FAIL | \
202 ETH_RETRANSMIT_16_ATTEMPTS | \
203 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
204 ETH_DTE_ADV_0 | \
205 ETH_DISABLE_AUTO_NEG_BYPASS | \
206 ETH_AUTO_NEG_NO_CHANGE | \
207 ETH_MAX_RX_PACKET_9700BYTE | \
208 ETH_CLR_EXT_LOOPBACK | \
209 ETH_SET_FULL_DUPLEX_MODE | \
210 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
211
212#ifndef __ASSEMBLY__
213
214typedef enum {
215 KATANA_ID_3750,
216 KATANA_ID_750I,
217 KATANA_ID_752I,
218 KATANA_ID_MAX
219} katana_id_t;
220
221#endif
222
223static inline u32
224katana_bus_freq(void __iomem *cpld_base)
225{
226 u8 bd_cfg_0;
227
228 bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0);
229
230 switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
231 case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
232 return 200000000;
233 break;
234
235 case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
236 return 166666666;
237 break;
238
239 case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
240 return 133333333;
241 break;
242
243 case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
244 return 100000000;
245 break;
246
247 default:
248 return 133333333;
249 break;
250 }
251}
252
253#endif /* __PPC_PLATFORMS_KATANA_H */
diff --git a/arch/ppc/platforms/lantec.h b/arch/ppc/platforms/lantec.h
deleted file mode 100644
index 5e5eb6d0f6aa..000000000000
--- a/arch/ppc/platforms/lantec.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * LANTEC board specific definitions
3 *
4 * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifndef __MACH_LANTEC_H
8#define __MACH_LANTEC_H
9
10
11#include <asm/ppcboot.h>
12
13#define IMAP_ADDR 0xFFF00000 /* physical base address of IMMR area */
14#define IMAP_SIZE (64 * 1024) /* mapped size of IMMR area */
15
16/* We don't use the 8259.
17*/
18#define NR_8259_INTS 0
19
20#endif /* __MACH_LANTEC_H */
diff --git a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
deleted file mode 100644
index b9e9db63f65b..000000000000
--- a/arch/ppc/platforms/lite5200.c
+++ /dev/null
@@ -1,245 +0,0 @@
1/*
2 * Platform support file for the Freescale LITE5200 based on MPC52xx.
3 * A maximum of this file should be moved to syslib/mpc52xx_?????
4 * so that new platform based on MPC52xx need a minimal platform file
5 * ( avoid code duplication )
6 *
7 *
8 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
9 *
10 * Based on the 2.4 code written by Kent Borg,
11 * Dale Farnsworth <dale.farnsworth@mvista.com> and
12 * Wolfgang Denk <wd@denx.de>
13 *
14 * Copyright 2004-2005 Sylvain Munaut <tnt@246tNt.com>
15 * Copyright 2003 Motorola Inc.
16 * Copyright 2003 MontaVista Software Inc.
17 * Copyright 2003 DENX Software Engineering (wd@denx.de)
18 *
19 * This file is licensed under the terms of the GNU General Public License
20 * version 2. This program is licensed "as is" without any warranty of any
21 * kind, whether express or implied.
22 */
23
24#include <linux/initrd.h>
25#include <linux/seq_file.h>
26#include <linux/kdev_t.h>
27#include <linux/root_dev.h>
28#include <linux/console.h>
29#include <linux/module.h>
30
31#include <asm/bootinfo.h>
32#include <asm/io.h>
33#include <asm/mpc52xx.h>
34#include <asm/ppc_sys.h>
35#include <asm/machdep.h>
36#include <asm/pci-bridge.h>
37
38
39extern int powersave_nap;
40
41/* Board data given by U-Boot */
42bd_t __res;
43EXPORT_SYMBOL(__res); /* For modules */
44
45
46/* ======================================================================== */
47/* Platform specific code */
48/* ======================================================================== */
49
50/* Supported PSC function in "preference" order */
51struct mpc52xx_psc_func mpc52xx_psc_functions[] = {
52 { .id = 0,
53 .func = "uart",
54 },
55 { .id = -1, /* End entry */
56 .func = NULL,
57 }
58 };
59
60
61static int
62lite5200_show_cpuinfo(struct seq_file *m)
63{
64 seq_printf(m, "machine\t\t: Freescale LITE5200\n");
65 return 0;
66}
67
68#ifdef CONFIG_PCI
69#ifdef CONFIG_LITE5200B
70static int
71lite5200_map_irq(struct pci_dev *dev, unsigned char idsel,
72 unsigned char pin)
73{
74 static char pci_irq_table[][4] =
75 /*
76 * PCI IDSEL/INTPIN->INTLINE
77 * A B C D
78 */
79 {
80 {MPC52xx_IRQ0, MPC52xx_IRQ1, MPC52xx_IRQ2, MPC52xx_IRQ3},
81 {MPC52xx_IRQ1, MPC52xx_IRQ2, MPC52xx_IRQ3, MPC52xx_IRQ0},
82 };
83
84 const long min_idsel = 24, max_idsel = 25, irqs_per_slot = 4;
85 return PCI_IRQ_TABLE_LOOKUP;
86}
87#else /* Original Lite */
88static int
89lite5200_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
90{
91 return (pin == 1) && (idsel==24) ? MPC52xx_IRQ0 : -1;
92}
93#endif
94#endif
95
96static void __init
97lite5200_setup_cpu(void)
98{
99 struct mpc52xx_gpio __iomem *gpio;
100 struct mpc52xx_intr __iomem *intr;
101
102 u32 port_config;
103 u32 intr_ctrl;
104
105 /* Map zones */
106 gpio = ioremap(MPC52xx_PA(MPC52xx_GPIO_OFFSET), MPC52xx_GPIO_SIZE);
107 intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
108
109 if (!gpio || !intr) {
110 printk(KERN_ERR __FILE__ ": "
111 "Error while mapping GPIO/INTR during "
112 "lite5200_setup_cpu\n");
113 goto unmap_regs;
114 }
115
116 /* Get port mux config */
117 port_config = in_be32(&gpio->port_config);
118
119 /* 48Mhz internal, pin is GPIO */
120 port_config &= ~0x00800000;
121
122 /* USB port */
123 port_config &= ~0x00007000; /* Differential mode - USB1 only */
124 port_config |= 0x00001000;
125
126 /* ATA CS is on csb_4/5 */
127 port_config &= ~0x03000000;
128 port_config |= 0x01000000;
129
130 /* Commit port config */
131 out_be32(&gpio->port_config, port_config);
132
133 /* IRQ[0-3] setup */
134 intr_ctrl = in_be32(&intr->ctrl);
135 intr_ctrl &= ~0x00ff0000;
136#ifdef CONFIG_LITE5200B
137 /* IRQ[0-3] Level Active Low */
138 intr_ctrl |= 0x00ff0000;
139#else
140 /* IRQ0 Level Active Low
141 * IRQ[1-3] Level Active High */
142 intr_ctrl |= 0x00c00000;
143#endif
144 out_be32(&intr->ctrl, intr_ctrl);
145
146 /* Unmap reg zone */
147unmap_regs:
148 if (gpio) iounmap(gpio);
149 if (intr) iounmap(intr);
150}
151
152static void __init
153lite5200_setup_arch(void)
154{
155 /* CPU & Port mux setup */
156 mpc52xx_setup_cpu(); /* Generic */
157 lite5200_setup_cpu(); /* Platform specific */
158
159#ifdef CONFIG_PCI
160 /* PCI Bridge setup */
161 mpc52xx_find_bridges();
162#endif
163}
164
165void __init
166platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
167 unsigned long r6, unsigned long r7)
168{
169 /* Generic MPC52xx platform initialization */
170 /* TODO Create one and move a max of stuff in it.
171 Put this init in the syslib */
172
173 struct bi_record *bootinfo = find_bootinfo();
174
175 if (bootinfo)
176 parse_bootinfo(bootinfo);
177 else {
178 /* Load the bd_t board info structure */
179 if (r3)
180 memcpy((void*)&__res,(void*)(r3+KERNELBASE),
181 sizeof(bd_t));
182
183#ifdef CONFIG_BLK_DEV_INITRD
184 /* Load the initrd */
185 if (r4) {
186 initrd_start = r4 + KERNELBASE;
187 initrd_end = r5 + KERNELBASE;
188 }
189#endif
190
191 /* Load the command line */
192 if (r6) {
193 *(char *)(r7+KERNELBASE) = 0;
194 strcpy(cmd_line, (char *)(r6+KERNELBASE));
195 }
196 }
197
198 /* PPC Sys identification */
199 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
200
201 /* BAT setup */
202 mpc52xx_set_bat();
203
204 /* No ISA bus by default */
205#ifdef CONFIG_PCI
206 isa_io_base = 0;
207 isa_mem_base = 0;
208#endif
209
210 /* Powersave */
211 /* This is provided as an example on how to do it. But you
212 need to be aware that NAP disable bus snoop and that may
213 be required for some devices to work properly, like USB ... */
214 /* powersave_nap = 1; */
215
216
217 /* Setup the ppc_md struct */
218 ppc_md.setup_arch = lite5200_setup_arch;
219 ppc_md.show_cpuinfo = lite5200_show_cpuinfo;
220 ppc_md.show_percpuinfo = NULL;
221 ppc_md.init_IRQ = mpc52xx_init_irq;
222 ppc_md.get_irq = mpc52xx_get_irq;
223
224#ifdef CONFIG_PCI
225 ppc_md.pci_map_irq = lite5200_map_irq;
226#endif
227
228 ppc_md.find_end_of_memory = mpc52xx_find_end_of_memory;
229 ppc_md.setup_io_mappings = mpc52xx_map_io;
230
231 ppc_md.restart = mpc52xx_restart;
232 ppc_md.power_off = mpc52xx_power_off;
233 ppc_md.halt = mpc52xx_halt;
234
235 /* No time keeper on the LITE5200 */
236 ppc_md.time_init = NULL;
237 ppc_md.get_rtc_time = NULL;
238 ppc_md.set_rtc_time = NULL;
239
240 ppc_md.calibrate_decr = mpc52xx_calibrate_decr;
241#ifdef CONFIG_SERIAL_TEXT_DEBUG
242 ppc_md.progress = mpc52xx_progress;
243#endif
244}
245
diff --git a/arch/ppc/platforms/lite5200.h b/arch/ppc/platforms/lite5200.h
deleted file mode 100644
index 852a18e24d0b..000000000000
--- a/arch/ppc/platforms/lite5200.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Definitions for Freescale LITE5200 : MPC52xx Standard Development
3 * Platform board support
4 *
5 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
6 *
7 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#ifndef __PLATFORMS_LITE5200_H__
15#define __PLATFORMS_LITE5200_H__
16
17/* Serial port used for low-level debug */
18#define MPC52xx_PF_CONSOLE_PORT 1 /* PSC1 */
19
20
21#endif /* __PLATFORMS_LITE5200_H__ */
diff --git a/arch/ppc/platforms/lopec.c b/arch/ppc/platforms/lopec.c
deleted file mode 100644
index 1e3aa6e9b6c7..000000000000
--- a/arch/ppc/platforms/lopec.c
+++ /dev/null
@@ -1,310 +0,0 @@
1/*
2 * Setup routines for the Motorola LoPEC.
3 *
4 * Author: Dan Cox
5 * Maintainer: Tom Rini <trini@kernel.crashing.org>
6 *
7 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#include <linux/types.h>
14#include <linux/delay.h>
15#include <linux/pci_ids.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/seq_file.h>
19#include <linux/initrd.h>
20#include <linux/console.h>
21#include <linux/root_dev.h>
22#include <linux/pci.h>
23
24#include <asm/machdep.h>
25#include <asm/pci-bridge.h>
26#include <asm/io.h>
27#include <asm/open_pic.h>
28#include <asm/i8259.h>
29#include <asm/todc.h>
30#include <asm/bootinfo.h>
31#include <asm/mpc10x.h>
32#include <asm/hw_irq.h>
33#include <asm/prep_nvram.h>
34#include <asm/kgdb.h>
35
36/*
37 * Define all of the IRQ senses and polarities. Taken from the
38 * LoPEC Programmer's Reference Guide.
39 */
40static u_char lopec_openpic_initsenses[16] __initdata = {
41 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 0 */
42 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 1 */
43 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 2 */
44 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 3 */
45 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 4 */
46 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 5 */
47 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 6 */
48 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 7 */
49 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 8 */
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 9 */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 10 */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 11 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 12 */
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 13 */
55 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ 14 */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* IRQ 15 */
57};
58
59static inline int __init
60lopec_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
61{
62 int irq;
63 static char pci_irq_table[][4] = {
64 {16, 0, 0, 0}, /* ID 11 - Winbond */
65 {22, 0, 0, 0}, /* ID 12 - SCSI */
66 {0, 0, 0, 0}, /* ID 13 - nothing */
67 {17, 0, 0, 0}, /* ID 14 - 82559 Ethernet */
68 {27, 0, 0, 0}, /* ID 15 - USB */
69 {23, 0, 0, 0}, /* ID 16 - PMC slot 1 */
70 {24, 0, 0, 0}, /* ID 17 - PMC slot 2 */
71 {25, 0, 0, 0}, /* ID 18 - PCI slot */
72 {0, 0, 0, 0}, /* ID 19 - nothing */
73 {0, 0, 0, 0}, /* ID 20 - nothing */
74 {0, 0, 0, 0}, /* ID 21 - nothing */
75 {0, 0, 0, 0}, /* ID 22 - nothing */
76 {0, 0, 0, 0}, /* ID 23 - nothing */
77 {0, 0, 0, 0}, /* ID 24 - PMC slot 1b */
78 {0, 0, 0, 0}, /* ID 25 - nothing */
79 {0, 0, 0, 0} /* ID 26 - PMC Slot 2b */
80 };
81 const long min_idsel = 11, max_idsel = 26, irqs_per_slot = 4;
82
83 irq = PCI_IRQ_TABLE_LOOKUP;
84 if (!irq)
85 return 0;
86
87 return irq;
88}
89
90static void __init
91lopec_setup_winbond_83553(struct pci_controller *hose)
92{
93 int devfn;
94
95 devfn = PCI_DEVFN(11,0);
96
97 /* IDE interrupt routing (primary 14, secondary 15) */
98 early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
99 /* PCI interrupt routing */
100 early_write_config_word(hose, 0, devfn, 0x44, 0x0000);
101
102 /* ISA-PCI address decoder */
103 early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);
104
105 /* RTC, kb, not used in PPC */
106 early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
107 early_write_config_byte(hose, 0, devfn, 0x4e, 0x04);
108 devfn = PCI_DEVFN(11, 1);
109 early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
110 early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
111}
112
113static void __init
114lopec_find_bridges(void)
115{
116 struct pci_controller *hose;
117
118 hose = pcibios_alloc_controller();
119 if (!hose)
120 return;
121
122 hose->first_busno = 0;
123 hose->last_busno = 0xff;
124
125 if (mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B,
126 MPC10X_MAPB_EUMB_BASE) == 0) {
127
128 hose->mem_resources[0].end = 0xffffffff;
129 lopec_setup_winbond_83553(hose);
130 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
131 ppc_md.pci_swizzle = common_swizzle;
132 ppc_md.pci_map_irq = lopec_map_irq;
133 }
134}
135
136static int
137lopec_show_cpuinfo(struct seq_file *m)
138{
139 seq_printf(m, "machine\t\t: Motorola LoPEC\n");
140 return 0;
141}
142
143static void
144lopec_restart(char *cmd)
145{
146#define LOPEC_SYSSTAT1 0xffe00000
147 /* force a hard reset, if possible */
148 unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
149 reg |= 0x80;
150 *((unsigned char *) LOPEC_SYSSTAT1) = reg;
151
152 local_irq_disable();
153 while(1);
154#undef LOPEC_SYSSTAT1
155}
156
157static void
158lopec_halt(void)
159{
160 local_irq_disable();
161 while(1);
162}
163
164static void
165lopec_power_off(void)
166{
167 lopec_halt();
168}
169
170static void __init
171lopec_init_IRQ(void)
172{
173 int i;
174
175 /*
176 * Provide the open_pic code with the correct table of interrupts.
177 */
178 OpenPIC_InitSenses = lopec_openpic_initsenses;
179 OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
180
181 mpc10x_set_openpic();
182
183 /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
184 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
185 &i8259_irq);
186
187 /*
188 * The EPIC allows for a read in the range of 0xFEF00000 ->
189 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
190 */
191 i8259_init(0xfef00000, 0);
192}
193
194static int __init
195lopec_request_io(void)
196{
197 outb(0x00, 0x4d0);
198 outb(0xc0, 0x4d1);
199
200 request_region(0x00, 0x20, "dma1");
201 request_region(0x20, 0x20, "pic1");
202 request_region(0x40, 0x20, "timer");
203 request_region(0x80, 0x10, "dma page reg");
204 request_region(0xa0, 0x20, "pic2");
205 request_region(0xc0, 0x20, "dma2");
206
207 return 0;
208}
209
210device_initcall(lopec_request_io);
211
212static void __init
213lopec_map_io(void)
214{
215 io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
216 io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
217}
218
219/*
220 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
221 */
222static __inline__ void
223lopec_set_bat(void)
224{
225 mb();
226 mtspr(SPRN_DBAT1U, 0xf8000ffe);
227 mtspr(SPRN_DBAT1L, 0xf800002a);
228 mb();
229}
230
231TODC_ALLOC();
232
233static void __init
234lopec_setup_arch(void)
235{
236
237 TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
238 ioremap(0xffe80000, 0x8000), 8);
239
240 loops_per_jiffy = 100000000/HZ;
241
242 lopec_find_bridges();
243
244#ifdef CONFIG_BLK_DEV_INITRD
245 if (initrd_start)
246 ROOT_DEV = Root_RAM0;
247 else
248#elif defined(CONFIG_ROOT_NFS)
249 ROOT_DEV = Root_NFS;
250#elif defined(CONFIG_BLK_DEV_IDEDISK)
251 ROOT_DEV = Root_HDA1;
252#else
253 ROOT_DEV = Root_SDA1;
254#endif
255
256#ifdef CONFIG_PPCBUG_NVRAM
257 /* Read in NVRAM data */
258 init_prep_nvram();
259
260 /* if no bootargs, look in NVRAM */
261 if ( cmd_line[0] == '\0' ) {
262 char *bootargs;
263 bootargs = prep_nvram_get_var("bootargs");
264 if (bootargs != NULL) {
265 strcpy(cmd_line, bootargs);
266 /* again.. */
267 strcpy(boot_command_line, cmd_line);
268 }
269 }
270#endif
271}
272
273void __init
274platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
275 unsigned long r6, unsigned long r7)
276{
277 parse_bootinfo(find_bootinfo());
278 lopec_set_bat();
279
280 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
281 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
282 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
283 ISA_DMA_THRESHOLD = 0x00ffffff;
284 DMA_MODE_READ = 0x44;
285 DMA_MODE_WRITE = 0x48;
286 ppc_do_canonicalize_irqs = 1;
287
288 ppc_md.setup_arch = lopec_setup_arch;
289 ppc_md.show_cpuinfo = lopec_show_cpuinfo;
290 ppc_md.init_IRQ = lopec_init_IRQ;
291 ppc_md.get_irq = openpic_get_irq;
292
293 ppc_md.restart = lopec_restart;
294 ppc_md.power_off = lopec_power_off;
295 ppc_md.halt = lopec_halt;
296
297 ppc_md.setup_io_mappings = lopec_map_io;
298
299 ppc_md.time_init = todc_time_init;
300 ppc_md.set_rtc_time = todc_set_rtc_time;
301 ppc_md.get_rtc_time = todc_get_rtc_time;
302 ppc_md.calibrate_decr = todc_calibrate_decr;
303
304 ppc_md.nvram_read_val = todc_direct_read_val;
305 ppc_md.nvram_write_val = todc_direct_write_val;
306
307#ifdef CONFIG_SERIAL_TEXT_DEBUG
308 ppc_md.progress = gen550_progress;
309#endif
310}
diff --git a/arch/ppc/platforms/lopec.h b/arch/ppc/platforms/lopec.h
deleted file mode 100644
index d597b6878693..000000000000
--- a/arch/ppc/platforms/lopec.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * arch/ppc/platforms/lopec.h
3 *
4 * Definitions for Motorola LoPEC board.
5 *
6 * Author: Dan Cox
7 * danc@mvista.com (or, alternately, source@mvista.com)
8 *
9 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifndef __H_LOPEC_SERIAL
16#define __H_LOPEC_SERIAL
17
18#define RS_TABLE_SIZE 3
19
20#define BASE_BAUD (1843200 / 16)
21
22#ifdef CONFIG_SERIAL_DETECT_IRQ
23#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
24#else
25#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
26#endif
27
28#define SERIAL_PORT_DFNS \
29 { 0, BASE_BAUD, 0xffe10000, 29, STD_COM_FLAGS, \
30 iomem_base: (u8 *) 0xffe10000, \
31 io_type: SERIAL_IO_MEM }, \
32 { 0, BASE_BAUD, 0xffe11000, 20, STD_COM_FLAGS, \
33 iomem_base: (u8 *) 0xffe11000, \
34 io_type: SERIAL_IO_MEM }, \
35 { 0, BASE_BAUD, 0xffe12000, 21, STD_COM_FLAGS, \
36 iomem_base: (u8 *) 0xffe12000, \
37 io_type: SERIAL_IO_MEM }
38
39#endif
diff --git a/arch/ppc/platforms/lwmon.h b/arch/ppc/platforms/lwmon.h
deleted file mode 100644
index e63f3b07a5db..000000000000
--- a/arch/ppc/platforms/lwmon.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Liebherr LWMON board specific definitions
3 *
4 * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifndef __MACH_LWMON_H
8#define __MACH_LWMON_H
9
10
11#include <asm/ppcboot.h>
12
13#define IMAP_ADDR 0xFFF00000 /* physical base address of IMMR area */
14#define IMAP_SIZE (64 * 1024) /* mapped size of IMMR area */
15
16/*-----------------------------------------------------------------------
17 * PCMCIA stuff
18 *-----------------------------------------------------------------------
19 *
20 */
21#define PCMCIA_MEM_SIZE ( 64 << 20 )
22
23#define MAX_HWIFS 1 /* overwrite default in include/asm-ppc/ide.h */
24
25/*
26 * Definitions for IDE0 Interface
27 */
28#define IDE0_BASE_OFFSET 0
29#define IDE0_DATA_REG_OFFSET (PCMCIA_MEM_SIZE + 0x320)
30#define IDE0_ERROR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 1)
31#define IDE0_NSECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 2)
32#define IDE0_SECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 3)
33#define IDE0_LCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 4)
34#define IDE0_HCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 5)
35#define IDE0_SELECT_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 6)
36#define IDE0_STATUS_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 7)
37#define IDE0_CONTROL_REG_OFFSET 0x0106
38#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
39
40#define IDE0_INTERRUPT 13
41
42/*
43 * Definitions for I2C devices
44 */
45#define I2C_ADDR_AUDIO 0x28 /* Audio volume control */
46#define I2C_ADDR_SYSMON 0x2E /* LM87 System Monitor */
47#define I2C_ADDR_RTC 0x51 /* PCF8563 RTC */
48#define I2C_ADDR_POWER_A 0x52 /* PCMCIA/USB power switch, channel A */
49#define I2C_ADDR_POWER_B 0x53 /* PCMCIA/USB power switch, channel B */
50#define I2C_ADDR_KEYBD 0x56 /* PIC LWE keyboard */
51#define I2C_ADDR_PICIO 0x57 /* PIC IO Expander */
52#define I2C_ADDR_EEPROM 0x58 /* EEPROM AT24C164 */
53
54
55/* We don't use the 8259.
56*/
57#define NR_8259_INTS 0
58
59#endif /* __MACH_LWMON_H */
diff --git a/arch/ppc/platforms/mbx.h b/arch/ppc/platforms/mbx.h
deleted file mode 100644
index 1cf36fa3592d..000000000000
--- a/arch/ppc/platforms/mbx.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola MBX boards. This was originally created for the
4 * MBX860, and probably needs revisions for other boards (like the 821).
5 * When this file gets out of control, we can split it up into more
6 * meaningful pieces.
7 *
8 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
9 */
10#ifdef __KERNEL__
11#ifndef __MACH_MBX_DEFS
12#define __MACH_MBX_DEFS
13
14#ifndef __ASSEMBLY__
15/* A Board Information structure that is given to a program when
16 * EPPC-Bug starts it up.
17 */
18typedef struct bd_info {
19 unsigned int bi_tag; /* Should be 0x42444944 "BDID" */
20 unsigned int bi_size; /* Size of this structure */
21 unsigned int bi_revision; /* revision of this structure */
22 unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */
23 unsigned int bi_memstart; /* Memory start address */
24 unsigned int bi_memsize; /* Memory (end) size in bytes */
25 unsigned int bi_intfreq; /* Internal Freq, in Hz */
26 unsigned int bi_busfreq; /* Bus Freq, in Hz */
27 unsigned int bi_clun; /* Boot device controller */
28 unsigned int bi_dlun; /* Boot device logical dev */
29
30 /* These fields are not part of the board information structure
31 * provided by the boot rom. They are filled in by embed_config.c
32 * so we have the information consistent with other platforms.
33 */
34 unsigned char bi_enetaddr[6];
35 unsigned int bi_baudrate;
36} bd_t;
37
38/* Memory map for the MBX as configured by EPPC-Bug. We could reprogram
39 * The SIU and PCI bridge, and try to use larger MMU pages, but the
40 * performance gain is not measurable and it certainly complicates the
41 * generic MMU model.
42 *
43 * In a effort to minimize memory usage for embedded applications, any
44 * PCI driver or ISA driver must request or map the region required by
45 * the device. For convenience (and since we can map up to 4 Mbytes with
46 * a single page table page), the MMU initialization will map the
47 * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI
48 * Bridge CSRs 1:1 into the kernel address space.
49 */
50#define PCI_ISA_IO_ADDR ((unsigned)0x80000000)
51#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024))
52#define PCI_IDE_ADDR ((unsigned)0x81000000)
53#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000)
54#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024))
55#define PCMCIA_MEM_ADDR ((uint)0xe0000000)
56#define PCMCIA_MEM_SIZE ((uint)(64 * 1024 * 1024))
57#define PCMCIA_DMA_ADDR ((uint)0xe4000000)
58#define PCMCIA_DMA_SIZE ((uint)(64 * 1024 * 1024))
59#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000)
60#define PCMCIA_ATTRB_SIZE ((uint)(64 * 1024 * 1024))
61#define PCMCIA_IO_ADDR ((uint)0xec000000)
62#define PCMCIA_IO_SIZE ((uint)(64 * 1024 * 1024))
63#define NVRAM_ADDR ((uint)0xfa000000)
64#define NVRAM_SIZE ((uint)(1 * 1024 * 1024))
65#define MBX_CSR_ADDR ((uint)0xfa100000)
66#define MBX_CSR_SIZE ((uint)(1 * 1024 * 1024))
67#define IMAP_ADDR ((uint)0xfa200000)
68#define IMAP_SIZE ((uint)(64 * 1024))
69#define PCI_CSR_ADDR ((uint)0xfa210000)
70#define PCI_CSR_SIZE ((uint)(64 * 1024))
71
72/* Map additional physical space into well known virtual addresses. Due
73 * to virtual address mapping, these physical addresses are not accessible
74 * in a 1:1 virtual to physical mapping.
75 */
76#define ISA_IO_VIRT_ADDR ((uint)0xfa220000)
77#define ISA_IO_VIRT_SIZE ((uint)64 * 1024)
78
79/* Interrupt assignments.
80 * These are defined (and fixed) by the MBX hardware implementation.
81 */
82#define POWER_FAIL_INT SIU_IRQ0 /* Power fail */
83#define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */
84#define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */
85#define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */
86#define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */
87#define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */
88
89/* CPM Ethernet through SCCx.
90 *
91 * Bits in parallel I/O port registers that have to be set/cleared
92 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
93 * to the MBX860 board. Any two of the four available clocks could be
94 * used, and the MPC860 cookbook manual has an example using different
95 * clock pins.
96 */
97#define PA_ENET_RXD ((ushort)0x0001)
98#define PA_ENET_TXD ((ushort)0x0002)
99#define PA_ENET_TCLK ((ushort)0x0200)
100#define PA_ENET_RCLK ((ushort)0x0800)
101#define PC_ENET_TENA ((ushort)0x0001)
102#define PC_ENET_CLSN ((ushort)0x0010)
103#define PC_ENET_RENA ((ushort)0x0020)
104
105/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
106 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
107 */
108#define SICR_ENET_MASK ((uint)0x000000ff)
109#define SICR_ENET_CLKRT ((uint)0x0000003d)
110
111/* The MBX uses the 8259.
112*/
113#define NR_8259_INTS 16
114
115#endif /* !__ASSEMBLY__ */
116#endif /* __MACH_MBX_DEFS */
117#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c
deleted file mode 100644
index 62370f4a5a0f..000000000000
--- a/arch/ppc/platforms/mpc866ads_setup.c
+++ /dev/null
@@ -1,413 +0,0 @@
1/*arch/ppc/platforms/mpc866ads_setup.c
2 *
3 * Platform setup for the Freescale mpc866ads board
4 *
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * Copyright 2005-2006 MontaVista Software Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/param.h>
17#include <linux/string.h>
18#include <linux/ioport.h>
19#include <linux/device.h>
20
21#include <linux/fs_enet_pd.h>
22#include <linux/fs_uart_pd.h>
23#include <linux/mii.h>
24#include <linux/phy.h>
25
26#include <asm/delay.h>
27#include <asm/io.h>
28#include <asm/machdep.h>
29#include <asm/page.h>
30#include <asm/processor.h>
31#include <asm/system.h>
32#include <asm/time.h>
33#include <asm/ppcboot.h>
34#include <asm/8xx_immap.h>
35#include <asm/cpm1.h>
36#include <asm/ppc_sys.h>
37#include <asm/mpc8xx.h>
38
39extern unsigned char __res[];
40
41static void setup_fec1_ioports(struct fs_platform_info*);
42static void setup_scc1_ioports(struct fs_platform_info*);
43static void setup_smc1_ioports(struct fs_uart_platform_info*);
44static void setup_smc2_ioports(struct fs_uart_platform_info*);
45
46static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
47
48static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
49
50static struct fs_platform_info mpc8xx_enet_pdata[] = {
51 [fsid_fec1] = {
52 .rx_ring = 128,
53 .tx_ring = 16,
54 .rx_copybreak = 240,
55
56 .use_napi = 1,
57 .napi_weight = 17,
58
59 .init_ioports = setup_fec1_ioports,
60
61 .bus_id = "0:0f",
62 .has_phy = 1,
63 },
64 [fsid_scc1] = {
65 .rx_ring = 64,
66 .tx_ring = 8,
67 .rx_copybreak = 240,
68 .use_napi = 1,
69 .napi_weight = 17,
70
71
72 .init_ioports = setup_scc1_ioports,
73
74 .bus_id = "fixed@100:1",
75 },
76};
77
78static struct fs_uart_platform_info mpc866_uart_pdata[] = {
79 [fsid_smc1_uart] = {
80 .brg = 1,
81 .fs_no = fsid_smc1_uart,
82 .init_ioports = setup_smc1_ioports,
83 .tx_num_fifo = 4,
84 .tx_buf_size = 32,
85 .rx_num_fifo = 4,
86 .rx_buf_size = 32,
87 },
88 [fsid_smc2_uart] = {
89 .brg = 2,
90 .fs_no = fsid_smc2_uart,
91 .init_ioports = setup_smc2_ioports,
92 .tx_num_fifo = 4,
93 .tx_buf_size = 32,
94 .rx_num_fifo = 4,
95 .rx_buf_size = 32,
96 },
97};
98
99void __init board_init(void)
100{
101 volatile cpm8xx_t *cp = cpmp;
102 unsigned *bcsr_io;
103
104 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
105
106 if (bcsr_io == NULL) {
107 printk(KERN_CRIT "Could not remap BCSR1\n");
108 return;
109 }
110
111#ifdef CONFIG_SERIAL_CPM_SMC1
112 cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
113 clrbits32(bcsr_io,(0x80000000 >> 7));
114 cp->cp_smc[0].smc_smcm |= (SMCM_RX | SMCM_TX);
115 cp->cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
116#else
117 setbits32(bcsr_io,(0x80000000 >> 7));
118
119 cp->cp_pbpar &= ~(0x000000c0);
120 cp->cp_pbdir |= 0x000000c0;
121 cp->cp_smc[0].smc_smcmr = 0;
122 cp->cp_smc[0].smc_smce = 0;
123#endif
124
125#ifdef CONFIG_SERIAL_CPM_SMC2
126 cp->cp_simode &= ~(0xe0000000 >> 1);
127 cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
128 clrbits32(bcsr_io,(0x80000000 >> 13));
129 cp->cp_smc[1].smc_smcm |= (SMCM_RX | SMCM_TX);
130 cp->cp_smc[1].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
131#else
132 clrbits32(bcsr_io,(0x80000000 >> 13));
133 cp->cp_pbpar &= ~(0x00000c00);
134 cp->cp_pbdir |= 0x00000c00;
135 cp->cp_smc[1].smc_smcmr = 0;
136 cp->cp_smc[1].smc_smce = 0;
137#endif
138 iounmap(bcsr_io);
139}
140
141static void setup_fec1_ioports(struct fs_platform_info* pdata)
142{
143 immap_t *immap = (immap_t *) IMAP_ADDR;
144
145 setbits16(&immap->im_ioport.iop_pdpar, 0x1fff);
146 setbits16(&immap->im_ioport.iop_pddir, 0x1fff);
147}
148
149static void setup_scc1_ioports(struct fs_platform_info* pdata)
150{
151 immap_t *immap = (immap_t *) IMAP_ADDR;
152 unsigned *bcsr_io;
153
154 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
155
156 if (bcsr_io == NULL) {
157 printk(KERN_CRIT "Could not remap BCSR1\n");
158 return;
159 }
160
161 /* Enable the PHY.
162 */
163 clrbits32(bcsr_io,BCSR1_ETHEN);
164
165 /* Configure port A pins for Txd and Rxd.
166 */
167 /* Disable receive and transmit in case EPPC-Bug started it.
168 */
169 setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
170 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
171 clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD);
172
173 /* Configure port C pins to enable CLSN and RENA.
174 */
175 clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
176 clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
177 setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
178 /* Configure port A for TCLK and RCLK.
179 */
180 setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
181 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
182 clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
183 clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
184
185 /* Configure Serial Interface clock routing.
186 * First, clear all SCC bits to zero, then set the ones we want.
187 */
188 clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
189 setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
190
191 /* In the original SCC enet driver the following code is placed at
192 the end of the initialization */
193 setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
194 setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
195
196}
197
198static void setup_smc1_ioports(struct fs_uart_platform_info* pdata)
199{
200 immap_t *immap = (immap_t *) IMAP_ADDR;
201 unsigned *bcsr_io;
202 unsigned int iobits = 0x000000c0;
203
204 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
205
206 if (bcsr_io == NULL) {
207 printk(KERN_CRIT "Could not remap BCSR1\n");
208 return;
209 }
210
211 clrbits32(bcsr_io,BCSR1_RS232EN_1);
212 iounmap(bcsr_io);
213
214 setbits32(&immap->im_cpm.cp_pbpar, iobits);
215 clrbits32(&immap->im_cpm.cp_pbdir, iobits);
216 clrbits16(&immap->im_cpm.cp_pbodr, iobits);
217
218}
219
220static void setup_smc2_ioports(struct fs_uart_platform_info* pdata)
221{
222 immap_t *immap = (immap_t *) IMAP_ADDR;
223 unsigned *bcsr_io;
224 unsigned int iobits = 0x00000c00;
225
226 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
227
228 if (bcsr_io == NULL) {
229 printk(KERN_CRIT "Could not remap BCSR1\n");
230 return;
231 }
232
233 clrbits32(bcsr_io,BCSR1_RS232EN_2);
234
235 iounmap(bcsr_io);
236
237#ifndef CONFIG_SERIAL_CPM_ALT_SMC2
238 setbits32(&immap->im_cpm.cp_pbpar, iobits);
239 clrbits32(&immap->im_cpm.cp_pbdir, iobits);
240 clrbits16(&immap->im_cpm.cp_pbodr, iobits);
241#else
242 setbits16(&immap->im_ioport.iop_papar, iobits);
243 clrbits16(&immap->im_ioport.iop_padir, iobits);
244 clrbits16(&immap->im_ioport.iop_paodr, iobits);
245#endif
246
247}
248
249static int ma_count = 0;
250
251static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
252{
253 struct fs_platform_info *fpi;
254
255 volatile cpm8xx_t *cp;
256 bd_t *bd = (bd_t *) __res;
257 char *e;
258 int i;
259
260 /* Get pointer to Communication Processor */
261 cp = cpmp;
262
263 if(fs_no >= ARRAY_SIZE(mpc8xx_enet_pdata)) {
264 printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
265 return;
266 }
267
268
269 fpi = &mpc8xx_enet_pdata[fs_no];
270 fpi->fs_no = fs_no;
271 pdev->dev.platform_data = fpi;
272
273 e = (unsigned char *)&bd->bi_enetaddr;
274 for (i = 0; i < 6; i++)
275 fpi->macaddr[i] = *e++;
276
277 fpi->macaddr[5] += ma_count++;
278}
279
280static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
281 int idx)
282{
283 /* This is for FEC devices only */
284 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
285 return;
286 mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
287}
288
289static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
290 int idx)
291{
292 /* This is for SCC devices only */
293 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
294 return;
295
296 mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
297}
298
299static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev,
300 int idx)
301{
302 bd_t *bd = (bd_t *) __res;
303 struct fs_uart_platform_info *pinfo;
304 int num = ARRAY_SIZE(mpc866_uart_pdata);
305
306 int id = fs_uart_id_smc2fsid(idx);
307
308 /* no need to alter anything if console */
309 if ((id < num) && (!pdev->dev.platform_data)) {
310 pinfo = &mpc866_uart_pdata[id];
311 pinfo->uart_clk = bd->bi_intfreq;
312 pdev->dev.platform_data = pinfo;
313 }
314}
315
316static int mpc866ads_platform_notify(struct device *dev)
317{
318 static const struct platform_notify_dev_map dev_map[] = {
319 {
320 .bus_id = "fsl-cpm-fec",
321 .rtn = mpc866ads_fixup_fec_enet_pdata,
322 },
323 {
324 .bus_id = "fsl-cpm-scc",
325 .rtn = mpc866ads_fixup_scc_enet_pdata,
326 },
327 {
328 .bus_id = "fsl-cpm-smc:uart",
329 .rtn = mpc866ads_fixup_uart_pdata
330 },
331 {
332 .bus_id = NULL
333 }
334 };
335
336 platform_notify_map(dev_map,dev);
337
338 return 0;
339}
340
341int __init mpc866ads_init(void)
342{
343 bd_t *bd = (bd_t *) __res;
344 struct fs_mii_fec_platform_info* fmpi;
345
346 printk(KERN_NOTICE "mpc866ads: Init\n");
347
348 platform_notify = mpc866ads_platform_notify;
349
350 ppc_sys_device_initfunc();
351 ppc_sys_device_disable_all();
352
353#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1
354 ppc_sys_device_enable(MPC8xx_CPM_SCC1);
355#endif
356 ppc_sys_device_enable(MPC8xx_CPM_FEC1);
357
358 ppc_sys_device_enable(MPC8xx_MDIO_FEC);
359
360 fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
361 &mpc8xx_mdio_fec_pdata;
362
363 fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
364 /* No PHY interrupt line here */
365 fmpi->irq[0xf] = PHY_POLL;
366
367/* Since either of the uarts could be used as console, they need to ready */
368#ifdef CONFIG_SERIAL_CPM_SMC1
369 ppc_sys_device_enable(MPC8xx_CPM_SMC1);
370 ppc_sys_device_setfunc(MPC8xx_CPM_SMC1, PPC_SYS_FUNC_UART);
371#endif
372
373#ifdef CONFIG_SERIAL_CPM_SMC2
374 ppc_sys_device_enable(MPC8xx_CPM_SMC2);
375 ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
376#endif
377 ppc_sys_device_enable(MPC8xx_MDIO_FEC);
378
379 fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
380 &mpc8xx_mdio_fec_pdata;
381
382 fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
383 /* No PHY interrupt line here */
384 fmpi->irq[0xf] = PHY_POLL;
385
386 return 0;
387}
388
389/*
390 To prevent confusion, console selection is gross:
391 by 0 assumed SMC1 and by 1 assumed SMC2
392 */
393struct platform_device* early_uart_get_pdev(int index)
394{
395 bd_t *bd = (bd_t *) __res;
396 struct fs_uart_platform_info *pinfo;
397
398 struct platform_device* pdev = NULL;
399 if(index) { /*assume SMC2 here*/
400 pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC2];
401 pinfo = &mpc866_uart_pdata[1];
402 } else { /*over SMC1*/
403 pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC1];
404 pinfo = &mpc866_uart_pdata[0];
405 }
406
407 pinfo->uart_clk = bd->bi_intfreq;
408 pdev->dev.platform_data = pinfo;
409 ppc_sys_fixup_mem_resource(pdev, IMAP_ADDR);
410 return NULL;
411}
412
413arch_initcall(mpc866ads_init);
diff --git a/arch/ppc/platforms/mvme5100.c b/arch/ppc/platforms/mvme5100.c
deleted file mode 100644
index 053b54ac88f2..000000000000
--- a/arch/ppc/platforms/mvme5100.c
+++ /dev/null
@@ -1,340 +0,0 @@
1/*
2 * Board setup routines for the Motorola MVME5100.
3 *
4 * Author: Matt Porter <mporter@mvista.com>
5 *
6 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/pci.h>
17#include <linux/initrd.h>
18#include <linux/console.h>
19#include <linux/delay.h>
20#include <linux/seq_file.h>
21#include <linux/kdev_t.h>
22#include <linux/root_dev.h>
23
24#include <asm/system.h>
25#include <asm/pgtable.h>
26#include <asm/page.h>
27#include <asm/dma.h>
28#include <asm/io.h>
29#include <asm/machdep.h>
30#include <asm/open_pic.h>
31#include <asm/i8259.h>
32#include <asm/todc.h>
33#include <asm/pci-bridge.h>
34#include <asm/bootinfo.h>
35#include <asm/hawk.h>
36
37#include <platforms/pplus.h>
38#include <platforms/mvme5100.h>
39
40static u_char mvme5100_openpic_initsenses[16] __initdata = {
41 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* i8259 cascade */
42 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* TL16C550 UART 1,2 */
43 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet1 front panel or P2 */
44 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Hawk Watchdog 1,2 */
45 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* DS1621 thermal alarm */
46 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT0# */
47 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT1# */
48 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT2# */
49 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT3# */
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTA#, PMC2 INTB# */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTB#, PMC2 INTC# */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTC#, PMC2 INTD# */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTD#, PMC2 INTA# */
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet 2 (front panel) */
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Abort Switch */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* RTC Alarm */
57};
58
59static inline int
60mvme5100_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
61{
62 int irq;
63
64 static char pci_irq_table[][4] =
65 /*
66 * PCI IDSEL/INTPIN->INTLINE
67 * A B C D
68 */
69 {
70 { 0, 0, 0, 0 }, /* IDSEL 11 - Winbond */
71 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
72 { 21, 22, 23, 24 }, /* IDSEL 13 - Universe II */
73 { 18, 0, 0, 0 }, /* IDSEL 14 - Enet 1 */
74 { 0, 0, 0, 0 }, /* IDSEL 15 - unused */
75 { 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
76 { 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
77 { 0, 0, 0, 0 }, /* IDSEL 18 - unused */
78 { 29, 0, 0, 0 }, /* IDSEL 19 - Enet 2 */
79 { 0, 0, 0, 0 }, /* IDSEL 20 - PMCSPAN */
80 };
81
82 const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4;
83 irq = PCI_IRQ_TABLE_LOOKUP;
84 /* If lookup is zero, always return 0 */
85 if (!irq)
86 return 0;
87 else
88#ifdef CONFIG_MVME5100_IPMC761_PRESENT
89 /* If IPMC761 present, return table value */
90 return irq;
91#else
92 /* If IPMC761 not present, we don't have an i8259 so adjust */
93 return (irq - NUM_8259_INTERRUPTS);
94#endif
95}
96
97static void
98mvme5100_pcibios_fixup_resources(struct pci_dev *dev)
99{
100 int i;
101
102 if ((dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
103 (dev->device == PCI_DEVICE_ID_MOTOROLA_HAWK))
104 for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
105 {
106 dev->resource[i].start = 0;
107 dev->resource[i].end = 0;
108 }
109}
110
111static void __init
112mvme5100_setup_bridge(void)
113{
114 struct pci_controller* hose;
115
116 hose = pcibios_alloc_controller();
117
118 if (!hose)
119 return;
120
121 hose->first_busno = 0;
122 hose->last_busno = 0xff;
123 hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET;
124
125 pci_init_resource(&hose->io_resource, MVME5100_PCI_LOWER_IO,
126 MVME5100_PCI_UPPER_IO, IORESOURCE_IO,
127 "PCI host bridge");
128
129 pci_init_resource(&hose->mem_resources[0], MVME5100_PCI_LOWER_MEM,
130 MVME5100_PCI_UPPER_MEM, IORESOURCE_MEM,
131 "PCI host bridge");
132
133 hose->io_space.start = MVME5100_PCI_LOWER_IO;
134 hose->io_space.end = MVME5100_PCI_UPPER_IO;
135 hose->mem_space.start = MVME5100_PCI_LOWER_MEM;
136 hose->mem_space.end = MVME5100_PCI_UPPER_MEM;
137 hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE;
138
139 /* Use indirect method of Hawk */
140 setup_indirect_pci(hose, MVME5100_PCI_CONFIG_ADDR,
141 MVME5100_PCI_CONFIG_DATA);
142
143 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
144
145 ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources;
146 ppc_md.pci_swizzle = common_swizzle;
147 ppc_md.pci_map_irq = mvme5100_map_irq;
148}
149
150static void __init
151mvme5100_setup_arch(void)
152{
153 if ( ppc_md.progress )
154 ppc_md.progress("mvme5100_setup_arch: enter", 0);
155
156 loops_per_jiffy = 50000000 / HZ;
157
158#ifdef CONFIG_BLK_DEV_INITRD
159 if (initrd_start)
160 ROOT_DEV = Root_RAM0;
161 else
162#endif
163#ifdef CONFIG_ROOT_NFS
164 ROOT_DEV = Root_NFS;
165#else
166 ROOT_DEV = Root_SDA2;
167#endif
168
169 if ( ppc_md.progress )
170 ppc_md.progress("mvme5100_setup_arch: find_bridges", 0);
171
172 /* Setup PCI host bridge */
173 mvme5100_setup_bridge();
174
175 /* Find and map our OpenPIC */
176 hawk_mpic_init(MVME5100_PCI_MEM_OFFSET);
177 OpenPIC_InitSenses = mvme5100_openpic_initsenses;
178 OpenPIC_NumInitSenses = sizeof(mvme5100_openpic_initsenses);
179
180 printk("MVME5100 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
181
182 if ( ppc_md.progress )
183 ppc_md.progress("mvme5100_setup_arch: exit", 0);
184
185 return;
186}
187
188static void __init
189mvme5100_init2(void)
190{
191#ifdef CONFIG_MVME5100_IPMC761_PRESENT
192 request_region(0x00,0x20,"dma1");
193 request_region(0x20,0x20,"pic1");
194 request_region(0x40,0x20,"timer");
195 request_region(0x80,0x10,"dma page reg");
196 request_region(0xa0,0x20,"pic2");
197 request_region(0xc0,0x20,"dma2");
198#endif
199 return;
200}
201
202/*
203 * Interrupt setup and service.
204 * Have MPIC on HAWK and cascaded 8259s on Winbond cascaded to MPIC.
205 */
206static void __init
207mvme5100_init_IRQ(void)
208{
209#ifdef CONFIG_MVME5100_IPMC761_PRESENT
210 int i;
211#endif
212
213 if ( ppc_md.progress )
214 ppc_md.progress("init_irq: enter", 0);
215
216 openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
217#ifdef CONFIG_MVME5100_IPMC761_PRESENT
218 openpic_init(NUM_8259_INTERRUPTS);
219 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
220 &i8259_irq);
221
222 i8259_init(0, 0);
223#else
224 openpic_init(0);
225#endif
226
227 if ( ppc_md.progress )
228 ppc_md.progress("init_irq: exit", 0);
229
230 return;
231}
232
233/*
234 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
235 */
236static __inline__ void
237mvme5100_set_bat(void)
238{
239 mb();
240 mtspr(SPRN_DBAT1U, 0xf0001ffe);
241 mtspr(SPRN_DBAT1L, 0xf000002a);
242 mb();
243}
244
245static unsigned long __init
246mvme5100_find_end_of_memory(void)
247{
248 return hawk_get_mem_size(MVME5100_HAWK_SMC_BASE);
249}
250
251static void __init
252mvme5100_map_io(void)
253{
254 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
255 ioremap_base = 0xfe000000;
256}
257
258static void
259mvme5100_reset_board(void)
260{
261 local_irq_disable();
262
263 /* Set exception prefix high - to the firmware */
264 _nmask_and_or_msr(0, MSR_IP);
265
266 out_8((u_char *)MVME5100_BOARD_MODRST_REG, 0x01);
267
268 return;
269}
270
271static void
272mvme5100_restart(char *cmd)
273{
274 volatile ulong i = 10000000;
275
276 mvme5100_reset_board();
277
278 while (i-- > 0);
279 panic("restart failed\n");
280}
281
282static void
283mvme5100_halt(void)
284{
285 local_irq_disable();
286 while (1);
287}
288
289static void
290mvme5100_power_off(void)
291{
292 mvme5100_halt();
293}
294
295static int
296mvme5100_show_cpuinfo(struct seq_file *m)
297{
298 seq_printf(m, "vendor\t\t: Motorola\n");
299 seq_printf(m, "machine\t\t: MVME5100\n");
300
301 return 0;
302}
303
304TODC_ALLOC();
305
306void __init
307platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
308 unsigned long r6, unsigned long r7)
309{
310 parse_bootinfo(find_bootinfo());
311 mvme5100_set_bat();
312
313 isa_io_base = MVME5100_ISA_IO_BASE;
314 isa_mem_base = MVME5100_ISA_MEM_BASE;
315 pci_dram_offset = MVME5100_PCI_DRAM_OFFSET;
316
317 ppc_md.setup_arch = mvme5100_setup_arch;
318 ppc_md.show_cpuinfo = mvme5100_show_cpuinfo;
319 ppc_md.init_IRQ = mvme5100_init_IRQ;
320 ppc_md.get_irq = openpic_get_irq;
321 ppc_md.init = mvme5100_init2;
322
323 ppc_md.restart = mvme5100_restart;
324 ppc_md.power_off = mvme5100_power_off;
325 ppc_md.halt = mvme5100_halt;
326
327 ppc_md.find_end_of_memory = mvme5100_find_end_of_memory;
328 ppc_md.setup_io_mappings = mvme5100_map_io;
329
330 TODC_INIT(TODC_TYPE_MK48T37, MVME5100_NVRAM_AS0, MVME5100_NVRAM_AS1,
331 MVME5100_NVRAM_DATA, 8);
332
333 ppc_md.time_init = todc_time_init;
334 ppc_md.set_rtc_time = todc_set_rtc_time;
335 ppc_md.get_rtc_time = todc_get_rtc_time;
336 ppc_md.calibrate_decr = todc_calibrate_decr;
337
338 ppc_md.nvram_read_val = todc_m48txx_read_val;
339 ppc_md.nvram_write_val = todc_m48txx_write_val;
340}
diff --git a/arch/ppc/platforms/mvme5100.h b/arch/ppc/platforms/mvme5100.h
deleted file mode 100644
index fbb5495165c7..000000000000
--- a/arch/ppc/platforms/mvme5100.h
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * arch/ppc/platforms/mvme5100.h
3 *
4 * Definitions for Motorola MVME5100.
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_MVME5100_H__
16#define __ASM_MVME5100_H__
17
18#define MVME5100_HAWK_SMC_BASE 0xfef80000
19
20#define MVME5100_PCI_CONFIG_ADDR 0xfe000cf8
21#define MVME5100_PCI_CONFIG_DATA 0xfe000cfc
22
23#define MVME5100_PCI_IO_BASE 0xfe000000
24#define MVME5100_PCI_MEM_BASE 0x80000000
25
26#define MVME5100_PCI_MEM_OFFSET 0x00000000
27
28#define MVME5100_PCI_DRAM_OFFSET 0x00000000
29#define MVME5100_ISA_MEM_BASE 0x00000000
30#define MVME5100_ISA_IO_BASE MVME5100_PCI_IO_BASE
31
32#define MVME5100_PCI_LOWER_MEM 0x80000000
33#define MVME5100_PCI_UPPER_MEM 0xf3f7ffff
34#define MVME5100_PCI_LOWER_IO 0x00000000
35#define MVME5100_PCI_UPPER_IO 0x0077ffff
36
37/* MVME5100 board register addresses. */
38#define MVME5100_BOARD_STATUS_REG 0xfef88080
39#define MVME5100_BOARD_MODFAIL_REG 0xfef88090
40#define MVME5100_BOARD_MODRST_REG 0xfef880a0
41#define MVME5100_BOARD_TBEN_REG 0xfef880c0
42#define MVME5100_BOARD_SW_READ_REG 0xfef880e0
43#define MVME5100_BOARD_GEO_ADDR_REG 0xfef880e8
44#define MVME5100_BOARD_EXT_FEATURE1_REG 0xfef880f0
45#define MVME5100_BOARD_EXT_FEATURE2_REG 0xfef88100
46
47/* Define the NVRAM/RTC address strobe & data registers */
48#define MVME5100_PHYS_NVRAM_AS0 0xfef880c8
49#define MVME5100_PHYS_NVRAM_AS1 0xfef880d0
50#define MVME5100_PHYS_NVRAM_DATA 0xfef880d8
51
52#define MVME5100_NVRAM_AS0 (MVME5100_PHYS_NVRAM_AS0 - MVME5100_ISA_IO_BASE)
53#define MVME5100_NVRAM_AS1 (MVME5100_PHYS_NVRAM_AS1 - MVME5100_ISA_IO_BASE)
54#define MVME5100_NVRAM_DATA (MVME5100_PHYS_NVRAM_DATA - MVME5100_ISA_IO_BASE)
55
56/* UART clock, addresses, and irq */
57#define MVME5100_BASE_BAUD 1843200
58#define MVME5100_SERIAL_1 0xfef88000
59#define MVME5100_SERIAL_2 0xfef88200
60#ifdef CONFIG_MVME5100_IPMC761_PRESENT
61#define MVME5100_SERIAL_IRQ 17
62#else
63#define MVME5100_SERIAL_IRQ 1
64#endif
65
66#define RS_TABLE_SIZE 4
67
68#define BASE_BAUD ( MVME5100_BASE_BAUD / 16 )
69
70#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
71
72/* All UART IRQs are wire-OR'd to one MPIC IRQ */
73#define STD_SERIAL_PORT_DFNS \
74 { 0, BASE_BAUD, MVME5100_SERIAL_1, \
75 MVME5100_SERIAL_IRQ, \
76 STD_COM_FLAGS, /* ttyS0 */ \
77 iomem_base: (unsigned char *)MVME5100_SERIAL_1, \
78 iomem_reg_shift: 4, \
79 io_type: SERIAL_IO_MEM }, \
80 { 0, BASE_BAUD, MVME5100_SERIAL_2, \
81 MVME5100_SERIAL_IRQ, \
82 STD_COM_FLAGS, /* ttyS1 */ \
83 iomem_base: (unsigned char *)MVME5100_SERIAL_2, \
84 iomem_reg_shift: 4, \
85 io_type: SERIAL_IO_MEM },
86
87#define SERIAL_PORT_DFNS \
88 STD_SERIAL_PORT_DFNS
89
90#endif /* __ASM_MVME5100_H__ */
91#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/pal4.h b/arch/ppc/platforms/pal4.h
deleted file mode 100644
index 8569c423d887..000000000000
--- a/arch/ppc/platforms/pal4.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * Definitions for SBS Palomar IV board
3 *
4 * Author: Dan Cox
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifndef __PPC_PLATFORMS_PAL4_H
13#define __PPC_PLATFORMS_PAL4_H
14
15#define PAL4_NVRAM 0xfffc0000
16#define PAL4_NVRAM_SIZE 0x8000
17
18#define PAL4_DRAM 0xfff80000
19#define PAL4_DRAM_BR_MASK 0xc0
20#define PAL4_DRAM_BR_SHIFT 6
21#define PAL4_DRAM_RESET 0x10
22#define PAL4_DRAM_EREADY 0x40
23
24#define PAL4_MISC 0xfff80004
25#define PAL4_MISC_FB_MASK 0xc0
26#define PAL4_MISC_FLASH 0x20 /* StratFlash mapping: 1->0xff80, 0->0xfff0 */
27#define PAL4_MISC_MISC 0x08
28#define PAL4_MISC_BITF 0x02
29#define PAL4_MISC_NVKS 0x01
30
31#define PAL4_L2 0xfff80008
32#define PAL4_L2_MASK 0x07
33
34#define PAL4_PLDR 0xfff8000c
35
36/* Only two Ethernet devices on the board... */
37#define PAL4_ETH 31
38#define PAL4_INTA 20
39
40#endif /* __PPC_PLATFORMS_PAL4_H */
diff --git a/arch/ppc/platforms/pal4_pci.c b/arch/ppc/platforms/pal4_pci.c
deleted file mode 100644
index d81ae1c7e1cf..000000000000
--- a/arch/ppc/platforms/pal4_pci.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * PCI support for SBS Palomar IV
3 *
4 * Author: Dan Cox
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15
16#include <asm/byteorder.h>
17#include <asm/machdep.h>
18#include <asm/io.h>
19#include <asm/pci-bridge.h>
20#include <asm/uaccess.h>
21
22#include <syslib/cpc700.h>
23
24#include "pal4.h"
25
26/* not much to this.... */
27static inline int __init
28pal4_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
29{
30 if (idsel == 9)
31 return PAL4_ETH;
32 else
33 return PAL4_INTA + (idsel - 3);
34}
35
36void __init
37pal4_find_bridges(void)
38{
39 struct pci_controller *hose;
40
41 hose = pcibios_alloc_controller();
42 if (!hose)
43 return;
44
45 hose->first_busno = 0;
46 hose->last_busno = 0xff;
47 hose->pci_mem_offset = 0;
48
49 /* Could snatch these from the CPC700.... */
50 pci_init_resource(&hose->io_resource,
51 0x0,
52 0x03ffffff,
53 IORESOURCE_IO,
54 "PCI host bridge");
55
56 pci_init_resource(&hose->mem_resources[0],
57 0x90000000,
58 0x9fffffff,
59 IORESOURCE_MEM,
60 "PCI host bridge");
61
62 hose->io_space.start = 0x00800000;
63 hose->io_space.end = 0x03ffffff;
64 hose->mem_space.start = 0x90000000;
65 hose->mem_space.end = 0x9fffffff;
66 hose->io_base_virt = (void *) 0xf8000000;
67
68 setup_indirect_pci(hose, CPC700_PCI_CONFIG_ADDR,
69 CPC700_PCI_CONFIG_DATA);
70
71 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
72
73 ppc_md.pci_swizzle = common_swizzle;
74 ppc_md.pci_map_irq = pal4_map_irq;
75}
diff --git a/arch/ppc/platforms/pal4_serial.h b/arch/ppc/platforms/pal4_serial.h
deleted file mode 100644
index a75343224cfd..000000000000
--- a/arch/ppc/platforms/pal4_serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Definitions for SBS PalomarIV serial support
3 *
4 * Author: Dan Cox
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifndef __PPC_PAL4_SERIAL_H
13#define __PPC_PAL4_SERIAL_H
14
15#define CPC700_SERIAL_1 0xff600300
16#define CPC700_SERIAL_2 0xff600400
17
18#define RS_TABLE_SIZE 2
19#define BASE_BAUD (33333333 / 4 / 16)
20
21#ifdef CONFIG_SERIAL_DETECT_IRQ
22#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
23#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
24#else
25#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
26#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF)
27#endif
28
29#define SERIAL_PORT_DFNS \
30 {0, BASE_BAUD, CPC700_SERIAL_1, 3, STD_COM_FLAGS, \
31 iomem_base: (unsigned char *) CPC700_SERIAL_1, \
32 io_type: SERIAL_IO_MEM}, /* ttyS0 */ \
33 {0, BASE_BAUD, CPC700_SERIAL_2, 4, STD_COM_FLAGS, \
34 iomem_base: (unsigned char *) CPC700_SERIAL_2, \
35 io_type: SERIAL_IO_MEM}
36
37#endif
diff --git a/arch/ppc/platforms/pal4_setup.c b/arch/ppc/platforms/pal4_setup.c
deleted file mode 100644
index 3da47d9ec7a2..000000000000
--- a/arch/ppc/platforms/pal4_setup.c
+++ /dev/null
@@ -1,173 +0,0 @@
1/*
2 * Board setup routines for the SBS PalomarIV.
3 *
4 * Author: Dan Cox
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/time.h>
18#include <linux/irq.h>
19#include <linux/kdev_t.h>
20#include <linux/initrd.h>
21#include <linux/console.h>
22#include <linux/seq_file.h>
23#include <linux/root_dev.h>
24
25#include <asm/io.h>
26#include <asm/todc.h>
27#include <asm/bootinfo.h>
28#include <asm/machdep.h>
29
30#include <syslib/cpc700.h>
31
32#include "pal4.h"
33
34extern void pal4_find_bridges(void);
35
36unsigned int cpc700_irq_assigns[][2] = {
37 {1, 1}, /* IRQ 0: ECC correctable error */
38 {1, 1}, /* IRQ 1: PCI write to memory range */
39 {0, 1}, /* IRQ 2: PCI write to command register */
40 {0, 1}, /* IRQ 3: UART 0 */
41 {0, 1}, /* IRQ 4: UART 1 */
42 {0, 1}, /* IRQ 5: ICC 0 */
43 {0, 1}, /* IRQ 6: ICC 1 */
44 {0, 1}, /* IRQ 7: GPT compare 0 */
45 {0, 1}, /* IRQ 8: GPT compare 1 */
46 {0, 1}, /* IRQ 9: GPT compare 2 */
47 {0, 1}, /* IRQ 10: GPT compare 3 */
48 {0, 1}, /* IRQ 11: GPT compare 4 */
49 {0, 1}, /* IRQ 12: GPT capture 0 */
50 {0, 1}, /* IRQ 13: GPT capture 1 */
51 {0, 1}, /* IRQ 14: GPT capture 2 */
52 {0, 1}, /* IRQ 15: GPT capture 3 */
53 {0, 1}, /* IRQ 16: GPT capture 4 */
54 {0, 0}, /* IRQ 17: reserved */
55 {0, 0}, /* IRQ 18: reserved */
56 {0, 0}, /* IRQ 19: reserved */
57 {0, 0}, /* IRQ 20: reserved */
58 {0, 1}, /* IRQ 21: Ethernet */
59 {0, 0}, /* IRQ 22: reserved */
60 {0, 0}, /* IRQ 23: reserved */
61 {0, 0}, /* IRQ 24: resreved */
62 {0, 0}, /* IRQ 25: reserved */
63 {0, 0}, /* IRQ 26: reserved */
64 {0, 0}, /* IRQ 27: reserved */
65 {0, 0}, /* IRQ 28: reserved */
66 {0, 0}, /* IRQ 29: reserved */
67 {0, 0}, /* IRQ 30: reserved */
68 {0, 0}, /* IRQ 31: reserved */
69};
70
71static int
72pal4_show_cpuinfo(struct seq_file *m)
73{
74 seq_printf(m, "board\t\t: SBS Palomar IV\n");
75
76 return 0;
77}
78
79static void
80pal4_restart(char *cmd)
81{
82 local_irq_disable();
83 __asm__ __volatile__("lis 3,0xfff0\n \
84 ori 3,3,0x100\n \
85 mtspr 26,3\n \
86 li 3,0\n \
87 mtspr 27,3\n \
88 rfi");
89
90 for(;;);
91}
92
93static void
94pal4_power_off(void)
95{
96 local_irq_disable();
97 for(;;);
98}
99
100static void
101pal4_halt(void)
102{
103 pal4_power_off();
104}
105
106TODC_ALLOC();
107
108static void __init
109pal4_setup_arch(void)
110{
111 unsigned long l2;
112
113 TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
114 ioremap(PAL4_NVRAM, PAL4_NVRAM_SIZE), 8);
115
116 pal4_find_bridges();
117
118#ifdef CONFIG_BLK_DEV_INITRD
119 if (initrd_start)
120 ROOT_DEV = Root_RAM0;
121 else
122#endif
123 ROOT_DEV = Root_NFS;
124
125 /* The L2 gets disabled in the bootloader, but all the proper
126 bits should be present from the fw, so just re-enable it */
127 l2 = _get_L2CR();
128 if (!(l2 & L2CR_L2E)) {
129 /* presume that it was initially set if the size is
130 still present. */
131 if (l2 ^ L2CR_L2SIZ_MASK)
132 _set_L2CR(l2 | L2CR_L2E);
133 else
134 printk("L2 not set by firmware; left disabled.\n");
135 }
136}
137
138static void __init
139pal4_map_io(void)
140{
141 io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
142}
143
144void __init
145platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
146 unsigned long r6, unsigned long r7)
147{
148 parse_bootinfo(find_bootinfo());
149
150 isa_io_base = 0 /*PAL4_ISA_IO_BASE*/;
151 pci_dram_offset = 0 /*PAL4_PCI_SYS_MEM_BASE*/;
152
153 ppc_md.setup_arch = pal4_setup_arch;
154 ppc_md.show_cpuinfo = pal4_show_cpuinfo;
155
156 ppc_md.setup_io_mappings = pal4_map_io;
157
158 ppc_md.init_IRQ = cpc700_init_IRQ;
159 ppc_md.get_irq = cpc700_get_irq;
160
161 ppc_md.restart = pal4_restart;
162 ppc_md.halt = pal4_halt;
163 ppc_md.power_off = pal4_power_off;
164
165 ppc_md.time_init = todc_time_init;
166 ppc_md.set_rtc_time = todc_set_rtc_time;
167 ppc_md.get_rtc_time = todc_get_rtc_time;
168 ppc_md.calibrate_decr = todc_calibrate_decr;
169
170 ppc_md.nvram_read_val = todc_direct_read_val;
171 ppc_md.nvram_write_val = todc_direct_write_val;
172}
173
diff --git a/arch/ppc/platforms/pcu_e.h b/arch/ppc/platforms/pcu_e.h
deleted file mode 100644
index a2c03a22875e..000000000000
--- a/arch/ppc/platforms/pcu_e.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Siemens PCU E board specific definitions
3 *
4 * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifndef __MACH_PCU_E_H
8#define __MACH_PCU_E_H
9
10
11#include <asm/ppcboot.h>
12
13#define PCU_E_IMMR_BASE 0xFE000000 /* phys. addr of IMMR */
14#define PCU_E_IMAP_SIZE (64 * 1024) /* size of mapped area */
15
16#define IMAP_ADDR PCU_E_IMMR_BASE /* physical base address of IMMR area */
17#define IMAP_SIZE PCU_E_IMAP_SIZE /* mapped size of IMMR area */
18
19#define FEC_INTERRUPT 15 /* = SIU_LEVEL7 */
20#define DEC_INTERRUPT 13 /* = SIU_LEVEL6 */
21#define CPM_INTERRUPT 11 /* = SIU_LEVEL5 (was: SIU_LEVEL2) */
22
23/* We don't use the 8259.
24*/
25#define NR_8259_INTS 0
26
27#endif /* __MACH_PCU_E_H */
diff --git a/arch/ppc/platforms/powerpmc250.c b/arch/ppc/platforms/powerpmc250.c
deleted file mode 100644
index 162dc85ff7be..000000000000
--- a/arch/ppc/platforms/powerpmc250.c
+++ /dev/null
@@ -1,378 +0,0 @@
1/*
2 * Board setup routines for Force PowerPMC-250 Processor PMC
3 *
4 * Author: Troy Benjegerdes <tbenjegerdes@mvista.com>
5 * Borrowed heavily from prpmc750_*.c by
6 * Matt Porter <mporter@mvista.com>
7 *
8 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/types.h>
22#include <linux/major.h>
23#include <linux/initrd.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29
30#include <asm/byteorder.h>
31#include <asm/system.h>
32#include <asm/pgtable.h>
33#include <asm/page.h>
34#include <asm/dma.h>
35#include <asm/io.h>
36#include <asm/irq.h>
37#include <asm/machdep.h>
38#include <asm/time.h>
39#include <platforms/powerpmc250.h>
40#include <asm/open_pic.h>
41#include <asm/pci-bridge.h>
42#include <asm/mpc10x.h>
43#include <asm/uaccess.h>
44#include <asm/bootinfo.h>
45
46extern void powerpmc250_find_bridges(void);
47extern unsigned long loops_per_jiffy;
48
49static u_char powerpmc250_openpic_initsenses[] __initdata =
50{
51 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
52 1, /* PMC INTA (also MPC107 output interrupt INTA) */
53 1, /* PMC INTB (also I82559 Ethernet controller) */
54 1, /* PMC INTC */
55 1, /* PMC INTD */
56 0, /* DUART interrupt (active high) */
57};
58
59static int
60powerpmc250_show_cpuinfo(struct seq_file *m)
61{
62 seq_printf(m,"machine\t\t: Force PowerPMC250\n");
63
64 return 0;
65}
66
67static void __init
68powerpmc250_setup_arch(void)
69{
70 /* init to some ~sane value until calibrate_delay() runs */
71 loops_per_jiffy = 50000000/HZ;
72
73 /* Lookup PCI host bridges */
74 powerpmc250_find_bridges();
75
76#ifdef CONFIG_BLK_DEV_INITRD
77 if (initrd_start)
78 ROOT_DEV = Root_RAM0;
79 else
80#endif
81#ifdef CONFIG_ROOT_NFS
82 ROOT_DEV = Root_NFS;
83#else
84 ROOT_DEV = Root_SDA2;
85#endif
86
87 printk("Force PowerPMC250 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
88}
89
90#if 0
91/*
92 * Compute the PrPMC750's bus speed using the baud clock as a
93 * reference.
94 */
95unsigned long __init powerpmc250_get_bus_speed(void)
96{
97 unsigned long tbl_start, tbl_end;
98 unsigned long current_state, old_state, bus_speed;
99 unsigned char lcr, dll, dlm;
100 int baud_divisor, count;
101
102 /* Read the UART's baud clock divisor */
103 lcr = readb(PRPMC750_SERIAL_0_LCR);
104 writeb(lcr | UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
105 dll = readb(PRPMC750_SERIAL_0_DLL);
106 dlm = readb(PRPMC750_SERIAL_0_DLM);
107 writeb(lcr & ~UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
108 baud_divisor = (dlm << 8) | dll;
109
110 /*
111 * Use the baud clock divisor and base baud clock
112 * to determine the baud rate and use that as
113 * the number of baud clock edges we use for
114 * the time base sample. Make it half the baud
115 * rate.
116 */
117 count = PRPMC750_BASE_BAUD / (baud_divisor * 16);
118
119 /* Find the first edge of the baud clock */
120 old_state = readb(PRPMC750_STATUS_REG) & PRPMC750_BAUDOUT_MASK;
121 do {
122 current_state = readb(PRPMC750_STATUS_REG) &
123 PRPMC750_BAUDOUT_MASK;
124 } while(old_state == current_state);
125
126 old_state = current_state;
127
128 /* Get the starting time base value */
129 tbl_start = get_tbl();
130
131 /*
132 * Loop until we have found a number of edges equal
133 * to half the count (half the baud rate)
134 */
135 do {
136 do {
137 current_state = readb(PRPMC750_STATUS_REG) &
138 PRPMC750_BAUDOUT_MASK;
139 } while(old_state == current_state);
140 old_state = current_state;
141 } while (--count);
142
143 /* Get the ending time base value */
144 tbl_end = get_tbl();
145
146 /* Compute bus speed */
147 bus_speed = (tbl_end-tbl_start)*128;
148
149 return bus_speed;
150}
151#endif
152
153static void __init
154powerpmc250_calibrate_decr(void)
155{
156 unsigned long freq;
157 int divisor = 4;
158
159 //freq = powerpmc250_get_bus_speed();
160#warning hardcoded bus freq
161 freq = 100000000;
162
163 tb_ticks_per_jiffy = freq / (HZ * divisor);
164 tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
165}
166
167static void
168powerpmc250_restart(char *cmd)
169{
170 local_irq_disable();
171 /* Hard reset */
172 writeb(0x11, 0xfe000332);
173 while(1);
174}
175
176static void
177powerpmc250_halt(void)
178{
179 local_irq_disable();
180 while (1);
181}
182
183static void
184powerpmc250_power_off(void)
185{
186 powerpmc250_halt();
187}
188
189static void __init
190powerpmc250_init_IRQ(void)
191{
192
193 OpenPIC_InitSenses = powerpmc250_openpic_initsenses;
194 OpenPIC_NumInitSenses = sizeof(powerpmc250_openpic_initsenses);
195 mpc10x_set_openpic();
196}
197
198/*
199 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
200 */
201static __inline__ void
202powerpmc250_set_bat(void)
203{
204 unsigned long bat3u, bat3l;
205 static int mapping_set = 0;
206
207 if (!mapping_set)
208 {
209 __asm__ __volatile__(
210 " lis %0,0xf000\n \
211 ori %1,%0,0x002a\n \
212 ori %0,%0,0x1ffe\n \
213 mtspr 0x21e,%0\n \
214 mtspr 0x21f,%1\n \
215 isync\n \
216 sync "
217 : "=r" (bat3u), "=r" (bat3l));
218
219 mapping_set = 1;
220 }
221 return;
222}
223
224static unsigned long __init
225powerpmc250_find_end_of_memory(void)
226{
227 /* Cover I/O space with a BAT */
228 /* yuck, better hope your ram size is a power of 2 -- paulus */
229 powerpmc250_set_bat();
230
231 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
232}
233
234static void __init
235powerpmc250_map_io(void)
236{
237 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
238}
239
240void __init
241platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
242 unsigned long r6, unsigned long r7)
243{
244 parse_bootinfo(find_bootinfo());
245
246#ifdef CONFIG_BLK_DEV_INITRD
247 if ( r4 )
248 {
249 initrd_start = r4 + KERNELBASE;
250 initrd_end = r5 + KERNELBASE;
251 }
252#endif
253
254 /* Copy cmd_line parameters */
255 if ( r6)
256 {
257 *(char *)(r7 + KERNELBASE) = 0;
258 strcpy(cmd_line, (char *)(r6 + KERNELBASE));
259 }
260
261 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
262 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
263 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
264
265 ppc_md.setup_arch = powerpmc250_setup_arch;
266 ppc_md.show_cpuinfo = powerpmc250_show_cpuinfo;
267 ppc_md.init_IRQ = powerpmc250_init_IRQ;
268 ppc_md.get_irq = openpic_get_irq;
269
270 ppc_md.find_end_of_memory = powerpmc250_find_end_of_memory;
271 ppc_md.setup_io_mappings = powerpmc250_map_io;
272
273 ppc_md.restart = powerpmc250_restart;
274 ppc_md.power_off = powerpmc250_power_off;
275 ppc_md.halt = powerpmc250_halt;
276
277 /* PowerPMC250 has no timekeeper part */
278 ppc_md.time_init = NULL;
279 ppc_md.get_rtc_time = NULL;
280 ppc_md.set_rtc_time = NULL;
281 ppc_md.calibrate_decr = powerpmc250_calibrate_decr;
282}
283
284
285/*
286 * (This used to be arch/ppc/platforms/powerpmc250_pci.c)
287 *
288 * PCI support for Force PowerPMC250
289 *
290 */
291
292#undef DEBUG
293#ifdef DEBUG
294#define DBG(x...) printk(x)
295#else
296#define DBG(x...)
297#endif /* DEBUG */
298
299static inline int __init
300powerpmc250_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
301{
302 static char pci_irq_table[][4] =
303 /*
304 * PCI IDSEL/INTPIN->INTLINE
305 * A B C D
306 */
307 {
308 {17, 0, 0, 0}, /* Device 11 - 82559 */
309 {0, 0, 0, 0}, /* 12 */
310 {0, 0, 0, 0}, /* 13 */
311 {0, 0, 0, 0}, /* 14 */
312 {0, 0, 0, 0}, /* 15 */
313 {16, 17, 18, 19}, /* Device 16 - PMC A1?? */
314 };
315 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
316 return PCI_IRQ_TABLE_LOOKUP;
317};
318
319static int
320powerpmc250_exclude_device(u_char bus, u_char devfn)
321{
322 /*
323 * While doing PCI Scan the MPC107 will 'detect' itself as
324 * device on the PCI Bus, will create an incorrect response and
325 * later will respond incorrectly to Configuration read coming
326 * from another device.
327 *
328 * The work around is that when doing a PCI Scan one
329 * should skip its own device number in the scan.
330 *
331 * The top IDsel is AD13 and the middle is AD14.
332 *
333 * -- Note from force
334 */
335
336 if ((bus == 0) && (PCI_SLOT(devfn) == 13 || PCI_SLOT(devfn) == 14)) {
337 return PCIBIOS_DEVICE_NOT_FOUND;
338 }
339 else {
340 return PCIBIOS_SUCCESSFUL;
341 }
342}
343
344void __init
345powerpmc250_find_bridges(void)
346{
347 struct pci_controller* hose;
348
349 hose = pcibios_alloc_controller();
350 if (!hose){
351 printk("Can't allocate PCI 'hose' structure!!!\n");
352 return;
353 }
354
355 hose->first_busno = 0;
356 hose->last_busno = 0xff;
357
358 if (mpc10x_bridge_init(hose,
359 MPC10X_MEM_MAP_B,
360 MPC10X_MEM_MAP_B,
361 MPC10X_MAPB_EUMB_BASE) == 0) {
362
363 hose->mem_resources[0].end = 0xffffffff;
364
365 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
366
367 /* ppc_md.pcibios_fixup = pcore_pcibios_fixup; */
368 ppc_md.pci_swizzle = common_swizzle;
369
370 ppc_md.pci_exclude_device = powerpmc250_exclude_device;
371 ppc_md.pci_map_irq = powerpmc250_map_irq;
372 } else {
373 if (ppc_md.progress)
374 ppc_md.progress("Bridge init failed", 0x100);
375 printk("Host bridge init failed\n");
376 }
377
378}
diff --git a/arch/ppc/platforms/powerpmc250.h b/arch/ppc/platforms/powerpmc250.h
deleted file mode 100644
index d33ad8dc0439..000000000000
--- a/arch/ppc/platforms/powerpmc250.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * arch/ppc/platforms/powerpmc250.h
3 *
4 * Definitions for Force PowerPMC-250 board support
5 *
6 * Author: Troy Benjegerdes <tbenjegerdes@mvista.com>
7 *
8 * Borrowed heavily from prpmc750.h by Matt Porter <mporter@mvista.com>
9 *
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#ifndef __ASMPPC_POWERPMC250_H
17#define __ASMPPC_POWERPMC250_H
18
19#define POWERPMC250_PCI_CONFIG_ADDR 0x80000cf8
20#define POWERPMC250_PCI_CONFIG_DATA 0x80000cfc
21
22#define POWERPMC250_PCI_PHY_MEM_BASE 0xc0000000
23#define POWERPMC250_PCI_MEM_BASE 0xf0000000
24#define POWERPMC250_PCI_IO_BASE 0x80000000
25
26#define POWERPMC250_ISA_IO_BASE POWERPMC250_PCI_IO_BASE
27#define POWERPMC250_ISA_MEM_BASE POWERPMC250_PCI_MEM_BASE
28#define POWERPMC250_PCI_MEM_OFFSET POWERPMC250_PCI_PHY_MEM_BASE
29
30#define POWERPMC250_SYS_MEM_BASE 0x80000000
31
32#define POWERPMC250_HAWK_SMC_BASE 0xfef80000
33
34#define POWERPMC250_BASE_BAUD 12288000
35#define POWERPMC250_SERIAL 0xff000000
36#define POWERPMC250_SERIAL_IRQ 20
37
38/* UART Defines. */
39#define RS_TABLE_SIZE 1
40
41#define BASE_BAUD (POWERPMC250_BASE_BAUD / 16)
42
43#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
44
45#define SERIAL_PORT_DFNS \
46 { 0, BASE_BAUD, POWERPMC250_SERIAL, POWERPMC250_SERIAL_IRQ, \
47 STD_COM_FLAGS, /* ttyS0 */ \
48 iomem_base: (u8 *)POWERPMC250_SERIAL, \
49 iomem_reg_shift: 0, \
50 io_type: SERIAL_IO_MEM }
51
52#endif /* __ASMPPC_POWERPMC250_H */
diff --git a/arch/ppc/platforms/pplus.c b/arch/ppc/platforms/pplus.c
deleted file mode 100644
index cbcac85c7a78..000000000000
--- a/arch/ppc/platforms/pplus.c
+++ /dev/null
@@ -1,844 +0,0 @@
1/*
2 * Board and PCI setup routines for MCG PowerPlus
3 *
4 * Author: Randy Vinson <rvinson@mvista.com>
5 *
6 * Derived from original PowerPlus PReP work by
7 * Cort Dougan, Johnnie Peters, Matt Porter, and
8 * Troy Benjegerdes.
9 *
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20#include <linux/console.h>
21#include <linux/pci.h>
22#include <linux/seq_file.h>
23#include <linux/root_dev.h>
24
25#include <asm/system.h>
26#include <asm/io.h>
27#include <asm/pgtable.h>
28#include <asm/dma.h>
29#include <asm/machdep.h>
30#include <asm/prep_nvram.h>
31#include <asm/vga.h>
32#include <asm/i8259.h>
33#include <asm/open_pic.h>
34#include <asm/hawk.h>
35#include <asm/todc.h>
36#include <asm/bootinfo.h>
37#include <asm/kgdb.h>
38#include <asm/reg.h>
39
40#include "pplus.h"
41
42#undef DUMP_DBATS
43
44TODC_ALLOC();
45
46extern void pplus_setup_hose(void);
47extern void pplus_set_VIA_IDE_native(void);
48
49extern unsigned long loops_per_jiffy;
50unsigned char *Motherboard_map_name;
51
52/* Tables for known hardware */
53
54/* Motorola Mesquite */
55static inline int
56mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
57{
58 static char pci_irq_table[][4] =
59 /*
60 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
61 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
62 * PCI IDSEL/INTPIN->INTLINE
63 * A B C D
64 */
65 {
66 {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
67 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
68 {19, 19, 19, 19}, /* IDSEL 16 - PMC Slot 1 */
69 { 0, 0, 0, 0}, /* IDSEL 17 - unused */
70 { 0, 0, 0, 0}, /* IDSEL 18 - unused */
71 { 0, 0, 0, 0}, /* IDSEL 19 - unused */
72 {24, 25, 26, 27}, /* IDSEL 20 - P2P bridge (to cPCI 1) */
73 { 0, 0, 0, 0}, /* IDSEL 21 - unused */
74 {28, 29, 30, 31} /* IDSEL 22 - P2P bridge (to cPCI 2) */
75 };
76
77 const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
78 return PCI_IRQ_TABLE_LOOKUP;
79}
80
81/* Motorola Sitka */
82static inline int
83sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
84{
85 static char pci_irq_table[][4] =
86 /*
87 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
88 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
89 * PCI IDSEL/INTPIN->INTLINE
90 * A B C D
91 */
92 {
93 {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
94 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
95 {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
96 {28, 25, 26, 27}, /* IDSEL 17 - PMC Slot 2 */
97 { 0, 0, 0, 0}, /* IDSEL 18 - unused */
98 { 0, 0, 0, 0}, /* IDSEL 19 - unused */
99 {20, 0, 0, 0} /* IDSEL 20 - P2P bridge (to cPCI) */
100 };
101
102 const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4;
103 return PCI_IRQ_TABLE_LOOKUP;
104}
105
106/* Motorola MTX */
107static inline int
108MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
109{
110 static char pci_irq_table[][4] =
111 /*
112 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
113 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
114 * PCI IDSEL/INTPIN->INTLINE
115 * A B C D
116 */
117 {
118 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
119 { 0, 0, 0, 0}, /* IDSEL 13 - unused */
120 {18, 0, 0, 0}, /* IDSEL 14 - Enet */
121 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
122 {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
123 {26, 27, 28, 25}, /* IDSEL 17 - PMC Slot 2 */
124 {27, 28, 25, 26} /* IDSEL 18 - PCI Slot 3 */
125 };
126
127 const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4;
128 return PCI_IRQ_TABLE_LOOKUP;
129}
130
131/* Motorola MTX Plus */
132/* Secondary bus interrupt routing is not supported yet */
133static inline int
134MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
135{
136 static char pci_irq_table[][4] =
137 /*
138 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
139 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
140 * PCI IDSEL/INTPIN->INTLINE
141 * A B C D
142 */
143 {
144 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
145 { 0, 0, 0, 0}, /* IDSEL 13 - unused */
146 {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
147 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
148 {25, 26, 27, 28}, /* IDSEL 16 - PCI Slot 1P */
149 {26, 27, 28, 25}, /* IDSEL 17 - PCI Slot 2P */
150 {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
151 {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
152 { 0, 0, 0, 0} /* IDSEL 20 - P2P Bridge */
153 };
154
155 const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
156 return PCI_IRQ_TABLE_LOOKUP;
157}
158
159static inline int
160Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
161{
162 /* 2600
163 * Raven 31
164 * ISA 11
165 * SCSI 12 - IRQ3
166 * Univ 13
167 * eth 14 - IRQ2
168 * VGA 15 - IRQ4
169 * PMC1 16 - IRQ9,10,11,12 = PMC1 A-D
170 * PMC2 17 - IRQ12,9,10,11 = A-D
171 * SCSI2 18 - IRQ11
172 * eth2 19 - IRQ10
173 * PCIX 20 - IRQ9,10,11,12 = PCI A-D
174 */
175
176 /* 2400
177 * Hawk 31
178 * ISA 11
179 * Univ 13
180 * eth 14 - IRQ2
181 * PMC1 16 - IRQ9,10,11,12 = PMC A-D
182 * PMC2 17 - IRQ12,9,10,11 = PMC A-D
183 * PCIX 20 - IRQ9,10,11,12 = PMC A-D
184 */
185
186 /* 2300
187 * Raven 31
188 * ISA 11
189 * Univ 13
190 * eth 14 - IRQ2
191 * PMC1 16 - 9,10,11,12 = A-D
192 * PMC2 17 - 9,10,11,12 = B,C,D,A
193 */
194
195 static char pci_irq_table[][4] =
196 /*
197 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
198 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
199 * PCI IDSEL/INTPIN->INTLINE
200 * A B C D
201 */
202 {
203 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
204 { 0, 0, 0, 0}, /* IDSEL 13 - Universe PCI - VME */
205 {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
206 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
207 {25, 26, 27, 28}, /* IDSEL 16 - PCI/PMC Slot 1P */
208 {28, 25, 26, 27}, /* IDSEL 17 - PCI/PMC Slot 2P */
209 {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
210 {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
211 {25, 26, 27, 28} /* IDSEL 20 - P2P Bridge */
212 };
213
214 const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
215 return PCI_IRQ_TABLE_LOOKUP;
216}
217
218#define MOTOROLA_CPUTYPE_REG 0x800
219#define MOTOROLA_BASETYPE_REG 0x803
220#define MPIC_RAVEN_ID 0x48010000
221#define MPIC_HAWK_ID 0x48030000
222#define MOT_PROC2_BIT 0x800
223
224static u_char pplus_openpic_initsenses[] __initdata = {
225 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
226 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */
227 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */
228 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
229 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */
230 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
231 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
232 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
233 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
234 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
235 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
236 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
237 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
238 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
239 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
240 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),
241};
242
243int mot_entry = -1;
244int prep_keybd_present = 1;
245int mot_multi = 0;
246
247struct brd_info {
248 /* 0x100 mask assumes for Raven and Hawk boards that the level/edge
249 * are set */
250 int cpu_type;
251 /* 0x200 if this board has a Hawk chip. */
252 int base_type;
253 /* or'ed with 0x80 if this board should be checked for multi CPU */
254 int max_cpu;
255 const char *name;
256 int (*map_irq) (struct pci_dev *, unsigned char, unsigned char);
257};
258struct brd_info mot_info[] = {
259 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq},
260 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", mesquite_map_irq},
261 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", sitka_map_irq},
262 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", mesquite_map_irq},
263 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_map_irq},
264 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_map_irq},
265 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_map_irq},
266 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_map_irq},
267 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_map_irq},
268 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_map_irq},
269 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_map_irq},
270 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_map_irq},
271 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_map_irq},
272 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_map_irq},
273 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_map_irq},
274 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_map_irq},
275 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_map_irq},
276 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_map_irq},
277 {0x000, 0x00, 0x00, "", NULL}
278};
279
280void __init pplus_set_board_type(void)
281{
282 unsigned char cpu_type;
283 unsigned char base_mod;
284 int entry;
285 unsigned short devid;
286 unsigned long *ProcInfo = NULL;
287
288 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
289 base_mod = inb(MOTOROLA_BASETYPE_REG);
290 early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
291
292 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
293 /* Check for Hawk chip */
294 if (mot_info[entry].cpu_type & 0x200) {
295 if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
296 continue;
297 } else {
298 /* store the system config register for later use. */
299 ProcInfo =
300 (unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
301
302 /* Check non hawk boards */
303 if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
304 continue;
305
306 if (mot_info[entry].base_type == 0) {
307 mot_entry = entry;
308 break;
309 }
310
311 if (mot_info[entry].base_type != base_mod)
312 continue;
313 }
314
315 if (!(mot_info[entry].max_cpu & 0x80)) {
316 mot_entry = entry;
317 break;
318 }
319
320 /* processor 1 not present and max processor zero indicated */
321 if ((*ProcInfo & MOT_PROC2_BIT)
322 && !(mot_info[entry].max_cpu & 0x7f)) {
323 mot_entry = entry;
324 break;
325 }
326
327 /* processor 1 present and max processor zero indicated */
328 if (!(*ProcInfo & MOT_PROC2_BIT)
329 && (mot_info[entry].max_cpu & 0x7f)) {
330 mot_entry = entry;
331 break;
332 }
333
334 /* Indicate to system if this is a multiprocessor board */
335 if (!(*ProcInfo & MOT_PROC2_BIT))
336 mot_multi = 1;
337 }
338
339 if (mot_entry == -1)
340 /* No particular cpu type found - assume Mesquite (MCP750) */
341 mot_entry = 1;
342
343 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
344 ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
345}
346void __init pplus_pib_init(void)
347{
348 unsigned char reg;
349 unsigned short short_reg;
350
351 struct pci_dev *dev = NULL;
352
353 /*
354 * Perform specific configuration for the Via Tech or
355 * or Winbond PCI-ISA-Bridge part.
356 */
357 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
358 PCI_DEVICE_ID_VIA_82C586_1, dev))) {
359 /*
360 * PPCBUG does not set the enable bits
361 * for the IDE device. Force them on here.
362 */
363 pci_read_config_byte(dev, 0x40, &reg);
364
365 reg |= 0x03; /* IDE: Chip Enable Bits */
366 pci_write_config_byte(dev, 0x40, reg);
367 }
368
369 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
370 PCI_DEVICE_ID_VIA_82C586_2,
371 dev)) && (dev->devfn = 0x5a)) {
372 /* Force correct USB interrupt */
373 dev->irq = 11;
374 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
375 }
376
377 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
378 PCI_DEVICE_ID_WINBOND_83C553, dev))) {
379 /* Clear PCI Interrupt Routing Control Register. */
380 short_reg = 0x0000;
381 pci_write_config_word(dev, 0x44, short_reg);
382 /* Route IDE interrupts to IRQ 14 */
383 reg = 0xEE;
384 pci_write_config_byte(dev, 0x43, reg);
385 }
386
387 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
388 PCI_DEVICE_ID_WINBOND_82C105, dev))) {
389 /*
390 * Disable LEGIRQ mode so PCI INTS are routed
391 * directly to the 8259 and enable both channels
392 */
393 pci_write_config_dword(dev, 0x40, 0x10ff0033);
394
395 /* Force correct IDE interrupt */
396 dev->irq = 14;
397 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
398 }
399 pci_dev_put(dev);
400}
401
402void __init pplus_set_VIA_IDE_legacy(void)
403{
404 unsigned short vend, dev;
405
406 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
407 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
408
409 if ((vend == PCI_VENDOR_ID_VIA) &&
410 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
411 unsigned char temp;
412
413 /* put back original "standard" port base addresses */
414 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
415 PCI_BASE_ADDRESS_0, 0x1f1);
416 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
417 PCI_BASE_ADDRESS_1, 0x3f5);
418 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
419 PCI_BASE_ADDRESS_2, 0x171);
420 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
421 PCI_BASE_ADDRESS_3, 0x375);
422 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
423 PCI_BASE_ADDRESS_4, 0xcc01);
424
425 /* put into legacy mode */
426 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
427 &temp);
428 temp &= ~0x05;
429 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
430 temp);
431 }
432}
433
434void pplus_set_VIA_IDE_native(void)
435{
436 unsigned short vend, dev;
437
438 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
439 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
440
441 if ((vend == PCI_VENDOR_ID_VIA) &&
442 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
443 unsigned char temp;
444
445 /* put into native mode */
446 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
447 &temp);
448 temp |= 0x05;
449 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
450 temp);
451 }
452}
453
454void __init pplus_pcibios_fixup(void)
455{
456
457 unsigned char reg;
458 unsigned short devid;
459 unsigned char base_mod;
460
461 printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
462 Motherboard_map_name);
463
464 /* Setup the Winbond or Via PIB */
465 pplus_pib_init();
466
467 /* Set up floppy in PS/2 mode */
468 outb(0x09, SIO_CONFIG_RA);
469 reg = inb(SIO_CONFIG_RD);
470 reg = (reg & 0x3F) | 0x40;
471 outb(reg, SIO_CONFIG_RD);
472 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
473
474 /* This is a hack. If this is a 2300 or 2400 mot board then there is
475 * no keyboard controller and we have to indicate that.
476 */
477
478 early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
479 base_mod = inb(MOTOROLA_BASETYPE_REG);
480 if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
481 (base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
482 prep_keybd_present = 0;
483}
484
485void __init pplus_find_bridges(void)
486{
487 struct pci_controller *hose;
488
489 hose = pcibios_alloc_controller();
490 if (!hose)
491 return;
492
493 hose->first_busno = 0;
494 hose->last_busno = 0xff;
495
496 hose->pci_mem_offset = PREP_ISA_MEM_BASE;
497 hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
498
499 pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START,
500 PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge");
501 pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START,
502 PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM,
503 "PCI host bridge");
504
505 hose->io_space.start = PPLUS_PCI_IO_START;
506 hose->io_space.end = PPLUS_PCI_IO_END;
507 hose->mem_space.start = PPLUS_PCI_MEM_START;
508 hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
509
510 if (hawk_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
511 PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
512 PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
513 PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
514 != 0) {
515 printk(KERN_CRIT "Could not initialize host bridge\n");
516
517 }
518
519 pplus_set_VIA_IDE_legacy();
520
521 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
522
523 ppc_md.pcibios_fixup = pplus_pcibios_fixup;
524 ppc_md.pci_swizzle = common_swizzle;
525}
526
527static int pplus_show_cpuinfo(struct seq_file *m)
528{
529 seq_printf(m, "vendor\t\t: Motorola MCG\n");
530 seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
531
532 return 0;
533}
534
535static void __init pplus_setup_arch(void)
536{
537 struct pci_controller *hose;
538
539 if (ppc_md.progress)
540 ppc_md.progress("pplus_setup_arch: enter", 0);
541
542 /* init to some ~sane value until calibrate_delay() runs */
543 loops_per_jiffy = 50000000;
544
545 if (ppc_md.progress)
546 ppc_md.progress("pplus_setup_arch: find_bridges", 0);
547
548 /* Setup PCI host bridge */
549 pplus_find_bridges();
550
551 hose = pci_bus_to_hose(0);
552 isa_io_base = (ulong) hose->io_base_virt;
553
554 if (ppc_md.progress)
555 ppc_md.progress("pplus_setup_arch: set_board_type", 0);
556
557 pplus_set_board_type();
558
559 /* Enable L2. Assume we don't need to flush -- Cort */
560 *(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3;
561
562#ifdef CONFIG_BLK_DEV_INITRD
563 if (initrd_start)
564 ROOT_DEV = Root_RAM0;
565 else
566#endif
567#ifdef CONFIG_ROOT_NFS
568 ROOT_DEV = Root_NFS;
569#else
570 ROOT_DEV = Root_SDA2;
571#endif
572
573 printk(KERN_INFO "Motorola PowerPlus Platform\n");
574 printk(KERN_INFO
575 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
576
577#ifdef CONFIG_VGA_CONSOLE
578 /* remap the VGA memory */
579 vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE,
580 0x08000000);
581 conswitchp = &vga_con;
582#endif
583#ifdef CONFIG_PPCBUG_NVRAM
584 /* Read in NVRAM data */
585 init_prep_nvram();
586
587 /* if no bootargs, look in NVRAM */
588 if (cmd_line[0] == '\0') {
589 char *bootargs;
590 bootargs = prep_nvram_get_var("bootargs");
591 if (bootargs != NULL) {
592 strcpy(cmd_line, bootargs);
593 /* again.. */
594 strcpy(boot_command_line, cmd_line);
595 }
596 }
597#endif
598 if (ppc_md.progress)
599 ppc_md.progress("pplus_setup_arch: exit", 0);
600}
601
602static void pplus_restart(char *cmd)
603{
604 unsigned long i = 10000;
605
606 local_irq_disable();
607
608 /* set VIA IDE controller into native mode */
609 pplus_set_VIA_IDE_native();
610
611 /* set exception prefix high - to the prom */
612 _nmask_and_or_msr(0, MSR_IP);
613
614 /* make sure bit 0 (reset) is a 0 */
615 outb(inb(0x92) & ~1L, 0x92);
616 /* signal a reset to system control port A - soft reset */
617 outb(inb(0x92) | 1, 0x92);
618
619 while (i != 0)
620 i++;
621 panic("restart failed\n");
622}
623
624static void pplus_halt(void)
625{
626 /* set exception prefix high - to the prom */
627 _nmask_and_or_msr(MSR_EE, MSR_IP);
628
629 /* make sure bit 0 (reset) is a 0 */
630 outb(inb(0x92) & ~1L, 0x92);
631 /* signal a reset to system control port A - soft reset */
632 outb(inb(0x92) | 1, 0x92);
633
634 while (1) ;
635 /*
636 * Not reached
637 */
638}
639
640static void pplus_power_off(void)
641{
642 pplus_halt();
643}
644
645static void __init pplus_init_IRQ(void)
646{
647 int i;
648
649 if (ppc_md.progress)
650 ppc_md.progress("init_irq: enter", 0);
651
652 OpenPIC_InitSenses = pplus_openpic_initsenses;
653 OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
654
655 if (OpenPIC_Addr != NULL) {
656
657 openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
658 openpic_init(NUM_8259_INTERRUPTS);
659 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
660 i8259_irq);
661 ppc_md.get_irq = openpic_get_irq;
662 }
663
664 i8259_init(0, 0);
665
666 if (ppc_md.progress)
667 ppc_md.progress("init_irq: exit", 0);
668}
669
670#ifdef CONFIG_SMP
671/* PowerPlus (MTX) support */
672static int __init smp_pplus_probe(void)
673{
674 extern int mot_multi;
675
676 if (mot_multi) {
677 openpic_request_IPIs();
678 smp_hw_index[1] = 1;
679 return 2;
680 }
681
682 return 1;
683}
684
685static void __init smp_pplus_kick_cpu(int nr)
686{
687 *(unsigned long *)KERNELBASE = nr;
688 asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
689 printk(KERN_INFO "CPU1 reset, waiting\n");
690}
691
692static void __init smp_pplus_setup_cpu(int cpu_nr)
693{
694 if (OpenPIC_Addr)
695 do_openpic_setup_cpu();
696}
697
698static struct smp_ops_t pplus_smp_ops = {
699 smp_openpic_message_pass,
700 smp_pplus_probe,
701 smp_pplus_kick_cpu,
702 smp_pplus_setup_cpu,
703 .give_timebase = smp_generic_give_timebase,
704 .take_timebase = smp_generic_take_timebase,
705};
706#endif /* CONFIG_SMP */
707
708#ifdef DUMP_DBATS
709static void print_dbat(int idx, u32 bat)
710{
711
712 char str[64];
713
714 sprintf(str, "DBAT%c%c = 0x%08x\n",
715 (char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat);
716 ppc_md.progress(str, 0);
717}
718
719#define DUMP_DBAT(x) \
720 do { \
721 u32 __temp = mfspr(x);\
722 print_dbat(x, __temp); \
723 } while (0)
724
725static void dump_dbats(void)
726{
727 if (ppc_md.progress) {
728 DUMP_DBAT(DBAT0U);
729 DUMP_DBAT(DBAT0L);
730 DUMP_DBAT(DBAT1U);
731 DUMP_DBAT(DBAT1L);
732 DUMP_DBAT(DBAT2U);
733 DUMP_DBAT(DBAT2L);
734 DUMP_DBAT(DBAT3U);
735 DUMP_DBAT(DBAT3L);
736 }
737}
738#endif
739
740static unsigned long __init pplus_find_end_of_memory(void)
741{
742 unsigned long total;
743
744 if (ppc_md.progress)
745 ppc_md.progress("pplus_find_end_of_memory", 0);
746
747#ifdef DUMP_DBATS
748 dump_dbats();
749#endif
750
751 total = hawk_get_mem_size(PPLUS_HAWK_SMC_BASE);
752 return (total);
753}
754
755static void __init pplus_map_io(void)
756{
757 io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
758 _PAGE_IO);
759 io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
760}
761
762static void __init pplus_init2(void)
763{
764#ifdef CONFIG_NVRAM
765 request_region(PREP_NVRAM_AS0, 0x8, "nvram");
766#endif
767 request_region(0x20, 0x20, "pic1");
768 request_region(0xa0, 0x20, "pic2");
769 request_region(0x00, 0x20, "dma1");
770 request_region(0x40, 0x20, "timer");
771 request_region(0x80, 0x10, "dma page reg");
772 request_region(0xc0, 0x20, "dma2");
773}
774
775/*
776 * Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
777 * to 0xf0000000 to access Falcon/Raven or Hawk registers
778 */
779static __inline__ void pplus_set_bat(void)
780{
781 /* wait for all outstanding memory accesses to complete */
782 mb();
783
784 /* setup DBATs */
785 mtspr(SPRN_DBAT2U, 0x80001ffe);
786 mtspr(SPRN_DBAT2L, 0x8000002a);
787 mtspr(SPRN_DBAT3U, 0xf0001ffe);
788 mtspr(SPRN_DBAT3L, 0xf000002a);
789
790 /* wait for updates */
791 mb();
792}
793
794void __init
795platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
796 unsigned long r6, unsigned long r7)
797{
798 parse_bootinfo(find_bootinfo());
799
800 /* Map in board regs, etc. */
801 pplus_set_bat();
802
803 isa_io_base = PREP_ISA_IO_BASE;
804 isa_mem_base = PREP_ISA_MEM_BASE;
805 pci_dram_offset = PREP_PCI_DRAM_OFFSET;
806 ISA_DMA_THRESHOLD = 0x00ffffff;
807 DMA_MODE_READ = 0x44;
808 DMA_MODE_WRITE = 0x48;
809 ppc_do_canonicalize_irqs = 1;
810
811 ppc_md.setup_arch = pplus_setup_arch;
812 ppc_md.show_cpuinfo = pplus_show_cpuinfo;
813 ppc_md.init_IRQ = pplus_init_IRQ;
814 /* this gets changed later on if we have an OpenPIC -- Cort */
815 ppc_md.get_irq = i8259_irq;
816 ppc_md.init = pplus_init2;
817
818 ppc_md.restart = pplus_restart;
819 ppc_md.power_off = pplus_power_off;
820 ppc_md.halt = pplus_halt;
821
822 TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
823 PREP_NVRAM_DATA, 8);
824
825 ppc_md.time_init = todc_time_init;
826 ppc_md.set_rtc_time = todc_set_rtc_time;
827 ppc_md.get_rtc_time = todc_get_rtc_time;
828 ppc_md.calibrate_decr = todc_calibrate_decr;
829 ppc_md.nvram_read_val = todc_m48txx_read_val;
830 ppc_md.nvram_write_val = todc_m48txx_write_val;
831
832 ppc_md.find_end_of_memory = pplus_find_end_of_memory;
833 ppc_md.setup_io_mappings = pplus_map_io;
834
835#ifdef CONFIG_SERIAL_TEXT_DEBUG
836 ppc_md.progress = gen550_progress;
837#endif /* CONFIG_SERIAL_TEXT_DEBUG */
838#ifdef CONFIG_KGDB
839 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
840#endif
841#ifdef CONFIG_SMP
842 smp_ops = &pplus_smp_ops;
843#endif /* CONFIG_SMP */
844}
diff --git a/arch/ppc/platforms/pplus.h b/arch/ppc/platforms/pplus.h
deleted file mode 100644
index a4bbaa8d858f..000000000000
--- a/arch/ppc/platforms/pplus.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
3 *
4 * Author: Mark A. Greerinclude/asm-ppc/hawk.h
5 * mgreer@mvista.com
6 *
7 * Modified by Randy Vinson (rvinson@mvista.com)
8 *
9 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifndef __PPC_PPLUS_H
16#define __PPC_PPLUS_H
17
18#include <asm/io.h>
19
20/*
21 * Due to limitations imposed by legacy hardware (primarily IDE controllers),
22 * the PPLUS boards operate using a PReP address map.
23 *
24 * From Processor (physical) -> PCI:
25 * PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
26 * PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
27 * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
28 *
29 * From PCI -> Processor (physical):
30 * System Memory: 0x80000000 -> 0x00000000
31 */
32
33#define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE
34#define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE
35
36/* PCI Memory space mapping info */
37#define PPLUS_PCI_MEM_SIZE 0x30000000U
38#define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE
39#define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \
40 PPLUS_PCI_MEM_SIZE - 1)
41#define PPLUS_PCI_MEM_START 0x00000000U
42#define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \
43 PPLUS_PCI_MEM_SIZE - 1)
44
45/* PCI I/O space mapping info */
46#define PPLUS_PCI_IO_SIZE 0x10000000U
47#define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE
48#define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \
49 PPLUS_PCI_IO_SIZE - 1)
50#define PPLUS_PCI_IO_START 0x00000000U
51#define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \
52 PPLUS_PCI_IO_SIZE - 1)
53/* System memory mapping info */
54#define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
55#define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
56
57/* Define base addresses for important sets of registers */
58#define PPLUS_HAWK_SMC_BASE 0xfef80000U
59#define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U
60#define PPLUS_SYS_CONFIG_REG 0xfef80400U
61#define PPLUS_L2_CONTROL_REG 0x8000081cU
62
63#define PPLUS_VGA_MEM_BASE 0xf0000000U
64
65#endif /* __PPC_PPLUS_H */
diff --git a/arch/ppc/platforms/prep_pci.c b/arch/ppc/platforms/prep_pci.c
deleted file mode 100644
index 8ed433e2a5c7..000000000000
--- a/arch/ppc/platforms/prep_pci.c
+++ /dev/null
@@ -1,1339 +0,0 @@
1/*
2 * PReP pci functions.
3 * Originally by Gary Thomas
4 * rewritten and updated by Cort Dougan (cort@cs.nmt.edu)
5 *
6 * The motherboard routes/maps will disappear shortly. -- Cort
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14#include <asm/sections.h>
15#include <asm/byteorder.h>
16#include <asm/io.h>
17#include <asm/ptrace.h>
18#include <asm/prom.h>
19#include <asm/pci-bridge.h>
20#include <asm/residual.h>
21#include <asm/irq.h>
22#include <asm/machdep.h>
23#include <asm/open_pic.h>
24
25extern void (*setup_ibm_pci)(char *irq_lo, char *irq_hi);
26
27/* Which PCI interrupt line does a given device [slot] use? */
28/* Note: This really should be two dimensional based in slot/pin used */
29static unsigned char *Motherboard_map;
30unsigned char *Motherboard_map_name;
31
32/* How is the 82378 PIRQ mapping setup? */
33static unsigned char *Motherboard_routes;
34
35static void (*Motherboard_non0)(struct pci_dev *);
36
37static void Powerplus_Map_Non0(struct pci_dev *);
38
39/* Used for Motorola to store system config register */
40static unsigned long *ProcInfo;
41
42/* Tables for known hardware */
43
44/* Motorola PowerStackII - Utah */
45static char Utah_pci_IRQ_map[23] =
46{
47 0, /* Slot 0 - unused */
48 0, /* Slot 1 - unused */
49 5, /* Slot 2 - SCSI - NCR825A */
50 0, /* Slot 3 - unused */
51 3, /* Slot 4 - Ethernet - DEC2114x */
52 0, /* Slot 5 - unused */
53 2, /* Slot 6 - PCI Card slot #1 */
54 3, /* Slot 7 - PCI Card slot #2 */
55 5, /* Slot 8 - PCI Card slot #3 */
56 5, /* Slot 9 - PCI Bridge */
57 /* added here in case we ever support PCI bridges */
58 /* Secondary PCI bus cards are at slot-9,6 & slot-9,7 */
59 0, /* Slot 10 - unused */
60 0, /* Slot 11 - unused */
61 5, /* Slot 12 - SCSI - NCR825A */
62 0, /* Slot 13 - unused */
63 3, /* Slot 14 - enet */
64 0, /* Slot 15 - unused */
65 2, /* Slot 16 - unused */
66 3, /* Slot 17 - unused */
67 5, /* Slot 18 - unused */
68 0, /* Slot 19 - unused */
69 0, /* Slot 20 - unused */
70 0, /* Slot 21 - unused */
71 0, /* Slot 22 - unused */
72};
73
74static char Utah_pci_IRQ_routes[] =
75{
76 0, /* Line 0 - Unused */
77 9, /* Line 1 */
78 10, /* Line 2 */
79 11, /* Line 3 */
80 14, /* Line 4 */
81 15, /* Line 5 */
82};
83
84/* Motorola PowerStackII - Omaha */
85/* no integrated SCSI or ethernet */
86static char Omaha_pci_IRQ_map[23] =
87{
88 0, /* Slot 0 - unused */
89 0, /* Slot 1 - unused */
90 3, /* Slot 2 - Winbond EIDE */
91 0, /* Slot 3 - unused */
92 0, /* Slot 4 - unused */
93 0, /* Slot 5 - unused */
94 1, /* Slot 6 - PCI slot 1 */
95 2, /* Slot 7 - PCI slot 2 */
96 3, /* Slot 8 - PCI slot 3 */
97 4, /* Slot 9 - PCI slot 4 */ /* needs indirect access */
98 0, /* Slot 10 - unused */
99 0, /* Slot 11 - unused */
100 0, /* Slot 12 - unused */
101 0, /* Slot 13 - unused */
102 0, /* Slot 14 - unused */
103 0, /* Slot 15 - unused */
104 1, /* Slot 16 - PCI slot 1 */
105 2, /* Slot 17 - PCI slot 2 */
106 3, /* Slot 18 - PCI slot 3 */
107 4, /* Slot 19 - PCI slot 4 */ /* needs indirect access */
108 0,
109 0,
110 0,
111};
112
113static char Omaha_pci_IRQ_routes[] =
114{
115 0, /* Line 0 - Unused */
116 9, /* Line 1 */
117 11, /* Line 2 */
118 14, /* Line 3 */
119 15 /* Line 4 */
120};
121
122/* Motorola PowerStack */
123static char Blackhawk_pci_IRQ_map[19] =
124{
125 0, /* Slot 0 - unused */
126 0, /* Slot 1 - unused */
127 0, /* Slot 2 - unused */
128 0, /* Slot 3 - unused */
129 0, /* Slot 4 - unused */
130 0, /* Slot 5 - unused */
131 0, /* Slot 6 - unused */
132 0, /* Slot 7 - unused */
133 0, /* Slot 8 - unused */
134 0, /* Slot 9 - unused */
135 0, /* Slot 10 - unused */
136 0, /* Slot 11 - unused */
137 3, /* Slot 12 - SCSI */
138 0, /* Slot 13 - unused */
139 1, /* Slot 14 - Ethernet */
140 0, /* Slot 15 - unused */
141 1, /* Slot P7 */
142 2, /* Slot P6 */
143 3, /* Slot P5 */
144};
145
146static char Blackhawk_pci_IRQ_routes[] =
147{
148 0, /* Line 0 - Unused */
149 9, /* Line 1 */
150 11, /* Line 2 */
151 15, /* Line 3 */
152 15 /* Line 4 */
153};
154
155/* Motorola Mesquite */
156static char Mesquite_pci_IRQ_map[23] =
157{
158 0, /* Slot 0 - unused */
159 0, /* Slot 1 - unused */
160 0, /* Slot 2 - unused */
161 0, /* Slot 3 - unused */
162 0, /* Slot 4 - unused */
163 0, /* Slot 5 - unused */
164 0, /* Slot 6 - unused */
165 0, /* Slot 7 - unused */
166 0, /* Slot 8 - unused */
167 0, /* Slot 9 - unused */
168 0, /* Slot 10 - unused */
169 0, /* Slot 11 - unused */
170 0, /* Slot 12 - unused */
171 0, /* Slot 13 - unused */
172 2, /* Slot 14 - Ethernet */
173 0, /* Slot 15 - unused */
174 3, /* Slot 16 - PMC */
175 0, /* Slot 17 - unused */
176 0, /* Slot 18 - unused */
177 0, /* Slot 19 - unused */
178 0, /* Slot 20 - unused */
179 0, /* Slot 21 - unused */
180 0, /* Slot 22 - unused */
181};
182
183/* Motorola Sitka */
184static char Sitka_pci_IRQ_map[21] =
185{
186 0, /* Slot 0 - unused */
187 0, /* Slot 1 - unused */
188 0, /* Slot 2 - unused */
189 0, /* Slot 3 - unused */
190 0, /* Slot 4 - unused */
191 0, /* Slot 5 - unused */
192 0, /* Slot 6 - unused */
193 0, /* Slot 7 - unused */
194 0, /* Slot 8 - unused */
195 0, /* Slot 9 - unused */
196 0, /* Slot 10 - unused */
197 0, /* Slot 11 - unused */
198 0, /* Slot 12 - unused */
199 0, /* Slot 13 - unused */
200 2, /* Slot 14 - Ethernet */
201 0, /* Slot 15 - unused */
202 9, /* Slot 16 - PMC 1 */
203 12, /* Slot 17 - PMC 2 */
204 0, /* Slot 18 - unused */
205 0, /* Slot 19 - unused */
206 4, /* Slot 20 - NT P2P bridge */
207};
208
209/* Motorola MTX */
210static char MTX_pci_IRQ_map[23] =
211{
212 0, /* Slot 0 - unused */
213 0, /* Slot 1 - unused */
214 0, /* Slot 2 - unused */
215 0, /* Slot 3 - unused */
216 0, /* Slot 4 - unused */
217 0, /* Slot 5 - unused */
218 0, /* Slot 6 - unused */
219 0, /* Slot 7 - unused */
220 0, /* Slot 8 - unused */
221 0, /* Slot 9 - unused */
222 0, /* Slot 10 - unused */
223 0, /* Slot 11 - unused */
224 3, /* Slot 12 - SCSI */
225 0, /* Slot 13 - unused */
226 2, /* Slot 14 - Ethernet */
227 0, /* Slot 15 - unused */
228 9, /* Slot 16 - PCI/PMC slot 1 */
229 10, /* Slot 17 - PCI/PMC slot 2 */
230 11, /* Slot 18 - PCI slot 3 */
231 0, /* Slot 19 - unused */
232 0, /* Slot 20 - unused */
233 0, /* Slot 21 - unused */
234 0, /* Slot 22 - unused */
235};
236
237/* Motorola MTX Plus */
238/* Secondary bus interrupt routing is not supported yet */
239static char MTXplus_pci_IRQ_map[23] =
240{
241 0, /* Slot 0 - unused */
242 0, /* Slot 1 - unused */
243 0, /* Slot 2 - unused */
244 0, /* Slot 3 - unused */
245 0, /* Slot 4 - unused */
246 0, /* Slot 5 - unused */
247 0, /* Slot 6 - unused */
248 0, /* Slot 7 - unused */
249 0, /* Slot 8 - unused */
250 0, /* Slot 9 - unused */
251 0, /* Slot 10 - unused */
252 0, /* Slot 11 - unused */
253 3, /* Slot 12 - SCSI */
254 0, /* Slot 13 - unused */
255 2, /* Slot 14 - Ethernet 1 */
256 0, /* Slot 15 - unused */
257 9, /* Slot 16 - PCI slot 1P */
258 10, /* Slot 17 - PCI slot 2P */
259 11, /* Slot 18 - PCI slot 3P */
260 10, /* Slot 19 - Ethernet 2 */
261 0, /* Slot 20 - P2P Bridge */
262 0, /* Slot 21 - unused */
263 0, /* Slot 22 - unused */
264};
265
266static char Raven_pci_IRQ_routes[] =
267{
268 0, /* This is a dummy structure */
269};
270
271/* Motorola MVME16xx */
272static char Genesis_pci_IRQ_map[16] =
273{
274 0, /* Slot 0 - unused */
275 0, /* Slot 1 - unused */
276 0, /* Slot 2 - unused */
277 0, /* Slot 3 - unused */
278 0, /* Slot 4 - unused */
279 0, /* Slot 5 - unused */
280 0, /* Slot 6 - unused */
281 0, /* Slot 7 - unused */
282 0, /* Slot 8 - unused */
283 0, /* Slot 9 - unused */
284 0, /* Slot 10 - unused */
285 0, /* Slot 11 - unused */
286 3, /* Slot 12 - SCSI */
287 0, /* Slot 13 - unused */
288 1, /* Slot 14 - Ethernet */
289 0, /* Slot 15 - unused */
290};
291
292static char Genesis_pci_IRQ_routes[] =
293{
294 0, /* Line 0 - Unused */
295 10, /* Line 1 */
296 11, /* Line 2 */
297 14, /* Line 3 */
298 15 /* Line 4 */
299};
300
301static char Genesis2_pci_IRQ_map[23] =
302{
303 0, /* Slot 0 - unused */
304 0, /* Slot 1 - unused */
305 0, /* Slot 2 - unused */
306 0, /* Slot 3 - unused */
307 0, /* Slot 4 - unused */
308 0, /* Slot 5 - unused */
309 0, /* Slot 6 - unused */
310 0, /* Slot 7 - unused */
311 0, /* Slot 8 - unused */
312 0, /* Slot 9 - unused */
313 0, /* Slot 10 - unused */
314 0, /* Slot 11 - IDE */
315 3, /* Slot 12 - SCSI */
316 5, /* Slot 13 - Universe PCI - VME Bridge */
317 2, /* Slot 14 - Ethernet */
318 0, /* Slot 15 - unused */
319 9, /* Slot 16 - PMC 1 */
320 12, /* Slot 17 - pci */
321 11, /* Slot 18 - pci */
322 10, /* Slot 19 - pci */
323 0, /* Slot 20 - pci */
324 0, /* Slot 21 - unused */
325 0, /* Slot 22 - unused */
326};
327
328/* Motorola Series-E */
329static char Comet_pci_IRQ_map[23] =
330{
331 0, /* Slot 0 - unused */
332 0, /* Slot 1 - unused */
333 0, /* Slot 2 - unused */
334 0, /* Slot 3 - unused */
335 0, /* Slot 4 - unused */
336 0, /* Slot 5 - unused */
337 0, /* Slot 6 - unused */
338 0, /* Slot 7 - unused */
339 0, /* Slot 8 - unused */
340 0, /* Slot 9 - unused */
341 0, /* Slot 10 - unused */
342 0, /* Slot 11 - unused */
343 3, /* Slot 12 - SCSI */
344 0, /* Slot 13 - unused */
345 1, /* Slot 14 - Ethernet */
346 0, /* Slot 15 - unused */
347 1, /* Slot 16 - PCI slot 1 */
348 2, /* Slot 17 - PCI slot 2 */
349 3, /* Slot 18 - PCI slot 3 */
350 4, /* Slot 19 - PCI bridge */
351 0,
352 0,
353 0,
354};
355
356static char Comet_pci_IRQ_routes[] =
357{
358 0, /* Line 0 - Unused */
359 10, /* Line 1 */
360 11, /* Line 2 */
361 14, /* Line 3 */
362 15 /* Line 4 */
363};
364
365/* Motorola Series-EX */
366static char Comet2_pci_IRQ_map[23] =
367{
368 0, /* Slot 0 - unused */
369 0, /* Slot 1 - unused */
370 3, /* Slot 2 - SCSI - NCR825A */
371 0, /* Slot 3 - unused */
372 1, /* Slot 4 - Ethernet - DEC2104X */
373 0, /* Slot 5 - unused */
374 1, /* Slot 6 - PCI slot 1 */
375 2, /* Slot 7 - PCI slot 2 */
376 3, /* Slot 8 - PCI slot 3 */
377 4, /* Slot 9 - PCI bridge */
378 0, /* Slot 10 - unused */
379 0, /* Slot 11 - unused */
380 3, /* Slot 12 - SCSI - NCR825A */
381 0, /* Slot 13 - unused */
382 1, /* Slot 14 - Ethernet - DEC2104X */
383 0, /* Slot 15 - unused */
384 1, /* Slot 16 - PCI slot 1 */
385 2, /* Slot 17 - PCI slot 2 */
386 3, /* Slot 18 - PCI slot 3 */
387 4, /* Slot 19 - PCI bridge */
388 0,
389 0,
390 0,
391};
392
393static char Comet2_pci_IRQ_routes[] =
394{
395 0, /* Line 0 - Unused */
396 10, /* Line 1 */
397 11, /* Line 2 */
398 14, /* Line 3 */
399 15, /* Line 4 */
400};
401
402/*
403 * ibm 830 (and 850?).
404 * This is actually based on the Carolina motherboard
405 * -- Cort
406 */
407static char ibm8xx_pci_IRQ_map[23] = {
408 0, /* Slot 0 - unused */
409 0, /* Slot 1 - unused */
410 0, /* Slot 2 - unused */
411 0, /* Slot 3 - unused */
412 0, /* Slot 4 - unused */
413 0, /* Slot 5 - unused */
414 0, /* Slot 6 - unused */
415 0, /* Slot 7 - unused */
416 0, /* Slot 8 - unused */
417 0, /* Slot 9 - unused */
418 0, /* Slot 10 - unused */
419 0, /* Slot 11 - FireCoral */
420 4, /* Slot 12 - Ethernet PCIINTD# */
421 2, /* Slot 13 - PCI Slot #2 */
422 2, /* Slot 14 - S3 Video PCIINTD# */
423 0, /* Slot 15 - onboard SCSI (INDI) [1] */
424 3, /* Slot 16 - NCR58C810 RS6000 Only PCIINTC# */
425 0, /* Slot 17 - unused */
426 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
427 0, /* Slot 19 - unused */
428 0, /* Slot 20 - unused */
429 0, /* Slot 21 - unused */
430 2, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
431};
432
433static char ibm8xx_pci_IRQ_routes[] = {
434 0, /* Line 0 - unused */
435 15, /* Line 1 */
436 15, /* Line 2 */
437 15, /* Line 3 */
438 15, /* Line 4 */
439};
440
441/*
442 * a 6015 ibm board
443 * -- Cort
444 */
445static char ibm6015_pci_IRQ_map[23] = {
446 0, /* Slot 0 - unused */
447 0, /* Slot 1 - unused */
448 0, /* Slot 2 - unused */
449 0, /* Slot 3 - unused */
450 0, /* Slot 4 - unused */
451 0, /* Slot 5 - unused */
452 0, /* Slot 6 - unused */
453 0, /* Slot 7 - unused */
454 0, /* Slot 8 - unused */
455 0, /* Slot 9 - unused */
456 0, /* Slot 10 - unused */
457 0, /* Slot 11 - */
458 1, /* Slot 12 - SCSI */
459 2, /* Slot 13 - */
460 2, /* Slot 14 - */
461 1, /* Slot 15 - */
462 1, /* Slot 16 - */
463 0, /* Slot 17 - */
464 2, /* Slot 18 - */
465 0, /* Slot 19 - */
466 0, /* Slot 20 - */
467 0, /* Slot 21 - */
468 2, /* Slot 22 - */
469};
470
471static char ibm6015_pci_IRQ_routes[] = {
472 0, /* Line 0 - unused */
473 13, /* Line 1 */
474 15, /* Line 2 */
475 15, /* Line 3 */
476 15, /* Line 4 */
477};
478
479
480/* IBM Nobis and Thinkpad 850 */
481static char Nobis_pci_IRQ_map[23] ={
482 0, /* Slot 0 - unused */
483 0, /* Slot 1 - unused */
484 0, /* Slot 2 - unused */
485 0, /* Slot 3 - unused */
486 0, /* Slot 4 - unused */
487 0, /* Slot 5 - unused */
488 0, /* Slot 6 - unused */
489 0, /* Slot 7 - unused */
490 0, /* Slot 8 - unused */
491 0, /* Slot 9 - unused */
492 0, /* Slot 10 - unused */
493 0, /* Slot 11 - unused */
494 3, /* Slot 12 - SCSI */
495 0, /* Slot 13 - unused */
496 0, /* Slot 14 - unused */
497 0, /* Slot 15 - unused */
498};
499
500static char Nobis_pci_IRQ_routes[] = {
501 0, /* Line 0 - Unused */
502 13, /* Line 1 */
503 13, /* Line 2 */
504 13, /* Line 3 */
505 13 /* Line 4 */
506};
507
508/*
509 * IBM RS/6000 43p/140 -- paulus
510 * XXX we should get all this from the residual data
511 */
512static char ibm43p_pci_IRQ_map[23] = {
513 0, /* Slot 0 - unused */
514 0, /* Slot 1 - unused */
515 0, /* Slot 2 - unused */
516 0, /* Slot 3 - unused */
517 0, /* Slot 4 - unused */
518 0, /* Slot 5 - unused */
519 0, /* Slot 6 - unused */
520 0, /* Slot 7 - unused */
521 0, /* Slot 8 - unused */
522 0, /* Slot 9 - unused */
523 0, /* Slot 10 - unused */
524 0, /* Slot 11 - FireCoral ISA bridge */
525 6, /* Slot 12 - Ethernet */
526 0, /* Slot 13 - openpic */
527 0, /* Slot 14 - unused */
528 0, /* Slot 15 - unused */
529 7, /* Slot 16 - NCR58C825a onboard scsi */
530 0, /* Slot 17 - unused */
531 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
532 0, /* Slot 19 - unused */
533 0, /* Slot 20 - unused */
534 0, /* Slot 21 - unused */
535 1, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
536};
537
538static char ibm43p_pci_IRQ_routes[] = {
539 0, /* Line 0 - unused */
540 15, /* Line 1 */
541 15, /* Line 2 */
542 15, /* Line 3 */
543 15, /* Line 4 */
544};
545
546/* Motorola PowerPlus architecture PCI IRQ tables */
547/* Interrupt line values for INTA-D on primary/secondary MPIC inputs */
548
549struct powerplus_irq_list
550{
551 unsigned char primary[4]; /* INT A-D */
552 unsigned char secondary[4]; /* INT A-D */
553};
554
555/*
556 * For standard PowerPlus boards, bus 0 PCI INTs A-D are routed to
557 * OpenPIC inputs 9-12. PCI INTs A-D from the on board P2P bridge
558 * are routed to OpenPIC inputs 5-8. These values are offset by
559 * 16 in the table to reflect the Linux kernel interrupt value.
560 */
561struct powerplus_irq_list Powerplus_pci_IRQ_list =
562{
563 {25, 26, 27, 28},
564 {21, 22, 23, 24}
565};
566
567/*
568 * For the MCP750 (system slot board), cPCI INTs A-D are routed to
569 * OpenPIC inputs 8-11 and the PMC INTs A-D are routed to OpenPIC
570 * input 3. On a hot swap MCP750, the companion card PCI INTs A-D
571 * are routed to OpenPIC inputs 12-15. These values are offset by
572 * 16 in the table to reflect the Linux kernel interrupt value.
573 */
574struct powerplus_irq_list Mesquite_pci_IRQ_list =
575{
576 {24, 25, 26, 27},
577 {28, 29, 30, 31}
578};
579
580/*
581 * This table represents the standard PCI swizzle defined in the
582 * PCI bus specification.
583 */
584static unsigned char prep_pci_intpins[4][4] =
585{
586 { 1, 2, 3, 4}, /* Buses 0, 4, 8, ... */
587 { 2, 3, 4, 1}, /* Buses 1, 5, 9, ... */
588 { 3, 4, 1, 2}, /* Buses 2, 6, 10 ... */
589 { 4, 1, 2, 3}, /* Buses 3, 7, 11 ... */
590};
591
592/* We have to turn on LEVEL mode for changed IRQs */
593/* All PCI IRQs need to be level mode, so this should be something
594 * other than hard-coded as well... IRQs are individually mappable
595 * to either edge or level.
596 */
597
598/*
599 * 8259 edge/level control definitions
600 */
601#define ISA8259_M_ELCR 0x4d0
602#define ISA8259_S_ELCR 0x4d1
603
604#define ELCRS_INT15_LVL 0x80
605#define ELCRS_INT14_LVL 0x40
606#define ELCRS_INT12_LVL 0x10
607#define ELCRS_INT11_LVL 0x08
608#define ELCRS_INT10_LVL 0x04
609#define ELCRS_INT9_LVL 0x02
610#define ELCRS_INT8_LVL 0x01
611#define ELCRM_INT7_LVL 0x80
612#define ELCRM_INT5_LVL 0x20
613
614#if 0
615/*
616 * PCI config space access.
617 */
618#define CFGADDR(dev) ((1<<(dev>>3)) | ((dev&7)<<8))
619#define DEVNO(dev) (dev>>3)
620
621#define MIN_DEVNR 11
622#define MAX_DEVNR 22
623
624static int
625prep_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
626 int len, u32 *val)
627{
628 struct pci_controller *hose = bus->sysdata;
629 volatile void __iomem *cfg_data;
630
631 if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR
632 || DEVNO(devfn) > MAX_DEVNR)
633 return PCIBIOS_DEVICE_NOT_FOUND;
634
635 /*
636 * Note: the caller has already checked that offset is
637 * suitably aligned and that len is 1, 2 or 4.
638 */
639 cfg_data = hose->cfg_data + CFGADDR(devfn) + offset;
640 switch (len) {
641 case 1:
642 *val = in_8(cfg_data);
643 break;
644 case 2:
645 *val = in_le16(cfg_data);
646 break;
647 default:
648 *val = in_le32(cfg_data);
649 break;
650 }
651 return PCIBIOS_SUCCESSFUL;
652}
653
654static int
655prep_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
656 int len, u32 val)
657{
658 struct pci_controller *hose = bus->sysdata;
659 volatile void __iomem *cfg_data;
660
661 if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR
662 || DEVNO(devfn) > MAX_DEVNR)
663 return PCIBIOS_DEVICE_NOT_FOUND;
664
665 /*
666 * Note: the caller has already checked that offset is
667 * suitably aligned and that len is 1, 2 or 4.
668 */
669 cfg_data = hose->cfg_data + CFGADDR(devfn) + offset;
670 switch (len) {
671 case 1:
672 out_8(cfg_data, val);
673 break;
674 case 2:
675 out_le16(cfg_data, val);
676 break;
677 default:
678 out_le32(cfg_data, val);
679 break;
680 }
681 return PCIBIOS_SUCCESSFUL;
682}
683
684static struct pci_ops prep_pci_ops =
685{
686 prep_read_config,
687 prep_write_config
688};
689#endif
690
691#define MOTOROLA_CPUTYPE_REG 0x800
692#define MOTOROLA_BASETYPE_REG 0x803
693#define MPIC_RAVEN_ID 0x48010000
694#define MPIC_HAWK_ID 0x48030000
695#define MOT_PROC2_BIT 0x800
696
697static u_char prep_openpic_initsenses[] __initdata = {
698 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
699 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_FALCN_ECC_ERR */
700 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_ETHERNET */
701 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
702 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_GRAPHICS */
703 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
704 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
705 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
706 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
707 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
708 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
709 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
710 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
711 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
712 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
713};
714
715#define MOT_RAVEN_PRESENT 0x1
716#define MOT_HAWK_PRESENT 0x2
717
718int mot_entry = -1;
719int prep_keybd_present = 1;
720int MotMPIC;
721int mot_multi;
722
723int __init
724raven_init(void)
725{
726 unsigned int devid;
727 unsigned int pci_membase;
728 unsigned char base_mod;
729
730 /* Check to see if the Raven chip exists. */
731 if ( _prep_type != _PREP_Motorola) {
732 OpenPIC_Addr = NULL;
733 return 0;
734 }
735
736 /* Check to see if this board is a type that might have a Raven. */
737 if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) {
738 OpenPIC_Addr = NULL;
739 return 0;
740 }
741
742 /* Check the first PCI device to see if it is a Raven. */
743 early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &devid);
744
745 switch (devid & 0xffff0000) {
746 case MPIC_RAVEN_ID:
747 MotMPIC = MOT_RAVEN_PRESENT;
748 break;
749 case MPIC_HAWK_ID:
750 MotMPIC = MOT_HAWK_PRESENT;
751 break;
752 default:
753 OpenPIC_Addr = NULL;
754 return 0;
755 }
756
757
758 /* Read the memory base register. */
759 early_read_config_dword(NULL, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
760
761 if (pci_membase == 0) {
762 OpenPIC_Addr = NULL;
763 return 0;
764 }
765
766 /* Map the Raven MPIC registers to virtual memory. */
767 OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000);
768
769 OpenPIC_InitSenses = prep_openpic_initsenses;
770 OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
771
772 ppc_md.get_irq = openpic_get_irq;
773
774 /* If raven is present on Motorola store the system config register
775 * for later use.
776 */
777 ProcInfo = (unsigned long *)ioremap(0xfef80400, 4);
778
779 /* Indicate to system if this is a multiprocessor board */
780 if (!(*ProcInfo & MOT_PROC2_BIT)) {
781 mot_multi = 1;
782 }
783
784 /* This is a hack. If this is a 2300 or 2400 mot board then there is
785 * no keyboard controller and we have to indicate that.
786 */
787 base_mod = inb(MOTOROLA_BASETYPE_REG);
788 if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) ||
789 (base_mod == 0xFA) || (base_mod == 0xE1))
790 prep_keybd_present = 0;
791
792 return 1;
793}
794
795struct mot_info {
796 int cpu_type; /* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */
797 /* 0x200 if this board has a Hawk chip. */
798 int base_type;
799 int max_cpu; /* ored with 0x80 if this board should be checked for multi CPU */
800 const char *name;
801 unsigned char *map;
802 unsigned char *routes;
803 void (*map_non0_bus)(struct pci_dev *); /* For boards with more than bus 0 devices. */
804 struct powerplus_irq_list *pci_irq_list; /* List of PCI MPIC inputs */
805 unsigned char secondary_bridge_devfn; /* devfn of secondary bus transparent bridge */
806} mot_info[] = {
807 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
808 {0x010, 0x00, 0x00, "Genesis", Genesis_pci_IRQ_map, Genesis_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
809 {0x020, 0x00, 0x00, "Powerstack (Series E)", Comet_pci_IRQ_map, Comet_pci_IRQ_routes, NULL, NULL, 0x00},
810 {0x040, 0x00, 0x00, "Blackhawk (Powerstack)", Blackhawk_pci_IRQ_map, Blackhawk_pci_IRQ_routes, NULL, NULL, 0x00},
811 {0x050, 0x00, 0x00, "Omaha (PowerStack II Pro3000)", Omaha_pci_IRQ_map, Omaha_pci_IRQ_routes, NULL, NULL, 0x00},
812 {0x060, 0x00, 0x00, "Utah (Powerstack II Pro4000)", Utah_pci_IRQ_map, Utah_pci_IRQ_routes, NULL, NULL, 0x00},
813 {0x0A0, 0x00, 0x00, "Powerstack (Series EX)", Comet2_pci_IRQ_map, Comet2_pci_IRQ_routes, NULL, NULL, 0x00},
814 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xFF},
815 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", Sitka_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
816 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xC0},
817 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
818 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
819 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
820 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
821 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
822 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
823 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
824 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
825 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
826 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
827 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
828 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
829 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
830 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
831 {0x1E0, 0xFF, 0x00, "MVME 1600-001 or 1600-011", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
832 {0x000, 0x00, 0x00, "", NULL, NULL, NULL, NULL, 0x00}
833};
834
835void __init
836ibm_prep_init(void)
837{
838 if (have_residual_data) {
839 u32 addr, real_addr, len, offset;
840 PPC_DEVICE *mpic;
841 PnP_TAG_PACKET *pkt;
842
843 /* Use the PReP residual data to determine if an OpenPIC is
844 * present. If so, get the large vendor packet which will
845 * tell us the base address and length in memory.
846 * If we are successful, ioremap the memory area and set
847 * OpenPIC_Addr (this indicates that the OpenPIC was found).
848 */
849 mpic = residual_find_device(-1, NULL, SystemPeripheral,
850 ProgrammableInterruptController, MPIC, 0);
851 if (!mpic)
852 return;
853
854 pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap +
855 mpic->AllocatedOffset, 9, 0);
856
857 if (!pkt)
858 return;
859
860#define p pkt->L4_Pack.L4_Data.L4_PPCPack
861 if (p.PPCData[1] == 32) {
862 switch (p.PPCData[0]) {
863 case 1: offset = PREP_ISA_IO_BASE; break;
864 case 2: offset = PREP_ISA_MEM_BASE; break;
865 default: return; /* Not I/O or memory?? */
866 }
867 }
868 else
869 return; /* Not a 32-bit address */
870
871 real_addr = ld_le32((unsigned int *) (p.PPCData + 4));
872 if (real_addr == 0xffffffff)
873 return;
874
875 /* Adjust address to be as seen by CPU */
876 addr = real_addr + offset;
877
878 len = ld_le32((unsigned int *) (p.PPCData + 12));
879 if (!len)
880 return;
881#undef p
882 OpenPIC_Addr = ioremap(addr, len);
883 ppc_md.get_irq = openpic_get_irq;
884
885 OpenPIC_InitSenses = prep_openpic_initsenses;
886 OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
887
888 printk(KERN_INFO "MPIC at 0x%08x (0x%08x), length 0x%08x "
889 "mapped to 0x%p\n", addr, real_addr, len, OpenPIC_Addr);
890 }
891}
892
893static void __init
894ibm43p_pci_map_non0(struct pci_dev *dev)
895{
896 unsigned char intpin;
897 static unsigned char bridge_intrs[4] = { 3, 4, 5, 8 };
898
899 if (dev == NULL)
900 return;
901 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin);
902 if (intpin < 1 || intpin > 4)
903 return;
904 intpin = (PCI_SLOT(dev->devfn) + intpin - 1) & 3;
905 dev->irq = openpic_to_irq(bridge_intrs[intpin]);
906 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
907}
908
909void __init
910prep_residual_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
911{
912 if (have_residual_data) {
913 Motherboard_map_name = res->VitalProductData.PrintableModel;
914 Motherboard_map = NULL;
915 Motherboard_routes = NULL;
916 residual_irq_mask(irq_edge_mask_lo, irq_edge_mask_hi);
917 }
918}
919
920void __init
921prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
922{
923 Motherboard_map_name = "IBM 6015/7020 (Sandalfoot/Sandalbow)";
924 Motherboard_map = ibm6015_pci_IRQ_map;
925 Motherboard_routes = ibm6015_pci_IRQ_routes;
926 *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
927 *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
928}
929
930void __init
931prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
932{
933 Motherboard_map_name = "IBM Thinkpad 850/860";
934 Motherboard_map = Nobis_pci_IRQ_map;
935 Motherboard_routes = Nobis_pci_IRQ_routes;
936 *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
937 *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
938}
939
940void __init
941prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
942{
943 Motherboard_map_name = "IBM 7248, PowerSeries 830/850 (Carolina)";
944 Motherboard_map = ibm8xx_pci_IRQ_map;
945 Motherboard_routes = ibm8xx_pci_IRQ_routes;
946 *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
947 *irq_edge_mask_hi = 0xA4; /* IRQs 10, 13, 15 level-triggered */
948}
949
950void __init
951prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
952{
953 Motherboard_map_name = "IBM 43P-140 (Tiger1)";
954 Motherboard_map = ibm43p_pci_IRQ_map;
955 Motherboard_routes = ibm43p_pci_IRQ_routes;
956 Motherboard_non0 = ibm43p_pci_map_non0;
957 *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
958 *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
959}
960
961void __init
962prep_route_pci_interrupts(void)
963{
964 unsigned char *ibc_pirq = (unsigned char *)0x80800860;
965 unsigned char *ibc_pcicon = (unsigned char *)0x80800840;
966 int i;
967
968 if ( _prep_type == _PREP_Motorola)
969 {
970 unsigned short irq_mode;
971 unsigned char cpu_type;
972 unsigned char base_mod;
973 int entry;
974
975 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
976 base_mod = inb(MOTOROLA_BASETYPE_REG);
977
978 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
979 if (mot_info[entry].cpu_type & 0x200) { /* Check for Hawk chip */
980 if (!(MotMPIC & MOT_HAWK_PRESENT))
981 continue;
982 } else { /* Check non hawk boards */
983 if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
984 continue;
985
986 if (mot_info[entry].base_type == 0) {
987 mot_entry = entry;
988 break;
989 }
990
991 if (mot_info[entry].base_type != base_mod)
992 continue;
993 }
994
995 if (!(mot_info[entry].max_cpu & 0x80)) {
996 mot_entry = entry;
997 break;
998 }
999
1000 /* processor 1 not present and max processor zero indicated */
1001 if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) {
1002 mot_entry = entry;
1003 break;
1004 }
1005
1006 /* processor 1 present and max processor zero indicated */
1007 if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) {
1008 mot_entry = entry;
1009 break;
1010 }
1011 }
1012
1013 if (mot_entry == -1) /* No particular cpu type found - assume Blackhawk */
1014 mot_entry = 3;
1015
1016 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
1017 Motherboard_map = mot_info[mot_entry].map;
1018 Motherboard_routes = mot_info[mot_entry].routes;
1019 Motherboard_non0 = mot_info[mot_entry].map_non0_bus;
1020
1021 if (!(mot_info[entry].cpu_type & 0x100)) {
1022 /* AJF adjust level/edge control according to routes */
1023 irq_mode = 0;
1024 for (i = 1; i <= 4; i++)
1025 irq_mode |= ( 1 << Motherboard_routes[i] );
1026 outb( irq_mode & 0xff, 0x4d0 );
1027 outb( (irq_mode >> 8) & 0xff, 0x4d1 );
1028 }
1029 } else if ( _prep_type == _PREP_IBM ) {
1030 unsigned char irq_edge_mask_lo, irq_edge_mask_hi;
1031 unsigned short irq_edge_mask;
1032 int i;
1033
1034 setup_ibm_pci(&irq_edge_mask_lo, &irq_edge_mask_hi);
1035
1036 outb(inb(0x04d0)|irq_edge_mask_lo, 0x4d0); /* primary 8259 */
1037 outb(inb(0x04d1)|irq_edge_mask_hi, 0x4d1); /* cascaded 8259 */
1038
1039 irq_edge_mask = (irq_edge_mask_hi << 8) | irq_edge_mask_lo;
1040 for (i = 0; i < 16; ++i, irq_edge_mask >>= 1)
1041 if (irq_edge_mask & 1)
1042 irq_desc[i].status |= IRQ_LEVEL;
1043 } else {
1044 printk("No known machine pci routing!\n");
1045 return;
1046 }
1047
1048 /* Set up mapping from slots */
1049 if (Motherboard_routes) {
1050 for (i = 1; i <= 4; i++)
1051 ibc_pirq[i-1] = Motherboard_routes[i];
1052
1053 /* Enable PCI interrupts */
1054 *ibc_pcicon |= 0x20;
1055 }
1056}
1057
1058void __init
1059prep_pib_init(void)
1060{
1061 unsigned char reg;
1062 unsigned short short_reg;
1063
1064 struct pci_dev *dev = NULL;
1065
1066 if (( _prep_type == _PREP_Motorola) && (OpenPIC_Addr)) {
1067 /*
1068 * Perform specific configuration for the Via Tech or
1069 * or Winbond PCI-ISA-Bridge part.
1070 */
1071 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
1072 PCI_DEVICE_ID_VIA_82C586_1, dev))) {
1073 /*
1074 * PPCBUG does not set the enable bits
1075 * for the IDE device. Force them on here.
1076 */
1077 pci_read_config_byte(dev, 0x40, &reg);
1078
1079 reg |= 0x03; /* IDE: Chip Enable Bits */
1080 pci_write_config_byte(dev, 0x40, reg);
1081 }
1082 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
1083 PCI_DEVICE_ID_VIA_82C586_2,
1084 dev)) && (dev->devfn = 0x5a)) {
1085 /* Force correct USB interrupt */
1086 dev->irq = 11;
1087 pci_write_config_byte(dev,
1088 PCI_INTERRUPT_LINE,
1089 dev->irq);
1090 }
1091 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
1092 PCI_DEVICE_ID_WINBOND_83C553, dev))) {
1093 /* Clear PCI Interrupt Routing Control Register. */
1094 short_reg = 0x0000;
1095 pci_write_config_word(dev, 0x44, short_reg);
1096 if (OpenPIC_Addr){
1097 /* Route IDE interrupts to IRQ 14 */
1098 reg = 0xEE;
1099 pci_write_config_byte(dev, 0x43, reg);
1100 }
1101 }
1102 }
1103
1104 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
1105 PCI_DEVICE_ID_WINBOND_82C105, dev))){
1106 if (OpenPIC_Addr){
1107 /*
1108 * Disable LEGIRQ mode so PCI INTS are routed
1109 * directly to the 8259 and enable both channels
1110 */
1111 pci_write_config_dword(dev, 0x40, 0x10ff0033);
1112
1113 /* Force correct IDE interrupt */
1114 dev->irq = 14;
1115 pci_write_config_byte(dev,
1116 PCI_INTERRUPT_LINE,
1117 dev->irq);
1118 } else {
1119 /* Enable LEGIRQ for PCI INT -> 8259 IRQ routing */
1120 pci_write_config_dword(dev, 0x40, 0x10ff08a1);
1121 }
1122 }
1123 pci_dev_put(dev);
1124}
1125
1126static void __init
1127Powerplus_Map_Non0(struct pci_dev *dev)
1128{
1129 struct pci_bus *pbus; /* Parent bus structure pointer */
1130 struct pci_dev *tdev = dev; /* Temporary device structure */
1131 unsigned int devnum; /* Accumulated device number */
1132 unsigned char intline; /* Linux interrupt value */
1133 unsigned char intpin; /* PCI interrupt pin */
1134
1135 /* Check for valid PCI dev pointer */
1136 if (dev == NULL) return;
1137
1138 /* Initialize bridge IDSEL variable */
1139 devnum = PCI_SLOT(tdev->devfn);
1140
1141 /* Read the interrupt pin of the device and adjust for indexing */
1142 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin);
1143
1144 /* If device doesn't request an interrupt, return */
1145 if ( (intpin < 1) || (intpin > 4) )
1146 return;
1147
1148 intpin--;
1149
1150 /*
1151 * Walk up to bus 0, adjusting the interrupt pin for the standard
1152 * PCI bus swizzle.
1153 */
1154 do {
1155 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
1156 pbus = tdev->bus; /* up one level */
1157 tdev = pbus->self;
1158 devnum = PCI_SLOT(tdev->devfn);
1159 } while(tdev->bus->number);
1160
1161 /* Use the primary interrupt inputs by default */
1162 intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
1163
1164 /*
1165 * If the board has secondary interrupt inputs, walk the bus and
1166 * note the devfn of the bridge from bus 0. If it is the same as
1167 * the devfn of the bus bridge with secondary inputs, use those.
1168 * Otherwise, assume it's a PMC site and get the interrupt line
1169 * value from the interrupt routing table.
1170 */
1171 if (mot_info[mot_entry].secondary_bridge_devfn) {
1172 pbus = dev->bus;
1173
1174 while (pbus->primary != 0)
1175 pbus = pbus->parent;
1176
1177 if ((pbus->self)->devfn != 0xA0) {
1178 if ((pbus->self)->devfn == mot_info[mot_entry].secondary_bridge_devfn)
1179 intline = mot_info[mot_entry].pci_irq_list->secondary[intpin];
1180 else {
1181 if ((char *)(mot_info[mot_entry].map) == (char *)Mesquite_pci_IRQ_map)
1182 intline = mot_info[mot_entry].map[((pbus->self)->devfn)/8] + 16;
1183 else {
1184 int i;
1185 for (i=0;i<3;i++)
1186 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
1187 intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
1188 }
1189 }
1190 }
1191 }
1192
1193 /* Write calculated interrupt value to header and device list */
1194 dev->irq = intline;
1195 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, (u8)dev->irq);
1196}
1197
1198void __init
1199prep_pcibios_fixup(void)
1200{
1201 struct pci_dev *dev = NULL;
1202 int irq;
1203 int have_openpic = (OpenPIC_Addr != NULL);
1204
1205 prep_route_pci_interrupts();
1206
1207 printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name);
1208
1209 /* Iterate through all the PCI devices, setting the IRQ */
1210 for_each_pci_dev(dev) {
1211 /*
1212 * If we have residual data, then this is easy: query the
1213 * residual data for the IRQ line allocated to the device.
1214 * This works the same whether we have an OpenPic or not.
1215 */
1216 if (have_residual_data) {
1217 irq = residual_pcidev_irq(dev);
1218 dev->irq = have_openpic ? openpic_to_irq(irq) : irq;
1219 }
1220 /*
1221 * If we don't have residual data, then we need to use
1222 * tables to determine the IRQ. The table organisation
1223 * is different depending on whether there is an OpenPIC
1224 * or not. The tables are only used for bus 0, so check
1225 * this first.
1226 */
1227 else if (dev->bus->number == 0) {
1228 irq = Motherboard_map[PCI_SLOT(dev->devfn)];
1229 dev->irq = have_openpic ? openpic_to_irq(irq)
1230 : Motherboard_routes[irq];
1231 }
1232 /*
1233 * Finally, if we don't have residual data and the bus is
1234 * non-zero, use the callback (if provided)
1235 */
1236 else {
1237 if (Motherboard_non0 != NULL)
1238 Motherboard_non0(dev);
1239
1240 continue;
1241 }
1242
1243 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1244 }
1245
1246 /* Setup the Winbond or Via PIB - prep_pib_init() is coded for
1247 * the non-openpic case, but it breaks (at least) the Utah
1248 * (Powerstack II Pro4000), so only call it if we have an
1249 * openpic.
1250 */
1251 if (have_openpic)
1252 prep_pib_init();
1253}
1254
1255static void __init
1256prep_pcibios_after_init(void)
1257{
1258#if 0
1259 struct pci_dev *dev;
1260
1261 /* If there is a WD 90C, reset the IO BAR to 0x0 (it started that
1262 * way, but the PCI layer relocated it because it thought 0x0 was
1263 * invalid for a BAR).
1264 * If you don't do this, the card's VGA base will be <IO BAR>+0xc0000
1265 * instead of 0xc0000. vgacon.c (for example) is completely unaware of
1266 * this little quirk.
1267 */
1268 dev = pci_get_device(PCI_VENDOR_ID_WD, PCI_DEVICE_ID_WD_90C, NULL);
1269 if (dev) {
1270 dev->resource[1].end -= dev->resource[1].start;
1271 dev->resource[1].start = 0;
1272 /* tell the hardware */
1273 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x0);
1274 pci_dev_put(dev);
1275 }
1276#endif
1277}
1278
1279static void __init
1280prep_init_resource(struct resource *res, unsigned long start,
1281 unsigned long end, int flags)
1282{
1283 res->flags = flags;
1284 res->start = start;
1285 res->end = end;
1286 res->name = "PCI host bridge";
1287 res->parent = NULL;
1288 res->sibling = NULL;
1289 res->child = NULL;
1290}
1291
1292void __init
1293prep_find_bridges(void)
1294{
1295 struct pci_controller* hose;
1296
1297 hose = pcibios_alloc_controller();
1298 if (!hose)
1299 return;
1300
1301 hose->first_busno = 0;
1302 hose->last_busno = 0xff;
1303 hose->pci_mem_offset = PREP_ISA_MEM_BASE;
1304 hose->io_base_phys = PREP_ISA_IO_BASE;
1305 hose->io_base_virt = ioremap(PREP_ISA_IO_BASE, 0x800000);
1306 prep_init_resource(&hose->io_resource, 0, 0x007fffff, IORESOURCE_IO);
1307 prep_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfeffffff,
1308 IORESOURCE_MEM);
1309 setup_indirect_pci(hose, PREP_ISA_IO_BASE + 0xcf8,
1310 PREP_ISA_IO_BASE + 0xcfc);
1311
1312 printk("PReP architecture\n");
1313
1314 if (have_residual_data) {
1315 PPC_DEVICE *hostbridge;
1316
1317 hostbridge = residual_find_device(PROCESSORDEVICE, NULL,
1318 BridgeController, PCIBridge, -1, 0);
1319 if (hostbridge &&
1320 ((hostbridge->DeviceId.Interface == PCIBridgeIndirect) ||
1321 (hostbridge->DeviceId.Interface == PCIBridgeRS6K))) {
1322 PnP_TAG_PACKET * pkt;
1323 pkt = PnP_find_large_vendor_packet(
1324 res->DevicePnPHeap+hostbridge->AllocatedOffset,
1325 3, 0);
1326 if(pkt) {
1327#define p pkt->L4_Pack.L4_Data.L4_PPCPack
1328 setup_indirect_pci(hose,
1329 ld_le32((unsigned *) (p.PPCData)),
1330 ld_le32((unsigned *) (p.PPCData+8)));
1331#undef p
1332 } else
1333 setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
1334 }
1335 }
1336
1337 ppc_md.pcibios_fixup = prep_pcibios_fixup;
1338 ppc_md.pcibios_after_init = prep_pcibios_after_init;
1339}
diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c
deleted file mode 100644
index 465b658c927d..000000000000
--- a/arch/ppc/platforms/prep_setup.c
+++ /dev/null
@@ -1,1043 +0,0 @@
1/*
2 * Copyright (C) 1995 Linus Torvalds
3 * Adapted from 'alpha' version by Gary Thomas
4 * Modified by Cort Dougan (cort@cs.nmt.edu)
5 *
6 * Support for PReP (Motorola MTX/MVME)
7 * by Troy Benjegerdes (hozer@drgw.net)
8 */
9
10/*
11 * bootup setup stuff..
12 */
13
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/errno.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/stddef.h>
21#include <linux/unistd.h>
22#include <linux/ptrace.h>
23#include <linux/slab.h>
24#include <linux/user.h>
25#include <linux/a.out.h>
26#include <linux/screen_info.h>
27#include <linux/major.h>
28#include <linux/interrupt.h>
29#include <linux/reboot.h>
30#include <linux/init.h>
31#include <linux/initrd.h>
32#include <linux/ioport.h>
33#include <linux/console.h>
34#include <linux/timex.h>
35#include <linux/pci.h>
36#include <linux/seq_file.h>
37#include <linux/root_dev.h>
38
39#include <asm/sections.h>
40#include <asm/mmu.h>
41#include <asm/processor.h>
42#include <asm/residual.h>
43#include <asm/io.h>
44#include <asm/pgtable.h>
45#include <asm/cache.h>
46#include <asm/dma.h>
47#include <asm/machdep.h>
48#include <asm/mc146818rtc.h>
49#include <asm/mk48t59.h>
50#include <asm/prep_nvram.h>
51#include <asm/raven.h>
52#include <asm/vga.h>
53#include <asm/time.h>
54#include <asm/mpc10x.h>
55#include <asm/i8259.h>
56#include <asm/open_pic.h>
57#include <asm/pci-bridge.h>
58#include <asm/todc.h>
59
60/* prep registers for L2 */
61#define CACHECRBA 0x80000823 /* Cache configuration register address */
62#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
63#define L2CACHE_512KB 0x00 /* 512KB */
64#define L2CACHE_256KB 0x01 /* 256KB */
65#define L2CACHE_1MB 0x02 /* 1MB */
66#define L2CACHE_NONE 0x03 /* NONE */
67#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
68
69TODC_ALLOC();
70
71extern unsigned char prep_nvram_read_val(int addr);
72extern void prep_nvram_write_val(int addr,
73 unsigned char val);
74extern unsigned char rs_nvram_read_val(int addr);
75extern void rs_nvram_write_val(int addr,
76 unsigned char val);
77extern void ibm_prep_init(void);
78
79extern void prep_find_bridges(void);
80
81int _prep_type;
82
83extern void prep_residual_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
84extern void prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
85extern void prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
86extern void prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
87extern void prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
88
89
90#define cached_21 (((char *)(ppc_cached_irq_mask))[3])
91#define cached_A1 (((char *)(ppc_cached_irq_mask))[2])
92
93extern PTE *Hash, *Hash_end;
94extern unsigned long Hash_size, Hash_mask;
95extern int probingmem;
96extern unsigned long loops_per_jiffy;
97
98/* useful ISA ports */
99#define PREP_SYSCTL 0x81c
100/* present in the IBM reference design; possibly identical in Mot boxes: */
101#define PREP_IBM_SIMM_ID 0x803 /* SIMM size: 32 or 8 MiB */
102#define PREP_IBM_SIMM_PRESENCE 0x804
103#define PREP_IBM_EQUIPMENT 0x80c
104#define PREP_IBM_L2INFO 0x80d
105#define PREP_IBM_PM1 0x82a /* power management register 1 */
106#define PREP_IBM_PLANAR 0x852 /* planar ID - identifies the motherboard */
107#define PREP_IBM_DISP 0x8c0 /* 4-digit LED display */
108
109/* Equipment Present Register masks: */
110#define PREP_IBM_EQUIPMENT_RESERVED 0x80
111#define PREP_IBM_EQUIPMENT_SCSIFUSE 0x40
112#define PREP_IBM_EQUIPMENT_L2_COPYBACK 0x08
113#define PREP_IBM_EQUIPMENT_L2_256 0x04
114#define PREP_IBM_EQUIPMENT_CPU 0x02
115#define PREP_IBM_EQUIPMENT_L2 0x01
116
117/* planar ID values: */
118/* Sandalfoot/Sandalbow (6015/7020) */
119#define PREP_IBM_SANDALFOOT 0xfc
120/* Woodfield, Thinkpad 850/860 (6042/7249) */
121#define PREP_IBM_THINKPAD 0xff /* planar ID unimplemented */
122/* PowerSeries 830/850 (6050/6070) */
123#define PREP_IBM_CAROLINA_IDE_0 0xf0
124#define PREP_IBM_CAROLINA_IDE_1 0xf1
125#define PREP_IBM_CAROLINA_IDE_2 0xf2
126#define PREP_IBM_CAROLINA_IDE_3 0xf3
127/* 7248-43P */
128#define PREP_IBM_CAROLINA_SCSI_0 0xf4
129#define PREP_IBM_CAROLINA_SCSI_1 0xf5
130#define PREP_IBM_CAROLINA_SCSI_2 0xf6
131#define PREP_IBM_CAROLINA_SCSI_3 0xf7 /* missing from Carolina Tech Spec */
132/* Tiger1 (7043-140) */
133#define PREP_IBM_TIGER1_133 0xd1
134#define PREP_IBM_TIGER1_166 0xd2
135#define PREP_IBM_TIGER1_180 0xd3
136#define PREP_IBM_TIGER1_xxx 0xd4 /* unknown, but probably exists */
137#define PREP_IBM_TIGER1_333 0xd5 /* missing from Tiger Tech Spec */
138
139/* setup_ibm_pci:
140 * set Motherboard_map_name, Motherboard_map, Motherboard_routes.
141 * return 8259 edge/level masks.
142 */
143void (*setup_ibm_pci)(char *irq_lo, char *irq_hi);
144
145extern char *Motherboard_map_name; /* for use in *_cpuinfo */
146
147/*
148 * As found in the PReP reference implementation.
149 * Used by Thinkpad, Sandalfoot (6015/7020), and all Motorola PReP.
150 */
151static void __init
152prep_gen_enable_l2(void)
153{
154 outb(inb(PREP_SYSCTL) | 0x3, PREP_SYSCTL);
155}
156
157/* Used by Carolina and Tiger1 */
158static void __init
159prep_carolina_enable_l2(void)
160{
161 outb(inb(PREP_SYSCTL) | 0xc0, PREP_SYSCTL);
162}
163
164/* cpuinfo code common to all IBM PReP */
165static void
166prep_ibm_cpuinfo(struct seq_file *m)
167{
168 unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
169
170 seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name);
171
172 seq_printf(m, "upgrade cpu\t: ");
173 if (equip_reg & PREP_IBM_EQUIPMENT_CPU) {
174 seq_printf(m, "not ");
175 }
176 seq_printf(m, "present\n");
177
178 /* print info about the SCSI fuse */
179 seq_printf(m, "scsi fuse\t: ");
180 if (equip_reg & PREP_IBM_EQUIPMENT_SCSIFUSE)
181 seq_printf(m, "ok");
182 else
183 seq_printf(m, "bad");
184 seq_printf(m, "\n");
185
186 /* print info about SIMMs */
187 if (have_residual_data) {
188 int i;
189 seq_printf(m, "simms\t\t: ");
190 for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
191 if (res->Memories[i].SIMMSize != 0)
192 seq_printf(m, "%d:%ldMiB ", i,
193 (res->Memories[i].SIMMSize > 1024) ?
194 res->Memories[i].SIMMSize>>20 :
195 res->Memories[i].SIMMSize);
196 }
197 seq_printf(m, "\n");
198 }
199}
200
201static int
202prep_gen_cpuinfo(struct seq_file *m)
203{
204 prep_ibm_cpuinfo(m);
205 return 0;
206}
207
208static int
209prep_sandalfoot_cpuinfo(struct seq_file *m)
210{
211 unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
212
213 prep_ibm_cpuinfo(m);
214
215 /* report amount and type of L2 cache present */
216 seq_printf(m, "L2 cache\t: ");
217 if (equip_reg & PREP_IBM_EQUIPMENT_L2) {
218 seq_printf(m, "not present");
219 } else {
220 if (equip_reg & PREP_IBM_EQUIPMENT_L2_256)
221 seq_printf(m, "256KiB");
222 else
223 seq_printf(m, "unknown size");
224
225 if (equip_reg & PREP_IBM_EQUIPMENT_L2_COPYBACK)
226 seq_printf(m, ", copy-back");
227 else
228 seq_printf(m, ", write-through");
229 }
230 seq_printf(m, "\n");
231
232 return 0;
233}
234
235static int
236prep_thinkpad_cpuinfo(struct seq_file *m)
237{
238 unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
239 char *cpubus_speed, *pci_speed;
240
241 prep_ibm_cpuinfo(m);
242
243 /* report amount and type of L2 cache present */
244 seq_printf(m, "l2 cache\t: ");
245 if ((equip_reg & 0x1) == 0) {
246 switch ((equip_reg & 0xc) >> 2) {
247 case 0x0:
248 seq_printf(m, "128KiB look-aside 2-way write-through\n");
249 break;
250 case 0x1:
251 seq_printf(m, "512KiB look-aside direct-mapped write-back\n");
252 break;
253 case 0x2:
254 seq_printf(m, "256KiB look-aside 2-way write-through\n");
255 break;
256 case 0x3:
257 seq_printf(m, "256KiB look-aside direct-mapped write-back\n");
258 break;
259 }
260 } else {
261 seq_printf(m, "not present\n");
262 }
263
264 /* report bus speeds because we can */
265 if ((equip_reg & 0x80) == 0) {
266 switch ((equip_reg & 0x30) >> 4) {
267 case 0x1:
268 cpubus_speed = "50";
269 pci_speed = "25";
270 break;
271 case 0x3:
272 cpubus_speed = "66";
273 pci_speed = "33";
274 break;
275 default:
276 cpubus_speed = "unknown";
277 pci_speed = "unknown";
278 break;
279 }
280 } else {
281 switch ((equip_reg & 0x30) >> 4) {
282 case 0x1:
283 cpubus_speed = "25";
284 pci_speed = "25";
285 break;
286 case 0x2:
287 cpubus_speed = "60";
288 pci_speed = "30";
289 break;
290 case 0x3:
291 cpubus_speed = "33";
292 pci_speed = "33";
293 break;
294 default:
295 cpubus_speed = "unknown";
296 pci_speed = "unknown";
297 break;
298 }
299 }
300 seq_printf(m, "60x bus\t\t: %sMHz\n", cpubus_speed);
301 seq_printf(m, "pci bus\t\t: %sMHz\n", pci_speed);
302
303 return 0;
304}
305
306static int
307prep_carolina_cpuinfo(struct seq_file *m)
308{
309 unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
310
311 prep_ibm_cpuinfo(m);
312
313 /* report amount and type of L2 cache present */
314 seq_printf(m, "l2 cache\t: ");
315 if ((equip_reg & 0x1) == 0) {
316 unsigned int l2_reg = inb(PREP_IBM_L2INFO);
317
318 /* L2 size */
319 if ((l2_reg & 0x60) == 0)
320 seq_printf(m, "256KiB");
321 else if ((l2_reg & 0x60) == 0x20)
322 seq_printf(m, "512KiB");
323 else
324 seq_printf(m, "unknown size");
325
326 /* L2 type */
327 if ((l2_reg & 0x3) == 0)
328 seq_printf(m, ", async");
329 else if ((l2_reg & 0x3) == 1)
330 seq_printf(m, ", sync");
331 else
332 seq_printf(m, ", unknown type");
333
334 seq_printf(m, "\n");
335 } else {
336 seq_printf(m, "not present\n");
337 }
338
339 return 0;
340}
341
342static int
343prep_tiger1_cpuinfo(struct seq_file *m)
344{
345 unsigned int l2_reg = inb(PREP_IBM_L2INFO);
346
347 prep_ibm_cpuinfo(m);
348
349 /* report amount and type of L2 cache present */
350 seq_printf(m, "l2 cache\t: ");
351 if ((l2_reg & 0xf) == 0xf) {
352 seq_printf(m, "not present\n");
353 } else {
354 if (l2_reg & 0x8)
355 seq_printf(m, "async, ");
356 else
357 seq_printf(m, "sync burst, ");
358
359 if (l2_reg & 0x4)
360 seq_printf(m, "parity, ");
361 else
362 seq_printf(m, "no parity, ");
363
364 switch (l2_reg & 0x3) {
365 case 0x0:
366 seq_printf(m, "256KiB\n");
367 break;
368 case 0x1:
369 seq_printf(m, "512KiB\n");
370 break;
371 case 0x2:
372 seq_printf(m, "1MiB\n");
373 break;
374 default:
375 seq_printf(m, "unknown size\n");
376 break;
377 }
378 }
379
380 return 0;
381}
382
383
384/* Used by all Motorola PReP */
385static int
386prep_mot_cpuinfo(struct seq_file *m)
387{
388 unsigned int cachew = *((unsigned char *)CACHECRBA);
389
390 seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name);
391
392 /* report amount and type of L2 cache present */
393 seq_printf(m, "l2 cache\t: ");
394 switch (cachew & L2CACHE_MASK) {
395 case L2CACHE_512KB:
396 seq_printf(m, "512KiB");
397 break;
398 case L2CACHE_256KB:
399 seq_printf(m, "256KiB");
400 break;
401 case L2CACHE_1MB:
402 seq_printf(m, "1MiB");
403 break;
404 case L2CACHE_NONE:
405 seq_printf(m, "none\n");
406 goto no_l2;
407 break;
408 default:
409 seq_printf(m, "%x\n", cachew);
410 }
411
412 seq_printf(m, ", parity %s",
413 (cachew & L2CACHE_PARITY)? "enabled" : "disabled");
414
415 seq_printf(m, " SRAM:");
416
417 switch ( ((cachew & 0xf0) >> 4) & ~(0x3) ) {
418 case 1: seq_printf(m, "synchronous, parity, flow-through\n");
419 break;
420 case 2: seq_printf(m, "asynchronous, no parity\n");
421 break;
422 case 3: seq_printf(m, "asynchronous, parity\n");
423 break;
424 default:seq_printf(m, "synchronous, pipelined, no parity\n");
425 break;
426 }
427
428no_l2:
429 /* print info about SIMMs */
430 if (have_residual_data) {
431 int i;
432 seq_printf(m, "simms\t\t: ");
433 for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
434 if (res->Memories[i].SIMMSize != 0)
435 seq_printf(m, "%d:%ldM ", i,
436 (res->Memories[i].SIMMSize > 1024) ?
437 res->Memories[i].SIMMSize>>20 :
438 res->Memories[i].SIMMSize);
439 }
440 seq_printf(m, "\n");
441 }
442
443 return 0;
444}
445
446static void
447prep_restart(char *cmd)
448{
449#define PREP_SP92 0x92 /* Special Port 92 */
450 local_irq_disable(); /* no interrupts */
451
452 /* set exception prefix high - to the prom */
453 _nmask_and_or_msr(0, MSR_IP);
454
455 /* make sure bit 0 (reset) is a 0 */
456 outb( inb(PREP_SP92) & ~1L , PREP_SP92);
457 /* signal a reset to system control port A - soft reset */
458 outb( inb(PREP_SP92) | 1 , PREP_SP92);
459
460 while ( 1 ) ;
461 /* not reached */
462#undef PREP_SP92
463}
464
465static void
466prep_halt(void)
467{
468 local_irq_disable(); /* no interrupts */
469
470 /* set exception prefix high - to the prom */
471 _nmask_and_or_msr(0, MSR_IP);
472
473 while ( 1 ) ;
474 /* not reached */
475}
476
477/* Carrera is the power manager in the Thinkpads. Unfortunately not much is
478 * known about it, so we can't power down.
479 */
480static void
481prep_carrera_poweroff(void)
482{
483 prep_halt();
484}
485
486/*
487 * On most IBM PReP's, power management is handled by a Signetics 87c750
488 * behind the Utah component on the ISA bus. To access the 750 you must write
489 * a series of nibbles to port 0x82a (decoded by the Utah). This is described
490 * somewhat in the IBM Carolina Technical Specification.
491 * -Hollis
492 */
493static void
494utah_sig87c750_setbit(unsigned int bytenum, unsigned int bitnum, int value)
495{
496 /*
497 * byte1: 0 0 0 1 0 d a5 a4
498 * byte2: 0 0 0 1 a3 a2 a1 a0
499 *
500 * d = the bit's value, enabled or disabled
501 * (a5 a4 a3) = the byte number, minus 20
502 * (a2 a1 a0) = the bit number
503 *
504 * example: set the 5th bit of byte 21 (21.5)
505 * a5 a4 a3 = 001 (byte 1)
506 * a2 a1 a0 = 101 (bit 5)
507 *
508 * byte1 = 0001 0100 (0x14)
509 * byte2 = 0001 1101 (0x1d)
510 */
511 unsigned char byte1=0x10, byte2=0x10;
512
513 /* the 750's '20.0' is accessed as '0.0' through Utah (which adds 20) */
514 bytenum -= 20;
515
516 byte1 |= (!!value) << 2; /* set d */
517 byte1 |= (bytenum >> 1) & 0x3; /* set a5, a4 */
518
519 byte2 |= (bytenum & 0x1) << 3; /* set a3 */
520 byte2 |= bitnum & 0x7; /* set a2, a1, a0 */
521
522 outb(byte1, PREP_IBM_PM1); /* first nibble */
523 mb();
524 udelay(100); /* important: let controller recover */
525
526 outb(byte2, PREP_IBM_PM1); /* second nibble */
527 mb();
528 udelay(100); /* important: let controller recover */
529}
530
531static void
532prep_sig750_poweroff(void)
533{
534 /* tweak the power manager found in most IBM PRePs (except Thinkpads) */
535
536 local_irq_disable();
537 /* set exception prefix high - to the prom */
538 _nmask_and_or_msr(0, MSR_IP);
539
540 utah_sig87c750_setbit(21, 5, 1); /* set bit 21.5, "PMEXEC_OFF" */
541
542 while (1) ;
543 /* not reached */
544}
545
546static int
547prep_show_percpuinfo(struct seq_file *m, int i)
548{
549 /* PREP's without residual data will give incorrect values here */
550 seq_printf(m, "clock\t\t: ");
551 if (have_residual_data)
552 seq_printf(m, "%ldMHz\n",
553 (res->VitalProductData.ProcessorHz > 1024) ?
554 res->VitalProductData.ProcessorHz / 1000000 :
555 res->VitalProductData.ProcessorHz);
556 else
557 seq_printf(m, "???\n");
558
559 return 0;
560}
561
562/*
563 * Fill out screen_info according to the residual data. This allows us to use
564 * at least vesafb.
565 */
566static void __init
567prep_init_vesa(void)
568{
569#if (defined(CONFIG_FB_VGA16) || defined(CONFIG_FB_VGA16_MODULE) || \
570 defined(CONFIG_FB_VESA))
571 PPC_DEVICE *vgadev = NULL;
572
573 if (have_residual_data)
574 vgadev = residual_find_device(~0, NULL, DisplayController,
575 SVGAController, -1, 0);
576
577 if (vgadev != NULL) {
578 PnP_TAG_PACKET *pkt;
579
580 pkt = PnP_find_large_vendor_packet(
581 (unsigned char *)&res->DevicePnPHeap[vgadev->AllocatedOffset],
582 0x04, 0); /* 0x04 = Display Tag */
583 if (pkt != NULL) {
584 unsigned char *ptr = (unsigned char *)pkt;
585
586 if (ptr[4]) {
587 /* graphics mode */
588 screen_info.orig_video_isVGA = VIDEO_TYPE_VLFB;
589
590 screen_info.lfb_depth = ptr[4] * 8;
591
592 screen_info.lfb_width = swab16(*(short *)(ptr+6));
593 screen_info.lfb_height = swab16(*(short *)(ptr+8));
594 screen_info.lfb_linelength = swab16(*(short *)(ptr+10));
595
596 screen_info.lfb_base = swab32(*(long *)(ptr+12));
597 screen_info.lfb_size = swab32(*(long *)(ptr+20)) / 65536;
598 }
599 }
600 }
601#endif
602}
603
604/*
605 * Set DBAT 2 to access 0x80000000 so early progress messages will work
606 */
607static __inline__ void
608prep_set_bat(void)
609{
610 /* wait for all outstanding memory access to complete */
611 mb();
612
613 /* setup DBATs */
614 mtspr(SPRN_DBAT2U, 0x80001ffe);
615 mtspr(SPRN_DBAT2L, 0x8000002a);
616
617 /* wait for updates */
618 mb();
619}
620
621/*
622 * IBM 3-digit status LED
623 */
624static unsigned int ibm_statusled_base;
625
626static void
627ibm_statusled_progress(char *s, unsigned short hex);
628
629static int
630ibm_statusled_panic(struct notifier_block *dummy1, unsigned long dummy2,
631 void * dummy3)
632{
633 ibm_statusled_progress(NULL, 0x505); /* SOS */
634 return NOTIFY_DONE;
635}
636
637static struct notifier_block ibm_statusled_block = {
638 ibm_statusled_panic,
639 NULL,
640 INT_MAX /* try to do it first */
641};
642
643static void
644ibm_statusled_progress(char *s, unsigned short hex)
645{
646 static int notifier_installed;
647 /*
648 * Progress uses 4 digits and we have only 3. So, we map 0xffff to
649 * 0xfff for display switch off. Out of range values are mapped to
650 * 0xeff, as I'm told 0xf00 and above are reserved for hardware codes.
651 * Install the panic notifier when the display is first switched off.
652 */
653 if (hex == 0xffff) {
654 hex = 0xfff;
655 if (!notifier_installed) {
656 ++notifier_installed;
657 atomic_notifier_chain_register(&panic_notifier_list,
658 &ibm_statusled_block);
659 }
660 }
661 else
662 if (hex > 0xfff)
663 hex = 0xeff;
664
665 mb();
666 outw(hex, ibm_statusled_base);
667}
668
669static void __init
670ibm_statusled_init(void)
671{
672 /*
673 * The IBM 3-digit LED display is specified in the residual data
674 * as an operator panel device, type "System Status LED". Find
675 * that device and determine its address. We validate all the
676 * other parameters on the off-chance another, similar device
677 * exists.
678 */
679 if (have_residual_data) {
680 PPC_DEVICE *led;
681 PnP_TAG_PACKET *pkt;
682
683 led = residual_find_device(~0, NULL, SystemPeripheral,
684 OperatorPanel, SystemStatusLED, 0);
685 if (!led)
686 return;
687
688 pkt = PnP_find_packet((unsigned char *)
689 &res->DevicePnPHeap[led->AllocatedOffset], S8_Packet, 0);
690 if (!pkt)
691 return;
692
693 if (pkt->S8_Pack.IOInfo != ISAAddr16bit)
694 return;
695 if (*(unsigned short *)pkt->S8_Pack.RangeMin !=
696 *(unsigned short *)pkt->S8_Pack.RangeMax)
697 return;
698 if (pkt->S8_Pack.IOAlign != 2)
699 return;
700 if (pkt->S8_Pack.IONum != 2)
701 return;
702
703 ibm_statusled_base = ld_le16((unsigned short *)
704 (pkt->S8_Pack.RangeMin));
705 ppc_md.progress = ibm_statusled_progress;
706 }
707}
708
709static void __init
710prep_setup_arch(void)
711{
712 unsigned char reg;
713 int is_ide=0;
714
715 /* init to some ~sane value until calibrate_delay() runs */
716 loops_per_jiffy = 50000000;
717
718 /* Lookup PCI host bridges */
719 prep_find_bridges();
720
721 /* Set up floppy in PS/2 mode */
722 outb(0x09, SIO_CONFIG_RA);
723 reg = inb(SIO_CONFIG_RD);
724 reg = (reg & 0x3F) | 0x40;
725 outb(reg, SIO_CONFIG_RD);
726 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
727
728 switch ( _prep_type )
729 {
730 case _PREP_IBM:
731 reg = inb(PREP_IBM_PLANAR);
732 printk(KERN_INFO "IBM planar ID: %02x", reg);
733 switch (reg) {
734 case PREP_IBM_SANDALFOOT:
735 prep_gen_enable_l2();
736 setup_ibm_pci = prep_sandalfoot_setup_pci;
737 ppc_md.power_off = prep_sig750_poweroff;
738 ppc_md.show_cpuinfo = prep_sandalfoot_cpuinfo;
739 break;
740 case PREP_IBM_THINKPAD:
741 prep_gen_enable_l2();
742 setup_ibm_pci = prep_thinkpad_setup_pci;
743 ppc_md.power_off = prep_carrera_poweroff;
744 ppc_md.show_cpuinfo = prep_thinkpad_cpuinfo;
745 break;
746 default:
747 if (have_residual_data) {
748 prep_gen_enable_l2();
749 setup_ibm_pci = prep_residual_setup_pci;
750 ppc_md.power_off = prep_halt;
751 ppc_md.show_cpuinfo = prep_gen_cpuinfo;
752 break;
753 }
754 else
755 printk(" - unknown! Assuming Carolina");
756 /* fall through */
757 case PREP_IBM_CAROLINA_IDE_0:
758 case PREP_IBM_CAROLINA_IDE_1:
759 case PREP_IBM_CAROLINA_IDE_2:
760 case PREP_IBM_CAROLINA_IDE_3:
761 is_ide = 1;
762 case PREP_IBM_CAROLINA_SCSI_0:
763 case PREP_IBM_CAROLINA_SCSI_1:
764 case PREP_IBM_CAROLINA_SCSI_2:
765 case PREP_IBM_CAROLINA_SCSI_3:
766 prep_carolina_enable_l2();
767 setup_ibm_pci = prep_carolina_setup_pci;
768 ppc_md.power_off = prep_sig750_poweroff;
769 ppc_md.show_cpuinfo = prep_carolina_cpuinfo;
770 break;
771 case PREP_IBM_TIGER1_133:
772 case PREP_IBM_TIGER1_166:
773 case PREP_IBM_TIGER1_180:
774 case PREP_IBM_TIGER1_xxx:
775 case PREP_IBM_TIGER1_333:
776 prep_carolina_enable_l2();
777 setup_ibm_pci = prep_tiger1_setup_pci;
778 ppc_md.power_off = prep_sig750_poweroff;
779 ppc_md.show_cpuinfo = prep_tiger1_cpuinfo;
780 break;
781 }
782 printk("\n");
783
784 /* default root device */
785 if (is_ide)
786 ROOT_DEV = MKDEV(IDE0_MAJOR, 3);
787 else
788 ROOT_DEV = MKDEV(SCSI_DISK0_MAJOR, 3);
789
790 break;
791 case _PREP_Motorola:
792 prep_gen_enable_l2();
793 ppc_md.power_off = prep_halt;
794 ppc_md.show_cpuinfo = prep_mot_cpuinfo;
795
796#ifdef CONFIG_BLK_DEV_INITRD
797 if (initrd_start)
798 ROOT_DEV = Root_RAM0;
799 else
800#endif
801#ifdef CONFIG_ROOT_NFS
802 ROOT_DEV = Root_NFS;
803#else
804 ROOT_DEV = Root_SDA2;
805#endif
806 break;
807 }
808
809 /* Read in NVRAM data */
810 init_prep_nvram();
811
812 /* if no bootargs, look in NVRAM */
813 if ( cmd_line[0] == '\0' ) {
814 char *bootargs;
815 bootargs = prep_nvram_get_var("bootargs");
816 if (bootargs != NULL) {
817 strcpy(cmd_line, bootargs);
818 /* again.. */
819 strcpy(boot_command_line, cmd_line);
820 }
821 }
822
823 prep_init_vesa();
824
825 switch (_prep_type) {
826 case _PREP_Motorola:
827 raven_init();
828 break;
829 case _PREP_IBM:
830 ibm_prep_init();
831 break;
832 }
833
834#ifdef CONFIG_VGA_CONSOLE
835 /* vgacon.c needs to know where we mapped IO memory in io_block_mapping() */
836 vgacon_remap_base = 0xf0000000;
837 conswitchp = &vga_con;
838#endif
839}
840
841/*
842 * First, see if we can get this information from the residual data.
843 * This is important on some IBM PReP systems. If we cannot, we let the
844 * TODC code handle doing this.
845 */
846static void __init
847prep_calibrate_decr(void)
848{
849 if (have_residual_data) {
850 unsigned long freq, divisor = 4;
851
852 if ( res->VitalProductData.ProcessorBusHz ) {
853 freq = res->VitalProductData.ProcessorBusHz;
854 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
855 (freq/divisor)/1000000,
856 (freq/divisor)%1000000);
857 tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
858 tb_ticks_per_jiffy = freq / HZ / divisor;
859 }
860 }
861 else
862 todc_calibrate_decr();
863}
864
865static void __init
866prep_init_IRQ(void)
867{
868 unsigned int pci_viddid, pci_did;
869
870 if (OpenPIC_Addr != NULL) {
871 openpic_init(NUM_8259_INTERRUPTS);
872 /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
873 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
874 i8259_irq);
875 }
876
877 if (have_residual_data) {
878 i8259_init(residual_isapic_addr(), 0);
879 return;
880 }
881
882 /* If we have a Raven PCI bridge or a Hawk PCI bridge / Memory
883 * controller, we poll (as they have a different int-ack address). */
884 early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &pci_viddid);
885 pci_did = (pci_viddid & 0xffff0000) >> 16;
886 if (((pci_viddid & 0xffff) == PCI_VENDOR_ID_MOTOROLA)
887 && ((pci_did == PCI_DEVICE_ID_MOTOROLA_RAVEN)
888 || (pci_did == PCI_DEVICE_ID_MOTOROLA_HAWK)))
889 i8259_init(0, 0);
890 else
891 /* PCI interrupt ack address given in section 6.1.8 of the
892 * PReP specification. */
893 i8259_init(MPC10X_MAPA_PCI_INTACK_ADDR, 0);
894}
895
896#ifdef CONFIG_SMP
897/* PReP (MTX) support */
898static int __init
899smp_prep_probe(void)
900{
901 extern int mot_multi;
902
903 if (mot_multi) {
904 openpic_request_IPIs();
905 smp_hw_index[1] = 1;
906 return 2;
907 }
908
909 return 1;
910}
911
912static void __init
913smp_prep_kick_cpu(int nr)
914{
915 *(unsigned long *)KERNELBASE = nr;
916 asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
917 printk("CPU1 released, waiting\n");
918}
919
920static void __init
921smp_prep_setup_cpu(int cpu_nr)
922{
923 if (OpenPIC_Addr)
924 do_openpic_setup_cpu();
925}
926
927static struct smp_ops_t prep_smp_ops = {
928 smp_openpic_message_pass,
929 smp_prep_probe,
930 smp_prep_kick_cpu,
931 smp_prep_setup_cpu,
932 .give_timebase = smp_generic_give_timebase,
933 .take_timebase = smp_generic_take_timebase,
934};
935#endif /* CONFIG_SMP */
936
937/*
938 * Setup the bat mappings we're going to load that cover
939 * the io areas. RAM was mapped by mapin_ram().
940 * -- Cort
941 */
942static void __init
943prep_map_io(void)
944{
945 io_block_mapping(0x80000000, PREP_ISA_IO_BASE, 0x10000000, _PAGE_IO);
946 io_block_mapping(0xf0000000, PREP_ISA_MEM_BASE, 0x08000000, _PAGE_IO);
947}
948
949static int __init
950prep_request_io(void)
951{
952#ifdef CONFIG_NVRAM
953 request_region(PREP_NVRAM_AS0, 0x8, "nvram");
954#endif
955 request_region(0x00,0x20,"dma1");
956 request_region(0x40,0x20,"timer");
957 request_region(0x80,0x10,"dma page reg");
958 request_region(0xc0,0x20,"dma2");
959
960 return 0;
961}
962
963device_initcall(prep_request_io);
964
965void __init
966prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
967 unsigned long r6, unsigned long r7)
968{
969#ifdef CONFIG_PREP_RESIDUAL
970 /* make a copy of residual data */
971 if ( r3 ) {
972 memcpy((void *)res,(void *)(r3+KERNELBASE),
973 sizeof(RESIDUAL));
974 }
975#endif
976
977 isa_io_base = PREP_ISA_IO_BASE;
978 isa_mem_base = PREP_ISA_MEM_BASE;
979 pci_dram_offset = PREP_PCI_DRAM_OFFSET;
980 ISA_DMA_THRESHOLD = 0x00ffffff;
981 DMA_MODE_READ = 0x44;
982 DMA_MODE_WRITE = 0x48;
983 ppc_do_canonicalize_irqs = 1;
984
985 /* figure out what kind of prep workstation we are */
986 if (have_residual_data) {
987 if ( !strncmp(res->VitalProductData.PrintableModel,"IBM",3) )
988 _prep_type = _PREP_IBM;
989 else
990 _prep_type = _PREP_Motorola;
991 }
992 else {
993 /* assume motorola if no residual (netboot?) */
994 _prep_type = _PREP_Motorola;
995 }
996
997#ifdef CONFIG_PREP_RESIDUAL
998 /* Switch off all residual data processing if the user requests it */
999 if (strstr(cmd_line, "noresidual") != NULL)
1000 res = NULL;
1001#endif
1002
1003 /* Initialise progress early to get maximum benefit */
1004 prep_set_bat();
1005 ibm_statusled_init();
1006
1007 ppc_md.setup_arch = prep_setup_arch;
1008 ppc_md.show_percpuinfo = prep_show_percpuinfo;
1009 ppc_md.show_cpuinfo = NULL; /* set in prep_setup_arch() */
1010 ppc_md.init_IRQ = prep_init_IRQ;
1011 /* this gets changed later on if we have an OpenPIC -- Cort */
1012 ppc_md.get_irq = i8259_irq;
1013
1014 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
1015
1016 ppc_md.restart = prep_restart;
1017 ppc_md.power_off = NULL; /* set in prep_setup_arch() */
1018 ppc_md.halt = prep_halt;
1019
1020 ppc_md.nvram_read_val = prep_nvram_read_val;
1021 ppc_md.nvram_write_val = prep_nvram_write_val;
1022
1023 ppc_md.time_init = todc_time_init;
1024 if (_prep_type == _PREP_IBM) {
1025 ppc_md.rtc_read_val = todc_mc146818_read_val;
1026 ppc_md.rtc_write_val = todc_mc146818_write_val;
1027 TODC_INIT(TODC_TYPE_MC146818, RTC_PORT(0), NULL, RTC_PORT(1),
1028 8);
1029 } else {
1030 TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
1031 PREP_NVRAM_DATA, 8);
1032 }
1033
1034 ppc_md.calibrate_decr = prep_calibrate_decr;
1035 ppc_md.set_rtc_time = todc_set_rtc_time;
1036 ppc_md.get_rtc_time = todc_get_rtc_time;
1037
1038 ppc_md.setup_io_mappings = prep_map_io;
1039
1040#ifdef CONFIG_SMP
1041 smp_ops = &prep_smp_ops;
1042#endif /* CONFIG_SMP */
1043}
diff --git a/arch/ppc/platforms/prpmc750.c b/arch/ppc/platforms/prpmc750.c
deleted file mode 100644
index 93bd593cf957..000000000000
--- a/arch/ppc/platforms/prpmc750.c
+++ /dev/null
@@ -1,360 +0,0 @@
1/*
2 * Board setup routines for Motorola PrPMC750
3 *
4 * Author: Matt Porter <mporter@mvista.com>
5 *
6 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/pci.h>
18#include <linux/kdev_t.h>
19#include <linux/types.h>
20#include <linux/major.h>
21#include <linux/initrd.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26#include <linux/slab.h>
27#include <linux/serial_reg.h>
28
29#include <asm/byteorder.h>
30#include <asm/system.h>
31#include <asm/pgtable.h>
32#include <asm/page.h>
33#include <asm/dma.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/machdep.h>
37#include <asm/pci-bridge.h>
38#include <asm/uaccess.h>
39#include <asm/time.h>
40#include <asm/open_pic.h>
41#include <asm/bootinfo.h>
42#include <asm/hawk.h>
43
44#include "prpmc750.h"
45
46extern unsigned long loops_per_jiffy;
47
48extern void gen550_progress(char *, unsigned short);
49
50static u_char prpmc750_openpic_initsenses[] __initdata =
51{
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HOSTINT0 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UART */
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_DEBUGINT */
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HAWK_WDT */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UNUSED */
57 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_ABORT */
58 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HOSTINT1 */
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HOSTINT2 */
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_HOSTINT3 */
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_PMC_INTA */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_PMC_INTB */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_PMC_INTC */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_PMC_INTD */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UNUSED */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UNUSED */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC750_INT_UNUSED */
68};
69
70/*
71 * Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
72 * Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22.
73 */
74static inline int
75prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
76{
77 static char pci_irq_table[][4] =
78 /*
79 * PCI IDSEL/INTPIN->INTLINE
80 * A B C D
81 */
82 {
83 {12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
84 {0, 0, 0, 0}, /* IDSEL 15 - unused */
85 {10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */
86 {10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */
87 {11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
88 {0, 0, 0, 0}, /* IDSEL 19 - unused */
89 {9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */
90 {11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */
91 {12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */
92 };
93 const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
94 return PCI_IRQ_TABLE_LOOKUP;
95};
96
97static void __init prpmc750_pcibios_fixup(void)
98{
99 struct pci_dev *dev;
100 unsigned short wtmp;
101
102 /*
103 * Kludge to clean up after PPC6BUG which doesn't
104 * configure the CL5446 VGA card. Also the
105 * resource subsystem doesn't fixup the
106 * PCI mem resources on the CL5446.
107 */
108 if ((dev = pci_get_device(PCI_VENDOR_ID_CIRRUS,
109 PCI_DEVICE_ID_CIRRUS_5446, 0))) {
110 dev->resource[0].start += PRPMC750_PCI_PHY_MEM_OFFSET;
111 dev->resource[0].end += PRPMC750_PCI_PHY_MEM_OFFSET;
112 pci_read_config_word(dev, PCI_COMMAND, &wtmp);
113 pci_write_config_word(dev, PCI_COMMAND, wtmp | 3);
114 /* Enable Color mode in MISC reg */
115 outb(0x03, 0x3c2);
116 /* Select DRAM config reg */
117 outb(0x0f, 0x3c4);
118 /* Set proper DRAM config */
119 outb(0xdf, 0x3c5);
120 pci_dev_put(dev);
121 }
122}
123
124void __init prpmc750_find_bridges(void)
125{
126 struct pci_controller *hose;
127
128 hose = pcibios_alloc_controller();
129 if (!hose)
130 return;
131
132 hose->first_busno = 0;
133 hose->last_busno = 0xff;
134 hose->io_base_virt = (void *)PRPMC750_ISA_IO_BASE;
135 hose->pci_mem_offset = PRPMC750_PCI_PHY_MEM_OFFSET;
136
137 pci_init_resource(&hose->io_resource,
138 PRPMC750_PCI_IO_START,
139 PRPMC750_PCI_IO_END,
140 IORESOURCE_IO, "PCI host bridge");
141
142 pci_init_resource(&hose->mem_resources[0],
143 PRPMC750_PROC_PCI_MEM_START,
144 PRPMC750_PROC_PCI_MEM_END,
145 IORESOURCE_MEM, "PCI host bridge");
146
147 hose->io_space.start = PRPMC750_PCI_IO_START;
148 hose->io_space.end = PRPMC750_PCI_IO_END;
149 hose->mem_space.start = PRPMC750_PCI_MEM_START;
150 hose->mem_space.end = PRPMC750_PCI_MEM_END - HAWK_MPIC_SIZE;
151
152 if (hawk_init(hose, PRPMC750_HAWK_PPC_REG_BASE,
153 PRPMC750_PROC_PCI_MEM_START,
154 PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
155 PRPMC750_PROC_PCI_IO_START, PRPMC750_PROC_PCI_IO_END,
156 PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
157 != 0) {
158 printk(KERN_CRIT "Could not initialize host bridge\n");
159 }
160
161 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
162
163 ppc_md.pcibios_fixup = prpmc750_pcibios_fixup;
164 ppc_md.pci_swizzle = common_swizzle;
165 ppc_md.pci_map_irq = prpmc_map_irq;
166}
167static int prpmc750_show_cpuinfo(struct seq_file *m)
168{
169 seq_printf(m, "machine\t\t: PrPMC750\n");
170
171 return 0;
172}
173
174static void __init prpmc750_setup_arch(void)
175{
176 /* init to some ~sane value until calibrate_delay() runs */
177 loops_per_jiffy = 50000000 / HZ;
178
179 /* Lookup PCI host bridges */
180 prpmc750_find_bridges();
181
182#ifdef CONFIG_BLK_DEV_INITRD
183 if (initrd_start)
184 ROOT_DEV = Root_RAM0;
185 else
186#endif
187#ifdef CONFIG_ROOT_NFS
188 ROOT_DEV = Root_NFS;
189#else
190 ROOT_DEV = Root_SDA2;
191#endif
192
193 OpenPIC_InitSenses = prpmc750_openpic_initsenses;
194 OpenPIC_NumInitSenses = sizeof(prpmc750_openpic_initsenses);
195
196 printk(KERN_INFO "Port by MontaVista Software, Inc. "
197 "(source@mvista.com)\n");
198}
199
200/*
201 * Compute the PrPMC750's bus speed using the baud clock as a
202 * reference.
203 */
204static unsigned long __init prpmc750_get_bus_speed(void)
205{
206 unsigned long tbl_start, tbl_end;
207 unsigned long current_state, old_state, bus_speed;
208 unsigned char lcr, dll, dlm;
209 int baud_divisor, count;
210
211 /* Read the UART's baud clock divisor */
212 lcr = readb(PRPMC750_SERIAL_0_LCR);
213 writeb(lcr | UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
214 dll = readb(PRPMC750_SERIAL_0_DLL);
215 dlm = readb(PRPMC750_SERIAL_0_DLM);
216 writeb(lcr & ~UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
217 baud_divisor = (dlm << 8) | dll;
218
219 /*
220 * Use the baud clock divisor and base baud clock
221 * to determine the baud rate and use that as
222 * the number of baud clock edges we use for
223 * the time base sample. Make it half the baud
224 * rate.
225 */
226 count = PRPMC750_BASE_BAUD / (baud_divisor * 16);
227
228 /* Find the first edge of the baud clock */
229 old_state = readb(PRPMC750_STATUS_REG) & PRPMC750_BAUDOUT_MASK;
230 do {
231 current_state = readb(PRPMC750_STATUS_REG) &
232 PRPMC750_BAUDOUT_MASK;
233 } while (old_state == current_state);
234
235 old_state = current_state;
236
237 /* Get the starting time base value */
238 tbl_start = get_tbl();
239
240 /*
241 * Loop until we have found a number of edges equal
242 * to half the count (half the baud rate)
243 */
244 do {
245 do {
246 current_state = readb(PRPMC750_STATUS_REG) &
247 PRPMC750_BAUDOUT_MASK;
248 } while (old_state == current_state);
249 old_state = current_state;
250 } while (--count);
251
252 /* Get the ending time base value */
253 tbl_end = get_tbl();
254
255 /* Compute bus speed */
256 bus_speed = (tbl_end - tbl_start) * 128;
257
258 return bus_speed;
259}
260
261static void __init prpmc750_calibrate_decr(void)
262{
263 unsigned long freq;
264 int divisor = 4;
265
266 freq = prpmc750_get_bus_speed();
267
268 tb_ticks_per_jiffy = freq / (HZ * divisor);
269 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
270}
271
272static void prpmc750_restart(char *cmd)
273{
274 local_irq_disable();
275 writeb(PRPMC750_MODRST_MASK, PRPMC750_MODRST_REG);
276 while (1) ;
277}
278
279static void prpmc750_halt(void)
280{
281 local_irq_disable();
282 while (1) ;
283}
284
285static void prpmc750_power_off(void)
286{
287 prpmc750_halt();
288}
289
290static void __init prpmc750_init_IRQ(void)
291{
292 openpic_init(0);
293}
294
295/*
296 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
297 */
298static __inline__ void prpmc750_set_bat(void)
299{
300 mb();
301 mtspr(SPRN_DBAT1U, 0xf0001ffe);
302 mtspr(SPRN_DBAT1L, 0xf000002a);
303 mb();
304}
305
306/*
307 * We need to read the Falcon/Hawk memory controller
308 * to properly determine this value
309 */
310static unsigned long __init prpmc750_find_end_of_memory(void)
311{
312 /* Read the memory size from the Hawk SMC */
313 return hawk_get_mem_size(PRPMC750_HAWK_SMC_BASE);
314}
315
316static void __init prpmc750_map_io(void)
317{
318 io_block_mapping(PRPMC750_ISA_IO_BASE, PRPMC750_ISA_IO_BASE,
319 0x10000000, _PAGE_IO);
320#if 0
321 io_block_mapping(0xf0000000, 0xc0000000, 0x08000000, _PAGE_IO);
322#endif
323 io_block_mapping(0xf8000000, 0xf8000000, 0x08000000, _PAGE_IO);
324}
325
326void __init
327platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
328 unsigned long r6, unsigned long r7)
329{
330 parse_bootinfo(find_bootinfo());
331
332 /* Cover the Hawk registers with a BAT */
333 prpmc750_set_bat();
334
335 isa_io_base = PRPMC750_ISA_IO_BASE;
336 isa_mem_base = PRPMC750_ISA_MEM_BASE;
337 pci_dram_offset = PRPMC750_PCI_DRAM_OFFSET;
338
339 ppc_md.setup_arch = prpmc750_setup_arch;
340 ppc_md.show_cpuinfo = prpmc750_show_cpuinfo;
341 ppc_md.init_IRQ = prpmc750_init_IRQ;
342 ppc_md.get_irq = openpic_get_irq;
343
344 ppc_md.find_end_of_memory = prpmc750_find_end_of_memory;
345 ppc_md.setup_io_mappings = prpmc750_map_io;
346
347 ppc_md.restart = prpmc750_restart;
348 ppc_md.power_off = prpmc750_power_off;
349 ppc_md.halt = prpmc750_halt;
350
351 /* PrPMC750 has no timekeeper part */
352 ppc_md.time_init = NULL;
353 ppc_md.get_rtc_time = NULL;
354 ppc_md.set_rtc_time = NULL;
355 ppc_md.calibrate_decr = prpmc750_calibrate_decr;
356
357#ifdef CONFIG_SERIAL_TEXT_DEBUG
358 ppc_md.progress = gen550_progress;
359#endif /* CONFIG_SERIAL_TEXT_DEBUG */
360}
diff --git a/arch/ppc/platforms/prpmc750.h b/arch/ppc/platforms/prpmc750.h
deleted file mode 100644
index c4dcff09d7ca..000000000000
--- a/arch/ppc/platforms/prpmc750.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * arch/ppc/platforms/prpmc750.h
3 *
4 * Definitions for Motorola PrPMC750 board support
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_PRPMC750_H__
16#define __ASM_PRPMC750_H__
17
18/*
19 * Due to limitations imposed by legacy hardware (primarily IDE controllers),
20 * the PrPMC750 carrier board operates using a PReP address map.
21 *
22 * From Processor (physical) -> PCI:
23 * PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
24 * PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
25 * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
26 *
27 * From PCI -> Processor (physical):
28 * System Memory: 0x80000000 -> 0x00000000
29 */
30
31#define PRPMC750_ISA_IO_BASE PREP_ISA_IO_BASE
32#define PRPMC750_ISA_MEM_BASE PREP_ISA_MEM_BASE
33
34/* PCI Memory space mapping info */
35#define PRPMC750_PCI_MEM_SIZE 0x30000000U
36#define PRPMC750_PROC_PCI_MEM_START PRPMC750_ISA_MEM_BASE
37#define PRPMC750_PROC_PCI_MEM_END (PRPMC750_PROC_PCI_MEM_START + \
38 PRPMC750_PCI_MEM_SIZE - 1)
39#define PRPMC750_PCI_MEM_START 0x00000000U
40#define PRPMC750_PCI_MEM_END (PRPMC750_PCI_MEM_START + \
41 PRPMC750_PCI_MEM_SIZE - 1)
42
43/* PCI I/O space mapping info */
44#define PRPMC750_PCI_IO_SIZE 0x10000000U
45#define PRPMC750_PROC_PCI_IO_START PRPMC750_ISA_IO_BASE
46#define PRPMC750_PROC_PCI_IO_END (PRPMC750_PROC_PCI_IO_START + \
47 PRPMC750_PCI_IO_SIZE - 1)
48#define PRPMC750_PCI_IO_START 0x00000000U
49#define PRPMC750_PCI_IO_END (PRPMC750_PCI_IO_START + \
50 PRPMC750_PCI_IO_SIZE - 1)
51
52/* System memory mapping info */
53#define PRPMC750_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
54#define PRPMC750_PCI_PHY_MEM_OFFSET (PRPMC750_ISA_MEM_BASE-PRPMC750_PCI_MEM_START)
55
56/* Register address definitions */
57#define PRPMC750_HAWK_SMC_BASE 0xfef80000U
58#define PRPMC750_HAWK_PPC_REG_BASE 0xfeff0000U
59
60#define PRPMC750_BASE_BAUD 1843200
61#define PRPMC750_SERIAL_0 0xfef88000
62#define PRPMC750_SERIAL_0_DLL (PRPMC750_SERIAL_0 + (UART_DLL << 4))
63#define PRPMC750_SERIAL_0_DLM (PRPMC750_SERIAL_0 + (UART_DLM << 4))
64#define PRPMC750_SERIAL_0_LCR (PRPMC750_SERIAL_0 + (UART_LCR << 4))
65
66#define PRPMC750_STATUS_REG 0xfef88080
67#define PRPMC750_BAUDOUT_MASK 0x02
68#define PRPMC750_MONARCH_MASK 0x01
69
70#define PRPMC750_MODRST_REG 0xfef880a0
71#define PRPMC750_MODRST_MASK 0x01
72
73#define PRPMC750_PIRQ_REG 0xfef880b0
74#define PRPMC750_SEL1_MASK 0x02
75#define PRPMC750_SEL0_MASK 0x01
76
77#define PRPMC750_TBEN_REG 0xfef880c0
78#define PRPMC750_TBEN_MASK 0x01
79
80/* UART Defines. */
81#define RS_TABLE_SIZE 4
82
83/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
84#define BASE_BAUD (PRPMC750_BASE_BAUD / 16)
85
86#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
87
88#define SERIAL_PORT_DFNS \
89 { 0, BASE_BAUD, PRPMC750_SERIAL_0, 1, STD_COM_FLAGS, \
90 iomem_base: (unsigned char *)PRPMC750_SERIAL_0, \
91 iomem_reg_shift: 4, \
92 io_type: SERIAL_IO_MEM } /* ttyS0 */
93
94#endif /* __ASM_PRPMC750_H__ */
95#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/prpmc800.c b/arch/ppc/platforms/prpmc800.c
deleted file mode 100644
index 5bcda7f92cd0..000000000000
--- a/arch/ppc/platforms/prpmc800.c
+++ /dev/null
@@ -1,472 +0,0 @@
1/*
2 * Author: Dale Farnsworth <dale.farnsworth@mvista.com>
3 *
4 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
5 * the terms of the GNU General Public License version 2. This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/stddef.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/errno.h>
14#include <linux/reboot.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/types.h>
18#include <linux/major.h>
19#include <linux/initrd.h>
20#include <linux/console.h>
21#include <linux/delay.h>
22#include <linux/seq_file.h>
23#include <linux/root_dev.h>
24#include <linux/harrier_defs.h>
25
26#include <asm/byteorder.h>
27#include <asm/system.h>
28#include <asm/pgtable.h>
29#include <asm/page.h>
30#include <asm/dma.h>
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/machdep.h>
34#include <asm/time.h>
35#include <asm/pci-bridge.h>
36#include <asm/open_pic.h>
37#include <asm/bootinfo.h>
38#include <asm/harrier.h>
39
40#include "prpmc800.h"
41
42#define HARRIER_REVI_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_REVI_OFF)
43#define HARRIER_UCTL_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_UCTL_OFF)
44#define HARRIER_MISC_CSR_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_MISC_CSR_OFF)
45#define HARRIER_IFEVP_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEVP_OFF)
46#define HARRIER_IFEDE_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEDE_OFF)
47#define HARRIER_FEEN_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEEN_OFF)
48#define HARRIER_FEMA_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEMA_OFF)
49
50#define HARRIER_VENI_REG (PRPMC800_HARRIER_XCSR_BASE + HARRIER_VENI_OFF)
51#define HARRIER_MISC_CSR (PRPMC800_HARRIER_XCSR_BASE + \
52 HARRIER_MISC_CSR_OFF)
53
54#define MONARCH (monarch != 0)
55#define NON_MONARCH (monarch == 0)
56
57extern int mpic_init(void);
58extern unsigned long loops_per_jiffy;
59extern void gen550_progress(char *, unsigned short);
60
61static int monarch = 0;
62static int found_self = 0;
63static int self = 0;
64
65static u_char prpmc800_openpic_initsenses[] __initdata =
66{
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT0 */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_DEBUGINT */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HARRIER_WDT */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT1 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT2 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT3 */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTA */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTB */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTC */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTD */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HARRIER_INT (UARTS, ABORT, DMA) */
84};
85
86/*
87 * Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
88 * Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22.
89 */
90static inline int
91prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
92{
93 static char pci_irq_table[][4] =
94 /*
95 * PCI IDSEL/INTPIN->INTLINE
96 * A B C D
97 */
98 {
99 {12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
100 {0, 0, 0, 0}, /* IDSEL 15 - unused */
101 {10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */
102 {10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */
103 {11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
104 {0, 0, 0, 0}, /* IDSEL 19 - unused */
105 {9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */
106 {11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */
107 {12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */
108 };
109 const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
110 return PCI_IRQ_TABLE_LOOKUP;
111};
112
113static int
114prpmc_read_config_dword(struct pci_controller *hose, u8 bus, u8 devfn,
115 int offset, u32 * val)
116{
117 /* paranoia */
118 if ((hose == NULL) ||
119 (hose->cfg_addr == NULL) || (hose->cfg_data == NULL))
120 return PCIBIOS_DEVICE_NOT_FOUND;
121
122 out_be32(hose->cfg_addr, ((offset & 0xfc) << 24) | (devfn << 16)
123 | ((bus - hose->bus_offset) << 8) | 0x80);
124 *val = in_le32((u32 *) (hose->cfg_data + (offset & 3)));
125
126 return PCIBIOS_SUCCESSFUL;
127}
128
129#define HARRIER_PCI_VEND_DEV_ID (PCI_VENDOR_ID_MOTOROLA | \
130 (PCI_DEVICE_ID_MOTOROLA_HARRIER << 16))
131static int prpmc_self(u8 bus, u8 devfn)
132{
133 /*
134 * Harriers always view themselves as being on bus 0. If we're not
135 * looking at bus 0, we're not going to find ourselves.
136 */
137 if (bus != 0)
138 return PCIBIOS_DEVICE_NOT_FOUND;
139 else {
140 int result;
141 int val;
142 struct pci_controller *hose;
143
144 hose = pci_bus_to_hose(bus);
145
146 /* See if target device is a Harrier */
147 result = prpmc_read_config_dword(hose, bus, devfn,
148 PCI_VENDOR_ID, &val);
149 if ((result != PCIBIOS_SUCCESSFUL) ||
150 (val != HARRIER_PCI_VEND_DEV_ID))
151 return PCIBIOS_DEVICE_NOT_FOUND;
152
153 /*
154 * LBA bit is set if target Harrier == initiating Harrier
155 * (i.e. if we are reading our own PCI header).
156 */
157 result = prpmc_read_config_dword(hose, bus, devfn,
158 HARRIER_LBA_OFF, &val);
159 if ((result != PCIBIOS_SUCCESSFUL) ||
160 ((val & HARRIER_LBA_MSK) != HARRIER_LBA_MSK))
161 return PCIBIOS_DEVICE_NOT_FOUND;
162
163 /* It's us, save our location for later */
164 self = devfn;
165 found_self = 1;
166 return PCIBIOS_SUCCESSFUL;
167 }
168}
169
170static int prpmc_exclude_device(u8 bus, u8 devfn)
171{
172 /*
173 * Monarch is allowed to access all PCI devices. Non-monarch is
174 * only allowed to access its own Harrier.
175 */
176
177 if (MONARCH)
178 return PCIBIOS_SUCCESSFUL;
179 if (found_self)
180 if ((bus == 0) && (devfn == self))
181 return PCIBIOS_SUCCESSFUL;
182 else
183 return PCIBIOS_DEVICE_NOT_FOUND;
184 else
185 return prpmc_self(bus, devfn);
186}
187
188void __init prpmc800_find_bridges(void)
189{
190 struct pci_controller *hose;
191 int host_bridge;
192
193 hose = pcibios_alloc_controller();
194 if (!hose)
195 return;
196
197 hose->first_busno = 0;
198 hose->last_busno = 0xff;
199
200 ppc_md.pci_exclude_device = prpmc_exclude_device;
201 ppc_md.pcibios_fixup = NULL;
202 ppc_md.pcibios_fixup_bus = NULL;
203 ppc_md.pci_swizzle = common_swizzle;
204 ppc_md.pci_map_irq = prpmc_map_irq;
205
206 setup_indirect_pci(hose,
207 PRPMC800_PCI_CONFIG_ADDR, PRPMC800_PCI_CONFIG_DATA);
208
209 /* Get host bridge vendor/dev id */
210
211 host_bridge = in_be32((uint *) (HARRIER_VENI_REG));
212
213 if (host_bridge != HARRIER_VEND_DEV_ID) {
214 printk(KERN_CRIT "Host bridge 0x%x not supported\n",
215 host_bridge);
216 return;
217 }
218
219 monarch = in_be32((uint *) HARRIER_MISC_CSR) & HARRIER_SYSCON;
220
221 printk(KERN_INFO "Running as %s.\n",
222 MONARCH ? "Monarch" : "Non-Monarch");
223
224 hose->io_space.start = PRPMC800_PCI_IO_START;
225 hose->io_space.end = PRPMC800_PCI_IO_END;
226 hose->io_base_virt = (void *)PRPMC800_ISA_IO_BASE;
227 hose->pci_mem_offset = PRPMC800_PCI_PHY_MEM_OFFSET;
228
229 pci_init_resource(&hose->io_resource,
230 PRPMC800_PCI_IO_START, PRPMC800_PCI_IO_END,
231 IORESOURCE_IO, "PCI host bridge");
232
233 if (MONARCH) {
234 hose->mem_space.start = PRPMC800_PCI_MEM_START;
235 hose->mem_space.end = PRPMC800_PCI_MEM_END;
236
237 pci_init_resource(&hose->mem_resources[0],
238 PRPMC800_PCI_MEM_START,
239 PRPMC800_PCI_MEM_END,
240 IORESOURCE_MEM, "PCI host bridge");
241
242 if (harrier_init(hose,
243 PRPMC800_HARRIER_XCSR_BASE,
244 PRPMC800_PROC_PCI_MEM_START,
245 PRPMC800_PROC_PCI_MEM_END,
246 PRPMC800_PROC_PCI_IO_START,
247 PRPMC800_PROC_PCI_IO_END,
248 PRPMC800_HARRIER_MPIC_BASE) != 0)
249 printk(KERN_CRIT "Could not initialize HARRIER "
250 "bridge\n");
251
252 harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE);
253 harrier_wait_eready(PRPMC800_HARRIER_XCSR_BASE);
254 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
255
256 } else {
257 pci_init_resource(&hose->mem_resources[0],
258 PRPMC800_NM_PCI_MEM_START,
259 PRPMC800_NM_PCI_MEM_END,
260 IORESOURCE_MEM, "PCI host bridge");
261
262 hose->mem_space.start = PRPMC800_NM_PCI_MEM_START;
263 hose->mem_space.end = PRPMC800_NM_PCI_MEM_END;
264
265 if (harrier_init(hose,
266 PRPMC800_HARRIER_XCSR_BASE,
267 PRPMC800_NM_PROC_PCI_MEM_START,
268 PRPMC800_NM_PROC_PCI_MEM_END,
269 PRPMC800_PROC_PCI_IO_START,
270 PRPMC800_PROC_PCI_IO_END,
271 PRPMC800_HARRIER_MPIC_BASE) != 0)
272 printk(KERN_CRIT "Could not initialize HARRIER "
273 "bridge\n");
274
275 harrier_setup_nonmonarch(PRPMC800_HARRIER_XCSR_BASE,
276 HARRIER_ITSZ_1MB);
277 harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE);
278 }
279}
280
281static int prpmc800_show_cpuinfo(struct seq_file *m)
282{
283 seq_printf(m, "machine\t\t: PrPMC800\n");
284
285 return 0;
286}
287
288static void __init prpmc800_setup_arch(void)
289{
290 /* init to some ~sane value until calibrate_delay() runs */
291 loops_per_jiffy = 50000000 / HZ;
292
293 /* Lookup PCI host bridges */
294 prpmc800_find_bridges();
295
296#ifdef CONFIG_BLK_DEV_INITRD
297 if (initrd_start)
298 ROOT_DEV = Root_RAM0;
299 else
300#endif
301#ifdef CONFIG_ROOT_NFS
302 ROOT_DEV = Root_NFS;
303#else
304 ROOT_DEV = Root_SDA2;
305#endif
306
307 printk(KERN_INFO "Port by MontaVista Software, Inc. "
308 "(source@mvista.com)\n");
309}
310
311/*
312 * Compute the PrPMC800's tbl frequency using the baud clock as a reference.
313 */
314static void __init prpmc800_calibrate_decr(void)
315{
316 unsigned long tbl_start, tbl_end;
317 unsigned long current_state, old_state, tb_ticks_per_second;
318 unsigned int count;
319 unsigned int harrier_revision;
320
321 harrier_revision = readb(HARRIER_REVI_REG);
322 if (harrier_revision < 2) {
323 /* XTAL64 was broken in harrier revision 1 */
324 printk(KERN_INFO "time_init: Harrier revision %d, assuming "
325 "100 Mhz bus\n", harrier_revision);
326 tb_ticks_per_second = 100000000 / 4;
327 tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
328 tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
329 return;
330 }
331
332 /*
333 * The XTAL64 bit oscillates at the 1/64 the base baud clock
334 * Set count to XTAL64 cycles per second. Since we'll count
335 * half-cycles, we'll reach the count in half a second.
336 */
337 count = PRPMC800_BASE_BAUD / 64;
338
339 /* Find the first edge of the baud clock */
340 old_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
341 do {
342 current_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
343 } while (old_state == current_state);
344
345 old_state = current_state;
346
347 /* Get the starting time base value */
348 tbl_start = get_tbl();
349
350 /*
351 * Loop until we have found a number of edges (half-cycles)
352 * equal to the count (half a second)
353 */
354 do {
355 do {
356 current_state = readb(HARRIER_UCTL_REG) &
357 HARRIER_XTAL64_MASK;
358 } while (old_state == current_state);
359 old_state = current_state;
360 } while (--count);
361
362 /* Get the ending time base value */
363 tbl_end = get_tbl();
364
365 /* We only counted for half a second, so double to get ticks/second */
366 tb_ticks_per_second = (tbl_end - tbl_start) * 2;
367 tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
368 tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
369}
370
371static void prpmc800_restart(char *cmd)
372{
373 ulong temp;
374
375 local_irq_disable();
376 temp = in_be32((uint *) HARRIER_MISC_CSR_REG);
377 temp |= HARRIER_RSTOUT;
378 out_be32((uint *) HARRIER_MISC_CSR_REG, temp);
379 while (1) ;
380}
381
382static void prpmc800_halt(void)
383{
384 local_irq_disable();
385 while (1) ;
386}
387
388static void prpmc800_power_off(void)
389{
390 prpmc800_halt();
391}
392
393static void __init prpmc800_init_IRQ(void)
394{
395 OpenPIC_InitSenses = prpmc800_openpic_initsenses;
396 OpenPIC_NumInitSenses = sizeof(prpmc800_openpic_initsenses);
397
398 /* Setup external interrupt sources. */
399 openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
400 /* Setup internal UART interrupt source. */
401 openpic_set_sources(16, 1, OpenPIC_Addr + 0x10200);
402
403 /* Do the MPIC initialization based on the above settings. */
404 openpic_init(0);
405
406 /* enable functional exceptions for uarts and abort */
407 out_8((u8 *) HARRIER_FEEN_REG, (HARRIER_FE_UA0 | HARRIER_FE_UA1));
408 out_8((u8 *) HARRIER_FEMA_REG, ~(HARRIER_FE_UA0 | HARRIER_FE_UA1));
409}
410
411/*
412 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
413 */
414static __inline__ void prpmc800_set_bat(void)
415{
416 mb();
417 mtspr(SPRN_DBAT1U, 0xf0001ffe);
418 mtspr(SPRN_DBAT1L, 0xf000002a);
419 mb();
420}
421
422/*
423 * We need to read the Harrier memory controller
424 * to properly determine this value
425 */
426static unsigned long __init prpmc800_find_end_of_memory(void)
427{
428 /* Read the memory size from the Harrier XCSR */
429 return harrier_get_mem_size(PRPMC800_HARRIER_XCSR_BASE);
430}
431
432static void __init prpmc800_map_io(void)
433{
434 io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
435 io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
436}
437
438void __init
439platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
440 unsigned long r6, unsigned long r7)
441{
442 parse_bootinfo(find_bootinfo());
443
444 prpmc800_set_bat();
445
446 isa_io_base = PRPMC800_ISA_IO_BASE;
447 isa_mem_base = PRPMC800_ISA_MEM_BASE;
448 pci_dram_offset = PRPMC800_PCI_DRAM_OFFSET;
449
450 ppc_md.setup_arch = prpmc800_setup_arch;
451 ppc_md.show_cpuinfo = prpmc800_show_cpuinfo;
452 ppc_md.init_IRQ = prpmc800_init_IRQ;
453 ppc_md.get_irq = openpic_get_irq;
454
455 ppc_md.find_end_of_memory = prpmc800_find_end_of_memory;
456 ppc_md.setup_io_mappings = prpmc800_map_io;
457
458 ppc_md.restart = prpmc800_restart;
459 ppc_md.power_off = prpmc800_power_off;
460 ppc_md.halt = prpmc800_halt;
461
462 /* PrPMC800 has no timekeeper part */
463 ppc_md.time_init = NULL;
464 ppc_md.get_rtc_time = NULL;
465 ppc_md.set_rtc_time = NULL;
466 ppc_md.calibrate_decr = prpmc800_calibrate_decr;
467#ifdef CONFIG_SERIAL_TEXT_DEBUG
468 ppc_md.progress = gen550_progress;
469#else /* !CONFIG_SERIAL_TEXT_DEBUG */
470 ppc_md.progress = NULL;
471#endif /* CONFIG_SERIAL_TEXT_DEBUG */
472}
diff --git a/arch/ppc/platforms/prpmc800.h b/arch/ppc/platforms/prpmc800.h
deleted file mode 100644
index 26f604e05cfa..000000000000
--- a/arch/ppc/platforms/prpmc800.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * arch/ppc/platforms/prpmc800.h
3 *
4 * Definitions for Motorola PrPMC800 board support
5 *
6 * Author: Dale Farnsworth <dale.farnsworth@mvista.com>
7 *
8 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13 /*
14 * From Processor to PCI:
15 * PCI Mem Space: 0x80000000 - 0xa0000000 -> 0x80000000 - 0xa0000000 (512 MB)
16 * PCI I/O Space: 0xfe400000 - 0xfeef0000 -> 0x00000000 - 0x00b00000 (11 MB)
17 * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
18 *
19 * From PCI to Processor:
20 * System Memory: 0x00000000 -> 0x00000000
21 */
22
23#ifndef __ASMPPC_PRPMC800_H
24#define __ASMPPC_PRPMC800_H
25
26#define PRPMC800_PCI_CONFIG_ADDR 0xfe000cf8
27#define PRPMC800_PCI_CONFIG_DATA 0xfe000cfc
28
29#define PRPMC800_PROC_PCI_IO_START 0xfe400000U
30#define PRPMC800_PROC_PCI_IO_END 0xfeefffffU
31#define PRPMC800_PCI_IO_START 0x00000000U
32#define PRPMC800_PCI_IO_END 0x00afffffU
33
34#define PRPMC800_PROC_PCI_MEM_START 0x80000000U
35#define PRPMC800_PROC_PCI_MEM_END 0x9fffffffU
36#define PRPMC800_PCI_MEM_START 0x80000000U
37#define PRPMC800_PCI_MEM_END 0x9fffffffU
38
39#define PRPMC800_NM_PROC_PCI_MEM_START 0x40000000U
40#define PRPMC800_NM_PROC_PCI_MEM_END 0xdfffffffU
41#define PRPMC800_NM_PCI_MEM_START 0x40000000U
42#define PRPMC800_NM_PCI_MEM_END 0xdfffffffU
43
44#define PRPMC800_PCI_DRAM_OFFSET 0x00000000U
45#define PRPMC800_PCI_PHY_MEM_OFFSET 0x00000000U
46
47#define PRPMC800_ISA_IO_BASE PRPMC800_PROC_PCI_IO_START
48#define PRPMC800_ISA_MEM_BASE 0x00000000U
49
50#define PRPMC800_HARRIER_XCSR_BASE HARRIER_DEFAULT_XCSR_BASE
51#define PRPMC800_HARRIER_MPIC_BASE 0xff000000
52
53#define PRPMC800_SERIAL_1 0xfeff00c0
54
55#define PRPMC800_BASE_BAUD 1843200
56
57/*
58 * interrupt vector number and priority for harrier internal interrupt
59 * sources
60 */
61#define PRPMC800_INT_IRQ 16
62#define PRPMC800_INT_PRI 15
63
64/* UART Defines. */
65#define RS_TABLE_SIZE 4
66
67/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
68#define BASE_BAUD (PRPMC800_BASE_BAUD / 16)
69
70#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
71
72/* UARTS are at IRQ 16 */
73#define STD_SERIAL_PORT_DFNS \
74 { 0, BASE_BAUD, PRPMC800_SERIAL_1, 16, STD_COM_FLAGS, /* ttyS0 */\
75 iomem_base: (unsigned char *)PRPMC800_SERIAL_1, \
76 iomem_reg_shift: 0, \
77 io_type: SERIAL_IO_MEM },
78
79#define SERIAL_PORT_DFNS \
80 STD_SERIAL_PORT_DFNS
81
82#endif /* __ASMPPC_PRPMC800_H */
diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c
deleted file mode 100644
index f1dee1e87809..000000000000
--- a/arch/ppc/platforms/radstone_ppc7d.c
+++ /dev/null
@@ -1,1492 +0,0 @@
1/*
2 * Board setup routines for the Radstone PPC7D boards.
3 *
4 * Author: James Chapman <jchapman@katalix.com>
5 *
6 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
7 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs,
16 * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse,
17 * 4 serial ports, 2 high speed serial ports (MPSCs) and optional
18 * SCSI / VGA.
19 */
20
21#include <linux/stddef.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/errno.h>
25#include <linux/reboot.h>
26#include <linux/pci.h>
27#include <linux/kdev_t.h>
28#include <linux/major.h>
29#include <linux/initrd.h>
30#include <linux/console.h>
31#include <linux/delay.h>
32#include <linux/seq_file.h>
33#include <linux/root_dev.h>
34#include <linux/serial.h>
35#include <linux/tty.h> /* for linux/serial_core.h */
36#include <linux/serial_core.h>
37#include <linux/serial_8250.h>
38#include <linux/mv643xx.h>
39#include <linux/netdevice.h>
40#include <linux/platform_device.h>
41
42#include <asm/system.h>
43#include <asm/pgtable.h>
44#include <asm/page.h>
45#include <asm/time.h>
46#include <asm/dma.h>
47#include <asm/io.h>
48#include <asm/machdep.h>
49#include <asm/prom.h>
50#include <asm/smp.h>
51#include <asm/vga.h>
52#include <asm/open_pic.h>
53#include <asm/i8259.h>
54#include <asm/todc.h>
55#include <asm/bootinfo.h>
56#include <asm/mpc10x.h>
57#include <asm/pci-bridge.h>
58#include <asm/mv64x60.h>
59
60#include "radstone_ppc7d.h"
61
62#undef DEBUG
63
64#define PPC7D_RST_PIN 17 /* GPP17 */
65
66extern u32 mv64360_irq_base;
67extern spinlock_t rtc_lock;
68
69static struct mv64x60_handle bh;
70static int ppc7d_has_alma;
71
72extern void gen550_progress(char *, unsigned short);
73extern void gen550_init(int, struct uart_port *);
74
75/* FIXME - move to h file */
76extern int ds1337_do_command(int id, int cmd, void *arg);
77#define DS1337_GET_DATE 0
78#define DS1337_SET_DATE 1
79
80/* residual data */
81unsigned char __res[sizeof(bd_t)];
82
83/*****************************************************************************
84 * Serial port code
85 *****************************************************************************/
86
87#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
88static void __init ppc7d_early_serial_map(void)
89{
90#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
91 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
92#elif defined(CONFIG_SERIAL_8250)
93 struct uart_port serial_req;
94
95 /* Setup serial port access */
96 memset(&serial_req, 0, sizeof(serial_req));
97 serial_req.uartclk = UART_CLK;
98 serial_req.irq = 4;
99 serial_req.flags = STD_COM_FLAGS;
100 serial_req.iotype = UPIO_MEM;
101 serial_req.membase = (u_char *) PPC7D_SERIAL_0;
102
103 gen550_init(0, &serial_req);
104 if (early_serial_setup(&serial_req) != 0)
105 printk(KERN_ERR "Early serial init of port 0 failed\n");
106
107 /* Assume early_serial_setup() doesn't modify serial_req */
108 serial_req.line = 1;
109 serial_req.irq = 3;
110 serial_req.membase = (u_char *) PPC7D_SERIAL_1;
111
112 gen550_init(1, &serial_req);
113 if (early_serial_setup(&serial_req) != 0)
114 printk(KERN_ERR "Early serial init of port 1 failed\n");
115#else
116#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
117#endif
118}
119#endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
120
121/*****************************************************************************
122 * Low-level board support code
123 *****************************************************************************/
124
125static unsigned long __init ppc7d_find_end_of_memory(void)
126{
127 bd_t *bp = (bd_t *) __res;
128
129 if (bp->bi_memsize)
130 return bp->bi_memsize;
131
132 return (256 * 1024 * 1024);
133}
134
135static void __init ppc7d_map_io(void)
136{
137 /* remove temporary mapping */
138 mtspr(SPRN_DBAT3U, 0x00000000);
139 mtspr(SPRN_DBAT3L, 0x00000000);
140
141 io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO);
142 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
143}
144
145static void ppc7d_restart(char *cmd)
146{
147 u32 data;
148
149 /* Disable GPP17 interrupt */
150 data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
151 data &= ~(1 << PPC7D_RST_PIN);
152 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
153
154 /* Configure MPP17 as GPP */
155 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
156 data &= ~(0x0000000f << 4);
157 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
158
159 /* Enable pin GPP17 for output */
160 data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
161 data |= (1 << PPC7D_RST_PIN);
162 mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
163
164 /* Toggle GPP9 pin to reset the board */
165 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN);
166 mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN);
167
168 for (;;) ; /* Spin until reset happens */
169 /* NOTREACHED */
170}
171
172static void ppc7d_power_off(void)
173{
174 u32 data;
175
176 local_irq_disable();
177
178 /* Ensure that internal MV643XX watchdog is disabled.
179 * The Disco watchdog uses MPP17 on this hardware.
180 */
181 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
182 data &= ~(0x0000000f << 4);
183 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
184
185 data = mv64x60_read(&bh, MV64x60_WDT_WDC);
186 if (data & 0x80000000) {
187 mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24);
188 mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24);
189 }
190
191 for (;;) ; /* No way to shut power off with software */
192 /* NOTREACHED */
193}
194
195static void ppc7d_halt(void)
196{
197 ppc7d_power_off();
198 /* NOTREACHED */
199}
200
201static unsigned long ppc7d_led_no_pulse;
202
203static int __init ppc7d_led_pulse_disable(char *str)
204{
205 ppc7d_led_no_pulse = 1;
206 return 1;
207}
208
209/* This kernel option disables the heartbeat pulsing of a board LED */
210__setup("ledoff", ppc7d_led_pulse_disable);
211
212static void ppc7d_heartbeat(void)
213{
214 u32 data32;
215 u8 data8;
216 static int max706_wdog = 0;
217
218 /* Unfortunately we can't access the LED control registers
219 * during early init because they're on the CPLD which is the
220 * other side of a PCI bridge which goes unreachable during
221 * PCI scan. So write the LEDs only if the MV64360 watchdog is
222 * enabled (i.e. userspace apps are running so kernel is up)..
223 */
224 data32 = mv64x60_read(&bh, MV64x60_WDT_WDC);
225 if (data32 & 0x80000000) {
226 /* Enable MAX706 watchdog if not done already */
227 if (!max706_wdog) {
228 outb(3, PPC7D_CPLD_RESET);
229 max706_wdog = 1;
230 }
231
232 /* Hit the MAX706 watchdog */
233 outb(0, PPC7D_CPLD_WATCHDOG_TRIG);
234
235 /* Pulse LED DS219 if not disabled */
236 if (!ppc7d_led_no_pulse) {
237 static int led_on = 0;
238
239 data8 = inb(PPC7D_CPLD_LEDS);
240 if (led_on)
241 data8 &= ~PPC7D_CPLD_LEDS_DS219_MASK;
242 else
243 data8 |= PPC7D_CPLD_LEDS_DS219_MASK;
244
245 outb(data8, PPC7D_CPLD_LEDS);
246 led_on = !led_on;
247 }
248 }
249 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
250}
251
252static int ppc7d_show_cpuinfo(struct seq_file *m)
253{
254 u8 val;
255 u8 val1, val2;
256 static int flash_sizes[4] = { 64, 32, 0, 16 };
257 static int flash_banks[4] = { 4, 3, 2, 1 };
258 static int sdram_bank_sizes[4] = { 128, 256, 512, 1 };
259 int sdram_num_banks = 2;
260 static char *pci_modes[] = { "PCI33", "PCI66",
261 "Unknown", "Unknown",
262 "PCIX33", "PCIX66",
263 "PCIX100", "PCIX133"
264 };
265
266 seq_printf(m, "vendor\t\t: Radstone Technology\n");
267 seq_printf(m, "machine\t\t: PPC7D\n");
268
269 val = inb(PPC7D_CPLD_BOARD_REVISION);
270 val1 = (val & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
271 val2 = (val & PPC7D_CPLD_BOARD_REVISION_LETTER_MASK);
272 seq_printf(m, "revision\t: %hd%c%c\n",
273 val1,
274 (val2 <= 0x18) ? 'A' + val2 : 'Y',
275 (val2 > 0x18) ? 'A' + (val2 - 0x19) : ' ');
276
277 val = inb(PPC7D_CPLD_MOTHERBOARD_TYPE);
278 val1 = val & PPC7D_CPLD_MB_TYPE_PLL_MASK;
279 val2 = val & (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK |
280 PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK);
281 seq_printf(m, "bus speed\t: %dMHz\n",
282 (val1 == PPC7D_CPLD_MB_TYPE_PLL_133) ? 133 :
283 (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 :
284 (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0);
285
286 val = inb(PPC7D_CPLD_MEM_CONFIG);
287 if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--;
288
289 val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND);
290 val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6;
291 seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c",
292 sdram_num_banks,
293 sdram_bank_sizes[val1],
294 (sdram_bank_sizes[val1] < 128) ? 'G' : 'M',
295 sdram_num_banks * sdram_bank_sizes[val1],
296 (sdram_bank_sizes[val1] < 128) ? 'G' : 'M');
297 if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) {
298 seq_printf(m, " [ECC %sabled]",
299 (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" :
300 "dis");
301 }
302 seq_printf(m, "\n");
303
304 val1 = (val & PPC7D_CPLD_FLASH_DEV_SIZE_MASK);
305 val2 = (val & PPC7D_CPLD_FLASH_BANK_NUM_MASK) >> 2;
306 seq_printf(m, "FLASH\t\t: %d banks of %dM, total %dM\n",
307 flash_banks[val2], flash_sizes[val1],
308 flash_banks[val2] * flash_sizes[val1]);
309
310 val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL);
311 val1 = inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
312 seq_printf(m, " write links\t: %s%s%s%s\n",
313 (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "WRITE " : "",
314 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "BOOT " : "",
315 (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "USER " : "",
316 (val & (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
317 PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
318 PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK)) ==
319 0 ? "NONE" : "");
320 seq_printf(m, " write sector h/w enables: %s%s%s%s%s\n",
321 (val & PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK) ? "RECOVERY " :
322 "",
323 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK) ? "BOOT " : "",
324 (val & PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK) ? "USER " : "",
325 (val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ? "NVRAM " :
326 "",
327 (((val &
328 (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK |
329 PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK |
330 PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK)) == 0)
331 && ((val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ==
332 0)) ? "NONE" : "");
333 val1 =
334 inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT) &
335 (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK |
336 PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK);
337 seq_printf(m, " software sector enables: %s%s%s\n",
338 (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK) ? "SYSBOOT "
339 : "",
340 (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK) ? "USER " : "",
341 (val1 == 0) ? "NONE " : "");
342
343 seq_printf(m, "Boot options\t: %s%s%s%s\n",
344 (val & PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK) ?
345 "ALTERNATE " : "",
346 (val & PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK) ? "VME " :
347 "",
348 (val & PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK) ? "RECOVERY "
349 : "",
350 ((val &
351 (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK |
352 PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK |
353 PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK)) ==
354 0) ? "NONE" : "");
355
356 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1);
357 seq_printf(m, "Fitted modules\t: %s%s%s%s\n",
358 (val & PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK) ? "" : "PMC1 ",
359 (val & PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK) ? "" : "PMC2 ",
360 (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) ? "AFIX " : "",
361 ((val & (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
362 PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK |
363 PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK)) ==
364 (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
365 PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK)) ? "NONE" : "");
366
367 if (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) {
368 static const char *ids[] = {
369 "unknown",
370 "1553 (Dual Channel)",
371 "1553 (Single Channel)",
372 "8-bit SCSI + VGA",
373 "16-bit SCSI + VGA",
374 "1553 (Single Channel with sideband)",
375 "1553 (Dual Channel with sideband)",
376 NULL
377 };
378 u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03);
379 seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id,
380 id < 7 ? ids[id] : "unknown");
381 }
382
383 val = inb(PPC7D_CPLD_PCI_CONFIG);
384 val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4;
385 val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK);
386 seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n",
387 pci_modes[val1], pci_modes[val2]);
388
389 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
390 seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n",
391 (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v",
392 (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v");
393 seq_printf(m, "PMC power source: %s\n",
394 (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" :
395 "internal");
396
397 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4);
398 val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
399 seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n",
400 (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "",
401 (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "",
402 (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "",
403 (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "",
404 (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "",
405 (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "",
406 (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " :
407 "");
408
409 val = inb(PPC7D_CPLD_ID_LINK);
410 val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK |
411 PPC7D_CPLD_ID_LINK_E7_MASK |
412 PPC7D_CPLD_ID_LINK_E12_MASK |
413 PPC7D_CPLD_ID_LINK_E13_MASK);
414
415 val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) &
416 (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
417 PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
418 PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK);
419
420 seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n",
421 (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "",
422 (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "",
423 (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "",
424 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "",
425 (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "",
426 (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "",
427 (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "",
428 ((val == 0) && (val1 == 0)) ? "NONE" : "");
429
430 val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK);
431 seq_printf(m, "Front panel reset switch: %sabled\n",
432 (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en");
433
434 return 0;
435}
436
437static void __init ppc7d_calibrate_decr(void)
438{
439 ulong freq;
440
441 freq = 100000000 / 4;
442
443 pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n",
444 freq / 1000000, freq % 1000000);
445
446 tb_ticks_per_jiffy = freq / HZ;
447 tb_to_us = mulhwu_scale_factor(freq, 1000000);
448}
449
450/*****************************************************************************
451 * Interrupt stuff
452 *****************************************************************************/
453
454static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id)
455{
456 u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
457 if (temp & (1 << 28)) {
458 i8259_irq();
459 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28)));
460 return IRQ_HANDLED;
461 }
462
463 return IRQ_NONE;
464}
465
466/*
467 * Each interrupt cause is assigned an IRQ number.
468 * Southbridge has 16*2 (two 8259's) interrupts.
469 * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
470 * If multiple interrupts are pending, get_irq() returns the
471 * lowest pending irq number first.
472 *
473 *
474 * IRQ # Source Trig Active
475 * =============================================================
476 *
477 * Southbridge
478 * -----------
479 * IRQ # Source Trig
480 * =============================================================
481 * 0 ISA High Resolution Counter Edge
482 * 1 Keyboard Edge
483 * 2 Cascade From (IRQ 8-15) Edge
484 * 3 Com 2 (Uart 2) Edge
485 * 4 Com 1 (Uart 1) Edge
486 * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
487 * 6 GPIO Level
488 * 7 LPT Edge
489 * 8 RTC Alarm Edge
490 * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
491 * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
492 * 11 USB2 Level
493 * 12 Mouse Edge
494 * 13 Reserved internally by Ali M1535+
495 * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
496 * 15 COM 5/6 Level
497 *
498 * 16..112 Discovery-II...
499 *
500 * MPP28 Southbridge Edge High
501 *
502 *
503 * Interrupts are cascaded through to the Discovery-II.
504 *
505 * PCI ---
506 * \
507 * CPLD --> ALI1535 -------> DISCOVERY-II
508 * INTF MPP28
509 */
510static void __init ppc7d_init_irq(void)
511{
512 int irq;
513
514 pr_debug("%s\n", __func__);
515 i8259_init(0, 0);
516 mv64360_init_irq();
517
518 /* IRQs 5,6,9,10,11,14,15 are level sensitive */
519 irq_desc[5].status |= IRQ_LEVEL;
520 irq_desc[6].status |= IRQ_LEVEL;
521 irq_desc[9].status |= IRQ_LEVEL;
522 irq_desc[10].status |= IRQ_LEVEL;
523 irq_desc[11].status |= IRQ_LEVEL;
524 irq_desc[14].status |= IRQ_LEVEL;
525 irq_desc[15].status |= IRQ_LEVEL;
526
527 /* GPP28 is edge triggered */
528 irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL;
529}
530
531static u32 ppc7d_irq_canonicalize(u32 irq)
532{
533 if ((irq >= 16) && (irq < (16 + 96)))
534 irq -= 16;
535
536 return irq;
537}
538
539static int ppc7d_get_irq(void)
540{
541 int irq;
542
543 irq = mv64360_get_irq();
544 if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
545 irq = i8259_irq();
546 return irq;
547}
548
549/*
550 * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
551 * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
552 * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
553 * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
554 */
555static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel,
556 unsigned char pin)
557{
558 static const char pci_irq_table[][4] =
559 /*
560 * PCI IDSEL/INTPIN->INTLINE
561 * A B C D
562 */
563 {
564 {10, 14, 5, 9}, /* IDSEL 10 - PMC2 / AFIX IRQW */
565 {9, 10, 14, 5}, /* IDSEL 11 - PMC1 / AFIX IRQX */
566 {5, 9, 10, 14}, /* IDSEL 12 - AFIX IRQY */
567 {14, 5, 9, 10}, /* IDSEL 13 - AFIX IRQZ */
568 };
569 const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4;
570
571 pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __func__,
572 dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin);
573
574 return PCI_IRQ_TABLE_LOOKUP;
575}
576
577void __init ppc7d_intr_setup(void)
578{
579 u32 data;
580
581 /*
582 * Define GPP 28 interrupt polarity as active high
583 * input signal and level triggered
584 */
585 data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL);
586 data &= ~(1 << 28);
587 mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data);
588 data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
589 data &= ~(1 << 28);
590 mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
591
592 /* Config GPP intr ctlr to respond to level trigger */
593 data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL);
594 data |= (1 << 10);
595 mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data);
596
597 /* XXXX Erranum FEr PCI-#8 */
598 data = mv64x60_read(&bh, MV64x60_PCI0_CMD);
599 data &= ~((1 << 5) | (1 << 9));
600 mv64x60_write(&bh, MV64x60_PCI0_CMD, data);
601 data = mv64x60_read(&bh, MV64x60_PCI1_CMD);
602 data &= ~((1 << 5) | (1 << 9));
603 mv64x60_write(&bh, MV64x60_PCI1_CMD, data);
604
605 /*
606 * Dismiss and then enable interrupt on GPP interrupt cause
607 * for CPU #0
608 */
609 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28));
610 data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
611 data |= (1 << 28);
612 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
613
614 /*
615 * Dismiss and then enable interrupt on CPU #0 high cause reg
616 * BIT27 summarizes GPP interrupts 23-31
617 */
618 mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27));
619 data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI);
620 data |= (1 << 27);
621 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data);
622}
623
624/*****************************************************************************
625 * Platform device data fixup routines.
626 *****************************************************************************/
627
628#if defined(CONFIG_SERIAL_MPSC)
629static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev)
630{
631 struct mpsc_pdata *pdata;
632
633 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
634
635 pdata->max_idle = 40;
636 pdata->default_baud = PPC7D_DEFAULT_BAUD;
637 pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC;
638 pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ;
639
640 return;
641}
642#endif
643
644#if defined(CONFIG_MV643XX_ETH)
645static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev)
646{
647 struct mv643xx_eth_platform_data *eth_pd;
648 static u16 phy_addr[] = {
649 PPC7D_ETH0_PHY_ADDR,
650 PPC7D_ETH1_PHY_ADDR,
651 PPC7D_ETH2_PHY_ADDR,
652 };
653 int i;
654
655 eth_pd = pdev->dev.platform_data;
656 eth_pd->force_phy_addr = 1;
657 eth_pd->phy_addr = phy_addr[pdev->id];
658 eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE;
659 eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE;
660
661 /* Adjust IRQ by mv64360_irq_base */
662 for (i = 0; i < pdev->num_resources; i++) {
663 struct resource *r = &pdev->resource[i];
664
665 if (r->flags & IORESOURCE_IRQ) {
666 r->start += mv64360_irq_base;
667 r->end += mv64360_irq_base;
668 pr_debug("%s, uses IRQ %d\n", pdev->name,
669 (int)r->start);
670 }
671 }
672
673}
674#endif
675
676#if defined(CONFIG_I2C_MV64XXX)
677static void __init
678ppc7d_fixup_i2c_pdata(struct platform_device *pdev)
679{
680 struct mv64xxx_i2c_pdata *pdata;
681 int i;
682
683 pdata = pdev->dev.platform_data;
684 if (pdata == NULL) {
685 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
686 if (pdata == NULL)
687 return;
688
689 pdev->dev.platform_data = pdata;
690 }
691
692 /* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
693 pdata->freq_m = 8;
694 pdata->freq_n = 3;
695 pdata->timeout = 500;
696 pdata->retries = 3;
697
698 /* Adjust IRQ by mv64360_irq_base */
699 for (i = 0; i < pdev->num_resources; i++) {
700 struct resource *r = &pdev->resource[i];
701
702 if (r->flags & IORESOURCE_IRQ) {
703 r->start += mv64360_irq_base;
704 r->end += mv64360_irq_base;
705 pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start);
706 }
707 }
708}
709#endif
710
711static int ppc7d_platform_notify(struct device *dev)
712{
713 static struct {
714 char *bus_id;
715 void ((*rtn) (struct platform_device * pdev));
716 } dev_map[] = {
717#if defined(CONFIG_SERIAL_MPSC)
718 { MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata },
719 { MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata },
720#endif
721#if defined(CONFIG_MV643XX_ETH)
722 { MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata },
723 { MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata },
724 { MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata },
725#endif
726#if defined(CONFIG_I2C_MV64XXX)
727 { MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata },
728#endif
729 };
730 struct platform_device *pdev;
731 int i;
732
733 if (dev && dev->bus_id)
734 for (i = 0; i < ARRAY_SIZE(dev_map); i++)
735 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
736 BUS_ID_SIZE)) {
737
738 pdev = container_of(dev,
739 struct platform_device,
740 dev);
741 dev_map[i].rtn(pdev);
742 }
743
744 return 0;
745}
746
747/*****************************************************************************
748 * PCI device fixups.
749 * These aren't really fixups per se. They are used to init devices as they
750 * are found during PCI scan.
751 *
752 * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI
753 * scan in order to find other devices on its secondary side.
754 *****************************************************************************/
755
756static void __init ppc7d_fixup_hb8(struct pci_dev *dev)
757{
758 u16 val16;
759
760 if (dev->bus->number == 0) {
761 pr_debug("PCI: HB8 init\n");
762
763 pci_write_config_byte(dev, 0x1c,
764 ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000)
765 >> 8) | 0x01);
766 pci_write_config_byte(dev, 0x1d,
767 (((PPC7D_PCI0_IO_START_PCI_ADDR +
768 PPC7D_PCI0_IO_SIZE -
769 1) & 0xf000) >> 8) | 0x01);
770 pci_write_config_word(dev, 0x30,
771 PPC7D_PCI0_IO_START_PCI_ADDR >> 16);
772 pci_write_config_word(dev, 0x32,
773 ((PPC7D_PCI0_IO_START_PCI_ADDR +
774 PPC7D_PCI0_IO_SIZE -
775 1) >> 16) & 0xffff);
776
777 pci_write_config_word(dev, 0x20,
778 PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16);
779 pci_write_config_word(dev, 0x22,
780 ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR +
781 PPC7D_PCI0_MEM0_SIZE -
782 1) >> 16) & 0xffff);
783 pci_write_config_word(dev, 0x24, 0);
784 pci_write_config_word(dev, 0x26, 0);
785 pci_write_config_dword(dev, 0x28, 0);
786 pci_write_config_dword(dev, 0x2c, 0);
787
788 pci_read_config_word(dev, 0x3e, &val16);
789 val16 |= ((1 << 5) | (1 << 1)); /* signal master aborts and
790 * SERR to primary
791 */
792 val16 &= ~(1 << 2); /* ISA disable, so all ISA
793 * ports forwarded to secondary
794 */
795 pci_write_config_word(dev, 0x3e, val16);
796 }
797}
798
799DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8);
800
801/* This should perhaps be a separate driver as we're actually initializing
802 * the chip for this board here. It's hardly a fixup...
803 */
804static void __init ppc7d_fixup_ali1535(struct pci_dev *dev)
805{
806 pr_debug("PCI: ALI1535 init\n");
807
808 if (dev->bus->number == 1) {
809 /* Configure the ISA Port Settings */
810 pci_write_config_byte(dev, 0x43, 0x00);
811
812 /* Disable PCI Interrupt polling mode */
813 pci_write_config_byte(dev, 0x45, 0x00);
814
815 /* Multifunction pin select INTFJ -> INTF */
816 pci_write_config_byte(dev, 0x78, 0x00);
817
818 /* Set PCI INT -> IRQ Routing control in for external
819 * pins south bridge.
820 */
821 pci_write_config_byte(dev, 0x48, 0x31); /* [7-4] INT B -> IRQ10
822 * [3-0] INT A -> IRQ9
823 */
824 pci_write_config_byte(dev, 0x49, 0x5D); /* [7-4] INT D -> IRQ5
825 * [3-0] INT C -> IRQ14
826 */
827
828 /* PPC7D setup */
829 /* NEC USB device on IRQ 11 (INTE) - INTF disabled */
830 pci_write_config_byte(dev, 0x4A, 0x09);
831
832 /* GPIO on IRQ 6 */
833 pci_write_config_byte(dev, 0x76, 0x07);
834
835 /* SIRQ I (COMS 5/6) use IRQ line 15.
836 * Positive (not subtractive) address decode.
837 */
838 pci_write_config_byte(dev, 0x44, 0x0f);
839
840 /* SIRQ II disabled */
841 pci_write_config_byte(dev, 0x75, 0x0);
842
843 /* On board USB and RTC disabled */
844 pci_write_config_word(dev, 0x52, (1 << 14));
845 pci_write_config_byte(dev, 0x74, 0x00);
846
847 /* On board IDE disabled */
848 pci_write_config_byte(dev, 0x58, 0x00);
849
850 /* Decode 32-bit addresses */
851 pci_write_config_byte(dev, 0x5b, 0);
852
853 /* Disable docking IO */
854 pci_write_config_word(dev, 0x5c, 0x0000);
855
856 /* Disable modem, enable sound */
857 pci_write_config_byte(dev, 0x77, (1 << 6));
858
859 /* Disable hot-docking mode */
860 pci_write_config_byte(dev, 0x7d, 0x00);
861 }
862}
863
864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535);
865
866static int ppc7d_pci_exclude_device(u8 bus, u8 devfn)
867{
868 /* Early versions of this board were fitted with IBM ALMA
869 * PCI-VME bridge chips. The PCI config space of these devices
870 * was not set up correctly and causes PCI scan problems.
871 */
872 if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma)
873 return PCIBIOS_DEVICE_NOT_FOUND;
874
875 return mv64x60_pci_exclude_device(bus, devfn);
876}
877
878/* This hook is called when each PCI bus is probed.
879 */
880static void ppc7d_pci_fixup_bus(struct pci_bus *bus)
881{
882 pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n",
883 bus->number,
884 bus->resource[0] ? bus->resource[0]->start : 0,
885 bus->resource[0] ? bus->resource[0]->end : 0,
886 bus->resource[1] ? bus->resource[1]->start : 0,
887 bus->resource[1] ? bus->resource[1]->end : 0,
888 bus->resource[2] ? bus->resource[2]->start : 0,
889 bus->resource[2] ? bus->resource[2]->end : 0,
890 bus->resource[3] ? bus->resource[3]->start : 0,
891 bus->resource[3] ? bus->resource[3]->end : 0);
892
893 if ((bus->number == 1) && (bus->resource[2] != NULL)) {
894 /* Hide PCI window 2 of Bus 1 which is used only to
895 * map legacy ISA memory space.
896 */
897 bus->resource[2]->start = 0;
898 bus->resource[2]->end = 0;
899 bus->resource[2]->flags = 0;
900 }
901}
902
903/*****************************************************************************
904 * Board device setup code
905 *****************************************************************************/
906
907void __init ppc7d_setup_peripherals(void)
908{
909 u32 val32;
910
911 /* Set up windows for boot CS */
912 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
913 PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE,
914 0);
915 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
916
917 /* Boot firmware configures the following DevCS addresses.
918 * DevCS0 - board control/status
919 * DevCS1 - test registers
920 * DevCS2 - AFIX port/address registers (for identifying)
921 * DevCS3 - FLASH
922 *
923 * We don't use DevCS0, DevCS1.
924 */
925 val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE);
926 val32 |= ((1 << 4) | (1 << 5));
927 mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32);
928 mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0);
929 mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0);
930 mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0);
931 mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0);
932
933 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
934 PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0);
935 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
936
937 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
938 PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0);
939 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
940
941 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
942 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
943 0);
944 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
945
946 /* Set up Enet->SRAM window */
947 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
948 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
949 0x2);
950 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
951
952 /* Give enet r/w access to memory region */
953 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0);
954 val32 |= (0x3 << (4 << 1));
955 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32);
956 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1);
957 val32 |= (0x3 << (4 << 1));
958 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32);
959 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2);
960 val32 |= (0x3 << (4 << 1));
961 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32);
962
963 val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL);
964 val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24));
965 mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32);
966
967 /* Enumerate pci bus.
968 *
969 * We scan PCI#0 first (the bus with the HB8 and other
970 * on-board peripherals). We must configure the 64360 before
971 * each scan, according to the bus number assignments. Busses
972 * are assigned incrementally, starting at 0. PCI#0 is
973 * usually assigned bus#0, the secondary side of the HB8 gets
974 * bus#1 and PCI#1 (second PMC site) gets bus#2. However, if
975 * any PMC card has a PCI bridge, these bus assignments will
976 * change.
977 */
978
979 /* Turn off PCI retries */
980 val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
981 val32 |= (1 << 17);
982 mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
983
984 /* Scan PCI#0 */
985 mv64x60_set_bus(&bh, 0, 0);
986 bh.hose_a->first_busno = 0;
987 bh.hose_a->last_busno = 0xff;
988 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
989 printk(KERN_INFO "PCI#0: first=%d last=%d\n",
990 bh.hose_a->first_busno, bh.hose_a->last_busno);
991
992 /* Scan PCI#1 */
993 bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
994 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
995 bh.hose_b->last_busno = 0xff;
996 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
997 bh.hose_b->first_busno);
998 printk(KERN_INFO "PCI#1: first=%d last=%d\n",
999 bh.hose_b->first_busno, bh.hose_b->last_busno);
1000
1001 /* Turn on PCI retries */
1002 val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1003 val32 &= ~(1 << 17);
1004 mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
1005
1006 /* Setup interrupts */
1007 ppc7d_intr_setup();
1008}
1009
1010static void __init ppc7d_setup_bridge(void)
1011{
1012 struct mv64x60_setup_info si;
1013 int i;
1014 u32 temp;
1015
1016 mv64360_irq_base = 16; /* first 16 intrs are 2 x 8259's */
1017
1018 memset(&si, 0, sizeof(si));
1019
1020 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
1021
1022 si.pci_0.enable_bus = 1;
1023 si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR;
1024 si.pci_0.pci_io.pci_base_hi = 0;
1025 si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR;
1026 si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE;
1027 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
1028 si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR;
1029 si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR;
1030 si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
1031 si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE;
1032 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
1033 si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR;
1034 si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR;
1035 si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR;
1036 si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE;
1037 si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
1038 si.pci_0.pci_cmd_bits = 0;
1039 si.pci_0.latency_timer = 0x80;
1040
1041 si.pci_1.enable_bus = 1;
1042 si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR;
1043 si.pci_1.pci_io.pci_base_hi = 0;
1044 si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR;
1045 si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE;
1046 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
1047 si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR;
1048 si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR;
1049 si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
1050 si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE;
1051 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
1052 si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR;
1053 si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR;
1054 si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR;
1055 si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE;
1056 si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
1057 si.pci_1.pci_cmd_bits = 0;
1058 si.pci_1.latency_timer = 0x80;
1059
1060 /* Don't clear the SRAM window since we use it for debug */
1061 si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN);
1062
1063 printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n",
1064 si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size);
1065 printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n",
1066 si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size);
1067
1068 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
1069#if defined(CONFIG_NOT_COHERENT_CACHE)
1070 si.cpu_prot_options[i] = 0;
1071 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
1072 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
1073 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
1074
1075 si.pci_0.acc_cntl_options[i] =
1076 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
1077 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1078 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
1079 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
1080
1081 si.pci_1.acc_cntl_options[i] =
1082 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
1083 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1084 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
1085 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
1086#else
1087 si.cpu_prot_options[i] = 0;
1088 /* All PPC7D hardware uses B0 or newer MV64360 silicon which
1089 * does not have snoop bugs.
1090 */
1091 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
1092 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
1093 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
1094
1095 si.pci_0.acc_cntl_options[i] =
1096 MV64360_PCI_ACC_CNTL_SNOOP_WB |
1097 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1098 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
1099 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
1100
1101 si.pci_1.acc_cntl_options[i] =
1102 MV64360_PCI_ACC_CNTL_SNOOP_WB |
1103 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1104 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
1105 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
1106#endif
1107 }
1108
1109 /* Lookup PCI host bridges */
1110 if (mv64x60_init(&bh, &si))
1111 printk(KERN_ERR "MV64360 initialization failed.\n");
1112
1113 pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base);
1114
1115 /* Enable WB Cache coherency on SRAM */
1116 temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG);
1117 pr_debug("SRAM_CONFIG: %x\n", temp);
1118#if defined(CONFIG_NOT_COHERENT_CACHE)
1119 mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2);
1120#else
1121 mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2);
1122#endif
1123 /* If system operates with internal bus arbiter (CPU master
1124 * control bit8) clear AACK Delay bit [25] in CPU
1125 * configuration register.
1126 */
1127 temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL);
1128 if (temp & (1 << 8)) {
1129 temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1130 mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25)));
1131 }
1132
1133 /* Data and address parity is enabled */
1134 temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1135 mv64x60_write(&bh, MV64x60_CPU_CONFIG,
1136 (temp | (1 << 26) | (1 << 19)));
1137
1138 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
1139 ppc_md.pci_swizzle = common_swizzle;
1140 ppc_md.pci_map_irq = ppc7d_map_irq;
1141 ppc_md.pci_exclude_device = ppc7d_pci_exclude_device;
1142
1143 mv64x60_set_bus(&bh, 0, 0);
1144 bh.hose_a->first_busno = 0;
1145 bh.hose_a->last_busno = 0xff;
1146 bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
1147 bh.hose_a->mem_space.end =
1148 PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE;
1149
1150 /* These will be set later, as a result of PCI0 scan */
1151 bh.hose_b->first_busno = 0;
1152 bh.hose_b->last_busno = 0xff;
1153 bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
1154 bh.hose_b->mem_space.end =
1155 PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE;
1156
1157 pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n",
1158 mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50),
1159 mv64x60_read(&bh, 0xf0));
1160}
1161
1162static void __init ppc7d_setup_arch(void)
1163{
1164 int port;
1165
1166 loops_per_jiffy = 100000000 / HZ;
1167
1168#ifdef CONFIG_BLK_DEV_INITRD
1169 if (initrd_start)
1170 ROOT_DEV = Root_RAM0;
1171 else
1172#endif
1173#ifdef CONFIG_ROOT_NFS
1174 ROOT_DEV = Root_NFS;
1175#else
1176 ROOT_DEV = Root_HDA1;
1177#endif
1178
1179 if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) ||
1180 (cur_cpu_spec->cpu_features & CPU_FTR_L3CR))
1181 /* 745x is different. We only want to pass along enable. */
1182 _set_L2CR(L2CR_L2E);
1183 else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR)
1184 /* All modules have 1MB of L2. We also assume that an
1185 * L2 divisor of 3 will work.
1186 */
1187 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
1188 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
1189
1190 if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)
1191 /* No L3 cache */
1192 _set_L3CR(0);
1193
1194#ifdef CONFIG_DUMMY_CONSOLE
1195 conswitchp = &dummy_con;
1196#endif
1197
1198 /* Lookup PCI host bridges */
1199 if (ppc_md.progress)
1200 ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0);
1201
1202 ppc7d_setup_bridge();
1203 ppc7d_setup_peripherals();
1204
1205 /* Disable ethernet. It might have been setup by the bootrom */
1206 for (port = 0; port < 3; port++)
1207 mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port),
1208 0x0000ff00);
1209
1210 /* Clear queue pointers to ensure they are all initialized,
1211 * otherwise since queues 1-7 are unused, they have random
1212 * pointers which look strange in register dumps. Don't bother
1213 * with queue 0 since it will be initialized later.
1214 */
1215 for (port = 0; port < 3; port++) {
1216 mv64x60_write(&bh,
1217 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port),
1218 0x00000000);
1219 mv64x60_write(&bh,
1220 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port),
1221 0x00000000);
1222 mv64x60_write(&bh,
1223 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port),
1224 0x00000000);
1225 mv64x60_write(&bh,
1226 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port),
1227 0x00000000);
1228 mv64x60_write(&bh,
1229 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port),
1230 0x00000000);
1231 mv64x60_write(&bh,
1232 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port),
1233 0x00000000);
1234 mv64x60_write(&bh,
1235 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port),
1236 0x00000000);
1237 }
1238
1239 printk(KERN_INFO "Radstone Technology PPC7D\n");
1240 if (ppc_md.progress)
1241 ppc_md.progress("ppc7d_setup_arch: exit", 0);
1242
1243}
1244
1245/* Real Time Clock support.
1246 * PPC7D has a DS1337 accessed by I2C.
1247 */
1248static ulong ppc7d_get_rtc_time(void)
1249{
1250 struct rtc_time tm;
1251 int result;
1252
1253 spin_lock(&rtc_lock);
1254 result = ds1337_do_command(0, DS1337_GET_DATE, &tm);
1255 spin_unlock(&rtc_lock);
1256
1257 if (result == 0)
1258 result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
1259
1260 return result;
1261}
1262
1263static int ppc7d_set_rtc_time(unsigned long nowtime)
1264{
1265 struct rtc_time tm;
1266 int result;
1267
1268 spin_lock(&rtc_lock);
1269 to_tm(nowtime, &tm);
1270 result = ds1337_do_command(0, DS1337_SET_DATE, &tm);
1271 spin_unlock(&rtc_lock);
1272
1273 return result;
1274}
1275
1276/* This kernel command line parameter can be used to have the target
1277 * wait for a JTAG debugger to attach. Of course, a JTAG debugger
1278 * with hardware breakpoint support can have the target stop at any
1279 * location during init, but this is a convenience feature that makes
1280 * it easier in the common case of loading the code using the ppcboot
1281 * bootloader..
1282 */
1283static unsigned long ppc7d_wait_debugger;
1284
1285static int __init ppc7d_waitdbg(char *str)
1286{
1287 ppc7d_wait_debugger = 1;
1288 return 1;
1289}
1290
1291__setup("waitdbg", ppc7d_waitdbg);
1292
1293/* Second phase board init, called after other (architecture common)
1294 * low-level services have been initialized.
1295 */
1296static void ppc7d_init2(void)
1297{
1298 unsigned long flags;
1299 u32 data;
1300 u8 data8;
1301
1302 pr_debug("%s: enter\n", __func__);
1303
1304 /* Wait for debugger? */
1305 if (ppc7d_wait_debugger) {
1306 printk("Waiting for debugger...\n");
1307
1308 while (readl(&ppc7d_wait_debugger)) ;
1309 }
1310
1311 /* Hook up i8259 interrupt which is connected to GPP28 */
1312 request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr,
1313 IRQF_DISABLED, "I8259 (GPP28) interrupt", (void *)0);
1314
1315 /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */
1316 spin_lock_irqsave(&mv64x60_lock, flags);
1317 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
1318 data &= ~(0x0000000f << 0);
1319 data |= (0x00000004 << 0);
1320 data &= ~(0x0000000f << 4);
1321 data |= (0x00000004 << 4);
1322 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
1323 spin_unlock_irqrestore(&mv64x60_lock, flags);
1324
1325 /* All LEDs off */
1326 data8 = inb(PPC7D_CPLD_LEDS);
1327 data8 &= ~0x08;
1328 data8 |= 0x07;
1329 outb(data8, PPC7D_CPLD_LEDS);
1330
1331 /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */
1332 ppc_md.set_rtc_time = ppc7d_set_rtc_time;
1333 ppc_md.get_rtc_time = ppc7d_get_rtc_time;
1334
1335 pr_debug("%s: exit\n", __func__);
1336}
1337
1338/* Called from machine_init(), early, before any of the __init functions
1339 * have run. We must init software-configurable pins before other functions
1340 * such as interrupt controllers are initialised.
1341 */
1342void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
1343 unsigned long r6, unsigned long r7)
1344{
1345 u8 val8;
1346 u8 rev_num;
1347
1348 /* Map 0xe0000000-0xffffffff early because we need access to SRAM
1349 * and the ISA memory space (for serial port) here. This mapping
1350 * is redone properly in ppc7d_map_io() later.
1351 */
1352 mtspr(SPRN_DBAT3U, 0xe0003fff);
1353 mtspr(SPRN_DBAT3L, 0xe000002a);
1354
1355 /*
1356 * Zero SRAM. Note that this generates parity errors on
1357 * internal data path in SRAM if it's first time accessing it
1358 * after reset.
1359 *
1360 * We do this ASAP to avoid parity errors when reading
1361 * uninitialized SRAM.
1362 */
1363 memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE);
1364
1365 pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n",
1366 r3, r4, r5, r6, r7);
1367
1368 parse_bootinfo(find_bootinfo());
1369
1370 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
1371 * are non-zero, then we should use the board info from the bd_t
1372 * structure and the cmdline pointed to by r6 instead of the
1373 * information from birecs, if any. Otherwise, use the information
1374 * from birecs as discovered by the preceding call to
1375 * parse_bootinfo(). This rule should work with both PPCBoot, which
1376 * uses a bd_t board info structure, and the kernel boot wrapper,
1377 * which uses birecs.
1378 */
1379 if (r3 && r6) {
1380 bd_t *bp = (bd_t *) __res;
1381
1382 /* copy board info structure */
1383 memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));
1384 /* copy command line */
1385 *(char *)(r7 + KERNELBASE) = 0;
1386 strcpy(cmd_line, (char *)(r6 + KERNELBASE));
1387
1388 printk(KERN_INFO "Board info data:-\n");
1389 printk(KERN_INFO " Internal freq: %lu MHz, bus freq: %lu MHz\n",
1390 bp->bi_intfreq, bp->bi_busfreq);
1391 printk(KERN_INFO " Memory: %lx, size %lx\n", bp->bi_memstart,
1392 bp->bi_memsize);
1393 printk(KERN_INFO " Console baudrate: %lu\n", bp->bi_baudrate);
1394 printk(KERN_INFO " Ethernet address: "
1395 "%02x:%02x:%02x:%02x:%02x:%02x\n",
1396 bp->bi_enetaddr[0], bp->bi_enetaddr[1],
1397 bp->bi_enetaddr[2], bp->bi_enetaddr[3],
1398 bp->bi_enetaddr[4], bp->bi_enetaddr[5]);
1399 }
1400#ifdef CONFIG_BLK_DEV_INITRD
1401 /* take care of initrd if we have one */
1402 if (r4) {
1403 initrd_start = r4 + KERNELBASE;
1404 initrd_end = r5 + KERNELBASE;
1405 printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end);
1406 }
1407#endif /* CONFIG_BLK_DEV_INITRD */
1408
1409 /* Map in board regs, etc. */
1410 isa_io_base = 0xe8000000;
1411 isa_mem_base = 0xe8000000;
1412 pci_dram_offset = 0x00000000;
1413 ISA_DMA_THRESHOLD = 0x00ffffff;
1414 DMA_MODE_READ = 0x44;
1415 DMA_MODE_WRITE = 0x48;
1416
1417 ppc_md.setup_arch = ppc7d_setup_arch;
1418 ppc_md.init = ppc7d_init2;
1419 ppc_md.show_cpuinfo = ppc7d_show_cpuinfo;
1420 /* XXX this is broken... */
1421 ppc_md.irq_canonicalize = ppc7d_irq_canonicalize;
1422 ppc_md.init_IRQ = ppc7d_init_irq;
1423 ppc_md.get_irq = ppc7d_get_irq;
1424
1425 ppc_md.restart = ppc7d_restart;
1426 ppc_md.power_off = ppc7d_power_off;
1427 ppc_md.halt = ppc7d_halt;
1428
1429 ppc_md.find_end_of_memory = ppc7d_find_end_of_memory;
1430 ppc_md.setup_io_mappings = ppc7d_map_io;
1431
1432 ppc_md.time_init = NULL;
1433 ppc_md.set_rtc_time = NULL;
1434 ppc_md.get_rtc_time = NULL;
1435 ppc_md.calibrate_decr = ppc7d_calibrate_decr;
1436 ppc_md.nvram_read_val = NULL;
1437 ppc_md.nvram_write_val = NULL;
1438
1439 ppc_md.heartbeat = ppc7d_heartbeat;
1440 ppc_md.heartbeat_reset = HZ;
1441 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
1442
1443 ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;
1444
1445#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
1446 defined(CONFIG_I2C_MV64XXX)
1447 platform_notify = ppc7d_platform_notify;
1448#endif
1449
1450#ifdef CONFIG_SERIAL_MPSC
1451 /* On PPC7D, we must configure MPSC support via CPLD control
1452 * registers.
1453 */
1454 outb(PPC7D_CPLD_RTS_COM4_SCLK |
1455 PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS);
1456 outb(PPC7D_CPLD_COMS_COM3_TCLKEN |
1457 PPC7D_CPLD_COMS_COM3_TXEN |
1458 PPC7D_CPLD_COMS_COM4_TCLKEN |
1459 PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS);
1460#endif /* CONFIG_SERIAL_MPSC */
1461
1462#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
1463 ppc7d_early_serial_map();
1464#ifdef CONFIG_SERIAL_TEXT_DEBUG
1465#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
1466 ppc_md.progress = mv64x60_mpsc_progress;
1467#elif defined(CONFIG_SERIAL_8250)
1468 ppc_md.progress = gen550_progress;
1469#else
1470#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
1471#endif /* CONFIG_SERIAL_8250 */
1472#endif /* CONFIG_SERIAL_TEXT_DEBUG */
1473#endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
1474
1475 /* Enable write access to user flash. This is necessary for
1476 * flash probe.
1477 */
1478 val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
1479 writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED &
1480 PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK),
1481 (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
1482
1483 /* Determine if this board has IBM ALMA VME devices */
1484 val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION);
1485 rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
1486 if (rev_num <= 1)
1487 ppc7d_has_alma = 1;
1488
1489#ifdef DEBUG
1490 console_printk[0] = 8;
1491#endif
1492}
diff --git a/arch/ppc/platforms/radstone_ppc7d.h b/arch/ppc/platforms/radstone_ppc7d.h
deleted file mode 100644
index 2bb093a0c03e..000000000000
--- a/arch/ppc/platforms/radstone_ppc7d.h
+++ /dev/null
@@ -1,433 +0,0 @@
1/*
2 * Board definitions for the Radstone PPC7D boards.
3 *
4 * Author: James Chapman <jchapman@katalix.com>
5 *
6 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
7 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/*
16 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
17 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
18 * We'll only use one PCI MEM window on each PCI bus.
19 *
20 * This is the CPU physical memory map (windows must be at least 1MB
21 * and start on a boundary that is a multiple of the window size):
22 *
23 * 0xff800000-0xffffffff - Boot window
24 * 0xff000000-0xff000fff - AFIX registers (DevCS2)
25 * 0xfef00000-0xfef0ffff - Internal MV64x60 registers
26 * 0xfef40000-0xfef7ffff - Internal SRAM
27 * 0xfef00000-0xfef0ffff - MV64360 Registers
28 * 0x70000000-0x7fffffff - soldered flash (DevCS3)
29 * 0xe8000000-0xe9ffffff - PCI I/O
30 * 0x80000000-0xbfffffff - PCI MEM
31 */
32
33#ifndef __PPC_PLATFORMS_PPC7D_H
34#define __PPC_PLATFORMS_PPC7D_H
35
36#include <asm/ppcboot.h>
37
38/*****************************************************************************
39 * CPU Physical Memory Map setup.
40 *****************************************************************************/
41
42#define PPC7D_BOOT_WINDOW_BASE 0xff800000
43#define PPC7D_AFIX_REG_BASE 0xff000000
44#define PPC7D_INTERNAL_SRAM_BASE 0xfef40000
45#define PPC7D_FLASH_BASE 0x70000000
46
47#define PPC7D_BOOT_WINDOW_SIZE_ACTUAL 0x00800000 /* 8MB */
48#define PPC7D_FLASH_SIZE_ACTUAL 0x10000000 /* 256MB */
49
50#define PPC7D_BOOT_WINDOW_SIZE max(MV64360_WINDOW_SIZE_MIN, \
51 PPC7D_BOOT_WINDOW_SIZE_ACTUAL)
52#define PPC7D_FLASH_SIZE max(MV64360_WINDOW_SIZE_MIN, \
53 PPC7D_FLASH_SIZE_ACTUAL)
54#define PPC7D_AFIX_REG_SIZE max(MV64360_WINDOW_SIZE_MIN, 0xff)
55
56
57#define PPC7D_PCI0_MEM0_START_PROC_ADDR 0x80000000UL
58#define PPC7D_PCI0_MEM0_START_PCI_HI_ADDR 0x00000000UL
59#define PPC7D_PCI0_MEM0_START_PCI_LO_ADDR 0x80000000UL
60#define PPC7D_PCI0_MEM0_SIZE 0x20000000UL
61#define PPC7D_PCI0_MEM1_START_PROC_ADDR 0xe8010000UL
62#define PPC7D_PCI0_MEM1_START_PCI_HI_ADDR 0x00000000UL
63#define PPC7D_PCI0_MEM1_START_PCI_LO_ADDR 0x00000000UL
64#define PPC7D_PCI0_MEM1_SIZE 0x000f0000UL
65#define PPC7D_PCI0_IO_START_PROC_ADDR 0xe8000000UL
66#define PPC7D_PCI0_IO_START_PCI_ADDR 0x00000000UL
67#define PPC7D_PCI0_IO_SIZE 0x00010000UL
68
69#define PPC7D_PCI1_MEM0_START_PROC_ADDR 0xa0000000UL
70#define PPC7D_PCI1_MEM0_START_PCI_HI_ADDR 0x00000000UL
71#define PPC7D_PCI1_MEM0_START_PCI_LO_ADDR 0xa0000000UL
72#define PPC7D_PCI1_MEM0_SIZE 0x20000000UL
73#define PPC7D_PCI1_MEM1_START_PROC_ADDR 0xe9800000UL
74#define PPC7D_PCI1_MEM1_START_PCI_HI_ADDR 0x00000000UL
75#define PPC7D_PCI1_MEM1_START_PCI_LO_ADDR 0x00000000UL
76#define PPC7D_PCI1_MEM1_SIZE 0x00800000UL
77#define PPC7D_PCI1_IO_START_PROC_ADDR 0xe9000000UL
78#define PPC7D_PCI1_IO_START_PCI_ADDR 0x00000000UL
79#define PPC7D_PCI1_IO_SIZE 0x00010000UL
80
81#define PPC7D_DEFAULT_BAUD 9600
82#define PPC7D_MPSC_CLK_SRC 8 /* TCLK */
83#define PPC7D_MPSC_CLK_FREQ 133333333 /* 133.3333... MHz */
84
85#define PPC7D_ETH0_PHY_ADDR 8
86#define PPC7D_ETH1_PHY_ADDR 9
87#define PPC7D_ETH2_PHY_ADDR 0
88
89#define PPC7D_ETH_TX_QUEUE_SIZE 400
90#define PPC7D_ETH_RX_QUEUE_SIZE 400
91
92#define PPC7D_ETH_PORT_CONFIG_VALUE \
93 MV64340_ETH_UNICAST_NORMAL_MODE | \
94 MV64340_ETH_DEFAULT_RX_QUEUE_0 | \
95 MV64340_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
96 MV64340_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
97 MV64340_ETH_RECEIVE_BC_IF_IP | \
98 MV64340_ETH_RECEIVE_BC_IF_ARP | \
99 MV64340_ETH_CAPTURE_TCP_FRAMES_DIS | \
100 MV64340_ETH_CAPTURE_UDP_FRAMES_DIS | \
101 MV64340_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
102 MV64340_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
103 MV64340_ETH_DEFAULT_RX_BPDU_QUEUE_0
104
105#define PPC7D_ETH_PORT_CONFIG_EXTEND_VALUE \
106 MV64340_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
107 MV64340_ETH_PARTITION_DISABLE
108
109#define GT_ETH_IPG_INT_RX(value) \
110 ((value & 0x3fff) << 8)
111
112#define PPC7D_ETH_PORT_SDMA_CONFIG_VALUE \
113 MV64340_ETH_RX_BURST_SIZE_4_64BIT | \
114 GT_ETH_IPG_INT_RX(0) | \
115 MV64340_ETH_TX_BURST_SIZE_4_64BIT
116
117#define PPC7D_ETH_PORT_SERIAL_CONTROL_VALUE \
118 MV64340_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
119 MV64340_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
120 MV64340_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
121 MV64340_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
122 MV64340_ETH_FORCE_BP_MODE_NO_JAM | \
123 (1 << 9) | \
124 MV64340_ETH_DO_NOT_FORCE_LINK_FAIL | \
125 MV64340_ETH_RETRANSMIT_16_ATTEMPTS | \
126 MV64340_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
127 MV64340_ETH_DTE_ADV_0 | \
128 MV64340_ETH_DISABLE_AUTO_NEG_BYPASS | \
129 MV64340_ETH_AUTO_NEG_NO_CHANGE | \
130 MV64340_ETH_MAX_RX_PACKET_9700BYTE | \
131 MV64340_ETH_CLR_EXT_LOOPBACK | \
132 MV64340_ETH_SET_FULL_DUPLEX_MODE | \
133 MV64340_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
134
135/*****************************************************************************
136 * Serial defines.
137 *****************************************************************************/
138
139#define PPC7D_SERIAL_0 0xe80003f8
140#define PPC7D_SERIAL_1 0xe80002f8
141
142#define RS_TABLE_SIZE 2
143
144/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
145#define UART_CLK 1843200
146#define BASE_BAUD ( UART_CLK / 16 )
147
148#ifdef CONFIG_SERIAL_DETECT_IRQ
149#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
150#else
151#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF)
152#endif
153
154#define STD_SERIAL_PORT_DFNS \
155 { 0, BASE_BAUD, PPC7D_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
156 iomem_base: (u8 *)PPC7D_SERIAL_0, \
157 io_type: SERIAL_IO_MEM, }, \
158 { 0, BASE_BAUD, PPC7D_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
159 iomem_base: (u8 *)PPC7D_SERIAL_1, \
160 io_type: SERIAL_IO_MEM },
161
162#define SERIAL_PORT_DFNS \
163 STD_SERIAL_PORT_DFNS
164
165/*****************************************************************************
166 * CPLD defines.
167 *
168 * Register map:-
169 *
170 * 0000 to 000F South Bridge DMA 1 Control
171 * 0020 and 0021 South Bridge Interrupt 1 Control
172 * 0040 to 0043 South Bridge Counter Control
173 * 0060 Keyboard
174 * 0061 South Bridge NMI Status and Control
175 * 0064 Keyboard
176 * 0071 and 0072 RTC R/W
177 * 0078 to 007B South Bridge BIOS Timer
178 * 0080 to 0090 South Bridge DMA Pages
179 * 00A0 and 00A1 South Bridge Interrupt 2 Control
180 * 00C0 to 00DE South Bridge DMA 2 Control
181 * 02E8 to 02EF COM6 R/W
182 * 02F8 to 02FF South Bridge COM2 R/W
183 * 03E8 to 03EF COM5 R/W
184 * 03F8 to 03FF South Bridge COM1 R/W
185 * 040A South Bridge DMA Scatter/Gather RO
186 * 040B DMA 1 Extended Mode WO
187 * 0410 to 043F South Bridge DMA Scatter/Gather
188 * 0481 to 048B South Bridge DMA High Pages
189 * 04D0 and 04D1 South Bridge Edge/Level Control
190 * 04D6 DMA 2 Extended Mode WO
191 * 0804 Memory Configuration RO
192 * 0806 Memory Configuration Extend RO
193 * 0808 SCSI Activity LED R/W
194 * 080C Equipment Present 1 RO
195 * 080E Equipment Present 2 RO
196 * 0810 Equipment Present 3 RO
197 * 0812 Equipment Present 4 RO
198 * 0818 Key Lock RO
199 * 0820 LEDS R/W
200 * 0824 COMs R/W
201 * 0826 RTS R/W
202 * 0828 Reset R/W
203 * 082C Watchdog Trig R/W
204 * 082E Interrupt R/W
205 * 0830 Interrupt Status RO
206 * 0832 PCI configuration RO
207 * 0854 Board Revision RO
208 * 0858 Extended ID RO
209 * 0864 ID Link RO
210 * 0866 Motherboard Type RO
211 * 0868 FLASH Write control RO
212 * 086A Software FLASH write protect R/W
213 * 086E FLASH Control R/W
214 *****************************************************************************/
215
216#define PPC7D_CPLD_MEM_CONFIG 0x0804
217#define PPC7D_CPLD_MEM_CONFIG_EXTEND 0x0806
218#define PPC7D_CPLD_SCSI_ACTIVITY_LED 0x0808
219#define PPC7D_CPLD_EQUIPMENT_PRESENT_1 0x080C
220#define PPC7D_CPLD_EQUIPMENT_PRESENT_2 0x080E
221#define PPC7D_CPLD_EQUIPMENT_PRESENT_3 0x0810
222#define PPC7D_CPLD_EQUIPMENT_PRESENT_4 0x0812
223#define PPC7D_CPLD_KEY_LOCK 0x0818
224#define PPC7D_CPLD_LEDS 0x0820
225#define PPC7D_CPLD_COMS 0x0824
226#define PPC7D_CPLD_RTS 0x0826
227#define PPC7D_CPLD_RESET 0x0828
228#define PPC7D_CPLD_WATCHDOG_TRIG 0x082C
229#define PPC7D_CPLD_INTR 0x082E
230#define PPC7D_CPLD_INTR_STATUS 0x0830
231#define PPC7D_CPLD_PCI_CONFIG 0x0832
232#define PPC7D_CPLD_BOARD_REVISION 0x0854
233#define PPC7D_CPLD_EXTENDED_ID 0x0858
234#define PPC7D_CPLD_ID_LINK 0x0864
235#define PPC7D_CPLD_MOTHERBOARD_TYPE 0x0866
236#define PPC7D_CPLD_FLASH_WRITE_CNTL 0x0868
237#define PPC7D_CPLD_SW_FLASH_WRITE_PROTECT 0x086A
238#define PPC7D_CPLD_FLASH_CNTL 0x086E
239
240/* MEMORY_CONFIG_EXTEND */
241#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02
242#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0
243#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0
244#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40
245#define PPC7D_CPLD_SDRAM_BANK_SIZE_512M 0x80
246#define PPC7D_CPLD_SDRAM_BANK_SIZE_1G 0xc0
247#define PPC7D_CPLD_FLASH_DEV_SIZE_MASK 0x03
248#define PPC7D_CPLD_FLASH_BANK_NUM_MASK 0x0c
249#define PPC7D_CPLD_FLASH_DEV_SIZE_64M 0
250#define PPC7D_CPLD_FLASH_DEV_SIZE_32M 1
251#define PPC7D_CPLD_FLASH_DEV_SIZE_16M 3
252#define PPC7D_CPLD_FLASH_BANK_NUM_4 0x00
253#define PPC7D_CPLD_FLASH_BANK_NUM_3 0x04
254#define PPC7D_CPLD_FLASH_BANK_NUM_2 0x08
255#define PPC7D_CPLD_FLASH_BANK_NUM_1 0x0c
256
257/* SCSI_LED */
258#define PPC7D_CPLD_SCSI_ACTIVITY_LED_OFF 0
259#define PPC7D_CPLD_SCSI_ACTIVITY_LED_ON 1
260
261/* EQUIPMENT_PRESENT_1 */
262#define PPC7D_CPLD_EQPT_PRES_1_FITTED 0
263#define PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK (0x80 >> 2)
264#define PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK (0x80 >> 3)
265#define PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK (0x80 >> 4)
266
267/* EQUIPMENT_PRESENT_2 */
268#define PPC7D_CPLD_EQPT_PRES_2_FITTED !0
269#define PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK (0x80 >> 0)
270#define PPC7D_CPLD_EQPT_PRES_2_COM36_MASK (0x80 >> 2)
271#define PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK (0x80 >> 3)
272#define PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK (0x80 >> 4)
273
274/* EQUIPMENT_PRESENT_3 */
275#define PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK (0x80 >> 3)
276#define PPC7D_CPLD_EQPT_PRES_3_PMC2_5V (0 >> 3)
277#define PPC7D_CPLD_EQPT_PRES_3_PMC2_3V (0x80 >> 3)
278#define PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK (0x80 >> 4)
279#define PPC7D_CPLD_EQPT_PRES_3_PMC1_5V (0 >> 4)
280#define PPC7D_CPLD_EQPT_PRES_3_PMC1_3V (0x80 >> 4)
281#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK (0x80 >> 5)
282#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_INTER (0 >> 5)
283#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_VME (0x80 >> 5)
284
285/* EQUIPMENT_PRESENT_4 */
286#define PPC7D_CPLD_EQPT_PRES_4_LPT_MASK (0x80 >> 2)
287#define PPC7D_CPLD_EQPT_PRES_4_LPT_FITTED (0x80 >> 2)
288#define PPC7D_CPLD_EQPT_PRES_4_PS2_USB2_MASK (0xc0 >> 6)
289#define PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED (0x40 >> 6)
290#define PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED (0x80 >> 6)
291
292/* CPLD_LEDS */
293#define PPC7D_CPLD_LEDS_ON (!0)
294#define PPC7D_CPLD_LEDS_OFF (0)
295#define PPC7D_CPLD_LEDS_NVRAM_PAGE_MASK (0xc0 >> 2)
296#define PPC7D_CPLD_LEDS_DS201_MASK (0x80 >> 4)
297#define PPC7D_CPLD_LEDS_DS219_MASK (0x80 >> 5)
298#define PPC7D_CPLD_LEDS_DS220_MASK (0x80 >> 6)
299#define PPC7D_CPLD_LEDS_DS221_MASK (0x80 >> 7)
300
301/* CPLD_COMS */
302#define PPC7D_CPLD_COMS_COM3_TCLKEN (0x80 >> 0)
303#define PPC7D_CPLD_COMS_COM3_RTCLKEN (0x80 >> 1)
304#define PPC7D_CPLD_COMS_COM3_MODE_MASK (0x80 >> 2)
305#define PPC7D_CPLD_COMS_COM3_MODE_RS232 (0)
306#define PPC7D_CPLD_COMS_COM3_MODE_RS422 (0x80 >> 2)
307#define PPC7D_CPLD_COMS_COM3_TXEN (0x80 >> 3)
308#define PPC7D_CPLD_COMS_COM4_TCLKEN (0x80 >> 4)
309#define PPC7D_CPLD_COMS_COM4_RTCLKEN (0x80 >> 5)
310#define PPC7D_CPLD_COMS_COM4_MODE_MASK (0x80 >> 6)
311#define PPC7D_CPLD_COMS_COM4_MODE_RS232 (0)
312#define PPC7D_CPLD_COMS_COM4_MODE_RS422 (0x80 >> 6)
313#define PPC7D_CPLD_COMS_COM4_TXEN (0x80 >> 7)
314
315/* CPLD_RTS */
316#define PPC7D_CPLD_RTS_COM36_LOOPBACK (0x80 >> 0)
317#define PPC7D_CPLD_RTS_COM4_SCLK (0x80 >> 1)
318#define PPC7D_CPLD_RTS_COM3_TXFUNC_MASK (0xc0 >> 2)
319#define PPC7D_CPLD_RTS_COM3_TXFUNC_DISABLED (0 >> 2)
320#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED (0x80 >> 2)
321#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3 (0xc0 >> 2)
322#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3S (0xc0 >> 2)
323#define PPC7D_CPLD_RTS_COM56_MODE_MASK (0x80 >> 4)
324#define PPC7D_CPLD_RTS_COM56_MODE_RS232 (0)
325#define PPC7D_CPLD_RTS_COM56_MODE_RS422 (0x80 >> 4)
326#define PPC7D_CPLD_RTS_COM56_ENABLE_MASK (0x80 >> 5)
327#define PPC7D_CPLD_RTS_COM56_DISABLED (0)
328#define PPC7D_CPLD_RTS_COM56_ENABLED (0x80 >> 5)
329#define PPC7D_CPLD_RTS_COM4_TXFUNC_MASK (0xc0 >> 6)
330#define PPC7D_CPLD_RTS_COM4_TXFUNC_DISABLED (0 >> 6)
331#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED (0x80 >> 6)
332#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3 (0x40 >> 6)
333#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3S (0x40 >> 6)
334
335/* WATCHDOG_TRIG */
336#define PPC7D_CPLD_WDOG_CAUSE_MASK (0x80 >> 0)
337#define PPC7D_CPLD_WDOG_CAUSE_NORMAL_RESET (0 >> 0)
338#define PPC7D_CPLD_WDOG_CAUSE_WATCHDOG (0x80 >> 0)
339#define PPC7D_CPLD_WDOG_ENABLE_MASK (0x80 >> 6)
340#define PPC7D_CPLD_WDOG_ENABLE_OFF (0 >> 6)
341#define PPC7D_CPLD_WDOG_ENABLE_ON (0x80 >> 6)
342#define PPC7D_CPLD_WDOG_RESETSW_MASK (0x80 >> 7)
343#define PPC7D_CPLD_WDOG_RESETSW_OFF (0 >> 7)
344#define PPC7D_CPLD_WDOG_RESETSW_ON (0x80 >> 7)
345
346/* Interrupt mask and status bits */
347#define PPC7D_CPLD_INTR_TEMP_MASK (0x80 >> 0)
348#define PPC7D_CPLD_INTR_HB8_MASK (0x80 >> 1)
349#define PPC7D_CPLD_INTR_PHY1_MASK (0x80 >> 2)
350#define PPC7D_CPLD_INTR_PHY0_MASK (0x80 >> 3)
351#define PPC7D_CPLD_INTR_ISANMI_MASK (0x80 >> 5)
352#define PPC7D_CPLD_INTR_CRITTEMP_MASK (0x80 >> 6)
353
354/* CPLD_INTR */
355#define PPC7D_CPLD_INTR_ENABLE_OFF (0)
356#define PPC7D_CPLD_INTR_ENABLE_ON (!0)
357
358/* CPLD_INTR_STATUS */
359#define PPC7D_CPLD_INTR_STATUS_OFF (0)
360#define PPC7D_CPLD_INTR_STATUS_ON (!0)
361
362/* CPLD_PCI_CONFIG */
363#define PPC7D_CPLD_PCI_CONFIG_PCI0_MASK 0x70
364#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI33 0x00
365#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI66 0x10
366#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX33 0x40
367#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX66 0x50
368#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX100 0x60
369#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX133 0x70
370#define PPC7D_CPLD_PCI_CONFIG_PCI1_MASK 0x07
371#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI33 0x00
372#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI66 0x01
373#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX33 0x04
374#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX66 0x05
375#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX100 0x06
376#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX133 0x07
377
378/* CPLD_BOARD_REVISION */
379#define PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK 0xe0
380#define PPC7D_CPLD_BOARD_REVISION_LETTER_MASK 0x1f
381
382/* CPLD_EXTENDED_ID */
383#define PPC7D_CPLD_EXTENDED_ID_PPC7D 0x18
384
385/* CPLD_ID_LINK */
386#define PPC7D_CPLD_ID_LINK_VME64_GAP_MASK (0x80 >> 2)
387#define PPC7D_CPLD_ID_LINK_VME64_GA4_MASK (0x80 >> 3)
388#define PPC7D_CPLD_ID_LINK_E13_MASK (0x80 >> 4)
389#define PPC7D_CPLD_ID_LINK_E12_MASK (0x80 >> 5)
390#define PPC7D_CPLD_ID_LINK_E7_MASK (0x80 >> 6)
391#define PPC7D_CPLD_ID_LINK_E6_MASK (0x80 >> 7)
392
393/* CPLD_MOTHERBOARD_TYPE */
394#define PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK (0x80 >> 0)
395#define PPC7D_CPLD_MB_TYPE_ECC_ENABLED (0x80 >> 0)
396#define PPC7D_CPLD_MB_TYPE_ECC_DISABLED (0 >> 0)
397#define PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK (0x80 >> 3)
398#define PPC7D_CPLD_MB_TYPE_PLL_MASK 0x0c
399#define PPC7D_CPLD_MB_TYPE_PLL_133 0x00
400#define PPC7D_CPLD_MB_TYPE_PLL_100 0x08
401#define PPC7D_CPLD_MB_TYPE_PLL_64 0x04
402#define PPC7D_CPLD_MB_TYPE_HW_ID_MASK 0x03
403
404/* CPLD_FLASH_WRITE_CNTL */
405#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK (0x80 >> 0)
406#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_FITTED (0x80 >> 0)
407#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK (0x80 >> 2)
408#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_FITTED (0x80 >> 2)
409#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK (0x80 >> 3)
410#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_FITTED (0x80 >> 3)
411#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK (0x80 >> 5)
412#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_ENABLED (0x80 >> 5)
413#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK (0x80 >> 6)
414#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_ENABLED (0x80 >> 6)
415#define PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK (0x80 >> 7)
416#define PPD7D_CPLD_FLASH_CNTL_USER_WR_ENABLED (0x80 >> 7)
417
418/* CPLD_SW_FLASH_WRITE_PROTECT */
419#define PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED (!0)
420#define PPC7D_CPLD_SW_FLASH_WRPROT_DISABLED (0)
421#define PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK (0x80 >> 6)
422#define PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK (0x80 >> 7)
423
424/* CPLD_FLASH_WRITE_CNTL */
425#define PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK (0x80 >> 0)
426#define PPC7D_CPLD_FLASH_CNTL_NVRAM_DISABLED (0 >> 0)
427#define PPC7D_CPLD_FLASH_CNTL_NVRAM_ENABLED (0x80 >> 0)
428#define PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK (0x80 >> 1)
429#define PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK (0x80 >> 2)
430#define PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK (0x80 >> 3)
431
432
433#endif /* __PPC_PLATFORMS_PPC7D_H */
diff --git a/arch/ppc/platforms/residual.c b/arch/ppc/platforms/residual.c
deleted file mode 100644
index d687b0f8763b..000000000000
--- a/arch/ppc/platforms/residual.c
+++ /dev/null
@@ -1,1034 +0,0 @@
1/*
2 * Code to deal with the PReP residual data.
3 *
4 * Written by: Cort Dougan (cort@cs.nmt.edu)
5 * Improved _greatly_ and rewritten by Gabriel Paubert (paubert@iram.es)
6 *
7 * This file is based on the following documentation:
8 *
9 * IBM Power Personal Systems Architecture
10 * Residual Data
11 * Document Number: PPS-AR-FW0001
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file COPYING in the main directory of this archive
15 * for more details.
16 *
17 */
18
19#include <linux/string.h>
20#include <asm/residual.h>
21#include <asm/pnp.h>
22#include <asm/byteorder.h>
23
24#include <linux/errno.h>
25#include <linux/sched.h>
26#include <linux/kernel.h>
27#include <linux/mm.h>
28#include <linux/stddef.h>
29#include <linux/unistd.h>
30#include <linux/ptrace.h>
31#include <linux/slab.h>
32#include <linux/user.h>
33#include <linux/a.out.h>
34#include <linux/tty.h>
35#include <linux/major.h>
36#include <linux/interrupt.h>
37#include <linux/reboot.h>
38#include <linux/init.h>
39#include <linux/ioport.h>
40#include <linux/pci.h>
41#include <linux/proc_fs.h>
42
43#include <asm/sections.h>
44#include <asm/mmu.h>
45#include <asm/io.h>
46#include <asm/pgtable.h>
47#include <asm/ide.h>
48
49
50unsigned char __res[sizeof(RESIDUAL)] = {0,};
51RESIDUAL *res = (RESIDUAL *)&__res;
52
53char * PnP_BASE_TYPES[] __initdata = {
54 "Reserved",
55 "MassStorageDevice",
56 "NetworkInterfaceController",
57 "DisplayController",
58 "MultimediaController",
59 "MemoryController",
60 "BridgeController",
61 "CommunicationsDevice",
62 "SystemPeripheral",
63 "InputDevice",
64 "ServiceProcessor"
65 };
66
67/* Device Sub Type Codes */
68
69unsigned char * PnP_SUB_TYPES[] __initdata = {
70 "\001\000SCSIController",
71 "\001\001IDEController",
72 "\001\002FloppyController",
73 "\001\003IPIController",
74 "\001\200OtherMassStorageController",
75 "\002\000EthernetController",
76 "\002\001TokenRingController",
77 "\002\002FDDIController",
78 "\002\0x80OtherNetworkController",
79 "\003\000VGAController",
80 "\003\001SVGAController",
81 "\003\002XGAController",
82 "\003\200OtherDisplayController",
83 "\004\000VideoController",
84 "\004\001AudioController",
85 "\004\200OtherMultimediaController",
86 "\005\000RAM",
87 "\005\001FLASH",
88 "\005\200OtherMemoryDevice",
89 "\006\000HostProcessorBridge",
90 "\006\001ISABridge",
91 "\006\002EISABridge",
92 "\006\003MicroChannelBridge",
93 "\006\004PCIBridge",
94 "\006\005PCMCIABridge",
95 "\006\006VMEBridge",
96 "\006\200OtherBridgeDevice",
97 "\007\000RS232Device",
98 "\007\001ATCompatibleParallelPort",
99 "\007\200OtherCommunicationsDevice",
100 "\010\000ProgrammableInterruptController",
101 "\010\001DMAController",
102 "\010\002SystemTimer",
103 "\010\003RealTimeClock",
104 "\010\004L2Cache",
105 "\010\005NVRAM",
106 "\010\006PowerManagement",
107 "\010\007CMOS",
108 "\010\010OperatorPanel",
109 "\010\011ServiceProcessorClass1",
110 "\010\012ServiceProcessorClass2",
111 "\010\013ServiceProcessorClass3",
112 "\010\014GraphicAssist",
113 "\010\017SystemPlanar",
114 "\010\200OtherSystemPeripheral",
115 "\011\000KeyboardController",
116 "\011\001Digitizer",
117 "\011\002MouseController",
118 "\011\003TabletController",
119 "\011\0x80OtherInputController",
120 "\012\000GeneralMemoryController",
121 NULL
122};
123
124/* Device Interface Type Codes */
125
126unsigned char * PnP_INTERFACES[] __initdata = {
127 "\000\000\000General",
128 "\001\000\000GeneralSCSI",
129 "\001\001\000GeneralIDE",
130 "\001\001\001ATACompatible",
131
132 "\001\002\000GeneralFloppy",
133 "\001\002\001Compatible765",
134 "\001\002\002NS398_Floppy", /* NS Super I/O wired to use index
135 register at port 398 and data
136 register at port 399 */
137 "\001\002\003NS26E_Floppy", /* Ports 26E and 26F */
138 "\001\002\004NS15C_Floppy", /* Ports 15C and 15D */
139 "\001\002\005NS2E_Floppy", /* Ports 2E and 2F */
140 "\001\002\006CHRP_Floppy", /* CHRP Floppy in PR*P system */
141
142 "\001\003\000GeneralIPI",
143
144 "\002\000\000GeneralEther",
145 "\002\001\000GeneralToken",
146 "\002\002\000GeneralFDDI",
147
148 "\003\000\000GeneralVGA",
149 "\003\001\000GeneralSVGA",
150 "\003\002\000GeneralXGA",
151
152 "\004\000\000GeneralVideo",
153 "\004\001\000GeneralAudio",
154 "\004\001\001CS4232Audio", /* CS 4232 Plug 'n Play Configured */
155
156 "\005\000\000GeneralRAM",
157 /* This one is obviously wrong ! */
158 "\005\000\000PCIMemoryController", /* PCI Config Method */
159 "\005\000\001RS6KMemoryController", /* RS6K Config Method */
160 "\005\001\000GeneralFLASH",
161
162 "\006\000\000GeneralHostBridge",
163 "\006\001\000GeneralISABridge",
164 "\006\002\000GeneralEISABridge",
165 "\006\003\000GeneralMCABridge",
166 /* GeneralPCIBridge = 0, */
167 "\006\004\000PCIBridgeDirect",
168 "\006\004\001PCIBridgeIndirect",
169 "\006\004\002PCIBridgeRS6K",
170 "\006\005\000GeneralPCMCIABridge",
171 "\006\006\000GeneralVMEBridge",
172
173 "\007\000\000GeneralRS232",
174 "\007\000\001COMx",
175 "\007\000\002Compatible16450",
176 "\007\000\003Compatible16550",
177 "\007\000\004NS398SerPort", /* NS Super I/O wired to use index
178 register at port 398 and data
179 register at port 399 */
180 "\007\000\005NS26ESerPort", /* Ports 26E and 26F */
181 "\007\000\006NS15CSerPort", /* Ports 15C and 15D */
182 "\007\000\007NS2ESerPort", /* Ports 2E and 2F */
183
184 "\007\001\000GeneralParPort",
185 "\007\001\001LPTx",
186 "\007\001\002NS398ParPort", /* NS Super I/O wired to use index
187 register at port 398 and data
188 register at port 399 */
189 "\007\001\003NS26EParPort", /* Ports 26E and 26F */
190 "\007\001\004NS15CParPort", /* Ports 15C and 15D */
191 "\007\001\005NS2EParPort", /* Ports 2E and 2F */
192
193 "\010\000\000GeneralPIC",
194 "\010\000\001ISA_PIC",
195 "\010\000\002EISA_PIC",
196 "\010\000\003MPIC",
197 "\010\000\004RS6K_PIC",
198
199 "\010\001\000GeneralDMA",
200 "\010\001\001ISA_DMA",
201 "\010\001\002EISA_DMA",
202
203 "\010\002\000GeneralTimer",
204 "\010\002\001ISA_Timer",
205 "\010\002\002EISA_Timer",
206 "\010\003\000GeneralRTC",
207 "\010\003\001ISA_RTC",
208
209 "\010\004\001StoreThruOnly",
210 "\010\004\002StoreInEnabled",
211 "\010\004\003RS6KL2Cache",
212
213 "\010\005\000IndirectNVRAM", /* Indirectly addressed */
214 "\010\005\001DirectNVRAM", /* Memory Mapped */
215 "\010\005\002IndirectNVRAM24", /* Indirectly addressed - 24 bit */
216
217 "\010\006\000GeneralPowerManagement",
218 "\010\006\001EPOWPowerManagement",
219 "\010\006\002PowerControl", // d1378
220
221 "\010\007\000GeneralCMOS",
222
223 "\010\010\000GeneralOPPanel",
224 "\010\010\001HarddiskLight",
225 "\010\010\002CDROMLight",
226 "\010\010\003PowerLight",
227 "\010\010\004KeyLock",
228 "\010\010\005ANDisplay", /* AlphaNumeric Display */
229 "\010\010\006SystemStatusLED", /* 3 digit 7 segment LED */
230 "\010\010\007CHRP_SystemStatusLED", /* CHRP LEDs in PR*P system */
231
232 "\010\011\000GeneralServiceProcessor",
233 "\010\012\000GeneralServiceProcessor",
234 "\010\013\000GeneralServiceProcessor",
235
236 "\010\014\001TransferData",
237 "\010\014\002IGMC32",
238 "\010\014\003IGMC64",
239
240 "\010\017\000GeneralSystemPlanar", /* 10/5/95 */
241 NULL
242 };
243
244static const unsigned char __init *PnP_SUB_TYPE_STR(unsigned char BaseType,
245 unsigned char SubType) {
246 unsigned char ** s=PnP_SUB_TYPES;
247 while (*s && !((*s)[0]==BaseType
248 && (*s)[1]==SubType)) s++;
249 if (*s) return *s+2;
250 else return("Unknown !");
251};
252
253static const unsigned char __init *PnP_INTERFACE_STR(unsigned char BaseType,
254 unsigned char SubType,
255 unsigned char Interface) {
256 unsigned char ** s=PnP_INTERFACES;
257 while (*s && !((*s)[0]==BaseType
258 && (*s)[1]==SubType
259 && (*s)[2]==Interface)) s++;
260 if (*s) return *s+3;
261 else return NULL;
262};
263
264static void __init printsmallvendor(PnP_TAG_PACKET *pkt, int size) {
265 int i, c;
266 char decomp[4];
267#define p pkt->S14_Pack.S14_Data.S14_PPCPack
268 switch(p.Type) {
269 case 1:
270 /* Decompress first 3 chars */
271 c = *(unsigned short *)p.PPCData;
272 decomp[0]='A'-1+((c>>10)&0x1F);
273 decomp[1]='A'-1+((c>>5)&0x1F);
274 decomp[2]='A'-1+(c&0x1F);
275 decomp[3]=0;
276 printk(" Chip identification: %s%4.4X\n",
277 decomp, ld_le16((unsigned short *)(p.PPCData+2)));
278 break;
279 default:
280 printk(" Small vendor item type 0x%2.2x, data (hex): ",
281 p.Type);
282 for(i=0; i<size-2; i++) printk("%2.2x ", p.PPCData[i]);
283 printk("\n");
284 break;
285 }
286#undef p
287}
288
289static void __init printsmallpacket(PnP_TAG_PACKET * pkt, int size) {
290 static const unsigned char * intlevel[] = {"high", "low"};
291 static const unsigned char * intsense[] = {"edge", "level"};
292
293 switch (tag_small_item_name(pkt->S1_Pack.Tag)) {
294 case PnPVersion:
295 printk(" PnPversion 0x%x.%x\n",
296 pkt->S1_Pack.Version[0], /* How to interpret version ? */
297 pkt->S1_Pack.Version[1]);
298 break;
299// case Logicaldevice:
300 break;
301// case CompatibleDevice:
302 break;
303 case IRQFormat:
304#define p pkt->S4_Pack
305 printk(" IRQ Mask 0x%4.4x, %s %s sensitive\n",
306 ld_le16((unsigned short *)p.IRQMask),
307 intlevel[(size>3) ? !(p.IRQInfo&0x05) : 0],
308 intsense[(size>3) ? !(p.IRQInfo&0x03) : 0]);
309#undef p
310 break;
311 case DMAFormat:
312#define p pkt->S5_Pack
313 printk(" DMA channel mask 0x%2.2x, info 0x%2.2x\n",
314 p.DMAMask, p.DMAInfo);
315#undef p
316 break;
317 case StartDepFunc:
318 printk("Start dependent function:\n");
319 break;
320 case EndDepFunc:
321 printk("End dependent function\n");
322 break;
323 case IOPort:
324#define p pkt->S8_Pack
325 printk(" Variable (%d decoded bits) I/O port\n"
326 " from 0x%4.4x to 0x%4.4x, alignment %d, %d ports\n",
327 p.IOInfo&ISAAddr16bit?16:10,
328 ld_le16((unsigned short *)p.RangeMin),
329 ld_le16((unsigned short *)p.RangeMax),
330 p.IOAlign, p.IONum);
331#undef p
332 break;
333 case FixedIOPort:
334#define p pkt->S9_Pack
335 printk(" Fixed (10 decoded bits) I/O port from %3.3x to %3.3x\n",
336 (p.Range[1]<<8)|p.Range[0],
337 ((p.Range[1]<<8)|p.Range[0])+p.IONum-1);
338#undef p
339 break;
340 case Res1:
341 case Res2:
342 case Res3:
343 printk(" Undefined packet type %d!\n",
344 tag_small_item_name(pkt->S1_Pack.Tag));
345 break;
346 case SmallVendorItem:
347 printsmallvendor(pkt,size);
348 break;
349 default:
350 printk(" Type 0x2.2x%d, size=%d\n",
351 pkt->S1_Pack.Tag, size);
352 break;
353 }
354}
355
356static void __init printlargevendor(PnP_TAG_PACKET * pkt, int size) {
357 static const unsigned char * addrtype[] = {"I/O", "Memory", "System"};
358 static const unsigned char * inttype[] = {"8259", "MPIC", "RS6k BUID %d"};
359 static const unsigned char * convtype[] = {"Bus Memory", "Bus I/O", "DMA"};
360 static const unsigned char * transtype[] = {"direct", "mapped", "direct-store segment"};
361 static const unsigned char * L2type[] = {"WriteThru", "CopyBack"};
362 static const unsigned char * L2assoc[] = {"DirectMapped", "2-way set"};
363
364 int i;
365 char tmpstr[30], *t;
366#define p pkt->L4_Pack.L4_Data.L4_PPCPack
367 switch(p.Type) {
368 case 2:
369 printk(" %d K %s %s L2 cache, %d/%d bytes line/sector size\n",
370 ld_le32((unsigned int *)p.PPCData),
371 L2type[p.PPCData[10]-1],
372 L2assoc[p.PPCData[4]-1],
373 ld_le16((unsigned short *)p.PPCData+3),
374 ld_le16((unsigned short *)p.PPCData+4));
375 break;
376 case 3:
377 printk(" PCI Bridge parameters\n"
378 " ConfigBaseAddress %0x\n"
379 " ConfigBaseData %0x\n"
380 " Bus number %d\n",
381 ld_le32((unsigned int *)p.PPCData),
382 ld_le32((unsigned int *)(p.PPCData+8)),
383 p.PPCData[16]);
384 for(i=20; i<size-4; i+=12) {
385 int j, first;
386 if(p.PPCData[i]) printk(" PCI Slot %d", p.PPCData[i]);
387 else printk (" Integrated PCI device");
388 for(j=0, first=1, t=tmpstr; j<4; j++) {
389 int line=ld_le16((unsigned short *)(p.PPCData+i+4)+j);
390 if(line!=0xffff){
391 if(first) first=0; else *t++='/';
392 *t++='A'+j;
393 }
394 }
395 *t='\0';
396 printk(" DevFunc 0x%x interrupt line(s) %s routed to",
397 p.PPCData[i+1],tmpstr);
398 sprintf(tmpstr,
399 inttype[p.PPCData[i+2]-1],
400 p.PPCData[i+3]);
401 printk(" %s line(s) ",
402 tmpstr);
403 for(j=0, first=1, t=tmpstr; j<4; j++) {
404 int line=ld_le16((unsigned short *)(p.PPCData+i+4)+j);
405 if(line!=0xffff){
406 if(first) first=0; else *t++='/';
407 t+=sprintf(t,"%d(%c)",
408 line&0x7fff,
409 line&0x8000?'E':'L');
410 }
411 }
412 printk("%s\n",tmpstr);
413 }
414 break;
415 case 5:
416 printk(" Bridge address translation, %s decoding:\n"
417 " Processor Bus Size Conversion Translation\n"
418 " 0x%8.8x 0x%8.8x 0x%8.8x %s %s\n",
419 p.PPCData[0]&1 ? "positive" : "subtractive",
420 ld_le32((unsigned int *)p.PPCData+1),
421 ld_le32((unsigned int *)p.PPCData+3),
422 ld_le32((unsigned int *)p.PPCData+5),
423 convtype[p.PPCData[2]-1],
424 transtype[p.PPCData[1]-1]);
425 break;
426 case 6:
427 printk(" Bus speed %d Hz, %d slot(s)\n",
428 ld_le32((unsigned int *)p.PPCData),
429 p.PPCData[4]);
430 break;
431 case 7:
432 printk(" SCSI buses: %d, id(s):", p.PPCData[0]);
433 for(i=1; i<=p.PPCData[0]; i++)
434 printk(" %d%c", p.PPCData[i], i==p.PPCData[0] ? '\n' : ',');
435 break;
436 case 9:
437 printk(" %s address (%d bits), at 0x%x size 0x%x bytes\n",
438 addrtype[p.PPCData[0]-1],
439 p.PPCData[1],
440 ld_le32((unsigned int *)(p.PPCData+4)),
441 ld_le32((unsigned int *)(p.PPCData+12)));
442 break;
443 case 10:
444 sprintf(tmpstr,
445 inttype[p.PPCData[0]-1],
446 p.PPCData[1]);
447
448 printk(" ISA interrupts routed to %s\n"
449 " lines",
450 tmpstr);
451 for(i=0; i<16; i++) {
452 int line=ld_le16((unsigned short *)p.PPCData+i+1);
453 if (line!=0xffff) printk(" %d(IRQ%d)", line, i);
454 }
455 printk("\n");
456 break;
457 default:
458 printk(" Large vendor item type 0x%2.2x\n Data (hex):",
459 p.Type);
460 for(i=0; i<size-4; i++) printk(" %2.2x", p.PPCData[i]);
461 printk("\n");
462#undef p
463 }
464}
465
466static void __init printlargepacket(PnP_TAG_PACKET * pkt, int size) {
467 switch (tag_large_item_name(pkt->S1_Pack.Tag)) {
468 case LargeVendorItem:
469 printlargevendor(pkt, size);
470 break;
471 default:
472 printk(" Type 0x2.2x%d, size=%d\n",
473 pkt->S1_Pack.Tag, size);
474 break;
475 }
476}
477
478static void __init printpackets(PnP_TAG_PACKET * pkt, const char * cat)
479{
480 if (pkt->S1_Pack.Tag== END_TAG) {
481 printk(" No packets describing %s resources.\n", cat);
482 return;
483 }
484 printk( " Packets describing %s resources:\n",cat);
485 do {
486 int size;
487 if (tag_type(pkt->S1_Pack.Tag)) {
488 size= 3 +
489 pkt->L1_Pack.Count0 +
490 pkt->L1_Pack.Count1*256;
491 printlargepacket(pkt, size);
492 } else {
493 size=tag_small_count(pkt->S1_Pack.Tag)+1;
494 printsmallpacket(pkt, size);
495 }
496 pkt = (PnP_TAG_PACKET *)((unsigned char *) pkt + size);
497 } while (pkt->S1_Pack.Tag != END_TAG);
498}
499
500void __init print_residual_device_info(void)
501{
502 int i;
503 PPC_DEVICE *dev;
504#define did dev->DeviceId
505
506 /* make sure we have residual data first */
507 if (!have_residual_data)
508 return;
509
510 printk("Residual: %ld devices\n", res->ActualNumDevices);
511 for ( i = 0;
512 i < res->ActualNumDevices ;
513 i++)
514 {
515 char decomp[4], sn[20];
516 const char * s;
517 dev = &res->Devices[i];
518 s = PnP_INTERFACE_STR(did.BaseType, did.SubType,
519 did.Interface);
520 if(!s) {
521 sprintf(sn, "interface %d", did.Interface);
522 s=sn;
523 }
524 if ( did.BusId & PCIDEVICE )
525 printk("PCI Device, Bus %d, DevFunc 0x%x:",
526 dev->BusAccess.PCIAccess.BusNumber,
527 dev->BusAccess.PCIAccess.DevFuncNumber);
528 if ( did.BusId & PNPISADEVICE ) printk("PNPISA Device:");
529 if ( did.BusId & ISADEVICE )
530 printk("ISA Device, Slot %d, LogicalDev %d:",
531 dev->BusAccess.ISAAccess.SlotNumber,
532 dev->BusAccess.ISAAccess.LogicalDevNumber);
533 if ( did.BusId & EISADEVICE ) printk("EISA Device:");
534 if ( did.BusId & PROCESSORDEVICE )
535 printk("ProcBus Device, Bus %d, BUID %d: ",
536 dev->BusAccess.ProcBusAccess.BusNumber,
537 dev->BusAccess.ProcBusAccess.BUID);
538 if ( did.BusId & PCMCIADEVICE ) printk("PCMCIA ");
539 if ( did.BusId & VMEDEVICE ) printk("VME ");
540 if ( did.BusId & MCADEVICE ) printk("MCA ");
541 if ( did.BusId & MXDEVICE ) printk("MX ");
542 /* Decompress first 3 chars */
543 decomp[0]='A'-1+((did.DevId>>26)&0x1F);
544 decomp[1]='A'-1+((did.DevId>>21)&0x1F);
545 decomp[2]='A'-1+((did.DevId>>16)&0x1F);
546 decomp[3]=0;
547 printk(" %s%4.4lX, %s, %s, %s\n",
548 decomp, did.DevId&0xffff,
549 PnP_BASE_TYPES[did.BaseType],
550 PnP_SUB_TYPE_STR(did.BaseType,did.SubType),
551 s);
552 if ( dev->AllocatedOffset )
553 printpackets( (union _PnP_TAG_PACKET *)
554 &res->DevicePnPHeap[dev->AllocatedOffset],
555 "allocated");
556 if ( dev->PossibleOffset )
557 printpackets( (union _PnP_TAG_PACKET *)
558 &res->DevicePnPHeap[dev->PossibleOffset],
559 "possible");
560 if ( dev->CompatibleOffset )
561 printpackets( (union _PnP_TAG_PACKET *)
562 &res->DevicePnPHeap[dev->CompatibleOffset],
563 "compatible");
564 }
565}
566
567
568#if 0
569static void __init printVPD(void) {
570#define vpd res->VitalProductData
571 int ps=vpd.PageSize, i, j;
572 static const char* Usage[]={
573 "FirmwareStack", "FirmwareHeap", "FirmwareCode", "BootImage",
574 "Free", "Unpopulated", "ISAAddr", "PCIConfig",
575 "IOMemory", "SystemIO", "SystemRegs", "PCIAddr",
576 "UnPopSystemRom", "SystemROM", "ResumeBlock", "Other"
577 };
578 static const unsigned char *FWMan[]={
579 "IBM", "Motorola", "FirmWorks", "Bull"
580 };
581 static const unsigned char *FWFlags[]={
582 "Conventional", "OpenFirmware", "Diagnostics", "LowDebug",
583 "MultiBoot", "LowClient", "Hex41", "FAT",
584 "ISO9660", "SCSI_ID_Override", "Tape_Boot", "FW_Boot_Path"
585 };
586 static const unsigned char *ESM[]={
587 "Port92", "PCIConfigA8", "FF001030", "????????"
588 };
589 static const unsigned char *SIOM[]={
590 "Port850", "????????", "PCIConfigA8", "????????"
591 };
592
593 printk("Model: %s\n",vpd.PrintableModel);
594 printk("Serial: %s\n", vpd.Serial);
595 printk("FirmwareSupplier: %s\n", FWMan[vpd.FirmwareSupplier]);
596 printk("FirmwareFlags:");
597 for(j=0; j<12; j++) {
598 if (vpd.FirmwareSupports & (1<<j)) {
599 printk(" %s%c", FWFlags[j],
600 vpd.FirmwareSupports&(-2<<j) ? ',' : '\n');
601 }
602 }
603 printk("NVRamSize: %ld\n", vpd.NvramSize);
604 printk("SIMMslots: %ld\n", vpd.NumSIMMSlots);
605 printk("EndianSwitchMethod: %s\n",
606 ESM[vpd.EndianSwitchMethod>2 ? 2 : vpd.EndianSwitchMethod]);
607 printk("SpreadIOMethod: %s\n",
608 SIOM[vpd.SpreadIOMethod>3 ? 3 : vpd.SpreadIOMethod]);
609 printk("Processor/Bus frequencies (Hz): %ld/%ld\n",
610 vpd.ProcessorHz, vpd.ProcessorBusHz);
611 printk("Time Base Divisor: %ld\n", vpd.TimeBaseDivisor);
612 printk("WordWidth, PageSize: %ld, %d\n", vpd.WordWidth, ps);
613 printk("Cache sector size, Lock granularity: %ld, %ld\n",
614 vpd.CoherenceBlockSize, vpd.GranuleSize);
615 for (i=0; i<res->ActualNumMemSegs; i++) {
616 int mask=res->Segs[i].Usage, first, j;
617 printk("%8.8lx-%8.8lx ",
618 res->Segs[i].BasePage*ps,
619 (res->Segs[i].PageCount+res->Segs[i].BasePage)*ps-1);
620 for(j=15, first=1; j>=0; j--) {
621 if (mask&(1<<j)) {
622 if (first) first=0;
623 else printk(", ");
624 printk("%s", Usage[j]);
625 }
626 }
627 printk("\n");
628 }
629}
630
631/*
632 * Spit out some info about residual data
633 */
634void print_residual_device_info(void)
635{
636 int i;
637 union _PnP_TAG_PACKET *pkt;
638 PPC_DEVICE *dev;
639#define did dev->DeviceId
640
641 /* make sure we have residual data first */
642 if (!have_residual_data)
643 return;
644 printk("Residual: %ld devices\n", res->ActualNumDevices);
645 for ( i = 0;
646 i < res->ActualNumDevices ;
647 i++)
648 {
649 dev = &res->Devices[i];
650 /*
651 * pci devices
652 */
653 if ( did.BusId & PCIDEVICE )
654 {
655 printk("PCI Device:");
656 /* unknown vendor */
657 if ( !strncmp( "Unknown", pci_strvendor(did.DevId>>16), 7) )
658 printk(" id %08lx types %d/%d", did.DevId,
659 did.BaseType, did.SubType);
660 /* known vendor */
661 else
662 printk(" %s %s",
663 pci_strvendor(did.DevId>>16),
664 pci_strdev(did.DevId>>16,
665 did.DevId&0xffff)
666 );
667
668 if ( did.BusId & PNPISADEVICE )
669 {
670 printk(" pnp:");
671 /* get pnp info on the device */
672 pkt = (union _PnP_TAG_PACKET *)
673 &res->DevicePnPHeap[dev->AllocatedOffset];
674 for (; pkt->S1_Pack.Tag != DF_END_TAG;
675 pkt++ )
676 {
677 if ( (pkt->S1_Pack.Tag == S4_Packet) ||
678 (pkt->S1_Pack.Tag == S4_Packet_flags) )
679 printk(" irq %02x%02x",
680 pkt->S4_Pack.IRQMask[0],
681 pkt->S4_Pack.IRQMask[1]);
682 }
683 }
684 printk("\n");
685 continue;
686 }
687 /*
688 * isa devices
689 */
690 if ( did.BusId & ISADEVICE )
691 {
692 printk("ISA Device: basetype: %d subtype: %d",
693 did.BaseType, did.SubType);
694 printk("\n");
695 continue;
696 }
697 /*
698 * eisa devices
699 */
700 if ( did.BusId & EISADEVICE )
701 {
702 printk("EISA Device: basetype: %d subtype: %d",
703 did.BaseType, did.SubType);
704 printk("\n");
705 continue;
706 }
707 /*
708 * proc bus devices
709 */
710 if ( did.BusId & PROCESSORDEVICE )
711 {
712 printk("ProcBus Device: basetype: %d subtype: %d",
713 did.BaseType, did.SubType);
714 printk("\n");
715 continue;
716 }
717 /*
718 * pcmcia devices
719 */
720 if ( did.BusId & PCMCIADEVICE )
721 {
722 printk("PCMCIA Device: basetype: %d subtype: %d",
723 did.BaseType, did.SubType);
724 printk("\n");
725 continue;
726 }
727 printk("Unknown bus access device: busid %lx\n",
728 did.BusId);
729 }
730}
731#endif
732
733/* Returns the device index in the residual data,
734 any of the search items may be set as -1 for wildcard,
735 DevID number field (second halfword) is big endian !
736
737 Examples:
738 - search for the Interrupt controller (8259 type), 2 methods:
739 1) i8259 = residual_find_device(~0,
740 NULL,
741 SystemPeripheral,
742 ProgrammableInterruptController,
743 ISA_PIC,
744 0);
745 2) i8259 = residual_find_device(~0, "PNP0000", -1, -1, -1, 0)
746
747 - search for the first two serial devices, whatever their type)
748 iserial1 = residual_find_device(~0,NULL,
749 CommunicationsDevice,
750 RS232Device,
751 -1, 0)
752 iserial2 = residual_find_device(~0,NULL,
753 CommunicationsDevice,
754 RS232Device,
755 -1, 1)
756 - but search for typical COM1 and COM2 is not easy due to the
757 fact that the interface may be anything and the name "PNP0500" or
758 "PNP0501". Quite bad.
759
760*/
761
762/* devid are easier to uncompress than to compress, so to minimize bloat
763in this rarely used area we unencode and compare */
764
765/* in residual data number is big endian in the device table and
766little endian in the heap, so we use two parameters to avoid writing
767two very similar functions */
768
769static int __init same_DevID(unsigned short vendor,
770 unsigned short Number,
771 char * str)
772{
773 static unsigned const char hexdigit[]="0123456789ABCDEF";
774 if (strlen(str)!=7) return 0;
775 if ( ( ((vendor>>10)&0x1f)+'A'-1 == str[0]) &&
776 ( ((vendor>>5)&0x1f)+'A'-1 == str[1]) &&
777 ( (vendor&0x1f)+'A'-1 == str[2]) &&
778 (hexdigit[(Number>>12)&0x0f] == str[3]) &&
779 (hexdigit[(Number>>8)&0x0f] == str[4]) &&
780 (hexdigit[(Number>>4)&0x0f] == str[5]) &&
781 (hexdigit[Number&0x0f] == str[6]) ) return 1;
782 return 0;
783}
784
785PPC_DEVICE __init *residual_find_device(unsigned long BusMask,
786 unsigned char * DevID,
787 int BaseType,
788 int SubType,
789 int Interface,
790 int n)
791{
792 int i;
793 if (!have_residual_data) return NULL;
794 for (i=0; i<res->ActualNumDevices; i++) {
795#define Dev res->Devices[i].DeviceId
796 if ( (Dev.BusId&BusMask) &&
797 (BaseType==-1 || Dev.BaseType==BaseType) &&
798 (SubType==-1 || Dev.SubType==SubType) &&
799 (Interface==-1 || Dev.Interface==Interface) &&
800 (DevID==NULL || same_DevID((Dev.DevId>>16)&0xffff,
801 Dev.DevId&0xffff, DevID)) &&
802 !(n--) ) return res->Devices+i;
803#undef Dev
804 }
805 return NULL;
806}
807
808PPC_DEVICE __init *residual_find_device_id(unsigned long BusMask,
809 unsigned short DevID,
810 int BaseType,
811 int SubType,
812 int Interface,
813 int n)
814{
815 int i;
816 if (!have_residual_data) return NULL;
817 for (i=0; i<res->ActualNumDevices; i++) {
818#define Dev res->Devices[i].DeviceId
819 if ( (Dev.BusId&BusMask) &&
820 (BaseType==-1 || Dev.BaseType==BaseType) &&
821 (SubType==-1 || Dev.SubType==SubType) &&
822 (Interface==-1 || Dev.Interface==Interface) &&
823 (DevID==0xffff || (Dev.DevId&0xffff) == DevID) &&
824 !(n--) ) return res->Devices+i;
825#undef Dev
826 }
827 return NULL;
828}
829
830static int __init
831residual_scan_pcibridge(PnP_TAG_PACKET * pkt, struct pci_dev *dev)
832{
833 int irq = -1;
834
835#define data pkt->L4_Pack.L4_Data.L4_PPCPack.PPCData
836 if (dev->bus->number == data[16]) {
837 int i, size;
838
839 size = 3 + ld_le16((u_short *) (&pkt->L4_Pack.Count0));
840 for (i = 20; i < size - 4; i += 12) {
841 unsigned char pin;
842 int line_irq;
843
844 if (dev->devfn != data[i + 1])
845 continue;
846
847 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
848 if (pin) {
849 line_irq = ld_le16((unsigned short *)
850 (&data[i + 4 + 2 * (pin - 1)]));
851 irq = (line_irq == 0xffff) ? 0
852 : line_irq & 0x7fff;
853 } else
854 irq = 0;
855
856 break;
857 }
858 }
859#undef data
860
861 return irq;
862}
863
864int __init
865residual_pcidev_irq(struct pci_dev *dev)
866{
867 int i = 0;
868 int irq = -1;
869 PPC_DEVICE *bridge;
870
871 while ((bridge = residual_find_device
872 (-1, NULL, BridgeController, PCIBridge, -1, i++))) {
873
874 PnP_TAG_PACKET *pkt;
875 if (bridge->AllocatedOffset) {
876 pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap +
877 bridge->AllocatedOffset, 3, 0);
878 if (!pkt)
879 continue;
880
881 irq = residual_scan_pcibridge(pkt, dev);
882 if (irq != -1)
883 break;
884 }
885 }
886
887 return (irq < 0) ? 0 : irq;
888}
889
890void __init residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
891{
892 PPC_DEVICE *dev;
893 int i = 0;
894 unsigned short irq_mask = 0x000; /* default to edge */
895
896 while ((dev = residual_find_device(-1, NULL, -1, -1, -1, i++))) {
897 PnP_TAG_PACKET *pkt;
898 unsigned short mask;
899 int size;
900 int offset = dev->AllocatedOffset;
901
902 if (!offset)
903 continue;
904
905 pkt = PnP_find_packet(res->DevicePnPHeap + offset,
906 IRQFormat, 0);
907 if (!pkt)
908 continue;
909
910 size = tag_small_count(pkt->S1_Pack.Tag) + 1;
911 mask = ld_le16((unsigned short *)pkt->S4_Pack.IRQMask);
912 if (size > 3 && (pkt->S4_Pack.IRQInfo & 0x0c))
913 irq_mask |= mask;
914 }
915
916 *irq_edge_mask_lo = irq_mask & 0xff;
917 *irq_edge_mask_hi = irq_mask >> 8;
918}
919
920unsigned int __init residual_isapic_addr(void)
921{
922 PPC_DEVICE *isapic;
923 PnP_TAG_PACKET *pkt;
924 unsigned int addr;
925
926 isapic = residual_find_device(~0, NULL, SystemPeripheral,
927 ProgrammableInterruptController,
928 ISA_PIC, 0);
929 if (!isapic)
930 goto unknown;
931
932 pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap +
933 isapic->AllocatedOffset, 9, 0);
934 if (!pkt)
935 goto unknown;
936
937#define p pkt->L4_Pack.L4_Data.L4_PPCPack
938 /* Must be 32-bit system address */
939 if (!((p.PPCData[0] == 3) && (p.PPCData[1] == 32)))
940 goto unknown;
941
942 /* It doesn't seem to work where length != 1 (what can I say? :-/ ) */
943 if (ld_le32((unsigned int *)(p.PPCData + 12)) != 1)
944 goto unknown;
945
946 addr = ld_le32((unsigned int *) (p.PPCData + 4));
947#undef p
948 return addr;
949unknown:
950 return 0;
951}
952
953PnP_TAG_PACKET *PnP_find_packet(unsigned char *p,
954 unsigned packet_tag,
955 int n)
956{
957 unsigned mask, masked_tag, size;
958 if(!p) return NULL;
959 if (tag_type(packet_tag)) mask=0xff; else mask=0xF8;
960 masked_tag = packet_tag&mask;
961 for(; *p != END_TAG; p+=size) {
962 if ((*p & mask) == masked_tag && !(n--))
963 return (PnP_TAG_PACKET *) p;
964 if (tag_type(*p))
965 size=ld_le16((unsigned short *)(p+1))+3;
966 else
967 size=tag_small_count(*p)+1;
968 }
969 return NULL; /* not found */
970}
971
972PnP_TAG_PACKET __init *PnP_find_small_vendor_packet(unsigned char *p,
973 unsigned packet_type,
974 int n)
975{
976 int next=0;
977 while (p) {
978 p = (unsigned char *) PnP_find_packet(p, 0x70, next);
979 if (p && p[1]==packet_type && !(n--))
980 return (PnP_TAG_PACKET *) p;
981 next = 1;
982 };
983 return NULL; /* not found */
984}
985
986PnP_TAG_PACKET __init *PnP_find_large_vendor_packet(unsigned char *p,
987 unsigned packet_type,
988 int n)
989{
990 int next=0;
991 while (p) {
992 p = (unsigned char *) PnP_find_packet(p, 0x84, next);
993 if (p && p[3]==packet_type && !(n--))
994 return (PnP_TAG_PACKET *) p;
995 next = 1;
996 };
997 return NULL; /* not found */
998}
999
1000#ifdef CONFIG_PROC_PREPRESIDUAL
1001static int proc_prep_residual_read(char * buf, char ** start, off_t off,
1002 int count, int *eof, void *data)
1003{
1004 int n;
1005
1006 n = res->ResidualLength - off;
1007 if (n < 0) {
1008 *eof = 1;
1009 n = 0;
1010 }
1011 else {
1012 if (n > count)
1013 n = count;
1014 else
1015 *eof = 1;
1016
1017 memcpy(buf, (char *)res + off, n);
1018 *start = buf;
1019 }
1020
1021 return n;
1022}
1023
1024int __init
1025proc_prep_residual_init(void)
1026{
1027 if (have_residual_data)
1028 create_proc_read_entry("residual", S_IRUGO, NULL,
1029 proc_prep_residual_read, NULL);
1030 return 0;
1031}
1032
1033__initcall(proc_prep_residual_init);
1034#endif
diff --git a/arch/ppc/platforms/rpx8260.h b/arch/ppc/platforms/rpx8260.h
deleted file mode 100644
index 843494a50ef3..000000000000
--- a/arch/ppc/platforms/rpx8260.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the Embedded Planet RPX6 (or RPX Super) MPC8260 board.
4 * Copied from the RPX-Classic and SBS8260 stuff.
5 *
6 * Copyright (c) 2001 Dan Malek <dan@embeddededge.com>
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_PLATFORMS_RPX8260_H__
10#define __ASM_PLATFORMS_RPX8260_H__
11
12/* A Board Information structure that is given to a program when
13 * prom starts it up.
14 */
15typedef struct bd_info {
16 unsigned int bi_memstart; /* Memory start address */
17 unsigned int bi_memsize; /* Memory (end) size in bytes */
18 unsigned int bi_nvsize; /* NVRAM size in bytes (can be 0) */
19 unsigned int bi_intfreq; /* Internal Freq, in Hz */
20 unsigned int bi_busfreq; /* Bus Freq, in MHz */
21 unsigned int bi_cpmfreq; /* CPM Freq, in MHz */
22 unsigned int bi_brgfreq; /* BRG Freq, in MHz */
23 unsigned int bi_vco; /* VCO Out from PLL */
24 unsigned int bi_baudrate; /* Default console baud rate */
25 unsigned int bi_immr; /* IMMR when called from boot rom */
26 unsigned char bi_enetaddr[6];
27} bd_t;
28
29extern bd_t m8xx_board_info;
30
31/* Memory map is configured by the PROM startup.
32 * We just map a few things we need. The CSR is actually 4 byte-wide
33 * registers that can be accessed as 8-, 16-, or 32-bit values.
34 */
35#define CPM_MAP_ADDR ((uint)0xf0000000)
36#define RPX_CSR_ADDR ((uint)0xfa000000)
37#define RPX_CSR_SIZE ((uint)(512 * 1024))
38#define RPX_NVRTC_ADDR ((uint)0xfa080000)
39#define RPX_NVRTC_SIZE ((uint)(512 * 1024))
40
41/* The RPX6 has 16, byte wide control/status registers.
42 * Not all are used (yet).
43 */
44extern volatile u_char *rpx6_csr_addr;
45
46/* Things of interest in the CSR.
47*/
48#define BCSR0_ID_MASK ((u_char)0xf0) /* Read only */
49#define BCSR0_SWITCH_MASK ((u_char)0x0f) /* Read only */
50#define BCSR1_XCVR_SMC1 ((u_char)0x80)
51#define BCSR1_XCVR_SMC2 ((u_char)0x40)
52#define BCSR2_FLASH_WENABLE ((u_char)0x20)
53#define BCSR2_NVRAM_ENABLE ((u_char)0x10)
54#define BCSR2_ALT_IRQ2 ((u_char)0x08)
55#define BCSR2_ALT_IRQ3 ((u_char)0x04)
56#define BCSR2_PRST ((u_char)0x02) /* Force reset */
57#define BCSR2_ENPRST ((u_char)0x01) /* Enable POR */
58#define BCSR3_MODCLK_MASK ((u_char)0xe0)
59#define BCSR3_ENCLKHDR ((u_char)0x10)
60#define BCSR3_LED5 ((u_char)0x04) /* 0 == on */
61#define BCSR3_LED6 ((u_char)0x02) /* 0 == on */
62#define BCSR3_LED7 ((u_char)0x01) /* 0 == on */
63#define BCSR4_EN_PHY ((u_char)0x80) /* Enable PHY */
64#define BCSR4_EN_MII ((u_char)0x40) /* Enable PHY */
65#define BCSR4_MII_READ ((u_char)0x04)
66#define BCSR4_MII_MDC ((u_char)0x02)
67#define BCSR4_MII_MDIO ((u_char)0x01)
68#define BCSR13_FETH_IRQMASK ((u_char)0xf0)
69#define BCSR15_FETH_IRQ ((u_char)0x20)
70
71#define PHY_INTERRUPT SIU_INT_IRQ7
72
73/* For our show_cpuinfo hooks. */
74#define CPUINFO_VENDOR "Embedded Planet"
75#define CPUINFO_MACHINE "EP8260 PowerPC"
76
77/* Warm reset vector. */
78#define BOOTROM_RESTART_ADDR ((uint)0xfff00104)
79
80#endif /* __ASM_PLATFORMS_RPX8260_H__ */
81#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/rpxclassic.h b/arch/ppc/platforms/rpxclassic.h
deleted file mode 100644
index a3c1118e5b09..000000000000
--- a/arch/ppc/platforms/rpxclassic.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the RPCG RPX-Classic board. Copied from the RPX-Lite stuff.
4 *
5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
6 */
7#ifdef __KERNEL__
8#ifndef __MACH_RPX_DEFS
9#define __MACH_RPX_DEFS
10
11
12#ifndef __ASSEMBLY__
13/* A Board Information structure that is given to a program when
14 * prom starts it up.
15 */
16typedef struct bd_info {
17 unsigned int bi_memstart; /* Memory start address */
18 unsigned int bi_memsize; /* Memory (end) size in bytes */
19 unsigned int bi_intfreq; /* Internal Freq, in Hz */
20 unsigned int bi_busfreq; /* Bus Freq, in Hz */
21 unsigned char bi_enetaddr[6];
22 unsigned int bi_baudrate;
23} bd_t;
24
25extern bd_t m8xx_board_info;
26
27/* Memory map is configured by the PROM startup.
28 * We just map a few things we need. The CSR is actually 4 byte-wide
29 * registers that can be accessed as 8-, 16-, or 32-bit values.
30 */
31#define PCI_ISA_IO_ADDR ((unsigned)0x80000000)
32#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024))
33#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000)
34#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024))
35#define RPX_CSR_ADDR ((uint)0xfa400000)
36#define RPX_CSR_SIZE ((uint)(4 * 1024))
37#define IMAP_ADDR ((uint)0xfa200000)
38#define IMAP_SIZE ((uint)(64 * 1024))
39#define PCI_CSR_ADDR ((uint)0x80000000)
40#define PCI_CSR_SIZE ((uint)(64 * 1024))
41#define PCMCIA_MEM_ADDR ((uint)0xe0000000)
42#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
43#define PCMCIA_IO_ADDR ((uint)0xe4000000)
44#define PCMCIA_IO_SIZE ((uint)(4 * 1024))
45#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000)
46#define PCMCIA_ATTRB_SIZE ((uint)(4 * 1024))
47
48/* Things of interest in the CSR.
49*/
50#define BCSR0_ETHEN ((uint)0x80000000)
51#define BCSR0_ETHLPBK ((uint)0x40000000)
52#define BCSR0_COLTESTDIS ((uint)0x20000000)
53#define BCSR0_FULLDPLXDIS ((uint)0x10000000)
54#define BCSR0_ENFLSHSEL ((uint)0x04000000)
55#define BCSR0_FLASH_SEL ((uint)0x02000000)
56#define BCSR0_ENMONXCVR ((uint)0x01000000)
57
58#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) /* CLLF */
59#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) /* CLLF */
60#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) /* CLLF */
61
62#define BCSR1_IPB5SEL ((uint)0x00100000)
63#define BCSR1_PCVCTL4 ((uint)0x00080000)
64#define BCSR1_PCVCTL5 ((uint)0x00040000)
65#define BCSR1_PCVCTL6 ((uint)0x00020000)
66#define BCSR1_PCVCTL7 ((uint)0x00010000)
67
68#define BCSR2_EN232XCVR ((uint)0x00008000)
69#define BCSR2_QSPACESEL ((uint)0x00004000)
70#define BCSR2_FETHLEDMODE ((uint)0x00000800) /* CLLF */
71
72/* define IO_BASE for pcmcia, CLLF only */
73#if !defined(CONFIG_PCI)
74#define _IO_BASE 0x80000000
75#define _IO_BASE_SIZE 0x1000
76
77/* for pcmcia sandisk */
78#ifdef CONFIG_IDE
79# define MAX_HWIFS 1
80#endif
81#endif
82
83/* Interrupt level assignments.
84*/
85#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
86
87
88/* CPM Ethernet through SCCx.
89 *
90 * Bits in parallel I/O port registers that have to be set/cleared
91 * to configure the pins for SCC1 use.
92 */
93#define PA_ENET_RXD ((ushort)0x0001)
94#define PA_ENET_TXD ((ushort)0x0002)
95#define PA_ENET_TCLK ((ushort)0x0200)
96#define PA_ENET_RCLK ((ushort)0x0800)
97#define PB_ENET_TENA ((uint)0x00001000)
98#define PC_ENET_CLSN ((ushort)0x0010)
99#define PC_ENET_RENA ((ushort)0x0020)
100
101/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
102 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
103 */
104#define SICR_ENET_MASK ((uint)0x000000ff)
105#define SICR_ENET_CLKRT ((uint)0x0000003d)
106
107/* We don't use the 8259.
108*/
109
110#define NR_8259_INTS 0
111
112#endif /* !__ASSEMBLY__ */
113#endif /* __MACH_RPX_DEFS */
114#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/rpxlite.h b/arch/ppc/platforms/rpxlite.h
deleted file mode 100644
index b615501d55fc..000000000000
--- a/arch/ppc/platforms/rpxlite.h
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the RPCG RPX-Lite board. Copied from the MBX stuff.
4 *
5 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
6 */
7#ifdef __KERNEL__
8#ifndef __MACH_RPX_DEFS
9#define __MACH_RPX_DEFS
10
11
12#ifndef __ASSEMBLY__
13/* A Board Information structure that is given to a program when
14 * prom starts it up.
15 */
16typedef struct bd_info {
17 unsigned int bi_memstart; /* Memory start address */
18 unsigned int bi_memsize; /* Memory (end) size in bytes */
19 unsigned int bi_intfreq; /* Internal Freq, in Hz */
20 unsigned int bi_busfreq; /* Bus Freq, in Hz */
21 unsigned char bi_enetaddr[6];
22 unsigned int bi_baudrate;
23} bd_t;
24
25extern bd_t m8xx_board_info;
26
27/* Memory map is configured by the PROM startup.
28 * We just map a few things we need. The CSR is actually 4 byte-wide
29 * registers that can be accessed as 8-, 16-, or 32-bit values.
30 */
31#define RPX_CSR_ADDR ((uint)0xfa400000)
32#define RPX_CSR_SIZE ((uint)(4 * 1024))
33#define IMAP_ADDR ((uint)0xfa200000)
34#define IMAP_SIZE ((uint)(64 * 1024))
35#define PCMCIA_MEM_ADDR ((uint)0x04000000)
36#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
37#define PCMCIA_IO_ADDR ((uint)0x04400000)
38#define PCMCIA_IO_SIZE ((uint)(4 * 1024))
39
40/* Things of interest in the CSR.
41*/
42#define BCSR0_ETHEN ((uint)0x80000000)
43#define BCSR0_ETHLPBK ((uint)0x40000000)
44#define BCSR0_COLTESTDIS ((uint)0x20000000)
45#define BCSR0_FULLDPLXDIS ((uint)0x10000000)
46#define BCSR0_LEDOFF ((uint)0x08000000)
47#define BCSR0_USBDISABLE ((uint)0x04000000)
48#define BCSR0_USBHISPEED ((uint)0x02000000)
49#define BCSR0_USBPWREN ((uint)0x01000000)
50#define BCSR0_PCMCIAVOLT ((uint)0x000f0000)
51#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000)
52#define BCSR0_PCMCIA5VOLT ((uint)0x00060000)
53
54#define BCSR1_IPB5SEL ((uint)0x00100000)
55#define BCSR1_PCVCTL4 ((uint)0x00080000)
56#define BCSR1_PCVCTL5 ((uint)0x00040000)
57#define BCSR1_PCVCTL6 ((uint)0x00020000)
58#define BCSR1_PCVCTL7 ((uint)0x00010000)
59
60/* define IO_BASE for pcmcia */
61#define _IO_BASE 0x80000000
62#define _IO_BASE_SIZE 0x1000
63
64#ifdef CONFIG_IDE
65# define MAX_HWIFS 1
66#endif
67
68/* CPM Ethernet through SCCx.
69 *
70 * This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
71 * this may be unique to the RPX-Lite configuration.
72 * Note TENA is on Port B.
73 */
74#define PA_ENET_RXD ((ushort)0x0004)
75#define PA_ENET_TXD ((ushort)0x0008)
76#define PA_ENET_TCLK ((ushort)0x0200)
77#define PA_ENET_RCLK ((ushort)0x0800)
78#define PB_ENET_TENA ((uint)0x00002000)
79#define PC_ENET_CLSN ((ushort)0x0040)
80#define PC_ENET_RENA ((ushort)0x0080)
81
82#define SICR_ENET_MASK ((uint)0x0000ff00)
83#define SICR_ENET_CLKRT ((uint)0x00003d00)
84
85/* We don't use the 8259.
86*/
87#define NR_8259_INTS 0
88
89#endif /* !__ASSEMBLY__ */
90#endif /* __MACH_RPX_DEFS */
91#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c
deleted file mode 100644
index b4897bdb742a..000000000000
--- a/arch/ppc/platforms/sandpoint.c
+++ /dev/null
@@ -1,651 +0,0 @@
1/*
2 * Board setup routines for the Motorola SPS Sandpoint Test Platform.
3 *
4 * Author: Mark A. Greer
5 * mgreer@mvista.com
6 *
7 * 2000-2003 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * This file adds support for the Motorola SPS Sandpoint Test Platform.
15 * These boards have a PPMC slot for the processor so any combination
16 * of cpu and host bridge can be attached. This port is for an 8240 PPMC
17 * module from Motorola SPS and other closely related cpu/host bridge
18 * combinations (e.g., 750/755/7400 with MPC107 host bridge).
19 * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
20 * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
21 * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
22 * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
23 * but are really 5V).
24 *
25 * The firmware on the sandpoint is called DINK (not my acronym :). This port
26 * depends on DINK to do some basic initialization (e.g., initialize the memory
27 * ctlr) and to ensure that the processor is using MAP B (CHRP map).
28 *
29 * The switch settings for the Sandpoint board MUST be as follows:
30 * S3: down
31 * S4: up
32 * S5: up
33 * S6: down
34 *
35 * 'down' is in the direction from the PCI slots towards the PPMC slot;
36 * 'up' is in the direction from the PPMC slot towards the PCI slots.
37 * Be careful, the way the sandpoint board is installed in XT chasses will
38 * make the directions reversed.
39 *
40 * Since Motorola listened to our suggestions for improvement, we now have
41 * the Sandpoint X3 board. All of the PCI slots are available, it uses
42 * the serial interrupt interface (just a hardware thing we need to
43 * configure properly).
44 *
45 * Use the default X3 switch settings. The interrupts are then:
46 * EPIC Source
47 * 0 SIOINT (8259, active low)
48 * 1 PCI #1
49 * 2 PCI #2
50 * 3 PCI #3
51 * 4 PCI #4
52 * 7 Winbond INTC (IDE interrupt)
53 * 8 Winbond INTD (IDE interrupt)
54 *
55 *
56 * Motorola has finally released a version of DINK32 that correctly
57 * (seemingly) initializes the memory controller correctly, regardless
58 * of the amount of memory in the system. Once a method of determining
59 * what version of DINK initializes the system for us, if applicable, is
60 * found, we can hopefully stop hardcoding 32MB of RAM.
61 */
62
63#include <linux/stddef.h>
64#include <linux/kernel.h>
65#include <linux/init.h>
66#include <linux/errno.h>
67#include <linux/reboot.h>
68#include <linux/pci.h>
69#include <linux/kdev_t.h>
70#include <linux/major.h>
71#include <linux/initrd.h>
72#include <linux/console.h>
73#include <linux/delay.h>
74#include <linux/seq_file.h>
75#include <linux/root_dev.h>
76#include <linux/serial.h>
77#include <linux/tty.h> /* for linux/serial_core.h */
78#include <linux/serial_core.h>
79#include <linux/serial_8250.h>
80
81#include <asm/system.h>
82#include <asm/pgtable.h>
83#include <asm/page.h>
84#include <asm/time.h>
85#include <asm/dma.h>
86#include <asm/io.h>
87#include <asm/machdep.h>
88#include <asm/prom.h>
89#include <asm/smp.h>
90#include <asm/vga.h>
91#include <asm/open_pic.h>
92#include <asm/i8259.h>
93#include <asm/todc.h>
94#include <asm/bootinfo.h>
95#include <asm/mpc10x.h>
96#include <asm/pci-bridge.h>
97#include <asm/kgdb.h>
98#include <asm/ppc_sys.h>
99
100#include "sandpoint.h"
101
102/* Set non-zero if an X2 Sandpoint detected. */
103static int sandpoint_is_x2;
104
105unsigned char __res[sizeof(bd_t)];
106
107static void sandpoint_halt(void);
108static void sandpoint_probe_type(void);
109
110/*
111 * Define all of the IRQ senses and polarities. Taken from the
112 * Sandpoint X3 User's manual.
113 */
114static u_char sandpoint_openpic_initsenses[] __initdata = {
115 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
116 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
117 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
118 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
119 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
120 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
121 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
122};
123
124/*
125 * Motorola SPS Sandpoint interrupt routing.
126 */
127static inline int
128x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
129{
130 static char pci_irq_table[][4] =
131 /*
132 * PCI IDSEL/INTPIN->INTLINE
133 * A B C D
134 */
135 {
136 { 16, 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */
137 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
138 { 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */
139 { 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */
140 { 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */
141 { 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */
142 };
143
144 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
145 return PCI_IRQ_TABLE_LOOKUP;
146}
147
148static inline int
149x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
150{
151 static char pci_irq_table[][4] =
152 /*
153 * PCI IDSEL/INTPIN->INTLINE
154 * A B C D
155 */
156 {
157 { 18, 0, 0, 0 }, /* IDSEL 11 - i8259 on Windbond */
158 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
159 { 16, 17, 18, 19 }, /* IDSEL 13 - PCI slot 1 */
160 { 17, 18, 19, 16 }, /* IDSEL 14 - PCI slot 2 */
161 { 18, 19, 16, 17 }, /* IDSEL 15 - PCI slot 3 */
162 { 19, 16, 17, 18 }, /* IDSEL 16 - PCI slot 4 */
163 };
164
165 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
166 return PCI_IRQ_TABLE_LOOKUP;
167}
168
169static void __init
170sandpoint_setup_winbond_83553(struct pci_controller *hose)
171{
172 int devfn;
173
174 /*
175 * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
176 * We can't route the IDE interrupt to PCI INTC# or INTD# because those
177 * woule interfere with the PMC's INTC# and INTD# lines.
178 */
179 /*
180 * Winbond Fcn 0
181 */
182 devfn = PCI_DEVFN(11,0);
183
184 early_write_config_byte(hose,
185 0,
186 devfn,
187 0x43, /* IDE Interrupt Routing Control */
188 0xef);
189 early_write_config_word(hose,
190 0,
191 devfn,
192 0x44, /* PCI Interrupt Routing Control */
193 0x0000);
194
195 /* Want ISA memory cycles to be forwarded to PCI bus */
196 early_write_config_byte(hose,
197 0,
198 devfn,
199 0x48, /* ISA-to-PCI Addr Decoder Control */
200 0xf0);
201
202 /* Enable Port 92. */
203 early_write_config_byte(hose,
204 0,
205 devfn,
206 0x4e, /* AT System Control Register */
207 0x06);
208 /*
209 * Winbond Fcn 1
210 */
211 devfn = PCI_DEVFN(11,1);
212
213 /* Put IDE controller into native mode. */
214 early_write_config_byte(hose,
215 0,
216 devfn,
217 0x09, /* Programming interface Register */
218 0x8f);
219
220 /* Init IRQ routing, enable both ports, disable fast 16 */
221 early_write_config_dword(hose,
222 0,
223 devfn,
224 0x40, /* IDE Control/Status Register */
225 0x00ff0011);
226 return;
227}
228
229/* On the sandpoint X2, we must avoid sending configuration cycles to
230 * device #12 (IDSEL addr = AD12).
231 */
232static int
233x2_exclude_device(u_char bus, u_char devfn)
234{
235 if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
236 return PCIBIOS_DEVICE_NOT_FOUND;
237 else
238 return PCIBIOS_SUCCESSFUL;
239}
240
241static void __init
242sandpoint_find_bridges(void)
243{
244 struct pci_controller *hose;
245
246 hose = pcibios_alloc_controller();
247
248 if (!hose)
249 return;
250
251 hose->first_busno = 0;
252 hose->last_busno = 0xff;
253
254 if (mpc10x_bridge_init(hose,
255 MPC10X_MEM_MAP_B,
256 MPC10X_MEM_MAP_B,
257 MPC10X_MAPB_EUMB_BASE) == 0) {
258
259 /* Do early winbond init, then scan PCI bus */
260 sandpoint_setup_winbond_83553(hose);
261 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
262
263 ppc_md.pcibios_fixup = NULL;
264 ppc_md.pcibios_fixup_bus = NULL;
265 ppc_md.pci_swizzle = common_swizzle;
266 if (sandpoint_is_x2) {
267 ppc_md.pci_map_irq = x2_map_irq;
268 ppc_md.pci_exclude_device = x2_exclude_device;
269 } else
270 ppc_md.pci_map_irq = x3_map_irq;
271 }
272 else {
273 if (ppc_md.progress)
274 ppc_md.progress("Bridge init failed", 0x100);
275 printk("Host bridge init failed\n");
276 }
277
278 return;
279}
280
281static void __init
282sandpoint_setup_arch(void)
283{
284 /* Probe for Sandpoint model */
285 sandpoint_probe_type();
286 if (sandpoint_is_x2)
287 epic_serial_mode = 0;
288
289 loops_per_jiffy = 100000000 / HZ;
290
291#ifdef CONFIG_BLK_DEV_INITRD
292 if (initrd_start)
293 ROOT_DEV = Root_RAM0;
294 else
295#endif
296#ifdef CONFIG_ROOT_NFS
297 ROOT_DEV = Root_NFS;
298#else
299 ROOT_DEV = Root_HDA1;
300#endif
301
302 /* Lookup PCI host bridges */
303 sandpoint_find_bridges();
304
305 if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0)
306 {
307 bd_t *bp = (bd_t *)__res;
308 struct plat_serial8250_port *pdata;
309
310 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
311 if (pdata)
312 {
313 pdata[0].uartclk = bp->bi_busfreq;
314 }
315
316#ifdef CONFIG_SANDPOINT_ENABLE_UART1
317 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
318 if (pdata)
319 {
320 pdata[0].uartclk = bp->bi_busfreq;
321 }
322#else
323 ppc_sys_device_remove(MPC10X_UART1);
324#endif
325 }
326
327 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
328 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
329
330 /* DINK32 12.3 and below do not correctly enable any caches.
331 * We will do this now with good known values. Future versions
332 * of DINK32 are supposed to get this correct.
333 */
334 if (cpu_has_feature(CPU_FTR_SPEC7450))
335 /* 745x is different. We only want to pass along enable. */
336 _set_L2CR(L2CR_L2E);
337 else if (cpu_has_feature(CPU_FTR_L2CR))
338 /* All modules have 1MB of L2. We also assume that an
339 * L2 divisor of 3 will work.
340 */
341 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
342 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
343#if 0
344 /* Untested right now. */
345 if (cpu_has_feature(CPU_FTR_L3CR)) {
346 /* Magic value. */
347 _set_L3CR(0x8f032000);
348 }
349#endif
350}
351
352#define SANDPOINT_87308_CFG_ADDR 0x15c
353#define SANDPOINT_87308_CFG_DATA 0x15d
354
355#define SANDPOINT_87308_CFG_INB(addr, byte) { \
356 outb((addr), SANDPOINT_87308_CFG_ADDR); \
357 (byte) = inb(SANDPOINT_87308_CFG_DATA); \
358}
359
360#define SANDPOINT_87308_CFG_OUTB(addr, byte) { \
361 outb((addr), SANDPOINT_87308_CFG_ADDR); \
362 outb((byte), SANDPOINT_87308_CFG_DATA); \
363}
364
365#define SANDPOINT_87308_SELECT_DEV(dev_num) { \
366 SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \
367}
368
369#define SANDPOINT_87308_DEV_ENABLE(dev_num) { \
370 SANDPOINT_87308_SELECT_DEV(dev_num); \
371 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \
372}
373
374/*
375 * To probe the Sandpoint type, we need to check for a connection between GPIO
376 * pins 6 and 7 on the NS87308 SuperIO.
377 */
378static void __init sandpoint_probe_type(void)
379{
380 u8 x;
381 /* First, ensure that the GPIO pins are enabled. */
382 SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
383 SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
384 SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
385 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
386
387 /* Now, set pin 7 to output and pin 6 to input. */
388 outb((inb(0x701) | 0x80) & 0xbf, 0x701);
389 /* Set push-pull output */
390 outb(inb(0x702) | 0x80, 0x702);
391 /* Set pull-up on input */
392 outb(inb(0x703) | 0x40, 0x703);
393 /* Set output high and check */
394 x = inb(0x700);
395 outb(x | 0x80, 0x700);
396 x = inb(0x700);
397 sandpoint_is_x2 = ! (x & 0x40);
398 if (ppc_md.progress && sandpoint_is_x2)
399 ppc_md.progress("High output says X2", 0);
400 /* Set output low and check */
401 outb(x & 0x7f, 0x700);
402 sandpoint_is_x2 |= inb(0x700) & 0x40;
403 if (ppc_md.progress && sandpoint_is_x2)
404 ppc_md.progress("Low output says X2", 0);
405 if (ppc_md.progress && ! sandpoint_is_x2)
406 ppc_md.progress("Sandpoint is X3", 0);
407}
408
409/*
410 * Fix IDE interrupts.
411 */
412static int __init
413sandpoint_fix_winbond_83553(void)
414{
415 /* Make some 8259 interrupt level sensitive */
416 outb(0xe0, 0x4d0);
417 outb(0xde, 0x4d1);
418
419 return 0;
420}
421
422arch_initcall(sandpoint_fix_winbond_83553);
423
424/*
425 * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
426 */
427static int __init
428sandpoint_setup_natl_87308(void)
429{
430 u_char reg;
431
432 /*
433 * Enable all the devices on the Super I/O chip.
434 */
435 SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
436 SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
437 SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
438 SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
439 SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
440 SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
441 SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
442 SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
443 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
444 SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
445 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
446
447 /* Set up floppy in PS/2 mode */
448 outb(0x09, SIO_CONFIG_RA);
449 reg = inb(SIO_CONFIG_RD);
450 reg = (reg & 0x3F) | 0x40;
451 outb(reg, SIO_CONFIG_RD);
452 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
453
454 return 0;
455}
456
457arch_initcall(sandpoint_setup_natl_87308);
458
459static int __init
460sandpoint_request_io(void)
461{
462 request_region(0x00,0x20,"dma1");
463 request_region(0x20,0x20,"pic1");
464 request_region(0x40,0x20,"timer");
465 request_region(0x80,0x10,"dma page reg");
466 request_region(0xa0,0x20,"pic2");
467 request_region(0xc0,0x20,"dma2");
468
469 return 0;
470}
471
472arch_initcall(sandpoint_request_io);
473
474/*
475 * Interrupt setup and service. Interrupts on the Sandpoint come
476 * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
477 * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
478 * IDE is on EPIC 7 and 8.
479 */
480static void __init
481sandpoint_init_IRQ(void)
482{
483 int i;
484
485 OpenPIC_InitSenses = sandpoint_openpic_initsenses;
486 OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
487
488 mpc10x_set_openpic();
489 openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
490 i8259_irq);
491
492 /*
493 * The EPIC allows for a read in the range of 0xFEF00000 ->
494 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
495 */
496 i8259_init(0xfef00000, 0);
497}
498
499static unsigned long __init
500sandpoint_find_end_of_memory(void)
501{
502 bd_t *bp = (bd_t *)__res;
503
504 if (bp->bi_memsize)
505 return bp->bi_memsize;
506
507 /* DINK32 13.0 correctly initializes things, so iff you use
508 * this you _should_ be able to change this instead of a
509 * hardcoded value. */
510#if 0
511 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
512#else
513 return 32*1024*1024;
514#endif
515}
516
517static void __init
518sandpoint_map_io(void)
519{
520 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
521}
522
523static void
524sandpoint_restart(char *cmd)
525{
526 local_irq_disable();
527
528 /* Set exception prefix high - to the firmware */
529 _nmask_and_or_msr(0, MSR_IP);
530
531 /* Reset system via Port 92 */
532 outb(0x00, 0x92);
533 outb(0x01, 0x92);
534 for(;;); /* Spin until reset happens */
535}
536
537static void
538sandpoint_power_off(void)
539{
540 local_irq_disable();
541 for(;;); /* No way to shut power off with software */
542 /* NOTREACHED */
543}
544
545static void
546sandpoint_halt(void)
547{
548 sandpoint_power_off();
549 /* NOTREACHED */
550}
551
552static int
553sandpoint_show_cpuinfo(struct seq_file *m)
554{
555 seq_printf(m, "vendor\t\t: Motorola SPS\n");
556 seq_printf(m, "machine\t\t: Sandpoint\n");
557
558 return 0;
559}
560
561/*
562 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
563 */
564static __inline__ void
565sandpoint_set_bat(void)
566{
567 unsigned long bat3u, bat3l;
568
569 __asm__ __volatile__(
570 " lis %0,0xf800\n \
571 ori %1,%0,0x002a\n \
572 ori %0,%0,0x0ffe\n \
573 mtspr 0x21e,%0\n \
574 mtspr 0x21f,%1\n \
575 isync\n \
576 sync "
577 : "=r" (bat3u), "=r" (bat3l));
578}
579
580TODC_ALLOC();
581
582void __init
583platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
584 unsigned long r6, unsigned long r7)
585{
586 parse_bootinfo(find_bootinfo());
587
588 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
589 * are non-zero, then we should use the board info from the bd_t
590 * structure and the cmdline pointed to by r6 instead of the
591 * information from birecs, if any. Otherwise, use the information
592 * from birecs as discovered by the preceding call to
593 * parse_bootinfo(). This rule should work with both PPCBoot, which
594 * uses a bd_t board info structure, and the kernel boot wrapper,
595 * which uses birecs.
596 */
597 if (r3 && r6) {
598 /* copy board info structure */
599 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
600 /* copy command line */
601 *(char *)(r7+KERNELBASE) = 0;
602 strcpy(cmd_line, (char *)(r6+KERNELBASE));
603 }
604
605#ifdef CONFIG_BLK_DEV_INITRD
606 /* take care of initrd if we have one */
607 if (r4) {
608 initrd_start = r4 + KERNELBASE;
609 initrd_end = r5 + KERNELBASE;
610 }
611#endif /* CONFIG_BLK_DEV_INITRD */
612
613 /* Map in board regs, etc. */
614 sandpoint_set_bat();
615
616 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
617 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
618 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
619 ISA_DMA_THRESHOLD = 0x00ffffff;
620 DMA_MODE_READ = 0x44;
621 DMA_MODE_WRITE = 0x48;
622 ppc_do_canonicalize_irqs = 1;
623
624 ppc_md.setup_arch = sandpoint_setup_arch;
625 ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
626 ppc_md.init_IRQ = sandpoint_init_IRQ;
627 ppc_md.get_irq = openpic_get_irq;
628
629 ppc_md.restart = sandpoint_restart;
630 ppc_md.power_off = sandpoint_power_off;
631 ppc_md.halt = sandpoint_halt;
632
633 ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
634 ppc_md.setup_io_mappings = sandpoint_map_io;
635
636 TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
637 ppc_md.time_init = todc_time_init;
638 ppc_md.set_rtc_time = todc_set_rtc_time;
639 ppc_md.get_rtc_time = todc_get_rtc_time;
640 ppc_md.calibrate_decr = todc_calibrate_decr;
641
642 ppc_md.nvram_read_val = todc_mc146818_read_val;
643 ppc_md.nvram_write_val = todc_mc146818_write_val;
644
645#ifdef CONFIG_KGDB
646 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
647#endif
648#ifdef CONFIG_SERIAL_TEXT_DEBUG
649 ppc_md.progress = gen550_progress;
650#endif
651}
diff --git a/arch/ppc/platforms/sandpoint.h b/arch/ppc/platforms/sandpoint.h
deleted file mode 100644
index ed83759e4044..000000000000
--- a/arch/ppc/platforms/sandpoint.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Definitions for Motorola SPS Sandpoint Test Platform
3 *
4 * Author: Mark A. Greer
5 * mgreer@mvista.com
6 *
7 * 2000-2003 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * Sandpoint uses the CHRP map (Map B).
15 */
16
17#ifndef __PPC_PLATFORMS_SANDPOINT_H
18#define __PPC_PLATFORMS_SANDPOINT_H
19
20#include <asm/ppcboot.h>
21
22#if 0
23/* The Sandpoint X3 allows the IDE interrupt to be directly connected
24 * from the Windbond (PCI INTC or INTD) to the serial EPIC. Someday
25 * we should try this, but it was easier to use the existing 83c553
26 * initialization than change it to route the different interrupts :-).
27 * -- Dan
28 */
29#define SANDPOINT_IDE_INT0 23 /* EPIC 7 */
30#define SANDPOINT_IDE_INT1 24 /* EPIC 8 */
31#endif
32
33/*
34 * The sandpoint boards have processor modules that either have an 8240 or
35 * an MPC107 host bridge on them. These bridges have an IDSEL line that allows
36 * them to respond to PCI transactions as if they were a normal PCI devices.
37 * However, the processor on the processor side of the bridge can not reach
38 * out onto the PCI bus and then select the bridge or bad things will happen
39 * (documented in the 8240 and 107 manuals).
40 * Because of this, we always skip the bridge PCI device when accessing the
41 * PCI bus. The PCI slot that the bridge occupies is defined by the macro
42 * below.
43 */
44#define SANDPOINT_HOST_BRIDGE_IDSEL 12
45
46/*
47 * Serial defines.
48 */
49#define SANDPOINT_SERIAL_0 0xfe0003f8
50#define SANDPOINT_SERIAL_1 0xfe0002f8
51
52#define RS_TABLE_SIZE 2
53
54/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
55#define BASE_BAUD ( 1843200 / 16 )
56#define UART_CLK 1843200
57
58#ifdef CONFIG_SERIAL_DETECT_IRQ
59#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
60#else
61#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF)
62#endif
63
64#define STD_SERIAL_PORT_DFNS \
65 { 0, BASE_BAUD, SANDPOINT_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
66 iomem_base: (u8 *)SANDPOINT_SERIAL_0, \
67 io_type: SERIAL_IO_MEM }, \
68 { 0, BASE_BAUD, SANDPOINT_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
69 iomem_base: (u8 *)SANDPOINT_SERIAL_1, \
70 io_type: SERIAL_IO_MEM },
71
72#define SERIAL_PORT_DFNS \
73 STD_SERIAL_PORT_DFNS
74
75#endif /* __PPC_PLATFORMS_SANDPOINT_H */
diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c
deleted file mode 100644
index 24f6e0694ac1..000000000000
--- a/arch/ppc/platforms/sbc82xx.c
+++ /dev/null
@@ -1,256 +0,0 @@
1/*
2 * SBC82XX platform support
3 *
4 * Author: Guy Streeter <streeter@redhat.com>
5 *
6 * Derived from: est8260_setup.c by Allen Curtis, ONZ
7 *
8 * Copyright 2004 Red Hat, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/init.h>
20#include <linux/pci.h>
21
22#include <asm/mpc8260.h>
23#include <asm/machdep.h>
24#include <asm/io.h>
25#include <asm/todc.h>
26#include <asm/immap_cpm2.h>
27#include <asm/pci.h>
28
29static void (*callback_init_IRQ)(void);
30
31extern unsigned char __res[sizeof(bd_t)];
32
33#ifdef CONFIG_GEN_RTC
34TODC_ALLOC();
35
36/*
37 * Timer init happens before mem_init but after paging init, so we cannot
38 * directly use ioremap() at that time.
39 * late_time_init() is call after paging init.
40 */
41
42static void sbc82xx_time_init(void)
43{
44 volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
45
46 /* Set up CS11 for RTC chip */
47 mc->memc_br11=0;
48 mc->memc_or11=0xffff0836;
49 mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
50
51 TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
52
53 todc_info->nvram_data =
54 (unsigned int)ioremap(todc_info->nvram_data, 0x2000);
55 BUG_ON(!todc_info->nvram_data);
56 ppc_md.get_rtc_time = todc_get_rtc_time;
57 ppc_md.set_rtc_time = todc_set_rtc_time;
58 ppc_md.nvram_read_val = todc_direct_read_val;
59 ppc_md.nvram_write_val = todc_direct_write_val;
60 todc_time_init();
61}
62#endif /* CONFIG_GEN_RTC */
63
64static volatile char *sbc82xx_i8259_map;
65static char sbc82xx_i8259_mask = 0xff;
66static DEFINE_SPINLOCK(sbc82xx_i8259_lock);
67
68static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr)
69{
70 unsigned long flags;
71
72 irq_nr -= NR_SIU_INTS;
73
74 spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
75 sbc82xx_i8259_mask |= 1 << irq_nr;
76 (void) sbc82xx_i8259_map[1]; /* Dummy read */
77 sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
78 sbc82xx_i8259_map[0] = 0x20; /* OCW2: Non-specific EOI */
79 spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
80}
81
82static void sbc82xx_i8259_mask_irq(unsigned int irq_nr)
83{
84 unsigned long flags;
85
86 irq_nr -= NR_SIU_INTS;
87
88 spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
89 sbc82xx_i8259_mask |= 1 << irq_nr;
90 sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
91 spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
92}
93
94static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr)
95{
96 unsigned long flags;
97
98 irq_nr -= NR_SIU_INTS;
99
100 spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
101 sbc82xx_i8259_mask &= ~(1 << irq_nr);
102 sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
103 spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
104}
105
106static void sbc82xx_i8259_end_irq(unsigned int irq)
107{
108 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
109 && irq_desc[irq].action)
110 sbc82xx_i8259_unmask_irq(irq);
111}
112
113
114struct hw_interrupt_type sbc82xx_i8259_ic = {
115 .typename = " i8259 ",
116 .enable = sbc82xx_i8259_unmask_irq,
117 .disable = sbc82xx_i8259_mask_irq,
118 .ack = sbc82xx_i8259_mask_and_ack_irq,
119 .end = sbc82xx_i8259_end_irq,
120};
121
122static irqreturn_t sbc82xx_i8259_demux(int dummy, void *dev_id)
123{
124 int irq;
125
126 spin_lock(&sbc82xx_i8259_lock);
127
128 sbc82xx_i8259_map[0] = 0x0c; /* OCW3: Read IR register on RD# pulse */
129 irq = sbc82xx_i8259_map[0] & 7; /* Read IRR */
130
131 if (irq == 7) {
132 /* Possible spurious interrupt */
133 int isr;
134 sbc82xx_i8259_map[0] = 0x0b; /* OCW3: Read IS register on RD# pulse */
135 isr = sbc82xx_i8259_map[0]; /* Read ISR */
136
137 if (!(isr & 0x80)) {
138 printk(KERN_INFO "Spurious i8259 interrupt\n");
139 return IRQ_HANDLED;
140 }
141 }
142 __do_IRQ(NR_SIU_INTS + irq);
143 return IRQ_HANDLED;
144}
145
146static struct irqaction sbc82xx_i8259_irqaction = {
147 .handler = sbc82xx_i8259_demux,
148 .flags = IRQF_DISABLED,
149 .mask = CPU_MASK_NONE,
150 .name = "i8259 demux",
151};
152
153void __init sbc82xx_init_IRQ(void)
154{
155 volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
156 volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl;
157 int i;
158
159 callback_init_IRQ();
160
161 /* u-boot doesn't always set the board up correctly */
162 mc->memc_br5 = 0;
163 mc->memc_or5 = 0xfff00856;
164 mc->memc_br5 = 0x22000801;
165
166 sbc82xx_i8259_map = ioremap(0x22008000, 2);
167 if (!sbc82xx_i8259_map) {
168 printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n");
169 return;
170 }
171
172 /* Set up the interrupt handlers for the i8259 IRQs */
173 for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
174 irq_desc[i].chip = &sbc82xx_i8259_ic;
175 irq_desc[i].status |= IRQ_LEVEL;
176 }
177
178 /* make IRQ6 level sensitive */
179 ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1)));
180 irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL;
181
182 /* Initialise the i8259 */
183 sbc82xx_i8259_map[0] = 0x1b; /* ICW1: Level, no cascade, ICW4 */
184 sbc82xx_i8259_map[1] = 0x00; /* ICW2: vector base */
185 /* No ICW3 (no cascade) */
186 sbc82xx_i8259_map[1] = 0x01; /* ICW4: 8086 mode, normal EOI */
187
188 sbc82xx_i8259_map[0] = 0x0b; /* OCW3: Read IS register on RD# pulse */
189
190 sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */
191
192 /* Request cascade IRQ */
193 if (setup_irq(SIU_INT_IRQ6, &sbc82xx_i8259_irqaction)) {
194 printk("Installation of i8259 IRQ demultiplexer failed.\n");
195 }
196}
197
198static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel,
199 unsigned char pin)
200{
201 static char pci_irq_table[][4] = {
202 /*
203 * PCI IDSEL/INTPIN->INTLINE
204 * A B C D
205 */
206 { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 16 - PMC slot */
207 { SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1, -1 }, /* IDSEL 17 - CardBus */
208 { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */
209 };
210
211 const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4;
212
213 return PCI_IRQ_TABLE_LOOKUP;
214}
215
216static void __devinit quirk_sbc8260_cardbus(struct pci_dev *pdev)
217{
218 uint32_t ctrl;
219
220 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(17, 0))
221 return;
222
223 printk(KERN_INFO "Setting up CardBus controller\n");
224
225 /* Set P2CCLK bit in System Control Register */
226 pci_read_config_dword(pdev, 0x80, &ctrl);
227 ctrl |= (1<<27);
228 pci_write_config_dword(pdev, 0x80, ctrl);
229
230 /* Set MFUNC up for PCI IRQ routing via INTA and INTB, and LEDs. */
231 pci_write_config_dword(pdev, 0x8c, 0x00c01d22);
232
233}
234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, quirk_sbc8260_cardbus);
235
236void __init
237m82xx_board_init(void)
238{
239 /* u-boot may be using one of the FCC Ethernet devices.
240 Use the MAC address to the SCC. */
241 __res[offsetof(bd_t, bi_enetaddr[5])] &= ~3;
242
243 /* Anything special for this platform */
244 callback_init_IRQ = ppc_md.init_IRQ;
245
246 ppc_md.init_IRQ = sbc82xx_init_IRQ;
247 ppc_md.pci_map_irq = sbc82xx_pci_map_irq;
248#ifdef CONFIG_GEN_RTC
249 ppc_md.time_init = NULL;
250 ppc_md.get_rtc_time = NULL;
251 ppc_md.set_rtc_time = NULL;
252 ppc_md.nvram_read_val = NULL;
253 ppc_md.nvram_write_val = NULL;
254 late_time_init = sbc82xx_time_init;
255#endif /* CONFIG_GEN_RTC */
256}
diff --git a/arch/ppc/platforms/sbc82xx.h b/arch/ppc/platforms/sbc82xx.h
deleted file mode 100644
index e4042d4995f6..000000000000
--- a/arch/ppc/platforms/sbc82xx.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/* Board information for the SBCPowerQUICCII, which should be generic for
2 * all 8260 boards. The IMMR is now given to us so the hard define
3 * will soon be removed. All of the clock values are computed from
4 * the configuration SCMR and the Power-On-Reset word.
5 */
6
7#ifndef __PPC_SBC82xx_H__
8#define __PPC_SBC82xx_H__
9
10#include <asm/ppcboot.h>
11
12#define CPM_MAP_ADDR 0xf0000000
13
14#define SBC82xx_TODC_NVRAM_ADDR 0xd0000000
15
16#define SBC82xx_MACADDR_NVRAM_FCC1 0x220000c9 /* JP6B */
17#define SBC82xx_MACADDR_NVRAM_SCC1 0x220000cf /* JP6A */
18#define SBC82xx_MACADDR_NVRAM_FCC2 0x220000d5 /* JP7A */
19#define SBC82xx_MACADDR_NVRAM_FCC3 0x220000db /* JP7B */
20
21/* For our show_cpuinfo hooks. */
22#define CPUINFO_VENDOR "Wind River"
23#define CPUINFO_MACHINE "SBC PowerQUICC II"
24
25#define BOOTROM_RESTART_ADDR ((uint)0x40000104)
26
27#define SBC82xx_PC_IRQA (NR_SIU_INTS+0)
28#define SBC82xx_PC_IRQB (NR_SIU_INTS+1)
29#define SBC82xx_MPC185_IRQ (NR_SIU_INTS+2)
30#define SBC82xx_ATM_IRQ (NR_SIU_INTS+3)
31#define SBC82xx_PIRQA (NR_SIU_INTS+4)
32#define SBC82xx_PIRQB (NR_SIU_INTS+5)
33#define SBC82xx_PIRQC (NR_SIU_INTS+6)
34#define SBC82xx_PIRQD (NR_SIU_INTS+7)
35
36#endif /* __PPC_SBC82xx_H__ */
diff --git a/arch/ppc/platforms/sbs8260.h b/arch/ppc/platforms/sbs8260.h
deleted file mode 100644
index d51427a0f0d4..000000000000
--- a/arch/ppc/platforms/sbs8260.h
+++ /dev/null
@@ -1,28 +0,0 @@
1#ifndef __ASSEMBLY__
2/* Board information for various SBS 8260 cards, which should be generic for
3 * all 8260 boards. The IMMR is now given to us so the hard define
4 * will soon be removed. All of the clock values are computed from
5 * the configuration SCMR and the Power-On-Reset word.
6 */
7
8#define CPM_MAP_ADDR ((uint)0xfe000000)
9
10
11/* A Board Information structure that is given to a program when
12 * prom starts it up.
13 */
14typedef struct bd_info {
15 unsigned int bi_memstart; /* Memory start address */
16 unsigned int bi_memsize; /* Memory (end) size in bytes */
17 unsigned int bi_intfreq; /* Internal Freq, in Hz */
18 unsigned int bi_busfreq; /* Bus Freq, in MHz */
19 unsigned int bi_cpmfreq; /* CPM Freq, in MHz */
20 unsigned int bi_brgfreq; /* BRG Freq, in MHz */
21 unsigned int bi_vco; /* VCO Out from PLL */
22 unsigned int bi_baudrate; /* Default console baud rate */
23 unsigned int bi_immr; /* IMMR when called from boot rom */
24 unsigned char bi_enetaddr[6];
25} bd_t;
26
27extern bd_t m8xx_board_info;
28#endif /* !__ASSEMBLY__ */
diff --git a/arch/ppc/platforms/spruce.c b/arch/ppc/platforms/spruce.c
deleted file mode 100644
index a344134f14b8..000000000000
--- a/arch/ppc/platforms/spruce.c
+++ /dev/null
@@ -1,322 +0,0 @@
1/*
2 * Board and PCI setup routines for IBM Spruce
3 *
4 * Author: MontaVista Software <source@mvista.com>
5 *
6 * 2000-2004 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/pci.h>
18#include <linux/kdev_t.h>
19#include <linux/types.h>
20#include <linux/major.h>
21#include <linux/initrd.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26#include <linux/serial.h>
27#include <linux/tty.h>
28#include <linux/serial_core.h>
29#include <linux/serial_8250.h>
30
31#include <asm/system.h>
32#include <asm/pgtable.h>
33#include <asm/page.h>
34#include <asm/dma.h>
35#include <asm/io.h>
36#include <asm/machdep.h>
37#include <asm/time.h>
38#include <asm/todc.h>
39#include <asm/bootinfo.h>
40#include <asm/kgdb.h>
41
42#include <syslib/cpc700.h>
43
44#include "spruce.h"
45
46static inline int
47spruce_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
48{
49 static char pci_irq_table[][4] =
50 /*
51 * PCI IDSEL/INTPIN->INTLINE
52 * A B C D
53 */
54 {
55 {23, 24, 25, 26}, /* IDSEL 1 - PCI slot 3 */
56 {24, 25, 26, 23}, /* IDSEL 2 - PCI slot 2 */
57 {25, 26, 23, 24}, /* IDSEL 3 - PCI slot 1 */
58 {26, 23, 24, 25}, /* IDSEL 4 - PCI slot 0 */
59 };
60
61 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
62 return PCI_IRQ_TABLE_LOOKUP;
63}
64
65static void __init
66spruce_setup_hose(void)
67{
68 struct pci_controller *hose;
69
70 /* Setup hose */
71 hose = pcibios_alloc_controller();
72 if (!hose)
73 return;
74
75 hose->first_busno = 0;
76 hose->last_busno = 0xff;
77
78 pci_init_resource(&hose->io_resource,
79 SPRUCE_PCI_LOWER_IO,
80 SPRUCE_PCI_UPPER_IO,
81 IORESOURCE_IO,
82 "PCI host bridge");
83
84 pci_init_resource(&hose->mem_resources[0],
85 SPRUCE_PCI_LOWER_MEM,
86 SPRUCE_PCI_UPPER_MEM,
87 IORESOURCE_MEM,
88 "PCI host bridge");
89
90 hose->io_space.start = SPRUCE_PCI_LOWER_IO;
91 hose->io_space.end = SPRUCE_PCI_UPPER_IO;
92 hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
93 hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
94 hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
95
96 setup_indirect_pci(hose,
97 SPRUCE_PCI_CONFIG_ADDR,
98 SPRUCE_PCI_CONFIG_DATA);
99
100 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
101
102 ppc_md.pci_swizzle = common_swizzle;
103 ppc_md.pci_map_irq = spruce_map_irq;
104}
105
106/*
107 * CPC700 PIC interrupt programming table
108 *
109 * First entry is the sensitivity (level/edge), second is the polarity.
110 */
111unsigned int cpc700_irq_assigns[32][2] = {
112 { 1, 1 }, /* IRQ 0: ECC Correctable Error - rising edge */
113 { 1, 1 }, /* IRQ 1: PCI Write Mem Range - rising edge */
114 { 0, 1 }, /* IRQ 2: PCI Write Command Reg - active high */
115 { 0, 1 }, /* IRQ 3: UART 0 - active high */
116 { 0, 1 }, /* IRQ 4: UART 1 - active high */
117 { 0, 1 }, /* IRQ 5: ICC 0 - active high */
118 { 0, 1 }, /* IRQ 6: ICC 1 - active high */
119 { 0, 1 }, /* IRQ 7: GPT Compare 0 - active high */
120 { 0, 1 }, /* IRQ 8: GPT Compare 1 - active high */
121 { 0, 1 }, /* IRQ 9: GPT Compare 2 - active high */
122 { 0, 1 }, /* IRQ 10: GPT Compare 3 - active high */
123 { 0, 1 }, /* IRQ 11: GPT Compare 4 - active high */
124 { 0, 1 }, /* IRQ 12: GPT Capture 0 - active high */
125 { 0, 1 }, /* IRQ 13: GPT Capture 1 - active high */
126 { 0, 1 }, /* IRQ 14: GPT Capture 2 - active high */
127 { 0, 1 }, /* IRQ 15: GPT Capture 3 - active high */
128 { 0, 1 }, /* IRQ 16: GPT Capture 4 - active high */
129 { 0, 0 }, /* IRQ 17: Reserved */
130 { 0, 0 }, /* IRQ 18: Reserved */
131 { 0, 0 }, /* IRQ 19: Reserved */
132 { 0, 1 }, /* IRQ 20: FPGA EXT_IRQ0 - active high */
133 { 1, 1 }, /* IRQ 21: Mouse - rising edge */
134 { 1, 1 }, /* IRQ 22: Keyboard - rising edge */
135 { 0, 0 }, /* IRQ 23: PCI Slot 3 - active low */
136 { 0, 0 }, /* IRQ 24: PCI Slot 2 - active low */
137 { 0, 0 }, /* IRQ 25: PCI Slot 1 - active low */
138 { 0, 0 }, /* IRQ 26: PCI Slot 0 - active low */
139};
140
141static void __init
142spruce_calibrate_decr(void)
143{
144 int freq, divisor = 4;
145
146 /* determine processor bus speed */
147 freq = SPRUCE_BUS_SPEED;
148 tb_ticks_per_jiffy = freq / HZ / divisor;
149 tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
150}
151
152static int
153spruce_show_cpuinfo(struct seq_file *m)
154{
155 seq_printf(m, "vendor\t\t: IBM\n");
156 seq_printf(m, "machine\t\t: Spruce\n");
157
158 return 0;
159}
160
161static void __init
162spruce_early_serial_map(void)
163{
164 u32 uart_clk;
165 struct uart_port serial_req;
166
167 if (SPRUCE_UARTCLK_IS_33M(readb(SPRUCE_FPGA_REG_A)))
168 uart_clk = SPRUCE_BAUD_33M * 16;
169 else
170 uart_clk = SPRUCE_BAUD_30M * 16;
171
172 /* Setup serial port access */
173 memset(&serial_req, 0, sizeof(serial_req));
174 serial_req.uartclk = uart_clk;
175 serial_req.irq = UART0_INT;
176 serial_req.flags = UPF_BOOT_AUTOCONF;
177 serial_req.iotype = UPIO_MEM;
178 serial_req.membase = (u_char *)UART0_IO_BASE;
179 serial_req.regshift = 0;
180
181#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
182 gen550_init(0, &serial_req);
183#endif
184#ifdef CONFIG_SERIAL_8250
185 if (early_serial_setup(&serial_req) != 0)
186 printk("Early serial init of port 0 failed\n");
187#endif
188
189 /* Assume early_serial_setup() doesn't modify serial_req */
190 serial_req.line = 1;
191 serial_req.irq = UART1_INT;
192 serial_req.membase = (u_char *)UART1_IO_BASE;
193
194#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
195 gen550_init(1, &serial_req);
196#endif
197#ifdef CONFIG_SERIAL_8250
198 if (early_serial_setup(&serial_req) != 0)
199 printk("Early serial init of port 1 failed\n");
200#endif
201}
202
203TODC_ALLOC();
204
205static void __init
206spruce_setup_arch(void)
207{
208 /* Setup TODC access */
209 TODC_INIT(TODC_TYPE_DS1643, 0, 0, SPRUCE_RTC_BASE_ADDR, 8);
210
211 /* init to some ~sane value until calibrate_delay() runs */
212 loops_per_jiffy = 50000000 / HZ;
213
214 /* Setup PCI host bridge */
215 spruce_setup_hose();
216
217#ifdef CONFIG_BLK_DEV_INITRD
218 if (initrd_start)
219 ROOT_DEV = Root_RAM0;
220 else
221#endif
222#ifdef CONFIG_ROOT_NFS
223 ROOT_DEV = Root_NFS;
224#else
225 ROOT_DEV = Root_SDA1;
226#endif
227
228 /* Identify the system */
229 printk(KERN_INFO "System Identification: IBM Spruce\n");
230 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
231}
232
233static void
234spruce_restart(char *cmd)
235{
236 local_irq_disable();
237
238 /* SRR0 has system reset vector, SRR1 has default MSR value */
239 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
240 __asm__ __volatile__
241 ("\n\
242 lis 3,0xfff0 \n\
243 ori 3,3,0x0100 \n\
244 mtspr 26,3 \n\
245 li 3,0 \n\
246 mtspr 27,3 \n\
247 rfi \n\
248 ");
249 for(;;);
250}
251
252static void
253spruce_power_off(void)
254{
255 for(;;);
256}
257
258static void
259spruce_halt(void)
260{
261 spruce_restart(NULL);
262}
263
264static void __init
265spruce_map_io(void)
266{
267 io_block_mapping(SPRUCE_PCI_IO_BASE, SPRUCE_PCI_PHY_IO_BASE,
268 0x08000000, _PAGE_IO);
269}
270
271/*
272 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
273 */
274static __inline__ void
275spruce_set_bat(void)
276{
277 mb();
278 mtspr(SPRN_DBAT1U, 0xf8000ffe);
279 mtspr(SPRN_DBAT1L, 0xf800002a);
280 mb();
281}
282
283void __init
284platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
285 unsigned long r6, unsigned long r7)
286{
287 parse_bootinfo(find_bootinfo());
288
289 /* Map in board regs, etc. */
290 spruce_set_bat();
291
292 isa_io_base = SPRUCE_ISA_IO_BASE;
293 pci_dram_offset = SPRUCE_PCI_SYS_MEM_BASE;
294
295 ppc_md.setup_arch = spruce_setup_arch;
296 ppc_md.show_cpuinfo = spruce_show_cpuinfo;
297 ppc_md.init_IRQ = cpc700_init_IRQ;
298 ppc_md.get_irq = cpc700_get_irq;
299
300 ppc_md.setup_io_mappings = spruce_map_io;
301
302 ppc_md.restart = spruce_restart;
303 ppc_md.power_off = spruce_power_off;
304 ppc_md.halt = spruce_halt;
305
306 ppc_md.time_init = todc_time_init;
307 ppc_md.set_rtc_time = todc_set_rtc_time;
308 ppc_md.get_rtc_time = todc_get_rtc_time;
309 ppc_md.calibrate_decr = spruce_calibrate_decr;
310
311 ppc_md.nvram_read_val = todc_direct_read_val;
312 ppc_md.nvram_write_val = todc_direct_write_val;
313
314 spruce_early_serial_map();
315
316#ifdef CONFIG_SERIAL_TEXT_DEBUG
317 ppc_md.progress = gen550_progress;
318#endif /* CONFIG_SERIAL_TEXT_DEBUG */
319#ifdef CONFIG_KGDB
320 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
321#endif
322}
diff --git a/arch/ppc/platforms/spruce.h b/arch/ppc/platforms/spruce.h
deleted file mode 100644
index f1f96f1de72a..000000000000
--- a/arch/ppc/platforms/spruce.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * arch/ppc/platforms/spruce.h
3 *
4 * Definitions for IBM Spruce reference board support
5 *
6 * Authors: Matt Porter and Johnnie Peters
7 * mporter@mvista.com
8 * jpeters@mvista.com
9 *
10 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_SPRUCE_H__
18#define __ASM_SPRUCE_H__
19
20#define SPRUCE_PCI_CONFIG_ADDR 0xfec00000
21#define SPRUCE_PCI_CONFIG_DATA 0xfec00004
22
23#define SPRUCE_PCI_PHY_IO_BASE 0xf8000000
24#define SPRUCE_PCI_IO_BASE SPRUCE_PCI_PHY_IO_BASE
25
26#define SPRUCE_PCI_SYS_MEM_BASE 0x00000000
27
28#define SPRUCE_PCI_LOWER_MEM 0x80000000
29#define SPRUCE_PCI_UPPER_MEM 0x9fffffff
30#define SPRUCE_PCI_LOWER_IO 0x00000000
31#define SPRUCE_PCI_UPPER_IO 0x03ffffff
32
33#define SPRUCE_ISA_IO_BASE SPRUCE_PCI_IO_BASE
34
35#define SPRUCE_MEM_SIZE 0x04000000
36#define SPRUCE_BUS_SPEED 66666667
37
38#define SPRUCE_NVRAM_BASE_ADDR 0xff800000
39#define SPRUCE_RTC_BASE_ADDR SPRUCE_NVRAM_BASE_ADDR
40
41/*
42 * Serial port defines
43 */
44#define SPRUCE_FPGA_REG_A 0xff820000
45#define SPRUCE_UARTCLK_33M 0x02
46#define SPRUCE_UARTCLK_IS_33M(reg) (reg & SPRUCE_UARTCLK_33M)
47
48#define UART0_IO_BASE 0xff600300
49#define UART1_IO_BASE 0xff600400
50
51#define RS_TABLE_SIZE 2
52
53#define SPRUCE_BAUD_33M (33000000/64)
54#define SPRUCE_BAUD_30M (30000000/64)
55#define BASE_BAUD SPRUCE_BAUD_33M
56
57#define UART0_INT 3
58#define UART1_INT 4
59
60#define STD_UART_OP(num) \
61 { 0, BASE_BAUD, 0, UART##num##_INT, \
62 ASYNC_BOOT_AUTOCONF, \
63 iomem_base: (unsigned char *) UART##num##_IO_BASE, \
64 io_type: SERIAL_IO_MEM},
65
66#define SERIAL_PORT_DFNS \
67 STD_UART_OP(0) \
68 STD_UART_OP(1)
69
70#endif /* __ASM_SPRUCE_H__ */
71#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/tqm8260.h b/arch/ppc/platforms/tqm8260.h
deleted file mode 100644
index 7f8c9a6928f8..000000000000
--- a/arch/ppc/platforms/tqm8260.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * TQM8260 board specific definitions
3 *
4 * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifndef __TQM8260_PLATFORM
8#define __TQM8260_PLATFORM
9
10
11#include <asm/ppcboot.h>
12
13#define CPM_MAP_ADDR ((uint)0xFFF00000)
14#define PHY_INTERRUPT 25
15
16/* For our show_cpuinfo hooks. */
17#define CPUINFO_VENDOR "IN2 Systems"
18#define CPUINFO_MACHINE "TQM8260 PowerPC"
19
20#define BOOTROM_RESTART_ADDR ((uint)0x40000104)
21
22#endif /* __TQM8260_PLATFORM */
diff --git a/arch/ppc/platforms/tqm8260_setup.c b/arch/ppc/platforms/tqm8260_setup.c
deleted file mode 100644
index b766339f44ac..000000000000
--- a/arch/ppc/platforms/tqm8260_setup.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * TQM8260 platform support
3 *
4 * Author: Allen Curtis <acurtis@onz.com>
5 * Derived from: m8260_setup.c by Dan Malek, MVista
6 *
7 * Copyright 2002 Ones and Zeros, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/init.h>
16
17#include <asm/mpc8260.h>
18#include <asm/cpm2.h>
19#include <asm/machdep.h>
20
21static int
22tqm8260_set_rtc_time(unsigned long time)
23{
24 ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt = time;
25 ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcntsc = 0x3;
26
27 return(0);
28}
29
30static unsigned long
31tqm8260_get_rtc_time(void)
32{
33 return ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt;
34}
35
36void __init
37m82xx_board_init(void)
38{
39 /* Anything special for this platform */
40 ppc_md.set_rtc_time = tqm8260_set_rtc_time;
41 ppc_md.get_rtc_time = tqm8260_get_rtc_time;
42}
diff --git a/arch/ppc/platforms/tqm8xx.h b/arch/ppc/platforms/tqm8xx.h
deleted file mode 100644
index 662131d0eb39..000000000000
--- a/arch/ppc/platforms/tqm8xx.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * TQM8xx(L) board specific definitions
3 *
4 * Copyright (c) 1999-2002 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifdef __KERNEL__
8#ifndef __MACH_TQM8xx_H
9#define __MACH_TQM8xx_H
10
11
12#include <asm/ppcboot.h>
13
14#ifndef __ASSEMBLY__
15#define TQM_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */
16#define TQM_IMAP_SIZE (64 * 1024) /* size of mapped area */
17
18#define IMAP_ADDR TQM_IMMR_BASE /* physical base address of IMMR area */
19#define IMAP_SIZE TQM_IMAP_SIZE /* mapped size of IMMR area */
20
21/*-----------------------------------------------------------------------
22 * PCMCIA stuff
23 *-----------------------------------------------------------------------
24 *
25 */
26#define PCMCIA_MEM_SIZE ( 64 << 20 )
27
28#ifndef CONFIG_KUP4K
29# define MAX_HWIFS 1 /* overwrite default in include/asm-ppc/ide.h */
30
31#else /* CONFIG_KUP4K */
32
33# define MAX_HWIFS 2 /* overwrite default in include/asm-ppc/ide.h */
34# ifndef __ASSEMBLY__
35# include <asm/8xx_immap.h>
36static __inline__ void ide_led(int on)
37{
38 volatile immap_t *immap = (immap_t *)IMAP_ADDR;
39
40 if (on) {
41 immap->im_ioport.iop_padat &= ~0x80;
42 } else {
43 immap->im_ioport.iop_padat |= 0x80;
44 }
45}
46# endif /* __ASSEMBLY__ */
47# define IDE_LED(x) ide_led((x))
48#endif /* CONFIG_KUP4K */
49
50/*
51 * Definitions for IDE0 Interface
52 */
53#define IDE0_BASE_OFFSET 0
54#define IDE0_DATA_REG_OFFSET (PCMCIA_MEM_SIZE + 0x320)
55#define IDE0_ERROR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 1)
56#define IDE0_NSECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 2)
57#define IDE0_SECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 3)
58#define IDE0_LCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 4)
59#define IDE0_HCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 5)
60#define IDE0_SELECT_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 6)
61#define IDE0_STATUS_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 7)
62#define IDE0_CONTROL_REG_OFFSET 0x0106
63#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
64
65/* define IO_BASE for PCMCIA */
66#define _IO_BASE 0x80000000
67#define _IO_BASE_SIZE (64<<10)
68
69#define FEC_INTERRUPT 9 /* = SIU_LEVEL4 */
70#define PHY_INTERRUPT 12 /* = IRQ6 */
71#define IDE0_INTERRUPT 13
72
73#ifdef CONFIG_IDE
74#endif
75
76/*-----------------------------------------------------------------------
77 * CPM Ethernet through SCCx.
78 *-----------------------------------------------------------------------
79 *
80 */
81
82/*** TQM823L, TQM850L ***********************************************/
83
84#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L)
85/* Bits in parallel I/O port registers that have to be set/cleared
86 * to configure the pins for SCC1 use.
87 */
88#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
89#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
90#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
91#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
92
93#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
94
95#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
96#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
97
98/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
99 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
100 */
101#define SICR_ENET_MASK ((uint)0x0000ff00)
102#define SICR_ENET_CLKRT ((uint)0x00002600)
103#endif /* CONFIG_TQM823L, CONFIG_TQM850L */
104
105/*** TQM860L ********************************************************/
106
107#ifdef CONFIG_TQM860L
108/* Bits in parallel I/O port registers that have to be set/cleared
109 * to configure the pins for SCC1 use.
110 */
111#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
112#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
113#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
114#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
115
116#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
117#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
118#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
119
120/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
121 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
122 */
123#define SICR_ENET_MASK ((uint)0x000000ff)
124#define SICR_ENET_CLKRT ((uint)0x00000026)
125#endif /* CONFIG_TQM860L */
126
127/*** FPS850L *********************************************************/
128
129#ifdef CONFIG_FPS850L
130/* Bits in parallel I/O port registers that have to be set/cleared
131 * to configure the pins for SCC1 use.
132 */
133#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
134#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
135#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
136#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
137
138#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
139#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
140#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
141
142/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
143 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
144 */
145#define SICR_ENET_MASK ((uint)0x0000ff00)
146#define SICR_ENET_CLKRT ((uint)0x00002600)
147#endif /* CONFIG_FPS850L */
148
149/* We don't use the 8259.
150*/
151#define NR_8259_INTS 0
152
153#endif /* !__ASSEMBLY__ */
154#endif /* __MACH_TQM8xx_H */
155#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 22:34:54 -0500