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-rw-r--r--arch/ppc/platforms/4xx/cpci405.c201
1 files changed, 0 insertions, 201 deletions
diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c
deleted file mode 100644
index 2e7e25dd84cb..000000000000
--- a/arch/ppc/platforms/4xx/cpci405.c
+++ /dev/null
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1/*
2 * Board setup routines for the esd CPCI-405 cPCI Board.
3 *
4 * Copyright 2001-2006 esd electronic system design - hannover germany
5 *
6 * Authors: Matthias Fuchs
7 * matthias.fuchs@esd-electronics.com
8 * Stefan Roese
9 * stefan.roese@esd-electronics.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <asm/system.h>
21#include <asm/pci-bridge.h>
22#include <asm/machdep.h>
23#include <asm/todc.h>
24#include <linux/serial.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <asm/ocp.h>
28#include <asm/ibm_ocp_pci.h>
29#include <platforms/4xx/ibm405gp.h>
30
31#ifdef CONFIG_GEN_RTC
32void *cpci405_nvram;
33#endif
34
35extern bd_t __res;
36
37/*
38 * Some IRQs unique to CPCI-405.
39 */
40int __init
41ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
42{
43 static char pci_irq_table[][4] =
44 /*
45 * PCI IDSEL/INTPIN->INTLINE
46 * A B C D
47 */
48 {
49 {28, 29, 30, 27}, /* IDSEL 15 - cPCI slot 8 */
50 {29, 30, 27, 28}, /* IDSEL 16 - cPCI slot 7 */
51 {30, 27, 28, 29}, /* IDSEL 17 - cPCI slot 6 */
52 {27, 28, 29, 30}, /* IDSEL 18 - cPCI slot 5 */
53 {28, 29, 30, 27}, /* IDSEL 19 - cPCI slot 4 */
54 {29, 30, 27, 28}, /* IDSEL 20 - cPCI slot 3 */
55 {30, 27, 28, 29}, /* IDSEL 21 - cPCI slot 2 */
56 };
57 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
58 return PCI_IRQ_TABLE_LOOKUP;
59};
60
61/* The serial clock for the chip is an internal clock determined by
62 * different clock speeds/dividers.
63 * Calculate the proper input baud rate and setup the serial driver.
64 */
65static void __init
66cpci405_early_serial_map(void)
67{
68 u32 uart_div;
69 int uart_clock;
70 struct uart_port port;
71
72 /* Calculate the serial clock input frequency
73 *
74 * The uart clock is the cpu frequency (provided in the board info
75 * structure) divided by the external UART Divisor.
76 */
77 uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
78 uart_clock = __res.bi_procfreq / uart_div;
79
80 /* Setup serial port access */
81 memset(&port, 0, sizeof(port));
82#if defined(CONFIG_UART0_TTYS0)
83 port.membase = (void*)UART0_IO_BASE;
84 port.irq = UART0_INT;
85#else
86 port.membase = (void*)UART1_IO_BASE;
87 port.irq = UART1_INT;
88#endif
89 port.uartclk = uart_clock;
90 port.regshift = 0;
91 port.iotype = UPIO_MEM;
92 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
93 port.line = 0;
94
95 if (early_serial_setup(&port) != 0) {
96 printk("Early serial init of port 0 failed\n");
97 }
98#if defined(CONFIG_UART0_TTYS0)
99 port.membase = (void*)UART1_IO_BASE;
100 port.irq = UART1_INT;
101#else
102 port.membase = (void*)UART0_IO_BASE;
103 port.irq = UART0_INT;
104#endif
105 port.line = 1;
106
107 if (early_serial_setup(&port) != 0) {
108 printk("Early serial init of port 1 failed\n");
109 }
110}
111
112void __init
113cpci405_setup_arch(void)
114{
115 ppc4xx_setup_arch();
116
117 ibm_ocp_set_emac(0, 0);
118
119 cpci405_early_serial_map();
120
121#ifdef CONFIG_GEN_RTC
122 TODC_INIT(TODC_TYPE_MK48T35,
123 cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
124#endif
125}
126
127void __init
128bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
129{
130#ifdef CONFIG_PCI
131 unsigned int bar_response, bar;
132
133 /* Disable region first */
134 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
135 /* PLB starting addr, PCI: 0x80000000 */
136 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
137 /* PCI start addr, 0x80000000 */
138 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
139 /* 512MB range of PLB to PCI */
140 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
141 /* Enable no pre-fetch, enable region */
142 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
143 (PPC405_PCI_UPPER_MEM -
144 PPC405_PCI_MEM_BASE)) | 0x01));
145
146 /* Disable region one */
147 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
148 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
149 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
150 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
151 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
152 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
153
154 /* Disable region two */
155 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
156 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
157 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
158 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
159 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
160 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
161 out_le32((void *) &(pcip->ptm2la), 0x00000000);
162
163 /* Zero config bars */
164 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
165 early_write_config_dword(hose, hose->first_busno,
166 PCI_FUNC(hose->first_busno), bar,
167 0x00000000);
168 early_read_config_dword(hose, hose->first_busno,
169 PCI_FUNC(hose->first_busno), bar,
170 &bar_response);
171 }
172#endif
173}
174
175void __init
176cpci405_map_io(void)
177{
178 ppc4xx_map_io();
179
180#ifdef CONFIG_GEN_RTC
181 cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
182#endif
183}
184
185void __init
186platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
187 unsigned long r6, unsigned long r7)
188{
189 ppc4xx_init(r3, r4, r5, r6, r7);
190
191 ppc_md.setup_arch = cpci405_setup_arch;
192 ppc_md.setup_io_mappings = cpci405_map_io;
193
194#ifdef CONFIG_GEN_RTC
195 ppc_md.time_init = todc_time_init;
196 ppc_md.set_rtc_time = todc_set_rtc_time;
197 ppc_md.get_rtc_time = todc_get_rtc_time;
198 ppc_md.nvram_read_val = todc_direct_read_val;
199 ppc_md.nvram_write_val = todc_direct_write_val;
200#endif
201}