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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-12-15 19:24:25 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-12-15 19:24:25 -0500
commit1e7342e7789fa2ca9202701467428726cbcfd649 (patch)
treee0ad000924e9875bd2ea17bd0e04382491765a09 /arch/powerpc/boot/dts
parent78c5c68a4cf4329d17abfa469345ddf323d4fd62 (diff)
parent228d55053397e6d5325ca179c7ffe331de2846d3 (diff)
Merge remote-tracking branch 'jwb/next' into next
Conflicts: arch/powerpc/platforms/40x/ppc40x_simple.c
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/currituck.dts237
-rw-r--r--arch/powerpc/boot/dts/klondike.dts227
2 files changed, 464 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/currituck.dts b/arch/powerpc/boot/dts/currituck.dts
new file mode 100644
index 000000000000..b801dd06e573
--- /dev/null
+++ b/arch/powerpc/boot/dts/currituck.dts
@@ -0,0 +1,237 @@
1/*
2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 *
4 * Copyright © 2011 Tony Breeds IBM Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/memreserve/ 0x01f00000 0x00100000; // spin table
14
15/ {
16 #address-cells = <2>;
17 #size-cells = <2>;
18 model = "ibm,currituck";
19 compatible = "ibm,currituck";
20 dcr-parent = <&{/cpus/cpu@0}>;
21
22 aliases {
23 serial0 = &UART0;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";
32 model = "PowerPC,476";
33 reg = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
38 i-cache-size = <32768>;
39 d-cache-size = <32768>;
40 dcr-controller;
41 dcr-access-method = "native";
42 status = "ok";
43 };
44 cpu@1 {
45 device_type = "cpu";
46 model = "PowerPC,476";
47 reg = <1>;
48 clock-frequency = <1600000000>; // 1.6 GHz
49 timebase-frequency = <100000000>; // 100Mhz
50 i-cache-line-size = <32>;
51 d-cache-line-size = <32>;
52 i-cache-size = <32768>;
53 d-cache-size = <32768>;
54 dcr-controller;
55 dcr-access-method = "native";
56 status = "disabled";
57 enable-method = "spin-table";
58 cpu-release-addr = <0x0 0x01f00000>;
59 };
60 };
61
62 memory {
63 device_type = "memory";
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
65 };
66
67 MPIC: interrupt-controller {
68 compatible = "chrp,open-pic";
69 interrupt-controller;
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
73 #interrupt-cells = <2>;
74
75 };
76
77 plb {
78 compatible = "ibm,plb6";
79 #address-cells = <2>;
80 #size-cells = <2>;
81 ranges;
82 clock-frequency = <200000000>; // 200Mhz
83
84 POB0: opb {
85 compatible = "ibm,opb-4xx", "ibm,opb";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 /* Wish there was a nicer way of specifying a full
89 * 32-bit range
90 */
91 ranges = <0x00000000 0x00000200 0x00000000 0x80000000
92 0x80000000 0x00000200 0x80000000 0x80000000>;
93 clock-frequency = <100000000>;
94
95 UART0: serial@10000000 {
96 device_type = "serial";
97 compatible = "ns16750", "ns16550";
98 reg = <0x10000000 0x00000008>;
99 virtual-reg = <0xe1000000>;
100 clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
101 current-speed = <115200>;
102 interrupt-parent = <&MPIC>;
103 interrupts = <34 2>;
104 };
105
106 IIC0: i2c@00000000 {
107 compatible = "ibm,iic-currituck", "ibm,iic";
108 reg = <0x0 0x00000014>;
109 interrupt-parent = <&MPIC>;
110 interrupts = <79 2>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 rtc@68 {
114 compatible = "stm,m41t80", "m41st85";
115 reg = <0x68>;
116 };
117 };
118 };
119
120 PCIE0: pciex@10100000000 { // 4xGBIF1
121 device_type = "pci";
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
126 primary;
127 port = <0x0>; /* port number */
128 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
129 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
130 dcr-reg = <0x80 0x20>;
131
132// pci_space < pci_addr > < cpu_addr > < size >
133 ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
134 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
135
136 /* Inbound starting at 0 to memsize filled in by zImage */
137 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
138
139 /* This drives busses 0 to 0xf */
140 bus-range = <0x0 0xf>;
141
142 /* Legacy interrupts (note the weird polarity, the bridge seems
143 * to invert PCIe legacy interrupts).
144 * We are de-swizzling here because the numbers are actually for
145 * port of the root complex virtual P2P bridge. But I want
146 * to avoid putting a node for it in the tree, so the numbers
147 * below are basically de-swizzled numbers.
148 * The real slot is on idsel 0, so the swizzling is 1:1
149 */
150 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
151 interrupt-map = <
152 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
153 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
154 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
155 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
156 };
157
158 PCIE1: pciex@30100000000 { // 4xGBIF0
159 device_type = "pci";
160 #interrupt-cells = <1>;
161 #size-cells = <2>;
162 #address-cells = <3>;
163 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
164 primary;
165 port = <0x1>; /* port number */
166 reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */
167 0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
168 dcr-reg = <0x60 0x20>;
169
170 ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
171 0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>;
172
173 /* Inbound starting at 0 to memsize filled in by zImage */
174 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
175
176 /* This drives busses 0 to 0xf */
177 bus-range = <0x0 0xf>;
178
179 /* Legacy interrupts (note the weird polarity, the bridge seems
180 * to invert PCIe legacy interrupts).
181 * We are de-swizzling here because the numbers are actually for
182 * port of the root complex virtual P2P bridge. But I want
183 * to avoid putting a node for it in the tree, so the numbers
184 * below are basically de-swizzled numbers.
185 * The real slot is on idsel 0, so the swizzling is 1:1
186 */
187 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
188 interrupt-map = <
189 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
190 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
191 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
192 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
193 };
194
195 PCIE2: pciex@38100000000 { // 2xGBIF0
196 device_type = "pci";
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
201 primary;
202 port = <0x2>; /* port number */
203 reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */
204 0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
205 dcr-reg = <0xA0 0x20>;
206
207 ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
208 0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>;
209
210 /* Inbound starting at 0 to memsize filled in by zImage */
211 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
212
213 /* This drives busses 0 to 0xf */
214 bus-range = <0x0 0xf>;
215
216 /* Legacy interrupts (note the weird polarity, the bridge seems
217 * to invert PCIe legacy interrupts).
218 * We are de-swizzling here because the numbers are actually for
219 * port of the root complex virtual P2P bridge. But I want
220 * to avoid putting a node for it in the tree, so the numbers
221 * below are basically de-swizzled numbers.
222 * The real slot is on idsel 0, so the swizzling is 1:1
223 */
224 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
225 interrupt-map = <
226 0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
227 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
228 0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
229 0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
230 };
231
232 };
233
234 chosen {
235 linux,stdout-path = &UART0;
236 };
237};
diff --git a/arch/powerpc/boot/dts/klondike.dts b/arch/powerpc/boot/dts/klondike.dts
new file mode 100644
index 000000000000..8c9429033618
--- /dev/null
+++ b/arch/powerpc/boot/dts/klondike.dts
@@ -0,0 +1,227 @@
1/*
2 * Device Tree for Klondike (APM8018X) board.
3 *
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tanmay Inamdar <tinamdar@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24/dts-v1/;
25
26/ {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 model = "apm,klondike";
30 compatible = "apm,klondike";
31 dcr-parent = <&{/cpus/cpu@0}>;
32
33 aliases {
34 ethernet0 = &EMAC0;
35 ethernet1 = &EMAC1;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu@0 {
43 device_type = "cpu";
44 model = "PowerPC,apm8018x";
45 reg = <0x00000000>;
46 clock-frequency = <300000000>; /* Filled in by U-Boot */
47 timebase-frequency = <300000000>; /* Filled in by U-Boot */
48 i-cache-line-size = <32>;
49 d-cache-line-size = <32>;
50 i-cache-size = <16384>; /* 16 kB */
51 d-cache-size = <16384>; /* 16 kB */
52 dcr-controller;
53 dcr-access-method = "native";
54 };
55 };
56
57 memory {
58 device_type = "memory";
59 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
60 };
61
62 UIC0: interrupt-controller {
63 compatible = "ibm,uic";
64 interrupt-controller;
65 cell-index = <0>;
66 dcr-reg = <0x0c0 0x010>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 };
71
72 UIC1: interrupt-controller1 {
73 compatible = "ibm,uic";
74 interrupt-controller;
75 cell-index = <1>;
76 dcr-reg = <0x0d0 0x010>;
77 #address-cells = <0>;
78 #size-cells = <0>;
79 #interrupt-cells = <2>;
80 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
81 interrupt-parent = <&UIC0>;
82 };
83
84 UIC2: interrupt-controller2 {
85 compatible = "ibm,uic";
86 interrupt-controller;
87 cell-index = <2>;
88 dcr-reg = <0x0e0 0x010>;
89 #address-cells = <0>;
90 #size-cells = <0>;
91 #interrupt-cells = <2>;
92 interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
93 interrupt-parent = <&UIC0>;
94 };
95
96 UIC3: interrupt-controller3 {
97 compatible = "ibm,uic";
98 interrupt-controller;
99 cell-index = <3>;
100 dcr-reg = <0x0f0 0x010>;
101 #address-cells = <0>;
102 #size-cells = <0>;
103 #interrupt-cells = <2>;
104 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
105 interrupt-parent = <&UIC0>;
106 };
107
108 plb {
109 compatible = "ibm,plb4";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges;
113 clock-frequency = <0>; /* Filled in by U-Boot */
114
115 SDRAM0: memory-controller {
116 compatible = "ibm,sdram-apm8018x";
117 dcr-reg = <0x010 0x002>;
118 };
119
120 MAL0: mcmal {
121 compatible = "ibm,mcmal2";
122 dcr-reg = <0x180 0x062>;
123 num-tx-chans = <2>;
124 num-rx-chans = <16>;
125 #address-cells = <0>;
126 #size-cells = <0>;
127 interrupt-parent = <&UIC1>;
128 interrupts = </*TXEOB*/ 0x6 0x4
129 /*RXEOB*/ 0x7 0x4
130 /*SERR*/ 0x1 0x4
131 /*TXDE*/ 0x2 0x4
132 /*RXDE*/ 0x3 0x4>;
133 };
134
135 POB0: opb {
136 compatible = "ibm,opb";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0x20000000 0x20000000 0x30000000
140 0x50000000 0x50000000 0x10000000
141 0x60000000 0x60000000 0x10000000
142 0xFE000000 0xFE000000 0x00010000>;
143 dcr-reg = <0x100 0x020>;
144 clock-frequency = <300000000>; /* Filled in by U-Boot */
145
146 RGMII0: emac-rgmii@400a2000 {
147 compatible = "ibm,rgmii";
148 reg = <0x400a2000 0x00000010>;
149 has-mdio;
150 };
151
152 TAH0: emac-tah@400a3000 {
153 compatible = "ibm,tah";
154 reg = <0x400a3000 0x100>;
155 };
156
157 TAH1: emac-tah@400a4000 {
158 compatible = "ibm,tah";
159 reg = <0x400a4000 0x100>;
160 };
161
162 EMAC0: ethernet@400a0000 {
163 compatible = "ibm,emac4", "ibm-emac4sync";
164 interrupt-parent = <&EMAC0>;
165 interrupts = <0x0>;
166 #interrupt-cells = <1>;
167 #address-cells = <0>;
168 #size-cells = <0>;
169 interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
170 reg = <0x400a0000 0x00000100>;
171 local-mac-address = [000000000000]; /* Filled in by U-Boot */
172 mal-device = <&MAL0>;
173 mal-tx-channel = <0x0>;
174 mal-rx-channel = <0x0>;
175 cell-index = <0>;
176 max-frame-size = <9000>;
177 rx-fifo-size = <4096>;
178 tx-fifo-size = <2048>;
179 phy-mode = "rgmii";
180 phy-address = <0x2>;
181 turbo = "no";
182 phy-map = <0x00000000>;
183 rgmii-device = <&RGMII0>;
184 rgmii-channel = <0>;
185 tah-device = <&TAH0>;
186 tah-channel = <0>;
187 has-inverted-stacr-oc;
188 has-new-stacr-staopc;
189 };
190
191 EMAC1: ethernet@400a1000 {
192 compatible = "ibm,emac4", "ibm-emac4sync";
193 status = "disabled";
194 interrupt-parent = <&EMAC1>;
195 interrupts = <0x0>;
196 #interrupt-cells = <1>;
197 #address-cells = <0>;
198 #size-cells = <0>;
199 interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
200 reg = <0x400a1000 0x00000100>;
201 local-mac-address = [000000000000]; /* Filled in by U-Boot */
202 mal-device = <&MAL0>;
203 mal-tx-channel = <1>;
204 mal-rx-channel = <8>;
205 cell-index = <1>;
206 max-frame-size = <9000>;
207 rx-fifo-size = <4096>;
208 tx-fifo-size = <2048>;
209 phy-mode = "rgmii";
210 phy-address = <0x3>;
211 turbo = "no";
212 phy-map = <0x00000000>;
213 rgmii-device = <&RGMII0>;
214 rgmii-channel = <1>;
215 tah-device = <&TAH1>;
216 tah-channel = <0>;
217 has-inverted-stacr-oc;
218 has-new-stacr-staopc;
219 mdio-device = <&EMAC0>;
220 };
221 };
222 };
223
224 chosen {
225 linux,stdout-path = "/plb/opb/serial@50001000";
226 };
227};
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