Merge remote-tracking branch 'jwb/next' into next

Conflicts:
	arch/powerpc/platforms/40x/ppc40x_simple.c

7 files changed, 648 insertions, 1 deletions

diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 80c133c88565..15986e70799c 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -45,6 +45,7 @@ $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
 $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
 
 
@@ -79,7 +80,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
                 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
                 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
                 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
-                gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c
+                gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c \
+                treeboot-currituck.c
 src-boot := $(src-wlib) $(src-plat) empty.c
 
 src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -213,6 +215,7 @@ image-$(CONFIG_WARP)			+= cuImage.warp
 image-$(CONFIG_YOSEMITE)                += cuImage.yosemite
 image-$(CONFIG_ISS4xx)                  += treeImage.iss4xx \
                                            treeImage.iss4xx-mpic
+image-$(CONFIG_CURRITUCK)                       += treeImage.currituck
 
 # Board ports in arch/powerpc/platform/8xx/Kconfig
 image-$(CONFIG_MPC86XADS)               += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 645a7c964e5f..cc73f7a95e26 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -9,6 +9,12 @@
         })
 #define mtdcr(rn, val) \
         asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
+#define mfdcrx(rn) \
+        ({      \
+                unsigned long rval; \
+                asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
+                rval; \
+        })
 
 /* 440GP/440GX SDRAM controller DCRs */
 #define DCRN_SDRAM0_CFGADDR                             0x010
diff --git a/arch/powerpc/boot/div64.S b/arch/powerpc/boot/div64.S
index d271ab542673..bbcb8a4cc121 100644
--- a/arch/powerpc/boot/div64.S
+++ b/arch/powerpc/boot/div64.S
@@ -57,3 +57,55 @@ __div64_32:
         stw     r8,4(r3)
         mr      r3,r6           # return the remainder in r3
         blr
+
+/*
+ * Extended precision shifts.
+ *
+ * Updated to be valid for shift counts from 0 to 63 inclusive.
+ * -- Gabriel
+ *
+ * R3/R4 has 64 bit value
+ * R5    has shift count
+ * result in R3/R4
+ *
+ *  ashrdi3: arithmetic right shift (sign propagation)  
+ *  lshrdi3: logical right shift
+ *  ashldi3: left shift
+ */
+        .globl __ashrdi3
+__ashrdi3:
+        subfic  r6,r5,32
+        srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
+        addi    r7,r5,32        # could be xori, or addi with -32
+        slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
+        rlwinm  r8,r7,0,32      # t3 = (count < 32) ? 32 : 0
+        sraw    r7,r3,r7        # t2 = MSW >> (count-32)
+        or      r4,r4,r6        # LSW |= t1
+        slw     r7,r7,r8        # t2 = (count < 32) ? 0 : t2
+        sraw    r3,r3,r5        # MSW = MSW >> count
+        or      r4,r4,r7        # LSW |= t2
+        blr
+
+        .globl __ashldi3
+__ashldi3:
+        subfic  r6,r5,32
+        slw     r3,r3,r5        # MSW = count > 31 ? 0 : MSW << count
+        addi    r7,r5,32        # could be xori, or addi with -32
+        srw     r6,r4,r6        # t1 = count > 31 ? 0 : LSW >> (32-count)
+        slw     r7,r4,r7        # t2 = count < 32 ? 0 : LSW << (count-32)
+        or      r3,r3,r6        # MSW |= t1
+        slw     r4,r4,r5        # LSW = LSW << count
+        or      r3,r3,r7        # MSW |= t2
+        blr
+
+        .globl __lshrdi3
+__lshrdi3:
+        subfic  r6,r5,32
+        srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
+        addi    r7,r5,32        # could be xori, or addi with -32
+        slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
+        srw     r7,r3,r7        # t2 = count < 32 ? 0 : MSW >> (count-32)
+        or      r4,r4,r6        # LSW |= t1
+        srw     r3,r3,r5        # MSW = MSW >> count
+        or      r4,r4,r7        # LSW |= t2
+        blr
diff --git a/arch/powerpc/boot/dts/currituck.dts b/arch/powerpc/boot/dts/currituck.dts
new file mode 100644
index 000000000000..b801dd06e573
--- /dev/null
+++ b/arch/powerpc/boot/dts/currituck.dts
@@ -0,0 +1,237 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright © 2011 Tony Breeds IBM Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x01f00000 0x00100000;     // spin table
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        model = "ibm,currituck";
+        compatible = "ibm,currituck";
+        dcr-parent = <&{/cpus/cpu@0}>;
+
+        aliases {
+                serial0 = &UART0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,476";
+                        reg = <0>;
+                        clock-frequency = <1600000000>; // 1.6 GHz
+                        timebase-frequency = <100000000>; // 100Mhz
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "ok";
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        model = "PowerPC,476";
+                        reg = <1>;
+                        clock-frequency = <1600000000>; // 1.6 GHz
+                        timebase-frequency = <100000000>; // 100Mhz
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "disabled";
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x01f00000>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
+        };
+
+        MPIC: interrupt-controller {
+                compatible = "chrp,open-pic";
+                interrupt-controller;
+                dcr-reg = <0xffc00000 0x00040000>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+
+        };
+
+        plb {
+                compatible = "ibm,plb6";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                clock-frequency = <200000000>; // 200Mhz
+
+                POB0: opb {
+                        compatible = "ibm,opb-4xx", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /* Wish there was a nicer way of specifying a full
+                         * 32-bit range
+                         */
+                        ranges = <0x00000000 0x00000200 0x00000000 0x80000000
+                                  0x80000000 0x00000200 0x80000000 0x80000000>;
+                        clock-frequency = <100000000>;
+
+                        UART0: serial@10000000 {
+                                device_type = "serial";
+                                compatible = "ns16750", "ns16550";
+                                reg = <0x10000000 0x00000008>;
+                                virtual-reg = <0xe1000000>;
+                                clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
+                                current-speed = <115200>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <34 2>;
+                        };
+
+                        IIC0: i2c@00000000 {
+                                compatible = "ibm,iic-currituck", "ibm,iic";
+                                reg = <0x0 0x00000014>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <79 2>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rtc@68 {
+                                        compatible = "stm,m41t80", "m41st85";
+                                        reg = <0x68>;
+                                };
+                        };
+                };
+
+                PCIE0: pciex@10100000000 {              // 4xGBIF1
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x0>; /* port number */
+                        reg = <0x00000101 0x00000000 0x0 0x10000000             /* Config space access */
+                               0x00000100 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0x80 0x20>;
+
+//                                pci_space  < pci_addr          > < cpu_addr          > < size       >
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x00000140 0x0        0x0 0x00010000>;
+
+                        /* Inbound starting at 0 to memsize filled in by zImage */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
+
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
+                };
+
+                PCIE1: pciex@30100000000 {              // 4xGBIF0
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x1>; /* port number */
+                        reg = <0x00000301 0x00000000 0x0 0x10000000             /* Config space access */
+                               0x00000300 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0x60 0x20>;
+
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x00000340 0x0        0x0 0x00010000>;
+
+                        /* Inbound starting at 0 to memsize filled in by zImage */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
+
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
+                };
+
+                PCIE2: pciex@38100000000 {              // 2xGBIF0
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x2>; /* port number */
+                        reg = <0x00000381 0x00000000 0x0 0x10000000             /* Config space access */
+                               0x00000380 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0xA0 0x20>;
+
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x000003C0 0x0        0x0 0x00010000>;
+
+                        /* Inbound starting at 0 to memsize filled in by zImage */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
+
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
+                };
+
+        };
+
+        chosen {
+                linux,stdout-path = &UART0;
+        };
+};
diff --git a/arch/powerpc/boot/dts/klondike.dts b/arch/powerpc/boot/dts/klondike.dts
new file mode 100644
index 000000000000..8c9429033618
--- /dev/null
+++ b/arch/powerpc/boot/dts/klondike.dts
@@ -0,0 +1,227 @@
+/*
+ * Device Tree for Klondike (APM8018X) board.
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tanmay Inamdar <tinamdar@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/dts-v1/;
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        model = "apm,klondike";
+        compatible = "apm,klondike";
+        dcr-parent = <&{/cpus/cpu@0}>;
+
+        aliases {
+                ethernet0 = &EMAC0;
+                ethernet1 = &EMAC1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,apm8018x";
+                        reg = <0x00000000>;
+                        clock-frequency = <300000000>; /* Filled in by U-Boot */
+                        timebase-frequency = <300000000>; /* Filled in by U-Boot */
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <16384>; /* 16 kB */
+                        d-cache-size = <16384>; /* 16 kB */
+                        dcr-controller;
+                        dcr-access-method = "native";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
+        };
+
+        UIC0: interrupt-controller {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <0>;
+                dcr-reg = <0x0c0 0x010>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+
+        UIC1: interrupt-controller1 {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <1>;
+                dcr-reg = <0x0d0 0x010>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        UIC2: interrupt-controller2 {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <2>;
+                dcr-reg = <0x0e0 0x010>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        UIC3: interrupt-controller3 {
+                compatible = "ibm,uic";
+                interrupt-controller;
+                cell-index = <3>;
+                dcr-reg = <0x0f0 0x010>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        plb {
+                compatible = "ibm,plb4";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; /* Filled in by U-Boot */
+
+                SDRAM0: memory-controller {
+                        compatible = "ibm,sdram-apm8018x";
+                        dcr-reg = <0x010 0x002>;
+                };
+
+                MAL0: mcmal {
+                        compatible = "ibm,mcmal2";
+                        dcr-reg = <0x180 0x062>;
+                        num-tx-chans = <2>;
+                        num-rx-chans = <16>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&UIC1>;
+                        interrupts = </*TXEOB*/   0x6 0x4
+                                        /*RXEOB*/ 0x7 0x4
+                                        /*SERR*/  0x1 0x4
+                                        /*TXDE*/  0x2 0x4
+                                        /*RXDE*/  0x3 0x4>;
+                };
+
+                POB0: opb {
+                        compatible = "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x20000000 0x20000000 0x30000000
+                                  0x50000000 0x50000000 0x10000000
+                                  0x60000000 0x60000000 0x10000000
+                                  0xFE000000 0xFE000000 0x00010000>;
+                        dcr-reg = <0x100 0x020>;
+                        clock-frequency = <300000000>; /* Filled in by U-Boot */
+
+                        RGMII0: emac-rgmii@400a2000 {
+                                compatible = "ibm,rgmii";
+                                reg = <0x400a2000 0x00000010>;
+                                has-mdio;
+                        };
+
+                        TAH0: emac-tah@400a3000 {
+                                compatible = "ibm,tah";
+                                reg = <0x400a3000 0x100>;
+                        };
+
+                        TAH1: emac-tah@400a4000 {
+                                compatible = "ibm,tah";
+                                reg = <0x400a4000 0x100>;
+                        };
+
+                        EMAC0: ethernet@400a0000 {
+                                compatible = "ibm,emac4", "ibm-emac4sync";
+                                interrupt-parent = <&EMAC0>;
+                                interrupts = <0x0>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
+                                reg = <0x400a0000 0x00000100>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <0x0>;
+                                mal-rx-channel = <0x0>;
+                                cell-index = <0>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                phy-mode = "rgmii";
+                                phy-address = <0x2>;
+                                turbo = "no";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <0>;
+                                tah-device = <&TAH0>;
+                                tah-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                        };
+
+                        EMAC1: ethernet@400a1000 {
+                                compatible = "ibm,emac4", "ibm-emac4sync";
+                                status = "disabled";
+                                interrupt-parent = <&EMAC1>;
+                                interrupts = <0x0>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
+                                reg = <0x400a1000 0x00000100>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <1>;
+                                mal-rx-channel = <8>;
+                                cell-index = <1>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                phy-mode = "rgmii";
+                                phy-address = <0x3>;
+                                turbo = "no";
+                                phy-map = <0x00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <1>;
+                                tah-device = <&TAH1>;
+                                tah-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+                };
+        };
+
+        chosen {
+                linux,stdout-path = "/plb/opb/serial@50001000";
+        };
+};
diff --git a/arch/powerpc/boot/treeboot-currituck.c b/arch/powerpc/boot/treeboot-currituck.c
new file mode 100644
index 000000000000..925ae43b7467
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-currituck.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright © 2011 Tony Breeds IBM Corporation
+ *
+ * Based on earlier code:
+ *   Copyright (C) Paul Mackerras 1997.
+ *
+ *   Matt Porter <mporter@kernel.crashing.org>
+ *   Copyright 2002-2005 MontaVista Software Inc.
+ *
+ *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ *   Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ *    Copyright 2007 David Gibson, IBM Corporation.
+ *    Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
+ *    Copyright © 2011 David Kleikamp IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "string.h"
+#include "stdio.h"
+#include "page.h"
+#include "ops.h"
+#include "reg.h"
+#include "io.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "44x.h"
+#include "libfdt.h"
+
+BSS_STACK(4096);
+
+#define MAX_RANKS       0x4
+#define DDR3_MR0CF      0x80010011U
+
+static unsigned long long ibm_currituck_memsize;
+static unsigned long long ibm_currituck_detect_memsize(void)
+{
+        u32 reg;
+        unsigned i;
+        unsigned long long memsize = 0;
+
+        for(i = 0; i < MAX_RANKS; i++){
+                reg = mfdcrx(DDR3_MR0CF + i);
+
+                if (!(reg & 1))
+                        continue;
+
+                reg &= 0x0000f000;
+                reg >>= 12;
+                memsize += (0x800000ULL << reg);
+        }
+
+        return memsize;
+}
+
+static void ibm_currituck_fixups(void)
+{
+        void *devp = finddevice("/");
+        u32 dma_ranges[7];
+
+        dt_fixup_memory(0x0ULL,  ibm_currituck_memsize);
+
+        while ((devp = find_node_by_devtype(devp, "pci"))) {
+                if (getprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges)) < 0) {
+                        printf("%s: Failed to get dma-ranges\r\n", __func__);
+                        continue;
+                }
+
+                dma_ranges[5] = ibm_currituck_memsize >> 32;
+                dma_ranges[6] = ibm_currituck_memsize & 0xffffffffUL;
+
+                setprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges));
+        }
+}
+
+#define SPRN_PIR        0x11E   /* Processor Indentification Register */
+void platform_init(void)
+{
+        unsigned long end_of_ram, avail_ram;
+        u32 pir_reg;
+        int node, size;
+        const u32 *timebase;
+
+        ibm_currituck_memsize = ibm_currituck_detect_memsize();
+        if (ibm_currituck_memsize >> 32)
+                end_of_ram = ~0UL;
+        else
+                end_of_ram = ibm_currituck_memsize;
+        avail_ram = end_of_ram - (unsigned long)_end;
+
+        simple_alloc_init(_end, avail_ram, 128, 64);
+        platform_ops.fixups = ibm_currituck_fixups;
+        platform_ops.exit = ibm44x_dbcr_reset;
+        pir_reg = mfspr(SPRN_PIR);
+
+        /* Make sure FDT blob is sane */
+        if (fdt_check_header(_dtb_start) != 0)
+                fatal("Invalid device tree blob\n");
+
+        node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+                                             "cpu", sizeof("cpu"));
+        if (!node)
+                fatal("Cannot find cpu node\n");
+        timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
+        if (timebase && (size == 4))
+                timebase_period_ns = 1000000000 / *timebase;
+
+        fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
+        fdt_init(_dtb_start);
+
+        serial_console_init();
+}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 14cd4bca8b8a..eb78e437ec1b 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -244,6 +244,9 @@ gamecube|wii)
     link_address='0x600000'
     platformo="$object/$platform-head.o $object/$platform.o"
     ;;
+treeboot-currituck)
+    link_address='0x1000000'
+    ;;
 treeboot-iss4xx-mpic)
     platformo="$object/treeboot-iss4xx.o"
     ;;