Merge remote-tracking branch 'linus/master' into testing

6 files changed, 388 insertions, 11 deletions

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 336228990808..19f9134bfe2f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
  * compile time if only one CPU support is enabled (idea stolen from
  * arm mach-types)
  */
+#define BCM3368_CPU_ID          0x3368
 #define BCM6328_CPU_ID          0x6328
 #define BCM6338_CPU_ID          0x6338
 #define BCM6345_CPU_ID          0x6345
@@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
 u8 bcm63xx_get_cpu_rev(void);
 unsigned int bcm63xx_get_cpu_freq(void);
 
+#ifdef CONFIG_BCM63XX_CPU_3368
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id()  BCM3368_CPU_ID
+# endif
+# define BCMCPU_IS_3368()       (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
+#else
+# define BCMCPU_IS_3368()       (0)
+#endif
+
 #ifdef CONFIG_BCM63XX_CPU_6328
 # ifdef bcm63xx_get_cpu_id
 #  undef bcm63xx_get_cpu_id
@@ -173,7 +187,10 @@ enum bcm63xx_regs_set {
 #define BCM_6358_RSET_SPI_SIZE          1804
 #define BCM_6368_RSET_SPI_SIZE          1804
 #define RSET_ENET_SIZE                  2048
-#define RSET_ENETDMA_SIZE               2048
+#define RSET_ENETDMA_SIZE               256
+#define RSET_6345_ENETDMA_SIZE          64
+#define RSET_ENETDMAC_SIZE(chans)       (16 * (chans))
+#define RSET_ENETDMAS_SIZE(chans)       (16 * (chans))
 #define RSET_ENETSW_SIZE                65536
 #define RSET_UART_SIZE                  24
 #define RSET_UDC_SIZE                   256
@@ -191,6 +208,53 @@ enum bcm63xx_regs_set {
 #define RSET_RNG_SIZE                   20
 
 /*
+ * 3368 register sets base address
+ */
+#define BCM_3368_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_3368_PERF_BASE              (0xfff8c000)
+#define BCM_3368_TIMER_BASE             (0xfff8c040)
+#define BCM_3368_WDT_BASE               (0xfff8c080)
+#define BCM_3368_UART0_BASE             (0xfff8c100)
+#define BCM_3368_UART1_BASE             (0xfff8c120)
+#define BCM_3368_GPIO_BASE              (0xfff8c080)
+#define BCM_3368_SPI_BASE               (0xfff8c800)
+#define BCM_3368_HSSPI_BASE             (0xdeadbeef)
+#define BCM_3368_UDC0_BASE              (0xdeadbeef)
+#define BCM_3368_USBDMA_BASE            (0xdeadbeef)
+#define BCM_3368_OHCI0_BASE             (0xdeadbeef)
+#define BCM_3368_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_3368_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_3368_USBD_BASE              (0xdeadbeef)
+#define BCM_3368_MPI_BASE               (0xfff80000)
+#define BCM_3368_PCMCIA_BASE            (0xfff80054)
+#define BCM_3368_PCIE_BASE              (0xdeadbeef)
+#define BCM_3368_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_3368_DSL_BASE               (0xdeadbeef)
+#define BCM_3368_UBUS_BASE              (0xdeadbeef)
+#define BCM_3368_ENET0_BASE             (0xfff98000)
+#define BCM_3368_ENET1_BASE             (0xfff98800)
+#define BCM_3368_ENETDMA_BASE           (0xfff99800)
+#define BCM_3368_ENETDMAC_BASE          (0xfff99900)
+#define BCM_3368_ENETDMAS_BASE          (0xfff99a00)
+#define BCM_3368_ENETSW_BASE            (0xdeadbeef)
+#define BCM_3368_EHCI0_BASE             (0xdeadbeef)
+#define BCM_3368_SDRAM_BASE             (0xdeadbeef)
+#define BCM_3368_MEMC_BASE              (0xfff84000)
+#define BCM_3368_DDR_BASE               (0xdeadbeef)
+#define BCM_3368_M2M_BASE               (0xdeadbeef)
+#define BCM_3368_ATM_BASE               (0xdeadbeef)
+#define BCM_3368_XTM_BASE               (0xdeadbeef)
+#define BCM_3368_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_3368_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_3368_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_3368_PCM_BASE               (0xfff9c200)
+#define BCM_3368_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_3368_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_3368_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_3368_RNG_BASE               (0xdeadbeef)
+#define BCM_3368_MISC_BASE              (0xdeadbeef)
+
+/*
  * 6328 register sets base address
  */
 #define BCM_6328_DSL_LMEM_BASE          (0xdeadbeef)
@@ -235,6 +299,8 @@ enum bcm63xx_regs_set {
 #define BCM_6328_PCMDMAS_BASE           (0xdeadbeef)
 #define BCM_6328_RNG_BASE               (0xdeadbeef)
 #define BCM_6328_MISC_BASE              (0xb0001800)
+#define BCM_6328_OTP_BASE               (0xb0000600)
+
 /*
  * 6338 register sets base address
  */
@@ -298,7 +364,7 @@ enum bcm63xx_regs_set {
 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 #define BCM_6345_ENET0_BASE             (0xfffe1800)
 #define BCM_6345_ENETDMA_BASE           (0xfffe2800)
-#define BCM_6345_ENETDMAC_BASE          (0xfffe2900)
+#define BCM_6345_ENETDMAC_BASE          (0xfffe2840)
 #define BCM_6345_ENETDMAS_BASE          (0xfffe2a00)
 #define BCM_6345_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE            (0xfffe2028)
@@ -620,6 +686,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 #ifdef BCMCPU_RUNTIME_DETECT
         return bcm63xx_regs_base[set];
 #else
+#ifdef CONFIG_BCM63XX_CPU_3368
+        __GEN_RSET(3368)
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6328
         __GEN_RSET(6328)
 #endif
@@ -687,6 +756,52 @@ enum bcm63xx_irq {
 };
 
 /*
+ * 3368 irqs
+ */
+#define BCM_3368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_3368_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
+#define BCM_3368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_3368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_3368_DSL_IRQ                0
+#define BCM_3368_UDC0_IRQ               0
+#define BCM_3368_OHCI0_IRQ              0
+#define BCM_3368_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_3368_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
+#define BCM_3368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_3368_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
+#define BCM_3368_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
+#define BCM_3368_HSSPI_IRQ              0
+#define BCM_3368_EHCI0_IRQ              0
+#define BCM_3368_USBD_IRQ               0
+#define BCM_3368_USBD_RXDMA0_IRQ        0
+#define BCM_3368_USBD_TXDMA0_IRQ        0
+#define BCM_3368_USBD_RXDMA1_IRQ        0
+#define BCM_3368_USBD_TXDMA1_IRQ        0
+#define BCM_3368_USBD_RXDMA2_IRQ        0
+#define BCM_3368_USBD_TXDMA2_IRQ        0
+#define BCM_3368_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
+#define BCM_3368_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
+#define BCM_3368_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
+#define BCM_3368_PCMCIA_IRQ             0
+#define BCM_3368_ATM_IRQ                0
+#define BCM_3368_ENETSW_RXDMA0_IRQ      0
+#define BCM_3368_ENETSW_RXDMA1_IRQ      0
+#define BCM_3368_ENETSW_RXDMA2_IRQ      0
+#define BCM_3368_ENETSW_RXDMA3_IRQ      0
+#define BCM_3368_ENETSW_TXDMA0_IRQ      0
+#define BCM_3368_ENETSW_TXDMA1_IRQ      0
+#define BCM_3368_ENETSW_TXDMA2_IRQ      0
+#define BCM_3368_ENETSW_TXDMA3_IRQ      0
+#define BCM_3368_XTM_IRQ                0
+#define BCM_3368_XTM_DMA0_IRQ           0
+
+#define BCM_3368_EXT_IRQ0               (IRQ_INTERNAL_BASE + 25)
+#define BCM_3368_EXT_IRQ1               (IRQ_INTERNAL_BASE + 26)
+#define BCM_3368_EXT_IRQ2               (IRQ_INTERNAL_BASE + 27)
+#define BCM_3368_EXT_IRQ3               (IRQ_INTERNAL_BASE + 28)
+
+
+/*
  * 6328 irqs
  */
 #define BCM_6328_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
index d53f611184b9..753953e86242 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -4,6 +4,8 @@
 #include <linux/if_ether.h>
 #include <linux/init.h>
 
+#include <bcm63xx_regs.h>
+
 /*
  * on board ethernet platform data
  */
@@ -37,9 +39,129 @@ struct bcm63xx_enet_platform_data {
                                           int phy_id, int reg),
                           void (*mii_write)(struct net_device *dev,
                                             int phy_id, int reg, int val));
+
+        /* DMA channel enable mask */
+        u32 dma_chan_en_mask;
+
+        /* DMA channel interrupt mask */
+        u32 dma_chan_int_mask;
+
+        /* DMA engine has internal SRAM */
+        bool dma_has_sram;
+
+        /* DMA channel register width */
+        unsigned int dma_chan_width;
+
+        /* DMA descriptor shift */
+        unsigned int dma_desc_shift;
+};
+
+/*
+ * on board ethernet switch platform data
+ */
+#define ENETSW_MAX_PORT 8
+#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
+#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
+
+#define ENETSW_RGMII_PORT0      4
+
+struct bcm63xx_enetsw_port {
+        int             used;
+        int             phy_id;
+
+        int             bypass_link;
+        int             force_speed;
+        int             force_duplex_full;
+
+        const char      *name;
+};
+
+struct bcm63xx_enetsw_platform_data {
+        char mac_addr[ETH_ALEN];
+        int num_ports;
+        struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
+
+        /* DMA channel enable mask */
+        u32 dma_chan_en_mask;
+
+        /* DMA channel interrupt mask */
+        u32 dma_chan_int_mask;
+
+        /* DMA channel register width */
+        unsigned int dma_chan_width;
+
+        /* DMA engine has internal SRAM */
+        bool dma_has_sram;
 };
 
 int __init bcm63xx_enet_register(int unit,
                                  const struct bcm63xx_enet_platform_data *pd);
 
+int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
+
+enum bcm63xx_regs_enetdmac {
+        ENETDMAC_CHANCFG,
+        ENETDMAC_IR,
+        ENETDMAC_IRMASK,
+        ENETDMAC_MAXBURST,
+        ENETDMAC_BUFALLOC,
+        ENETDMAC_RSTART,
+        ENETDMAC_FC,
+        ENETDMAC_LEN,
+};
+
+static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
+{
+#ifdef BCMCPU_RUNTIME_DETECT
+        extern const unsigned long *bcm63xx_regs_enetdmac;
+
+        return bcm63xx_regs_enetdmac[reg];
+#else
+#ifdef CONFIG_BCM63XX_CPU_6345
+        switch (reg) {
+        case ENETDMAC_CHANCFG:
+                return ENETDMA_6345_CHANCFG_REG;
+        case ENETDMAC_IR:
+                return ENETDMA_6345_IR_REG;
+        case ENETDMAC_IRMASK:
+                return ENETDMA_6345_IRMASK_REG;
+        case ENETDMAC_MAXBURST:
+                return ENETDMA_6345_MAXBURST_REG;
+        case ENETDMAC_BUFALLOC:
+                return ENETDMA_6345_BUFALLOC_REG;
+        case ENETDMAC_RSTART:
+                return ENETDMA_6345_RSTART_REG;
+        case ENETDMAC_FC:
+                return ENETDMA_6345_FC_REG;
+        case ENETDMAC_LEN:
+                return ENETDMA_6345_LEN_REG;
+        }
+#endif
+#if defined(CONFIG_BCM63XX_CPU_6328) || \
+        defined(CONFIG_BCM63XX_CPU_6338) || \
+        defined(CONFIG_BCM63XX_CPU_6348) || \
+        defined(CONFIG_BCM63XX_CPU_6358) || \
+        defined(CONFIG_BCM63XX_CPU_6362) || \
+        defined(CONFIG_BCM63XX_CPU_6368)
+        switch (reg) {
+        case ENETDMAC_CHANCFG:
+                return ENETDMAC_CHANCFG_REG;
+        case ENETDMAC_IR:
+                return ENETDMAC_IR_REG;
+        case ENETDMAC_IRMASK:
+                return ENETDMAC_IRMASK_REG;
+        case ENETDMAC_MAXBURST:
+                return ENETDMAC_MAXBURST_REG;
+        case ENETDMAC_BUFALLOC:
+        case ENETDMAC_RSTART:
+        case ENETDMAC_FC:
+        case ENETDMAC_LEN:
+                return 0;
+        }
+#endif
+#endif
+        return 0;
+}
+
+
 #endif /* ! BCM63XX_DEV_ENET_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 35baa1a60a64..565ff36a1119 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio_count(void)
         switch (bcm63xx_get_cpu_id()) {
         case BCM6328_CPU_ID:
                 return 32;
+        case BCM3368_CPU_ID:
         case BCM6358_CPU_ID:
                 return 40;
         case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 3203fe49b34d..9875db31d883 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,39 @@
 /* Clock Control register */
 #define PERF_CKCTL_REG                  0x4
 
+#define CKCTL_3368_MAC_EN               (1 << 3)
+#define CKCTL_3368_TC_EN                (1 << 5)
+#define CKCTL_3368_US_TOP_EN            (1 << 6)
+#define CKCTL_3368_DS_TOP_EN            (1 << 7)
+#define CKCTL_3368_APM_EN               (1 << 8)
+#define CKCTL_3368_SPI_EN               (1 << 9)
+#define CKCTL_3368_USBS_EN              (1 << 10)
+#define CKCTL_3368_BMU_EN               (1 << 11)
+#define CKCTL_3368_PCM_EN               (1 << 12)
+#define CKCTL_3368_NTP_EN               (1 << 13)
+#define CKCTL_3368_ACP_B_EN             (1 << 14)
+#define CKCTL_3368_ACP_A_EN             (1 << 15)
+#define CKCTL_3368_EMUSB_EN             (1 << 17)
+#define CKCTL_3368_ENET0_EN             (1 << 18)
+#define CKCTL_3368_ENET1_EN             (1 << 19)
+#define CKCTL_3368_USBU_EN              (1 << 20)
+#define CKCTL_3368_EPHY_EN              (1 << 21)
+
+#define CKCTL_3368_ALL_SAFE_EN          (CKCTL_3368_MAC_EN | \
+                                         CKCTL_3368_TC_EN | \
+                                         CKCTL_3368_US_TOP_EN | \
+                                         CKCTL_3368_DS_TOP_EN | \
+                                         CKCTL_3368_APM_EN | \
+                                         CKCTL_3368_SPI_EN | \
+                                         CKCTL_3368_USBS_EN | \
+                                         CKCTL_3368_BMU_EN | \
+                                         CKCTL_3368_PCM_EN | \
+                                         CKCTL_3368_NTP_EN | \
+                                         CKCTL_3368_ACP_B_EN | \
+                                         CKCTL_3368_ACP_A_EN | \
+                                         CKCTL_3368_EMUSB_EN | \
+                                         CKCTL_3368_USBU_EN)
+
 #define CKCTL_6328_PHYMIPS_EN           (1 << 0)
 #define CKCTL_6328_ADSL_QPROC_EN        (1 << 1)
 #define CKCTL_6328_ADSL_AFE_EN          (1 << 2)
@@ -181,6 +214,7 @@
 #define SYS_PLL_SOFT_RESET              0x1
 
 /* Interrupt Mask register */
+#define PERF_IRQMASK_3368_REG           0xc
 #define PERF_IRQMASK_6328_REG           0x20
 #define PERF_IRQMASK_6338_REG           0xc
 #define PERF_IRQMASK_6345_REG           0xc
@@ -190,6 +224,7 @@
 #define PERF_IRQMASK_6368_REG           0x20
 
 /* Interrupt Status register */
+#define PERF_IRQSTAT_3368_REG           0x10
 #define PERF_IRQSTAT_6328_REG           0x28
 #define PERF_IRQSTAT_6338_REG           0x10
 #define PERF_IRQSTAT_6345_REG           0x10
@@ -199,6 +234,7 @@
 #define PERF_IRQSTAT_6368_REG           0x28
 
 /* External Interrupt Configuration register */
+#define PERF_EXTIRQ_CFG_REG_3368        0x14
 #define PERF_EXTIRQ_CFG_REG_6328        0x18
 #define PERF_EXTIRQ_CFG_REG_6338        0x14
 #define PERF_EXTIRQ_CFG_REG_6345        0x14
@@ -236,6 +272,13 @@
 #define PERF_SOFTRESET_6362_REG         0x10
 #define PERF_SOFTRESET_6368_REG         0x10
 
+#define SOFTRESET_3368_SPI_MASK         (1 << 0)
+#define SOFTRESET_3368_ENET_MASK        (1 << 2)
+#define SOFTRESET_3368_MPI_MASK         (1 << 3)
+#define SOFTRESET_3368_EPHY_MASK        (1 << 6)
+#define SOFTRESET_3368_USBS_MASK        (1 << 11)
+#define SOFTRESET_3368_PCM_MASK         (1 << 13)
+
 #define SOFTRESET_6328_SPI_MASK         (1 << 0)
 #define SOFTRESET_6328_EPHY_MASK        (1 << 1)
 #define SOFTRESET_6328_SAR_MASK         (1 << 2)
@@ -727,6 +770,8 @@
 /*************************************************************************
  * _REG relative to RSET_ENETDMA
  *************************************************************************/
+#define ENETDMA_CHAN_WIDTH              0x10
+#define ENETDMA_6345_CHAN_WIDTH         0x40
 
 /* Controller Configuration Register */
 #define ENETDMA_CFG_REG                 (0x0)
@@ -782,31 +827,56 @@
 /* State Ram Word 4 */
 #define ENETDMA_SRAM4_REG(x)            (0x20c + (x) * 0x10)
 
+/* Broadcom 6345 ENET DMA definitions */
+#define ENETDMA_6345_CHANCFG_REG        (0x00)
+
+#define ENETDMA_6345_MAXBURST_REG       (0x40)
+
+#define ENETDMA_6345_RSTART_REG         (0x08)
+
+#define ENETDMA_6345_LEN_REG            (0x0C)
+
+#define ENETDMA_6345_IR_REG             (0x14)
+
+#define ENETDMA_6345_IRMASK_REG         (0x18)
+
+#define ENETDMA_6345_FC_REG             (0x1C)
+
+#define ENETDMA_6345_BUFALLOC_REG       (0x20)
+
+/* Shift down for EOP, SOP and WRAP bits */
+#define ENETDMA_6345_DESC_SHIFT         (3)
 
 /*************************************************************************
  * _REG relative to RSET_ENETDMAC
  *************************************************************************/
 
 /* Channel Configuration register */
-#define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
+#define ENETDMAC_CHANCFG_REG            (0x0)
 #define ENETDMAC_CHANCFG_EN_SHIFT       0
 #define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
 #define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
 #define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
+#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
+#define ENETDMAC_CHANCFG_CHAINING_MASK  (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
+#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT  3
+#define ENETDMAC_CHANCFG_WRAP_EN_MASK   (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
+#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
+#define ENETDMAC_CHANCFG_FLOWC_EN_MASK  (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
 
 /* Interrupt Control/Status register */
-#define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
+#define ENETDMAC_IR_REG                 (0x4)
 #define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
 #define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
 #define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
 
 /* Interrupt Mask register */
-#define ENETDMAC_IRMASK_REG(x)          (0x8 + (x) * 0x10)
+#define ENETDMAC_IRMASK_REG             (0x8)
 
 /* Maximum Burst Length */
-#define ENETDMAC_MAXBURST_REG(x)        (0xc + (x) * 0x10)
+#define ENETDMAC_MAXBURST_REG           (0xc)
 
 
 /*************************************************************************
@@ -814,26 +884,76 @@
  *************************************************************************/
 
 /* Ring Start Address register */
-#define ENETDMAS_RSTART_REG(x)          ((x) * 0x10)
+#define ENETDMAS_RSTART_REG             (0x0)
 
 /* State Ram Word 2 */
-#define ENETDMAS_SRAM2_REG(x)           (0x4 + (x) * 0x10)
+#define ENETDMAS_SRAM2_REG              (0x4)
 
 /* State Ram Word 3 */
-#define ENETDMAS_SRAM3_REG(x)           (0x8 + (x) * 0x10)
+#define ENETDMAS_SRAM3_REG              (0x8)
 
 /* State Ram Word 4 */
-#define ENETDMAS_SRAM4_REG(x)           (0xc + (x) * 0x10)
+#define ENETDMAS_SRAM4_REG              (0xc)
 
 
 /*************************************************************************
  * _REG relative to RSET_ENETSW
  *************************************************************************/
 
+/* Port traffic control */
+#define ENETSW_PTCTRL_REG(x)            (0x0 + (x))
+#define ENETSW_PTCTRL_RXDIS_MASK        (1 << 0)
+#define ENETSW_PTCTRL_TXDIS_MASK        (1 << 1)
+
+/* Switch mode register */
+#define ENETSW_SWMODE_REG               (0xb)
+#define ENETSW_SWMODE_FWD_EN_MASK       (1 << 1)
+
+/* IMP override Register */
+#define ENETSW_IMPOV_REG                (0xe)
+#define ENETSW_IMPOV_FORCE_MASK         (1 << 7)
+#define ENETSW_IMPOV_TXFLOW_MASK        (1 << 5)
+#define ENETSW_IMPOV_RXFLOW_MASK        (1 << 4)
+#define ENETSW_IMPOV_1000_MASK          (1 << 3)
+#define ENETSW_IMPOV_100_MASK           (1 << 2)
+#define ENETSW_IMPOV_FDX_MASK           (1 << 1)
+#define ENETSW_IMPOV_LINKUP_MASK        (1 << 0)
+
+/* Port override Register */
+#define ENETSW_PORTOV_REG(x)            (0x58 + (x))
+#define ENETSW_PORTOV_ENABLE_MASK       (1 << 6)
+#define ENETSW_PORTOV_TXFLOW_MASK       (1 << 5)
+#define ENETSW_PORTOV_RXFLOW_MASK       (1 << 4)
+#define ENETSW_PORTOV_1000_MASK         (1 << 3)
+#define ENETSW_PORTOV_100_MASK          (1 << 2)
+#define ENETSW_PORTOV_FDX_MASK          (1 << 1)
+#define ENETSW_PORTOV_LINKUP_MASK       (1 << 0)
+
+/* MDIO control register */
+#define ENETSW_MDIOC_REG                (0xb0)
+#define ENETSW_MDIOC_EXT_MASK           (1 << 16)
+#define ENETSW_MDIOC_REG_SHIFT          20
+#define ENETSW_MDIOC_PHYID_SHIFT        25
+#define ENETSW_MDIOC_RD_MASK            (1 << 30)
+#define ENETSW_MDIOC_WR_MASK            (1 << 31)
+
+/* MDIO data register */
+#define ENETSW_MDIOD_REG                (0xb4)
+
+/* Global Management Configuration Register */
+#define ENETSW_GMCR_REG                 (0x200)
+#define ENETSW_GMCR_RST_MIB_MASK        (1 << 0)
+
 /* MIB register */
 #define ENETSW_MIB_REG(x)               (0x2800 + (x) * 4)
 #define ENETSW_MIB_REG_COUNT            47
 
+/* Jumbo control register port mask register */
+#define ENETSW_JMBCTL_PORT_REG          (0x4004)
+
+/* Jumbo control mib good frame register */
+#define ENETSW_JMBCTL_MAXSIZE_REG       (0x4008)
+
 
 /*************************************************************************
  * _REG relative to RSET_OHCI_PRIV
@@ -1293,7 +1413,7 @@
 #define SPI_6348_RX_DATA                0x80
 #define SPI_6348_RX_DATA_SIZE           0x3f
 
-/* BCM 6358/6262/6368 SPI core */
+/* BCM 3368/6358/6262/6368 SPI core */
 #define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
 #define SPI_6358_MSG_CTL_WIDTH          16
 #define SPI_6358_MSG_DATA               0x02
@@ -1434,4 +1554,11 @@
 
 #define PCIE_DEVICE_OFFSET              0x8000
 
+/*************************************************************************
+ * _REG relative to RSET_OTP
+ *************************************************************************/
+
+#define OTP_USER_BITS_6328_REG(i)       (0x20 + (i) * 4)
+#define   OTP_6328_REG3_TP1_DISABLED    BIT(9)
+
 #endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 682bcf3b492a..b86a0efba665 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -24,6 +24,7 @@ struct board_info {
         /* enabled feature/device */
         unsigned int    has_enet0:1;
         unsigned int    has_enet1:1;
+        unsigned int    has_enetsw:1;
         unsigned int    has_pci:1;
         unsigned int    has_pccard:1;
         unsigned int    has_ohci0:1;
@@ -36,6 +37,7 @@ struct board_info {
         /* ethernet config */
         struct bcm63xx_enet_platform_data enet0;
         struct bcm63xx_enet_platform_data enet1;
+        struct bcm63xx_enetsw_platform_data enetsw;
 
         /* USB config */
         struct bcm63xx_usbd_platform_data usbd;
@@ -45,6 +47,12 @@ struct board_info {
 
         /* GPIO LEDs */
         struct gpio_led leds[5];
+
+        /* External PHY reset GPIO */
+        unsigned int ephy_reset_gpio;
+
+        /* External PHY reset GPIO flags from gpio.h */
+        unsigned long ephy_reset_gpio_flags;
 };
 
 #endif /* ! BOARD_BCM963XX_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index 94e3011ba7df..ff15e3b14e7a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
 static inline int is_bcm63xx_internal_registers(phys_t offset)
 {
         switch (bcm63xx_get_cpu_id()) {
+        case BCM3368_CPU_ID:
+                if (offset >= 0xfff80000)
+                        return 1;
+                break;
         case BCM6338_CPU_ID:
         case BCM6345_CPU_ID:
         case BCM6348_CPU_ID: