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authorSage Weil <sage@inktank.com>2013-08-15 14:11:45 -0400
committerSage Weil <sage@inktank.com>2013-08-15 14:11:45 -0400
commitee3e542fec6e69bc9fb668698889a37d93950ddf (patch)
treee74ee766a4764769ef1d3d45d266b4dea64101d3 /arch/mips/include/asm
parentfe2a801b50c0bb8039d627e5ae1fec249d10ff39 (diff)
parentf1d6e17f540af37bb1891480143669ba7636c4cf (diff)
Merge remote-tracking branch 'linus/master' into testing
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/cop2.h29
-rw-r--r--arch/mips/include/asm/cpu-features.h51
-rw-r--r--arch/mips/include/asm/cpu.h23
-rw-r--r--arch/mips/include/asm/fw/cfe/cfe_api.h4
-rw-r--r--arch/mips/include/asm/gic.h2
-rw-r--r--arch/mips/include/asm/io.h10
-rw-r--r--arch/mips/include/asm/kspd.h32
-rw-r--r--arch/mips/include/asm/mach-ar7/spaces.h7
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h119
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h122
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h145
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h8
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h4
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h7
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h7
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/spaces.h24
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h12
-rw-r--r--arch/mips/include/asm/mach-generic/kernel-entry-init.h4
-rw-r--r--arch/mips/include/asm/mach-generic/spaces.h4
-rw-r--r--arch/mips/include/asm/mach-ip27/kernel-entry-init.h47
-rw-r--r--arch/mips/include/asm/mach-ip28/spaces.h9
-rw-r--r--arch/mips/include/asm/mach-jz4740/dma.h56
-rw-r--r--arch/mips/include/asm/mach-jz4740/platform.h1
-rw-r--r--arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h46
-rw-r--r--arch/mips/include/asm/mach-wrppmc/mach-gt64120.h83
-rw-r--r--arch/mips/include/asm/mach-wrppmc/war.h24
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h6
-rw-r--r--arch/mips/include/asm/mipsregs.h2
-rw-r--r--arch/mips/include/asm/mmu_context.h6
-rw-r--r--arch/mips/include/asm/netlogic/common.h21
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h1
-rw-r--r--arch/mips/include/asm/netlogic/xlr/fmn.h12
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h2
-rw-r--r--arch/mips/include/asm/page.h6
-rw-r--r--arch/mips/include/asm/pci.h1
-rw-r--r--arch/mips/include/asm/pgtable.h4
-rw-r--r--arch/mips/include/asm/processor.h35
-rw-r--r--arch/mips/include/asm/stackframe.h29
-rw-r--r--arch/mips/include/asm/stackprotector.h40
-rw-r--r--arch/mips/include/asm/switch_to.h19
-rw-r--r--arch/mips/include/asm/thread_info.h11
-rw-r--r--arch/mips/include/asm/uasm.h37
-rw-r--r--arch/mips/include/asm/xtalk/xtalk.h9
45 files changed, 743 insertions, 381 deletions
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 3532e2c5f098..c1516cc0285f 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -11,6 +11,35 @@
11 11
12#include <linux/notifier.h> 12#include <linux/notifier.h>
13 13
14#if defined(CONFIG_CPU_CAVIUM_OCTEON)
15
16extern void octeon_cop2_save(struct octeon_cop2_state *);
17extern void octeon_cop2_restore(struct octeon_cop2_state *);
18
19#define cop2_save(r) octeon_cop2_save(r)
20#define cop2_restore(r) octeon_cop2_restore(r)
21
22#define cop2_present 1
23#define cop2_lazy_restore 1
24
25#elif defined(CONFIG_CPU_XLP)
26
27extern void nlm_cop2_save(struct nlm_cop2_state *);
28extern void nlm_cop2_restore(struct nlm_cop2_state *);
29#define cop2_save(r) nlm_cop2_save(r)
30#define cop2_restore(r) nlm_cop2_restore(r)
31
32#define cop2_present 1
33#define cop2_lazy_restore 0
34
35#else
36
37#define cop2_present 0
38#define cop2_lazy_restore 0
39#define cop2_save(r)
40#define cop2_restore(r)
41#endif
42
14enum cu2_ops { 43enum cu2_ops {
15 CU2_EXCEPTION, 44 CU2_EXCEPTION,
16 CU2_LWC2_OP, 45 CU2_LWC2_OP,
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index e5ec8fcd8afa..fa44f3ec5302 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -17,6 +17,8 @@
17#define current_cpu_type() current_cpu_data.cputype 17#define current_cpu_type() current_cpu_data.cputype
18#endif 18#endif
19 19
20#define boot_cpu_type() cpu_data[0].cputype
21
20/* 22/*
21 * SMP assumption: Options of CPU 0 are a superset of all processors. 23 * SMP assumption: Options of CPU 0 are a superset of all processors.
22 * This is true for all known MIPS systems. 24 * This is true for all known MIPS systems.
@@ -24,6 +26,16 @@
24#ifndef cpu_has_tlb 26#ifndef cpu_has_tlb
25#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 27#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
26#endif 28#endif
29
30/*
31 * For the moment we don't consider R6000 and R8000 so we can assume that
32 * anything that doesn't support R4000-style exceptions and interrupts is
33 * R3000-like. Users should still treat these two macro definitions as
34 * opaque.
35 */
36#ifndef cpu_has_3kex
37#define cpu_has_3kex (!cpu_has_4kex)
38#endif
27#ifndef cpu_has_4kex 39#ifndef cpu_has_4kex
28#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 40#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
29#endif 41#endif
@@ -87,19 +99,23 @@
87#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 99#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
88#endif 100#endif
89#ifndef cpu_has_mdmx 101#ifndef cpu_has_mdmx
90#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 102#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
91#endif 103#endif
92#ifndef cpu_has_mips3d 104#ifndef cpu_has_mips3d
93#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 105#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
94#endif 106#endif
95#ifndef cpu_has_smartmips 107#ifndef cpu_has_smartmips
96#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 108#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
97#endif 109#endif
98#ifndef cpu_has_rixi 110#ifndef cpu_has_rixi
99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 111#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
100#endif 112#endif
101#ifndef cpu_has_mmips 113#ifndef cpu_has_mmips
102#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 114# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
115# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
116# else
117# define cpu_has_mmips 0
118# endif
103#endif 119#endif
104#ifndef cpu_has_vtag_icache 120#ifndef cpu_has_vtag_icache
105#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 121#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
@@ -111,7 +127,7 @@
111#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 127#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
112#endif 128#endif
113#ifndef cpu_has_pindexed_dcache 129#ifndef cpu_has_pindexed_dcache
114#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 130#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
115#endif 131#endif
116#ifndef cpu_has_local_ebase 132#ifndef cpu_has_local_ebase
117#define cpu_has_local_ebase 1 133#define cpu_has_local_ebase 1
@@ -136,7 +152,6 @@
136#endif 152#endif
137#endif 153#endif
138 154
139# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I)
140#ifndef cpu_has_mips_2 155#ifndef cpu_has_mips_2
141# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 156# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
142#endif 157#endif
@@ -149,18 +164,18 @@
149#ifndef cpu_has_mips_5 164#ifndef cpu_has_mips_5
150# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 165# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
151#endif 166#endif
152# ifndef cpu_has_mips32r1 167#ifndef cpu_has_mips32r1
153# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 168# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
154# endif 169#endif
155# ifndef cpu_has_mips32r2 170#ifndef cpu_has_mips32r2
156# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 171# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
157# endif 172#endif
158# ifndef cpu_has_mips64r1 173#ifndef cpu_has_mips64r1
159# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 174# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
160# endif 175#endif
161# ifndef cpu_has_mips64r2 176#ifndef cpu_has_mips64r2
162# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 177# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
163# endif 178#endif
164 179
165/* 180/*
166 * Shortcuts ... 181 * Shortcuts ...
@@ -182,9 +197,9 @@
182 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 197 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
183 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 198 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
184 */ 199 */
185# ifndef cpu_has_clo_clz 200#ifndef cpu_has_clo_clz
186# define cpu_has_clo_clz cpu_has_mips_r 201#define cpu_has_clo_clz cpu_has_mips_r
187# endif 202#endif
188 203
189#ifndef cpu_has_dsp 204#ifndef cpu_has_dsp
190#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 205#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
@@ -210,7 +225,7 @@
210# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 225# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
211# endif 226# endif
212# ifndef cpu_has_64bit_zero_reg 227# ifndef cpu_has_64bit_zero_reg
213# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 228# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
214# endif 229# endif
215# ifndef cpu_has_64bit_gp_regs 230# ifndef cpu_has_64bit_gp_regs
216# define cpu_has_64bit_gp_regs 0 231# define cpu_has_64bit_gp_regs 0
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index dd86ab205483..632bbe5a79ea 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -282,18 +282,17 @@ enum cpu_type_enum {
282 * ISA Level encodings 282 * ISA Level encodings
283 * 283 *
284 */ 284 */
285#define MIPS_CPU_ISA_I 0x00000001 285#define MIPS_CPU_ISA_II 0x00000001
286#define MIPS_CPU_ISA_II 0x00000002 286#define MIPS_CPU_ISA_III 0x00000002
287#define MIPS_CPU_ISA_III 0x00000004 287#define MIPS_CPU_ISA_IV 0x00000004
288#define MIPS_CPU_ISA_IV 0x00000008 288#define MIPS_CPU_ISA_V 0x00000008
289#define MIPS_CPU_ISA_V 0x00000010 289#define MIPS_CPU_ISA_M32R1 0x00000010
290#define MIPS_CPU_ISA_M32R1 0x00000020 290#define MIPS_CPU_ISA_M32R2 0x00000020
291#define MIPS_CPU_ISA_M32R2 0x00000040 291#define MIPS_CPU_ISA_M64R1 0x00000040
292#define MIPS_CPU_ISA_M64R1 0x00000080 292#define MIPS_CPU_ISA_M64R2 0x00000080
293#define MIPS_CPU_ISA_M64R2 0x00000100 293
294 294#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
295#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 295 MIPS_CPU_ISA_M32R2)
296 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
297#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 296#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
298 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 297 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
299 298
diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
index 17347551a1b2..a0ea69e91e2e 100644
--- a/arch/mips/include/asm/fw/cfe/cfe_api.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
@@ -115,8 +115,8 @@ int cfe_read(int handle, unsigned char *buffer, int length);
115int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, 115int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
116 int length); 116 int length);
117int cfe_setenv(char *name, char *val); 117int cfe_setenv(char *name, char *val);
118int cfe_write(int handle, unsigned char *buffer, int length); 118int cfe_write(int handle, const char *buffer, int length);
119int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, 119int cfe_writeblk(int handle, int64_t offset, const char *buffer,
120 int length); 120 int length);
121 121
122#endif /* CFE_API_H */ 122#endif /* CFE_API_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 7153b32de18e..b2e3e93dd7d8 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -347,7 +347,7 @@ struct gic_shared_intr_map {
347#define GIC_CPU_INT2 2 /* . */ 347#define GIC_CPU_INT2 2 /* . */
348#define GIC_CPU_INT3 3 /* . */ 348#define GIC_CPU_INT3 3 /* . */
349#define GIC_CPU_INT4 4 /* . */ 349#define GIC_CPU_INT4 4 /* . */
350#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ 350#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
351 351
352/* Local GIC interrupts. */ 352/* Local GIC interrupts. */
353#define GIC_INT_TMR (GIC_CPU_INT5) 353#define GIC_INT_TMR (GIC_CPU_INT5)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index b7e59853fd33..3321dd5a8872 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -170,6 +170,11 @@ static inline void * isa_bus_to_virt(unsigned long address)
170extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); 170extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
171extern void __iounmap(const volatile void __iomem *addr); 171extern void __iounmap(const volatile void __iomem *addr);
172 172
173#ifndef CONFIG_PCI
174struct pci_dev;
175static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
176#endif
177
173static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, 178static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
174 unsigned long flags) 179 unsigned long flags)
175{ 180{
@@ -449,6 +454,11 @@ __BUILDIO(q, u64)
449#define readl_relaxed readl 454#define readl_relaxed readl
450#define readq_relaxed readq 455#define readq_relaxed readq
451 456
457#define writeb_relaxed writeb
458#define writew_relaxed writew
459#define writel_relaxed writel
460#define writeq_relaxed writeq
461
452#define readb_be(addr) \ 462#define readb_be(addr) \
453 __raw_readb((__force unsigned *)(addr)) 463 __raw_readb((__force unsigned *)(addr))
454#define readw_be(addr) \ 464#define readw_be(addr) \
diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h
deleted file mode 100644
index ec6832950ace..000000000000
--- a/arch/mips/include/asm/kspd.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18
19#ifndef _ASM_KSPD_H
20#define _ASM_KSPD_H
21
22struct kspd_notifications {
23 void (*kspd_sp_exit)(int sp_id);
24
25 struct list_head list;
26};
27
28static inline void kspd_notify(struct kspd_notifications *notify)
29{
30}
31
32#endif
diff --git a/arch/mips/include/asm/mach-ar7/spaces.h b/arch/mips/include/asm/mach-ar7/spaces.h
index ac28f273449c..660ab64c0fc9 100644
--- a/arch/mips/include/asm/mach-ar7/spaces.h
+++ b/arch/mips/include/asm/mach-ar7/spaces.h
@@ -14,8 +14,11 @@
14 * This handles the memory map. 14 * This handles the memory map.
15 * We handle pages at KSEG0 for kernels with 32 bit address space. 15 * We handle pages at KSEG0 for kernels with 32 bit address space.
16 */ 16 */
17#define PAGE_OFFSET 0x94000000UL 17#define PAGE_OFFSET _AC(0x94000000, UL)
18#define PHYS_OFFSET 0x14000000UL 18#define PHYS_OFFSET _AC(0x14000000, UL)
19
20#define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */
21#define IO_BASE UNCAC_BASE
19 22
20#include <asm/mach-generic/spaces.h> 23#include <asm/mach-generic/spaces.h>
21 24
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 336228990808..19f9134bfe2f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
9 * compile time if only one CPU support is enabled (idea stolen from 9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types) 10 * arm mach-types)
11 */ 11 */
12#define BCM3368_CPU_ID 0x3368
12#define BCM6328_CPU_ID 0x6328 13#define BCM6328_CPU_ID 0x6328
13#define BCM6338_CPU_ID 0x6338 14#define BCM6338_CPU_ID 0x6338
14#define BCM6345_CPU_ID 0x6345 15#define BCM6345_CPU_ID 0x6345
@@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
22u8 bcm63xx_get_cpu_rev(void); 23u8 bcm63xx_get_cpu_rev(void);
23unsigned int bcm63xx_get_cpu_freq(void); 24unsigned int bcm63xx_get_cpu_freq(void);
24 25
26#ifdef CONFIG_BCM63XX_CPU_3368
27# ifdef bcm63xx_get_cpu_id
28# undef bcm63xx_get_cpu_id
29# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
30# define BCMCPU_RUNTIME_DETECT
31# else
32# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
33# endif
34# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
35#else
36# define BCMCPU_IS_3368() (0)
37#endif
38
25#ifdef CONFIG_BCM63XX_CPU_6328 39#ifdef CONFIG_BCM63XX_CPU_6328
26# ifdef bcm63xx_get_cpu_id 40# ifdef bcm63xx_get_cpu_id
27# undef bcm63xx_get_cpu_id 41# undef bcm63xx_get_cpu_id
@@ -173,7 +187,10 @@ enum bcm63xx_regs_set {
173#define BCM_6358_RSET_SPI_SIZE 1804 187#define BCM_6358_RSET_SPI_SIZE 1804
174#define BCM_6368_RSET_SPI_SIZE 1804 188#define BCM_6368_RSET_SPI_SIZE 1804
175#define RSET_ENET_SIZE 2048 189#define RSET_ENET_SIZE 2048
176#define RSET_ENETDMA_SIZE 2048 190#define RSET_ENETDMA_SIZE 256
191#define RSET_6345_ENETDMA_SIZE 64
192#define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
193#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
177#define RSET_ENETSW_SIZE 65536 194#define RSET_ENETSW_SIZE 65536
178#define RSET_UART_SIZE 24 195#define RSET_UART_SIZE 24
179#define RSET_UDC_SIZE 256 196#define RSET_UDC_SIZE 256
@@ -191,6 +208,53 @@ enum bcm63xx_regs_set {
191#define RSET_RNG_SIZE 20 208#define RSET_RNG_SIZE 20
192 209
193/* 210/*
211 * 3368 register sets base address
212 */
213#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
214#define BCM_3368_PERF_BASE (0xfff8c000)
215#define BCM_3368_TIMER_BASE (0xfff8c040)
216#define BCM_3368_WDT_BASE (0xfff8c080)
217#define BCM_3368_UART0_BASE (0xfff8c100)
218#define BCM_3368_UART1_BASE (0xfff8c120)
219#define BCM_3368_GPIO_BASE (0xfff8c080)
220#define BCM_3368_SPI_BASE (0xfff8c800)
221#define BCM_3368_HSSPI_BASE (0xdeadbeef)
222#define BCM_3368_UDC0_BASE (0xdeadbeef)
223#define BCM_3368_USBDMA_BASE (0xdeadbeef)
224#define BCM_3368_OHCI0_BASE (0xdeadbeef)
225#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
226#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
227#define BCM_3368_USBD_BASE (0xdeadbeef)
228#define BCM_3368_MPI_BASE (0xfff80000)
229#define BCM_3368_PCMCIA_BASE (0xfff80054)
230#define BCM_3368_PCIE_BASE (0xdeadbeef)
231#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
232#define BCM_3368_DSL_BASE (0xdeadbeef)
233#define BCM_3368_UBUS_BASE (0xdeadbeef)
234#define BCM_3368_ENET0_BASE (0xfff98000)
235#define BCM_3368_ENET1_BASE (0xfff98800)
236#define BCM_3368_ENETDMA_BASE (0xfff99800)
237#define BCM_3368_ENETDMAC_BASE (0xfff99900)
238#define BCM_3368_ENETDMAS_BASE (0xfff99a00)
239#define BCM_3368_ENETSW_BASE (0xdeadbeef)
240#define BCM_3368_EHCI0_BASE (0xdeadbeef)
241#define BCM_3368_SDRAM_BASE (0xdeadbeef)
242#define BCM_3368_MEMC_BASE (0xfff84000)
243#define BCM_3368_DDR_BASE (0xdeadbeef)
244#define BCM_3368_M2M_BASE (0xdeadbeef)
245#define BCM_3368_ATM_BASE (0xdeadbeef)
246#define BCM_3368_XTM_BASE (0xdeadbeef)
247#define BCM_3368_XTMDMA_BASE (0xdeadbeef)
248#define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
249#define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
250#define BCM_3368_PCM_BASE (0xfff9c200)
251#define BCM_3368_PCMDMA_BASE (0xdeadbeef)
252#define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
253#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
254#define BCM_3368_RNG_BASE (0xdeadbeef)
255#define BCM_3368_MISC_BASE (0xdeadbeef)
256
257/*
194 * 6328 register sets base address 258 * 6328 register sets base address
195 */ 259 */
196#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) 260#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
@@ -235,6 +299,8 @@ enum bcm63xx_regs_set {
235#define BCM_6328_PCMDMAS_BASE (0xdeadbeef) 299#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
236#define BCM_6328_RNG_BASE (0xdeadbeef) 300#define BCM_6328_RNG_BASE (0xdeadbeef)
237#define BCM_6328_MISC_BASE (0xb0001800) 301#define BCM_6328_MISC_BASE (0xb0001800)
302#define BCM_6328_OTP_BASE (0xb0000600)
303
238/* 304/*
239 * 6338 register sets base address 305 * 6338 register sets base address
240 */ 306 */
@@ -298,7 +364,7 @@ enum bcm63xx_regs_set {
298#define BCM_6345_USBDMA_BASE (0xfffe2800) 364#define BCM_6345_USBDMA_BASE (0xfffe2800)
299#define BCM_6345_ENET0_BASE (0xfffe1800) 365#define BCM_6345_ENET0_BASE (0xfffe1800)
300#define BCM_6345_ENETDMA_BASE (0xfffe2800) 366#define BCM_6345_ENETDMA_BASE (0xfffe2800)
301#define BCM_6345_ENETDMAC_BASE (0xfffe2900) 367#define BCM_6345_ENETDMAC_BASE (0xfffe2840)
302#define BCM_6345_ENETDMAS_BASE (0xfffe2a00) 368#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
303#define BCM_6345_ENETSW_BASE (0xdeadbeef) 369#define BCM_6345_ENETSW_BASE (0xdeadbeef)
304#define BCM_6345_PCMCIA_BASE (0xfffe2028) 370#define BCM_6345_PCMCIA_BASE (0xfffe2028)
@@ -620,6 +686,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
620#ifdef BCMCPU_RUNTIME_DETECT 686#ifdef BCMCPU_RUNTIME_DETECT
621 return bcm63xx_regs_base[set]; 687 return bcm63xx_regs_base[set];
622#else 688#else
689#ifdef CONFIG_BCM63XX_CPU_3368
690 __GEN_RSET(3368)
691#endif
623#ifdef CONFIG_BCM63XX_CPU_6328 692#ifdef CONFIG_BCM63XX_CPU_6328
624 __GEN_RSET(6328) 693 __GEN_RSET(6328)
625#endif 694#endif
@@ -687,6 +756,52 @@ enum bcm63xx_irq {
687}; 756};
688 757
689/* 758/*
759 * 3368 irqs
760 */
761#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
762#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
763#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
764#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
765#define BCM_3368_DSL_IRQ 0
766#define BCM_3368_UDC0_IRQ 0
767#define BCM_3368_OHCI0_IRQ 0
768#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
769#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
770#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
771#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
772#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
773#define BCM_3368_HSSPI_IRQ 0
774#define BCM_3368_EHCI0_IRQ 0
775#define BCM_3368_USBD_IRQ 0
776#define BCM_3368_USBD_RXDMA0_IRQ 0
777#define BCM_3368_USBD_TXDMA0_IRQ 0
778#define BCM_3368_USBD_RXDMA1_IRQ 0
779#define BCM_3368_USBD_TXDMA1_IRQ 0
780#define BCM_3368_USBD_RXDMA2_IRQ 0
781#define BCM_3368_USBD_TXDMA2_IRQ 0
782#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
783#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
784#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
785#define BCM_3368_PCMCIA_IRQ 0
786#define BCM_3368_ATM_IRQ 0
787#define BCM_3368_ENETSW_RXDMA0_IRQ 0
788#define BCM_3368_ENETSW_RXDMA1_IRQ 0
789#define BCM_3368_ENETSW_RXDMA2_IRQ 0
790#define BCM_3368_ENETSW_RXDMA3_IRQ 0
791#define BCM_3368_ENETSW_TXDMA0_IRQ 0
792#define BCM_3368_ENETSW_TXDMA1_IRQ 0
793#define BCM_3368_ENETSW_TXDMA2_IRQ 0
794#define BCM_3368_ENETSW_TXDMA3_IRQ 0
795#define BCM_3368_XTM_IRQ 0
796#define BCM_3368_XTM_DMA0_IRQ 0
797
798#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
799#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
800#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
801#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
802
803
804/*
690 * 6328 irqs 805 * 6328 irqs
691 */ 806 */
692#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 807#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
index d53f611184b9..753953e86242 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -4,6 +4,8 @@
4#include <linux/if_ether.h> 4#include <linux/if_ether.h>
5#include <linux/init.h> 5#include <linux/init.h>
6 6
7#include <bcm63xx_regs.h>
8
7/* 9/*
8 * on board ethernet platform data 10 * on board ethernet platform data
9 */ 11 */
@@ -37,9 +39,129 @@ struct bcm63xx_enet_platform_data {
37 int phy_id, int reg), 39 int phy_id, int reg),
38 void (*mii_write)(struct net_device *dev, 40 void (*mii_write)(struct net_device *dev,
39 int phy_id, int reg, int val)); 41 int phy_id, int reg, int val));
42
43 /* DMA channel enable mask */
44 u32 dma_chan_en_mask;
45
46 /* DMA channel interrupt mask */
47 u32 dma_chan_int_mask;
48
49 /* DMA engine has internal SRAM */
50 bool dma_has_sram;
51
52 /* DMA channel register width */
53 unsigned int dma_chan_width;
54
55 /* DMA descriptor shift */
56 unsigned int dma_desc_shift;
57};
58
59/*
60 * on board ethernet switch platform data
61 */
62#define ENETSW_MAX_PORT 8
63#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
64#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
65
66#define ENETSW_RGMII_PORT0 4
67
68struct bcm63xx_enetsw_port {
69 int used;
70 int phy_id;
71
72 int bypass_link;
73 int force_speed;
74 int force_duplex_full;
75
76 const char *name;
77};
78
79struct bcm63xx_enetsw_platform_data {
80 char mac_addr[ETH_ALEN];
81 int num_ports;
82 struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
83
84 /* DMA channel enable mask */
85 u32 dma_chan_en_mask;
86
87 /* DMA channel interrupt mask */
88 u32 dma_chan_int_mask;
89
90 /* DMA channel register width */
91 unsigned int dma_chan_width;
92
93 /* DMA engine has internal SRAM */
94 bool dma_has_sram;
40}; 95};
41 96
42int __init bcm63xx_enet_register(int unit, 97int __init bcm63xx_enet_register(int unit,
43 const struct bcm63xx_enet_platform_data *pd); 98 const struct bcm63xx_enet_platform_data *pd);
44 99
100int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
101
102enum bcm63xx_regs_enetdmac {
103 ENETDMAC_CHANCFG,
104 ENETDMAC_IR,
105 ENETDMAC_IRMASK,
106 ENETDMAC_MAXBURST,
107 ENETDMAC_BUFALLOC,
108 ENETDMAC_RSTART,
109 ENETDMAC_FC,
110 ENETDMAC_LEN,
111};
112
113static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
114{
115#ifdef BCMCPU_RUNTIME_DETECT
116 extern const unsigned long *bcm63xx_regs_enetdmac;
117
118 return bcm63xx_regs_enetdmac[reg];
119#else
120#ifdef CONFIG_BCM63XX_CPU_6345
121 switch (reg) {
122 case ENETDMAC_CHANCFG:
123 return ENETDMA_6345_CHANCFG_REG;
124 case ENETDMAC_IR:
125 return ENETDMA_6345_IR_REG;
126 case ENETDMAC_IRMASK:
127 return ENETDMA_6345_IRMASK_REG;
128 case ENETDMAC_MAXBURST:
129 return ENETDMA_6345_MAXBURST_REG;
130 case ENETDMAC_BUFALLOC:
131 return ENETDMA_6345_BUFALLOC_REG;
132 case ENETDMAC_RSTART:
133 return ENETDMA_6345_RSTART_REG;
134 case ENETDMAC_FC:
135 return ENETDMA_6345_FC_REG;
136 case ENETDMAC_LEN:
137 return ENETDMA_6345_LEN_REG;
138 }
139#endif
140#if defined(CONFIG_BCM63XX_CPU_6328) || \
141 defined(CONFIG_BCM63XX_CPU_6338) || \
142 defined(CONFIG_BCM63XX_CPU_6348) || \
143 defined(CONFIG_BCM63XX_CPU_6358) || \
144 defined(CONFIG_BCM63XX_CPU_6362) || \
145 defined(CONFIG_BCM63XX_CPU_6368)
146 switch (reg) {
147 case ENETDMAC_CHANCFG:
148 return ENETDMAC_CHANCFG_REG;
149 case ENETDMAC_IR:
150 return ENETDMAC_IR_REG;
151 case ENETDMAC_IRMASK:
152 return ENETDMAC_IRMASK_REG;
153 case ENETDMAC_MAXBURST:
154 return ENETDMAC_MAXBURST_REG;
155 case ENETDMAC_BUFALLOC:
156 case ENETDMAC_RSTART:
157 case ENETDMAC_FC:
158 case ENETDMAC_LEN:
159 return 0;
160 }
161#endif
162#endif
163 return 0;
164}
165
166
45#endif /* ! BCM63XX_DEV_ENET_H_ */ 167#endif /* ! BCM63XX_DEV_ENET_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 35baa1a60a64..565ff36a1119 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio_count(void)
11 switch (bcm63xx_get_cpu_id()) { 11 switch (bcm63xx_get_cpu_id()) {
12 case BCM6328_CPU_ID: 12 case BCM6328_CPU_ID:
13 return 32; 13 return 32;
14 case BCM3368_CPU_ID:
14 case BCM6358_CPU_ID: 15 case BCM6358_CPU_ID:
15 return 40; 16 return 40;
16 case BCM6338_CPU_ID: 17 case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 3203fe49b34d..9875db31d883 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,39 @@
15/* Clock Control register */ 15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4 16#define PERF_CKCTL_REG 0x4
17 17
18#define CKCTL_3368_MAC_EN (1 << 3)
19#define CKCTL_3368_TC_EN (1 << 5)
20#define CKCTL_3368_US_TOP_EN (1 << 6)
21#define CKCTL_3368_DS_TOP_EN (1 << 7)
22#define CKCTL_3368_APM_EN (1 << 8)
23#define CKCTL_3368_SPI_EN (1 << 9)
24#define CKCTL_3368_USBS_EN (1 << 10)
25#define CKCTL_3368_BMU_EN (1 << 11)
26#define CKCTL_3368_PCM_EN (1 << 12)
27#define CKCTL_3368_NTP_EN (1 << 13)
28#define CKCTL_3368_ACP_B_EN (1 << 14)
29#define CKCTL_3368_ACP_A_EN (1 << 15)
30#define CKCTL_3368_EMUSB_EN (1 << 17)
31#define CKCTL_3368_ENET0_EN (1 << 18)
32#define CKCTL_3368_ENET1_EN (1 << 19)
33#define CKCTL_3368_USBU_EN (1 << 20)
34#define CKCTL_3368_EPHY_EN (1 << 21)
35
36#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
37 CKCTL_3368_TC_EN | \
38 CKCTL_3368_US_TOP_EN | \
39 CKCTL_3368_DS_TOP_EN | \
40 CKCTL_3368_APM_EN | \
41 CKCTL_3368_SPI_EN | \
42 CKCTL_3368_USBS_EN | \
43 CKCTL_3368_BMU_EN | \
44 CKCTL_3368_PCM_EN | \
45 CKCTL_3368_NTP_EN | \
46 CKCTL_3368_ACP_B_EN | \
47 CKCTL_3368_ACP_A_EN | \
48 CKCTL_3368_EMUSB_EN | \
49 CKCTL_3368_USBU_EN)
50
18#define CKCTL_6328_PHYMIPS_EN (1 << 0) 51#define CKCTL_6328_PHYMIPS_EN (1 << 0)
19#define CKCTL_6328_ADSL_QPROC_EN (1 << 1) 52#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20#define CKCTL_6328_ADSL_AFE_EN (1 << 2) 53#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
@@ -181,6 +214,7 @@
181#define SYS_PLL_SOFT_RESET 0x1 214#define SYS_PLL_SOFT_RESET 0x1
182 215
183/* Interrupt Mask register */ 216/* Interrupt Mask register */
217#define PERF_IRQMASK_3368_REG 0xc
184#define PERF_IRQMASK_6328_REG 0x20 218#define PERF_IRQMASK_6328_REG 0x20
185#define PERF_IRQMASK_6338_REG 0xc 219#define PERF_IRQMASK_6338_REG 0xc
186#define PERF_IRQMASK_6345_REG 0xc 220#define PERF_IRQMASK_6345_REG 0xc
@@ -190,6 +224,7 @@
190#define PERF_IRQMASK_6368_REG 0x20 224#define PERF_IRQMASK_6368_REG 0x20
191 225
192/* Interrupt Status register */ 226/* Interrupt Status register */
227#define PERF_IRQSTAT_3368_REG 0x10
193#define PERF_IRQSTAT_6328_REG 0x28 228#define PERF_IRQSTAT_6328_REG 0x28
194#define PERF_IRQSTAT_6338_REG 0x10 229#define PERF_IRQSTAT_6338_REG 0x10
195#define PERF_IRQSTAT_6345_REG 0x10 230#define PERF_IRQSTAT_6345_REG 0x10
@@ -199,6 +234,7 @@
199#define PERF_IRQSTAT_6368_REG 0x28 234#define PERF_IRQSTAT_6368_REG 0x28
200 235
201/* External Interrupt Configuration register */ 236/* External Interrupt Configuration register */
237#define PERF_EXTIRQ_CFG_REG_3368 0x14
202#define PERF_EXTIRQ_CFG_REG_6328 0x18 238#define PERF_EXTIRQ_CFG_REG_6328 0x18
203#define PERF_EXTIRQ_CFG_REG_6338 0x14 239#define PERF_EXTIRQ_CFG_REG_6338 0x14
204#define PERF_EXTIRQ_CFG_REG_6345 0x14 240#define PERF_EXTIRQ_CFG_REG_6345 0x14
@@ -236,6 +272,13 @@
236#define PERF_SOFTRESET_6362_REG 0x10 272#define PERF_SOFTRESET_6362_REG 0x10
237#define PERF_SOFTRESET_6368_REG 0x10 273#define PERF_SOFTRESET_6368_REG 0x10
238 274
275#define SOFTRESET_3368_SPI_MASK (1 << 0)
276#define SOFTRESET_3368_ENET_MASK (1 << 2)
277#define SOFTRESET_3368_MPI_MASK (1 << 3)
278#define SOFTRESET_3368_EPHY_MASK (1 << 6)
279#define SOFTRESET_3368_USBS_MASK (1 << 11)
280#define SOFTRESET_3368_PCM_MASK (1 << 13)
281
239#define SOFTRESET_6328_SPI_MASK (1 << 0) 282#define SOFTRESET_6328_SPI_MASK (1 << 0)
240#define SOFTRESET_6328_EPHY_MASK (1 << 1) 283#define SOFTRESET_6328_EPHY_MASK (1 << 1)
241#define SOFTRESET_6328_SAR_MASK (1 << 2) 284#define SOFTRESET_6328_SAR_MASK (1 << 2)
@@ -727,6 +770,8 @@
727/************************************************************************* 770/*************************************************************************
728 * _REG relative to RSET_ENETDMA 771 * _REG relative to RSET_ENETDMA
729 *************************************************************************/ 772 *************************************************************************/
773#define ENETDMA_CHAN_WIDTH 0x10
774#define ENETDMA_6345_CHAN_WIDTH 0x40
730 775
731/* Controller Configuration Register */ 776/* Controller Configuration Register */
732#define ENETDMA_CFG_REG (0x0) 777#define ENETDMA_CFG_REG (0x0)
@@ -782,31 +827,56 @@
782/* State Ram Word 4 */ 827/* State Ram Word 4 */
783#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) 828#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
784 829
830/* Broadcom 6345 ENET DMA definitions */
831#define ENETDMA_6345_CHANCFG_REG (0x00)
832
833#define ENETDMA_6345_MAXBURST_REG (0x40)
834
835#define ENETDMA_6345_RSTART_REG (0x08)
836
837#define ENETDMA_6345_LEN_REG (0x0C)
838
839#define ENETDMA_6345_IR_REG (0x14)
840
841#define ENETDMA_6345_IRMASK_REG (0x18)
842
843#define ENETDMA_6345_FC_REG (0x1C)
844
845#define ENETDMA_6345_BUFALLOC_REG (0x20)
846
847/* Shift down for EOP, SOP and WRAP bits */
848#define ENETDMA_6345_DESC_SHIFT (3)
785 849
786/************************************************************************* 850/*************************************************************************
787 * _REG relative to RSET_ENETDMAC 851 * _REG relative to RSET_ENETDMAC
788 *************************************************************************/ 852 *************************************************************************/
789 853
790/* Channel Configuration register */ 854/* Channel Configuration register */
791#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) 855#define ENETDMAC_CHANCFG_REG (0x0)
792#define ENETDMAC_CHANCFG_EN_SHIFT 0 856#define ENETDMAC_CHANCFG_EN_SHIFT 0
793#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) 857#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
794#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 858#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
795#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) 859#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
796#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 860#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
797#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) 861#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
862#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
863#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
864#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
865#define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
866#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
867#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
798 868
799/* Interrupt Control/Status register */ 869/* Interrupt Control/Status register */
800#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) 870#define ENETDMAC_IR_REG (0x4)
801#define ENETDMAC_IR_BUFDONE_MASK (1 << 0) 871#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
802#define ENETDMAC_IR_PKTDONE_MASK (1 << 1) 872#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
803#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) 873#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
804 874
805/* Interrupt Mask register */ 875/* Interrupt Mask register */
806#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10) 876#define ENETDMAC_IRMASK_REG (0x8)
807 877
808/* Maximum Burst Length */ 878/* Maximum Burst Length */
809#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10) 879#define ENETDMAC_MAXBURST_REG (0xc)
810 880
811 881
812/************************************************************************* 882/*************************************************************************
@@ -814,26 +884,76 @@
814 *************************************************************************/ 884 *************************************************************************/
815 885
816/* Ring Start Address register */ 886/* Ring Start Address register */
817#define ENETDMAS_RSTART_REG(x) ((x) * 0x10) 887#define ENETDMAS_RSTART_REG (0x0)
818 888
819/* State Ram Word 2 */ 889/* State Ram Word 2 */
820#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10) 890#define ENETDMAS_SRAM2_REG (0x4)
821 891
822/* State Ram Word 3 */ 892/* State Ram Word 3 */
823#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10) 893#define ENETDMAS_SRAM3_REG (0x8)
824 894
825/* State Ram Word 4 */ 895/* State Ram Word 4 */
826#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10) 896#define ENETDMAS_SRAM4_REG (0xc)
827 897
828 898
829/************************************************************************* 899/*************************************************************************
830 * _REG relative to RSET_ENETSW 900 * _REG relative to RSET_ENETSW
831 *************************************************************************/ 901 *************************************************************************/
832 902
903/* Port traffic control */
904#define ENETSW_PTCTRL_REG(x) (0x0 + (x))
905#define ENETSW_PTCTRL_RXDIS_MASK (1 << 0)
906#define ENETSW_PTCTRL_TXDIS_MASK (1 << 1)
907
908/* Switch mode register */
909#define ENETSW_SWMODE_REG (0xb)
910#define ENETSW_SWMODE_FWD_EN_MASK (1 << 1)
911
912/* IMP override Register */
913#define ENETSW_IMPOV_REG (0xe)
914#define ENETSW_IMPOV_FORCE_MASK (1 << 7)
915#define ENETSW_IMPOV_TXFLOW_MASK (1 << 5)
916#define ENETSW_IMPOV_RXFLOW_MASK (1 << 4)
917#define ENETSW_IMPOV_1000_MASK (1 << 3)
918#define ENETSW_IMPOV_100_MASK (1 << 2)
919#define ENETSW_IMPOV_FDX_MASK (1 << 1)
920#define ENETSW_IMPOV_LINKUP_MASK (1 << 0)
921
922/* Port override Register */
923#define ENETSW_PORTOV_REG(x) (0x58 + (x))
924#define ENETSW_PORTOV_ENABLE_MASK (1 << 6)
925#define ENETSW_PORTOV_TXFLOW_MASK (1 << 5)
926#define ENETSW_PORTOV_RXFLOW_MASK (1 << 4)
927#define ENETSW_PORTOV_1000_MASK (1 << 3)
928#define ENETSW_PORTOV_100_MASK (1 << 2)
929#define ENETSW_PORTOV_FDX_MASK (1 << 1)
930#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
931
932/* MDIO control register */
933#define ENETSW_MDIOC_REG (0xb0)
934#define ENETSW_MDIOC_EXT_MASK (1 << 16)
935#define ENETSW_MDIOC_REG_SHIFT 20
936#define ENETSW_MDIOC_PHYID_SHIFT 25
937#define ENETSW_MDIOC_RD_MASK (1 << 30)
938#define ENETSW_MDIOC_WR_MASK (1 << 31)
939
940/* MDIO data register */
941#define ENETSW_MDIOD_REG (0xb4)
942
943/* Global Management Configuration Register */
944#define ENETSW_GMCR_REG (0x200)
945#define ENETSW_GMCR_RST_MIB_MASK (1 << 0)
946
833/* MIB register */ 947/* MIB register */
834#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) 948#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
835#define ENETSW_MIB_REG_COUNT 47 949#define ENETSW_MIB_REG_COUNT 47
836 950
951/* Jumbo control register port mask register */
952#define ENETSW_JMBCTL_PORT_REG (0x4004)
953
954/* Jumbo control mib good frame register */
955#define ENETSW_JMBCTL_MAXSIZE_REG (0x4008)
956
837 957
838/************************************************************************* 958/*************************************************************************
839 * _REG relative to RSET_OHCI_PRIV 959 * _REG relative to RSET_OHCI_PRIV
@@ -1293,7 +1413,7 @@
1293#define SPI_6348_RX_DATA 0x80 1413#define SPI_6348_RX_DATA 0x80
1294#define SPI_6348_RX_DATA_SIZE 0x3f 1414#define SPI_6348_RX_DATA_SIZE 0x3f
1295 1415
1296/* BCM 6358/6262/6368 SPI core */ 1416/* BCM 3368/6358/6262/6368 SPI core */
1297#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 1417#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1298#define SPI_6358_MSG_CTL_WIDTH 16 1418#define SPI_6358_MSG_CTL_WIDTH 16
1299#define SPI_6358_MSG_DATA 0x02 1419#define SPI_6358_MSG_DATA 0x02
@@ -1434,4 +1554,11 @@
1434 1554
1435#define PCIE_DEVICE_OFFSET 0x8000 1555#define PCIE_DEVICE_OFFSET 0x8000
1436 1556
1557/*************************************************************************
1558 * _REG relative to RSET_OTP
1559 *************************************************************************/
1560
1561#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
1562#define OTP_6328_REG3_TP1_DISABLED BIT(9)
1563
1437#endif /* BCM63XX_REGS_H_ */ 1564#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 682bcf3b492a..b86a0efba665 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -24,6 +24,7 @@ struct board_info {
24 /* enabled feature/device */ 24 /* enabled feature/device */
25 unsigned int has_enet0:1; 25 unsigned int has_enet0:1;
26 unsigned int has_enet1:1; 26 unsigned int has_enet1:1;
27 unsigned int has_enetsw:1;
27 unsigned int has_pci:1; 28 unsigned int has_pci:1;
28 unsigned int has_pccard:1; 29 unsigned int has_pccard:1;
29 unsigned int has_ohci0:1; 30 unsigned int has_ohci0:1;
@@ -36,6 +37,7 @@ struct board_info {
36 /* ethernet config */ 37 /* ethernet config */
37 struct bcm63xx_enet_platform_data enet0; 38 struct bcm63xx_enet_platform_data enet0;
38 struct bcm63xx_enet_platform_data enet1; 39 struct bcm63xx_enet_platform_data enet1;
40 struct bcm63xx_enetsw_platform_data enetsw;
39 41
40 /* USB config */ 42 /* USB config */
41 struct bcm63xx_usbd_platform_data usbd; 43 struct bcm63xx_usbd_platform_data usbd;
@@ -45,6 +47,12 @@ struct board_info {
45 47
46 /* GPIO LEDs */ 48 /* GPIO LEDs */
47 struct gpio_led leds[5]; 49 struct gpio_led leds[5];
50
51 /* External PHY reset GPIO */
52 unsigned int ephy_reset_gpio;
53
54 /* External PHY reset GPIO flags from gpio.h */
55 unsigned long ephy_reset_gpio_flags;
48}; 56};
49 57
50#endif /* ! BOARD_BCM963XX_H_ */ 58#endif /* ! BOARD_BCM963XX_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index 94e3011ba7df..ff15e3b14e7a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
11static inline int is_bcm63xx_internal_registers(phys_t offset) 11static inline int is_bcm63xx_internal_registers(phys_t offset)
12{ 12{
13 switch (bcm63xx_get_cpu_id()) { 13 switch (bcm63xx_get_cpu_id()) {
14 case BCM3368_CPU_ID:
15 if (offset >= 0xfff80000)
16 return 1;
17 break;
14 case BCM6338_CPU_ID: 18 case BCM6338_CPU_ID:
15 case BCM6345_CPU_ID: 19 case BCM6345_CPU_ID:
16 case BCM6348_CPU_ID: 20 case BCM6348_CPU_ID:
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index be8fb4240cec..47fb247f9663 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H 13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H 14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
15 15
16#include <linux/bug.h>
17
16struct device; 18struct device;
17 19
18extern void octeon_pci_dma_init(void); 20extern void octeon_pci_dma_init(void);
@@ -21,18 +23,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
21 size_t size) 23 size_t size)
22{ 24{
23 BUG(); 25 BUG();
26 return 0;
24} 27}
25 28
26static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, 29static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
27 struct page *page) 30 struct page *page)
28{ 31{
29 BUG(); 32 BUG();
33 return 0;
30} 34}
31 35
32static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 36static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
33 dma_addr_t dma_addr) 37 dma_addr_t dma_addr)
34{ 38{
35 BUG(); 39 BUG();
40 return 0;
36} 41}
37 42
38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, 43static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
@@ -44,6 +49,7 @@ static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
44static inline int plat_dma_supported(struct device *dev, u64 mask) 49static inline int plat_dma_supported(struct device *dev, u64 mask)
45{ 50{
46 BUG(); 51 BUG();
52 return 0;
47} 53}
48 54
49static inline void plat_extra_sync_for_device(struct device *dev) 55static inline void plat_extra_sync_for_device(struct device *dev)
@@ -60,6 +66,7 @@ static inline int plat_dma_mapping_error(struct device *dev,
60 dma_addr_t dma_addr) 66 dma_addr_t dma_addr)
61{ 67{
62 BUG(); 68 BUG();
69 return 0;
63} 70}
64 71
65dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); 72dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 1e7dbb192657..1668ee57acb9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -34,15 +34,10 @@
34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE 34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register 35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register 36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
37#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
38 # Disable unaligned load/store support but leave HW fixup enabled 37 # Disable unaligned load/store support but leave HW fixup enabled
38 # Needed for octeon specific memcpy
39 or v0, v0, 0x5001 39 or v0, v0, 0x5001
40 xor v0, v0, 0x1001 40 xor v0, v0, 0x1001
41#else
42 # Disable unaligned load/store and HW fixup support
43 or v0, v0, 0x5001
44 xor v0, v0, 0x5001
45#endif
46 # Read the processor ID register 41 # Read the processor ID register
47 mfc0 v1, CP0_PRID_REG 42 mfc0 v1, CP0_PRID_REG
48 # Disable instruction prefetching (Octeon Pass1 errata) 43 # Disable instruction prefetching (Octeon Pass1 errata)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/spaces.h b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
new file mode 100644
index 000000000000..daa91accf5ab
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
@@ -0,0 +1,24 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 Cavium, Inc.
7 */
8#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H
9#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H
10
11#include <linux/const.h>
12
13#ifdef CONFIG_64BIT
14/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */
15#define CAC_BASE _AC(0x8000000000000000, UL)
16#define UNCAC_BASE _AC(0x8000000000000000, UL)
17#define IO_BASE _AC(0x8000000000000000, UL)
18
19
20#endif /* CONFIG_64BIT */
21
22#include <asm/mach-generic/spaces.h>
23
24#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index fe23034aaf72..74cb99257d5b 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -66,4 +66,16 @@ static inline int plat_device_is_coherent(struct device *dev)
66#endif 66#endif
67} 67}
68 68
69#ifdef CONFIG_SWIOTLB
70static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
71{
72 return paddr;
73}
74
75static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
76{
77 return daddr;
78}
79#endif
80
69#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ 81#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
index 7e66505fa574..13b0751b010a 100644
--- a/arch/mips/include/asm/mach-generic/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
@@ -12,8 +12,8 @@
12/* Intentionally empty macro, used in head.S. Override in 12/* Intentionally empty macro, used in head.S. Override in
13 * arch/mips/mach-xxx/kernel-entry-init.h when necessary. 13 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
14 */ 14 */
15.macro kernel_entry_setup 15 .macro kernel_entry_setup
16.endm 16 .endm
17 17
18/* 18/*
19 * Do SMP slave processor setup necessary before we can savely execute C code. 19 * Do SMP slave processor setup necessary before we can savely execute C code.
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index 5b2f2e68e57f..9488fa5f8866 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -25,8 +25,12 @@
25#else 25#else
26#define CAC_BASE _AC(0x80000000, UL) 26#define CAC_BASE _AC(0x80000000, UL)
27#endif 27#endif
28#ifndef IO_BASE
28#define IO_BASE _AC(0xa0000000, UL) 29#define IO_BASE _AC(0xa0000000, UL)
30#endif
31#ifndef UNCAC_BASE
29#define UNCAC_BASE _AC(0xa0000000, UL) 32#define UNCAC_BASE _AC(0xa0000000, UL)
33#endif
30 34
31#ifndef MAP_BASE 35#ifndef MAP_BASE
32#ifdef CONFIG_KVM_GUEST 36#ifdef CONFIG_KVM_GUEST
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
index a323efb720dc..b087cb83da3a 100644
--- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -24,6 +24,53 @@
24 .endm 24 .endm
25 25
26/* 26/*
27 * TLB bits
28 */
29#define PAGE_GLOBAL (1 << 6)
30#define PAGE_VALID (1 << 7)
31#define PAGE_DIRTY (1 << 8)
32#define CACHE_CACHABLE_COW (5 << 9)
33
34 /*
35 * inputs are the text nasid in t1, data nasid in t2.
36 */
37 .macro MAPPED_KERNEL_SETUP_TLB
38#ifdef CONFIG_MAPPED_KERNEL
39 /*
40 * This needs to read the nasid - assume 0 for now.
41 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
42 * 0+DVG in tlblo_1.
43 */
44 dli t0, 0xffffffffc0000000
45 dmtc0 t0, CP0_ENTRYHI
46 li t0, 0x1c000 # Offset of text into node memory
47 dsll t1, NASID_SHFT # Shift text nasid into place
48 dsll t2, NASID_SHFT # Same for data nasid
49 or t1, t1, t0 # Physical load address of kernel text
50 or t2, t2, t0 # Physical load address of kernel data
51 dsrl t1, 12 # 4K pfn
52 dsrl t2, 12 # 4K pfn
53 dsll t1, 6 # Get pfn into place
54 dsll t2, 6 # Get pfn into place
55 li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6)
56 or t0, t0, t1
57 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
58 li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6)
59 or t0, t0, t2
60 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
61 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
62 mtc0 t0, CP0_PAGEMASK
63 li t0, 0 # KMAP_INX
64 mtc0 t0, CP0_INDEX
65 li t0, 1
66 mtc0 t0, CP0_WIRED
67 tlbwi
68#else
69 mtc0 zero, CP0_WIRED
70#endif
71 .endm
72
73/*
27 * Intentionally empty macro, used in head.S. Override in 74 * Intentionally empty macro, used in head.S. Override in
28 * arch/mips/mach-xxx/kernel-entry-init.h when necessary. 75 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
29 */ 76 */
diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
index 5edf05d9dad8..5d6a76434d00 100644
--- a/arch/mips/include/asm/mach-ip28/spaces.h
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
@@ -11,11 +11,14 @@
11#ifndef _ASM_MACH_IP28_SPACES_H 11#ifndef _ASM_MACH_IP28_SPACES_H
12#define _ASM_MACH_IP28_SPACES_H 12#define _ASM_MACH_IP28_SPACES_H
13 13
14#define CAC_BASE 0xa800000000000000 14#define CAC_BASE _AC(0xa800000000000000, UL)
15 15
16#define HIGHMEM_START (~0UL) 16#define HIGHMEM_START (~0UL)
17 17
18#define PHYS_OFFSET _AC(0x20000000, UL) 18#define PHYS_OFFSET _AC(0x20000000, UL)
19
20#define UNCAC_BASE _AC(0xc0000000, UL) /* 0xa0000000 + PHYS_OFFSET */
21#define IO_BASE UNCAC_BASE
19 22
20#include <asm/mach-generic/spaces.h> 23#include <asm/mach-generic/spaces.h>
21 24
diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
index 98b4e7c0dbae..509cd5828044 100644
--- a/arch/mips/include/asm/mach-jz4740/dma.h
+++ b/arch/mips/include/asm/mach-jz4740/dma.h
@@ -16,8 +16,6 @@
16#ifndef __ASM_MACH_JZ4740_DMA_H__ 16#ifndef __ASM_MACH_JZ4740_DMA_H__
17#define __ASM_MACH_JZ4740_DMA_H__ 17#define __ASM_MACH_JZ4740_DMA_H__
18 18
19struct jz4740_dma_chan;
20
21enum jz4740_dma_request_type { 19enum jz4740_dma_request_type {
22 JZ4740_DMA_TYPE_AUTO_REQUEST = 8, 20 JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
23 JZ4740_DMA_TYPE_UART_TRANSMIT = 20, 21 JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
@@ -33,58 +31,4 @@ enum jz4740_dma_request_type {
33 JZ4740_DMA_TYPE_SLCD = 30, 31 JZ4740_DMA_TYPE_SLCD = 30,
34}; 32};
35 33
36enum jz4740_dma_width {
37 JZ4740_DMA_WIDTH_32BIT = 0,
38 JZ4740_DMA_WIDTH_8BIT = 1,
39 JZ4740_DMA_WIDTH_16BIT = 2,
40};
41
42enum jz4740_dma_transfer_size {
43 JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
44 JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
45 JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
46 JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
47 JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
48};
49
50enum jz4740_dma_flags {
51 JZ4740_DMA_SRC_AUTOINC = 0x2,
52 JZ4740_DMA_DST_AUTOINC = 0x1,
53};
54
55enum jz4740_dma_mode {
56 JZ4740_DMA_MODE_SINGLE = 0,
57 JZ4740_DMA_MODE_BLOCK = 1,
58};
59
60struct jz4740_dma_config {
61 enum jz4740_dma_width src_width;
62 enum jz4740_dma_width dst_width;
63 enum jz4740_dma_transfer_size transfer_size;
64 enum jz4740_dma_request_type request_type;
65 enum jz4740_dma_flags flags;
66 enum jz4740_dma_mode mode;
67};
68
69typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
70
71struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
72void jz4740_dma_free(struct jz4740_dma_chan *dma);
73
74void jz4740_dma_configure(struct jz4740_dma_chan *dma,
75 const struct jz4740_dma_config *config);
76
77
78void jz4740_dma_enable(struct jz4740_dma_chan *dma);
79void jz4740_dma_disable(struct jz4740_dma_chan *dma);
80
81void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
82void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
83void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
84
85uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
86
87void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
88 jz4740_dma_complete_callback_t cb);
89
90#endif /* __ASM_JZ4740_DMA_H__ */ 34#endif /* __ASM_JZ4740_DMA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
index 72cfebdb5a47..05988c2d6565 100644
--- a/arch/mips/include/asm/mach-jz4740/platform.h
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -32,6 +32,7 @@ extern struct platform_device jz4740_codec_device;
32extern struct platform_device jz4740_adc_device; 32extern struct platform_device jz4740_adc_device;
33extern struct platform_device jz4740_wdt_device; 33extern struct platform_device jz4740_wdt_device;
34extern struct platform_device jz4740_pwm_device; 34extern struct platform_device jz4740_pwm_device;
35extern struct platform_device jz4740_dma_device;
35 36
36void jz4740_serial_device_register(void); 37void jz4740_serial_device_register(void);
37 38
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h b/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h
deleted file mode 100644
index ebdbab973e41..000000000000
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * include/asm-mips/pmc-sierra/msp71xx/gpio.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * @author Patrick Glass <patrickglass@gmail.com>
9 */
10
11#ifndef __PMC_MSP71XX_GPIO_H
12#define __PMC_MSP71XX_GPIO_H
13
14/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
15#define ARCH_NR_GPIOS (28 + (3 * 8))
16
17/* new generic GPIO API - see Documentation/gpio.txt */
18#include <asm-generic/gpio.h>
19
20#define gpio_get_value __gpio_get_value
21#define gpio_set_value __gpio_set_value
22#define gpio_cansleep __gpio_cansleep
23
24/* Setup calls for the gpio and gpio extended */
25extern void msp71xx_init_gpio(void);
26extern void msp71xx_init_gpio_extended(void);
27extern int msp71xx_set_output_drive(unsigned gpio, int value);
28
29/* Custom output drive functionss */
30static inline int gpio_set_output_drive(unsigned gpio, int value)
31{
32 return msp71xx_set_output_drive(gpio, value);
33}
34
35/* IRQ's are not supported for gpio lines */
36static inline int gpio_to_irq(unsigned gpio)
37{
38 return -EINVAL;
39}
40
41static inline int irq_to_gpio(unsigned irq)
42{
43 return -EINVAL;
44}
45
46#endif /* __PMC_MSP71XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
deleted file mode 100644
index 00fa3684ac98..000000000000
--- a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef __ASM_MIPS_GT64120_H
9#define __ASM_MIPS_GT64120_H
10
11/*
12 * This is the CPU physical memory map of PPMC Board:
13 *
14 * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
15 * 0x1C000000-0x1C000000 - LED (CS0)
16 * 0x1C800000-0x1C800007 - UART 16550 port (CS1)
17 * 0x1F000000-0x1F000000 - MailBox (CS3)
18 * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
19 */
20
21#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
22#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
23
24#define WRPPMC_UART16550_BASE 0x1C800000
25#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
26
27#define WRPPMC_LED_BASE 0x1C000000
28#define WRPPMC_MBOX_BASE 0x1F000000
29
30#define WRPPMC_BOOTROM_BASE 0x1FC00000
31#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
32
33#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
34#define WRPPMC_UART16550_IRQ 6
35#define WRPPMC_PCI_INTA_IRQ 3
36
37/*
38 * PCI Bus I/O and Memory resources allocation
39 *
40 * NOTE: We only have PCI_0 hose interface
41 */
42#define GT_PCI_MEM_BASE 0x13000000UL
43#define GT_PCI_MEM_SIZE 0x02000000UL
44#define GT_PCI_IO_BASE 0x11000000UL
45#define GT_PCI_IO_SIZE 0x02000000UL
46
47/*
48 * PCI interrupts will come in on either the INTA or INTD interrupt lines,
49 * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
50 * boards, they all either come in on IntD or they all come in on IntA, they
51 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
52 * "requested" interrupt numbers and go through the list whenever we get an
53 * IntA/D.
54 *
55 * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
56 * INTD is 11.
57 */
58#define GT_TIMER 4
59#define GT_INTA 2
60#define GT_INTD 5
61
62#ifndef __ASSEMBLY__
63
64/*
65 * GT64120 internal register space base address
66 */
67extern unsigned long gt64120_base;
68
69#define GT64120_BASE (gt64120_base)
70
71/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
72#undef WRPPMC_EARLY_DEBUG
73
74#ifdef WRPPMC_EARLY_DEBUG
75extern void wrppmc_led_on(int mask);
76extern void wrppmc_led_off(int mask);
77extern void wrppmc_early_printk(const char *fmt, ...);
78#else
79#define wrppmc_early_printk(fmt, ...) do {} while (0)
80#endif /* WRPPMC_EARLY_DEBUG */
81
82#endif /* __ASSEMBLY__ */
83#endif /* __ASM_MIPS_GT64120_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
deleted file mode 100644
index e86084c0bd6b..000000000000
--- a/arch/mips/include/asm/mach-wrppmc/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
9#define __ASM_MIPS_MACH_WRPPMC_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 1
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index bd9746fbe4af..48616816bcbc 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -24,12 +24,6 @@
24#define ASCII_DISPLAY_POS_BASE 0x1f000418 24#define ASCII_DISPLAY_POS_BASE 0x1f000418
25 25
26/* 26/*
27 * Reset register.
28 */
29#define SOFTRES_REG 0x1f000500
30#define GORESET 0x42
31
32/*
33 * Revision register. 27 * Revision register.
34 */ 28 */
35#define MIPS_REVISION_REG 0x1fc00010 29#define MIPS_REVISION_REG 0x1fc00010
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 87e6207b05e4..fed1c3e9b486 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -596,7 +596,7 @@
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599#define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16) 599#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
600#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 600#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
601 601
602#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 602#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 516e6e9a5594..3b29079b5424 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -28,11 +28,7 @@
28 28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30do { \ 30do { \
31 void (*tlbmiss_handler_setup_pgd)(unsigned long); \ 31 extern void tlbmiss_handler_setup_pgd(unsigned long); \
32 extern u32 tlbmiss_handler_setup_pgd_array[16]; \
33 \
34 tlbmiss_handler_setup_pgd = \
35 (__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \
36 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 32 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
37} while (0) 33} while (0)
38 34
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index aef560a51a7e..bb68c3398c80 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -39,11 +39,17 @@
39 * Common SMP definitions 39 * Common SMP definitions
40 */ 40 */
41#define RESET_VEC_PHYS 0x1fc00000 41#define RESET_VEC_PHYS 0x1fc00000
42#define RESET_VEC_SIZE 8192 /* 8KB reset code and data */
42#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) 43#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
44
45/* Offsets of parameters in the RESET_DATA_PHYS area */
43#define BOOT_THREAD_MODE 0 46#define BOOT_THREAD_MODE 0
44#define BOOT_NMI_LOCK 4 47#define BOOT_NMI_LOCK 4
45#define BOOT_NMI_HANDLER 8 48#define BOOT_NMI_HANDLER 8
46 49
50/* CPU ready flags for each CPU */
51#define BOOT_CPU_READY 2048
52
47#ifndef __ASSEMBLY__ 53#ifndef __ASSEMBLY__
48#include <linux/cpumask.h> 54#include <linux/cpumask.h>
49#include <linux/spinlock.h> 55#include <linux/spinlock.h>
@@ -59,23 +65,32 @@ int nlm_wakeup_secondary_cpus(void);
59void nlm_rmiboot_preboot(void); 65void nlm_rmiboot_preboot(void);
60void nlm_percpu_init(int hwcpuid); 66void nlm_percpu_init(int hwcpuid);
61 67
68static inline void *
69nlm_get_boot_data(int offset)
70{
71 return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset);
72}
73
62static inline void 74static inline void
63nlm_set_nmi_handler(void *handler) 75nlm_set_nmi_handler(void *handler)
64{ 76{
65 char *reset_data; 77 void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER);
66 78
67 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); 79 *(int64_t *)nmih = (long)handler;
68 *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
69} 80}
70 81
71/* 82/*
72 * Misc. 83 * Misc.
73 */ 84 */
85void nlm_init_boot_cpu(void);
74unsigned int nlm_get_cpu_frequency(void); 86unsigned int nlm_get_cpu_frequency(void);
75void nlm_node_init(int node); 87void nlm_node_init(int node);
76extern struct plat_smp_ops nlm_smp_ops; 88extern struct plat_smp_ops nlm_smp_ops;
77extern char nlm_reset_entry[], nlm_reset_entry_end[]; 89extern char nlm_reset_entry[], nlm_reset_entry_end[];
78 90
91/* SWIOTLB */
92extern struct dma_map_ops nlm_swiotlb_dma_ops;
93
79extern unsigned int nlm_threads_per_core; 94extern unsigned int nlm_threads_per_core;
80extern cpumask_t nlm_cpumask; 95extern cpumask_t nlm_cpumask;
81 96
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index a981f4681a15..4b5108dfaa16 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -315,7 +315,7 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
315{ 315{
316 uint64_t ipi; 316 uint64_t ipi;
317 317
318 ipi = (nmi << 31) | (irq << 20); 318 ipi = ((uint64_t)nmi << 31) | (irq << 20);
319 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ 319 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
320 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 320 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
321} 321}
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 7e47209327a5..f4ea0f7f3965 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -59,6 +59,7 @@ void xlp_wakeup_secondary_cpus(void);
59 59
60void xlp_mmu_init(void); 60void xlp_mmu_init(void);
61void nlm_hal_init(void); 61void nlm_hal_init(void);
62void *xlp_dt_init(void *fdtp);
62 63
63#endif /* !__ASSEMBLY__ */ 64#endif /* !__ASSEMBLY__ */
64#endif /* _ASM_NLM_XLP_H */ 65#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
index 2a78929cef73..5604db3d1836 100644
--- a/arch/mips/include/asm/netlogic/xlr/fmn.h
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -175,6 +175,10 @@
175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v) 175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v) 176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
177 177
178#define nlm_read_c2_status0() __read_32bit_c2_register($2, 0)
179#define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v)
180#define nlm_read_c2_status1() __read_32bit_c2_register($2, 1)
181#define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v)
178#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) 182#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
179#define nlm_read_c2_config() __read_32bit_c2_register($3, 0) 183#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
180#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) 184#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
@@ -237,7 +241,7 @@ static inline void nlm_msgwait(unsigned int mask)
237/* 241/*
238 * Disable interrupts and enable COP2 access 242 * Disable interrupts and enable COP2 access
239 */ 243 */
240static inline uint32_t nlm_cop2_enable(void) 244static inline uint32_t nlm_cop2_enable_irqsave(void)
241{ 245{
242 uint32_t sr = read_c0_status(); 246 uint32_t sr = read_c0_status();
243 247
@@ -245,7 +249,7 @@ static inline uint32_t nlm_cop2_enable(void)
245 return sr; 249 return sr;
246} 250}
247 251
248static inline void nlm_cop2_restore(uint32_t sr) 252static inline void nlm_cop2_disable_irqrestore(uint32_t sr)
249{ 253{
250 write_c0_status(sr); 254 write_c0_status(sr);
251} 255}
@@ -296,7 +300,7 @@ static inline int nlm_fmn_send(unsigned int size, unsigned int code,
296 */ 300 */
297 for (i = 0; i < 8; i++) { 301 for (i = 0; i < 8; i++) {
298 nlm_msgsnd(dest); 302 nlm_msgsnd(dest);
299 status = nlm_read_c2_status(0); 303 status = nlm_read_c2_status0();
300 if ((status & 0x2) == 1) 304 if ((status & 0x2) == 1)
301 pr_info("Send pending fail!\n"); 305 pr_info("Send pending fail!\n");
302 if ((status & 0x4) == 0) 306 if ((status & 0x4) == 0)
@@ -316,7 +320,7 @@ static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
316 320
317 /* wait for load pending to clear */ 321 /* wait for load pending to clear */
318 do { 322 do {
319 status = nlm_read_c2_status(1); 323 status = nlm_read_c2_status0();
320 } while ((status & 0x08) != 0); 324 } while ((status & 0x08) != 0);
321 325
322 /* receive error bits */ 326 /* receive error bits */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 284fa8d773ba..7b7818d1e4d5 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -227,6 +227,7 @@ enum cvmx_board_types_enum {
227 * use any numbers in this range. 227 * use any numbers in this range.
228 */ 228 */
229 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, 229 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
230 CVMX_BOARD_TYPE_UBNT_E100 = 20002,
230 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, 231 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
231 232
232 /* The remaining range is reserved for future use. */ 233 /* The remaining range is reserved for future use. */
@@ -325,6 +326,7 @@ static inline const char *cvmx_board_type_to_string(enum
325 326
326 /* Customer private range */ 327 /* Customer private range */
327 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) 328 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
329 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
328 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) 330 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
329 } 331 }
330 return "Unsupported Board"; 332 return "Unsupported Board";
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f59552fae917..f6be4741f7e8 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -205,10 +205,8 @@ extern int __virt_addr_valid(const volatile void *kaddr);
205#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ 205#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
206 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 206 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
207 207
208#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \ 208#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
209 PHYS_OFFSET) 209#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
210#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \
211 PHYS_OFFSET)
212 210
213#include <asm-generic/memory_model.h> 211#include <asm-generic/memory_model.h>
214#include <asm-generic/getorder.h> 212#include <asm-generic/getorder.h>
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index b8e24fd4cbc5..fa8e0aa250ca 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -52,7 +52,6 @@ struct pci_controller {
52/* 52/*
53 * Used by boards to register their PCI busses before the actual scanning. 53 * Used by boards to register their PCI busses before the actual scanning.
54 */ 54 */
55extern struct pci_controller * alloc_pci_controller(void);
56extern void register_pci_controller(struct pci_controller *hose); 55extern void register_pci_controller(struct pci_controller *hose);
57 56
58/* 57/*
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 8b8f6b393363..008324d1c261 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -394,9 +394,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
394 phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); 394 phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
395 return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot); 395 return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
396} 396}
397#else 397#define io_remap_pfn_range io_remap_pfn_range
398#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
399 remap_pfn_range(vma, vaddr, pfn, size, prot)
400#endif 398#endif
401 399
402#ifdef CONFIG_TRANSPARENT_HUGEPAGE 400#ifdef CONFIG_TRANSPARENT_HUGEPAGE
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 1470b7b68b0e..3605b844ad87 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -137,7 +137,7 @@ union mips_watch_reg_state {
137 struct mips3264_watch_reg_state mips3264; 137 struct mips3264_watch_reg_state mips3264;
138}; 138};
139 139
140#ifdef CONFIG_CPU_CAVIUM_OCTEON 140#if defined(CONFIG_CPU_CAVIUM_OCTEON)
141 141
142struct octeon_cop2_state { 142struct octeon_cop2_state {
143 /* DMFC2 rt, 0x0201 */ 143 /* DMFC2 rt, 0x0201 */
@@ -182,13 +182,26 @@ struct octeon_cop2_state {
182 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 182 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
183 unsigned long cop2_gfm_result[2]; 183 unsigned long cop2_gfm_result[2];
184}; 184};
185#define INIT_OCTEON_COP2 {0,} 185#define COP2_INIT \
186 .cp2 = {0,},
186 187
187struct octeon_cvmseg_state { 188struct octeon_cvmseg_state {
188 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] 189 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
189 [cpu_dcache_line_size() / sizeof(unsigned long)]; 190 [cpu_dcache_line_size() / sizeof(unsigned long)];
190}; 191};
191 192
193#elif defined(CONFIG_CPU_XLP)
194struct nlm_cop2_state {
195 u64 rx[4];
196 u64 tx[4];
197 u32 tx_msg_status;
198 u32 rx_msg_status;
199};
200
201#define COP2_INIT \
202 .cp2 = {{0}, {0}, 0, 0},
203#else
204#define COP2_INIT
192#endif 205#endif
193 206
194typedef struct { 207typedef struct {
@@ -231,8 +244,11 @@ struct thread_struct {
231 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 244 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
232 unsigned long error_code; 245 unsigned long error_code;
233#ifdef CONFIG_CPU_CAVIUM_OCTEON 246#ifdef CONFIG_CPU_CAVIUM_OCTEON
234 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 247 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
235 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 248 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
249#endif
250#ifdef CONFIG_CPU_XLP
251 struct nlm_cop2_state cp2;
236#endif 252#endif
237 struct mips_abi *abi; 253 struct mips_abi *abi;
238}; 254};
@@ -245,13 +261,6 @@ struct thread_struct {
245#define FPAFF_INIT 261#define FPAFF_INIT
246#endif /* CONFIG_MIPS_MT_FPAFF */ 262#endif /* CONFIG_MIPS_MT_FPAFF */
247 263
248#ifdef CONFIG_CPU_CAVIUM_OCTEON
249#define OCTEON_INIT \
250 .cp2 = INIT_OCTEON_COP2,
251#else
252#define OCTEON_INIT
253#endif /* CONFIG_CPU_CAVIUM_OCTEON */
254
255#define INIT_THREAD { \ 264#define INIT_THREAD { \
256 /* \ 265 /* \
257 * Saved main processor registers \ 266 * Saved main processor registers \
@@ -300,9 +309,9 @@ struct thread_struct {
300 .cp0_baduaddr = 0, \ 309 .cp0_baduaddr = 0, \
301 .error_code = 0, \ 310 .error_code = 0, \
302 /* \ 311 /* \
303 * Cavium Octeon specifics (null if not Octeon) \ 312 * Platform specific cop2 registers(null if no COP2) \
304 */ \ 313 */ \
305 OCTEON_INIT \ 314 COP2_INIT \
306} 315}
307 316
308struct task_struct; 317struct task_struct;
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index a89d1b10d027..23fc95e65673 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -70,6 +70,14 @@
70#ifndef CONFIG_CPU_HAS_SMARTMIPS 70#ifndef CONFIG_CPU_HAS_SMARTMIPS
71 LONG_S v1, PT_LO(sp) 71 LONG_S v1, PT_LO(sp)
72#endif 72#endif
73#ifdef CONFIG_CPU_CAVIUM_OCTEON
74 /*
75 * The Octeon multiplier state is affected by general
76 * multiply instructions. It must be saved before and
77 * kernel code might corrupt it
78 */
79 jal octeon_mult_save
80#endif
73 .endm 81 .endm
74 82
75 .macro SAVE_STATIC 83 .macro SAVE_STATIC
@@ -218,17 +226,8 @@
218 ori $28, sp, _THREAD_MASK 226 ori $28, sp, _THREAD_MASK
219 xori $28, _THREAD_MASK 227 xori $28, _THREAD_MASK
220#ifdef CONFIG_CPU_CAVIUM_OCTEON 228#ifdef CONFIG_CPU_CAVIUM_OCTEON
221 .set mips64 229 .set mips64
222 pref 0, 0($28) /* Prefetch the current pointer */ 230 pref 0, 0($28) /* Prefetch the current pointer */
223 pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
224 /* The Octeon multiplier state is affected by general multiply
225 instructions. It must be saved before and kernel code might
226 corrupt it */
227 jal octeon_mult_save
228 LONG_L v1, 0($28) /* Load the current pointer */
229 /* Restore $31(ra) that was changed by the jal */
230 LONG_L ra, PT_R31(sp)
231 pref 0, 0(v1) /* Prefetch the current thread */
232#endif 231#endif
233 .set pop 232 .set pop
234 .endm 233 .endm
@@ -248,6 +247,10 @@
248 .endm 247 .endm
249 248
250 .macro RESTORE_TEMP 249 .macro RESTORE_TEMP
250#ifdef CONFIG_CPU_CAVIUM_OCTEON
251 /* Restore the Octeon multiplier state */
252 jal octeon_mult_restore
253#endif
251#ifdef CONFIG_CPU_HAS_SMARTMIPS 254#ifdef CONFIG_CPU_HAS_SMARTMIPS
252 LONG_L $24, PT_ACX(sp) 255 LONG_L $24, PT_ACX(sp)
253 mtlhx $24 256 mtlhx $24
@@ -360,10 +363,6 @@
360 DVPE 5 # dvpe a1 363 DVPE 5 # dvpe a1
361 jal mips_ihb 364 jal mips_ihb
362#endif /* CONFIG_MIPS_MT_SMTC */ 365#endif /* CONFIG_MIPS_MT_SMTC */
363#ifdef CONFIG_CPU_CAVIUM_OCTEON
364 /* Restore the Octeon multiplier state */
365 jal octeon_mult_restore
366#endif
367 mfc0 a0, CP0_STATUS 366 mfc0 a0, CP0_STATUS
368 ori a0, STATMASK 367 ori a0, STATMASK
369 xori a0, STATMASK 368 xori a0, STATMASK
diff --git a/arch/mips/include/asm/stackprotector.h b/arch/mips/include/asm/stackprotector.h
new file mode 100644
index 000000000000..eb9b1035e926
--- /dev/null
+++ b/arch/mips/include/asm/stackprotector.h
@@ -0,0 +1,40 @@
1/*
2 * GCC stack protector support.
3 *
4 * (This is directly adopted from the ARM implementation)
5 *
6 * Stack protector works by putting predefined pattern at the start of
7 * the stack frame and verifying that it hasn't been overwritten when
8 * returning from the function. The pattern is called stack canary
9 * and gcc expects it to be defined by a global variable called
10 * "__stack_chk_guard" on MIPS. This unfortunately means that on SMP
11 * we cannot have a different canary value per task.
12 */
13
14#ifndef _ASM_STACKPROTECTOR_H
15#define _ASM_STACKPROTECTOR_H 1
16
17#include <linux/random.h>
18#include <linux/version.h>
19
20extern unsigned long __stack_chk_guard;
21
22/*
23 * Initialize the stackprotector canary value.
24 *
25 * NOTE: this must only be called from functions that never return,
26 * and it must always be inlined.
27 */
28static __always_inline void boot_init_stack_canary(void)
29{
30 unsigned long canary;
31
32 /* Try to get a semi random initial value. */
33 get_random_bytes(&canary, sizeof(canary));
34 canary ^= LINUX_VERSION_CODE;
35
36 current->stack_canary = canary;
37 __stack_chk_guard = current->stack_canary;
38}
39
40#endif /* _ASM_STACKPROTECTOR_H */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index fd16bcb6c311..eb0af15ac656 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -15,6 +15,7 @@
15#include <asm/cpu-features.h> 15#include <asm/cpu-features.h>
16#include <asm/watch.h> 16#include <asm/watch.h>
17#include <asm/dsp.h> 17#include <asm/dsp.h>
18#include <asm/cop2.h>
18 19
19struct task_struct; 20struct task_struct;
20 21
@@ -66,10 +67,18 @@ do { \
66 67
67#define switch_to(prev, next, last) \ 68#define switch_to(prev, next, last) \
68do { \ 69do { \
69 u32 __usedfpu; \ 70 u32 __usedfpu, __c0_stat; \
70 __mips_mt_fpaff_switch_to(prev); \ 71 __mips_mt_fpaff_switch_to(prev); \
71 if (cpu_has_dsp) \ 72 if (cpu_has_dsp) \
72 __save_dsp(prev); \ 73 __save_dsp(prev); \
74 if (cop2_present && (KSTK_STATUS(prev) & ST0_CU2)) { \
75 if (cop2_lazy_restore) \
76 KSTK_STATUS(prev) &= ~ST0_CU2; \
77 __c0_stat = read_c0_status(); \
78 write_c0_status(__c0_stat | ST0_CU2); \
79 cop2_save(&prev->thread.cp2); \
80 write_c0_status(__c0_stat & ~ST0_CU2); \
81 } \
73 __clear_software_ll_bit(); \ 82 __clear_software_ll_bit(); \
74 __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \ 83 __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \
75 (last) = resume(prev, next, task_thread_info(next), __usedfpu); \ 84 (last) = resume(prev, next, task_thread_info(next), __usedfpu); \
@@ -77,6 +86,14 @@ do { \
77 86
78#define finish_arch_switch(prev) \ 87#define finish_arch_switch(prev) \
79do { \ 88do { \
89 u32 __c0_stat; \
90 if (cop2_present && !cop2_lazy_restore && \
91 (KSTK_STATUS(current) & ST0_CU2)) { \
92 __c0_stat = read_c0_status(); \
93 write_c0_status(__c0_stat | ST0_CU2); \
94 cop2_restore(&current->thread.cp2); \
95 write_c0_status(__c0_stat & ~ST0_CU2); \
96 } \
80 if (cpu_has_dsp) \ 97 if (cpu_has_dsp) \
81 __restore_dsp(current); \ 98 __restore_dsp(current); \
82 if (cpu_has_userlocal) \ 99 if (cpu_has_userlocal) \
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 895320e25662..61215a34acc6 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -109,6 +109,7 @@ static inline struct thread_info *current_thread_info(void)
109#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ 109#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
110#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ 110#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
111#define TIF_MEMDIE 18 /* is terminating due to OOM killer */ 111#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
112#define TIF_NOHZ 19 /* in adaptive nohz mode */
112#define TIF_FIXADE 20 /* Fix address errors in software */ 113#define TIF_FIXADE 20 /* Fix address errors in software */
113#define TIF_LOGADE 21 /* Log address errors to syslog */ 114#define TIF_LOGADE 21 /* Log address errors to syslog */
114#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ 115#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */
@@ -124,6 +125,7 @@ static inline struct thread_info *current_thread_info(void)
124#define _TIF_SECCOMP (1<<TIF_SECCOMP) 125#define _TIF_SECCOMP (1<<TIF_SECCOMP)
125#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) 126#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
126#define _TIF_USEDFPU (1<<TIF_USEDFPU) 127#define _TIF_USEDFPU (1<<TIF_USEDFPU)
128#define _TIF_NOHZ (1<<TIF_NOHZ)
127#define _TIF_FIXADE (1<<TIF_FIXADE) 129#define _TIF_FIXADE (1<<TIF_FIXADE)
128#define _TIF_LOGADE (1<<TIF_LOGADE) 130#define _TIF_LOGADE (1<<TIF_LOGADE)
129#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) 131#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
@@ -131,14 +133,19 @@ static inline struct thread_info *current_thread_info(void)
131#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 133#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
132#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 134#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
133 135
136#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
137 _TIF_SYSCALL_AUDIT)
138
134/* work to do in syscall_trace_leave() */ 139/* work to do in syscall_trace_leave() */
135#define _TIF_WORK_SYSCALL_EXIT (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT) 140#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
141 _TIF_SYSCALL_AUDIT)
136 142
137/* work to do on interrupt/exception return */ 143/* work to do on interrupt/exception return */
138#define _TIF_WORK_MASK \ 144#define _TIF_WORK_MASK \
139 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) 145 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
140/* work to do on any return to u-space */ 146/* work to do on any return to u-space */
141#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT) 147#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
148 _TIF_WORK_SYSCALL_EXIT)
142 149
143#endif /* __KERNEL__ */ 150#endif /* __KERNEL__ */
144 151
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 370d967725c2..c33a9564fb41 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -13,12 +13,8 @@
13 13
14#ifdef CONFIG_EXPORT_UASM 14#ifdef CONFIG_EXPORT_UASM
15#include <linux/export.h> 15#include <linux/export.h>
16#define __uasminit
17#define __uasminitdata
18#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym) 16#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
19#else 17#else
20#define __uasminit __cpuinit
21#define __uasminitdata __cpuinitdata
22#define UASM_EXPORT_SYMBOL(sym) 18#define UASM_EXPORT_SYMBOL(sym)
23#endif 19#endif
24 20
@@ -54,43 +50,36 @@
54#endif 50#endif
55 51
56#define Ip_u1u2u3(op) \ 52#define Ip_u1u2u3(op) \
57void __uasminit \ 53void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
58ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
59 54
60#define Ip_u2u1u3(op) \ 55#define Ip_u2u1u3(op) \
61void __uasminit \ 56void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
62ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
63 57
64#define Ip_u3u1u2(op) \ 58#define Ip_u3u1u2(op) \
65void __uasminit \ 59void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
66ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
67 60
68#define Ip_u1u2s3(op) \ 61#define Ip_u1u2s3(op) \
69void __uasminit \ 62void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
70ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
71 63
72#define Ip_u2s3u1(op) \ 64#define Ip_u2s3u1(op) \
73void __uasminit \ 65void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
74ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
75 66
76#define Ip_u2u1s3(op) \ 67#define Ip_u2u1s3(op) \
77void __uasminit \ 68void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
78ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
79 69
80#define Ip_u2u1msbu3(op) \ 70#define Ip_u2u1msbu3(op) \
81void __uasminit \ 71void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
82ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
83 unsigned int d) 72 unsigned int d)
84 73
85#define Ip_u1u2(op) \ 74#define Ip_u1u2(op) \
86void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) 75void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
87 76
88#define Ip_u1s2(op) \ 77#define Ip_u1s2(op) \
89void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, signed int b) 78void ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
90 79
91#define Ip_u1(op) void __uasminit ISAOPC(op)(u32 **buf, unsigned int a) 80#define Ip_u1(op) void ISAOPC(op)(u32 **buf, unsigned int a)
92 81
93#define Ip_0(op) void __uasminit ISAOPC(op)(u32 **buf) 82#define Ip_0(op) void ISAOPC(op)(u32 **buf)
94 83
95Ip_u2u1s3(_addiu); 84Ip_u2u1s3(_addiu);
96Ip_u3u1u2(_addu); 85Ip_u3u1u2(_addu);
@@ -163,7 +152,7 @@ struct uasm_label {
163 int lab; 152 int lab;
164}; 153};
165 154
166void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, 155void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr,
167 int lid); 156 int lid);
168#ifdef CONFIG_64BIT 157#ifdef CONFIG_64BIT
169int ISAFUNC(uasm_in_compat_space_p)(long addr); 158int ISAFUNC(uasm_in_compat_space_p)(long addr);
@@ -174,7 +163,7 @@ void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr);
174void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr); 163void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr);
175 164
176#define UASM_L_LA(lb) \ 165#define UASM_L_LA(lb) \
177static inline void __uasminit ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \ 166static inline void ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \
178{ \ 167{ \
179 ISAFUNC(uasm_build_label)(lab, addr, label##lb); \ 168 ISAFUNC(uasm_build_label)(lab, addr, label##lb); \
180} 169}
diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
index 680e7efebbaf..26d2ed1fa917 100644
--- a/arch/mips/include/asm/xtalk/xtalk.h
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -47,6 +47,15 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) 47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) 48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
49 49
50#ifdef CONFIG_PCI
51extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
52#else
53static inline int bridge_probe(nasid_t nasid, int widget, int masterwid)
54{
55 return 0;
56}
57#endif
58
50#endif /* !__ASSEMBLY__ */ 59#endif /* !__ASSEMBLY__ */
51 60
52#endif /* _ASM_XTALK_XTALK_H */ 61#endif /* _ASM_XTALK_XTALK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 04:51:06 -0400