Merge remote-tracking branch 'linus/master' into testing

52 files changed, 776 insertions, 408 deletions

diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 3532e2c5f098..c1516cc0285f 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -11,6 +11,35 @@
 
 #include <linux/notifier.h>
 
+#if defined(CONFIG_CPU_CAVIUM_OCTEON)
+
+extern void octeon_cop2_save(struct octeon_cop2_state *);
+extern void octeon_cop2_restore(struct octeon_cop2_state *);
+
+#define cop2_save(r)            octeon_cop2_save(r)
+#define cop2_restore(r)         octeon_cop2_restore(r)
+
+#define cop2_present            1
+#define cop2_lazy_restore       1
+
+#elif defined(CONFIG_CPU_XLP)
+
+extern void nlm_cop2_save(struct nlm_cop2_state *);
+extern void nlm_cop2_restore(struct nlm_cop2_state *);
+#define cop2_save(r)            nlm_cop2_save(r)
+#define cop2_restore(r)         nlm_cop2_restore(r)
+
+#define cop2_present            1
+#define cop2_lazy_restore       0
+
+#else
+
+#define cop2_present            0
+#define cop2_lazy_restore       0
+#define cop2_save(r)
+#define cop2_restore(r)
+#endif
+
 enum cu2_ops {
         CU2_EXCEPTION,
         CU2_LWC2_OP,
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index e5ec8fcd8afa..fa44f3ec5302 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -17,6 +17,8 @@
 #define current_cpu_type()      current_cpu_data.cputype
 #endif
 
+#define boot_cpu_type()         cpu_data[0].cputype
+
 /*
  * SMP assumption: Options of CPU 0 are a superset of all processors.
  * This is true for all known MIPS systems.
@@ -24,6 +26,16 @@
 #ifndef cpu_has_tlb
 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
 #endif
+
+/*
+ * For the moment we don't consider R6000 and R8000 so we can assume that
+ * anything that doesn't support R4000-style exceptions and interrupts is
+ * R3000-like.  Users should still treat these two macro definitions as
+ * opaque.
+ */
+#ifndef cpu_has_3kex
+#define cpu_has_3kex            (!cpu_has_4kex)
+#endif
 #ifndef cpu_has_4kex
 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
 #endif
@@ -87,19 +99,23 @@
 #define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
 #endif
 #ifndef cpu_has_mdmx
-#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
+#define cpu_has_mdmx            (cpu_data[0].ases & MIPS_ASE_MDMX)
 #endif
 #ifndef cpu_has_mips3d
-#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#define cpu_has_mips3d          (cpu_data[0].ases & MIPS_ASE_MIPS3D)
 #endif
 #ifndef cpu_has_smartmips
-#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#define cpu_has_smartmips       (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 #endif
 #ifndef cpu_has_rixi
 #define cpu_has_rixi            (cpu_data[0].options & MIPS_CPU_RIXI)
 #endif
 #ifndef cpu_has_mmips
-#define cpu_has_mmips           (cpu_data[0].options & MIPS_CPU_MICROMIPS)
+# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
+#  define cpu_has_mmips         (cpu_data[0].options & MIPS_CPU_MICROMIPS)
+# else
+#  define cpu_has_mmips         0
+# endif
 #endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
@@ -111,7 +127,7 @@
 #define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
 #endif
 #ifndef cpu_has_pindexed_dcache
-#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
 #endif
 #ifndef cpu_has_local_ebase
 #define cpu_has_local_ebase     1
@@ -136,7 +152,6 @@
 #endif
 #endif
 
-# define cpu_has_mips_1         (cpu_data[0].isa_level & MIPS_CPU_ISA_I)
 #ifndef cpu_has_mips_2
 # define cpu_has_mips_2         (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
 #endif
@@ -149,18 +164,18 @@
 #ifndef cpu_has_mips_5
 # define cpu_has_mips_5         (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
 #endif
-# ifndef cpu_has_mips32r1
+#ifndef cpu_has_mips32r1
 # define cpu_has_mips32r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
-# endif
-# ifndef cpu_has_mips32r2
+#endif
+#ifndef cpu_has_mips32r2
 # define cpu_has_mips32r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
-# endif
-# ifndef cpu_has_mips64r1
+#endif
+#ifndef cpu_has_mips64r1
 # define cpu_has_mips64r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
-# endif
-# ifndef cpu_has_mips64r2
+#endif
+#ifndef cpu_has_mips64r2
 # define cpu_has_mips64r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
-# endif
+#endif
 
 /*
  * Shortcuts ...
@@ -182,9 +197,9 @@
  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */
-# ifndef cpu_has_clo_clz
-# define cpu_has_clo_clz        cpu_has_mips_r
-# endif
+#ifndef cpu_has_clo_clz
+#define cpu_has_clo_clz cpu_has_mips_r
+#endif
 
 #ifndef cpu_has_dsp
 #define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
@@ -210,7 +225,7 @@
 # define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 # endif
 # ifndef cpu_has_64bit_zero_reg
-# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 # endif
 # ifndef cpu_has_64bit_gp_regs
 # define cpu_has_64bit_gp_regs          0
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index dd86ab205483..632bbe5a79ea 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -282,18 +282,17 @@ enum cpu_type_enum {
  * ISA Level encodings
  *
  */
-#define MIPS_CPU_ISA_I          0x00000001
-#define MIPS_CPU_ISA_II         0x00000002
-#define MIPS_CPU_ISA_III        0x00000004
-#define MIPS_CPU_ISA_IV         0x00000008
-#define MIPS_CPU_ISA_V          0x00000010
-#define MIPS_CPU_ISA_M32R1      0x00000020
-#define MIPS_CPU_ISA_M32R2      0x00000040
-#define MIPS_CPU_ISA_M64R1      0x00000080
-#define MIPS_CPU_ISA_M64R2      0x00000100
-
-#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
-        MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
+#define MIPS_CPU_ISA_II         0x00000001
+#define MIPS_CPU_ISA_III        0x00000002
+#define MIPS_CPU_ISA_IV         0x00000004
+#define MIPS_CPU_ISA_V          0x00000008
+#define MIPS_CPU_ISA_M32R1      0x00000010
+#define MIPS_CPU_ISA_M32R2      0x00000020
+#define MIPS_CPU_ISA_M64R1      0x00000040
+#define MIPS_CPU_ISA_M64R2      0x00000080
+
+#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
+        MIPS_CPU_ISA_M32R2)
 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
         MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
 
diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
index 17347551a1b2..a0ea69e91e2e 100644
--- a/arch/mips/include/asm/fw/cfe/cfe_api.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
@@ -115,8 +115,8 @@ int cfe_read(int handle, unsigned char *buffer, int length);
 int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
                 int length);
 int cfe_setenv(char *name, char *val);
-int cfe_write(int handle, unsigned char *buffer, int length);
-int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer,
+int cfe_write(int handle, const char *buffer, int length);
+int cfe_writeblk(int handle, int64_t offset, const char *buffer,
                  int length);
 
 #endif                          /* CFE_API_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 7153b32de18e..b2e3e93dd7d8 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -347,7 +347,7 @@ struct gic_shared_intr_map {
 #define GIC_CPU_INT2            2 /* .                */
 #define GIC_CPU_INT3            3 /* .                */
 #define GIC_CPU_INT4            4 /* .                */
-#define GIC_CPU_INT5            5 /* Core Interrupt 5 */
+#define GIC_CPU_INT5            5 /* Core Interrupt 7 */
 
 /* Local GIC interrupts. */
 #define GIC_INT_TMR             (GIC_CPU_INT5)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index b7e59853fd33..3321dd5a8872 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -170,6 +170,11 @@ static inline void * isa_bus_to_virt(unsigned long address)
 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
 extern void __iounmap(const volatile void __iomem *addr);
 
+#ifndef CONFIG_PCI
+struct pci_dev;
+static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
+#endif
+
 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
         unsigned long flags)
 {
@@ -449,6 +454,11 @@ __BUILDIO(q, u64)
 #define readl_relaxed                   readl
 #define readq_relaxed                   readq
 
+#define writeb_relaxed                  writeb
+#define writew_relaxed                  writew
+#define writel_relaxed                  writel
+#define writeq_relaxed                  writeq
+
 #define readb_be(addr)                                                  \
         __raw_readb((__force unsigned *)(addr))
 #define readw_be(addr)                                                  \
diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h
deleted file mode 100644
index ec6832950ace..000000000000
--- a/arch/mips/include/asm/kspd.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- */
-
-#ifndef _ASM_KSPD_H
-#define _ASM_KSPD_H
-
-struct kspd_notifications {
-        void (*kspd_sp_exit)(int sp_id);
-
-        struct list_head list;
-};
-
-static inline void kspd_notify(struct kspd_notifications *notify)
-{
-}
-
-#endif
diff --git a/arch/mips/include/asm/mach-ar7/spaces.h b/arch/mips/include/asm/mach-ar7/spaces.h
index ac28f273449c..660ab64c0fc9 100644
--- a/arch/mips/include/asm/mach-ar7/spaces.h
+++ b/arch/mips/include/asm/mach-ar7/spaces.h
@@ -14,8 +14,11 @@
  * This handles the memory map.
  * We handle pages at KSEG0 for kernels with 32 bit address space.
  */
-#define PAGE_OFFSET             0x94000000UL
-#define PHYS_OFFSET             0x14000000UL
+#define PAGE_OFFSET     _AC(0x94000000, UL)
+#define PHYS_OFFSET     _AC(0x14000000, UL)
+
+#define UNCAC_BASE      _AC(0xb4000000, UL)     /* 0xa0000000 + PHYS_OFFSET */
+#define IO_BASE         UNCAC_BASE
 
 #include <asm/mach-generic/spaces.h>
 
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 336228990808..19f9134bfe2f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
  * compile time if only one CPU support is enabled (idea stolen from
  * arm mach-types)
  */
+#define BCM3368_CPU_ID          0x3368
 #define BCM6328_CPU_ID          0x6328
 #define BCM6338_CPU_ID          0x6338
 #define BCM6345_CPU_ID          0x6345
@@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
 u8 bcm63xx_get_cpu_rev(void);
 unsigned int bcm63xx_get_cpu_freq(void);
 
+#ifdef CONFIG_BCM63XX_CPU_3368
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id()  BCM3368_CPU_ID
+# endif
+# define BCMCPU_IS_3368()       (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
+#else
+# define BCMCPU_IS_3368()       (0)
+#endif
+
 #ifdef CONFIG_BCM63XX_CPU_6328
 # ifdef bcm63xx_get_cpu_id
 #  undef bcm63xx_get_cpu_id
@@ -173,7 +187,10 @@ enum bcm63xx_regs_set {
 #define BCM_6358_RSET_SPI_SIZE          1804
 #define BCM_6368_RSET_SPI_SIZE          1804
 #define RSET_ENET_SIZE                  2048
-#define RSET_ENETDMA_SIZE               2048
+#define RSET_ENETDMA_SIZE               256
+#define RSET_6345_ENETDMA_SIZE          64
+#define RSET_ENETDMAC_SIZE(chans)       (16 * (chans))
+#define RSET_ENETDMAS_SIZE(chans)       (16 * (chans))
 #define RSET_ENETSW_SIZE                65536
 #define RSET_UART_SIZE                  24
 #define RSET_UDC_SIZE                   256
@@ -191,6 +208,53 @@ enum bcm63xx_regs_set {
 #define RSET_RNG_SIZE                   20
 
 /*
+ * 3368 register sets base address
+ */
+#define BCM_3368_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_3368_PERF_BASE              (0xfff8c000)
+#define BCM_3368_TIMER_BASE             (0xfff8c040)
+#define BCM_3368_WDT_BASE               (0xfff8c080)
+#define BCM_3368_UART0_BASE             (0xfff8c100)
+#define BCM_3368_UART1_BASE             (0xfff8c120)
+#define BCM_3368_GPIO_BASE              (0xfff8c080)
+#define BCM_3368_SPI_BASE               (0xfff8c800)
+#define BCM_3368_HSSPI_BASE             (0xdeadbeef)
+#define BCM_3368_UDC0_BASE              (0xdeadbeef)
+#define BCM_3368_USBDMA_BASE            (0xdeadbeef)
+#define BCM_3368_OHCI0_BASE             (0xdeadbeef)
+#define BCM_3368_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_3368_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_3368_USBD_BASE              (0xdeadbeef)
+#define BCM_3368_MPI_BASE               (0xfff80000)
+#define BCM_3368_PCMCIA_BASE            (0xfff80054)
+#define BCM_3368_PCIE_BASE              (0xdeadbeef)
+#define BCM_3368_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_3368_DSL_BASE               (0xdeadbeef)
+#define BCM_3368_UBUS_BASE              (0xdeadbeef)
+#define BCM_3368_ENET0_BASE             (0xfff98000)
+#define BCM_3368_ENET1_BASE             (0xfff98800)
+#define BCM_3368_ENETDMA_BASE           (0xfff99800)
+#define BCM_3368_ENETDMAC_BASE          (0xfff99900)
+#define BCM_3368_ENETDMAS_BASE          (0xfff99a00)
+#define BCM_3368_ENETSW_BASE            (0xdeadbeef)
+#define BCM_3368_EHCI0_BASE             (0xdeadbeef)
+#define BCM_3368_SDRAM_BASE             (0xdeadbeef)
+#define BCM_3368_MEMC_BASE              (0xfff84000)
+#define BCM_3368_DDR_BASE               (0xdeadbeef)
+#define BCM_3368_M2M_BASE               (0xdeadbeef)
+#define BCM_3368_ATM_BASE               (0xdeadbeef)
+#define BCM_3368_XTM_BASE               (0xdeadbeef)
+#define BCM_3368_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_3368_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_3368_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_3368_PCM_BASE               (0xfff9c200)
+#define BCM_3368_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_3368_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_3368_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_3368_RNG_BASE               (0xdeadbeef)
+#define BCM_3368_MISC_BASE              (0xdeadbeef)
+
+/*
  * 6328 register sets base address
  */
 #define BCM_6328_DSL_LMEM_BASE          (0xdeadbeef)
@@ -235,6 +299,8 @@ enum bcm63xx_regs_set {
 #define BCM_6328_PCMDMAS_BASE           (0xdeadbeef)
 #define BCM_6328_RNG_BASE               (0xdeadbeef)
 #define BCM_6328_MISC_BASE              (0xb0001800)
+#define BCM_6328_OTP_BASE               (0xb0000600)
+
 /*
  * 6338 register sets base address
  */
@@ -298,7 +364,7 @@ enum bcm63xx_regs_set {
 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 #define BCM_6345_ENET0_BASE             (0xfffe1800)
 #define BCM_6345_ENETDMA_BASE           (0xfffe2800)
-#define BCM_6345_ENETDMAC_BASE          (0xfffe2900)
+#define BCM_6345_ENETDMAC_BASE          (0xfffe2840)
 #define BCM_6345_ENETDMAS_BASE          (0xfffe2a00)
 #define BCM_6345_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE            (0xfffe2028)
@@ -620,6 +686,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 #ifdef BCMCPU_RUNTIME_DETECT
         return bcm63xx_regs_base[set];
 #else
+#ifdef CONFIG_BCM63XX_CPU_3368
+        __GEN_RSET(3368)
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6328
         __GEN_RSET(6328)
 #endif
@@ -687,6 +756,52 @@ enum bcm63xx_irq {
 };
 
 /*
+ * 3368 irqs
+ */
+#define BCM_3368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_3368_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
+#define BCM_3368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_3368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_3368_DSL_IRQ                0
+#define BCM_3368_UDC0_IRQ               0
+#define BCM_3368_OHCI0_IRQ              0
+#define BCM_3368_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_3368_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
+#define BCM_3368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_3368_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
+#define BCM_3368_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
+#define BCM_3368_HSSPI_IRQ              0
+#define BCM_3368_EHCI0_IRQ              0
+#define BCM_3368_USBD_IRQ               0
+#define BCM_3368_USBD_RXDMA0_IRQ        0
+#define BCM_3368_USBD_TXDMA0_IRQ        0
+#define BCM_3368_USBD_RXDMA1_IRQ        0
+#define BCM_3368_USBD_TXDMA1_IRQ        0
+#define BCM_3368_USBD_RXDMA2_IRQ        0
+#define BCM_3368_USBD_TXDMA2_IRQ        0
+#define BCM_3368_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
+#define BCM_3368_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
+#define BCM_3368_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
+#define BCM_3368_PCMCIA_IRQ             0
+#define BCM_3368_ATM_IRQ                0
+#define BCM_3368_ENETSW_RXDMA0_IRQ      0
+#define BCM_3368_ENETSW_RXDMA1_IRQ      0
+#define BCM_3368_ENETSW_RXDMA2_IRQ      0
+#define BCM_3368_ENETSW_RXDMA3_IRQ      0
+#define BCM_3368_ENETSW_TXDMA0_IRQ      0
+#define BCM_3368_ENETSW_TXDMA1_IRQ      0
+#define BCM_3368_ENETSW_TXDMA2_IRQ      0
+#define BCM_3368_ENETSW_TXDMA3_IRQ      0
+#define BCM_3368_XTM_IRQ                0
+#define BCM_3368_XTM_DMA0_IRQ           0
+
+#define BCM_3368_EXT_IRQ0               (IRQ_INTERNAL_BASE + 25)
+#define BCM_3368_EXT_IRQ1               (IRQ_INTERNAL_BASE + 26)
+#define BCM_3368_EXT_IRQ2               (IRQ_INTERNAL_BASE + 27)
+#define BCM_3368_EXT_IRQ3               (IRQ_INTERNAL_BASE + 28)
+
+
+/*
  * 6328 irqs
  */
 #define BCM_6328_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
index d53f611184b9..753953e86242 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -4,6 +4,8 @@
 #include <linux/if_ether.h>
 #include <linux/init.h>
 
+#include <bcm63xx_regs.h>
+
 /*
  * on board ethernet platform data
  */
@@ -37,9 +39,129 @@ struct bcm63xx_enet_platform_data {
                                           int phy_id, int reg),
                           void (*mii_write)(struct net_device *dev,
                                             int phy_id, int reg, int val));
+
+        /* DMA channel enable mask */
+        u32 dma_chan_en_mask;
+
+        /* DMA channel interrupt mask */
+        u32 dma_chan_int_mask;
+
+        /* DMA engine has internal SRAM */
+        bool dma_has_sram;
+
+        /* DMA channel register width */
+        unsigned int dma_chan_width;
+
+        /* DMA descriptor shift */
+        unsigned int dma_desc_shift;
+};
+
+/*
+ * on board ethernet switch platform data
+ */
+#define ENETSW_MAX_PORT 8
+#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
+#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
+
+#define ENETSW_RGMII_PORT0      4
+
+struct bcm63xx_enetsw_port {
+        int             used;
+        int             phy_id;
+
+        int             bypass_link;
+        int             force_speed;
+        int             force_duplex_full;
+
+        const char      *name;
+};
+
+struct bcm63xx_enetsw_platform_data {
+        char mac_addr[ETH_ALEN];
+        int num_ports;
+        struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
+
+        /* DMA channel enable mask */
+        u32 dma_chan_en_mask;
+
+        /* DMA channel interrupt mask */
+        u32 dma_chan_int_mask;
+
+        /* DMA channel register width */
+        unsigned int dma_chan_width;
+
+        /* DMA engine has internal SRAM */
+        bool dma_has_sram;
 };
 
 int __init bcm63xx_enet_register(int unit,
                                  const struct bcm63xx_enet_platform_data *pd);
 
+int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
+
+enum bcm63xx_regs_enetdmac {
+        ENETDMAC_CHANCFG,
+        ENETDMAC_IR,
+        ENETDMAC_IRMASK,
+        ENETDMAC_MAXBURST,
+        ENETDMAC_BUFALLOC,
+        ENETDMAC_RSTART,
+        ENETDMAC_FC,
+        ENETDMAC_LEN,
+};
+
+static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
+{
+#ifdef BCMCPU_RUNTIME_DETECT
+        extern const unsigned long *bcm63xx_regs_enetdmac;
+
+        return bcm63xx_regs_enetdmac[reg];
+#else
+#ifdef CONFIG_BCM63XX_CPU_6345
+        switch (reg) {
+        case ENETDMAC_CHANCFG:
+                return ENETDMA_6345_CHANCFG_REG;
+        case ENETDMAC_IR:
+                return ENETDMA_6345_IR_REG;
+        case ENETDMAC_IRMASK:
+                return ENETDMA_6345_IRMASK_REG;
+        case ENETDMAC_MAXBURST:
+                return ENETDMA_6345_MAXBURST_REG;
+        case ENETDMAC_BUFALLOC:
+                return ENETDMA_6345_BUFALLOC_REG;
+        case ENETDMAC_RSTART:
+                return ENETDMA_6345_RSTART_REG;
+        case ENETDMAC_FC:
+                return ENETDMA_6345_FC_REG;
+        case ENETDMAC_LEN:
+                return ENETDMA_6345_LEN_REG;
+        }
+#endif
+#if defined(CONFIG_BCM63XX_CPU_6328) || \
+        defined(CONFIG_BCM63XX_CPU_6338) || \
+        defined(CONFIG_BCM63XX_CPU_6348) || \
+        defined(CONFIG_BCM63XX_CPU_6358) || \
+        defined(CONFIG_BCM63XX_CPU_6362) || \
+        defined(CONFIG_BCM63XX_CPU_6368)
+        switch (reg) {
+        case ENETDMAC_CHANCFG:
+                return ENETDMAC_CHANCFG_REG;
+        case ENETDMAC_IR:
+                return ENETDMAC_IR_REG;
+        case ENETDMAC_IRMASK:
+                return ENETDMAC_IRMASK_REG;
+        case ENETDMAC_MAXBURST:
+                return ENETDMAC_MAXBURST_REG;
+        case ENETDMAC_BUFALLOC:
+        case ENETDMAC_RSTART:
+        case ENETDMAC_FC:
+        case ENETDMAC_LEN:
+                return 0;
+        }
+#endif
+#endif
+        return 0;
+}
+
+
 #endif /* ! BCM63XX_DEV_ENET_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 35baa1a60a64..565ff36a1119 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio_count(void)
         switch (bcm63xx_get_cpu_id()) {
         case BCM6328_CPU_ID:
                 return 32;
+        case BCM3368_CPU_ID:
         case BCM6358_CPU_ID:
                 return 40;
         case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 3203fe49b34d..9875db31d883 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,39 @@
 /* Clock Control register */
 #define PERF_CKCTL_REG                  0x4
 
+#define CKCTL_3368_MAC_EN               (1 << 3)
+#define CKCTL_3368_TC_EN                (1 << 5)
+#define CKCTL_3368_US_TOP_EN            (1 << 6)
+#define CKCTL_3368_DS_TOP_EN            (1 << 7)
+#define CKCTL_3368_APM_EN               (1 << 8)
+#define CKCTL_3368_SPI_EN               (1 << 9)
+#define CKCTL_3368_USBS_EN              (1 << 10)
+#define CKCTL_3368_BMU_EN               (1 << 11)
+#define CKCTL_3368_PCM_EN               (1 << 12)
+#define CKCTL_3368_NTP_EN               (1 << 13)
+#define CKCTL_3368_ACP_B_EN             (1 << 14)
+#define CKCTL_3368_ACP_A_EN             (1 << 15)
+#define CKCTL_3368_EMUSB_EN             (1 << 17)
+#define CKCTL_3368_ENET0_EN             (1 << 18)
+#define CKCTL_3368_ENET1_EN             (1 << 19)
+#define CKCTL_3368_USBU_EN              (1 << 20)
+#define CKCTL_3368_EPHY_EN              (1 << 21)
+
+#define CKCTL_3368_ALL_SAFE_EN          (CKCTL_3368_MAC_EN | \
+                                         CKCTL_3368_TC_EN | \
+                                         CKCTL_3368_US_TOP_EN | \
+                                         CKCTL_3368_DS_TOP_EN | \
+                                         CKCTL_3368_APM_EN | \
+                                         CKCTL_3368_SPI_EN | \
+                                         CKCTL_3368_USBS_EN | \
+                                         CKCTL_3368_BMU_EN | \
+                                         CKCTL_3368_PCM_EN | \
+                                         CKCTL_3368_NTP_EN | \
+                                         CKCTL_3368_ACP_B_EN | \
+                                         CKCTL_3368_ACP_A_EN | \
+                                         CKCTL_3368_EMUSB_EN | \
+                                         CKCTL_3368_USBU_EN)
+
 #define CKCTL_6328_PHYMIPS_EN           (1 << 0)
 #define CKCTL_6328_ADSL_QPROC_EN        (1 << 1)
 #define CKCTL_6328_ADSL_AFE_EN          (1 << 2)
@@ -181,6 +214,7 @@
 #define SYS_PLL_SOFT_RESET              0x1
 
 /* Interrupt Mask register */
+#define PERF_IRQMASK_3368_REG           0xc
 #define PERF_IRQMASK_6328_REG           0x20
 #define PERF_IRQMASK_6338_REG           0xc
 #define PERF_IRQMASK_6345_REG           0xc
@@ -190,6 +224,7 @@
 #define PERF_IRQMASK_6368_REG           0x20
 
 /* Interrupt Status register */
+#define PERF_IRQSTAT_3368_REG           0x10
 #define PERF_IRQSTAT_6328_REG           0x28
 #define PERF_IRQSTAT_6338_REG           0x10
 #define PERF_IRQSTAT_6345_REG           0x10
@@ -199,6 +234,7 @@
 #define PERF_IRQSTAT_6368_REG           0x28
 
 /* External Interrupt Configuration register */
+#define PERF_EXTIRQ_CFG_REG_3368        0x14
 #define PERF_EXTIRQ_CFG_REG_6328        0x18
 #define PERF_EXTIRQ_CFG_REG_6338        0x14
 #define PERF_EXTIRQ_CFG_REG_6345        0x14
@@ -236,6 +272,13 @@
 #define PERF_SOFTRESET_6362_REG         0x10
 #define PERF_SOFTRESET_6368_REG         0x10
 
+#define SOFTRESET_3368_SPI_MASK         (1 << 0)
+#define SOFTRESET_3368_ENET_MASK        (1 << 2)
+#define SOFTRESET_3368_MPI_MASK         (1 << 3)
+#define SOFTRESET_3368_EPHY_MASK        (1 << 6)
+#define SOFTRESET_3368_USBS_MASK        (1 << 11)
+#define SOFTRESET_3368_PCM_MASK         (1 << 13)
+
 #define SOFTRESET_6328_SPI_MASK         (1 << 0)
 #define SOFTRESET_6328_EPHY_MASK        (1 << 1)
 #define SOFTRESET_6328_SAR_MASK         (1 << 2)
@@ -727,6 +770,8 @@
 /*************************************************************************
  * _REG relative to RSET_ENETDMA
  *************************************************************************/
+#define ENETDMA_CHAN_WIDTH              0x10
+#define ENETDMA_6345_CHAN_WIDTH         0x40
 
 /* Controller Configuration Register */
 #define ENETDMA_CFG_REG                 (0x0)
@@ -782,31 +827,56 @@
 /* State Ram Word 4 */
 #define ENETDMA_SRAM4_REG(x)            (0x20c + (x) * 0x10)
 
+/* Broadcom 6345 ENET DMA definitions */
+#define ENETDMA_6345_CHANCFG_REG        (0x00)
+
+#define ENETDMA_6345_MAXBURST_REG       (0x40)
+
+#define ENETDMA_6345_RSTART_REG         (0x08)
+
+#define ENETDMA_6345_LEN_REG            (0x0C)
+
+#define ENETDMA_6345_IR_REG             (0x14)
+
+#define ENETDMA_6345_IRMASK_REG         (0x18)
+
+#define ENETDMA_6345_FC_REG             (0x1C)
+
+#define ENETDMA_6345_BUFALLOC_REG       (0x20)
+
+/* Shift down for EOP, SOP and WRAP bits */
+#define ENETDMA_6345_DESC_SHIFT         (3)
 
 /*************************************************************************
  * _REG relative to RSET_ENETDMAC
  *************************************************************************/
 
 /* Channel Configuration register */
-#define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
+#define ENETDMAC_CHANCFG_REG            (0x0)
 #define ENETDMAC_CHANCFG_EN_SHIFT       0
 #define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
 #define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
 #define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
+#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
+#define ENETDMAC_CHANCFG_CHAINING_MASK  (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
+#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT  3
+#define ENETDMAC_CHANCFG_WRAP_EN_MASK   (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
+#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
+#define ENETDMAC_CHANCFG_FLOWC_EN_MASK  (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
 
 /* Interrupt Control/Status register */
-#define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
+#define ENETDMAC_IR_REG                 (0x4)
 #define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
 #define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
 #define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
 
 /* Interrupt Mask register */
-#define ENETDMAC_IRMASK_REG(x)          (0x8 + (x) * 0x10)
+#define ENETDMAC_IRMASK_REG             (0x8)
 
 /* Maximum Burst Length */
-#define ENETDMAC_MAXBURST_REG(x)        (0xc + (x) * 0x10)
+#define ENETDMAC_MAXBURST_REG           (0xc)
 
 
 /*************************************************************************
@@ -814,26 +884,76 @@
  *************************************************************************/
 
 /* Ring Start Address register */
-#define ENETDMAS_RSTART_REG(x)          ((x) * 0x10)
+#define ENETDMAS_RSTART_REG             (0x0)
 
 /* State Ram Word 2 */
-#define ENETDMAS_SRAM2_REG(x)           (0x4 + (x) * 0x10)
+#define ENETDMAS_SRAM2_REG              (0x4)
 
 /* State Ram Word 3 */
-#define ENETDMAS_SRAM3_REG(x)           (0x8 + (x) * 0x10)
+#define ENETDMAS_SRAM3_REG              (0x8)
 
 /* State Ram Word 4 */
-#define ENETDMAS_SRAM4_REG(x)           (0xc + (x) * 0x10)
+#define ENETDMAS_SRAM4_REG              (0xc)
 
 
 /*************************************************************************
  * _REG relative to RSET_ENETSW
  *************************************************************************/
 
+/* Port traffic control */
+#define ENETSW_PTCTRL_REG(x)            (0x0 + (x))
+#define ENETSW_PTCTRL_RXDIS_MASK        (1 << 0)
+#define ENETSW_PTCTRL_TXDIS_MASK        (1 << 1)
+
+/* Switch mode register */
+#define ENETSW_SWMODE_REG               (0xb)
+#define ENETSW_SWMODE_FWD_EN_MASK       (1 << 1)
+
+/* IMP override Register */
+#define ENETSW_IMPOV_REG                (0xe)
+#define ENETSW_IMPOV_FORCE_MASK         (1 << 7)
+#define ENETSW_IMPOV_TXFLOW_MASK        (1 << 5)
+#define ENETSW_IMPOV_RXFLOW_MASK        (1 << 4)
+#define ENETSW_IMPOV_1000_MASK          (1 << 3)
+#define ENETSW_IMPOV_100_MASK           (1 << 2)
+#define ENETSW_IMPOV_FDX_MASK           (1 << 1)
+#define ENETSW_IMPOV_LINKUP_MASK        (1 << 0)
+
+/* Port override Register */
+#define ENETSW_PORTOV_REG(x)            (0x58 + (x))
+#define ENETSW_PORTOV_ENABLE_MASK       (1 << 6)
+#define ENETSW_PORTOV_TXFLOW_MASK       (1 << 5)
+#define ENETSW_PORTOV_RXFLOW_MASK       (1 << 4)
+#define ENETSW_PORTOV_1000_MASK         (1 << 3)
+#define ENETSW_PORTOV_100_MASK          (1 << 2)
+#define ENETSW_PORTOV_FDX_MASK          (1 << 1)
+#define ENETSW_PORTOV_LINKUP_MASK       (1 << 0)
+
+/* MDIO control register */
+#define ENETSW_MDIOC_REG                (0xb0)
+#define ENETSW_MDIOC_EXT_MASK           (1 << 16)
+#define ENETSW_MDIOC_REG_SHIFT          20
+#define ENETSW_MDIOC_PHYID_SHIFT        25
+#define ENETSW_MDIOC_RD_MASK            (1 << 30)
+#define ENETSW_MDIOC_WR_MASK            (1 << 31)
+
+/* MDIO data register */
+#define ENETSW_MDIOD_REG                (0xb4)
+
+/* Global Management Configuration Register */
+#define ENETSW_GMCR_REG                 (0x200)
+#define ENETSW_GMCR_RST_MIB_MASK        (1 << 0)
+
 /* MIB register */
 #define ENETSW_MIB_REG(x)               (0x2800 + (x) * 4)
 #define ENETSW_MIB_REG_COUNT            47
 
+/* Jumbo control register port mask register */
+#define ENETSW_JMBCTL_PORT_REG          (0x4004)
+
+/* Jumbo control mib good frame register */
+#define ENETSW_JMBCTL_MAXSIZE_REG       (0x4008)
+
 
 /*************************************************************************
  * _REG relative to RSET_OHCI_PRIV
@@ -1293,7 +1413,7 @@
 #define SPI_6348_RX_DATA                0x80
 #define SPI_6348_RX_DATA_SIZE           0x3f
 
-/* BCM 6358/6262/6368 SPI core */
+/* BCM 3368/6358/6262/6368 SPI core */
 #define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
 #define SPI_6358_MSG_CTL_WIDTH          16
 #define SPI_6358_MSG_DATA               0x02
@@ -1434,4 +1554,11 @@
 
 #define PCIE_DEVICE_OFFSET              0x8000
 
+/*************************************************************************
+ * _REG relative to RSET_OTP
+ *************************************************************************/
+
+#define OTP_USER_BITS_6328_REG(i)       (0x20 + (i) * 4)
+#define   OTP_6328_REG3_TP1_DISABLED    BIT(9)
+
 #endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 682bcf3b492a..b86a0efba665 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -24,6 +24,7 @@ struct board_info {
         /* enabled feature/device */
         unsigned int    has_enet0:1;
         unsigned int    has_enet1:1;
+        unsigned int    has_enetsw:1;
         unsigned int    has_pci:1;
         unsigned int    has_pccard:1;
         unsigned int    has_ohci0:1;
@@ -36,6 +37,7 @@ struct board_info {
         /* ethernet config */
         struct bcm63xx_enet_platform_data enet0;
         struct bcm63xx_enet_platform_data enet1;
+        struct bcm63xx_enetsw_platform_data enetsw;
 
         /* USB config */
         struct bcm63xx_usbd_platform_data usbd;
@@ -45,6 +47,12 @@ struct board_info {
 
         /* GPIO LEDs */
         struct gpio_led leds[5];
+
+        /* External PHY reset GPIO */
+        unsigned int ephy_reset_gpio;
+
+        /* External PHY reset GPIO flags from gpio.h */
+        unsigned long ephy_reset_gpio_flags;
 };
 
 #endif /* ! BOARD_BCM963XX_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index 94e3011ba7df..ff15e3b14e7a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
 static inline int is_bcm63xx_internal_registers(phys_t offset)
 {
         switch (bcm63xx_get_cpu_id()) {
+        case BCM3368_CPU_ID:
+                if (offset >= 0xfff80000)
+                        return 1;
+                break;
         case BCM6338_CPU_ID:
         case BCM6345_CPU_ID:
         case BCM6348_CPU_ID:
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index be8fb4240cec..47fb247f9663 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
 #define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
 
+#include <linux/bug.h>
+
 struct device;
 
 extern void octeon_pci_dma_init(void);
@@ -21,18 +23,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         size_t size)
 {
         BUG();
+        return 0;
 }
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         struct page *page)
 {
         BUG();
+        return 0;
 }
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
         BUG();
+        return 0;
 }
 
 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
@@ -44,6 +49,7 @@ static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
 static inline int plat_dma_supported(struct device *dev, u64 mask)
 {
         BUG();
+        return 0;
 }
 
 static inline void plat_extra_sync_for_device(struct device *dev)
@@ -60,6 +66,7 @@ static inline int plat_dma_mapping_error(struct device *dev,
                                          dma_addr_t dma_addr)
 {
         BUG();
+        return 0;
 }
 
 dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 1e7dbb192657..1668ee57acb9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -34,15 +34,10 @@
         ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
         dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
         dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register
-#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
         # Disable unaligned load/store support but leave HW fixup enabled
+        # Needed for octeon specific memcpy
         or  v0, v0, 0x5001
         xor v0, v0, 0x1001
-#else
-        # Disable unaligned load/store and HW fixup support
-        or  v0, v0, 0x5001
-        xor v0, v0, 0x5001
-#endif
         # Read the processor ID register
         mfc0 v1, CP0_PRID_REG
         # Disable instruction prefetching (Octeon Pass1 errata)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/spaces.h b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
new file mode 100644
index 000000000000..daa91accf5ab
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 Cavium, Inc.
+ */
+#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H
+#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H
+
+#include <linux/const.h>
+
+#ifdef CONFIG_64BIT
+/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */
+#define CAC_BASE                _AC(0x8000000000000000, UL)
+#define UNCAC_BASE              _AC(0x8000000000000000, UL)
+#define IO_BASE                 _AC(0x8000000000000000, UL)
+
+
+#endif /* CONFIG_64BIT */
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index fe23034aaf72..74cb99257d5b 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -66,4 +66,16 @@ static inline int plat_device_is_coherent(struct device *dev)
 #endif
 }
 
+#ifdef CONFIG_SWIOTLB
+static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        return paddr;
+}
+
+static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return daddr;
+}
+#endif
+
 #endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
index 7e66505fa574..13b0751b010a 100644
--- a/arch/mips/include/asm/mach-generic/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
@@ -12,8 +12,8 @@
 /* Intentionally empty macro, used in head.S. Override in
  * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
  */
-.macro  kernel_entry_setup
-.endm
+        .macro  kernel_entry_setup
+        .endm
 
 /*
  * Do SMP slave processor setup necessary before we can savely execute C code.
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index 5b2f2e68e57f..9488fa5f8866 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -25,8 +25,12 @@
 #else
 #define CAC_BASE                _AC(0x80000000, UL)
 #endif
+#ifndef IO_BASE
 #define IO_BASE                 _AC(0xa0000000, UL)
+#endif
+#ifndef UNCAC_BASE
 #define UNCAC_BASE              _AC(0xa0000000, UL)
+#endif
 
 #ifndef MAP_BASE
 #ifdef CONFIG_KVM_GUEST
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
index a323efb720dc..b087cb83da3a 100644
--- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -24,6 +24,53 @@
         .endm
 
 /*
+ * TLB bits
+ */
+#define PAGE_GLOBAL             (1 << 6)
+#define PAGE_VALID              (1 << 7)
+#define PAGE_DIRTY              (1 << 8)
+#define CACHE_CACHABLE_COW      (5 << 9)
+
+        /*
+         * inputs are the text nasid in t1, data nasid in t2.
+         */
+        .macro MAPPED_KERNEL_SETUP_TLB
+#ifdef CONFIG_MAPPED_KERNEL
+        /*
+         * This needs to read the nasid - assume 0 for now.
+         * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
+         * 0+DVG in tlblo_1.
+         */
+        dli     t0, 0xffffffffc0000000
+        dmtc0   t0, CP0_ENTRYHI
+        li      t0, 0x1c000             # Offset of text into node memory
+        dsll    t1, NASID_SHFT          # Shift text nasid into place
+        dsll    t2, NASID_SHFT          # Same for data nasid
+        or      t1, t1, t0              # Physical load address of kernel text
+        or      t2, t2, t0              # Physical load address of kernel data
+        dsrl    t1, 12                  # 4K pfn
+        dsrl    t2, 12                  # 4K pfn
+        dsll    t1, 6                   # Get pfn into place
+        dsll    t2, 6                   # Get pfn into place
+        li      t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6)
+        or      t0, t0, t1
+        mtc0    t0, CP0_ENTRYLO0        # physaddr, VG, cach exlwr
+        li      t0, ((PAGE_GLOBAL | PAGE_VALID |  PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6)
+        or      t0, t0, t2
+        mtc0    t0, CP0_ENTRYLO1        # physaddr, DVG, cach exlwr
+        li      t0, 0x1ffe000           # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
+        mtc0    t0, CP0_PAGEMASK
+        li      t0, 0                   # KMAP_INX
+        mtc0    t0, CP0_INDEX
+        li      t0, 1
+        mtc0    t0, CP0_WIRED
+        tlbwi
+#else
+        mtc0    zero, CP0_WIRED
+#endif
+        .endm
+
+/*
  * Intentionally empty macro, used in head.S. Override in
  * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
  */
diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
index 5edf05d9dad8..5d6a76434d00 100644
--- a/arch/mips/include/asm/mach-ip28/spaces.h
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
@@ -11,11 +11,14 @@
 #ifndef _ASM_MACH_IP28_SPACES_H
 #define _ASM_MACH_IP28_SPACES_H
 
-#define CAC_BASE                0xa800000000000000
+#define CAC_BASE        _AC(0xa800000000000000, UL)
 
-#define HIGHMEM_START           (~0UL)
+#define HIGHMEM_START   (~0UL)
 
-#define PHYS_OFFSET             _AC(0x20000000, UL)
+#define PHYS_OFFSET     _AC(0x20000000, UL)
+
+#define UNCAC_BASE      _AC(0xc0000000, UL)     /* 0xa0000000 + PHYS_OFFSET */
+#define IO_BASE         UNCAC_BASE
 
 #include <asm/mach-generic/spaces.h>
 
diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
index 98b4e7c0dbae..509cd5828044 100644
--- a/arch/mips/include/asm/mach-jz4740/dma.h
+++ b/arch/mips/include/asm/mach-jz4740/dma.h
@@ -16,8 +16,6 @@
 #ifndef __ASM_MACH_JZ4740_DMA_H__
 #define __ASM_MACH_JZ4740_DMA_H__
 
-struct jz4740_dma_chan;
-
 enum jz4740_dma_request_type {
         JZ4740_DMA_TYPE_AUTO_REQUEST    = 8,
         JZ4740_DMA_TYPE_UART_TRANSMIT   = 20,
@@ -33,58 +31,4 @@ enum jz4740_dma_request_type {
         JZ4740_DMA_TYPE_SLCD            = 30,
 };
 
-enum jz4740_dma_width {
-        JZ4740_DMA_WIDTH_32BIT  = 0,
-        JZ4740_DMA_WIDTH_8BIT   = 1,
-        JZ4740_DMA_WIDTH_16BIT  = 2,
-};
-
-enum jz4740_dma_transfer_size {
-        JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
-        JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
-        JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
-        JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
-        JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
-};
-
-enum jz4740_dma_flags {
-        JZ4740_DMA_SRC_AUTOINC = 0x2,
-        JZ4740_DMA_DST_AUTOINC = 0x1,
-};
-
-enum jz4740_dma_mode {
-        JZ4740_DMA_MODE_SINGLE  = 0,
-        JZ4740_DMA_MODE_BLOCK   = 1,
-};
-
-struct jz4740_dma_config {
-        enum jz4740_dma_width src_width;
-        enum jz4740_dma_width dst_width;
-        enum jz4740_dma_transfer_size transfer_size;
-        enum jz4740_dma_request_type request_type;
-        enum jz4740_dma_flags flags;
-        enum jz4740_dma_mode mode;
-};
-
-typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
-
-struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
-void jz4740_dma_free(struct jz4740_dma_chan *dma);
-
-void jz4740_dma_configure(struct jz4740_dma_chan *dma,
-        const struct jz4740_dma_config *config);
-
-
-void jz4740_dma_enable(struct jz4740_dma_chan *dma);
-void jz4740_dma_disable(struct jz4740_dma_chan *dma);
-
-void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
-void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
-void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
-
-uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
-
-void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
-        jz4740_dma_complete_callback_t cb);
-
 #endif  /* __ASM_JZ4740_DMA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
index 72cfebdb5a47..05988c2d6565 100644
--- a/arch/mips/include/asm/mach-jz4740/platform.h
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -32,6 +32,7 @@ extern struct platform_device jz4740_codec_device;
 extern struct platform_device jz4740_adc_device;
 extern struct platform_device jz4740_wdt_device;
 extern struct platform_device jz4740_pwm_device;
+extern struct platform_device jz4740_dma_device;
 
 void jz4740_serial_device_register(void);
 
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h b/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h
deleted file mode 100644
index ebdbab973e41..000000000000
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * include/asm-mips/pmc-sierra/msp71xx/gpio.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * @author Patrick Glass <patrickglass@gmail.com>
- */
-
-#ifndef __PMC_MSP71XX_GPIO_H
-#define __PMC_MSP71XX_GPIO_H
-
-/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
-#define ARCH_NR_GPIOS (28 + (3 * 8))
-
-/* new generic GPIO API - see Documentation/gpio.txt */
-#include <asm-generic/gpio.h>
-
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-
-/* Setup calls for the gpio and gpio extended */
-extern void msp71xx_init_gpio(void);
-extern void msp71xx_init_gpio_extended(void);
-extern int msp71xx_set_output_drive(unsigned gpio, int value);
-
-/* Custom output drive functionss */
-static inline int gpio_set_output_drive(unsigned gpio, int value)
-{
-        return msp71xx_set_output_drive(gpio, value);
-}
-
-/* IRQ's are not supported for gpio lines */
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return -EINVAL;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return -EINVAL;
-}
-
-#endif /* __PMC_MSP71XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
deleted file mode 100644
index 00fa3684ac98..000000000000
--- a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- * The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef __ASM_MIPS_GT64120_H
-#define __ASM_MIPS_GT64120_H
-
-/*
- * This is the CPU physical memory map of PPMC Board:
- *
- *    0x00000000-0x03FFFFFF      - 64MB SDRAM (SCS[0]#)
- *    0x1C000000-0x1C000000      - LED (CS0)
- *    0x1C800000-0x1C800007      - UART 16550 port (CS1)
- *    0x1F000000-0x1F000000      - MailBox (CS3)
- *    0x1FC00000-0x20000000      - 4MB Flash (BOOT CS)
- */
-
-#define WRPPMC_SDRAM_SCS0_BASE  0x00000000
-#define WRPPMC_SDRAM_SCS0_SIZE  0x04000000
-
-#define WRPPMC_UART16550_BASE   0x1C800000
-#define WRPPMC_UART16550_CLOCK  3686400 /* 3.68MHZ */
-
-#define WRPPMC_LED_BASE         0x1C000000
-#define WRPPMC_MBOX_BASE        0x1F000000
-
-#define WRPPMC_BOOTROM_BASE     0x1FC00000
-#define WRPPMC_BOOTROM_SIZE     0x00400000 /* 4M Flash */
-
-#define WRPPMC_MIPS_TIMER_IRQ   7 /* MIPS compare/count timer interrupt */
-#define WRPPMC_UART16550_IRQ    6
-#define WRPPMC_PCI_INTA_IRQ     3
-
-/*
- * PCI Bus I/O and Memory resources allocation
- *
- * NOTE: We only have PCI_0 hose interface
- */
-#define GT_PCI_MEM_BASE 0x13000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE  0x11000000UL
-#define GT_PCI_IO_SIZE  0x02000000UL
-
-/*
- * PCI interrupts will come in on either the INTA or INTD interrupt lines,
- * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
- * boards, they all either come in on IntD or they all come in on IntA, they
- * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
- * "requested" interrupt numbers and go through the list whenever we get an
- * IntA/D.
- *
- * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
- * INTD is 11.
- */
-#define GT_TIMER        4
-#define GT_INTA         2
-#define GT_INTD         5
-
-#ifndef __ASSEMBLY__
-
-/*
- * GT64120 internal register space base address
- */
-extern unsigned long gt64120_base;
-
-#define GT64120_BASE    (gt64120_base)
-
-/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
-#undef WRPPMC_EARLY_DEBUG
-
-#ifdef WRPPMC_EARLY_DEBUG
-extern void wrppmc_led_on(int mask);
-extern void wrppmc_led_off(int mask);
-extern void wrppmc_early_printk(const char *fmt, ...);
-#else
-#define wrppmc_early_printk(fmt, ...) do {} while (0)
-#endif /* WRPPMC_EARLY_DEBUG */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_MIPS_GT64120_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
deleted file mode 100644
index e86084c0bd6b..000000000000
--- a/arch/mips/include/asm/mach-wrppmc/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
-#define __ASM_MIPS_MACH_WRPPMC_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index bd9746fbe4af..48616816bcbc 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -24,12 +24,6 @@
 #define ASCII_DISPLAY_POS_BASE     0x1f000418
 
 /*
- * Reset register.
- */
-#define SOFTRES_REG       0x1f000500
-#define GORESET           0x42
-
-/*
  * Revision register.
  */
 #define MIPS_REVISION_REG                  0x1fc00010
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 87e6207b05e4..fed1c3e9b486 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -596,7 +596,7 @@
 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
-#define MIPS_CONF3_ISA_OE       (_ULCAST_(3) << 16)
+#define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 
 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 516e6e9a5594..3b29079b5424 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -28,11 +28,7 @@
 
 #define TLBMISS_HANDLER_SETUP_PGD(pgd)                                  \
 do {                                                                    \
-        void (*tlbmiss_handler_setup_pgd)(unsigned long);               \
-        extern u32 tlbmiss_handler_setup_pgd_array[16];                 \
-                                                                        \
-        tlbmiss_handler_setup_pgd =                                     \
-                (__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \
+        extern void tlbmiss_handler_setup_pgd(unsigned long);           \
         tlbmiss_handler_setup_pgd((unsigned long)(pgd));                \
 } while (0)
 
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index aef560a51a7e..bb68c3398c80 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -39,11 +39,17 @@
  * Common SMP definitions
  */
 #define RESET_VEC_PHYS          0x1fc00000
+#define RESET_VEC_SIZE          8192            /* 8KB reset code and data */
 #define RESET_DATA_PHYS         (RESET_VEC_PHYS + (1<<10))
+
+/* Offsets of parameters in the RESET_DATA_PHYS area */
 #define BOOT_THREAD_MODE        0
 #define BOOT_NMI_LOCK           4
 #define BOOT_NMI_HANDLER        8
 
+/* CPU ready flags for each CPU */
+#define BOOT_CPU_READY          2048
+
 #ifndef __ASSEMBLY__
 #include <linux/cpumask.h>
 #include <linux/spinlock.h>
@@ -59,23 +65,32 @@ int nlm_wakeup_secondary_cpus(void);
 void nlm_rmiboot_preboot(void);
 void nlm_percpu_init(int hwcpuid);
 
+static inline void *
+nlm_get_boot_data(int offset)
+{
+        return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset);
+}
+
 static inline void
 nlm_set_nmi_handler(void *handler)
 {
-        char *reset_data;
+        void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER);
 
-        reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
-        *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
+        *(int64_t *)nmih = (long)handler;
 }
 
 /*
  * Misc.
  */
+void nlm_init_boot_cpu(void);
 unsigned int nlm_get_cpu_frequency(void);
 void nlm_node_init(int node);
 extern struct plat_smp_ops nlm_smp_ops;
 extern char nlm_reset_entry[], nlm_reset_entry_end[];
 
+/* SWIOTLB */
+extern struct dma_map_ops nlm_swiotlb_dma_ops;
+
 extern unsigned int nlm_threads_per_core;
 extern cpumask_t nlm_cpumask;
 
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index a981f4681a15..4b5108dfaa16 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -315,7 +315,7 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
 {
         uint64_t ipi;
 
-        ipi = (nmi << 31) | (irq << 20);
+        ipi = ((uint64_t)nmi << 31) | (irq << 20);
         ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
         nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
 }
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 7e47209327a5..f4ea0f7f3965 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -59,6 +59,7 @@ void xlp_wakeup_secondary_cpus(void);
 
 void xlp_mmu_init(void);
 void nlm_hal_init(void);
+void *xlp_dt_init(void *fdtp);
 
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
index 2a78929cef73..5604db3d1836 100644
--- a/arch/mips/include/asm/netlogic/xlr/fmn.h
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -175,6 +175,10 @@
 #define nlm_write_c2_cc14(s, v)         __write_32bit_c2_register($30, s, v)
 #define nlm_write_c2_cc15(s, v)         __write_32bit_c2_register($31, s, v)
 
+#define nlm_read_c2_status0()           __read_32bit_c2_register($2, 0)
+#define nlm_write_c2_status0(v)         __write_32bit_c2_register($2, 0, v)
+#define nlm_read_c2_status1()           __read_32bit_c2_register($2, 1)
+#define nlm_write_c2_status1(v)         __write_32bit_c2_register($2, 1, v)
 #define nlm_read_c2_status(sel)         __read_32bit_c2_register($2, 0)
 #define nlm_read_c2_config()            __read_32bit_c2_register($3, 0)
 #define nlm_write_c2_config(v)          __write_32bit_c2_register($3, 0, v)
@@ -237,7 +241,7 @@ static inline void nlm_msgwait(unsigned int mask)
 /*
  * Disable interrupts and enable COP2 access
  */
-static inline uint32_t nlm_cop2_enable(void)
+static inline uint32_t nlm_cop2_enable_irqsave(void)
 {
         uint32_t sr = read_c0_status();
 
@@ -245,7 +249,7 @@ static inline uint32_t nlm_cop2_enable(void)
         return sr;
 }
 
-static inline void nlm_cop2_restore(uint32_t sr)
+static inline void nlm_cop2_disable_irqrestore(uint32_t sr)
 {
         write_c0_status(sr);
 }
@@ -296,7 +300,7 @@ static inline int nlm_fmn_send(unsigned int size, unsigned int code,
          */
         for (i = 0; i < 8; i++) {
                 nlm_msgsnd(dest);
-                status = nlm_read_c2_status(0);
+                status = nlm_read_c2_status0();
                 if ((status & 0x2) == 1)
                         pr_info("Send pending fail!\n");
                 if ((status & 0x4) == 0)
@@ -316,7 +320,7 @@ static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
 
         /* wait for load pending to clear */
         do {
-                status = nlm_read_c2_status(1);
+                status = nlm_read_c2_status0();
         } while ((status & 0x08) != 0);
 
         /* receive error bits */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 284fa8d773ba..7b7818d1e4d5 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -227,6 +227,7 @@ enum cvmx_board_types_enum {
          * use any numbers in this range.
          */
         CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
+        CVMX_BOARD_TYPE_UBNT_E100 = 20002,
         CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
 
         /* The remaining range is reserved for future use. */
@@ -325,6 +326,7 @@ static inline const char *cvmx_board_type_to_string(enum
 
                     /* Customer private range */
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
         }
         return "Unsupported Board";
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f59552fae917..f6be4741f7e8 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -205,10 +205,8 @@ extern int __virt_addr_valid(const volatile void *kaddr);
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
                                  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
-#define UNCAC_ADDR(addr)        ((addr) - PAGE_OFFSET + UNCAC_BASE +    \
-                                                                PHYS_OFFSET)
-#define CAC_ADDR(addr)          ((addr) - UNCAC_BASE + PAGE_OFFSET -    \
-                                                                PHYS_OFFSET)
+#define UNCAC_ADDR(addr)        ((addr) - PAGE_OFFSET + UNCAC_BASE)
+#define CAC_ADDR(addr)          ((addr) - UNCAC_BASE + PAGE_OFFSET)
 
 #include <asm-generic/memory_model.h>
 #include <asm-generic/getorder.h>
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index b8e24fd4cbc5..fa8e0aa250ca 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -52,7 +52,6 @@ struct pci_controller {
 /*
  * Used by boards to register their PCI busses before the actual scanning.
  */
-extern struct pci_controller * alloc_pci_controller(void);
 extern void register_pci_controller(struct pci_controller *hose);
 
 /*
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 8b8f6b393363..008324d1c261 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -394,9 +394,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
         phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
         return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
 }
-#else
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
+#define io_remap_pfn_range io_remap_pfn_range
 #endif
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 1470b7b68b0e..3605b844ad87 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -137,7 +137,7 @@ union mips_watch_reg_state {
         struct mips3264_watch_reg_state mips3264;
 };
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#if defined(CONFIG_CPU_CAVIUM_OCTEON)
 
 struct octeon_cop2_state {
         /* DMFC2 rt, 0x0201 */
@@ -182,13 +182,26 @@ struct octeon_cop2_state {
         /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
         unsigned long   cop2_gfm_result[2];
 };
-#define INIT_OCTEON_COP2 {0,}
+#define COP2_INIT                                               \
+        .cp2                    = {0,},
 
 struct octeon_cvmseg_state {
         unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
                             [cpu_dcache_line_size() / sizeof(unsigned long)];
 };
 
+#elif defined(CONFIG_CPU_XLP)
+struct nlm_cop2_state {
+        u64     rx[4];
+        u64     tx[4];
+        u32     tx_msg_status;
+        u32     rx_msg_status;
+};
+
+#define COP2_INIT                                               \
+        .cp2                    = {{0}, {0}, 0, 0},
+#else
+#define COP2_INIT
 #endif
 
 typedef struct {
@@ -231,8 +244,11 @@ struct thread_struct {
         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
         unsigned long error_code;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
-    struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
-    struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
+        struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
+        struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
+#endif
+#ifdef CONFIG_CPU_XLP
+        struct nlm_cop2_state cp2;
 #endif
         struct mips_abi *abi;
 };
@@ -245,13 +261,6 @@ struct thread_struct {
 #define FPAFF_INIT
 #endif /* CONFIG_MIPS_MT_FPAFF */
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-#define OCTEON_INIT                                             \
-        .cp2                    = INIT_OCTEON_COP2,
-#else
-#define OCTEON_INIT
-#endif /* CONFIG_CPU_CAVIUM_OCTEON */
-
 #define INIT_THREAD  {                                          \
         /*                                                      \
          * Saved main processor registers                       \
@@ -300,9 +309,9 @@ struct thread_struct {
         .cp0_baduaddr           = 0,                            \
         .error_code             = 0,                            \
         /*                                                      \
-         * Cavium Octeon specifics (null if not Octeon)         \
+         * Platform specific cop2 registers(null if no COP2)    \
          */                                                     \
-        OCTEON_INIT                                             \
+        COP2_INIT                                               \
 }
 
 struct task_struct;
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index a89d1b10d027..23fc95e65673 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -70,6 +70,14 @@
 #ifndef CONFIG_CPU_HAS_SMARTMIPS
                 LONG_S  v1, PT_LO(sp)
 #endif
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+                /*
+                 * The Octeon multiplier state is affected by general
+                 * multiply instructions. It must be saved before and
+                 * kernel code might corrupt it
+                 */
+                jal     octeon_mult_save
+#endif
                 .endm
 
                 .macro  SAVE_STATIC
@@ -218,17 +226,8 @@
                 ori     $28, sp, _THREAD_MASK
                 xori    $28, _THREAD_MASK
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
-                .set    mips64
-                pref    0, 0($28)       /* Prefetch the current pointer */
-                pref    0, PT_R31(sp)   /* Prefetch the $31(ra) */
-                /* The Octeon multiplier state is affected by general multiply
-                    instructions. It must be saved before and kernel code might
-                    corrupt it */
-                jal     octeon_mult_save
-                LONG_L  v1, 0($28)  /* Load the current pointer */
-                         /* Restore $31(ra) that was changed by the jal */
-                LONG_L  ra, PT_R31(sp)
-                pref    0, 0(v1)    /* Prefetch the current thread */
+                .set    mips64
+                pref    0, 0($28)       /* Prefetch the current pointer */
 #endif
                 .set    pop
                 .endm
@@ -248,6 +247,10 @@
                 .endm
 
                 .macro  RESTORE_TEMP
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+                /* Restore the Octeon multiplier state */
+                jal     octeon_mult_restore
+#endif
 #ifdef CONFIG_CPU_HAS_SMARTMIPS
                 LONG_L  $24, PT_ACX(sp)
                 mtlhx   $24
@@ -360,10 +363,6 @@
                 DVPE    5                               # dvpe a1
                 jal     mips_ihb
 #endif /* CONFIG_MIPS_MT_SMTC */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-                /* Restore the Octeon multiplier state */
-                jal     octeon_mult_restore
-#endif
                 mfc0    a0, CP0_STATUS
                 ori     a0, STATMASK
                 xori    a0, STATMASK
diff --git a/arch/mips/include/asm/stackprotector.h b/arch/mips/include/asm/stackprotector.h
new file mode 100644
index 000000000000..eb9b1035e926
--- /dev/null
+++ b/arch/mips/include/asm/stackprotector.h
@@ -0,0 +1,40 @@
+/*
+ * GCC stack protector support.
+ *
+ * (This is directly adopted from the ARM implementation)
+ *
+ * Stack protector works by putting predefined pattern at the start of
+ * the stack frame and verifying that it hasn't been overwritten when
+ * returning from the function.  The pattern is called stack canary
+ * and gcc expects it to be defined by a global variable called
+ * "__stack_chk_guard" on MIPS.  This unfortunately means that on SMP
+ * we cannot have a different canary value per task.
+ */
+
+#ifndef _ASM_STACKPROTECTOR_H
+#define _ASM_STACKPROTECTOR_H 1
+
+#include <linux/random.h>
+#include <linux/version.h>
+
+extern unsigned long __stack_chk_guard;
+
+/*
+ * Initialize the stackprotector canary value.
+ *
+ * NOTE: this must only be called from functions that never return,
+ * and it must always be inlined.
+ */
+static __always_inline void boot_init_stack_canary(void)
+{
+        unsigned long canary;
+
+        /* Try to get a semi random initial value. */
+        get_random_bytes(&canary, sizeof(canary));
+        canary ^= LINUX_VERSION_CODE;
+
+        current->stack_canary = canary;
+        __stack_chk_guard = current->stack_canary;
+}
+
+#endif  /* _ASM_STACKPROTECTOR_H */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index fd16bcb6c311..eb0af15ac656 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -15,6 +15,7 @@
 #include <asm/cpu-features.h>
 #include <asm/watch.h>
 #include <asm/dsp.h>
+#include <asm/cop2.h>
 
 struct task_struct;
 
@@ -66,10 +67,18 @@ do {									\
 
 #define switch_to(prev, next, last)                                     \
 do {                                                                    \
-        u32 __usedfpu;                                                  \
+        u32 __usedfpu, __c0_stat;                                       \
         __mips_mt_fpaff_switch_to(prev);                                \
         if (cpu_has_dsp)                                                \
                 __save_dsp(prev);                                       \
+        if (cop2_present && (KSTK_STATUS(prev) & ST0_CU2)) {            \
+                if (cop2_lazy_restore)                                  \
+                        KSTK_STATUS(prev) &= ~ST0_CU2;                  \
+                __c0_stat = read_c0_status();                           \
+                write_c0_status(__c0_stat | ST0_CU2);                   \
+                cop2_save(&prev->thread.cp2);                           \
+                write_c0_status(__c0_stat & ~ST0_CU2);                  \
+        }                                                               \
         __clear_software_ll_bit();                                      \
         __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU);  \
         (last) = resume(prev, next, task_thread_info(next), __usedfpu); \
@@ -77,6 +86,14 @@ do {									\
 
 #define finish_arch_switch(prev)                                        \
 do {                                                                    \
+        u32 __c0_stat;                                                  \
+        if (cop2_present && !cop2_lazy_restore &&                       \
+                        (KSTK_STATUS(current) & ST0_CU2)) {             \
+                __c0_stat = read_c0_status();                           \
+                write_c0_status(__c0_stat | ST0_CU2);                   \
+                cop2_restore(&current->thread.cp2);                     \
+                write_c0_status(__c0_stat & ~ST0_CU2);                  \
+        }                                                               \
         if (cpu_has_dsp)                                                \
                 __restore_dsp(current);                                 \
         if (cpu_has_userlocal)                                          \
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 895320e25662..61215a34acc6 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -109,6 +109,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal() */
 #define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
+#define TIF_NOHZ                19      /* in adaptive nohz mode */
 #define TIF_FIXADE              20      /* Fix address errors in software */
 #define TIF_LOGADE              21      /* Log address errors to syslog */
 #define TIF_32BIT_REGS          22      /* also implies 16/32 fprs */
@@ -124,6 +125,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_USEDFPU            (1<<TIF_USEDFPU)
+#define _TIF_NOHZ               (1<<TIF_NOHZ)
 #define _TIF_FIXADE             (1<<TIF_FIXADE)
 #define _TIF_LOGADE             (1<<TIF_LOGADE)
 #define _TIF_32BIT_REGS         (1<<TIF_32BIT_REGS)
@@ -131,14 +133,19 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_FPUBOUND           (1<<TIF_FPUBOUND)
 #define _TIF_LOAD_WATCH         (1<<TIF_LOAD_WATCH)
 
+#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE |       \
+                                 _TIF_SYSCALL_AUDIT)
+
 /* work to do in syscall_trace_leave() */
-#define _TIF_WORK_SYSCALL_EXIT  (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
+#define _TIF_WORK_SYSCALL_EXIT  (_TIF_NOHZ | _TIF_SYSCALL_TRACE |       \
+                                 _TIF_SYSCALL_AUDIT)
 
 /* work to do on interrupt/exception return */
 #define _TIF_WORK_MASK          \
         (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
 /* work to do on any return to u-space */
-#define _TIF_ALLWORK_MASK       (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT)
+#define _TIF_ALLWORK_MASK       (_TIF_NOHZ | _TIF_WORK_MASK |           \
+                                 _TIF_WORK_SYSCALL_EXIT)
 
 #endif /* __KERNEL__ */
 
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 370d967725c2..c33a9564fb41 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -13,12 +13,8 @@
 
 #ifdef CONFIG_EXPORT_UASM
 #include <linux/export.h>
-#define __uasminit
-#define __uasminitdata
 #define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
 #else
-#define __uasminit __cpuinit
-#define __uasminitdata __cpuinitdata
 #define UASM_EXPORT_SYMBOL(sym)
 #endif
 
@@ -54,43 +50,36 @@
 #endif
 
 #define Ip_u1u2u3(op)                                                   \
-void __uasminit                                                         \
-ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
+void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u2u1u3(op)                                                   \
-void __uasminit                                                         \
-ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
+void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u3u1u2(op)                                                   \
-void __uasminit                                                         \
-ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
+void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u1u2s3(op)                                                   \
-void __uasminit                                                         \
-ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
+void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
 #define Ip_u2s3u1(op)                                                   \
-void __uasminit                                                         \
-ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
+void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
 
 #define Ip_u2u1s3(op)                                                   \
-void __uasminit                                                         \
-ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
+void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
 #define Ip_u2u1msbu3(op)                                                \
-void __uasminit                                                         \
-ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c,   \
+void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
            unsigned int d)
 
 #define Ip_u1u2(op)                                                     \
-void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
+void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
 
 #define Ip_u1s2(op)                                                     \
-void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
+void ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
 
-#define Ip_u1(op) void __uasminit ISAOPC(op)(u32 **buf, unsigned int a)
+#define Ip_u1(op) void ISAOPC(op)(u32 **buf, unsigned int a)
 
-#define Ip_0(op) void __uasminit ISAOPC(op)(u32 **buf)
+#define Ip_0(op) void ISAOPC(op)(u32 **buf)
 
 Ip_u2u1s3(_addiu);
 Ip_u3u1u2(_addu);
@@ -163,7 +152,7 @@ struct uasm_label {
         int lab;
 };
 
-void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr,
+void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr,
                         int lid);
 #ifdef CONFIG_64BIT
 int ISAFUNC(uasm_in_compat_space_p)(long addr);
@@ -174,7 +163,7 @@ void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr);
 void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr);
 
 #define UASM_L_LA(lb)                                                   \
-static inline void __uasminit ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \
+static inline void ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \
 {                                                                       \
         ISAFUNC(uasm_build_label)(lab, addr, label##lb);                \
 }
diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
index 680e7efebbaf..26d2ed1fa917 100644
--- a/arch/mips/include/asm/xtalk/xtalk.h
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -47,6 +47,15 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
 #define XIO_PORT(x)     ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
 #define XIO_PACK(p, o)  ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
 
+#ifdef CONFIG_PCI
+extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
+#else
+static inline int bridge_probe(nasid_t nasid, int widget, int masterwid)
+{
+        return 0;
+}
+#endif
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_XTALK_XTALK_H */
diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h
index 0bda78f70e1e..6ca432f00860 100644
--- a/arch/mips/include/uapi/asm/fcntl.h
+++ b/arch/mips/include/uapi/asm/fcntl.h
@@ -5,9 +5,10 @@
  *
  * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
  */
-#ifndef _ASM_FCNTL_H
-#define _ASM_FCNTL_H
+#ifndef _UAPI_ASM_FCNTL_H
+#define _UAPI_ASM_FCNTL_H
 
+#include <asm/sgidefs.h>
 
 #define O_APPEND        0x0008
 #define O_DSYNC         0x0010  /* used to be O_SYNC, see below */
@@ -55,14 +56,15 @@
  * contain all the same fields as struct flock.
  */
 
-#ifdef CONFIG_32BIT
+#if _MIPS_SIM != _MIPS_SIM_ABI64
+
 #include <linux/types.h>
 
 struct flock {
         short   l_type;
         short   l_whence;
-        off_t   l_start;
-        off_t   l_len;
+        __kernel_off_t  l_start;
+        __kernel_off_t  l_len;
         long    l_sysid;
         __kernel_pid_t l_pid;
         long    pad[4];
@@ -70,8 +72,8 @@ struct flock {
 
 #define HAVE_ARCH_STRUCT_FLOCK
 
-#endif /* CONFIG_32BIT */
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #include <asm-generic/fcntl.h>
 
-#endif /* _ASM_FCNTL_H */
+#endif /* _UAPI_ASM_FCNTL_H */
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 0f4aec2ad1e6..e5a676e3d3c0 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -409,10 +409,11 @@ enum mm_32f_73_minor_op {
 enum mm_16c_minor_op {
         mm_lwm16_op = 0x04,
         mm_swm16_op = 0x05,
-        mm_jr16_op = 0x18,
-        mm_jrc_op = 0x1a,
-        mm_jalr16_op = 0x1c,
-        mm_jalrs16_op = 0x1e,
+        mm_jr16_op = 0x0c,
+        mm_jrc_op = 0x0d,
+        mm_jalr16_op = 0x0e,
+        mm_jalrs16_op = 0x0f,
+        mm_jraddiusp_op = 0x18,
 };
 
 /*
diff --git a/arch/mips/include/uapi/asm/msgbuf.h b/arch/mips/include/uapi/asm/msgbuf.h
index 0d6c7f14de31..df849e87d9ae 100644
--- a/arch/mips/include/uapi/asm/msgbuf.h
+++ b/arch/mips/include/uapi/asm/msgbuf.h
@@ -14,25 +14,25 @@
 
 struct msqid64_ds {
         struct ipc64_perm msg_perm;
-#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if !defined(__mips64) && defined(__MIPSEB__)
         unsigned long   __unused1;
 #endif
         __kernel_time_t msg_stime;      /* last msgsnd time */
-#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if !defined(__mips64) && defined(__MIPSEL__)
         unsigned long   __unused1;
 #endif
-#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if !defined(__mips64) && defined(__MIPSEB__)
         unsigned long   __unused2;
 #endif
         __kernel_time_t msg_rtime;      /* last msgrcv time */
-#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if !defined(__mips64) && defined(__MIPSEL__)
         unsigned long   __unused2;
 #endif
-#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if !defined(__mips64) && defined(__MIPSEB__)
         unsigned long   __unused3;
 #endif
         __kernel_time_t msg_ctime;      /* last change time */
-#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if !defined(__mips64) && defined(__MIPSEL__)
         unsigned long   __unused3;
 #endif
         unsigned long  msg_cbytes;      /* current number of bytes on queue */
diff --git a/arch/mips/include/uapi/asm/resource.h b/arch/mips/include/uapi/asm/resource.h
index 87cb3085269c..b26439d4ab0b 100644
--- a/arch/mips/include/uapi/asm/resource.h
+++ b/arch/mips/include/uapi/asm/resource.h
@@ -26,7 +26,7 @@
  * but we keep the old value on MIPS32,
  * for compatibility:
  */
-#ifdef CONFIG_32BIT
+#ifndef __mips64
 # define RLIM_INFINITY          0x7fffffffUL
 #endif
 
diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h
index 6a8714193fb9..88e292b7719e 100644
--- a/arch/mips/include/uapi/asm/siginfo.h
+++ b/arch/mips/include/uapi/asm/siginfo.h
@@ -25,11 +25,12 @@ struct siginfo;
 /*
  * Careful to keep union _sifields from shifting ...
  */
-#ifdef CONFIG_32BIT
+#if _MIPS_SZLONG == 32
 #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
-#endif
-#ifdef CONFIG_64BIT
+#elif _MIPS_SZLONG == 64
 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+#else
+#error _MIPS_SZLONG neither 32 nor 64
 #endif
 
 #include <asm-generic/siginfo.h>
diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h
index 3b211507be7f..61c01f054d1b 100644
--- a/arch/mips/include/uapi/asm/socket.h
+++ b/arch/mips/include/uapi/asm/socket.h
@@ -92,4 +92,6 @@
 
 #define SO_SELECT_ERR_QUEUE     45
 
+#define SO_BUSY_POLL            46
+
 #endif /* _UAPI_ASM_SOCKET_H */
diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h
index 97c2f81b4b43..ac9a8f9cd1fb 100644
--- a/arch/mips/include/uapi/asm/swab.h
+++ b/arch/mips/include/uapi/asm/swab.h
@@ -13,7 +13,7 @@
 
 #define __SWAB_64_THRU_32__
 
-#ifdef CONFIG_CPU_MIPSR2
+#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
 
 static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
 {
@@ -39,10 +39,10 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 #define __arch_swab32 __arch_swab32
 
 /*
- * Having already checked for CONFIG_CPU_MIPSR2, enable the
- * optimized version for 64-bit kernel on r2 CPUs.
+ * Having already checked for MIPS R2, enable the optimized version for
+ * 64-bit kernel on r2 CPUs.
  */
-#ifdef CONFIG_64BIT
+#ifdef __mips64
 static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
 {
         __asm__(
@@ -54,6 +54,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
         return x;
 }
 #define __arch_swab64 __arch_swab64
-#endif /* CONFIG_64BIT */
-#endif /* CONFIG_CPU_MIPSR2 */
+#endif /* __mips64 */
+#endif /* MIPS R2 or newer  */
 #endif /* _ASM_SWAB_H */