Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "MIPS updates:

   - All the things that didn't make 3.10.
   - Removes the Windriver PPMC platform.  Nobody will miss it.
   - Remove a workaround from kernel/irq/irqdomain.c which was there
     exclusivly for MIPS.  Patch by Grant Likely.
   - More small improvments for the SEAD 3 platform
   - Improvments on the BMIPS / SMP support for the BCM63xx series.
   - Various cleanups of dead leftovers.
   - Platform support for the Cavium Octeon-based EdgeRouter Lite.

  Two large KVM patchsets didn't make it for this pull request because
  their respective authors are vacationing"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (124 commits)
  MIPS: Kconfig: Add missing MODULES dependency to VPE_LOADER
  MIPS: BCM63xx: CLK: Add dummy clk_{set,round}_rate() functions
  MIPS: SEAD3: Disable L2 cache on SEAD-3.
  MIPS: BCM63xx: Enable second core SMP on BCM6328 if available
  MIPS: BCM63xx: Add SMP support to prom.c
  MIPS: define write{b,w,l,q}_relaxed
  MIPS: Expose missing pci_io{map,unmap} declarations
  MIPS: Malta: Update GCMP detection.
  Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"
  MIPS: APSP: Remove <asm/kspd.h>
  SSB: Kconfig: Amend SSB_EMBEDDED dependencies
  MIPS: microMIPS: Fix improper definition of ISA exception bit.
  MIPS: Don't try to decode microMIPS branch instructions where they cannot exist.
  MIPS: Declare emulate_load_store_microMIPS as a static function.
  MIPS: Fix typos and cleanup comment
  MIPS: Cleanup indentation and whitespace
  MIPS: BMIPS: support booting from physical CPU other than 0
  MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS
  MIPS: GIC: Fix gic_set_affinity infinite loop
  MIPS: Don't save/restore OCTEON wide multiplier state on syscalls.
  ...

1 files changed, 28 insertions, 1 deletions

diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c
index 317931c6cf58..acbeb1fe7c57 100644
--- a/arch/mips/bcm63xx/reset.c
+++ b/arch/mips/bcm63xx/reset.c
@@ -30,6 +30,19 @@
         [BCM63XX_RESET_PCIE]            = BCM## __cpu ##_RESET_PCIE,    \
         [BCM63XX_RESET_PCIE_EXT]        = BCM## __cpu ##_RESET_PCIE_EXT,
 
+#define BCM3368_RESET_SPI       SOFTRESET_3368_SPI_MASK
+#define BCM3368_RESET_ENET      SOFTRESET_3368_ENET_MASK
+#define BCM3368_RESET_USBH      0
+#define BCM3368_RESET_USBD      SOFTRESET_3368_USBS_MASK
+#define BCM3368_RESET_DSL       0
+#define BCM3368_RESET_SAR       0
+#define BCM3368_RESET_EPHY      SOFTRESET_3368_EPHY_MASK
+#define BCM3368_RESET_ENETSW    0
+#define BCM3368_RESET_PCM       SOFTRESET_3368_PCM_MASK
+#define BCM3368_RESET_MPI       SOFTRESET_3368_MPI_MASK
+#define BCM3368_RESET_PCIE      0
+#define BCM3368_RESET_PCIE_EXT  0
+
 #define BCM6328_RESET_SPI       SOFTRESET_6328_SPI_MASK
 #define BCM6328_RESET_ENET      0
 #define BCM6328_RESET_USBH      SOFTRESET_6328_USBH_MASK
@@ -117,6 +130,10 @@
 /*
  * core reset bits
  */
+static const u32 bcm3368_reset_bits[] = {
+        __GEN_RESET_BITS_TABLE(3368)
+};
+
 static const u32 bcm6328_reset_bits[] = {
         __GEN_RESET_BITS_TABLE(6328)
 };
@@ -146,7 +163,10 @@ static int reset_reg;
 
 static int __init bcm63xx_reset_bits_init(void)
 {
-        if (BCMCPU_IS_6328()) {
+        if (BCMCPU_IS_3368()) {
+                reset_reg = PERF_SOFTRESET_6358_REG;
+                bcm63xx_reset_bits = bcm3368_reset_bits;
+        } else if (BCMCPU_IS_6328()) {
                 reset_reg = PERF_SOFTRESET_6328_REG;
                 bcm63xx_reset_bits = bcm6328_reset_bits;
         } else if (BCMCPU_IS_6338()) {
@@ -170,6 +190,13 @@ static int __init bcm63xx_reset_bits_init(void)
 }
 #else
 
+#ifdef CONFIG_BCM63XX_CPU_3368
+static const u32 bcm63xx_reset_bits[] = {
+        __GEN_RESET_BITS_TABLE(3368)
+};
+#define reset_reg PERF_SOFTRESET_6358_REG
+#endif
+
 #ifdef CONFIG_BCM63XX_CPU_6328
 static const u32 bcm63xx_reset_bits[] = {
         __GEN_RESET_BITS_TABLE(6328)