Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

56 files changed, 2790 insertions, 582 deletions

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 71f90f864748..c0deacae778d 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -20,23 +20,23 @@ config ARCH_DAVINCI_DM644x
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM355
-        bool "DaVinci 355 based system"
+        bool "DaVinci 355 based system"
         select AINTC
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM646x
-        bool "DaVinci 646x based system"
+        bool "DaVinci 646x based system"
         select AINTC
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DA830
-        bool "DA830/OMAP-L137 based system"
+        bool "DA830/OMAP-L137/AM17x based system"
         select CP_INTC
         select ARCH_DAVINCI_DA8XX
         select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
 
 config ARCH_DAVINCI_DA850
-        bool "DA850/OMAP-L138 based system"
+        bool "DA850/OMAP-L138/AM18x based system"
         select CP_INTC
         select ARCH_DAVINCI_DA8XX
         select ARCH_HAS_CPUFREQ
@@ -61,6 +61,9 @@ config MACH_DAVINCI_EVM
         bool "TI DM644x EVM"
         default ARCH_DAVINCI_DM644x
         depends on ARCH_DAVINCI_DM644x
+        select MISC_DEVICES
+        select EEPROM_AT24
+        select I2C
         help
           Configure this option to specify the whether the board used
           for development is a DM644x EVM
@@ -68,6 +71,9 @@ config MACH_DAVINCI_EVM
 config MACH_SFFSDR
         bool "Lyrtech SFFSDR"
         depends on ARCH_DAVINCI_DM644x
+        select MISC_DEVICES
+        select EEPROM_AT24
+        select I2C
         help
           Say Y here to select the Lyrtech Small Form Factor
           Software Defined Radio (SFFSDR) board.
@@ -99,6 +105,9 @@ config MACH_DAVINCI_DM6467_EVM
         default ARCH_DAVINCI_DM646x
         depends on ARCH_DAVINCI_DM646x
         select MACH_DAVINCI_DM6467TEVM
+        select MISC_DEVICES
+        select EEPROM_AT24
+        select I2C
         help
           Configure this option to specify the whether the board used
           for development is a DM6467 EVM
@@ -110,26 +119,32 @@ config MACH_DAVINCI_DM365_EVM
         bool "TI DM365 EVM"
         default ARCH_DAVINCI_DM365
         depends on ARCH_DAVINCI_DM365
+        select MISC_DEVICES
+        select EEPROM_AT24
+        select I2C
         help
           Configure this option to specify whether the board used
           for development is a DM365 EVM
 
 config MACH_DAVINCI_DA830_EVM
-        bool "TI DA830/OMAP-L137 Reference Platform"
+        bool "TI DA830/OMAP-L137/AM17x Reference Platform"
         default ARCH_DAVINCI_DA830
         depends on ARCH_DAVINCI_DA830
         select GPIO_PCF857X
+        select MISC_DEVICES
+        select EEPROM_AT24
+        select I2C
         help
-          Say Y here to select the TI DA830/OMAP-L137 Evaluation Module.
+          Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
 
 choice
-        prompt "Select DA830/OMAP-L137 UI board peripheral"
+        prompt "Select DA830/OMAP-L137/AM17x UI board peripheral"
         depends on MACH_DAVINCI_DA830_EVM
         help
-          The presence of UI card on the DA830/OMAP-L137 EVM is detected
-          automatically based on successful probe of the I2C based GPIO
-          expander on that board. This option selected in this menu has
-          an effect only in case of a successful UI card detection.
+          The presence of UI card on the DA830/OMAP-L137/AM17x EVM is
+          detected automatically based on successful probe of the I2C
+          based GPIO expander on that board. This option selected in this
+          menu has an effect only in case of a successful UI card detection.
 
 config DA830_UI_LCD
         bool "LCD"
@@ -140,23 +155,22 @@ config DA830_UI_LCD
 config DA830_UI_NAND
         bool "NAND flash"
         help
-          Say Y here to use the NAND flash.  Do not forget to setup
+          Say Y here to use the NAND flash. Do not forget to setup
           the switch correctly.
 endchoice
 
 config MACH_DAVINCI_DA850_EVM
-        bool "TI DA850/OMAP-L138 Reference Platform"
+        bool "TI DA850/OMAP-L138/AM18x Reference Platform"
         default ARCH_DAVINCI_DA850
         depends on ARCH_DAVINCI_DA850
-        select GPIO_PCA953X
         help
-          Say Y here to select the TI DA850/OMAP-L138 Evaluation Module.
+          Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module.
 
 choice
         prompt "Select peripherals connected to expander on UI board"
         depends on MACH_DAVINCI_DA850_EVM
         help
-          The presence of User Interface (UI) card on the DA850/OMAP-L138
+          The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x
           EVM is detected automatically based on successful probe of the I2C
           based GPIO expander on that card. This option selected in this
           menu has an effect only in case of a successful UI card detection.
@@ -165,19 +179,25 @@ config DA850_UI_NONE
         bool "No peripheral is enabled"
         help
           Say Y if you do not want to enable any of the peripherals connected
-          to TCA6416 expander on DA850/OMAP-L138 EVM UI card
+          to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card
 
 config DA850_UI_RMII
         bool "RMII Ethernet PHY"
         help
-          Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM.
-          This PHY is found on the UI daughter card that is supplied with
+          Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x
+          EVM. This PHY is found on the UI daughter card that is supplied with
           the EVM.
           NOTE: Please take care while choosing this option, MII PHY will
           not be functional if RMII mode is selected.
 
 endchoice
 
+config GPIO_PCA953X
+        default MACH_DAVINCI_DA850_EVM
+
+config KEYBOARD_GPIO_POLLED
+        default MACH_DAVINCI_DA850_EVM
+
 config MACH_TNETV107X
         bool "TI TNETV107X Reference Platform"
         default ARCH_DAVINCI_TNETV107X
@@ -185,6 +205,25 @@ config MACH_TNETV107X
         help
           Say Y here to select the TI TNETV107X Evaluation Module.
 
+config MACH_MITYOMAPL138
+        bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
+        depends on ARCH_DAVINCI_DA850
+        select MISC_DEVICES
+        select EEPROM_AT24
+        select I2C
+        help
+          Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
+          System on Module.  Information on this SoM may be found at
+          http://www.mitydsp.com
+
+config MACH_OMAPL138_HAWKBOARD
+        bool "TI AM1808 / OMAPL-138 Hawkboard platform"
+        depends on ARCH_DAVINCI_DA850
+        help
+          Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform .
+          Information of this board may be found at
+          http://www.hawkboard.org/
+
 config DAVINCI_MUX
         bool "DAVINCI multiplexing support"
         depends on ARCH_DAVINCI
@@ -195,20 +234,20 @@ config DAVINCI_MUX
           say Y.
 
 config DAVINCI_MUX_DEBUG
-        bool "Multiplexing debug output"
-        depends on DAVINCI_MUX
-        help
-          Makes the multiplexing functions print out a lot of debug info.
-          This is useful if you want to find out the correct values of the
-          multiplexing registers.
+        bool "Multiplexing debug output"
+        depends on DAVINCI_MUX
+        help
+          Makes the multiplexing functions print out a lot of debug info.
+          This is useful if you want to find out the correct values of the
+          multiplexing registers.
 
 config DAVINCI_MUX_WARNINGS
-        bool "Warn about pins the bootloader didn't set up"
-        depends on DAVINCI_MUX
-        help
-          Choose Y here to warn whenever driver initialization logic needs
-          to change the pin multiplexing setup.  When there are no warnings
-          printed, it's safe to deselect DAVINCI_MUX for your product.
+        bool "Warn about pins the bootloader didn't set up"
+        depends on DAVINCI_MUX
+        help
+          Choose Y here to warn whenever driver initialization logic needs
+          to change the pin multiplexing setup. When there are no warnings
+          printed, it's safe to deselect DAVINCI_MUX for your product.
 
 config DAVINCI_RESET_CLOCKS
         bool "Reset unused clocks during boot"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index eab4c0fd667a..0b87a1ca2bb3 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
 
 # Common objects
 obj-y                   := time.o clock.o serial.o io.o psc.o \
-                           gpio.o dma.o usb.o common.o sram.o
+                           gpio.o dma.o usb.o common.o sram.o aemif.o
 
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
 
@@ -33,6 +33,8 @@ obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)    += board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)    += board-da850-evm.o
 obj-$(CONFIG_MACH_TNETV107X)            += board-tnetv107x-evm.o
+obj-$(CONFIG_MACH_MITYOMAPL138)         += board-mityomapl138.o
+obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)   += board-omapl138-hawk.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)                  += cpufreq.o
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
new file mode 100644
index 000000000000..1ce70a91f2e9
--- /dev/null
+++ b/arch/arm/mach-davinci/aemif.c
@@ -0,0 +1,133 @@
+/*
+ * AEMIF support for DaVinci SoCs
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/time.h>
+
+#include <mach/aemif.h>
+
+/* Timing value configuration */
+
+#define TA(x)           ((x) << 2)
+#define RHOLD(x)        ((x) << 4)
+#define RSTROBE(x)      ((x) << 7)
+#define RSETUP(x)       ((x) << 13)
+#define WHOLD(x)        ((x) << 17)
+#define WSTROBE(x)      ((x) << 20)
+#define WSETUP(x)       ((x) << 26)
+
+#define TA_MAX          0x3
+#define RHOLD_MAX       0x7
+#define RSTROBE_MAX     0x3f
+#define RSETUP_MAX      0xf
+#define WHOLD_MAX       0x7
+#define WSTROBE_MAX     0x3f
+#define WSETUP_MAX      0xf
+
+#define TIMING_MASK     (TA(TA_MAX) | \
+                                RHOLD(RHOLD_MAX) | \
+                                RSTROBE(RSTROBE_MAX) |  \
+                                RSETUP(RSETUP_MAX) | \
+                                WHOLD(WHOLD_MAX) | \
+                                WSTROBE(WSTROBE_MAX) | \
+                                WSETUP(WSETUP_MAX))
+
+/*
+ * aemif_calc_rate - calculate timing data.
+ * @wanted: The cycle time needed in nanoseconds.
+ * @clk: The input clock rate in kHz.
+ * @max: The maximum divider value that can be programmed.
+ *
+ * On success, returns the calculated timing value minus 1 for easy
+ * programming into AEMIF timing registers, else negative errno.
+ */
+static int aemif_calc_rate(int wanted, unsigned long clk, int max)
+{
+        int result;
+
+        result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
+
+        pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted);
+
+        /* It is generally OK to have a more relaxed timing than requested... */
+        if (result < 0)
+                result = 0;
+
+        /* ... But configuring tighter timings is not an option. */
+        else if (result > max)
+                result = -EINVAL;
+
+        return result;
+}
+
+/**
+ * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface
+ * @t: timing values to be progammed
+ * @base: The virtual base address of the AEMIF interface
+ * @cs: chip-select to program the timing values for
+ *
+ * This function programs the given timing values (in real clock) into the
+ * AEMIF registers taking the AEMIF clock into account.
+ *
+ * This function does not use any locking while programming the AEMIF
+ * because it is expected that there is only one user of a given
+ * chip-select.
+ *
+ * Returns 0 on success, else negative errno.
+ */
+int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+                                        void __iomem *base, unsigned cs)
+{
+        unsigned set, val;
+        int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
+        unsigned offset = A1CR_OFFSET + cs * 4;
+        struct clk *aemif_clk;
+        unsigned long clkrate;
+
+        if (!t)
+                return 0;       /* Nothing to do */
+
+        aemif_clk = clk_get(NULL, "aemif");
+        if (IS_ERR(aemif_clk))
+                return PTR_ERR(aemif_clk);
+
+        clkrate = clk_get_rate(aemif_clk);
+
+        clkrate /= 1000;        /* turn clock into kHz for ease of use */
+
+        ta      = aemif_calc_rate(t->ta, clkrate, TA_MAX);
+        rhold   = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX);
+        rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX);
+        rsetup  = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX);
+        whold   = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX);
+        wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX);
+        wsetup  = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX);
+
+        if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
+                        whold < 0 || wstrobe < 0 || wsetup < 0) {
+                pr_err("%s: cannot get suitable timings\n", __func__);
+                return -EINVAL;
+        }
+
+        set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
+                WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
+
+        val = __raw_readl(base + offset);
+        val &= ~TIMING_MASK;
+        val |= set;
+        __raw_writel(val, base + offset);
+
+        return 0;
+}
+EXPORT_SYMBOL(davinci_aemif_setup_timing);
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index c3994f341e49..8bc3701aa05c 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -20,6 +20,8 @@
 #include <linux/i2c/at24.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -29,10 +31,10 @@
 #include <mach/nand.h>
 #include <mach/da8xx.h>
 #include <mach/usb.h>
+#include <mach/aemif.h>
+#include <mach/spi.h>
 
-#define DA830_EVM_PHY_MASK              0x0
-#define DA830_EVM_MDIO_FREQUENCY        2200000 /* PHY bus frequency */
-
+#define DA830_EVM_PHY_ID                ""
 /*
  * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
  */
@@ -360,6 +362,16 @@ static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = {
         .pattern        = da830_evm_nand_mirror_pattern
 };
 
+static struct davinci_aemif_timing da830_evm_nandflash_timing = {
+        .wsetup         = 24,
+        .wstrobe        = 21,
+        .whold          = 14,
+        .rsetup         = 19,
+        .rstrobe        = 50,
+        .rhold          = 0,
+        .ta             = 20,
+};
+
 static struct davinci_nand_pdata da830_evm_nand_pdata = {
         .parts          = da830_evm_nand_partitions,
         .nr_parts       = ARRAY_SIZE(da830_evm_nand_partitions),
@@ -368,6 +380,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
         .options        = NAND_USE_FLASH_BBT,
         .bbt_td         = &da830_evm_nand_bbt_main_descr,
         .bbt_md         = &da830_evm_nand_bbt_mirror_descr,
+        .timing         = &da830_evm_nandflash_timing,
 };
 
 static struct resource da830_evm_nand_resources[] = {
@@ -524,6 +537,64 @@ static struct edma_rsv_info da830_edma_rsv[] = {
         },
 };
 
+static struct mtd_partition da830evm_spiflash_part[] = {
+        [0] = {
+                .name = "DSP-UBL",
+                .offset = 0,
+                .size = SZ_8K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [1] = {
+                .name = "ARM-UBL",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_16K + SZ_8K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [2] = {
+                .name = "U-Boot",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_256K - SZ_32K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [3] = {
+                .name = "U-Boot-Environment",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_16K,
+                .mask_flags = 0,
+        },
+        [4] = {
+                .name = "Kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+                .mask_flags = 0,
+        },
+};
+
+static struct flash_platform_data da830evm_spiflash_data = {
+        .name           = "m25p80",
+        .parts          = da830evm_spiflash_part,
+        .nr_parts       = ARRAY_SIZE(da830evm_spiflash_part),
+        .type           = "w25x32",
+};
+
+static struct davinci_spi_config da830evm_spiflash_cfg = {
+        .io_type        = SPI_IO_TYPE_DMA,
+        .c2tdelay       = 8,
+        .t2cdelay       = 8,
+};
+
+static struct spi_board_info da830evm_spi_info[] = {
+        {
+                .modalias               = "m25p80",
+                .platform_data          = &da830evm_spiflash_data,
+                .controller_data        = &da830evm_spiflash_cfg,
+                .mode                   = SPI_MODE_0,
+                .max_speed_hz           = 30000000,
+                .bus_num                = 0,
+                .chip_select            = 0,
+        },
+};
+
 static __init void da830_evm_init(void)
 {
         struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -546,9 +617,8 @@ static __init void da830_evm_init(void)
 
         da830_evm_usb_init();
 
-        soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
         soc_info->emac_pdata->rmii_en = 1;
+        soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID;
 
         ret = davinci_cfg_reg_list(da830_cpgmac_pins);
         if (ret)
@@ -581,11 +651,20 @@ static __init void da830_evm_init(void)
         ret = da8xx_register_rtc();
         if (ret)
                 pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
+
+        ret = da8xx_register_spi(0, da830evm_spi_info,
+                                 ARRAY_SIZE(da830evm_spi_info));
+        if (ret)
+                pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
+                           ret);
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
 static int __init da830_evm_console_init(void)
 {
+        if (!machine_is_davinci_da830_evm())
+                return 0;
+
         return add_preferred_console("ttyS", 2, "115200");
 }
 console_initcall(da830_evm_console_init);
@@ -596,9 +675,7 @@ static void __init da830_evm_map_io(void)
         da830_init();
 }
 
-MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
-        .phys_io        = IO_PHYS,
-        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
         .boot_params    = (DA8XX_DDR_BASE + 0x100),
         .map_io         = da830_evm_map_io,
         .init_irq       = cp_intc_init,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index fdc2cc500fc6..a7b41bf505f1 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -17,8 +17,10 @@
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/input.h>
 #include <linux/mfd/tps6507x.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -26,8 +28,9 @@
 #include <linux/mtd/physmap.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/tps6507x.h>
-#include <linux/mfd/tps6507x.h>
 #include <linux/input/tps6507x-ts.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -36,10 +39,10 @@
 #include <mach/da8xx.h>
 #include <mach/nand.h>
 #include <mach/mux.h>
+#include <mach/aemif.h>
+#include <mach/spi.h>
 
-#define DA850_EVM_PHY_MASK              0x1
-#define DA850_EVM_MDIO_FREQUENCY        2200000 /* PHY bus frequency */
-
+#define DA850_EVM_PHY_ID                "0:00"
 #define DA850_LCD_PWR_PIN               GPIO_TO_PIN(2, 8)
 #define DA850_LCD_BL_PIN                GPIO_TO_PIN(2, 15)
 
@@ -48,6 +51,70 @@
 
 #define DA850_MII_MDIO_CLKEN_PIN        GPIO_TO_PIN(2, 6)
 
+static struct mtd_partition da850evm_spiflash_part[] = {
+        [0] = {
+                .name = "UBL",
+                .offset = 0,
+                .size = SZ_64K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [1] = {
+                .name = "U-Boot",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_512K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [2] = {
+                .name = "U-Boot-Env",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_64K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [3] = {
+                .name = "Kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_2M + SZ_512K,
+                .mask_flags = 0,
+        },
+        [4] = {
+                .name = "Filesystem",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_4M,
+                .mask_flags = 0,
+        },
+        [5] = {
+                .name = "MAC-Address",
+                .offset = SZ_8M - SZ_64K,
+                .size = SZ_64K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+};
+
+static struct flash_platform_data da850evm_spiflash_data = {
+        .name           = "m25p80",
+        .parts          = da850evm_spiflash_part,
+        .nr_parts       = ARRAY_SIZE(da850evm_spiflash_part),
+        .type           = "m25p64",
+};
+
+static struct davinci_spi_config da850evm_spiflash_cfg = {
+        .io_type        = SPI_IO_TYPE_DMA,
+        .c2tdelay       = 8,
+        .t2cdelay       = 8,
+};
+
+static struct spi_board_info da850evm_spi_info[] = {
+        {
+                .modalias               = "m25p80",
+                .platform_data          = &da850evm_spiflash_data,
+                .controller_data        = &da850evm_spiflash_cfg,
+                .mode                   = SPI_MODE_0,
+                .max_speed_hz           = 30000000,
+                .bus_num                = 1,
+                .chip_select            = 0,
+        },
+};
+
 static struct mtd_partition da850_evm_norflash_partition[] = {
         {
                 .name           = "bootloaders + env",
@@ -110,7 +177,7 @@ static struct platform_device da850_pm_device = {
  * to boot, using TI's tools to install the secondary boot loader
  * (UBL) and U-Boot.
  */
-struct mtd_partition da850_evm_nandflash_partition[] = {
+static struct mtd_partition da850_evm_nandflash_partition[] = {
         {
                 .name           = "u-boot env",
                 .offset         = 0,
@@ -143,12 +210,23 @@ struct mtd_partition da850_evm_nandflash_partition[] = {
         },
 };
 
+static struct davinci_aemif_timing da850_evm_nandflash_timing = {
+        .wsetup         = 24,
+        .wstrobe        = 21,
+        .whold          = 14,
+        .rsetup         = 19,
+        .rstrobe        = 50,
+        .rhold          = 0,
+        .ta             = 20,
+};
+
 static struct davinci_nand_pdata da850_evm_nandflash_data = {
         .parts          = da850_evm_nandflash_partition,
         .nr_parts       = ARRAY_SIZE(da850_evm_nandflash_partition),
         .ecc_mode       = NAND_ECC_HW,
         .ecc_bits       = 4,
         .options        = NAND_USE_FLASH_BBT,
+        .timing         = &da850_evm_nandflash_timing,
 };
 
 static struct resource da850_evm_nandflash_resource[] = {
@@ -196,7 +274,29 @@ static void __init da850_evm_init_nor(void)
         iounmap(aemif_addr);
 }
 
-static u32 ui_card_detected;
+static const short da850_evm_nand_pins[] = {
+        DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
+        DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
+        DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
+        DA850_NEMA_WE, DA850_NEMA_OE,
+        -1
+};
+
+static const short da850_evm_nor_pins[] = {
+        DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
+        DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
+        DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
+        DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
+        DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
+        DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
+        DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
+        DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
+        DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
+        DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
+        DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
+        DA850_EMA_A_22, DA850_EMA_A_23,
+        -1
+};
 
 #if defined(CONFIG_MMC_DAVINCI) || \
     defined(CONFIG_MMC_DAVINCI_MODULE)
@@ -205,17 +305,17 @@ static u32 ui_card_detected;
 #define HAS_MMC 0
 #endif
 
-static __init void da850_evm_setup_nor_nand(void)
+static inline void da850_evm_setup_nor_nand(void)
 {
         int ret = 0;
 
-        if (ui_card_detected & !HAS_MMC) {
-                ret = davinci_cfg_reg_list(da850_nand_pins);
+        if (!HAS_MMC) {
+                ret = davinci_cfg_reg_list(da850_evm_nand_pins);
                 if (ret)
                         pr_warning("da850_evm_init: nand mux setup failed: "
                                         "%d\n", ret);
 
-                ret = davinci_cfg_reg_list(da850_nor_pins);
+                ret = davinci_cfg_reg_list(da850_evm_nor_pins);
                 if (ret)
                         pr_warning("da850_evm_init: nor mux setup failed: %d\n",
                                 ret);
@@ -233,34 +333,115 @@ static inline void da850_evm_setup_emac_rmii(int rmii_sel)
         struct davinci_soc_info *soc_info = &davinci_soc_info;
 
         soc_info->emac_pdata->rmii_en = 1;
-        gpio_set_value(rmii_sel, 0);
+        gpio_set_value_cansleep(rmii_sel, 0);
 }
 #else
 static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
 #endif
 
+
+#define DA850_KEYS_DEBOUNCE_MS  10
+/*
+ * At 200ms polling interval it is possible to miss an
+ * event by tapping very lightly on the push button but most
+ * pushes do result in an event; longer intervals require the
+ * user to hold the button whereas shorter intervals require
+ * more CPU time for polling.
+ */
+#define DA850_GPIO_KEYS_POLL_MS 200
+
+enum da850_evm_ui_exp_pins {
+        DA850_EVM_UI_EXP_SEL_C = 5,
+        DA850_EVM_UI_EXP_SEL_B,
+        DA850_EVM_UI_EXP_SEL_A,
+        DA850_EVM_UI_EXP_PB8,
+        DA850_EVM_UI_EXP_PB7,
+        DA850_EVM_UI_EXP_PB6,
+        DA850_EVM_UI_EXP_PB5,
+        DA850_EVM_UI_EXP_PB4,
+        DA850_EVM_UI_EXP_PB3,
+        DA850_EVM_UI_EXP_PB2,
+        DA850_EVM_UI_EXP_PB1,
+};
+
+static const char const *da850_evm_ui_exp[] = {
+        [DA850_EVM_UI_EXP_SEL_C]        = "sel_c",
+        [DA850_EVM_UI_EXP_SEL_B]        = "sel_b",
+        [DA850_EVM_UI_EXP_SEL_A]        = "sel_a",
+        [DA850_EVM_UI_EXP_PB8]          = "pb8",
+        [DA850_EVM_UI_EXP_PB7]          = "pb7",
+        [DA850_EVM_UI_EXP_PB6]          = "pb6",
+        [DA850_EVM_UI_EXP_PB5]          = "pb5",
+        [DA850_EVM_UI_EXP_PB4]          = "pb4",
+        [DA850_EVM_UI_EXP_PB3]          = "pb3",
+        [DA850_EVM_UI_EXP_PB2]          = "pb2",
+        [DA850_EVM_UI_EXP_PB1]          = "pb1",
+};
+
+#define DA850_N_UI_PB           8
+
+static struct gpio_keys_button da850_evm_ui_keys[] = {
+        [0 ... DA850_N_UI_PB - 1] = {
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = -1, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+                .desc                   = NULL, /* assigned at runtime */
+        },
+};
+
+static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
+        .buttons = da850_evm_ui_keys,
+        .nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
+        .poll_interval = DA850_GPIO_KEYS_POLL_MS,
+};
+
+static struct platform_device da850_evm_ui_keys_device = {
+        .name = "gpio-keys-polled",
+        .id = 0,
+        .dev = {
+                .platform_data = &da850_evm_ui_keys_pdata
+        },
+};
+
+static void da850_evm_ui_keys_init(unsigned gpio)
+{
+        int i;
+        struct gpio_keys_button *button;
+
+        for (i = 0; i < DA850_N_UI_PB; i++) {
+                button = &da850_evm_ui_keys[i];
+                button->code = KEY_F8 - i;
+                button->desc = (char *)
+                                da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
+                button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
+        }
+}
+
 static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
                                                 unsigned ngpio, void *c)
 {
         int sel_a, sel_b, sel_c, ret;
 
-        sel_a = gpio + 7;
-        sel_b = gpio + 6;
-        sel_c = gpio + 5;
+        sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
+        sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
+        sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
 
-        ret = gpio_request(sel_a, "sel_a");
+        ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_a);
                 goto exp_setup_sela_fail;
         }
 
-        ret = gpio_request(sel_b, "sel_b");
+        ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_b);
                 goto exp_setup_selb_fail;
         }
 
-        ret = gpio_request(sel_c, "sel_c");
+        ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_c);
                 goto exp_setup_selc_fail;
@@ -271,7 +452,13 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
         gpio_direction_output(sel_b, 1);
         gpio_direction_output(sel_c, 1);
 
-        ui_card_detected = 1;
+        da850_evm_ui_keys_init(gpio);
+        ret = platform_device_register(&da850_evm_ui_keys_device);
+        if (ret) {
+                pr_warning("Could not register UI GPIO expander push-buttons");
+                goto exp_setup_keys_fail;
+        }
+
         pr_info("DA850/OMAP-L138 EVM UI card detected\n");
 
         da850_evm_setup_nor_nand();
@@ -280,6 +467,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
 
         return 0;
 
+exp_setup_keys_fail:
+        gpio_free(sel_c);
 exp_setup_selc_fail:
         gpio_free(sel_b);
 exp_setup_selb_fail:
@@ -291,14 +480,192 @@ exp_setup_sela_fail:
 static int da850_evm_ui_expander_teardown(struct i2c_client *client,
                                         unsigned gpio, unsigned ngpio, void *c)
 {
+        platform_device_unregister(&da850_evm_ui_keys_device);
+
         /* deselect all functionalities */
-        gpio_set_value(gpio + 5, 1);
-        gpio_set_value(gpio + 6, 1);
-        gpio_set_value(gpio + 7, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
 
-        gpio_free(gpio + 5);
-        gpio_free(gpio + 6);
-        gpio_free(gpio + 7);
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
+
+        return 0;
+}
+
+/* assign the baseboard expander's GPIOs after the UI board's */
+#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
+#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
+
+enum da850_evm_bb_exp_pins {
+        DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
+        DA850_EVM_BB_EXP_SW_RST,
+        DA850_EVM_BB_EXP_TP_23,
+        DA850_EVM_BB_EXP_TP_22,
+        DA850_EVM_BB_EXP_TP_21,
+        DA850_EVM_BB_EXP_USER_PB1,
+        DA850_EVM_BB_EXP_USER_LED2,
+        DA850_EVM_BB_EXP_USER_LED1,
+        DA850_EVM_BB_EXP_USER_SW1,
+        DA850_EVM_BB_EXP_USER_SW2,
+        DA850_EVM_BB_EXP_USER_SW3,
+        DA850_EVM_BB_EXP_USER_SW4,
+        DA850_EVM_BB_EXP_USER_SW5,
+        DA850_EVM_BB_EXP_USER_SW6,
+        DA850_EVM_BB_EXP_USER_SW7,
+        DA850_EVM_BB_EXP_USER_SW8
+};
+
+static const char const *da850_evm_bb_exp[] = {
+        [DA850_EVM_BB_EXP_DEEP_SLEEP_EN]        = "deep_sleep_en",
+        [DA850_EVM_BB_EXP_SW_RST]               = "sw_rst",
+        [DA850_EVM_BB_EXP_TP_23]                = "tp_23",
+        [DA850_EVM_BB_EXP_TP_22]                = "tp_22",
+        [DA850_EVM_BB_EXP_TP_21]                = "tp_21",
+        [DA850_EVM_BB_EXP_USER_PB1]             = "user_pb1",
+        [DA850_EVM_BB_EXP_USER_LED2]            = "user_led2",
+        [DA850_EVM_BB_EXP_USER_LED1]            = "user_led1",
+        [DA850_EVM_BB_EXP_USER_SW1]             = "user_sw1",
+        [DA850_EVM_BB_EXP_USER_SW2]             = "user_sw2",
+        [DA850_EVM_BB_EXP_USER_SW3]             = "user_sw3",
+        [DA850_EVM_BB_EXP_USER_SW4]             = "user_sw4",
+        [DA850_EVM_BB_EXP_USER_SW5]             = "user_sw5",
+        [DA850_EVM_BB_EXP_USER_SW6]             = "user_sw6",
+        [DA850_EVM_BB_EXP_USER_SW7]             = "user_sw7",
+        [DA850_EVM_BB_EXP_USER_SW8]             = "user_sw8",
+};
+
+#define DA850_N_BB_USER_SW      8
+
+static struct gpio_keys_button da850_evm_bb_keys[] = {
+        [0] = {
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = KEY_PROG1,
+                .desc                   = NULL, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+        },
+        [1 ... DA850_N_BB_USER_SW] = {
+                .type                   = EV_SW,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = -1, /* assigned at runtime */
+                .desc                   = NULL, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+        },
+};
+
+static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
+        .buttons = da850_evm_bb_keys,
+        .nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
+        .poll_interval = DA850_GPIO_KEYS_POLL_MS,
+};
+
+static struct platform_device da850_evm_bb_keys_device = {
+        .name = "gpio-keys-polled",
+        .id = 1,
+        .dev = {
+                .platform_data = &da850_evm_bb_keys_pdata
+        },
+};
+
+static void da850_evm_bb_keys_init(unsigned gpio)
+{
+        int i;
+        struct gpio_keys_button *button;
+
+        button = &da850_evm_bb_keys[0];
+        button->desc = (char *)
+                da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
+        button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
+
+        for (i = 0; i < DA850_N_BB_USER_SW; i++) {
+                button = &da850_evm_bb_keys[i + 1];
+                button->code = SW_LID + i;
+                button->desc = (char *)
+                                da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
+                button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
+        }
+}
+
+#define DA850_N_BB_USER_LED     2
+
+static struct gpio_led da850_evm_bb_leds[] = {
+        [0 ... DA850_N_BB_USER_LED - 1] = {
+                .active_low = 1,
+                .gpio = -1, /* assigned at runtime */
+                .name = NULL, /* assigned at runtime */
+        },
+};
+
+static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
+        .leds = da850_evm_bb_leds,
+        .num_leds = ARRAY_SIZE(da850_evm_bb_leds),
+};
+
+static struct platform_device da850_evm_bb_leds_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev = {
+                .platform_data = &da850_evm_bb_leds_pdata
+        }
+};
+
+static void da850_evm_bb_leds_init(unsigned gpio)
+{
+        int i;
+        struct gpio_led *led;
+
+        for (i = 0; i < DA850_N_BB_USER_LED; i++) {
+                led = &da850_evm_bb_leds[i];
+
+                led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i;
+                led->name =
+                        da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i];
+        }
+}
+
+static int da850_evm_bb_expander_setup(struct i2c_client *client,
+                                                unsigned gpio, unsigned ngpio,
+                                                void *c)
+{
+        int ret;
+
+        /*
+         * Register the switches and pushbutton on the baseboard as a gpio-keys
+         * device.
+         */
+        da850_evm_bb_keys_init(gpio);
+        ret = platform_device_register(&da850_evm_bb_keys_device);
+        if (ret) {
+                pr_warning("Could not register baseboard GPIO expander keys");
+                goto io_exp_setup_sw_fail;
+        }
+
+        da850_evm_bb_leds_init(gpio);
+        ret = platform_device_register(&da850_evm_bb_leds_device);
+        if (ret) {
+                pr_warning("Could not register baseboard GPIO expander LEDS");
+                goto io_exp_setup_leds_fail;
+        }
+
+        return 0;
+
+io_exp_setup_leds_fail:
+        platform_device_unregister(&da850_evm_bb_keys_device);
+io_exp_setup_sw_fail:
+        return ret;
+}
+
+static int da850_evm_bb_expander_teardown(struct i2c_client *client,
+                                        unsigned gpio, unsigned ngpio, void *c)
+{
+        platform_device_unregister(&da850_evm_bb_leds_device);
+        platform_device_unregister(&da850_evm_bb_keys_device);
 
         return 0;
 }
@@ -307,6 +674,14 @@ static struct pca953x_platform_data da850_evm_ui_expander_info = {
         .gpio_base      = DAVINCI_N_GPIO,
         .setup          = da850_evm_ui_expander_setup,
         .teardown       = da850_evm_ui_expander_teardown,
+        .names          = da850_evm_ui_exp,
+};
+
+static struct pca953x_platform_data da850_evm_bb_expander_info = {
+        .gpio_base      = DA850_BB_EXPANDER_GPIO_BASE,
+        .setup          = da850_evm_bb_expander_setup,
+        .teardown       = da850_evm_bb_expander_teardown,
+        .names          = da850_evm_bb_exp,
 };
 
 static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
@@ -317,6 +692,10 @@ static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
                 I2C_BOARD_INFO("tca6416", 0x20),
                 .platform_data = &da850_evm_ui_expander_info,
         },
+        {
+                I2C_BOARD_INFO("tca6416", 0x21),
+                .platform_data = &da850_evm_bb_expander_info,
+        },
 };
 
 static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
@@ -349,6 +728,13 @@ static struct snd_platform_data da850_evm_snd_data = {
         .rxnumevt       = 1,
 };
 
+static const short da850_evm_mcasp_pins[] __initconst = {
+        DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
+        DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
+        DA850_AXR_11, DA850_AXR_12,
+        -1
+};
+
 static int da850_evm_mmc_get_ro(int index)
 {
         return gpio_get_value(DA850_MMCSD_WP_PIN);
@@ -368,6 +754,13 @@ static struct davinci_mmc_config da850_mmc_config = {
         .version        = MMC_CTLR_VERSION_2,
 };
 
+static const short da850_evm_mmcsd0_pins[] __initconst = {
+        DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
+        DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
+        DA850_GPIO4_0, DA850_GPIO4_1,
+        -1
+};
+
 static void da850_panel_power_ctrl(int val)
 {
         /* lcd backlight */
@@ -406,7 +799,7 @@ static int da850_lcd_hw_init(void)
 /* TPS65070 voltage regulator support */
 
 /* 3.3V */
-struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
+static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
         {
                 .supply = "usb0_vdda33",
         },
@@ -416,7 +809,7 @@ struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
 };
 
 /* 3.3V or 1.8V */
-struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
+static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
         {
                 .supply = "dvdd3318_a",
         },
@@ -429,14 +822,14 @@ struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
 };
 
 /* 1.2V */
-struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
+static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
         {
                 .supply = "cvdd",
         },
 };
 
 /* 1.8V LDO */
-struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
+static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
         {
                 .supply = "sata_vddr",
         },
@@ -452,7 +845,7 @@ struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
 };
 
 /* 1.2V LDO */
-struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
+static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
         {
                 .supply = "sata_vdd",
         },
@@ -475,7 +868,7 @@ static struct tps6507x_reg_platform_data tps6507x_platform_data = {
         .defdcdc_default = true,
 };
 
-struct regulator_init_data tps65070_regulator_data[] = {
+static struct regulator_init_data tps65070_regulator_data[] = {
         /* dcdc1 */
         {
                 .constraints = {
@@ -507,7 +900,7 @@ struct regulator_init_data tps65070_regulator_data[] = {
         {
                 .constraints = {
                         .min_uV = 950000,
-                        .max_uV = 1320000,
+                        .max_uV = 1350000,
                         .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
                                 REGULATOR_CHANGE_STATUS),
                         .boot_on = 1,
@@ -558,7 +951,7 @@ static struct tps6507x_board tps_board = {
         .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
 };
 
-static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
+static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
         {
                 I2C_BOARD_INFO("tps6507x", 0x48),
                 .platform_data = &tps_board,
@@ -567,8 +960,8 @@ static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
 
 static int __init pmic_tps65070_init(void)
 {
-        return i2c_register_board_info(1, da850evm_tps65070_info,
-                                        ARRAY_SIZE(da850evm_tps65070_info));
+        return i2c_register_board_info(1, da850_evm_tps65070_info,
+                                        ARRAY_SIZE(da850_evm_tps65070_info));
 }
 
 static const short da850_evm_lcdc_pins[] = {
@@ -576,6 +969,23 @@ static const short da850_evm_lcdc_pins[] = {
         -1
 };
 
+static const short da850_evm_mii_pins[] = {
+        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
+        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
+        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
+        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+static const short da850_evm_rmii_pins[] = {
+        DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
+        DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
+        DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
 static int __init da850_evm_config_emac(void)
 {
         void __iomem *cfg_chip3_base;
@@ -593,12 +1003,12 @@ static int __init da850_evm_config_emac(void)
 
         if (rmii_en) {
                 val |= BIT(8);
-                ret = davinci_cfg_reg_list(da850_rmii_pins);
+                ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
                 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
                                                         " functional\n");
         } else {
                 val &= ~BIT(8);
-                ret = davinci_cfg_reg_list(da850_cpgmac_pins);
+                ret = davinci_cfg_reg_list(da850_evm_mii_pins);
                 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
                                                         " functional\n");
         }
@@ -625,8 +1035,7 @@ static int __init da850_evm_config_emac(void)
         /* Enable/Disable MII MDIO clock */
         gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
 
-        soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
+        soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
 
         ret = da8xx_register_emac();
         if (ret)
@@ -687,6 +1096,27 @@ static struct edma_rsv_info *da850_edma_rsv[2] = {
         &da850_edma_cc1_rsv,
 };
 
+#ifdef CONFIG_CPU_FREQ
+static __init int da850_evm_init_cpufreq(void)
+{
+        switch (system_rev & 0xF) {
+        case 3:
+                da850_max_speed = 456000;
+                break;
+        case 2:
+                da850_max_speed = 408000;
+                break;
+        case 1:
+                da850_max_speed = 372000;
+                break;
+        }
+
+        return da850_register_cpufreq("pll0_sysclk3");
+}
+#else
+static __init int da850_evm_init_cpufreq(void) { return 0; }
+#endif
+
 static __init void da850_evm_init(void)
 {
         int ret;
@@ -718,7 +1148,7 @@ static __init void da850_evm_init(void)
                                 ret);
 
         if (HAS_MMC) {
-                ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
+                ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
                 if (ret)
                         pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
                                         " %d\n", ret);
@@ -754,7 +1184,7 @@ static __init void da850_evm_init(void)
         __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
         __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
 
-        ret = davinci_cfg_reg_list(da850_mcasp_pins);
+        ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
         if (ret)
                 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
                                 ret);
@@ -787,7 +1217,7 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
 
-        ret = da850_register_cpufreq();
+        ret = da850_evm_init_cpufreq();
         if (ret)
                 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
                                 ret);
@@ -801,11 +1231,20 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warning("da850_evm_init: suspend registration failed: %d\n",
                                 ret);
+
+        ret = da8xx_register_spi(1, da850evm_spi_info,
+                                 ARRAY_SIZE(da850evm_spi_info));
+        if (ret)
+                pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
+                                ret);
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
 static int __init da850_evm_console_init(void)
 {
+        if (!machine_is_davinci_da850_evm())
+                return 0;
+
         return add_preferred_console("ttyS", 2, "115200");
 }
 console_initcall(da850_evm_console_init);
@@ -816,9 +1255,7 @@ static void __init da850_evm_map_io(void)
         da850_init();
 }
 
-MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
-        .phys_io        = IO_PHYS,
-        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
         .boot_params    = (DA8XX_DDR_BASE + 0x100),
         .map_io         = da850_evm_map_io,
         .init_irq       = cp_intc_init,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index a3191015efee..6e7cad13352c 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -351,8 +351,6 @@ static __init void dm355_evm_init(void)
 }
 
 MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (0x80000100),
         .map_io       = dm355_evm_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index f1d8132cf0c3..543f9911b281 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -270,8 +270,6 @@ static __init void dm355_leopard_init(void)
 }
 
 MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (0x80000100),
         .map_io       = dm355_leopard_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 84acef1d0b3d..09a87e61ffcf 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -54,9 +54,7 @@ static inline int have_tvp7002(void)
         return 0;
 }
 
-#define DM365_EVM_PHY_MASK              (0x2)
-#define DM365_EVM_MDIO_FREQUENCY        (2200000) /* PHY bus frequency */
-
+#define DM365_EVM_PHY_ID                "0:01"
 /*
  * A MAX-II CPLD is used for various board control functions.
  */
@@ -175,7 +173,9 @@ static struct at24_platform_data eeprom_info = {
         .context        = (void *)0x7f00,
 };
 
-static struct snd_platform_data dm365_evm_snd_data;
+static struct snd_platform_data dm365_evm_snd_data = {
+        .asp_chan_q = EVENTQ_3,
+};
 
 static struct i2c_board_info i2c_info[] = {
         {
@@ -520,7 +520,7 @@ fail:
          */
         if (have_imager()) {
                 label = "HD imager";
-                mux |= 1;
+                mux |= 2;
 
                 /* externally mux MMC1/ENET/AIC33 to imager */
                 mux |= BIT(6) | BIT(5) | BIT(3);
@@ -533,15 +533,14 @@ fail:
 
                 /* ... and ENET ... */
                 dm365evm_emac_configure();
-                soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
-                soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
+                soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
                 resets &= ~BIT(3);
 
                 /* ... and AIC33 */
                 resets &= ~BIT(1);
 
                 if (have_tvp7002()) {
-                        mux |= 2;
+                        mux |= 1;
                         resets &= ~BIT(2);
                         label = "tvp7002 HD";
                 } else {
@@ -613,8 +612,6 @@ static __init void dm365_evm_init(void)
 }
 
 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
-        .phys_io        = IO_PHYS,
-        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params    = (0x80000100),
         .map_io         = dm365_evm_map_io,
         .init_irq       = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 34c8b418cd72..556bbd468db3 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -37,10 +37,9 @@
 #include <mach/nand.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
+#include <mach/aemif.h>
 
-#define DM644X_EVM_PHY_MASK             (0x2)
-#define DM644X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
-
+#define DM644X_EVM_PHY_ID               "0:01"
 #define LXT971_PHY_ID   (0x001378e2)
 #define LXT971_PHY_MASK (0xfffffff0)
 
@@ -137,11 +136,22 @@ static struct mtd_partition davinci_evm_nandflash_partition[] = {
          */
 };
 
+static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
+        .wsetup         = 20,
+        .wstrobe        = 40,
+        .whold          = 20,
+        .rsetup         = 10,
+        .rstrobe        = 40,
+        .rhold          = 10,
+        .ta             = 40,
+};
+
 static struct davinci_nand_pdata davinci_evm_nandflash_data = {
         .parts          = davinci_evm_nandflash_partition,
         .nr_parts       = ARRAY_SIZE(davinci_evm_nandflash_partition),
         .ecc_mode       = NAND_ECC_HW,
         .options        = NAND_USE_FLASH_BBT,
+        .timing         = &davinci_evm_nandflash_timing,
 };
 
 static struct resource davinci_evm_nandflash_resource[] = {
@@ -430,11 +440,6 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
         gpio_request(gpio + 7, "nCF_SEL");
         gpio_direction_output(gpio + 7, 1);
 
-        /* irlml6401 switches over 1A, in under 8 msec;
-         * now it can be managed by nDRV_VBUS ...
-         */
-        davinci_setup_usb(1000, 8);
-
         return 0;
 }
 
@@ -695,9 +700,10 @@ static __init void davinci_evm_init(void)
         davinci_serial_init(&uart_config);
         dm644x_init_asp(&dm644x_evm_snd_data);
 
-        soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
+        /* irlml6401 switches over 1A, in under 8 msec */
+        davinci_setup_usb(1000, 8);
 
+        soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
         /* Register the fixup for PHY on DaVinci */
         phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
                                         davinci_phy_fixup);
@@ -706,8 +712,6 @@ static __init void davinci_evm_init(void)
 
 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
         /* Maintainer: MontaVista Software <source@mvista.com> */
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (DAVINCI_DDR_BASE + 0x100),
         .map_io       = davinci_evm_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 4502f346b2b0..f6ac9ba74878 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -42,6 +42,7 @@
 #include <mach/nand.h>
 #include <mach/clock.h>
 #include <mach/cdce949.h>
+#include <mach/aemif.h>
 
 #include "clock.h"
 
@@ -71,6 +72,16 @@ static struct mtd_partition davinci_nand_partitions[] = {
         }
 };
 
+static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
+        .wsetup         = 29,
+        .wstrobe        = 24,
+        .whold          = 14,
+        .rsetup         = 19,
+        .rstrobe        = 33,
+        .rhold          = 0,
+        .ta             = 29,
+};
+
 static struct davinci_nand_pdata davinci_nand_data = {
         .mask_cle               = 0x80000,
         .mask_ale               = 0x40000,
@@ -718,9 +729,7 @@ static struct davinci_uart_config uart_config __initdata = {
         .enabled_uarts = (1 << 0),
 };
 
-#define DM646X_EVM_PHY_MASK             (0x2)
-#define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
-
+#define DM646X_EVM_PHY_ID               "0:01"
 /*
  * The following EDMA channels/slots are not being used by drivers (for
  * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
@@ -763,6 +772,9 @@ static __init void evm_init(void)
         dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
         dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
 
+        if (machine_is_davinci_dm6467tevm())
+                davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
+
         platform_device_register(&davinci_nand_device);
 
         dm646x_init_edma(dm646x_edma_rsv);
@@ -770,8 +782,7 @@ static __init void evm_init(void)
         if (HAS_ATA)
                 davinci_init_ide();
 
-        soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
+        soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
 }
 
 #define DM646X_EVM_REF_FREQ             27000000
@@ -786,8 +797,6 @@ void __init dm646x_board_setup_refclk(struct clk *clk)
 }
 
 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (0x80000100),
         .map_io       = davinci_map_io,
         .init_irq     = davinci_irq_init,
@@ -796,8 +805,6 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
 MACHINE_END
 
 MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (0x80000100),
         .map_io       = davinci_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
new file mode 100644
index 000000000000..606a6f27ed6c
--- /dev/null
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -0,0 +1,573 @@
+/*
+ * Critical Link MityOMAP-L138 SoM
+ *
+ * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of
+ * any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/regulator/machine.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/etherdevice.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/common.h>
+#include <mach/cp_intc.h>
+#include <mach/da8xx.h>
+#include <mach/nand.h>
+#include <mach/mux.h>
+#include <mach/spi.h>
+
+#define MITYOMAPL138_PHY_ID             ""
+
+#define FACTORY_CONFIG_MAGIC    0x012C0138
+#define FACTORY_CONFIG_VERSION  0x00010001
+
+/* Data Held in On-Board I2C device */
+struct factory_config {
+        u32     magic;
+        u32     version;
+        u8      mac[6];
+        u32     fpga_type;
+        u32     spare;
+        u32     serialnumber;
+        char    partnum[32];
+};
+
+static struct factory_config factory_config;
+
+struct part_no_info {
+        const char      *part_no;       /* part number string of interest */
+        int             max_freq;       /* khz */
+};
+
+static struct part_no_info mityomapl138_pn_info[] = {
+        {
+                .part_no        = "L138-C",
+                .max_freq       = 300000,
+        },
+        {
+                .part_no        = "L138-D",
+                .max_freq       = 375000,
+        },
+        {
+                .part_no        = "L138-F",
+                .max_freq       = 456000,
+        },
+        {
+                .part_no        = "1808-C",
+                .max_freq       = 300000,
+        },
+        {
+                .part_no        = "1808-D",
+                .max_freq       = 375000,
+        },
+        {
+                .part_no        = "1808-F",
+                .max_freq       = 456000,
+        },
+        {
+                .part_no        = "1810-D",
+                .max_freq       = 375000,
+        },
+};
+
+#ifdef CONFIG_CPU_FREQ
+static void mityomapl138_cpufreq_init(const char *partnum)
+{
+        int i, ret;
+
+        for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
+                /*
+                 * the part number has additional characters beyond what is
+                 * stored in the table.  This information is not needed for
+                 * determining the speed grade, and would require several
+                 * more table entries.  Only check the first N characters
+                 * for a match.
+                 */
+                if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
+                             strlen(mityomapl138_pn_info[i].part_no))) {
+                        da850_max_speed = mityomapl138_pn_info[i].max_freq;
+                        break;
+                }
+        }
+
+        ret = da850_register_cpufreq("pll0_sysclk3");
+        if (ret)
+                pr_warning("cpufreq registration failed: %d\n", ret);
+}
+#else
+static void mityomapl138_cpufreq_init(const char *partnum) { }
+#endif
+
+static void read_factory_config(struct memory_accessor *a, void *context)
+{
+        int ret;
+        const char *partnum = NULL;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
+        if (ret != sizeof(struct factory_config)) {
+                pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
+                                ret);
+                goto bad_config;
+        }
+
+        if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
+                pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
+                                factory_config.magic);
+                goto bad_config;
+        }
+
+        if (factory_config.version != FACTORY_CONFIG_VERSION) {
+                pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
+                                factory_config.version);
+                goto bad_config;
+        }
+
+        pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
+        if (is_valid_ether_addr(factory_config.mac))
+                memcpy(soc_info->emac_pdata->mac_addr,
+                        factory_config.mac, ETH_ALEN);
+        else
+                pr_warning("MityOMAPL138: Invalid MAC found "
+                                "in factory config block\n");
+
+        partnum = factory_config.partnum;
+        pr_info("MityOMAPL138: Part Number = %s\n", partnum);
+
+bad_config:
+        /* default maximum speed is valid for all platforms */
+        mityomapl138_cpufreq_init(partnum);
+}
+
+static struct at24_platform_data mityomapl138_fd_chip = {
+        .byte_len       = 256,
+        .page_size      = 8,
+        .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
+        .setup          = read_factory_config,
+        .context        = NULL,
+};
+
+static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
+        .bus_freq       = 100,  /* kHz */
+        .bus_delay      = 0,    /* usec */
+};
+
+/* TPS65023 voltage regulator support */
+/* 1.2V Core */
+static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
+        {
+                .supply = "cvdd",
+        },
+};
+
+/* 1.8V */
+static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
+        {
+                .supply = "usb0_vdda18",
+        },
+        {
+                .supply = "usb1_vdda18",
+        },
+        {
+                .supply = "ddr_dvdd18",
+        },
+        {
+                .supply = "sata_vddr",
+        },
+};
+
+/* 1.2V */
+static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
+        {
+                .supply = "sata_vdd",
+        },
+        {
+                .supply = "usb_cvdd",
+        },
+        {
+                .supply = "pll0_vdda",
+        },
+        {
+                .supply = "pll1_vdda",
+        },
+};
+
+/* 1.8V Aux LDO, not used */
+static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
+        {
+                .supply = "1.8v_aux",
+        },
+};
+
+/* FPGA VCC Aux (2.5 or 3.3) LDO */
+static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
+        {
+                .supply = "vccaux",
+        },
+};
+
+static struct regulator_init_data tps65023_regulator_data[] = {
+        /* dcdc1 */
+        {
+                .constraints = {
+                        .min_uV = 1150000,
+                        .max_uV = 1350000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
+                .consumer_supplies = tps65023_dcdc1_consumers,
+        },
+        /* dcdc2 */
+        {
+                .constraints = {
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
+                .consumer_supplies = tps65023_dcdc2_consumers,
+        },
+        /* dcdc3 */
+        {
+                .constraints = {
+                        .min_uV = 1200000,
+                        .max_uV = 1200000,
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
+                .consumer_supplies = tps65023_dcdc3_consumers,
+        },
+        /* ldo1 */
+        {
+                .constraints = {
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
+                .consumer_supplies = tps65023_ldo1_consumers,
+        },
+        /* ldo2 */
+        {
+                .constraints = {
+                        .min_uV = 2500000,
+                        .max_uV = 3300000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
+                .consumer_supplies = tps65023_ldo2_consumers,
+        },
+};
+
+static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
+        {
+                I2C_BOARD_INFO("tps65023", 0x48),
+                .platform_data = &tps65023_regulator_data[0],
+        },
+        {
+                I2C_BOARD_INFO("24c02", 0x50),
+                .platform_data = &mityomapl138_fd_chip,
+        },
+};
+
+static int __init pmic_tps65023_init(void)
+{
+        return i2c_register_board_info(1, mityomap_tps65023_info,
+                                        ARRAY_SIZE(mityomap_tps65023_info));
+}
+
+/*
+ * SPI Devices:
+ *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
+ */
+static struct mtd_partition spi_flash_partitions[] = {
+        [0] = {
+                .name           = "ubl",
+                .offset         = 0,
+                .size           = SZ_64K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        [1] = {
+                .name           = "u-boot",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_512K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        [2] = {
+                .name           = "u-boot-env",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_64K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        [3] = {
+                .name           = "periph-config",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_64K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        [4] = {
+                .name           = "reserved",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_256K + SZ_64K,
+        },
+        [5] = {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_2M + SZ_1M,
+        },
+        [6] = {
+                .name           = "fpga",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_2M,
+        },
+        [7] = {
+                .name           = "spare",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct flash_platform_data mityomapl138_spi_flash_data = {
+        .name           = "m25p80",
+        .parts          = spi_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
+        .type           = "m24p64",
+};
+
+static struct davinci_spi_config spi_eprom_config = {
+        .io_type        = SPI_IO_TYPE_DMA,
+        .c2tdelay       = 8,
+        .t2cdelay       = 8,
+};
+
+static struct spi_board_info mityomapl138_spi_flash_info[] = {
+        {
+                .modalias               = "m25p80",
+                .platform_data          = &mityomapl138_spi_flash_data,
+                .controller_data        = &spi_eprom_config,
+                .mode                   = SPI_MODE_0,
+                .max_speed_hz           = 30000000,
+                .bus_num                = 1,
+                .chip_select            = 0,
+        },
+};
+
+/*
+ * MityDSP-L138 includes a 256 MByte large-page NAND flash
+ * (128K blocks).
+ */
+static struct mtd_partition mityomapl138_nandflash_partition[] = {
+        {
+                .name           = "rootfs",
+                .offset         = 0,
+                .size           = SZ_128M,
+                .mask_flags     = 0, /* MTD_WRITEABLE, */
+        },
+        {
+                .name           = "homefs",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        },
+};
+
+static struct davinci_nand_pdata mityomapl138_nandflash_data = {
+        .parts          = mityomapl138_nandflash_partition,
+        .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
+        .ecc_mode       = NAND_ECC_HW,
+        .options        = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16,
+        .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
+};
+
+static struct resource mityomapl138_nandflash_resource[] = {
+        {
+                .start  = DA8XX_AEMIF_CS3_BASE,
+                .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = DA8XX_AEMIF_CTL_BASE,
+                .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mityomapl138_nandflash_device = {
+        .name           = "davinci_nand",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &mityomapl138_nandflash_data,
+        },
+        .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
+        .resource       = mityomapl138_nandflash_resource,
+};
+
+static struct platform_device *mityomapl138_devices[] __initdata = {
+        &mityomapl138_nandflash_device,
+};
+
+static void __init mityomapl138_setup_nand(void)
+{
+        platform_add_devices(mityomapl138_devices,
+                                 ARRAY_SIZE(mityomapl138_devices));
+}
+
+static struct davinci_uart_config mityomapl138_uart_config __initdata = {
+        .enabled_uarts = 0x7,
+};
+
+static const short mityomap_mii_pins[] = {
+        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
+        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
+        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
+        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+static const short mityomap_rmii_pins[] = {
+        DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
+        DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
+        DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+static void __init mityomapl138_config_emac(void)
+{
+        void __iomem *cfg_chip3_base;
+        int ret;
+        u32 val;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
+
+        cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
+        val = __raw_readl(cfg_chip3_base);
+
+        if (soc_info->emac_pdata->rmii_en) {
+                val |= BIT(8);
+                ret = davinci_cfg_reg_list(mityomap_rmii_pins);
+                pr_info("RMII PHY configured\n");
+        } else {
+                val &= ~BIT(8);
+                ret = davinci_cfg_reg_list(mityomap_mii_pins);
+                pr_info("MII PHY configured\n");
+        }
+
+        if (ret) {
+                pr_warning("mii/rmii mux setup failed: %d\n", ret);
+                return;
+        }
+
+        /* configure the CFGCHIP3 register for RMII or MII */
+        __raw_writel(val, cfg_chip3_base);
+
+        soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
+
+        ret = da8xx_register_emac();
+        if (ret)
+                pr_warning("emac registration failed: %d\n", ret);
+}
+
+static struct davinci_pm_config da850_pm_pdata = {
+        .sleepcount = 128,
+};
+
+static struct platform_device da850_pm_device = {
+        .name   = "pm-davinci",
+        .dev = {
+                .platform_data  = &da850_pm_pdata,
+        },
+        .id     = -1,
+};
+
+static void __init mityomapl138_init(void)
+{
+        int ret;
+
+        /* for now, no special EDMA channels are reserved */
+        ret = da850_register_edma(NULL);
+        if (ret)
+                pr_warning("edma registration failed: %d\n", ret);
+
+        ret = da8xx_register_watchdog();
+        if (ret)
+                pr_warning("watchdog registration failed: %d\n", ret);
+
+        davinci_serial_init(&mityomapl138_uart_config);
+
+        ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
+        if (ret)
+                pr_warning("i2c0 registration failed: %d\n", ret);
+
+        ret = pmic_tps65023_init();
+        if (ret)
+                pr_warning("TPS65023 PMIC init failed: %d\n", ret);
+
+        mityomapl138_setup_nand();
+
+        ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
+                               ARRAY_SIZE(mityomapl138_spi_flash_info));
+        if (ret)
+                pr_warning("spi 1 registration failed: %d\n", ret);
+
+        mityomapl138_config_emac();
+
+        ret = da8xx_register_rtc();
+        if (ret)
+                pr_warning("rtc setup failed: %d\n", ret);
+
+        ret = da8xx_register_cpuidle();
+        if (ret)
+                pr_warning("cpuidle registration failed: %d\n", ret);
+
+        ret = da850_register_pm(&da850_pm_device);
+        if (ret)
+                pr_warning("da850_evm_init: suspend registration failed: %d\n",
+                                ret);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init mityomapl138_console_init(void)
+{
+        if (!machine_is_mityomapl138())
+                return 0;
+
+        return add_preferred_console("ttyS", 1, "115200");
+}
+console_initcall(mityomapl138_console_init);
+#endif
+
+static void __init mityomapl138_map_io(void)
+{
+        da850_init();
+}
+
+MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
+        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .map_io         = mityomapl138_map_io,
+        .init_irq       = cp_intc_init,
+        .timer          = &davinci_timer,
+        .init_machine   = mityomapl138_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 4c30e929bbf9..3e7be2de96de 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -11,7 +11,7 @@
  * DM644X-EVM board. It has:
  *      DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
  *      USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
- *      Additionaly realtime clock, IR remote control receiver,
+ *      Additionally realtime clock, IR remote control receiver,
  *      IR Blaster based on MSP430 (firmware although is different
  *      from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
  *      with PATA interface, two muxed red-green leds.
@@ -39,9 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
-#define NEUROS_OSD2_PHY_MASK            0x2
-#define NEUROS_OSD2_MDIO_FREQUENCY      2200000 /* PHY bus frequency */
-
+#define NEUROS_OSD2_PHY_ID              "0:01"
 #define LXT971_PHY_ID                   0x001378e2
 #define LXT971_PHY_MASK                 0xfffffff0
 
@@ -252,8 +250,7 @@ static __init void davinci_ntosd2_init(void)
         davinci_serial_init(&uart_config);
         dm644x_init_asp(&dm644x_ntosd2_snd_data);
 
-        soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
+        soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
 
         davinci_setup_usb(1000, 8);
         /*
@@ -275,8 +272,6 @@ static __init void davinci_ntosd2_init(void)
 
 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
         /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
-        .phys_io        = IO_PHYS,
-        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params    = (DAVINCI_DDR_BASE + 0x100),
         .map_io          = davinci_ntosd2_map_io,
         .init_irq       = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
new file mode 100644
index 000000000000..67c38d0ecd10
--- /dev/null
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -0,0 +1,346 @@
+/*
+ * Hawkboard.org based on TI's OMAP-L138 Platform
+ *
+ * Initial code: Syed Mohammed Khasim
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of
+ * any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/cp_intc.h>
+#include <mach/da8xx.h>
+#include <mach/mux.h>
+
+#define HAWKBOARD_PHY_ID                "0:07"
+#define DA850_HAWK_MMCSD_CD_PIN         GPIO_TO_PIN(3, 12)
+#define DA850_HAWK_MMCSD_WP_PIN         GPIO_TO_PIN(3, 13)
+
+#define DA850_USB1_VBUS_PIN             GPIO_TO_PIN(2, 4)
+#define DA850_USB1_OC_PIN               GPIO_TO_PIN(6, 13)
+
+static short omapl138_hawk_mii_pins[] __initdata = {
+        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
+        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
+        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
+        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+static __init void omapl138_hawk_config_emac(void)
+{
+        void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
+        int ret;
+        u32 val;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        val = __raw_readl(cfgchip3);
+        val &= ~BIT(8);
+        ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins);
+        if (ret) {
+                pr_warning("%s: cpgmac/mii mux setup failed: %d\n",
+                        __func__, ret);
+                return;
+        }
+
+        /* configure the CFGCHIP3 register for MII */
+        __raw_writel(val, cfgchip3);
+        pr_info("EMAC: MII PHY configured\n");
+
+        soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID;
+
+        ret = da8xx_register_emac();
+        if (ret)
+                pr_warning("%s: emac registration failed: %d\n",
+                        __func__, ret);
+}
+
+/*
+ * The following EDMA channels/slots are not being used by drivers (for
+ * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard,
+ * hence they are being reserved for codecs on the DSP side.
+ */
+static const s16 da850_dma0_rsv_chans[][2] = {
+        /* (offset, number) */
+        { 8,  6},
+        {24,  4},
+        {30,  2},
+        {-1, -1}
+};
+
+static const s16 da850_dma0_rsv_slots[][2] = {
+        /* (offset, number) */
+        { 8,  6},
+        {24,  4},
+        {30, 50},
+        {-1, -1}
+};
+
+static const s16 da850_dma1_rsv_chans[][2] = {
+        /* (offset, number) */
+        { 0, 28},
+        {30,  2},
+        {-1, -1}
+};
+
+static const s16 da850_dma1_rsv_slots[][2] = {
+        /* (offset, number) */
+        { 0, 28},
+        {30, 90},
+        {-1, -1}
+};
+
+static struct edma_rsv_info da850_edma_cc0_rsv = {
+        .rsv_chans      = da850_dma0_rsv_chans,
+        .rsv_slots      = da850_dma0_rsv_slots,
+};
+
+static struct edma_rsv_info da850_edma_cc1_rsv = {
+        .rsv_chans      = da850_dma1_rsv_chans,
+        .rsv_slots      = da850_dma1_rsv_slots,
+};
+
+static struct edma_rsv_info *da850_edma_rsv[2] = {
+        &da850_edma_cc0_rsv,
+        &da850_edma_cc1_rsv,
+};
+
+static const short hawk_mmcsd0_pins[] = {
+        DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
+        DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
+        DA850_GPIO3_12, DA850_GPIO3_13,
+        -1
+};
+
+static int da850_hawk_mmc_get_ro(int index)
+{
+        return gpio_get_value(DA850_HAWK_MMCSD_WP_PIN);
+}
+
+static int da850_hawk_mmc_get_cd(int index)
+{
+        return !gpio_get_value(DA850_HAWK_MMCSD_CD_PIN);
+}
+
+static struct davinci_mmc_config da850_mmc_config = {
+        .get_ro         = da850_hawk_mmc_get_ro,
+        .get_cd         = da850_hawk_mmc_get_cd,
+        .wires          = 4,
+        .max_freq       = 50000000,
+        .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+        .version        = MMC_CTLR_VERSION_2,
+};
+
+static __init void omapl138_hawk_mmc_init(void)
+{
+        int ret;
+
+        ret = davinci_cfg_reg_list(hawk_mmcsd0_pins);
+        if (ret) {
+                pr_warning("%s: MMC/SD0 mux setup failed: %d\n",
+                        __func__, ret);
+                return;
+        }
+
+        ret = gpio_request_one(DA850_HAWK_MMCSD_CD_PIN,
+                        GPIOF_DIR_IN, "MMC CD");
+        if (ret < 0) {
+                pr_warning("%s: can not open GPIO %d\n",
+                        __func__, DA850_HAWK_MMCSD_CD_PIN);
+                return;
+        }
+
+        ret = gpio_request_one(DA850_HAWK_MMCSD_WP_PIN,
+                        GPIOF_DIR_IN, "MMC WP");
+        if (ret < 0) {
+                pr_warning("%s: can not open GPIO %d\n",
+                        __func__, DA850_HAWK_MMCSD_WP_PIN);
+                goto mmc_setup_wp_fail;
+        }
+
+        ret = da8xx_register_mmcsd0(&da850_mmc_config);
+        if (ret) {
+                pr_warning("%s: MMC/SD0 registration failed: %d\n",
+                        __func__, ret);
+                goto mmc_setup_mmcsd_fail;
+        }
+
+        return;
+
+mmc_setup_mmcsd_fail:
+        gpio_free(DA850_HAWK_MMCSD_WP_PIN);
+mmc_setup_wp_fail:
+        gpio_free(DA850_HAWK_MMCSD_CD_PIN);
+}
+
+static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id);
+static da8xx_ocic_handler_t hawk_usb_ocic_handler;
+
+static const short da850_hawk_usb11_pins[] = {
+        DA850_GPIO2_4, DA850_GPIO6_13,
+        -1
+};
+
+static int hawk_usb_set_power(unsigned port, int on)
+{
+        gpio_set_value(DA850_USB1_VBUS_PIN, on);
+        return 0;
+}
+
+static int hawk_usb_get_power(unsigned port)
+{
+        return gpio_get_value(DA850_USB1_VBUS_PIN);
+}
+
+static int hawk_usb_get_oci(unsigned port)
+{
+        return !gpio_get_value(DA850_USB1_OC_PIN);
+}
+
+static int hawk_usb_ocic_notify(da8xx_ocic_handler_t handler)
+{
+        int irq         = gpio_to_irq(DA850_USB1_OC_PIN);
+        int error       = 0;
+
+        if (handler != NULL) {
+                hawk_usb_ocic_handler = handler;
+
+                error = request_irq(irq, omapl138_hawk_usb_ocic_irq,
+                                        IRQF_DISABLED | IRQF_TRIGGER_RISING |
+                                        IRQF_TRIGGER_FALLING,
+                                        "OHCI over-current indicator", NULL);
+                if (error)
+                        pr_err("%s: could not request IRQ to watch "
+                                "over-current indicator changes\n", __func__);
+        } else {
+                free_irq(irq, NULL);
+        }
+        return error;
+}
+
+static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = {
+        .set_power      = hawk_usb_set_power,
+        .get_power      = hawk_usb_get_power,
+        .get_oci        = hawk_usb_get_oci,
+        .ocic_notify    = hawk_usb_ocic_notify,
+        /* TPS2087 switch @ 5V */
+        .potpgt         = (3 + 1) / 2,  /* 3 ms max */
+};
+
+static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id)
+{
+        hawk_usb_ocic_handler(&omapl138_hawk_usb11_pdata, 1);
+        return IRQ_HANDLED;
+}
+
+static __init void omapl138_hawk_usb_init(void)
+{
+        int ret;
+        u32 cfgchip2;
+
+        ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
+        if (ret) {
+                pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
+                        __func__, ret);
+                return;
+        }
+
+        /* Setup the Ref. clock frequency for the HAWK at 24 MHz. */
+
+        cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
+        cfgchip2 &= ~CFGCHIP2_REFFREQ;
+        cfgchip2 |=  CFGCHIP2_REFFREQ_24MHZ;
+        __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
+
+        ret = gpio_request_one(DA850_USB1_VBUS_PIN,
+                        GPIOF_DIR_OUT, "USB1 VBUS");
+        if (ret < 0) {
+                pr_err("%s: failed to request GPIO for USB 1.1 port "
+                        "power control: %d\n", __func__, ret);
+                return;
+        }
+
+        ret = gpio_request_one(DA850_USB1_OC_PIN,
+                        GPIOF_DIR_IN, "USB1 OC");
+        if (ret < 0) {
+                pr_err("%s: failed to request GPIO for USB 1.1 port "
+                        "over-current indicator: %d\n", __func__, ret);
+                goto usb11_setup_oc_fail;
+        }
+
+        ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
+        if (ret) {
+                pr_warning("%s: USB 1.1 registration failed: %d\n",
+                        __func__, ret);
+                goto usb11_setup_fail;
+        }
+
+        return;
+
+usb11_setup_fail:
+        gpio_free(DA850_USB1_OC_PIN);
+usb11_setup_oc_fail:
+        gpio_free(DA850_USB1_VBUS_PIN);
+}
+
+static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
+        .enabled_uarts = 0x7,
+};
+
+static __init void omapl138_hawk_init(void)
+{
+        int ret;
+
+        davinci_serial_init(&omapl138_hawk_uart_config);
+
+        omapl138_hawk_config_emac();
+
+        ret = da850_register_edma(da850_edma_rsv);
+        if (ret)
+                pr_warning("%s: EDMA registration failed: %d\n",
+                        __func__, ret);
+
+        omapl138_hawk_mmc_init();
+
+        omapl138_hawk_usb_init();
+
+        ret = da8xx_register_watchdog();
+        if (ret)
+                pr_warning("omapl138_hawk_init: "
+                        "watchdog registration failed: %d\n",
+                        ret);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init omapl138_hawk_console_init(void)
+{
+        if (!machine_is_omapl138_hawkboard())
+                return 0;
+
+        return add_preferred_console("ttyS", 2, "115200");
+}
+console_initcall(omapl138_hawk_console_init);
+#endif
+
+static void __init omapl138_hawk_map_io(void)
+{
+        da850_init();
+}
+
+MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
+        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .map_io         = omapl138_hawk_map_io,
+        .init_irq       = cp_intc_init,
+        .timer          = &davinci_timer,
+        .init_machine   = omapl138_hawk_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 23e664a1a802..61ac96d8f00d 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -42,9 +42,7 @@
 #include <mach/mux.h>
 #include <mach/usb.h>
 
-#define SFFSDR_PHY_MASK         (0x2)
-#define SFFSDR_MDIO_FREQUENCY   (2200000) /* PHY bus frequency */
-
+#define SFFSDR_PHY_ID           "0:01"
 static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
         /* U-Boot Environment: Block 0
          * UBL:                Block 1
@@ -143,8 +141,7 @@ static __init void davinci_sffsdr_init(void)
                              ARRAY_SIZE(davinci_sffsdr_devices));
         sffsdr_init_i2c();
         davinci_serial_init(&uart_config);
-        soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY;
+        soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID;
         davinci_setup_usb(0, 0); /* We support only peripheral mode. */
 
         /* mux VLYNQ pins */
@@ -154,8 +151,6 @@ static __init void davinci_sffsdr_init(void)
 
 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
         /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (DAVINCI_DDR_BASE + 0x100),
         .map_io       = davinci_sffsdr_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index fe2a9d9c8bb7..1a656e882262 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -23,6 +23,10 @@
 #include <linux/ratelimit.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -34,6 +38,7 @@
 
 #define EVM_MMC_WP_GPIO         21
 #define EVM_MMC_CD_GPIO         24
+#define EVM_SPI_CS_GPIO         54
 
 static int initialize_gpio(int gpio, char *desc)
 {
@@ -96,6 +101,12 @@ static const short uart1_pins[] __initdata = {
         -1
 };
 
+static const short ssp_pins[] __initdata = {
+        TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
+        TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
+        TNETV107X_SSP1_3, -1
+};
+
 static struct mtd_partition nand_partitions[] = {
         /* bootloader (U-Boot, etc) in first 12 sectors */
         {
@@ -141,18 +152,120 @@ static struct davinci_uart_config serial_config __initconst = {
         .enabled_uarts  = BIT(1),
 };
 
+static const uint32_t keymap[] = {
+        KEY(0, 0, KEY_NUMERIC_1),
+        KEY(0, 1, KEY_NUMERIC_2),
+        KEY(0, 2, KEY_NUMERIC_3),
+        KEY(0, 3, KEY_FN_F1),
+        KEY(0, 4, KEY_MENU),
+
+        KEY(1, 0, KEY_NUMERIC_4),
+        KEY(1, 1, KEY_NUMERIC_5),
+        KEY(1, 2, KEY_NUMERIC_6),
+        KEY(1, 3, KEY_UP),
+        KEY(1, 4, KEY_FN_F2),
+
+        KEY(2, 0, KEY_NUMERIC_7),
+        KEY(2, 1, KEY_NUMERIC_8),
+        KEY(2, 2, KEY_NUMERIC_9),
+        KEY(2, 3, KEY_LEFT),
+        KEY(2, 4, KEY_ENTER),
+
+        KEY(3, 0, KEY_NUMERIC_STAR),
+        KEY(3, 1, KEY_NUMERIC_0),
+        KEY(3, 2, KEY_NUMERIC_POUND),
+        KEY(3, 3, KEY_DOWN),
+        KEY(3, 4, KEY_RIGHT),
+
+        KEY(4, 0, KEY_FN_F3),
+        KEY(4, 1, KEY_FN_F4),
+        KEY(4, 2, KEY_MUTE),
+        KEY(4, 3, KEY_HOME),
+        KEY(4, 4, KEY_BACK),
+
+        KEY(5, 0, KEY_VOLUMEDOWN),
+        KEY(5, 1, KEY_VOLUMEUP),
+        KEY(5, 2, KEY_F1),
+        KEY(5, 3, KEY_F2),
+        KEY(5, 4, KEY_F3),
+};
+
+static const struct matrix_keymap_data keymap_data = {
+        .keymap         = keymap,
+        .keymap_size    = ARRAY_SIZE(keymap),
+};
+
+static struct matrix_keypad_platform_data keypad_config = {
+        .keymap_data    = &keymap_data,
+        .num_row_gpios  = 6,
+        .num_col_gpios  = 5,
+        .debounce_ms    = 0, /* minimum */
+        .active_low     = 0, /* pull up realization */
+        .no_autorepeat  = 0,
+};
+
+static void spi_select_device(int cs)
+{
+        static int gpio;
+
+        if (!gpio) {
+                int ret;
+                ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
+                if (ret < 0) {
+                        pr_err("cannot open spi chipsel gpio\n");
+                        gpio = -ENOSYS;
+                        return;
+                } else {
+                        gpio = EVM_SPI_CS_GPIO;
+                        gpio_direction_output(gpio, 0);
+                }
+        }
+
+        if (gpio < 0)
+                return;
+
+        return gpio_set_value(gpio, cs ? 1 : 0);
+}
+
+static struct ti_ssp_spi_data spi_master_data = {
+        .num_cs = 2,
+        .select = spi_select_device,
+        .iosel  = SSP_PIN_SEL(0, SSP_CLOCK)     | SSP_PIN_SEL(1, SSP_DATA) |
+                  SSP_PIN_SEL(2, SSP_CHIPSEL)   | SSP_PIN_SEL(3, SSP_IN)   |
+                  SSP_INPUT_SEL(3),
+};
+
+static struct ti_ssp_data ssp_config = {
+        .out_clock      = 250 * 1000,
+        .dev_data       = {
+                [1] = {
+                        .dev_name = "ti-ssp-spi",
+                        .pdata = &spi_master_data,
+                        .pdata_size = sizeof(spi_master_data),
+                },
+        },
+};
+
 static struct tnetv107x_device_info evm_device_info __initconst = {
         .serial_config          = &serial_config,
         .mmc_config[1]          = &mmc_config,  /* controller 1 */
         .nand_config[0]         = &nand_config, /* chip select 0 */
+        .keypad_config          = &keypad_config,
+        .ssp_config             = &ssp_config,
+};
+
+static struct spi_board_info spi_info[] __initconst = {
 };
 
 static __init void tnetv107x_evm_board_init(void)
 {
         davinci_cfg_reg_list(sdio1_pins);
         davinci_cfg_reg_list(uart1_pins);
+        davinci_cfg_reg_list(ssp_pins);
 
         tnetv107x_devices_init(&evm_device_info);
+
+        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -164,8 +277,6 @@ console_initcall(tnetv107x_evm_console_init);
 #endif
 
 MACHINE_START(TNETV107X, "TNETV107X EVM")
-        .phys_io        = TNETV107X_IO_BASE,
-        .io_pg_offst    = (TNETV107X_IO_VIRT >> 18) & 0xfffc,
         .boot_params    = (TNETV107X_DDR_BASE + 0x100),
         .map_io         = tnetv107x_init,
         .init_irq       = cp_intc_init,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 054c303caead..e4e3af179f02 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -236,7 +236,7 @@ static int __init clk_disable_unused(void)
                 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
                         continue;
 
-                pr_info("Clocks: disable unused %s\n", ck->name);
+                pr_debug("Clocks: disable unused %s\n", ck->name);
 
                 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
                                 (ck->flags & PSC_SWRSTDISABLE) ?
@@ -287,6 +287,79 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
         return rate;
 }
 
+int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned v;
+        struct pll_data *pll;
+        unsigned long input;
+        unsigned ratio = 0;
+
+        /* If this is the PLL base clock, wrong function to call */
+        if (clk->pll_data)
+                return -EINVAL;
+
+        /* There must be a parent... */
+        if (WARN_ON(!clk->parent))
+                return -EINVAL;
+
+        /* ... the parent must be a PLL... */
+        if (WARN_ON(!clk->parent->pll_data))
+                return -EINVAL;
+
+        /* ... and this clock must have a divider. */
+        if (WARN_ON(!clk->div_reg))
+                return -EINVAL;
+
+        pll = clk->parent->pll_data;
+
+        input = clk->parent->rate;
+
+        /* If pre-PLL, source clock is before the multiplier and divider(s) */
+        if (clk->flags & PRE_PLL)
+                input = pll->input_rate;
+
+        if (input > rate) {
+                /*
+                 * Can afford to provide an output little higher than requested
+                 * only if maximum rate supported by hardware on this sysclk
+                 * is known.
+                 */
+                if (clk->maxrate) {
+                        ratio = DIV_ROUND_CLOSEST(input, rate);
+                        if (input / ratio > clk->maxrate)
+                                ratio = 0;
+                }
+
+                if (ratio == 0)
+                        ratio = DIV_ROUND_UP(input, rate);
+
+                ratio--;
+        }
+
+        if (ratio > pll->div_ratio_mask)
+                return -EINVAL;
+
+        do {
+                v = __raw_readl(pll->base + PLLSTAT);
+        } while (v & PLLSTAT_GOSTAT);
+
+        v = __raw_readl(pll->base + clk->div_reg);
+        v &= ~pll->div_ratio_mask;
+        v |= ratio | PLLDIV_EN;
+        __raw_writel(v, pll->base + clk->div_reg);
+
+        v = __raw_readl(pll->base + PLLCMD);
+        v |= PLLCMD_GOSET;
+        __raw_writel(v, pll->base + PLLCMD);
+
+        do {
+                v = __raw_readl(pll->base + PLLSTAT);
+        } while (v & PLLSTAT_GOSTAT);
+
+        return 0;
+}
+EXPORT_SYMBOL(davinci_set_sysclk_rate);
+
 static unsigned long clk_leafclk_recalc(struct clk *clk)
 {
         if (WARN_ON(!clk->parent))
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 01e36483ac3d..0dd22031ec62 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -68,7 +68,10 @@
 #ifndef __ASSEMBLER__
 
 #include <linux/list.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
+
+#define PLLSTAT_GOSTAT  BIT(0)
+#define PLLCMD_GOSET    BIT(0)
 
 struct pll_data {
         u32 phys_base;
@@ -86,6 +89,7 @@ struct clk {
         struct module           *owner;
         const char              *name;
         unsigned long           rate;
+        unsigned long           maxrate;        /* H/W supported max rate */
         u8                      usecount;
         u8                      lpsc;
         u8                      gpsc;
@@ -118,6 +122,7 @@ struct clk {
 int davinci_clk_init(struct clk_lookup *clocks);
 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
                                 unsigned int mult, unsigned int postdiv);
+int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
 
 extern struct platform_device davinci_wdt_device;
 extern void davinci_watchdog_reset(struct platform_device *);
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index bb4c40ecb803..f83152d643c5 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -26,30 +26,30 @@ static inline void cp_intc_write(unsigned long value, unsigned offset)
         __raw_writel(value, davinci_intc_base + offset);
 }
 
-static void cp_intc_ack_irq(unsigned int irq)
+static void cp_intc_ack_irq(struct irq_data *d)
 {
-        cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR);
+        cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR);
 }
 
 /* Disable interrupt */
-static void cp_intc_mask_irq(unsigned int irq)
+static void cp_intc_mask_irq(struct irq_data *d)
 {
         /* XXX don't know why we need to disable nIRQ here... */
         cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
-        cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR);
+        cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR);
         cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
 }
 
 /* Enable interrupt */
-static void cp_intc_unmask_irq(unsigned int irq)
+static void cp_intc_unmask_irq(struct irq_data *d)
 {
-        cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET);
+        cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET);
 }
 
-static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
+static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-        unsigned reg            = BIT_WORD(irq);
-        unsigned mask           = BIT_MASK(irq);
+        unsigned reg            = BIT_WORD(d->irq);
+        unsigned mask           = BIT_MASK(d->irq);
         unsigned polarity       = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
         unsigned type           = cp_intc_read(CP_INTC_SYS_TYPE(reg));
 
@@ -85,18 +85,18 @@ static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
  * generic drivers which call {enable|disable}_irq_wake for
  * wake up interrupt sources (eg RTC on DA850).
  */
-static int cp_intc_set_wake(unsigned int irq, unsigned int on)
+static int cp_intc_set_wake(struct irq_data *d, unsigned int on)
 {
         return 0;
 }
 
 static struct irq_chip cp_intc_irq_chip = {
         .name           = "cp_intc",
-        .ack            = cp_intc_ack_irq,
-        .mask           = cp_intc_mask_irq,
-        .unmask         = cp_intc_unmask_irq,
-        .set_type       = cp_intc_set_irq_type,
-        .set_wake       = cp_intc_set_wake,
+        .irq_ack        = cp_intc_ack_irq,
+        .irq_mask       = cp_intc_mask_irq,
+        .irq_unmask     = cp_intc_unmask_irq,
+        .irq_set_type   = cp_intc_set_irq_type,
+        .irq_set_wake   = cp_intc_set_wake,
 };
 
 void __init cp_intc_init(void)
@@ -167,9 +167,9 @@ void __init cp_intc_init(void)
 
         /* Set up genirq dispatching for cp_intc */
         for (i = 0; i < num_irq; i++) {
-                set_irq_chip(i, &cp_intc_irq_chip);
+                irq_set_chip(i, &cp_intc_irq_chip);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                set_irq_handler(i, handle_edge_irq);
+                irq_set_handler(i, handle_edge_irq);
         }
 
         /* Enable global interrupt */
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index d3fa6de1e20f..41669ecc1f91 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -34,6 +34,8 @@
 struct davinci_cpufreq {
         struct device *dev;
         struct clk *armclk;
+        struct clk *asyncclk;
+        unsigned long asyncrate;
 };
 static struct davinci_cpufreq cpufreq;
 
@@ -92,9 +94,7 @@ static int davinci_target(struct cpufreq_policy *policy,
         if (freqs.old == freqs.new)
                 return ret;
 
-        cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER,
-                        dev_driver_string(cpufreq.dev),
-                        "transition: %u --> %u\n", freqs.old, freqs.new);
+        dev_dbg(&cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
 
         ret = cpufreq_frequency_table_target(policy, pdata->freq_table,
                                                 freqs.new, relation, &idx);
@@ -104,21 +104,33 @@ static int davinci_target(struct cpufreq_policy *policy,
         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 
         /* if moving to higher frequency, up the voltage beforehand */
-        if (pdata->set_voltage && freqs.new > freqs.old)
-                pdata->set_voltage(idx);
+        if (pdata->set_voltage && freqs.new > freqs.old) {
+                ret = pdata->set_voltage(idx);
+                if (ret)
+                        goto out;
+        }
 
         ret = clk_set_rate(armclk, idx);
+        if (ret)
+                goto out;
+
+        if (cpufreq.asyncclk) {
+                ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate);
+                if (ret)
+                        goto out;
+        }
 
         /* if moving to lower freq, lower the voltage after lowering freq */
         if (pdata->set_voltage && freqs.new < freqs.old)
                 pdata->set_voltage(idx);
 
+out:
         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 
         return ret;
 }
 
-static int __init davinci_cpu_init(struct cpufreq_policy *policy)
+static int davinci_cpu_init(struct cpufreq_policy *policy)
 {
         int result = 0;
         struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
@@ -153,7 +165,7 @@ static int __init davinci_cpu_init(struct cpufreq_policy *policy)
         /*
          * Time measurement across the target() function yields ~1500-1800us
          * time taken with no drivers on notification list.
-         * Setting the latency to 2000 us to accomodate addition of drivers
+         * Setting the latency to 2000 us to accommodate addition of drivers
          * to pre/post change notification list.
          */
         policy->cpuinfo.transition_latency = 2000 * 1000;
@@ -185,6 +197,7 @@ static struct cpufreq_driver davinci_driver = {
 static int __init davinci_cpufreq_probe(struct platform_device *pdev)
 {
         struct davinci_cpufreq_config *pdata = pdev->dev.platform_data;
+        struct clk *asyncclk;
 
         if (!pdata)
                 return -EINVAL;
@@ -199,6 +212,12 @@ static int __init davinci_cpufreq_probe(struct platform_device *pdev)
                 return PTR_ERR(cpufreq.armclk);
         }
 
+        asyncclk = clk_get(cpufreq.dev, "async");
+        if (!IS_ERR(asyncclk)) {
+                cpufreq.asyncclk = asyncclk;
+                cpufreq.asyncrate = clk_get_rate(asyncclk);
+        }
+
         return cpufreq_register_driver(&davinci_driver);
 }
 
@@ -206,6 +225,9 @@ static int __exit davinci_cpufreq_remove(struct platform_device *pdev)
 {
         clk_put(cpufreq.armclk);
 
+        if (cpufreq.asyncclk)
+                clk_put(cpufreq.asyncclk);
+
         return cpufreq_unregister_driver(&davinci_driver);
 }
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index ec23ab473620..2ed2f822fc40 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -148,7 +148,7 @@ static struct clk scr2_ss_clk = {
 static struct clk dmax_clk = {
         .name           = "dmax",
         .parent         = &pll0_sysclk2,
-        .lpsc           = DA8XX_LPSC0_DMAX,
+        .lpsc           = DA8XX_LPSC0_PRUSS,
         .flags          = ALWAYS_ENABLED,
 };
 
@@ -397,8 +397,8 @@ static struct clk_lookup da830_clks[] = {
         CLK(NULL,               "uart0",        &uart0_clk),
         CLK(NULL,               "uart1",        &uart1_clk),
         CLK(NULL,               "uart2",        &uart2_clk),
-        CLK("dm_spi.0",         NULL,           &spi0_clk),
-        CLK("dm_spi.1",         NULL,           &spi1_clk),
+        CLK("spi_davinci.0",    NULL,           &spi0_clk),
+        CLK("spi_davinci.1",    NULL,           &spi1_clk),
         CLK(NULL,               "ecap0",        &ecap0_clk),
         CLK(NULL,               "ecap1",        &ecap1_clk),
         CLK(NULL,               "ecap2",        &ecap2_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 68ed58a48252..133aac405853 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -86,6 +86,8 @@ static struct clk pll0_sysclk3 = {
         .parent         = &pll0_clk,
         .flags          = CLK_PLL,
         .div_reg        = PLLDIV3,
+        .set_rate       = davinci_set_sysclk_rate,
+        .maxrate        = 100000000,
 };
 
 static struct clk pll0_sysclk4 = {
@@ -323,12 +325,19 @@ static struct clk lcdc_clk = {
         .gpsc           = 1,
 };
 
-static struct clk mmcsd_clk = {
-        .name           = "mmcsd",
+static struct clk mmcsd0_clk = {
+        .name           = "mmcsd0",
         .parent         = &pll0_sysclk2,
         .lpsc           = DA8XX_LPSC0_MMC_SD,
 };
 
+static struct clk mmcsd1_clk = {
+        .name           = "mmcsd1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA850_LPSC1_MMC_SD1,
+        .gpsc           = 1,
+};
+
 static struct clk aemif_clk = {
         .name           = "aemif",
         .parent         = &pll0_sysclk3,
@@ -336,6 +345,34 @@ static struct clk aemif_clk = {
         .flags          = ALWAYS_ENABLED,
 };
 
+static struct clk usb11_clk = {
+        .name           = "usb11",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_USB11,
+        .gpsc           = 1,
+};
+
+static struct clk usb20_clk = {
+        .name           = "usb20",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_USB20,
+        .gpsc           = 1,
+};
+
+static struct clk spi0_clk = {
+        .name           = "spi0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SPI0,
+};
+
+static struct clk spi1_clk = {
+        .name           = "spi1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_SPI1,
+        .gpsc           = 1,
+        .flags          = DA850_CLK_ASYNC3,
+};
+
 static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "ref",          &ref_clk),
         CLK(NULL,               "pll0",         &pll0_clk),
@@ -375,8 +412,13 @@ static struct clk_lookup da850_clks[] = {
         CLK("davinci_emac.1",   NULL,           &emac_clk),
         CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
         CLK("da8xx_lcdc.0",     NULL,           &lcdc_clk),
-        CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
+        CLK("davinci_mmc.0",    NULL,           &mmcsd0_clk),
+        CLK("davinci_mmc.1",    NULL,           &mmcsd1_clk),
         CLK(NULL,               "aemif",        &aemif_clk),
+        CLK(NULL,               "usb11",        &usb11_clk),
+        CLK(NULL,               "usb20",        &usb20_clk),
+        CLK("spi_davinci.0",    NULL,           &spi0_clk),
+        CLK("spi_davinci.1",    NULL,           &spi1_clk),
         CLK(NULL,               NULL,           NULL),
 };
 
@@ -533,30 +575,19 @@ static const struct mux_config da850_pins[] = {
         MUX_CFG(DA850, EMA_WAIT_1,      6,      24,     15,     1,      false)
         MUX_CFG(DA850, NEMA_CS_2,       7,      0,      15,     1,      false)
         /* GPIO function */
+        MUX_CFG(DA850, GPIO2_4,         6,      12,     15,     8,      false)
         MUX_CFG(DA850, GPIO2_6,         6,      4,      15,     8,      false)
         MUX_CFG(DA850, GPIO2_8,         5,      28,     15,     8,      false)
         MUX_CFG(DA850, GPIO2_15,        5,      0,      15,     8,      false)
+        MUX_CFG(DA850, GPIO3_12,        7,      12,     15,     8,      false)
+        MUX_CFG(DA850, GPIO3_13,        7,      8,      15,     8,      false)
         MUX_CFG(DA850, GPIO4_0,         10,     28,     15,     8,      false)
         MUX_CFG(DA850, GPIO4_1,         10,     24,     15,     8,      false)
+        MUX_CFG(DA850, GPIO6_13,        13,     8,      15,     8,      false)
         MUX_CFG(DA850, RTC_ALARM,       0,      28,     15,     2,      false)
 #endif
 };
 
-const short da850_uart0_pins[] __initdata = {
-        DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
-        -1
-};
-
-const short da850_uart1_pins[] __initdata = {
-        DA850_UART1_RXD, DA850_UART1_TXD,
-        -1
-};
-
-const short da850_uart2_pins[] __initdata = {
-        DA850_UART2_RXD, DA850_UART2_TXD,
-        -1
-};
-
 const short da850_i2c0_pins[] __initdata = {
         DA850_I2C0_SDA, DA850_I2C0_SCL,
         -1
@@ -567,30 +598,6 @@ const short da850_i2c1_pins[] __initdata = {
         -1
 };
 
-const short da850_cpgmac_pins[] __initdata = {
-        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
-        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
-        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
-        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
-        DA850_MDIO_D,
-        -1
-};
-
-const short da850_rmii_pins[] __initdata = {
-        DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
-        DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
-        DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
-        DA850_MDIO_D,
-        -1
-};
-
-const short da850_mcasp_pins[] __initdata = {
-        DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
-        DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
-        DA850_AXR_11, DA850_AXR_12,
-        -1
-};
-
 const short da850_lcdcntl_pins[] __initdata = {
         DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
         DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
@@ -600,37 +607,6 @@ const short da850_lcdcntl_pins[] __initdata = {
         -1
 };
 
-const short da850_mmcsd0_pins[] __initdata = {
-        DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
-        DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
-        DA850_GPIO4_0, DA850_GPIO4_1,
-        -1
-};
-
-const short da850_nand_pins[] __initdata = {
-        DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
-        DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
-        DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
-        DA850_NEMA_WE, DA850_NEMA_OE,
-        -1
-};
-
-const short da850_nor_pins[] __initdata = {
-        DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
-        DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
-        DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
-        DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
-        DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
-        DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
-        DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
-        DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
-        DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
-        DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
-        DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
-        DA850_EMA_A_22, DA850_EMA_A_23,
-        -1
-};
-
 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
         [IRQ_DA8XX_COMMTX]              = 7,
@@ -768,6 +744,13 @@ static struct davinci_id da850_ids[] = {
                 .cpu_id         = DAVINCI_CPU_ID_DA850,
                 .name           = "da850/omap-l138",
         },
+        {
+                .variant        = 0x1,
+                .part_no        = 0xb7d1,
+                .manufacturer   = 0x017,        /* 0x02f >> 1 */
+                .cpu_id         = DAVINCI_CPU_ID_DA850,
+                .name           = "da850/omap-l138/am18x",
+        },
 };
 
 static struct davinci_timer_instance da850_timer_instance[4] = {
@@ -834,8 +817,7 @@ static void da850_set_async3_src(int pllnum)
  * According to the TRM, minimum PLLM results in maximum power savings.
  * The OPP definitions below should keep the PLLM as low as possible.
  *
- * The output of the PLLM must be between 400 to 600 MHz.
- * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
+ * The output of the PLLM must be between 300 to 600 MHz.
  */
 struct da850_opp {
         unsigned int    freq;   /* in KHz */
@@ -846,12 +828,39 @@ struct da850_opp {
         unsigned int    cvdd_max; /* in uV */
 };
 
+static const struct da850_opp da850_opp_456 = {
+        .freq           = 456000,
+        .prediv         = 1,
+        .mult           = 19,
+        .postdiv        = 1,
+        .cvdd_min       = 1300000,
+        .cvdd_max       = 1350000,
+};
+
+static const struct da850_opp da850_opp_408 = {
+        .freq           = 408000,
+        .prediv         = 1,
+        .mult           = 17,
+        .postdiv        = 1,
+        .cvdd_min       = 1300000,
+        .cvdd_max       = 1350000,
+};
+
+static const struct da850_opp da850_opp_372 = {
+        .freq           = 372000,
+        .prediv         = 2,
+        .mult           = 31,
+        .postdiv        = 1,
+        .cvdd_min       = 1200000,
+        .cvdd_max       = 1320000,
+};
+
 static const struct da850_opp da850_opp_300 = {
         .freq           = 300000,
         .prediv         = 1,
         .mult           = 25,
         .postdiv        = 2,
-        .cvdd_min       = 1140000,
+        .cvdd_min       = 1200000,
         .cvdd_max       = 1320000,
 };
 
@@ -860,7 +869,7 @@ static const struct da850_opp da850_opp_200 = {
         .prediv         = 1,
         .mult           = 25,
         .postdiv        = 3,
-        .cvdd_min       = 1050000,
+        .cvdd_min       = 1100000,
         .cvdd_max       = 1160000,
 };
 
@@ -869,7 +878,7 @@ static const struct da850_opp da850_opp_96 = {
         .prediv         = 1,
         .mult           = 20,
         .postdiv        = 5,
-        .cvdd_min       = 950000,
+        .cvdd_min       = 1000000,
         .cvdd_max       = 1050000,
 };
 
@@ -880,6 +889,9 @@ static const struct da850_opp da850_opp_96 = {
         }
 
 static struct cpufreq_frequency_table da850_freq_table[] = {
+        OPP(456),
+        OPP(408),
+        OPP(372),
         OPP(300),
         OPP(200),
         OPP(96),
@@ -890,6 +902,19 @@ static struct cpufreq_frequency_table da850_freq_table[] = {
 };
 
 #ifdef CONFIG_REGULATOR
+static int da850_set_voltage(unsigned int index);
+static int da850_regulator_init(void);
+#endif
+
+static struct davinci_cpufreq_config cpufreq_info = {
+        .freq_table = da850_freq_table,
+#ifdef CONFIG_REGULATOR
+        .init = da850_regulator_init,
+        .set_voltage = da850_set_voltage,
+#endif
+};
+
+#ifdef CONFIG_REGULATOR
 static struct regulator *cvdd;
 
 static int da850_set_voltage(unsigned int index)
@@ -899,7 +924,7 @@ static int da850_set_voltage(unsigned int index)
         if (!cvdd)
                 return -ENODEV;
 
-        opp = (struct da850_opp *) da850_freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
 
         return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
 }
@@ -916,23 +941,31 @@ static int da850_regulator_init(void)
 }
 #endif
 
-static struct davinci_cpufreq_config cpufreq_info = {
-        .freq_table = &da850_freq_table[0],
-#ifdef CONFIG_REGULATOR
-        .init = da850_regulator_init,
-        .set_voltage = da850_set_voltage,
-#endif
-};
-
 static struct platform_device da850_cpufreq_device = {
         .name                   = "cpufreq-davinci",
         .dev = {
                 .platform_data  = &cpufreq_info,
         },
+        .id = -1,
 };
 
-int __init da850_register_cpufreq(void)
+unsigned int da850_max_speed = 300000;
+
+int __init da850_register_cpufreq(char *async_clk)
 {
+        int i;
+
+        /* cpufreq driver can help keep an "async" clock constant */
+        if (async_clk)
+                clk_add_alias("async", da850_cpufreq_device.name,
+                                                        async_clk, NULL);
+        for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
+                if (da850_freq_table[i].frequency <= da850_max_speed) {
+                        cpufreq_info.freq_table = &da850_freq_table[i];
+                        break;
+                }
+        }
+
         return platform_device_register(&da850_cpufreq_device);
 }
 
@@ -940,17 +973,18 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
 {
         int i, ret = 0, diff;
         unsigned int best = (unsigned int) -1;
+        struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
 
         rate /= 1000; /* convert to kHz */
 
-        for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
-                diff = da850_freq_table[i].frequency - rate;
+        for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+                diff = table[i].frequency - rate;
                 if (diff < 0)
                         diff = -diff;
 
                 if (diff < best) {
                         best = diff;
-                        ret = da850_freq_table[i].frequency;
+                        ret = table[i].frequency;
                 }
         }
 
@@ -971,7 +1005,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         struct pll_data *pll = clk->pll_data;
         int ret;
 
-        opp = (struct da850_opp *) da850_freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
         prediv = opp->prediv;
         mult = opp->mult;
         postdiv = opp->postdiv;
@@ -983,7 +1017,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         return 0;
 }
 #else
-int __init da850_register_cpufreq(void)
+int __init da850_register_cpufreq(char *async_clk)
 {
         return 0;
 }
@@ -1021,7 +1055,7 @@ int da850_register_pm(struct platform_device *pdev)
         if (!pdata->cpupll_reg_base)
                 return -ENOMEM;
 
-        pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
+        pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
         if (!pdata->ddrpll_reg_base) {
                 ret = -ENOMEM;
                 goto no_ddrpll_mem;
@@ -1089,7 +1123,7 @@ void __init da850_init(void)
          * This helps keeping the peripherals on this domain insulated
          * from CPU frequency changes caused by DVFS. The firmware sets
          * both PLL0 and PLL1 to the same frequency so, there should not
-         * be any noticible change even in non-DVFS use cases.
+         * be any noticeable change even in non-DVFS use cases.
          */
         da850_set_async3_src(1);
 
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 52bc7b1c6ca3..fc4e98ea7543 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -24,26 +24,40 @@
 #include "clock.h"
 
 #define DA8XX_TPCC_BASE                 0x01c00000
-#define DA850_TPCC1_BASE                0x01e30000
 #define DA8XX_TPTC0_BASE                0x01c08000
 #define DA8XX_TPTC1_BASE                0x01c08400
-#define DA850_TPTC2_BASE                0x01e38000
 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
 #define DA8XX_I2C0_BASE                 0x01c22000
-#define DA8XX_RTC_BASE                  0x01C23000
+#define DA8XX_RTC_BASE                  0x01c23000
+#define DA8XX_MMCSD0_BASE               0x01c40000
+#define DA8XX_SPI0_BASE                 0x01c41000
+#define DA830_SPI1_BASE                 0x01e12000
+#define DA8XX_LCD_CNTRL_BASE            0x01e13000
+#define DA850_MMCSD1_BASE               0x01e1b000
 #define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
 #define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
 #define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
 #define DA8XX_EMAC_MDIO_BASE            0x01e24000
-#define DA8XX_GPIO_BASE                 0x01e26000
 #define DA8XX_I2C1_BASE                 0x01e28000
+#define DA850_TPCC1_BASE                0x01e30000
+#define DA850_TPTC2_BASE                0x01e38000
+#define DA850_SPI1_BASE                 0x01f0e000
+#define DA8XX_DDR2_CTL_BASE             0xb0000000
 
 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
 #define DA8XX_EMAC_RAM_OFFSET           0x0000
-#define DA8XX_MDIO_REG_OFFSET           0x4000
 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
 
+#define DA8XX_DMA_SPI0_RX       EDMA_CTLR_CHAN(0, 14)
+#define DA8XX_DMA_SPI0_TX       EDMA_CTLR_CHAN(0, 15)
+#define DA8XX_DMA_MMCSD0_RX     EDMA_CTLR_CHAN(0, 16)
+#define DA8XX_DMA_MMCSD0_TX     EDMA_CTLR_CHAN(0, 17)
+#define DA8XX_DMA_SPI1_RX       EDMA_CTLR_CHAN(0, 18)
+#define DA8XX_DMA_SPI1_TX       EDMA_CTLR_CHAN(0, 19)
+#define DA850_DMA_MMCSD1_RX     EDMA_CTLR_CHAN(1, 28)
+#define DA850_DMA_MMCSD1_TX     EDMA_CTLR_CHAN(1, 29)
+
 void __iomem *da8xx_syscfg0_base;
 void __iomem *da8xx_syscfg1_base;
 
@@ -351,7 +365,7 @@ int __init da8xx_register_watchdog(void)
 static struct resource da8xx_emac_resources[] = {
         {
                 .start  = DA8XX_EMAC_CPPI_PORT_BASE,
-                .end    = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
+                .end    = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -380,7 +394,6 @@ struct emac_platform_data da8xx_emac_pdata = {
         .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
         .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
         .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
-        .mdio_reg_offset        = DA8XX_MDIO_REG_OFFSET,
         .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
         .version                = EMAC_VERSION_2,
 };
@@ -395,9 +408,34 @@ static struct platform_device da8xx_emac_device = {
         .resource       = da8xx_emac_resources,
 };
 
+static struct resource da8xx_mdio_resources[] = {
+        {
+                .start  = DA8XX_EMAC_MDIO_BASE,
+                .end    = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device da8xx_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(da8xx_mdio_resources),
+        .resource       = da8xx_mdio_resources,
+};
+
 int __init da8xx_register_emac(void)
 {
-        return platform_device_register(&da8xx_emac_device);
+        int ret;
+
+        ret = platform_device_register(&da8xx_mdio_device);
+        if (ret < 0)
+                return ret;
+        ret = platform_device_register(&da8xx_emac_device);
+        if (ret < 0)
+                return ret;
+        ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
+                            NULL, &da8xx_emac_device.dev);
+        return ret;
 }
 
 static struct resource da830_mcasp1_resources[] = {
@@ -456,8 +494,15 @@ static struct platform_device da850_mcasp_device = {
         .resource       = da850_mcasp_resources,
 };
 
+static struct platform_device davinci_pcm_device = {
+        .name   = "davinci-pcm-audio",
+        .id     = -1,
+};
+
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 {
+        platform_device_register(&davinci_pcm_device);
+
         /* DA830/OMAP-L137 has 3 instances of McASP */
         if (cpu_is_davinci_da830() && id == 1) {
                 da830_mcasp1_device.dev.platform_data = pdata;
@@ -542,13 +587,13 @@ static struct resource da8xx_mmcsd0_resources[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         {               /* DMA RX */
-                .start  = EDMA_CTLR_CHAN(0, 16),
-                .end    = EDMA_CTLR_CHAN(0, 16),
+                .start  = DA8XX_DMA_MMCSD0_RX,
+                .end    = DA8XX_DMA_MMCSD0_RX,
                 .flags  = IORESOURCE_DMA,
         },
         {               /* DMA TX */
-                .start  = EDMA_CTLR_CHAN(0, 17),
-                .end    = EDMA_CTLR_CHAN(0, 17),
+                .start  = DA8XX_DMA_MMCSD0_TX,
+                .end    = DA8XX_DMA_MMCSD0_TX,
                 .flags  = IORESOURCE_DMA,
         },
 };
@@ -566,6 +611,44 @@ int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
         return platform_device_register(&da8xx_mmcsd0_device);
 }
 
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+static struct resource da850_mmcsd1_resources[] = {
+        {               /* registers */
+                .start  = DA850_MMCSD1_BASE,
+                .end    = DA850_MMCSD1_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {               /* interrupt */
+                .start  = IRQ_DA850_MMCSDINT0_1,
+                .end    = IRQ_DA850_MMCSDINT0_1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {               /* DMA RX */
+                .start  = DA850_DMA_MMCSD1_RX,
+                .end    = DA850_DMA_MMCSD1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        {               /* DMA TX */
+                .start  = DA850_DMA_MMCSD1_TX,
+                .end    = DA850_DMA_MMCSD1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device da850_mmcsd1_device = {
+        .name           = "davinci_mmc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
+        .resource       = da850_mmcsd1_resources,
+};
+
+int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
+{
+        da850_mmcsd1_device.dev.platform_data = config;
+        return platform_device_register(&da850_mmcsd1_device);
+}
+#endif
+
 static struct resource da8xx_rtc_resources[] = {
         {
                 .start          = DA8XX_RTC_BASE,
@@ -656,3 +739,106 @@ int __init da8xx_register_cpuidle(void)
 
         return platform_device_register(&da8xx_cpuidle_device);
 }
+
+static struct resource da8xx_spi0_resources[] = {
+        [0] = {
+                .start  = DA8XX_SPI0_BASE,
+                .end    = DA8XX_SPI0_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_DA8XX_SPINT0,
+                .end    = IRQ_DA8XX_SPINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DA8XX_DMA_SPI0_RX,
+                .end    = DA8XX_DMA_SPI0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DA8XX_DMA_SPI0_TX,
+                .end    = DA8XX_DMA_SPI0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct resource da8xx_spi1_resources[] = {
+        [0] = {
+                .start  = DA830_SPI1_BASE,
+                .end    = DA830_SPI1_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_DA8XX_SPINT1,
+                .end    = IRQ_DA8XX_SPINT1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DA8XX_DMA_SPI1_RX,
+                .end    = DA8XX_DMA_SPI1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DA8XX_DMA_SPI1_TX,
+                .end    = DA8XX_DMA_SPI1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct davinci_spi_platform_data da8xx_spi_pdata[] = {
+        [0] = {
+                .version        = SPI_VERSION_2,
+                .intr_line      = 1,
+                .dma_event_q    = EVENTQ_0,
+        },
+        [1] = {
+                .version        = SPI_VERSION_2,
+                .intr_line      = 1,
+                .dma_event_q    = EVENTQ_0,
+        },
+};
+
+static struct platform_device da8xx_spi_device[] = {
+        [0] = {
+                .name           = "spi_davinci",
+                .id             = 0,
+                .num_resources  = ARRAY_SIZE(da8xx_spi0_resources),
+                .resource       = da8xx_spi0_resources,
+                .dev            = {
+                        .platform_data = &da8xx_spi_pdata[0],
+                },
+        },
+        [1] = {
+                .name           = "spi_davinci",
+                .id             = 1,
+                .num_resources  = ARRAY_SIZE(da8xx_spi1_resources),
+                .resource       = da8xx_spi1_resources,
+                .dev            = {
+                        .platform_data = &da8xx_spi_pdata[1],
+                },
+        },
+};
+
+int __init da8xx_register_spi(int instance, struct spi_board_info *info,
+                              unsigned len)
+{
+        int ret;
+
+        if (instance < 0 || instance > 1)
+                return -EINVAL;
+
+        ret = spi_register_board_info(info, len);
+        if (ret)
+                pr_warning("%s: failed to register board info for spi %d :"
+                           " %d\n", __func__, instance, ret);
+
+        da8xx_spi_pdata[instance].num_chipselect = len;
+
+        if (instance == 1 && cpu_is_davinci_da850()) {
+                da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
+                da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
+        }
+
+        return platform_device_register(&da8xx_spi_device[instance]);
+}
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 2718a3a90dff..6162cae7f868 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -31,8 +31,11 @@
 #define TNETV107X_TPTC0_BASE                    0x01c10000
 #define TNETV107X_TPTC1_BASE                    0x01c10400
 #define TNETV107X_WDOG_BASE                     0x08086700
+#define TNETV107X_TSC_BASE                      0x08088500
 #define TNETV107X_SDIO0_BASE                    0x08088700
 #define TNETV107X_SDIO1_BASE                    0x08088800
+#define TNETV107X_KEYPAD_BASE                   0x08088a00
+#define TNETV107X_SSP_BASE                      0x08088c00
 #define TNETV107X_ASYNC_EMIF_CNTRL_BASE         0x08200000
 #define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE      0x30000000
 #define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE      0x40000000
@@ -298,12 +301,87 @@ static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
         return platform_device_register(pdev);
 }
 
+static struct resource keypad_resources[] = {
+        {
+                .start  = TNETV107X_KEYPAD_BASE,
+                .end    = TNETV107X_KEYPAD_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_TNETV107X_KEYPAD,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "press",
+        },
+        {
+                .start  = IRQ_TNETV107X_KEYPAD_FREE,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "release",
+        },
+};
+
+static struct platform_device keypad_device = {
+        .name           = "tnetv107x-keypad",
+        .num_resources  = ARRAY_SIZE(keypad_resources),
+        .resource       = keypad_resources,
+};
+
+static struct resource tsc_resources[] = {
+        {
+                .start  = TNETV107X_TSC_BASE,
+                .end    = TNETV107X_TSC_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_TNETV107X_TSC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tsc_device = {
+        .name           = "tnetv107x-ts",
+        .num_resources  = ARRAY_SIZE(tsc_resources),
+        .resource       = tsc_resources,
+};
+
+static struct resource ssp_resources[] = {
+        {
+                .start  = TNETV107X_SSP_BASE,
+                .end    = TNETV107X_SSP_BASE + 0x1ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_TNETV107X_SSP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ssp_device = {
+        .name           = "ti-ssp",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ssp_resources),
+        .resource       = ssp_resources,
+};
+
 void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
 {
-        int i;
+        int i, error;
+        struct clk *tsc_clk;
+
+        /*
+         * The reset defaults for tnetv107x tsc clock divider is set too high.
+         * This forces the clock down to a range that allows the ADC to
+         * complete sample conversion in time.
+         */
+        tsc_clk = clk_get(NULL, "sys_tsc_clk");
+        if (tsc_clk) {
+                error = clk_set_rate(tsc_clk, 5000000);
+                WARN_ON(error < 0);
+                clk_put(tsc_clk);
+        }
 
         platform_device_register(&edma_device);
         platform_device_register(&tnetv107x_wdt_device);
+        platform_device_register(&tsc_device);
 
         if (info->serial_config)
                 davinci_serial_init(info->serial_config);
@@ -317,4 +395,14 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
         for (i = 0; i < 4; i++)
                 if (info->nand_config[i])
                         nand_init(i, info->nand_config[i]);
+
+        if (info->keypad_config) {
+                keypad_device.dev.platform_data = info->keypad_config;
+                platform_device_register(&keypad_device);
+        }
+
+        if (info->ssp_config) {
+                ssp_device.dev.platform_data = info->ssp_config;
+                platform_device_register(&ssp_device);
+        }
 }
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 8b7201e4c79c..806a2f02b980 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -33,6 +33,9 @@
 #define DM365_MMCSD0_BASE            0x01D11000
 #define DM365_MMCSD1_BASE            0x01D00000
 
+/* System control register offsets */
+#define DM64XX_VDD3P3V_PWDN     0x48
+
 static struct resource i2c_resources[] = {
         {
                 .start          = DAVINCI_I2C_BASE,
@@ -213,7 +216,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                                 IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
 
                         /* Configure pull down control */
-                        __raw_writel((__raw_readl(pupdctl1) & ~0x400),
+                        __raw_writel((__raw_readl(pupdctl1) & ~0xfc0),
                                         pupdctl1);
 
                         mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
@@ -295,6 +298,18 @@ static void davinci_init_wdt(void)
 
 /*-------------------------------------------------------------------------*/
 
+static struct platform_device davinci_pcm_device = {
+        .name           = "davinci-pcm-audio",
+        .id             = -1,
+};
+
+static void davinci_init_pcm(void)
+{
+        platform_device_register(&davinci_pcm_device);
+}
+
+/*-------------------------------------------------------------------------*/
+
 struct davinci_timer_instance davinci_timer_instance[2] = {
         {
                 .base           = DAVINCI_TIMER0_BASE,
@@ -315,6 +330,7 @@ static int __init davinci_init_devices(void)
         /* please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
+        davinci_init_pcm();
         davinci_init_wdt();
 
         return 0;
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 9be261beae7d..a3a94e9c9378 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -314,7 +314,7 @@ static struct clk timer2_clk = {
         .name = "timer2",
         .parent = &pll1_aux_clk,
         .lpsc = DAVINCI_LPSC_TIMER2,
-        .usecount = 1,              /* REVISIT: why cant' this be disabled? */
+        .usecount = 1,              /* REVISIT: why can't this be disabled? */
 };
 
 static struct clk timer3_clk = {
@@ -359,8 +359,8 @@ static struct clk_lookup dm355_clks[] = {
         CLK(NULL, "uart1", &uart1_clk),
         CLK(NULL, "uart2", &uart2_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
-        CLK("davinci-asp.0", NULL, &asp0_clk),
-        CLK("davinci-asp.1", NULL, &asp1_clk),
+        CLK("davinci-mcbsp.0", NULL, &asp0_clk),
+        CLK("davinci-mcbsp.1", NULL, &asp1_clk),
         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
         CLK("spi_davinci.0", NULL, &spi0_clk),
@@ -403,21 +403,13 @@ static struct resource dm355_spi0_resources[] = {
                 .start = 16,
                 .flags = IORESOURCE_DMA,
         },
-        {
-                .start = EVENTQ_1,
-                .flags = IORESOURCE_DMA,
-        },
 };
 
 static struct davinci_spi_platform_data dm355_spi0_pdata = {
         .version        = SPI_VERSION_1,
         .num_chipselect = 2,
-        .clk_internal   = 1,
-        .cs_hold        = 1,
-        .intr_level     = 0,
-        .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
-        .c2tdelay       = 0,
-        .t2cdelay       = 0,
+        .cshold_bug     = true,
+        .dma_event_q    = EVENTQ_1,
 };
 static struct platform_device dm355_spi0_device = {
         .name = "spi_davinci",
@@ -664,7 +656,7 @@ static struct resource dm355_asp1_resources[] = {
 };
 
 static struct platform_device dm355_asp1_device = {
-        .name           = "davinci-asp",
+        .name           = "davinci-mcbsp",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
         .resource       = dm355_asp1_resources,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 7781e35daec3..4604e72d7d99 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -459,7 +459,7 @@ static struct clk_lookup dm365_clks[] = {
         CLK(NULL, "usb", &usb_clk),
         CLK("davinci_emac.1", NULL, &emac_clk),
         CLK("davinci_voicecodec", NULL, &voicecodec_clk),
-        CLK("davinci-asp.0", NULL, &asp0_clk),
+        CLK("davinci-mcbsp", NULL, &asp0_clk),
         CLK(NULL, "rto", &rto_clk),
         CLK(NULL, "mjcp", &mjcp_clk),
         CLK(NULL, NULL, NULL),
@@ -625,12 +625,7 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 static struct davinci_spi_platform_data dm365_spi0_pdata = {
         .version        = SPI_VERSION_1,
         .num_chipselect = 2,
-        .clk_internal   = 1,
-        .cs_hold        = 1,
-        .intr_level     = 0,
-        .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
-        .c2tdelay       = 0,
-        .t2cdelay       = 0,
+        .dma_event_q    = EVENTQ_3,
 };
 
 static struct resource dm365_spi0_resources[] = {
@@ -651,10 +646,6 @@ static struct resource dm365_spi0_resources[] = {
                 .start = 16,
                 .flags = IORESOURCE_DMA,
         },
-        {
-                .start = EVENTQ_3,
-                .flags = IORESOURCE_DMA,
-        },
 };
 
 static struct platform_device dm365_spi0_device = {
@@ -691,7 +682,6 @@ static struct emac_platform_data dm365_emac_pdata = {
         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
-        .mdio_reg_offset        = DM365_EMAC_MDIO_OFFSET,
         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
         .version                = EMAC_VERSION_2,
 };
@@ -699,7 +689,7 @@ static struct emac_platform_data dm365_emac_pdata = {
 static struct resource dm365_emac_resources[] = {
         {
                 .start  = DM365_EMAC_BASE,
-                .end    = DM365_EMAC_BASE + 0x47ff,
+                .end    = DM365_EMAC_BASE + SZ_16K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -734,6 +724,21 @@ static struct platform_device dm365_emac_device = {
         .resource       = dm365_emac_resources,
 };
 
+static struct resource dm365_mdio_resources[] = {
+        {
+                .start  = DM365_EMAC_MDIO_BASE,
+                .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm365_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
+        .resource       = dm365_mdio_resources,
+};
+
 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
         [IRQ_VDINT0]                    = 2,
         [IRQ_VDINT1]                    = 6,
@@ -908,8 +913,8 @@ static struct resource dm365_asp_resources[] = {
 };
 
 static struct platform_device dm365_asp_device = {
-        .name           = "davinci-asp",
-        .id             = 0,
+        .name           = "davinci-mcbsp",
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
         .resource       = dm365_asp_resources,
 };
@@ -1219,7 +1224,12 @@ static int __init dm365_init_devices(void)
 
         davinci_cfg_reg(DM365_INT_EDMA_CC);
         platform_device_register(&dm365_edma_device);
+
+        platform_device_register(&dm365_mdio_device);
         platform_device_register(&dm365_emac_device);
+        clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
+                      NULL, &dm365_emac_device.dev);
+
         /* Add isif clock alias */
         clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
         platform_device_register(&dm365_vpss_device);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 5e5b0a7831fb..4c82c2716293 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -274,7 +274,7 @@ static struct clk timer2_clk = {
         .name = "timer2",
         .parent = &pll1_aux_clk,
         .lpsc = DAVINCI_LPSC_TIMER2,
-        .usecount = 1,              /* REVISIT: why cant' this be disabled? */
+        .usecount = 1,              /* REVISIT: why can't this be disabled? */
 };
 
 static struct clk_lookup dm644x_clks[] = {
@@ -302,7 +302,7 @@ static struct clk_lookup dm644x_clks[] = {
         CLK("davinci_emac.1", NULL, &emac_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("palm_bk3710", NULL, &ide_clk),
-        CLK("davinci-asp", NULL, &asp_clk),
+        CLK("davinci-mcbsp", NULL, &asp_clk),
         CLK("davinci_mmc.0", NULL, &mmcsd_clk),
         CLK(NULL, "spi", &spi_clk),
         CLK(NULL, "gpio", &gpio_clk),
@@ -322,7 +322,6 @@ static struct emac_platform_data dm644x_emac_pdata = {
         .ctrl_reg_offset        = DM644X_EMAC_CNTRL_OFFSET,
         .ctrl_mod_reg_offset    = DM644X_EMAC_CNTRL_MOD_OFFSET,
         .ctrl_ram_offset        = DM644X_EMAC_CNTRL_RAM_OFFSET,
-        .mdio_reg_offset        = DM644X_EMAC_MDIO_OFFSET,
         .ctrl_ram_size          = DM644X_EMAC_CNTRL_RAM_SIZE,
         .version                = EMAC_VERSION_1,
 };
@@ -330,7 +329,7 @@ static struct emac_platform_data dm644x_emac_pdata = {
 static struct resource dm644x_emac_resources[] = {
         {
                 .start  = DM644X_EMAC_BASE,
-                .end    = DM644X_EMAC_BASE + 0x47ff,
+                .end    = DM644X_EMAC_BASE + SZ_16K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -350,6 +349,21 @@ static struct platform_device dm644x_emac_device = {
        .resource        = dm644x_emac_resources,
 };
 
+static struct resource dm644x_mdio_resources[] = {
+        {
+                .start  = DM644X_EMAC_MDIO_BASE,
+                .end    = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm644x_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm644x_mdio_resources),
+        .resource       = dm644x_mdio_resources,
+};
+
 /*
  * Device specific mux setup
  *
@@ -566,7 +580,7 @@ static struct resource dm644x_asp_resources[] = {
 };
 
 static struct platform_device dm644x_asp_device = {
-        .name           = "davinci-asp",
+        .name           = "davinci-mcbsp",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(dm644x_asp_resources),
         .resource       = dm644x_asp_resources,
@@ -776,7 +790,12 @@ static int __init dm644x_init_devices(void)
         clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
         clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
         platform_device_register(&dm644x_edma_device);
+
+        platform_device_register(&dm644x_mdio_device);
         platform_device_register(&dm644x_emac_device);
+        clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
+                      NULL, &dm644x_emac_device.dev);
+
         platform_device_register(&dm644x_vpss_device);
         platform_device_register(&dm644x_ccdc_dev);
         platform_device_register(&vpfe_capture_dev);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 26e8a9c7f50b..1e0f809644bb 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -358,7 +358,6 @@ static struct emac_platform_data dm646x_emac_pdata = {
         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
-        .mdio_reg_offset        = DM646X_EMAC_MDIO_OFFSET,
         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
         .version                = EMAC_VERSION_2,
 };
@@ -366,7 +365,7 @@ static struct emac_platform_data dm646x_emac_pdata = {
 static struct resource dm646x_emac_resources[] = {
         {
                 .start  = DM646X_EMAC_BASE,
-                .end    = DM646X_EMAC_BASE + 0x47ff,
+                .end    = DM646X_EMAC_BASE + SZ_16K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -401,6 +400,21 @@ static struct platform_device dm646x_emac_device = {
         .resource       = dm646x_emac_resources,
 };
 
+static struct resource dm646x_mdio_resources[] = {
+        {
+                .start  = DM646X_EMAC_MDIO_BASE,
+                .end    = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm646x_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm646x_mdio_resources),
+        .resource       = dm646x_mdio_resources,
+};
+
 /*
  * Device specific mux setup
  *
@@ -896,7 +910,11 @@ static int __init dm646x_init_devices(void)
         if (!cpu_is_davinci_dm646x())
                 return 0;
 
+        platform_device_register(&dm646x_mdio_device);
         platform_device_register(&dm646x_emac_device);
+        clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
+                      NULL, &dm646x_emac_device.dev);
+
         return 0;
 }
 postcore_initcall(dm646x_init_devices);
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 2ede598b77dd..6b9669869c46 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -354,10 +354,12 @@ static int irq2ctlr(int irq)
 static irqreturn_t dma_irq_handler(int irq, void *data)
 {
         int i;
-        unsigned ctlr;
+        int ctlr;
         unsigned int cnt = 0;
 
         ctlr = irq2ctlr(irq);
+        if (ctlr < 0)
+                return IRQ_NONE;
 
         dev_dbg(data, "dma_irq_handler\n");
 
@@ -408,10 +410,12 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 static irqreturn_t dma_ccerr_handler(int irq, void *data)
 {
         int i;
-        unsigned ctlr;
+        int ctlr;
         unsigned int cnt = 0;
 
         ctlr = irq2ctlr(irq);
+        if (ctlr < 0)
+                return IRQ_NONE;
 
         dev_dbg(data, "dma_ccerr_handler\n");
 
diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c
index d10298620e2c..3fa3e2867e19 100644
--- a/arch/arm/mach-davinci/gpio-tnetv107x.c
+++ b/arch/arm/mach-davinci/gpio-tnetv107x.c
@@ -58,7 +58,7 @@ static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
 
         spin_lock_irqsave(&ctlr->lock, flags);
 
-        gpio_reg_set_bit(&regs->enable, gpio);
+        gpio_reg_set_bit(regs->enable, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 
@@ -74,7 +74,7 @@ static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
 
         spin_lock_irqsave(&ctlr->lock, flags);
 
-        gpio_reg_clear_bit(&regs->enable, gpio);
+        gpio_reg_clear_bit(regs->enable, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 }
@@ -88,7 +88,7 @@ static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
 
         spin_lock_irqsave(&ctlr->lock, flags);
 
-        gpio_reg_set_bit(&regs->direction, gpio);
+        gpio_reg_set_bit(regs->direction, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 
@@ -106,11 +106,11 @@ static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
         spin_lock_irqsave(&ctlr->lock, flags);
 
         if (value)
-                gpio_reg_set_bit(&regs->data_out, gpio);
+                gpio_reg_set_bit(regs->data_out, gpio);
         else
-                gpio_reg_clear_bit(&regs->data_out, gpio);
+                gpio_reg_clear_bit(regs->data_out, gpio);
 
-        gpio_reg_clear_bit(&regs->direction, gpio);
+        gpio_reg_clear_bit(regs->direction, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 
@@ -124,7 +124,7 @@ static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
         unsigned gpio = chip->base + offset;
         int ret;
 
-        ret = gpio_reg_get_bit(&regs->data_in, gpio);
+        ret = gpio_reg_get_bit(regs->data_in, gpio);
 
         return ret ? 1 : 0;
 }
@@ -140,9 +140,9 @@ static void tnetv107x_gpio_set(struct gpio_chip *chip,
         spin_lock_irqsave(&ctlr->lock, flags);
 
         if (value)
-                gpio_reg_set_bit(&regs->data_out, gpio);
+                gpio_reg_set_bit(regs->data_out, gpio);
         else
-                gpio_reg_clear_bit(&regs->data_out, gpio);
+                gpio_reg_clear_bit(regs->data_out, gpio);
 
         spin_unlock_irqrestore(&ctlr->lock, flags);
 }
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index bf0ff587e46a..cafbe13a82a5 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
 {
         struct davinci_gpio_regs __iomem *g;
 
-        g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
+        g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
 
         return g;
 }
@@ -205,20 +205,20 @@ pure_initcall(davinci_gpio_setup);
  * serve as EDMA event triggers.
  */
 
-static void gpio_irq_disable(unsigned irq)
+static void gpio_irq_disable(struct irq_data *d)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
-        u32 mask = (u32) get_irq_data(irq);
+        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        u32 mask = (u32) irq_data_get_irq_handler_data(d);
 
         __raw_writel(mask, &g->clr_falling);
         __raw_writel(mask, &g->clr_rising);
 }
 
-static void gpio_irq_enable(unsigned irq)
+static void gpio_irq_enable(struct irq_data *d)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
-        u32 mask = (u32) get_irq_data(irq);
-        unsigned status = irq_desc[irq].status;
+        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        u32 mask = (u32) irq_data_get_irq_handler_data(d);
+        unsigned status = irqd_get_trigger_type(d);
 
         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
         if (!status)
@@ -230,47 +230,42 @@ static void gpio_irq_enable(unsigned irq)
                 __raw_writel(mask, &g->set_rising);
 }
 
-static int gpio_irq_type(unsigned irq, unsigned trigger)
+static int gpio_irq_type(struct irq_data *d, unsigned trigger)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
-        u32 mask = (u32) get_irq_data(irq);
+        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        u32 mask = (u32) irq_data_get_irq_handler_data(d);
 
         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
                 return -EINVAL;
 
-        irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
-        irq_desc[irq].status |= trigger;
-
-        /* don't enable the IRQ if it's currently disabled */
-        if (irq_desc[irq].depth == 0) {
-                __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
-                             ? &g->set_falling : &g->clr_falling);
-                __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
-                             ? &g->set_rising : &g->clr_rising);
-        }
         return 0;
 }
 
 static struct irq_chip gpio_irqchip = {
         .name           = "GPIO",
-        .enable         = gpio_irq_enable,
-        .disable        = gpio_irq_disable,
-        .set_type       = gpio_irq_type,
+        .irq_enable     = gpio_irq_enable,
+        .irq_disable    = gpio_irq_disable,
+        .irq_set_type   = gpio_irq_type,
+        .flags          = IRQCHIP_SET_TYPE_MASKED,
 };
 
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
+        struct davinci_gpio_regs __iomem *g;
         u32 mask = 0xffff;
+        struct davinci_gpio_controller *d;
+
+        d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
+        g = (struct davinci_gpio_regs __iomem *)d->regs;
 
         /* we only care about one bank */
         if (irq & 1)
                 mask <<= 16;
 
         /* temporarily mask (level sensitive) parent IRQ */
-        desc->chip->mask(irq);
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_mask(&desc->irq_data);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
         while (1) {
                 u32             status;
                 int             n;
@@ -281,11 +276,14 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                 if (!status)
                         break;
                 __raw_writel(status, &g->intstat);
-                if (irq & 1)
-                        status >>= 16;
 
                 /* now demux them to the right lowlevel handler */
-                n = (int)get_irq_data(irq);
+                n = d->irq_base;
+                if (irq & 1) {
+                        n += 16;
+                        status >>= 16;
+                }
+
                 while (status) {
                         res = ffs(status);
                         n += res;
@@ -293,7 +291,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         status >>= res;
                 }
         }
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
         /* now it may re-trigger */
 }
 
@@ -320,10 +318,10 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
                 return -ENODEV;
 }
 
-static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
+static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
-        u32 mask = (u32) get_irq_data(irq);
+        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        u32 mask = (u32) irq_data_get_irq_handler_data(d);
 
         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
                 return -EINVAL;
@@ -395,9 +393,9 @@ static int __init davinci_gpio_irq_setup(void)
 
                 /* AINTC handles mask/unmask; GPIO handles triggering */
                 irq = bank_irq;
-                gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
+                gpio_irqchip_unbanked = *irq_get_chip(irq);
                 gpio_irqchip_unbanked.name = "GPIO-AINTC";
-                gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
+                gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
 
                 /* default trigger: both edges */
                 g = gpio2regs(0);
@@ -406,10 +404,10 @@ static int __init davinci_gpio_irq_setup(void)
 
                 /* set the direct IRQs up to use that irqchip */
                 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
-                        set_irq_chip(irq, &gpio_irqchip_unbanked);
-                        set_irq_data(irq, (void *) __gpio_mask(gpio));
-                        set_irq_chip_data(irq, (__force void *) g);
-                        irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
+                        irq_set_chip(irq, &gpio_irqchip_unbanked);
+                        irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
+                        irq_set_chip_data(irq, (__force void *)g);
+                        irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
                 }
 
                 goto done;
@@ -430,15 +428,20 @@ static int __init davinci_gpio_irq_setup(void)
                 __raw_writel(~0, &g->clr_rising);
 
                 /* set up all irqs in this bank */
-                set_irq_chained_handler(bank_irq, gpio_irq_handler);
-                set_irq_chip_data(bank_irq, (__force void *) g);
-                set_irq_data(bank_irq, (void *) irq);
+                irq_set_chained_handler(bank_irq, gpio_irq_handler);
+
+                /*
+                 * Each chip handles 32 gpios, and each irq bank consists of 16
+                 * gpio irqs. Pass the irq bank's corresponding controller to
+                 * the chained irq handler.
+                 */
+                irq_set_handler_data(bank_irq, &chips[gpio / 32]);
 
                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
-                        set_irq_chip(irq, &gpio_irqchip);
-                        set_irq_chip_data(irq, (__force void *) g);
-                        set_irq_data(irq, (void *) __gpio_mask(gpio));
-                        set_irq_handler(irq, handle_simple_irq);
+                        irq_set_chip(irq, &gpio_irqchip);
+                        irq_set_chip_data(irq, (__force void *)g);
+                        irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
+                        irq_set_handler(irq, handle_simple_irq);
                         set_irq_flags(irq, IRQF_VALID);
                 }
 
diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h
new file mode 100644
index 000000000000..05b293443097
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/aemif.h
@@ -0,0 +1,36 @@
+/*
+ * TI DaVinci AEMIF support
+ *
+ * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef _MACH_DAVINCI_AEMIF_H
+#define _MACH_DAVINCI_AEMIF_H
+
+#define NRCSR_OFFSET            0x00
+#define AWCCR_OFFSET            0x04
+#define A1CR_OFFSET             0x10
+
+#define ACR_ASIZE_MASK          0x3
+#define ACR_EW_MASK             BIT(30)
+#define ACR_SS_MASK             BIT(31)
+
+/* All timings in nanoseconds */
+struct davinci_aemif_timing {
+        u8      wsetup;
+        u8      wstrobe;
+        u8      whold;
+
+        u8      rsetup;
+        u8      rstrobe;
+        u8      rhold;
+
+        u8      ta;
+};
+
+int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+                                        void __iomem *base, unsigned cs);
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
index 730c49d1ebd8..14a504887189 100644
--- a/arch/arm/mach-davinci/include/mach/clkdev.h
+++ b/arch/arm/mach-davinci/include/mach/clkdev.h
@@ -1,6 +1,8 @@
 #ifndef __MACH_CLKDEV_H
 #define __MACH_CLKDEV_H
 
+struct clk;
+
 static inline int __clk_get(struct clk *clk)
 {
         return 1;
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index cea6b8972043..957fb87e832e 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -4,7 +4,7 @@
  * Author: Kevin Hilman, Deep Root Systems, LLC
  *
  * Defines the cpu_is_*() macros for runtime detection of DaVinci
- * device type.  In addtion, if support for a given device is not
+ * device type.  In addition, if support for a given device is not
  * compiled in to the kernel, the macros return 0 so that
  * resulting code can be optimized out.
  *
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 3c07059f526e..ad64da713fc8 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -15,6 +15,7 @@
 
 #include <linux/platform_device.h>
 #include <linux/davinci_emac.h>
+#include <linux/spi/spi.h>
 
 #include <mach/serial.h>
 #include <mach/edma.h>
@@ -23,11 +24,19 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 #include <mach/pm.h>
+#include <mach/spi.h>
 
 extern void __iomem *da8xx_syscfg0_base;
 extern void __iomem *da8xx_syscfg1_base;
 
 /*
+ * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
+ * (than the regular 300Mhz variant), the board code should set this up
+ * with the supported speed before calling da850_register_cpufreq().
+ */
+extern unsigned int da850_max_speed;
+
+/*
  * The cp_intc interrupt controller for the da8xx isn't in the same
  * chunk of physical memory space as the other registers (like it is
  * on the davincis) so it needs to be mapped separately.  It will be
@@ -55,13 +64,9 @@ extern void __iomem *da8xx_syscfg1_base;
 #define DA8XX_TIMER64P1_BASE    0x01c21000
 #define DA8XX_GPIO_BASE         0x01e26000
 #define DA8XX_PSC1_BASE         0x01e27000
-#define DA8XX_LCD_CNTRL_BASE    0x01e13000
-#define DA8XX_PLL1_BASE         0x01e1a000
-#define DA8XX_MMCSD0_BASE       0x01c40000
 #define DA8XX_AEMIF_CS2_BASE    0x60000000
 #define DA8XX_AEMIF_CS3_BASE    0x62000000
 #define DA8XX_AEMIF_CTL_BASE    0x68000000
-#define DA8XX_DDR2_CTL_BASE     0xb0000000
 #define DA8XX_ARM_RAM_BASE      0xffff0000
 
 void __init da830_init(void);
@@ -70,15 +75,17 @@ void __init da850_init(void);
 int da830_register_edma(struct edma_rsv_info *rsv);
 int da850_register_edma(struct edma_rsv_info *rsv[2]);
 int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
+int da8xx_register_spi(int instance, struct spi_board_info *info, unsigned len);
 int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
 int da8xx_register_emac(void);
 int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
 int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
+int da850_register_mmcsd1(struct davinci_mmc_config *config);
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
-int da850_register_cpufreq(void);
+int da850_register_cpufreq(char *async_clk);
 int da8xx_register_cpuidle(void);
 void __iomem * __init da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
@@ -87,6 +94,7 @@ extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
+extern struct davinci_spi_platform_data da8xx_spi_pdata[];
 
 extern struct platform_device da8xx_wdt_device;
 
@@ -115,17 +123,8 @@ extern const short da830_ecap2_pins[];
 extern const short da830_eqep0_pins[];
 extern const short da830_eqep1_pins[];
 
-extern const short da850_uart0_pins[];
-extern const short da850_uart1_pins[];
-extern const short da850_uart2_pins[];
 extern const short da850_i2c0_pins[];
 extern const short da850_i2c1_pins[];
-extern const short da850_cpgmac_pins[];
-extern const short da850_rmii_pins[];
-extern const short da850_mcasp_pins[];
 extern const short da850_lcdcntl_pins[];
-extern const short da850_mmcsd0_pins[];
-extern const short da850_nand_pins[];
-extern const short da850_nor_pins[];
 
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index f761dfdb8689..f8b7ea4f6235 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -24,40 +24,47 @@
 
 #define UART_SHIFT      2
 
+#define davinci_uart_v2p(x)     ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
+#define davinci_uart_p2v(x)     ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
+
                 .pushsection .data
 davinci_uart_phys:      .word   0
 davinci_uart_virt:      .word   0
                 .popsection
 
-                .macro addruart, rx, tmp
+                .macro addruart, rp, rv
 
                 /* Use davinci_uart_phys/virt if already configured */
-10:             mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =__virt_to_phys(davinci_uart_phys)
-                ldrne   \rx, =davinci_uart_virt
-                ldr     \rx, [\rx]
-                cmp     \rx, #0                 @ is port configured?
+10:             mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                ldreq   \rp, =davinci_uart_v2p(davinci_uart_phys)
+                ldrne   \rp, =davinci_uart_phys
+                add     \rv, \rp, #4            @ davinci_uart_virt
+                ldr     \rp, [\rp, #0]
+                ldr     \rv, [\rv, #0]
+                cmp     \rp, #0                 @ is port configured?
+                cmpne   \rv, #0
                 bne     99f                     @ already configured
 
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
+                /* Check the debug UART address set in uncompress.h */
+                mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
 
                 /* Copy uart phys address from decompressor uart info */
-                ldreq   \tmp, =__virt_to_phys(davinci_uart_phys)
-                ldrne   \tmp, =davinci_uart_phys
-                ldreq   \rx, =DAVINCI_UART_INFO
-                ldrne   \rx, =__phys_to_virt(DAVINCI_UART_INFO)
-                ldr     \rx, [\rx, #0]
-                str     \rx, [\tmp]
+                ldreq   \rv, =davinci_uart_v2p(davinci_uart_phys)
+                ldrne   \rv, =davinci_uart_phys
+                ldreq   \rp, =DAVINCI_UART_INFO
+                ldrne   \rp, =davinci_uart_p2v(DAVINCI_UART_INFO)
+                ldr     \rp, [\rp, #0]
+                str     \rp, [\rv]
 
                 /* Copy uart virt address from decompressor uart info */
-                ldreq   \tmp, =__virt_to_phys(davinci_uart_virt)
-                ldrne   \tmp, =davinci_uart_virt
-                ldreq   \rx, =DAVINCI_UART_INFO
-                ldrne   \rx, =__phys_to_virt(DAVINCI_UART_INFO)
-                ldr     \rx, [\rx, #4]
-                str     \rx, [\tmp]
+                ldreq   \rv, =davinci_uart_v2p(davinci_uart_virt)
+                ldrne   \rv, =davinci_uart_virt
+                ldreq   \rp, =DAVINCI_UART_INFO
+                ldrne   \rp, =davinci_uart_p2v(DAVINCI_UART_INFO)
+                ldr     \rp, [\rp, #4]
+                str     \rp, [\rv]
 
                 b       10b
 99:
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index ea5df3b49ec4..2563bf4e93a1 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -21,10 +21,10 @@
 #include <media/davinci/vpfe_capture.h>
 
 #define DM365_EMAC_BASE                 (0x01D07000)
+#define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
 #define DM365_EMAC_CNTRL_OFFSET         (0x0000)
 #define DM365_EMAC_CNTRL_MOD_OFFSET     (0x3000)
 #define DM365_EMAC_CNTRL_RAM_OFFSET     (0x1000)
-#define DM365_EMAC_MDIO_OFFSET          (0x4000)
 #define DM365_EMAC_CNTRL_RAM_SIZE       (0x2000)
 
 /* Base of key scan register bank */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 6fca568a0fd2..5a1b26d4e68b 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -28,10 +28,10 @@
 #include <media/davinci/vpfe_capture.h>
 
 #define DM644X_EMAC_BASE                (0x01C80000)
+#define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
 #define DM644X_EMAC_CNTRL_OFFSET        (0x0000)
 #define DM644X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
 #define DM644X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
-#define DM644X_EMAC_MDIO_OFFSET         (0x4000)
 #define DM644X_EMAC_CNTRL_RAM_SIZE      (0x2000)
 
 #define DM644X_ASYNC_EMIF_CONTROL_BASE  0x01E00000
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 0a27ee9a70e1..7a27f3f13913 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -19,10 +19,10 @@
 #include <linux/davinci_emac.h>
 
 #define DM646X_EMAC_BASE                (0x01C80000)
+#define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
 #define DM646X_EMAC_CNTRL_OFFSET        (0x0000)
 #define DM646X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
 #define DM646X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
-#define DM646X_EMAC_MDIO_OFFSET         (0x4000)
 #define DM646X_EMAC_CNTRL_RAM_SIZE      (0x2000)
 
 #define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index dc10ef6cf572..20c77f29bf0f 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -151,42 +151,6 @@ struct edmacc_param {
 #define DA830_DMACH2EVENT_MAP1          0x00000000u
 #define DA830_EDMA_ARM_OWN              0x30FFCCFFu
 
-/* DA830 specific EDMA3 Events Information */
-enum DA830_edma_ch {
-        DA830_DMACH_MCASP0_RX,
-        DA830_DMACH_MCASP0_TX,
-        DA830_DMACH_MCASP1_RX,
-        DA830_DMACH_MCASP1_TX,
-        DA830_DMACH_MCASP2_RX,
-        DA830_DMACH_MCASP2_TX,
-        DA830_DMACH_GPIO_BNK0INT,
-        DA830_DMACH_GPIO_BNK1INT,
-        DA830_DMACH_UART0_RX,
-        DA830_DMACH_UART0_TX,
-        DA830_DMACH_TMR64P0_EVTOUT12,
-        DA830_DMACH_TMR64P0_EVTOUT34,
-        DA830_DMACH_UART1_RX,
-        DA830_DMACH_UART1_TX,
-        DA830_DMACH_SPI0_RX,
-        DA830_DMACH_SPI0_TX,
-        DA830_DMACH_MMCSD_RX,
-        DA830_DMACH_MMCSD_TX,
-        DA830_DMACH_SPI1_RX,
-        DA830_DMACH_SPI1_TX,
-        DA830_DMACH_DMAX_EVTOUT6,
-        DA830_DMACH_DMAX_EVTOUT7,
-        DA830_DMACH_GPIO_BNK2INT,
-        DA830_DMACH_GPIO_BNK3INT,
-        DA830_DMACH_I2C0_RX,
-        DA830_DMACH_I2C0_TX,
-        DA830_DMACH_I2C1_RX,
-        DA830_DMACH_I2C1_TX,
-        DA830_DMACH_GPIO_BNK4INT,
-        DA830_DMACH_GPIO_BNK5INT,
-        DA830_DMACH_UART2_RX,
-        DA830_DMACH_UART2_TX
-};
-
 /*ch_status paramater of callback function possible values*/
 #define DMA_COMPLETE 1
 #define DMA_CC_ERROR 2
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index c45ba1f62a11..414e0b93e741 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -21,9 +21,6 @@
  */
 #define DAVINCI_SYSTEM_MODULE_BASE        0x01C40000
 
-/* System control register offsets */
-#define DM64XX_VDD3P3V_PWDN     0x48
-
 /*
  * I/O mapping
  */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 62b0a90309ad..d1b954955c12 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -22,8 +22,8 @@
 #define __mem_isa(a)            (a)
 
 #ifndef __ASSEMBLER__
-#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
-#define __arch_iounmap(v)       davinci_iounmap(v)
+#define __arch_ioremap          davinci_ioremap
+#define __arch_iounmap          davinci_iounmap
 
 void __iomem *davinci_ioremap(unsigned long phys, size_t size,
                               unsigned int type);
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 22eb97c1c30b..491249ef209c 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -26,9 +26,9 @@
 #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
 #error Cannot enable DaVinci and DA8XX platforms concurrently
 #elif defined(CONFIG_ARCH_DAVINCI_DA8XX)
-#define PHYS_OFFSET DA8XX_DDR_BASE
+#define PLAT_PHYS_OFFSET DA8XX_DDR_BASE
 #else
-#define PHYS_OFFSET DAVINCI_DDR_BASE
+#define PLAT_PHYS_OFFSET DAVINCI_DDR_BASE
 #endif
 
 #define DDR2_SDRCR_OFFSET       0xc
@@ -41,27 +41,11 @@
  */
 #define CONSISTENT_DMA_SIZE (14<<20)
 
-#ifndef __ASSEMBLY__
 /*
  * Restrict DMA-able region to workaround silicon bug.  The bug
  * restricts buffers available for DMA to video hardware to be
  * below 128M
  */
-static inline void
-__arch_adjust_zones(unsigned long *size, unsigned long *holes)
-{
-        unsigned int sz = (128<<20) >> PAGE_SHIFT;
-
-        size[1] = size[0] - sz;
-        size[0] = sz;
-}
-
-#define arch_adjust_zones(zone_size, holes) \
-        if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
-
-#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + (128<<20) - 1)
-#define MAX_DMA_ADDRESS         (PAGE_OFFSET + (128<<20))
-
-#endif
+#define ARM_DMA_ZONE_SIZE       SZ_128M
 
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index de11aac76a80..5d4e0fed828a 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -908,11 +908,15 @@ enum davinci_da850_index {
         DA850_NEMA_CS_2,
 
         /* GPIO function */
+        DA850_GPIO2_4,
         DA850_GPIO2_6,
         DA850_GPIO2_8,
         DA850_GPIO2_15,
+        DA850_GPIO3_12,
+        DA850_GPIO3_13,
         DA850_GPIO4_0,
         DA850_GPIO4_1,
+        DA850_GPIO6_13,
         DA850_RTC_ALARM,
 };
 
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
index b2ad8090bd10..025151049f05 100644
--- a/arch/arm/mach-davinci/include/mach/nand.h
+++ b/arch/arm/mach-davinci/include/mach/nand.h
@@ -30,9 +30,6 @@
 
 #include <linux/mtd/nand.h>
 
-#define NRCSR_OFFSET            0x00
-#define AWCCR_OFFSET            0x04
-#define A1CR_OFFSET             0x10
 #define NANDFCR_OFFSET          0x60
 #define NANDFSR_OFFSET          0x64
 #define NANDF1ECC_OFFSET        0x70
@@ -83,6 +80,9 @@ struct davinci_nand_pdata {		/* platform_data */
         /* Main and mirror bbt descriptor overrides */
         struct nand_bbt_descr   *bbt_td;
         struct nand_bbt_descr   *bbt_md;
+
+        /* Access timings */
+        struct davinci_aemif_timing     *timing;
 };
 
 #endif  /* __ARCH_ARM_DAVINCI_NAND_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 983da6e4554c..a47e6f29206e 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -150,7 +150,7 @@
 #define DA8XX_LPSC0_SCR0_SS             10
 #define DA8XX_LPSC0_SCR1_SS             11
 #define DA8XX_LPSC0_SCR2_SS             12
-#define DA8XX_LPSC0_DMAX                13
+#define DA8XX_LPSC0_PRUSS               13
 #define DA8XX_LPSC0_ARM                 14
 #define DA8XX_LPSC0_GEM                 15
 
@@ -172,6 +172,7 @@
 #define DA8XX_LPSC1_UART2               13
 #define DA8XX_LPSC1_LCDC                16
 #define DA8XX_LPSC1_PWM                 17
+#define DA850_LPSC1_MMC_SD1             18
 #define DA8XX_LPSC1_ECAP                20
 #define DA830_LPSC1_EQEP                21
 #define DA850_LPSC1_TPTC2               21
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 8051110b8ac3..c9e6ce185a66 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -22,7 +22,7 @@
  *
  * This area sits just below the page tables (see arch/arm/kernel/head.S).
  */
-#define DAVINCI_UART_INFO       (PHYS_OFFSET + 0x3ff8)
+#define DAVINCI_UART_INFO       (PLAT_PHYS_OFFSET + 0x3ff8)
 
 #define DAVINCI_UART0_BASE      (IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE      (IO_PHYS + 0x20400)
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
index 910efbf099c0..7af305b37868 100644
--- a/arch/arm/mach-davinci/include/mach/spi.h
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -19,26 +19,71 @@
 #ifndef __ARCH_ARM_DAVINCI_SPI_H
 #define __ARCH_ARM_DAVINCI_SPI_H
 
+#include <mach/edma.h>
+
+#define SPI_INTERN_CS   0xFF
+
 enum {
         SPI_VERSION_1, /* For DM355/DM365/DM6467 */
         SPI_VERSION_2, /* For DA8xx */
 };
 
+/**
+ * davinci_spi_platform_data - Platform data for SPI master device on DaVinci
+ *
+ * @version:    version of the SPI IP. Different DaVinci devices have slightly
+ *              varying versions of the same IP.
+ * @num_chipselect: number of chipselects supported by this SPI master
+ * @intr_line:  interrupt line used to connect the SPI IP to the ARM interrupt
+ *              controller withn the SoC. Possible values are 0 and 1.
+ * @chip_sel:   list of GPIOs which can act as chip-selects for the SPI.
+ *              SPI_INTERN_CS denotes internal SPI chip-select. Not necessary
+ *              to populate if all chip-selects are internal.
+ * @cshold_bug: set this to true if the SPI controller on your chip requires
+ *              a write to CSHOLD bit in between transfers (like in DM355).
+ * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
+ *              device on the bus.
+ */
 struct davinci_spi_platform_data {
-        u8      version;
-        u8      num_chipselect;
+        u8                      version;
+        u8                      num_chipselect;
+        u8                      intr_line;
+        u8                      *chip_sel;
+        bool                    cshold_bug;
+        enum dma_event_q        dma_event_q;
+};
+
+/**
+ * davinci_spi_config - Per-chip-select configuration for SPI slave devices
+ *
+ * @wdelay:     amount of delay between transmissions. Measured in number of
+ *              SPI module clocks.
+ * @odd_parity: polarity of parity flag at the end of transmit data stream.
+ *              0 - odd parity, 1 - even parity.
+ * @parity_enable: enable transmission of parity at end of each transmit
+ *              data stream.
+ * @io_type:    type of IO transfer. Choose between polled, interrupt and DMA.
+ * @timer_disable: disable chip-select timers (setup and hold)
+ * @c2tdelay:   chip-select setup time. Measured in number of SPI module clocks.
+ * @t2cdelay:   chip-select hold time. Measured in number of SPI module clocks.
+ * @t2edelay:   transmit data finished to SPI ENAn pin inactive time. Measured
+ *              in number of SPI clocks.
+ * @c2edelay:   chip-select active to SPI ENAn signal active time. Measured in
+ *              number of SPI clocks.
+ */
+struct davinci_spi_config {
         u8      wdelay;
         u8      odd_parity;
         u8      parity_enable;
-        u8      wait_enable;
+#define SPI_IO_TYPE_INTR        0
+#define SPI_IO_TYPE_POLL        1
+#define SPI_IO_TYPE_DMA         2
+        u8      io_type;
         u8      timer_disable;
-        u8      clk_internal;
-        u8      cs_hold;
-        u8      intr_level;
-        u8      poll_mode;
-        u8      use_dma;
         u8      c2tdelay;
         u8      t2cdelay;
+        u8      t2edelay;
+        u8      c2edelay;
 };
 
 #endif  /* __ARCH_ARM_DAVINCI_SPI_H */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index c72064733123..89c1fdc63c0b 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -33,6 +33,9 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/serial_8250.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/mfd/ti_ssp.h>
+
 #include <mach/mmc.h>
 #include <mach/nand.h>
 #include <mach/serial.h>
@@ -41,6 +44,8 @@ struct tnetv107x_device_info {
         struct davinci_uart_config      *serial_config;
         struct davinci_mmc_config       *mmc_config[2];  /* 2 controllers */
         struct davinci_nand_pdata       *nand_config[4]; /* 4 chipsels */
+        struct matrix_keypad_platform_data *keypad_config;
+        struct ti_ssp_data              *ssp_config;
 };
 
 extern struct platform_device tnetv107x_wdt_device;
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 15a6192ad6eb..78d80683cdc2 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -25,8 +25,7 @@
 
 #include <mach/serial.h>
 
-static u32 *uart;
-static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+u32 *uart;
 
 /* PORT_16C550A, in polled non-fifo mode */
 static void putc(char c)
@@ -44,6 +43,8 @@ static inline void flush(void)
 
 static inline void set_uart_info(u32 phys, void * __iomem virt)
 {
+        u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+
         uart = (u32 *)phys;
         uart_info[0] = phys;
         uart_info[1] = (u32)virt;
@@ -88,6 +89,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 /* DA8xx boards */
                 DEBUG_LL_DA8XX(davinci_da830_evm,       2);
                 DEBUG_LL_DA8XX(davinci_da850_evm,       2);
+                DEBUG_LL_DA8XX(mityomapl138,            1);
+                DEBUG_LL_DA8XX(omapl138_hawkboard,      2);
 
                 /* TNETV107x boards */
                 DEBUG_LL_TNETV107X(tnetv107x,           1);
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 784ddf3c5ad4..952dc126c390 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -29,8 +29,6 @@
 #include <mach/common.h>
 #include <asm/mach/irq.h>
 
-#define IRQ_BIT(irq)            ((irq) & 0x1f)
-
 #define FIQ_REG0_OFFSET         0x0000
 #define FIQ_REG1_OFFSET         0x0004
 #define IRQ_REG0_OFFSET         0x0008
@@ -42,78 +40,39 @@
 #define IRQ_INTPRI0_REG_OFFSET  0x0030
 #define IRQ_INTPRI7_REG_OFFSET  0x004C
 
-static inline unsigned int davinci_irq_readl(int offset)
-{
-        return __raw_readl(davinci_intc_base + offset);
-}
-
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
         __raw_writel(value, davinci_intc_base + offset);
 }
 
-/* Disable interrupt */
-static void davinci_mask_irq(unsigned int irq)
+static __init void
+davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 {
-        unsigned int mask;
-        u32 l;
-
-        mask = 1 << IRQ_BIT(irq);
-
-        if (irq > 31) {
-                l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-                l &= ~mask;
-                davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-        } else {
-                l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-                l &= ~mask;
-                davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-        }
-}
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
-/* Enable interrupt */
-static void davinci_unmask_irq(unsigned int irq)
-{
-        unsigned int mask;
-        u32 l;
-
-        mask = 1 << IRQ_BIT(irq);
-
-        if (irq > 31) {
-                l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-                l |= mask;
-                davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-        } else {
-                l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-                l |= mask;
-                davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
+        gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
+        if (!gc) {
+                pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
+                       __func__, irq_start);
+                return;
         }
-}
-
-/* EOI interrupt */
-static void davinci_ack_irq(unsigned int irq)
-{
-        unsigned int mask;
 
-        mask = 1 << IRQ_BIT(irq);
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack_set_bit;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
 
-        if (irq > 31)
-                davinci_irq_writel(mask, IRQ_REG1_OFFSET);
-        else
-                davinci_irq_writel(mask, IRQ_REG0_OFFSET);
+        ct->regs.ack = IRQ_REG0_OFFSET;
+        ct->regs.mask = IRQ_ENT_REG0_OFFSET;
+        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 
-static struct irq_chip davinci_irq_chip_0 = {
-        .name   = "AINTC",
-        .ack    = davinci_ack_irq,
-        .mask   = davinci_mask_irq,
-        .unmask = davinci_unmask_irq,
-};
-
 /* ARM Interrupt Controller Initialization */
 void __init davinci_irq_init(void)
 {
-        unsigned i;
+        unsigned i, j;
         const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
 
         davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
@@ -144,7 +103,6 @@ void __init davinci_irq_init(void)
         davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 
         for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
-                unsigned        j;
                 u32             pri;
 
                 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
@@ -152,13 +110,8 @@ void __init davinci_irq_init(void)
                 davinci_irq_writel(pri, i);
         }
 
-        /* set up genirq dispatch for ARM INTC */
-        for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
-                set_irq_chip(i, &davinci_irq_chip_0);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                if (i != IRQ_TINT1_TINT34)
-                        set_irq_handler(i, handle_edge_irq);
-                else
-                        set_irq_handler(i, handle_level_irq);
-        }
+        for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
+                davinci_alloc_gc(davinci_intc_base + j, i, 32);
+
+        irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
 }
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index fab953b43dea..1bd73a04be20 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -110,7 +110,7 @@ static int davinci_pm_enter(suspend_state_t state)
         return ret;
 }
 
-static struct platform_suspend_ops davinci_pm_ops = {
+static const struct platform_suspend_ops davinci_pm_ops = {
         .enter          = davinci_pm_enter,
         .valid          = suspend_valid_only_mem,
 };
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 1b15dbd0a77b..a41580400701 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -83,21 +83,16 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
                 pdctl1 = __raw_readl(psc_base + PDCTL1);
                 pdctl1 |= 0x100;
                 __raw_writel(pdctl1, psc_base + PDCTL1);
-
-                do {
-                        ptstat = __raw_readl(psc_base +
-                                               PTSTAT);
-                } while (!(((ptstat >> domain) & 1) == 0));
         } else {
                 ptcmd = 1 << domain;
                 __raw_writel(ptcmd, psc_base + PTCMD);
-
-                do {
-                        ptstat = __raw_readl(psc_base + PTSTAT);
-                } while (!(((ptstat >> domain) & 1) == 0));
         }
 
         do {
+                ptstat = __raw_readl(psc_base + PTSTAT);
+        } while (!(((ptstat >> domain) & 1) == 0));
+
+        do {
                 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
         } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
 
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 0f21c36e65dd..e1969ce904dc 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -272,15 +272,35 @@ static cycle_t read_cycles(struct clocksource *cs)
         return (cycles_t)timer32_read(t);
 }
 
+/*
+ * Kernel assumes that sched_clock can be called early but may not have
+ * things ready yet.
+ */
+static cycle_t read_dummy(struct clocksource *cs)
+{
+        return 0;
+}
+
+
 static struct clocksource clocksource_davinci = {
         .rating         = 300,
-        .read           = read_cycles,
+        .read           = read_dummy,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 24,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
 /*
+ * Overwrite weak default sched_clock with something more precise
+ */
+unsigned long long notrace sched_clock(void)
+{
+        const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci);
+
+        return clocksource_cyc2ns(cyc, clocksource_davinci.mult,
+                                clocksource_davinci.shift);
+}
+
+/*
  * clockevent
  */
 static int davinci_set_next_event(unsigned long cycles,
@@ -377,11 +397,10 @@ static void __init davinci_timer_init(void)
         davinci_clock_tick_rate = clk_get_rate(timer_clk);
 
         /* setup clocksource */
+        clocksource_davinci.read = read_cycles;
         clocksource_davinci.name = id_to_name[clocksource_id];
-        clocksource_davinci.mult =
-                clocksource_khz2mult(davinci_clock_tick_rate/1000,
-                                     clocksource_davinci.shift);
-        if (clocksource_register(&clocksource_davinci))
+        if (clocksource_register_hz(&clocksource_davinci,
+                                    davinci_clock_tick_rate))
                 printk(err, clocksource_davinci.name);
 
         /* setup clockevent */
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 864e60482c53..1b28fdd892a6 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -104,7 +104,7 @@ static u32 pll_ext_freq[] = {
 };
 
 /* PSC control registers */
-static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE };
+static u32 psc_regs[] = { TNETV107X_PSC_BASE };
 
 /* Host map for interrupt controller */
 static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
@@ -131,12 +131,13 @@ define_pll_clk(tdm, 1, 0x0ff, 0x200);
 define_pll_clk(eth, 2, 0x0ff, 0x400);
 
 /* Level 2 - divided outputs from the PLLs */
-#define define_pll_div_clk(pll, cname, div)             \
-        static struct clk pll##_##cname##_clk = {       \
-                .name           = #pll "_" #cname "_clk",\
-                .parent         = &pll_##pll##_clk,     \
-                .flags          = CLK_PLL,              \
-                .div_reg        = PLLDIV##div,          \
+#define define_pll_div_clk(pll, cname, div)                     \
+        static struct clk pll##_##cname##_clk = {               \
+                .name           = #pll "_" #cname "_clk",       \
+                .parent         = &pll_##pll##_clk,             \
+                .flags          = CLK_PLL,                      \
+                .div_reg        = PLLDIV##div,                  \
+                .set_rate       = davinci_set_sysclk_rate,      \
         }
 
 define_pll_div_clk(sys, arm1176,        1);
@@ -192,6 +193,7 @@ lpsc_clk_enabled(system,	sys_half_clk,	SYSTEM);
 lpsc_clk_enabled(ddr2_vrst,     sys_ddr_clk,    DDR2_EMIF1_VRST);
 lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk,    DDR2_EMIF2_VCTL_RST);
 lpsc_clk_enabled(wdt_arm,       sys_half_clk,   WDT_ARM);
+lpsc_clk_enabled(timer1,        sys_half_clk,   TIMER1);
 
 lpsc_clk(mbx_lite,      sys_arm1176_clk,        MBX_LITE);
 lpsc_clk(ethss,         eth_125mhz_clk,         ETHSS);
@@ -205,16 +207,15 @@ lpsc_clk(mdio,		sys_half_clk,		MDIO);
 lpsc_clk(sdio0,         sys_half_clk,           SDIO0);
 lpsc_clk(sdio1,         sys_half_clk,           SDIO1);
 lpsc_clk(timer0,        sys_half_clk,           TIMER0);
-lpsc_clk(timer1,        sys_half_clk,           TIMER1);
 lpsc_clk(wdt_dsp,       sys_half_clk,           WDT_DSP);
 lpsc_clk(ssp,           sys_half_clk,           SSP);
 lpsc_clk(tdm0,          tdm_0_clk,              TDM0);
 lpsc_clk(tdm1,          tdm_1_clk,              TDM1);
 lpsc_clk(vlynq,         sys_vlynq_ref_clk,      VLYNQ);
 lpsc_clk(mcdma,         sys_half_clk,           MCDMA);
-lpsc_clk(usb0,          sys_half_clk,           USB0);
-lpsc_clk(usb1,          sys_half_clk,           USB1);
 lpsc_clk(usbss,         sys_half_clk,           USBSS);
+lpsc_clk(usb0,          clk_usbss,              USB0);
+lpsc_clk(usb1,          clk_usbss,              USB1);
 lpsc_clk(ethss_rgmii,   eth_250mhz_clk,         ETHSS_RGMII);
 lpsc_clk(imcop,         sys_dsp_clk,            IMCOP);
 lpsc_clk(spare,         sys_half_clk,           SPARE);
@@ -277,11 +278,13 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "timer1",               &clk_timer1),
         CLK("tnetv107x_wdt.0",  NULL,                   &clk_wdt_arm),
         CLK(NULL,               "clk_wdt_dsp",          &clk_wdt_dsp),
-        CLK("ti-ssp.0",         NULL,                   &clk_ssp),
+        CLK("ti-ssp",           NULL,                   &clk_ssp),
         CLK(NULL,               "clk_tdm0",             &clk_tdm0),
         CLK(NULL,               "clk_vlynq",            &clk_vlynq),
         CLK(NULL,               "clk_mcdma",            &clk_mcdma),
+        CLK(NULL,               "clk_usbss",            &clk_usbss),
         CLK(NULL,               "clk_usb0",             &clk_usb0),
+        CLK(NULL,               "clk_usb1",             &clk_usb1),
         CLK(NULL,               "clk_tdm1",             &clk_tdm1),
         CLK(NULL,               "clk_debugss",          &clk_debugss),
         CLK(NULL,               "clk_ethss_rgmii",      &clk_ethss_rgmii),
@@ -289,8 +292,6 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_imcop",            &clk_imcop),
         CLK(NULL,               "clk_spare",            &clk_spare),
         CLK("davinci_mmc.1",    NULL,                   &clk_sdio1),
-        CLK(NULL,               "clk_usb1",             &clk_usb1),
-        CLK(NULL,               "clk_usbss",            &clk_usbss),
         CLK(NULL,               "clk_ddr2_vrst",        &clk_ddr2_vrst),
         CLK(NULL,               "clk_ddr2_vctl_rst",    &clk_ddr2_vctl_rst),
         CLK(NULL,               NULL,                   NULL),
@@ -581,7 +582,14 @@ static struct davinci_id ids[] = {
                 .part_no        = 0xb8a1,
                 .manufacturer   = 0x017,
                 .cpu_id         = DAVINCI_CPU_ID_TNETV107X,
-                .name           = "tnetv107x rev1.0",
+                .name           = "tnetv107x rev 1.0",
+        },
+        {
+                .variant        = 0x1,
+                .part_no        = 0xb8a1,
+                .manufacturer   = 0x017,
+                .cpu_id         = DAVINCI_CPU_ID_TNETV107X,
+                .name           = "tnetv107x rev 1.1/1.2",
         },
 };
 
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 31f0cbea0caa..23d2b6d9fa63 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -64,17 +64,19 @@ static struct resource usb_resources[] = {
         {
                 .start          = IRQ_USBINT,
                 .flags          = IORESOURCE_IRQ,
+                .name           = "mc"
         },
         {
                 /* placeholder for the dedicated CPPI IRQ */
                 .flags          = IORESOURCE_IRQ,
+                .name           = "dma"
         },
 };
 
 static u64 usb_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device usb_dev = {
-        .name           = "musb_hdrc",
+        .name           = "musb-davinci",
         .id             = -1,
         .dev = {
                 .platform_data          = &usb_data,
@@ -110,6 +112,7 @@ static struct resource da8xx_usb20_resources[] = {
         {
                 .start          = IRQ_DA8XX_USB_INT,
                 .flags          = IORESOURCE_IRQ,
+                .name           = "mc",
         },
 };
 
@@ -121,6 +124,7 @@ int __init da8xx_register_usb20(unsigned mA, unsigned potpgt)
 
         usb_dev.resource = da8xx_usb20_resources;
         usb_dev.num_resources = ARRAY_SIZE(da8xx_usb20_resources);
+        usb_dev.name = "musb-da8xx";
 
         return platform_device_register(&usb_dev);
 }