diff options
Diffstat (limited to 'arch/arm/mach-davinci/tnetv107x.c')
-rw-r--r-- | arch/arm/mach-davinci/tnetv107x.c | 36 |
1 files changed, 22 insertions, 14 deletions
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index 864e60482c53..1b28fdd892a6 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c | |||
@@ -104,7 +104,7 @@ static u32 pll_ext_freq[] = { | |||
104 | }; | 104 | }; |
105 | 105 | ||
106 | /* PSC control registers */ | 106 | /* PSC control registers */ |
107 | static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE }; | 107 | static u32 psc_regs[] = { TNETV107X_PSC_BASE }; |
108 | 108 | ||
109 | /* Host map for interrupt controller */ | 109 | /* Host map for interrupt controller */ |
110 | static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; | 110 | static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; |
@@ -131,12 +131,13 @@ define_pll_clk(tdm, 1, 0x0ff, 0x200); | |||
131 | define_pll_clk(eth, 2, 0x0ff, 0x400); | 131 | define_pll_clk(eth, 2, 0x0ff, 0x400); |
132 | 132 | ||
133 | /* Level 2 - divided outputs from the PLLs */ | 133 | /* Level 2 - divided outputs from the PLLs */ |
134 | #define define_pll_div_clk(pll, cname, div) \ | 134 | #define define_pll_div_clk(pll, cname, div) \ |
135 | static struct clk pll##_##cname##_clk = { \ | 135 | static struct clk pll##_##cname##_clk = { \ |
136 | .name = #pll "_" #cname "_clk",\ | 136 | .name = #pll "_" #cname "_clk", \ |
137 | .parent = &pll_##pll##_clk, \ | 137 | .parent = &pll_##pll##_clk, \ |
138 | .flags = CLK_PLL, \ | 138 | .flags = CLK_PLL, \ |
139 | .div_reg = PLLDIV##div, \ | 139 | .div_reg = PLLDIV##div, \ |
140 | .set_rate = davinci_set_sysclk_rate, \ | ||
140 | } | 141 | } |
141 | 142 | ||
142 | define_pll_div_clk(sys, arm1176, 1); | 143 | define_pll_div_clk(sys, arm1176, 1); |
@@ -192,6 +193,7 @@ lpsc_clk_enabled(system, sys_half_clk, SYSTEM); | |||
192 | lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); | 193 | lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); |
193 | lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); | 194 | lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); |
194 | lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); | 195 | lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); |
196 | lpsc_clk_enabled(timer1, sys_half_clk, TIMER1); | ||
195 | 197 | ||
196 | lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); | 198 | lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); |
197 | lpsc_clk(ethss, eth_125mhz_clk, ETHSS); | 199 | lpsc_clk(ethss, eth_125mhz_clk, ETHSS); |
@@ -205,16 +207,15 @@ lpsc_clk(mdio, sys_half_clk, MDIO); | |||
205 | lpsc_clk(sdio0, sys_half_clk, SDIO0); | 207 | lpsc_clk(sdio0, sys_half_clk, SDIO0); |
206 | lpsc_clk(sdio1, sys_half_clk, SDIO1); | 208 | lpsc_clk(sdio1, sys_half_clk, SDIO1); |
207 | lpsc_clk(timer0, sys_half_clk, TIMER0); | 209 | lpsc_clk(timer0, sys_half_clk, TIMER0); |
208 | lpsc_clk(timer1, sys_half_clk, TIMER1); | ||
209 | lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); | 210 | lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); |
210 | lpsc_clk(ssp, sys_half_clk, SSP); | 211 | lpsc_clk(ssp, sys_half_clk, SSP); |
211 | lpsc_clk(tdm0, tdm_0_clk, TDM0); | 212 | lpsc_clk(tdm0, tdm_0_clk, TDM0); |
212 | lpsc_clk(tdm1, tdm_1_clk, TDM1); | 213 | lpsc_clk(tdm1, tdm_1_clk, TDM1); |
213 | lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); | 214 | lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); |
214 | lpsc_clk(mcdma, sys_half_clk, MCDMA); | 215 | lpsc_clk(mcdma, sys_half_clk, MCDMA); |
215 | lpsc_clk(usb0, sys_half_clk, USB0); | ||
216 | lpsc_clk(usb1, sys_half_clk, USB1); | ||
217 | lpsc_clk(usbss, sys_half_clk, USBSS); | 216 | lpsc_clk(usbss, sys_half_clk, USBSS); |
217 | lpsc_clk(usb0, clk_usbss, USB0); | ||
218 | lpsc_clk(usb1, clk_usbss, USB1); | ||
218 | lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); | 219 | lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); |
219 | lpsc_clk(imcop, sys_dsp_clk, IMCOP); | 220 | lpsc_clk(imcop, sys_dsp_clk, IMCOP); |
220 | lpsc_clk(spare, sys_half_clk, SPARE); | 221 | lpsc_clk(spare, sys_half_clk, SPARE); |
@@ -277,11 +278,13 @@ static struct clk_lookup clks[] = { | |||
277 | CLK(NULL, "timer1", &clk_timer1), | 278 | CLK(NULL, "timer1", &clk_timer1), |
278 | CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), | 279 | CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), |
279 | CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp), | 280 | CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp), |
280 | CLK("ti-ssp.0", NULL, &clk_ssp), | 281 | CLK("ti-ssp", NULL, &clk_ssp), |
281 | CLK(NULL, "clk_tdm0", &clk_tdm0), | 282 | CLK(NULL, "clk_tdm0", &clk_tdm0), |
282 | CLK(NULL, "clk_vlynq", &clk_vlynq), | 283 | CLK(NULL, "clk_vlynq", &clk_vlynq), |
283 | CLK(NULL, "clk_mcdma", &clk_mcdma), | 284 | CLK(NULL, "clk_mcdma", &clk_mcdma), |
285 | CLK(NULL, "clk_usbss", &clk_usbss), | ||
284 | CLK(NULL, "clk_usb0", &clk_usb0), | 286 | CLK(NULL, "clk_usb0", &clk_usb0), |
287 | CLK(NULL, "clk_usb1", &clk_usb1), | ||
285 | CLK(NULL, "clk_tdm1", &clk_tdm1), | 288 | CLK(NULL, "clk_tdm1", &clk_tdm1), |
286 | CLK(NULL, "clk_debugss", &clk_debugss), | 289 | CLK(NULL, "clk_debugss", &clk_debugss), |
287 | CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), | 290 | CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), |
@@ -289,8 +292,6 @@ static struct clk_lookup clks[] = { | |||
289 | CLK(NULL, "clk_imcop", &clk_imcop), | 292 | CLK(NULL, "clk_imcop", &clk_imcop), |
290 | CLK(NULL, "clk_spare", &clk_spare), | 293 | CLK(NULL, "clk_spare", &clk_spare), |
291 | CLK("davinci_mmc.1", NULL, &clk_sdio1), | 294 | CLK("davinci_mmc.1", NULL, &clk_sdio1), |
292 | CLK(NULL, "clk_usb1", &clk_usb1), | ||
293 | CLK(NULL, "clk_usbss", &clk_usbss), | ||
294 | CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), | 295 | CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), |
295 | CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), | 296 | CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), |
296 | CLK(NULL, NULL, NULL), | 297 | CLK(NULL, NULL, NULL), |
@@ -581,7 +582,14 @@ static struct davinci_id ids[] = { | |||
581 | .part_no = 0xb8a1, | 582 | .part_no = 0xb8a1, |
582 | .manufacturer = 0x017, | 583 | .manufacturer = 0x017, |
583 | .cpu_id = DAVINCI_CPU_ID_TNETV107X, | 584 | .cpu_id = DAVINCI_CPU_ID_TNETV107X, |
584 | .name = "tnetv107x rev1.0", | 585 | .name = "tnetv107x rev 1.0", |
586 | }, | ||
587 | { | ||
588 | .variant = 0x1, | ||
589 | .part_no = 0xb8a1, | ||
590 | .manufacturer = 0x017, | ||
591 | .cpu_id = DAVINCI_CPU_ID_TNETV107X, | ||
592 | .name = "tnetv107x rev 1.1/1.2", | ||
585 | }, | 593 | }, |
586 | }; | 594 | }; |
587 | 595 | ||