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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 17:42:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 17:42:51 -0400
commit42daabf62bfa3c00974b43f030dadcf704c0db59 (patch)
tree255f279cad48557227d974d67cbbc8390d057404 /arch/arm/boot
parent0bf6a210a43f7118d858806200127e421649fc4e (diff)
parent8c3d913888cfb0066d62831969c3a992f7e4aba5 (diff)
Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Arnd Bergmann: "These are changes that arrived a little late before the merge window or that have multiple dependencies on previous branches so they did not fit into one of the earlier ones. There are 10 branches merged here, a total of 39 non-merge commits. Contents are a mixed bag for the above reasons: * Two new SoC platforms: ST microelectronics stixxxx and the TI 'Nspire' graphing calculator. These should have been in the 'soc' branch but were a little late * Support for the Exynos 5420 variant in mach-exynos, which is based on the other exynos branches to avoid conflicts. * Various small changes for sh-mobile, ux500 and davinci * Common clk support for MSM" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits) ARM: ux500: bail out on alien cpus ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins serial: sh-sci: Initialise variables before access in sci_set_termios() ARM: stih41x: Add B2020 board support ARM: stih41x: Add B2000 board support ARM: sti: Add DEBUG_LL console support ARM: sti: Add STiH416 SOC support ARM: sti: Add STiH415 SOC support ARM: msm: Migrate to common clock framework ARM: msm: Make proc_comm clock control into a platform driver ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver ARM: msm: Remove clock-7x30.h include file ARM: msm: Remove custom clk_set_{max,min}_rate() API ARM: msm: Remove custom clk_set_flags() API msm: iommu: Use clk_set_rate() instead of clk_set_min_rate() msm: iommu: Convert to clk_prepare/unprepare msm_sdcc: Convert to clk_prepare/unprepare usb: otg: msm: Convert to clk_prepare/unprepare msm_serial: Use devm_clk_get() and properly return errors msm_serial: Convert to clk_prepare/unprepare ...
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/Makefile8
-rw-r--r--arch/arm/boot/dts/da850-enbw-cmc.dts2
-rw-r--r--arch/arm/boot/dts/da850-evm.dts2
-rw-r--r--arch/arm/boot/dts/da850.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi111
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi78
-rw-r--r--arch/arm/boot/dts/exynos5420-pinctrl.dtsi680
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts33
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi148
-rw-r--r--arch/arm/boot/dts/nspire-classic.dtsi74
-rw-r--r--arch/arm/boot/dts/nspire-clp.dts45
-rw-r--r--arch/arm/boot/dts/nspire-cx.dts112
-rw-r--r--arch/arm/boot/dts/nspire-tp.dts44
-rw-r--r--arch/arm/boot/dts/nspire.dtsi175
-rw-r--r--arch/arm/boot/dts/st-pincfg.h71
-rw-r--r--arch/arm/boot/dts/stih415-b2000.dts15
-rw-r--r--arch/arm/boot/dts/stih415-b2020.dts15
-rw-r--r--arch/arm/boot/dts/stih415-clock.dtsi38
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi268
-rw-r--r--arch/arm/boot/dts/stih415.dtsi87
-rw-r--r--arch/arm/boot/dts/stih416-b2000.dts16
-rw-r--r--arch/arm/boot/dts/stih416-b2020.dts16
-rw-r--r--arch/arm/boot/dts/stih416-clock.dtsi41
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi295
-rw-r--r--arch/arm/boot/dts/stih416.dtsi96
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi41
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi42
-rw-r--r--arch/arm/boot/dts/stih41x.dtsi38
28 files changed, 2528 insertions, 67 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 962c0eee3039..641b3c9a7028 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
59 exynos5440-sd5v1.dtb \ 59 exynos5440-sd5v1.dtb \
60 exynos5250-smdk5250.dtb \ 60 exynos5250-smdk5250.dtb \
61 exynos5250-snow.dtb \ 61 exynos5250-snow.dtb \
62 exynos5420-smdk5420.dtb \
62 exynos5440-ssdk5440.dtb 63 exynos5440-ssdk5440.dtb
63dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 64dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
64 ecx-2000.dtb 65 ecx-2000.dtb
@@ -148,6 +149,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
148 imx28-sps1.dtb \ 149 imx28-sps1.dtb \
149 imx28-tx28.dtb 150 imx28-tx28.dtb
150dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb 151dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
152dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
153 nspire-tp.dtb \
154 nspire-clp.dtb
151dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ 155dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
152 omap3430-sdp.dtb \ 156 omap3430-sdp.dtb \
153 omap3-beagle.dtb \ 157 omap3-beagle.dtb \
@@ -197,6 +201,10 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
197 spear320-evb.dtb \ 201 spear320-evb.dtb \
198 spear320-hmi.dtb 202 spear320-hmi.dtb
199dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 203dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
204dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
205 stih416-b2000.dtb \
206 stih415-b2020.dtb \
207 stih416-b2020.dtb
200dtb-$(CONFIG_ARCH_SUNXI) += \ 208dtb-$(CONFIG_ARCH_SUNXI) += \
201 sun4i-a10-cubieboard.dtb \ 209 sun4i-a10-cubieboard.dtb \
202 sun4i-a10-mini-xplus.dtb \ 210 sun4i-a10-mini-xplus.dtb \
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
index 422fdb3fcfc1..e750ab9086d5 100644
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -10,7 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12/dts-v1/; 12/dts-v1/;
13/include/ "da850.dtsi" 13#include "da850.dtsi"
14 14
15/ { 15/ {
16 compatible = "enbw,cmc", "ti,da850"; 16 compatible = "enbw,cmc", "ti,da850";
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c914357c0d89..5bce7cc55cf3 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -8,7 +8,7 @@
8 * Free Software Foundation, version 2. 8 * Free Software Foundation, version 2.
9 */ 9 */
10/dts-v1/; 10/dts-v1/;
11/include/ "da850.dtsi" 11#include "da850.dtsi"
12 12
13/ { 13/ {
14 compatible = "ti,da850-evm", "ti,da850"; 14 compatible = "ti,da850-evm", "ti,da850";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 2c88313d2c7a..d70ba5504481 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -7,7 +7,7 @@
7 * Free Software Foundation; either version 2 of the License, or (at your 7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version. 8 * option) any later version.
9 */ 9 */
10/include/ "skeleton.dtsi" 10#include "skeleton.dtsi"
11 11
12/ { 12/ {
13 arm { 13 arm {
@@ -37,7 +37,7 @@
37 #size-cells = <0>; 37 #size-cells = <0>;
38 pinctrl-single,bit-per-mux; 38 pinctrl-single,bit-per-mux;
39 pinctrl-single,register-width = <32>; 39 pinctrl-single,register-width = <32>;
40 pinctrl-single,function-mask = <0xffffffff>; 40 pinctrl-single,function-mask = <0xf>;
41 status = "disabled"; 41 status = "disabled";
42 42
43 nand_cs3_pins: pinmux_nand_pins { 43 nand_cs3_pins: pinmux_nand_pins {
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
new file mode 100644
index 000000000000..f65e124c04a6
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -0,0 +1,111 @@
1/*
2 * Samsung's Exynos5 SoC series common device tree source
3 *
4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
8 * SoCs from Exynos5 series can include this file and provide values for SoCs
9 * specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "skeleton.dtsi"
17
18/ {
19 interrupt-parent = <&gic>;
20
21 chipid@10000000 {
22 compatible = "samsung,exynos4210-chipid";
23 reg = <0x10000000 0x100>;
24 };
25
26 combiner:interrupt-controller@10440000 {
27 compatible = "samsung,exynos4210-combiner";
28 #interrupt-cells = <2>;
29 interrupt-controller;
30 samsung,combiner-nr = <32>;
31 reg = <0x10440000 0x1000>;
32 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
33 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
34 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
35 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
37 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
38 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
39 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
40 };
41
42 gic:interrupt-controller@10481000 {
43 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
44 #interrupt-cells = <3>;
45 interrupt-controller;
46 reg = <0x10481000 0x1000>,
47 <0x10482000 0x1000>,
48 <0x10484000 0x2000>,
49 <0x10486000 0x2000>;
50 interrupts = <1 9 0xf04>;
51 };
52
53 dwmmc_0: dwmmc0@12200000 {
54 compatible = "samsung,exynos5250-dw-mshc";
55 interrupts = <0 75 0>;
56 #address-cells = <1>;
57 #size-cells = <0>;
58 };
59
60 dwmmc_1: dwmmc1@12210000 {
61 compatible = "samsung,exynos5250-dw-mshc";
62 interrupts = <0 76 0>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 };
66
67 dwmmc_2: dwmmc2@12220000 {
68 compatible = "samsung,exynos5250-dw-mshc";
69 interrupts = <0 77 0>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72 };
73
74 serial@12C00000 {
75 compatible = "samsung,exynos4210-uart";
76 reg = <0x12C00000 0x100>;
77 interrupts = <0 51 0>;
78 };
79
80 serial@12C10000 {
81 compatible = "samsung,exynos4210-uart";
82 reg = <0x12C10000 0x100>;
83 interrupts = <0 52 0>;
84 };
85
86 serial@12C20000 {
87 compatible = "samsung,exynos4210-uart";
88 reg = <0x12C20000 0x100>;
89 interrupts = <0 53 0>;
90 };
91
92 serial@12C30000 {
93 compatible = "samsung,exynos4210-uart";
94 reg = <0x12C30000 0x100>;
95 interrupts = <0 54 0>;
96 };
97
98 rtc {
99 compatible = "samsung,s3c6410-rtc";
100 reg = <0x101E0000 0x100>;
101 interrupts = <0 43 0>, <0 44 0>;
102 status = "disabled";
103 };
104
105 watchdog {
106 compatible = "samsung,s3c2410-wdt";
107 reg = <0x101D0000 0x100>;
108 interrupts = <0 42 0>;
109 status = "disabled";
110 };
111};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 964158c1844f..41cd625b6020 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,14 +17,13 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20#include "skeleton.dtsi" 20#include "exynos5.dtsi"
21#include "exynos5250-pinctrl.dtsi" 21#include "exynos5250-pinctrl.dtsi"
22 22
23#include <dt-bindings/clk/exynos-audss-clk.h> 23#include <dt-bindings/clk/exynos-audss-clk.h>
24 24
25/ { 25/ {
26 compatible = "samsung,exynos5250"; 26 compatible = "samsung,exynos5250";
27 interrupt-parent = <&gic>;
28 27
29 aliases { 28 aliases {
30 spi0 = &spi_0; 29 spi0 = &spi_0;
@@ -53,9 +52,20 @@
53 pinctrl3 = &pinctrl_3; 52 pinctrl3 = &pinctrl_3;
54 }; 53 };
55 54
56 chipid@10000000 { 55 cpus {
57 compatible = "samsung,exynos4210-chipid"; 56 #address-cells = <1>;
58 reg = <0x10000000 0x100>; 57 #size-cells = <0>;
58
59 cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0>;
63 };
64 cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 };
59 }; 69 };
60 70
61 pd_gsc: gsc-power-domain@0x10044000 { 71 pd_gsc: gsc-power-domain@0x10044000 {
@@ -80,17 +90,6 @@
80 #clock-cells = <1>; 90 #clock-cells = <1>;
81 }; 91 };
82 92
83 gic:interrupt-controller@10481000 {
84 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
85 #interrupt-cells = <3>;
86 interrupt-controller;
87 reg = <0x10481000 0x1000>,
88 <0x10482000 0x1000>,
89 <0x10484000 0x2000>,
90 <0x10486000 0x2000>;
91 interrupts = <1 9 0xf04>;
92 };
93
94 timer { 93 timer {
95 compatible = "arm,armv7-timer"; 94 compatible = "arm,armv7-timer";
96 interrupts = <1 13 0xf08>, 95 interrupts = <1 13 0xf08>,
@@ -99,22 +98,6 @@
99 <1 10 0xf08>; 98 <1 10 0xf08>;
100 }; 99 };
101 100
102 combiner:interrupt-controller@10440000 {
103 compatible = "samsung,exynos4210-combiner";
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 samsung,combiner-nr = <32>;
107 reg = <0x10440000 0x1000>;
108 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
109 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
110 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
111 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
112 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
113 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
114 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
115 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
116 };
117
118 mct@101C0000 { 101 mct@101C0000 {
119 compatible = "samsung,exynos4210-mct"; 102 compatible = "samsung,exynos4210-mct";
120 reg = <0x101C0000 0x800>; 103 reg = <0x101C0000 0x800>;
@@ -176,9 +159,6 @@
176 }; 159 };
177 160
178 watchdog { 161 watchdog {
179 compatible = "samsung,s3c2410-wdt";
180 reg = <0x101D0000 0x100>;
181 interrupts = <0 42 0>;
182 clocks = <&clock 336>; 162 clocks = <&clock 336>;
183 clock-names = "watchdog"; 163 clock-names = "watchdog";
184 }; 164 };
@@ -191,12 +171,8 @@
191 }; 171 };
192 172
193 rtc { 173 rtc {
194 compatible = "samsung,s3c6410-rtc";
195 reg = <0x101E0000 0x100>;
196 interrupts = <0 43 0>, <0 44 0>;
197 clocks = <&clock 337>; 174 clocks = <&clock 337>;
198 clock-names = "rtc"; 175 clock-names = "rtc";
199 status = "disabled";
200 }; 176 };
201 177
202 tmu@10060000 { 178 tmu@10060000 {
@@ -208,33 +184,21 @@
208 }; 184 };
209 185
210 serial@12C00000 { 186 serial@12C00000 {
211 compatible = "samsung,exynos4210-uart";
212 reg = <0x12C00000 0x100>;
213 interrupts = <0 51 0>;
214 clocks = <&clock 289>, <&clock 146>; 187 clocks = <&clock 289>, <&clock 146>;
215 clock-names = "uart", "clk_uart_baud0"; 188 clock-names = "uart", "clk_uart_baud0";
216 }; 189 };
217 190
218 serial@12C10000 { 191 serial@12C10000 {
219 compatible = "samsung,exynos4210-uart";
220 reg = <0x12C10000 0x100>;
221 interrupts = <0 52 0>;
222 clocks = <&clock 290>, <&clock 147>; 192 clocks = <&clock 290>, <&clock 147>;
223 clock-names = "uart", "clk_uart_baud0"; 193 clock-names = "uart", "clk_uart_baud0";
224 }; 194 };
225 195
226 serial@12C20000 { 196 serial@12C20000 {
227 compatible = "samsung,exynos4210-uart";
228 reg = <0x12C20000 0x100>;
229 interrupts = <0 53 0>;
230 clocks = <&clock 291>, <&clock 148>; 197 clocks = <&clock 291>, <&clock 148>;
231 clock-names = "uart", "clk_uart_baud0"; 198 clock-names = "uart", "clk_uart_baud0";
232 }; 199 };
233 200
234 serial@12C30000 { 201 serial@12C30000 {
235 compatible = "samsung,exynos4210-uart";
236 reg = <0x12C30000 0x100>;
237 interrupts = <0 54 0>;
238 clocks = <&clock 292>, <&clock 149>; 202 clocks = <&clock 292>, <&clock 149>;
239 clock-names = "uart", "clk_uart_baud0"; 203 clock-names = "uart", "clk_uart_baud0";
240 }; 204 };
@@ -413,31 +377,19 @@
413 }; 377 };
414 378
415 dwmmc_0: dwmmc0@12200000 { 379 dwmmc_0: dwmmc0@12200000 {
416 compatible = "samsung,exynos5250-dw-mshc";
417 reg = <0x12200000 0x1000>; 380 reg = <0x12200000 0x1000>;
418 interrupts = <0 75 0>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 clocks = <&clock 280>, <&clock 139>; 381 clocks = <&clock 280>, <&clock 139>;
422 clock-names = "biu", "ciu"; 382 clock-names = "biu", "ciu";
423 }; 383 };
424 384
425 dwmmc_1: dwmmc1@12210000 { 385 dwmmc_1: dwmmc1@12210000 {
426 compatible = "samsung,exynos5250-dw-mshc";
427 reg = <0x12210000 0x1000>; 386 reg = <0x12210000 0x1000>;
428 interrupts = <0 76 0>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&clock 281>, <&clock 140>; 387 clocks = <&clock 281>, <&clock 140>;
432 clock-names = "biu", "ciu"; 388 clock-names = "biu", "ciu";
433 }; 389 };
434 390
435 dwmmc_2: dwmmc2@12220000 { 391 dwmmc_2: dwmmc2@12220000 {
436 compatible = "samsung,exynos5250-dw-mshc";
437 reg = <0x12220000 0x1000>; 392 reg = <0x12220000 0x1000>;
438 interrupts = <0 77 0>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 clocks = <&clock 282>, <&clock 141>; 393 clocks = <&clock 282>, <&clock 141>;
442 clock-names = "biu", "ciu"; 394 clock-names = "biu", "ciu";
443 }; 395 };
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
new file mode 100644
index 000000000000..5848c425ae4d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -0,0 +1,680 @@
1/*
2 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
8 * tree nodes are listed in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/ {
16 pinctrl@13400000 {
17 gpy7: gpy7 {
18 gpio-controller;
19 #gpio-cells = <2>;
20
21 interrupt-controller;
22 #interrupt-cells = <2>;
23 };
24
25 gpx0: gpx0 {
26 gpio-controller;
27 #gpio-cells = <2>;
28
29 interrupt-controller;
30 interrupt-parent = <&combiner>;
31 #interrupt-cells = <2>;
32 interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
33 <26 0>, <26 1>, <27 0>, <27 1>;
34 };
35
36 gpx1: gpx1 {
37 gpio-controller;
38 #gpio-cells = <2>;
39
40 interrupt-controller;
41 interrupt-parent = <&combiner>;
42 #interrupt-cells = <2>;
43 interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
44 <30 0>, <30 1>, <31 0>, <31 1>;
45 };
46
47 gpx2: gpx2 {
48 gpio-controller;
49 #gpio-cells = <2>;
50
51 interrupt-controller;
52 #interrupt-cells = <2>;
53 };
54
55 gpx3: gpx3 {
56 gpio-controller;
57 #gpio-cells = <2>;
58
59 interrupt-controller;
60 #interrupt-cells = <2>;
61 };
62 };
63
64 pinctrl@13410000 {
65 gpc0: gpc0 {
66 gpio-controller;
67 #gpio-cells = <2>;
68
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 };
72
73 gpc1: gpc1 {
74 gpio-controller;
75 #gpio-cells = <2>;
76
77 interrupt-controller;
78 #interrupt-cells = <2>;
79 };
80
81 gpc2: gpc2 {
82 gpio-controller;
83 #gpio-cells = <2>;
84
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 };
88
89 gpc3: gpc3 {
90 gpio-controller;
91 #gpio-cells = <2>;
92
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 };
96
97 gpc4: gpc4 {
98 gpio-controller;
99 #gpio-cells = <2>;
100
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 };
104
105 gpd1: gpd1 {
106 gpio-controller;
107 #gpio-cells = <2>;
108
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpy0: gpy0 {
114 gpio-controller;
115 #gpio-cells = <2>;
116 };
117
118 gpy1: gpy1 {
119 gpio-controller;
120 #gpio-cells = <2>;
121 };
122
123 gpy2: gpy2 {
124 gpio-controller;
125 #gpio-cells = <2>;
126 };
127
128 gpy3: gpy3 {
129 gpio-controller;
130 #gpio-cells = <2>;
131 };
132
133 gpy4: gpy4 {
134 gpio-controller;
135 #gpio-cells = <2>;
136 };
137
138 gpy5: gpy5 {
139 gpio-controller;
140 #gpio-cells = <2>;
141 };
142
143 gpy6: gpy6 {
144 gpio-controller;
145 #gpio-cells = <2>;
146 };
147
148 sd0_clk: sd0-clk {
149 samsung,pins = "gpc0-0";
150 samsung,pin-function = <2>;
151 samsung,pin-pud = <0>;
152 samsung,pin-drv = <3>;
153 };
154
155 sd0_cmd: sd0-cmd {
156 samsung,pins = "gpc0-1";
157 samsung,pin-function = <2>;
158 samsung,pin-pud = <0>;
159 samsung,pin-drv = <3>;
160 };
161
162 sd0_cd: sd0-cd {
163 samsung,pins = "gpc0-2";
164 samsung,pin-function = <2>;
165 samsung,pin-pud = <3>;
166 samsung,pin-drv = <3>;
167 };
168
169 sd0_bus1: sd0-bus-width1 {
170 samsung,pins = "gpc0-3";
171 samsung,pin-function = <2>;
172 samsung,pin-pud = <3>;
173 samsung,pin-drv = <3>;
174 };
175
176 sd0_bus4: sd0-bus-width4 {
177 samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
178 samsung,pin-function = <2>;
179 samsung,pin-pud = <3>;
180 samsung,pin-drv = <3>;
181 };
182
183 sd0_bus8: sd0-bus-width8 {
184 samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
185 samsung,pin-function = <2>;
186 samsung,pin-pud = <3>;
187 samsung,pin-drv = <3>;
188 };
189
190 sd1_clk: sd1-clk {
191 samsung,pins = "gpc1-0";
192 samsung,pin-function = <2>;
193 samsung,pin-pud = <0>;
194 samsung,pin-drv = <3>;
195 };
196
197 sd1_cmd: sd1-cmd {
198 samsung,pins = "gpc1-1";
199 samsung,pin-function = <2>;
200 samsung,pin-pud = <0>;
201 samsung,pin-drv = <3>;
202 };
203
204 sd1_cd: sd1-cd {
205 samsung,pins = "gpc1-2";
206 samsung,pin-function = <2>;
207 samsung,pin-pud = <3>;
208 samsung,pin-drv = <3>;
209 };
210
211 sd1_int: sd1-int {
212 samsung,pins = "gpd1-1";
213 samsung,pin-function = <2>;
214 samsung,pin-pud = <3>;
215 samsung,pin-drv = <0>;
216 };
217
218 sd1_bus1: sd1-bus-width1 {
219 samsung,pins = "gpc1-3";
220 samsung,pin-function = <2>;
221 samsung,pin-pud = <3>;
222 samsung,pin-drv = <3>;
223 };
224
225 sd1_bus4: sd1-bus-width4 {
226 samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6";
227 samsung,pin-function = <2>;
228 samsung,pin-pud = <3>;
229 samsung,pin-drv = <3>;
230 };
231
232 sd1_bus8: sd1-bus-width8 {
233 samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7";
234 samsung,pin-function = <2>;
235 samsung,pin-pud = <3>;
236 samsung,pin-drv = <3>;
237 };
238
239 sd2_clk: sd2-clk {
240 samsung,pins = "gpc2-0";
241 samsung,pin-function = <2>;
242 samsung,pin-pud = <0>;
243 samsung,pin-drv = <3>;
244 };
245
246 sd2_cmd: sd2-cmd {
247 samsung,pins = "gpc2-1";
248 samsung,pin-function = <2>;
249 samsung,pin-pud = <0>;
250 samsung,pin-drv = <3>;
251 };
252
253 sd2_cd: sd2-cd {
254 samsung,pins = "gpc2-2";
255 samsung,pin-function = <2>;
256 samsung,pin-pud = <3>;
257 samsung,pin-drv = <3>;
258 };
259
260 sd2_bus1: sd2-bus-width1 {
261 samsung,pins = "gpc2-3";
262 samsung,pin-function = <2>;
263 samsung,pin-pud = <3>;
264 samsung,pin-drv = <3>;
265 };
266
267 sd2_bus4: sd2-bus-width4 {
268 samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
269 samsung,pin-function = <2>;
270 samsung,pin-pud = <3>;
271 samsung,pin-drv = <3>;
272 };
273 };
274
275 pinctrl@14000000 {
276 gpe0: gpe0 {
277 gpio-controller;
278 #gpio-cells = <2>;
279
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
283
284 gpe1: gpe1 {
285 gpio-controller;
286 #gpio-cells = <2>;
287
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 };
291
292 gpf0: gpf0 {
293 gpio-controller;
294 #gpio-cells = <2>;
295
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 };
299
300 gpf1: gpf1 {
301 gpio-controller;
302 #gpio-cells = <2>;
303
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
307
308 gpg0: gpg0 {
309 gpio-controller;
310 #gpio-cells = <2>;
311
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 };
315
316 gpg1: gpg1 {
317 gpio-controller;
318 #gpio-cells = <2>;
319
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
323
324 gpg2: gpg2 {
325 gpio-controller;
326 #gpio-cells = <2>;
327
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 };
331
332 gpj4: gpj4 {
333 gpio-controller;
334 #gpio-cells = <2>;
335
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
339
340 cam_gpio_a: cam-gpio-a {
341 samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
342 "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
343 "gpe1-0", "gpe1-1";
344 samsung,pin-function = <2>;
345 samsung,pin-pud = <0>;
346 samsung,pin-drv = <0>;
347 };
348
349 cam_gpio_b: cam-gpio-b {
350 samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
351 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
352 samsung,pin-function = <3>;
353 samsung,pin-pud = <0>;
354 samsung,pin-drv = <0>;
355 };
356
357 cam_i2c2_bus: cam-i2c2-bus {
358 samsung,pins = "gpf0-4", "gpf0-5";
359 samsung,pin-function = <2>;
360 samsung,pin-pud = <3>;
361 samsung,pin-drv = <0>;
362 };
363 cam_spi1_bus: cam-spi1-bus {
364 samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
365 samsung,pin-function = <4>;
366 samsung,pin-pud = <0>;
367 samsung,pin-drv = <0>;
368 };
369
370 cam_i2c1_bus: cam-i2c1-bus {
371 samsung,pins = "gpf0-2", "gpf0-3";
372 samsung,pin-function = <2>;
373 samsung,pin-pud = <3>;
374 samsung,pin-drv = <0>;
375 };
376
377 cam_i2c0_bus: cam-i2c0-bus {
378 samsung,pins = "gpf0-0", "gpf0-1";
379 samsung,pin-function = <2>;
380 samsung,pin-pud = <3>;
381 samsung,pin-drv = <0>;
382 };
383
384 cam_spi0_bus: cam-spi0-bus {
385 samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
386 samsung,pin-function = <2>;
387 samsung,pin-pud = <0>;
388 samsung,pin-drv = <0>;
389 };
390
391 cam_bayrgb_bus: cam-bayrgb-bus {
392 samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
393 "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
394 "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
395 "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
396 "gpg2-0";
397 samsung,pin-function = <2>;
398 samsung,pin-pud = <0>;
399 samsung,pin-drv = <0>;
400 };
401 };
402
403 pinctrl@14010000 {
404 gpa0: gpa0 {
405 gpio-controller;
406 #gpio-cells = <2>;
407
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 gpa1: gpa1 {
413 gpio-controller;
414 #gpio-cells = <2>;
415
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 };
419
420 gpa2: gpa2 {
421 gpio-controller;
422 #gpio-cells = <2>;
423
424 interrupt-controller;
425 #interrupt-cells = <2>;
426 };
427
428 gpb0: gpb0 {
429 gpio-controller;
430 #gpio-cells = <2>;
431
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
435
436 gpb1: gpb1 {
437 gpio-controller;
438 #gpio-cells = <2>;
439
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 };
443
444 gpb2: gpb2 {
445 gpio-controller;
446 #gpio-cells = <2>;
447
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 };
451
452 gpb3: gpb3 {
453 gpio-controller;
454 #gpio-cells = <2>;
455
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 };
459
460 gpb4: gpb4 {
461 gpio-controller;
462 #gpio-cells = <2>;
463
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 };
467
468 gph0: gph0 {
469 gpio-controller;
470 #gpio-cells = <2>;
471
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 };
475
476 uart0_data: uart0-data {
477 samsung,pins = "gpa0-0", "gpa0-1";
478 samsung,pin-function = <2>;
479 samsung,pin-pud = <0>;
480 samsung,pin-drv = <0>;
481 };
482
483 uart0_fctl: uart0-fctl {
484 samsung,pins = "gpa0-2", "gpa0-3";
485 samsung,pin-function = <2>;
486 samsung,pin-pud = <0>;
487 samsung,pin-drv = <0>;
488 };
489
490 uart1_data: uart1-data {
491 samsung,pins = "gpa0-4", "gpa0-5";
492 samsung,pin-function = <2>;
493 samsung,pin-pud = <0>;
494 samsung,pin-drv = <0>;
495 };
496
497 uart1_fctl: uart1-fctl {
498 samsung,pins = "gpa0-6", "gpa0-7";
499 samsung,pin-function = <2>;
500 samsung,pin-pud = <0>;
501 samsung,pin-drv = <0>;
502 };
503
504 i2c2_bus: i2c2-bus {
505 samsung,pins = "gpa0-6", "gpa0-7";
506 samsung,pin-function = <3>;
507 samsung,pin-pud = <3>;
508 samsung,pin-drv = <0>;
509 };
510
511 uart2_data: uart2-data {
512 samsung,pins = "gpa1-0", "gpa1-1";
513 samsung,pin-function = <2>;
514 samsung,pin-pud = <0>;
515 samsung,pin-drv = <0>;
516 };
517
518 uart2_fctl: uart2-fctl {
519 samsung,pins = "gpa1-2", "gpa1-3";
520 samsung,pin-function = <2>;
521 samsung,pin-pud = <0>;
522 samsung,pin-drv = <0>;
523 };
524
525 i2c3_bus: i2c3-bus {
526 samsung,pins = "gpa1-2", "gpa1-3";
527 samsung,pin-function = <3>;
528 samsung,pin-pud = <3>;
529 samsung,pin-drv = <0>;
530 };
531
532 uart3_data: uart3-data {
533 samsung,pins = "gpa1-4", "gpa1-5";
534 samsung,pin-function = <2>;
535 samsung,pin-pud = <0>;
536 samsung,pin-drv = <0>;
537 };
538
539 spi0_bus: spi0-bus {
540 samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3";
541 samsung,pin-function = <2>;
542 samsung,pin-pud = <3>;
543 samsung,pin-drv = <0>;
544 };
545
546 spi1_bus: spi1-bus {
547 samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
548 samsung,pin-function = <2>;
549 samsung,pin-pud = <3>;
550 samsung,pin-drv = <0>;
551 };
552
553 i2c4_hs_bus: i2c4-hs-bus {
554 samsung,pins = "gpa2-0", "gpa2-1";
555 samsung,pin-function = <3>;
556 samsung,pin-pud = <3>;
557 samsung,pin-drv = <0>;
558 };
559
560 i2c5_hs_bus: i2c5-hs-bus {
561 samsung,pins = "gpa2-2", "gpa2-3";
562 samsung,pin-function = <3>;
563 samsung,pin-pud = <3>;
564 samsung,pin-drv = <0>;
565 };
566
567 i2s1_bus: i2s1-bus {
568 samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
569 "gpb0-4";
570 samsung,pin-function = <2>;
571 samsung,pin-pud = <0>;
572 samsung,pin-drv = <0>;
573 };
574
575 pcm1_bus: pcm1-bus {
576 samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
577 "gpb0-4";
578 samsung,pin-function = <3>;
579 samsung,pin-pud = <0>;
580 samsung,pin-drv = <0>;
581 };
582
583 i2s2_bus: i2s2-bus {
584 samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
585 "gpb1-4";
586 samsung,pin-function = <2>;
587 samsung,pin-pud = <0>;
588 samsung,pin-drv = <0>;
589 };
590
591 pcm2_bus: pcm2-bus {
592 samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
593 "gpb1-4";
594 samsung,pin-function = <3>;
595 samsung,pin-pud = <0>;
596 samsung,pin-drv = <0>;
597 };
598
599 spdif_bus: spdif-bus {
600 samsung,pins = "gpb1-0", "gpb1-1";
601 samsung,pin-function = <4>;
602 samsung,pin-pud = <0>;
603 samsung,pin-drv = <0>;
604 };
605
606 spi2_bus: spi2-bus {
607 samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
608 samsung,pin-function = <5>;
609 samsung,pin-pud = <3>;
610 samsung,pin-drv = <0>;
611 };
612
613 i2c6_hs_bus: i2c6-hs-bus {
614 samsung,pins = "gpb1-3", "gpb1-4";
615 samsung,pin-function = <4>;
616 samsung,pin-pud = <3>;
617 samsung,pin-drv = <0>;
618 };
619
620 i2c7_hs_bus: i2c7-hs-bus {
621 samsung,pins = "gpb2-2", "gpb2-3";
622 samsung,pin-function = <3>;
623 samsung,pin-pud = <3>;
624 samsung,pin-drv = <0>;
625 };
626
627 i2c0_bus: i2c0-bus {
628 samsung,pins = "gpb3-0", "gpb3-1";
629 samsung,pin-function = <2>;
630 samsung,pin-pud = <3>;
631 samsung,pin-drv = <0>;
632 };
633
634 i2c1_bus: i2c1-bus {
635 samsung,pins = "gpb3-2", "gpb3-3";
636 samsung,pin-function = <2>;
637 samsung,pin-pud = <3>;
638 samsung,pin-drv = <0>;
639 };
640
641 i2c8_hs_bus: i2c8-hs-bus {
642 samsung,pins = "gpb3-4", "gpb3-5";
643 samsung,pin-function = <2>;
644 samsung,pin-pud = <3>;
645 samsung,pin-drv = <0>;
646 };
647
648 i2c9_hs_bus: i2c9-hs-bus {
649 samsung,pins = "gpb3-6", "gpb3-7";
650 samsung,pin-function = <2>;
651 samsung,pin-pud = <3>;
652 samsung,pin-drv = <0>;
653 };
654
655 i2c10_hs_bus: i2c10-hs-bus {
656 samsung,pins = "gpb4-0", "gpb4-1";
657 samsung,pin-function = <2>;
658 samsung,pin-pud = <3>;
659 samsung,pin-drv = <0>;
660 };
661 };
662
663 pinctrl@03860000 {
664 gpz: gpz {
665 gpio-controller;
666 #gpio-cells = <2>;
667
668 interrupt-controller;
669 #interrupt-cells = <2>;
670 };
671
672 i2s0_bus: i2s0-bus {
673 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
674 "gpz-4", "gpz-5", "gpz-6";
675 samsung,pin-function = <2>;
676 samsung,pin-pud = <0>;
677 samsung,pin-drv = <0>;
678 };
679 };
680};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
new file mode 100644
index 000000000000..08607df6a180
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,33 @@
1/*
2 * SAMSUNG SMDK5420 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13#include "exynos5420.dtsi"
14
15/ {
16 model = "Samsung SMDK5420 board based on EXYNOS5420";
17 compatible = "samsung,smdk5420", "samsung,exynos5420";
18
19 memory {
20 reg = <0x20000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttySAC2,115200 init=/linuxrc";
25 };
26
27 fixed-rate-clocks {
28 oscclk {
29 compatible = "samsung,exynos5420-oscclk";
30 clock-frequency = <24000000>;
31 };
32 };
33};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
new file mode 100644
index 000000000000..8c54c4b74f0e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -0,0 +1,148 @@
1/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "exynos5.dtsi"
17/include/ "exynos5420-pinctrl.dtsi"
18/ {
19 compatible = "samsung,exynos5420";
20
21 aliases {
22 pinctrl0 = &pinctrl_0;
23 pinctrl1 = &pinctrl_1;
24 pinctrl2 = &pinctrl_2;
25 pinctrl3 = &pinctrl_3;
26 pinctrl4 = &pinctrl_4;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a15";
36 reg = <0x0>;
37 clock-frequency = <1800000000>;
38 };
39
40 cpu1: cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x1>;
44 clock-frequency = <1800000000>;
45 };
46
47 cpu2: cpu@2 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0x2>;
51 clock-frequency = <1800000000>;
52 };
53
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <0x3>;
58 clock-frequency = <1800000000>;
59 };
60 };
61
62 clock: clock-controller@0x10010000 {
63 compatible = "samsung,exynos5420-clock";
64 reg = <0x10010000 0x30000>;
65 #clock-cells = <1>;
66 };
67
68 mct@101C0000 {
69 compatible = "samsung,exynos4210-mct";
70 reg = <0x101C0000 0x800>;
71 interrupt-controller;
72 #interrups-cells = <1>;
73 interrupt-parent = <&mct_map>;
74 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
75 clocks = <&clock 1>, <&clock 315>;
76 clock-names = "fin_pll", "mct";
77
78 mct_map: mct-map {
79 #interrupt-cells = <1>;
80 #address-cells = <0>;
81 #size-cells = <0>;
82 interrupt-map = <0 &combiner 23 3>,
83 <1 &combiner 23 4>,
84 <2 &combiner 25 2>,
85 <3 &combiner 25 3>,
86 <4 &gic 0 120 0>,
87 <5 &gic 0 121 0>,
88 <6 &gic 0 122 0>,
89 <7 &gic 0 123 0>;
90 };
91 };
92
93 pinctrl_0: pinctrl@13400000 {
94 compatible = "samsung,exynos5420-pinctrl";
95 reg = <0x13400000 0x1000>;
96 interrupts = <0 45 0>;
97
98 wakeup-interrupt-controller {
99 compatible = "samsung,exynos4210-wakeup-eint";
100 interrupt-parent = <&gic>;
101 interrupts = <0 32 0>;
102 };
103 };
104
105 pinctrl_1: pinctrl@13410000 {
106 compatible = "samsung,exynos5420-pinctrl";
107 reg = <0x13410000 0x1000>;
108 interrupts = <0 78 0>;
109 };
110
111 pinctrl_2: pinctrl@14000000 {
112 compatible = "samsung,exynos5420-pinctrl";
113 reg = <0x14000000 0x1000>;
114 interrupts = <0 46 0>;
115 };
116
117 pinctrl_3: pinctrl@14010000 {
118 compatible = "samsung,exynos5420-pinctrl";
119 reg = <0x14010000 0x1000>;
120 interrupts = <0 50 0>;
121 };
122
123 pinctrl_4: pinctrl@03860000 {
124 compatible = "samsung,exynos5420-pinctrl";
125 reg = <0x03860000 0x1000>;
126 interrupts = <0 47 0>;
127 };
128
129 serial@12C00000 {
130 clocks = <&clock 257>, <&clock 128>;
131 clock-names = "uart", "clk_uart_baud0";
132 };
133
134 serial@12C10000 {
135 clocks = <&clock 258>, <&clock 129>;
136 clock-names = "uart", "clk_uart_baud0";
137 };
138
139 serial@12C20000 {
140 clocks = <&clock 259>, <&clock 130>;
141 clock-names = "uart", "clk_uart_baud0";
142 };
143
144 serial@12C30000 {
145 clocks = <&clock 260>, <&clock 131>;
146 clock-names = "uart", "clk_uart_baud0";
147 };
148};
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
new file mode 100644
index 000000000000..9565199bce7a
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -0,0 +1,74 @@
1/*
2 * linux/arch/arm/boot/nspire-classic.dts
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/include/ "nspire.dtsi"
13
14&lcd {
15 lcd-type = "classic";
16};
17
18&fast_timer {
19 /* compatible = "lsi,zevio-timer"; */
20 reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
21};
22
23&uart {
24 compatible = "ns16550";
25 reg-shift = <2>;
26 reg-io-width = <4>;
27 clocks = <&apb_pclk>;
28 no-loopback-test;
29};
30
31&timer0 {
32 /* compatible = "lsi,zevio-timer"; */
33 reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
34};
35
36&timer1 {
37 compatible = "lsi,zevio-timer";
38 reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
39};
40
41&keypad {
42 active-low;
43
44};
45
46&base_clk {
47 compatible = "lsi,nspire-classic-clock";
48};
49
50&ahb_clk {
51 compatible = "lsi,nspire-classic-ahb-divider";
52};
53
54/ {
55 memory {
56 device_type = "memory";
57 reg = <0x10000000 0x2000000>; /* 32 MB */
58 };
59
60 ahb {
61 #address-cells = <1>;
62 #size-cells = <1>;
63
64 intc: interrupt-controller@DC000000 {
65 compatible = "lsi,zevio-intc";
66 interrupt-controller;
67 reg = <0xDC000000 0x1000>;
68 #interrupt-cells = <1>;
69 };
70 };
71 chosen {
72 bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
73 };
74};
diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts
new file mode 100644
index 000000000000..fa5a044656de
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-clp.dts
@@ -0,0 +1,45 @@
1/*
2 * linux/arch/arm/boot/nspire-clp.dts
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12
13/include/ "nspire-classic.dtsi"
14
15&keypad {
16 linux,keymap = <
17 0x0000001c 0x0001001c 0x00020039
18 0x0004002c 0x00050034 0x00060015
19 0x0007000b 0x0008002d 0x01000033
20 0x0101004e 0x01020011 0x01030004
21 0x0104002f 0x01050003 0x01060016
22 0x01070002 0x01080014 0x02000062
23 0x0201000c 0x0202001f 0x02030007
24 0x02040013 0x02050006 0x02060010
25 0x02070005 0x02080019 0x03000027
26 0x03010037 0x03020018 0x0303000a
27 0x03040031 0x03050009 0x03060032
28 0x03070008 0x03080026 0x04000028
29 0x04010035 0x04020025 0x04040024
30 0x04060017 0x04080023 0x05000028
31 0x05020022 0x0503001b 0x05040021
32 0x0505001a 0x05060012 0x0507006f
33 0x05080020 0x0509002a 0x0601001c
34 0x0602002e 0x06030068 0x06040030
35 0x0605006d 0x0606001e 0x06070001
36 0x0608002b 0x0609000f 0x07000067
37 0x0702006a 0x0704006c 0x07060069
38 0x0707000e 0x0708001d 0x070a000d
39 >;
40};
41
42/ {
43 model = "TI-NSPIRE Clickpad";
44 compatible = "ti,nspire-clp";
45};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
new file mode 100644
index 000000000000..375b924f60d8
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -0,0 +1,112 @@
1/*
2 * linux/arch/arm/boot/nspire-cx.dts
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12
13/include/ "nspire.dtsi"
14
15&lcd {
16 lcd-type = "cx";
17};
18
19&fast_timer {
20 /* compatible = "arm,sp804", "arm,primecell"; */
21};
22
23&uart {
24 compatible = "arm,pl011", "arm,primecell";
25
26 clocks = <&uart_clk>, <&apb_pclk>;
27 clock-names = "uart_clk", "apb_pclk";
28};
29
30&timer0 {
31 compatible = "arm,sp804", "arm,primecell";
32};
33
34&timer1 {
35 compatible = "arm,sp804", "arm,primecell";
36};
37
38&base_clk {
39 compatible = "lsi,nspire-cx-clock";
40};
41
42&ahb_clk {
43 compatible = "lsi,nspire-cx-ahb-divider";
44};
45
46&keypad {
47 linux,keymap = <
48 0x0000001c 0x0001001c 0x00040039
49 0x0005002c 0x00060015 0x0007000b
50 0x0008000f 0x0100002d 0x01010011
51 0x0102002f 0x01030004 0x01040016
52 0x01050014 0x0106001f 0x01070002
53 0x010a006a 0x02000013 0x02010010
54 0x02020019 0x02030007 0x02040018
55 0x02050031 0x02060032 0x02070005
56 0x02080028 0x0209006c 0x03000026
57 0x03010025 0x03020024 0x0303000a
58 0x03040017 0x03050023 0x03060022
59 0x03070008 0x03080035 0x03090069
60 0x04000021 0x04010012 0x04020020
61 0x0404002e 0x04050030 0x0406001e
62 0x0407000d 0x04080037 0x04090067
63 0x05010038 0x0502000c 0x0503001b
64 0x05040034 0x0505001a 0x05060006
65 0x05080027 0x0509000e 0x050a006f
66 0x0600002b 0x0602004e 0x06030068
67 0x06040003 0x0605006d 0x06060009
68 0x06070001 0x0609000f 0x0708002a
69 0x0709001d 0x070a0033 >;
70};
71
72/ {
73 model = "TI-NSPIRE CX";
74 compatible = "ti,nspire-cx";
75
76 memory {
77 device_type = "memory";
78 reg = <0x10000000 0x4000000>; /* 64 MB */
79 };
80
81 uart_clk: uart_clk {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <12000000>;
85 };
86
87 ahb {
88 #address-cells = <1>;
89 #size-cells = <1>;
90
91 intc: interrupt-controller@DC000000 {
92 compatible = "arm,pl190-vic";
93 interrupt-controller;
94 reg = <0xDC000000 0x1000>;
95 #interrupt-cells = <1>;
96 };
97
98 apb@90000000 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101
102 i2c@90050000 {
103 compatible = "snps,designware-i2c";
104 reg = <0x90050000 0x1000>;
105 interrupts = <20>;
106 };
107 };
108 };
109 chosen {
110 bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
111 };
112};
diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts
new file mode 100644
index 000000000000..621391ce6ed6
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-tp.dts
@@ -0,0 +1,44 @@
1/*
2 * linux/arch/arm/boot/nspire-tp.dts
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12
13/include/ "nspire-classic.dtsi"
14
15&keypad {
16 linux,keymap = <
17 0x0000001c 0x0001001c 0x00040039
18 0x0005002c 0x00060015 0x0007000b
19 0x0008000f 0x0100002d 0x01010011
20 0x0102002f 0x01030004 0x01040016
21 0x01050014 0x0106001f 0x01070002
22 0x010a006a 0x02000013 0x02010010
23 0x02020019 0x02030007 0x02040018
24 0x02050031 0x02060032 0x02070005
25 0x02080028 0x0209006c 0x03000026
26 0x03010025 0x03020024 0x0303000a
27 0x03040017 0x03050023 0x03060022
28 0x03070008 0x03080035 0x03090069
29 0x04000021 0x04010012 0x04020020
30 0x0404002e 0x04050030 0x0406001e
31 0x0407000d 0x04080037 0x04090067
32 0x05010038 0x0502000c 0x0503001b
33 0x05040034 0x0505001a 0x05060006
34 0x05080027 0x0509000e 0x050a006f
35 0x0600002b 0x0602004e 0x06030068
36 0x06040003 0x0605006d 0x06060009
37 0x06070001 0x0609000f 0x0708002a
38 0x0709001d 0x070a0033 >;
39};
40
41/ {
42 model = "TI-NSPIRE Touchpad";
43 compatible = "ti,nspire-tp";
44};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
new file mode 100644
index 000000000000..a22ffe633b49
--- /dev/null
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -0,0 +1,175 @@
1/*
2 * linux/arch/arm/boot/nspire.dtsi
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&intc>;
16
17 cpus {
18 cpu@0 {
19 compatible = "arm,arm926ejs";
20 };
21 };
22
23 bootrom: bootrom@00000000 {
24 reg = <0x00000000 0x80000>;
25 };
26
27 sram: sram@A4000000 {
28 device = "memory";
29 reg = <0xA4000000 0x20000>;
30 };
31
32 timer_clk: timer_clk {
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <32768>;
36 };
37
38 base_clk: base_clk {
39 #clock-cells = <0>;
40 reg = <0x900B0024 0x4>;
41 };
42
43 ahb_clk: ahb_clk {
44 #clock-cells = <0>;
45 reg = <0x900B0024 0x4>;
46 clocks = <&base_clk>;
47 };
48
49 apb_pclk: apb_pclk {
50 #clock-cells = <0>;
51 compatible = "fixed-factor-clock";
52 clock-div = <2>;
53 clock-mult = <1>;
54 clocks = <&ahb_clk>;
55 };
56
57 ahb {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 spi: spi@A9000000 {
64 reg = <0xA9000000 0x1000>;
65 };
66
67 usb0: usb@B0000000 {
68 reg = <0xB0000000 0x1000>;
69 interrupts = <8>;
70 };
71
72 usb1: usb@B4000000 {
73 reg = <0xB4000000 0x1000>;
74 interrupts = <9>;
75 status = "disabled";
76 };
77
78 lcd: lcd@C0000000 {
79 compatible = "arm,pl111", "arm,primecell";
80 reg = <0xC0000000 0x1000>;
81 interrupts = <21>;
82
83 clocks = <&apb_pclk>;
84 clock-names = "apb_pclk";
85 };
86
87 adc: adc@C4000000 {
88 reg = <0xC4000000 0x1000>;
89 interrupts = <11>;
90 };
91
92 tdes: crypto@C8010000 {
93 reg = <0xC8010000 0x1000>;
94 };
95
96 sha256: crypto@CC000000 {
97 reg = <0xCC000000 0x1000>;
98 };
99
100 apb@90000000 {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 clock-ranges;
105 ranges;
106
107 gpio: gpio@90000000 {
108 reg = <0x90000000 0x1000>;
109 interrupts = <7>;
110 };
111
112 fast_timer: timer@90010000 {
113 reg = <0x90010000 0x1000>;
114 interrupts = <17>;
115 };
116
117 uart: serial@90020000 {
118 reg = <0x90020000 0x1000>;
119 interrupts = <1>;
120 };
121
122 timer0: timer@900C0000 {
123 reg = <0x900C0000 0x1000>;
124
125 clocks = <&timer_clk>;
126 };
127
128 timer1: timer@900D0000 {
129 reg = <0x900D0000 0x1000>;
130 interrupts = <19>;
131
132 clocks = <&timer_clk>;
133 };
134
135 watchdog: watchdog@90060000 {
136 compatible = "arm,amba-primecell";
137 reg = <0x90060000 0x1000>;
138 interrupts = <3>;
139 };
140
141 rtc: rtc@90090000 {
142 reg = <0x90090000 0x1000>;
143 interrupts = <4>;
144 };
145
146 misc: misc@900A0000 {
147 reg = <0x900A0000 0x1000>;
148 };
149
150 pwr: pwr@900B0000 {
151 reg = <0x900B0000 0x1000>;
152 interrupts = <15>;
153 };
154
155 keypad: input@900E0000 {
156 compatible = "ti,nspire-keypad";
157 reg = <0x900E0000 0x1000>;
158 interrupts = <16>;
159
160 scan-interval = <1000>;
161 row-delay = <200>;
162
163 clocks = <&apb_pclk>;
164 };
165
166 contrast: contrast@900F0000 {
167 reg = <0x900F0000 0x1000>;
168 };
169
170 led: led@90110000 {
171 reg = <0x90110000 0x1000>;
172 };
173 };
174 };
175};
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
new file mode 100644
index 000000000000..8c45d85ac13e
--- /dev/null
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -0,0 +1,71 @@
1#ifndef _ST_PINCFG_H_
2#define _ST_PINCFG_H_
3
4/* Alternate functions */
5#define ALT1 1
6#define ALT2 2
7#define ALT3 3
8#define ALT4 4
9#define ALT5 5
10#define ALT6 6
11#define ALT7 7
12
13/* Output enable */
14#define OE (1 << 27)
15/* Pull Up */
16#define PU (1 << 26)
17/* Open Drain */
18#define OD (1 << 26)
19#define RT (1 << 23)
20#define INVERTCLK (1 << 22)
21#define CLKNOTDATA (1 << 21)
22#define DOUBLE_EDGE (1 << 20)
23#define CLK_A (0 << 18)
24#define CLK_B (1 << 18)
25#define CLK_C (2 << 18)
26#define CLK_D (3 << 18)
27
28/* User-frendly defines for Pin Direction */
29 /* oe = 0, pu = 0, od = 0 */
30#define IN (0)
31 /* oe = 0, pu = 1, od = 0 */
32#define IN_PU (PU)
33 /* oe = 1, pu = 0, od = 0 */
34#define OUT (OE)
35 /* oe = 1, pu = 0, od = 1 */
36#define BIDIR (OE | OD)
37 /* oe = 1, pu = 1, od = 1 */
38#define BIDIR_PU (OE | PU | OD)
39
40/* RETIME_TYPE */
41/*
42 * B Mode
43 * Bypass retime with optional delay parameter
44 */
45#define BYPASS (0)
46/*
47 * R0, R1, R0D, R1D modes
48 * single-edge data non inverted clock, retime data with clk
49 */
50#define SE_NICLK_IO (RT)
51/*
52 * RIV0, RIV1, RIV0D, RIV1D modes
53 * single-edge data inverted clock, retime data with clk
54 */
55#define SE_ICLK_IO (RT | INVERTCLK)
56/*
57 * R0E, R1E, R0ED, R1ED modes
58 * double-edge data, retime data with clk
59 */
60#define DE_IO (RT | DOUBLE_EDGE)
61/*
62 * CIV0, CIV1 modes with inverted clock
63 * Retiming the clk pins will park clock & reduce the noise within the core.
64 */
65#define ICLK (RT | CLKNOTDATA | INVERTCLK)
66/*
67 * CLK0, CLK1 modes with non-inverted clock
68 * Retiming the clk pins will park clock & reduce the noise within the core.
69 */
70#define NICLK (RT | CLKNOTDATA)
71#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts
new file mode 100644
index 000000000000..d4af53160435
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2000.dts
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih415.dtsi"
11#include "stih41x-b2000.dtsi"
12/ {
13 model = "STiH415 B2000 Board";
14 compatible = "st,stih415", "st,stih415-b2000";
15};
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000000000000..442b019e9a3a
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih415.dtsi"
11#include "stih41x-b2020.dtsi"
12/ {
13 model = "STiH415 B2020 Board";
14 compatible = "st,stih415", "st,stih415-b2020";
15};
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
new file mode 100644
index 000000000000..174c799df741
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/ {
9 clocks {
10 /*
11 * Fixed 30MHz oscillator input to SoC
12 */
13 CLK_SYSIN: CLK_SYSIN {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <30000000>;
17 };
18
19 /*
20 * ARM Peripheral clock for timers
21 */
22 arm_periph_clk: arm_periph_clk {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <500000000>;
26 };
27
28 /*
29 * Bootloader initialized system infrastructure clock for
30 * serial devices.
31 */
32 CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <100000000>;
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
new file mode 100644
index 000000000000..1d322b24d1e4
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -0,0 +1,268 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10/ {
11
12 aliases {
13 gpio0 = &PIO0;
14 gpio1 = &PIO1;
15 gpio2 = &PIO2;
16 gpio3 = &PIO3;
17 gpio4 = &PIO4;
18 gpio5 = &PIO5;
19 gpio6 = &PIO6;
20 gpio7 = &PIO7;
21 gpio8 = &PIO8;
22 gpio9 = &PIO9;
23 gpio10 = &PIO10;
24 gpio11 = &PIO11;
25 gpio12 = &PIO12;
26 gpio13 = &PIO13;
27 gpio14 = &PIO14;
28 gpio15 = &PIO15;
29 gpio16 = &PIO16;
30 gpio17 = &PIO17;
31 gpio18 = &PIO18;
32 gpio19 = &PIO100;
33 gpio20 = &PIO101;
34 gpio21 = &PIO102;
35 gpio22 = &PIO103;
36 gpio23 = &PIO104;
37 gpio24 = &PIO105;
38 gpio25 = &PIO106;
39 gpio26 = &PIO107;
40 };
41
42 soc {
43 pin-controller-sbc {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "st,stih415-sbc-pinctrl";
47 st,syscfg = <&syscfg_sbc>;
48 ranges = <0 0xfe610000 0x5000>;
49
50 PIO0: gpio@fe610000 {
51 gpio-controller;
52 #gpio-cells = <1>;
53 reg = <0 0x100>;
54 st,bank-name = "PIO0";
55 };
56 PIO1: gpio@fe611000 {
57 gpio-controller;
58 #gpio-cells = <1>;
59 reg = <0x1000 0x100>;
60 st,bank-name = "PIO1";
61 };
62 PIO2: gpio@fe612000 {
63 gpio-controller;
64 #gpio-cells = <1>;
65 reg = <0x2000 0x100>;
66 st,bank-name = "PIO2";
67 };
68 PIO3: gpio@fe613000 {
69 gpio-controller;
70 #gpio-cells = <1>;
71 reg = <0x3000 0x100>;
72 st,bank-name = "PIO3";
73 };
74 PIO4: gpio@fe614000 {
75 gpio-controller;
76 #gpio-cells = <1>;
77 reg = <0x4000 0x100>;
78 st,bank-name = "PIO4";
79 };
80
81 sbc_serial1 {
82 pinctrl_sbc_serial1:sbc_serial1 {
83 st,pins {
84 tx = <&PIO2 6 ALT3 OUT>;
85 rx = <&PIO2 7 ALT3 IN>;
86 };
87 };
88 };
89 };
90
91 pin-controller-front {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "st,stih415-front-pinctrl";
95 st,syscfg = <&syscfg_front>;
96 ranges = <0 0xfee00000 0x8000>;
97
98 PIO5: gpio@fee00000 {
99 gpio-controller;
100 #gpio-cells = <1>;
101 reg = <0 0x100>;
102 st,bank-name = "PIO5";
103 };
104 PIO6: gpio@fee01000 {
105 gpio-controller;
106 #gpio-cells = <1>;
107 reg = <0x1000 0x100>;
108 st,bank-name = "PIO6";
109 };
110 PIO7: gpio@fee02000 {
111 gpio-controller;
112 #gpio-cells = <1>;
113 reg = <0x2000 0x100>;
114 st,bank-name = "PIO7";
115 };
116 PIO8: gpio@fee03000 {
117 gpio-controller;
118 #gpio-cells = <1>;
119 reg = <0x3000 0x100>;
120 st,bank-name = "PIO8";
121 };
122 PIO9: gpio@fee04000 {
123 gpio-controller;
124 #gpio-cells = <1>;
125 reg = <0x4000 0x100>;
126 st,bank-name = "PIO9";
127 };
128 PIO10: gpio@fee05000 {
129 gpio-controller;
130 #gpio-cells = <1>;
131 reg = <0x5000 0x100>;
132 st,bank-name = "PIO10";
133 };
134 PIO11: gpio@fee06000 {
135 gpio-controller;
136 #gpio-cells = <1>;
137 reg = <0x6000 0x100>;
138 st,bank-name = "PIO11";
139 };
140 PIO12: gpio@fee07000 {
141 gpio-controller;
142 #gpio-cells = <1>;
143 reg = <0x7000 0x100>;
144 st,bank-name = "PIO12";
145 };
146 };
147
148 pin-controller-rear {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "st,stih415-rear-pinctrl";
152 st,syscfg = <&syscfg_rear>;
153 ranges = <0 0xfe820000 0x8000>;
154
155 PIO13: gpio@fe820000 {
156 gpio-controller;
157 #gpio-cells = <1>;
158 reg = <0 0x100>;
159 st,bank-name = "PIO13";
160 };
161 PIO14: gpio@fe821000 {
162 gpio-controller;
163 #gpio-cells = <1>;
164 reg = <0x1000 0x100>;
165 st,bank-name = "PIO14";
166 };
167 PIO15: gpio@fe822000 {
168 gpio-controller;
169 #gpio-cells = <1>;
170 reg = <0x2000 0x100>;
171 st,bank-name = "PIO15";
172 };
173 PIO16: gpio@fe823000 {
174 gpio-controller;
175 #gpio-cells = <1>;
176 reg = <0x3000 0x100>;
177 st,bank-name = "PIO16";
178 };
179 PIO17: gpio@fe824000 {
180 gpio-controller;
181 #gpio-cells = <1>;
182 reg = <0x4000 0x100>;
183 st,bank-name = "PIO17";
184 };
185 PIO18: gpio@fe825000 {
186 gpio-controller;
187 #gpio-cells = <1>;
188 reg = <0x5000 0x100>;
189 st,bank-name = "PIO18";
190 };
191
192 serial2 {
193 pinctrl_serial2: serial2-0 {
194 st,pins {
195 tx = <&PIO17 4 ALT2 OUT>;
196 rx = <&PIO17 5 ALT2 IN>;
197 };
198 };
199 };
200 };
201
202 pin-controller-left {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "st,stih415-left-pinctrl";
206 st,syscfg = <&syscfg_left>;
207 ranges = <0 0xfd6b0000 0x3000>;
208
209 PIO100: gpio@fd6b0000 {
210 gpio-controller;
211 #gpio-cells = <1>;
212 reg = <0 0x100>;
213 st,bank-name = "PIO100";
214 };
215 PIO101: gpio@fd6b1000 {
216 gpio-controller;
217 #gpio-cells = <1>;
218 reg = <0x1000 0x100>;
219 st,bank-name = "PIO101";
220 };
221 PIO102: gpio@fd6b2000 {
222 gpio-controller;
223 #gpio-cells = <1>;
224 reg = <0x2000 0x100>;
225 st,bank-name = "PIO102";
226 };
227 };
228
229 pin-controller-right {
230 #address-cells = <1>;
231 #size-cells = <1>;
232 compatible = "st,stih415-right-pinctrl";
233 st,syscfg = <&syscfg_right>;
234 ranges = <0 0xfd330000 0x5000>;
235
236 PIO103: gpio@fd330000 {
237 gpio-controller;
238 #gpio-cells = <1>;
239 reg = <0 0x100>;
240 st,bank-name = "PIO103";
241 };
242 PIO104: gpio@fd331000 {
243 gpio-controller;
244 #gpio-cells = <1>;
245 reg = <0x1000 0x100>;
246 st,bank-name = "PIO104";
247 };
248 PIO105: gpio@fd332000 {
249 gpio-controller;
250 #gpio-cells = <1>;
251 reg = <0x2000 0x100>;
252 st,bank-name = "PIO105";
253 };
254 PIO106: gpio@fd333000 {
255 gpio-controller;
256 #gpio-cells = <1>;
257 reg = <0x3000 0x100>;
258 st,bank-name = "PIO106";
259 };
260 PIO107: gpio@fd334000 {
261 gpio-controller;
262 #gpio-cells = <1>;
263 reg = <0x4000 0x100>;
264 st,bank-name = "PIO107";
265 };
266 };
267 };
268};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
new file mode 100644
index 000000000000..74ab8ded4b49
--- /dev/null
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -0,0 +1,87 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih41x.dtsi"
10#include "stih415-clock.dtsi"
11#include "stih415-pinctrl.dtsi"
12/ {
13
14 L2: cache-controller {
15 compatible = "arm,pl310-cache";
16 reg = <0xfffe2000 0x1000>;
17 arm,data-latency = <3 2 2>;
18 arm,tag-latency = <1 1 1>;
19 cache-unified;
20 cache-level = <2>;
21 };
22
23 soc {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 interrupt-parent = <&intc>;
27 ranges;
28 compatible = "simple-bus";
29
30 syscfg_sbc: sbc-syscfg@fe600000{
31 compatible = "st,stih415-sbc-syscfg", "syscon";
32 reg = <0xfe600000 0xb4>;
33 };
34
35 syscfg_front: front-syscfg@fee10000{
36 compatible = "st,stih415-front-syscfg", "syscon";
37 reg = <0xfee10000 0x194>;
38 };
39
40 syscfg_rear: rear-syscfg@fe830000{
41 compatible = "st,stih415-rear-syscfg", "syscon";
42 reg = <0xfe830000 0x190>;
43 };
44
45 /* MPE syscfgs */
46 syscfg_left: left-syscfg@fd690000{
47 compatible = "st,stih415-left-syscfg", "syscon";
48 reg = <0xfd690000 0x78>;
49 };
50
51 syscfg_right: right-syscfg@fd320000{
52 compatible = "st,stih415-right-syscfg", "syscon";
53 reg = <0xfd320000 0x180>;
54 };
55
56 syscfg_system: system-syscfg@fdde0000 {
57 compatible = "st,stih415-system-syscfg", "syscon";
58 reg = <0xfdde0000 0x15c>;
59 };
60
61 syscfg_lpm: lpm-syscfg@fe4b5100{
62 compatible = "st,stih415-lpm-syscfg", "syscon";
63 reg = <0xfe4b5100 0x08>;
64 };
65
66 serial2: serial@fed32000 {
67 compatible = "st,asc";
68 status = "disabled";
69 reg = <0xfed32000 0x2c>;
70 interrupts = <0 197 0>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_serial2>;
73 clocks = <&CLKS_ICN_REG_0>;
74 };
75
76 /* SBC comms block ASCs in SASG1 */
77 sbc_serial1: serial@fe531000 {
78 compatible = "st,asc";
79 status = "disabled";
80 reg = <0xfe531000 0x2c>;
81 interrupts = <0 210 0>;
82 clocks = <&CLK_SYSIN>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_sbc_serial1>;
85 };
86 };
87};
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts
new file mode 100644
index 000000000000..a5eb6eee10bf
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2000.dts
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih416.dtsi"
11#include "stih41x-b2000.dtsi"
12
13/ {
14 compatible = "st,stih416", "st,stih416-b2000";
15 model = "STiH416 B2000";
16};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
new file mode 100644
index 000000000000..276f28da573a
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih416.dtsi"
11#include "stih41x-b2020.dtsi"
12/ {
13 model = "STiH416 B2020";
14 compatible = "st,stih416", "st,stih416-b2020";
15
16};
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
new file mode 100644
index 000000000000..7026bf1158d8
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics R&D Limited
3 * <stlinux-devel@stlinux.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/ {
10 clocks {
11 /*
12 * Fixed 30MHz oscillator inputs to SoC
13 */
14 CLK_SYSIN: CLK_SYSIN {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <30000000>;
18 clock-output-names = "CLK_SYSIN";
19 };
20
21 /*
22 * ARM Peripheral clock for timers
23 */
24 arm_periph_clk: arm_periph_clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <600000000>;
28 };
29
30 /*
31 * Bootloader initialized system infrastructure clock for
32 * serial devices.
33 */
34 CLK_S_ICN_REG_0: clockgenA0@4 {
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <100000000>;
38 clock-output-names = "CLK_S_ICN_REG_0";
39 };
40 };
41};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
new file mode 100644
index 000000000000..957b21a71b4b
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -0,0 +1,295 @@
1
2/*
3 * Copyright (C) 2013 STMicroelectronics Limited.
4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#include "st-pincfg.h"
11/ {
12
13 aliases {
14 gpio0 = &PIO0;
15 gpio1 = &PIO1;
16 gpio2 = &PIO2;
17 gpio3 = &PIO3;
18 gpio4 = &PIO4;
19 gpio5 = &PIO40;
20 gpio6 = &PIO5;
21 gpio7 = &PIO6;
22 gpio8 = &PIO7;
23 gpio9 = &PIO8;
24 gpio10 = &PIO9;
25 gpio11 = &PIO10;
26 gpio12 = &PIO11;
27 gpio13 = &PIO12;
28 gpio14 = &PIO30;
29 gpio15 = &PIO31;
30 gpio16 = &PIO13;
31 gpio17 = &PIO14;
32 gpio18 = &PIO15;
33 gpio19 = &PIO16;
34 gpio20 = &PIO17;
35 gpio21 = &PIO18;
36 gpio22 = &PIO100;
37 gpio23 = &PIO101;
38 gpio24 = &PIO102;
39 gpio25 = &PIO103;
40 gpio26 = &PIO104;
41 gpio27 = &PIO105;
42 gpio28 = &PIO106;
43 gpio29 = &PIO107;
44 };
45
46 soc {
47 pin-controller-sbc {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stih416-sbc-pinctrl";
51 st,syscfg = <&syscfg_sbc>;
52 ranges = <0 0xfe610000 0x6000>;
53
54 PIO0: gpio@fe610000 {
55 gpio-controller;
56 #gpio-cells = <1>;
57 reg = <0 0x100>;
58 st,bank-name = "PIO0";
59 };
60 PIO1: gpio@fe611000 {
61 gpio-controller;
62 #gpio-cells = <1>;
63 reg = <0x1000 0x100>;
64 st,bank-name = "PIO1";
65 };
66 PIO2: gpio@fe612000 {
67 gpio-controller;
68 #gpio-cells = <1>;
69 reg = <0x2000 0x100>;
70 st,bank-name = "PIO2";
71 };
72 PIO3: gpio@fe613000 {
73 gpio-controller;
74 #gpio-cells = <1>;
75 reg = <0x3000 0x100>;
76 st,bank-name = "PIO3";
77 };
78 PIO4: gpio@fe614000 {
79 gpio-controller;
80 #gpio-cells = <1>;
81 reg = <0x4000 0x100>;
82 st,bank-name = "PIO4";
83 };
84 PIO40: gpio@fe615000 {
85 gpio-controller;
86 #gpio-cells = <1>;
87 reg = <0x5000 0x100>;
88 st,bank-name = "PIO40";
89 st,retime-pin-mask = <0x7f>;
90 };
91
92 sbc_serial1 {
93 pinctrl_sbc_serial1: sbc_serial1 {
94 st,pins {
95 tx = <&PIO2 6 ALT3 OUT>;
96 rx = <&PIO2 7 ALT3 IN>;
97 };
98 };
99 };
100 };
101
102 pin-controller-front {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "st,stih416-front-pinctrl";
106 st,syscfg = <&syscfg_front>;
107 ranges = <0 0xfee00000 0x10000>;
108
109 PIO5: gpio@fee00000 {
110 gpio-controller;
111 #gpio-cells = <1>;
112 reg = <0 0x100>;
113 st,bank-name = "PIO5";
114 };
115 PIO6: gpio@fee01000 {
116 gpio-controller;
117 #gpio-cells = <1>;
118 reg = <0x1000 0x100>;
119 st,bank-name = "PIO6";
120 };
121 PIO7: gpio@fee02000 {
122 gpio-controller;
123 #gpio-cells = <1>;
124 reg = <0x2000 0x100>;
125 st,bank-name = "PIO7";
126 };
127 PIO8: gpio@fee03000 {
128 gpio-controller;
129 #gpio-cells = <1>;
130 reg = <0x3000 0x100>;
131 st,bank-name = "PIO8";
132 };
133 PIO9: gpio@fee04000 {
134 gpio-controller;
135 #gpio-cells = <1>;
136 reg = <0x4000 0x100>;
137 st,bank-name = "PIO9";
138 };
139 PIO10: gpio@fee05000 {
140 gpio-controller;
141 #gpio-cells = <1>;
142 reg = <0x5000 0x100>;
143 st,bank-name = "PIO10";
144 };
145 PIO11: gpio@fee06000 {
146 gpio-controller;
147 #gpio-cells = <1>;
148 reg = <0x6000 0x100>;
149 st,bank-name = "PIO11";
150 };
151 PIO12: gpio@fee07000 {
152 gpio-controller;
153 #gpio-cells = <1>;
154 reg = <0x7000 0x100>;
155 st,bank-name = "PIO12";
156 };
157 PIO30: gpio@fee08000 {
158 gpio-controller;
159 #gpio-cells = <1>;
160 reg = <0x8000 0x100>;
161 st,bank-name = "PIO30";
162 };
163 PIO31: gpio@fee09000 {
164 gpio-controller;
165 #gpio-cells = <1>;
166 reg = <0x9000 0x100>;
167 st,bank-name = "PIO31";
168 };
169 };
170
171 pin-controller-rear {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 compatible = "st,stih416-rear-pinctrl";
175 st,syscfg = <&syscfg_rear>;
176 ranges = <0 0xfe820000 0x6000>;
177
178 PIO13: gpio@fe820000 {
179 gpio-controller;
180 #gpio-cells = <1>;
181 reg = <0 0x100>;
182 st,bank-name = "PIO13";
183 };
184 PIO14: gpio@fe821000 {
185 gpio-controller;
186 #gpio-cells = <1>;
187 reg = <0x1000 0x100>;
188 st,bank-name = "PIO14";
189 };
190 PIO15: gpio@fe822000 {
191 gpio-controller;
192 #gpio-cells = <1>;
193 reg = <0x2000 0x100>;
194 st,bank-name = "PIO15";
195 };
196 PIO16: gpio@fe823000 {
197 gpio-controller;
198 #gpio-cells = <1>;
199 reg = <0x3000 0x100>;
200 st,bank-name = "PIO16";
201 };
202 PIO17: gpio@fe824000 {
203 gpio-controller;
204 #gpio-cells = <1>;
205 reg = <0x4000 0x100>;
206 st,bank-name = "PIO17";
207 };
208 PIO18: gpio@fe825000 {
209 gpio-controller;
210 #gpio-cells = <1>;
211 reg = <0x5000 0x100>;
212 st,bank-name = "PIO18";
213 st,retime-pin-mask = <0xf>;
214 };
215
216 serial2 {
217 pinctrl_serial2: serial2-0 {
218 st,pins {
219 tx = <&PIO17 4 ALT2 OUT>;
220 rx = <&PIO17 5 ALT2 IN>;
221 output-enable = <&PIO11 3 ALT2 OUT>;
222 };
223 };
224 };
225 };
226
227 pin-controller-fvdp-fe {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "st,stih416-fvdp-fe-pinctrl";
231 st,syscfg = <&syscfg_fvdp_fe>;
232 ranges = <0 0xfd6b0000 0x3000>;
233
234 PIO100: gpio@fd6b0000 {
235 gpio-controller;
236 #gpio-cells = <1>;
237 reg = <0 0x100>;
238 st,bank-name = "PIO100";
239 };
240 PIO101: gpio@fd6b1000 {
241 gpio-controller;
242 #gpio-cells = <1>;
243 reg = <0x1000 0x100>;
244 st,bank-name = "PIO101";
245 };
246 PIO102: gpio@fd6b2000 {
247 gpio-controller;
248 #gpio-cells = <1>;
249 reg = <0x2000 0x100>;
250 st,bank-name = "PIO102";
251 };
252 };
253
254 pin-controller-fvdp-lite {
255 #address-cells = <1>;
256 #size-cells = <1>;
257 compatible = "st,stih416-fvdp-lite-pinctrl";
258 st,syscfg = <&syscfg_fvdp_lite>;
259 ranges = <0 0xfd330000 0x5000>;
260
261 PIO103: gpio@fd330000 {
262 gpio-controller;
263 #gpio-cells = <1>;
264 reg = <0 0x100>;
265 st,bank-name = "PIO103";
266 };
267 PIO104: gpio@fd331000 {
268 gpio-controller;
269 #gpio-cells = <1>;
270 reg = <0x1000 0x100>;
271 st,bank-name = "PIO104";
272 };
273 PIO105: gpio@fd332000 {
274 gpio-controller;
275 #gpio-cells = <1>;
276 reg = <0x2000 0x100>;
277 st,bank-name = "PIO105";
278 };
279 PIO106: gpio@fd333000 {
280 gpio-controller;
281 #gpio-cells = <1>;
282 reg = <0x3000 0x100>;
283 st,bank-name = "PIO106";
284 };
285
286 PIO107: gpio@fd334000 {
287 gpio-controller;
288 #gpio-cells = <1>;
289 reg = <0x4000 0x100>;
290 st,bank-name = "PIO107";
291 st,retime-pin-mask = <0xf>;
292 };
293 };
294 };
295};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
new file mode 100644
index 000000000000..3cecd9689a49
--- /dev/null
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -0,0 +1,96 @@
1/*
2 * Copyright (C) 2012 STMicroelectronics Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi"
12/ {
13 L2: cache-controller {
14 compatible = "arm,pl310-cache";
15 reg = <0xfffe2000 0x1000>;
16 arm,data-latency = <3 3 3>;
17 arm,tag-latency = <2 2 2>;
18 cache-unified;
19 cache-level = <2>;
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 interrupt-parent = <&intc>;
26 ranges;
27 compatible = "simple-bus";
28
29 syscfg_sbc:sbc-syscfg@fe600000{
30 compatible = "st,stih416-sbc-syscfg", "syscon";
31 reg = <0xfe600000 0x1000>;
32 };
33
34 syscfg_front:front-syscfg@fee10000{
35 compatible = "st,stih416-front-syscfg", "syscon";
36 reg = <0xfee10000 0x1000>;
37 };
38
39 syscfg_rear:rear-syscfg@fe830000{
40 compatible = "st,stih416-rear-syscfg", "syscon";
41 reg = <0xfe830000 0x1000>;
42 };
43
44 /* MPE */
45 syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
46 compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
47 reg = <0xfddf0000 0x1000>;
48 };
49
50 syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
51 compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
52 reg = <0xfd6a0000 0x1000>;
53 };
54
55 syscfg_cpu:cpu-syscfg@fdde0000{
56 compatible = "st,stih416-cpu-syscfg", "syscon";
57 reg = <0xfdde0000 0x1000>;
58 };
59
60 syscfg_compo:compo-syscfg@fd320000{
61 compatible = "st,stih416-compo-syscfg", "syscon";
62 reg = <0xfd320000 0x1000>;
63 };
64
65 syscfg_transport:transport-syscfg@fd690000{
66 compatible = "st,stih416-transport-syscfg", "syscon";
67 reg = <0xfd690000 0x1000>;
68 };
69
70 syscfg_lpm:lpm-syscfg@fe4b5100{
71 compatible = "st,stih416-lpm-syscfg", "syscon";
72 reg = <0xfe4b5100 0x8>;
73 };
74
75 serial2: serial@fed32000{
76 compatible = "st,asc";
77 status = "disabled";
78 reg = <0xfed32000 0x2c>;
79 interrupts = <0 197 0>;
80 clocks = <&CLK_S_ICN_REG_0>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_serial2>;
83 };
84
85 /* SBC_UART1 */
86 sbc_serial1: serial@fe531000 {
87 compatible = "st,asc";
88 status = "disabled";
89 reg = <0xfe531000 0x2c>;
90 interrupts = <0 210 0>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_sbc_serial1>;
93 clocks = <&CLK_SYSIN>;
94 };
95 };
96};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
new file mode 100644
index 000000000000..8e694d2b8f5b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/ {
10
11 memory{
12 device_type = "memory";
13 reg = <0x60000000 0x40000000>;
14 };
15
16 chosen {
17 bootargs = "console=ttyAS0,115200";
18 linux,stdout-path = &serial2;
19 };
20
21 aliases {
22 ttyAS0 = &serial2;
23 };
24
25 soc {
26 serial2: serial@fed32000 {
27 status = "okay";
28 };
29
30 leds {
31 compatible = "gpio-leds";
32 fp_led {
33 #gpio-cells = <1>;
34 label = "Front Panel LED";
35 gpios = <&PIO105 7>;
36 linux,default-trigger = "heartbeat";
37 };
38 };
39
40 };
41};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
new file mode 100644
index 000000000000..133e18143b1b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/ {
10 memory{
11 device_type = "memory";
12 reg = <0x40000000 0x80000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyAS0,115200";
17 linux,stdout-path = &sbc_serial1;
18 };
19
20 aliases {
21 ttyAS0 = &sbc_serial1;
22 };
23 soc {
24 sbc_serial1: serial@fe531000 {
25 status = "okay";
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 red {
31 #gpio-cells = <1>;
32 label = "Front Panel LED";
33 gpios = <&PIO4 1>;
34 linux,default-trigger = "heartbeat";
35 };
36 green {
37 gpios = <&PIO4 7>;
38 default-state = "off";
39 };
40 };
41 };
42};
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
new file mode 100644
index 000000000000..7321403cab8a
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x.dtsi
@@ -0,0 +1,38 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4
5 cpus {
6 #address-cells = <1>;
7 #size-cells = <0>;
8 cpu@0 {
9 compatible = "arm,cortex-a9";
10 reg = <0>;
11 };
12 cpu@1 {
13 compatible = "arm,cortex-a9";
14 reg = <1>;
15 };
16 };
17
18 intc: interrupt-controller@fffe1000 {
19 compatible = "arm,cortex-a9-gic";
20 #interrupt-cells = <3>;
21 interrupt-controller;
22 reg = <0xfffe1000 0x1000>,
23 <0xfffe0100 0x100>;
24 };
25
26 scu@fffe0000 {
27 compatible = "arm,cortex-a9-scu";
28 reg = <0xfffe0000 0x1000>;
29 };
30
31 timer@fffe0200 {
32 interrupt-parent = <&intc>;
33 compatible = "arm,cortex-a9-global-timer";
34 reg = <0xfffe0200 0x100>;
35 interrupts = <1 11 0x04>;
36 clocks = <&arm_periph_clk>;
37 };
38};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-13 12:40:55 -0400