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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 17:42:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 17:42:51 -0400
commit42daabf62bfa3c00974b43f030dadcf704c0db59 (patch)
tree255f279cad48557227d974d67cbbc8390d057404
parent0bf6a210a43f7118d858806200127e421649fc4e (diff)
parent8c3d913888cfb0066d62831969c3a992f7e4aba5 (diff)
Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Arnd Bergmann: "These are changes that arrived a little late before the merge window or that have multiple dependencies on previous branches so they did not fit into one of the earlier ones. There are 10 branches merged here, a total of 39 non-merge commits. Contents are a mixed bag for the above reasons: * Two new SoC platforms: ST microelectronics stixxxx and the TI 'Nspire' graphing calculator. These should have been in the 'soc' branch but were a little late * Support for the Exynos 5420 variant in mach-exynos, which is based on the other exynos branches to avoid conflicts. * Various small changes for sh-mobile, ux500 and davinci * Common clk support for MSM" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits) ARM: ux500: bail out on alien cpus ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins serial: sh-sci: Initialise variables before access in sci_set_termios() ARM: stih41x: Add B2020 board support ARM: stih41x: Add B2000 board support ARM: sti: Add DEBUG_LL console support ARM: sti: Add STiH416 SOC support ARM: sti: Add STiH415 SOC support ARM: msm: Migrate to common clock framework ARM: msm: Make proc_comm clock control into a platform driver ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver ARM: msm: Remove clock-7x30.h include file ARM: msm: Remove custom clk_set_{max,min}_rate() API ARM: msm: Remove custom clk_set_flags() API msm: iommu: Use clk_set_rate() instead of clk_set_min_rate() msm: iommu: Convert to clk_prepare/unprepare msm_sdcc: Convert to clk_prepare/unprepare usb: otg: msm: Convert to clk_prepare/unprepare msm_serial: Use devm_clk_get() and properly return errors msm_serial: Convert to clk_prepare/unprepare ...
Diffstat
-rw-r--r--Documentation/arm/sti/overview.txt33
-rw-r--r--Documentation/arm/sti/stih415-overview.txt12
-rw-r--r--Documentation/arm/sti/stih416-overview.txt12
-rw-r--r--Documentation/devicetree/bindings/arm/nspire.txt14
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5420-clock.txt201
-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--MAINTAINERS9
-rw-r--r--arch/arm/Kconfig6
-rw-r--r--arch/arm/Kconfig.debug51
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/dts/Makefile8
-rw-r--r--arch/arm/boot/dts/da850-enbw-cmc.dts2
-rw-r--r--arch/arm/boot/dts/da850-evm.dts2
-rw-r--r--arch/arm/boot/dts/da850.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi111
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi78
-rw-r--r--arch/arm/boot/dts/exynos5420-pinctrl.dtsi680
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts33
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi148
-rw-r--r--arch/arm/boot/dts/nspire-classic.dtsi74
-rw-r--r--arch/arm/boot/dts/nspire-clp.dts45
-rw-r--r--arch/arm/boot/dts/nspire-cx.dts112
-rw-r--r--arch/arm/boot/dts/nspire-tp.dts44
-rw-r--r--arch/arm/boot/dts/nspire.dtsi175
-rw-r--r--arch/arm/boot/dts/st-pincfg.h71
-rw-r--r--arch/arm/boot/dts/stih415-b2000.dts15
-rw-r--r--arch/arm/boot/dts/stih415-b2020.dts15
-rw-r--r--arch/arm/boot/dts/stih415-clock.dtsi38
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi268
-rw-r--r--arch/arm/boot/dts/stih415.dtsi87
-rw-r--r--arch/arm/boot/dts/stih416-b2000.dts16
-rw-r--r--arch/arm/boot/dts/stih416-b2020.dts16
-rw-r--r--arch/arm/boot/dts/stih416-clock.dtsi41
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi295
-rw-r--r--arch/arm/boot/dts/stih416.dtsi96
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi41
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi42
-rw-r--r--arch/arm/boot/dts/stih41x.dtsi38
-rw-r--r--arch/arm/include/debug/nspire.S28
-rw-r--r--arch/arm/include/debug/sti.S61
-rw-r--r--arch/arm/mach-exynos/Kconfig10
-rw-r--r--arch/arm/mach-exynos/common.c18
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h7
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c1
-rw-r--r--arch/arm/mach-exynos/platsmp.c12
-rw-r--r--arch/arm/mach-msm/Makefile10
-rw-r--r--arch/arm/mach-msm/board-halibut.c2
-rw-r--r--arch/arm/mach-msm/board-msm7x30.c2
-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c2
-rw-r--r--arch/arm/mach-msm/board-trout-panel.c19
-rw-r--r--arch/arm/mach-msm/board-trout.c3
-rw-r--r--arch/arm/mach-msm/clock-7x30.h155
-rw-r--r--arch/arm/mach-msm/clock-debug.c130
-rw-r--r--arch/arm/mach-msm/clock-pcom.c149
-rw-r--r--arch/arm/mach-msm/clock-pcom.h31
-rw-r--r--arch/arm/mach-msm/clock.c166
-rw-r--r--arch/arm/mach-msm/clock.h51
-rw-r--r--arch/arm/mach-msm/devices-msm7x00.c12
-rw-r--r--arch/arm/mach-msm/devices-msm7x30.c15
-rw-r--r--arch/arm/mach-msm/devices-qsd8x50.c12
-rw-r--r--arch/arm/mach-msm/devices.h15
-rw-r--r--arch/arm/mach-msm/dma.c5
-rw-r--r--arch/arm/mach-msm/include/mach/board.h5
-rw-r--r--arch/arm/mach-msm/include/mach/clk.h9
-rw-r--r--arch/arm/mach-nspire/Kconfig16
-rw-r--r--arch/arm/mach-nspire/Makefile2
-rw-r--r--arch/arm/mach-nspire/Makefile.boot0
-rw-r--r--arch/arm/mach-nspire/clcd.c119
-rw-r--r--arch/arm/mach-nspire/clcd.h14
-rw-r--r--arch/arm/mach-nspire/mmio.h20
-rw-r--r--arch/arm/mach-nspire/nspire.c89
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c28
-rw-r--r--arch/arm/mach-sti/Kconfig45
-rw-r--r--arch/arm/mach-sti/Makefile2
-rw-r--r--arch/arm/mach-sti/board-dt.c48
-rw-r--r--arch/arm/mach-sti/headsmp.S44
-rw-r--r--arch/arm/mach-sti/platsmp.c117
-rw-r--r--arch/arm/mach-sti/smp.h17
-rw-r--r--arch/arm/mach-ux500/cache-l2x0.c3
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h8
-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c762
-rw-r--r--drivers/clocksource/exynos_mct.c35
-rw-r--r--drivers/iommu/msm_iommu_dev.c20
-rw-r--r--drivers/mmc/host/msm_sdcc.c14
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c118
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c2
-rw-r--r--drivers/pinctrl/pinctrl-samsung.h1
-rw-r--r--drivers/tty/serial/msm_serial.c35
-rw-r--r--drivers/tty/serial/samsung.c4
-rw-r--r--drivers/tty/serial/sh-sci.c104
-rw-r--r--drivers/usb/phy/phy-msm-usb.c38
-rw-r--r--include/linux/serial_sci.h12
-rw-r--r--include/uapi/linux/serial_core.h3
95 files changed, 4798 insertions, 790 deletions
diff --git a/Documentation/arm/sti/overview.txt b/Documentation/arm/sti/overview.txt
new file mode 100644
index 000000000000..1a4e93d6027f
--- /dev/null
+++ b/Documentation/arm/sti/overview.txt
@@ -0,0 +1,33 @@
1 STi ARM Linux Overview
2 ==========================
3
4Introduction
5------------
6
7 The ST Microelectronics Multimedia and Application Processors range of
8 CortexA9 System-on-Chip are supported by the 'STi' platform of
9 ARM Linux. Currently STiH415, STiH416 SOCs are supported with both
10 B2000 and B2020 Reference boards.
11
12
13 configuration
14 -------------
15
16 A generic configuration is provided for both STiH415/416, and can be used as the
17 default by
18 make stih41x_defconfig
19
20 Layout
21 ------
22 All the files for multiple machine families (STiH415, STiH416, and STiG125)
23 are located in the platform code contained in arch/arm/mach-sti
24
25 There is a generic board board-dt.c in the mach folder which support
26 Flattened Device Tree, which means, It works with any compatible board with
27 Device Trees.
28
29
30 Document Author
31 ---------------
32
33 Srinivas Kandagatla <srinivas.kandagatla@st.com>, (c) 2013 ST Microelectronics
diff --git a/Documentation/arm/sti/stih415-overview.txt b/Documentation/arm/sti/stih415-overview.txt
new file mode 100644
index 000000000000..1383e33f265d
--- /dev/null
+++ b/Documentation/arm/sti/stih415-overview.txt
@@ -0,0 +1,12 @@
1 STiH415 Overview
2 ================
3
4Introduction
5------------
6
7 The STiH415 is the next generation of HD, AVC set-top box processors
8 for satellite, cable, terrestrial and IP-STB markets.
9
10 Features
11 - ARM Cortex-A9 1.0 GHz, dual-core CPU
12 - SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
diff --git a/Documentation/arm/sti/stih416-overview.txt b/Documentation/arm/sti/stih416-overview.txt
new file mode 100644
index 000000000000..558444c201c6
--- /dev/null
+++ b/Documentation/arm/sti/stih416-overview.txt
@@ -0,0 +1,12 @@
1 STiH416 Overview
2 ================
3
4Introduction
5------------
6
7 The STiH416 is the next generation of HD, AVC set-top box processors
8 for satellite, cable, terrestrial and IP-STB markets.
9
10 Features
11 - ARM Cortex-A9 1.2 GHz dual core CPU
12 - SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
diff --git a/Documentation/devicetree/bindings/arm/nspire.txt b/Documentation/devicetree/bindings/arm/nspire.txt
new file mode 100644
index 000000000000..4d08518bd176
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/nspire.txt
@@ -0,0 +1,14 @@
1TI-NSPIRE calculators
2
3Required properties:
4- compatible: Compatible property value should contain "ti,nspire".
5 CX models should have "ti,nspire-cx"
6 Touchpad models should have "ti,nspire-tp"
7 Clickpad models should have "ti,nspire-clp"
8
9Example:
10
11/ {
12 model = "TI-NSPIRE CX";
13 compatible = "ti,nspire-cx";
14 ...
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
new file mode 100644
index 000000000000..9bcc4b1bff51
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -0,0 +1,201 @@
1* Samsung Exynos5420 Clock Controller
2
3The Exynos5420 clock controller generates and supplies clock to various
4controllers within the Exynos5420 SoC.
5
6Required Properties:
7
8- comptible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10
11- reg: physical base address of the controller and length of memory mapped
12 region.
13
14- #clock-cells: should be 1.
15
16The following is the list of clocks generated by the controller. Each clock is
17assigned an identifier and client nodes use this identifier to specify the
18clock which they consume.
19
20
21 [Core Clocks]
22
23 Clock ID
24 ----------------------------
25
26 fin_pll 1
27
28 [Clock Gate for Special Clocks]
29
30 Clock ID
31 ----------------------------
32 sclk_uart0 128
33 sclk_uart1 129
34 sclk_uart2 130
35 sclk_uart3 131
36 sclk_mmc0 132
37 sclk_mmc1 133
38 sclk_mmc2 134
39 sclk_spi0 135
40 sclk_spi1 136
41 sclk_spi2 137
42 sclk_i2s1 138
43 sclk_i2s2 139
44 sclk_pcm1 140
45 sclk_pcm2 141
46 sclk_spdif 142
47 sclk_hdmi 143
48 sclk_pixel 144
49 sclk_dp1 145
50 sclk_mipi1 146
51 sclk_fimd1 147
52 sclk_maudio0 148
53 sclk_maupcm0 149
54 sclk_usbd300 150
55 sclk_usbd301 151
56 sclk_usbphy300 152
57 sclk_usbphy301 153
58 sclk_unipro 154
59 sclk_pwm 155
60 sclk_gscl_wa 156
61 sclk_gscl_wb 157
62
63 [Peripheral Clock Gates]
64
65 Clock ID
66 ----------------------------
67
68 aclk66_peric 256
69 uart0 257
70 uart1 258
71 uart2 259
72 uart3 260
73 i2c0 261
74 i2c1 262
75 i2c2 263
76 i2c3 264
77 i2c4 265
78 i2c5 266
79 i2c6 267
80 i2c7 268
81 i2c_hdmi 269
82 tsadc 270
83 spi0 271
84 spi1 272
85 spi2 273
86 keyif 274
87 i2s1 275
88 i2s2 276
89 pcm1 277
90 pcm2 278
91 pwm 279
92 spdif 280
93 i2c8 281
94 i2c9 282
95 i2c10 283
96 aclk66_psgen 300
97 chipid 301
98 sysreg 302
99 tzpc0 303
100 tzpc1 304
101 tzpc2 305
102 tzpc3 306
103 tzpc4 307
104 tzpc5 308
105 tzpc6 309
106 tzpc7 310
107 tzpc8 311
108 tzpc9 312
109 hdmi_cec 313
110 seckey 314
111 mct 315
112 wdt 316
113 rtc 317
114 tmu 318
115 tmu_gpu 319
116 pclk66_gpio 330
117 aclk200_fsys2 350
118 mmc0 351
119 mmc1 352
120 mmc2 353
121 sromc 354
122 ufs 355
123 aclk200_fsys 360
124 tsi 361
125 pdma0 362
126 pdma1 363
127 rtic 364
128 usbh20 365
129 usbd300 366
130 usbd301 377
131 aclk400_mscl 380
132 mscl0 381
133 mscl1 382
134 mscl2 383
135 smmu_mscl0 384
136 smmu_mscl1 385
137 smmu_mscl2 386
138 aclk333 400
139 mfc 401
140 smmu_mfcl 402
141 smmu_mfcr 403
142 aclk200_disp1 410
143 dsim1 411
144 dp1 412
145 hdmi 413
146 aclk300_disp1 420
147 fimd1 421
148 smmu_fimd1 422
149 aclk166 430
150 mixer 431
151 aclk266 440
152 rotator 441
153 mdma1 442
154 smmu_rotator 443
155 smmu_mdma1 444
156 aclk300_jpeg 450
157 jpeg 451
158 jpeg2 452
159 smmu_jpeg 453
160 aclk300_gscl 460
161 smmu_gscl0 461
162 smmu_gscl1 462
163 gscl_wa 463
164 gscl_wb 464
165 gscl0 465
166 gscl1 466
167 clk_3aa 467
168 aclk266_g2d 470
169 sss 471
170 slim_sss 472
171 mdma0 473
172 aclk333_g2d 480
173 g2d 481
174 aclk333_432_gscl 490
175 smmu_3aa 491
176 smmu_fimcl0 492
177 smmu_fimcl1 493
178 smmu_fimcl3 494
179 fimc_lite3 495
180 aclk_g3d 500
181 g3d 501
182
183Example 1: An example of a clock controller node is listed below.
184
185 clock: clock-controller@0x10010000 {
186 compatible = "samsung,exynos5420-clock";
187 reg = <0x10010000 0x30000>;
188 #clock-cells = <1>;
189 };
190
191Example 2: UART controller node that consumes the clock generated by the clock
192 controller. Refer to the standard clock bindings for information
193 about 'clocks' and 'clock-names' property.
194
195 serial@13820000 {
196 compatible = "samsung,exynos4210-uart";
197 reg = <0x13820000 0x100>;
198 interrupts = <0 54 0>;
199 clocks = <&clock 259>, <&clock 130>;
200 clock-names = "uart", "clk_uart_baud0";
201 };
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 72e9cd1e89b7..36281e7a2a46 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -15,6 +15,7 @@ Required Properties:
15 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. 15 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
16 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. 16 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
17 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. 17 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
18 - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
18 19
19- reg: Base address of the pin controller hardware module and length of 20- reg: Base address of the pin controller hardware module and length of
20 the address space it occupies. 21 the address space it occupies.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index d247d1003987..db0457d61682 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -31,6 +31,7 @@ idt Integrated Device Technologies, Inc.
31img Imagination Technologies Ltd. 31img Imagination Technologies Ltd.
32intercontrol Inter Control Group 32intercontrol Inter Control Group
33linux Linux-specific binding 33linux Linux-specific binding
34lsi LSI Corp. (LSI Logic)
34marvell Marvell Technology Group Ltd. 35marvell Marvell Technology Group Ltd.
35maxim Maxim Integrated Products 36maxim Maxim Integrated Products
36mosaixtech Mosaix Technologies, Inc. 37mosaixtech Mosaix Technologies, Inc.
diff --git a/MAINTAINERS b/MAINTAINERS
index 8128b141b92b..e626794c3860 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1203,6 +1203,15 @@ M: Dinh Nguyen <dinguyen@altera.com>
1203S: Maintained 1203S: Maintained
1204F: drivers/clk/socfpga/ 1204F: drivers/clk/socfpga/
1205 1205
1206ARM/STI ARCHITECTURE
1207M: Srinivas Kandagatla <srinivas.kandagatla@st.com>
1208M: Stuart Menefy <stuart.menefy@st.com>
1209L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1210L: kernel@stlinux.com
1211W: http://www.stlinux.com
1212S: Maintained
1213F: arch/arm/mach-sti/
1214
1206ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT 1215ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
1207M: Lennert Buytenhek <kernel@wantstofly.org> 1216M: Lennert Buytenhek <kernel@wantstofly.org>
1208L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1217L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49fdc432512f..de7049bdea85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -625,8 +625,8 @@ config ARCH_MSM
625 bool "Qualcomm MSM" 625 bool "Qualcomm MSM"
626 select ARCH_REQUIRE_GPIOLIB 626 select ARCH_REQUIRE_GPIOLIB
627 select CLKDEV_LOOKUP 627 select CLKDEV_LOOKUP
628 select COMMON_CLK
628 select GENERIC_CLOCKEVENTS 629 select GENERIC_CLOCKEVENTS
629 select HAVE_CLK
630 help 630 help
631 Support for Qualcomm MSM/QSD based systems. This runs on the 631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory 632 apps processor of the MSM/QSD and depends on a shared memory
@@ -969,6 +969,8 @@ source "arch/arm/mach-netx/Kconfig"
969 969
970source "arch/arm/mach-nomadik/Kconfig" 970source "arch/arm/mach-nomadik/Kconfig"
971 971
972source "arch/arm/mach-nspire/Kconfig"
973
972source "arch/arm/plat-omap/Kconfig" 974source "arch/arm/plat-omap/Kconfig"
973 975
974source "arch/arm/mach-omap1/Kconfig" 976source "arch/arm/mach-omap1/Kconfig"
@@ -996,6 +998,8 @@ source "arch/arm/mach-socfpga/Kconfig"
996 998
997source "arch/arm/mach-spear/Kconfig" 999source "arch/arm/mach-spear/Kconfig"
998 1000
1001source "arch/arm/mach-sti/Kconfig"
1002
999source "arch/arm/mach-s3c24xx/Kconfig" 1003source "arch/arm/mach-s3c24xx/Kconfig"
1000 1004
1001if ARCH_S3C64XX 1005if ARCH_S3C64XX
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index ab95f07e1541..77c1411c9a91 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -362,6 +362,20 @@ choice
362 Say Y here if you want kernel low-level debugging support 362 Say Y here if you want kernel low-level debugging support
363 on NOMADIK based platforms. 363 on NOMADIK based platforms.
364 364
365 config DEBUG_NSPIRE_CLASSIC_UART
366 bool "Kernel low-level debugging via TI-NSPIRE 8250 UART"
367 depends on ARCH_NSPIRE
368 help
369 Say Y here if you want kernel low-level debugging support
370 on TI-NSPIRE classic models.
371
372 config DEBUG_NSPIRE_CX_UART
373 bool "Kernel low-level debugging via TI-NSPIRE PL011 UART"
374 depends on ARCH_NSPIRE
375 help
376 Say Y here if you want kernel low-level debugging support
377 on TI-NSPIRE CX models.
378
365 config DEBUG_OMAP2PLUS_UART 379 config DEBUG_OMAP2PLUS_UART
366 bool "Kernel low-level debugging messages via OMAP2PLUS UART" 380 bool "Kernel low-level debugging messages via OMAP2PLUS UART"
367 depends on ARCH_OMAP2PLUS 381 depends on ARCH_OMAP2PLUS
@@ -543,6 +557,16 @@ choice
543 This option selects UART0 on VIA/Wondermedia System-on-a-chip 557 This option selects UART0 on VIA/Wondermedia System-on-a-chip
544 devices, including VT8500, WM8505, WM8650 and WM8850. 558 devices, including VT8500, WM8505, WM8650 and WM8850.
545 559
560 config DEBUG_STI_UART
561 depends on ARCH_STI
562 bool "Use StiH415/416 ASC for low-level debug"
563 help
564 Say Y here if you want kernel low-level debugging support
565 on StiH415/416 based platforms like B2000, B2020.
566 It support UART2 and SBC_UART1.
567
568 If unsure, say N.
569
546 config DEBUG_LL_UART_NONE 570 config DEBUG_LL_UART_NONE
547 bool "No low-level debugging UART" 571 bool "No low-level debugging UART"
548 depends on !ARCH_MULTIPLATFORM 572 depends on !ARCH_MULTIPLATFORM
@@ -704,6 +728,30 @@ choice
704 728
705endchoice 729endchoice
706 730
731choice
732 prompt "Low-level debug console UART"
733 depends on DEBUG_LL && DEBUG_STI_UART
734
735 config STIH41X_DEBUG_ASC2
736 bool "ASC2 UART"
737 help
738 Say Y here if you want kernel low-level debugging support
739 on STiH415/416 based platforms like b2000, which has
740 default UART wired up to ASC2.
741
742 If unsure, say N.
743
744 config STIH41X_DEBUG_SBC_ASC1
745 bool "SBC ASC1 UART"
746 help
747 Say Y here if you want kernel low-level debugging support
748 on STiH415/416 based platforms like b2020. which has
749 default UART wired up to SBC ASC1.
750
751 If unsure, say N.
752
753endchoice
754
707config DEBUG_LL_INCLUDE 755config DEBUG_LL_INCLUDE
708 string 756 string
709 default "debug/bcm2835.S" if DEBUG_BCM2835 757 default "debug/bcm2835.S" if DEBUG_BCM2835
@@ -726,6 +774,8 @@ config DEBUG_LL_INCLUDE
726 DEBUG_MVEBU_UART_ALTERNATE 774 DEBUG_MVEBU_UART_ALTERNATE
727 default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART 775 default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
728 default "debug/nomadik.S" if DEBUG_NOMADIK_UART 776 default "debug/nomadik.S" if DEBUG_NOMADIK_UART
777 default "debug/nspire.S" if DEBUG_NSPIRE_CX_UART || \
778 DEBUG_NSPIRE_CLASSIC_UART
729 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART 779 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
730 default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART 780 default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
731 default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \ 781 default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
@@ -733,6 +783,7 @@ config DEBUG_LL_INCLUDE
733 default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART 783 default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART
734 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 784 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
735 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART 785 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
786 default "debug/sti.S" if DEBUG_STI_UART
736 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 787 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
737 default "debug/tegra.S" if DEBUG_TEGRA_UART 788 default "debug/tegra.S" if DEBUG_TEGRA_UART
738 default "debug/u300.S" if DEBUG_U300_UART 789 default "debug/u300.S" if DEBUG_U300_UART
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c01e4a728554..72caf82a8280 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -165,6 +165,7 @@ machine-$(CONFIG_ARCH_MXS) += mxs
165machine-$(CONFIG_ARCH_MVEBU) += mvebu 165machine-$(CONFIG_ARCH_MVEBU) += mvebu
166machine-$(CONFIG_ARCH_NETX) += netx 166machine-$(CONFIG_ARCH_NETX) += netx
167machine-$(CONFIG_ARCH_NOMADIK) += nomadik 167machine-$(CONFIG_ARCH_NOMADIK) += nomadik
168machine-$(CONFIG_ARCH_NSPIRE) += nspire
168machine-$(CONFIG_ARCH_OMAP1) += omap1 169machine-$(CONFIG_ARCH_OMAP1) += omap1
169machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 170machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
170machine-$(CONFIG_ARCH_ORION5X) += orion5x 171machine-$(CONFIG_ARCH_ORION5X) += orion5x
@@ -193,6 +194,7 @@ machine-$(CONFIG_ARCH_W90X900) += w90x900
193machine-$(CONFIG_FOOTBRIDGE) += footbridge 194machine-$(CONFIG_FOOTBRIDGE) += footbridge
194machine-$(CONFIG_ARCH_SOCFPGA) += socfpga 195machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
195machine-$(CONFIG_PLAT_SPEAR) += spear 196machine-$(CONFIG_PLAT_SPEAR) += spear
197machine-$(CONFIG_ARCH_STI) += sti
196machine-$(CONFIG_ARCH_VIRT) += virt 198machine-$(CONFIG_ARCH_VIRT) += virt
197machine-$(CONFIG_ARCH_ZYNQ) += zynq 199machine-$(CONFIG_ARCH_ZYNQ) += zynq
198machine-$(CONFIG_ARCH_SUNXI) += sunxi 200machine-$(CONFIG_ARCH_SUNXI) += sunxi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 962c0eee3039..641b3c9a7028 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
59 exynos5440-sd5v1.dtb \ 59 exynos5440-sd5v1.dtb \
60 exynos5250-smdk5250.dtb \ 60 exynos5250-smdk5250.dtb \
61 exynos5250-snow.dtb \ 61 exynos5250-snow.dtb \
62 exynos5420-smdk5420.dtb \
62 exynos5440-ssdk5440.dtb 63 exynos5440-ssdk5440.dtb
63dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 64dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
64 ecx-2000.dtb 65 ecx-2000.dtb
@@ -148,6 +149,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
148 imx28-sps1.dtb \ 149 imx28-sps1.dtb \
149 imx28-tx28.dtb 150 imx28-tx28.dtb
150dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb 151dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
152dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
153 nspire-tp.dtb \
154 nspire-clp.dtb
151dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ 155dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
152 omap3430-sdp.dtb \ 156 omap3430-sdp.dtb \
153 omap3-beagle.dtb \ 157 omap3-beagle.dtb \
@@ -197,6 +201,10 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
197 spear320-evb.dtb \ 201 spear320-evb.dtb \
198 spear320-hmi.dtb 202 spear320-hmi.dtb
199dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 203dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
204dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
205 stih416-b2000.dtb \
206 stih415-b2020.dtb \
207 stih416-b2020.dtb
200dtb-$(CONFIG_ARCH_SUNXI) += \ 208dtb-$(CONFIG_ARCH_SUNXI) += \
201 sun4i-a10-cubieboard.dtb \ 209 sun4i-a10-cubieboard.dtb \
202 sun4i-a10-mini-xplus.dtb \ 210 sun4i-a10-mini-xplus.dtb \
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
index 422fdb3fcfc1..e750ab9086d5 100644
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -10,7 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12/dts-v1/; 12/dts-v1/;
13/include/ "da850.dtsi" 13#include "da850.dtsi"
14 14
15/ { 15/ {
16 compatible = "enbw,cmc", "ti,da850"; 16 compatible = "enbw,cmc", "ti,da850";
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c914357c0d89..5bce7cc55cf3 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -8,7 +8,7 @@
8 * Free Software Foundation, version 2. 8 * Free Software Foundation, version 2.
9 */ 9 */
10/dts-v1/; 10/dts-v1/;
11/include/ "da850.dtsi" 11#include "da850.dtsi"
12 12
13/ { 13/ {
14 compatible = "ti,da850-evm", "ti,da850"; 14 compatible = "ti,da850-evm", "ti,da850";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 2c88313d2c7a..d70ba5504481 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -7,7 +7,7 @@
7 * Free Software Foundation; either version 2 of the License, or (at your 7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version. 8 * option) any later version.
9 */ 9 */
10/include/ "skeleton.dtsi" 10#include "skeleton.dtsi"
11 11
12/ { 12/ {
13 arm { 13 arm {
@@ -37,7 +37,7 @@
37 #size-cells = <0>; 37 #size-cells = <0>;
38 pinctrl-single,bit-per-mux; 38 pinctrl-single,bit-per-mux;
39 pinctrl-single,register-width = <32>; 39 pinctrl-single,register-width = <32>;
40 pinctrl-single,function-mask = <0xffffffff>; 40 pinctrl-single,function-mask = <0xf>;
41 status = "disabled"; 41 status = "disabled";
42 42
43 nand_cs3_pins: pinmux_nand_pins { 43 nand_cs3_pins: pinmux_nand_pins {
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
new file mode 100644
index 000000000000..f65e124c04a6
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -0,0 +1,111 @@
1/*
2 * Samsung's Exynos5 SoC series common device tree source
3 *
4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
8 * SoCs from Exynos5 series can include this file and provide values for SoCs
9 * specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "skeleton.dtsi"
17
18/ {
19 interrupt-parent = <&gic>;
20
21 chipid@10000000 {
22 compatible = "samsung,exynos4210-chipid";
23 reg = <0x10000000 0x100>;
24 };
25
26 combiner:interrupt-controller@10440000 {
27 compatible = "samsung,exynos4210-combiner";
28 #interrupt-cells = <2>;
29 interrupt-controller;
30 samsung,combiner-nr = <32>;
31 reg = <0x10440000 0x1000>;
32 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
33 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
34 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
35 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
37 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
38 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
39 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
40 };
41
42 gic:interrupt-controller@10481000 {
43 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
44 #interrupt-cells = <3>;
45 interrupt-controller;
46 reg = <0x10481000 0x1000>,
47 <0x10482000 0x1000>,
48 <0x10484000 0x2000>,
49 <0x10486000 0x2000>;
50 interrupts = <1 9 0xf04>;
51 };
52
53 dwmmc_0: dwmmc0@12200000 {
54 compatible = "samsung,exynos5250-dw-mshc";
55 interrupts = <0 75 0>;
56 #address-cells = <1>;
57 #size-cells = <0>;
58 };
59
60 dwmmc_1: dwmmc1@12210000 {
61 compatible = "samsung,exynos5250-dw-mshc";
62 interrupts = <0 76 0>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 };
66
67 dwmmc_2: dwmmc2@12220000 {
68 compatible = "samsung,exynos5250-dw-mshc";
69 interrupts = <0 77 0>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72 };
73
74 serial@12C00000 {
75 compatible = "samsung,exynos4210-uart";
76 reg = <0x12C00000 0x100>;
77 interrupts = <0 51 0>;
78 };
79
80 serial@12C10000 {
81 compatible = "samsung,exynos4210-uart";
82 reg = <0x12C10000 0x100>;
83 interrupts = <0 52 0>;
84 };
85
86 serial@12C20000 {
87 compatible = "samsung,exynos4210-uart";
88 reg = <0x12C20000 0x100>;
89 interrupts = <0 53 0>;
90 };
91
92 serial@12C30000 {
93 compatible = "samsung,exynos4210-uart";
94 reg = <0x12C30000 0x100>;
95 interrupts = <0 54 0>;
96 };
97
98 rtc {
99 compatible = "samsung,s3c6410-rtc";
100 reg = <0x101E0000 0x100>;
101 interrupts = <0 43 0>, <0 44 0>;
102 status = "disabled";
103 };
104
105 watchdog {
106 compatible = "samsung,s3c2410-wdt";
107 reg = <0x101D0000 0x100>;
108 interrupts = <0 42 0>;
109 status = "disabled";
110 };
111};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 964158c1844f..41cd625b6020 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,14 +17,13 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20#include "skeleton.dtsi" 20#include "exynos5.dtsi"
21#include "exynos5250-pinctrl.dtsi" 21#include "exynos5250-pinctrl.dtsi"
22 22
23#include <dt-bindings/clk/exynos-audss-clk.h> 23#include <dt-bindings/clk/exynos-audss-clk.h>
24 24
25/ { 25/ {
26 compatible = "samsung,exynos5250"; 26 compatible = "samsung,exynos5250";
27 interrupt-parent = <&gic>;
28 27
29 aliases { 28 aliases {
30 spi0 = &spi_0; 29 spi0 = &spi_0;
@@ -53,9 +52,20 @@
53 pinctrl3 = &pinctrl_3; 52 pinctrl3 = &pinctrl_3;
54 }; 53 };
55 54
56 chipid@10000000 { 55 cpus {
57 compatible = "samsung,exynos4210-chipid"; 56 #address-cells = <1>;
58 reg = <0x10000000 0x100>; 57 #size-cells = <0>;
58
59 cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0>;
63 };
64 cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 };
59 }; 69 };
60 70
61 pd_gsc: gsc-power-domain@0x10044000 { 71 pd_gsc: gsc-power-domain@0x10044000 {
@@ -80,17 +90,6 @@
80 #clock-cells = <1>; 90 #clock-cells = <1>;
81 }; 91 };
82 92
83 gic:interrupt-controller@10481000 {
84 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
85 #interrupt-cells = <3>;
86 interrupt-controller;
87 reg = <0x10481000 0x1000>,
88 <0x10482000 0x1000>,
89 <0x10484000 0x2000>,
90 <0x10486000 0x2000>;
91 interrupts = <1 9 0xf04>;
92 };
93
94 timer { 93 timer {
95 compatible = "arm,armv7-timer"; 94 compatible = "arm,armv7-timer";
96 interrupts = <1 13 0xf08>, 95 interrupts = <1 13 0xf08>,
@@ -99,22 +98,6 @@
99 <1 10 0xf08>; 98 <1 10 0xf08>;
100 }; 99 };
101 100
102 combiner:interrupt-controller@10440000 {
103 compatible = "samsung,exynos4210-combiner";
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 samsung,combiner-nr = <32>;
107 reg = <0x10440000 0x1000>;
108 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
109 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
110 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
111 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
112 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
113 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
114 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
115 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
116 };
117
118 mct@101C0000 { 101 mct@101C0000 {
119 compatible = "samsung,exynos4210-mct"; 102 compatible = "samsung,exynos4210-mct";
120 reg = <0x101C0000 0x800>; 103 reg = <0x101C0000 0x800>;
@@ -176,9 +159,6 @@
176 }; 159 };
177 160
178 watchdog { 161 watchdog {
179 compatible = "samsung,s3c2410-wdt";
180 reg = <0x101D0000 0x100>;
181 interrupts = <0 42 0>;
182 clocks = <&clock 336>; 162 clocks = <&clock 336>;
183 clock-names = "watchdog"; 163 clock-names = "watchdog";
184 }; 164 };
@@ -191,12 +171,8 @@
191 }; 171 };
192 172
193 rtc { 173 rtc {
194 compatible = "samsung,s3c6410-rtc";
195 reg = <0x101E0000 0x100>;
196 interrupts = <0 43 0>, <0 44 0>;
197 clocks = <&clock 337>; 174 clocks = <&clock 337>;
198 clock-names = "rtc"; 175 clock-names = "rtc";
199 status = "disabled";
200 }; 176 };
201 177
202 tmu@10060000 { 178 tmu@10060000 {
@@ -208,33 +184,21 @@
208 }; 184 };
209 185
210 serial@12C00000 { 186 serial@12C00000 {
211 compatible = "samsung,exynos4210-uart";
212 reg = <0x12C00000 0x100>;
213 interrupts = <0 51 0>;
214 clocks = <&clock 289>, <&clock 146>; 187 clocks = <&clock 289>, <&clock 146>;
215 clock-names = "uart", "clk_uart_baud0"; 188 clock-names = "uart", "clk_uart_baud0";
216 }; 189 };
217 190
218 serial@12C10000 { 191 serial@12C10000 {
219 compatible = "samsung,exynos4210-uart";
220 reg = <0x12C10000 0x100>;
221 interrupts = <0 52 0>;
222 clocks = <&clock 290>, <&clock 147>; 192 clocks = <&clock 290>, <&clock 147>;
223 clock-names = "uart", "clk_uart_baud0"; 193 clock-names = "uart", "clk_uart_baud0";
224 }; 194 };
225 195
226 serial@12C20000 { 196 serial@12C20000 {
227 compatible = "samsung,exynos4210-uart";
228 reg = <0x12C20000 0x100>;
229 interrupts = <0 53 0>;
230 clocks = <&clock 291>, <&clock 148>; 197 clocks = <&clock 291>, <&clock 148>;
231 clock-names = "uart", "clk_uart_baud0"; 198 clock-names = "uart", "clk_uart_baud0";
232 }; 199 };
233 200
234 serial@12C30000 { 201 serial@12C30000 {
235 compatible = "samsung,exynos4210-uart";
236 reg = <0x12C30000 0x100>;
237 interrupts = <0 54 0>;
238 clocks = <&clock 292>, <&clock 149>; 202 clocks = <&clock 292>, <&clock 149>;
239 clock-names = "uart", "clk_uart_baud0"; 203 clock-names = "uart", "clk_uart_baud0";
240 }; 204 };
@@ -413,31 +377,19 @@
413 }; 377 };
414 378
415 dwmmc_0: dwmmc0@12200000 { 379 dwmmc_0: dwmmc0@12200000 {
416 compatible = "samsung,exynos5250-dw-mshc";
417 reg = <0x12200000 0x1000>; 380 reg = <0x12200000 0x1000>;
418 interrupts = <0 75 0>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 clocks = <&clock 280>, <&clock 139>; 381 clocks = <&clock 280>, <&clock 139>;
422 clock-names = "biu", "ciu"; 382 clock-names = "biu", "ciu";
423 }; 383 };
424 384
425 dwmmc_1: dwmmc1@12210000 { 385 dwmmc_1: dwmmc1@12210000 {
426 compatible = "samsung,exynos5250-dw-mshc";
427 reg = <0x12210000 0x1000>; 386 reg = <0x12210000 0x1000>;
428 interrupts = <0 76 0>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&clock 281>, <&clock 140>; 387 clocks = <&clock 281>, <&clock 140>;
432 clock-names = "biu", "ciu"; 388 clock-names = "biu", "ciu";
433 }; 389 };
434 390
435 dwmmc_2: dwmmc2@12220000 { 391 dwmmc_2: dwmmc2@12220000 {
436 compatible = "samsung,exynos5250-dw-mshc";
437 reg = <0x12220000 0x1000>; 392 reg = <0x12220000 0x1000>;
438 interrupts = <0 77 0>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 clocks = <&clock 282>, <&clock 141>; 393 clocks = <&clock 282>, <&clock 141>;
442 clock-names = "biu", "ciu"; 394 clock-names = "biu", "ciu";
443 }; 395 };
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
new file mode 100644
index 000000000000..5848c425ae4d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -0,0 +1,680 @@
1/*
2 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
8 * tree nodes are listed in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/ {
16 pinctrl@13400000 {
17 gpy7: gpy7 {
18 gpio-controller;
19 #gpio-cells = <2>;
20
21 interrupt-controller;
22 #interrupt-cells = <2>;
23 };
24
25 gpx0: gpx0 {
26 gpio-controller;
27 #gpio-cells = <2>;
28
29 interrupt-controller;
30 interrupt-parent = <&combiner>;
31 #interrupt-cells = <2>;
32 interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
33 <26 0>, <26 1>, <27 0>, <27 1>;
34 };
35
36 gpx1: gpx1 {
37 gpio-controller;
38 #gpio-cells = <2>;
39
40 interrupt-controller;
41 interrupt-parent = <&combiner>;
42 #interrupt-cells = <2>;
43 interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
44 <30 0>, <30 1>, <31 0>, <31 1>;
45 };
46
47 gpx2: gpx2 {
48 gpio-controller;
49 #gpio-cells = <2>;
50
51 interrupt-controller;
52 #interrupt-cells = <2>;
53 };
54
55 gpx3: gpx3 {
56 gpio-controller;
57 #gpio-cells = <2>;
58
59 interrupt-controller;
60 #interrupt-cells = <2>;
61 };
62 };
63
64 pinctrl@13410000 {
65 gpc0: gpc0 {
66 gpio-controller;
67 #gpio-cells = <2>;
68
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 };
72
73 gpc1: gpc1 {
74 gpio-controller;
75 #gpio-cells = <2>;
76
77 interrupt-controller;
78 #interrupt-cells = <2>;
79 };
80
81 gpc2: gpc2 {
82 gpio-controller;
83 #gpio-cells = <2>;
84
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 };
88
89 gpc3: gpc3 {
90 gpio-controller;
91 #gpio-cells = <2>;
92
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 };
96
97 gpc4: gpc4 {
98 gpio-controller;
99 #gpio-cells = <2>;
100
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 };
104
105 gpd1: gpd1 {
106 gpio-controller;
107 #gpio-cells = <2>;
108
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpy0: gpy0 {
114 gpio-controller;
115 #gpio-cells = <2>;
116 };
117
118 gpy1: gpy1 {
119 gpio-controller;
120 #gpio-cells = <2>;
121 };
122
123 gpy2: gpy2 {
124 gpio-controller;
125 #gpio-cells = <2>;
126 };
127
128 gpy3: gpy3 {
129 gpio-controller;
130 #gpio-cells = <2>;
131 };
132
133 gpy4: gpy4 {
134 gpio-controller;
135 #gpio-cells = <2>;
136 };
137
138 gpy5: gpy5 {
139 gpio-controller;
140 #gpio-cells = <2>;
141 };
142
143 gpy6: gpy6 {
144 gpio-controller;
145 #gpio-cells = <2>;
146 };
147
148 sd0_clk: sd0-clk {
149 samsung,pins = "gpc0-0";
150 samsung,pin-function = <2>;
151 samsung,pin-pud = <0>;
152 samsung,pin-drv = <3>;
153 };
154
155 sd0_cmd: sd0-cmd {
156 samsung,pins = "gpc0-1";
157 samsung,pin-function = <2>;
158 samsung,pin-pud = <0>;
159 samsung,pin-drv = <3>;
160 };
161
162 sd0_cd: sd0-cd {
163 samsung,pins = "gpc0-2";
164 samsung,pin-function = <2>;
165 samsung,pin-pud = <3>;
166 samsung,pin-drv = <3>;
167 };
168
169 sd0_bus1: sd0-bus-width1 {
170 samsung,pins = "gpc0-3";
171 samsung,pin-function = <2>;
172 samsung,pin-pud = <3>;
173 samsung,pin-drv = <3>;
174 };
175
176 sd0_bus4: sd0-bus-width4 {
177 samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
178 samsung,pin-function = <2>;
179 samsung,pin-pud = <3>;
180 samsung,pin-drv = <3>;
181 };
182
183 sd0_bus8: sd0-bus-width8 {
184 samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
185 samsung,pin-function = <2>;
186 samsung,pin-pud = <3>;
187 samsung,pin-drv = <3>;
188 };
189
190 sd1_clk: sd1-clk {
191 samsung,pins = "gpc1-0";
192 samsung,pin-function = <2>;
193 samsung,pin-pud = <0>;
194 samsung,pin-drv = <3>;
195 };
196
197 sd1_cmd: sd1-cmd {
198 samsung,pins = "gpc1-1";
199 samsung,pin-function = <2>;
200 samsung,pin-pud = <0>;
201 samsung,pin-drv = <3>;
202 };
203
204 sd1_cd: sd1-cd {
205 samsung,pins = "gpc1-2";
206 samsung,pin-function = <2>;
207 samsung,pin-pud = <3>;
208 samsung,pin-drv = <3>;
209 };
210
211 sd1_int: sd1-int {
212 samsung,pins = "gpd1-1";
213 samsung,pin-function = <2>;
214 samsung,pin-pud = <3>;
215 samsung,pin-drv = <0>;
216 };
217
218 sd1_bus1: sd1-bus-width1 {
219 samsung,pins = "gpc1-3";
220 samsung,pin-function = <2>;
221 samsung,pin-pud = <3>;
222 samsung,pin-drv = <3>;
223 };
224
225 sd1_bus4: sd1-bus-width4 {
226 samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6";
227 samsung,pin-function = <2>;
228 samsung,pin-pud = <3>;
229 samsung,pin-drv = <3>;
230 };
231
232 sd1_bus8: sd1-bus-width8 {
233 samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7";
234 samsung,pin-function = <2>;
235 samsung,pin-pud = <3>;
236 samsung,pin-drv = <3>;
237 };
238
239 sd2_clk: sd2-clk {
240 samsung,pins = "gpc2-0";
241 samsung,pin-function = <2>;
242 samsung,pin-pud = <0>;
243 samsung,pin-drv = <3>;
244 };
245
246 sd2_cmd: sd2-cmd {
247 samsung,pins = "gpc2-1";
248 samsung,pin-function = <2>;
249 samsung,pin-pud = <0>;
250 samsung,pin-drv = <3>;
251 };
252
253 sd2_cd: sd2-cd {
254 samsung,pins = "gpc2-2";
255 samsung,pin-function = <2>;
256 samsung,pin-pud = <3>;
257 samsung,pin-drv = <3>;
258 };
259
260 sd2_bus1: sd2-bus-width1 {
261 samsung,pins = "gpc2-3";
262 samsung,pin-function = <2>;
263 samsung,pin-pud = <3>;
264 samsung,pin-drv = <3>;
265 };
266
267 sd2_bus4: sd2-bus-width4 {
268 samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
269 samsung,pin-function = <2>;
270 samsung,pin-pud = <3>;
271 samsung,pin-drv = <3>;
272 };
273 };
274
275 pinctrl@14000000 {
276 gpe0: gpe0 {
277 gpio-controller;
278 #gpio-cells = <2>;
279
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
283
284 gpe1: gpe1 {
285 gpio-controller;
286 #gpio-cells = <2>;
287
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 };
291
292 gpf0: gpf0 {
293 gpio-controller;
294 #gpio-cells = <2>;
295
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 };
299
300 gpf1: gpf1 {
301 gpio-controller;
302 #gpio-cells = <2>;
303
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
307
308 gpg0: gpg0 {
309 gpio-controller;
310 #gpio-cells = <2>;
311
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 };
315
316 gpg1: gpg1 {
317 gpio-controller;
318 #gpio-cells = <2>;
319
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
323
324 gpg2: gpg2 {
325 gpio-controller;
326 #gpio-cells = <2>;
327
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 };
331
332 gpj4: gpj4 {
333 gpio-controller;
334 #gpio-cells = <2>;
335
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
339
340 cam_gpio_a: cam-gpio-a {
341 samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
342 "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
343 "gpe1-0", "gpe1-1";
344 samsung,pin-function = <2>;
345 samsung,pin-pud = <0>;
346 samsung,pin-drv = <0>;
347 };
348
349 cam_gpio_b: cam-gpio-b {
350 samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
351 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
352 samsung,pin-function = <3>;
353 samsung,pin-pud = <0>;
354 samsung,pin-drv = <0>;
355 };
356
357 cam_i2c2_bus: cam-i2c2-bus {
358 samsung,pins = "gpf0-4", "gpf0-5";
359 samsung,pin-function = <2>;
360 samsung,pin-pud = <3>;
361 samsung,pin-drv = <0>;
362 };
363 cam_spi1_bus: cam-spi1-bus {
364 samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
365 samsung,pin-function = <4>;
366 samsung,pin-pud = <0>;
367 samsung,pin-drv = <0>;
368 };
369
370 cam_i2c1_bus: cam-i2c1-bus {
371 samsung,pins = "gpf0-2", "gpf0-3";
372 samsung,pin-function = <2>;
373 samsung,pin-pud = <3>;
374 samsung,pin-drv = <0>;
375 };
376
377 cam_i2c0_bus: cam-i2c0-bus {
378 samsung,pins = "gpf0-0", "gpf0-1";
379 samsung,pin-function = <2>;
380 samsung,pin-pud = <3>;
381 samsung,pin-drv = <0>;
382 };
383
384 cam_spi0_bus: cam-spi0-bus {
385 samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
386 samsung,pin-function = <2>;
387 samsung,pin-pud = <0>;
388 samsung,pin-drv = <0>;
389 };
390
391 cam_bayrgb_bus: cam-bayrgb-bus {
392 samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
393 "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
394 "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
395 "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
396 "gpg2-0";
397 samsung,pin-function = <2>;
398 samsung,pin-pud = <0>;
399 samsung,pin-drv = <0>;
400 };
401 };
402
403 pinctrl@14010000 {
404 gpa0: gpa0 {
405 gpio-controller;
406 #gpio-cells = <2>;
407
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 gpa1: gpa1 {
413 gpio-controller;
414 #gpio-cells = <2>;
415
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 };
419
420 gpa2: gpa2 {
421 gpio-controller;
422 #gpio-cells = <2>;
423
424 interrupt-controller;
425 #interrupt-cells = <2>;
426 };
427
428 gpb0: gpb0 {
429 gpio-controller;
430 #gpio-cells = <2>;
431
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
435
436 gpb1: gpb1 {
437 gpio-controller;
438 #gpio-cells = <2>;
439
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 };
443
444 gpb2: gpb2 {
445 gpio-controller;
446 #gpio-cells = <2>;
447
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 };
451
452 gpb3: gpb3 {
453 gpio-controller;
454 #gpio-cells = <2>;
455
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 };
459
460 gpb4: gpb4 {
461 gpio-controller;
462 #gpio-cells = <2>;
463
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 };
467
468 gph0: gph0 {
469 gpio-controller;
470 #gpio-cells = <2>;
471
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 };
475
476 uart0_data: uart0-data {
477 samsung,pins = "gpa0-0", "gpa0-1";
478 samsung,pin-function = <2>;
479 samsung,pin-pud = <0>;
480 samsung,pin-drv = <0>;
481 };
482
483 uart0_fctl: uart0-fctl {
484 samsung,pins = "gpa0-2", "gpa0-3";
485 samsung,pin-function = <2>;
486 samsung,pin-pud = <0>;
487 samsung,pin-drv = <0>;
488 };
489
490 uart1_data: uart1-data {
491 samsung,pins = "gpa0-4", "gpa0-5";
492 samsung,pin-function = <2>;
493 samsung,pin-pud = <0>;
494 samsung,pin-drv = <0>;
495 };
496
497 uart1_fctl: uart1-fctl {
498 samsung,pins = "gpa0-6", "gpa0-7";
499 samsung,pin-function = <2>;
500 samsung,pin-pud = <0>;
501 samsung,pin-drv = <0>;
502 };
503
504 i2c2_bus: i2c2-bus {
505 samsung,pins = "gpa0-6", "gpa0-7";
506 samsung,pin-function = <3>;
507 samsung,pin-pud = <3>;
508 samsung,pin-drv = <0>;
509 };
510
511 uart2_data: uart2-data {
512 samsung,pins = "gpa1-0", "gpa1-1";
513 samsung,pin-function = <2>;
514 samsung,pin-pud = <0>;
515 samsung,pin-drv = <0>;
516 };
517
518 uart2_fctl: uart2-fctl {
519 samsung,pins = "gpa1-2", "gpa1-3";
520 samsung,pin-function = <2>;
521 samsung,pin-pud = <0>;
522 samsung,pin-drv = <0>;
523 };
524
525 i2c3_bus: i2c3-bus {
526 samsung,pins = "gpa1-2", "gpa1-3";
527 samsung,pin-function = <3>;
528 samsung,pin-pud = <3>;
529 samsung,pin-drv = <0>;
530 };
531
532 uart3_data: uart3-data {
533 samsung,pins = "gpa1-4", "gpa1-5";
534 samsung,pin-function = <2>;
535 samsung,pin-pud = <0>;
536 samsung,pin-drv = <0>;
537 };
538
539 spi0_bus: spi0-bus {
540 samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3";
541 samsung,pin-function = <2>;
542 samsung,pin-pud = <3>;
543 samsung,pin-drv = <0>;
544 };
545
546 spi1_bus: spi1-bus {
547 samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
548 samsung,pin-function = <2>;
549 samsung,pin-pud = <3>;
550 samsung,pin-drv = <0>;
551 };
552
553 i2c4_hs_bus: i2c4-hs-bus {
554 samsung,pins = "gpa2-0", "gpa2-1";
555 samsung,pin-function = <3>;
556 samsung,pin-pud = <3>;
557 samsung,pin-drv = <0>;
558 };
559
560 i2c5_hs_bus: i2c5-hs-bus {
561 samsung,pins = "gpa2-2", "gpa2-3";
562 samsung,pin-function = <3>;
563 samsung,pin-pud = <3>;
564 samsung,pin-drv = <0>;
565 };
566
567 i2s1_bus: i2s1-bus {
568 samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
569 "gpb0-4";
570 samsung,pin-function = <2>;
571 samsung,pin-pud = <0>;
572 samsung,pin-drv = <0>;
573 };
574
575 pcm1_bus: pcm1-bus {
576 samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
577 "gpb0-4";
578 samsung,pin-function = <3>;
579 samsung,pin-pud = <0>;
580 samsung,pin-drv = <0>;
581 };
582
583 i2s2_bus: i2s2-bus {
584 samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
585 "gpb1-4";
586 samsung,pin-function = <2>;
587 samsung,pin-pud = <0>;
588 samsung,pin-drv = <0>;
589 };
590
591 pcm2_bus: pcm2-bus {
592 samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
593 "gpb1-4";
594 samsung,pin-function = <3>;
595 samsung,pin-pud = <0>;
596 samsung,pin-drv = <0>;
597 };
598
599 spdif_bus: spdif-bus {
600 samsung,pins = "gpb1-0", "gpb1-1";
601 samsung,pin-function = <4>;
602 samsung,pin-pud = <0>;
603 samsung,pin-drv = <0>;
604 };
605
606 spi2_bus: spi2-bus {
607 samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
608 samsung,pin-function = <5>;
609 samsung,pin-pud = <3>;
610 samsung,pin-drv = <0>;
611 };
612
613 i2c6_hs_bus: i2c6-hs-bus {
614 samsung,pins = "gpb1-3", "gpb1-4";
615 samsung,pin-function = <4>;
616 samsung,pin-pud = <3>;
617 samsung,pin-drv = <0>;
618 };
619
620 i2c7_hs_bus: i2c7-hs-bus {
621 samsung,pins = "gpb2-2", "gpb2-3";
622 samsung,pin-function = <3>;
623 samsung,pin-pud = <3>;
624 samsung,pin-drv = <0>;
625 };
626
627 i2c0_bus: i2c0-bus {
628 samsung,pins = "gpb3-0", "gpb3-1";
629 samsung,pin-function = <2>;
630 samsung,pin-pud = <3>;
631 samsung,pin-drv = <0>;
632 };
633
634 i2c1_bus: i2c1-bus {
635 samsung,pins = "gpb3-2", "gpb3-3";
636 samsung,pin-function = <2>;
637 samsung,pin-pud = <3>;
638 samsung,pin-drv = <0>;
639 };
640
641 i2c8_hs_bus: i2c8-hs-bus {
642 samsung,pins = "gpb3-4", "gpb3-5";
643 samsung,pin-function = <2>;
644 samsung,pin-pud = <3>;
645 samsung,pin-drv = <0>;
646 };
647
648 i2c9_hs_bus: i2c9-hs-bus {
649 samsung,pins = "gpb3-6", "gpb3-7";
650 samsung,pin-function = <2>;
651 samsung,pin-pud = <3>;
652 samsung,pin-drv = <0>;
653 };
654
655 i2c10_hs_bus: i2c10-hs-bus {
656 samsung,pins = "gpb4-0", "gpb4-1";
657 samsung,pin-function = <2>;
658 samsung,pin-pud = <3>;
659 samsung,pin-drv = <0>;
660 };
661 };
662
663 pinctrl@03860000 {
664 gpz: gpz {
665 gpio-controller;
666 #gpio-cells = <2>;
667
668 interrupt-controller;
669 #interrupt-cells = <2>;
670 };
671
672 i2s0_bus: i2s0-bus {
673 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
674 "gpz-4", "gpz-5", "gpz-6";
675 samsung,pin-function = <2>;
676 samsung,pin-pud = <0>;
677 samsung,pin-drv = <0>;
678 };
679 };
680};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
new file mode 100644
index 000000000000..08607df6a180
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,33 @@
1/*
2 * SAMSUNG SMDK5420 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13#include "exynos5420.dtsi"
14
15/ {
16 model = "Samsung SMDK5420 board based on EXYNOS5420";
17 compatible = "samsung,smdk5420", "samsung,exynos5420";
18
19 memory {
20 reg = <0x20000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttySAC2,115200 init=/linuxrc";
25 };
26
27 fixed-rate-clocks {
28 oscclk {
29 compatible = "samsung,exynos5420-oscclk";
30 clock-frequency = <24000000>;
31 };
32 };
33};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
new file mode 100644
index 000000000000..8c54c4b74f0e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -0,0 +1,148 @@
1/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "exynos5.dtsi"
17/include/ "exynos5420-pinctrl.dtsi"
18/ {
19 compatible = "samsung,exynos5420";
20
21 aliases {
22 pinctrl0 = &pinctrl_0;
23 pinctrl1 = &pinctrl_1;
24 pinctrl2 = &pinctrl_2;
25 pinctrl3 = &pinctrl_3;
26 pinctrl4 = &pinctrl_4;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a15";
36 reg = <0x0>;
37 clock-frequency = <1800000000>;
38 };
39
40 cpu1: cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x1>;
44 clock-frequency = <1800000000>;
45 };
46
47 cpu2: cpu@2 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0x2>;
51 clock-frequency = <1800000000>;
52 };
53
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <0x3>;
58 clock-frequency = <1800000000>;
59 };
60 };
61
62 clock: clock-controller@0x10010000 {
63 compatible = "samsung,exynos5420-clock";
64 reg = <0x10010000 0x30000>;
65 #clock-cells = <1>;
66 };
67
68 mct@101C0000 {
69 compatible = "samsung,exynos4210-mct";
70 reg = <0x101C0000 0x800>;
71 interrupt-controller;
72 #interrups-cells = <1>;
73 interrupt-parent = <&mct_map>;
74 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
75 clocks = <&clock 1>, <&clock 315>;
76 clock-names = "fin_pll", "mct";
77
78 mct_map: mct-map {
79 #interrupt-cells = <1>;
80 #address-cells = <0>;
81 #size-cells = <0>;
82 interrupt-map = <0 &combiner 23 3>,
83 <1 &combiner 23 4>,
84 <2 &combiner 25 2>,
85 <3 &combiner 25 3>,
86 <4 &gic 0 120 0>,
87 <5 &gic 0 121 0>,
88 <6 &gic 0 122 0>,
89 <7 &gic 0 123 0>;
90 };
91 };
92
93 pinctrl_0: pinctrl@13400000 {
94 compatible = "samsung,exynos5420-pinctrl";
95 reg = <0x13400000 0x1000>;
96 interrupts = <0 45 0>;
97
98 wakeup-interrupt-controller {
99 compatible = "samsung,exynos4210-wakeup-eint";
100 interrupt-parent = <&gic>;
101 interrupts = <0 32 0>;
102 };
103 };
104
105 pinctrl_1: pinctrl@13410000 {
106 compatible = "samsung,exynos5420-pinctrl";
107 reg = <0x13410000 0x1000>;
108 interrupts = <0 78 0>;
109 };
110
111 pinctrl_2: pinctrl@14000000 {
112 compatible = "samsung,exynos5420-pinctrl";
113 reg = <0x14000000 0x1000>;
114 interrupts = <0 46 0>;
115 };
116
117 pinctrl_3: pinctrl@14010000 {
118 compatible = "samsung,exynos5420-pinctrl";
119 reg = <0x14010000 0x1000>;
120 interrupts = <0 50 0>;
121 };
122
123 pinctrl_4: pinctrl@03860000 {
124 compatible = "samsung,exynos5420-pinctrl";
125 reg = <0x03860000 0x1000>;
126 interrupts = <0 47 0>;
127 };
128
129 serial@12C00000 {
130 clocks = <&clock 257>, <&clock 128>;
131 clock-names = "uart", "clk_uart_baud0";
132 };
133
134 serial@12C10000 {
135 clocks = <&clock 258>, <&clock 129>;
136 clock-names = "uart", "clk_uart_baud0";
137 };
138
139 serial@12C20000 {
140 clocks = <&clock 259>, <&clock 130>;
141 clock-names = "uart", "clk_uart_baud0";
142 };
143
144 serial@12C30000 {
145 clocks = <&clock 260>, <&clock 131>;
146 clock-names = "uart", "clk_uart_baud0";
147 };
148};
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
new file mode 100644
index 000000000000..9565199bce7a
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -0,0 +1,74 @@
1/*
2 * linux/arch/arm/boot/nspire-classic.dts
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/include/ "nspire.dtsi"
13
14&lcd {
15 lcd-type = "classic";
16};
17
18&fast_timer {
19 /* compatible = "lsi,zevio-timer"; */
20 reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
21};
22
23&uart {
24 compatible = "ns16550";
25 reg-shift = <2>;
26 reg-io-width = <4>;
27 clocks = <&apb_pclk>;
28 no-loopback-test;
29};
30
31&timer0 {
32 /* compatible = "lsi,zevio-timer"; */
33 reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
34};
35
36&timer1 {
37 compatible = "lsi,zevio-timer";
38 reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
39};
40
41&keypad {
42 active-low;
43
44};
45
46&base_clk {
47 compatible = "lsi,nspire-classic-clock";
48};
49
50&ahb_clk {
51 compatible = "lsi,nspire-classic-ahb-divider";
52};
53
54/ {
55 memory {
56 device_type = "memory";
57 reg = <0x10000000 0x2000000>; /* 32 MB */
58 };
59
60 ahb {
61 #address-cells = <1>;
62 #size-cells = <1>;
63
64 intc: interrupt-controller@DC000000 {
65 compatible = "lsi,zevio-intc";
66 interrupt-controller;
67 reg = <0xDC000000 0x1000>;
68 #interrupt-cells = <1>;
69 };
70 };
71 chosen {
72 bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
73 };
74};
diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts
new file mode 100644
index 000000000000..fa5a044656de
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-clp.dts
@@ -0,0 +1,45 @@
1/*
2 * linux/arch/arm/boot/nspire-clp.dts
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12
13/include/ "nspire-classic.dtsi"
14
15&keypad {
16 linux,keymap = <
17 0x0000001c 0x0001001c 0x00020039
18 0x0004002c 0x00050034 0x00060015
19 0x0007000b 0x0008002d 0x01000033
20 0x0101004e 0x01020011 0x01030004
21 0x0104002f 0x01050003 0x01060016
22 0x01070002 0x01080014 0x02000062
23 0x0201000c 0x0202001f 0x02030007
24 0x02040013 0x02050006 0x02060010
25 0x02070005 0x02080019 0x03000027
26 0x03010037 0x03020018 0x0303000a
27 0x03040031 0x03050009 0x03060032
28 0x03070008 0x03080026 0x04000028
29 0x04010035 0x04020025 0x04040024
30 0x04060017 0x04080023 0x05000028
31 0x05020022 0x0503001b 0x05040021
32 0x0505001a 0x05060012 0x0507006f
33 0x05080020 0x0509002a 0x0601001c
34 0x0602002e 0x06030068 0x06040030
35 0x0605006d 0x0606001e 0x06070001
36 0x0608002b 0x0609000f 0x07000067
37 0x0702006a 0x0704006c 0x07060069
38 0x0707000e 0x0708001d 0x070a000d
39 >;
40};
41
42/ {
43 model = "TI-NSPIRE Clickpad";
44 compatible = "ti,nspire-clp";
45};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
new file mode 100644
index 000000000000..375b924f60d8
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -0,0 +1,112 @@
1/*
2 * linux/arch/arm/boot/nspire-cx.dts
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12
13/include/ "nspire.dtsi"
14
15&lcd {
16 lcd-type = "cx";
17};
18
19&fast_timer {
20 /* compatible = "arm,sp804", "arm,primecell"; */
21};
22
23&uart {
24 compatible = "arm,pl011", "arm,primecell";
25
26 clocks = <&uart_clk>, <&apb_pclk>;
27 clock-names = "uart_clk", "apb_pclk";
28};
29
30&timer0 {
31 compatible = "arm,sp804", "arm,primecell";
32};
33
34&timer1 {
35 compatible = "arm,sp804", "arm,primecell";
36};
37
38&base_clk {
39 compatible = "lsi,nspire-cx-clock";
40};
41
42&ahb_clk {
43 compatible = "lsi,nspire-cx-ahb-divider";
44};
45
46&keypad {
47 linux,keymap = <
48 0x0000001c 0x0001001c 0x00040039
49 0x0005002c 0x00060015 0x0007000b
50 0x0008000f 0x0100002d 0x01010011
51 0x0102002f 0x01030004 0x01040016
52 0x01050014 0x0106001f 0x01070002
53 0x010a006a 0x02000013 0x02010010
54 0x02020019 0x02030007 0x02040018
55 0x02050031 0x02060032 0x02070005
56 0x02080028 0x0209006c 0x03000026
57 0x03010025 0x03020024 0x0303000a
58 0x03040017 0x03050023 0x03060022
59 0x03070008 0x03080035 0x03090069
60 0x04000021 0x04010012 0x04020020
61 0x0404002e 0x04050030 0x0406001e
62 0x0407000d 0x04080037 0x04090067
63 0x05010038 0x0502000c 0x0503001b
64 0x05040034 0x0505001a 0x05060006
65 0x05080027 0x0509000e 0x050a006f
66 0x0600002b 0x0602004e 0x06030068
67 0x06040003 0x0605006d 0x06060009
68 0x06070001 0x0609000f 0x0708002a
69 0x0709001d 0x070a0033 >;
70};
71
72/ {
73 model = "TI-NSPIRE CX";
74 compatible = "ti,nspire-cx";
75
76 memory {
77 device_type = "memory";
78 reg = <0x10000000 0x4000000>; /* 64 MB */
79 };
80
81 uart_clk: uart_clk {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <12000000>;
85 };
86
87 ahb {
88 #address-cells = <1>;
89 #size-cells = <1>;
90
91 intc: interrupt-controller@DC000000 {
92 compatible = "arm,pl190-vic";
93 interrupt-controller;
94 reg = <0xDC000000 0x1000>;
95 #interrupt-cells = <1>;
96 };
97
98 apb@90000000 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101
102 i2c@90050000 {
103 compatible = "snps,designware-i2c";
104 reg = <0x90050000 0x1000>;
105 interrupts = <20>;
106 };
107 };
108 };
109 chosen {
110 bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
111 };
112};
diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts
new file mode 100644
index 000000000000..621391ce6ed6
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-tp.dts
@@ -0,0 +1,44 @@
1/*
2 * linux/arch/arm/boot/nspire-tp.dts
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12
13/include/ "nspire-classic.dtsi"
14
15&keypad {
16 linux,keymap = <
17 0x0000001c 0x0001001c 0x00040039
18 0x0005002c 0x00060015 0x0007000b
19 0x0008000f 0x0100002d 0x01010011
20 0x0102002f 0x01030004 0x01040016
21 0x01050014 0x0106001f 0x01070002
22 0x010a006a 0x02000013 0x02010010
23 0x02020019 0x02030007 0x02040018
24 0x02050031 0x02060032 0x02070005
25 0x02080028 0x0209006c 0x03000026
26 0x03010025 0x03020024 0x0303000a
27 0x03040017 0x03050023 0x03060022
28 0x03070008 0x03080035 0x03090069
29 0x04000021 0x04010012 0x04020020
30 0x0404002e 0x04050030 0x0406001e
31 0x0407000d 0x04080037 0x04090067
32 0x05010038 0x0502000c 0x0503001b
33 0x05040034 0x0505001a 0x05060006
34 0x05080027 0x0509000e 0x050a006f
35 0x0600002b 0x0602004e 0x06030068
36 0x06040003 0x0605006d 0x06060009
37 0x06070001 0x0609000f 0x0708002a
38 0x0709001d 0x070a0033 >;
39};
40
41/ {
42 model = "TI-NSPIRE Touchpad";
43 compatible = "ti,nspire-tp";
44};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
new file mode 100644
index 000000000000..a22ffe633b49
--- /dev/null
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -0,0 +1,175 @@
1/*
2 * linux/arch/arm/boot/nspire.dtsi
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&intc>;
16
17 cpus {
18 cpu@0 {
19 compatible = "arm,arm926ejs";
20 };
21 };
22
23 bootrom: bootrom@00000000 {
24 reg = <0x00000000 0x80000>;
25 };
26
27 sram: sram@A4000000 {
28 device = "memory";
29 reg = <0xA4000000 0x20000>;
30 };
31
32 timer_clk: timer_clk {
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <32768>;
36 };
37
38 base_clk: base_clk {
39 #clock-cells = <0>;
40 reg = <0x900B0024 0x4>;
41 };
42
43 ahb_clk: ahb_clk {
44 #clock-cells = <0>;
45 reg = <0x900B0024 0x4>;
46 clocks = <&base_clk>;
47 };
48
49 apb_pclk: apb_pclk {
50 #clock-cells = <0>;
51 compatible = "fixed-factor-clock";
52 clock-div = <2>;
53 clock-mult = <1>;
54 clocks = <&ahb_clk>;
55 };
56
57 ahb {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 spi: spi@A9000000 {
64 reg = <0xA9000000 0x1000>;
65 };
66
67 usb0: usb@B0000000 {
68 reg = <0xB0000000 0x1000>;
69 interrupts = <8>;
70 };
71
72 usb1: usb@B4000000 {
73 reg = <0xB4000000 0x1000>;
74 interrupts = <9>;
75 status = "disabled";
76 };
77
78 lcd: lcd@C0000000 {
79 compatible = "arm,pl111", "arm,primecell";
80 reg = <0xC0000000 0x1000>;
81 interrupts = <21>;
82
83 clocks = <&apb_pclk>;
84 clock-names = "apb_pclk";
85 };
86
87 adc: adc@C4000000 {
88 reg = <0xC4000000 0x1000>;
89 interrupts = <11>;
90 };
91
92 tdes: crypto@C8010000 {
93 reg = <0xC8010000 0x1000>;
94 };
95
96 sha256: crypto@CC000000 {
97 reg = <0xCC000000 0x1000>;
98 };
99
100 apb@90000000 {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 clock-ranges;
105 ranges;
106
107 gpio: gpio@90000000 {
108 reg = <0x90000000 0x1000>;
109 interrupts = <7>;
110 };
111
112 fast_timer: timer@90010000 {
113 reg = <0x90010000 0x1000>;
114 interrupts = <17>;
115 };
116
117 uart: serial@90020000 {
118 reg = <0x90020000 0x1000>;
119 interrupts = <1>;
120 };
121
122 timer0: timer@900C0000 {
123 reg = <0x900C0000 0x1000>;
124
125 clocks = <&timer_clk>;
126 };
127
128 timer1: timer@900D0000 {
129 reg = <0x900D0000 0x1000>;
130 interrupts = <19>;
131
132 clocks = <&timer_clk>;
133 };
134
135 watchdog: watchdog@90060000 {
136 compatible = "arm,amba-primecell";
137 reg = <0x90060000 0x1000>;
138 interrupts = <3>;
139 };
140
141 rtc: rtc@90090000 {
142 reg = <0x90090000 0x1000>;
143 interrupts = <4>;
144 };
145
146 misc: misc@900A0000 {
147 reg = <0x900A0000 0x1000>;
148 };
149
150 pwr: pwr@900B0000 {
151 reg = <0x900B0000 0x1000>;
152 interrupts = <15>;
153 };
154
155 keypad: input@900E0000 {
156 compatible = "ti,nspire-keypad";
157 reg = <0x900E0000 0x1000>;
158 interrupts = <16>;
159
160 scan-interval = <1000>;
161 row-delay = <200>;
162
163 clocks = <&apb_pclk>;
164 };
165
166 contrast: contrast@900F0000 {
167 reg = <0x900F0000 0x1000>;
168 };
169
170 led: led@90110000 {
171 reg = <0x90110000 0x1000>;
172 };
173 };
174 };
175};
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
new file mode 100644
index 000000000000..8c45d85ac13e
--- /dev/null
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -0,0 +1,71 @@
1#ifndef _ST_PINCFG_H_
2#define _ST_PINCFG_H_
3
4/* Alternate functions */
5#define ALT1 1
6#define ALT2 2
7#define ALT3 3
8#define ALT4 4
9#define ALT5 5
10#define ALT6 6
11#define ALT7 7
12
13/* Output enable */
14#define OE (1 << 27)
15/* Pull Up */
16#define PU (1 << 26)
17/* Open Drain */
18#define OD (1 << 26)
19#define RT (1 << 23)
20#define INVERTCLK (1 << 22)
21#define CLKNOTDATA (1 << 21)
22#define DOUBLE_EDGE (1 << 20)
23#define CLK_A (0 << 18)
24#define CLK_B (1 << 18)
25#define CLK_C (2 << 18)
26#define CLK_D (3 << 18)
27
28/* User-frendly defines for Pin Direction */
29 /* oe = 0, pu = 0, od = 0 */
30#define IN (0)
31 /* oe = 0, pu = 1, od = 0 */
32#define IN_PU (PU)
33 /* oe = 1, pu = 0, od = 0 */
34#define OUT (OE)
35 /* oe = 1, pu = 0, od = 1 */
36#define BIDIR (OE | OD)
37 /* oe = 1, pu = 1, od = 1 */
38#define BIDIR_PU (OE | PU | OD)
39
40/* RETIME_TYPE */
41/*
42 * B Mode
43 * Bypass retime with optional delay parameter
44 */
45#define BYPASS (0)
46/*
47 * R0, R1, R0D, R1D modes
48 * single-edge data non inverted clock, retime data with clk
49 */
50#define SE_NICLK_IO (RT)
51/*
52 * RIV0, RIV1, RIV0D, RIV1D modes
53 * single-edge data inverted clock, retime data with clk
54 */
55#define SE_ICLK_IO (RT | INVERTCLK)
56/*
57 * R0E, R1E, R0ED, R1ED modes
58 * double-edge data, retime data with clk
59 */
60#define DE_IO (RT | DOUBLE_EDGE)
61/*
62 * CIV0, CIV1 modes with inverted clock
63 * Retiming the clk pins will park clock & reduce the noise within the core.
64 */
65#define ICLK (RT | CLKNOTDATA | INVERTCLK)
66/*
67 * CLK0, CLK1 modes with non-inverted clock
68 * Retiming the clk pins will park clock & reduce the noise within the core.
69 */
70#define NICLK (RT | CLKNOTDATA)
71#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts
new file mode 100644
index 000000000000..d4af53160435
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2000.dts
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih415.dtsi"
11#include "stih41x-b2000.dtsi"
12/ {
13 model = "STiH415 B2000 Board";
14 compatible = "st,stih415", "st,stih415-b2000";
15};
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000000000000..442b019e9a3a
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih415.dtsi"
11#include "stih41x-b2020.dtsi"
12/ {
13 model = "STiH415 B2020 Board";
14 compatible = "st,stih415", "st,stih415-b2020";
15};
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
new file mode 100644
index 000000000000..174c799df741
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/ {
9 clocks {
10 /*
11 * Fixed 30MHz oscillator input to SoC
12 */
13 CLK_SYSIN: CLK_SYSIN {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <30000000>;
17 };
18
19 /*
20 * ARM Peripheral clock for timers
21 */
22 arm_periph_clk: arm_periph_clk {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <500000000>;
26 };
27
28 /*
29 * Bootloader initialized system infrastructure clock for
30 * serial devices.
31 */
32 CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <100000000>;
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
new file mode 100644
index 000000000000..1d322b24d1e4
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -0,0 +1,268 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10/ {
11
12 aliases {
13 gpio0 = &PIO0;
14 gpio1 = &PIO1;
15 gpio2 = &PIO2;
16 gpio3 = &PIO3;
17 gpio4 = &PIO4;
18 gpio5 = &PIO5;
19 gpio6 = &PIO6;
20 gpio7 = &PIO7;
21 gpio8 = &PIO8;
22 gpio9 = &PIO9;
23 gpio10 = &PIO10;
24 gpio11 = &PIO11;
25 gpio12 = &PIO12;
26 gpio13 = &PIO13;
27 gpio14 = &PIO14;
28 gpio15 = &PIO15;
29 gpio16 = &PIO16;
30 gpio17 = &PIO17;
31 gpio18 = &PIO18;
32 gpio19 = &PIO100;
33 gpio20 = &PIO101;
34 gpio21 = &PIO102;
35 gpio22 = &PIO103;
36 gpio23 = &PIO104;
37 gpio24 = &PIO105;
38 gpio25 = &PIO106;
39 gpio26 = &PIO107;
40 };
41
42 soc {
43 pin-controller-sbc {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "st,stih415-sbc-pinctrl";
47 st,syscfg = <&syscfg_sbc>;
48 ranges = <0 0xfe610000 0x5000>;
49
50 PIO0: gpio@fe610000 {
51 gpio-controller;
52 #gpio-cells = <1>;
53 reg = <0 0x100>;
54 st,bank-name = "PIO0";
55 };
56 PIO1: gpio@fe611000 {
57 gpio-controller;
58 #gpio-cells = <1>;
59 reg = <0x1000 0x100>;
60 st,bank-name = "PIO1";
61 };
62 PIO2: gpio@fe612000 {
63 gpio-controller;
64 #gpio-cells = <1>;
65 reg = <0x2000 0x100>;
66 st,bank-name = "PIO2";
67 };
68 PIO3: gpio@fe613000 {
69 gpio-controller;
70 #gpio-cells = <1>;
71 reg = <0x3000 0x100>;
72 st,bank-name = "PIO3";
73 };
74 PIO4: gpio@fe614000 {
75 gpio-controller;
76 #gpio-cells = <1>;
77 reg = <0x4000 0x100>;
78 st,bank-name = "PIO4";
79 };
80
81 sbc_serial1 {
82 pinctrl_sbc_serial1:sbc_serial1 {
83 st,pins {
84 tx = <&PIO2 6 ALT3 OUT>;
85 rx = <&PIO2 7 ALT3 IN>;
86 };
87 };
88 };
89 };
90
91 pin-controller-front {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "st,stih415-front-pinctrl";
95 st,syscfg = <&syscfg_front>;
96 ranges = <0 0xfee00000 0x8000>;
97
98 PIO5: gpio@fee00000 {
99 gpio-controller;
100 #gpio-cells = <1>;
101 reg = <0 0x100>;
102 st,bank-name = "PIO5";
103 };
104 PIO6: gpio@fee01000 {
105 gpio-controller;
106 #gpio-cells = <1>;
107 reg = <0x1000 0x100>;
108 st,bank-name = "PIO6";
109 };
110 PIO7: gpio@fee02000 {
111 gpio-controller;
112 #gpio-cells = <1>;
113 reg = <0x2000 0x100>;
114 st,bank-name = "PIO7";
115 };
116 PIO8: gpio@fee03000 {
117 gpio-controller;
118 #gpio-cells = <1>;
119 reg = <0x3000 0x100>;
120 st,bank-name = "PIO8";
121 };
122 PIO9: gpio@fee04000 {
123 gpio-controller;
124 #gpio-cells = <1>;
125 reg = <0x4000 0x100>;
126 st,bank-name = "PIO9";
127 };
128 PIO10: gpio@fee05000 {
129 gpio-controller;
130 #gpio-cells = <1>;
131 reg = <0x5000 0x100>;
132 st,bank-name = "PIO10";
133 };
134 PIO11: gpio@fee06000 {
135 gpio-controller;
136 #gpio-cells = <1>;
137 reg = <0x6000 0x100>;
138 st,bank-name = "PIO11";
139 };
140 PIO12: gpio@fee07000 {
141 gpio-controller;
142 #gpio-cells = <1>;
143 reg = <0x7000 0x100>;
144 st,bank-name = "PIO12";
145 };
146 };
147
148 pin-controller-rear {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "st,stih415-rear-pinctrl";
152 st,syscfg = <&syscfg_rear>;
153 ranges = <0 0xfe820000 0x8000>;
154
155 PIO13: gpio@fe820000 {
156 gpio-controller;
157 #gpio-cells = <1>;
158 reg = <0 0x100>;
159 st,bank-name = "PIO13";
160 };
161 PIO14: gpio@fe821000 {
162 gpio-controller;
163 #gpio-cells = <1>;
164 reg = <0x1000 0x100>;
165 st,bank-name = "PIO14";
166 };
167 PIO15: gpio@fe822000 {
168 gpio-controller;
169 #gpio-cells = <1>;
170 reg = <0x2000 0x100>;
171 st,bank-name = "PIO15";
172 };
173 PIO16: gpio@fe823000 {
174 gpio-controller;
175 #gpio-cells = <1>;
176 reg = <0x3000 0x100>;
177 st,bank-name = "PIO16";
178 };
179 PIO17: gpio@fe824000 {
180 gpio-controller;
181 #gpio-cells = <1>;
182 reg = <0x4000 0x100>;
183 st,bank-name = "PIO17";
184 };
185 PIO18: gpio@fe825000 {
186 gpio-controller;
187 #gpio-cells = <1>;
188 reg = <0x5000 0x100>;
189 st,bank-name = "PIO18";
190 };
191
192 serial2 {
193 pinctrl_serial2: serial2-0 {
194 st,pins {
195 tx = <&PIO17 4 ALT2 OUT>;
196 rx = <&PIO17 5 ALT2 IN>;
197 };
198 };
199 };
200 };
201
202 pin-controller-left {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "st,stih415-left-pinctrl";
206 st,syscfg = <&syscfg_left>;
207 ranges = <0 0xfd6b0000 0x3000>;
208
209 PIO100: gpio@fd6b0000 {
210 gpio-controller;
211 #gpio-cells = <1>;
212 reg = <0 0x100>;
213 st,bank-name = "PIO100";
214 };
215 PIO101: gpio@fd6b1000 {
216 gpio-controller;
217 #gpio-cells = <1>;
218 reg = <0x1000 0x100>;
219 st,bank-name = "PIO101";
220 };
221 PIO102: gpio@fd6b2000 {
222 gpio-controller;
223 #gpio-cells = <1>;
224 reg = <0x2000 0x100>;
225 st,bank-name = "PIO102";
226 };
227 };
228
229 pin-controller-right {
230 #address-cells = <1>;
231 #size-cells = <1>;
232 compatible = "st,stih415-right-pinctrl";
233 st,syscfg = <&syscfg_right>;
234 ranges = <0 0xfd330000 0x5000>;
235
236 PIO103: gpio@fd330000 {
237 gpio-controller;
238 #gpio-cells = <1>;
239 reg = <0 0x100>;
240 st,bank-name = "PIO103";
241 };
242 PIO104: gpio@fd331000 {
243 gpio-controller;
244 #gpio-cells = <1>;
245 reg = <0x1000 0x100>;
246 st,bank-name = "PIO104";
247 };
248 PIO105: gpio@fd332000 {
249 gpio-controller;
250 #gpio-cells = <1>;
251 reg = <0x2000 0x100>;
252 st,bank-name = "PIO105";
253 };
254 PIO106: gpio@fd333000 {
255 gpio-controller;
256 #gpio-cells = <1>;
257 reg = <0x3000 0x100>;
258 st,bank-name = "PIO106";
259 };
260 PIO107: gpio@fd334000 {
261 gpio-controller;
262 #gpio-cells = <1>;
263 reg = <0x4000 0x100>;
264 st,bank-name = "PIO107";
265 };
266 };
267 };
268};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
new file mode 100644
index 000000000000..74ab8ded4b49
--- /dev/null
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -0,0 +1,87 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih41x.dtsi"
10#include "stih415-clock.dtsi"
11#include "stih415-pinctrl.dtsi"
12/ {
13
14 L2: cache-controller {
15 compatible = "arm,pl310-cache";
16 reg = <0xfffe2000 0x1000>;
17 arm,data-latency = <3 2 2>;
18 arm,tag-latency = <1 1 1>;
19 cache-unified;
20 cache-level = <2>;
21 };
22
23 soc {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 interrupt-parent = <&intc>;
27 ranges;
28 compatible = "simple-bus";
29
30 syscfg_sbc: sbc-syscfg@fe600000{
31 compatible = "st,stih415-sbc-syscfg", "syscon";
32 reg = <0xfe600000 0xb4>;
33 };
34
35 syscfg_front: front-syscfg@fee10000{
36 compatible = "st,stih415-front-syscfg", "syscon";
37 reg = <0xfee10000 0x194>;
38 };
39
40 syscfg_rear: rear-syscfg@fe830000{
41 compatible = "st,stih415-rear-syscfg", "syscon";
42 reg = <0xfe830000 0x190>;
43 };
44
45 /* MPE syscfgs */
46 syscfg_left: left-syscfg@fd690000{
47 compatible = "st,stih415-left-syscfg", "syscon";
48 reg = <0xfd690000 0x78>;
49 };
50
51 syscfg_right: right-syscfg@fd320000{
52 compatible = "st,stih415-right-syscfg", "syscon";
53 reg = <0xfd320000 0x180>;
54 };
55
56 syscfg_system: system-syscfg@fdde0000 {
57 compatible = "st,stih415-system-syscfg", "syscon";
58 reg = <0xfdde0000 0x15c>;
59 };
60
61 syscfg_lpm: lpm-syscfg@fe4b5100{
62 compatible = "st,stih415-lpm-syscfg", "syscon";
63 reg = <0xfe4b5100 0x08>;
64 };
65
66 serial2: serial@fed32000 {
67 compatible = "st,asc";
68 status = "disabled";
69 reg = <0xfed32000 0x2c>;
70 interrupts = <0 197 0>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_serial2>;
73 clocks = <&CLKS_ICN_REG_0>;
74 };
75
76 /* SBC comms block ASCs in SASG1 */
77 sbc_serial1: serial@fe531000 {
78 compatible = "st,asc";
79 status = "disabled";
80 reg = <0xfe531000 0x2c>;
81 interrupts = <0 210 0>;
82 clocks = <&CLK_SYSIN>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_sbc_serial1>;
85 };
86 };
87};
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts
new file mode 100644
index 000000000000..a5eb6eee10bf
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2000.dts
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih416.dtsi"
11#include "stih41x-b2000.dtsi"
12
13/ {
14 compatible = "st,stih416", "st,stih416-b2000";
15 model = "STiH416 B2000";
16};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
new file mode 100644
index 000000000000..276f28da573a
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih416.dtsi"
11#include "stih41x-b2020.dtsi"
12/ {
13 model = "STiH416 B2020";
14 compatible = "st,stih416", "st,stih416-b2020";
15
16};
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
new file mode 100644
index 000000000000..7026bf1158d8
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics R&D Limited
3 * <stlinux-devel@stlinux.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/ {
10 clocks {
11 /*
12 * Fixed 30MHz oscillator inputs to SoC
13 */
14 CLK_SYSIN: CLK_SYSIN {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <30000000>;
18 clock-output-names = "CLK_SYSIN";
19 };
20
21 /*
22 * ARM Peripheral clock for timers
23 */
24 arm_periph_clk: arm_periph_clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <600000000>;
28 };
29
30 /*
31 * Bootloader initialized system infrastructure clock for
32 * serial devices.
33 */
34 CLK_S_ICN_REG_0: clockgenA0@4 {
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <100000000>;
38 clock-output-names = "CLK_S_ICN_REG_0";
39 };
40 };
41};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
new file mode 100644
index 000000000000..957b21a71b4b
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -0,0 +1,295 @@
1
2/*
3 * Copyright (C) 2013 STMicroelectronics Limited.
4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#include "st-pincfg.h"
11/ {
12
13 aliases {
14 gpio0 = &PIO0;
15 gpio1 = &PIO1;
16 gpio2 = &PIO2;
17 gpio3 = &PIO3;
18 gpio4 = &PIO4;
19 gpio5 = &PIO40;
20 gpio6 = &PIO5;
21 gpio7 = &PIO6;
22 gpio8 = &PIO7;
23 gpio9 = &PIO8;
24 gpio10 = &PIO9;
25 gpio11 = &PIO10;
26 gpio12 = &PIO11;
27 gpio13 = &PIO12;
28 gpio14 = &PIO30;
29 gpio15 = &PIO31;
30 gpio16 = &PIO13;
31 gpio17 = &PIO14;
32 gpio18 = &PIO15;
33 gpio19 = &PIO16;
34 gpio20 = &PIO17;
35 gpio21 = &PIO18;
36 gpio22 = &PIO100;
37 gpio23 = &PIO101;
38 gpio24 = &PIO102;
39 gpio25 = &PIO103;
40 gpio26 = &PIO104;
41 gpio27 = &PIO105;
42 gpio28 = &PIO106;
43 gpio29 = &PIO107;
44 };
45
46 soc {
47 pin-controller-sbc {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stih416-sbc-pinctrl";
51 st,syscfg = <&syscfg_sbc>;
52 ranges = <0 0xfe610000 0x6000>;
53
54 PIO0: gpio@fe610000 {
55 gpio-controller;
56 #gpio-cells = <1>;
57 reg = <0 0x100>;
58 st,bank-name = "PIO0";
59 };
60 PIO1: gpio@fe611000 {
61 gpio-controller;
62 #gpio-cells = <1>;
63 reg = <0x1000 0x100>;
64 st,bank-name = "PIO1";
65 };
66 PIO2: gpio@fe612000 {
67 gpio-controller;
68 #gpio-cells = <1>;
69 reg = <0x2000 0x100>;
70 st,bank-name = "PIO2";
71 };
72 PIO3: gpio@fe613000 {
73 gpio-controller;
74 #gpio-cells = <1>;
75 reg = <0x3000 0x100>;
76 st,bank-name = "PIO3";
77 };
78 PIO4: gpio@fe614000 {
79 gpio-controller;
80 #gpio-cells = <1>;
81 reg = <0x4000 0x100>;
82 st,bank-name = "PIO4";
83 };
84 PIO40: gpio@fe615000 {
85 gpio-controller;
86 #gpio-cells = <1>;
87 reg = <0x5000 0x100>;
88 st,bank-name = "PIO40";
89 st,retime-pin-mask = <0x7f>;
90 };
91
92 sbc_serial1 {
93 pinctrl_sbc_serial1: sbc_serial1 {
94 st,pins {
95 tx = <&PIO2 6 ALT3 OUT>;
96 rx = <&PIO2 7 ALT3 IN>;
97 };
98 };
99 };
100 };
101
102 pin-controller-front {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "st,stih416-front-pinctrl";
106 st,syscfg = <&syscfg_front>;
107 ranges = <0 0xfee00000 0x10000>;
108
109 PIO5: gpio@fee00000 {
110 gpio-controller;
111 #gpio-cells = <1>;
112 reg = <0 0x100>;
113 st,bank-name = "PIO5";
114 };
115 PIO6: gpio@fee01000 {
116 gpio-controller;
117 #gpio-cells = <1>;
118 reg = <0x1000 0x100>;
119 st,bank-name = "PIO6";
120 };
121 PIO7: gpio@fee02000 {
122 gpio-controller;
123 #gpio-cells = <1>;
124 reg = <0x2000 0x100>;
125 st,bank-name = "PIO7";
126 };
127 PIO8: gpio@fee03000 {
128 gpio-controller;
129 #gpio-cells = <1>;
130 reg = <0x3000 0x100>;
131 st,bank-name = "PIO8";
132 };
133 PIO9: gpio@fee04000 {
134 gpio-controller;
135 #gpio-cells = <1>;
136 reg = <0x4000 0x100>;
137 st,bank-name = "PIO9";
138 };
139 PIO10: gpio@fee05000 {
140 gpio-controller;
141 #gpio-cells = <1>;
142 reg = <0x5000 0x100>;
143 st,bank-name = "PIO10";
144 };
145 PIO11: gpio@fee06000 {
146 gpio-controller;
147 #gpio-cells = <1>;
148 reg = <0x6000 0x100>;
149 st,bank-name = "PIO11";
150 };
151 PIO12: gpio@fee07000 {
152 gpio-controller;
153 #gpio-cells = <1>;
154 reg = <0x7000 0x100>;
155 st,bank-name = "PIO12";
156 };
157 PIO30: gpio@fee08000 {
158 gpio-controller;
159 #gpio-cells = <1>;
160 reg = <0x8000 0x100>;
161 st,bank-name = "PIO30";
162 };
163 PIO31: gpio@fee09000 {
164 gpio-controller;
165 #gpio-cells = <1>;
166 reg = <0x9000 0x100>;
167 st,bank-name = "PIO31";
168 };
169 };
170
171 pin-controller-rear {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 compatible = "st,stih416-rear-pinctrl";
175 st,syscfg = <&syscfg_rear>;
176 ranges = <0 0xfe820000 0x6000>;
177
178 PIO13: gpio@fe820000 {
179 gpio-controller;
180 #gpio-cells = <1>;
181 reg = <0 0x100>;
182 st,bank-name = "PIO13";
183 };
184 PIO14: gpio@fe821000 {
185 gpio-controller;
186 #gpio-cells = <1>;
187 reg = <0x1000 0x100>;
188 st,bank-name = "PIO14";
189 };
190 PIO15: gpio@fe822000 {
191 gpio-controller;
192 #gpio-cells = <1>;
193 reg = <0x2000 0x100>;
194 st,bank-name = "PIO15";
195 };
196 PIO16: gpio@fe823000 {
197 gpio-controller;
198 #gpio-cells = <1>;
199 reg = <0x3000 0x100>;
200 st,bank-name = "PIO16";
201 };
202 PIO17: gpio@fe824000 {
203 gpio-controller;
204 #gpio-cells = <1>;
205 reg = <0x4000 0x100>;
206 st,bank-name = "PIO17";
207 };
208 PIO18: gpio@fe825000 {
209 gpio-controller;
210 #gpio-cells = <1>;
211 reg = <0x5000 0x100>;
212 st,bank-name = "PIO18";
213 st,retime-pin-mask = <0xf>;
214 };
215
216 serial2 {
217 pinctrl_serial2: serial2-0 {
218 st,pins {
219 tx = <&PIO17 4 ALT2 OUT>;
220 rx = <&PIO17 5 ALT2 IN>;
221 output-enable = <&PIO11 3 ALT2 OUT>;
222 };
223 };
224 };
225 };
226
227 pin-controller-fvdp-fe {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "st,stih416-fvdp-fe-pinctrl";
231 st,syscfg = <&syscfg_fvdp_fe>;
232 ranges = <0 0xfd6b0000 0x3000>;
233
234 PIO100: gpio@fd6b0000 {
235 gpio-controller;
236 #gpio-cells = <1>;
237 reg = <0 0x100>;
238 st,bank-name = "PIO100";
239 };
240 PIO101: gpio@fd6b1000 {
241 gpio-controller;
242 #gpio-cells = <1>;
243 reg = <0x1000 0x100>;
244 st,bank-name = "PIO101";
245 };
246 PIO102: gpio@fd6b2000 {
247 gpio-controller;
248 #gpio-cells = <1>;
249 reg = <0x2000 0x100>;
250 st,bank-name = "PIO102";
251 };
252 };
253
254 pin-controller-fvdp-lite {
255 #address-cells = <1>;
256 #size-cells = <1>;
257 compatible = "st,stih416-fvdp-lite-pinctrl";
258 st,syscfg = <&syscfg_fvdp_lite>;
259 ranges = <0 0xfd330000 0x5000>;
260
261 PIO103: gpio@fd330000 {
262 gpio-controller;
263 #gpio-cells = <1>;
264 reg = <0 0x100>;
265 st,bank-name = "PIO103";
266 };
267 PIO104: gpio@fd331000 {
268 gpio-controller;
269 #gpio-cells = <1>;
270 reg = <0x1000 0x100>;
271 st,bank-name = "PIO104";
272 };
273 PIO105: gpio@fd332000 {
274 gpio-controller;
275 #gpio-cells = <1>;
276 reg = <0x2000 0x100>;
277 st,bank-name = "PIO105";
278 };
279 PIO106: gpio@fd333000 {
280 gpio-controller;
281 #gpio-cells = <1>;
282 reg = <0x3000 0x100>;
283 st,bank-name = "PIO106";
284 };
285
286 PIO107: gpio@fd334000 {
287 gpio-controller;
288 #gpio-cells = <1>;
289 reg = <0x4000 0x100>;
290 st,bank-name = "PIO107";
291 st,retime-pin-mask = <0xf>;
292 };
293 };
294 };
295};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
new file mode 100644
index 000000000000..3cecd9689a49
--- /dev/null
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -0,0 +1,96 @@
1/*
2 * Copyright (C) 2012 STMicroelectronics Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi"
12/ {
13 L2: cache-controller {
14 compatible = "arm,pl310-cache";
15 reg = <0xfffe2000 0x1000>;
16 arm,data-latency = <3 3 3>;
17 arm,tag-latency = <2 2 2>;
18 cache-unified;
19 cache-level = <2>;
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 interrupt-parent = <&intc>;
26 ranges;
27 compatible = "simple-bus";
28
29 syscfg_sbc:sbc-syscfg@fe600000{
30 compatible = "st,stih416-sbc-syscfg", "syscon";
31 reg = <0xfe600000 0x1000>;
32 };
33
34 syscfg_front:front-syscfg@fee10000{
35 compatible = "st,stih416-front-syscfg", "syscon";
36 reg = <0xfee10000 0x1000>;
37 };
38
39 syscfg_rear:rear-syscfg@fe830000{
40 compatible = "st,stih416-rear-syscfg", "syscon";
41 reg = <0xfe830000 0x1000>;
42 };
43
44 /* MPE */
45 syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
46 compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
47 reg = <0xfddf0000 0x1000>;
48 };
49
50 syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
51 compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
52 reg = <0xfd6a0000 0x1000>;
53 };
54
55 syscfg_cpu:cpu-syscfg@fdde0000{
56 compatible = "st,stih416-cpu-syscfg", "syscon";
57 reg = <0xfdde0000 0x1000>;
58 };
59
60 syscfg_compo:compo-syscfg@fd320000{
61 compatible = "st,stih416-compo-syscfg", "syscon";
62 reg = <0xfd320000 0x1000>;
63 };
64
65 syscfg_transport:transport-syscfg@fd690000{
66 compatible = "st,stih416-transport-syscfg", "syscon";
67 reg = <0xfd690000 0x1000>;
68 };
69
70 syscfg_lpm:lpm-syscfg@fe4b5100{
71 compatible = "st,stih416-lpm-syscfg", "syscon";
72 reg = <0xfe4b5100 0x8>;
73 };
74
75 serial2: serial@fed32000{
76 compatible = "st,asc";
77 status = "disabled";
78 reg = <0xfed32000 0x2c>;
79 interrupts = <0 197 0>;
80 clocks = <&CLK_S_ICN_REG_0>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_serial2>;
83 };
84
85 /* SBC_UART1 */
86 sbc_serial1: serial@fe531000 {
87 compatible = "st,asc";
88 status = "disabled";
89 reg = <0xfe531000 0x2c>;
90 interrupts = <0 210 0>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_sbc_serial1>;
93 clocks = <&CLK_SYSIN>;
94 };
95 };
96};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
new file mode 100644
index 000000000000..8e694d2b8f5b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/ {
10
11 memory{
12 device_type = "memory";
13 reg = <0x60000000 0x40000000>;
14 };
15
16 chosen {
17 bootargs = "console=ttyAS0,115200";
18 linux,stdout-path = &serial2;
19 };
20
21 aliases {
22 ttyAS0 = &serial2;
23 };
24
25 soc {
26 serial2: serial@fed32000 {
27 status = "okay";
28 };
29
30 leds {
31 compatible = "gpio-leds";
32 fp_led {
33 #gpio-cells = <1>;
34 label = "Front Panel LED";
35 gpios = <&PIO105 7>;
36 linux,default-trigger = "heartbeat";
37 };
38 };
39
40 };
41};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
new file mode 100644
index 000000000000..133e18143b1b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/ {
10 memory{
11 device_type = "memory";
12 reg = <0x40000000 0x80000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyAS0,115200";
17 linux,stdout-path = &sbc_serial1;
18 };
19
20 aliases {
21 ttyAS0 = &sbc_serial1;
22 };
23 soc {
24 sbc_serial1: serial@fe531000 {
25 status = "okay";
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 red {
31 #gpio-cells = <1>;
32 label = "Front Panel LED";
33 gpios = <&PIO4 1>;
34 linux,default-trigger = "heartbeat";
35 };
36 green {
37 gpios = <&PIO4 7>;
38 default-state = "off";
39 };
40 };
41 };
42};
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
new file mode 100644
index 000000000000..7321403cab8a
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x.dtsi
@@ -0,0 +1,38 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4
5 cpus {
6 #address-cells = <1>;
7 #size-cells = <0>;
8 cpu@0 {
9 compatible = "arm,cortex-a9";
10 reg = <0>;
11 };
12 cpu@1 {
13 compatible = "arm,cortex-a9";
14 reg = <1>;
15 };
16 };
17
18 intc: interrupt-controller@fffe1000 {
19 compatible = "arm,cortex-a9-gic";
20 #interrupt-cells = <3>;
21 interrupt-controller;
22 reg = <0xfffe1000 0x1000>,
23 <0xfffe0100 0x100>;
24 };
25
26 scu@fffe0000 {
27 compatible = "arm,cortex-a9-scu";
28 reg = <0xfffe0000 0x1000>;
29 };
30
31 timer@fffe0200 {
32 interrupt-parent = <&intc>;
33 compatible = "arm,cortex-a9-global-timer";
34 reg = <0xfffe0200 0x100>;
35 interrupts = <1 11 0x04>;
36 clocks = <&arm_periph_clk>;
37 };
38};
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
new file mode 100644
index 000000000000..886fd276fcbc
--- /dev/null
+++ b/arch/arm/include/debug/nspire.S
@@ -0,0 +1,28 @@
1/*
2 * linux/arch/arm/include/debug/nspire.S
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define NSPIRE_EARLY_UART_PHYS_BASE 0x90020000
13#define NSPIRE_EARLY_UART_VIRT_BASE 0xfee20000
14
15.macro addruart, rp, rv, tmp
16 ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE) @ physical base address
17 ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE) @ virtual base address
18.endm
19
20
21#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
22#include <asm/hardware/debug-pl01x.S>
23#endif
24
25#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
26#define UART_SHIFT 2
27#include <asm/hardware/debug-8250.S>
28#endif
diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S
new file mode 100644
index 000000000000..e3aa58ff1776
--- /dev/null
+++ b/arch/arm/include/debug/sti.S
@@ -0,0 +1,61 @@
1/*
2 * arch/arm/include/debug/sti.S
3 *
4 * Debugging macro include header
5 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define STIH41X_COMMS_BASE 0xfed00000
13#define STIH41X_ASC2_BASE (STIH41X_COMMS_BASE+0x32000)
14
15#define STIH41X_SBC_LPM_BASE 0xfe400000
16#define STIH41X_SBC_COMMS_BASE (STIH41X_SBC_LPM_BASE + 0x100000)
17#define STIH41X_SBC_ASC1_BASE (STIH41X_SBC_COMMS_BASE + 0x31000)
18
19
20#define VIRT_ADDRESS(x) (x - 0x1000000)
21
22#if IS_ENABLED(CONFIG_STIH41X_DEBUG_ASC2)
23#define DEBUG_LL_UART_BASE STIH41X_ASC2_BASE
24#endif
25
26#if IS_ENABLED(CONFIG_STIH41X_DEBUG_SBC_ASC1)
27#define DEBUG_LL_UART_BASE STIH41X_SBC_ASC1_BASE
28#endif
29
30#ifndef DEBUG_LL_UART_BASE
31#error "DEBUG UART is not Configured"
32#endif
33
34#define ASC_TX_BUF_OFF 0x04
35#define ASC_CTRL_OFF 0x0c
36#define ASC_STA_OFF 0x14
37
38#define ASC_STA_TX_FULL (1<<9)
39#define ASC_STA_TX_EMPTY (1<<1)
40
41
42 .macro addruart, rp, rv, tmp
43 ldr \rp, =DEBUG_LL_UART_BASE @ physical base
44 ldr \rv, =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base
45 .endm
46
47 .macro senduart,rd,rx
48 strb \rd, [\rx, #ASC_TX_BUF_OFF]
49 .endm
50
51 .macro waituart,rd,rx
521001: ldr \rd, [\rx, #ASC_STA_OFF]
53 tst \rd, #ASC_STA_TX_FULL
54 bne 1001b
55 .endm
56
57 .macro busyuart,rd,rx
581001: ldr \rd, [\rx, #ASC_STA_OFF]
59 tst \rd, #ASC_STA_TX_EMPTY
60 beq 1001b
61 .endm
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0ecd5af20545..2d503b3684c4 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -78,6 +78,16 @@ config SOC_EXYNOS5250
78 help 78 help
79 Enable EXYNOS5250 SoC support 79 Enable EXYNOS5250 SoC support
80 80
81config SOC_EXYNOS5420
82 bool "SAMSUNG EXYNOS5420"
83 default y
84 depends on ARCH_EXYNOS5
85 select PM_GENERIC_DOMAINS if PM
86 select S5P_PM if PM
87 select S5P_SLEEP if PM
88 help
89 Enable EXYNOS5420 SoC support
90
81config SOC_EXYNOS5440 91config SOC_EXYNOS5440
82 bool "SAMSUNG EXYNOS5440" 92 bool "SAMSUNG EXYNOS5440"
83 default y 93 default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 81e6320ca091..2c655db4b78e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
53static const char name_exynos4212[] = "EXYNOS4212"; 53static const char name_exynos4212[] = "EXYNOS4212";
54static const char name_exynos4412[] = "EXYNOS4412"; 54static const char name_exynos4412[] = "EXYNOS4412";
55static const char name_exynos5250[] = "EXYNOS5250"; 55static const char name_exynos5250[] = "EXYNOS5250";
56static const char name_exynos5420[] = "EXYNOS5420";
56static const char name_exynos5440[] = "EXYNOS5440"; 57static const char name_exynos5440[] = "EXYNOS5440";
57 58
58static void exynos4_map_io(void); 59static void exynos4_map_io(void);
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
86 .init = exynos_init, 87 .init = exynos_init,
87 .name = name_exynos5250, 88 .name = name_exynos5250,
88 }, { 89 }, {
90 .idcode = EXYNOS5420_SOC_ID,
91 .idmask = EXYNOS5_SOC_MASK,
92 .map_io = exynos5_map_io,
93 .init = exynos_init,
94 .name = name_exynos5420,
95 }, {
89 .idcode = EXYNOS5440_SOC_ID, 96 .idcode = EXYNOS5440_SOC_ID,
90 .idmask = EXYNOS5_SOC_MASK, 97 .idmask = EXYNOS5_SOC_MASK,
91 .map_io = exynos5440_map_io, 98 .map_io = exynos5440_map_io,
@@ -289,10 +296,10 @@ void exynos5_restart(char mode, const char *cmd)
289 u32 val; 296 u32 val;
290 void __iomem *addr; 297 void __iomem *addr;
291 298
292 if (of_machine_is_compatible("samsung,exynos5250")) { 299 val = 0x1;
293 val = 0x1; 300 addr = EXYNOS_SWRESET;
294 addr = EXYNOS_SWRESET; 301
295 } else if (of_machine_is_compatible("samsung,exynos5440")) { 302 if (of_machine_is_compatible("samsung,exynos5440")) {
296 u32 status; 303 u32 status;
297 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); 304 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
298 305
@@ -303,9 +310,6 @@ void exynos5_restart(char mode, const char *cmd)
303 val = __raw_readl(addr); 310 val = __raw_readl(addr);
304 311
305 val = (val & 0xffff0000) | (status & 0xffff); 312 val = (val & 0xffff0000) | (status & 0xffff);
306 } else {
307 pr_err("%s: cannot support non-DT\n", __func__);
308 return;
309 } 313 }
310 314
311 __raw_writel(val, addr); 315 __raw_writel(val, addr);
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index d405762be183..5d7ce36be46f 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -28,13 +28,12 @@ static void arch_detect_cpu(void)
28 28
29 /* 29 /*
30 * product_id is bits 31:12 30 * product_id is bits 31:12
31 * bits 23:20 describe the exynosX family 31 * bits 23:20 describe the exynosX family
32 * 32 * bits 27:24 describe the exynosX family in exynos5420
33 */ 33 */
34 chip_id >>= 20; 34 chip_id >>= 20;
35 chip_id &= 0xf;
36 35
37 if (chip_id == 0x5) 36 if ((chip_id & 0x0f) == 0x5 || (chip_id & 0xf0) == 0x50)
38 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); 37 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
39 else 38 else
40 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); 39 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index d5c8afdeaa39..f874b773ca13 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
52 52
53static char const *exynos5_dt_compat[] __initdata = { 53static char const *exynos5_dt_compat[] __initdata = {
54 "samsung,exynos5250", 54 "samsung,exynos5250",
55 "samsung,exynos5420",
55 "samsung,exynos5440", 56 "samsung,exynos5440",
56 NULL 57 NULL
57}; 58};
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d9c6d0ab6a0c..deba1308ff16 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -50,6 +50,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
50 boot_reg = cpu_boot_reg_base(); 50 boot_reg = cpu_boot_reg_base();
51 if (soc_is_exynos4412()) 51 if (soc_is_exynos4412())
52 boot_reg += 4*cpu; 52 boot_reg += 4*cpu;
53 else if (soc_is_exynos5420())
54 boot_reg += 4;
53 return boot_reg; 55 return boot_reg;
54} 56}
55 57
@@ -180,10 +182,14 @@ static void __init exynos_smp_init_cpus(void)
180 void __iomem *scu_base = scu_base_addr(); 182 void __iomem *scu_base = scu_base_addr();
181 unsigned int i, ncores; 183 unsigned int i, ncores;
182 184
183 if (soc_is_exynos5250()) 185 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
184 ncores = 2;
185 else
186 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 186 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
187 else
188 /*
189 * CPU Nodes are passed thru DT and set_cpu_possible
190 * is set by "arm_dt_init_cpu_maps".
191 */
192 return;
187 193
188 /* sanity check */ 194 /* sanity check */
189 if (ncores > nr_cpu_ids) { 195 if (ncores > nr_cpu_ids) {
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 1a26d04c9400..d257ff40e16b 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,16 +1,18 @@
1obj-y += io.o timer.o 1obj-y += io.o timer.o
2obj-y += clock.o 2obj-y += clock.o
3obj-$(CONFIG_DEBUG_FS) += clock-debug.o
4 3
5obj-$(CONFIG_MSM_VIC) += irq-vic.o 4obj-$(CONFIG_MSM_VIC) += irq-vic.o
6obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o 5obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
7 6
8obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o 7obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
9obj-$(CONFIG_ARCH_MSM7X30) += dma.o 8obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
10obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
11 9
12obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o 10obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
13 11
12obj-$(CONFIG_ARCH_MSM7X00A) += dma.o
13obj-$(CONFIG_ARCH_MSM7X30) += dma.o
14obj-$(CONFIG_ARCH_QSD8X50) += dma.o
15
14obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o 16obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
15obj-$(CONFIG_MSM_SMD) += last_radio_log.o 17obj-$(CONFIG_MSM_SMD) += last_radio_log.o
16obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o 18obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 82eaf88d2026..803651ad4f62 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -59,6 +59,7 @@ static struct platform_device smc91x_device = {
59}; 59};
60 60
61static struct platform_device *devices[] __initdata = { 61static struct platform_device *devices[] __initdata = {
62 &msm_clock_7x01a,
62 &msm_device_gpio_7201, 63 &msm_device_gpio_7201,
63 &msm_device_uart3, 64 &msm_device_uart3,
64 &msm_device_smd, 65 &msm_device_smd,
@@ -91,7 +92,6 @@ static void __init halibut_fixup(struct tag *tags, char **cmdline,
91static void __init halibut_map_io(void) 92static void __init halibut_map_io(void)
92{ 93{
93 msm_map_common_io(); 94 msm_map_common_io();
94 msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a);
95} 95}
96 96
97static void __init halibut_init_late(void) 97static void __init halibut_init_late(void)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 520c141acd03..db3d8c0bc8a4 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -89,6 +89,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
89}; 89};
90 90
91static struct platform_device *devices[] __initdata = { 91static struct platform_device *devices[] __initdata = {
92 &msm_clock_7x30,
92 &msm_device_gpio_7x30, 93 &msm_device_gpio_7x30,
93#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) 94#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
94 &msm_device_uart2, 95 &msm_device_uart2,
@@ -116,7 +117,6 @@ static void __init msm7x30_init(void)
116static void __init msm7x30_map_io(void) 117static void __init msm7x30_map_io(void)
117{ 118{
118 msm_map_msm7x30_io(); 119 msm_map_msm7x30_io();
119 msm_clock_init(msm_clocks_7x30, msm_num_clocks_7x30);
120} 120}
121 121
122static void __init msm7x30_init_late(void) 122static void __init msm7x30_init_late(void)
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 38a532d6937c..f14a73d86bc0 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -89,6 +89,7 @@ static struct msm_otg_platform_data msm_otg_pdata = {
89}; 89};
90 90
91static struct platform_device *devices[] __initdata = { 91static struct platform_device *devices[] __initdata = {
92 &msm_clock_8x50,
92 &msm_device_gpio_8x50, 93 &msm_device_gpio_8x50,
93 &msm_device_uart3, 94 &msm_device_uart3,
94 &msm_device_smd, 95 &msm_device_smd,
@@ -172,7 +173,6 @@ static void __init qsd8x50_init_mmc(void)
172static void __init qsd8x50_map_io(void) 173static void __init qsd8x50_map_io(void)
173{ 174{
174 msm_map_qsd8x50_io(); 175 msm_map_qsd8x50_io();
175 msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50);
176} 176}
177 177
178static void __init qsd8x50_init_irq(void) 178static void __init qsd8x50_init_irq(void)
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
index f9a5db6d2ced..77b0a26f897f 100644
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -7,7 +7,6 @@
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/delay.h> 8#include <linux/delay.h>
9#include <linux/leds.h> 9#include <linux/leds.h>
10#include <linux/clk.h>
11#include <linux/err.h> 10#include <linux/err.h>
12 11
13#include <asm/io.h> 12#include <asm/io.h>
@@ -19,6 +18,7 @@
19 18
20#include "board-trout.h" 19#include "board-trout.h"
21#include "proc_comm.h" 20#include "proc_comm.h"
21#include "clock-pcom.h"
22#include "devices.h" 22#include "devices.h"
23 23
24#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255 24#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
@@ -170,7 +170,6 @@ static struct mddi_table mddi_toshiba_init_table[] = {
170#define INTMASK_VWAKEOUT (1U << 0) 170#define INTMASK_VWAKEOUT (1U << 0)
171 171
172 172
173static struct clk *gp_clk;
174static int trout_new_backlight = 1; 173static int trout_new_backlight = 1;
175static struct vreg *vreg_mddi_1v5; 174static struct vreg *vreg_mddi_1v5;
176static struct vreg *vreg_lcm_2v85; 175static struct vreg *vreg_lcm_2v85;
@@ -273,18 +272,14 @@ int __init trout_init_panel(void)
273 } else { 272 } else {
274 uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT, 273 uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
275 GPIO_NO_PULL, GPIO_8MA); 274 GPIO_NO_PULL, GPIO_8MA);
275 uint32_t id = P_GP_CLK;
276 uint32_t rate = 19200000;
277
276 msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); 278 msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
277 279
278 gp_clk = clk_get(NULL, "gp_clk"); 280 msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
279 if (IS_ERR(gp_clk)) { 281 if (id < 0)
280 printk(KERN_ERR "trout_init_panel: could not get gp" 282 pr_err("trout_init_panel: set clock rate failed\n");
281 "clock\n");
282 gp_clk = NULL;
283 }
284 rc = clk_set_rate(gp_clk, 19200000);
285 if (rc)
286 printk(KERN_ERR "trout_init_panel: set clock rate "
287 "failed\n");
288 } 283 }
289 284
290 rc = platform_device_register(&msm_device_mdp); 285 rc = platform_device_register(&msm_device_mdp);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 80fe1c5ff5c1..64a46eb4fc49 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -36,6 +36,7 @@
36extern int trout_init_mmc(unsigned int); 36extern int trout_init_mmc(unsigned int);
37 37
38static struct platform_device *devices[] __initdata = { 38static struct platform_device *devices[] __initdata = {
39 &msm_clock_7x01a,
39 &msm_device_gpio_7201, 40 &msm_device_gpio_7201,
40 &msm_device_uart3, 41 &msm_device_uart3,
41 &msm_device_smd, 42 &msm_device_smd,
@@ -94,8 +95,6 @@ static void __init trout_map_io(void)
94 /* route UART3 to the "H2W" extended usb connector */ 95 /* route UART3 to the "H2W" extended usb connector */
95 writeb(0x80, TROUT_CPLD_BASE + 0x00); 96 writeb(0x80, TROUT_CPLD_BASE + 0x00);
96#endif 97#endif
97
98 msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a);
99} 98}
100 99
101static void __init trout_init_late(void) 100static void __init trout_init_late(void)
diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h
deleted file mode 100644
index 14104453688b..000000000000
--- a/arch/arm/mach-msm/clock-7x30.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
14#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
15
16enum {
17 L_7X30_NONE_CLK = -1,
18 L_7X30_ADM_CLK,
19 L_7X30_I2C_CLK,
20 L_7X30_I2C_2_CLK,
21 L_7X30_QUP_I2C_CLK,
22 L_7X30_UART1DM_CLK,
23 L_7X30_UART1DM_P_CLK,
24 L_7X30_UART2DM_CLK,
25 L_7X30_UART2DM_P_CLK,
26 L_7X30_EMDH_CLK,
27 L_7X30_EMDH_P_CLK,
28 L_7X30_PMDH_CLK,
29 L_7X30_PMDH_P_CLK,
30 L_7X30_GRP_2D_CLK,
31 L_7X30_GRP_2D_P_CLK,
32 L_7X30_GRP_3D_SRC_CLK,
33 L_7X30_GRP_3D_CLK,
34 L_7X30_GRP_3D_P_CLK,
35 L_7X30_IMEM_CLK,
36 L_7X30_SDC1_CLK,
37 L_7X30_SDC1_P_CLK,
38 L_7X30_SDC2_CLK,
39 L_7X30_SDC2_P_CLK,
40 L_7X30_SDC3_CLK,
41 L_7X30_SDC3_P_CLK,
42 L_7X30_SDC4_CLK,
43 L_7X30_SDC4_P_CLK,
44 L_7X30_MDP_CLK,
45 L_7X30_MDP_P_CLK,
46 L_7X30_MDP_LCDC_PCLK_CLK,
47 L_7X30_MDP_LCDC_PAD_PCLK_CLK,
48 L_7X30_MDP_VSYNC_CLK,
49 L_7X30_MI2S_CODEC_RX_M_CLK,
50 L_7X30_MI2S_CODEC_RX_S_CLK,
51 L_7X30_MI2S_CODEC_TX_M_CLK,
52 L_7X30_MI2S_CODEC_TX_S_CLK,
53 L_7X30_MI2S_M_CLK,
54 L_7X30_MI2S_S_CLK,
55 L_7X30_LPA_CODEC_CLK,
56 L_7X30_LPA_CORE_CLK,
57 L_7X30_LPA_P_CLK,
58 L_7X30_MIDI_CLK,
59 L_7X30_MDC_CLK,
60 L_7X30_ROTATOR_IMEM_CLK,
61 L_7X30_ROTATOR_P_CLK,
62 L_7X30_SDAC_M_CLK,
63 L_7X30_SDAC_CLK,
64 L_7X30_UART1_CLK,
65 L_7X30_UART2_CLK,
66 L_7X30_UART3_CLK,
67 L_7X30_TV_CLK,
68 L_7X30_TV_DAC_CLK,
69 L_7X30_TV_ENC_CLK,
70 L_7X30_HDMI_CLK,
71 L_7X30_TSIF_REF_CLK,
72 L_7X30_TSIF_P_CLK,
73 L_7X30_USB_HS_SRC_CLK,
74 L_7X30_USB_HS_CLK,
75 L_7X30_USB_HS_CORE_CLK,
76 L_7X30_USB_HS_P_CLK,
77 L_7X30_USB_HS2_CLK,
78 L_7X30_USB_HS2_CORE_CLK,
79 L_7X30_USB_HS2_P_CLK,
80 L_7X30_USB_HS3_CLK,
81 L_7X30_USB_HS3_CORE_CLK,
82 L_7X30_USB_HS3_P_CLK,
83 L_7X30_VFE_CLK,
84 L_7X30_VFE_P_CLK,
85 L_7X30_VFE_MDC_CLK,
86 L_7X30_VFE_CAMIF_CLK,
87 L_7X30_CAMIF_PAD_P_CLK,
88 L_7X30_CAM_M_CLK,
89 L_7X30_JPEG_CLK,
90 L_7X30_JPEG_P_CLK,
91 L_7X30_VPE_CLK,
92 L_7X30_MFC_CLK,
93 L_7X30_MFC_DIV2_CLK,
94 L_7X30_MFC_P_CLK,
95 L_7X30_SPI_CLK,
96 L_7X30_SPI_P_CLK,
97 L_7X30_CSI0_CLK,
98 L_7X30_CSI0_VFE_CLK,
99 L_7X30_CSI0_P_CLK,
100 L_7X30_CSI1_CLK,
101 L_7X30_CSI1_VFE_CLK,
102 L_7X30_CSI1_P_CLK,
103 L_7X30_GLBL_ROOT_CLK,
104
105 L_7X30_AXI_LI_VG_CLK,
106 L_7X30_AXI_LI_GRP_CLK,
107 L_7X30_AXI_LI_JPEG_CLK,
108 L_7X30_AXI_GRP_2D_CLK,
109 L_7X30_AXI_MFC_CLK,
110 L_7X30_AXI_VPE_CLK,
111 L_7X30_AXI_LI_VFE_CLK,
112 L_7X30_AXI_LI_APPS_CLK,
113 L_7X30_AXI_MDP_CLK,
114 L_7X30_AXI_IMEM_CLK,
115 L_7X30_AXI_LI_ADSP_A_CLK,
116 L_7X30_AXI_ROTATOR_CLK,
117
118 L_7X30_NR_CLKS
119};
120
121struct clk_ops;
122extern struct clk_ops clk_ops_7x30;
123
124struct clk_ops *clk_7x30_is_local(uint32_t id);
125int clk_7x30_init(void);
126
127void pll_enable(uint32_t pll);
128void pll_disable(uint32_t pll);
129
130extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
131
132#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \
133 .con_id = clk_name, \
134 .dev_id = clk_dev, \
135 .clk = &(struct clk){ \
136 .id = L_7X30_##clk_id, \
137 .remote_id = P_##clk_id, \
138 .flags = clk_flags, \
139 .dbg_name = #clk_id, \
140 }, \
141 }
142
143#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \
144 .con_id = clk_name, \
145 .dev_id = clk_dev, \
146 .clk = &(struct clk){ \
147 .id = L_7X30_##l_id, \
148 .remote_id = P_##r_id, \
149 .flags = clk_flags, \
150 .dbg_name = #l_id, \
151 .ops = &clk_ops_pcom, \
152 }, \
153 }
154
155#endif
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
deleted file mode 100644
index b0fbdf1cbdd1..000000000000
--- a/arch/arm/mach-msm/clock-debug.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/ctype.h>
19#include <linux/debugfs.h>
20#include <linux/clk.h>
21#include "clock.h"
22
23static int clock_debug_rate_set(void *data, u64 val)
24{
25 struct clk *clock = data;
26 int ret;
27
28 /* Only increases to max rate will succeed, but that's actually good
29 * for debugging purposes so we don't check for error. */
30 if (clock->flags & CLK_MAX)
31 clk_set_max_rate(clock, val);
32 if (clock->flags & CLK_MIN)
33 ret = clk_set_min_rate(clock, val);
34 else
35 ret = clk_set_rate(clock, val);
36 if (ret != 0)
37 printk(KERN_ERR "clk_set%s_rate failed (%d)\n",
38 (clock->flags & CLK_MIN) ? "_min" : "", ret);
39 return ret;
40}
41
42static int clock_debug_rate_get(void *data, u64 *val)
43{
44 struct clk *clock = data;
45 *val = clk_get_rate(clock);
46 return 0;
47}
48
49DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get,
50 clock_debug_rate_set, "%llu\n");
51
52static int clock_debug_enable_set(void *data, u64 val)
53{
54 struct clk *clock = data;
55 int rc = 0;
56
57 if (val)
58 rc = clock->ops->enable(clock->id);
59 else
60 clock->ops->disable(clock->id);
61
62 return rc;
63}
64
65static int clock_debug_enable_get(void *data, u64 *val)
66{
67 struct clk *clock = data;
68
69 *val = clock->ops->is_enabled(clock->id);
70
71 return 0;
72}
73
74DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get,
75 clock_debug_enable_set, "%llu\n");
76
77static int clock_debug_local_get(void *data, u64 *val)
78{
79 struct clk *clock = data;
80
81 *val = clock->ops->is_local(clock->id);
82
83 return 0;
84}
85
86DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get,
87 NULL, "%llu\n");
88
89static struct dentry *debugfs_base;
90
91int __init clock_debug_init(void)
92{
93 debugfs_base = debugfs_create_dir("clk", NULL);
94 if (!debugfs_base)
95 return -ENOMEM;
96 return 0;
97}
98
99int __init clock_debug_add(struct clk *clock)
100{
101 char temp[50], *ptr;
102 struct dentry *clk_dir;
103
104 if (!debugfs_base)
105 return -ENOMEM;
106
107 strlcpy(temp, clock->dbg_name, ARRAY_SIZE(temp));
108 for (ptr = temp; *ptr; ptr++)
109 *ptr = tolower(*ptr);
110
111 clk_dir = debugfs_create_dir(temp, debugfs_base);
112 if (!clk_dir)
113 return -ENOMEM;
114
115 if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir,
116 clock, &clock_rate_fops))
117 goto error;
118
119 if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir,
120 clock, &clock_enable_fops))
121 goto error;
122
123 if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock,
124 &clock_local_fops))
125 goto error;
126 return 0;
127error:
128 debugfs_remove_recursive(clk_dir);
129 return -ENOMEM;
130}
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index a52c970df157..9a80449518e6 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -13,20 +13,33 @@
13 * 13 *
14 */ 14 */
15 15
16#include <linux/kernel.h>
16#include <linux/err.h> 17#include <linux/err.h>
17#include <linux/ctype.h> 18#include <linux/platform_device.h>
18#include <linux/stddef.h> 19#include <linux/module.h>
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22
19#include <mach/clk.h> 23#include <mach/clk.h>
20 24
21#include "proc_comm.h" 25#include "proc_comm.h"
22#include "clock.h" 26#include "clock.h"
23#include "clock-pcom.h" 27#include "clock-pcom.h"
24 28
25/* 29struct clk_pcom {
26 * glue for the proc_comm interface 30 unsigned id;
27 */ 31 unsigned long flags;
28static int pc_clk_enable(unsigned id) 32 struct msm_clk msm_clk;
33};
34
35static inline struct clk_pcom *to_clk_pcom(struct clk_hw *hw)
29{ 36{
37 return container_of(to_msm_clk(hw), struct clk_pcom, msm_clk);
38}
39
40static int pc_clk_enable(struct clk_hw *hw)
41{
42 unsigned id = to_clk_pcom(hw)->id;
30 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); 43 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
31 if (rc < 0) 44 if (rc < 0)
32 return rc; 45 return rc;
@@ -34,14 +47,16 @@ static int pc_clk_enable(unsigned id)
34 return (int)id < 0 ? -EINVAL : 0; 47 return (int)id < 0 ? -EINVAL : 0;
35} 48}
36 49
37static void pc_clk_disable(unsigned id) 50static void pc_clk_disable(struct clk_hw *hw)
38{ 51{
52 unsigned id = to_clk_pcom(hw)->id;
39 msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); 53 msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
40} 54}
41 55
42int pc_clk_reset(unsigned id, enum clk_reset_action action) 56static int pc_clk_reset(struct clk_hw *hw, enum clk_reset_action action)
43{ 57{
44 int rc; 58 int rc;
59 unsigned id = to_clk_pcom(hw)->id;
45 60
46 if (action == CLK_RESET_ASSERT) 61 if (action == CLK_RESET_ASSERT)
47 rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL); 62 rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
@@ -54,85 +69,109 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
54 return (int)id < 0 ? -EINVAL : 0; 69 return (int)id < 0 ? -EINVAL : 0;
55} 70}
56 71
57static int pc_clk_set_rate(unsigned id, unsigned rate) 72static int pc_clk_set_rate(struct clk_hw *hw, unsigned long new_rate,
73 unsigned long p_rate)
58{ 74{
59 /* The rate _might_ be rounded off to the nearest KHz value by the 75 struct clk_pcom *p = to_clk_pcom(hw);
76 unsigned id = p->id, rate = new_rate;
77 int rc;
78
79 /*
80 * The rate _might_ be rounded off to the nearest KHz value by the
60 * remote function. So a return value of 0 doesn't necessarily mean 81 * remote function. So a return value of 0 doesn't necessarily mean
61 * that the exact rate was set successfully. 82 * that the exact rate was set successfully.
62 */ 83 */
63 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate); 84 if (p->flags & CLKFLAG_MIN)
64 if (rc < 0) 85 rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
65 return rc;
66 else
67 return (int)id < 0 ? -EINVAL : 0;
68}
69
70static int pc_clk_set_min_rate(unsigned id, unsigned rate)
71{
72 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
73 if (rc < 0)
74 return rc;
75 else
76 return (int)id < 0 ? -EINVAL : 0;
77}
78
79static int pc_clk_set_max_rate(unsigned id, unsigned rate)
80{
81 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
82 if (rc < 0)
83 return rc;
84 else 86 else
85 return (int)id < 0 ? -EINVAL : 0; 87 rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
86}
87
88static int pc_clk_set_flags(unsigned id, unsigned flags)
89{
90 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
91 if (rc < 0) 88 if (rc < 0)
92 return rc; 89 return rc;
93 else 90 else
94 return (int)id < 0 ? -EINVAL : 0; 91 return (int)id < 0 ? -EINVAL : 0;
95} 92}
96 93
97static unsigned pc_clk_get_rate(unsigned id) 94static unsigned long pc_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
98{ 95{
96 unsigned id = to_clk_pcom(hw)->id;
99 if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) 97 if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
100 return 0; 98 return 0;
101 else 99 else
102 return id; 100 return id;
103} 101}
104 102
105static unsigned pc_clk_is_enabled(unsigned id) 103static int pc_clk_is_enabled(struct clk_hw *hw)
106{ 104{
105 unsigned id = to_clk_pcom(hw)->id;
107 if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) 106 if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
108 return 0; 107 return 0;
109 else 108 else
110 return id; 109 return id;
111} 110}
112 111
113static long pc_clk_round_rate(unsigned id, unsigned rate) 112static long pc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
113 unsigned long *p_rate)
114{ 114{
115
116 /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ 115 /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
117 return rate; 116 return rate;
118} 117}
119 118
120static bool pc_clk_is_local(unsigned id) 119static struct clk_ops clk_ops_pcom = {
121{
122 return false;
123}
124
125struct clk_ops clk_ops_pcom = {
126 .enable = pc_clk_enable, 120 .enable = pc_clk_enable,
127 .disable = pc_clk_disable, 121 .disable = pc_clk_disable,
128 .auto_off = pc_clk_disable,
129 .reset = pc_clk_reset,
130 .set_rate = pc_clk_set_rate, 122 .set_rate = pc_clk_set_rate,
131 .set_min_rate = pc_clk_set_min_rate, 123 .recalc_rate = pc_clk_recalc_rate,
132 .set_max_rate = pc_clk_set_max_rate,
133 .set_flags = pc_clk_set_flags,
134 .get_rate = pc_clk_get_rate,
135 .is_enabled = pc_clk_is_enabled, 124 .is_enabled = pc_clk_is_enabled,
136 .round_rate = pc_clk_round_rate, 125 .round_rate = pc_clk_round_rate,
137 .is_local = pc_clk_is_local,
138}; 126};
127
128static int msm_clock_pcom_probe(struct platform_device *pdev)
129{
130 const struct pcom_clk_pdata *pdata = pdev->dev.platform_data;
131 int i, ret;
132
133 for (i = 0; i < pdata->num_lookups; i++) {
134 const struct clk_pcom_desc *desc = &pdata->lookup[i];
135 struct clk *c;
136 struct clk_pcom *p;
137 struct clk_hw *hw;
138 struct clk_init_data init;
139
140 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
141 if (!p)
142 return -ENOMEM;
143
144 p->id = desc->id;
145 p->flags = desc->flags;
146 p->msm_clk.reset = pc_clk_reset;
147
148 hw = &p->msm_clk.hw;
149 hw->init = &init;
150
151 init.name = desc->name;
152 init.ops = &clk_ops_pcom;
153 init.num_parents = 0;
154 init.flags = CLK_IS_ROOT;
155
156 if (!(p->flags & CLKFLAG_AUTO_OFF))
157 init.flags |= CLK_IGNORE_UNUSED;
158
159 c = devm_clk_register(&pdev->dev, hw);
160 ret = clk_register_clkdev(c, desc->con, desc->dev);
161 if (ret)
162 return ret;
163 }
164
165 return 0;
166}
167
168static struct platform_driver msm_clock_pcom_driver = {
169 .probe = msm_clock_pcom_probe,
170 .driver = {
171 .name = "msm-clock-pcom",
172 .owner = THIS_MODULE,
173 },
174};
175module_platform_driver(msm_clock_pcom_driver);
176
177MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 974d0032f3a3..5bb164fd46a8 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -1,4 +1,5 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. 1/*
2 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
2 * 3 *
3 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 5 * it under the terms of the GNU General Public License version 2 and
@@ -120,21 +121,25 @@
120 121
121#define P_NR_CLKS 102 122#define P_NR_CLKS 102
122 123
123struct clk_ops; 124struct clk_pcom_desc {
124extern struct clk_ops clk_ops_pcom; 125 unsigned id;
126 const char *name;
127 const char *con;
128 const char *dev;
129 unsigned long flags;
130};
125 131
126int pc_clk_reset(unsigned id, enum clk_reset_action action); 132struct pcom_clk_pdata {
133 struct clk_pcom_desc *lookup;
134 u32 num_lookups;
135};
127 136
128#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \ 137#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \
129 .con_id = clk_name, \ 138 .id = P_##clk_id, \
130 .dev_id = clk_dev, \ 139 .name = #clk_id, \
131 .clk = &(struct clk){ \ 140 .con = clk_name, \
132 .id = P_##clk_id, \ 141 .dev = clk_dev, \
133 .remote_id = P_##clk_id, \ 142 .flags = clk_flags, \
134 .ops = &clk_ops_pcom, \
135 .flags = clk_flags, \
136 .dbg_name = #clk_id, \
137 }, \
138 } 143 }
139 144
140#endif 145#endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index d9145dfc2a3b..35ea02b52483 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -1,7 +1,7 @@
1/* arch/arm/mach-msm/clock.c 1/* arch/arm/mach-msm/clock.c
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. 4 * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
@@ -14,171 +14,15 @@
14 * 14 *
15 */ 15 */
16 16
17#include <linux/kernel.h> 17#include <linux/clk-provider.h>
18#include <linux/list.h>
19#include <linux/err.h>
20#include <linux/spinlock.h>
21#include <linux/pm_qos.h>
22#include <linux/mutex.h>
23#include <linux/clk.h>
24#include <linux/string.h>
25#include <linux/module.h> 18#include <linux/module.h>
26#include <linux/clkdev.h>
27 19
28#include "clock.h" 20#include "clock.h"
29 21
30static DEFINE_MUTEX(clocks_mutex);
31static DEFINE_SPINLOCK(clocks_lock);
32static LIST_HEAD(clocks);
33
34/*
35 * Standard clock functions defined in include/linux/clk.h
36 */
37int clk_enable(struct clk *clk)
38{
39 unsigned long flags;
40 spin_lock_irqsave(&clocks_lock, flags);
41 clk->count++;
42 if (clk->count == 1)
43 clk->ops->enable(clk->id);
44 spin_unlock_irqrestore(&clocks_lock, flags);
45 return 0;
46}
47EXPORT_SYMBOL(clk_enable);
48
49void clk_disable(struct clk *clk)
50{
51 unsigned long flags;
52 spin_lock_irqsave(&clocks_lock, flags);
53 BUG_ON(clk->count == 0);
54 clk->count--;
55 if (clk->count == 0)
56 clk->ops->disable(clk->id);
57 spin_unlock_irqrestore(&clocks_lock, flags);
58}
59EXPORT_SYMBOL(clk_disable);
60
61int clk_reset(struct clk *clk, enum clk_reset_action action) 22int clk_reset(struct clk *clk, enum clk_reset_action action)
62{ 23{
63 return clk->ops->reset(clk->remote_id, action); 24 struct clk_hw *hw = __clk_get_hw(clk);
25 struct msm_clk *m = to_msm_clk(hw);
26 return m->reset(hw, action);
64} 27}
65EXPORT_SYMBOL(clk_reset); 28EXPORT_SYMBOL(clk_reset);
66
67unsigned long clk_get_rate(struct clk *clk)
68{
69 return clk->ops->get_rate(clk->id);
70}
71EXPORT_SYMBOL(clk_get_rate);
72
73int clk_set_rate(struct clk *clk, unsigned long rate)
74{
75 int ret;
76 if (clk->flags & CLKFLAG_MAX) {
77 ret = clk->ops->set_max_rate(clk->id, rate);
78 if (ret)
79 return ret;
80 }
81 if (clk->flags & CLKFLAG_MIN) {
82 ret = clk->ops->set_min_rate(clk->id, rate);
83 if (ret)
84 return ret;
85 }
86
87 if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN)
88 return ret;
89
90 return clk->ops->set_rate(clk->id, rate);
91}
92EXPORT_SYMBOL(clk_set_rate);
93
94long clk_round_rate(struct clk *clk, unsigned long rate)
95{
96 return clk->ops->round_rate(clk->id, rate);
97}
98EXPORT_SYMBOL(clk_round_rate);
99
100int clk_set_min_rate(struct clk *clk, unsigned long rate)
101{
102 return clk->ops->set_min_rate(clk->id, rate);
103}
104EXPORT_SYMBOL(clk_set_min_rate);
105
106int clk_set_max_rate(struct clk *clk, unsigned long rate)
107{
108 return clk->ops->set_max_rate(clk->id, rate);
109}
110EXPORT_SYMBOL(clk_set_max_rate);
111
112int clk_set_parent(struct clk *clk, struct clk *parent)
113{
114 return -ENOSYS;
115}
116EXPORT_SYMBOL(clk_set_parent);
117
118struct clk *clk_get_parent(struct clk *clk)
119{
120 return ERR_PTR(-ENOSYS);
121}
122EXPORT_SYMBOL(clk_get_parent);
123
124int clk_set_flags(struct clk *clk, unsigned long flags)
125{
126 if (clk == NULL || IS_ERR(clk))
127 return -EINVAL;
128 return clk->ops->set_flags(clk->id, flags);
129}
130EXPORT_SYMBOL(clk_set_flags);
131
132/* EBI1 is the only shared clock that several clients want to vote on as of
133 * this commit. If this changes in the future, then it might be better to
134 * make clk_min_rate handle the voting or make ebi1_clk_set_min_rate more
135 * generic to support different clocks.
136 */
137static struct clk *ebi1_clk;
138
139void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
140{
141 unsigned n;
142
143 mutex_lock(&clocks_mutex);
144 for (n = 0; n < num_clocks; n++) {
145 clkdev_add(&clock_tbl[n]);
146 list_add_tail(&clock_tbl[n].clk->list, &clocks);
147 }
148 mutex_unlock(&clocks_mutex);
149
150 ebi1_clk = clk_get(NULL, "ebi1_clk");
151 BUG_ON(ebi1_clk == NULL);
152
153}
154
155/* The bootloader and/or AMSS may have left various clocks enabled.
156 * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have
157 * not been explicitly enabled by a clk_enable() call.
158 */
159static int __init clock_late_init(void)
160{
161 unsigned long flags;
162 struct clk *clk;
163 unsigned count = 0;
164
165 clock_debug_init();
166 mutex_lock(&clocks_mutex);
167 list_for_each_entry(clk, &clocks, list) {
168 clock_debug_add(clk);
169 if (clk->flags & CLKFLAG_AUTO_OFF) {
170 spin_lock_irqsave(&clocks_lock, flags);
171 if (!clk->count) {
172 count++;
173 clk->ops->auto_off(clk->id);
174 }
175 spin_unlock_irqrestore(&clocks_lock, flags);
176 }
177 }
178 mutex_unlock(&clocks_mutex);
179 pr_info("clock_late_init() disabled %d unused clocks\n", count);
180 return 0;
181}
182
183late_initcall(clock_late_init);
184
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 2c007f606d29..42d29dd7aafc 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -1,7 +1,7 @@
1/* arch/arm/mach-msm/clock.h 1/* arch/arm/mach-msm/clock.h
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. 4 * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
@@ -17,56 +17,27 @@
17#ifndef __ARCH_ARM_MACH_MSM_CLOCK_H 17#ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
18#define __ARCH_ARM_MACH_MSM_CLOCK_H 18#define __ARCH_ARM_MACH_MSM_CLOCK_H
19 19
20#include <linux/init.h> 20#include <linux/clk-provider.h>
21#include <linux/list.h>
22#include <mach/clk.h> 21#include <mach/clk.h>
23 22
24#define CLKFLAG_INVERT 0x00000001
25#define CLKFLAG_NOINVERT 0x00000002
26#define CLKFLAG_NONEST 0x00000004
27#define CLKFLAG_NORESET 0x00000008
28
29#define CLK_FIRST_AVAILABLE_FLAG 0x00000100 23#define CLK_FIRST_AVAILABLE_FLAG 0x00000100
30#define CLKFLAG_AUTO_OFF 0x00000200 24#define CLKFLAG_AUTO_OFF 0x00000200
31#define CLKFLAG_MIN 0x00000400 25#define CLKFLAG_MIN 0x00000400
32#define CLKFLAG_MAX 0x00000800 26#define CLKFLAG_MAX 0x00000800
33 27
34struct clk_ops {
35 int (*enable)(unsigned id);
36 void (*disable)(unsigned id);
37 void (*auto_off)(unsigned id);
38 int (*reset)(unsigned id, enum clk_reset_action action);
39 int (*set_rate)(unsigned id, unsigned rate);
40 int (*set_min_rate)(unsigned id, unsigned rate);
41 int (*set_max_rate)(unsigned id, unsigned rate);
42 int (*set_flags)(unsigned id, unsigned flags);
43 unsigned (*get_rate)(unsigned id);
44 unsigned (*is_enabled)(unsigned id);
45 long (*round_rate)(unsigned id, unsigned rate);
46 bool (*is_local)(unsigned id);
47};
48
49struct clk {
50 uint32_t id;
51 uint32_t remote_id;
52 uint32_t count;
53 uint32_t flags;
54 struct clk_ops *ops;
55 const char *dbg_name;
56 struct list_head list;
57};
58
59#define OFF CLKFLAG_AUTO_OFF 28#define OFF CLKFLAG_AUTO_OFF
60#define CLK_MIN CLKFLAG_MIN 29#define CLK_MIN CLKFLAG_MIN
61#define CLK_MAX CLKFLAG_MAX 30#define CLK_MAX CLKFLAG_MAX
62#define CLK_MINMAX (CLK_MIN | CLK_MAX) 31#define CLK_MINMAX (CLK_MIN | CLK_MAX)
63 32
64#ifdef CONFIG_DEBUG_FS 33struct msm_clk {
65int __init clock_debug_init(void); 34 int (*reset)(struct clk_hw *hw, enum clk_reset_action action);
66int __init clock_debug_add(struct clk *clock); 35 struct clk_hw hw;
67#else 36};
68static inline int __init clock_debug_init(void) { return 0; } 37
69static inline int __init clock_debug_add(struct clk *clock) { return 0; } 38static inline struct msm_clk *to_msm_clk(struct clk_hw *hw)
70#endif 39{
40 return container_of(hw, struct msm_clk, hw);
41}
71 42
72#endif 43#endif
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 1a0a2306b115..6d50fb964863 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -425,7 +425,7 @@ struct platform_device msm_device_mdp = {
425 .resource = resources_mdp, 425 .resource = resources_mdp,
426}; 426};
427 427
428struct clk_lookup msm_clocks_7x01a[] = { 428static struct clk_pcom_desc msm_clocks_7x01a[] = {
429 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), 429 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
430 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), 430 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
431 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0), 431 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0),
@@ -469,4 +469,12 @@ struct clk_lookup msm_clocks_7x01a[] = {
469 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF), 469 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
470}; 470};
471 471
472unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a); 472static struct pcom_clk_pdata msm_clock_7x01a_pdata = {
473 .lookup = msm_clocks_7x01a,
474 .num_lookups = ARRAY_SIZE(msm_clocks_7x01a),
475};
476
477struct platform_device msm_clock_7x01a = {
478 .name = "msm-clock-pcom",
479 .dev.platform_data = &msm_clock_7x01a_pdata,
480};
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 12f482c07740..d4db75acff56 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -28,8 +28,8 @@
28 28
29#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
30 30
31#include "clock.h"
31#include "clock-pcom.h" 32#include "clock-pcom.h"
32#include "clock-7x30.h"
33 33
34#include <linux/platform_data/mmc-msm_sdcc.h> 34#include <linux/platform_data/mmc-msm_sdcc.h>
35 35
@@ -161,7 +161,7 @@ struct platform_device msm_device_hsusb_host = {
161 }, 161 },
162}; 162};
163 163
164struct clk_lookup msm_clocks_7x30[] = { 164static struct clk_pcom_desc msm_clocks_7x30[] = {
165 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), 165 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
166 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), 166 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
167 CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), 167 CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0),
@@ -177,7 +177,6 @@ struct clk_lookup msm_clocks_7x30[] = {
177 CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK, NULL, 0), 177 CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK, NULL, 0),
178 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), 178 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
179 CLK_PCOM("grp_pclk", GRP_3D_P_CLK, NULL, 0), 179 CLK_PCOM("grp_pclk", GRP_3D_P_CLK, NULL, 0),
180 CLK_7X30S("grp_src_clk", GRP_3D_SRC_CLK, GRP_3D_CLK, NULL, 0),
181 CLK_PCOM("hdmi_clk", HDMI_CLK, NULL, 0), 180 CLK_PCOM("hdmi_clk", HDMI_CLK, NULL, 0),
182 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), 181 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
183 CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF), 182 CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF),
@@ -210,7 +209,6 @@ struct clk_lookup msm_clocks_7x30[] = {
210 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), 209 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
211 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), 210 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
212 CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0), 211 CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0),
213 CLK_7X30S("tv_src_clk", TV_CLK, TV_ENC_CLK, NULL, 0),
214 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), 212 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
215 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), 213 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
216 CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), 214 CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0),
@@ -237,5 +235,12 @@ struct clk_lookup msm_clocks_7x30[] = {
237 CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK, NULL, 0), 235 CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK, NULL, 0),
238}; 236};
239 237
240unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30); 238static struct pcom_clk_pdata msm_clock_7x30_pdata = {
239 .lookup = msm_clocks_7x30,
240 .num_lookups = ARRAY_SIZE(msm_clocks_7x30),
241};
241 242
243struct platform_device msm_clock_7x30 = {
244 .name = "msm-clock-pcom",
245 .dev.platform_data = &msm_clock_7x30_pdata,
246};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2e1b3ec9dfc7..f5518112284b 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -28,6 +28,7 @@
28#include <asm/mach/flash.h> 28#include <asm/mach/flash.h>
29 29
30#include <linux/platform_data/mmc-msm_sdcc.h> 30#include <linux/platform_data/mmc-msm_sdcc.h>
31#include "clock.h"
31#include "clock-pcom.h" 32#include "clock-pcom.h"
32 33
33static struct resource msm_gpio_resources[] = { 34static struct resource msm_gpio_resources[] = {
@@ -322,7 +323,7 @@ int __init msm_add_sdcc(unsigned int controller,
322 return platform_device_register(pdev); 323 return platform_device_register(pdev);
323} 324}
324 325
325struct clk_lookup msm_clocks_8x50[] = { 326static struct clk_pcom_desc msm_clocks_8x50[] = {
326 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), 327 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
327 CLK_PCOM("ce_clk", CE_CLK, NULL, 0), 328 CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
328 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), 329 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
@@ -376,5 +377,12 @@ struct clk_lookup msm_clocks_8x50[] = {
376 CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), 377 CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
377}; 378};
378 379
379unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50); 380static struct pcom_clk_pdata msm_clock_8x50_pdata = {
381 .lookup = msm_clocks_8x50,
382 .num_lookups = ARRAY_SIZE(msm_clocks_8x50),
383};
380 384
385struct platform_device msm_clock_8x50 = {
386 .name = "msm-clock-pcom",
387 .dev.platform_data = &msm_clock_8x50_pdata,
388};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index da902cf51161..dccefad9f9b9 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -16,10 +16,6 @@
16#ifndef __ARCH_ARM_MACH_MSM_DEVICES_H 16#ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
17#define __ARCH_ARM_MACH_MSM_DEVICES_H 17#define __ARCH_ARM_MACH_MSM_DEVICES_H
18 18
19#include <linux/clkdev.h>
20
21#include "clock.h"
22
23extern struct platform_device msm_device_gpio_7201; 19extern struct platform_device msm_device_gpio_7201;
24extern struct platform_device msm_device_gpio_7x30; 20extern struct platform_device msm_device_gpio_7x30;
25extern struct platform_device msm_device_gpio_8x50; 21extern struct platform_device msm_device_gpio_8x50;
@@ -50,13 +46,8 @@ extern struct platform_device msm_device_mddi0;
50extern struct platform_device msm_device_mddi1; 46extern struct platform_device msm_device_mddi1;
51extern struct platform_device msm_device_mdp; 47extern struct platform_device msm_device_mdp;
52 48
53extern struct clk_lookup msm_clocks_7x01a[]; 49extern struct platform_device msm_clock_7x01a;
54extern unsigned msm_num_clocks_7x01a; 50extern struct platform_device msm_clock_7x30;
55 51extern struct platform_device msm_clock_8x50;
56extern struct clk_lookup msm_clocks_7x30[];
57extern unsigned msm_num_clocks_7x30;
58
59extern struct clk_lookup msm_clocks_8x50[];
60extern unsigned msm_num_clocks_8x50;
61 52
62#endif 53#endif
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index b279fd8a31b1..f8f6adfa07c6 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -284,6 +284,7 @@ static int __init msm_init_datamover(void)
284 clk = clk_get(NULL, "adm_clk"); 284 clk = clk_get(NULL, "adm_clk");
285 if (IS_ERR(clk)) 285 if (IS_ERR(clk))
286 return PTR_ERR(clk); 286 return PTR_ERR(clk);
287 clk_prepare(clk);
287 msm_dmov_clk = clk; 288 msm_dmov_clk = clk;
288 ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL); 289 ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL);
289 if (ret) 290 if (ret)
@@ -291,6 +292,4 @@ static int __init msm_init_datamover(void)
291 disable_irq(INT_ADM_AARM); 292 disable_irq(INT_ADM_AARM);
292 return 0; 293 return 0;
293} 294}
294 295module_init(msm_init_datamover);
295arch_initcall(msm_init_datamover);
296
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 8cebedb11233..c34e246a3e07 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -20,16 +20,11 @@
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/platform_data/mmc-msm_sdcc.h> 21#include <linux/platform_data/mmc-msm_sdcc.h>
22 22
23/* platform device data structures */
24
25struct clk_lookup;
26
27/* common init routines for use by arch/arm/mach-msm/board-*.c */ 23/* common init routines for use by arch/arm/mach-msm/board-*.c */
28 24
29void __init msm_add_devices(void); 25void __init msm_add_devices(void);
30void __init msm_init_irq(void); 26void __init msm_init_irq(void);
31void __init msm_init_gpio(void); 27void __init msm_init_gpio(void);
32void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
33int __init msm_add_sdcc(unsigned int controller, 28int __init msm_add_sdcc(unsigned int controller,
34 struct msm_mmc_platform_data *plat, 29 struct msm_mmc_platform_data *plat,
35 unsigned int stat_irq, unsigned long stat_irq_flags); 30 unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
index e8d38428d813..fd4f4a7a83b3 100644
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ b/arch/arm/mach-msm/include/mach/clk.h
@@ -25,16 +25,7 @@ enum clk_reset_action {
25 25
26struct clk; 26struct clk;
27 27
28/* Rate is minimum clock rate in Hz */
29int clk_set_min_rate(struct clk *clk, unsigned long rate);
30
31/* Rate is maximum clock rate in Hz */
32int clk_set_max_rate(struct clk *clk, unsigned long rate);
33
34/* Assert/Deassert reset to a hardware block associated with a clock */ 28/* Assert/Deassert reset to a hardware block associated with a clock */
35int clk_reset(struct clk *clk, enum clk_reset_action action); 29int clk_reset(struct clk *clk, enum clk_reset_action action);
36 30
37/* Set clock-specific configuration parameters */
38int clk_set_flags(struct clk *clk, unsigned long flags);
39
40#endif 31#endif
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
new file mode 100644
index 000000000000..59d8f0a70919
--- /dev/null
+++ b/arch/arm/mach-nspire/Kconfig
@@ -0,0 +1,16 @@
1config ARCH_NSPIRE
2 bool "TI-NSPIRE based"
3 depends on ARCH_MULTI_V4_V5
4 depends on MMU
5 select CPU_ARM926T
6 select COMMON_CLK
7 select GENERIC_CLOCKEVENTS
8 select GENERIC_IRQ_CHIP
9 select SPARSE_IRQ
10 select ARM_AMBA
11 select ARM_VIC
12 select ARM_TIMER_SP804
13 select USE_OF
14 select CLKSRC_OF
15 help
16 This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile
new file mode 100644
index 000000000000..1bec256eba07
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile
@@ -0,0 +1,2 @@
1obj-y += nspire.o
2obj-y += clcd.o
diff --git a/arch/arm/mach-nspire/Makefile.boot b/arch/arm/mach-nspire/Makefile.boot
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile.boot
diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
new file mode 100644
index 000000000000..abea12617b17
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.c
@@ -0,0 +1,119 @@
1/*
2 * linux/arch/arm/mach-nspire/clcd.c
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/init.h>
13#include <linux/of.h>
14#include <linux/amba/bus.h>
15#include <linux/amba/clcd.h>
16#include <linux/dma-mapping.h>
17
18static struct clcd_panel nspire_cx_lcd_panel = {
19 .mode = {
20 .name = "Color LCD",
21 .refresh = 60,
22 .xres = 320,
23 .yres = 240,
24 .sync = 0,
25 .vmode = FB_VMODE_NONINTERLACED,
26 .pixclock = 1,
27 .hsync_len = 6,
28 .vsync_len = 1,
29 .right_margin = 50,
30 .left_margin = 38,
31 .lower_margin = 3,
32 .upper_margin = 17,
33 },
34 .width = 65, /* ~6.50 cm */
35 .height = 49, /* ~4.87 cm */
36 .tim2 = TIM2_IPC,
37 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
38 .bpp = 16,
39 .caps = CLCD_CAP_565,
40};
41
42static struct clcd_panel nspire_classic_lcd_panel = {
43 .mode = {
44 .name = "Grayscale LCD",
45 .refresh = 60,
46 .xres = 320,
47 .yres = 240,
48 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
49 .vmode = FB_VMODE_NONINTERLACED,
50 .pixclock = 1,
51 .hsync_len = 6,
52 .vsync_len = 1,
53 .right_margin = 6,
54 .left_margin = 6,
55 },
56 .width = 71, /* 7.11cm */
57 .height = 53, /* 5.33cm */
58 .tim2 = 0x80007d0,
59 .cntl = CNTL_LCDMONO8,
60 .bpp = 8,
61 .grayscale = 1,
62 .caps = CLCD_CAP_5551,
63};
64
65int nspire_clcd_setup(struct clcd_fb *fb)
66{
67 struct clcd_panel *panel;
68 size_t panel_size;
69 const char *type;
70 dma_addr_t dma;
71 int err;
72
73 BUG_ON(!fb->dev->dev.of_node);
74
75 err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type);
76 if (err) {
77 pr_err("CLCD: Could not find lcd-type property\n");
78 return err;
79 }
80
81 if (!strcmp(type, "cx")) {
82 panel = &nspire_cx_lcd_panel;
83 } else if (!strcmp(type, "classic")) {
84 panel = &nspire_classic_lcd_panel;
85 } else {
86 pr_err("CLCD: Unknown lcd-type %s\n", type);
87 return -EINVAL;
88 }
89
90 panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8;
91 panel_size = ALIGN(panel_size, PAGE_SIZE);
92
93 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
94 panel_size, &dma, GFP_KERNEL);
95
96 if (!fb->fb.screen_base) {
97 pr_err("CLCD: unable to map framebuffer\n");
98 return -ENOMEM;
99 }
100
101 fb->fb.fix.smem_start = dma;
102 fb->fb.fix.smem_len = panel_size;
103 fb->panel = panel;
104
105 return 0;
106}
107
108int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
109{
110 return dma_mmap_writecombine(&fb->dev->dev, vma,
111 fb->fb.screen_base, fb->fb.fix.smem_start,
112 fb->fb.fix.smem_len);
113}
114
115void nspire_clcd_remove(struct clcd_fb *fb)
116{
117 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
118 fb->fb.screen_base, fb->fb.fix.smem_start);
119}
diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h
new file mode 100644
index 000000000000..8c33d2c18371
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.h
@@ -0,0 +1,14 @@
1/*
2 * linux/arch/arm/mach-nspire/clcd.h
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12int nspire_clcd_setup(struct clcd_fb *fb);
13int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
14void nspire_clcd_remove(struct clcd_fb *fb);
diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h
new file mode 100644
index 000000000000..8813471af4cf
--- /dev/null
+++ b/arch/arm/mach-nspire/mmio.h
@@ -0,0 +1,20 @@
1/*
2 * linux/arch/arm/mach-nspire/mmio.h
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define NSPIRE_MISC_PHYS_BASE 0x900A0000
13#define NSPIRE_MISC_HWRESET 0x08
14
15#define NSPIRE_PWR_PHYS_BASE 0x900B0000
16#define NSPIRE_PWR_VIRT_BASE 0xFEEB0000
17#define NSPIRE_PWR_BUS_DISABLE1 0x18
18#define NSPIRE_PWR_BUS_DISABLE2 0x20
19
20#define NSPIRE_LCD_PHYS_BASE 0xC0000000
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
new file mode 100644
index 000000000000..99e26092a9f7
--- /dev/null
+++ b/arch/arm/mach-nspire/nspire.c
@@ -0,0 +1,89 @@
1/*
2 * linux/arch/arm/mach-nspire/nspire.c
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/init.h>
12#include <linux/of_irq.h>
13#include <linux/of_address.h>
14#include <linux/of_platform.h>
15#include <linux/irqchip.h>
16#include <linux/irqchip/arm-vic.h>
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/amba/bus.h>
20#include <linux/amba/clcd.h>
21#include <linux/clocksource.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach-types.h>
25#include <asm/mach/map.h>
26
27#include <asm/hardware/timer-sp.h>
28
29#include "mmio.h"
30#include "clcd.h"
31
32static const char *nspire_dt_match[] __initconst = {
33 "ti,nspire",
34 "ti,nspire-cx",
35 "ti,nspire-tp",
36 "ti,nspire-clp",
37 NULL,
38};
39
40static void __init nspire_map_io(void)
41{
42 debug_ll_io_init();
43}
44
45static struct clcd_board nspire_clcd_data = {
46 .name = "LCD",
47 .caps = CLCD_CAP_5551 | CLCD_CAP_565,
48 .check = clcdfb_check,
49 .decode = clcdfb_decode,
50 .setup = nspire_clcd_setup,
51 .mmap = nspire_clcd_mmap,
52 .remove = nspire_clcd_remove,
53};
54
55
56static struct of_dev_auxdata nspire_auxdata[] __initdata = {
57 OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE,
58 NULL, &nspire_clcd_data),
59 { }
60};
61
62static void __init nspire_init(void)
63{
64 of_platform_populate(NULL, of_default_bus_match_table,
65 nspire_auxdata, NULL);
66}
67
68static void __init nspire_init_time(void)
69{
70 of_clk_init(NULL);
71 clocksource_of_init();
72}
73
74static void nspire_restart(char mode, const char *cmd)
75{
76 void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
77 if (!base)
78 return;
79
80 writel(2, base + NSPIRE_MISC_HWRESET);
81}
82
83DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
84 .dt_compat = nspire_dt_match,
85 .map_io = nspire_map_io,
86 .init_time = nspire_init_time,
87 .init_machine = nspire_init,
88 .restart = nspire_restart,
89MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index b461d93431ed..28f94752b8ff 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -30,17 +30,17 @@
30#include <mach/r8a7790.h> 30#include <mach/r8a7790.h>
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32 32
33static const struct resource pfc_resources[] = { 33static struct resource pfc_resources[] __initdata = {
34 DEFINE_RES_MEM(0xe6060000, 0x250), 34 DEFINE_RES_MEM(0xe6060000, 0x250),
35}; 35};
36 36
37#define R8A7790_GPIO(idx) \ 37#define R8A7790_GPIO(idx) \
38static struct resource r8a7790_gpio##idx##_resources[] = { \ 38static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \
39 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ 39 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
40 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ 40 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
41}; \ 41}; \
42 \ 42 \
43static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = { \ 43static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
44 .gpio_base = 32 * (idx), \ 44 .gpio_base = 32 * (idx), \
45 .irq_base = 0, \ 45 .irq_base = 0, \
46 .number_of_pins = 32, \ 46 .number_of_pins = 32, \
@@ -98,12 +98,20 @@ void __init r8a7790_pinmux_init(void)
98[index] = { \ 98[index] = { \
99 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ 99 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
100 .scbrr_algo_id = SCBRR_ALGO_2, \ 100 .scbrr_algo_id = SCBRR_ALGO_2, \
101 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 101 .scscr = SCSCR_RE | SCSCR_TE, \
102} 102}
103 103
104enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 }; 104#define HSCIF_DATA(index, baseaddr, irq) \
105[index] = { \
106 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
107 .scbrr_algo_id = SCBRR_ALGO_6, \
108 .scscr = SCSCR_RE | SCSCR_TE, \
109}
110
111enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
112 HSCIF0, HSCIF1 };
105 113
106static const struct plat_sci_port scif[] = { 114static struct plat_sci_port scif[] __initdata = {
107 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 115 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
108 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 116 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
109 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 117 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
@@ -112,6 +120,8 @@ static const struct plat_sci_port scif[] = {
112 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ 120 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
113 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ 121 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
114 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ 122 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
123 HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
124 HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
115}; 125};
116 126
117static inline void r8a7790_register_scif(int idx) 127static inline void r8a7790_register_scif(int idx)
@@ -120,11 +130,11 @@ static inline void r8a7790_register_scif(int idx)
120 sizeof(struct plat_sci_port)); 130 sizeof(struct plat_sci_port));
121} 131}
122 132
123static struct renesas_irqc_config irqc0_data = { 133static struct renesas_irqc_config irqc0_data __initdata = {
124 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 134 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
125}; 135};
126 136
127static struct resource irqc0_resources[] = { 137static struct resource irqc0_resources[] __initdata = {
128 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ 138 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
129 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ 139 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
130 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ 140 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
@@ -149,6 +159,8 @@ void __init r8a7790_add_standard_devices(void)
149 r8a7790_register_scif(SCIFA2); 159 r8a7790_register_scif(SCIFA2);
150 r8a7790_register_scif(SCIF0); 160 r8a7790_register_scif(SCIF0);
151 r8a7790_register_scif(SCIF1); 161 r8a7790_register_scif(SCIF1);
162 r8a7790_register_scif(HSCIF0);
163 r8a7790_register_scif(HSCIF1);
152 r8a7790_register_irqc(0); 164 r8a7790_register_irqc(0);
153} 165}
154 166
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
new file mode 100644
index 000000000000..d04e3bfe1918
--- /dev/null
+++ b/arch/arm/mach-sti/Kconfig
@@ -0,0 +1,45 @@
1menuconfig ARCH_STI
2 bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
3 select GENERIC_CLOCKEVENTS
4 select CLKDEV_LOOKUP
5 select ARM_GIC
6 select ARM_GLOBAL_TIMER
7 select PINCTRL
8 select PINCTRL_ST
9 select MFD_SYSCON
10 select MIGHT_HAVE_CACHE_L2X0
11 select HAVE_SMP
12 select HAVE_ARM_SCU if SMP
13 select ARCH_REQUIRE_GPIOLIB
14 select ARM_ERRATA_720789
15 select ARM_ERRATA_754322
16 select PL310_ERRATA_753970 if CACHE_PL310
17 select PL310_ERRATA_769419 if CACHE_PL310
18 help
19 Include support for STiH41x SOCs like STiH415/416 using the device tree
20 for discovery
21 More information at Documentation/arm/STiH41x and
22 at Documentation/devicetree
23
24
25if ARCH_STI
26
27config SOC_STIH415
28 bool "STiH415 STMicroelectronics Consumer Electronics family"
29 default y
30 help
31 This enables support for STMicroelectronics Digital Consumer
32 Electronics family StiH415 parts, primarily targetted at set-top-box
33 and other digital audio/video applications using Flattned Device
34 Trees.
35
36config SOC_STIH416
37 bool "STiH416 STMicroelectronics Consumer Electronics family"
38 default y
39 help
40 This enables support for STMicroelectronics Digital Consumer
41 Electronics family StiH416 parts, primarily targetted at set-top-box
42 and other digital audio/video applications using Flattened Device
43 Trees.
44
45endif
diff --git a/arch/arm/mach-sti/Makefile b/arch/arm/mach-sti/Makefile
new file mode 100644
index 000000000000..acb330916333
--- /dev/null
+++ b/arch/arm/mach-sti/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_SMP) += platsmp.o headsmp.o
2obj-$(CONFIG_ARCH_STI) += board-dt.o
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
new file mode 100644
index 000000000000..8fe6f0c46480
--- /dev/null
+++ b/arch/arm/mach-sti/board-dt.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author(s): Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/clocksource.h>
12#include <linux/irq.h>
13#include <asm/hardware/cache-l2x0.h>
14#include <asm/mach/arch.h>
15
16#include "smp.h"
17
18void __init stih41x_l2x0_init(void)
19{
20 u32 way_size = 0x4;
21 u32 aux_ctrl;
22 /* may be this can be encoded in macros like BIT*() */
23 aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
24 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
25 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
26 (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
27
28 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
29}
30
31static void __init stih41x_timer_init(void)
32{
33 of_clk_init(NULL);
34 clocksource_of_init();
35 stih41x_l2x0_init();
36}
37
38static const char *stih41x_dt_match[] __initdata = {
39 "st,stih415",
40 "st,stih416",
41 NULL
42};
43
44DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
45 .init_time = stih41x_timer_init,
46 .smp = smp_ops(sti_smp_ops),
47 .dt_compat = stih41x_dt_match,
48MACHINE_END
diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S
new file mode 100644
index 000000000000..78ebc7559f53
--- /dev/null
+++ b/arch/arm/mach-sti/headsmp.S
@@ -0,0 +1,44 @@
1/*
2 * arch/arm/mach-sti/headsmp.S
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * http://www.st.com
6 *
7 * Cloned from linux/arch/arm/mach-vexpress/headsmp.S
8 *
9 * Copyright (c) 2003 ARM Limited
10 * All Rights Reserved
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/linkage.h>
17#include <linux/init.h>
18
19 __INIT
20
21/*
22 * ST specific entry point for secondary CPUs. This provides
23 * a "holding pen" into which all secondary cores are held until we're
24 * ready for them to initialise.
25 */
26ENTRY(sti_secondary_startup)
27 mrc p15, 0, r0, c0, c0, 5
28 and r0, r0, #15
29 adr r4, 1f
30 ldmia r4, {r5, r6}
31 sub r4, r4, r5
32 add r6, r6, r4
33pen: ldr r7, [r6]
34 cmp r7, r0
35 bne pen
36
37 /*
38 * we've been released from the holding pen: secondary_stack
39 * should now contain the SVC stack for this core
40 */
41 b secondary_startup
42
431: .long .
44 .long pen_release
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
new file mode 100644
index 000000000000..977a863468fc
--- /dev/null
+++ b/arch/arm/mach-sti/platsmp.c
@@ -0,0 +1,117 @@
1/*
2 * arch/arm/mach-sti/platsmp.c
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * http://www.st.com
6 *
7 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 *
9 * Copyright (C) 2002 ARM Ltd.
10 * All Rights Reserved
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/delay.h>
19#include <linux/smp.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23
24#include <asm/cacheflush.h>
25#include <asm/smp_plat.h>
26#include <asm/smp_scu.h>
27
28#include "smp.h"
29
30static void __cpuinit write_pen_release(int val)
31{
32 pen_release = val;
33 smp_wmb();
34 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
35 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
36}
37
38static DEFINE_SPINLOCK(boot_lock);
39
40void __cpuinit sti_secondary_init(unsigned int cpu)
41{
42 trace_hardirqs_off();
43
44 /*
45 * let the primary processor know we're out of the
46 * pen, then head off into the C entry point
47 */
48 write_pen_release(-1);
49
50 /*
51 * Synchronise with the boot thread.
52 */
53 spin_lock(&boot_lock);
54 spin_unlock(&boot_lock);
55}
56
57int __cpuinit sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
58{
59 unsigned long timeout;
60
61 /*
62 * set synchronisation state between this boot processor
63 * and the secondary one
64 */
65 spin_lock(&boot_lock);
66
67 /*
68 * The secondary processor is waiting to be released from
69 * the holding pen - release it, then wait for it to flag
70 * that it has been released by resetting pen_release.
71 *
72 * Note that "pen_release" is the hardware CPU ID, whereas
73 * "cpu" is Linux's internal ID.
74 */
75 write_pen_release(cpu_logical_map(cpu));
76
77 /*
78 * Send the secondary CPU a soft interrupt, thereby causing
79 * it to jump to the secondary entrypoint.
80 */
81 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
82
83 timeout = jiffies + (1 * HZ);
84 while (time_before(jiffies, timeout)) {
85 smp_rmb();
86 if (pen_release == -1)
87 break;
88
89 udelay(10);
90 }
91
92 /*
93 * now the secondary core is starting up let it run its
94 * calibrations, then wait for it to finish
95 */
96 spin_unlock(&boot_lock);
97
98 return pen_release != -1 ? -ENOSYS : 0;
99}
100
101void __init sti_smp_prepare_cpus(unsigned int max_cpus)
102{
103 void __iomem *scu_base = NULL;
104 struct device_node *np = of_find_compatible_node(
105 NULL, NULL, "arm,cortex-a9-scu");
106 if (np) {
107 scu_base = of_iomap(np, 0);
108 scu_enable(scu_base);
109 of_node_put(np);
110 }
111}
112
113struct smp_operations __initdata sti_smp_ops = {
114 .smp_prepare_cpus = sti_smp_prepare_cpus,
115 .smp_secondary_init = sti_secondary_init,
116 .smp_boot_secondary = sti_boot_secondary,
117};
diff --git a/arch/arm/mach-sti/smp.h b/arch/arm/mach-sti/smp.h
new file mode 100644
index 000000000000..1871b72b1a7e
--- /dev/null
+++ b/arch/arm/mach-sti/smp.h
@@ -0,0 +1,17 @@
1/*
2 * arch/arm/mach-sti/smp.h
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * http://www.st.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_STI_SMP_H
13#define __MACH_STI_SMP_H
14
15extern struct smp_operations sti_smp_ops;
16
17#endif
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index f58615b5c601..82ccf1d98735 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -42,7 +42,8 @@ static int __init ux500_l2x0_init(void)
42 if (cpu_is_u8500_family() || cpu_is_ux540_family()) 42 if (cpu_is_u8500_family() || cpu_is_ux540_family())
43 l2x0_base = __io_address(U8500_L2CC_BASE); 43 l2x0_base = __io_address(U8500_L2CC_BASE);
44 else 44 else
45 ux500_unknown_soc(); 45 /* Non-Ux500 platform */
46 return -ENODEV;
46 47
47 /* Unlock before init */ 48 /* Unlock before init */
48 ux500_l2x0_unlock(); 49 ux500_l2x0_unlock();
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 989fefe18be6..4fb1f03a10d1 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
46#define EXYNOS4_CPU_MASK 0xFFFE0000 46#define EXYNOS4_CPU_MASK 0xFFFE0000
47 47
48#define EXYNOS5250_SOC_ID 0x43520000 48#define EXYNOS5250_SOC_ID 0x43520000
49#define EXYNOS5420_SOC_ID 0xE5420000
49#define EXYNOS5440_SOC_ID 0xE5440000 50#define EXYNOS5440_SOC_ID 0xE5440000
50#define EXYNOS5_SOC_MASK 0xFFFFF000 51#define EXYNOS5_SOC_MASK 0xFFFFF000
51 52
@@ -67,6 +68,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
67IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) 68IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
68IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) 69IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
69IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) 70IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
71IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
70IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) 72IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
71 73
72#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 74#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
@@ -142,6 +144,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
142# define soc_is_exynos5250() 0 144# define soc_is_exynos5250() 0
143#endif 145#endif
144 146
147#if defined(CONFIG_SOC_EXYNOS5420)
148# define soc_is_exynos5420() is_samsung_exynos5420()
149#else
150# define soc_is_exynos5420() 0
151#endif
152
145#if defined(CONFIG_SOC_EXYNOS5440) 153#if defined(CONFIG_SOC_EXYNOS5440)
146# define soc_is_exynos5440() is_samsung_exynos5440() 154# define soc_is_exynos5440() is_samsung_exynos5440()
147#else 155#else
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 187681013bdb..5d4d432cc4ac 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,5 +5,6 @@
5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o 5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o 6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o 7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
8obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
8obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 9obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
9obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 10obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
new file mode 100644
index 000000000000..68a96cbd4936
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -0,0 +1,762 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Authors: Thomas Abraham <thomas.ab@samsung.com>
4 * Chander Kashyap <k.chander@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5420 SoC.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22#define SRC_CPU 0x200
23#define DIV_CPU0 0x500
24#define DIV_CPU1 0x504
25#define GATE_BUS_CPU 0x700
26#define GATE_SCLK_CPU 0x800
27#define SRC_TOP0 0x10200
28#define SRC_TOP1 0x10204
29#define SRC_TOP2 0x10208
30#define SRC_TOP3 0x1020c
31#define SRC_TOP4 0x10210
32#define SRC_TOP5 0x10214
33#define SRC_TOP6 0x10218
34#define SRC_TOP7 0x1021c
35#define SRC_DISP10 0x1022c
36#define SRC_MAU 0x10240
37#define SRC_FSYS 0x10244
38#define SRC_PERIC0 0x10250
39#define SRC_PERIC1 0x10254
40#define SRC_TOP10 0x10280
41#define SRC_TOP11 0x10284
42#define SRC_TOP12 0x10288
43#define SRC_MASK_DISP10 0x1032c
44#define SRC_MASK_FSYS 0x10340
45#define SRC_MASK_PERIC0 0x10350
46#define SRC_MASK_PERIC1 0x10354
47#define DIV_TOP0 0x10500
48#define DIV_TOP1 0x10504
49#define DIV_TOP2 0x10508
50#define DIV_DISP10 0x1052c
51#define DIV_MAU 0x10544
52#define DIV_FSYS0 0x10548
53#define DIV_FSYS1 0x1054c
54#define DIV_FSYS2 0x10550
55#define DIV_PERIC0 0x10558
56#define DIV_PERIC1 0x1055c
57#define DIV_PERIC2 0x10560
58#define DIV_PERIC3 0x10564
59#define DIV_PERIC4 0x10568
60#define GATE_BUS_TOP 0x10700
61#define GATE_BUS_FSYS0 0x10740
62#define GATE_BUS_PERIC 0x10750
63#define GATE_BUS_PERIC1 0x10754
64#define GATE_BUS_PERIS0 0x10760
65#define GATE_BUS_PERIS1 0x10764
66#define GATE_IP_GSCL0 0x10910
67#define GATE_IP_GSCL1 0x10920
68#define GATE_IP_MFC 0x1092c
69#define GATE_IP_DISP1 0x10928
70#define GATE_IP_G3D 0x10930
71#define GATE_IP_GEN 0x10934
72#define GATE_IP_MSCL 0x10970
73#define GATE_TOP_SCLK_GSCL 0x10820
74#define GATE_TOP_SCLK_DISP1 0x10828
75#define GATE_TOP_SCLK_MAU 0x1083c
76#define GATE_TOP_SCLK_FSYS 0x10840
77#define GATE_TOP_SCLK_PERIC 0x10850
78#define SRC_CDREX 0x20200
79#define SRC_KFC 0x28200
80#define DIV_KFC0 0x28500
81
82enum exynos5420_clks {
83 none,
84
85 /* core clocks */
86 fin_pll,
87
88 /* gate for special clocks (sclk) */
89 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
90 sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
91 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
92 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
93 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
94 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
95
96 /* gate clocks */
97 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
98 i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
99 i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
100 chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
101 tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
102 pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
103 aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
104 aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
105 smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
106 aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
107 smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
108 smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
109 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
110 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
111 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
112 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
113
114 nr_clks,
115};
116
117/*
118 * list of controller registers to be saved and restored during a
119 * suspend/resume cycle.
120 */
121static __initdata unsigned long exynos5420_clk_regs[] = {
122 SRC_CPU,
123 DIV_CPU0,
124 DIV_CPU1,
125 GATE_BUS_CPU,
126 GATE_SCLK_CPU,
127 SRC_TOP0,
128 SRC_TOP1,
129 SRC_TOP2,
130 SRC_TOP3,
131 SRC_TOP4,
132 SRC_TOP5,
133 SRC_TOP6,
134 SRC_TOP7,
135 SRC_DISP10,
136 SRC_MAU,
137 SRC_FSYS,
138 SRC_PERIC0,
139 SRC_PERIC1,
140 SRC_TOP10,
141 SRC_TOP11,
142 SRC_TOP12,
143 SRC_MASK_DISP10,
144 SRC_MASK_FSYS,
145 SRC_MASK_PERIC0,
146 SRC_MASK_PERIC1,
147 DIV_TOP0,
148 DIV_TOP1,
149 DIV_TOP2,
150 DIV_DISP10,
151 DIV_MAU,
152 DIV_FSYS0,
153 DIV_FSYS1,
154 DIV_FSYS2,
155 DIV_PERIC0,
156 DIV_PERIC1,
157 DIV_PERIC2,
158 DIV_PERIC3,
159 DIV_PERIC4,
160 GATE_BUS_TOP,
161 GATE_BUS_FSYS0,
162 GATE_BUS_PERIC,
163 GATE_BUS_PERIC1,
164 GATE_BUS_PERIS0,
165 GATE_BUS_PERIS1,
166 GATE_IP_GSCL0,
167 GATE_IP_GSCL1,
168 GATE_IP_MFC,
169 GATE_IP_DISP1,
170 GATE_IP_G3D,
171 GATE_IP_GEN,
172 GATE_IP_MSCL,
173 GATE_TOP_SCLK_GSCL,
174 GATE_TOP_SCLK_DISP1,
175 GATE_TOP_SCLK_MAU,
176 GATE_TOP_SCLK_FSYS,
177 GATE_TOP_SCLK_PERIC,
178 SRC_CDREX,
179 SRC_KFC,
180 DIV_KFC0,
181};
182
183/* list of all parent clocks */
184PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll",
185 "sclk_mpll", "sclk_spll" };
186PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" };
187PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" };
188PNAME(apll_p) = { "fin_pll", "fout_apll", };
189PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
190PNAME(cpll_p) = { "fin_pll", "fout_cpll", };
191PNAME(dpll_p) = { "fin_pll", "fout_dpll", };
192PNAME(epll_p) = { "fin_pll", "fout_epll", };
193PNAME(ipll_p) = { "fin_pll", "fout_ipll", };
194PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
195PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
196PNAME(rpll_p) = { "fin_pll", "fout_rpll", };
197PNAME(spll_p) = { "fin_pll", "fout_spll", };
198PNAME(vpll_p) = { "fin_pll", "fout_vpll", };
199
200PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" };
201PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
202 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
203PNAME(group3_p) = { "sclk_rpll", "sclk_spll" };
204PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" };
205PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" };
206
207PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" };
208PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" };
209
210PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"};
211PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" };
212
213PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"};
214PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" };
215
216PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"};
217PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" };
218
219PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"};
220PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" };
221
222PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"};
223PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" };
224
225PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"};
226PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" };
227
228PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"};
229PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" };
230
231PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"};
232PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" };
233
234PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"};
235PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" };
236
237PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"};
238PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" };
239
240PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"};
241PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" };
242
243PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"};
244PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" };
245
246PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"};
247PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" };
248
249PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"};
250PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" };
251
252PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll",
253 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
254PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll",
255 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
256PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
257 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
258PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
259 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
260PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" };
261PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
262 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
263
264/* fixed rate clocks generated outside the soc */
265struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
266 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
267};
268
269/* fixed rate clocks generated inside the soc */
270struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
271 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
272 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
273 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
274 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
275 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
276};
277
278struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
279 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
280};
281
282struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
283 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
284 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
285 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
286 MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
287 MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
288 MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
289
290 MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
291
292 MUX_A(none, "mout_aclk400_mscl", group1_p,
293 SRC_TOP0, 4, 2, "aclk400_mscl"),
294 MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
295 MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
296 MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
297
298 MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
299 MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
300 MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
301 MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
302 MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
303
304 MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
305 MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
306 MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
307 MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
308 MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
309 MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
310
311 MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
312 SRC_TOP3, 4, 1),
313 MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p,
314 SRC_TOP3, 8, 1, "aclk200_disp1"),
315 MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
316 SRC_TOP3, 12, 1),
317 MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
318 SRC_TOP3, 28, 1),
319
320 MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
321 SRC_TOP4, 0, 1),
322 MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
323 MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
324 MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
325 MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
326
327 MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
328 MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
329 MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
330 MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p,
331 SRC_TOP5, 16, 1, "aclkg3d"),
332 MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
333 SRC_TOP5, 20, 1),
334 MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
335 SRC_TOP5, 24, 1),
336 MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
337 SRC_TOP5, 28, 1),
338
339 MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
340 MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
341 MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
342 MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
343 MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
344 MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
345 MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
346 MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
347
348 MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
349 MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
350 MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
351 SRC_TOP10, 12, 1),
352 MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
353
354 MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
355 SRC_TOP11, 0, 1),
356 MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
357 MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
358 MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
359 MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
360
361 MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
362 MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
363 MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
364 MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
365 MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
366 SRC_TOP12, 24, 1),
367 MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
368
369 /* DISP1 Block */
370 MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
371 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
372 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
373 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
374 MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
375
376 /* MAU Block */
377 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
378
379 /* FSYS Block */
380 MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
381 MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
382 MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
383 MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
384 MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
385 MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
386
387 /* PERIC Block */
388 MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
389 MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
390 MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
391 MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
392 MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
393 MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
394 MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
395 MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
396 MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
397 MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
398 MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
399 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
400};
401
402struct samsung_div_clock exynos5420_div_clks[] __initdata = {
403 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
404 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
405 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3),
406 DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
407 DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
408
409 DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
410 DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
411 DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
412 DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
413 DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
414
415 DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
416 DIV_TOP1, 0, 3),
417 DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
418 DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
419 DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
420 DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
421
422 DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
423 DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
424 DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
425 DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
426 DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1",
427 DIV_TOP2, 24, 3, "aclk300_disp1"),
428 DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
429
430 /* DISP1 Block */
431 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
432 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
433 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
434 DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
435
436 /* Audio Block */
437 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
438 DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
439
440 /* USB3.0 */
441 DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
442 DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
443 DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
444 DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
445
446 /* MMC */
447 DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
448 DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
449 DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
450
451 DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
452
453 /* UART and PWM */
454 DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
455 DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
456 DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
457 DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
458 DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
459
460 /* SPI */
461 DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
462 DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
463 DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
464
465 /* PCM */
466 DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
467 DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
468
469 /* Audio - I2S */
470 DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
471 DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
472 DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
473 DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
474 DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
475
476 /* SPI Pre-Ratio */
477 DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
478 DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
479 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
480};
481
482struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
483 /* TODO: Re-verify the CG bits for all the gate clocks */
484 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"),
485
486 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
487 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
488 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
489 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
490
491 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
492 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
493 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
494 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
495 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
496 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
497 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
498 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
499 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
500 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
501 GATE(0, "pclk66_gpio", "mout_sw_aclk66",
502 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
503 GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
504 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
505 GATE(0, "aclk66_peric", "mout_aclk66_peric",
506 GATE_BUS_TOP, 11, 0, 0),
507 GATE(0, "aclk166", "mout_user_aclk166",
508 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
509 GATE(0, "aclk333", "mout_aclk333",
510 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
511
512 /* sclk */
513 GATE(sclk_uart0, "sclk_uart0", "dout_uart0",
514 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
515 GATE(sclk_uart1, "sclk_uart1", "dout_uart1",
516 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
517 GATE(sclk_uart2, "sclk_uart2", "dout_uart2",
518 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
519 GATE(sclk_uart3, "sclk_uart3", "dout_uart3",
520 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
521 GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0",
522 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
523 GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1",
524 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
525 GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2",
526 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
527 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
528 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
529 GATE(sclk_pwm, "sclk_pwm", "dout_pwm",
530 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
531 GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1",
532 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
533 GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2",
534 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
535 GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1",
536 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
537 GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2",
538 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
539
540 GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0",
541 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
542 GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1",
543 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
544 GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2",
545 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
546 GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301",
547 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
548 GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300",
549 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
550 GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300",
551 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
552 GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301",
553 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
554
555 GATE(sclk_usbd301, "sclk_unipro", "dout_unipro",
556 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
557
558 GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl",
559 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
560 GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl",
561 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
562
563 /* Display */
564 GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1",
565 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
566 GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1",
567 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
568 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
569 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
570 GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
571 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
572 GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
573 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
574
575 /* Maudio Block */
576 GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0",
577 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
578 GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0",
579 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
580 /* FSYS */
581 GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
582 GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
583 GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
584 GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
585 GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
586 GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
587 GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
588 GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
589 GATE(sromc, "sromc", "aclk200_fsys2",
590 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
591 GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
592 GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
593 GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
594
595 /* UART */
596 GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
597 GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
598 GATE_A(uart2, "uart2", "aclk66_peric",
599 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
600 GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
601 /* I2C */
602 GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
603 GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
604 GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
605 GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
606 GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
607 GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
608 GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
609 GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
610 GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0),
611 GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
612 /* SPI */
613 GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
614 GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
615 GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
616 GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
617 /* I2S */
618 GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
619 GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
620 /* PCM */
621 GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
622 GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
623 /* PWM */
624 GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
625 /* SPDIF */
626 GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
627
628 GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
629 GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
630 GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
631
632 GATE(chipid, "chipid", "aclk66_psgen",
633 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
634 GATE(sysreg, "sysreg", "aclk66_psgen",
635 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
636 GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
637 GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
638 GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
639 GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
640 GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
641 GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
642 GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
643 GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
644 GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
645 GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
646
647 GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0),
648 GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
649 GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
650 GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
651 GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
652 GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
653
654 GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
655 GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
656 GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
657
658 GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0),
659 GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl",
660 GATE_IP_GSCL1, 3, 0, 0),
661 GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl",
662 GATE_IP_GSCL1, 4, 0, 0),
663 GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0),
664 GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0),
665 GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
666 GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
667 GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl",
668 GATE_IP_GSCL1, 16, 0, 0),
669 GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl",
670 GATE_IP_GSCL1, 17, 0, 0),
671
672 GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
673 GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
674 GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
675 GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
676 GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
677 GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0),
678
679 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
680 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
681 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
682
683 GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
684
685 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
686 GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
687 GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
688 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
689 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
690 GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
691 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
692
693 GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
694 GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
695 GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
696 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
697 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
698 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
699};
700
701static __initdata struct of_device_id ext_clk_match[] = {
702 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
703 { },
704};
705
706/* register exynos5420 clocks */
707void __init exynos5420_clk_init(struct device_node *np)
708{
709 void __iomem *reg_base;
710 struct clk *apll, *bpll, *cpll, *dpll, *epll, *ipll, *kpll, *mpll;
711 struct clk *rpll, *spll, *vpll;
712
713 if (np) {
714 reg_base = of_iomap(np, 0);
715 if (!reg_base)
716 panic("%s: failed to map registers\n", __func__);
717 } else {
718 panic("%s: unable to determine soc\n", __func__);
719 }
720
721 samsung_clk_init(np, reg_base, nr_clks,
722 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
723 NULL, 0);
724 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
725 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
726 ext_clk_match);
727
728 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
729 reg_base + 0x100);
730 bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
731 reg_base + 0x20110);
732 cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
733 reg_base + 0x10120);
734 dpll = samsung_clk_register_pll35xx("fout_dpll", "fin_pll",
735 reg_base + 0x10128);
736 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
737 reg_base + 0x10130);
738 ipll = samsung_clk_register_pll35xx("fout_ipll", "fin_pll",
739 reg_base + 0x10150);
740 kpll = samsung_clk_register_pll35xx("fout_kpll", "fin_pll",
741 reg_base + 0x28100);
742 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
743 reg_base + 0x10180);
744 rpll = samsung_clk_register_pll36xx("fout_rpll", "fin_pll",
745 reg_base + 0x10140);
746 spll = samsung_clk_register_pll35xx("fout_spll", "fin_pll",
747 reg_base + 0x10160);
748 vpll = samsung_clk_register_pll35xx("fout_vpll", "fin_pll",
749 reg_base + 0x10170);
750
751 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
752 ARRAY_SIZE(exynos5420_fixed_rate_clks));
753 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
754 ARRAY_SIZE(exynos5420_fixed_factor_clks));
755 samsung_clk_register_mux(exynos5420_mux_clks,
756 ARRAY_SIZE(exynos5420_mux_clks));
757 samsung_clk_register_div(exynos5420_div_clks,
758 ARRAY_SIZE(exynos5420_div_clks));
759 samsung_clk_register_gate(exynos5420_gate_clks,
760 ARRAY_SIZE(exynos5420_gate_clks));
761}
762CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 662fcc065821..a70480409ea5 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -400,18 +400,6 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
400 return IRQ_HANDLED; 400 return IRQ_HANDLED;
401} 401}
402 402
403static struct irqaction mct_tick0_event_irq = {
404 .name = "mct_tick0_irq",
405 .flags = IRQF_TIMER | IRQF_NOBALANCING,
406 .handler = exynos4_mct_tick_isr,
407};
408
409static struct irqaction mct_tick1_event_irq = {
410 .name = "mct_tick1_irq",
411 .flags = IRQF_TIMER | IRQF_NOBALANCING,
412 .handler = exynos4_mct_tick_isr,
413};
414
415static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) 403static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
416{ 404{
417 struct mct_clock_event_device *mevt; 405 struct mct_clock_event_device *mevt;
@@ -435,16 +423,15 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
435 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 423 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
436 424
437 if (mct_int_type == MCT_INT_SPI) { 425 if (mct_int_type == MCT_INT_SPI) {
438 if (cpu == 0) { 426 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
439 mct_tick0_event_irq.dev_id = mevt; 427 if (request_irq(evt->irq, exynos4_mct_tick_isr,
440 evt->irq = mct_irqs[MCT_L0_IRQ]; 428 IRQF_TIMER | IRQF_NOBALANCING,
441 setup_irq(evt->irq, &mct_tick0_event_irq); 429 evt->name, mevt)) {
442 } else { 430 pr_err("exynos-mct: cannot register IRQ %d\n",
443 mct_tick1_event_irq.dev_id = mevt; 431 evt->irq);
444 evt->irq = mct_irqs[MCT_L1_IRQ]; 432 return -EIO;
445 setup_irq(evt->irq, &mct_tick1_event_irq);
446 irq_set_affinity(evt->irq, cpumask_of(1));
447 } 433 }
434 irq_set_affinity(evt->irq, cpumask_of(cpu));
448 } else { 435 } else {
449 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); 436 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
450 } 437 }
@@ -454,13 +441,9 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
454 441
455static void exynos4_local_timer_stop(struct clock_event_device *evt) 442static void exynos4_local_timer_stop(struct clock_event_device *evt)
456{ 443{
457 unsigned int cpu = smp_processor_id();
458 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 444 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
459 if (mct_int_type == MCT_INT_SPI) 445 if (mct_int_type == MCT_INT_SPI)
460 if (cpu == 0) 446 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
461 remove_irq(evt->irq, &mct_tick0_event_irq);
462 else
463 remove_irq(evt->irq, &mct_tick1_event_irq);
464 else 447 else
465 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); 448 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
466} 449}
diff --git a/drivers/iommu/msm_iommu_dev.c b/drivers/iommu/msm_iommu_dev.c
index 8e8fb079852d..9144a6beed92 100644
--- a/drivers/iommu/msm_iommu_dev.c
+++ b/drivers/iommu/msm_iommu_dev.c
@@ -29,7 +29,6 @@
29 29
30#include <mach/iommu_hw-8xxx.h> 30#include <mach/iommu_hw-8xxx.h>
31#include <mach/iommu.h> 31#include <mach/iommu.h>
32#include <mach/clk.h>
33 32
34struct iommu_ctx_iter_data { 33struct iommu_ctx_iter_data {
35 /* input */ 34 /* input */
@@ -160,7 +159,7 @@ static int msm_iommu_probe(struct platform_device *pdev)
160 goto fail; 159 goto fail;
161 } 160 }
162 161
163 ret = clk_enable(iommu_pclk); 162 ret = clk_prepare_enable(iommu_pclk);
164 if (ret) 163 if (ret)
165 goto fail_enable; 164 goto fail_enable;
166 165
@@ -168,9 +167,9 @@ static int msm_iommu_probe(struct platform_device *pdev)
168 167
169 if (!IS_ERR(iommu_clk)) { 168 if (!IS_ERR(iommu_clk)) {
170 if (clk_get_rate(iommu_clk) == 0) 169 if (clk_get_rate(iommu_clk) == 0)
171 clk_set_min_rate(iommu_clk, 1); 170 clk_set_rate(iommu_clk, 1);
172 171
173 ret = clk_enable(iommu_clk); 172 ret = clk_prepare_enable(iommu_clk);
174 if (ret) { 173 if (ret) {
175 clk_put(iommu_clk); 174 clk_put(iommu_clk);
176 goto fail_pclk; 175 goto fail_pclk;
@@ -261,7 +260,7 @@ fail_clk:
261 clk_put(iommu_clk); 260 clk_put(iommu_clk);
262 } 261 }
263fail_pclk: 262fail_pclk:
264 clk_disable(iommu_pclk); 263 clk_disable_unprepare(iommu_pclk);
265fail_enable: 264fail_enable:
266 clk_put(iommu_pclk); 265 clk_put(iommu_pclk);
267fail: 266fail:
@@ -275,8 +274,11 @@ static int msm_iommu_remove(struct platform_device *pdev)
275 274
276 drv = platform_get_drvdata(pdev); 275 drv = platform_get_drvdata(pdev);
277 if (drv) { 276 if (drv) {
278 if (drv->clk) 277 if (drv->clk) {
278 clk_unprepare(drv->clk);
279 clk_put(drv->clk); 279 clk_put(drv->clk);
280 }
281 clk_unprepare(drv->pclk);
280 clk_put(drv->pclk); 282 clk_put(drv->pclk);
281 memset(drv, 0, sizeof(*drv)); 283 memset(drv, 0, sizeof(*drv));
282 kfree(drv); 284 kfree(drv);
@@ -314,14 +316,14 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev)
314 INIT_LIST_HEAD(&ctx_drvdata->attached_elm); 316 INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
315 platform_set_drvdata(pdev, ctx_drvdata); 317 platform_set_drvdata(pdev, ctx_drvdata);
316 318
317 ret = clk_enable(drvdata->pclk); 319 ret = clk_prepare_enable(drvdata->pclk);
318 if (ret) 320 if (ret)
319 goto fail; 321 goto fail;
320 322
321 if (drvdata->clk) { 323 if (drvdata->clk) {
322 ret = clk_enable(drvdata->clk); 324 ret = clk_prepare_enable(drvdata->clk);
323 if (ret) { 325 if (ret) {
324 clk_disable(drvdata->pclk); 326 clk_disable_unprepare(drvdata->pclk);
325 goto fail; 327 goto fail;
326 } 328 }
327 } 329 }
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 0ee4a57fe6b2..b900de4e7e94 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -1268,10 +1268,18 @@ msmsdcc_probe(struct platform_device *pdev)
1268 goto clk_put; 1268 goto clk_put;
1269 } 1269 }
1270 1270
1271 ret = clk_prepare(host->pclk);
1272 if (ret)
1273 goto clk_put;
1274
1275 ret = clk_prepare(host->clk);
1276 if (ret)
1277 goto clk_unprepare_p;
1278
1271 /* Enable clocks */ 1279 /* Enable clocks */
1272 ret = msmsdcc_enable_clocks(host); 1280 ret = msmsdcc_enable_clocks(host);
1273 if (ret) 1281 if (ret)
1274 goto clk_put; 1282 goto clk_unprepare;
1275 1283
1276 host->pclk_rate = clk_get_rate(host->pclk); 1284 host->pclk_rate = clk_get_rate(host->pclk);
1277 host->clk_rate = clk_get_rate(host->clk); 1285 host->clk_rate = clk_get_rate(host->clk);
@@ -1386,6 +1394,10 @@ msmsdcc_probe(struct platform_device *pdev)
1386 free_irq(host->stat_irq, host); 1394 free_irq(host->stat_irq, host);
1387 clk_disable: 1395 clk_disable:
1388 msmsdcc_disable_clocks(host, 0); 1396 msmsdcc_disable_clocks(host, 0);
1397 clk_unprepare:
1398 clk_unprepare(host->clk);
1399 clk_unprepare_p:
1400 clk_unprepare(host->pclk);
1389 clk_put: 1401 clk_put:
1390 clk_put(host->clk); 1402 clk_put(host->clk);
1391 pclk_put: 1403 pclk_put:
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 2d76f66a2e0b..5f58cf0e96e2 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -941,3 +941,121 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
941 .label = "exynos5250-gpio-ctrl3", 941 .label = "exynos5250-gpio-ctrl3",
942 }, 942 },
943}; 943};
944
945/* pin banks of exynos5420 pin-controller 0 */
946static struct samsung_pin_bank exynos5420_pin_banks0[] = {
947 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
948 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
949 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
950 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
951 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
952};
953
954/* pin banks of exynos5420 pin-controller 1 */
955static struct samsung_pin_bank exynos5420_pin_banks1[] = {
956 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
957 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
958 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
959 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
960 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
961 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
962 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
963 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
964 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
965 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
966 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
967 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
968 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
969};
970
971/* pin banks of exynos5420 pin-controller 2 */
972static struct samsung_pin_bank exynos5420_pin_banks2[] = {
973 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
974 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
975 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
976 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
977 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
978 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
979 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
980 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
981};
982
983/* pin banks of exynos5420 pin-controller 3 */
984static struct samsung_pin_bank exynos5420_pin_banks3[] = {
985 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
986 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
987 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
988 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
989 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
990 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
991 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
992 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
993 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
994};
995
996/* pin banks of exynos5420 pin-controller 4 */
997static struct samsung_pin_bank exynos5420_pin_banks4[] = {
998 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
999};
1000
1001/*
1002 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1003 * four gpio/pin-mux/pinconfig controllers.
1004 */
1005struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1006 {
1007 /* pin-controller instance 0 data */
1008 .pin_banks = exynos5420_pin_banks0,
1009 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
1010 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1011 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1012 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1013 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1014 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1015 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1016 .svc = EXYNOS_SVC_OFFSET,
1017 .eint_gpio_init = exynos_eint_gpio_init,
1018 .eint_wkup_init = exynos_eint_wkup_init,
1019 .label = "exynos5420-gpio-ctrl0",
1020 }, {
1021 /* pin-controller instance 1 data */
1022 .pin_banks = exynos5420_pin_banks1,
1023 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
1024 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1025 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1026 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1027 .svc = EXYNOS_SVC_OFFSET,
1028 .eint_gpio_init = exynos_eint_gpio_init,
1029 .label = "exynos5420-gpio-ctrl1",
1030 }, {
1031 /* pin-controller instance 2 data */
1032 .pin_banks = exynos5420_pin_banks2,
1033 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
1034 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1035 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1036 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1037 .svc = EXYNOS_SVC_OFFSET,
1038 .eint_gpio_init = exynos_eint_gpio_init,
1039 .label = "exynos5420-gpio-ctrl2",
1040 }, {
1041 /* pin-controller instance 3 data */
1042 .pin_banks = exynos5420_pin_banks3,
1043 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
1044 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1045 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1046 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1047 .svc = EXYNOS_SVC_OFFSET,
1048 .eint_gpio_init = exynos_eint_gpio_init,
1049 .label = "exynos5420-gpio-ctrl3",
1050 }, {
1051 /* pin-controller instance 4 data */
1052 .pin_banks = exynos5420_pin_banks4,
1053 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
1054 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1055 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1056 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1057 .svc = EXYNOS_SVC_OFFSET,
1058 .eint_gpio_init = exynos_eint_gpio_init,
1059 .label = "exynos5420-gpio-ctrl4",
1060 },
1061};
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index e67ff1b8042c..0a6c720b6655 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1113,6 +1113,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
1113 .data = (void *)exynos4x12_pin_ctrl }, 1113 .data = (void *)exynos4x12_pin_ctrl },
1114 { .compatible = "samsung,exynos5250-pinctrl", 1114 { .compatible = "samsung,exynos5250-pinctrl",
1115 .data = (void *)exynos5250_pin_ctrl }, 1115 .data = (void *)exynos5250_pin_ctrl },
1116 { .compatible = "samsung,exynos5420-pinctrl",
1117 .data = (void *)exynos5420_pin_ctrl },
1116#endif 1118#endif
1117#ifdef CONFIG_PINCTRL_S3C64XX 1119#ifdef CONFIG_PINCTRL_S3C64XX
1118 { .compatible = "samsung,s3c64xx-pinctrl", 1120 { .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 79fcc2076c00..11bb75ba81a9 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -254,6 +254,7 @@ struct samsung_pmx_func {
254extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; 254extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
255extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; 255extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
256extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; 256extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
257extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
257extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; 258extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
258extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; 259extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
259extern struct samsung_pin_ctrl s3c2416_pin_ctrl[]; 260extern struct samsung_pin_ctrl s3c2416_pin_ctrl[];
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index b11e99797fd8..2c6cfb3cf032 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -408,9 +408,9 @@ static void msm_init_clock(struct uart_port *port)
408{ 408{
409 struct msm_port *msm_port = UART_TO_MSM(port); 409 struct msm_port *msm_port = UART_TO_MSM(port);
410 410
411 clk_enable(msm_port->clk); 411 clk_prepare_enable(msm_port->clk);
412 if (!IS_ERR(msm_port->pclk)) 412 if (!IS_ERR(msm_port->pclk))
413 clk_enable(msm_port->pclk); 413 clk_prepare_enable(msm_port->pclk);
414 msm_serial_set_mnd_regs(port); 414 msm_serial_set_mnd_regs(port);
415} 415}
416 416
@@ -486,7 +486,7 @@ static void msm_shutdown(struct uart_port *port)
486 msm_port->imr = 0; 486 msm_port->imr = 0;
487 msm_write(port, 0, UART_IMR); /* disable interrupts */ 487 msm_write(port, 0, UART_IMR); /* disable interrupts */
488 488
489 clk_disable(msm_port->clk); 489 clk_disable_unprepare(msm_port->clk);
490 490
491 free_irq(port->irq, port); 491 free_irq(port->irq, port);
492} 492}
@@ -688,14 +688,14 @@ static void msm_power(struct uart_port *port, unsigned int state,
688 688
689 switch (state) { 689 switch (state) {
690 case 0: 690 case 0:
691 clk_enable(msm_port->clk); 691 clk_prepare_enable(msm_port->clk);
692 if (!IS_ERR(msm_port->pclk)) 692 if (!IS_ERR(msm_port->pclk))
693 clk_enable(msm_port->pclk); 693 clk_prepare_enable(msm_port->pclk);
694 break; 694 break;
695 case 3: 695 case 3:
696 clk_disable(msm_port->clk); 696 clk_disable_unprepare(msm_port->clk);
697 if (!IS_ERR(msm_port->pclk)) 697 if (!IS_ERR(msm_port->pclk))
698 clk_disable(msm_port->pclk); 698 clk_disable_unprepare(msm_port->pclk);
699 break; 699 break;
700 default: 700 default:
701 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state); 701 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
@@ -884,19 +884,22 @@ static int __init msm_serial_probe(struct platform_device *pdev)
884 msm_port->is_uartdm = 0; 884 msm_port->is_uartdm = 0;
885 885
886 if (msm_port->is_uartdm) { 886 if (msm_port->is_uartdm) {
887 msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk"); 887 msm_port->clk = devm_clk_get(&pdev->dev, "gsbi_uart_clk");
888 msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk"); 888 msm_port->pclk = devm_clk_get(&pdev->dev, "gsbi_pclk");
889 } else { 889 } else {
890 msm_port->clk = clk_get(&pdev->dev, "uart_clk"); 890 msm_port->clk = devm_clk_get(&pdev->dev, "uart_clk");
891 msm_port->pclk = ERR_PTR(-ENOENT); 891 msm_port->pclk = ERR_PTR(-ENOENT);
892 } 892 }
893 893
894 if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) && 894 if (IS_ERR(msm_port->clk))
895 msm_port->is_uartdm))) 895 return PTR_ERR(msm_port->clk);
896 return PTR_ERR(msm_port->clk); 896
897 if (msm_port->is_uartdm) {
898 if (IS_ERR(msm_port->pclk))
899 return PTR_ERR(msm_port->pclk);
897 900
898 if (msm_port->is_uartdm)
899 clk_set_rate(msm_port->clk, 1843200); 901 clk_set_rate(msm_port->clk, 1843200);
902 }
900 903
901 port->uartclk = clk_get_rate(msm_port->clk); 904 port->uartclk = clk_get_rate(msm_port->clk);
902 printk(KERN_INFO "uartclk = %d\n", port->uartclk); 905 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
@@ -919,9 +922,9 @@ static int __init msm_serial_probe(struct platform_device *pdev)
919 922
920static int msm_serial_remove(struct platform_device *pdev) 923static int msm_serial_remove(struct platform_device *pdev)
921{ 924{
922 struct msm_port *msm_port = platform_get_drvdata(pdev); 925 struct uart_port *port = platform_get_drvdata(pdev);
923 926
924 clk_put(msm_port->clk); 927 uart_remove_one_port(&msm_uart_driver, port);
925 928
926 return 0; 929 return 0;
927} 930}
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 81ebc86a9e23..376079b9bd75 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1713,9 +1713,7 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1713#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL 1713#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1714#endif 1714#endif
1715 1715
1716#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \ 1716#if defined(CONFIG_ARCH_EXYNOS)
1717 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1718 defined(CONFIG_SOC_EXYNOS5440)
1719static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 1717static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1720 .info = &(struct s3c24xx_uart_info) { 1718 .info = &(struct s3c24xx_uart_info) {
1721 .name = "Samsung Exynos4 UART", 1719 .name = "Samsung Exynos4 UART",
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 156418619949..7477e0ea5cdb 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -146,6 +146,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
146 [SCRFDR] = sci_reg_invalid, 146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid, 147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid, 148 [SCLSR] = sci_reg_invalid,
149 [HSSRR] = sci_reg_invalid,
149 }, 150 },
150 151
151 /* 152 /*
@@ -165,6 +166,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
165 [SCRFDR] = sci_reg_invalid, 166 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid, 167 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid, 168 [SCLSR] = sci_reg_invalid,
169 [HSSRR] = sci_reg_invalid,
168 }, 170 },
169 171
170 /* 172 /*
@@ -183,6 +185,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
183 [SCRFDR] = sci_reg_invalid, 185 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid, 186 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid, 187 [SCLSR] = sci_reg_invalid,
188 [HSSRR] = sci_reg_invalid,
186 }, 189 },
187 190
188 /* 191 /*
@@ -201,6 +204,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
201 [SCRFDR] = { 0x3c, 16 }, 204 [SCRFDR] = { 0x3c, 16 },
202 [SCSPTR] = sci_reg_invalid, 205 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid, 206 [SCLSR] = sci_reg_invalid,
207 [HSSRR] = sci_reg_invalid,
204 }, 208 },
205 209
206 /* 210 /*
@@ -220,6 +224,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
220 [SCRFDR] = sci_reg_invalid, 224 [SCRFDR] = sci_reg_invalid,
221 [SCSPTR] = { 0x20, 16 }, 225 [SCSPTR] = { 0x20, 16 },
222 [SCLSR] = { 0x24, 16 }, 226 [SCLSR] = { 0x24, 16 },
227 [HSSRR] = sci_reg_invalid,
223 }, 228 },
224 229
225 /* 230 /*
@@ -238,6 +243,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
238 [SCRFDR] = sci_reg_invalid, 243 [SCRFDR] = sci_reg_invalid,
239 [SCSPTR] = sci_reg_invalid, 244 [SCSPTR] = sci_reg_invalid,
240 [SCLSR] = sci_reg_invalid, 245 [SCLSR] = sci_reg_invalid,
246 [HSSRR] = sci_reg_invalid,
241 }, 247 },
242 248
243 /* 249 /*
@@ -256,6 +262,26 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
256 [SCRFDR] = sci_reg_invalid, 262 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = { 0x20, 16 }, 263 [SCSPTR] = { 0x20, 16 },
258 [SCLSR] = { 0x24, 16 }, 264 [SCLSR] = { 0x24, 16 },
265 [HSSRR] = sci_reg_invalid,
266 },
267
268 /*
269 * Common HSCIF definitions.
270 */
271 [SCIx_HSCIF_REGTYPE] = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCTFDR] = sci_reg_invalid,
281 [SCRFDR] = sci_reg_invalid,
282 [SCSPTR] = { 0x20, 16 },
283 [SCLSR] = { 0x24, 16 },
284 [HSSRR] = { 0x40, 16 },
259 }, 285 },
260 286
261 /* 287 /*
@@ -275,6 +301,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
275 [SCRFDR] = sci_reg_invalid, 301 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid, 302 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = { 0x24, 16 }, 303 [SCLSR] = { 0x24, 16 },
304 [HSSRR] = sci_reg_invalid,
278 }, 305 },
279 306
280 /* 307 /*
@@ -294,6 +321,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
294 [SCRFDR] = { 0x20, 16 }, 321 [SCRFDR] = { 0x20, 16 },
295 [SCSPTR] = { 0x24, 16 }, 322 [SCSPTR] = { 0x24, 16 },
296 [SCLSR] = { 0x28, 16 }, 323 [SCLSR] = { 0x28, 16 },
324 [HSSRR] = sci_reg_invalid,
297 }, 325 },
298 326
299 /* 327 /*
@@ -313,6 +341,7 @@ static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
313 [SCRFDR] = sci_reg_invalid, 341 [SCRFDR] = sci_reg_invalid,
314 [SCSPTR] = sci_reg_invalid, 342 [SCSPTR] = sci_reg_invalid,
315 [SCLSR] = sci_reg_invalid, 343 [SCLSR] = sci_reg_invalid,
344 [HSSRR] = sci_reg_invalid,
316 }, 345 },
317}; 346};
318 347
@@ -374,6 +403,9 @@ static int sci_probe_regmap(struct plat_sci_port *cfg)
374 */ 403 */
375 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 404 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
376 break; 405 break;
406 case PORT_HSCIF:
407 cfg->regtype = SCIx_HSCIF_REGTYPE;
408 break;
377 default: 409 default:
378 printk(KERN_ERR "Can't probe register map for given port\n"); 410 printk(KERN_ERR "Can't probe register map for given port\n");
379 return -EINVAL; 411 return -EINVAL;
@@ -1798,6 +1830,42 @@ static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1798 return ((freq + 16 * bps) / (32 * bps) - 1); 1830 return ((freq + 16 * bps) / (32 * bps) - 1);
1799} 1831}
1800 1832
1833/* calculate sample rate, BRR, and clock select for HSCIF */
1834static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1835 int *brr, unsigned int *srr,
1836 unsigned int *cks)
1837{
1838 int sr, c, br, err;
1839 int min_err = 1000; /* 100% */
1840
1841 /* Find the combination of sample rate and clock select with the
1842 smallest deviation from the desired baud rate. */
1843 for (sr = 8; sr <= 32; sr++) {
1844 for (c = 0; c <= 3; c++) {
1845 /* integerized formulas from HSCIF documentation */
1846 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1847 if (br < 0 || br > 255)
1848 continue;
1849 err = freq / ((br + 1) * bps * sr *
1850 (1 << (2 * c + 1)) / 1000) - 1000;
1851 if (min_err > err) {
1852 min_err = err;
1853 *brr = br;
1854 *srr = sr - 1;
1855 *cks = c;
1856 }
1857 }
1858 }
1859
1860 if (min_err == 1000) {
1861 WARN_ON(1);
1862 /* use defaults */
1863 *brr = 255;
1864 *srr = 15;
1865 *cks = 0;
1866 }
1867}
1868
1801static void sci_reset(struct uart_port *port) 1869static void sci_reset(struct uart_port *port)
1802{ 1870{
1803 struct plat_sci_reg *reg; 1871 struct plat_sci_reg *reg;
@@ -1819,8 +1887,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1819{ 1887{
1820 struct sci_port *s = to_sci_port(port); 1888 struct sci_port *s = to_sci_port(port);
1821 struct plat_sci_reg *reg; 1889 struct plat_sci_reg *reg;
1822 unsigned int baud, smr_val, max_baud, cks; 1890 unsigned int baud, smr_val, max_baud, cks = 0;
1823 int t = -1; 1891 int t = -1;
1892 unsigned int srr = 15;
1824 1893
1825 /* 1894 /*
1826 * earlyprintk comes here early on with port->uartclk set to zero. 1895 * earlyprintk comes here early on with port->uartclk set to zero.
@@ -1833,8 +1902,17 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1833 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1902 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1834 1903
1835 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1904 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1836 if (likely(baud && port->uartclk)) 1905 if (likely(baud && port->uartclk)) {
1837 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1906 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
1907 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1908 &cks);
1909 } else {
1910 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
1911 port->uartclk);
1912 for (cks = 0; t >= 256 && cks <= 3; cks++)
1913 t >>= 2;
1914 }
1915 }
1838 1916
1839 sci_port_enable(s); 1917 sci_port_enable(s);
1840 1918
@@ -1853,15 +1931,15 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1853 1931
1854 uart_update_timeout(port, termios->c_cflag, baud); 1932 uart_update_timeout(port, termios->c_cflag, baud);
1855 1933
1856 for (cks = 0; t >= 256 && cks <= 3; cks++)
1857 t >>= 2;
1858
1859 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n", 1934 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1860 __func__, smr_val, cks, t, s->cfg->scscr); 1935 __func__, smr_val, cks, t, s->cfg->scscr);
1861 1936
1862 if (t >= 0) { 1937 if (t >= 0) {
1863 serial_port_out(port, SCSMR, (smr_val & ~3) | cks); 1938 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
1864 serial_port_out(port, SCBRR, t); 1939 serial_port_out(port, SCBRR, t);
1940 reg = sci_getreg(port, HSSRR);
1941 if (reg->size)
1942 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1865 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1943 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1866 } else 1944 } else
1867 serial_port_out(port, SCSMR, smr_val); 1945 serial_port_out(port, SCSMR, smr_val);
@@ -1947,6 +2025,8 @@ static const char *sci_type(struct uart_port *port)
1947 return "scifa"; 2025 return "scifa";
1948 case PORT_SCIFB: 2026 case PORT_SCIFB:
1949 return "scifb"; 2027 return "scifb";
2028 case PORT_HSCIF:
2029 return "hscif";
1950 } 2030 }
1951 2031
1952 return NULL; 2032 return NULL;
@@ -1960,7 +2040,10 @@ static inline unsigned long sci_port_size(struct uart_port *port)
1960 * from platform resource data at such a time that ports begin to 2040 * from platform resource data at such a time that ports begin to
1961 * behave more erratically. 2041 * behave more erratically.
1962 */ 2042 */
1963 return 64; 2043 if (port->type == PORT_HSCIF)
2044 return 96;
2045 else
2046 return 64;
1964} 2047}
1965 2048
1966static int sci_remap_port(struct uart_port *port) 2049static int sci_remap_port(struct uart_port *port)
@@ -2085,6 +2168,9 @@ static int sci_init_single(struct platform_device *dev,
2085 case PORT_SCIFB: 2168 case PORT_SCIFB:
2086 port->fifosize = 256; 2169 port->fifosize = 256;
2087 break; 2170 break;
2171 case PORT_HSCIF:
2172 port->fifosize = 128;
2173 break;
2088 case PORT_SCIFA: 2174 case PORT_SCIFA:
2089 port->fifosize = 64; 2175 port->fifosize = 64;
2090 break; 2176 break;
@@ -2325,7 +2411,7 @@ static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2325#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2411#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2326 2412
2327static char banner[] __initdata = 2413static char banner[] __initdata =
2328 KERN_INFO "SuperH SCI(F) driver initialized\n"; 2414 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
2329 2415
2330static struct uart_driver sci_uart_driver = { 2416static struct uart_driver sci_uart_driver = {
2331 .owner = THIS_MODULE, 2417 .owner = THIS_MODULE,
@@ -2484,4 +2570,4 @@ module_exit(sci_exit);
2484MODULE_LICENSE("GPL"); 2570MODULE_LICENSE("GPL");
2485MODULE_ALIAS("platform:sh-sci"); 2571MODULE_ALIAS("platform:sh-sci");
2486MODULE_AUTHOR("Paul Mundt"); 2572MODULE_AUTHOR("Paul Mundt");
2487MODULE_DESCRIPTION("SuperH SCI(F) serial driver"); 2573MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 749fbf41fb6f..d08f33435e96 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -514,13 +514,13 @@ static int msm_otg_suspend(struct msm_otg *motg)
514 motg->pdata->otg_control == OTG_PMIC_CONTROL) 514 motg->pdata->otg_control == OTG_PMIC_CONTROL)
515 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL); 515 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
516 516
517 clk_disable(motg->pclk); 517 clk_disable_unprepare(motg->pclk);
518 clk_disable(motg->clk); 518 clk_disable_unprepare(motg->clk);
519 if (motg->core_clk) 519 if (motg->core_clk)
520 clk_disable(motg->core_clk); 520 clk_disable_unprepare(motg->core_clk);
521 521
522 if (!IS_ERR(motg->pclk_src)) 522 if (!IS_ERR(motg->pclk_src))
523 clk_disable(motg->pclk_src); 523 clk_disable_unprepare(motg->pclk_src);
524 524
525 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && 525 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
526 motg->pdata->otg_control == OTG_PMIC_CONTROL) { 526 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
@@ -552,12 +552,12 @@ static int msm_otg_resume(struct msm_otg *motg)
552 return 0; 552 return 0;
553 553
554 if (!IS_ERR(motg->pclk_src)) 554 if (!IS_ERR(motg->pclk_src))
555 clk_enable(motg->pclk_src); 555 clk_prepare_enable(motg->pclk_src);
556 556
557 clk_enable(motg->pclk); 557 clk_prepare_enable(motg->pclk);
558 clk_enable(motg->clk); 558 clk_prepare_enable(motg->clk);
559 if (motg->core_clk) 559 if (motg->core_clk)
560 clk_enable(motg->core_clk); 560 clk_prepare_enable(motg->core_clk);
561 561
562 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && 562 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
563 motg->pdata->otg_control == OTG_PMIC_CONTROL) { 563 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
@@ -1468,7 +1468,7 @@ static int __init msm_otg_probe(struct platform_device *pdev)
1468 if (IS_ERR(motg->pclk_src)) 1468 if (IS_ERR(motg->pclk_src))
1469 goto put_clk; 1469 goto put_clk;
1470 clk_set_rate(motg->pclk_src, INT_MAX); 1470 clk_set_rate(motg->pclk_src, INT_MAX);
1471 clk_enable(motg->pclk_src); 1471 clk_prepare_enable(motg->pclk_src);
1472 } else 1472 } else
1473 motg->pclk_src = ERR_PTR(-ENOENT); 1473 motg->pclk_src = ERR_PTR(-ENOENT);
1474 1474
@@ -1511,8 +1511,8 @@ static int __init msm_otg_probe(struct platform_device *pdev)
1511 goto free_regs; 1511 goto free_regs;
1512 } 1512 }
1513 1513
1514 clk_enable(motg->clk); 1514 clk_prepare_enable(motg->clk);
1515 clk_enable(motg->pclk); 1515 clk_prepare_enable(motg->pclk);
1516 1516
1517 ret = msm_hsusb_init_vddcx(motg, 1); 1517 ret = msm_hsusb_init_vddcx(motg, 1);
1518 if (ret) { 1518 if (ret) {
@@ -1532,7 +1532,7 @@ static int __init msm_otg_probe(struct platform_device *pdev)
1532 } 1532 }
1533 1533
1534 if (motg->core_clk) 1534 if (motg->core_clk)
1535 clk_enable(motg->core_clk); 1535 clk_prepare_enable(motg->core_clk);
1536 1536
1537 writel(0, USB_USBINTR); 1537 writel(0, USB_USBINTR);
1538 writel(0, USB_OTGSC); 1538 writel(0, USB_OTGSC);
@@ -1579,8 +1579,8 @@ static int __init msm_otg_probe(struct platform_device *pdev)
1579free_irq: 1579free_irq:
1580 free_irq(motg->irq, motg); 1580 free_irq(motg->irq, motg);
1581disable_clks: 1581disable_clks:
1582 clk_disable(motg->pclk); 1582 clk_disable_unprepare(motg->pclk);
1583 clk_disable(motg->clk); 1583 clk_disable_unprepare(motg->clk);
1584ldo_exit: 1584ldo_exit:
1585 msm_hsusb_ldo_init(motg, 0); 1585 msm_hsusb_ldo_init(motg, 0);
1586vddcx_exit: 1586vddcx_exit:
@@ -1593,7 +1593,7 @@ put_core_clk:
1593 clk_put(motg->pclk); 1593 clk_put(motg->pclk);
1594put_pclk_src: 1594put_pclk_src:
1595 if (!IS_ERR(motg->pclk_src)) { 1595 if (!IS_ERR(motg->pclk_src)) {
1596 clk_disable(motg->pclk_src); 1596 clk_disable_unprepare(motg->pclk_src);
1597 clk_put(motg->pclk_src); 1597 clk_put(motg->pclk_src);
1598 } 1598 }
1599put_clk: 1599put_clk:
@@ -1643,12 +1643,12 @@ static int msm_otg_remove(struct platform_device *pdev)
1643 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) 1643 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1644 dev_err(phy->dev, "Unable to suspend PHY\n"); 1644 dev_err(phy->dev, "Unable to suspend PHY\n");
1645 1645
1646 clk_disable(motg->pclk); 1646 clk_disable_unprepare(motg->pclk);
1647 clk_disable(motg->clk); 1647 clk_disable_unprepare(motg->clk);
1648 if (motg->core_clk) 1648 if (motg->core_clk)
1649 clk_disable(motg->core_clk); 1649 clk_disable_unprepare(motg->core_clk);
1650 if (!IS_ERR(motg->pclk_src)) { 1650 if (!IS_ERR(motg->pclk_src)) {
1651 clk_disable(motg->pclk_src); 1651 clk_disable_unprepare(motg->pclk_src);
1652 clk_put(motg->pclk_src); 1652 clk_put(motg->pclk_src);
1653 } 1653 }
1654 msm_hsusb_ldo_init(motg, 0); 1654 msm_hsusb_ldo_init(motg, 0);
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index eb763adf9815..d34049712a4d 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -5,7 +5,7 @@
5#include <linux/sh_dma.h> 5#include <linux/sh_dma.h>
6 6
7/* 7/*
8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) 8 * Generic header for SuperH (H)SCI(F) (used by sh/sh64/h8300 and related parts)
9 */ 9 */
10 10
11#define SCIx_NOT_SUPPORTED (-1) 11#define SCIx_NOT_SUPPORTED (-1)
@@ -16,6 +16,7 @@ enum {
16 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */ 16 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
17 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */ 17 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
18 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */ 18 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
19 SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
19}; 20};
20 21
21#define SCSCR_TIE (1 << 7) 22#define SCSCR_TIE (1 << 7)
@@ -37,7 +38,7 @@ enum {
37 38
38#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) 39#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
39 40
40/* SCxSR SCIF */ 41/* SCxSR SCIF, HSCIF */
41#define SCIF_ER 0x0080 42#define SCIF_ER 0x0080
42#define SCIF_TEND 0x0040 43#define SCIF_TEND 0x0040
43#define SCIF_TDFE 0x0020 44#define SCIF_TDFE 0x0020
@@ -55,6 +56,9 @@ enum {
55#define SCSPTR_SPB2IO (1 << 1) 56#define SCSPTR_SPB2IO (1 << 1)
56#define SCSPTR_SPB2DT (1 << 0) 57#define SCSPTR_SPB2DT (1 << 0)
57 58
59/* HSSRR HSCIF */
60#define HSCIF_SRE 0x8000
61
58/* Offsets into the sci_port->irqs array */ 62/* Offsets into the sci_port->irqs array */
59enum { 63enum {
60 SCIx_ERI_IRQ, 64 SCIx_ERI_IRQ,
@@ -90,6 +94,7 @@ enum {
90 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 94 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
91 SCIx_SH4_SCIF_FIFODATA_REGTYPE, 95 SCIx_SH4_SCIF_FIFODATA_REGTYPE,
92 SCIx_SH7705_SCIF_REGTYPE, 96 SCIx_SH7705_SCIF_REGTYPE,
97 SCIx_HSCIF_REGTYPE,
93 98
94 SCIx_NR_REGTYPES, 99 SCIx_NR_REGTYPES,
95}; 100};
@@ -115,6 +120,7 @@ enum {
115 SCSMR, SCBRR, SCSCR, SCxSR, 120 SCSMR, SCBRR, SCSCR, SCxSR,
116 SCFCR, SCFDR, SCxTDR, SCxRDR, 121 SCFCR, SCFDR, SCxTDR, SCxRDR,
117 SCLSR, SCTFDR, SCRFDR, SCSPTR, 122 SCLSR, SCTFDR, SCRFDR, SCSPTR,
123 HSSRR,
118 124
119 SCIx_NR_REGS, 125 SCIx_NR_REGS,
120}; 126};
@@ -137,7 +143,7 @@ struct plat_sci_port {
137 unsigned long mapbase; /* resource base */ 143 unsigned long mapbase; /* resource base */
138 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */ 144 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
139 unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */ 145 unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */
140 unsigned int type; /* SCI / SCIF / IRDA */ 146 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
141 upf_t flags; /* UPF_* flags */ 147 upf_t flags; /* UPF_* flags */
142 unsigned long capabilities; /* Port features/capabilities */ 148 unsigned long capabilities; /* Port features/capabilities */
143 149
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index c8eaeb5465ef..9119cc0977bf 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -229,4 +229,7 @@
229/* Freescale lpuart */ 229/* Freescale lpuart */
230#define PORT_LPUART 103 230#define PORT_LPUART 103
231 231
232/* SH-SCI */
233#define PORT_HSCIF 104
234
232#endif /* _UAPILINUX_SERIAL_CORE_H */ 235#endif /* _UAPILINUX_SERIAL_CORE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 20:36:43 -0500