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authorOlof Johansson <olof@lixom.net>2013-04-18 02:26:57 -0400
committerOlof Johansson <olof@lixom.net>2013-04-18 02:27:52 -0400
commitdb39ad7d418b3b64f92295c3d9d7d8595ff68f08 (patch)
tree5357280b5edf0a5ddac4da422447f00bcf5c5190 /arch/arm/boot/dts
parentbf049ded36b2178e80bb9f227d4490714d838c11 (diff)
parent74898364e717c6bd939bb88d95049fc91d2b4950 (diff)
Merge tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux into next/dt2
From Jason Cooper: mvebu dt for v3.10 round 4 - mvebu LPAE 64bit dts file changes * tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux: (52 commits) ARM: dts: mvebu: Convert mvebu device tree files to 64 bits ARM: dts: mvebu: introduce internal-regs node ARM: dts: mvebu: Convert all the mvebu files to use the range property ARM: dts: mvebu: move all peripherals inside soc ARM: dts: mvebu: fix cpus section indentation arm: mvebu: PCIe Device Tree informations for Armada XP GP arm: mvebu: PCIe Device Tree informations for Armada 370 DB arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox arm: mvebu: PCIe Device Tree informations for Armada XP DB arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 arm: mvebu: add PCIe Device Tree informations for Armada XP arm: mvebu: add PCIe Device Tree informations for Armada 370 ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts123
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts142
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts85
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi296
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi278
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts187
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts184
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi194
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi238
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi332
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts232
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi196
-rw-r--r--arch/arm/boot/dts/dove.dtsi5
-rw-r--r--arch/arm/boot/dts/kirkwood-6282.dtsi6
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts1
-rw-r--r--arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts14
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi42
-rw-r--r--arch/arm/boot/dts/skeleton64.dtsi13
19 files changed, 1702 insertions, 870 deletions
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e34b280ce6ec..2353b1f13704 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,68 +30,87 @@
30 }; 30 };
31 31
32 soc { 32 soc {
33 serial@d0012000 { 33 internal-regs {
34 clock-frequency = <200000000>; 34 serial@12000 {
35 status = "okay"; 35 clock-frequency = <200000000>;
36 }; 36 status = "okay";
37 sata@d00a0000 { 37 };
38 nr-ports = <2>; 38 sata@a0000 {
39 status = "okay"; 39 nr-ports = <2>;
40 }; 40 status = "okay";
41 };
41 42
42 mdio { 43 mdio {
43 phy0: ethernet-phy@0 { 44 phy0: ethernet-phy@0 {
44 reg = <0>; 45 reg = <0>;
46 };
47
48 phy1: ethernet-phy@1 {
49 reg = <1>;
50 };
45 }; 51 };
46 52
47 phy1: ethernet-phy@1 { 53 ethernet@70000 {
48 reg = <1>; 54 status = "okay";
55 phy = <&phy0>;
56 phy-mode = "rgmii-id";
57 };
58 ethernet@74000 {
59 status = "okay";
60 phy = <&phy1>;
61 phy-mode = "rgmii-id";
49 }; 62 };
50 };
51 63
52 ethernet@d0070000 { 64 mvsdio@d4000 {
53 status = "okay"; 65 pinctrl-0 = <&sdio_pins1>;
54 phy = <&phy0>; 66 pinctrl-names = "default";
55 phy-mode = "rgmii-id"; 67 /*
56 }; 68 * This device is disabled by default, because
57 ethernet@d0074000 { 69 * using the SD card connector requires
58 status = "okay"; 70 * changing the default CON40 connector
59 phy = <&phy1>; 71 * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
60 phy-mode = "rgmii-id"; 72 * different connector
61 }; 73 * "DB-88F6710_MPP_RGMII_SD_Jumper".
74 */
75 status = "disabled";
76 /* No CD or WP GPIOs */
77 };
62 78
63 mvsdio@d00d4000 { 79 usb@50000 {
64 pinctrl-0 = <&sdio_pins1>; 80 status = "okay";
65 pinctrl-names = "default"; 81 };
66 /*
67 * This device is disabled by default, because
68 * using the SD card connector requires
69 * changing the default CON40 connector
70 * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
71 * different connector
72 * "DB-88F6710_MPP_RGMII_SD_Jumper".
73 */
74 status = "disabled";
75 /* No CD or WP GPIOs */
76 };
77 82
78 usb@d0050000 { 83 usb@51000 {
79 status = "okay"; 84 status = "okay";
80 }; 85 };
81 86
82 usb@d0051000 { 87 spi0: spi@10600 {
83 status = "okay"; 88 status = "okay";
84 };
85 89
86 spi0: spi@d0010600 { 90 spi-flash@0 {
87 status = "okay"; 91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "mx25l25635e";
94 reg = <0>; /* Chip select 0 */
95 spi-max-frequency = <50000000>;
96 };
97 };
88 98
89 spi-flash@0 { 99 pcie-controller {
90 #address-cells = <1>; 100 status = "okay";
91 #size-cells = <1>; 101 /*
92 compatible = "mx25l25635e"; 102 * The two PCIe units are accessible through
93 reg = <0>; /* Chip select 0 */ 103 * both standard PCIe slots and mini-PCIe
94 spi-max-frequency = <50000000>; 104 * slots on the board.
105 */
106 pcie@1,0 {
107 /* Port 0, Lane 0 */
108 status = "okay";
109 };
110 pcie@2,0 {
111 /* Port 1, Lane 0 */
112 status = "okay";
113 };
95 }; 114 };
96 }; 115 };
97 }; 116 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index dd0c57dd9f30..14e36e19d515 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,50 +25,116 @@
25 }; 25 };
26 26
27 soc { 27 soc {
28 serial@d0012000 { 28 internal-regs {
29 clock-frequency = <200000000>; 29 serial@12000 {
30 status = "okay"; 30 clock-frequency = <200000000>;
31 }; 31 status = "okay";
32 timer@d0020300 {
33 clock-frequency = <600000000>;
34 status = "okay";
35 };
36 mdio {
37 phy0: ethernet-phy@0 {
38 reg = <0>;
39 }; 32 };
33 timer@20300 {
34 clock-frequency = <600000000>;
35 status = "okay";
36 };
37
38 pinctrl {
39 pwr_led_pin: pwr-led-pin {
40 marvell,pins = "mpp63";
41 marvell,function = "gpo";
42 };
40 43
41 phy1: ethernet-phy@1 { 44 stat_led_pins: stat-led-pins {
42 reg = <1>; 45 marvell,pins = "mpp64", "mpp65";
46 marvell,function = "gpio";
47 };
43 }; 48 };
44 };
45 ethernet@d0070000 {
46 status = "okay";
47 phy = <&phy0>;
48 phy-mode = "rgmii-id";
49 };
50 ethernet@d0074000 {
51 status = "okay";
52 phy = <&phy1>;
53 phy-mode = "rgmii-id";
54 };
55 49
56 mvsdio@d00d4000 { 50 gpio_leds {
57 pinctrl-0 = <&sdio_pins2>; 51 compatible = "gpio-leds";
58 pinctrl-names = "default"; 52 pinctrl-names = "default";
59 status = "okay"; 53 pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
60 /*
61 * No CD or WP GPIOs: SDIO interface used for
62 * Wifi/Bluetooth chip
63 */
64 };
65 54
66 usb@d0050000 { 55 green_pwr_led {
67 status = "okay"; 56 label = "mirabox:green:pwr";
68 }; 57 gpios = <&gpio1 31 1>;
58 linux,default-trigger = "heartbeat";
59 };
60
61 blue_stat_led {
62 label = "mirabox:blue:stat";
63 gpios = <&gpio2 0 1>;
64 linux,default-trigger = "cpu0";
65 };
66
67 green_stat_led {
68 label = "mirabox:green:stat";
69 gpios = <&gpio2 1 1>;
70 default-state = "off";
71 };
72 };
73
74 mdio {
75 phy0: ethernet-phy@0 {
76 reg = <0>;
77 };
78
79 phy1: ethernet-phy@1 {
80 reg = <1>;
81 };
82 };
83 ethernet@70000 {
84 status = "okay";
85 phy = <&phy0>;
86 phy-mode = "rgmii-id";
87 };
88 ethernet@74000 {
89 status = "okay";
90 phy = <&phy1>;
91 phy-mode = "rgmii-id";
92 };
93
94 mvsdio@d4000 {
95 pinctrl-0 = <&sdio_pins3>;
96 pinctrl-names = "default";
97 status = "okay";
98 /*
99 * No CD or WP GPIOs: SDIO interface used for
100 * Wifi/Bluetooth chip
101 */
102 };
103
104 usb@50000 {
105 status = "okay";
106 };
69 107
70 usb@d0051000 { 108 usb@51000 {
71 status = "okay"; 109 status = "okay";
110 };
111
112 i2c@11000 {
113 status = "okay";
114 clock-frequency = <100000>;
115 pca9505: pca9505@25 {
116 compatible = "nxp,pca9505";
117 gpio-controller;
118 #gpio-cells = <2>;
119 reg = <0x25>;
120 };
121 };
122
123 pcie-controller {
124 status = "okay";
125
126 /* Internal mini-PCIe connector */
127 pcie@1,0 {
128 /* Port 0, Lane 0 */
129 status = "okay";
130 };
131
132 /* Connected on the PCB to a USB 3.0 XHCI controller */
133 pcie@2,0 {
134 /* Port 1, Lane 0 */
135 status = "okay";
136 };
137 };
72 }; 138 };
73 }; 139 };
74}; 140};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 070bba4f2585..130f8390a7e4 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,49 +28,62 @@
28 }; 28 };
29 29
30 soc { 30 soc {
31 serial@d0012000 { 31 internal-regs {
32 clock-frequency = <200000000>; 32 serial@12000 {
33 status = "okay"; 33 clock-frequency = <200000000>;
34 }; 34 status = "okay";
35 sata@d00a0000 { 35 };
36 nr-ports = <2>; 36 sata@a0000 {
37 status = "okay"; 37 nr-ports = <2>;
38 }; 38 status = "okay";
39 };
39 40
40 mdio { 41 mdio {
41 phy0: ethernet-phy@0 { 42 phy0: ethernet-phy@0 {
42 reg = <0>; 43 reg = <0>;
44 };
45
46 phy1: ethernet-phy@1 {
47 reg = <1>;
48 };
43 }; 49 };
44 50
45 phy1: ethernet-phy@1 { 51 ethernet@70000 {
46 reg = <1>; 52 status = "okay";
53 phy = <&phy0>;
54 phy-mode = "sgmii";
55 };
56 ethernet@74000 {
57 status = "okay";
58 phy = <&phy1>;
59 phy-mode = "rgmii-id";
47 }; 60 };
48 };
49 61
50 ethernet@d0070000 { 62 mvsdio@d4000 {
51 status = "okay"; 63 pinctrl-0 = <&sdio_pins1>;
52 phy = <&phy0>; 64 pinctrl-names = "default";
53 phy-mode = "sgmii"; 65 status = "okay";
54 }; 66 /* No CD or WP GPIOs */
55 ethernet@d0074000 { 67 };
56 status = "okay";
57 phy = <&phy1>;
58 phy-mode = "rgmii-id";
59 };
60 68
61 mvsdio@d00d4000 { 69 usb@50000 {
62 pinctrl-0 = <&sdio_pins1>; 70 status = "okay";
63 pinctrl-names = "default"; 71 };
64 status = "okay";
65 /* No CD or WP GPIOs */
66 };
67 72
68 usb@d0050000 { 73 usb@51000 {
69 status = "okay"; 74 status = "okay";
70 }; 75 };
71 76
72 usb@d0051000 { 77 gpio-keys {
73 status = "okay"; 78 compatible = "gpio-keys";
79 #address-cells = <1>;
80 #size-cells = <0>;
81 button@1 {
82 label = "Software Button";
83 linux,code = <116>;
84 gpios = <&gpio0 6 1>;
85 };
86 };
74 }; 87 };
75 }; 88 };
76}; 89 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 5b708208b607..272bbc65fab0 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -16,7 +16,7 @@
16 * 370 and Armada XP SoC. 16 * 370 and Armada XP SoC.
17 */ 17 */
18 18
19/include/ "skeleton.dtsi" 19/include/ "skeleton64.dtsi"
20 20
21/ { 21/ {
22 model = "Marvell Armada 370 and XP SoC"; 22 model = "Marvell Armada 370 and XP SoC";
@@ -28,159 +28,203 @@
28 }; 28 };
29 }; 29 };
30 30
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
34 #size-cells = <1>;
35 interrupt-controller;
36 };
37
38 coherency-fabric@d0020200 {
39 compatible = "marvell,coherency-fabric";
40 reg = <0xd0020200 0xb0>,
41 <0xd0021810 0x1c>;
42 };
43
44 soc { 31 soc {
45 #address-cells = <1>; 32 #address-cells = <1>;
46 #size-cells = <1>; 33 #size-cells = <1>;
47 compatible = "simple-bus"; 34 compatible = "simple-bus";
48 interrupt-parent = <&mpic>; 35 interrupt-parent = <&mpic>;
49 ranges; 36 ranges = <0 0 0xd0000000 0x100000>;
50 37
51 serial@d0012000 { 38 internal-regs {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 ranges;
43
44 mpic: interrupt-controller@20000 {
45 compatible = "marvell,mpic";
46 #interrupt-cells = <1>;
47 #size-cells = <1>;
48 interrupt-controller;
49 };
50
51 coherency-fabric@20200 {
52 compatible = "marvell,coherency-fabric";
53 reg = <0x20200 0xb0>, <0x21810 0x1c>;
54 };
55
56 serial@12000 {
52 compatible = "snps,dw-apb-uart"; 57 compatible = "snps,dw-apb-uart";
53 reg = <0xd0012000 0x100>; 58 reg = <0x12000 0x100>;
54 reg-shift = <2>; 59 reg-shift = <2>;
55 interrupts = <41>; 60 interrupts = <41>;
56 reg-io-width = <1>; 61 reg-io-width = <1>;
57 status = "disabled"; 62 status = "disabled";
58 }; 63 };
59 serial@d0012100 { 64 serial@12100 {
60 compatible = "snps,dw-apb-uart"; 65 compatible = "snps,dw-apb-uart";
61 reg = <0xd0012100 0x100>; 66 reg = <0x12100 0x100>;
62 reg-shift = <2>; 67 reg-shift = <2>;
63 interrupts = <42>; 68 interrupts = <42>;
64 reg-io-width = <1>; 69 reg-io-width = <1>;
65 status = "disabled"; 70 status = "disabled";
66 }; 71 };
67 72
68 timer@d0020300 { 73 timer@20300 {
69 compatible = "marvell,armada-370-xp-timer"; 74 compatible = "marvell,armada-370-xp-timer";
70 reg = <0xd0020300 0x30>, 75 reg = <0x20300 0x30>, <0x21040 0x30>;
71 <0xd0021040 0x30>; 76 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
72 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 77 clocks = <&coreclk 2>;
73 clocks = <&coreclk 2>; 78 };
74 }; 79
75 80 sata@a0000 {
76 addr-decoding@d0020000 { 81 compatible = "marvell,orion-sata";
77 compatible = "marvell,armada-addr-decoding-controller"; 82 reg = <0xa0000 0x2400>;
78 reg = <0xd0020000 0x258>; 83 interrupts = <55>;
79 }; 84 clocks = <&gateclk 15>, <&gateclk 30>;
80 85 clock-names = "0", "1";
81 sata@d00a0000 { 86 status = "disabled";
82 compatible = "marvell,orion-sata"; 87 };
83 reg = <0xd00a0000 0x2400>;
84 interrupts = <55>;
85 clocks = <&gateclk 15>, <&gateclk 30>;
86 clock-names = "0", "1";
87 status = "disabled";
88 };
89 88
90 mdio { 89 mdio {
91 #address-cells = <1>; 90 #address-cells = <1>;
92 #size-cells = <0>; 91 #size-cells = <0>;
93 compatible = "marvell,orion-mdio"; 92 compatible = "marvell,orion-mdio";
94 reg = <0xd0072004 0x4>; 93 reg = <0x72004 0x4>;
95 }; 94 };
96 95
97 ethernet@d0070000 { 96 ethernet@70000 {
98 compatible = "marvell,armada-370-neta"; 97 compatible = "marvell,armada-370-neta";
99 reg = <0xd0070000 0x2500>; 98 reg = <0x70000 0x2500>;
100 interrupts = <8>; 99 interrupts = <8>;
101 clocks = <&gateclk 4>; 100 clocks = <&gateclk 4>;
102 status = "disabled"; 101 status = "disabled";
103 }; 102 };
104 103
105 ethernet@d0074000 { 104 ethernet@74000 {
106 compatible = "marvell,armada-370-neta"; 105 compatible = "marvell,armada-370-neta";
107 reg = <0xd0074000 0x2500>; 106 reg = <0x74000 0x2500>;
108 interrupts = <10>; 107 interrupts = <10>;
109 clocks = <&gateclk 3>; 108 clocks = <&gateclk 3>;
110 status = "disabled"; 109 status = "disabled";
111 }; 110 };
112 111
113 i2c0: i2c@d0011000 { 112 i2c0: i2c@11000 {
114 compatible = "marvell,mv64xxx-i2c"; 113 compatible = "marvell,mv64xxx-i2c";
115 reg = <0xd0011000 0x20>; 114 reg = <0x11000 0x20>;
116 #address-cells = <1>; 115 #address-cells = <1>;
117 #size-cells = <0>; 116 #size-cells = <0>;
118 interrupts = <31>; 117 interrupts = <31>;
119 timeout-ms = <1000>; 118 timeout-ms = <1000>;
120 clocks = <&coreclk 0>; 119 clocks = <&coreclk 0>;
121 status = "disabled"; 120 status = "disabled";
122 }; 121 };
123 122
124 i2c1: i2c@d0011100 { 123 i2c1: i2c@11100 {
125 compatible = "marvell,mv64xxx-i2c"; 124 compatible = "marvell,mv64xxx-i2c";
126 reg = <0xd0011100 0x20>; 125 reg = <0x11100 0x20>;
127 #address-cells = <1>; 126 #address-cells = <1>;
128 #size-cells = <0>; 127 #size-cells = <0>;
129 interrupts = <32>; 128 interrupts = <32>;
130 timeout-ms = <1000>; 129 timeout-ms = <1000>;
131 clocks = <&coreclk 0>; 130 clocks = <&coreclk 0>;
132 status = "disabled"; 131 status = "disabled";
133 }; 132 };
134 133
135 rtc@10300 { 134 rtc@10300 {
136 compatible = "marvell,orion-rtc"; 135 compatible = "marvell,orion-rtc";
137 reg = <0xd0010300 0x20>; 136 reg = <0x10300 0x20>;
138 interrupts = <50>; 137 interrupts = <50>;
139 }; 138 };
140 139
141 mvsdio@d00d4000 { 140 mvsdio@d4000 {
142 compatible = "marvell,orion-sdio"; 141 compatible = "marvell,orion-sdio";
143 reg = <0xd00d4000 0x200>; 142 reg = <0xd4000 0x200>;
144 interrupts = <54>; 143 interrupts = <54>;
145 clocks = <&gateclk 17>; 144 clocks = <&gateclk 17>;
146 status = "disabled"; 145 status = "disabled";
147 }; 146 };
148
149 usb@d0050000 {
150 compatible = "marvell,orion-ehci";
151 reg = <0xd0050000 0x500>;
152 interrupts = <45>;
153 status = "disabled";
154 };
155
156 usb@d0051000 {
157 compatible = "marvell,orion-ehci";
158 reg = <0xd0051000 0x500>;
159 interrupts = <46>;
160 status = "disabled";
161 };
162 147
163 spi0: spi@d0010600 { 148 usb@50000 {
164 compatible = "marvell,orion-spi"; 149 compatible = "marvell,orion-ehci";
165 reg = <0xd0010600 0x28>; 150 reg = <0x50000 0x500>;
166 #address-cells = <1>; 151 interrupts = <45>;
167 #size-cells = <0>; 152 status = "disabled";
168 cell-index = <0>; 153 };
169 interrupts = <30>;
170 clocks = <&coreclk 0>;
171 status = "disabled";
172 };
173 154
174 spi1: spi@d0010680 { 155 usb@51000 {
175 compatible = "marvell,orion-spi"; 156 compatible = "marvell,orion-ehci";
176 reg = <0xd0010680 0x28>; 157 reg = <0x51000 0x500>;
177 #address-cells = <1>; 158 interrupts = <46>;
178 #size-cells = <0>; 159 status = "disabled";
179 cell-index = <1>; 160 };
180 interrupts = <92>; 161
181 clocks = <&coreclk 0>; 162 spi0: spi@10600 {
182 status = "disabled"; 163 compatible = "marvell,orion-spi";
164 reg = <0x10600 0x28>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 cell-index = <0>;
168 interrupts = <30>;
169 clocks = <&coreclk 0>;
170 status = "disabled";
171 };
172
173 spi1: spi@10680 {
174 compatible = "marvell,orion-spi";
175 reg = <0x10680 0x28>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 cell-index = <1>;
179 interrupts = <92>;
180 clocks = <&coreclk 0>;
181 status = "disabled";
182 };
183
184 devbus-bootcs@10400 {
185 compatible = "marvell,mvebu-devbus";
186 reg = <0x10400 0x8>;
187 #address-cells = <1>;
188 #size-cells = <1>;
189 clocks = <&coreclk 0>;
190 status = "disabled";
191 };
192
193 devbus-cs0@10408 {
194 compatible = "marvell,mvebu-devbus";
195 reg = <0x10408 0x8>;
196 #address-cells = <1>;
197 #size-cells = <1>;
198 clocks = <&coreclk 0>;
199 status = "disabled";
200 };
201
202 devbus-cs1@10410 {
203 compatible = "marvell,mvebu-devbus";
204 reg = <0x10410 0x8>;
205 #address-cells = <1>;
206 #size-cells = <1>;
207 clocks = <&coreclk 0>;
208 status = "disabled";
209 };
210
211 devbus-cs2@10418 {
212 compatible = "marvell,mvebu-devbus";
213 reg = <0x10418 0x8>;
214 #address-cells = <1>;
215 #size-cells = <1>;
216 clocks = <&coreclk 0>;
217 status = "disabled";
218 };
219
220 devbus-cs3@10420 {
221 compatible = "marvell,mvebu-devbus";
222 reg = <0x10420 0x8>;
223 #address-cells = <1>;
224 #size-cells = <1>;
225 clocks = <&coreclk 0>;
226 status = "disabled";
227 };
183 }; 228 };
184 }; 229 };
185}; 230 };
186
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 8188d138020e..b2c1b5af9749 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -16,16 +16,11 @@
16 */ 16 */
17 17
18/include/ "armada-370-xp.dtsi" 18/include/ "armada-370-xp.dtsi"
19/include/ "skeleton.dtsi"
19 20
20/ { 21/ {
21 model = "Marvell Armada 370 family SoC"; 22 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp"; 23 compatible = "marvell,armada370", "marvell,armada-370-xp";
23 L2: l2-cache {
24 compatible = "marvell,aurora-outer-cache";
25 reg = <0xd0008000 0x1000>;
26 cache-id-part = <0x100>;
27 wt-override;
28 };
29 24
30 aliases { 25 aliases {
31 gpio0 = &gpio0; 26 gpio0 = &gpio0;
@@ -33,125 +28,198 @@
33 gpio2 = &gpio2; 28 gpio2 = &gpio2;
34 }; 29 };
35 30
36 mpic: interrupt-controller@d0020000 {
37 reg = <0xd0020a00 0x1d0>,
38 <0xd0021870 0x58>;
39 };
40
41 soc { 31 soc {
42 system-controller@d0018200 { 32 ranges = <0 0xd0000000 0x100000>;
33 internal-regs {
34 system-controller@18200 {
43 compatible = "marvell,armada-370-xp-system-controller"; 35 compatible = "marvell,armada-370-xp-system-controller";
44 reg = <0xd0018200 0x100>; 36 reg = <0x18200 0x100>;
45 }; 37 };
46
47 pinctrl {
48 compatible = "marvell,mv88f6710-pinctrl";
49 reg = <0xd0018000 0x38>;
50 38
51 sdio_pins1: sdio-pins1 { 39 L2: l2-cache {
52 marvell,pins = "mpp9", "mpp11", "mpp12", 40 compatible = "marvell,aurora-outer-cache";
53 "mpp13", "mpp14", "mpp15"; 41 reg = <0xd0008000 0x1000>;
54 marvell,function = "sd0"; 42 cache-id-part = <0x100>;
43 wt-override;
55 }; 44 };
56 45
57 sdio_pins2: sdio-pins2 { 46 mpic: interrupt-controller@20000 {
58 marvell,pins = "mpp47", "mpp48", "mpp49", 47 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
59 "mpp50", "mpp51", "mpp52";
60 marvell,function = "sd0";
61 }; 48 };
62 };
63
64 gpio0: gpio@d0018100 {
65 compatible = "marvell,orion-gpio";
66 reg = <0xd0018100 0x40>;
67 ngpios = <32>;
68 gpio-controller;
69 #gpio-cells = <2>;
70 interrupt-controller;
71 #interrupts-cells = <2>;
72 interrupts = <82>, <83>, <84>, <85>;
73 };
74 49
75 gpio1: gpio@d0018140 { 50 pinctrl {
76 compatible = "marvell,orion-gpio"; 51 compatible = "marvell,mv88f6710-pinctrl";
77 reg = <0xd0018140 0x40>; 52 reg = <0x18000 0x38>;
78 ngpios = <32>; 53
79 gpio-controller; 54 sdio_pins1: sdio-pins1 {
80 #gpio-cells = <2>; 55 marvell,pins = "mpp9", "mpp11", "mpp12",
81 interrupt-controller; 56 "mpp13", "mpp14", "mpp15";
82 #interrupts-cells = <2>; 57 marvell,function = "sd0";
83 interrupts = <87>, <88>, <89>, <90>; 58 };
84 }; 59
60 sdio_pins2: sdio-pins2 {
61 marvell,pins = "mpp47", "mpp48", "mpp49",
62 "mpp50", "mpp51", "mpp52";
63 marvell,function = "sd0";
64 };
65
66 sdio_pins3: sdio-pins3 {
67 marvell,pins = "mpp48", "mpp49", "mpp50",
68 "mpp51", "mpp52", "mpp53";
69 marvell,function = "sd0";
70 };
71 };
85 72
86 gpio2: gpio@d0018180 { 73 gpio0: gpio@18100 {
87 compatible = "marvell,orion-gpio"; 74 compatible = "marvell,orion-gpio";
88 reg = <0xd0018180 0x40>; 75 reg = <0x18100 0x40>;
89 ngpios = <2>; 76 ngpios = <32>;
90 gpio-controller; 77 gpio-controller;
91 #gpio-cells = <2>; 78 #gpio-cells = <2>;
92 interrupt-controller; 79 interrupt-controller;
93 #interrupts-cells = <2>; 80 #interrupts-cells = <2>;
94 interrupts = <91>; 81 interrupts = <82>, <83>, <84>, <85>;
95 }; 82 };
96 83
97 coreclk: mvebu-sar@d0018230 { 84 gpio1: gpio@18140 {
98 compatible = "marvell,armada-370-core-clock"; 85 compatible = "marvell,orion-gpio";
99 reg = <0xd0018230 0x08>; 86 reg = <0x18140 0x40>;
100 #clock-cells = <1>; 87 ngpios = <32>;
101 }; 88 gpio-controller;
89 #gpio-cells = <2>;
90 interrupt-controller;
91 #interrupts-cells = <2>;
92 interrupts = <87>, <88>, <89>, <90>;
93 };
102 94
103 gateclk: clock-gating-control@d0018220 { 95 gpio2: gpio@18180 {
104 compatible = "marvell,armada-370-gating-clock"; 96 compatible = "marvell,orion-gpio";
105 reg = <0xd0018220 0x4>; 97 reg = <0x18180 0x40>;
106 clocks = <&coreclk 0>; 98 ngpios = <2>;
107 #clock-cells = <1>; 99 gpio-controller;
108 }; 100 #gpio-cells = <2>;
101 interrupt-controller;
102 #interrupts-cells = <2>;
103 interrupts = <91>;
104 };
109 105
110 xor@d0060800 { 106 coreclk: mvebu-sar@18230 {
111 compatible = "marvell,orion-xor"; 107 compatible = "marvell,armada-370-core-clock";
112 reg = <0xd0060800 0x100 108 reg = <0x18230 0x08>;
113 0xd0060A00 0x100>; 109 #clock-cells = <1>;
114 status = "okay"; 110 };
115 111
116 xor00 { 112 gateclk: clock-gating-control@18220 {
117 interrupts = <51>; 113 compatible = "marvell,armada-370-gating-clock";
118 dmacap,memcpy; 114 reg = <0x18220 0x4>;
119 dmacap,xor; 115 clocks = <&coreclk 0>;
116 #clock-cells = <1>;
120 }; 117 };
121 xor01 { 118
122 interrupts = <52>; 119 xor@60800 {
123 dmacap,memcpy; 120 compatible = "marvell,orion-xor";
124 dmacap,xor; 121 reg = <0x60800 0x100
125 dmacap,memset; 122 0x60A00 0x100>;
123 status = "okay";
124
125 xor00 {
126 interrupts = <51>;
127 dmacap,memcpy;
128 dmacap,xor;
129 };
130 xor01 {
131 interrupts = <52>;
132 dmacap,memcpy;
133 dmacap,xor;
134 dmacap,memset;
135 };
126 }; 136 };
127 };
128 137
129 xor@d0060900 { 138 xor@60900 {
130 compatible = "marvell,orion-xor"; 139 compatible = "marvell,orion-xor";
131 reg = <0xd0060900 0x100 140 reg = <0x60900 0x100
132 0xd0060b00 0x100>; 141 0x60b00 0x100>;
133 status = "okay"; 142 status = "okay";
143
144 xor10 {
145 interrupts = <94>;
146 dmacap,memcpy;
147 dmacap,xor;
148 };
149 xor11 {
150 interrupts = <95>;
151 dmacap,memcpy;
152 dmacap,xor;
153 dmacap,memset;
154 };
155 };
134 156
135 xor10 { 157 usb@50000 {
136 interrupts = <94>; 158 clocks = <&coreclk 0>;
137 dmacap,memcpy;
138 dmacap,xor;
139 }; 159 };
140 xor11 { 160
141 interrupts = <95>; 161 usb@51000 {
142 dmacap,memcpy; 162 clocks = <&coreclk 0>;
143 dmacap,xor;
144 dmacap,memset;
145 }; 163 };
146 };
147 164
148 usb@d0050000 { 165 thermal@18300 {
149 clocks = <&coreclk 0>; 166 compatible = "marvell,armada370-thermal";
150 }; 167 reg = <0x18300 0x4
168 0x18304 0x4>;
169 status = "okay";
170 };
151 171
152 usb@d0051000 { 172 pcie-controller {
153 clocks = <&coreclk 0>; 173 compatible = "marvell,armada-370-pcie";
174 status = "disabled";
175 device_type = "pci";
176
177 #address-cells = <3>;
178 #size-cells = <2>;
179
180 bus-range = <0x00 0xff>;
181
182 reg = <0x40000 0x2000>, <0x80000 0x2000>;
183
184 reg-names = "pcie0.0", "pcie1.0";
185
186 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
187 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
188 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
189 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
190
191 pcie@1,0 {
192 device_type = "pci";
193 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
194 reg = <0x0800 0 0 0 0>;
195 #address-cells = <3>;
196 #size-cells = <2>;
197 #interrupt-cells = <1>;
198 ranges;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 58>;
201 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <0>;
203 clocks = <&gateclk 5>;
204 status = "disabled";
205 };
206
207 pcie@2,0 {
208 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x1000 0 0 0 0>;
211 #address-cells = <3>;
212 #size-cells = <2>;
213 #interrupt-cells = <1>;
214 ranges;
215 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>;
220 status = "disabled";
221 };
222 };
154 }; 223 };
155
156 }; 224 };
157}; 225};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e83505e4c236..d6cc8bf8272e 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -26,99 +26,134 @@
26 26
27 memory { 27 memory {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x00000000 0x80000000>; /* 2 GB */ 29 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
30 }; 30 };
31 31
32 soc { 32 soc {
33 serial@d0012000 { 33 internal-regs {
34 clock-frequency = <250000000>; 34 serial@12000 {
35 status = "okay"; 35 clock-frequency = <250000000>;
36 }; 36 status = "okay";
37 serial@d0012100 { 37 };
38 clock-frequency = <250000000>; 38 serial@12100 {
39 status = "okay"; 39 clock-frequency = <250000000>;
40 }; 40 status = "okay";
41 serial@d0012200 { 41 };
42 clock-frequency = <250000000>; 42 serial@12200 {
43 status = "okay"; 43 clock-frequency = <250000000>;
44 }; 44 status = "okay";
45 serial@d0012300 { 45 };
46 clock-frequency = <250000000>; 46 serial@12300 {
47 status = "okay"; 47 clock-frequency = <250000000>;
48 }; 48 status = "okay";
49
50 sata@d00a0000 {
51 nr-ports = <2>;
52 status = "okay";
53 };
54
55 mdio {
56 phy0: ethernet-phy@0 {
57 reg = <0>;
58 }; 49 };
59 50
60 phy1: ethernet-phy@1 { 51 sata@a0000 {
61 reg = <1>; 52 nr-ports = <2>;
53 status = "okay";
62 }; 54 };
63 55
64 phy2: ethernet-phy@2 { 56 mdio {
65 reg = <25>; 57 phy0: ethernet-phy@0 {
58 reg = <0>;
59 };
60
61 phy1: ethernet-phy@1 {
62 reg = <1>;
63 };
64
65 phy2: ethernet-phy@2 {
66 reg = <25>;
67 };
68
69 phy3: ethernet-phy@3 {
70 reg = <27>;
71 };
66 }; 72 };
67 73
68 phy3: ethernet-phy@3 { 74 ethernet@70000 {
69 reg = <27>; 75 status = "okay";
76 phy = <&phy0>;
77 phy-mode = "rgmii-id";
78 };
79 ethernet@74000 {
80 status = "okay";
81 phy = <&phy1>;
82 phy-mode = "rgmii-id";
83 };
84 ethernet@30000 {
85 status = "okay";
86 phy = <&phy2>;
87 phy-mode = "sgmii";
88 };
89 ethernet@34000 {
90 status = "okay";
91 phy = <&phy3>;
92 phy-mode = "sgmii";
70 }; 93 };
71 };
72 94
73 ethernet@d0070000 { 95 mvsdio@d4000 {
74 status = "okay"; 96 pinctrl-0 = <&sdio_pins>;
75 phy = <&phy0>; 97 pinctrl-names = "default";
76 phy-mode = "rgmii-id"; 98 status = "okay";
77 }; 99 /* No CD or WP GPIOs */
78 ethernet@d0074000 { 100 };
79 status = "okay";
80 phy = <&phy1>;
81 phy-mode = "rgmii-id";
82 };
83 ethernet@d0030000 {
84 status = "okay";
85 phy = <&phy2>;
86 phy-mode = "sgmii";
87 };
88 ethernet@d0034000 {
89 status = "okay";
90 phy = <&phy3>;
91 phy-mode = "sgmii";
92 };
93 101
94 mvsdio@d00d4000 { 102 usb@50000 {
95 pinctrl-0 = <&sdio_pins>; 103 status = "okay";
96 pinctrl-names = "default"; 104 };
97 status = "okay";
98 /* No CD or WP GPIOs */
99 };
100 105
101 usb@d0050000 { 106 usb@51000 {
102 status = "okay"; 107 status = "okay";
103 }; 108 };
104 109
105 usb@d0051000 { 110 usb@52000 {
106 status = "okay"; 111 status = "okay";
107 }; 112 };
108 113
109 usb@d0052000 { 114 spi0: spi@10600 {
110 status = "okay"; 115 status = "okay";
111 };
112 116
113 spi0: spi@d0010600 { 117 spi-flash@0 {
114 status = "okay"; 118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "m25p64";
121 reg = <0>; /* Chip select 0 */
122 spi-max-frequency = <20000000>;
123 };
124 };
115 125
116 spi-flash@0 { 126 pcie-controller {
117 #address-cells = <1>; 127 status = "okay";
118 #size-cells = <1>; 128
119 compatible = "m25p64"; 129 /*
120 reg = <0>; /* Chip select 0 */ 130 * All 6 slots are physically present as
121 spi-max-frequency = <20000000>; 131 * standard PCIe slots on the board.
132 */
133 pcie@1,0 {
134 /* Port 0, Lane 0 */
135 status = "okay";
136 };
137 pcie@2,0 {
138 /* Port 0, Lane 1 */
139 status = "okay";
140 };
141 pcie@3,0 {
142 /* Port 0, Lane 2 */
143 status = "okay";
144 };
145 pcie@4,0 {
146 /* Port 0, Lane 3 */
147 status = "okay";
148 };
149 pcie@9,0 {
150 /* Port 2, Lane 0 */
151 status = "okay";
152 };
153 pcie@10,0 {
154 /* Port 3, Lane 0 */
155 status = "okay";
156 };
122 }; 157 };
123 }; 158 };
124 }; 159 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1c8afe2ffebc..26ad06fc147e 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -26,87 +26,141 @@
26 26
27 memory { 27 memory {
28 device_type = "memory"; 28 device_type = "memory";
29
30 /* 29 /*
31 * 4 GB of plug-in RAM modules by default but only 3GB 30 * 8 GB of plug-in RAM modules by default.The amount
32 * are visible, the amount of memory available can be 31 * of memory available can be changed by the
33 * changed by the bootloader according the size of the 32 * bootloader according the size of the module
34 * module actually plugged 33 * actually plugged. Only 7GB are usable because
34 * addresses from 0xC0000000 to 0xffffffff are used by
35 * the internal registers of the SoC.
35 */ 36 */
36 reg = <0x00000000 0xC0000000>; 37 reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
38 <0x00000001 0x00000000 0x00000001 0x00000000>;
37 }; 39 };
38 40
39 soc { 41 soc {
40 serial@d0012000 { 42 internal-regs {
41 clock-frequency = <250000000>; 43 serial@12000 {
42 status = "okay"; 44 clock-frequency = <250000000>;
43 }; 45 status = "okay";
44 serial@d0012100 { 46 };
45 clock-frequency = <250000000>; 47 serial@12100 {
46 status = "okay"; 48 clock-frequency = <250000000>;
47 }; 49 status = "okay";
48 serial@d0012200 { 50 };
49 clock-frequency = <250000000>; 51 serial@12200 {
50 status = "okay"; 52 clock-frequency = <250000000>;
51 }; 53 status = "okay";
52 serial@d0012300 { 54 };
53 clock-frequency = <250000000>; 55 serial@12300 {
54 status = "okay"; 56 clock-frequency = <250000000>;
55 }; 57 status = "okay";
56 58 };
57 sata@d00a0000 {
58 nr-ports = <2>;
59 status = "okay";
60 };
61 59
62 mdio { 60 sata@a0000 {
63 phy0: ethernet-phy@0 { 61 nr-ports = <2>;
64 reg = <16>; 62 status = "okay";
65 }; 63 };
66 64
67 phy1: ethernet-phy@1 { 65 mdio {
68 reg = <17>; 66 phy0: ethernet-phy@0 {
67 reg = <16>;
68 };
69
70 phy1: ethernet-phy@1 {
71 reg = <17>;
72 };
73
74 phy2: ethernet-phy@2 {
75 reg = <18>;
76 };
77
78 phy3: ethernet-phy@3 {
79 reg = <19>;
80 };
69 }; 81 };
70 82
71 phy2: ethernet-phy@2 { 83 ethernet@70000 {
72 reg = <18>; 84 status = "okay";
85 phy = <&phy0>;
86 phy-mode = "rgmii-id";
73 }; 87 };
88 ethernet@74000 {
89 status = "okay";
90 phy = <&phy1>;
91 phy-mode = "rgmii-id";
92 };
93 ethernet@30000 {
94 status = "okay";
95 phy = <&phy2>;
96 phy-mode = "rgmii-id";
97 };
98 ethernet@34000 {
99 status = "okay";
100 phy = <&phy3>;
101 phy-mode = "rgmii-id";
102 };
103
104 spi0: spi@10600 {
105 status = "okay";
74 106
75 phy3: ethernet-phy@3 { 107 spi-flash@0 {
76 reg = <19>; 108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "n25q128a13";
111 reg = <0>; /* Chip select 0 */
112 spi-max-frequency = <108000000>;
113 };
77 }; 114 };
78 };
79 115
80 ethernet@d0070000 { 116 devbus-bootcs@10400 {
81 status = "okay"; 117 status = "okay";
82 phy = <&phy0>; 118 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
83 phy-mode = "rgmii-id"; 119
84 }; 120 /* Device Bus parameters are required */
85 ethernet@d0074000 { 121
86 status = "okay"; 122 /* Read parameters */
87 phy = <&phy1>; 123 devbus,bus-width = <8>;
88 phy-mode = "rgmii-id"; 124 devbus,turn-off-ps = <60000>;
89 }; 125 devbus,badr-skew-ps = <0>;
90 ethernet@d0030000 { 126 devbus,acc-first-ps = <124000>;
91 status = "okay"; 127 devbus,acc-next-ps = <248000>;
92 phy = <&phy2>; 128 devbus,rd-setup-ps = <0>;
93 phy-mode = "rgmii-id"; 129 devbus,rd-hold-ps = <0>;
94 }; 130
95 ethernet@d0034000 { 131 /* Write parameters */
96 status = "okay"; 132 devbus,sync-enable = <0>;
97 phy = <&phy3>; 133 devbus,wr-high-ps = <60000>;
98 phy-mode = "rgmii-id"; 134 devbus,wr-low-ps = <60000>;
99 }; 135 devbus,ale-wr-ps = <60000>;
136
137 /* NOR 16 MiB */
138 nor@0 {
139 compatible = "cfi-flash";
140 reg = <0 0x1000000>;
141 bank-width = <2>;
142 };
143 };
100 144
101 spi0: spi@d0010600 { 145 pcie-controller {
102 status = "okay"; 146 status = "okay";
103 147
104 spi-flash@0 { 148 /*
105 #address-cells = <1>; 149 * The 3 slots are physically present as
106 #size-cells = <1>; 150 * standard PCIe slots on the board.
107 compatible = "n25q128a13"; 151 */
108 reg = <0>; /* Chip select 0 */ 152 pcie@1,0 {
109 spi-max-frequency = <108000000>; 153 /* Port 0, Lane 0 */
154 status = "okay";
155 };
156 pcie@9,0 {
157 /* Port 2, Lane 0 */
158 status = "okay";
159 };
160 pcie@10,0 {
161 /* Port 3, Lane 0 */
162 status = "okay";
163 };
110 }; 164 };
111 }; 165 };
112 }; 166 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f56c40599f5b..f8eaa383e07f 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -25,56 +25,162 @@
25 }; 25 };
26 26
27 cpus { 27 cpus {
28 #address-cells = <1>; 28 #address-cells = <1>;
29 #size-cells = <0>; 29 #size-cells = <0>;
30 30
31 cpu@0 { 31 cpu@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7"; 33 compatible = "marvell,sheeva-v7";
34 reg = <0>; 34 reg = <0>;
35 clocks = <&cpuclk 0>; 35 clocks = <&cpuclk 0>;
36 }; 36 };
37 37
38 cpu@1 { 38 cpu@1 {
39 device_type = "cpu"; 39 device_type = "cpu";
40 compatible = "marvell,sheeva-v7"; 40 compatible = "marvell,sheeva-v7";
41 reg = <1>; 41 reg = <1>;
42 clocks = <&cpuclk 1>; 42 clocks = <&cpuclk 1>;
43 }; 43 };
44 }; 44 };
45 45
46 soc { 46 soc {
47 pinctrl { 47 internal-regs {
48 compatible = "marvell,mv78230-pinctrl"; 48 pinctrl {
49 reg = <0xd0018000 0x38>; 49 compatible = "marvell,mv78230-pinctrl";
50 50 reg = <0x18000 0x38>;
51 sdio_pins: sdio-pins { 51
52 marvell,pins = "mpp30", "mpp31", "mpp32", 52 sdio_pins: sdio-pins {
53 "mpp33", "mpp34", "mpp35"; 53 marvell,pins = "mpp30", "mpp31", "mpp32",
54 marvell,function = "sd0"; 54 "mpp33", "mpp34", "mpp35";
55 marvell,function = "sd0";
56 };
55 }; 57 };
56 };
57 58
58 gpio0: gpio@d0018100 { 59 gpio0: gpio@18100 {
59 compatible = "marvell,orion-gpio"; 60 compatible = "marvell,orion-gpio";
60 reg = <0xd0018100 0x40>; 61 reg = <0x18100 0x40>;
61 ngpios = <32>; 62 ngpios = <32>;
62 gpio-controller; 63 gpio-controller;
63 #gpio-cells = <2>; 64 #gpio-cells = <2>;
64 interrupt-controller; 65 interrupt-controller;
65 #interrupts-cells = <2>; 66 #interrupts-cells = <2>;
66 interrupts = <82>, <83>, <84>, <85>; 67 interrupts = <82>, <83>, <84>, <85>;
67 }; 68 };
69
70 gpio1: gpio@18140 {
71 compatible = "marvell,orion-gpio";
72 reg = <0x18140 0x40>;
73 ngpios = <17>;
74 gpio-controller;
75 #gpio-cells = <2>;
76 interrupt-controller;
77 #interrupts-cells = <2>;
78 interrupts = <87>, <88>, <89>;
79 };
68 80
69 gpio1: gpio@d0018140 { 81 /*
70 compatible = "marvell,orion-gpio"; 82 * MV78230 has 2 PCIe units Gen2.0: One unit can be
71 reg = <0xd0018140 0x40>; 83 * configured as x4 or quad x1 lanes. One unit is
72 ngpios = <17>; 84 * x4/x1.
73 gpio-controller; 85 */
74 #gpio-cells = <2>; 86 pcie-controller {
75 interrupt-controller; 87 compatible = "marvell,armada-xp-pcie";
76 #interrupts-cells = <2>; 88 status = "disabled";
77 interrupts = <87>, <88>, <89>; 89 device_type = "pci";
90
91#address-cells = <3>;
92#size-cells = <2>;
93
94 bus-range = <0x00 0xff>;
95
96 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
97 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
98 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
99 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
100 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
101 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
102 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
103
104 pcie@1,0 {
105 device_type = "pci";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 #address-cells = <3>;
109 #size-cells = <2>;
110 #interrupt-cells = <1>;
111 ranges;
112 interrupt-map-mask = <0 0 0 0>;
113 interrupt-map = <0 0 0 0 &mpic 58>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 5>;
117 status = "disabled";
118 };
119
120 pcie@2,0 {
121 device_type = "pci";
122 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
123 reg = <0x1000 0 0 0 0>;
124 #address-cells = <3>;
125 #size-cells = <2>;
126 #interrupt-cells = <1>;
127 ranges;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &mpic 59>;
130 marvell,pcie-port = <0>;
131 marvell,pcie-lane = <1>;
132 clocks = <&gateclk 6>;
133 status = "disabled";
134 };
135
136 pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 ranges;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 60>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <2>;
148 clocks = <&gateclk 7>;
149 status = "disabled";
150 };
151
152 pcie@4,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 61>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <3>;
164 clocks = <&gateclk 8>;
165 status = "disabled";
166 };
167
168 pcie@9,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171 reg = <0x4800 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 99>;
178 marvell,pcie-port = <2>;
179 marvell,pcie-lane = <0>;
180 clocks = <&gateclk 26>;
181 status = "disabled";
182 };
183 };
78 }; 184 };
79 }; 185 };
80}; 186};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f8f2b787d2b0..f4029f015aff 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -26,75 +26,199 @@
26 }; 26 };
27 27
28 cpus { 28 cpus {
29 #address-cells = <1>; 29 #address-cells = <1>;
30 #size-cells = <0>; 30 #size-cells = <0>;
31 31
32 cpu@0 { 32 cpu@0 {
33 device_type = "cpu"; 33 device_type = "cpu";
34 compatible = "marvell,sheeva-v7"; 34 compatible = "marvell,sheeva-v7";
35 reg = <0>; 35 reg = <0>;
36 clocks = <&cpuclk 0>; 36 clocks = <&cpuclk 0>;
37 }; 37 };
38 38
39 cpu@1 { 39 cpu@1 {
40 device_type = "cpu"; 40 device_type = "cpu";
41 compatible = "marvell,sheeva-v7"; 41 compatible = "marvell,sheeva-v7";
42 reg = <1>; 42 reg = <1>;
43 clocks = <&cpuclk 1>; 43 clocks = <&cpuclk 1>;
44 }; 44 };
45 }; 45 };
46 46
47 soc { 47 soc {
48 pinctrl { 48 internal-regs {
49 compatible = "marvell,mv78260-pinctrl"; 49 pinctrl {
50 reg = <0xd0018000 0x38>; 50 compatible = "marvell,mv78260-pinctrl";
51 51 reg = <0x18000 0x38>;
52 sdio_pins: sdio-pins { 52
53 marvell,pins = "mpp30", "mpp31", "mpp32", 53 sdio_pins: sdio-pins {
54 "mpp33", "mpp34", "mpp35"; 54 marvell,pins = "mpp30", "mpp31", "mpp32",
55 marvell,function = "sd0"; 55 "mpp33", "mpp34", "mpp35";
56 marvell,function = "sd0";
57 };
56 }; 58 };
57 };
58 59
59 gpio0: gpio@d0018100 { 60 gpio0: gpio@18100 {
60 compatible = "marvell,orion-gpio"; 61 compatible = "marvell,orion-gpio";
61 reg = <0xd0018100 0x40>; 62 reg = <0x18100 0x40>;
62 ngpios = <32>; 63 ngpios = <32>;
63 gpio-controller; 64 gpio-controller;
64 #gpio-cells = <2>; 65 #gpio-cells = <2>;
65 interrupt-controller; 66 interrupt-controller;
66 #interrupts-cells = <2>; 67 #interrupts-cells = <2>;
67 interrupts = <82>, <83>, <84>, <85>; 68 interrupts = <82>, <83>, <84>, <85>;
68 }; 69 };
69 70
70 gpio1: gpio@d0018140 { 71 gpio1: gpio@18140 {
71 compatible = "marvell,orion-gpio"; 72 compatible = "marvell,orion-gpio";
72 reg = <0xd0018140 0x40>; 73 reg = <0x18140 0x40>;
73 ngpios = <32>; 74 ngpios = <32>;
74 gpio-controller; 75 gpio-controller;
75 #gpio-cells = <2>; 76 #gpio-cells = <2>;
76 interrupt-controller; 77 interrupt-controller;
77 #interrupts-cells = <2>; 78 #interrupts-cells = <2>;
78 interrupts = <87>, <88>, <89>, <90>; 79 interrupts = <87>, <88>, <89>, <90>;
79 }; 80 };
80 81
81 gpio2: gpio@d0018180 { 82 gpio2: gpio@18180 {
82 compatible = "marvell,orion-gpio"; 83 compatible = "marvell,orion-gpio";
83 reg = <0xd0018180 0x40>; 84 reg = <0x18180 0x40>;
84 ngpios = <3>; 85 ngpios = <3>;
85 gpio-controller; 86 gpio-controller;
86 #gpio-cells = <2>; 87 #gpio-cells = <2>;
87 interrupt-controller; 88 interrupt-controller;
88 #interrupts-cells = <2>; 89 #interrupts-cells = <2>;
89 interrupts = <91>; 90 interrupts = <91>;
90 }; 91 };
91 92
92 ethernet@d0034000 { 93 ethernet@34000 {
93 compatible = "marvell,armada-370-neta"; 94 compatible = "marvell,armada-370-neta";
94 reg = <0xd0034000 0x2500>; 95 reg = <0x34000 0x2500>;
95 interrupts = <14>; 96 interrupts = <14>;
96 clocks = <&gateclk 1>; 97 clocks = <&gateclk 1>;
97 status = "disabled"; 98 status = "disabled";
99 };
100
101 /*
102 * MV78260 has 3 PCIe units Gen2.0: Two units can be
103 * configured as x4 or quad x1 lanes. One unit is
104 * x4/x1.
105 */
106 pcie-controller {
107 compatible = "marvell,armada-xp-pcie";
108 status = "disabled";
109 device_type = "pci";
110
111 #address-cells = <3>;
112 #size-cells = <2>;
113
114 bus-range = <0x00 0xff>;
115
116 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
117 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
118 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
119 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
120 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
121 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
122 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
123 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
124 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
125
126 pcie@1,0 {
127 device_type = "pci";
128 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
129 reg = <0x0800 0 0 0 0>;
130 #address-cells = <3>;
131 #size-cells = <2>;
132 #interrupt-cells = <1>;
133 ranges;
134 interrupt-map-mask = <0 0 0 0>;
135 interrupt-map = <0 0 0 0 &mpic 58>;
136 marvell,pcie-port = <0>;
137 marvell,pcie-lane = <0>;
138 clocks = <&gateclk 5>;
139 status = "disabled";
140 };
141
142 pcie@2,0 {
143 device_type = "pci";
144 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
145 reg = <0x1000 0 0 0 0>;
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 ranges;
150 interrupt-map-mask = <0 0 0 0>;
151 interrupt-map = <0 0 0 0 &mpic 59>;
152 marvell,pcie-port = <0>;
153 marvell,pcie-lane = <1>;
154 clocks = <&gateclk 6>;
155 status = "disabled";
156 };
157
158 pcie@3,0 {
159 device_type = "pci";
160 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
161 reg = <0x1800 0 0 0 0>;
162 #address-cells = <3>;
163 #size-cells = <2>;
164 #interrupt-cells = <1>;
165 ranges;
166 interrupt-map-mask = <0 0 0 0>;
167 interrupt-map = <0 0 0 0 &mpic 60>;
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
170 clocks = <&gateclk 7>;
171 status = "disabled";
172 };
173
174 pcie@4,0 {
175 device_type = "pci";
176 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
177 reg = <0x2000 0 0 0 0>;
178 #address-cells = <3>;
179 #size-cells = <2>;
180 #interrupt-cells = <1>;
181 ranges;
182 interrupt-map-mask = <0 0 0 0>;
183 interrupt-map = <0 0 0 0 &mpic 61>;
184 marvell,pcie-port = <0>;
185 marvell,pcie-lane = <3>;
186 clocks = <&gateclk 8>;
187 status = "disabled";
188 };
189
190 pcie@9,0 {
191 device_type = "pci";
192 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
193 reg = <0x4800 0 0 0 0>;
194 #address-cells = <3>;
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 99>;
200 marvell,pcie-port = <2>;
201 marvell,pcie-lane = <0>;
202 clocks = <&gateclk 26>;
203 status = "disabled";
204 };
205
206 pcie@10,0 {
207 device_type = "pci";
208 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
209 reg = <0x5000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 #interrupt-cells = <1>;
213 ranges;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 103>;
216 marvell,pcie-port = <3>;
217 marvell,pcie-lane = <0>;
218 clocks = <&gateclk 27>;
219 status = "disabled";
220 };
221 };
98 }; 222 };
99 }; 223 };
100}; 224};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 936c25dc32b0..6ab56bd35de9 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -27,89 +27,279 @@
27 27
28 28
29 cpus { 29 cpus {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <0>; 31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "marvell,sheeva-v7";
36 reg = <0>;
37 clocks = <&cpuclk 0>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "marvell,sheeva-v7";
43 reg = <1>;
44 clocks = <&cpuclk 1>;
45 };
46
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "marvell,sheeva-v7";
50 reg = <2>;
51 clocks = <&cpuclk 2>;
52 };
53
54 cpu@3 {
55 device_type = "cpu";
56 compatible = "marvell,sheeva-v7";
57 reg = <3>;
58 clocks = <&cpuclk 3>;
59 };
60 };
61 32
62 soc { 33 cpu@0 {
63 pinctrl { 34 device_type = "cpu";
64 compatible = "marvell,mv78460-pinctrl"; 35 compatible = "marvell,sheeva-v7";
65 reg = <0xd0018000 0x38>; 36 reg = <0>;
66 37 clocks = <&cpuclk 0>;
67 sdio_pins: sdio-pins {
68 marvell,pins = "mpp30", "mpp31", "mpp32",
69 "mpp33", "mpp34", "mpp35";
70 marvell,function = "sd0";
71 };
72 }; 38 };
73 39
74 gpio0: gpio@d0018100 { 40 cpu@1 {
75 compatible = "marvell,orion-gpio"; 41 device_type = "cpu";
76 reg = <0xd0018100 0x40>; 42 compatible = "marvell,sheeva-v7";
77 ngpios = <32>; 43 reg = <1>;
78 gpio-controller; 44 clocks = <&cpuclk 1>;
79 #gpio-cells = <2>;
80 interrupt-controller;
81 #interrupts-cells = <2>;
82 interrupts = <82>, <83>, <84>, <85>;
83 }; 45 };
84 46
85 gpio1: gpio@d0018140 { 47 cpu@2 {
86 compatible = "marvell,orion-gpio"; 48 device_type = "cpu";
87 reg = <0xd0018140 0x40>; 49 compatible = "marvell,sheeva-v7";
88 ngpios = <32>; 50 reg = <2>;
89 gpio-controller; 51 clocks = <&cpuclk 2>;
90 #gpio-cells = <2>;
91 interrupt-controller;
92 #interrupts-cells = <2>;
93 interrupts = <87>, <88>, <89>, <90>;
94 }; 52 };
95 53
96 gpio2: gpio@d0018180 { 54 cpu@3 {
97 compatible = "marvell,orion-gpio"; 55 device_type = "cpu";
98 reg = <0xd0018180 0x40>; 56 compatible = "marvell,sheeva-v7";
99 ngpios = <3>; 57 reg = <3>;
100 gpio-controller; 58 clocks = <&cpuclk 3>;
101 #gpio-cells = <2>;
102 interrupt-controller;
103 #interrupts-cells = <2>;
104 interrupts = <91>;
105 }; 59 };
60 };
61
62 soc {
63 internal-regs {
64 pinctrl {
65 compatible = "marvell,mv78460-pinctrl";
66 reg = <0x18000 0x38>;
67
68 sdio_pins: sdio-pins {
69 marvell,pins = "mpp30", "mpp31", "mpp32",
70 "mpp33", "mpp34", "mpp35";
71 marvell,function = "sd0";
72 };
73 };
106 74
107 ethernet@d0034000 { 75 gpio0: gpio@18100 {
76 compatible = "marvell,orion-gpio";
77 reg = <0x18100 0x40>;
78 ngpios = <32>;
79 gpio-controller;
80 #gpio-cells = <2>;
81 interrupt-controller;
82 #interrupts-cells = <2>;
83 interrupts = <82>, <83>, <84>, <85>;
84 };
85
86 gpio1: gpio@18140 {
87 compatible = "marvell,orion-gpio";
88 reg = <0x18140 0x40>;
89 ngpios = <32>;
90 gpio-controller;
91 #gpio-cells = <2>;
92 interrupt-controller;
93 #interrupts-cells = <2>;
94 interrupts = <87>, <88>, <89>, <90>;
95 };
96
97 gpio2: gpio@18180 {
98 compatible = "marvell,orion-gpio";
99 reg = <0x18180 0x40>;
100 ngpios = <3>;
101 gpio-controller;
102 #gpio-cells = <2>;
103 interrupt-controller;
104 #interrupts-cells = <2>;
105 interrupts = <91>;
106 };
107
108 ethernet@34000 {
108 compatible = "marvell,armada-370-neta"; 109 compatible = "marvell,armada-370-neta";
109 reg = <0xd0034000 0x2500>; 110 reg = <0x34000 0x2500>;
110 interrupts = <14>; 111 interrupts = <14>;
111 clocks = <&gateclk 1>; 112 clocks = <&gateclk 1>;
112 status = "disabled"; 113 status = "disabled";
114 };
115
116 /*
117 * MV78460 has 4 PCIe units Gen2.0: Two units can be
118 * configured as x4 or quad x1 lanes. Two units are
119 * x4/x1.
120 */
121 pcie-controller {
122 compatible = "marvell,armada-xp-pcie";
123 status = "disabled";
124 device_type = "pci";
125
126 #address-cells = <3>;
127 #size-cells = <2>;
128
129 bus-range = <0x00 0xff>;
130
131 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
132 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
133 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
134 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
135 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
136 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
137 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
138 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
139 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
140 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
141 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
142 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
143
144 pcie@1,0 {
145 device_type = "pci";
146 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
147 reg = <0x0800 0 0 0 0>;
148 #address-cells = <3>;
149 #size-cells = <2>;
150 #interrupt-cells = <1>;
151 ranges;
152 interrupt-map-mask = <0 0 0 0>;
153 interrupt-map = <0 0 0 0 &mpic 58>;
154 marvell,pcie-port = <0>;
155 marvell,pcie-lane = <0>;
156 clocks = <&gateclk 5>;
157 status = "disabled";
158 };
159
160 pcie@2,0 {
161 device_type = "pci";
162 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
163 reg = <0x1000 0 0 0 0>;
164 #address-cells = <3>;
165 #size-cells = <2>;
166 #interrupt-cells = <1>;
167 ranges;
168 interrupt-map-mask = <0 0 0 0>;
169 interrupt-map = <0 0 0 0 &mpic 59>;
170 marvell,pcie-port = <0>;
171 marvell,pcie-lane = <1>;
172 clocks = <&gateclk 6>;
173 status = "disabled";
174 };
175
176 pcie@3,0 {
177 device_type = "pci";
178 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
179 reg = <0x1800 0 0 0 0>;
180 #address-cells = <3>;
181 #size-cells = <2>;
182 #interrupt-cells = <1>;
183 ranges;
184 interrupt-map-mask = <0 0 0 0>;
185 interrupt-map = <0 0 0 0 &mpic 60>;
186 marvell,pcie-port = <0>;
187 marvell,pcie-lane = <2>;
188 clocks = <&gateclk 7>;
189 status = "disabled";
190 };
191
192 pcie@4,0 {
193 device_type = "pci";
194 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
195 reg = <0x2000 0 0 0 0>;
196 #address-cells = <3>;
197 #size-cells = <2>;
198 #interrupt-cells = <1>;
199 ranges;
200 interrupt-map-mask = <0 0 0 0>;
201 interrupt-map = <0 0 0 0 &mpic 61>;
202 marvell,pcie-port = <0>;
203 marvell,pcie-lane = <3>;
204 clocks = <&gateclk 8>;
205 status = "disabled";
206 };
207
208 pcie@5,0 {
209 device_type = "pci";
210 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
211 reg = <0x2800 0 0 0 0>;
212 #address-cells = <3>;
213 #size-cells = <2>;
214 #interrupt-cells = <1>;
215 ranges;
216 interrupt-map-mask = <0 0 0 0>;
217 interrupt-map = <0 0 0 0 &mpic 62>;
218 marvell,pcie-port = <1>;
219 marvell,pcie-lane = <0>;
220 clocks = <&gateclk 9>;
221 status = "disabled";
222 };
223
224 pcie@6,0 {
225 device_type = "pci";
226 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
227 reg = <0x3000 0 0 0 0>;
228 #address-cells = <3>;
229 #size-cells = <2>;
230 #interrupt-cells = <1>;
231 ranges;
232 interrupt-map-mask = <0 0 0 0>;
233 interrupt-map = <0 0 0 0 &mpic 63>;
234 marvell,pcie-port = <1>;
235 marvell,pcie-lane = <1>;
236 clocks = <&gateclk 10>;
237 status = "disabled";
238 };
239
240 pcie@7,0 {
241 device_type = "pci";
242 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
243 reg = <0x3800 0 0 0 0>;
244 #address-cells = <3>;
245 #size-cells = <2>;
246 #interrupt-cells = <1>;
247 ranges;
248 interrupt-map-mask = <0 0 0 0>;
249 interrupt-map = <0 0 0 0 &mpic 64>;
250 marvell,pcie-port = <1>;
251 marvell,pcie-lane = <2>;
252 clocks = <&gateclk 11>;
253 status = "disabled";
254 };
255
256 pcie@8,0 {
257 device_type = "pci";
258 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
259 reg = <0x4000 0 0 0 0>;
260 #address-cells = <3>;
261 #size-cells = <2>;
262 #interrupt-cells = <1>;
263 ranges;
264 interrupt-map-mask = <0 0 0 0>;
265 interrupt-map = <0 0 0 0 &mpic 65>;
266 marvell,pcie-port = <1>;
267 marvell,pcie-lane = <3>;
268 clocks = <&gateclk 12>;
269 status = "disabled";
270 };
271 pcie@9,0 {
272 device_type = "pci";
273 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
274 reg = <0x4800 0 0 0 0>;
275 #address-cells = <3>;
276 #size-cells = <2>;
277 #interrupt-cells = <1>;
278 ranges;
279 interrupt-map-mask = <0 0 0 0>;
280 interrupt-map = <0 0 0 0 &mpic 99>;
281 marvell,pcie-port = <2>;
282 marvell,pcie-lane = <0>;
283 clocks = <&gateclk 26>;
284 status = "disabled";
285 };
286
287 pcie@10,0 {
288 device_type = "pci";
289 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
290 reg = <0x5000 0 0 0 0>;
291 #address-cells = <3>;
292 #size-cells = <2>;
293 #interrupt-cells = <1>;
294 ranges;
295 interrupt-map-mask = <0 0 0 0>;
296 interrupt-map = <0 0 0 0 &mpic 103>;
297 marvell,pcie-port = <3>;
298 marvell,pcie-lane = <0>;
299 clocks = <&gateclk 27>;
300 status = "disabled";
301 };
302 };
113 }; 303 };
114 }; 304 };
115 }; 305};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 3818a82176a2..f14d36c46159 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -23,121 +23,161 @@
23 23
24 memory { 24 memory {
25 device_type = "memory"; 25 device_type = "memory";
26 reg = <0x00000000 0xC0000000>; /* 3 GB */ 26 reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
27 }; 27 };
28 28
29 soc { 29 soc {
30 serial@d0012000 { 30 internal-regs {
31 clock-frequency = <250000000>; 31 serial@12000 {
32 status = "okay"; 32 clock-frequency = <250000000>;
33 }; 33 status = "okay";
34 serial@d0012100 {
35 clock-frequency = <250000000>;
36 status = "okay";
37 };
38 pinctrl {
39 led_pins: led-pins-0 {
40 marvell,pins = "mpp49", "mpp51", "mpp53";
41 marvell,function = "gpio";
42 }; 34 };
43 }; 35 serial@12100 {
44 leds { 36 clock-frequency = <250000000>;
45 compatible = "gpio-leds"; 37 status = "okay";
46 pinctrl-names = "default";
47 pinctrl-0 = <&led_pins>;
48
49 red_led {
50 label = "red_led";
51 gpios = <&gpio1 17 1>;
52 default-state = "off";
53 }; 38 };
54 39 pinctrl {
55 yellow_led { 40 led_pins: led-pins-0 {
56 label = "yellow_led"; 41 marvell,pins = "mpp49", "mpp51", "mpp53";
57 gpios = <&gpio1 19 1>; 42 marvell,function = "gpio";
58 default-state = "off"; 43 };
59 }; 44 };
60 45 leds {
61 green_led { 46 compatible = "gpio-leds";
62 label = "green_led"; 47 pinctrl-names = "default";
63 gpios = <&gpio1 21 1>; 48 pinctrl-0 = <&led_pins>;
64 default-state = "off"; 49
65 linux,default-trigger = "heartbeat"; 50 red_led {
51 label = "red_led";
52 gpios = <&gpio1 17 1>;
53 default-state = "off";
54 };
55
56 yellow_led {
57 label = "yellow_led";
58 gpios = <&gpio1 19 1>;
59 default-state = "off";
60 };
61
62 green_led {
63 label = "green_led";
64 gpios = <&gpio1 21 1>;
65 default-state = "off";
66 linux,default-trigger = "heartbeat";
67 };
66 }; 68 };
67 };
68 69
69 gpio_keys { 70 gpio_keys {
70 compatible = "gpio-keys"; 71 compatible = "gpio-keys";
71 #address-cells = <1>; 72 #address-cells = <1>;
72 #size-cells = <0>; 73 #size-cells = <0>;
73 74
74 button@1 { 75 button@1 {
75 label = "Init Button"; 76 label = "Init Button";
76 linux,code = <116>; 77 linux,code = <116>;
77 gpios = <&gpio1 28 0>; 78 gpios = <&gpio1 28 0>;
79 };
78 }; 80 };
79 };
80 81
81 mdio { 82 mdio {
82 phy0: ethernet-phy@0 { 83 phy0: ethernet-phy@0 {
83 reg = <0>; 84 reg = <0>;
84 }; 85 };
85 86
86 phy1: ethernet-phy@1 { 87 phy1: ethernet-phy@1 {
87 reg = <1>; 88 reg = <1>;
88 }; 89 };
89 90
90 phy2: ethernet-phy@2 { 91 phy2: ethernet-phy@2 {
91 reg = <2>; 92 reg = <2>;
93 };
94
95 phy3: ethernet-phy@3 {
96 reg = <3>;
97 };
92 }; 98 };
93 99
94 phy3: ethernet-phy@3 { 100 ethernet@70000 {
95 reg = <3>; 101 status = "okay";
102 phy = <&phy0>;
103 phy-mode = "sgmii";
104 };
105 ethernet@74000 {
106 status = "okay";
107 phy = <&phy1>;
108 phy-mode = "sgmii";
109 };
110 ethernet@30000 {
111 status = "okay";
112 phy = <&phy2>;
113 phy-mode = "sgmii";
114 };
115 ethernet@34000 {
116 status = "okay";
117 phy = <&phy3>;
118 phy-mode = "sgmii";
119 };
120 i2c@11000 {
121 status = "okay";
122 clock-frequency = <400000>;
123 };
124 i2c@11100 {
125 status = "okay";
126 clock-frequency = <400000>;
127
128 s35390a: s35390a@30 {
129 compatible = "s35390a";
130 reg = <0x30>;
131 };
132 };
133 sata@a0000 {
134 nr-ports = <2>;
135 status = "okay";
136 };
137 usb@50000 {
138 status = "okay";
139 };
140 usb@51000 {
141 status = "okay";
96 }; 142 };
97 };
98 143
99 ethernet@d0070000 { 144 devbus-bootcs@10400 {
100 status = "okay"; 145 status = "okay";
101 phy = <&phy0>; 146 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
102 phy-mode = "sgmii"; 147
103 }; 148 /* Device Bus parameters are required */
104 ethernet@d0074000 { 149
105 status = "okay"; 150 /* Read parameters */
106 phy = <&phy1>; 151 devbus,bus-width = <8>;
107 phy-mode = "sgmii"; 152 devbus,turn-off-ps = <60000>;
108 }; 153 devbus,badr-skew-ps = <0>;
109 ethernet@d0030000 { 154 devbus,acc-first-ps = <124000>;
110 status = "okay"; 155 devbus,acc-next-ps = <248000>;
111 phy = <&phy2>; 156 devbus,rd-setup-ps = <0>;
112 phy-mode = "sgmii"; 157 devbus,rd-hold-ps = <0>;
113 }; 158
114 ethernet@d0034000 { 159 /* Write parameters */
115 status = "okay"; 160 devbus,sync-enable = <0>;
116 phy = <&phy3>; 161 devbus,wr-high-ps = <60000>;
117 phy-mode = "sgmii"; 162 devbus,wr-low-ps = <60000>;
118 }; 163 devbus,ale-wr-ps = <60000>;
119 i2c@d0011000 { 164
120 status = "okay"; 165 /* NOR 128 MiB */
121 clock-frequency = <400000>; 166 nor@0 {
122 }; 167 compatible = "cfi-flash";
123 i2c@d0011100 { 168 reg = <0 0x8000000>;
124 status = "okay"; 169 bank-width = <2>;
125 clock-frequency = <400000>; 170 };
171 };
126 172
127 s35390a: s35390a@30 { 173 pcie-controller {
128 compatible = "s35390a"; 174 status = "okay";
129 reg = <0x30>; 175 /* Internal mini-PCIe connector */
176 pcie@1,0 {
177 /* Port 0, Lane 0 */
178 status = "okay";
179 };
130 }; 180 };
131 }; 181 };
132 sata@d00a0000 {
133 nr-ports = <2>;
134 status = "okay";
135 };
136 usb@d0050000 {
137 status = "okay";
138 };
139 usb@d0051000 {
140 status = "okay";
141 };
142 }; 182 };
143}; 183};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ca00d8326c87..bacab11c10dc 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,134 +22,140 @@
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25 L2: l2-cache { 25 soc {
26 compatible = "marvell,aurora-system-cache"; 26 internal-regs {
27 reg = <0xd0008000 0x1000>; 27 L2: l2-cache {
28 cache-id-part = <0x100>; 28 compatible = "marvell,aurora-system-cache";
29 wt-override; 29 reg = <0x08000 0x1000>;
30 }; 30 cache-id-part = <0x100>;
31 wt-override;
32 };
31 33
32 mpic: interrupt-controller@d0020000 { 34 mpic: interrupt-controller@20000 {
33 reg = <0xd0020a00 0x2d0>, 35 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
34 <0xd0021070 0x58>; 36 };
35 };
36 37
37 armada-370-xp-pmsu@d0022000 { 38 armada-370-xp-pmsu@22000 {
38 compatible = "marvell,armada-370-xp-pmsu"; 39 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>, 40 reg = <0x22100 0x430>, <0x20800 0x20>;
40 <0xd0020800 0x20>; 41 };
41 };
42 42
43 soc { 43 serial@12200 {
44 serial@d0012200 {
45 compatible = "snps,dw-apb-uart"; 44 compatible = "snps,dw-apb-uart";
46 reg = <0xd0012200 0x100>; 45 reg = <0x12200 0x100>;
47 reg-shift = <2>; 46 reg-shift = <2>;
48 interrupts = <43>; 47 interrupts = <43>;
49 reg-io-width = <1>; 48 reg-io-width = <1>;
50 status = "disabled"; 49 status = "disabled";
51 }; 50 };
52 serial@d0012300 { 51 serial@12300 {
53 compatible = "snps,dw-apb-uart"; 52 compatible = "snps,dw-apb-uart";
54 reg = <0xd0012300 0x100>; 53 reg = <0x12300 0x100>;
55 reg-shift = <2>; 54 reg-shift = <2>;
56 interrupts = <44>; 55 interrupts = <44>;
57 reg-io-width = <1>; 56 reg-io-width = <1>;
58 status = "disabled"; 57 status = "disabled";
59 }; 58 };
60 59
61 timer@d0020300 { 60 timer@20300 {
62 marvell,timer-25Mhz; 61 marvell,timer-25Mhz;
63 }; 62 };
64 63
65 coreclk: mvebu-sar@d0018230 { 64 coreclk: mvebu-sar@18230 {
66 compatible = "marvell,armada-xp-core-clock"; 65 compatible = "marvell,armada-xp-core-clock";
67 reg = <0xd0018230 0x08>; 66 reg = <0x18230 0x08>;
68 #clock-cells = <1>; 67 #clock-cells = <1>;
69 }; 68 };
70 69
71 cpuclk: clock-complex@d0018700 { 70 cpuclk: clock-complex@18700 {
72 #clock-cells = <1>; 71 #clock-cells = <1>;
73 compatible = "marvell,armada-xp-cpu-clock"; 72 compatible = "marvell,armada-xp-cpu-clock";
74 reg = <0xd0018700 0xA0>; 73 reg = <0x18700 0xA0>;
75 clocks = <&coreclk 1>; 74 clocks = <&coreclk 1>;
76 }; 75 };
77 76
78 gateclk: clock-gating-control@d0018220 { 77 gateclk: clock-gating-control@18220 {
79 compatible = "marvell,armada-xp-gating-clock"; 78 compatible = "marvell,armada-xp-gating-clock";
80 reg = <0xd0018220 0x4>; 79 reg = <0x18220 0x4>;
81 clocks = <&coreclk 0>; 80 clocks = <&coreclk 0>;
82 #clock-cells = <1>; 81 #clock-cells = <1>;
83 }; 82 };
84 83
85 system-controller@d0018200 { 84 system-controller@18200 {
86 compatible = "marvell,armada-370-xp-system-controller"; 85 compatible = "marvell,armada-370-xp-system-controller";
87 reg = <0xd0018200 0x500>; 86 reg = <0x18200 0x500>;
88 }; 87 };
89 88
90 ethernet@d0030000 { 89 ethernet@30000 {
91 compatible = "marvell,armada-370-neta"; 90 compatible = "marvell,armada-370-neta";
92 reg = <0xd0030000 0x2500>; 91 reg = <0x30000 0x2500>;
93 interrupts = <12>; 92 interrupts = <12>;
94 clocks = <&gateclk 2>; 93 clocks = <&gateclk 2>;
95 status = "disabled"; 94 status = "disabled";
96 };
97
98 xor@d0060900 {
99 compatible = "marvell,orion-xor";
100 reg = <0xd0060900 0x100
101 0xd0060b00 0x100>;
102 clocks = <&gateclk 22>;
103 status = "okay";
104
105 xor10 {
106 interrupts = <51>;
107 dmacap,memcpy;
108 dmacap,xor;
109 };
110 xor11 {
111 interrupts = <52>;
112 dmacap,memcpy;
113 dmacap,xor;
114 dmacap,memset;
115 }; 95 };
116 };
117 96
118 xor@d00f0900 { 97 xor@60900 {
119 compatible = "marvell,orion-xor"; 98 compatible = "marvell,orion-xor";
120 reg = <0xd00F0900 0x100 99 reg = <0x60900 0x100
121 0xd00F0B00 0x100>; 100 0x60b00 0x100>;
122 clocks = <&gateclk 28>; 101 clocks = <&gateclk 22>;
123 status = "okay"; 102 status = "okay";
103
104 xor10 {
105 interrupts = <51>;
106 dmacap,memcpy;
107 dmacap,xor;
108 };
109 xor11 {
110 interrupts = <52>;
111 dmacap,memcpy;
112 dmacap,xor;
113 dmacap,memset;
114 };
115 };
124 116
125 xor00 { 117 xor@f0900 {
126 interrupts = <94>; 118 compatible = "marvell,orion-xor";
127 dmacap,memcpy; 119 reg = <0xF0900 0x100
128 dmacap,xor; 120 0xF0B00 0x100>;
121 clocks = <&gateclk 28>;
122 status = "okay";
123
124 xor00 {
125 interrupts = <94>;
126 dmacap,memcpy;
127 dmacap,xor;
128 };
129 xor01 {
130 interrupts = <95>;
131 dmacap,memcpy;
132 dmacap,xor;
133 dmacap,memset;
134 };
129 }; 135 };
130 xor01 { 136
131 interrupts = <95>; 137 usb@50000 {
132 dmacap,memcpy; 138 clocks = <&gateclk 18>;
133 dmacap,xor;
134 dmacap,memset;
135 }; 139 };
136 };
137 140
138 usb@d0050000 { 141 usb@51000 {
139 clocks = <&gateclk 18>; 142 clocks = <&gateclk 19>;
140 }; 143 };
141 144
142 usb@d0051000 { 145 usb@52000 {
143 clocks = <&gateclk 19>; 146 compatible = "marvell,orion-ehci";
144 }; 147 reg = <0x52000 0x500>;
148 interrupts = <47>;
149 clocks = <&gateclk 20>;
150 status = "disabled";
151 };
145 152
146 usb@d0052000 { 153 thermal@182b0 {
147 compatible = "marvell,orion-ehci"; 154 compatible = "marvell,armadaxp-thermal";
148 reg = <0xd0052000 0x500>; 155 reg = <0x182b0 0x4
149 interrupts = <47>; 156 0x184d0 0x4>;
150 clocks = <&gateclk 20>; 157 status = "okay";
151 status = "disabled"; 158 };
152 }; 159 };
153
154 }; 160 };
155}; 161};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index f7509cafc377..6cab46849cdb 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -50,6 +50,11 @@
50 #clock-cells = <1>; 50 #clock-cells = <1>;
51 }; 51 };
52 52
53 thermal: thermal@d001c {
54 compatible = "marvell,dove-thermal";
55 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
56 };
57
53 uart0: serial@12000 { 58 uart0: serial@12000 {
54 compatible = "ns16550a"; 59 compatible = "ns16550a";
55 reg = <0x12000 0x100>; 60 reg = <0x12000 0x100>;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 192cf76fbf93..23991e45bc55 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,12 @@
49 }; 49 };
50 }; 50 };
51 51
52 thermal@10078 {
53 compatible = "marvell,kirkwood-thermal";
54 reg = <0x10078 0x4>;
55 status = "okay";
56 };
57
52 i2c@11100 { 58 i2c@11100 {
53 compatible = "marvell,mv64xxx-i2c"; 59 compatible = "marvell,mv64xxx-i2c";
54 reg = <0x11100 0x20>; 60 reg = <0x11100 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index bd83b8fc7c83..c3573be7b92c 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -77,6 +77,7 @@
77 }; 77 };
78 78
79 nand@3000000 { 79 nand@3000000 {
80 chip-delay = <40>;
80 status = "okay"; 81 status = "okay";
81 82
82 partition@0 { 83 partition@0 {
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 9555a86297c2..44fd97dfc1f3 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -69,6 +69,10 @@
69 status = "okay"; 69 status = "okay";
70 nr-ports = <1>; 70 nr-ports = <1>;
71 }; 71 };
72
73 mvsdio@90000 {
74 status = "okay";
75 };
72 }; 76 };
73 77
74 gpio-leds { 78 gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 93c3afbef9ee..3694e94f6e99 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -96,11 +96,11 @@
96 marvell,function = "gpio"; 96 marvell,function = "gpio";
97 }; 97 };
98 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { 98 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
99 marvell,pins = "mpp44"; 99 marvell,pins = "mpp46";
100 marvell,function = "gpio"; 100 marvell,function = "gpio";
101 }; 101 };
102 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { 102 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
103 marvell,pins = "mpp45"; 103 marvell,pins = "mpp47";
104 marvell,function = "gpio"; 104 marvell,function = "gpio";
105 }; 105 };
106 106
@@ -157,14 +157,14 @@
157 gpios = <&gpio0 16 0>; 157 gpios = <&gpio0 16 0>;
158 linux,default-trigger = "default-on"; 158 linux,default-trigger = "default-on";
159 }; 159 };
160 health_led1 { 160 rebuild_led {
161 label = "status:white:rebuild_led";
162 gpios = <&gpio1 4 0>;
163 };
164 health_led {
161 label = "status:red:health_led"; 165 label = "status:red:health_led";
162 gpios = <&gpio1 5 0>; 166 gpios = <&gpio1 5 0>;
163 }; 167 };
164 health_led2 {
165 label = "status:white:health_led";
166 gpios = <&gpio1 4 0>;
167 };
168 backup_led { 168 backup_led {
169 label = "status:blue:backup_led"; 169 label = "status:blue:backup_led";
170 gpios = <&gpio0 15 0>; 170 gpios = <&gpio0 15 0>;
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 8aad00f81ed9..892c64e3f1e1 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -13,6 +13,9 @@
13 compatible = "marvell,orion5x"; 13 compatible = "marvell,orion5x";
14 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
15 15
16 aliases {
17 gpio0 = &gpio0;
18 };
16 intc: interrupt-controller { 19 intc: interrupt-controller {
17 compatible = "marvell,orion-intc", "marvell,intc"; 20 compatible = "marvell,orion-intc", "marvell,intc";
18 interrupt-controller; 21 interrupt-controller;
@@ -32,7 +35,9 @@
32 #gpio-cells = <2>; 35 #gpio-cells = <2>;
33 gpio-controller; 36 gpio-controller;
34 reg = <0x10100 0x40>; 37 reg = <0x10100 0x40>;
35 ngpio = <32>; 38 ngpios = <32>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
36 interrupts = <6>, <7>, <8>, <9>; 41 interrupts = <6>, <7>, <8>, <9>;
37 }; 42 };
38 43
@@ -69,6 +74,20 @@
69 status = "okay"; 74 status = "okay";
70 }; 75 };
71 76
77 ehci@50000 {
78 compatible = "marvell,orion-ehci";
79 reg = <0x50000 0x1000>;
80 interrupts = <17>;
81 status = "disabled";
82 };
83
84 ehci@a0000 {
85 compatible = "marvell,orion-ehci";
86 reg = <0xa0000 0x1000>;
87 interrupts = <12>;
88 status = "disabled";
89 };
90
72 sata@80000 { 91 sata@80000 {
73 compatible = "marvell,orion-sata"; 92 compatible = "marvell,orion-sata";
74 reg = <0x80000 0x5000>; 93 reg = <0x80000 0x5000>;
@@ -86,12 +105,31 @@
86 status = "disabled"; 105 status = "disabled";
87 }; 106 };
88 107
108 xor@60900 {
109 compatible = "marvell,orion-xor";
110 reg = <0x60900 0x100
111 0x60b00 0x100>;
112 status = "okay";
113
114 xor00 {
115 interrupts = <30>;
116 dmacap,memcpy;
117 dmacap,xor;
118 };
119 xor01 {
120 interrupts = <31>;
121 dmacap,memcpy;
122 dmacap,xor;
123 dmacap,memset;
124 };
125 };
126
89 crypto@90000 { 127 crypto@90000 {
90 compatible = "marvell,orion-crypto"; 128 compatible = "marvell,orion-crypto";
91 reg = <0x90000 0x10000>, 129 reg = <0x90000 0x10000>,
92 <0xf2200000 0x800>; 130 <0xf2200000 0x800>;
93 reg-names = "regs", "sram"; 131 reg-names = "regs", "sram";
94 interrupts = <22>; 132 interrupts = <28>;
95 status = "okay"; 133 status = "okay";
96 }; 134 };
97 }; 135 };
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi
new file mode 100644
index 000000000000..15994158a998
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton64.dtsi
@@ -0,0 +1,13 @@
1/*
2 * Skeleton device tree in the 64 bits version; the bare minimum
3 * needed to boot; just include and add a compatible value. The
4 * bootloader will typically populate the memory node.
5 */
6
7/ {
8 #address-cells = <2>;
9 #size-cells = <2>;
10 chosen { };
11 aliases { };
12 memory { device_type = "memory"; reg = <0 0>; };
13};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 05:26:15 -0400