1 files changed, 119 insertions, 65 deletions
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1c8afe2ffebc..26ad06fc147e 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -26,87 +26,141 @@
        memory {
                device_type = "memory";
                /*
-                 * 4 GB of plug-in RAM modules by default but only 3GB
+                 * 8 GB of plug-in RAM modules by default.The amount
-                 * are visible, the amount of memory available can be
+                 * of memory available can be changed by the
-                 * changed by the bootloader according the size of the
+                 * bootloader according the size of the module
-                 * module actually plugged
+                 * actually plugged. Only 7GB are usable because
+                 * addresses from 0xC0000000 to 0xffffffff are used by
+                 * the internal registers of the SoC.
                 */
-                reg = <0x00000000 0xC0000000>;
+                reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
+                      <0x00000001 0x00000000 0x00000001 0x00000000>;
        };
        soc {
-                serial@d0012000 {
+                internal-regs {
-                        clock-frequency = <250000000>;
+                        serial@12000 {
-                        status = "okay";
+                                clock-frequency = <250000000>;
-                };
+                                status = "okay";
-                serial@d0012100 {
+                        };
-                        clock-frequency = <250000000>;
+                        serial@12100 {
-                        status = "okay";
+                                clock-frequency = <250000000>;
-                };
+                                status = "okay";
-                serial@d0012200 {
+                        };
-                        clock-frequency = <250000000>;
+                        serial@12200 {
-                        status = "okay";
+                                clock-frequency = <250000000>;
-                };
+                                status = "okay";
-                serial@d0012300 {
+                        };
-                        clock-frequency = <250000000>;
+                        serial@12300 {
-                        status = "okay";
+                                clock-frequency = <250000000>;
-                };
+                                status = "okay";
+                        };
-                sata@d00a0000 {
-                        nr-ports = <2>;
-                        status = "okay";
-                };
-                mdio {
+                        sata@a0000 {
-                        phy0: ethernet-phy@0 {
+                                nr-ports = <2>;
-                                reg = <16>;
+                                status = "okay";
                        };
-                        phy1: ethernet-phy@1 {
+                        mdio {
-                                reg = <17>;
+                                phy0: ethernet-phy@0 {
+                                        reg = <16>;
+                                };
+                                phy1: ethernet-phy@1 {
+                                        reg = <17>;
+                                };
+                                phy2: ethernet-phy@2 {
+                                        reg = <18>;
+                                };
+                                phy3: ethernet-phy@3 {
+                                        reg = <19>;
+                                };
                        };
-                        phy2: ethernet-phy@2 {
+                        ethernet@70000 {
-                                reg = <18>;
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
                        };
+                        ethernet@74000 {
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@30000 {
+                                status = "okay";
+                                phy = <&phy2>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@34000 {
+                                status = "okay";
+                                phy = <&phy3>;
+                                phy-mode = "rgmii-id";
+                        };
+                        spi0: spi@10600 {
+                                status = "okay";
-                        phy3: ethernet-phy@3 {
+                                spi-flash@0 {
-                                reg = <19>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "n25q128a13";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <108000000>;
+                                };
                        };
-                };
-                ethernet@d0070000 {
+                        devbus-bootcs@10400 {
-                        status = "okay";
+                                status = "okay";
-                        phy = <&phy0>;
+                                ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
-                        phy-mode = "rgmii-id";
-                };
+                                /* Device Bus parameters are required */
-                ethernet@d0074000 {
-                        status = "okay";
+                                /* Read parameters */
-                        phy = <&phy1>;
+                                devbus,bus-width    = <8>;
-                        phy-mode = "rgmii-id";
+                                devbus,turn-off-ps  = <60000>;
-                };
+                                devbus,badr-skew-ps = <0>;
-                ethernet@d0030000 {
+                                devbus,acc-first-ps = <124000>;
-                        status = "okay";
+                                devbus,acc-next-ps  = <248000>;
-                        phy = <&phy2>;
+                                devbus,rd-setup-ps  = <0>;
-                        phy-mode = "rgmii-id";
+                                devbus,rd-hold-ps   = <0>;
-                };
-                ethernet@d0034000 {
+                                /* Write parameters */
-                        status = "okay";
+                                devbus,sync-enable = <0>;
-                        phy = <&phy3>;
+                                devbus,wr-high-ps  = <60000>;
-                        phy-mode = "rgmii-id";
+                                devbus,wr-low-ps   = <60000>;
-                };
+                                devbus,ale-wr-ps   = <60000>;
+                                /* NOR 16 MiB */
+                                nor@0 {
+                                        compatible = "cfi-flash";
+                                        reg = <0 0x1000000>;
+                                        bank-width = <2>;
+                                };
+                        };
-                spi0: spi@d0010600 {
+                        pcie-controller {
-                        status = "okay";
+                                status = "okay";
-                        spi-flash@0 {
+                                /*
-                                #address-cells = <1>;
+                                 * The 3 slots are physically present as
-                                #size-cells = <1>;
+                                 * standard PCIe slots on the board.
-                                compatible = "n25q128a13";
+                                 */
-                                reg = <0>; /* Chip select 0 */
+                                pcie@1,0 {
-                                spi-max-frequency = <108000000>;
+                                        /* Port 0, Lane 0 */
+                                        status = "okay";
+                                };
+                                pcie@9,0 {
+                                        /* Port 2, Lane 0 */
+                                        status = "okay";
+                                };
+                                pcie@10,0 {
+                                        /* Port 3, Lane 0 */
+                                        status = "okay";
+                                };
                        };
                };
        };

diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 1c8afe2ffebc..26ad06fc147e 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -26,87 +26,141 @@
26		26
27	memory {	27	memory {
28	device_type = "memory";	28	device_type = "memory";
29
30	/*	29	/*
31	* 4 GB of plug-in RAM modules by default but only 3GB	30	* 8 GB of plug-in RAM modules by default.The amount
32	* are visible, the amount of memory available can be	31	* of memory available can be changed by the
33	* changed by the bootloader according the size of the	32	* bootloader according the size of the module
34	* module actually plugged	33	* actually plugged. Only 7GB are usable because
		34	* addresses from 0xC0000000 to 0xffffffff are used by
		35	* the internal registers of the SoC.
35	*/	36	*/
36	reg = <0x00000000 0xC0000000>;	37	reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
		38	<0x00000001 0x00000000 0x00000001 0x00000000>;
37	};	39	};
38		40
39	soc {	41	soc {
40	serial@d0012000 {	42	internal-regs {
41	clock-frequency = <250000000>;	43	serial@12000 {
42	status = "okay";	44	clock-frequency = <250000000>;
43	};	45	status = "okay";
44	serial@d0012100 {	46	};
45	clock-frequency = <250000000>;	47	serial@12100 {
46	status = "okay";	48	clock-frequency = <250000000>;
47	};	49	status = "okay";
48	serial@d0012200 {	50	};
49	clock-frequency = <250000000>;	51	serial@12200 {
50	status = "okay";	52	clock-frequency = <250000000>;
51	};	53	status = "okay";
52	serial@d0012300 {	54	};
53	clock-frequency = <250000000>;	55	serial@12300 {
54	status = "okay";	56	clock-frequency = <250000000>;
55	};	57	status = "okay";
56		58	};
57	sata@d00a0000 {
58	nr-ports = <2>;
59	status = "okay";
60	};
61		59
62	mdio {	60	sata@a0000 {
63	phy0: ethernet-phy@0 {	61	nr-ports = <2>;
64	reg = <16>;	62	status = "okay";
65	};	63	};
66		64
67	phy1: ethernet-phy@1 {	65	mdio {
68	reg = <17>;	66	phy0: ethernet-phy@0 {
		67	reg = <16>;
		68	};
		69
		70	phy1: ethernet-phy@1 {
		71	reg = <17>;
		72	};
		73
		74	phy2: ethernet-phy@2 {
		75	reg = <18>;
		76	};
		77
		78	phy3: ethernet-phy@3 {
		79	reg = <19>;
		80	};
69	};	81	};
70		82
71	phy2: ethernet-phy@2 {	83	ethernet@70000 {
72	reg = <18>;	84	status = "okay";
		85	phy = <&phy0>;
		86	phy-mode = "rgmii-id";
73	};	87	};
		88	ethernet@74000 {
		89	status = "okay";
		90	phy = <&phy1>;
		91	phy-mode = "rgmii-id";
		92	};
		93	ethernet@30000 {
		94	status = "okay";
		95	phy = <&phy2>;
		96	phy-mode = "rgmii-id";
		97	};
		98	ethernet@34000 {
		99	status = "okay";
		100	phy = <&phy3>;
		101	phy-mode = "rgmii-id";
		102	};
		103
		104	spi0: spi@10600 {
		105	status = "okay";
74		106
75	phy3: ethernet-phy@3 {	107	spi-flash@0 {
76	reg = <19>;	108	#address-cells = <1>;
		109	#size-cells = <1>;
		110	compatible = "n25q128a13";
		111	reg = <0>; /* Chip select 0 */
		112	spi-max-frequency = <108000000>;
		113	};
77	};	114	};
78	};
79		115
80	ethernet@d0070000 {	116	devbus-bootcs@10400 {
81	status = "okay";	117	status = "okay";
82	phy = <&phy0>;	118	ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
83	phy-mode = "rgmii-id";	119
84	};	120	/* Device Bus parameters are required */
85	ethernet@d0074000 {	121
86	status = "okay";	122	/* Read parameters */
87	phy = <&phy1>;	123	devbus,bus-width = <8>;
88	phy-mode = "rgmii-id";	124	devbus,turn-off-ps = <60000>;
89	};	125	devbus,badr-skew-ps = <0>;
90	ethernet@d0030000 {	126	devbus,acc-first-ps = <124000>;
91	status = "okay";	127	devbus,acc-next-ps = <248000>;
92	phy = <&phy2>;	128	devbus,rd-setup-ps = <0>;
93	phy-mode = "rgmii-id";	129	devbus,rd-hold-ps = <0>;
94	};	130
95	ethernet@d0034000 {	131	/* Write parameters */
96	status = "okay";	132	devbus,sync-enable = <0>;
97	phy = <&phy3>;	133	devbus,wr-high-ps = <60000>;
98	phy-mode = "rgmii-id";	134	devbus,wr-low-ps = <60000>;
99	};	135	devbus,ale-wr-ps = <60000>;
		136
		137	/* NOR 16 MiB */
		138	nor@0 {
		139	compatible = "cfi-flash";
		140	reg = <0 0x1000000>;
		141	bank-width = <2>;
		142	};
		143	};
100		144
101	spi0: spi@d0010600 {	145	pcie-controller {
102	status = "okay";	146	status = "okay";
103		147
104	spi-flash@0 {	148	/*
105	#address-cells = <1>;	149	* The 3 slots are physically present as
106	#size-cells = <1>;	150	* standard PCIe slots on the board.
107	compatible = "n25q128a13";	151	*/
108	reg = <0>; /* Chip select 0 */	152	pcie@1,0 {
109	spi-max-frequency = <108000000>;	153	/* Port 0, Lane 0 */
		154	status = "okay";
		155	};
		156	pcie@9,0 {
		157	/* Port 2, Lane 0 */
		158	status = "okay";
		159	};
		160	pcie@10,0 {
		161	/* Port 3, Lane 0 */
		162	status = "okay";
		163	};
110	};	164	};
111	};	165	};
112	};	166	};