diff options
| author | Olof Johansson <olof@lixom.net> | 2013-04-18 02:26:57 -0400 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2013-04-18 02:27:52 -0400 |
| commit | db39ad7d418b3b64f92295c3d9d7d8595ff68f08 (patch) | |
| tree | 5357280b5edf0a5ddac4da422447f00bcf5c5190 | |
| parent | bf049ded36b2178e80bb9f227d4490714d838c11 (diff) | |
| parent | 74898364e717c6bd939bb88d95049fc91d2b4950 (diff) | |
Merge tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux into next/dt2
From Jason Cooper:
mvebu dt for v3.10 round 4
- mvebu LPAE 64bit dts file changes
* tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux: (52 commits)
ARM: dts: mvebu: Convert mvebu device tree files to 64 bits
ARM: dts: mvebu: introduce internal-regs node
ARM: dts: mvebu: Convert all the mvebu files to use the range property
ARM: dts: mvebu: move all peripherals inside soc
ARM: dts: mvebu: fix cpus section indentation
arm: mvebu: PCIe Device Tree informations for Armada XP GP
arm: mvebu: PCIe Device Tree informations for Armada 370 DB
arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
arm: mvebu: PCIe Device Tree informations for Armada XP DB
arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
arm: mvebu: add PCIe Device Tree informations for Armada XP
arm: mvebu: add PCIe Device Tree informations for Armada 370
ARM: mvebu: Align the internal registers virtual base to support LPAE
ARM: mvebu: Limit the DMA zone when LPAE is selected
arm: plat-orion: remove addr-map code
arm: mach-mv78xx0: convert to use the mvebu-mbus driver
arm: mach-orion5x: convert to use mvebu-mbus driver
arm: mach-dove: convert to use mvebu-mbus driver
arm: mach-kirkwood: convert to use mvebu-mbus driver
arm: mach-mvebu: convert to use mvebu-mbus driver
...
Signed-off-by: Olof Johansson <olof@lixom.net>
88 files changed, 2969 insertions, 1769 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 135dff88e882..398a9fbcd427 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -564,6 +564,7 @@ config ARCH_DOVE | |||
| 564 | select PINCTRL_DOVE | 564 | select PINCTRL_DOVE |
| 565 | select PLAT_ORION_LEGACY | 565 | select PLAT_ORION_LEGACY |
| 566 | select USB_ARCH_HAS_EHCI | 566 | select USB_ARCH_HAS_EHCI |
| 567 | select MVEBU_MBUS | ||
| 567 | help | 568 | help |
| 568 | Support for the Marvell Dove SoC 88AP510 | 569 | Support for the Marvell Dove SoC 88AP510 |
| 569 | 570 | ||
| @@ -577,6 +578,7 @@ config ARCH_KIRKWOOD | |||
| 577 | select PINCTRL | 578 | select PINCTRL |
| 578 | select PINCTRL_KIRKWOOD | 579 | select PINCTRL_KIRKWOOD |
| 579 | select PLAT_ORION_LEGACY | 580 | select PLAT_ORION_LEGACY |
| 581 | select MVEBU_MBUS | ||
| 580 | help | 582 | help |
| 581 | Support for the following Marvell Kirkwood series SoCs: | 583 | Support for the following Marvell Kirkwood series SoCs: |
| 582 | 88F6180, 88F6192 and 88F6281. | 584 | 88F6180, 88F6192 and 88F6281. |
| @@ -588,6 +590,7 @@ config ARCH_MV78XX0 | |||
| 588 | select GENERIC_CLOCKEVENTS | 590 | select GENERIC_CLOCKEVENTS |
| 589 | select PCI | 591 | select PCI |
| 590 | select PLAT_ORION_LEGACY | 592 | select PLAT_ORION_LEGACY |
| 593 | select MVEBU_MBUS | ||
| 591 | help | 594 | help |
| 592 | Support for the following Marvell MV78xx0 series SoCs: | 595 | Support for the following Marvell MV78xx0 series SoCs: |
| 593 | MV781x0, MV782x0. | 596 | MV781x0, MV782x0. |
| @@ -600,6 +603,7 @@ config ARCH_ORION5X | |||
| 600 | select GENERIC_CLOCKEVENTS | 603 | select GENERIC_CLOCKEVENTS |
| 601 | select PCI | 604 | select PCI |
| 602 | select PLAT_ORION_LEGACY | 605 | select PLAT_ORION_LEGACY |
| 606 | select MVEBU_MBUS | ||
| 603 | help | 607 | help |
| 604 | Support for the following Marvell Orion 5x series SoCs: | 608 | Support for the following Marvell Orion 5x series SoCs: |
| 605 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), | 609 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index e34b280ce6ec..2353b1f13704 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts | |||
| @@ -30,68 +30,87 @@ | |||
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | soc { | 32 | soc { |
| 33 | serial@d0012000 { | 33 | internal-regs { |
| 34 | clock-frequency = <200000000>; | 34 | serial@12000 { |
| 35 | status = "okay"; | 35 | clock-frequency = <200000000>; |
| 36 | }; | 36 | status = "okay"; |
| 37 | sata@d00a0000 { | 37 | }; |
| 38 | nr-ports = <2>; | 38 | sata@a0000 { |
| 39 | status = "okay"; | 39 | nr-ports = <2>; |
| 40 | }; | 40 | status = "okay"; |
| 41 | }; | ||
| 41 | 42 | ||
| 42 | mdio { | 43 | mdio { |
| 43 | phy0: ethernet-phy@0 { | 44 | phy0: ethernet-phy@0 { |
| 44 | reg = <0>; | 45 | reg = <0>; |
| 46 | }; | ||
| 47 | |||
| 48 | phy1: ethernet-phy@1 { | ||
| 49 | reg = <1>; | ||
| 50 | }; | ||
| 45 | }; | 51 | }; |
| 46 | 52 | ||
| 47 | phy1: ethernet-phy@1 { | 53 | ethernet@70000 { |
| 48 | reg = <1>; | 54 | status = "okay"; |
| 55 | phy = <&phy0>; | ||
| 56 | phy-mode = "rgmii-id"; | ||
| 57 | }; | ||
| 58 | ethernet@74000 { | ||
| 59 | status = "okay"; | ||
| 60 | phy = <&phy1>; | ||
| 61 | phy-mode = "rgmii-id"; | ||
| 49 | }; | 62 | }; |
| 50 | }; | ||
| 51 | 63 | ||
| 52 | ethernet@d0070000 { | 64 | mvsdio@d4000 { |
| 53 | status = "okay"; | 65 | pinctrl-0 = <&sdio_pins1>; |
| 54 | phy = <&phy0>; | 66 | pinctrl-names = "default"; |
| 55 | phy-mode = "rgmii-id"; | 67 | /* |
| 56 | }; | 68 | * This device is disabled by default, because |
| 57 | ethernet@d0074000 { | 69 | * using the SD card connector requires |
| 58 | status = "okay"; | 70 | * changing the default CON40 connector |
| 59 | phy = <&phy1>; | 71 | * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a |
| 60 | phy-mode = "rgmii-id"; | 72 | * different connector |
| 61 | }; | 73 | * "DB-88F6710_MPP_RGMII_SD_Jumper". |
| 74 | */ | ||
| 75 | status = "disabled"; | ||
| 76 | /* No CD or WP GPIOs */ | ||
| 77 | }; | ||
| 62 | 78 | ||
| 63 | mvsdio@d00d4000 { | 79 | usb@50000 { |
| 64 | pinctrl-0 = <&sdio_pins1>; | 80 | status = "okay"; |
| 65 | pinctrl-names = "default"; | 81 | }; |
| 66 | /* | ||
| 67 | * This device is disabled by default, because | ||
| 68 | * using the SD card connector requires | ||
| 69 | * changing the default CON40 connector | ||
| 70 | * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a | ||
| 71 | * different connector | ||
| 72 | * "DB-88F6710_MPP_RGMII_SD_Jumper". | ||
| 73 | */ | ||
| 74 | status = "disabled"; | ||
| 75 | /* No CD or WP GPIOs */ | ||
| 76 | }; | ||
| 77 | 82 | ||
| 78 | usb@d0050000 { | 83 | usb@51000 { |
| 79 | status = "okay"; | 84 | status = "okay"; |
| 80 | }; | 85 | }; |
| 81 | 86 | ||
| 82 | usb@d0051000 { | 87 | spi0: spi@10600 { |
| 83 | status = "okay"; | 88 | status = "okay"; |
| 84 | }; | ||
| 85 | 89 | ||
| 86 | spi0: spi@d0010600 { | 90 | spi-flash@0 { |
| 87 | status = "okay"; | 91 | #address-cells = <1>; |
| 92 | #size-cells = <1>; | ||
| 93 | compatible = "mx25l25635e"; | ||
| 94 | reg = <0>; /* Chip select 0 */ | ||
| 95 | spi-max-frequency = <50000000>; | ||
| 96 | }; | ||
| 97 | }; | ||
| 88 | 98 | ||
| 89 | spi-flash@0 { | 99 | pcie-controller { |
| 90 | #address-cells = <1>; | 100 | status = "okay"; |
| 91 | #size-cells = <1>; | 101 | /* |
| 92 | compatible = "mx25l25635e"; | 102 | * The two PCIe units are accessible through |
| 93 | reg = <0>; /* Chip select 0 */ | 103 | * both standard PCIe slots and mini-PCIe |
| 94 | spi-max-frequency = <50000000>; | 104 | * slots on the board. |
| 105 | */ | ||
| 106 | pcie@1,0 { | ||
| 107 | /* Port 0, Lane 0 */ | ||
| 108 | status = "okay"; | ||
| 109 | }; | ||
| 110 | pcie@2,0 { | ||
| 111 | /* Port 1, Lane 0 */ | ||
| 112 | status = "okay"; | ||
| 113 | }; | ||
| 95 | }; | 114 | }; |
| 96 | }; | 115 | }; |
| 97 | }; | 116 | }; |
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index dd0c57dd9f30..14e36e19d515 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts | |||
| @@ -25,50 +25,116 @@ | |||
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | soc { | 27 | soc { |
| 28 | serial@d0012000 { | 28 | internal-regs { |
| 29 | clock-frequency = <200000000>; | 29 | serial@12000 { |
| 30 | status = "okay"; | 30 | clock-frequency = <200000000>; |
| 31 | }; | 31 | status = "okay"; |
| 32 | timer@d0020300 { | ||
| 33 | clock-frequency = <600000000>; | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | mdio { | ||
| 37 | phy0: ethernet-phy@0 { | ||
| 38 | reg = <0>; | ||
| 39 | }; | 32 | }; |
| 33 | timer@20300 { | ||
| 34 | clock-frequency = <600000000>; | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | pinctrl { | ||
| 39 | pwr_led_pin: pwr-led-pin { | ||
| 40 | marvell,pins = "mpp63"; | ||
| 41 | marvell,function = "gpo"; | ||
| 42 | }; | ||
| 40 | 43 | ||
| 41 | phy1: ethernet-phy@1 { | 44 | stat_led_pins: stat-led-pins { |
| 42 | reg = <1>; | 45 | marvell,pins = "mpp64", "mpp65"; |
| 46 | marvell,function = "gpio"; | ||
| 47 | }; | ||
| 43 | }; | 48 | }; |
| 44 | }; | ||
| 45 | ethernet@d0070000 { | ||
| 46 | status = "okay"; | ||
| 47 | phy = <&phy0>; | ||
| 48 | phy-mode = "rgmii-id"; | ||
| 49 | }; | ||
| 50 | ethernet@d0074000 { | ||
| 51 | status = "okay"; | ||
| 52 | phy = <&phy1>; | ||
| 53 | phy-mode = "rgmii-id"; | ||
| 54 | }; | ||
| 55 | 49 | ||
| 56 | mvsdio@d00d4000 { | 50 | gpio_leds { |
| 57 | pinctrl-0 = <&sdio_pins2>; | 51 | compatible = "gpio-leds"; |
| 58 | pinctrl-names = "default"; | 52 | pinctrl-names = "default"; |
| 59 | status = "okay"; | 53 | pinctrl-0 = <&pwr_led_pin &stat_led_pins>; |
| 60 | /* | ||
| 61 | * No CD or WP GPIOs: SDIO interface used for | ||
| 62 | * Wifi/Bluetooth chip | ||
| 63 | */ | ||
| 64 | }; | ||
| 65 | 54 | ||
| 66 | usb@d0050000 { | 55 | green_pwr_led { |
| 67 | status = "okay"; | 56 | label = "mirabox:green:pwr"; |
| 68 | }; | 57 | gpios = <&gpio1 31 1>; |
| 58 | linux,default-trigger = "heartbeat"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | blue_stat_led { | ||
| 62 | label = "mirabox:blue:stat"; | ||
| 63 | gpios = <&gpio2 0 1>; | ||
| 64 | linux,default-trigger = "cpu0"; | ||
| 65 | }; | ||
| 66 | |||
| 67 | green_stat_led { | ||
| 68 | label = "mirabox:green:stat"; | ||
| 69 | gpios = <&gpio2 1 1>; | ||
| 70 | default-state = "off"; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
| 74 | mdio { | ||
| 75 | phy0: ethernet-phy@0 { | ||
| 76 | reg = <0>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | phy1: ethernet-phy@1 { | ||
| 80 | reg = <1>; | ||
| 81 | }; | ||
| 82 | }; | ||
| 83 | ethernet@70000 { | ||
| 84 | status = "okay"; | ||
| 85 | phy = <&phy0>; | ||
| 86 | phy-mode = "rgmii-id"; | ||
| 87 | }; | ||
| 88 | ethernet@74000 { | ||
| 89 | status = "okay"; | ||
| 90 | phy = <&phy1>; | ||
| 91 | phy-mode = "rgmii-id"; | ||
| 92 | }; | ||
| 93 | |||
| 94 | mvsdio@d4000 { | ||
| 95 | pinctrl-0 = <&sdio_pins3>; | ||
| 96 | pinctrl-names = "default"; | ||
| 97 | status = "okay"; | ||
| 98 | /* | ||
| 99 | * No CD or WP GPIOs: SDIO interface used for | ||
| 100 | * Wifi/Bluetooth chip | ||
| 101 | */ | ||
| 102 | }; | ||
| 103 | |||
| 104 | usb@50000 { | ||
| 105 | status = "okay"; | ||
| 106 | }; | ||
| 69 | 107 | ||
| 70 | usb@d0051000 { | 108 | usb@51000 { |
| 71 | status = "okay"; | 109 | status = "okay"; |
| 110 | }; | ||
| 111 | |||
| 112 | i2c@11000 { | ||
| 113 | status = "okay"; | ||
| 114 | clock-frequency = <100000>; | ||
| 115 | pca9505: pca9505@25 { | ||
| 116 | compatible = "nxp,pca9505"; | ||
| 117 | gpio-controller; | ||
| 118 | #gpio-cells = <2>; | ||
| 119 | reg = <0x25>; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | pcie-controller { | ||
| 124 | status = "okay"; | ||
| 125 | |||
| 126 | /* Internal mini-PCIe connector */ | ||
| 127 | pcie@1,0 { | ||
| 128 | /* Port 0, Lane 0 */ | ||
| 129 | status = "okay"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | /* Connected on the PCB to a USB 3.0 XHCI controller */ | ||
| 133 | pcie@2,0 { | ||
| 134 | /* Port 1, Lane 0 */ | ||
| 135 | status = "okay"; | ||
| 136 | }; | ||
| 137 | }; | ||
| 72 | }; | 138 | }; |
| 73 | }; | 139 | }; |
| 74 | }; | 140 | }; |
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 070bba4f2585..130f8390a7e4 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts | |||
| @@ -28,49 +28,62 @@ | |||
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | soc { | 30 | soc { |
| 31 | serial@d0012000 { | 31 | internal-regs { |
| 32 | clock-frequency = <200000000>; | 32 | serial@12000 { |
| 33 | status = "okay"; | 33 | clock-frequency = <200000000>; |
| 34 | }; | 34 | status = "okay"; |
| 35 | sata@d00a0000 { | 35 | }; |
| 36 | nr-ports = <2>; | 36 | sata@a0000 { |
| 37 | status = "okay"; | 37 | nr-ports = <2>; |
| 38 | }; | 38 | status = "okay"; |
| 39 | }; | ||
| 39 | 40 | ||
| 40 | mdio { | 41 | mdio { |
| 41 | phy0: ethernet-phy@0 { | 42 | phy0: ethernet-phy@0 { |
| 42 | reg = <0>; | 43 | reg = <0>; |
| 44 | }; | ||
| 45 | |||
| 46 | phy1: ethernet-phy@1 { | ||
| 47 | reg = <1>; | ||
| 48 | }; | ||
| 43 | }; | 49 | }; |
| 44 | 50 | ||
| 45 | phy1: ethernet-phy@1 { | 51 | ethernet@70000 { |
| 46 | reg = <1>; | 52 | status = "okay"; |
| 53 | phy = <&phy0>; | ||
| 54 | phy-mode = "sgmii"; | ||
| 55 | }; | ||
| 56 | ethernet@74000 { | ||
| 57 | status = "okay"; | ||
| 58 | phy = <&phy1>; | ||
| 59 | phy-mode = "rgmii-id"; | ||
| 47 | }; | 60 | }; |
| 48 | }; | ||
| 49 | 61 | ||
| 50 | ethernet@d0070000 { | 62 | mvsdio@d4000 { |
| 51 | status = "okay"; | 63 | pinctrl-0 = <&sdio_pins1>; |
| 52 | phy = <&phy0>; | 64 | pinctrl-names = "default"; |
| 53 | phy-mode = "sgmii"; | 65 | status = "okay"; |
| 54 | }; | 66 | /* No CD or WP GPIOs */ |
| 55 | ethernet@d0074000 { | 67 | }; |
| 56 | status = "okay"; | ||
| 57 | phy = <&phy1>; | ||
| 58 | phy-mode = "rgmii-id"; | ||
| 59 | }; | ||
| 60 | 68 | ||
| 61 | mvsdio@d00d4000 { | 69 | usb@50000 { |
| 62 | pinctrl-0 = <&sdio_pins1>; | 70 | status = "okay"; |
| 63 | pinctrl-names = "default"; | 71 | }; |
| 64 | status = "okay"; | ||
| 65 | /* No CD or WP GPIOs */ | ||
| 66 | }; | ||
| 67 | 72 | ||
| 68 | usb@d0050000 { | 73 | usb@51000 { |
| 69 | status = "okay"; | 74 | status = "okay"; |
| 70 | }; | 75 | }; |
| 71 | 76 | ||
| 72 | usb@d0051000 { | 77 | gpio-keys { |
| 73 | status = "okay"; | 78 | compatible = "gpio-keys"; |
| 79 | #address-cells = <1>; | ||
| 80 | #size-cells = <0>; | ||
| 81 | button@1 { | ||
| 82 | label = "Software Button"; | ||
| 83 | linux,code = <116>; | ||
| 84 | gpios = <&gpio0 6 1>; | ||
| 85 | }; | ||
| 86 | }; | ||
| 74 | }; | 87 | }; |
| 75 | }; | 88 | }; |
| 76 | }; | 89 | }; |
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 5b708208b607..272bbc65fab0 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | * 370 and Armada XP SoC. | 16 | * 370 and Armada XP SoC. |
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | /include/ "skeleton.dtsi" | 19 | /include/ "skeleton64.dtsi" |
| 20 | 20 | ||
| 21 | / { | 21 | / { |
| 22 | model = "Marvell Armada 370 and XP SoC"; | 22 | model = "Marvell Armada 370 and XP SoC"; |
| @@ -28,159 +28,203 @@ | |||
| 28 | }; | 28 | }; |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | mpic: interrupt-controller@d0020000 { | ||
| 32 | compatible = "marvell,mpic"; | ||
| 33 | #interrupt-cells = <1>; | ||
| 34 | #size-cells = <1>; | ||
| 35 | interrupt-controller; | ||
| 36 | }; | ||
| 37 | |||
| 38 | coherency-fabric@d0020200 { | ||
| 39 | compatible = "marvell,coherency-fabric"; | ||
| 40 | reg = <0xd0020200 0xb0>, | ||
| 41 | <0xd0021810 0x1c>; | ||
| 42 | }; | ||
| 43 | |||
| 44 | soc { | 31 | soc { |
| 45 | #address-cells = <1>; | 32 | #address-cells = <1>; |
| 46 | #size-cells = <1>; | 33 | #size-cells = <1>; |
| 47 | compatible = "simple-bus"; | 34 | compatible = "simple-bus"; |
| 48 | interrupt-parent = <&mpic>; | 35 | interrupt-parent = <&mpic>; |
| 49 | ranges; | 36 | ranges = <0 0 0xd0000000 0x100000>; |
| 50 | 37 | ||
| 51 | serial@d0012000 { | 38 | internal-regs { |
| 39 | compatible = "simple-bus"; | ||
| 40 | #address-cells = <1>; | ||
| 41 | #size-cells = <1>; | ||
| 42 | ranges; | ||
| 43 | |||
| 44 | mpic: interrupt-controller@20000 { | ||
| 45 | compatible = "marvell,mpic"; | ||
| 46 | #interrupt-cells = <1>; | ||
| 47 | #size-cells = <1>; | ||
| 48 | interrupt-controller; | ||
| 49 | }; | ||
| 50 | |||
| 51 | coherency-fabric@20200 { | ||
| 52 | compatible = "marvell,coherency-fabric"; | ||
| 53 | reg = <0x20200 0xb0>, <0x21810 0x1c>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | serial@12000 { | ||
| 52 | compatible = "snps,dw-apb-uart"; | 57 | compatible = "snps,dw-apb-uart"; |
| 53 | reg = <0xd0012000 0x100>; | 58 | reg = <0x12000 0x100>; |
| 54 | reg-shift = <2>; | 59 | reg-shift = <2>; |
| 55 | interrupts = <41>; | 60 | interrupts = <41>; |
| 56 | reg-io-width = <1>; | 61 | reg-io-width = <1>; |
| 57 | status = "disabled"; | 62 | status = "disabled"; |
| 58 | }; | 63 | }; |
| 59 | serial@d0012100 { | 64 | serial@12100 { |
| 60 | compatible = "snps,dw-apb-uart"; | 65 | compatible = "snps,dw-apb-uart"; |
| 61 | reg = <0xd0012100 0x100>; | 66 | reg = <0x12100 0x100>; |
| 62 | reg-shift = <2>; | 67 | reg-shift = <2>; |
| 63 | interrupts = <42>; | 68 | interrupts = <42>; |
| 64 | reg-io-width = <1>; | 69 | reg-io-width = <1>; |
| 65 | status = "disabled"; | 70 | status = "disabled"; |
| 66 | }; | 71 | }; |
| 67 | 72 | ||
| 68 | timer@d0020300 { | 73 | timer@20300 { |
| 69 | compatible = "marvell,armada-370-xp-timer"; | 74 | compatible = "marvell,armada-370-xp-timer"; |
| 70 | reg = <0xd0020300 0x30>, | 75 | reg = <0x20300 0x30>, <0x21040 0x30>; |
| 71 | <0xd0021040 0x30>; | 76 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; |
| 72 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; | 77 | clocks = <&coreclk 2>; |
| 73 | clocks = <&coreclk 2>; | 78 | }; |
| 74 | }; | 79 | |
| 75 | 80 | sata@a0000 { | |
| 76 | addr-decoding@d0020000 { | 81 | compatible = "marvell,orion-sata"; |
| 77 | compatible = "marvell,armada-addr-decoding-controller"; | 82 | reg = <0xa0000 0x2400>; |
| 78 | reg = <0xd0020000 0x258>; | 83 | interrupts = <55>; |
| 79 | }; | 84 | clocks = <&gateclk 15>, <&gateclk 30>; |
| 80 | 85 | clock-names = "0", "1"; | |
| 81 | sata@d00a0000 { | 86 | status = "disabled"; |
| 82 | compatible = "marvell,orion-sata"; | 87 | }; |
| 83 | reg = <0xd00a0000 0x2400>; | ||
| 84 | interrupts = <55>; | ||
| 85 | clocks = <&gateclk 15>, <&gateclk 30>; | ||
| 86 | clock-names = "0", "1"; | ||
| 87 | status = "disabled"; | ||
| 88 | }; | ||
| 89 | 88 | ||
| 90 | mdio { | 89 | mdio { |
| 91 | #address-cells = <1>; | 90 | #address-cells = <1>; |
| 92 | #size-cells = <0>; | 91 | #size-cells = <0>; |
| 93 | compatible = "marvell,orion-mdio"; | 92 | compatible = "marvell,orion-mdio"; |
| 94 | reg = <0xd0072004 0x4>; | 93 | reg = <0x72004 0x4>; |
| 95 | }; | 94 | }; |
| 96 | 95 | ||
| 97 | ethernet@d0070000 { | 96 | ethernet@70000 { |
| 98 | compatible = "marvell,armada-370-neta"; | 97 | compatible = "marvell,armada-370-neta"; |
| 99 | reg = <0xd0070000 0x2500>; | 98 | reg = <0x70000 0x2500>; |
| 100 | interrupts = <8>; | 99 | interrupts = <8>; |
| 101 | clocks = <&gateclk 4>; | 100 | clocks = <&gateclk 4>; |
| 102 | status = "disabled"; | 101 | status = "disabled"; |
| 103 | }; | 102 | }; |
| 104 | 103 | ||
| 105 | ethernet@d0074000 { | 104 | ethernet@74000 { |
| 106 | compatible = "marvell,armada-370-neta"; | 105 | compatible = "marvell,armada-370-neta"; |
| 107 | reg = <0xd0074000 0x2500>; | 106 | reg = <0x74000 0x2500>; |
| 108 | interrupts = <10>; | 107 | interrupts = <10>; |
| 109 | clocks = <&gateclk 3>; | 108 | clocks = <&gateclk 3>; |
| 110 | status = "disabled"; | 109 | status = "disabled"; |
| 111 | }; | 110 | }; |
| 112 | 111 | ||
| 113 | i2c0: i2c@d0011000 { | 112 | i2c0: i2c@11000 { |
| 114 | compatible = "marvell,mv64xxx-i2c"; | 113 | compatible = "marvell,mv64xxx-i2c"; |
| 115 | reg = <0xd0011000 0x20>; | 114 | reg = <0x11000 0x20>; |
| 116 | #address-cells = <1>; | 115 | #address-cells = <1>; |
| 117 | #size-cells = <0>; | 116 | #size-cells = <0>; |
| 118 | interrupts = <31>; | 117 | interrupts = <31>; |
| 119 | timeout-ms = <1000>; | 118 | timeout-ms = <1000>; |
| 120 | clocks = <&coreclk 0>; | 119 | clocks = <&coreclk 0>; |
| 121 | status = "disabled"; | 120 | status = "disabled"; |
| 122 | }; | 121 | }; |
| 123 | 122 | ||
| 124 | i2c1: i2c@d0011100 { | 123 | i2c1: i2c@11100 { |
| 125 | compatible = "marvell,mv64xxx-i2c"; | 124 | compatible = "marvell,mv64xxx-i2c"; |
| 126 | reg = <0xd0011100 0x20>; | 125 | reg = <0x11100 0x20>; |
| 127 | #address-cells = <1>; | 126 | #address-cells = <1>; |
| 128 | #size-cells = <0>; | 127 | #size-cells = <0>; |
| 129 | interrupts = <32>; | 128 | interrupts = <32>; |
| 130 | timeout-ms = <1000>; | 129 | timeout-ms = <1000>; |
| 131 | clocks = <&coreclk 0>; | 130 | clocks = <&coreclk 0>; |
| 132 | status = "disabled"; | 131 | status = "disabled"; |
| 133 | }; | 132 | }; |
| 134 | 133 | ||
| 135 | rtc@10300 { | 134 | rtc@10300 { |
| 136 | compatible = "marvell,orion-rtc"; | 135 | compatible = "marvell,orion-rtc"; |
| 137 | reg = <0xd0010300 0x20>; | 136 | reg = <0x10300 0x20>; |
| 138 | interrupts = <50>; | 137 | interrupts = <50>; |
| 139 | }; | 138 | }; |
| 140 | 139 | ||
| 141 | mvsdio@d00d4000 { | 140 | mvsdio@d4000 { |
| 142 | compatible = "marvell,orion-sdio"; | 141 | compatible = "marvell,orion-sdio"; |
| 143 | reg = <0xd00d4000 0x200>; | 142 | reg = <0xd4000 0x200>; |
| 144 | interrupts = <54>; | 143 | interrupts = <54>; |
| 145 | clocks = <&gateclk 17>; | 144 | clocks = <&gateclk 17>; |
| 146 | status = "disabled"; | 145 | status = "disabled"; |
| 147 | }; | 146 | }; |
| 148 | |||
| 149 | usb@d0050000 { | ||
| 150 | compatible = "marvell,orion-ehci"; | ||
| 151 | reg = <0xd0050000 0x500>; | ||
| 152 | interrupts = <45>; | ||
| 153 | status = "disabled"; | ||
| 154 | }; | ||
| 155 | |||
| 156 | usb@d0051000 { | ||
| 157 | compatible = "marvell,orion-ehci"; | ||
| 158 | reg = <0xd0051000 0x500>; | ||
| 159 | interrupts = <46>; | ||
| 160 | status = "disabled"; | ||
| 161 | }; | ||
| 162 | 147 | ||
| 163 | spi0: spi@d0010600 { | 148 | usb@50000 { |
| 164 | compatible = "marvell,orion-spi"; | 149 | compatible = "marvell,orion-ehci"; |
| 165 | reg = <0xd0010600 0x28>; | 150 | reg = <0x50000 0x500>; |
| 166 | #address-cells = <1>; | 151 | interrupts = <45>; |
| 167 | #size-cells = <0>; | 152 | status = "disabled"; |
| 168 | cell-index = <0>; | 153 | }; |
| 169 | interrupts = <30>; | ||
| 170 | clocks = <&coreclk 0>; | ||
| 171 | status = "disabled"; | ||
| 172 | }; | ||
| 173 | 154 | ||
| 174 | spi1: spi@d0010680 { | 155 | usb@51000 { |
| 175 | compatible = "marvell,orion-spi"; | 156 | compatible = "marvell,orion-ehci"; |
| 176 | reg = <0xd0010680 0x28>; | 157 | reg = <0x51000 0x500>; |
| 177 | #address-cells = <1>; | 158 | interrupts = <46>; |
| 178 | #size-cells = <0>; | 159 | status = "disabled"; |
| 179 | cell-index = <1>; | 160 | }; |
| 180 | interrupts = <92>; | 161 | |
| 181 | clocks = <&coreclk 0>; | 162 | spi0: spi@10600 { |
| 182 | status = "disabled"; | 163 | compatible = "marvell,orion-spi"; |
| 164 | reg = <0x10600 0x28>; | ||
| 165 | #address-cells = <1>; | ||
| 166 | #size-cells = <0>; | ||
| 167 | cell-index = <0>; | ||
| 168 | interrupts = <30>; | ||
| 169 | clocks = <&coreclk 0>; | ||
| 170 | status = "disabled"; | ||
| 171 | }; | ||
| 172 | |||
| 173 | spi1: spi@10680 { | ||
| 174 | compatible = "marvell,orion-spi"; | ||
| 175 | reg = <0x10680 0x28>; | ||
| 176 | #address-cells = <1>; | ||
| 177 | #size-cells = <0>; | ||
| 178 | cell-index = <1>; | ||
| 179 | interrupts = <92>; | ||
| 180 | clocks = <&coreclk 0>; | ||
| 181 | status = "disabled"; | ||
| 182 | }; | ||
| 183 | |||
| 184 | devbus-bootcs@10400 { | ||
| 185 | compatible = "marvell,mvebu-devbus"; | ||
| 186 | reg = <0x10400 0x8>; | ||
| 187 | #address-cells = <1>; | ||
| 188 | #size-cells = <1>; | ||
| 189 | clocks = <&coreclk 0>; | ||
| 190 | status = "disabled"; | ||
| 191 | }; | ||
| 192 | |||
| 193 | devbus-cs0@10408 { | ||
| 194 | compatible = "marvell,mvebu-devbus"; | ||
| 195 | reg = <0x10408 0x8>; | ||
| 196 | #address-cells = <1>; | ||
| 197 | #size-cells = <1>; | ||
| 198 | clocks = <&coreclk 0>; | ||
| 199 | status = "disabled"; | ||
| 200 | }; | ||
| 201 | |||
| 202 | devbus-cs1@10410 { | ||
| 203 | compatible = "marvell,mvebu-devbus"; | ||
| 204 | reg = <0x10410 0x8>; | ||
| 205 | #address-cells = <1>; | ||
| 206 | #size-cells = <1>; | ||
| 207 | clocks = <&coreclk 0>; | ||
| 208 | status = "disabled"; | ||
| 209 | }; | ||
| 210 | |||
| 211 | devbus-cs2@10418 { | ||
| 212 | compatible = "marvell,mvebu-devbus"; | ||
| 213 | reg = <0x10418 0x8>; | ||
| 214 | #address-cells = <1>; | ||
| 215 | #size-cells = <1>; | ||
| 216 | clocks = <&coreclk 0>; | ||
| 217 | status = "disabled"; | ||
| 218 | }; | ||
| 219 | |||
| 220 | devbus-cs3@10420 { | ||
| 221 | compatible = "marvell,mvebu-devbus"; | ||
| 222 | reg = <0x10420 0x8>; | ||
| 223 | #address-cells = <1>; | ||
| 224 | #size-cells = <1>; | ||
| 225 | clocks = <&coreclk 0>; | ||
| 226 | status = "disabled"; | ||
| 227 | }; | ||
| 183 | }; | 228 | }; |
| 184 | }; | 229 | }; |
| 185 | }; | 230 | }; |
| 186 | |||
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 8188d138020e..b2c1b5af9749 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi | |||
| @@ -16,16 +16,11 @@ | |||
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /include/ "armada-370-xp.dtsi" | 18 | /include/ "armada-370-xp.dtsi" |
| 19 | /include/ "skeleton.dtsi" | ||
| 19 | 20 | ||
| 20 | / { | 21 | / { |
| 21 | model = "Marvell Armada 370 family SoC"; | 22 | model = "Marvell Armada 370 family SoC"; |
| 22 | compatible = "marvell,armada370", "marvell,armada-370-xp"; | 23 | compatible = "marvell,armada370", "marvell,armada-370-xp"; |
| 23 | L2: l2-cache { | ||
| 24 | compatible = "marvell,aurora-outer-cache"; | ||
| 25 | reg = <0xd0008000 0x1000>; | ||
| 26 | cache-id-part = <0x100>; | ||
| 27 | wt-override; | ||
| 28 | }; | ||
| 29 | 24 | ||
| 30 | aliases { | 25 | aliases { |
| 31 | gpio0 = &gpio0; | 26 | gpio0 = &gpio0; |
| @@ -33,125 +28,198 @@ | |||
| 33 | gpio2 = &gpio2; | 28 | gpio2 = &gpio2; |
| 34 | }; | 29 | }; |
| 35 | 30 | ||
| 36 | mpic: interrupt-controller@d0020000 { | ||
| 37 | reg = <0xd0020a00 0x1d0>, | ||
| 38 | <0xd0021870 0x58>; | ||
| 39 | }; | ||
| 40 | |||
| 41 | soc { | 31 | soc { |
| 42 | system-controller@d0018200 { | 32 | ranges = <0 0xd0000000 0x100000>; |
| 33 | internal-regs { | ||
| 34 | system-controller@18200 { | ||
| 43 | compatible = "marvell,armada-370-xp-system-controller"; | 35 | compatible = "marvell,armada-370-xp-system-controller"; |
| 44 | reg = <0xd0018200 0x100>; | 36 | reg = <0x18200 0x100>; |
| 45 | }; | 37 | }; |
| 46 | |||
| 47 | pinctrl { | ||
| 48 | compatible = "marvell,mv88f6710-pinctrl"; | ||
| 49 | reg = <0xd0018000 0x38>; | ||
| 50 | 38 | ||
| 51 | sdio_pins1: sdio-pins1 { | 39 | L2: l2-cache { |
| 52 | marvell,pins = "mpp9", "mpp11", "mpp12", | 40 | compatible = "marvell,aurora-outer-cache"; |
| 53 | "mpp13", "mpp14", "mpp15"; | 41 | reg = <0xd0008000 0x1000>; |
| 54 | marvell,function = "sd0"; | 42 | cache-id-part = <0x100>; |
| 43 | wt-override; | ||
| 55 | }; | 44 | }; |
| 56 | 45 | ||
| 57 | sdio_pins2: sdio-pins2 { | 46 | mpic: interrupt-controller@20000 { |
| 58 | marvell,pins = "mpp47", "mpp48", "mpp49", | 47 | reg = <0x20a00 0x1d0>, <0x21870 0x58>; |
| 59 | "mpp50", "mpp51", "mpp52"; | ||
| 60 | marvell,function = "sd0"; | ||
| 61 | }; | 48 | }; |
| 62 | }; | ||
| 63 | |||
| 64 | gpio0: gpio@d0018100 { | ||
| 65 | compatible = "marvell,orion-gpio"; | ||
| 66 | reg = <0xd0018100 0x40>; | ||
| 67 | ngpios = <32>; | ||
| 68 | gpio-controller; | ||
| 69 | #gpio-cells = <2>; | ||
| 70 | interrupt-controller; | ||
| 71 | #interrupts-cells = <2>; | ||
| 72 | interrupts = <82>, <83>, <84>, <85>; | ||
| 73 | }; | ||
| 74 | 49 | ||
| 75 | gpio1: gpio@d0018140 { | 50 | pinctrl { |
| 76 | compatible = "marvell,orion-gpio"; | 51 | compatible = "marvell,mv88f6710-pinctrl"; |
| 77 | reg = <0xd0018140 0x40>; | 52 | reg = <0x18000 0x38>; |
| 78 | ngpios = <32>; | 53 | |
| 79 | gpio-controller; | 54 | sdio_pins1: sdio-pins1 { |
| 80 | #gpio-cells = <2>; | 55 | marvell,pins = "mpp9", "mpp11", "mpp12", |
| 81 | interrupt-controller; | 56 | "mpp13", "mpp14", "mpp15"; |
| 82 | #interrupts-cells = <2>; | 57 | marvell,function = "sd0"; |
| 83 | interrupts = <87>, <88>, <89>, <90>; | 58 | }; |
| 84 | }; | 59 | |
| 60 | sdio_pins2: sdio-pins2 { | ||
| 61 | marvell,pins = "mpp47", "mpp48", "mpp49", | ||
| 62 | "mpp50", "mpp51", "mpp52"; | ||
| 63 | marvell,function = "sd0"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | sdio_pins3: sdio-pins3 { | ||
| 67 | marvell,pins = "mpp48", "mpp49", "mpp50", | ||
| 68 | "mpp51", "mpp52", "mpp53"; | ||
| 69 | marvell,function = "sd0"; | ||
| 70 | }; | ||
| 71 | }; | ||
| 85 | 72 | ||
| 86 | gpio2: gpio@d0018180 { | 73 | gpio0: gpio@18100 { |
| 87 | compatible = "marvell,orion-gpio"; | 74 | compatible = "marvell,orion-gpio"; |
| 88 | reg = <0xd0018180 0x40>; | 75 | reg = <0x18100 0x40>; |
| 89 | ngpios = <2>; | 76 | ngpios = <32>; |
| 90 | gpio-controller; | 77 | gpio-controller; |
| 91 | #gpio-cells = <2>; | 78 | #gpio-cells = <2>; |
| 92 | interrupt-controller; | 79 | interrupt-controller; |
| 93 | #interrupts-cells = <2>; | 80 | #interrupts-cells = <2>; |
| 94 | interrupts = <91>; | 81 | interrupts = <82>, <83>, <84>, <85>; |
| 95 | }; | 82 | }; |
| 96 | 83 | ||
| 97 | coreclk: mvebu-sar@d0018230 { | 84 | gpio1: gpio@18140 { |
| 98 | compatible = "marvell,armada-370-core-clock"; | 85 | compatible = "marvell,orion-gpio"; |
| 99 | reg = <0xd0018230 0x08>; | 86 | reg = <0x18140 0x40>; |
| 100 | #clock-cells = <1>; | 87 | ngpios = <32>; |
| 101 | }; | 88 | gpio-controller; |
| 89 | #gpio-cells = <2>; | ||
| 90 | interrupt-controller; | ||
| 91 | #interrupts-cells = <2>; | ||
| 92 | interrupts = <87>, <88>, <89>, <90>; | ||
| 93 | }; | ||
| 102 | 94 | ||
| 103 | gateclk: clock-gating-control@d0018220 { | 95 | gpio2: gpio@18180 { |
| 104 | compatible = "marvell,armada-370-gating-clock"; | 96 | compatible = "marvell,orion-gpio"; |
| 105 | reg = <0xd0018220 0x4>; | 97 | reg = <0x18180 0x40>; |
| 106 | clocks = <&coreclk 0>; | 98 | ngpios = <2>; |
| 107 | #clock-cells = <1>; | 99 | gpio-controller; |
| 108 | }; | 100 | #gpio-cells = <2>; |
| 101 | interrupt-controller; | ||
| 102 | #interrupts-cells = <2>; | ||
| 103 | interrupts = <91>; | ||
| 104 | }; | ||
| 109 | 105 | ||
| 110 | xor@d0060800 { | 106 | coreclk: mvebu-sar@18230 { |
| 111 | compatible = "marvell,orion-xor"; | 107 | compatible = "marvell,armada-370-core-clock"; |
| 112 | reg = <0xd0060800 0x100 | 108 | reg = <0x18230 0x08>; |
| 113 | 0xd0060A00 0x100>; | 109 | #clock-cells = <1>; |
| 114 | status = "okay"; | 110 | }; |
| 115 | 111 | ||
| 116 | xor00 { | 112 | gateclk: clock-gating-control@18220 { |
| 117 | interrupts = <51>; | 113 | compatible = "marvell,armada-370-gating-clock"; |
| 118 | dmacap,memcpy; | 114 | reg = <0x18220 0x4>; |
| 119 | dmacap,xor; | 115 | clocks = <&coreclk 0>; |
| 116 | #clock-cells = <1>; | ||
| 120 | }; | 117 | }; |
| 121 | xor01 { | 118 | |
| 122 | interrupts = <52>; | 119 | xor@60800 { |
| 123 | dmacap,memcpy; | 120 | compatible = "marvell,orion-xor"; |
| 124 | dmacap,xor; | 121 | reg = <0x60800 0x100 |
| 125 | dmacap,memset; | 122 | 0x60A00 0x100>; |
| 123 | status = "okay"; | ||
| 124 | |||
| 125 | xor00 { | ||
| 126 | interrupts = <51>; | ||
| 127 | dmacap,memcpy; | ||
| 128 | dmacap,xor; | ||
| 129 | }; | ||
| 130 | xor01 { | ||
| 131 | interrupts = <52>; | ||
| 132 | dmacap,memcpy; | ||
| 133 | dmacap,xor; | ||
| 134 | dmacap,memset; | ||
| 135 | }; | ||
| 126 | }; | 136 | }; |
| 127 | }; | ||
| 128 | 137 | ||
| 129 | xor@d0060900 { | 138 | xor@60900 { |
| 130 | compatible = "marvell,orion-xor"; | 139 | compatible = "marvell,orion-xor"; |
| 131 | reg = <0xd0060900 0x100 | 140 | reg = <0x60900 0x100 |
| 132 | 0xd0060b00 0x100>; | 141 | 0x60b00 0x100>; |
| 133 | status = "okay"; | 142 | status = "okay"; |
| 143 | |||
| 144 | xor10 { | ||
| 145 | interrupts = <94>; | ||
| 146 | dmacap,memcpy; | ||
| 147 | dmacap,xor; | ||
| 148 | }; | ||
| 149 | xor11 { | ||
| 150 | interrupts = <95>; | ||
| 151 | dmacap,memcpy; | ||
| 152 | dmacap,xor; | ||
| 153 | dmacap,memset; | ||
| 154 | }; | ||
| 155 | }; | ||
| 134 | 156 | ||
| 135 | xor10 { | 157 | usb@50000 { |
| 136 | interrupts = <94>; | 158 | clocks = <&coreclk 0>; |
| 137 | dmacap,memcpy; | ||
| 138 | dmacap,xor; | ||
| 139 | }; | 159 | }; |
| 140 | xor11 { | 160 | |
| 141 | interrupts = <95>; | 161 | usb@51000 { |
| 142 | dmacap,memcpy; | 162 | clocks = <&coreclk 0>; |
| 143 | dmacap,xor; | ||
| 144 | dmacap,memset; | ||
| 145 | }; | 163 | }; |
| 146 | }; | ||
| 147 | 164 | ||
| 148 | usb@d0050000 { | 165 | thermal@18300 { |
| 149 | clocks = <&coreclk 0>; | 166 | compatible = "marvell,armada370-thermal"; |
| 150 | }; | 167 | reg = <0x18300 0x4 |
| 168 | 0x18304 0x4>; | ||
| 169 | status = "okay"; | ||
| 170 | }; | ||
| 151 | 171 | ||
| 152 | usb@d0051000 { | 172 | pcie-controller { |
| 153 | clocks = <&coreclk 0>; | 173 | compatible = "marvell,armada-370-pcie"; |
| 174 | status = "disabled"; | ||
| 175 | device_type = "pci"; | ||
| 176 | |||
| 177 | #address-cells = <3>; | ||
| 178 | #size-cells = <2>; | ||
| 179 | |||
| 180 | bus-range = <0x00 0xff>; | ||
| 181 | |||
| 182 | reg = <0x40000 0x2000>, <0x80000 0x2000>; | ||
| 183 | |||
| 184 | reg-names = "pcie0.0", "pcie1.0"; | ||
| 185 | |||
| 186 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 187 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | ||
| 188 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 189 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 190 | |||
| 191 | pcie@1,0 { | ||
| 192 | device_type = "pci"; | ||
| 193 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 194 | reg = <0x0800 0 0 0 0>; | ||
| 195 | #address-cells = <3>; | ||
| 196 | #size-cells = <2>; | ||
| 197 | #interrupt-cells = <1>; | ||
| 198 | ranges; | ||
| 199 | interrupt-map-mask = <0 0 0 0>; | ||
| 200 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 201 | marvell,pcie-port = <0>; | ||
| 202 | marvell,pcie-lane = <0>; | ||
| 203 | clocks = <&gateclk 5>; | ||
| 204 | status = "disabled"; | ||
| 205 | }; | ||
| 206 | |||
| 207 | pcie@2,0 { | ||
| 208 | device_type = "pci"; | ||
| 209 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | ||
| 210 | reg = <0x1000 0 0 0 0>; | ||
| 211 | #address-cells = <3>; | ||
| 212 | #size-cells = <2>; | ||
| 213 | #interrupt-cells = <1>; | ||
| 214 | ranges; | ||
| 215 | interrupt-map-mask = <0 0 0 0>; | ||
| 216 | interrupt-map = <0 0 0 0 &mpic 62>; | ||
| 217 | marvell,pcie-port = <1>; | ||
| 218 | marvell,pcie-lane = <0>; | ||
| 219 | clocks = <&gateclk 9>; | ||
| 220 | status = "disabled"; | ||
| 221 | }; | ||
| 222 | }; | ||
| 154 | }; | 223 | }; |
| 155 | |||
| 156 | }; | 224 | }; |
| 157 | }; | 225 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index e83505e4c236..d6cc8bf8272e 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts | |||
| @@ -26,99 +26,134 @@ | |||
| 26 | 26 | ||
| 27 | memory { | 27 | memory { |
| 28 | device_type = "memory"; | 28 | device_type = "memory"; |
| 29 | reg = <0x00000000 0x80000000>; /* 2 GB */ | 29 | reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ |
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | soc { | 32 | soc { |
| 33 | serial@d0012000 { | 33 | internal-regs { |
| 34 | clock-frequency = <250000000>; | 34 | serial@12000 { |
| 35 | status = "okay"; | 35 | clock-frequency = <250000000>; |
| 36 | }; | 36 | status = "okay"; |
| 37 | serial@d0012100 { | 37 | }; |
| 38 | clock-frequency = <250000000>; | 38 | serial@12100 { |
| 39 | status = "okay"; | 39 | clock-frequency = <250000000>; |
| 40 | }; | 40 | status = "okay"; |
| 41 | serial@d0012200 { | 41 | }; |
| 42 | clock-frequency = <250000000>; | 42 | serial@12200 { |
| 43 | status = "okay"; | 43 | clock-frequency = <250000000>; |
| 44 | }; | 44 | status = "okay"; |
| 45 | serial@d0012300 { | 45 | }; |
| 46 | clock-frequency = <250000000>; | 46 | serial@12300 { |
| 47 | status = "okay"; | 47 | clock-frequency = <250000000>; |
| 48 | }; | 48 | status = "okay"; |
| 49 | |||
| 50 | sata@d00a0000 { | ||
| 51 | nr-ports = <2>; | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | |||
| 55 | mdio { | ||
| 56 | phy0: ethernet-phy@0 { | ||
| 57 | reg = <0>; | ||
| 58 | }; | 49 | }; |
| 59 | 50 | ||
| 60 | phy1: ethernet-phy@1 { | 51 | sata@a0000 { |
| 61 | reg = <1>; | 52 | nr-ports = <2>; |
| 53 | status = "okay"; | ||
| 62 | }; | 54 | }; |
| 63 | 55 | ||
| 64 | phy2: ethernet-phy@2 { | 56 | mdio { |
| 65 | reg = <25>; | 57 | phy0: ethernet-phy@0 { |
| 58 | reg = <0>; | ||
| 59 | }; | ||
| 60 | |||
| 61 | phy1: ethernet-phy@1 { | ||
| 62 | reg = <1>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | phy2: ethernet-phy@2 { | ||
| 66 | reg = <25>; | ||
| 67 | }; | ||
| 68 | |||
| 69 | phy3: ethernet-phy@3 { | ||
| 70 | reg = <27>; | ||
| 71 | }; | ||
| 66 | }; | 72 | }; |
| 67 | 73 | ||
| 68 | phy3: ethernet-phy@3 { | 74 | ethernet@70000 { |
| 69 | reg = <27>; | 75 | status = "okay"; |
| 76 | phy = <&phy0>; | ||
| 77 | phy-mode = "rgmii-id"; | ||
| 78 | }; | ||
| 79 | ethernet@74000 { | ||
| 80 | status = "okay"; | ||
| 81 | phy = <&phy1>; | ||
| 82 | phy-mode = "rgmii-id"; | ||
| 83 | }; | ||
| 84 | ethernet@30000 { | ||
| 85 | status = "okay"; | ||
| 86 | phy = <&phy2>; | ||
| 87 | phy-mode = "sgmii"; | ||
| 88 | }; | ||
| 89 | ethernet@34000 { | ||
| 90 | status = "okay"; | ||
| 91 | phy = <&phy3>; | ||
| 92 | phy-mode = "sgmii"; | ||
| 70 | }; | 93 | }; |
| 71 | }; | ||
| 72 | 94 | ||
| 73 | ethernet@d0070000 { | 95 | mvsdio@d4000 { |
| 74 | status = "okay"; | 96 | pinctrl-0 = <&sdio_pins>; |
| 75 | phy = <&phy0>; | 97 | pinctrl-names = "default"; |
| 76 | phy-mode = "rgmii-id"; | 98 | status = "okay"; |
| 77 | }; | 99 | /* No CD or WP GPIOs */ |
| 78 | ethernet@d0074000 { | 100 | }; |
| 79 | status = "okay"; | ||
| 80 | phy = <&phy1>; | ||
| 81 | phy-mode = "rgmii-id"; | ||
| 82 | }; | ||
| 83 | ethernet@d0030000 { | ||
| 84 | status = "okay"; | ||
| 85 | phy = <&phy2>; | ||
| 86 | phy-mode = "sgmii"; | ||
| 87 | }; | ||
| 88 | ethernet@d0034000 { | ||
| 89 | status = "okay"; | ||
| 90 | phy = <&phy3>; | ||
| 91 | phy-mode = "sgmii"; | ||
| 92 | }; | ||
| 93 | 101 | ||
| 94 | mvsdio@d00d4000 { | 102 | usb@50000 { |
| 95 | pinctrl-0 = <&sdio_pins>; | 103 | status = "okay"; |
| 96 | pinctrl-names = "default"; | 104 | }; |
| 97 | status = "okay"; | ||
| 98 | /* No CD or WP GPIOs */ | ||
| 99 | }; | ||
| 100 | 105 | ||
| 101 | usb@d0050000 { | 106 | usb@51000 { |
| 102 | status = "okay"; | 107 | status = "okay"; |
| 103 | }; | 108 | }; |
| 104 | 109 | ||
| 105 | usb@d0051000 { | 110 | usb@52000 { |
| 106 | status = "okay"; | 111 | status = "okay"; |
| 107 | }; | 112 | }; |
| 108 | 113 | ||
| 109 | usb@d0052000 { | 114 | spi0: spi@10600 { |
| 110 | status = "okay"; | 115 | status = "okay"; |
| 111 | }; | ||
| 112 | 116 | ||
| 113 | spi0: spi@d0010600 { | 117 | spi-flash@0 { |
| 114 | status = "okay"; | 118 | #address-cells = <1>; |
| 119 | #size-cells = <1>; | ||
| 120 | compatible = "m25p64"; | ||
| 121 | reg = <0>; /* Chip select 0 */ | ||
| 122 | spi-max-frequency = <20000000>; | ||
| 123 | }; | ||
| 124 | }; | ||
| 115 | 125 | ||
| 116 | spi-flash@0 { | 126 | pcie-controller { |
| 117 | #address-cells = <1>; | 127 | status = "okay"; |
| 118 | #size-cells = <1>; | 128 | |
| 119 | compatible = "m25p64"; | 129 | /* |
| 120 | reg = <0>; /* Chip select 0 */ | 130 | * All 6 slots are physically present as |
| 121 | spi-max-frequency = <20000000>; | 131 | * standard PCIe slots on the board. |
| 132 | */ | ||
| 133 | pcie@1,0 { | ||
| 134 | /* Port 0, Lane 0 */ | ||
| 135 | status = "okay"; | ||
| 136 | }; | ||
| 137 | pcie@2,0 { | ||
| 138 | /* Port 0, Lane 1 */ | ||
| 139 | status = "okay"; | ||
| 140 | }; | ||
| 141 | pcie@3,0 { | ||
| 142 | /* Port 0, Lane 2 */ | ||
| 143 | status = "okay"; | ||
| 144 | }; | ||
| 145 | pcie@4,0 { | ||
| 146 | /* Port 0, Lane 3 */ | ||
| 147 | status = "okay"; | ||
| 148 | }; | ||
| 149 | pcie@9,0 { | ||
| 150 | /* Port 2, Lane 0 */ | ||
| 151 | status = "okay"; | ||
| 152 | }; | ||
| 153 | pcie@10,0 { | ||
| 154 | /* Port 3, Lane 0 */ | ||
| 155 | status = "okay"; | ||
| 156 | }; | ||
| 122 | }; | 157 | }; |
| 123 | }; | 158 | }; |
| 124 | }; | 159 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 1c8afe2ffebc..26ad06fc147e 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts | |||
| @@ -26,87 +26,141 @@ | |||
| 26 | 26 | ||
| 27 | memory { | 27 | memory { |
| 28 | device_type = "memory"; | 28 | device_type = "memory"; |
| 29 | |||
| 30 | /* | 29 | /* |
| 31 | * 4 GB of plug-in RAM modules by default but only 3GB | 30 | * 8 GB of plug-in RAM modules by default.The amount |
| 32 | * are visible, the amount of memory available can be | 31 | * of memory available can be changed by the |
| 33 | * changed by the bootloader according the size of the | 32 | * bootloader according the size of the module |
| 34 | * module actually plugged | 33 | * actually plugged. Only 7GB are usable because |
| 34 | * addresses from 0xC0000000 to 0xffffffff are used by | ||
| 35 | * the internal registers of the SoC. | ||
| 35 | */ | 36 | */ |
| 36 | reg = <0x00000000 0xC0000000>; | 37 | reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, |
| 38 | <0x00000001 0x00000000 0x00000001 0x00000000>; | ||
| 37 | }; | 39 | }; |
| 38 | 40 | ||
| 39 | soc { | 41 | soc { |
| 40 | serial@d0012000 { | 42 | internal-regs { |
| 41 | clock-frequency = <250000000>; | 43 | serial@12000 { |
| 42 | status = "okay"; | 44 | clock-frequency = <250000000>; |
| 43 | }; | 45 | status = "okay"; |
| 44 | serial@d0012100 { | 46 | }; |
| 45 | clock-frequency = <250000000>; | 47 | serial@12100 { |
| 46 | status = "okay"; | 48 | clock-frequency = <250000000>; |
| 47 | }; | 49 | status = "okay"; |
| 48 | serial@d0012200 { | 50 | }; |
| 49 | clock-frequency = <250000000>; | 51 | serial@12200 { |
| 50 | status = "okay"; | 52 | clock-frequency = <250000000>; |
| 51 | }; | 53 | status = "okay"; |
| 52 | serial@d0012300 { | 54 | }; |
| 53 | clock-frequency = <250000000>; | 55 | serial@12300 { |
| 54 | status = "okay"; | 56 | clock-frequency = <250000000>; |
| 55 | }; | 57 | status = "okay"; |
| 56 | 58 | }; | |
| 57 | sata@d00a0000 { | ||
| 58 | nr-ports = <2>; | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
| 61 | 59 | ||
| 62 | mdio { | 60 | sata@a0000 { |
| 63 | phy0: ethernet-phy@0 { | 61 | nr-ports = <2>; |
| 64 | reg = <16>; | 62 | status = "okay"; |
| 65 | }; | 63 | }; |
| 66 | 64 | ||
| 67 | phy1: ethernet-phy@1 { | 65 | mdio { |
| 68 | reg = <17>; | 66 | phy0: ethernet-phy@0 { |
| 67 | reg = <16>; | ||
| 68 | }; | ||
| 69 | |||
| 70 | phy1: ethernet-phy@1 { | ||
| 71 | reg = <17>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | phy2: ethernet-phy@2 { | ||
| 75 | reg = <18>; | ||
| 76 | }; | ||
| 77 | |||
| 78 | phy3: ethernet-phy@3 { | ||
| 79 | reg = <19>; | ||
| 80 | }; | ||
| 69 | }; | 81 | }; |
| 70 | 82 | ||
| 71 | phy2: ethernet-phy@2 { | 83 | ethernet@70000 { |
| 72 | reg = <18>; | 84 | status = "okay"; |
| 85 | phy = <&phy0>; | ||
| 86 | phy-mode = "rgmii-id"; | ||
| 73 | }; | 87 | }; |
| 88 | ethernet@74000 { | ||
| 89 | status = "okay"; | ||
| 90 | phy = <&phy1>; | ||
| 91 | phy-mode = "rgmii-id"; | ||
| 92 | }; | ||
| 93 | ethernet@30000 { | ||
| 94 | status = "okay"; | ||
| 95 | phy = <&phy2>; | ||
| 96 | phy-mode = "rgmii-id"; | ||
| 97 | }; | ||
| 98 | ethernet@34000 { | ||
| 99 | status = "okay"; | ||
| 100 | phy = <&phy3>; | ||
| 101 | phy-mode = "rgmii-id"; | ||
| 102 | }; | ||
| 103 | |||
| 104 | spi0: spi@10600 { | ||
| 105 | status = "okay"; | ||
| 74 | 106 | ||
| 75 | phy3: ethernet-phy@3 { | 107 | spi-flash@0 { |
| 76 | reg = <19>; | 108 | #address-cells = <1>; |
| 109 | #size-cells = <1>; | ||
| 110 | compatible = "n25q128a13"; | ||
| 111 | reg = <0>; /* Chip select 0 */ | ||
| 112 | spi-max-frequency = <108000000>; | ||
| 113 | }; | ||
| 77 | }; | 114 | }; |
| 78 | }; | ||
| 79 | 115 | ||
| 80 | ethernet@d0070000 { | 116 | devbus-bootcs@10400 { |
| 81 | status = "okay"; | 117 | status = "okay"; |
| 82 | phy = <&phy0>; | 118 | ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ |
| 83 | phy-mode = "rgmii-id"; | 119 | |
| 84 | }; | 120 | /* Device Bus parameters are required */ |
| 85 | ethernet@d0074000 { | 121 | |
| 86 | status = "okay"; | 122 | /* Read parameters */ |
| 87 | phy = <&phy1>; | 123 | devbus,bus-width = <8>; |
| 88 | phy-mode = "rgmii-id"; | 124 | devbus,turn-off-ps = <60000>; |
| 89 | }; | 125 | devbus,badr-skew-ps = <0>; |
| 90 | ethernet@d0030000 { | 126 | devbus,acc-first-ps = <124000>; |
| 91 | status = "okay"; | 127 | devbus,acc-next-ps = <248000>; |
| 92 | phy = <&phy2>; | 128 | devbus,rd-setup-ps = <0>; |
| 93 | phy-mode = "rgmii-id"; | 129 | devbus,rd-hold-ps = <0>; |
| 94 | }; | 130 | |
| 95 | ethernet@d0034000 { | 131 | /* Write parameters */ |
| 96 | status = "okay"; | 132 | devbus,sync-enable = <0>; |
| 97 | phy = <&phy3>; | 133 | devbus,wr-high-ps = <60000>; |
| 98 | phy-mode = "rgmii-id"; | 134 | devbus,wr-low-ps = <60000>; |
| 99 | }; | 135 | devbus,ale-wr-ps = <60000>; |
| 136 | |||
| 137 | /* NOR 16 MiB */ | ||
| 138 | nor@0 { | ||
| 139 | compatible = "cfi-flash"; | ||
| 140 | reg = <0 0x1000000>; | ||
| 141 | bank-width = <2>; | ||
| 142 | }; | ||
| 143 | }; | ||
| 100 | 144 | ||
| 101 | spi0: spi@d0010600 { | 145 | pcie-controller { |
| 102 | status = "okay"; | 146 | status = "okay"; |
| 103 | 147 | ||
| 104 | spi-flash@0 { | 148 | /* |
| 105 | #address-cells = <1>; | 149 | * The 3 slots are physically present as |
| 106 | #size-cells = <1>; | 150 | * standard PCIe slots on the board. |
| 107 | compatible = "n25q128a13"; | 151 | */ |
| 108 | reg = <0>; /* Chip select 0 */ | 152 | pcie@1,0 { |
| 109 | spi-max-frequency = <108000000>; | 153 | /* Port 0, Lane 0 */ |
| 154 | status = "okay"; | ||
| 155 | }; | ||
| 156 | pcie@9,0 { | ||
| 157 | /* Port 2, Lane 0 */ | ||
| 158 | status = "okay"; | ||
| 159 | }; | ||
| 160 | pcie@10,0 { | ||
| 161 | /* Port 3, Lane 0 */ | ||
| 162 | status = "okay"; | ||
| 163 | }; | ||
| 110 | }; | 164 | }; |
| 111 | }; | 165 | }; |
| 112 | }; | 166 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index f56c40599f5b..f8eaa383e07f 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi | |||
| @@ -25,56 +25,162 @@ | |||
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | cpus { | 27 | cpus { |
| 28 | #address-cells = <1>; | 28 | #address-cells = <1>; |
| 29 | #size-cells = <0>; | 29 | #size-cells = <0>; |
| 30 | 30 | ||
| 31 | cpu@0 { | 31 | cpu@0 { |
| 32 | device_type = "cpu"; | 32 | device_type = "cpu"; |
| 33 | compatible = "marvell,sheeva-v7"; | 33 | compatible = "marvell,sheeva-v7"; |
| 34 | reg = <0>; | 34 | reg = <0>; |
| 35 | clocks = <&cpuclk 0>; | 35 | clocks = <&cpuclk 0>; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | cpu@1 { | 38 | cpu@1 { |
| 39 | device_type = "cpu"; | 39 | device_type = "cpu"; |
| 40 | compatible = "marvell,sheeva-v7"; | 40 | compatible = "marvell,sheeva-v7"; |
| 41 | reg = <1>; | 41 | reg = <1>; |
| 42 | clocks = <&cpuclk 1>; | 42 | clocks = <&cpuclk 1>; |
| 43 | }; | 43 | }; |
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | soc { | 46 | soc { |
| 47 | pinctrl { | 47 | internal-regs { |
| 48 | compatible = "marvell,mv78230-pinctrl"; | 48 | pinctrl { |
| 49 | reg = <0xd0018000 0x38>; | 49 | compatible = "marvell,mv78230-pinctrl"; |
| 50 | 50 | reg = <0x18000 0x38>; | |
| 51 | sdio_pins: sdio-pins { | 51 | |
| 52 | marvell,pins = "mpp30", "mpp31", "mpp32", | 52 | sdio_pins: sdio-pins { |
| 53 | "mpp33", "mpp34", "mpp35"; | 53 | marvell,pins = "mpp30", "mpp31", "mpp32", |
| 54 | marvell,function = "sd0"; | 54 | "mpp33", "mpp34", "mpp35"; |
| 55 | marvell,function = "sd0"; | ||
| 56 | }; | ||
| 55 | }; | 57 | }; |
| 56 | }; | ||
| 57 | 58 | ||
| 58 | gpio0: gpio@d0018100 { | 59 | gpio0: gpio@18100 { |
| 59 | compatible = "marvell,orion-gpio"; | 60 | compatible = "marvell,orion-gpio"; |
| 60 | reg = <0xd0018100 0x40>; | 61 | reg = <0x18100 0x40>; |
| 61 | ngpios = <32>; | 62 | ngpios = <32>; |
| 62 | gpio-controller; | 63 | gpio-controller; |
| 63 | #gpio-cells = <2>; | 64 | #gpio-cells = <2>; |
| 64 | interrupt-controller; | 65 | interrupt-controller; |
| 65 | #interrupts-cells = <2>; | 66 | #interrupts-cells = <2>; |
| 66 | interrupts = <82>, <83>, <84>, <85>; | 67 | interrupts = <82>, <83>, <84>, <85>; |
| 67 | }; | 68 | }; |
| 69 | |||
| 70 | gpio1: gpio@18140 { | ||
| 71 | compatible = "marvell,orion-gpio"; | ||
| 72 | reg = <0x18140 0x40>; | ||
| 73 | ngpios = <17>; | ||
| 74 | gpio-controller; | ||
| 75 | #gpio-cells = <2>; | ||
| 76 | interrupt-controller; | ||
| 77 | #interrupts-cells = <2>; | ||
| 78 | interrupts = <87>, <88>, <89>; | ||
| 79 | }; | ||
| 68 | 80 | ||
| 69 | gpio1: gpio@d0018140 { | 81 | /* |
| 70 | compatible = "marvell,orion-gpio"; | 82 | * MV78230 has 2 PCIe units Gen2.0: One unit can be |
| 71 | reg = <0xd0018140 0x40>; | 83 | * configured as x4 or quad x1 lanes. One unit is |
| 72 | ngpios = <17>; | 84 | * x4/x1. |
| 73 | gpio-controller; | 85 | */ |
| 74 | #gpio-cells = <2>; | 86 | pcie-controller { |
| 75 | interrupt-controller; | 87 | compatible = "marvell,armada-xp-pcie"; |
| 76 | #interrupts-cells = <2>; | 88 | status = "disabled"; |
| 77 | interrupts = <87>, <88>, <89>; | 89 | device_type = "pci"; |
| 90 | |||
| 91 | #address-cells = <3>; | ||
| 92 | #size-cells = <2>; | ||
| 93 | |||
| 94 | bus-range = <0x00 0xff>; | ||
| 95 | |||
| 96 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 97 | 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 98 | 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 99 | 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 100 | 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 101 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 102 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 103 | |||
| 104 | pcie@1,0 { | ||
| 105 | device_type = "pci"; | ||
| 106 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 107 | reg = <0x0800 0 0 0 0>; | ||
| 108 | #address-cells = <3>; | ||
| 109 | #size-cells = <2>; | ||
| 110 | #interrupt-cells = <1>; | ||
| 111 | ranges; | ||
| 112 | interrupt-map-mask = <0 0 0 0>; | ||
| 113 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 114 | marvell,pcie-port = <0>; | ||
| 115 | marvell,pcie-lane = <0>; | ||
| 116 | clocks = <&gateclk 5>; | ||
| 117 | status = "disabled"; | ||
| 118 | }; | ||
| 119 | |||
| 120 | pcie@2,0 { | ||
| 121 | device_type = "pci"; | ||
| 122 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 123 | reg = <0x1000 0 0 0 0>; | ||
| 124 | #address-cells = <3>; | ||
| 125 | #size-cells = <2>; | ||
| 126 | #interrupt-cells = <1>; | ||
| 127 | ranges; | ||
| 128 | interrupt-map-mask = <0 0 0 0>; | ||
| 129 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 130 | marvell,pcie-port = <0>; | ||
| 131 | marvell,pcie-lane = <1>; | ||
| 132 | clocks = <&gateclk 6>; | ||
| 133 | status = "disabled"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | pcie@3,0 { | ||
| 137 | device_type = "pci"; | ||
| 138 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | ||
| 139 | reg = <0x1800 0 0 0 0>; | ||
| 140 | #address-cells = <3>; | ||
| 141 | #size-cells = <2>; | ||
| 142 | #interrupt-cells = <1>; | ||
| 143 | ranges; | ||
| 144 | interrupt-map-mask = <0 0 0 0>; | ||
| 145 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 146 | marvell,pcie-port = <0>; | ||
| 147 | marvell,pcie-lane = <2>; | ||
| 148 | clocks = <&gateclk 7>; | ||
| 149 | status = "disabled"; | ||
| 150 | }; | ||
| 151 | |||
| 152 | pcie@4,0 { | ||
| 153 | device_type = "pci"; | ||
| 154 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; | ||
| 155 | reg = <0x2000 0 0 0 0>; | ||
| 156 | #address-cells = <3>; | ||
| 157 | #size-cells = <2>; | ||
| 158 | #interrupt-cells = <1>; | ||
| 159 | ranges; | ||
| 160 | interrupt-map-mask = <0 0 0 0>; | ||
| 161 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 162 | marvell,pcie-port = <0>; | ||
| 163 | marvell,pcie-lane = <3>; | ||
| 164 | clocks = <&gateclk 8>; | ||
| 165 | status = "disabled"; | ||
| 166 | }; | ||
| 167 | |||
| 168 | pcie@9,0 { | ||
| 169 | device_type = "pci"; | ||
| 170 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; | ||
| 171 | reg = <0x4800 0 0 0 0>; | ||
| 172 | #address-cells = <3>; | ||
| 173 | #size-cells = <2>; | ||
| 174 | #interrupt-cells = <1>; | ||
| 175 | ranges; | ||
| 176 | interrupt-map-mask = <0 0 0 0>; | ||
| 177 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 178 | marvell,pcie-port = <2>; | ||
| 179 | marvell,pcie-lane = <0>; | ||
| 180 | clocks = <&gateclk 26>; | ||
| 181 | status = "disabled"; | ||
| 182 | }; | ||
| 183 | }; | ||
| 78 | }; | 184 | }; |
| 79 | }; | 185 | }; |
| 80 | }; | 186 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index f8f2b787d2b0..f4029f015aff 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi | |||
| @@ -26,75 +26,199 @@ | |||
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | cpus { | 28 | cpus { |
| 29 | #address-cells = <1>; | 29 | #address-cells = <1>; |
| 30 | #size-cells = <0>; | 30 | #size-cells = <0>; |
| 31 | 31 | ||
| 32 | cpu@0 { | 32 | cpu@0 { |
| 33 | device_type = "cpu"; | 33 | device_type = "cpu"; |
| 34 | compatible = "marvell,sheeva-v7"; | 34 | compatible = "marvell,sheeva-v7"; |
| 35 | reg = <0>; | 35 | reg = <0>; |
| 36 | clocks = <&cpuclk 0>; | 36 | clocks = <&cpuclk 0>; |
| 37 | }; | 37 | }; |
| 38 | 38 | ||
| 39 | cpu@1 { | 39 | cpu@1 { |
| 40 | device_type = "cpu"; | 40 | device_type = "cpu"; |
| 41 | compatible = "marvell,sheeva-v7"; | 41 | compatible = "marvell,sheeva-v7"; |
| 42 | reg = <1>; | 42 | reg = <1>; |
| 43 | clocks = <&cpuclk 1>; | 43 | clocks = <&cpuclk 1>; |
| 44 | }; | 44 | }; |
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | soc { | 47 | soc { |
| 48 | pinctrl { | 48 | internal-regs { |
| 49 | compatible = "marvell,mv78260-pinctrl"; | 49 | pinctrl { |
| 50 | reg = <0xd0018000 0x38>; | 50 | compatible = "marvell,mv78260-pinctrl"; |
| 51 | 51 | reg = <0x18000 0x38>; | |
| 52 | sdio_pins: sdio-pins { | 52 | |
| 53 | marvell,pins = "mpp30", "mpp31", "mpp32", | 53 | sdio_pins: sdio-pins { |
| 54 | "mpp33", "mpp34", "mpp35"; | 54 | marvell,pins = "mpp30", "mpp31", "mpp32", |
| 55 | marvell,function = "sd0"; | 55 | "mpp33", "mpp34", "mpp35"; |
| 56 | marvell,function = "sd0"; | ||
| 57 | }; | ||
| 56 | }; | 58 | }; |
| 57 | }; | ||
| 58 | 59 | ||
| 59 | gpio0: gpio@d0018100 { | 60 | gpio0: gpio@18100 { |
| 60 | compatible = "marvell,orion-gpio"; | 61 | compatible = "marvell,orion-gpio"; |
| 61 | reg = <0xd0018100 0x40>; | 62 | reg = <0x18100 0x40>; |
| 62 | ngpios = <32>; | 63 | ngpios = <32>; |
| 63 | gpio-controller; | 64 | gpio-controller; |
| 64 | #gpio-cells = <2>; | 65 | #gpio-cells = <2>; |
| 65 | interrupt-controller; | 66 | interrupt-controller; |
| 66 | #interrupts-cells = <2>; | 67 | #interrupts-cells = <2>; |
| 67 | interrupts = <82>, <83>, <84>, <85>; | 68 | interrupts = <82>, <83>, <84>, <85>; |
| 68 | }; | 69 | }; |
| 69 | 70 | ||
| 70 | gpio1: gpio@d0018140 { | 71 | gpio1: gpio@18140 { |
| 71 | compatible = "marvell,orion-gpio"; | 72 | compatible = "marvell,orion-gpio"; |
| 72 | reg = <0xd0018140 0x40>; | 73 | reg = <0x18140 0x40>; |
| 73 | ngpios = <32>; | 74 | ngpios = <32>; |
| 74 | gpio-controller; | 75 | gpio-controller; |
| 75 | #gpio-cells = <2>; | 76 | #gpio-cells = <2>; |
| 76 | interrupt-controller; | 77 | interrupt-controller; |
| 77 | #interrupts-cells = <2>; | 78 | #interrupts-cells = <2>; |
| 78 | interrupts = <87>, <88>, <89>, <90>; | 79 | interrupts = <87>, <88>, <89>, <90>; |
| 79 | }; | 80 | }; |
| 80 | 81 | ||
| 81 | gpio2: gpio@d0018180 { | 82 | gpio2: gpio@18180 { |
| 82 | compatible = "marvell,orion-gpio"; | 83 | compatible = "marvell,orion-gpio"; |
| 83 | reg = <0xd0018180 0x40>; | 84 | reg = <0x18180 0x40>; |
| 84 | ngpios = <3>; | 85 | ngpios = <3>; |
| 85 | gpio-controller; | 86 | gpio-controller; |
| 86 | #gpio-cells = <2>; | 87 | #gpio-cells = <2>; |
| 87 | interrupt-controller; | 88 | interrupt-controller; |
| 88 | #interrupts-cells = <2>; | 89 | #interrupts-cells = <2>; |
| 89 | interrupts = <91>; | 90 | interrupts = <91>; |
| 90 | }; | 91 | }; |
| 91 | 92 | ||
| 92 | ethernet@d0034000 { | 93 | ethernet@34000 { |
| 93 | compatible = "marvell,armada-370-neta"; | 94 | compatible = "marvell,armada-370-neta"; |
| 94 | reg = <0xd0034000 0x2500>; | 95 | reg = <0x34000 0x2500>; |
| 95 | interrupts = <14>; | 96 | interrupts = <14>; |
| 96 | clocks = <&gateclk 1>; | 97 | clocks = <&gateclk 1>; |
| 97 | status = "disabled"; | 98 | status = "disabled"; |
| 99 | }; | ||
| 100 | |||
| 101 | /* | ||
| 102 | * MV78260 has 3 PCIe units Gen2.0: Two units can be | ||
| 103 | * configured as x4 or quad x1 lanes. One unit is | ||
| 104 | * x4/x1. | ||
| 105 | */ | ||
| 106 | pcie-controller { | ||
| 107 | compatible = "marvell,armada-xp-pcie"; | ||
| 108 | status = "disabled"; | ||
| 109 | device_type = "pci"; | ||
| 110 | |||
| 111 | #address-cells = <3>; | ||
| 112 | #size-cells = <2>; | ||
| 113 | |||
| 114 | bus-range = <0x00 0xff>; | ||
| 115 | |||
| 116 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 117 | 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 118 | 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 119 | 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 120 | 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 121 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | ||
| 122 | 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ | ||
| 123 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 124 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 125 | |||
| 126 | pcie@1,0 { | ||
| 127 | device_type = "pci"; | ||
| 128 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 129 | reg = <0x0800 0 0 0 0>; | ||
| 130 | #address-cells = <3>; | ||
| 131 | #size-cells = <2>; | ||
| 132 | #interrupt-cells = <1>; | ||
| 133 | ranges; | ||
| 134 | interrupt-map-mask = <0 0 0 0>; | ||
| 135 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 136 | marvell,pcie-port = <0>; | ||
| 137 | marvell,pcie-lane = <0>; | ||
| 138 | clocks = <&gateclk 5>; | ||
| 139 | status = "disabled"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | pcie@2,0 { | ||
| 143 | device_type = "pci"; | ||
| 144 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 145 | reg = <0x1000 0 0 0 0>; | ||
| 146 | #address-cells = <3>; | ||
| 147 | #size-cells = <2>; | ||
| 148 | #interrupt-cells = <1>; | ||
| 149 | ranges; | ||
| 150 | interrupt-map-mask = <0 0 0 0>; | ||
| 151 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 152 | marvell,pcie-port = <0>; | ||
| 153 | marvell,pcie-lane = <1>; | ||
| 154 | clocks = <&gateclk 6>; | ||
| 155 | status = "disabled"; | ||
| 156 | }; | ||
| 157 | |||
| 158 | pcie@3,0 { | ||
| 159 | device_type = "pci"; | ||
| 160 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | ||
| 161 | reg = <0x1800 0 0 0 0>; | ||
| 162 | #address-cells = <3>; | ||
| 163 | #size-cells = <2>; | ||
| 164 | #interrupt-cells = <1>; | ||
| 165 | ranges; | ||
| 166 | interrupt-map-mask = <0 0 0 0>; | ||
| 167 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 168 | marvell,pcie-port = <0>; | ||
| 169 | marvell,pcie-lane = <2>; | ||
| 170 | clocks = <&gateclk 7>; | ||
| 171 | status = "disabled"; | ||
| 172 | }; | ||
| 173 | |||
| 174 | pcie@4,0 { | ||
| 175 | device_type = "pci"; | ||
| 176 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; | ||
| 177 | reg = <0x2000 0 0 0 0>; | ||
| 178 | #address-cells = <3>; | ||
| 179 | #size-cells = <2>; | ||
| 180 | #interrupt-cells = <1>; | ||
| 181 | ranges; | ||
| 182 | interrupt-map-mask = <0 0 0 0>; | ||
| 183 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 184 | marvell,pcie-port = <0>; | ||
| 185 | marvell,pcie-lane = <3>; | ||
| 186 | clocks = <&gateclk 8>; | ||
| 187 | status = "disabled"; | ||
| 188 | }; | ||
| 189 | |||
| 190 | pcie@9,0 { | ||
| 191 | device_type = "pci"; | ||
| 192 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; | ||
| 193 | reg = <0x4800 0 0 0 0>; | ||
| 194 | #address-cells = <3>; | ||
| 195 | #size-cells = <2>; | ||
| 196 | #interrupt-cells = <1>; | ||
| 197 | ranges; | ||
| 198 | interrupt-map-mask = <0 0 0 0>; | ||
| 199 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 200 | marvell,pcie-port = <2>; | ||
| 201 | marvell,pcie-lane = <0>; | ||
| 202 | clocks = <&gateclk 26>; | ||
| 203 | status = "disabled"; | ||
| 204 | }; | ||
| 205 | |||
| 206 | pcie@10,0 { | ||
| 207 | device_type = "pci"; | ||
| 208 | assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; | ||
| 209 | reg = <0x5000 0 0 0 0>; | ||
| 210 | #address-cells = <3>; | ||
| 211 | #size-cells = <2>; | ||
| 212 | #interrupt-cells = <1>; | ||
| 213 | ranges; | ||
| 214 | interrupt-map-mask = <0 0 0 0>; | ||
| 215 | interrupt-map = <0 0 0 0 &mpic 103>; | ||
| 216 | marvell,pcie-port = <3>; | ||
| 217 | marvell,pcie-lane = <0>; | ||
| 218 | clocks = <&gateclk 27>; | ||
| 219 | status = "disabled"; | ||
| 220 | }; | ||
| 221 | }; | ||
| 98 | }; | 222 | }; |
| 99 | }; | 223 | }; |
| 100 | }; | 224 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 936c25dc32b0..6ab56bd35de9 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi | |||
| @@ -27,89 +27,279 @@ | |||
| 27 | 27 | ||
| 28 | 28 | ||
| 29 | cpus { | 29 | cpus { |
| 30 | #address-cells = <1>; | 30 | #address-cells = <1>; |
| 31 | #size-cells = <0>; | 31 | #size-cells = <0>; |
| 32 | |||
| 33 | cpu@0 { | ||
| 34 | device_type = "cpu"; | ||
| 35 | compatible = "marvell,sheeva-v7"; | ||
| 36 | reg = <0>; | ||
| 37 | clocks = <&cpuclk 0>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | cpu@1 { | ||
| 41 | device_type = "cpu"; | ||
| 42 | compatible = "marvell,sheeva-v7"; | ||
| 43 | reg = <1>; | ||
| 44 | clocks = <&cpuclk 1>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | cpu@2 { | ||
| 48 | device_type = "cpu"; | ||
| 49 | compatible = "marvell,sheeva-v7"; | ||
| 50 | reg = <2>; | ||
| 51 | clocks = <&cpuclk 2>; | ||
| 52 | }; | ||
| 53 | |||
| 54 | cpu@3 { | ||
| 55 | device_type = "cpu"; | ||
| 56 | compatible = "marvell,sheeva-v7"; | ||
| 57 | reg = <3>; | ||
| 58 | clocks = <&cpuclk 3>; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | 32 | ||
| 62 | soc { | 33 | cpu@0 { |
| 63 | pinctrl { | 34 | device_type = "cpu"; |
| 64 | compatible = "marvell,mv78460-pinctrl"; | 35 | compatible = "marvell,sheeva-v7"; |
| 65 | reg = <0xd0018000 0x38>; | 36 | reg = <0>; |
| 66 | 37 | clocks = <&cpuclk 0>; | |
| 67 | sdio_pins: sdio-pins { | ||
| 68 | marvell,pins = "mpp30", "mpp31", "mpp32", | ||
| 69 | "mpp33", "mpp34", "mpp35"; | ||
| 70 | marvell,function = "sd0"; | ||
| 71 | }; | ||
| 72 | }; | 38 | }; |
| 73 | 39 | ||
| 74 | gpio0: gpio@d0018100 { | 40 | cpu@1 { |
| 75 | compatible = "marvell,orion-gpio"; | 41 | device_type = "cpu"; |
| 76 | reg = <0xd0018100 0x40>; | 42 | compatible = "marvell,sheeva-v7"; |
| 77 | ngpios = <32>; | 43 | reg = <1>; |
| 78 | gpio-controller; | 44 | clocks = <&cpuclk 1>; |
| 79 | #gpio-cells = <2>; | ||
| 80 | interrupt-controller; | ||
| 81 | #interrupts-cells = <2>; | ||
| 82 | interrupts = <82>, <83>, <84>, <85>; | ||
| 83 | }; | 45 | }; |
| 84 | 46 | ||
| 85 | gpio1: gpio@d0018140 { | 47 | cpu@2 { |
| 86 | compatible = "marvell,orion-gpio"; | 48 | device_type = "cpu"; |
| 87 | reg = <0xd0018140 0x40>; | 49 | compatible = "marvell,sheeva-v7"; |
| 88 | ngpios = <32>; | 50 | reg = <2>; |
| 89 | gpio-controller; | 51 | clocks = <&cpuclk 2>; |
| 90 | #gpio-cells = <2>; | ||
| 91 | interrupt-controller; | ||
| 92 | #interrupts-cells = <2>; | ||
| 93 | interrupts = <87>, <88>, <89>, <90>; | ||
| 94 | }; | 52 | }; |
| 95 | 53 | ||
| 96 | gpio2: gpio@d0018180 { | 54 | cpu@3 { |
| 97 | compatible = "marvell,orion-gpio"; | 55 | device_type = "cpu"; |
| 98 | reg = <0xd0018180 0x40>; | 56 | compatible = "marvell,sheeva-v7"; |
| 99 | ngpios = <3>; | 57 | reg = <3>; |
| 100 | gpio-controller; | 58 | clocks = <&cpuclk 3>; |
| 101 | #gpio-cells = <2>; | ||
| 102 | interrupt-controller; | ||
| 103 | #interrupts-cells = <2>; | ||
| 104 | interrupts = <91>; | ||
| 105 | }; | 59 | }; |
| 60 | }; | ||
| 61 | |||
| 62 | soc { | ||
| 63 | internal-regs { | ||
| 64 | pinctrl { | ||
| 65 | compatible = "marvell,mv78460-pinctrl"; | ||
| 66 | reg = <0x18000 0x38>; | ||
| 67 | |||
| 68 | sdio_pins: sdio-pins { | ||
| 69 | marvell,pins = "mpp30", "mpp31", "mpp32", | ||
| 70 | "mpp33", "mpp34", "mpp35"; | ||
| 71 | marvell,function = "sd0"; | ||
| 72 | }; | ||
| 73 | }; | ||
| 106 | 74 | ||
| 107 | ethernet@d0034000 { | 75 | gpio0: gpio@18100 { |
| 76 | compatible = "marvell,orion-gpio"; | ||
| 77 | reg = <0x18100 0x40>; | ||
| 78 | ngpios = <32>; | ||
| 79 | gpio-controller; | ||
| 80 | #gpio-cells = <2>; | ||
| 81 | interrupt-controller; | ||
| 82 | #interrupts-cells = <2>; | ||
| 83 | interrupts = <82>, <83>, <84>, <85>; | ||
| 84 | }; | ||
| 85 | |||
| 86 | gpio1: gpio@18140 { | ||
| 87 | compatible = "marvell,orion-gpio"; | ||
| 88 | reg = <0x18140 0x40>; | ||
| 89 | ngpios = <32>; | ||
| 90 | gpio-controller; | ||
| 91 | #gpio-cells = <2>; | ||
| 92 | interrupt-controller; | ||
| 93 | #interrupts-cells = <2>; | ||
| 94 | interrupts = <87>, <88>, <89>, <90>; | ||
| 95 | }; | ||
| 96 | |||
| 97 | gpio2: gpio@18180 { | ||
| 98 | compatible = "marvell,orion-gpio"; | ||
| 99 | reg = <0x18180 0x40>; | ||
| 100 | ngpios = <3>; | ||
| 101 | gpio-controller; | ||
| 102 | #gpio-cells = <2>; | ||
| 103 | interrupt-controller; | ||
| 104 | #interrupts-cells = <2>; | ||
| 105 | interrupts = <91>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | ethernet@34000 { | ||
| 108 | compatible = "marvell,armada-370-neta"; | 109 | compatible = "marvell,armada-370-neta"; |
| 109 | reg = <0xd0034000 0x2500>; | 110 | reg = <0x34000 0x2500>; |
| 110 | interrupts = <14>; | 111 | interrupts = <14>; |
| 111 | clocks = <&gateclk 1>; | 112 | clocks = <&gateclk 1>; |
| 112 | status = "disabled"; | 113 | status = "disabled"; |
| 114 | }; | ||
| 115 | |||
| 116 | /* | ||
| 117 | * MV78460 has 4 PCIe units Gen2.0: Two units can be | ||
| 118 | * configured as x4 or quad x1 lanes. Two units are | ||
| 119 | * x4/x1. | ||
| 120 | */ | ||
| 121 | pcie-controller { | ||
| 122 | compatible = "marvell,armada-xp-pcie"; | ||
| 123 | status = "disabled"; | ||
| 124 | device_type = "pci"; | ||
| 125 | |||
| 126 | #address-cells = <3>; | ||
| 127 | #size-cells = <2>; | ||
| 128 | |||
| 129 | bus-range = <0x00 0xff>; | ||
| 130 | |||
| 131 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 132 | 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 133 | 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 134 | 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 135 | 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 136 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | ||
| 137 | 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ | ||
| 138 | 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */ | ||
| 139 | 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */ | ||
| 140 | 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */ | ||
| 141 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 142 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 143 | |||
| 144 | pcie@1,0 { | ||
| 145 | device_type = "pci"; | ||
| 146 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 147 | reg = <0x0800 0 0 0 0>; | ||
| 148 | #address-cells = <3>; | ||
| 149 | #size-cells = <2>; | ||
| 150 | #interrupt-cells = <1>; | ||
| 151 | ranges; | ||
| 152 | interrupt-map-mask = <0 0 0 0>; | ||
| 153 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 154 | marvell,pcie-port = <0>; | ||
| 155 | marvell,pcie-lane = <0>; | ||
| 156 | clocks = <&gateclk 5>; | ||
| 157 | status = "disabled"; | ||
| 158 | }; | ||
| 159 | |||
| 160 | pcie@2,0 { | ||
| 161 | device_type = "pci"; | ||
| 162 | assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; | ||
| 163 | reg = <0x1000 0 0 0 0>; | ||
| 164 | #address-cells = <3>; | ||
| 165 | #size-cells = <2>; | ||
| 166 | #interrupt-cells = <1>; | ||
| 167 | ranges; | ||
| 168 | interrupt-map-mask = <0 0 0 0>; | ||
| 169 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 170 | marvell,pcie-port = <0>; | ||
| 171 | marvell,pcie-lane = <1>; | ||
| 172 | clocks = <&gateclk 6>; | ||
| 173 | status = "disabled"; | ||
| 174 | }; | ||
| 175 | |||
| 176 | pcie@3,0 { | ||
| 177 | device_type = "pci"; | ||
| 178 | assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; | ||
| 179 | reg = <0x1800 0 0 0 0>; | ||
| 180 | #address-cells = <3>; | ||
| 181 | #size-cells = <2>; | ||
| 182 | #interrupt-cells = <1>; | ||
| 183 | ranges; | ||
| 184 | interrupt-map-mask = <0 0 0 0>; | ||
| 185 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 186 | marvell,pcie-port = <0>; | ||
| 187 | marvell,pcie-lane = <2>; | ||
| 188 | clocks = <&gateclk 7>; | ||
| 189 | status = "disabled"; | ||
| 190 | }; | ||
| 191 | |||
| 192 | pcie@4,0 { | ||
| 193 | device_type = "pci"; | ||
| 194 | assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; | ||
| 195 | reg = <0x2000 0 0 0 0>; | ||
| 196 | #address-cells = <3>; | ||
| 197 | #size-cells = <2>; | ||
| 198 | #interrupt-cells = <1>; | ||
| 199 | ranges; | ||
| 200 | interrupt-map-mask = <0 0 0 0>; | ||
| 201 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 202 | marvell,pcie-port = <0>; | ||
| 203 | marvell,pcie-lane = <3>; | ||
| 204 | clocks = <&gateclk 8>; | ||
| 205 | status = "disabled"; | ||
| 206 | }; | ||
| 207 | |||
| 208 | pcie@5,0 { | ||
| 209 | device_type = "pci"; | ||
| 210 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | ||
| 211 | reg = <0x2800 0 0 0 0>; | ||
| 212 | #address-cells = <3>; | ||
| 213 | #size-cells = <2>; | ||
| 214 | #interrupt-cells = <1>; | ||
| 215 | ranges; | ||
| 216 | interrupt-map-mask = <0 0 0 0>; | ||
| 217 | interrupt-map = <0 0 0 0 &mpic 62>; | ||
| 218 | marvell,pcie-port = <1>; | ||
| 219 | marvell,pcie-lane = <0>; | ||
| 220 | clocks = <&gateclk 9>; | ||
| 221 | status = "disabled"; | ||
| 222 | }; | ||
| 223 | |||
| 224 | pcie@6,0 { | ||
| 225 | device_type = "pci"; | ||
| 226 | assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; | ||
| 227 | reg = <0x3000 0 0 0 0>; | ||
| 228 | #address-cells = <3>; | ||
| 229 | #size-cells = <2>; | ||
| 230 | #interrupt-cells = <1>; | ||
| 231 | ranges; | ||
| 232 | interrupt-map-mask = <0 0 0 0>; | ||
| 233 | interrupt-map = <0 0 0 0 &mpic 63>; | ||
| 234 | marvell,pcie-port = <1>; | ||
| 235 | marvell,pcie-lane = <1>; | ||
| 236 | clocks = <&gateclk 10>; | ||
| 237 | status = "disabled"; | ||
| 238 | }; | ||
| 239 | |||
| 240 | pcie@7,0 { | ||
| 241 | device_type = "pci"; | ||
| 242 | assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; | ||
| 243 | reg = <0x3800 0 0 0 0>; | ||
| 244 | #address-cells = <3>; | ||
| 245 | #size-cells = <2>; | ||
| 246 | #interrupt-cells = <1>; | ||
| 247 | ranges; | ||
| 248 | interrupt-map-mask = <0 0 0 0>; | ||
| 249 | interrupt-map = <0 0 0 0 &mpic 64>; | ||
| 250 | marvell,pcie-port = <1>; | ||
| 251 | marvell,pcie-lane = <2>; | ||
| 252 | clocks = <&gateclk 11>; | ||
| 253 | status = "disabled"; | ||
| 254 | }; | ||
| 255 | |||
| 256 | pcie@8,0 { | ||
| 257 | device_type = "pci"; | ||
| 258 | assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; | ||
| 259 | reg = <0x4000 0 0 0 0>; | ||
| 260 | #address-cells = <3>; | ||
| 261 | #size-cells = <2>; | ||
| 262 | #interrupt-cells = <1>; | ||
| 263 | ranges; | ||
| 264 | interrupt-map-mask = <0 0 0 0>; | ||
| 265 | interrupt-map = <0 0 0 0 &mpic 65>; | ||
| 266 | marvell,pcie-port = <1>; | ||
| 267 | marvell,pcie-lane = <3>; | ||
| 268 | clocks = <&gateclk 12>; | ||
| 269 | status = "disabled"; | ||
| 270 | }; | ||
| 271 | pcie@9,0 { | ||
| 272 | device_type = "pci"; | ||
| 273 | assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; | ||
| 274 | reg = <0x4800 0 0 0 0>; | ||
| 275 | #address-cells = <3>; | ||
| 276 | #size-cells = <2>; | ||
| 277 | #interrupt-cells = <1>; | ||
| 278 | ranges; | ||
| 279 | interrupt-map-mask = <0 0 0 0>; | ||
| 280 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 281 | marvell,pcie-port = <2>; | ||
| 282 | marvell,pcie-lane = <0>; | ||
| 283 | clocks = <&gateclk 26>; | ||
| 284 | status = "disabled"; | ||
| 285 | }; | ||
| 286 | |||
| 287 | pcie@10,0 { | ||
| 288 | device_type = "pci"; | ||
| 289 | assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; | ||
| 290 | reg = <0x5000 0 0 0 0>; | ||
| 291 | #address-cells = <3>; | ||
| 292 | #size-cells = <2>; | ||
| 293 | #interrupt-cells = <1>; | ||
| 294 | ranges; | ||
| 295 | interrupt-map-mask = <0 0 0 0>; | ||
| 296 | interrupt-map = <0 0 0 0 &mpic 103>; | ||
| 297 | marvell,pcie-port = <3>; | ||
| 298 | marvell,pcie-lane = <0>; | ||
| 299 | clocks = <&gateclk 27>; | ||
| 300 | status = "disabled"; | ||
| 301 | }; | ||
| 302 | }; | ||
| 113 | }; | 303 | }; |
| 114 | }; | 304 | }; |
| 115 | }; | 305 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 3818a82176a2..f14d36c46159 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | |||
| @@ -23,121 +23,161 @@ | |||
| 23 | 23 | ||
| 24 | memory { | 24 | memory { |
| 25 | device_type = "memory"; | 25 | device_type = "memory"; |
| 26 | reg = <0x00000000 0xC0000000>; /* 3 GB */ | 26 | reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */ |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | soc { | 29 | soc { |
| 30 | serial@d0012000 { | 30 | internal-regs { |
| 31 | clock-frequency = <250000000>; | 31 | serial@12000 { |
| 32 | status = "okay"; | 32 | clock-frequency = <250000000>; |
| 33 | }; | 33 | status = "okay"; |
| 34 | serial@d0012100 { | ||
| 35 | clock-frequency = <250000000>; | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
| 38 | pinctrl { | ||
| 39 | led_pins: led-pins-0 { | ||
| 40 | marvell,pins = "mpp49", "mpp51", "mpp53"; | ||
| 41 | marvell,function = "gpio"; | ||
| 42 | }; | 34 | }; |
| 43 | }; | 35 | serial@12100 { |
| 44 | leds { | 36 | clock-frequency = <250000000>; |
| 45 | compatible = "gpio-leds"; | 37 | status = "okay"; |
| 46 | pinctrl-names = "default"; | ||
| 47 | pinctrl-0 = <&led_pins>; | ||
| 48 | |||
| 49 | red_led { | ||
| 50 | label = "red_led"; | ||
| 51 | gpios = <&gpio1 17 1>; | ||
| 52 | default-state = "off"; | ||
| 53 | }; | 38 | }; |
| 54 | 39 | pinctrl { | |
| 55 | yellow_led { | 40 | led_pins: led-pins-0 { |
| 56 | label = "yellow_led"; | 41 | marvell,pins = "mpp49", "mpp51", "mpp53"; |
| 57 | gpios = <&gpio1 19 1>; | 42 | marvell,function = "gpio"; |
| 58 | default-state = "off"; | 43 | }; |
| 59 | }; | 44 | }; |
| 60 | 45 | leds { | |
| 61 | green_led { | 46 | compatible = "gpio-leds"; |
| 62 | label = "green_led"; | 47 | pinctrl-names = "default"; |
| 63 | gpios = <&gpio1 21 1>; | 48 | pinctrl-0 = <&led_pins>; |
| 64 | default-state = "off"; | 49 | |
| 65 | linux,default-trigger = "heartbeat"; | 50 | red_led { |
| 51 | label = "red_led"; | ||
| 52 | gpios = <&gpio1 17 1>; | ||
| 53 | default-state = "off"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | yellow_led { | ||
| 57 | label = "yellow_led"; | ||
| 58 | gpios = <&gpio1 19 1>; | ||
| 59 | default-state = "off"; | ||
| 60 | }; | ||
| 61 | |||
| 62 | green_led { | ||
| 63 | label = "green_led"; | ||
| 64 | gpios = <&gpio1 21 1>; | ||
| 65 | default-state = "off"; | ||
| 66 | linux,default-trigger = "heartbeat"; | ||
| 67 | }; | ||
| 66 | }; | 68 | }; |
| 67 | }; | ||
| 68 | 69 | ||
| 69 | gpio_keys { | 70 | gpio_keys { |
| 70 | compatible = "gpio-keys"; | 71 | compatible = "gpio-keys"; |
| 71 | #address-cells = <1>; | 72 | #address-cells = <1>; |
| 72 | #size-cells = <0>; | 73 | #size-cells = <0>; |
| 73 | 74 | ||
| 74 | button@1 { | 75 | button@1 { |
| 75 | label = "Init Button"; | 76 | label = "Init Button"; |
| 76 | linux,code = <116>; | 77 | linux,code = <116>; |
| 77 | gpios = <&gpio1 28 0>; | 78 | gpios = <&gpio1 28 0>; |
| 79 | }; | ||
| 78 | }; | 80 | }; |
| 79 | }; | ||
| 80 | 81 | ||
| 81 | mdio { | 82 | mdio { |
| 82 | phy0: ethernet-phy@0 { | 83 | phy0: ethernet-phy@0 { |
| 83 | reg = <0>; | 84 | reg = <0>; |
| 84 | }; | 85 | }; |
| 85 | 86 | ||
| 86 | phy1: ethernet-phy@1 { | 87 | phy1: ethernet-phy@1 { |
| 87 | reg = <1>; | 88 | reg = <1>; |
| 88 | }; | 89 | }; |
| 89 | 90 | ||
| 90 | phy2: ethernet-phy@2 { | 91 | phy2: ethernet-phy@2 { |
| 91 | reg = <2>; | 92 | reg = <2>; |
| 93 | }; | ||
| 94 | |||
| 95 | phy3: ethernet-phy@3 { | ||
| 96 | reg = <3>; | ||
| 97 | }; | ||
| 92 | }; | 98 | }; |
| 93 | 99 | ||
| 94 | phy3: ethernet-phy@3 { | 100 | ethernet@70000 { |
| 95 | reg = <3>; | 101 | status = "okay"; |
| 102 | phy = <&phy0>; | ||
| 103 | phy-mode = "sgmii"; | ||
| 104 | }; | ||
| 105 | ethernet@74000 { | ||
| 106 | status = "okay"; | ||
| 107 | phy = <&phy1>; | ||
| 108 | phy-mode = "sgmii"; | ||
| 109 | }; | ||
| 110 | ethernet@30000 { | ||
| 111 | status = "okay"; | ||
| 112 | phy = <&phy2>; | ||
| 113 | phy-mode = "sgmii"; | ||
| 114 | }; | ||
| 115 | ethernet@34000 { | ||
| 116 | status = "okay"; | ||
| 117 | phy = <&phy3>; | ||
| 118 | phy-mode = "sgmii"; | ||
| 119 | }; | ||
| 120 | i2c@11000 { | ||
| 121 | status = "okay"; | ||
| 122 | clock-frequency = <400000>; | ||
| 123 | }; | ||
| 124 | i2c@11100 { | ||
| 125 | status = "okay"; | ||
| 126 | clock-frequency = <400000>; | ||
| 127 | |||
| 128 | s35390a: s35390a@30 { | ||
| 129 | compatible = "s35390a"; | ||
| 130 | reg = <0x30>; | ||
| 131 | }; | ||
| 132 | }; | ||
| 133 | sata@a0000 { | ||
| 134 | nr-ports = <2>; | ||
| 135 | status = "okay"; | ||
| 136 | }; | ||
| 137 | usb@50000 { | ||
| 138 | status = "okay"; | ||
| 139 | }; | ||
| 140 | usb@51000 { | ||
| 141 | status = "okay"; | ||
| 96 | }; | 142 | }; |
| 97 | }; | ||
| 98 | 143 | ||
| 99 | ethernet@d0070000 { | 144 | devbus-bootcs@10400 { |
| 100 | status = "okay"; | 145 | status = "okay"; |
| 101 | phy = <&phy0>; | 146 | ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ |
| 102 | phy-mode = "sgmii"; | 147 | |
| 103 | }; | 148 | /* Device Bus parameters are required */ |
| 104 | ethernet@d0074000 { | 149 | |
| 105 | status = "okay"; | 150 | /* Read parameters */ |
| 106 | phy = <&phy1>; | 151 | devbus,bus-width = <8>; |
| 107 | phy-mode = "sgmii"; | 152 | devbus,turn-off-ps = <60000>; |
| 108 | }; | 153 | devbus,badr-skew-ps = <0>; |
| 109 | ethernet@d0030000 { | 154 | devbus,acc-first-ps = <124000>; |
| 110 | status = "okay"; | 155 | devbus,acc-next-ps = <248000>; |
| 111 | phy = <&phy2>; | 156 | devbus,rd-setup-ps = <0>; |
| 112 | phy-mode = "sgmii"; | 157 | devbus,rd-hold-ps = <0>; |
| 113 | }; | 158 | |
| 114 | ethernet@d0034000 { | 159 | /* Write parameters */ |
| 115 | status = "okay"; | 160 | devbus,sync-enable = <0>; |
| 116 | phy = <&phy3>; | 161 | devbus,wr-high-ps = <60000>; |
| 117 | phy-mode = "sgmii"; | 162 | devbus,wr-low-ps = <60000>; |
| 118 | }; | 163 | devbus,ale-wr-ps = <60000>; |
| 119 | i2c@d0011000 { | 164 | |
| 120 | status = "okay"; | 165 | /* NOR 128 MiB */ |
| 121 | clock-frequency = <400000>; | 166 | nor@0 { |
| 122 | }; | 167 | compatible = "cfi-flash"; |
| 123 | i2c@d0011100 { | 168 | reg = <0 0x8000000>; |
| 124 | status = "okay"; | 169 | bank-width = <2>; |
| 125 | clock-frequency = <400000>; | 170 | }; |
| 171 | }; | ||
| 126 | 172 | ||
| 127 | s35390a: s35390a@30 { | 173 | pcie-controller { |
| 128 | compatible = "s35390a"; | 174 | status = "okay"; |
| 129 | reg = <0x30>; | 175 | /* Internal mini-PCIe connector */ |
| 176 | pcie@1,0 { | ||
| 177 | /* Port 0, Lane 0 */ | ||
| 178 | status = "okay"; | ||
| 179 | }; | ||
| 130 | }; | 180 | }; |
| 131 | }; | 181 | }; |
| 132 | sata@d00a0000 { | ||
| 133 | nr-ports = <2>; | ||
| 134 | status = "okay"; | ||
| 135 | }; | ||
| 136 | usb@d0050000 { | ||
| 137 | status = "okay"; | ||
| 138 | }; | ||
| 139 | usb@d0051000 { | ||
| 140 | status = "okay"; | ||
| 141 | }; | ||
| 142 | }; | 182 | }; |
| 143 | }; | 183 | }; |
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index ca00d8326c87..bacab11c10dc 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi | |||
| @@ -22,134 +22,140 @@ | |||
| 22 | model = "Marvell Armada XP family SoC"; | 22 | model = "Marvell Armada XP family SoC"; |
| 23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | 23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; |
| 24 | 24 | ||
| 25 | L2: l2-cache { | 25 | soc { |
| 26 | compatible = "marvell,aurora-system-cache"; | 26 | internal-regs { |
| 27 | reg = <0xd0008000 0x1000>; | 27 | L2: l2-cache { |
| 28 | cache-id-part = <0x100>; | 28 | compatible = "marvell,aurora-system-cache"; |
| 29 | wt-override; | 29 | reg = <0x08000 0x1000>; |
| 30 | }; | 30 | cache-id-part = <0x100>; |
| 31 | wt-override; | ||
| 32 | }; | ||
| 31 | 33 | ||
| 32 | mpic: interrupt-controller@d0020000 { | 34 | mpic: interrupt-controller@20000 { |
| 33 | reg = <0xd0020a00 0x2d0>, | 35 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; |
| 34 | <0xd0021070 0x58>; | 36 | }; |
| 35 | }; | ||
| 36 | 37 | ||
| 37 | armada-370-xp-pmsu@d0022000 { | 38 | armada-370-xp-pmsu@22000 { |
| 38 | compatible = "marvell,armada-370-xp-pmsu"; | 39 | compatible = "marvell,armada-370-xp-pmsu"; |
| 39 | reg = <0xd0022100 0x430>, | 40 | reg = <0x22100 0x430>, <0x20800 0x20>; |
| 40 | <0xd0020800 0x20>; | 41 | }; |
| 41 | }; | ||
| 42 | 42 | ||
| 43 | soc { | 43 | serial@12200 { |
| 44 | serial@d0012200 { | ||
| 45 | compatible = "snps,dw-apb-uart"; | 44 | compatible = "snps,dw-apb-uart"; |
| 46 | reg = <0xd0012200 0x100>; | 45 | reg = <0x12200 0x100>; |
| 47 | reg-shift = <2>; | 46 | reg-shift = <2>; |
| 48 | interrupts = <43>; | 47 | interrupts = <43>; |
| 49 | reg-io-width = <1>; | 48 | reg-io-width = <1>; |
| 50 | status = "disabled"; | 49 | status = "disabled"; |
| 51 | }; | 50 | }; |
| 52 | serial@d0012300 { | 51 | serial@12300 { |
| 53 | compatible = "snps,dw-apb-uart"; | 52 | compatible = "snps,dw-apb-uart"; |
| 54 | reg = <0xd0012300 0x100>; | 53 | reg = <0x12300 0x100>; |
| 55 | reg-shift = <2>; | 54 | reg-shift = <2>; |
| 56 | interrupts = <44>; | 55 | interrupts = <44>; |
| 57 | reg-io-width = <1>; | 56 | reg-io-width = <1>; |
| 58 | status = "disabled"; | 57 | status = "disabled"; |
| 59 | }; | 58 | }; |
| 60 | 59 | ||
| 61 | timer@d0020300 { | 60 | timer@20300 { |
| 62 | marvell,timer-25Mhz; | 61 | marvell,timer-25Mhz; |
| 63 | }; | 62 | }; |
| 64 | 63 | ||
| 65 | coreclk: mvebu-sar@d0018230 { | 64 | coreclk: mvebu-sar@18230 { |
| 66 | compatible = "marvell,armada-xp-core-clock"; | 65 | compatible = "marvell,armada-xp-core-clock"; |
| 67 | reg = <0xd0018230 0x08>; | 66 | reg = <0x18230 0x08>; |
| 68 | #clock-cells = <1>; | 67 | #clock-cells = <1>; |
| 69 | }; | 68 | }; |
| 70 | 69 | ||
| 71 | cpuclk: clock-complex@d0018700 { | 70 | cpuclk: clock-complex@18700 { |
| 72 | #clock-cells = <1>; | 71 | #clock-cells = <1>; |
| 73 | compatible = "marvell,armada-xp-cpu-clock"; | 72 | compatible = "marvell,armada-xp-cpu-clock"; |
| 74 | reg = <0xd0018700 0xA0>; | 73 | reg = <0x18700 0xA0>; |
| 75 | clocks = <&coreclk 1>; | 74 | clocks = <&coreclk 1>; |
| 76 | }; | 75 | }; |
| 77 | 76 | ||
| 78 | gateclk: clock-gating-control@d0018220 { | 77 | gateclk: clock-gating-control@18220 { |
| 79 | compatible = "marvell,armada-xp-gating-clock"; | 78 | compatible = "marvell,armada-xp-gating-clock"; |
| 80 | reg = <0xd0018220 0x4>; | 79 | reg = <0x18220 0x4>; |
| 81 | clocks = <&coreclk 0>; | 80 | clocks = <&coreclk 0>; |
| 82 | #clock-cells = <1>; | 81 | #clock-cells = <1>; |
| 83 | }; | 82 | }; |
| 84 | 83 | ||
| 85 | system-controller@d0018200 { | 84 | system-controller@18200 { |
| 86 | compatible = "marvell,armada-370-xp-system-controller"; | 85 | compatible = "marvell,armada-370-xp-system-controller"; |
| 87 | reg = <0xd0018200 0x500>; | 86 | reg = <0x18200 0x500>; |
| 88 | }; | 87 | }; |
| 89 | 88 | ||
| 90 | ethernet@d0030000 { | 89 | ethernet@30000 { |
| 91 | compatible = "marvell,armada-370-neta"; | 90 | compatible = "marvell,armada-370-neta"; |
| 92 | reg = <0xd0030000 0x2500>; | 91 | reg = <0x30000 0x2500>; |
| 93 | interrupts = <12>; | 92 | interrupts = <12>; |
| 94 | clocks = <&gateclk 2>; | 93 | clocks = <&gateclk 2>; |
| 95 | status = "disabled"; | 94 | status = "disabled"; |
| 96 | }; | ||
| 97 | |||
| 98 | xor@d0060900 { | ||
| 99 | compatible = "marvell,orion-xor"; | ||
| 100 | reg = <0xd0060900 0x100 | ||
| 101 | 0xd0060b00 0x100>; | ||
| 102 | clocks = <&gateclk 22>; | ||
| 103 | status = "okay"; | ||
| 104 | |||
| 105 | xor10 { | ||
| 106 | interrupts = <51>; | ||
| 107 | dmacap,memcpy; | ||
| 108 | dmacap,xor; | ||
| 109 | }; | ||
| 110 | xor11 { | ||
| 111 | interrupts = <52>; | ||
| 112 | dmacap,memcpy; | ||
| 113 | dmacap,xor; | ||
| 114 | dmacap,memset; | ||
| 115 | }; | 95 | }; |
| 116 | }; | ||
| 117 | 96 | ||
| 118 | xor@d00f0900 { | 97 | xor@60900 { |
| 119 | compatible = "marvell,orion-xor"; | 98 | compatible = "marvell,orion-xor"; |
| 120 | reg = <0xd00F0900 0x100 | 99 | reg = <0x60900 0x100 |
| 121 | 0xd00F0B00 0x100>; | 100 | 0x60b00 0x100>; |
| 122 | clocks = <&gateclk 28>; | 101 | clocks = <&gateclk 22>; |
| 123 | status = "okay"; | 102 | status = "okay"; |
| 103 | |||
| 104 | xor10 { | ||
| 105 | interrupts = <51>; | ||
| 106 | dmacap,memcpy; | ||
| 107 | dmacap,xor; | ||
| 108 | }; | ||
| 109 | xor11 { | ||
| 110 | interrupts = <52>; | ||
| 111 | dmacap,memcpy; | ||
| 112 | dmacap,xor; | ||
| 113 | dmacap,memset; | ||
| 114 | }; | ||
| 115 | }; | ||
| 124 | 116 | ||
| 125 | xor00 { | 117 | xor@f0900 { |
| 126 | interrupts = <94>; | 118 | compatible = "marvell,orion-xor"; |
| 127 | dmacap,memcpy; | 119 | reg = <0xF0900 0x100 |
| 128 | dmacap,xor; | 120 | 0xF0B00 0x100>; |
| 121 | clocks = <&gateclk 28>; | ||
| 122 | status = "okay"; | ||
| 123 | |||
| 124 | xor00 { | ||
| 125 | interrupts = <94>; | ||
| 126 | dmacap,memcpy; | ||
| 127 | dmacap,xor; | ||
| 128 | }; | ||
| 129 | xor01 { | ||
| 130 | interrupts = <95>; | ||
| 131 | dmacap,memcpy; | ||
| 132 | dmacap,xor; | ||
| 133 | dmacap,memset; | ||
| 134 | }; | ||
| 129 | }; | 135 | }; |
| 130 | xor01 { | 136 | |
| 131 | interrupts = <95>; | 137 | usb@50000 { |
| 132 | dmacap,memcpy; | 138 | clocks = <&gateclk 18>; |
| 133 | dmacap,xor; | ||
| 134 | dmacap,memset; | ||
| 135 | }; | 139 | }; |
| 136 | }; | ||
| 137 | 140 | ||
| 138 | usb@d0050000 { | 141 | usb@51000 { |
| 139 | clocks = <&gateclk 18>; | 142 | clocks = <&gateclk 19>; |
| 140 | }; | 143 | }; |
| 141 | 144 | ||
| 142 | usb@d0051000 { | 145 | usb@52000 { |
| 143 | clocks = <&gateclk 19>; | 146 | compatible = "marvell,orion-ehci"; |
| 144 | }; | 147 | reg = <0x52000 0x500>; |
| 148 | interrupts = <47>; | ||
| 149 | clocks = <&gateclk 20>; | ||
| 150 | status = "disabled"; | ||
| 151 | }; | ||
| 145 | 152 | ||
| 146 | usb@d0052000 { | 153 | thermal@182b0 { |
| 147 | compatible = "marvell,orion-ehci"; | 154 | compatible = "marvell,armadaxp-thermal"; |
| 148 | reg = <0xd0052000 0x500>; | 155 | reg = <0x182b0 0x4 |
| 149 | interrupts = <47>; | 156 | 0x184d0 0x4>; |
| 150 | clocks = <&gateclk 20>; | 157 | status = "okay"; |
| 151 | status = "disabled"; | 158 | }; |
| 152 | }; | 159 | }; |
| 153 | |||
| 154 | }; | 160 | }; |
| 155 | }; | 161 | }; |
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index f7509cafc377..6cab46849cdb 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi | |||
| @@ -50,6 +50,11 @@ | |||
| 50 | #clock-cells = <1>; | 50 | #clock-cells = <1>; |
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | thermal: thermal@d001c { | ||
| 54 | compatible = "marvell,dove-thermal"; | ||
| 55 | reg = <0xd001c 0x0c>, <0xd005c 0x08>; | ||
| 56 | }; | ||
| 57 | |||
| 53 | uart0: serial@12000 { | 58 | uart0: serial@12000 { |
| 54 | compatible = "ns16550a"; | 59 | compatible = "ns16550a"; |
| 55 | reg = <0x12000 0x100>; | 60 | reg = <0x12000 0x100>; |
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 192cf76fbf93..23991e45bc55 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi | |||
| @@ -49,6 +49,12 @@ | |||
| 49 | }; | 49 | }; |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | thermal@10078 { | ||
| 53 | compatible = "marvell,kirkwood-thermal"; | ||
| 54 | reg = <0x10078 0x4>; | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 52 | i2c@11100 { | 58 | i2c@11100 { |
| 53 | compatible = "marvell,mv64xxx-i2c"; | 59 | compatible = "marvell,mv64xxx-i2c"; |
| 54 | reg = <0x11100 0x20>; | 60 | reg = <0x11100 0x20>; |
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index bd83b8fc7c83..c3573be7b92c 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts | |||
| @@ -77,6 +77,7 @@ | |||
| 77 | }; | 77 | }; |
| 78 | 78 | ||
| 79 | nand@3000000 { | 79 | nand@3000000 { |
| 80 | chip-delay = <40>; | ||
| 80 | status = "okay"; | 81 | status = "okay"; |
| 81 | 82 | ||
| 82 | partition@0 { | 83 | partition@0 { |
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 9555a86297c2..44fd97dfc1f3 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | |||
| @@ -69,6 +69,10 @@ | |||
| 69 | status = "okay"; | 69 | status = "okay"; |
| 70 | nr-ports = <1>; | 70 | nr-ports = <1>; |
| 71 | }; | 71 | }; |
| 72 | |||
| 73 | mvsdio@90000 { | ||
| 74 | status = "okay"; | ||
| 75 | }; | ||
| 72 | }; | 76 | }; |
| 73 | 77 | ||
| 74 | gpio-leds { | 78 | gpio-leds { |
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 93c3afbef9ee..3694e94f6e99 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | |||
| @@ -96,11 +96,11 @@ | |||
| 96 | marvell,function = "gpio"; | 96 | marvell,function = "gpio"; |
| 97 | }; | 97 | }; |
| 98 | pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { | 98 | pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { |
| 99 | marvell,pins = "mpp44"; | 99 | marvell,pins = "mpp46"; |
| 100 | marvell,function = "gpio"; | 100 | marvell,function = "gpio"; |
| 101 | }; | 101 | }; |
| 102 | pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { | 102 | pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { |
| 103 | marvell,pins = "mpp45"; | 103 | marvell,pins = "mpp47"; |
| 104 | marvell,function = "gpio"; | 104 | marvell,function = "gpio"; |
| 105 | }; | 105 | }; |
| 106 | 106 | ||
| @@ -157,14 +157,14 @@ | |||
| 157 | gpios = <&gpio0 16 0>; | 157 | gpios = <&gpio0 16 0>; |
| 158 | linux,default-trigger = "default-on"; | 158 | linux,default-trigger = "default-on"; |
| 159 | }; | 159 | }; |
| 160 | health_led1 { | 160 | rebuild_led { |
| 161 | label = "status:white:rebuild_led"; | ||
| 162 | gpios = <&gpio1 4 0>; | ||
| 163 | }; | ||
| 164 | health_led { | ||
| 161 | label = "status:red:health_led"; | 165 | label = "status:red:health_led"; |
| 162 | gpios = <&gpio1 5 0>; | 166 | gpios = <&gpio1 5 0>; |
| 163 | }; | 167 | }; |
| 164 | health_led2 { | ||
| 165 | label = "status:white:health_led"; | ||
| 166 | gpios = <&gpio1 4 0>; | ||
| 167 | }; | ||
| 168 | backup_led { | 168 | backup_led { |
| 169 | label = "status:blue:backup_led"; | 169 | label = "status:blue:backup_led"; |
| 170 | gpios = <&gpio0 15 0>; | 170 | gpios = <&gpio0 15 0>; |
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 8aad00f81ed9..892c64e3f1e1 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi | |||
| @@ -13,6 +13,9 @@ | |||
| 13 | compatible = "marvell,orion5x"; | 13 | compatible = "marvell,orion5x"; |
| 14 | interrupt-parent = <&intc>; | 14 | interrupt-parent = <&intc>; |
| 15 | 15 | ||
| 16 | aliases { | ||
| 17 | gpio0 = &gpio0; | ||
| 18 | }; | ||
| 16 | intc: interrupt-controller { | 19 | intc: interrupt-controller { |
| 17 | compatible = "marvell,orion-intc", "marvell,intc"; | 20 | compatible = "marvell,orion-intc", "marvell,intc"; |
| 18 | interrupt-controller; | 21 | interrupt-controller; |
| @@ -32,7 +35,9 @@ | |||
| 32 | #gpio-cells = <2>; | 35 | #gpio-cells = <2>; |
| 33 | gpio-controller; | 36 | gpio-controller; |
| 34 | reg = <0x10100 0x40>; | 37 | reg = <0x10100 0x40>; |
| 35 | ngpio = <32>; | 38 | ngpios = <32>; |
| 39 | interrupt-controller; | ||
| 40 | #interrupt-cells = <2>; | ||
| 36 | interrupts = <6>, <7>, <8>, <9>; | 41 | interrupts = <6>, <7>, <8>, <9>; |
| 37 | }; | 42 | }; |
| 38 | 43 | ||
| @@ -69,6 +74,20 @@ | |||
| 69 | status = "okay"; | 74 | status = "okay"; |
| 70 | }; | 75 | }; |
| 71 | 76 | ||
| 77 | ehci@50000 { | ||
| 78 | compatible = "marvell,orion-ehci"; | ||
| 79 | reg = <0x50000 0x1000>; | ||
| 80 | interrupts = <17>; | ||
| 81 | status = "disabled"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | ehci@a0000 { | ||
| 85 | compatible = "marvell,orion-ehci"; | ||
| 86 | reg = <0xa0000 0x1000>; | ||
| 87 | interrupts = <12>; | ||
| 88 | status = "disabled"; | ||
| 89 | }; | ||
| 90 | |||
| 72 | sata@80000 { | 91 | sata@80000 { |
| 73 | compatible = "marvell,orion-sata"; | 92 | compatible = "marvell,orion-sata"; |
| 74 | reg = <0x80000 0x5000>; | 93 | reg = <0x80000 0x5000>; |
| @@ -86,12 +105,31 @@ | |||
| 86 | status = "disabled"; | 105 | status = "disabled"; |
| 87 | }; | 106 | }; |
| 88 | 107 | ||
| 108 | xor@60900 { | ||
| 109 | compatible = "marvell,orion-xor"; | ||
| 110 | reg = <0x60900 0x100 | ||
| 111 | 0x60b00 0x100>; | ||
| 112 | status = "okay"; | ||
| 113 | |||
| 114 | xor00 { | ||
| 115 | interrupts = <30>; | ||
| 116 | dmacap,memcpy; | ||
| 117 | dmacap,xor; | ||
| 118 | }; | ||
| 119 | xor01 { | ||
| 120 | interrupts = <31>; | ||
| 121 | dmacap,memcpy; | ||
| 122 | dmacap,xor; | ||
| 123 | dmacap,memset; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | |||
| 89 | crypto@90000 { | 127 | crypto@90000 { |
| 90 | compatible = "marvell,orion-crypto"; | 128 | compatible = "marvell,orion-crypto"; |
| 91 | reg = <0x90000 0x10000>, | 129 | reg = <0x90000 0x10000>, |
| 92 | <0xf2200000 0x800>; | 130 | <0xf2200000 0x800>; |
| 93 | reg-names = "regs", "sram"; | 131 | reg-names = "regs", "sram"; |
| 94 | interrupts = <22>; | 132 | interrupts = <28>; |
| 95 | status = "okay"; | 133 | status = "okay"; |
| 96 | }; | 134 | }; |
| 97 | }; | 135 | }; |
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi new file mode 100644 index 000000000000..15994158a998 --- /dev/null +++ b/arch/arm/boot/dts/skeleton64.dtsi | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * Skeleton device tree in the 64 bits version; the bare minimum | ||
| 3 | * needed to boot; just include and add a compatible value. The | ||
| 4 | * bootloader will typically populate the memory node. | ||
| 5 | */ | ||
| 6 | |||
| 7 | / { | ||
| 8 | #address-cells = <2>; | ||
| 9 | #size-cells = <2>; | ||
| 10 | chosen { }; | ||
| 11 | aliases { }; | ||
| 12 | memory { device_type = "memory"; reg = <0 0>; }; | ||
| 13 | }; | ||
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 3fe8dae8d32d..4364eff5b01e 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig | |||
| @@ -75,6 +75,8 @@ CONFIG_I2C_MV64XXX=y | |||
| 75 | CONFIG_SPI=y | 75 | CONFIG_SPI=y |
| 76 | CONFIG_SPI_ORION=y | 76 | CONFIG_SPI_ORION=y |
| 77 | # CONFIG_HWMON is not set | 77 | # CONFIG_HWMON is not set |
| 78 | CONFIG_THERMAL=y | ||
| 79 | CONFIG_DOVE_THERMAL=y | ||
| 78 | CONFIG_USB=y | 80 | CONFIG_USB=y |
| 79 | CONFIG_USB_EHCI_HCD=y | 81 | CONFIG_USB_EHCI_HCD=y |
| 80 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | 82 | CONFIG_USB_EHCI_ROOT_HUB_TT=y |
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 13482ea58b09..8f0065bb6f39 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig | |||
| @@ -119,6 +119,8 @@ CONFIG_SPI=y | |||
| 119 | CONFIG_SPI_ORION=y | 119 | CONFIG_SPI_ORION=y |
| 120 | CONFIG_GPIO_SYSFS=y | 120 | CONFIG_GPIO_SYSFS=y |
| 121 | # CONFIG_HWMON is not set | 121 | # CONFIG_HWMON is not set |
| 122 | CONFIG_THERMAL=y | ||
| 123 | CONFIG_KIRKWOOD_THERMAL=y | ||
| 122 | CONFIG_WATCHDOG=y | 124 | CONFIG_WATCHDOG=y |
| 123 | CONFIG_ORION_WATCHDOG=y | 125 | CONFIG_ORION_WATCHDOG=y |
| 124 | CONFIG_HID_DRAGONRISE=y | 126 | CONFIG_HID_DRAGONRISE=y |
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 2ec8119cff73..f3e8ae001ff1 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig | |||
| @@ -46,9 +46,16 @@ CONFIG_I2C_MV64XXX=y | |||
| 46 | CONFIG_MTD=y | 46 | CONFIG_MTD=y |
| 47 | CONFIG_MTD_CHAR=y | 47 | CONFIG_MTD_CHAR=y |
| 48 | CONFIG_MTD_M25P80=y | 48 | CONFIG_MTD_M25P80=y |
| 49 | CONFIG_MTD_CFI=y | ||
| 50 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 51 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 52 | CONFIG_MTD_CFI_STAA=y | ||
| 53 | CONFIG_MTD_PHYSMAP_OF=y | ||
| 49 | CONFIG_SERIAL_8250_DW=y | 54 | CONFIG_SERIAL_8250_DW=y |
| 50 | CONFIG_GPIOLIB=y | 55 | CONFIG_GPIOLIB=y |
| 51 | CONFIG_GPIO_SYSFS=y | 56 | CONFIG_GPIO_SYSFS=y |
| 57 | CONFIG_THERMAL=y | ||
| 58 | CONFIG_ARMADA_THERMAL=y | ||
| 52 | CONFIG_USB_SUPPORT=y | 59 | CONFIG_USB_SUPPORT=y |
| 53 | CONFIG_USB=y | 60 | CONFIG_USB=y |
| 54 | CONFIG_USB_EHCI_HCD=y | 61 | CONFIG_USB_EHCI_HCD=y |
| @@ -65,6 +72,8 @@ CONFIG_RTC_DRV_S35390A=y | |||
| 65 | CONFIG_RTC_DRV_MV=y | 72 | CONFIG_RTC_DRV_MV=y |
| 66 | CONFIG_DMADEVICES=y | 73 | CONFIG_DMADEVICES=y |
| 67 | CONFIG_MV_XOR=y | 74 | CONFIG_MV_XOR=y |
| 75 | CONFIG_MEMORY=y | ||
| 76 | CONFIG_MVEBU_DEVBUS=y | ||
| 68 | # CONFIG_IOMMU_SUPPORT is not set | 77 | # CONFIG_IOMMU_SUPPORT is not set |
| 69 | CONFIG_EXT2_FS=y | 78 | CONFIG_EXT2_FS=y |
| 70 | CONFIG_EXT3_FS=y | 79 | CONFIG_EXT3_FS=y |
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S index 865c6d02b332..df191afa3be1 100644 --- a/arch/arm/include/debug/mvebu.S +++ b/arch/arm/include/debug/mvebu.S | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 | 14 | #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 |
| 15 | #define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 | 15 | #define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000 |
| 16 | 16 | ||
| 17 | .macro addruart, rp, rv, tmp | 17 | .macro addruart, rp, rv, tmp |
| 18 | ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE | 18 | ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE |
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index 3f0a858fb597..4d9d2ffc4535 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | obj-y += common.o addr-map.o irq.o | 1 | obj-y += common.o irq.o |
| 2 | obj-$(CONFIG_DOVE_LEGACY) += mpp.o | 2 | obj-$(CONFIG_DOVE_LEGACY) += mpp.o |
| 3 | obj-$(CONFIG_PCI) += pcie.o | 3 | obj-$(CONFIG_PCI) += pcie.o |
| 4 | obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o | 4 | obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o |
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c deleted file mode 100644 index 2a06c0163418..000000000000 --- a/arch/arm/mach-dove/addr-map.c +++ /dev/null | |||
| @@ -1,125 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Dove 88AP510 SoC | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <asm/mach/arch.h> | ||
| 16 | #include <asm/setup.h> | ||
| 17 | #include <mach/dove.h> | ||
| 18 | #include <plat/addr-map.h> | ||
| 19 | #include "common.h" | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Generic Address Decode Windows bit settings | ||
| 23 | */ | ||
| 24 | #define TARGET_DDR 0x0 | ||
| 25 | #define TARGET_BOOTROM 0x1 | ||
| 26 | #define TARGET_CESA 0x3 | ||
| 27 | #define TARGET_PCIE0 0x4 | ||
| 28 | #define TARGET_PCIE1 0x8 | ||
| 29 | #define TARGET_SCRATCHPAD 0xd | ||
| 30 | |||
| 31 | #define ATTR_CESA 0x01 | ||
| 32 | #define ATTR_BOOTROM 0xfd | ||
| 33 | #define ATTR_DEV_SPI0_ROM 0xfe | ||
| 34 | #define ATTR_DEV_SPI1_ROM 0xfb | ||
| 35 | #define ATTR_PCIE_IO 0xe0 | ||
| 36 | #define ATTR_PCIE_MEM 0xe8 | ||
| 37 | #define ATTR_SCRATCHPAD 0x0 | ||
| 38 | |||
| 39 | static inline void __iomem *ddr_map_sc(int i) | ||
| 40 | { | ||
| 41 | return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); | ||
| 42 | } | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Description of the windows needed by the platform code | ||
| 46 | */ | ||
| 47 | static struct __initdata orion_addr_map_cfg addr_map_cfg = { | ||
| 48 | .num_wins = 8, | ||
| 49 | .remappable_wins = 4, | ||
| 50 | .bridge_virt_base = BRIDGE_VIRT_BASE, | ||
| 51 | }; | ||
| 52 | |||
| 53 | static const struct __initdata orion_addr_map_info addr_map_info[] = { | ||
| 54 | /* | ||
| 55 | * Windows for PCIe IO+MEM space. | ||
| 56 | */ | ||
| 57 | { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, | ||
| 58 | TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE | ||
| 59 | }, | ||
| 60 | { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, | ||
| 61 | TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE | ||
| 62 | }, | ||
| 63 | { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, | ||
| 64 | TARGET_PCIE0, ATTR_PCIE_MEM, -1 | ||
| 65 | }, | ||
| 66 | { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, | ||
| 67 | TARGET_PCIE1, ATTR_PCIE_MEM, -1 | ||
| 68 | }, | ||
| 69 | /* | ||
| 70 | * Window for CESA engine. | ||
| 71 | */ | ||
| 72 | { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, | ||
| 73 | TARGET_CESA, ATTR_CESA, -1 | ||
| 74 | }, | ||
| 75 | /* | ||
| 76 | * Window to the BootROM for Standby and Sleep Resume | ||
| 77 | */ | ||
| 78 | { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, | ||
| 79 | TARGET_BOOTROM, ATTR_BOOTROM, -1 | ||
| 80 | }, | ||
| 81 | /* | ||
| 82 | * Window to the PMU Scratch Pad space | ||
| 83 | */ | ||
| 84 | { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, | ||
| 85 | TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 | ||
| 86 | }, | ||
| 87 | /* End marker */ | ||
| 88 | { -1, 0, 0, 0, 0, 0 } | ||
| 89 | }; | ||
| 90 | |||
| 91 | void __init dove_setup_cpu_mbus(void) | ||
| 92 | { | ||
| 93 | int i; | ||
| 94 | int cs; | ||
| 95 | |||
| 96 | /* | ||
| 97 | * Disable, clear and configure windows. | ||
| 98 | */ | ||
| 99 | orion_config_wins(&addr_map_cfg, addr_map_info); | ||
| 100 | |||
| 101 | /* | ||
| 102 | * Setup MBUS dram target info. | ||
| 103 | */ | ||
| 104 | orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | ||
| 105 | |||
| 106 | for (i = 0, cs = 0; i < 2; i++) { | ||
| 107 | u32 map = readl(ddr_map_sc(i)); | ||
| 108 | |||
| 109 | /* | ||
| 110 | * Chip select enabled? | ||
| 111 | */ | ||
| 112 | if (map & 1) { | ||
| 113 | struct mbus_dram_window *w; | ||
| 114 | |||
| 115 | w = &orion_mbus_dram_info.cs[cs++]; | ||
| 116 | w->cs_index = i; | ||
| 117 | w->mbus_attr = 0; /* CS address decoding done inside */ | ||
| 118 | /* the DDR controller, no need to */ | ||
| 119 | /* provide attributes */ | ||
| 120 | w->base = map & 0xff800000; | ||
| 121 | w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); | ||
| 122 | } | ||
| 123 | } | ||
| 124 | orion_mbus_dram_info.num_cs = cs; | ||
| 125 | } | ||
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index fbde1dd67113..0b142803b2e1 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c | |||
| @@ -64,7 +64,7 @@ static void __init dove_dt_init(void) | |||
| 64 | #ifdef CONFIG_CACHE_TAUROS2 | 64 | #ifdef CONFIG_CACHE_TAUROS2 |
| 65 | tauros2_init(0); | 65 | tauros2_init(0); |
| 66 | #endif | 66 | #endif |
| 67 | dove_setup_cpu_mbus(); | 67 | dove_setup_cpu_wins(); |
| 68 | 68 | ||
| 69 | /* Setup root of clk tree */ | 69 | /* Setup root of clk tree */ |
| 70 | dove_of_clk_init(); | 70 | dove_of_clk_init(); |
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index c6b3b2bb50e7..e2b5da031f96 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c | |||
| @@ -224,6 +224,9 @@ void __init dove_i2c_init(void) | |||
| 224 | void __init dove_init_early(void) | 224 | void __init dove_init_early(void) |
| 225 | { | 225 | { |
| 226 | orion_time_set_base(TIMER_VIRT_BASE); | 226 | orion_time_set_base(TIMER_VIRT_BASE); |
| 227 | mvebu_mbus_init("marvell,dove-mbus", | ||
| 228 | BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, | ||
| 229 | DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); | ||
| 227 | } | 230 | } |
| 228 | 231 | ||
| 229 | static int __init dove_find_tclk(void) | 232 | static int __init dove_find_tclk(void) |
| @@ -326,6 +329,40 @@ void __init dove_sdio1_init(void) | |||
| 326 | platform_device_register(&dove_sdio1); | 329 | platform_device_register(&dove_sdio1); |
| 327 | } | 330 | } |
| 328 | 331 | ||
| 332 | void __init dove_setup_cpu_wins(void) | ||
| 333 | { | ||
| 334 | /* | ||
| 335 | * The PCIe windows will no longer be statically allocated | ||
| 336 | * here once Dove is migrated to the pci-mvebu driver. | ||
| 337 | */ | ||
| 338 | mvebu_mbus_add_window_remap_flags("pcie0.0", | ||
| 339 | DOVE_PCIE0_IO_PHYS_BASE, | ||
| 340 | DOVE_PCIE0_IO_SIZE, | ||
| 341 | DOVE_PCIE0_IO_BUS_BASE, | ||
| 342 | MVEBU_MBUS_PCI_IO); | ||
| 343 | mvebu_mbus_add_window_remap_flags("pcie1.0", | ||
| 344 | DOVE_PCIE1_IO_PHYS_BASE, | ||
| 345 | DOVE_PCIE1_IO_SIZE, | ||
| 346 | DOVE_PCIE1_IO_BUS_BASE, | ||
| 347 | MVEBU_MBUS_PCI_IO); | ||
| 348 | mvebu_mbus_add_window_remap_flags("pcie0.0", | ||
| 349 | DOVE_PCIE0_MEM_PHYS_BASE, | ||
| 350 | DOVE_PCIE0_MEM_SIZE, | ||
| 351 | MVEBU_MBUS_NO_REMAP, | ||
| 352 | MVEBU_MBUS_PCI_MEM); | ||
| 353 | mvebu_mbus_add_window_remap_flags("pcie1.0", | ||
| 354 | DOVE_PCIE1_MEM_PHYS_BASE, | ||
| 355 | DOVE_PCIE1_MEM_SIZE, | ||
| 356 | MVEBU_MBUS_NO_REMAP, | ||
| 357 | MVEBU_MBUS_PCI_MEM); | ||
| 358 | mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE, | ||
| 359 | DOVE_CESA_SIZE); | ||
| 360 | mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE, | ||
| 361 | DOVE_BOOTROM_SIZE); | ||
| 362 | mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE, | ||
| 363 | DOVE_SCRATCHPAD_SIZE); | ||
| 364 | } | ||
| 365 | |||
| 329 | void __init dove_init(void) | 366 | void __init dove_init(void) |
| 330 | { | 367 | { |
| 331 | pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", | 368 | pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", |
| @@ -334,7 +371,7 @@ void __init dove_init(void) | |||
| 334 | #ifdef CONFIG_CACHE_TAUROS2 | 371 | #ifdef CONFIG_CACHE_TAUROS2 |
| 335 | tauros2_init(0); | 372 | tauros2_init(0); |
| 336 | #endif | 373 | #endif |
| 337 | dove_setup_cpu_mbus(); | 374 | dove_setup_cpu_wins(); |
| 338 | 375 | ||
| 339 | /* Setup root of clk tree */ | 376 | /* Setup root of clk tree */ |
| 340 | dove_clk_init(); | 377 | dove_clk_init(); |
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index ee59fba4c6d1..e86347928b67 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h | |||
| @@ -23,7 +23,7 @@ void dove_map_io(void); | |||
| 23 | void dove_init(void); | 23 | void dove_init(void); |
| 24 | void dove_init_early(void); | 24 | void dove_init_early(void); |
| 25 | void dove_init_irq(void); | 25 | void dove_init_irq(void); |
| 26 | void dove_setup_cpu_mbus(void); | 26 | void dove_setup_cpu_wins(void); |
| 27 | void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); | 27 | void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); |
| 28 | void dove_sata_init(struct mv_sata_platform_data *sata_data); | 28 | void dove_sata_init(struct mv_sata_platform_data *sata_data); |
| 29 | #ifdef CONFIG_PCI | 29 | #ifdef CONFIG_PCI |
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index 661725e3115a..0c4b35f4ee5b 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h | |||
| @@ -77,6 +77,8 @@ | |||
| 77 | /* North-South Bridge */ | 77 | /* North-South Bridge */ |
| 78 | #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) | 78 | #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) |
| 79 | #define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) | 79 | #define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) |
| 80 | #define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) | ||
| 81 | #define BRIDGE_WINS_SZ (0x80) | ||
| 80 | 82 | ||
| 81 | /* Cryptographic Engine */ | 83 | /* Cryptographic Engine */ |
| 82 | #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) | 84 | #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) |
| @@ -168,6 +170,9 @@ | |||
| 168 | #define DOVE_SSP_CLOCK_ENABLE (1 << 1) | 170 | #define DOVE_SSP_CLOCK_ENABLE (1 << 1) |
| 169 | #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) | 171 | #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) |
| 170 | /* Memory Controller */ | 172 | /* Memory Controller */ |
| 173 | #define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000) | ||
| 174 | #define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100) | ||
| 175 | #define DOVE_MC_WINS_SZ (0x8) | ||
| 171 | #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) | 176 | #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) |
| 172 | 177 | ||
| 173 | /* LCD Controller */ | 178 | /* LCD Controller */ |
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 4cc4bee4d0cf..d805f8078fa3 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | obj-y += common.o addr-map.o irq.o pcie.o mpp.o | 1 | obj-y += common.o irq.o pcie.o mpp.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o | 3 | obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o |
| 4 | obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o | 4 | obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o |
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c deleted file mode 100644 index 8f0d162a1e1d..000000000000 --- a/arch/arm/mach-kirkwood/addr-map.c +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-kirkwood/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Kirkwood SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <mach/hardware.h> | ||
| 16 | #include <plat/addr-map.h> | ||
| 17 | #include "common.h" | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Generic Address Decode Windows bit settings | ||
| 21 | */ | ||
| 22 | #define TARGET_DEV_BUS 1 | ||
| 23 | #define TARGET_SRAM 3 | ||
| 24 | #define TARGET_PCIE 4 | ||
| 25 | #define ATTR_DEV_SPI_ROM 0x1e | ||
| 26 | #define ATTR_DEV_BOOT 0x1d | ||
| 27 | #define ATTR_DEV_NAND 0x2f | ||
| 28 | #define ATTR_DEV_CS3 0x37 | ||
| 29 | #define ATTR_DEV_CS2 0x3b | ||
| 30 | #define ATTR_DEV_CS1 0x3d | ||
| 31 | #define ATTR_DEV_CS0 0x3e | ||
| 32 | #define ATTR_PCIE_IO 0xe0 | ||
| 33 | #define ATTR_PCIE_MEM 0xe8 | ||
| 34 | #define ATTR_PCIE1_IO 0xd0 | ||
| 35 | #define ATTR_PCIE1_MEM 0xd8 | ||
| 36 | #define ATTR_SRAM 0x01 | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Description of the windows needed by the platform code | ||
| 40 | */ | ||
| 41 | static struct __initdata orion_addr_map_cfg addr_map_cfg = { | ||
| 42 | .num_wins = 8, | ||
| 43 | .remappable_wins = 4, | ||
| 44 | .bridge_virt_base = BRIDGE_VIRT_BASE, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static const struct __initdata orion_addr_map_info addr_map_info[] = { | ||
| 48 | /* | ||
| 49 | * Windows for PCIe IO+MEM space. | ||
| 50 | */ | ||
| 51 | { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, | ||
| 52 | TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE | ||
| 53 | }, | ||
| 54 | { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, | ||
| 55 | TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE | ||
| 56 | }, | ||
| 57 | { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, | ||
| 58 | TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE | ||
| 59 | }, | ||
| 60 | { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, | ||
| 61 | TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE | ||
| 62 | }, | ||
| 63 | /* | ||
| 64 | * Window for NAND controller. | ||
| 65 | */ | ||
| 66 | { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, | ||
| 67 | TARGET_DEV_BUS, ATTR_DEV_NAND, -1 | ||
| 68 | }, | ||
| 69 | /* | ||
| 70 | * Window for SRAM. | ||
| 71 | */ | ||
| 72 | { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, | ||
| 73 | TARGET_SRAM, ATTR_SRAM, -1 | ||
| 74 | }, | ||
| 75 | /* End marker */ | ||
| 76 | { -1, 0, 0, 0, 0, 0 } | ||
| 77 | }; | ||
| 78 | |||
| 79 | void __init kirkwood_setup_cpu_mbus(void) | ||
| 80 | { | ||
| 81 | /* | ||
| 82 | * Disable, clear and configure windows. | ||
| 83 | */ | ||
| 84 | orion_config_wins(&addr_map_cfg, addr_map_info); | ||
| 85 | |||
| 86 | /* | ||
| 87 | * Setup MBUS dram target info. | ||
| 88 | */ | ||
| 89 | orion_setup_cpu_mbus_target(&addr_map_cfg, | ||
| 90 | (void __iomem *) DDR_WINDOW_CPU_BASE); | ||
| 91 | } | ||
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index d367aa6b47bb..f5437c27dc2a 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c | |||
| @@ -93,7 +93,7 @@ static void __init kirkwood_dt_init(void) | |||
| 93 | */ | 93 | */ |
| 94 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | 94 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); |
| 95 | 95 | ||
| 96 | kirkwood_setup_cpu_mbus(); | 96 | kirkwood_setup_wins(); |
| 97 | 97 | ||
| 98 | kirkwood_l2_init(); | 98 | kirkwood_l2_init(); |
| 99 | 99 | ||
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c index 0a0df4554d8b..a857163954a5 100644 --- a/arch/arm/mach-kirkwood/board-guruplug.c +++ b/arch/arm/mach-kirkwood/board-guruplug.c | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/mv643xx_eth.h> | 14 | #include <linux/mv643xx_eth.h> |
| 15 | #include <linux/gpio.h> | 15 | #include <linux/gpio.h> |
| 16 | #include <linux/platform_data/mmc-mvsdio.h> | ||
| 17 | #include "common.h" | 16 | #include "common.h" |
| 18 | 17 | ||
| 19 | static struct mv643xx_eth_platform_data guruplug_ge00_data = { | 18 | static struct mv643xx_eth_platform_data guruplug_ge00_data = { |
| @@ -24,10 +23,6 @@ static struct mv643xx_eth_platform_data guruplug_ge01_data = { | |||
| 24 | .phy_addr = MV643XX_ETH_PHY_ADDR(1), | 23 | .phy_addr = MV643XX_ETH_PHY_ADDR(1), |
| 25 | }; | 24 | }; |
| 26 | 25 | ||
| 27 | static struct mvsdio_platform_data guruplug_mvsdio_data = { | ||
| 28 | /* unfortunately the CD signal has not been connected */ | ||
| 29 | }; | ||
| 30 | |||
| 31 | void __init guruplug_dt_init(void) | 26 | void __init guruplug_dt_init(void) |
| 32 | { | 27 | { |
| 33 | /* | 28 | /* |
| @@ -35,5 +30,4 @@ void __init guruplug_dt_init(void) | |||
| 35 | */ | 30 | */ |
| 36 | kirkwood_ge00_init(&guruplug_ge00_data); | 31 | kirkwood_ge00_init(&guruplug_ge00_data); |
| 37 | kirkwood_ge01_init(&guruplug_ge01_data); | 32 | kirkwood_ge01_init(&guruplug_ge01_data); |
| 38 | kirkwood_sdio_init(&guruplug_mvsdio_data); | ||
| 39 | } | 33 | } |
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c index f655b2637b0e..e5f70415905a 100644 --- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c | |||
| @@ -20,10 +20,15 @@ static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = { | |||
| 20 | .duplex = DUPLEX_FULL, | 20 | .duplex = DUPLEX_FULL, |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = { | ||
| 24 | .phy_addr = MV643XX_ETH_PHY_ADDR(11), | ||
| 25 | }; | ||
| 26 | |||
| 23 | void __init iomega_ix2_200_init(void) | 27 | void __init iomega_ix2_200_init(void) |
| 24 | { | 28 | { |
| 25 | /* | 29 | /* |
| 26 | * Basic setup. Needs to be called early. | 30 | * Basic setup. Needs to be called early. |
| 27 | */ | 31 | */ |
| 28 | kirkwood_ge01_init(&iomega_ix2_200_ge00_data); | 32 | kirkwood_ge00_init(&iomega_ix2_200_ge00_data); |
| 33 | kirkwood_ge01_init(&iomega_ix2_200_ge01_data); | ||
| 29 | } | 34 | } |
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 49792a0cd2d3..c2cae69e6d2b 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
| @@ -33,7 +33,6 @@ | |||
| 33 | #include <linux/platform_data/usb-ehci-orion.h> | 33 | #include <linux/platform_data/usb-ehci-orion.h> |
| 34 | #include <plat/common.h> | 34 | #include <plat/common.h> |
| 35 | #include <plat/time.h> | 35 | #include <plat/time.h> |
| 36 | #include <plat/addr-map.h> | ||
| 37 | #include <linux/platform_data/dma-mv_xor.h> | 36 | #include <linux/platform_data/dma-mv_xor.h> |
| 38 | #include "common.h" | 37 | #include "common.h" |
| 39 | 38 | ||
| @@ -535,6 +534,9 @@ void __init kirkwood_init_early(void) | |||
| 535 | * the allocations won't fail. | 534 | * the allocations won't fail. |
| 536 | */ | 535 | */ |
| 537 | init_dma_coherent_pool_size(SZ_1M); | 536 | init_dma_coherent_pool_size(SZ_1M); |
| 537 | mvebu_mbus_init("marvell,kirkwood-mbus", | ||
| 538 | BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, | ||
| 539 | DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); | ||
| 538 | } | 540 | } |
| 539 | 541 | ||
| 540 | int kirkwood_tclk; | 542 | int kirkwood_tclk; |
| @@ -650,6 +652,38 @@ char * __init kirkwood_id(void) | |||
| 650 | } | 652 | } |
| 651 | } | 653 | } |
| 652 | 654 | ||
| 655 | void __init kirkwood_setup_wins(void) | ||
| 656 | { | ||
| 657 | /* | ||
| 658 | * The PCIe windows will no longer be statically allocated | ||
| 659 | * here once Kirkwood is migrated to the pci-mvebu driver. | ||
| 660 | */ | ||
| 661 | mvebu_mbus_add_window_remap_flags("pcie0.0", | ||
| 662 | KIRKWOOD_PCIE_IO_PHYS_BASE, | ||
| 663 | KIRKWOOD_PCIE_IO_SIZE, | ||
| 664 | KIRKWOOD_PCIE_IO_BUS_BASE, | ||
| 665 | MVEBU_MBUS_PCI_IO); | ||
| 666 | mvebu_mbus_add_window_remap_flags("pcie0.0", | ||
| 667 | KIRKWOOD_PCIE_MEM_PHYS_BASE, | ||
| 668 | KIRKWOOD_PCIE_MEM_SIZE, | ||
| 669 | MVEBU_MBUS_NO_REMAP, | ||
| 670 | MVEBU_MBUS_PCI_MEM); | ||
| 671 | mvebu_mbus_add_window_remap_flags("pcie1.0", | ||
| 672 | KIRKWOOD_PCIE1_IO_PHYS_BASE, | ||
| 673 | KIRKWOOD_PCIE1_IO_SIZE, | ||
| 674 | KIRKWOOD_PCIE1_IO_BUS_BASE, | ||
| 675 | MVEBU_MBUS_PCI_IO); | ||
| 676 | mvebu_mbus_add_window_remap_flags("pcie1.0", | ||
| 677 | KIRKWOOD_PCIE1_MEM_PHYS_BASE, | ||
| 678 | KIRKWOOD_PCIE1_MEM_SIZE, | ||
| 679 | MVEBU_MBUS_NO_REMAP, | ||
| 680 | MVEBU_MBUS_PCI_MEM); | ||
| 681 | mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, | ||
| 682 | KIRKWOOD_NAND_MEM_SIZE); | ||
| 683 | mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, | ||
| 684 | KIRKWOOD_SRAM_SIZE); | ||
| 685 | } | ||
| 686 | |||
| 653 | void __init kirkwood_l2_init(void) | 687 | void __init kirkwood_l2_init(void) |
| 654 | { | 688 | { |
| 655 | #ifdef CONFIG_CACHE_FEROCEON_L2 | 689 | #ifdef CONFIG_CACHE_FEROCEON_L2 |
| @@ -675,7 +709,7 @@ void __init kirkwood_init(void) | |||
| 675 | */ | 709 | */ |
| 676 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | 710 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); |
| 677 | 711 | ||
| 678 | kirkwood_setup_cpu_mbus(); | 712 | kirkwood_setup_wins(); |
| 679 | 713 | ||
| 680 | kirkwood_l2_init(); | 714 | kirkwood_l2_init(); |
| 681 | 715 | ||
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 5ed70565c843..e24f74305b34 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h | |||
| @@ -30,7 +30,7 @@ void kirkwood_init(void); | |||
| 30 | void kirkwood_init_early(void); | 30 | void kirkwood_init_early(void); |
| 31 | void kirkwood_init_irq(void); | 31 | void kirkwood_init_irq(void); |
| 32 | 32 | ||
| 33 | void kirkwood_setup_cpu_mbus(void); | 33 | void kirkwood_setup_wins(void); |
| 34 | 34 | ||
| 35 | void kirkwood_enable_pcie(void); | 35 | void kirkwood_enable_pcie(void); |
| 36 | void kirkwood_pcie_id(u32 *dev, u32 *rev); | 36 | void kirkwood_pcie_id(u32 *dev, u32 *rev); |
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c index 1c6e736cbbf8..08dd739aa709 100644 --- a/arch/arm/mach-kirkwood/guruplug-setup.c +++ b/arch/arm/mach-kirkwood/guruplug-setup.c | |||
| @@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = { | |||
| 53 | 53 | ||
| 54 | static struct mvsdio_platform_data guruplug_mvsdio_data = { | 54 | static struct mvsdio_platform_data guruplug_mvsdio_data = { |
| 55 | /* unfortunately the CD signal has not been connected */ | 55 | /* unfortunately the CD signal has not been connected */ |
| 56 | .gpio_card_detect = -1, | ||
| 57 | .gpio_write_protect = -1, | ||
| 56 | }; | 58 | }; |
| 57 | 59 | ||
| 58 | static struct gpio_led guruplug_led_pins[] = { | 60 | static struct gpio_led guruplug_led_pins[] = { |
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index a05563a31c95..92976cef3910 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h | |||
| @@ -60,8 +60,9 @@ | |||
| 60 | * Register Map | 60 | * Register Map |
| 61 | */ | 61 | */ |
| 62 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) | 62 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) |
| 63 | #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) | 63 | #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) |
| 64 | #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) | 64 | #define DDR_WINDOW_CPU_BASE (DDR_PHYS_BASE + 0x1500) |
| 65 | #define DDR_WINDOW_CPU_SZ (0x20) | ||
| 65 | #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) | 66 | #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) |
| 66 | 67 | ||
| 67 | #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) | 68 | #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) |
| @@ -80,6 +81,8 @@ | |||
| 80 | 81 | ||
| 81 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) | 82 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) |
| 82 | #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) | 83 | #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) |
| 84 | #define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) | ||
| 85 | #define BRIDGE_WINS_SZ (0x80) | ||
| 83 | 86 | ||
| 84 | #define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) | 87 | #define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) |
| 85 | 88 | ||
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c index 8ddd69fdc937..6a6eb548307d 100644 --- a/arch/arm/mach-kirkwood/openrd-setup.c +++ b/arch/arm/mach-kirkwood/openrd-setup.c | |||
| @@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = { | |||
| 55 | 55 | ||
| 56 | static struct mvsdio_platform_data openrd_mvsdio_data = { | 56 | static struct mvsdio_platform_data openrd_mvsdio_data = { |
| 57 | .gpio_card_detect = 29, /* MPP29 used as SD card detect */ | 57 | .gpio_card_detect = 29, /* MPP29 used as SD card detect */ |
| 58 | .gpio_write_protect = -1, | ||
| 58 | }; | 59 | }; |
| 59 | 60 | ||
| 60 | static unsigned int openrd_mpp_config[] __initdata = { | 61 | static unsigned int openrd_mpp_config[] __initdata = { |
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index d96ad4c09972..7f43e6c2f8c0 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <asm/mach/pci.h> | 17 | #include <asm/mach/pci.h> |
| 18 | #include <plat/pcie.h> | 18 | #include <plat/pcie.h> |
| 19 | #include <mach/bridge-regs.h> | 19 | #include <mach/bridge-regs.h> |
| 20 | #include <plat/addr-map.h> | ||
| 21 | #include "common.h" | 20 | #include "common.h" |
| 22 | 21 | ||
| 23 | static void kirkwood_enable_pcie_clk(const char *port) | 22 | static void kirkwood_enable_pcie_clk(const char *port) |
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index c7d93b48926b..d24223166e06 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c | |||
| @@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = { | |||
| 69 | 69 | ||
| 70 | static struct mvsdio_platform_data rd88f6281_mvsdio_data = { | 70 | static struct mvsdio_platform_data rd88f6281_mvsdio_data = { |
| 71 | .gpio_card_detect = 28, | 71 | .gpio_card_detect = 28, |
| 72 | .gpio_write_protect = -1, | ||
| 72 | }; | 73 | }; |
| 73 | 74 | ||
| 74 | static unsigned int rd88f6281_mpp_config[] __initdata = { | 75 | static unsigned int rd88f6281_mpp_config[] __initdata = { |
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 67a13f9bfe64..7cd04634d302 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | obj-y += common.o addr-map.o mpp.o irq.o pcie.o | 1 | obj-y += common.o mpp.o irq.o pcie.o |
| 2 | obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o | 2 | obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o |
| 3 | obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o | 3 | obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o |
| 4 | obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o | 4 | obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o |
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c deleted file mode 100644 index 26e9876b50e9..000000000000 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ /dev/null | |||
| @@ -1,93 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-mv78xx0/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell MV78xx0 SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <plat/addr-map.h> | ||
| 16 | #include <mach/mv78xx0.h> | ||
| 17 | #include "common.h" | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Generic Address Decode Windows bit settings | ||
| 21 | */ | ||
| 22 | #define TARGET_DEV_BUS 1 | ||
| 23 | #define TARGET_PCIE0 4 | ||
| 24 | #define TARGET_PCIE1 8 | ||
| 25 | #define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0) | ||
| 26 | #define ATTR_DEV_SPI_ROM 0x1f | ||
| 27 | #define ATTR_DEV_BOOT 0x2f | ||
| 28 | #define ATTR_DEV_CS3 0x37 | ||
| 29 | #define ATTR_DEV_CS2 0x3b | ||
| 30 | #define ATTR_DEV_CS1 0x3d | ||
| 31 | #define ATTR_DEV_CS0 0x3e | ||
| 32 | #define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l))) | ||
| 33 | #define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) | ||
| 34 | |||
| 35 | /* | ||
| 36 | * CPU Address Decode Windows registers | ||
| 37 | */ | ||
| 38 | #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) | ||
| 39 | #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) | ||
| 40 | |||
| 41 | static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) | ||
| 42 | { | ||
| 43 | /* | ||
| 44 | * Find the control register base address for this window. | ||
| 45 | * | ||
| 46 | * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's) | ||
| 47 | * MBUS bridge depending on which CPU core we're running on, | ||
| 48 | * so we don't need to take that into account here. | ||
| 49 | */ | ||
| 50 | |||
| 51 | return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win); | ||
| 52 | } | ||
| 53 | |||
| 54 | /* | ||
| 55 | * Description of the windows needed by the platform code | ||
| 56 | */ | ||
| 57 | static struct orion_addr_map_cfg addr_map_cfg __initdata = { | ||
| 58 | .num_wins = 14, | ||
| 59 | .remappable_wins = 8, | ||
| 60 | .win_cfg_base = win_cfg_base, | ||
| 61 | }; | ||
| 62 | |||
| 63 | void __init mv78xx0_setup_cpu_mbus(void) | ||
| 64 | { | ||
| 65 | /* | ||
| 66 | * Disable, clear and configure windows. | ||
| 67 | */ | ||
| 68 | orion_config_wins(&addr_map_cfg, NULL); | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Setup MBUS dram target info. | ||
| 72 | */ | ||
| 73 | if (mv78xx0_core_index() == 0) | ||
| 74 | orion_setup_cpu_mbus_target(&addr_map_cfg, | ||
| 75 | (void __iomem *) DDR_WINDOW_CPU0_BASE); | ||
| 76 | else | ||
| 77 | orion_setup_cpu_mbus_target(&addr_map_cfg, | ||
| 78 | (void __iomem *) DDR_WINDOW_CPU1_BASE); | ||
| 79 | } | ||
| 80 | |||
| 81 | void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, | ||
| 82 | int maj, int min) | ||
| 83 | { | ||
| 84 | orion_setup_cpu_win(&addr_map_cfg, window, base, size, | ||
| 85 | TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0); | ||
| 86 | } | ||
| 87 | |||
| 88 | void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, | ||
| 89 | int maj, int min) | ||
| 90 | { | ||
| 91 | orion_setup_cpu_win(&addr_map_cfg, window, base, size, | ||
| 92 | TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1); | ||
| 93 | } | ||
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 0efa14498ebc..749a7f8c4992 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c | |||
| @@ -334,6 +334,14 @@ void __init mv78xx0_uart3_init(void) | |||
| 334 | void __init mv78xx0_init_early(void) | 334 | void __init mv78xx0_init_early(void) |
| 335 | { | 335 | { |
| 336 | orion_time_set_base(TIMER_VIRT_BASE); | 336 | orion_time_set_base(TIMER_VIRT_BASE); |
| 337 | if (mv78xx0_core_index() == 0) | ||
| 338 | mvebu_mbus_init("marvell,mv78xx0-mbus", | ||
| 339 | BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ, | ||
| 340 | DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ); | ||
| 341 | else | ||
| 342 | mvebu_mbus_init("marvell,mv78xx0-mbus", | ||
| 343 | BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ, | ||
| 344 | DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ); | ||
| 337 | } | 345 | } |
| 338 | 346 | ||
| 339 | void __init_refok mv78xx0_timer_init(void) | 347 | void __init_refok mv78xx0_timer_init(void) |
| @@ -397,8 +405,6 @@ void __init mv78xx0_init(void) | |||
| 397 | printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); | 405 | printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); |
| 398 | printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); | 406 | printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); |
| 399 | 407 | ||
| 400 | mv78xx0_setup_cpu_mbus(); | ||
| 401 | |||
| 402 | #ifdef CONFIG_CACHE_FEROCEON_L2 | 408 | #ifdef CONFIG_CACHE_FEROCEON_L2 |
| 403 | feroceon_l2_init(is_l2_writethrough()); | 409 | feroceon_l2_init(is_l2_writethrough()); |
| 404 | #endif | 410 | #endif |
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 46200a183cf2..723748d8ba7d 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
| @@ -60,13 +60,18 @@ | |||
| 60 | */ | 60 | */ |
| 61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) | 61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) |
| 62 | #define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) | 62 | #define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) |
| 63 | #define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) | ||
| 64 | #define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) | ||
| 65 | #define BRIDGE_WINS_SZ (0xA000) | ||
| 63 | 66 | ||
| 64 | /* | 67 | /* |
| 65 | * Register Map | 68 | * Register Map |
| 66 | */ | 69 | */ |
| 67 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) | 70 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) |
| 68 | #define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) | 71 | #define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) |
| 69 | #define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) | 72 | #define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) |
| 73 | #define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) | ||
| 74 | #define DDR_WINDOW_CPU_SZ (0x20) | ||
| 70 | 75 | ||
| 71 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) | 76 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) |
| 72 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) | 77 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) |
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index ee8c0b51df2c..dc26a654c496 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c | |||
| @@ -10,11 +10,11 @@ | |||
| 10 | 10 | ||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/pci.h> | 12 | #include <linux/pci.h> |
| 13 | #include <linux/mbus.h> | ||
| 13 | #include <video/vga.h> | 14 | #include <video/vga.h> |
| 14 | #include <asm/irq.h> | 15 | #include <asm/irq.h> |
| 15 | #include <asm/mach/pci.h> | 16 | #include <asm/mach/pci.h> |
| 16 | #include <plat/pcie.h> | 17 | #include <plat/pcie.h> |
| 17 | #include <plat/addr-map.h> | ||
| 18 | #include <mach/mv78xx0.h> | 18 | #include <mach/mv78xx0.h> |
| 19 | #include "common.h" | 19 | #include "common.h" |
| 20 | 20 | ||
| @@ -54,7 +54,6 @@ static void __init mv78xx0_pcie_preinit(void) | |||
| 54 | int i; | 54 | int i; |
| 55 | u32 size_each; | 55 | u32 size_each; |
| 56 | u32 start; | 56 | u32 start; |
| 57 | int win = 0; | ||
| 58 | 57 | ||
| 59 | pcie_io_space.name = "PCIe I/O Space"; | 58 | pcie_io_space.name = "PCIe I/O Space"; |
| 60 | pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); | 59 | pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); |
| @@ -72,6 +71,7 @@ static void __init mv78xx0_pcie_preinit(void) | |||
| 72 | start = MV78XX0_PCIE_MEM_PHYS_BASE; | 71 | start = MV78XX0_PCIE_MEM_PHYS_BASE; |
| 73 | for (i = 0; i < num_pcie_ports; i++) { | 72 | for (i = 0; i < num_pcie_ports; i++) { |
| 74 | struct pcie_port *pp = pcie_port + i; | 73 | struct pcie_port *pp = pcie_port + i; |
| 74 | char winname[MVEBU_MBUS_MAX_WINNAME_SZ]; | ||
| 75 | 75 | ||
| 76 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), | 76 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), |
| 77 | "PCIe %d.%d MEM", pp->maj, pp->min); | 77 | "PCIe %d.%d MEM", pp->maj, pp->min); |
| @@ -85,12 +85,17 @@ static void __init mv78xx0_pcie_preinit(void) | |||
| 85 | if (request_resource(&iomem_resource, &pp->res)) | 85 | if (request_resource(&iomem_resource, &pp->res)) |
| 86 | panic("can't allocate PCIe MEM sub-space"); | 86 | panic("can't allocate PCIe MEM sub-space"); |
| 87 | 87 | ||
| 88 | mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start, | 88 | snprintf(winname, sizeof(winname), "pcie%d.%d", |
| 89 | resource_size(&pp->res), | 89 | pp->maj, pp->min); |
| 90 | pp->maj, pp->min); | 90 | |
| 91 | 91 | mvebu_mbus_add_window_remap_flags(winname, | |
| 92 | mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K, | 92 | pp->res.start, |
| 93 | pp->maj, pp->min); | 93 | resource_size(&pp->res), |
| 94 | MVEBU_MBUS_NO_REMAP, | ||
| 95 | MVEBU_MBUS_PCI_MEM); | ||
| 96 | mvebu_mbus_add_window_remap_flags(winname, | ||
| 97 | i * SZ_64K, SZ_64K, | ||
| 98 | 0, MVEBU_MBUS_PCI_IO); | ||
| 94 | } | 99 | } |
| 95 | } | 100 | } |
| 96 | 101 | ||
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 440b13ef1fed..e11acbb0a46d 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig | |||
| @@ -13,6 +13,8 @@ config ARCH_MVEBU | |||
| 13 | select MVEBU_CLK_CORE | 13 | select MVEBU_CLK_CORE |
| 14 | select MVEBU_CLK_CPU | 14 | select MVEBU_CLK_CPU |
| 15 | select MVEBU_CLK_GATING | 15 | select MVEBU_CLK_GATING |
| 16 | select MVEBU_MBUS | ||
| 17 | select ZONE_DMA if ARM_LPAE | ||
| 16 | 18 | ||
| 17 | if ARCH_MVEBU | 19 | if ARCH_MVEBU |
| 18 | 20 | ||
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index da93bcbc74c1..ba769e082ad4 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile | |||
| @@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a | |||
| 5 | 5 | ||
| 6 | obj-y += system-controller.o | 6 | obj-y += system-controller.o |
| 7 | obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o | 7 | obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o |
| 8 | obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o | 8 | obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o |
| 9 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 9 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 10 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 10 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c deleted file mode 100644 index ab9b3bd4fef5..000000000000 --- a/arch/arm/mach-mvebu/addr-map.c +++ /dev/null | |||
| @@ -1,137 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Address map functions for Marvell 370 / XP SoCs | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Marvell | ||
| 5 | * | ||
| 6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/mbus.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/of.h> | ||
| 18 | #include <linux/of_address.h> | ||
| 19 | #include <plat/addr-map.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Generic Address Decode Windows bit settings | ||
| 23 | */ | ||
| 24 | #define ARMADA_XP_TARGET_DEV_BUS 1 | ||
| 25 | #define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D | ||
| 26 | #define ARMADA_XP_TARGET_ETH1 3 | ||
| 27 | #define ARMADA_XP_TARGET_PCIE_0_2 4 | ||
| 28 | #define ARMADA_XP_TARGET_ETH0 7 | ||
| 29 | #define ARMADA_XP_TARGET_PCIE_1_3 8 | ||
| 30 | |||
| 31 | #define ARMADA_370_TARGET_DEV_BUS 1 | ||
| 32 | #define ARMADA_370_ATTR_DEV_BOOTROM 0x1D | ||
| 33 | #define ARMADA_370_TARGET_PCIE_0 4 | ||
| 34 | #define ARMADA_370_TARGET_PCIE_1 8 | ||
| 35 | |||
| 36 | #define ARMADA_WINDOW_8_PLUS_OFFSET 0x90 | ||
| 37 | #define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180 | ||
| 38 | |||
| 39 | static const struct __initdata orion_addr_map_info | ||
| 40 | armada_xp_addr_map_info[] = { | ||
| 41 | /* | ||
| 42 | * Window for the BootROM, needed for SMP on Armada XP | ||
| 43 | */ | ||
| 44 | { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS, | ||
| 45 | ARMADA_XP_ATTR_DEV_BOOTROM, -1 }, | ||
| 46 | /* End marker */ | ||
| 47 | { -1, 0, 0, 0, 0, 0 }, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static const struct __initdata orion_addr_map_info | ||
| 51 | armada_370_addr_map_info[] = { | ||
| 52 | /* End marker */ | ||
| 53 | { -1, 0, 0, 0, 0, 0 }, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static struct of_device_id of_addr_decoding_controller_table[] = { | ||
| 57 | { .compatible = "marvell,armada-addr-decoding-controller" }, | ||
| 58 | { /* end of list */ }, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static void __iomem * | ||
| 62 | armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win) | ||
| 63 | { | ||
| 64 | unsigned int offset; | ||
| 65 | |||
| 66 | /* The register layout is a bit annoying and the below code | ||
| 67 | * tries to cope with it. | ||
| 68 | * - At offset 0x0, there are the registers for the first 8 | ||
| 69 | * windows, with 4 registers of 32 bits per window (ctrl, | ||
| 70 | * base, remap low, remap high) | ||
| 71 | * - Then at offset 0x80, there is a hole of 0x10 bytes for | ||
| 72 | * the internal registers base address and internal units | ||
| 73 | * sync barrier register. | ||
| 74 | * - Then at offset 0x90, there the registers for 12 | ||
| 75 | * windows, with only 2 registers of 32 bits per window | ||
| 76 | * (ctrl, base). | ||
| 77 | */ | ||
| 78 | if (win < 8) | ||
| 79 | offset = (win << 4); | ||
| 80 | else | ||
| 81 | offset = ARMADA_WINDOW_8_PLUS_OFFSET + ((win - 8) << 3); | ||
| 82 | |||
| 83 | return cfg->bridge_virt_base + offset; | ||
| 84 | } | ||
| 85 | |||
| 86 | static struct __initdata orion_addr_map_cfg addr_map_cfg = { | ||
| 87 | .num_wins = 20, | ||
| 88 | .remappable_wins = 8, | ||
| 89 | .win_cfg_base = armada_cfg_base, | ||
| 90 | }; | ||
| 91 | |||
| 92 | static int __init armada_setup_cpu_mbus(void) | ||
| 93 | { | ||
| 94 | struct device_node *np; | ||
| 95 | void __iomem *mbus_unit_addr_decoding_base; | ||
| 96 | void __iomem *sdram_addr_decoding_base; | ||
| 97 | |||
| 98 | np = of_find_matching_node(NULL, of_addr_decoding_controller_table); | ||
| 99 | if (!np) | ||
| 100 | return -ENODEV; | ||
| 101 | |||
| 102 | mbus_unit_addr_decoding_base = of_iomap(np, 0); | ||
| 103 | BUG_ON(!mbus_unit_addr_decoding_base); | ||
| 104 | |||
| 105 | sdram_addr_decoding_base = | ||
| 106 | mbus_unit_addr_decoding_base + | ||
| 107 | ARMADA_SDRAM_ADDR_DECODING_OFFSET; | ||
| 108 | |||
| 109 | addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base; | ||
| 110 | |||
| 111 | if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric")) | ||
| 112 | addr_map_cfg.hw_io_coherency = 1; | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Disable, clear and configure windows. | ||
| 116 | */ | ||
| 117 | if (of_machine_is_compatible("marvell,armadaxp")) | ||
| 118 | orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info); | ||
| 119 | else if (of_machine_is_compatible("marvell,armada370")) | ||
| 120 | orion_config_wins(&addr_map_cfg, armada_370_addr_map_info); | ||
| 121 | else { | ||
| 122 | pr_err("Unsupported SoC\n"); | ||
| 123 | return -EINVAL; | ||
| 124 | } | ||
| 125 | |||
| 126 | /* | ||
| 127 | * Setup MBUS dram target info. | ||
| 128 | */ | ||
| 129 | orion_setup_cpu_mbus_target(&addr_map_cfg, | ||
| 130 | sdram_addr_decoding_base); | ||
| 131 | return 0; | ||
| 132 | } | ||
| 133 | |||
| 134 | /* Using a early_initcall is needed so that this initialization gets | ||
| 135 | * done before the SMP initialization, which requires the BootROM to | ||
| 136 | * be remapped. */ | ||
| 137 | early_initcall(armada_setup_cpu_mbus); | ||
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index a5ea616d6d12..12d3655830d1 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/time-armada-370-xp.h> | 19 | #include <linux/time-armada-370-xp.h> |
| 20 | #include <linux/clk/mvebu.h> | 20 | #include <linux/clk/mvebu.h> |
| 21 | #include <linux/dma-mapping.h> | 21 | #include <linux/dma-mapping.h> |
| 22 | #include <linux/mbus.h> | ||
| 22 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
| 24 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
| @@ -48,12 +49,29 @@ void __init armada_370_xp_timer_and_clk_init(void) | |||
| 48 | 49 | ||
| 49 | void __init armada_370_xp_init_early(void) | 50 | void __init armada_370_xp_init_early(void) |
| 50 | { | 51 | { |
| 52 | char *mbus_soc_name; | ||
| 53 | |||
| 51 | /* | 54 | /* |
| 52 | * Some Armada 370/XP devices allocate their coherent buffers | 55 | * Some Armada 370/XP devices allocate their coherent buffers |
| 53 | * from atomic context. Increase size of atomic coherent pool | 56 | * from atomic context. Increase size of atomic coherent pool |
| 54 | * to make sure such the allocations won't fail. | 57 | * to make sure such the allocations won't fail. |
| 55 | */ | 58 | */ |
| 56 | init_dma_coherent_pool_size(SZ_1M); | 59 | init_dma_coherent_pool_size(SZ_1M); |
| 60 | |||
| 61 | /* | ||
| 62 | * This initialization will be replaced by a DT-based | ||
| 63 | * initialization once the mvebu-mbus driver gains DT support. | ||
| 64 | */ | ||
| 65 | if (of_machine_is_compatible("marvell,armada370")) | ||
| 66 | mbus_soc_name = "marvell,armada370-mbus"; | ||
| 67 | else | ||
| 68 | mbus_soc_name = "marvell,armadaxp-mbus"; | ||
| 69 | |||
| 70 | mvebu_mbus_init(mbus_soc_name, | ||
| 71 | ARMADA_370_XP_MBUS_WINS_BASE, | ||
| 72 | ARMADA_370_XP_MBUS_WINS_SIZE, | ||
| 73 | ARMADA_370_XP_SDRAM_WINS_BASE, | ||
| 74 | ARMADA_370_XP_SDRAM_WINS_SIZE); | ||
| 57 | } | 75 | } |
| 58 | 76 | ||
| 59 | static void __init armada_370_xp_dt_init(void) | 77 | static void __init armada_370_xp_dt_init(void) |
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h index c6a7d74fddfe..2070e1b4f342 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.h +++ b/arch/arm/mach-mvebu/armada-370-xp.h | |||
| @@ -16,9 +16,15 @@ | |||
| 16 | #define __MACH_ARMADA_370_XP_H | 16 | #define __MACH_ARMADA_370_XP_H |
| 17 | 17 | ||
| 18 | #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 | 18 | #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 |
| 19 | #define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000) | 19 | #define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000) |
| 20 | #define ARMADA_370_XP_REGS_SIZE SZ_1M | 20 | #define ARMADA_370_XP_REGS_SIZE SZ_1M |
| 21 | 21 | ||
| 22 | /* These defines can go away once mvebu-mbus has a DT binding */ | ||
| 23 | #define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000) | ||
| 24 | #define ARMADA_370_XP_MBUS_WINS_SIZE 0x100 | ||
| 25 | #define ARMADA_370_XP_SDRAM_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180) | ||
| 26 | #define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20 | ||
| 27 | |||
| 22 | #ifdef CONFIG_SMP | 28 | #ifdef CONFIG_SMP |
| 23 | #include <linux/cpumask.h> | 29 | #include <linux/cpumask.h> |
| 24 | 30 | ||
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c index 274ff58271de..d5970f5a1e8d 100644 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c | |||
| @@ -44,6 +44,8 @@ | |||
| 44 | 44 | ||
| 45 | #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) | 45 | #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) |
| 46 | 46 | ||
| 47 | #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) | ||
| 48 | |||
| 47 | #define ACTIVE_DOORBELLS (8) | 49 | #define ACTIVE_DOORBELLS (8) |
| 48 | 50 | ||
| 49 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); | 51 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
| @@ -59,36 +61,26 @@ static struct irq_domain *armada_370_xp_mpic_domain; | |||
| 59 | */ | 61 | */ |
| 60 | static void armada_370_xp_irq_mask(struct irq_data *d) | 62 | static void armada_370_xp_irq_mask(struct irq_data *d) |
| 61 | { | 63 | { |
| 62 | #ifdef CONFIG_SMP | ||
| 63 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | 64 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
| 64 | 65 | ||
| 65 | if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) | 66 | if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) |
| 66 | writel(hwirq, main_int_base + | 67 | writel(hwirq, main_int_base + |
| 67 | ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); | 68 | ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); |
| 68 | else | 69 | else |
| 69 | writel(hwirq, per_cpu_int_base + | 70 | writel(hwirq, per_cpu_int_base + |
| 70 | ARMADA_370_XP_INT_SET_MASK_OFFS); | 71 | ARMADA_370_XP_INT_SET_MASK_OFFS); |
| 71 | #else | ||
| 72 | writel(irqd_to_hwirq(d), | ||
| 73 | per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); | ||
| 74 | #endif | ||
| 75 | } | 72 | } |
| 76 | 73 | ||
| 77 | static void armada_370_xp_irq_unmask(struct irq_data *d) | 74 | static void armada_370_xp_irq_unmask(struct irq_data *d) |
| 78 | { | 75 | { |
| 79 | #ifdef CONFIG_SMP | ||
| 80 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | 76 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
| 81 | 77 | ||
| 82 | if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) | 78 | if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) |
| 83 | writel(hwirq, main_int_base + | 79 | writel(hwirq, main_int_base + |
| 84 | ARMADA_370_XP_INT_SET_ENABLE_OFFS); | 80 | ARMADA_370_XP_INT_SET_ENABLE_OFFS); |
| 85 | else | 81 | else |
| 86 | writel(hwirq, per_cpu_int_base + | 82 | writel(hwirq, per_cpu_int_base + |
| 87 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | 83 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); |
| 88 | #else | ||
| 89 | writel(irqd_to_hwirq(d), | ||
| 90 | per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | ||
| 91 | #endif | ||
| 92 | } | 84 | } |
| 93 | 85 | ||
| 94 | #ifdef CONFIG_SMP | 86 | #ifdef CONFIG_SMP |
| @@ -144,10 +136,14 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, | |||
| 144 | unsigned int virq, irq_hw_number_t hw) | 136 | unsigned int virq, irq_hw_number_t hw) |
| 145 | { | 137 | { |
| 146 | armada_370_xp_irq_mask(irq_get_irq_data(virq)); | 138 | armada_370_xp_irq_mask(irq_get_irq_data(virq)); |
| 147 | writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); | 139 | if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) |
| 140 | writel(hw, per_cpu_int_base + | ||
| 141 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | ||
| 142 | else | ||
| 143 | writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); | ||
| 148 | irq_set_status_flags(virq, IRQ_LEVEL); | 144 | irq_set_status_flags(virq, IRQ_LEVEL); |
| 149 | 145 | ||
| 150 | if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { | 146 | if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) { |
| 151 | irq_set_percpu_devid(virq); | 147 | irq_set_percpu_devid(virq); |
| 152 | irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, | 148 | irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, |
| 153 | handle_percpu_devid_irq); | 149 | handle_percpu_devid_irq); |
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index fe16aaf7c19c..875ea748391c 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <linux/smp.h> | 21 | #include <linux/smp.h> |
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/of.h> | 23 | #include <linux/of.h> |
| 24 | #include <linux/mbus.h> | ||
| 24 | #include <asm/cacheflush.h> | 25 | #include <asm/cacheflush.h> |
| 25 | #include <asm/smp_plat.h> | 26 | #include <asm/smp_plat.h> |
| 26 | #include "common.h" | 27 | #include "common.h" |
| @@ -109,6 +110,7 @@ void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) | |||
| 109 | set_secondary_cpus_clock(); | 110 | set_secondary_cpus_clock(); |
| 110 | flush_cache_all(); | 111 | flush_cache_all(); |
| 111 | set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); | 112 | set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); |
| 113 | mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M); | ||
| 112 | } | 114 | } |
| 113 | 115 | ||
| 114 | struct smp_operations armada_xp_smp_ops __initdata = { | 116 | struct smp_operations armada_xp_smp_ops __initdata = { |
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 9e809a7c05c0..45da805fb236 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | obj-y += common.o addr-map.o pci.o irq.o mpp.o | 1 | obj-y += common.o pci.o irq.o mpp.o |
| 2 | obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o | 2 | obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o |
| 3 | obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o | 3 | obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o |
| 4 | obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o | 4 | obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o |
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c deleted file mode 100644 index b5efc0fd31cb..000000000000 --- a/arch/arm/mach-orion5x/addr-map.c +++ /dev/null | |||
| @@ -1,155 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion5x/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Orion 5x SoCs | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/mbus.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <mach/hardware.h> | ||
| 18 | #include <plat/addr-map.h> | ||
| 19 | #include "common.h" | ||
| 20 | |||
| 21 | /* | ||
| 22 | * The Orion has fully programmable address map. There's a separate address | ||
| 23 | * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB, | ||
| 24 | * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own | ||
| 25 | * address decode windows that allow it to access any of the Orion resources. | ||
| 26 | * | ||
| 27 | * CPU address decoding -- | ||
| 28 | * Linux assumes that it is the boot loader that already setup the access to | ||
| 29 | * DDR and internal registers. | ||
| 30 | * Setup access to PCI and PCIe IO/MEM space is issued by this file. | ||
| 31 | * Setup access to various devices located on the device bus interface (e.g. | ||
| 32 | * flashes, RTC, etc) should be issued by machine-setup.c according to | ||
| 33 | * specific board population (by using orion5x_setup_*_win()). | ||
| 34 | * | ||
| 35 | * Non-CPU Masters address decoding -- | ||
| 36 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR | ||
| 37 | * banks only (the typical use case). | ||
| 38 | * Setup access for each master to DDR is issued by platform device setup. | ||
| 39 | */ | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Generic Address Decode Windows bit settings | ||
| 43 | */ | ||
| 44 | #define TARGET_DEV_BUS 1 | ||
| 45 | #define TARGET_PCI 3 | ||
| 46 | #define TARGET_PCIE 4 | ||
| 47 | #define TARGET_SRAM 9 | ||
| 48 | #define ATTR_PCIE_MEM 0x59 | ||
| 49 | #define ATTR_PCIE_IO 0x51 | ||
| 50 | #define ATTR_PCIE_WA 0x79 | ||
| 51 | #define ATTR_PCI_MEM 0x59 | ||
| 52 | #define ATTR_PCI_IO 0x51 | ||
| 53 | #define ATTR_DEV_CS0 0x1e | ||
| 54 | #define ATTR_DEV_CS1 0x1d | ||
| 55 | #define ATTR_DEV_CS2 0x1b | ||
| 56 | #define ATTR_DEV_BOOT 0xf | ||
| 57 | #define ATTR_SRAM 0x0 | ||
| 58 | |||
| 59 | static int __initdata win_alloc_count; | ||
| 60 | |||
| 61 | static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, | ||
| 62 | const int win) | ||
| 63 | { | ||
| 64 | u32 dev, rev; | ||
| 65 | |||
| 66 | orion5x_pcie_id(&dev, &rev); | ||
| 67 | if ((dev == MV88F5281_DEV_ID && win < 4) | ||
| 68 | || (dev == MV88F5182_DEV_ID && win < 2) | ||
| 69 | || (dev == MV88F5181_DEV_ID && win < 2) | ||
| 70 | || (dev == MV88F6183_DEV_ID && win < 4)) | ||
| 71 | return 1; | ||
| 72 | |||
| 73 | return 0; | ||
| 74 | } | ||
| 75 | |||
| 76 | /* | ||
| 77 | * Description of the windows needed by the platform code | ||
| 78 | */ | ||
| 79 | static struct orion_addr_map_cfg addr_map_cfg __initdata = { | ||
| 80 | .num_wins = 8, | ||
| 81 | .cpu_win_can_remap = cpu_win_can_remap, | ||
| 82 | .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static const struct __initdata orion_addr_map_info addr_map_info[] = { | ||
| 86 | /* | ||
| 87 | * Setup windows for PCI+PCIe IO+MEM space. | ||
| 88 | */ | ||
| 89 | { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, | ||
| 90 | TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE | ||
| 91 | }, | ||
| 92 | { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, | ||
| 93 | TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE | ||
| 94 | }, | ||
| 95 | { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, | ||
| 96 | TARGET_PCIE, ATTR_PCIE_MEM, -1 | ||
| 97 | }, | ||
| 98 | { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, | ||
| 99 | TARGET_PCI, ATTR_PCI_MEM, -1 | ||
| 100 | }, | ||
| 101 | /* End marker */ | ||
| 102 | { -1, 0, 0, 0, 0, 0 } | ||
| 103 | }; | ||
| 104 | |||
| 105 | void __init orion5x_setup_cpu_mbus_bridge(void) | ||
| 106 | { | ||
| 107 | /* | ||
| 108 | * Disable, clear and configure windows. | ||
| 109 | */ | ||
| 110 | orion_config_wins(&addr_map_cfg, addr_map_info); | ||
| 111 | win_alloc_count = 4; | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Setup MBUS dram target info. | ||
| 115 | */ | ||
| 116 | orion_setup_cpu_mbus_target(&addr_map_cfg, | ||
| 117 | (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE); | ||
| 118 | } | ||
| 119 | |||
| 120 | void __init orion5x_setup_dev_boot_win(u32 base, u32 size) | ||
| 121 | { | ||
| 122 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, | ||
| 123 | TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); | ||
| 124 | } | ||
| 125 | |||
| 126 | void __init orion5x_setup_dev0_win(u32 base, u32 size) | ||
| 127 | { | ||
| 128 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, | ||
| 129 | TARGET_DEV_BUS, ATTR_DEV_CS0, -1); | ||
| 130 | } | ||
| 131 | |||
| 132 | void __init orion5x_setup_dev1_win(u32 base, u32 size) | ||
| 133 | { | ||
| 134 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, | ||
| 135 | TARGET_DEV_BUS, ATTR_DEV_CS1, -1); | ||
| 136 | } | ||
| 137 | |||
| 138 | void __init orion5x_setup_dev2_win(u32 base, u32 size) | ||
| 139 | { | ||
| 140 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, | ||
| 141 | TARGET_DEV_BUS, ATTR_DEV_CS2, -1); | ||
| 142 | } | ||
| 143 | |||
| 144 | void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) | ||
| 145 | { | ||
| 146 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, | ||
| 147 | TARGET_PCIE, ATTR_PCIE_WA, -1); | ||
| 148 | } | ||
| 149 | |||
| 150 | void __init orion5x_setup_sram_win(void) | ||
| 151 | { | ||
| 152 | orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, | ||
| 153 | ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, | ||
| 154 | TARGET_SRAM, ATTR_SRAM, -1); | ||
| 155 | } | ||
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 35a8014529ca..6bbc8786c1e3 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c | |||
| @@ -41,7 +41,7 @@ static void __init orion5x_dt_init(void) | |||
| 41 | /* | 41 | /* |
| 42 | * Setup Orion address map | 42 | * Setup Orion address map |
| 43 | */ | 43 | */ |
| 44 | orion5x_setup_cpu_mbus_bridge(); | 44 | orion5x_setup_wins(); |
| 45 | 45 | ||
| 46 | /* Setup root of clk tree */ | 46 | /* Setup root of clk tree */ |
| 47 | clk_init(); | 47 | clk_init(); |
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index d068f1431c40..8e468e3a6015 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
| @@ -34,7 +34,6 @@ | |||
| 34 | #include <linux/platform_data/usb-ehci-orion.h> | 34 | #include <linux/platform_data/usb-ehci-orion.h> |
| 35 | #include <plat/time.h> | 35 | #include <plat/time.h> |
| 36 | #include <plat/common.h> | 36 | #include <plat/common.h> |
| 37 | #include <plat/addr-map.h> | ||
| 38 | #include "common.h" | 37 | #include "common.h" |
| 39 | 38 | ||
| 40 | /***************************************************************************** | 39 | /***************************************************************************** |
| @@ -174,7 +173,8 @@ void __init orion5x_xor_init(void) | |||
| 174 | ****************************************************************************/ | 173 | ****************************************************************************/ |
| 175 | static void __init orion5x_crypto_init(void) | 174 | static void __init orion5x_crypto_init(void) |
| 176 | { | 175 | { |
| 177 | orion5x_setup_sram_win(); | 176 | mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE, |
| 177 | ORION5X_SRAM_SIZE); | ||
| 178 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, | 178 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
| 179 | SZ_8K, IRQ_ORION5X_CESA); | 179 | SZ_8K, IRQ_ORION5X_CESA); |
| 180 | } | 180 | } |
| @@ -193,6 +193,9 @@ void __init orion5x_wdt_init(void) | |||
| 193 | ****************************************************************************/ | 193 | ****************************************************************************/ |
| 194 | void __init orion5x_init_early(void) | 194 | void __init orion5x_init_early(void) |
| 195 | { | 195 | { |
| 196 | u32 rev, dev; | ||
| 197 | const char *mbus_soc_name; | ||
| 198 | |||
| 196 | orion_time_set_base(TIMER_VIRT_BASE); | 199 | orion_time_set_base(TIMER_VIRT_BASE); |
| 197 | 200 | ||
| 198 | /* | 201 | /* |
| @@ -201,6 +204,46 @@ void __init orion5x_init_early(void) | |||
| 201 | * the allocations won't fail. | 204 | * the allocations won't fail. |
| 202 | */ | 205 | */ |
| 203 | init_dma_coherent_pool_size(SZ_1M); | 206 | init_dma_coherent_pool_size(SZ_1M); |
| 207 | |||
| 208 | /* Initialize the MBUS driver */ | ||
| 209 | orion5x_pcie_id(&dev, &rev); | ||
| 210 | if (dev == MV88F5281_DEV_ID) | ||
| 211 | mbus_soc_name = "marvell,orion5x-88f5281-mbus"; | ||
| 212 | else if (dev == MV88F5182_DEV_ID) | ||
| 213 | mbus_soc_name = "marvell,orion5x-88f5182-mbus"; | ||
| 214 | else if (dev == MV88F5181_DEV_ID) | ||
| 215 | mbus_soc_name = "marvell,orion5x-88f5181-mbus"; | ||
| 216 | else if (dev == MV88F6183_DEV_ID) | ||
| 217 | mbus_soc_name = "marvell,orion5x-88f6183-mbus"; | ||
| 218 | else | ||
| 219 | mbus_soc_name = NULL; | ||
| 220 | mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, | ||
| 221 | ORION5X_BRIDGE_WINS_SZ, | ||
| 222 | ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); | ||
| 223 | } | ||
| 224 | |||
| 225 | void orion5x_setup_wins(void) | ||
| 226 | { | ||
| 227 | /* | ||
| 228 | * The PCIe windows will no longer be statically allocated | ||
| 229 | * here once Orion5x is migrated to the pci-mvebu driver. | ||
| 230 | */ | ||
| 231 | mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE, | ||
| 232 | ORION5X_PCIE_IO_SIZE, | ||
| 233 | ORION5X_PCIE_IO_BUS_BASE, | ||
| 234 | MVEBU_MBUS_PCI_IO); | ||
| 235 | mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE, | ||
| 236 | ORION5X_PCIE_MEM_SIZE, | ||
| 237 | MVEBU_MBUS_NO_REMAP, | ||
| 238 | MVEBU_MBUS_PCI_MEM); | ||
| 239 | mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE, | ||
| 240 | ORION5X_PCI_IO_SIZE, | ||
| 241 | ORION5X_PCI_IO_BUS_BASE, | ||
| 242 | MVEBU_MBUS_PCI_IO); | ||
| 243 | mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE, | ||
| 244 | ORION5X_PCI_MEM_SIZE, | ||
| 245 | MVEBU_MBUS_NO_REMAP, | ||
| 246 | MVEBU_MBUS_PCI_MEM); | ||
| 204 | } | 247 | } |
| 205 | 248 | ||
| 206 | int orion5x_tclk; | 249 | int orion5x_tclk; |
| @@ -282,7 +325,7 @@ void __init orion5x_init(void) | |||
| 282 | /* | 325 | /* |
| 283 | * Setup Orion address map | 326 | * Setup Orion address map |
| 284 | */ | 327 | */ |
| 285 | orion5x_setup_cpu_mbus_bridge(); | 328 | orion5x_setup_wins(); |
| 286 | 329 | ||
| 287 | /* Setup root of clk tree */ | 330 | /* Setup root of clk tree */ |
| 288 | clk_init(); | 331 | clk_init(); |
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index e60345760283..cdaa01f3d186 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h | |||
| @@ -17,18 +17,7 @@ void clk_init(void); | |||
| 17 | extern int orion5x_tclk; | 17 | extern int orion5x_tclk; |
| 18 | extern void orion5x_timer_init(void); | 18 | extern void orion5x_timer_init(void); |
| 19 | 19 | ||
| 20 | /* | 20 | void orion5x_setup_wins(void); |
| 21 | * Enumerations and functions for Orion windows mapping. Used by Orion core | ||
| 22 | * functions to map its interfaces and by the machine-setup to map its on- | ||
| 23 | * board devices. Details in /mach-orion/addr-map.c | ||
| 24 | */ | ||
| 25 | void orion5x_setup_cpu_mbus_bridge(void); | ||
| 26 | void orion5x_setup_dev_boot_win(u32 base, u32 size); | ||
| 27 | void orion5x_setup_dev0_win(u32 base, u32 size); | ||
| 28 | void orion5x_setup_dev1_win(u32 base, u32 size); | ||
| 29 | void orion5x_setup_dev2_win(u32 base, u32 size); | ||
| 30 | void orion5x_setup_pcie_wa_win(u32 base, u32 size); | ||
| 31 | void orion5x_setup_sram_win(void); | ||
| 32 | 21 | ||
| 33 | void orion5x_ehci0_init(void); | 22 | void orion5x_ehci0_init(void); |
| 34 | void orion5x_ehci1_init(void); | 23 | void orion5x_ehci1_init(void); |
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 57d0af74874d..16c88bbabc98 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c | |||
| @@ -317,8 +317,8 @@ static void __init d2net_init(void) | |||
| 317 | d2net_sata_power_init(); | 317 | d2net_sata_power_init(); |
| 318 | orion5x_sata_init(&d2net_sata_data); | 318 | orion5x_sata_init(&d2net_sata_data); |
| 319 | 319 | ||
| 320 | orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE, | 320 | mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE, |
| 321 | D2NET_NOR_BOOT_SIZE); | 321 | D2NET_NOR_BOOT_SIZE); |
| 322 | platform_device_register(&d2net_nor_flash); | 322 | platform_device_register(&d2net_nor_flash); |
| 323 | 323 | ||
| 324 | platform_device_register(&d2net_gpio_buttons); | 324 | platform_device_register(&d2net_gpio_buttons); |
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 76665640087b..4e1263da38bb 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c | |||
| @@ -340,16 +340,19 @@ static void __init db88f5281_init(void) | |||
| 340 | orion5x_uart0_init(); | 340 | orion5x_uart0_init(); |
| 341 | orion5x_uart1_init(); | 341 | orion5x_uart1_init(); |
| 342 | 342 | ||
| 343 | orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, | 343 | mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE, |
| 344 | DB88F5281_NOR_BOOT_SIZE); | 344 | DB88F5281_NOR_BOOT_SIZE); |
| 345 | platform_device_register(&db88f5281_boot_flash); | 345 | platform_device_register(&db88f5281_boot_flash); |
| 346 | 346 | ||
| 347 | orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); | 347 | mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE, |
| 348 | DB88F5281_7SEG_SIZE); | ||
| 348 | 349 | ||
| 349 | orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); | 350 | mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE, |
| 351 | DB88F5281_NOR_SIZE); | ||
| 350 | platform_device_register(&db88f5281_nor_flash); | 352 | platform_device_register(&db88f5281_nor_flash); |
| 351 | 353 | ||
| 352 | orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); | 354 | mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE, |
| 355 | DB88F5281_NAND_SIZE); | ||
| 353 | platform_device_register(&db88f5281_nand_flash); | 356 | platform_device_register(&db88f5281_nand_flash); |
| 354 | 357 | ||
| 355 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); | 358 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); |
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 6eb1732757fd..9e6baf581ed3 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c | |||
| @@ -611,7 +611,8 @@ static void __init dns323_init(void) | |||
| 611 | /* setup flash mapping | 611 | /* setup flash mapping |
| 612 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 | 612 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 |
| 613 | */ | 613 | */ |
| 614 | orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); | 614 | mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE, |
| 615 | DNS323_NOR_BOOT_SIZE); | ||
| 615 | platform_device_register(&dns323_nor_flash); | 616 | platform_device_register(&dns323_nor_flash); |
| 616 | 617 | ||
| 617 | /* Sort out LEDs, Buttons and i2c devices */ | 618 | /* Sort out LEDs, Buttons and i2c devices */ |
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index d675e727803d..147615510dd0 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c | |||
| @@ -154,8 +154,8 @@ void __init edmini_v2_init(void) | |||
| 154 | orion5x_ehci0_init(); | 154 | orion5x_ehci0_init(); |
| 155 | orion5x_eth_init(&edmini_v2_eth_data); | 155 | orion5x_eth_init(&edmini_v2_eth_data); |
| 156 | 156 | ||
| 157 | orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE, | 157 | mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE, |
| 158 | EDMINI_V2_NOR_BOOT_SIZE); | 158 | EDMINI_V2_NOR_BOOT_SIZE); |
| 159 | platform_device_register(&edmini_v2_nor_flash); | 159 | platform_device_register(&edmini_v2_nor_flash); |
| 160 | 160 | ||
| 161 | pr_notice("edmini_v2: USB device port, flash write and power-off " | 161 | pr_notice("edmini_v2: USB device port, flash write and power-off " |
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index d265f5484a8e..b78ff3248868 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h | |||
| @@ -66,8 +66,10 @@ | |||
| 66 | * Orion Registers Map | 66 | * Orion Registers Map |
| 67 | ******************************************************************************/ | 67 | ******************************************************************************/ |
| 68 | 68 | ||
| 69 | #define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000) | ||
| 70 | #define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500) | ||
| 71 | #define ORION5X_DDR_WINS_SZ (0x10) | ||
| 69 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) | 72 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) |
| 70 | #define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500) | ||
| 71 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) | 73 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) |
| 72 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) | 74 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) |
| 73 | #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) | 75 | #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) |
| @@ -81,6 +83,8 @@ | |||
| 81 | 83 | ||
| 82 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) | 84 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) |
| 83 | #define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) | 85 | #define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) |
| 86 | #define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE) | ||
| 87 | #define ORION5X_BRIDGE_WINS_SZ (0x80) | ||
| 84 | 88 | ||
| 85 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) | 89 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) |
| 86 | 90 | ||
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index b98403526218..aae10e4a917c 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c | |||
| @@ -359,13 +359,13 @@ static void __init kurobox_pro_init(void) | |||
| 359 | orion5x_uart1_init(); | 359 | orion5x_uart1_init(); |
| 360 | orion5x_xor_init(); | 360 | orion5x_xor_init(); |
| 361 | 361 | ||
| 362 | orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, | 362 | mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE, |
| 363 | KUROBOX_PRO_NOR_BOOT_SIZE); | 363 | KUROBOX_PRO_NOR_BOOT_SIZE); |
| 364 | platform_device_register(&kurobox_pro_nor_flash); | 364 | platform_device_register(&kurobox_pro_nor_flash); |
| 365 | 365 | ||
| 366 | if (machine_is_kurobox_pro()) { | 366 | if (machine_is_kurobox_pro()) { |
| 367 | orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, | 367 | mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE, |
| 368 | KUROBOX_PRO_NAND_SIZE); | 368 | KUROBOX_PRO_NAND_SIZE); |
| 369 | platform_device_register(&kurobox_pro_nand_flash); | 369 | platform_device_register(&kurobox_pro_nand_flash); |
| 370 | } | 370 | } |
| 371 | 371 | ||
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 044da5b6a6ae..24f4e14e5893 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c | |||
| @@ -294,8 +294,8 @@ static void __init lschl_init(void) | |||
| 294 | orion5x_uart0_init(); | 294 | orion5x_uart0_init(); |
| 295 | orion5x_xor_init(); | 295 | orion5x_xor_init(); |
| 296 | 296 | ||
| 297 | orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE, | 297 | mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE, |
| 298 | LSCHL_NOR_BOOT_SIZE); | 298 | LSCHL_NOR_BOOT_SIZE); |
| 299 | platform_device_register(&lschl_nor_flash); | 299 | platform_device_register(&lschl_nor_flash); |
| 300 | 300 | ||
| 301 | platform_device_register(&lschl_leds); | 301 | platform_device_register(&lschl_leds); |
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index d49f93423f52..fc653bb41e78 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c | |||
| @@ -243,8 +243,8 @@ static void __init ls_hgl_init(void) | |||
| 243 | orion5x_uart0_init(); | 243 | orion5x_uart0_init(); |
| 244 | orion5x_xor_init(); | 244 | orion5x_xor_init(); |
| 245 | 245 | ||
| 246 | orion5x_setup_dev_boot_win(LS_HGL_NOR_BOOT_BASE, | 246 | mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE, |
| 247 | LS_HGL_NOR_BOOT_SIZE); | 247 | LS_HGL_NOR_BOOT_SIZE); |
| 248 | platform_device_register(&ls_hgl_nor_flash); | 248 | platform_device_register(&ls_hgl_nor_flash); |
| 249 | 249 | ||
| 250 | platform_device_register(&ls_hgl_button_device); | 250 | platform_device_register(&ls_hgl_button_device); |
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index 8e3965c6c0fe..18e66e617dc2 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c | |||
| @@ -244,8 +244,8 @@ static void __init lsmini_init(void) | |||
| 244 | orion5x_uart0_init(); | 244 | orion5x_uart0_init(); |
| 245 | orion5x_xor_init(); | 245 | orion5x_xor_init(); |
| 246 | 246 | ||
| 247 | orion5x_setup_dev_boot_win(LSMINI_NOR_BOOT_BASE, | 247 | mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE, |
| 248 | LSMINI_NOR_BOOT_SIZE); | 248 | LSMINI_NOR_BOOT_SIZE); |
| 249 | platform_device_register(&lsmini_nor_flash); | 249 | platform_device_register(&lsmini_nor_flash); |
| 250 | 250 | ||
| 251 | platform_device_register(&lsmini_button_device); | 251 | platform_device_register(&lsmini_button_device); |
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 0ec94a1f2b16..827acbafc9dc 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c | |||
| @@ -241,7 +241,8 @@ static void __init mss2_init(void) | |||
| 241 | orion5x_uart0_init(); | 241 | orion5x_uart0_init(); |
| 242 | orion5x_xor_init(); | 242 | orion5x_xor_init(); |
| 243 | 243 | ||
| 244 | orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE); | 244 | mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE, |
| 245 | MSS2_NOR_BOOT_SIZE); | ||
| 245 | platform_device_register(&mss2_nor_flash); | 246 | platform_device_register(&mss2_nor_flash); |
| 246 | 247 | ||
| 247 | platform_device_register(&mss2_button_device); | 248 | platform_device_register(&mss2_button_device); |
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index 18143f2a9093..92600ae2b4b6 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c | |||
| @@ -204,7 +204,8 @@ static void __init mv2120_init(void) | |||
| 204 | orion5x_uart0_init(); | 204 | orion5x_uart0_init(); |
| 205 | orion5x_xor_init(); | 205 | orion5x_xor_init(); |
| 206 | 206 | ||
| 207 | orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE); | 207 | mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE, |
| 208 | MV2120_NOR_BOOT_SIZE); | ||
| 208 | platform_device_register(&mv2120_nor_flash); | 209 | platform_device_register(&mv2120_nor_flash); |
| 209 | 210 | ||
| 210 | platform_device_register(&mv2120_button_device); | 211 | platform_device_register(&mv2120_button_device); |
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index 282e503b003e..dd0641a0d074 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c | |||
| @@ -397,8 +397,8 @@ static void __init net2big_init(void) | |||
| 397 | net2big_sata_power_init(); | 397 | net2big_sata_power_init(); |
| 398 | orion5x_sata_init(&net2big_sata_data); | 398 | orion5x_sata_init(&net2big_sata_data); |
| 399 | 399 | ||
| 400 | orion5x_setup_dev_boot_win(NET2BIG_NOR_BOOT_BASE, | 400 | mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE, |
| 401 | NET2BIG_NOR_BOOT_SIZE); | 401 | NET2BIG_NOR_BOOT_SIZE); |
| 402 | platform_device_register(&net2big_nor_flash); | 402 | platform_device_register(&net2big_nor_flash); |
| 403 | 403 | ||
| 404 | platform_device_register(&net2big_gpio_buttons); | 404 | platform_device_register(&net2big_gpio_buttons); |
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index d9c7c3bf0d9c..503368023bb1 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c | |||
| @@ -157,8 +157,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
| 157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | 157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { |
| 158 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " | 158 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " |
| 159 | "read transaction workaround\n"); | 159 | "read transaction workaround\n"); |
| 160 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, | 160 | mvebu_mbus_add_window_remap_flags("pcie0.0", |
| 161 | ORION5X_PCIE_WA_SIZE); | 161 | ORION5X_PCIE_WA_PHYS_BASE, |
| 162 | ORION5X_PCIE_WA_SIZE, | ||
| 163 | MVEBU_MBUS_NO_REMAP, | ||
| 164 | MVEBU_MBUS_PCI_WA); | ||
| 162 | pcie_ops.read = pcie_rd_conf_wa; | 165 | pcie_ops.read = pcie_rd_conf_wa; |
| 163 | } | 166 | } |
| 164 | 167 | ||
| @@ -402,8 +405,9 @@ static void __init orion5x_pci_master_slave_enable(void) | |||
| 402 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); | 405 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
| 403 | } | 406 | } |
| 404 | 407 | ||
| 405 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) | 408 | static void __init orion5x_setup_pci_wins(void) |
| 406 | { | 409 | { |
| 410 | const struct mbus_dram_target_info *dram = mv_mbus_dram_info(); | ||
| 407 | u32 win_enable; | 411 | u32 win_enable; |
| 408 | int bus; | 412 | int bus; |
| 409 | int i; | 413 | int i; |
| @@ -420,7 +424,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) | |||
| 420 | bus = orion5x_pci_local_bus_nr(); | 424 | bus = orion5x_pci_local_bus_nr(); |
| 421 | 425 | ||
| 422 | for (i = 0; i < dram->num_cs; i++) { | 426 | for (i = 0; i < dram->num_cs; i++) { |
| 423 | struct mbus_dram_window *cs = dram->cs + i; | 427 | const struct mbus_dram_window *cs = dram->cs + i; |
| 424 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); | 428 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); |
| 425 | u32 reg; | 429 | u32 reg; |
| 426 | u32 val; | 430 | u32 val; |
| @@ -467,7 +471,7 @@ static int __init pci_setup(struct pci_sys_data *sys) | |||
| 467 | /* | 471 | /* |
| 468 | * Point PCI unit MBUS decode windows to DRAM space. | 472 | * Point PCI unit MBUS decode windows to DRAM space. |
| 469 | */ | 473 | */ |
| 470 | orion5x_setup_pci_wins(&orion_mbus_dram_info); | 474 | orion5x_setup_pci_wins(); |
| 471 | 475 | ||
| 472 | /* | 476 | /* |
| 473 | * Master + Slave enable | 477 | * Master + Slave enable |
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index d6e72f672afb..1c4498bf650a 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | |||
| @@ -123,8 +123,8 @@ static void __init rd88f5181l_fxo_init(void) | |||
| 123 | orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); | 123 | orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); |
| 124 | orion5x_uart0_init(); | 124 | orion5x_uart0_init(); |
| 125 | 125 | ||
| 126 | orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE, | 126 | mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE, |
| 127 | RD88F5181L_FXO_NOR_BOOT_SIZE); | 127 | RD88F5181L_FXO_NOR_BOOT_SIZE); |
| 128 | platform_device_register(&rd88f5181l_fxo_nor_boot_flash); | 128 | platform_device_register(&rd88f5181l_fxo_nor_boot_flash); |
| 129 | } | 129 | } |
| 130 | 130 | ||
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index c8b7913310e5..adabe34c4fc6 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | |||
| @@ -130,8 +130,8 @@ static void __init rd88f5181l_ge_init(void) | |||
| 130 | orion5x_i2c_init(); | 130 | orion5x_i2c_init(); |
| 131 | orion5x_uart0_init(); | 131 | orion5x_uart0_init(); |
| 132 | 132 | ||
| 133 | orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE, | 133 | mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE, |
| 134 | RD88F5181L_GE_NOR_BOOT_SIZE); | 134 | RD88F5181L_GE_NOR_BOOT_SIZE); |
| 135 | platform_device_register(&rd88f5181l_ge_nor_boot_flash); | 135 | platform_device_register(&rd88f5181l_ge_nor_boot_flash); |
| 136 | 136 | ||
| 137 | i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); | 137 | i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); |
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index f9e156725d7c..66e77ec91532 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c | |||
| @@ -264,10 +264,11 @@ static void __init rd88f5182_init(void) | |||
| 264 | orion5x_uart0_init(); | 264 | orion5x_uart0_init(); |
| 265 | orion5x_xor_init(); | 265 | orion5x_xor_init(); |
| 266 | 266 | ||
| 267 | orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, | 267 | mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE, |
| 268 | RD88F5182_NOR_BOOT_SIZE); | 268 | RD88F5182_NOR_BOOT_SIZE); |
| 269 | 269 | ||
| 270 | orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); | 270 | mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE, |
| 271 | RD88F5182_NOR_SIZE); | ||
| 271 | platform_device_register(&rd88f5182_nor_flash); | 272 | platform_device_register(&rd88f5182_nor_flash); |
| 272 | platform_device_register(&rd88f5182_gpio_leds); | 273 | platform_device_register(&rd88f5182_gpio_leds); |
| 273 | 274 | ||
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index acc0877ec1c9..a0bfa53e7556 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c | |||
| @@ -329,8 +329,8 @@ static void __init tsp2_init(void) | |||
| 329 | /* | 329 | /* |
| 330 | * Configure peripherals. | 330 | * Configure peripherals. |
| 331 | */ | 331 | */ |
| 332 | orion5x_setup_dev_boot_win(TSP2_NOR_BOOT_BASE, | 332 | mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE, |
| 333 | TSP2_NOR_BOOT_SIZE); | 333 | TSP2_NOR_BOOT_SIZE); |
| 334 | platform_device_register(&tsp2_nor_flash); | 334 | platform_device_register(&tsp2_nor_flash); |
| 335 | 335 | ||
| 336 | orion5x_ehci0_init(); | 336 | orion5x_ehci0_init(); |
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 9c17f0c2b488..80174f0f168e 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c | |||
| @@ -286,8 +286,8 @@ static void __init qnap_ts209_init(void) | |||
| 286 | /* | 286 | /* |
| 287 | * Configure peripherals. | 287 | * Configure peripherals. |
| 288 | */ | 288 | */ |
| 289 | orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, | 289 | mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE, |
| 290 | QNAP_TS209_NOR_BOOT_SIZE); | 290 | QNAP_TS209_NOR_BOOT_SIZE); |
| 291 | platform_device_register(&qnap_ts209_nor_flash); | 291 | platform_device_register(&qnap_ts209_nor_flash); |
| 292 | 292 | ||
| 293 | orion5x_ehci0_init(); | 293 | orion5x_ehci0_init(); |
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 8cc5ab6c503e..92592790d6da 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c | |||
| @@ -277,8 +277,8 @@ static void __init qnap_ts409_init(void) | |||
| 277 | /* | 277 | /* |
| 278 | * Configure peripherals. | 278 | * Configure peripherals. |
| 279 | */ | 279 | */ |
| 280 | orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE, | 280 | mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE, |
| 281 | QNAP_TS409_NOR_BOOT_SIZE); | 281 | QNAP_TS409_NOR_BOOT_SIZE); |
| 282 | platform_device_register(&qnap_ts409_nor_flash); | 282 | platform_device_register(&qnap_ts409_nor_flash); |
| 283 | 283 | ||
| 284 | orion5x_ehci0_init(); | 284 | orion5x_ehci0_init(); |
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 66552ca7e05d..6b84863c018d 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c | |||
| @@ -127,8 +127,8 @@ static void __init wnr854t_init(void) | |||
| 127 | orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); | 127 | orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); |
| 128 | orion5x_uart0_init(); | 128 | orion5x_uart0_init(); |
| 129 | 129 | ||
| 130 | orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE, | 130 | mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE, |
| 131 | WNR854T_NOR_BOOT_SIZE); | 131 | WNR854T_NOR_BOOT_SIZE); |
| 132 | platform_device_register(&wnr854t_nor_flash); | 132 | platform_device_register(&wnr854t_nor_flash); |
| 133 | } | 133 | } |
| 134 | 134 | ||
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index 2c5408e2e689..fae684bc54f2 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c | |||
| @@ -213,8 +213,8 @@ static void __init wrt350n_v2_init(void) | |||
| 213 | orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); | 213 | orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); |
| 214 | orion5x_uart0_init(); | 214 | orion5x_uart0_init(); |
| 215 | 215 | ||
| 216 | orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE, | 216 | mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE, |
| 217 | WRT350N_V2_NOR_BOOT_SIZE); | 217 | WRT350N_V2_NOR_BOOT_SIZE); |
| 218 | platform_device_register(&wrt350n_v2_nor_flash); | 218 | platform_device_register(&wrt350n_v2_nor_flash); |
| 219 | platform_device_register(&wrt350n_v2_leds); | 219 | platform_device_register(&wrt350n_v2_leds); |
| 220 | platform_device_register(&wrt350n_v2_button_device); | 220 | platform_device_register(&wrt350n_v2_button_device); |
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index a82cecb84948..2eca54b65906 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile | |||
| @@ -3,8 +3,6 @@ | |||
| 3 | # | 3 | # |
| 4 | ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include | 4 | ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include |
| 5 | 5 | ||
| 6 | obj-y += addr-map.o | ||
| 7 | |||
| 8 | orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o | 6 | orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o |
| 9 | obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o | 7 | obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o |
| 10 | obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y) | 8 | obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y) |
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c deleted file mode 100644 index 807ac8e5cbc0..000000000000 --- a/arch/arm/plat-orion/addr-map.c +++ /dev/null | |||
| @@ -1,178 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Orion based SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/mbus.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <plat/addr-map.h> | ||
| 17 | |||
| 18 | struct mbus_dram_target_info orion_mbus_dram_info; | ||
| 19 | |||
| 20 | const struct mbus_dram_target_info *mv_mbus_dram_info(void) | ||
| 21 | { | ||
| 22 | return &orion_mbus_dram_info; | ||
| 23 | } | ||
| 24 | EXPORT_SYMBOL_GPL(mv_mbus_dram_info); | ||
| 25 | |||
| 26 | /* | ||
| 27 | * DDR target is the same on all Orion platforms. | ||
| 28 | */ | ||
| 29 | #define TARGET_DDR 0 | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Helpers to get DDR bank info | ||
| 33 | */ | ||
| 34 | #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) | ||
| 35 | #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) | ||
| 36 | |||
| 37 | /* | ||
| 38 | * CPU Address Decode Windows registers | ||
| 39 | */ | ||
| 40 | #define WIN_CTRL_OFF 0x0000 | ||
| 41 | #define WIN_BASE_OFF 0x0004 | ||
| 42 | #define WIN_REMAP_LO_OFF 0x0008 | ||
| 43 | #define WIN_REMAP_HI_OFF 0x000c | ||
| 44 | |||
| 45 | #define ATTR_HW_COHERENCY (0x1 << 4) | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Default implementation | ||
| 49 | */ | ||
| 50 | static void __init __iomem * | ||
| 51 | orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) | ||
| 52 | { | ||
| 53 | return cfg->bridge_virt_base + (win << 4); | ||
| 54 | } | ||
| 55 | |||
| 56 | /* | ||
| 57 | * Default implementation | ||
| 58 | */ | ||
| 59 | static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, | ||
| 60 | const int win) | ||
| 61 | { | ||
| 62 | if (win < cfg->remappable_wins) | ||
| 63 | return 1; | ||
| 64 | |||
| 65 | return 0; | ||
| 66 | } | ||
| 67 | |||
| 68 | void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, | ||
| 69 | const int win, const u32 base, | ||
| 70 | const u32 size, const u8 target, | ||
| 71 | const u8 attr, const int remap) | ||
| 72 | { | ||
| 73 | void __iomem *addr = cfg->win_cfg_base(cfg, win); | ||
| 74 | u32 ctrl, base_high, remap_addr; | ||
| 75 | |||
| 76 | if (win >= cfg->num_wins) { | ||
| 77 | printk(KERN_ERR "setup_cpu_win: trying to allocate window " | ||
| 78 | "%d when only %d allowed\n", win, cfg->num_wins); | ||
| 79 | } | ||
| 80 | |||
| 81 | base_high = base & 0xffff0000; | ||
| 82 | ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; | ||
| 83 | |||
| 84 | writel(base_high, addr + WIN_BASE_OFF); | ||
| 85 | writel(ctrl, addr + WIN_CTRL_OFF); | ||
| 86 | if (cfg->cpu_win_can_remap(cfg, win)) { | ||
| 87 | if (remap < 0) | ||
| 88 | remap_addr = base; | ||
| 89 | else | ||
| 90 | remap_addr = remap; | ||
| 91 | writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF); | ||
| 92 | writel(0, addr + WIN_REMAP_HI_OFF); | ||
| 93 | } | ||
| 94 | } | ||
| 95 | |||
| 96 | /* | ||
| 97 | * Configure a number of windows. | ||
| 98 | */ | ||
| 99 | static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg, | ||
| 100 | const struct orion_addr_map_info *info) | ||
| 101 | { | ||
| 102 | while (info->win != -1) { | ||
| 103 | orion_setup_cpu_win(cfg, info->win, info->base, info->size, | ||
| 104 | info->target, info->attr, info->remap); | ||
| 105 | info++; | ||
| 106 | } | ||
| 107 | } | ||
| 108 | |||
| 109 | static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg) | ||
| 110 | { | ||
| 111 | void __iomem *addr; | ||
| 112 | int i; | ||
| 113 | |||
| 114 | for (i = 0; i < cfg->num_wins; i++) { | ||
| 115 | addr = cfg->win_cfg_base(cfg, i); | ||
| 116 | |||
| 117 | writel(0, addr + WIN_BASE_OFF); | ||
| 118 | writel(0, addr + WIN_CTRL_OFF); | ||
| 119 | if (cfg->cpu_win_can_remap(cfg, i)) { | ||
| 120 | writel(0, addr + WIN_REMAP_LO_OFF); | ||
| 121 | writel(0, addr + WIN_REMAP_HI_OFF); | ||
| 122 | } | ||
| 123 | } | ||
| 124 | } | ||
| 125 | |||
| 126 | /* | ||
| 127 | * Disable, clear and configure windows. | ||
| 128 | */ | ||
| 129 | void __init orion_config_wins(struct orion_addr_map_cfg * cfg, | ||
| 130 | const struct orion_addr_map_info *info) | ||
| 131 | { | ||
| 132 | if (!cfg->cpu_win_can_remap) | ||
| 133 | cfg->cpu_win_can_remap = orion_cpu_win_can_remap; | ||
| 134 | |||
| 135 | if (!cfg->win_cfg_base) | ||
| 136 | cfg->win_cfg_base = orion_win_cfg_base; | ||
| 137 | |||
| 138 | orion_disable_wins(cfg); | ||
| 139 | |||
| 140 | if (info) | ||
| 141 | orion_setup_cpu_wins(cfg, info); | ||
| 142 | } | ||
| 143 | |||
| 144 | /* | ||
| 145 | * Setup MBUS dram target info. | ||
| 146 | */ | ||
| 147 | void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, | ||
| 148 | const void __iomem *ddr_window_cpu_base) | ||
| 149 | { | ||
| 150 | int i; | ||
| 151 | int cs; | ||
| 152 | |||
| 153 | orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | ||
| 154 | |||
| 155 | for (i = 0, cs = 0; i < 4; i++) { | ||
| 156 | u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i)); | ||
| 157 | u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i)); | ||
| 158 | |||
| 159 | /* | ||
| 160 | * We only take care of entries for which the chip | ||
| 161 | * select is enabled, and that don't have high base | ||
| 162 | * address bits set (devices can only access the first | ||
| 163 | * 32 bits of the memory). | ||
| 164 | */ | ||
| 165 | if ((size & 1) && !(base & 0xF)) { | ||
| 166 | struct mbus_dram_window *w; | ||
| 167 | |||
| 168 | w = &orion_mbus_dram_info.cs[cs++]; | ||
| 169 | w->cs_index = i; | ||
| 170 | w->mbus_attr = 0xf & ~(1 << i); | ||
| 171 | if (cfg->hw_io_coherency) | ||
| 172 | w->mbus_attr |= ATTR_HW_COHERENCY; | ||
| 173 | w->base = base & 0xffff0000; | ||
| 174 | w->size = (size | 0x0000ffff) + 1; | ||
| 175 | } | ||
| 176 | } | ||
| 177 | orion_mbus_dram_info.num_cs = cs; | ||
| 178 | } | ||
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index c29ee7ea200b..e39c2ba6e2fb 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c | |||
| @@ -439,6 +439,64 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
| 439 | } | 439 | } |
| 440 | } | 440 | } |
| 441 | 441 | ||
| 442 | #ifdef CONFIG_DEBUG_FS | ||
| 443 | #include <linux/seq_file.h> | ||
| 444 | |||
| 445 | static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | ||
| 446 | { | ||
| 447 | struct orion_gpio_chip *ochip = | ||
| 448 | container_of(chip, struct orion_gpio_chip, chip); | ||
| 449 | u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; | ||
| 450 | int i; | ||
| 451 | |||
| 452 | out = readl_relaxed(GPIO_OUT(ochip)); | ||
| 453 | io_conf = readl_relaxed(GPIO_IO_CONF(ochip)); | ||
| 454 | blink = readl_relaxed(GPIO_BLINK_EN(ochip)); | ||
| 455 | in_pol = readl_relaxed(GPIO_IN_POL(ochip)); | ||
| 456 | data_in = readl_relaxed(GPIO_DATA_IN(ochip)); | ||
| 457 | cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip)); | ||
| 458 | edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip)); | ||
| 459 | lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip)); | ||
| 460 | |||
| 461 | for (i = 0; i < chip->ngpio; i++) { | ||
| 462 | const char *label; | ||
| 463 | u32 msk; | ||
| 464 | bool is_out; | ||
| 465 | |||
| 466 | label = gpiochip_is_requested(chip, i); | ||
| 467 | if (!label) | ||
| 468 | continue; | ||
| 469 | |||
| 470 | msk = 1 << i; | ||
| 471 | is_out = !(io_conf & msk); | ||
| 472 | |||
| 473 | seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); | ||
| 474 | |||
| 475 | if (is_out) { | ||
| 476 | seq_printf(s, " out %s %s\n", | ||
| 477 | out & msk ? "hi" : "lo", | ||
| 478 | blink & msk ? "(blink )" : ""); | ||
| 479 | continue; | ||
| 480 | } | ||
| 481 | |||
| 482 | seq_printf(s, " in %s (act %s) - IRQ", | ||
| 483 | (data_in ^ in_pol) & msk ? "hi" : "lo", | ||
| 484 | in_pol & msk ? "lo" : "hi"); | ||
| 485 | if (!((edg_msk | lvl_msk) & msk)) { | ||
| 486 | seq_printf(s, " disabled\n"); | ||
| 487 | continue; | ||
| 488 | } | ||
| 489 | if (edg_msk & msk) | ||
| 490 | seq_printf(s, " edge "); | ||
| 491 | if (lvl_msk & msk) | ||
| 492 | seq_printf(s, " level"); | ||
| 493 | seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); | ||
| 494 | } | ||
| 495 | } | ||
| 496 | #else | ||
| 497 | #define orion_gpio_dbg_show NULL | ||
| 498 | #endif | ||
| 499 | |||
| 442 | void __init orion_gpio_init(struct device_node *np, | 500 | void __init orion_gpio_init(struct device_node *np, |
| 443 | int gpio_base, int ngpio, | 501 | int gpio_base, int ngpio, |
| 444 | void __iomem *base, int mask_offset, | 502 | void __iomem *base, int mask_offset, |
| @@ -471,6 +529,7 @@ void __init orion_gpio_init(struct device_node *np, | |||
| 471 | #ifdef CONFIG_OF | 529 | #ifdef CONFIG_OF |
| 472 | ochip->chip.of_node = np; | 530 | ochip->chip.of_node = np; |
| 473 | #endif | 531 | #endif |
| 532 | ochip->chip.dbg_show = orion_gpio_dbg_show; | ||
| 474 | 533 | ||
| 475 | spin_lock_init(&ochip->lock); | 534 | spin_lock_init(&ochip->lock); |
| 476 | ochip->base = (void __iomem *)base; | 535 | ochip->base = (void __iomem *)base; |
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index f20a321088a2..8b8c06d2e9c4 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c | |||
| @@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base) | |||
| 120 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | 120 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks |
| 121 | * WIN[0-3] -> DRAM bank[0-3] | 121 | * WIN[0-3] -> DRAM bank[0-3] |
| 122 | */ | 122 | */ |
| 123 | static void __init orion_pcie_setup_wins(void __iomem *base, | 123 | static void __init orion_pcie_setup_wins(void __iomem *base) |
| 124 | struct mbus_dram_target_info *dram) | ||
| 125 | { | 124 | { |
| 125 | const struct mbus_dram_target_info *dram; | ||
| 126 | u32 size; | 126 | u32 size; |
| 127 | int i; | 127 | int i; |
| 128 | 128 | ||
| 129 | dram = mv_mbus_dram_info(); | ||
| 130 | |||
| 129 | /* | 131 | /* |
| 130 | * First, disable and clear BARs and windows. | 132 | * First, disable and clear BARs and windows. |
| 131 | */ | 133 | */ |
| @@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, | |||
| 150 | */ | 152 | */ |
| 151 | size = 0; | 153 | size = 0; |
| 152 | for (i = 0; i < dram->num_cs; i++) { | 154 | for (i = 0; i < dram->num_cs; i++) { |
| 153 | struct mbus_dram_window *cs = dram->cs + i; | 155 | const struct mbus_dram_window *cs = dram->cs + i; |
| 154 | 156 | ||
| 155 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); | 157 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); |
| 156 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | 158 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); |
| @@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base) | |||
| 184 | /* | 186 | /* |
| 185 | * Point PCIe unit MBUS decode windows to DRAM space. | 187 | * Point PCIe unit MBUS decode windows to DRAM space. |
| 186 | */ | 188 | */ |
| 187 | orion_pcie_setup_wins(base, &orion_mbus_dram_info); | 189 | orion_pcie_setup_wins(base); |
| 188 | 190 | ||
| 189 | /* | 191 | /* |
| 190 | * Master + slave enable. | 192 | * Master + slave enable. |
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 0f51ed687dc8..b05ecab915c4 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig | |||
| @@ -4,6 +4,13 @@ | |||
| 4 | 4 | ||
| 5 | menu "Bus devices" | 5 | menu "Bus devices" |
| 6 | 6 | ||
| 7 | config MVEBU_MBUS | ||
| 8 | bool | ||
| 9 | depends on PLAT_ORION | ||
| 10 | help | ||
| 11 | Driver needed for the MBus configuration on Marvell EBU SoCs | ||
| 12 | (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP). | ||
| 13 | |||
| 7 | config OMAP_OCP2SCP | 14 | config OMAP_OCP2SCP |
| 8 | tristate "OMAP OCP2SCP DRIVER" | 15 | tristate "OMAP OCP2SCP DRIVER" |
| 9 | depends on ARCH_OMAP2PLUS | 16 | depends on ARCH_OMAP2PLUS |
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 45d997c85453..3c7b53c12091 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | # Makefile for the bus drivers. | 2 | # Makefile for the bus drivers. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o | ||
| 5 | obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o | 6 | obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o |
| 6 | 7 | ||
| 7 | # Interconnect bus driver for OMAP SoCs. | 8 | # Interconnect bus driver for OMAP SoCs. |
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c new file mode 100644 index 000000000000..8740f46b4d0d --- /dev/null +++ b/drivers/bus/mvebu-mbus.c | |||
| @@ -0,0 +1,870 @@ | |||
| 1 | /* | ||
| 2 | * Address map functions for Marvell EBU SoCs (Kirkwood, Armada | ||
| 3 | * 370/XP, Dove, Orion5x and MV78xx0) | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | * | ||
| 9 | * The Marvell EBU SoCs have a configurable physical address space: | ||
| 10 | * the physical address at which certain devices (PCIe, NOR, NAND, | ||
| 11 | * etc.) sit can be configured. The configuration takes place through | ||
| 12 | * two sets of registers: | ||
| 13 | * | ||
| 14 | * - One to configure the access of the CPU to the devices. Depending | ||
| 15 | * on the families, there are between 8 and 20 configurable windows, | ||
| 16 | * each can be use to create a physical memory window that maps to a | ||
| 17 | * specific device. Devices are identified by a tuple (target, | ||
| 18 | * attribute). | ||
| 19 | * | ||
| 20 | * - One to configure the access to the CPU to the SDRAM. There are | ||
| 21 | * either 2 (for Dove) or 4 (for other families) windows to map the | ||
| 22 | * SDRAM into the physical address space. | ||
| 23 | * | ||
| 24 | * This driver: | ||
| 25 | * | ||
| 26 | * - Reads out the SDRAM address decoding windows at initialization | ||
| 27 | * time, and fills the mvebu_mbus_dram_info structure with these | ||
| 28 | * informations. The exported function mv_mbus_dram_info() allow | ||
| 29 | * device drivers to get those informations related to the SDRAM | ||
| 30 | * address decoding windows. This is because devices also have their | ||
| 31 | * own windows (configured through registers that are part of each | ||
| 32 | * device register space), and therefore the drivers for Marvell | ||
| 33 | * devices have to configure those device -> SDRAM windows to ensure | ||
| 34 | * that DMA works properly. | ||
| 35 | * | ||
| 36 | * - Provides an API for platform code or device drivers to | ||
| 37 | * dynamically add or remove address decoding windows for the CPU -> | ||
| 38 | * device accesses. This API is mvebu_mbus_add_window(), | ||
| 39 | * mvebu_mbus_add_window_remap_flags() and | ||
| 40 | * mvebu_mbus_del_window(). Since the (target, attribute) values | ||
| 41 | * differ from one SoC family to another, the API uses a 'const char | ||
| 42 | * *' string to identify devices, and this driver is responsible for | ||
| 43 | * knowing the mapping between the name of a device and its | ||
| 44 | * corresponding (target, attribute) in the current SoC family. | ||
| 45 | * | ||
| 46 | * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to | ||
| 47 | * see the list of CPU -> SDRAM windows and their configuration | ||
| 48 | * (file 'sdram') and the list of CPU -> devices windows and their | ||
| 49 | * configuration (file 'devices'). | ||
| 50 | */ | ||
| 51 | |||
| 52 | #include <linux/kernel.h> | ||
| 53 | #include <linux/module.h> | ||
| 54 | #include <linux/init.h> | ||
| 55 | #include <linux/mbus.h> | ||
| 56 | #include <linux/io.h> | ||
| 57 | #include <linux/ioport.h> | ||
| 58 | #include <linux/of.h> | ||
| 59 | #include <linux/of_address.h> | ||
| 60 | #include <linux/debugfs.h> | ||
| 61 | |||
| 62 | /* | ||
| 63 | * DDR target is the same on all platforms. | ||
| 64 | */ | ||
| 65 | #define TARGET_DDR 0 | ||
| 66 | |||
| 67 | /* | ||
| 68 | * CPU Address Decode Windows registers | ||
| 69 | */ | ||
| 70 | #define WIN_CTRL_OFF 0x0000 | ||
| 71 | #define WIN_CTRL_ENABLE BIT(0) | ||
| 72 | #define WIN_CTRL_TGT_MASK 0xf0 | ||
| 73 | #define WIN_CTRL_TGT_SHIFT 4 | ||
| 74 | #define WIN_CTRL_ATTR_MASK 0xff00 | ||
| 75 | #define WIN_CTRL_ATTR_SHIFT 8 | ||
| 76 | #define WIN_CTRL_SIZE_MASK 0xffff0000 | ||
| 77 | #define WIN_CTRL_SIZE_SHIFT 16 | ||
| 78 | #define WIN_BASE_OFF 0x0004 | ||
| 79 | #define WIN_BASE_LOW 0xffff0000 | ||
| 80 | #define WIN_BASE_HIGH 0xf | ||
| 81 | #define WIN_REMAP_LO_OFF 0x0008 | ||
| 82 | #define WIN_REMAP_LOW 0xffff0000 | ||
| 83 | #define WIN_REMAP_HI_OFF 0x000c | ||
| 84 | |||
| 85 | #define ATTR_HW_COHERENCY (0x1 << 4) | ||
| 86 | |||
| 87 | #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) | ||
| 88 | #define DDR_BASE_CS_HIGH_MASK 0xf | ||
| 89 | #define DDR_BASE_CS_LOW_MASK 0xff000000 | ||
| 90 | #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) | ||
| 91 | #define DDR_SIZE_ENABLED BIT(0) | ||
| 92 | #define DDR_SIZE_CS_MASK 0x1c | ||
| 93 | #define DDR_SIZE_CS_SHIFT 2 | ||
| 94 | #define DDR_SIZE_MASK 0xff000000 | ||
| 95 | |||
| 96 | #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4) | ||
| 97 | |||
| 98 | struct mvebu_mbus_mapping { | ||
| 99 | const char *name; | ||
| 100 | u8 target; | ||
| 101 | u8 attr; | ||
| 102 | u8 attrmask; | ||
| 103 | }; | ||
| 104 | |||
| 105 | /* | ||
| 106 | * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They | ||
| 107 | * allow to get the real attribute value, discarding the special bits | ||
| 108 | * used to select a PCI MEM region or a PCI WA region. This allows the | ||
| 109 | * debugfs code to reverse-match the name of a device from its | ||
| 110 | * target/attr values. | ||
| 111 | * | ||
| 112 | * For all devices except PCI, all bits of 'attr' must be | ||
| 113 | * considered. For most SoCs, only bit 3 should be ignored (it allows | ||
| 114 | * to select between PCI MEM and PCI I/O). On Orion5x however, there | ||
| 115 | * is the special bit 5 to select a PCI WA region. | ||
| 116 | */ | ||
| 117 | #define MAPDEF_NOMASK 0xff | ||
| 118 | #define MAPDEF_PCIMASK 0xf7 | ||
| 119 | #define MAPDEF_ORIONPCIMASK 0xd7 | ||
| 120 | |||
| 121 | /* Macro used to define one mvebu_mbus_mapping entry */ | ||
| 122 | #define MAPDEF(__n, __t, __a, __m) \ | ||
| 123 | { .name = __n, .target = __t, .attr = __a, .attrmask = __m } | ||
| 124 | |||
| 125 | struct mvebu_mbus_state; | ||
| 126 | |||
| 127 | struct mvebu_mbus_soc_data { | ||
| 128 | unsigned int num_wins; | ||
| 129 | unsigned int num_remappable_wins; | ||
| 130 | unsigned int (*win_cfg_offset)(const int win); | ||
| 131 | void (*setup_cpu_target)(struct mvebu_mbus_state *s); | ||
| 132 | int (*show_cpu_target)(struct mvebu_mbus_state *s, | ||
| 133 | struct seq_file *seq, void *v); | ||
| 134 | const struct mvebu_mbus_mapping *map; | ||
| 135 | }; | ||
| 136 | |||
| 137 | struct mvebu_mbus_state { | ||
| 138 | void __iomem *mbuswins_base; | ||
| 139 | void __iomem *sdramwins_base; | ||
| 140 | struct dentry *debugfs_root; | ||
| 141 | struct dentry *debugfs_sdram; | ||
| 142 | struct dentry *debugfs_devs; | ||
| 143 | const struct mvebu_mbus_soc_data *soc; | ||
| 144 | int hw_io_coherency; | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct mvebu_mbus_state mbus_state; | ||
| 148 | |||
| 149 | static struct mbus_dram_target_info mvebu_mbus_dram_info; | ||
| 150 | const struct mbus_dram_target_info *mv_mbus_dram_info(void) | ||
| 151 | { | ||
| 152 | return &mvebu_mbus_dram_info; | ||
| 153 | } | ||
| 154 | EXPORT_SYMBOL_GPL(mv_mbus_dram_info); | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Functions to manipulate the address decoding windows | ||
| 158 | */ | ||
| 159 | |||
| 160 | static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus, | ||
| 161 | int win, int *enabled, u64 *base, | ||
| 162 | u32 *size, u8 *target, u8 *attr, | ||
| 163 | u64 *remap) | ||
| 164 | { | ||
| 165 | void __iomem *addr = mbus->mbuswins_base + | ||
| 166 | mbus->soc->win_cfg_offset(win); | ||
| 167 | u32 basereg = readl(addr + WIN_BASE_OFF); | ||
| 168 | u32 ctrlreg = readl(addr + WIN_CTRL_OFF); | ||
| 169 | |||
| 170 | if (!(ctrlreg & WIN_CTRL_ENABLE)) { | ||
| 171 | *enabled = 0; | ||
| 172 | return; | ||
| 173 | } | ||
| 174 | |||
| 175 | *enabled = 1; | ||
| 176 | *base = ((u64)basereg & WIN_BASE_HIGH) << 32; | ||
| 177 | *base |= (basereg & WIN_BASE_LOW); | ||
| 178 | *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1; | ||
| 179 | |||
| 180 | if (target) | ||
| 181 | *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT; | ||
| 182 | |||
| 183 | if (attr) | ||
| 184 | *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT; | ||
| 185 | |||
| 186 | if (remap) { | ||
| 187 | if (win < mbus->soc->num_remappable_wins) { | ||
| 188 | u32 remap_low = readl(addr + WIN_REMAP_LO_OFF); | ||
| 189 | u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF); | ||
| 190 | *remap = ((u64)remap_hi << 32) | remap_low; | ||
| 191 | } else | ||
| 192 | *remap = 0; | ||
| 193 | } | ||
| 194 | } | ||
| 195 | |||
| 196 | static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus, | ||
| 197 | int win) | ||
| 198 | { | ||
| 199 | void __iomem *addr; | ||
| 200 | |||
| 201 | addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); | ||
| 202 | |||
| 203 | writel(0, addr + WIN_BASE_OFF); | ||
| 204 | writel(0, addr + WIN_CTRL_OFF); | ||
| 205 | if (win < mbus->soc->num_remappable_wins) { | ||
| 206 | writel(0, addr + WIN_REMAP_LO_OFF); | ||
| 207 | writel(0, addr + WIN_REMAP_HI_OFF); | ||
| 208 | } | ||
| 209 | } | ||
| 210 | |||
| 211 | /* Checks whether the given window number is available */ | ||
| 212 | static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus, | ||
| 213 | const int win) | ||
| 214 | { | ||
| 215 | void __iomem *addr = mbus->mbuswins_base + | ||
| 216 | mbus->soc->win_cfg_offset(win); | ||
| 217 | u32 ctrl = readl(addr + WIN_CTRL_OFF); | ||
| 218 | return !(ctrl & WIN_CTRL_ENABLE); | ||
| 219 | } | ||
| 220 | |||
| 221 | /* | ||
| 222 | * Checks whether the given (base, base+size) area doesn't overlap an | ||
| 223 | * existing region | ||
| 224 | */ | ||
| 225 | static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, | ||
| 226 | phys_addr_t base, size_t size, | ||
| 227 | u8 target, u8 attr) | ||
| 228 | { | ||
| 229 | u64 end = (u64)base + size; | ||
| 230 | int win; | ||
| 231 | |||
| 232 | for (win = 0; win < mbus->soc->num_wins; win++) { | ||
| 233 | u64 wbase, wend; | ||
| 234 | u32 wsize; | ||
| 235 | u8 wtarget, wattr; | ||
| 236 | int enabled; | ||
| 237 | |||
| 238 | mvebu_mbus_read_window(mbus, win, | ||
| 239 | &enabled, &wbase, &wsize, | ||
| 240 | &wtarget, &wattr, NULL); | ||
| 241 | |||
| 242 | if (!enabled) | ||
| 243 | continue; | ||
| 244 | |||
| 245 | wend = wbase + wsize; | ||
| 246 | |||
| 247 | /* | ||
| 248 | * Check if the current window overlaps with the | ||
| 249 | * proposed physical range | ||
| 250 | */ | ||
| 251 | if ((u64)base < wend && end > wbase) | ||
| 252 | return 0; | ||
| 253 | |||
| 254 | /* | ||
| 255 | * Check if target/attribute conflicts | ||
| 256 | */ | ||
| 257 | if (target == wtarget && attr == wattr) | ||
| 258 | return 0; | ||
| 259 | } | ||
| 260 | |||
| 261 | return 1; | ||
| 262 | } | ||
| 263 | |||
| 264 | static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus, | ||
| 265 | phys_addr_t base, size_t size) | ||
| 266 | { | ||
| 267 | int win; | ||
| 268 | |||
| 269 | for (win = 0; win < mbus->soc->num_wins; win++) { | ||
| 270 | u64 wbase; | ||
| 271 | u32 wsize; | ||
| 272 | int enabled; | ||
| 273 | |||
| 274 | mvebu_mbus_read_window(mbus, win, | ||
| 275 | &enabled, &wbase, &wsize, | ||
| 276 | NULL, NULL, NULL); | ||
| 277 | |||
| 278 | if (!enabled) | ||
| 279 | continue; | ||
| 280 | |||
| 281 | if (base == wbase && size == wsize) | ||
| 282 | return win; | ||
| 283 | } | ||
| 284 | |||
| 285 | return -ENODEV; | ||
| 286 | } | ||
| 287 | |||
| 288 | static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, | ||
| 289 | int win, phys_addr_t base, size_t size, | ||
| 290 | phys_addr_t remap, u8 target, | ||
| 291 | u8 attr) | ||
| 292 | { | ||
| 293 | void __iomem *addr = mbus->mbuswins_base + | ||
| 294 | mbus->soc->win_cfg_offset(win); | ||
| 295 | u32 ctrl, remap_addr; | ||
| 296 | |||
| 297 | ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | | ||
| 298 | (attr << WIN_CTRL_ATTR_SHIFT) | | ||
| 299 | (target << WIN_CTRL_TGT_SHIFT) | | ||
| 300 | WIN_CTRL_ENABLE; | ||
| 301 | |||
| 302 | writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF); | ||
| 303 | writel(ctrl, addr + WIN_CTRL_OFF); | ||
| 304 | if (win < mbus->soc->num_remappable_wins) { | ||
| 305 | if (remap == MVEBU_MBUS_NO_REMAP) | ||
| 306 | remap_addr = base; | ||
| 307 | else | ||
| 308 | remap_addr = remap; | ||
| 309 | writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF); | ||
| 310 | writel(0, addr + WIN_REMAP_HI_OFF); | ||
| 311 | } | ||
| 312 | |||
| 313 | return 0; | ||
| 314 | } | ||
| 315 | |||
| 316 | static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus, | ||
| 317 | phys_addr_t base, size_t size, | ||
| 318 | phys_addr_t remap, u8 target, | ||
| 319 | u8 attr) | ||
| 320 | { | ||
| 321 | int win; | ||
| 322 | |||
| 323 | if (remap == MVEBU_MBUS_NO_REMAP) { | ||
| 324 | for (win = mbus->soc->num_remappable_wins; | ||
| 325 | win < mbus->soc->num_wins; win++) | ||
| 326 | if (mvebu_mbus_window_is_free(mbus, win)) | ||
| 327 | return mvebu_mbus_setup_window(mbus, win, base, | ||
| 328 | size, remap, | ||
| 329 | target, attr); | ||
| 330 | } | ||
| 331 | |||
| 332 | |||
| 333 | for (win = 0; win < mbus->soc->num_wins; win++) | ||
| 334 | if (mvebu_mbus_window_is_free(mbus, win)) | ||
| 335 | return mvebu_mbus_setup_window(mbus, win, base, size, | ||
| 336 | remap, target, attr); | ||
| 337 | |||
| 338 | return -ENOMEM; | ||
| 339 | } | ||
| 340 | |||
| 341 | /* | ||
| 342 | * Debugfs debugging | ||
| 343 | */ | ||
| 344 | |||
| 345 | /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */ | ||
| 346 | static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus, | ||
| 347 | struct seq_file *seq, void *v) | ||
| 348 | { | ||
| 349 | int i; | ||
| 350 | |||
| 351 | for (i = 0; i < 4; i++) { | ||
| 352 | u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); | ||
| 353 | u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); | ||
| 354 | u64 base; | ||
| 355 | u32 size; | ||
| 356 | |||
| 357 | if (!(sizereg & DDR_SIZE_ENABLED)) { | ||
| 358 | seq_printf(seq, "[%d] disabled\n", i); | ||
| 359 | continue; | ||
| 360 | } | ||
| 361 | |||
| 362 | base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32; | ||
| 363 | base |= basereg & DDR_BASE_CS_LOW_MASK; | ||
| 364 | size = (sizereg | ~DDR_SIZE_MASK); | ||
| 365 | |||
| 366 | seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n", | ||
| 367 | i, (unsigned long long)base, | ||
| 368 | (unsigned long long)base + size + 1, | ||
| 369 | (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT); | ||
| 370 | } | ||
| 371 | |||
| 372 | return 0; | ||
| 373 | } | ||
| 374 | |||
| 375 | /* Special function for Dove */ | ||
| 376 | static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus, | ||
| 377 | struct seq_file *seq, void *v) | ||
| 378 | { | ||
| 379 | int i; | ||
| 380 | |||
| 381 | for (i = 0; i < 2; i++) { | ||
| 382 | u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); | ||
| 383 | u64 base; | ||
| 384 | u32 size; | ||
| 385 | |||
| 386 | if (!(map & 1)) { | ||
| 387 | seq_printf(seq, "[%d] disabled\n", i); | ||
| 388 | continue; | ||
| 389 | } | ||
| 390 | |||
| 391 | base = map & 0xff800000; | ||
| 392 | size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); | ||
| 393 | |||
| 394 | seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n", | ||
| 395 | i, (unsigned long long)base, | ||
| 396 | (unsigned long long)base + size, i); | ||
| 397 | } | ||
| 398 | |||
| 399 | return 0; | ||
| 400 | } | ||
| 401 | |||
| 402 | static int mvebu_sdram_debug_show(struct seq_file *seq, void *v) | ||
| 403 | { | ||
| 404 | struct mvebu_mbus_state *mbus = &mbus_state; | ||
| 405 | return mbus->soc->show_cpu_target(mbus, seq, v); | ||
| 406 | } | ||
| 407 | |||
| 408 | static int mvebu_sdram_debug_open(struct inode *inode, struct file *file) | ||
| 409 | { | ||
| 410 | return single_open(file, mvebu_sdram_debug_show, inode->i_private); | ||
| 411 | } | ||
| 412 | |||
| 413 | static const struct file_operations mvebu_sdram_debug_fops = { | ||
| 414 | .open = mvebu_sdram_debug_open, | ||
| 415 | .read = seq_read, | ||
| 416 | .llseek = seq_lseek, | ||
| 417 | .release = single_release, | ||
| 418 | }; | ||
| 419 | |||
| 420 | static int mvebu_devs_debug_show(struct seq_file *seq, void *v) | ||
| 421 | { | ||
| 422 | struct mvebu_mbus_state *mbus = &mbus_state; | ||
| 423 | int win; | ||
| 424 | |||
| 425 | for (win = 0; win < mbus->soc->num_wins; win++) { | ||
| 426 | u64 wbase, wremap; | ||
| 427 | u32 wsize; | ||
| 428 | u8 wtarget, wattr; | ||
| 429 | int enabled, i; | ||
| 430 | const char *name; | ||
| 431 | |||
| 432 | mvebu_mbus_read_window(mbus, win, | ||
| 433 | &enabled, &wbase, &wsize, | ||
| 434 | &wtarget, &wattr, &wremap); | ||
| 435 | |||
| 436 | if (!enabled) { | ||
| 437 | seq_printf(seq, "[%02d] disabled\n", win); | ||
| 438 | continue; | ||
| 439 | } | ||
| 440 | |||
| 441 | |||
| 442 | for (i = 0; mbus->soc->map[i].name; i++) | ||
| 443 | if (mbus->soc->map[i].target == wtarget && | ||
| 444 | mbus->soc->map[i].attr == | ||
| 445 | (wattr & mbus->soc->map[i].attrmask)) | ||
| 446 | break; | ||
| 447 | |||
| 448 | name = mbus->soc->map[i].name ?: "unknown"; | ||
| 449 | |||
| 450 | seq_printf(seq, "[%02d] %016llx - %016llx : %s", | ||
| 451 | win, (unsigned long long)wbase, | ||
| 452 | (unsigned long long)(wbase + wsize), name); | ||
| 453 | |||
| 454 | if (win < mbus->soc->num_remappable_wins) { | ||
| 455 | seq_printf(seq, " (remap %016llx)\n", | ||
| 456 | (unsigned long long)wremap); | ||
| 457 | } else | ||
| 458 | seq_printf(seq, "\n"); | ||
| 459 | } | ||
| 460 | |||
| 461 | return 0; | ||
| 462 | } | ||
| 463 | |||
| 464 | static int mvebu_devs_debug_open(struct inode *inode, struct file *file) | ||
| 465 | { | ||
| 466 | return single_open(file, mvebu_devs_debug_show, inode->i_private); | ||
| 467 | } | ||
| 468 | |||
| 469 | static const struct file_operations mvebu_devs_debug_fops = { | ||
| 470 | .open = mvebu_devs_debug_open, | ||
| 471 | .read = seq_read, | ||
| 472 | .llseek = seq_lseek, | ||
| 473 | .release = single_release, | ||
| 474 | }; | ||
| 475 | |||
| 476 | /* | ||
| 477 | * SoC-specific functions and definitions | ||
| 478 | */ | ||
| 479 | |||
| 480 | static unsigned int orion_mbus_win_offset(int win) | ||
| 481 | { | ||
| 482 | return win << 4; | ||
| 483 | } | ||
| 484 | |||
| 485 | static unsigned int armada_370_xp_mbus_win_offset(int win) | ||
| 486 | { | ||
| 487 | /* The register layout is a bit annoying and the below code | ||
| 488 | * tries to cope with it. | ||
| 489 | * - At offset 0x0, there are the registers for the first 8 | ||
| 490 | * windows, with 4 registers of 32 bits per window (ctrl, | ||
| 491 | * base, remap low, remap high) | ||
| 492 | * - Then at offset 0x80, there is a hole of 0x10 bytes for | ||
| 493 | * the internal registers base address and internal units | ||
| 494 | * sync barrier register. | ||
| 495 | * - Then at offset 0x90, there the registers for 12 | ||
| 496 | * windows, with only 2 registers of 32 bits per window | ||
| 497 | * (ctrl, base). | ||
| 498 | */ | ||
| 499 | if (win < 8) | ||
| 500 | return win << 4; | ||
| 501 | else | ||
| 502 | return 0x90 + ((win - 8) << 3); | ||
| 503 | } | ||
| 504 | |||
| 505 | static unsigned int mv78xx0_mbus_win_offset(int win) | ||
| 506 | { | ||
| 507 | if (win < 8) | ||
| 508 | return win << 4; | ||
| 509 | else | ||
| 510 | return 0x900 + ((win - 8) << 4); | ||
| 511 | } | ||
| 512 | |||
| 513 | static void __init | ||
| 514 | mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) | ||
| 515 | { | ||
| 516 | int i; | ||
| 517 | int cs; | ||
| 518 | |||
| 519 | mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | ||
| 520 | |||
| 521 | for (i = 0, cs = 0; i < 4; i++) { | ||
| 522 | u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); | ||
| 523 | u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); | ||
| 524 | |||
| 525 | /* | ||
| 526 | * We only take care of entries for which the chip | ||
| 527 | * select is enabled, and that don't have high base | ||
| 528 | * address bits set (devices can only access the first | ||
| 529 | * 32 bits of the memory). | ||
| 530 | */ | ||
| 531 | if ((size & DDR_SIZE_ENABLED) && | ||
| 532 | !(base & DDR_BASE_CS_HIGH_MASK)) { | ||
| 533 | struct mbus_dram_window *w; | ||
| 534 | |||
| 535 | w = &mvebu_mbus_dram_info.cs[cs++]; | ||
| 536 | w->cs_index = i; | ||
| 537 | w->mbus_attr = 0xf & ~(1 << i); | ||
| 538 | if (mbus->hw_io_coherency) | ||
| 539 | w->mbus_attr |= ATTR_HW_COHERENCY; | ||
| 540 | w->base = base & DDR_BASE_CS_LOW_MASK; | ||
| 541 | w->size = (size | ~DDR_SIZE_MASK) + 1; | ||
| 542 | } | ||
| 543 | } | ||
| 544 | mvebu_mbus_dram_info.num_cs = cs; | ||
| 545 | } | ||
| 546 | |||
| 547 | static void __init | ||
| 548 | mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus) | ||
| 549 | { | ||
| 550 | int i; | ||
| 551 | int cs; | ||
| 552 | |||
| 553 | mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | ||
| 554 | |||
| 555 | for (i = 0, cs = 0; i < 2; i++) { | ||
| 556 | u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); | ||
| 557 | |||
| 558 | /* | ||
| 559 | * Chip select enabled? | ||
| 560 | */ | ||
| 561 | if (map & 1) { | ||
| 562 | struct mbus_dram_window *w; | ||
| 563 | |||
| 564 | w = &mvebu_mbus_dram_info.cs[cs++]; | ||
| 565 | w->cs_index = i; | ||
| 566 | w->mbus_attr = 0; /* CS address decoding done inside */ | ||
| 567 | /* the DDR controller, no need to */ | ||
| 568 | /* provide attributes */ | ||
| 569 | w->base = map & 0xff800000; | ||
| 570 | w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); | ||
| 571 | } | ||
| 572 | } | ||
| 573 | |||
| 574 | mvebu_mbus_dram_info.num_cs = cs; | ||
| 575 | } | ||
| 576 | |||
| 577 | static const struct mvebu_mbus_mapping armada_370_map[] = { | ||
| 578 | MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK), | ||
| 579 | MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK), | ||
| 580 | MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK), | ||
| 581 | MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK), | ||
| 582 | MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK), | ||
| 583 | MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK), | ||
| 584 | MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK), | ||
| 585 | MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK), | ||
| 586 | {}, | ||
| 587 | }; | ||
| 588 | |||
| 589 | static const struct mvebu_mbus_soc_data armada_370_mbus_data = { | ||
| 590 | .num_wins = 20, | ||
| 591 | .num_remappable_wins = 8, | ||
| 592 | .win_cfg_offset = armada_370_xp_mbus_win_offset, | ||
| 593 | .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, | ||
| 594 | .show_cpu_target = mvebu_sdram_debug_show_orion, | ||
| 595 | .map = armada_370_map, | ||
| 596 | }; | ||
| 597 | |||
| 598 | static const struct mvebu_mbus_mapping armada_xp_map[] = { | ||
| 599 | MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK), | ||
| 600 | MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK), | ||
| 601 | MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK), | ||
| 602 | MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK), | ||
| 603 | MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK), | ||
| 604 | MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK), | ||
| 605 | MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK), | ||
| 606 | MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK), | ||
| 607 | MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK), | ||
| 608 | MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK), | ||
| 609 | MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK), | ||
| 610 | MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK), | ||
| 611 | MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK), | ||
| 612 | MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK), | ||
| 613 | MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK), | ||
| 614 | MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK), | ||
| 615 | {}, | ||
| 616 | }; | ||
| 617 | |||
| 618 | static const struct mvebu_mbus_soc_data armada_xp_mbus_data = { | ||
| 619 | .num_wins = 20, | ||
| 620 | .num_remappable_wins = 8, | ||
| 621 | .win_cfg_offset = armada_370_xp_mbus_win_offset, | ||
| 622 | .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, | ||
| 623 | .show_cpu_target = mvebu_sdram_debug_show_orion, | ||
| 624 | .map = armada_xp_map, | ||
| 625 | }; | ||
| 626 | |||
| 627 | static const struct mvebu_mbus_mapping kirkwood_map[] = { | ||
| 628 | MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK), | ||
| 629 | MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK), | ||
| 630 | MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK), | ||
| 631 | MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK), | ||
| 632 | {}, | ||
| 633 | }; | ||
| 634 | |||
| 635 | static const struct mvebu_mbus_soc_data kirkwood_mbus_data = { | ||
| 636 | .num_wins = 8, | ||
| 637 | .num_remappable_wins = 4, | ||
| 638 | .win_cfg_offset = orion_mbus_win_offset, | ||
| 639 | .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, | ||
| 640 | .show_cpu_target = mvebu_sdram_debug_show_orion, | ||
| 641 | .map = kirkwood_map, | ||
| 642 | }; | ||
| 643 | |||
| 644 | static const struct mvebu_mbus_mapping dove_map[] = { | ||
| 645 | MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK), | ||
| 646 | MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK), | ||
| 647 | MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK), | ||
| 648 | MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK), | ||
| 649 | MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK), | ||
| 650 | {}, | ||
| 651 | }; | ||
| 652 | |||
| 653 | static const struct mvebu_mbus_soc_data dove_mbus_data = { | ||
| 654 | .num_wins = 8, | ||
| 655 | .num_remappable_wins = 4, | ||
| 656 | .win_cfg_offset = orion_mbus_win_offset, | ||
| 657 | .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target, | ||
| 658 | .show_cpu_target = mvebu_sdram_debug_show_dove, | ||
| 659 | .map = dove_map, | ||
| 660 | }; | ||
| 661 | |||
| 662 | static const struct mvebu_mbus_mapping orion5x_map[] = { | ||
| 663 | MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK), | ||
| 664 | MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK), | ||
| 665 | MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK), | ||
| 666 | MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK), | ||
| 667 | MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK), | ||
| 668 | MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK), | ||
| 669 | MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK), | ||
| 670 | {}, | ||
| 671 | }; | ||
| 672 | |||
| 673 | /* | ||
| 674 | * Some variants of Orion5x have 4 remappable windows, some other have | ||
| 675 | * only two of them. | ||
| 676 | */ | ||
| 677 | static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = { | ||
| 678 | .num_wins = 8, | ||
| 679 | .num_remappable_wins = 4, | ||
| 680 | .win_cfg_offset = orion_mbus_win_offset, | ||
| 681 | .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, | ||
| 682 | .show_cpu_target = mvebu_sdram_debug_show_orion, | ||
| 683 | .map = orion5x_map, | ||
| 684 | }; | ||
| 685 | |||
| 686 | static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = { | ||
| 687 | .num_wins = 8, | ||
| 688 | .num_remappable_wins = 2, | ||
| 689 | .win_cfg_offset = orion_mbus_win_offset, | ||
| 690 | .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, | ||
| 691 | .show_cpu_target = mvebu_sdram_debug_show_orion, | ||
| 692 | .map = orion5x_map, | ||
| 693 | }; | ||
| 694 | |||
| 695 | static const struct mvebu_mbus_mapping mv78xx0_map[] = { | ||
| 696 | MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK), | ||
| 697 | MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK), | ||
| 698 | MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK), | ||
| 699 | MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK), | ||
| 700 | MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK), | ||
| 701 | MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK), | ||
| 702 | MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK), | ||
| 703 | MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK), | ||
| 704 | MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK), | ||
| 705 | MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK), | ||
| 706 | {}, | ||
| 707 | }; | ||
| 708 | |||
| 709 | static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = { | ||
| 710 | .num_wins = 14, | ||
| 711 | .num_remappable_wins = 8, | ||
| 712 | .win_cfg_offset = mv78xx0_mbus_win_offset, | ||
| 713 | .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, | ||
| 714 | .show_cpu_target = mvebu_sdram_debug_show_orion, | ||
| 715 | .map = mv78xx0_map, | ||
| 716 | }; | ||
| 717 | |||
| 718 | /* | ||
| 719 | * The driver doesn't yet have a DT binding because the details of | ||
| 720 | * this DT binding still need to be sorted out. However, as a | ||
| 721 | * preparation, we already use of_device_id to match a SoC description | ||
| 722 | * string against the SoC specific details of this driver. | ||
| 723 | */ | ||
| 724 | static const struct of_device_id of_mvebu_mbus_ids[] = { | ||
| 725 | { .compatible = "marvell,armada370-mbus", | ||
| 726 | .data = &armada_370_mbus_data, }, | ||
| 727 | { .compatible = "marvell,armadaxp-mbus", | ||
| 728 | .data = &armada_xp_mbus_data, }, | ||
| 729 | { .compatible = "marvell,kirkwood-mbus", | ||
| 730 | .data = &kirkwood_mbus_data, }, | ||
| 731 | { .compatible = "marvell,dove-mbus", | ||
| 732 | .data = &dove_mbus_data, }, | ||
| 733 | { .compatible = "marvell,orion5x-88f5281-mbus", | ||
| 734 | .data = &orion5x_4win_mbus_data, }, | ||
| 735 | { .compatible = "marvell,orion5x-88f5182-mbus", | ||
| 736 | .data = &orion5x_2win_mbus_data, }, | ||
| 737 | { .compatible = "marvell,orion5x-88f5181-mbus", | ||
| 738 | .data = &orion5x_2win_mbus_data, }, | ||
| 739 | { .compatible = "marvell,orion5x-88f6183-mbus", | ||
| 740 | .data = &orion5x_4win_mbus_data, }, | ||
| 741 | { .compatible = "marvell,mv78xx0-mbus", | ||
| 742 | .data = &mv78xx0_mbus_data, }, | ||
| 743 | { }, | ||
| 744 | }; | ||
| 745 | |||
| 746 | /* | ||
| 747 | * Public API of the driver | ||
| 748 | */ | ||
| 749 | int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base, | ||
| 750 | size_t size, phys_addr_t remap, | ||
| 751 | unsigned int flags) | ||
| 752 | { | ||
| 753 | struct mvebu_mbus_state *s = &mbus_state; | ||
| 754 | u8 target, attr; | ||
| 755 | int i; | ||
| 756 | |||
| 757 | if (!s->soc->map) | ||
| 758 | return -ENODEV; | ||
| 759 | |||
| 760 | for (i = 0; s->soc->map[i].name; i++) | ||
| 761 | if (!strcmp(s->soc->map[i].name, devname)) | ||
| 762 | break; | ||
| 763 | |||
| 764 | if (!s->soc->map[i].name) { | ||
| 765 | pr_err("mvebu-mbus: unknown device '%s'\n", devname); | ||
| 766 | return -ENODEV; | ||
| 767 | } | ||
| 768 | |||
| 769 | target = s->soc->map[i].target; | ||
| 770 | attr = s->soc->map[i].attr; | ||
| 771 | |||
| 772 | if (flags == MVEBU_MBUS_PCI_MEM) | ||
| 773 | attr |= 0x8; | ||
| 774 | else if (flags == MVEBU_MBUS_PCI_WA) | ||
| 775 | attr |= 0x28; | ||
| 776 | |||
| 777 | if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) { | ||
| 778 | pr_err("mvebu-mbus: cannot add window '%s', conflicts with another window\n", | ||
| 779 | devname); | ||
| 780 | return -EINVAL; | ||
| 781 | } | ||
| 782 | |||
| 783 | return mvebu_mbus_alloc_window(s, base, size, remap, target, attr); | ||
| 784 | |||
| 785 | } | ||
| 786 | |||
| 787 | int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size) | ||
| 788 | { | ||
| 789 | return mvebu_mbus_add_window_remap_flags(devname, base, size, | ||
| 790 | MVEBU_MBUS_NO_REMAP, 0); | ||
| 791 | } | ||
| 792 | |||
| 793 | int mvebu_mbus_del_window(phys_addr_t base, size_t size) | ||
| 794 | { | ||
| 795 | int win; | ||
| 796 | |||
| 797 | win = mvebu_mbus_find_window(&mbus_state, base, size); | ||
| 798 | if (win < 0) | ||
| 799 | return win; | ||
| 800 | |||
| 801 | mvebu_mbus_disable_window(&mbus_state, win); | ||
| 802 | return 0; | ||
| 803 | } | ||
| 804 | |||
| 805 | static __init int mvebu_mbus_debugfs_init(void) | ||
| 806 | { | ||
| 807 | struct mvebu_mbus_state *s = &mbus_state; | ||
| 808 | |||
| 809 | /* | ||
| 810 | * If no base has been initialized, doesn't make sense to | ||
| 811 | * register the debugfs entries. We may be on a multiplatform | ||
| 812 | * kernel that isn't running a Marvell EBU SoC. | ||
| 813 | */ | ||
| 814 | if (!s->mbuswins_base) | ||
| 815 | return 0; | ||
| 816 | |||
| 817 | s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL); | ||
| 818 | if (s->debugfs_root) { | ||
| 819 | s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO, | ||
| 820 | s->debugfs_root, NULL, | ||
| 821 | &mvebu_sdram_debug_fops); | ||
| 822 | s->debugfs_devs = debugfs_create_file("devices", S_IRUGO, | ||
| 823 | s->debugfs_root, NULL, | ||
| 824 | &mvebu_devs_debug_fops); | ||
| 825 | } | ||
| 826 | |||
| 827 | return 0; | ||
| 828 | } | ||
| 829 | fs_initcall(mvebu_mbus_debugfs_init); | ||
| 830 | |||
| 831 | int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base, | ||
| 832 | size_t mbuswins_size, | ||
| 833 | phys_addr_t sdramwins_phys_base, | ||
| 834 | size_t sdramwins_size) | ||
| 835 | { | ||
| 836 | struct mvebu_mbus_state *mbus = &mbus_state; | ||
| 837 | const struct of_device_id *of_id; | ||
| 838 | int win; | ||
| 839 | |||
| 840 | for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++) | ||
| 841 | if (!strcmp(of_id->compatible, soc)) | ||
| 842 | break; | ||
| 843 | |||
| 844 | if (!of_id->compatible) { | ||
| 845 | pr_err("mvebu-mbus: could not find a matching SoC family\n"); | ||
| 846 | return -ENODEV; | ||
| 847 | } | ||
| 848 | |||
| 849 | mbus->soc = of_id->data; | ||
| 850 | |||
| 851 | mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size); | ||
| 852 | if (!mbus->mbuswins_base) | ||
| 853 | return -ENOMEM; | ||
| 854 | |||
| 855 | mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size); | ||
| 856 | if (!mbus->sdramwins_base) { | ||
| 857 | iounmap(mbus_state.mbuswins_base); | ||
| 858 | return -ENOMEM; | ||
| 859 | } | ||
| 860 | |||
| 861 | if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric")) | ||
| 862 | mbus->hw_io_coherency = 1; | ||
| 863 | |||
| 864 | for (win = 0; win < mbus->soc->num_wins; win++) | ||
| 865 | mvebu_mbus_disable_window(mbus, win); | ||
| 866 | |||
| 867 | mbus->soc->setup_cpu_target(mbus); | ||
| 868 | |||
| 869 | return 0; | ||
| 870 | } | ||
diff --git a/include/linux/mbus.h b/include/linux/mbus.h index efa1a6d7aca8..dba482e31a13 100644 --- a/include/linux/mbus.h +++ b/include/linux/mbus.h | |||
| @@ -32,6 +32,20 @@ struct mbus_dram_target_info | |||
| 32 | } cs[4]; | 32 | } cs[4]; |
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | /* Flags for PCI/PCIe address decoding regions */ | ||
| 36 | #define MVEBU_MBUS_PCI_IO 0x1 | ||
| 37 | #define MVEBU_MBUS_PCI_MEM 0x2 | ||
| 38 | #define MVEBU_MBUS_PCI_WA 0x3 | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Magic value that explicits that we don't need a remapping-capable | ||
| 42 | * address decoding window. | ||
| 43 | */ | ||
| 44 | #define MVEBU_MBUS_NO_REMAP (0xffffffff) | ||
| 45 | |||
| 46 | /* Maximum size of a mbus window name */ | ||
| 47 | #define MVEBU_MBUS_MAX_WINNAME_SZ 32 | ||
| 48 | |||
| 35 | /* | 49 | /* |
| 36 | * The Marvell mbus is to be found only on SOCs from the Orion family | 50 | * The Marvell mbus is to be found only on SOCs from the Orion family |
| 37 | * at the moment. Provide a dummy stub for other architectures. | 51 | * at the moment. Provide a dummy stub for other architectures. |
| @@ -44,4 +58,15 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void) | |||
| 44 | return NULL; | 58 | return NULL; |
| 45 | } | 59 | } |
| 46 | #endif | 60 | #endif |
| 47 | #endif | 61 | |
| 62 | int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base, | ||
| 63 | size_t size, phys_addr_t remap, | ||
| 64 | unsigned int flags); | ||
| 65 | int mvebu_mbus_add_window(const char *devname, phys_addr_t base, | ||
| 66 | size_t size); | ||
| 67 | int mvebu_mbus_del_window(phys_addr_t base, size_t size); | ||
| 68 | int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base, | ||
| 69 | size_t mbus_size, phys_addr_t sdram_phys_base, | ||
| 70 | size_t sdram_size); | ||
| 71 | |||
| 72 | #endif /* __LINUX_MBUS_H */ | ||