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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 12:28:03 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 12:28:03 -0400
commitdfab34aa61a0f8c14a67d7b4c1dae28e57ba592d (patch)
tree581fd4d7394b838acb70c3c2e5d585b5b8a86b0d
parenta7726350e06401929eac0aa0677a5467106565fc (diff)
parent88cf9c5e494795a53ec360d0b38f483a6d4e508f (diff)
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree updates from Olof Johansson: "Part 1 of device-tree updates for 3.10. The bulk of the churn in this branch is due to i.MX moving from C-defined pin control over to device tree, which is a one-time conversion that will allow greater flexibility down the road. Besides that, there's PCI-e bindings for Marvell mvebu platforms and a handful of cleanups to tegra due to the new include file functionality of the device tree compiler" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (113 commits) arm: mvebu: PCIe Device Tree informations for Armada XP GP arm: mvebu: PCIe Device Tree informations for Armada 370 DB arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox arm: mvebu: PCIe Device Tree informations for Armada XP DB arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 arm: mvebu: add PCIe Device Tree informations for Armada XP arm: mvebu: add PCIe Device Tree informations for Armada 370 ARM: sunxi: unify osc24M_fixed and osc24M arm: vt8500: Add SDHC support to WM8505 DT ARM: dts: Add a 64 bits version of the skeleton device tree ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board ARM: mvebu: Add support for NOR flash device on Armada XP-GP board ARM: mvebu: Add Device Bus support for Armada 370/XP SoC ARM: dts: imx6dl-wandboard: Add USB Host support ARM: dts: imx51 cpu node ARM: dts: Add missing imx27-phytec-phycore dtb target ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module ARM: i.MX51: Add PATA support ARM: dts: Add initial support for Wandboard Dual-Lite ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx27-clock.txt117
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt6
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt955
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt759
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt1174
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt38
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt1596
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt39
-rw-r--r--Documentation/devicetree/bindings/timer/fsl,imxgpt.txt18
-rw-r--r--arch/arm/boot/dts/Makefile11
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts17
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts64
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts11
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi45
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi58
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts33
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts50
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi104
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi122
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi188
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts38
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi6
-rw-r--r--arch/arm/boot/dts/at91-ariag25.dts171
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi19
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9g15.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9g15ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9g25.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts9
-rw-r--r--arch/arm/boot/dts/at91sam9g35.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9g35ek.dts9
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi3
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9x25ek.dts14
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9x35ek.dts9
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi70
-rw-r--r--arch/arm/boot/dts/at91sam9x5cm.dtsi20
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi15
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi22
-rw-r--r--arch/arm/boot/dts/dove.dtsi5
-rw-r--r--arch/arm/boot/dts/imx25-karo-tx25.dts2
-rw-r--r--arch/arm/boot/dts/imx25-pdk.dts2
-rw-r--r--arch/arm/boot/dts/imx25.dtsi2
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts2
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts60
-rw-r--r--arch/arm/boot/dts/imx27-pdk.dts2
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts8
-rw-r--r--arch/arm/boot/dts/imx27.dtsi82
-rw-r--r--arch/arm/boot/dts/imx31-bug.dts2
-rw-r--r--arch/arm/boot/dts/imx31.dtsi18
-rw-r--r--arch/arm/boot/dts/imx35-pinfunc.h970
-rw-r--r--arch/arm/boot/dts/imx51-apf51.dts2
-rw-r--r--arch/arm/boot/dts/imx51-apf51dev.dts97
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts16
-rw-r--r--arch/arm/boot/dts/imx51-pinfunc.h773
-rw-r--r--arch/arm/boot/dts/imx51.dtsi343
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts70
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts18
-rw-r--r--arch/arm/boot/dts/imx53-mba53.dts82
-rw-r--r--arch/arm/boot/dts/imx53-pinfunc.h1189
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts22
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts16
-rw-r--r--arch/arm/boot/dts/imx53-tqma53.dtsi32
-rw-r--r--arch/arm/boot/dts/imx53.dtsi256
-rw-r--r--arch/arm/boot/dts/imx6dl-pinfunc.h1085
-rw-r--r--arch/arm/boot/dts/imx6dl-sabreauto.dts31
-rw-r--r--arch/arm/boot/dts/imx6dl-sabresd.dts35
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard.dts44
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi125
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts8
-rw-r--r--arch/arm/boot/dts/imx6q-pinfunc.h1041
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts33
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts18
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts67
-rw-r--r--arch/arm/boot/dts/imx6q-sbc6x.dts44
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi280
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi38
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi87
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi33
-rw-r--r--arch/arm/boot/dts/imx6sl-pinfunc.h1077
l---------arch/arm/boot/dts/include/dt-bindings1
-rw-r--r--arch/arm/boot/dts/kirkwood-6282.dtsi6
-rw-r--r--arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts4
-rw-r--r--arch/arm/boot/dts/mpa1600.dts69
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi33
-rw-r--r--arch/arm/boot/dts/skeleton64.dtsi13
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts32
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts6
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts32
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi253
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts24
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi193
-rw-r--r--arch/arm/boot/dts/sunxi.dtsi82
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi31
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi7
-rw-r--r--arch/arm/configs/dove_defconfig2
-rw-r--r--arch/arm/configs/kirkwood_defconfig2
-rw-r--r--arch/arm/configs/mvebu_defconfig9
-rw-r--r--arch/arm/mach-at91/at91rm9200.c1
-rw-r--r--arch/arm/mach-imx/Kconfig2
-rw-r--r--arch/arm/mach-imx/clk-imx27.c11
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c9
-rw-r--r--arch/arm/mach-imx/imx27-dt.c22
-rw-r--r--arch/arm/mach-imx/imx51-dt.c3
-rw-r--r--arch/arm/mach-imx/mm-imx5.c2
-rw-r--r--arch/arm/mach-imx/src.c4
-rw-r--r--arch/arm/mach-kirkwood/board-guruplug.c6
-rw-r--r--drivers/pinctrl/Kconfig12
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-imx.c126
-rw-r--r--drivers/pinctrl/pinctrl-imx.h29
-rw-r--r--drivers/pinctrl/pinctrl-imx35.c2088
-rw-r--r--drivers/pinctrl/pinctrl-imx51.c1532
-rw-r--r--drivers/pinctrl/pinctrl-imx53.c1597
-rw-r--r--drivers/pinctrl/pinctrl-imx6dl.c497
-rw-r--r--drivers/pinctrl/pinctrl-imx6q.c2301
-rw-r--r--drivers/pinctrl/pinctrl-imx6sl.c403
-rw-r--r--include/dt-bindings/gpio/gpio.h15
-rw-r--r--include/dt-bindings/interrupt-controller/arm-gic.h22
-rw-r--r--include/dt-bindings/interrupt-controller/irq.h19
-rw-r--r--scripts/Makefile.lib17
-rw-r--r--scripts/basic/fixdep.c93
127 files changed, 12434 insertions, 11152 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.txt b/Documentation/devicetree/bindings/clock/imx27-clock.txt
new file mode 100644
index 000000000000..ab1a56e9de9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx27-clock.txt
@@ -0,0 +1,117 @@
1* Clock bindings for Freescale i.MX27
2
3Required properties:
4- compatible: Should be "fsl,imx27-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX27
11clocks and IDs.
12
13 Clock ID
14 -----------------------
15 dummy 0
16 ckih 1
17 ckil 2
18 mpll 3
19 spll 4
20 mpll_main2 5
21 ahb 6
22 ipg 7
23 nfc_div 8
24 per1_div 9
25 per2_div 10
26 per3_div 11
27 per4_div 12
28 vpu_sel 13
29 vpu_div 14
30 usb_div 15
31 cpu_sel 16
32 clko_sel 17
33 cpu_div 18
34 clko_div 19
35 ssi1_sel 20
36 ssi2_sel 21
37 ssi1_div 22
38 ssi2_div 23
39 clko_en 24
40 ssi2_ipg_gate 25
41 ssi1_ipg_gate 26
42 slcdc_ipg_gate 27
43 sdhc3_ipg_gate 28
44 sdhc2_ipg_gate 29
45 sdhc1_ipg_gate 30
46 scc_ipg_gate 31
47 sahara_ipg_gate 32
48 rtc_ipg_gate 33
49 pwm_ipg_gate 34
50 owire_ipg_gate 35
51 lcdc_ipg_gate 36
52 kpp_ipg_gate 37
53 iim_ipg_gate 38
54 i2c2_ipg_gate 39
55 i2c1_ipg_gate 40
56 gpt6_ipg_gate 41
57 gpt5_ipg_gate 42
58 gpt4_ipg_gate 43
59 gpt3_ipg_gate 44
60 gpt2_ipg_gate 45
61 gpt1_ipg_gate 46
62 gpio_ipg_gate 47
63 fec_ipg_gate 48
64 emma_ipg_gate 49
65 dma_ipg_gate 50
66 cspi3_ipg_gate 51
67 cspi2_ipg_gate 52
68 cspi1_ipg_gate 53
69 nfc_baud_gate 54
70 ssi2_baud_gate 55
71 ssi1_baud_gate 56
72 vpu_baud_gate 57
73 per4_gate 58
74 per3_gate 59
75 per2_gate 60
76 per1_gate 61
77 usb_ahb_gate 62
78 slcdc_ahb_gate 63
79 sahara_ahb_gate 64
80 lcdc_ahb_gate 65
81 vpu_ahb_gate 66
82 fec_ahb_gate 67
83 emma_ahb_gate 68
84 emi_ahb_gate 69
85 dma_ahb_gate 70
86 csi_ahb_gate 71
87 brom_ahb_gate 72
88 ata_ahb_gate 73
89 wdog_ipg_gate 74
90 usb_ipg_gate 75
91 uart6_ipg_gate 76
92 uart5_ipg_gate 77
93 uart4_ipg_gate 78
94 uart3_ipg_gate 79
95 uart2_ipg_gate 80
96 uart1_ipg_gate 81
97 ckih_div1p5 82
98 fpm 83
99 mpll_osc_sel 84
100 mpll_sel 85
101
102Examples:
103
104clks: ccm@10027000{
105 compatible = "fsl,imx27-ccm";
106 reg = <0x10027000 0x1000>;
107 #clock-cells = <1>;
108};
109
110uart1: serial@1000a000 {
111 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
112 reg = <0x1000a000 0x1000>;
113 interrupts = <20>;
114 clocks = <&clks 81>, <&clks 61>;
115 clock-names = "ipg", "per";
116 status = "disabled";
117};
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
index ab19e6bc7d3b..bcfdab5d442e 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -24,9 +24,9 @@ Required properties for iomux controller:
24Required properties for pin configuration node: 24Required properties for pin configuration node:
25- fsl,pins: two integers array, represents a group of pins mux and config 25- fsl,pins: two integers array, represents a group of pins mux and config
26 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a 26 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
27 pin working on a specific function, CONFIG is the pad setting value like 27 pin working on a specific function, which consists of a tuple of
28 pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid 28 <mux_reg conf_reg input_reg mux_val input_val>. CONFIG is the pad setting
29 pins and functions of each SoC. 29 value like pull-up on this pin.
30 30
31Bits used for CONFIG: 31Bits used for CONFIG:
32NO_PAD_CTL(1 << 31): indicate this pin does not need config. 32NO_PAD_CTL(1 << 31): indicate this pin does not need config.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
index 1183f1a3be33..c083dfd25db9 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
@@ -29,956 +29,5 @@ PAD_CTL_DSE_MAX (2 << 1)
29PAD_CTL_SRE_FAST (1 << 0) 29PAD_CTL_SRE_FAST (1 << 0)
30PAD_CTL_SRE_SLOW (0 << 0) 30PAD_CTL_SRE_SLOW (0 << 0)
31 31
32See below for available PIN_FUNC_ID for imx35: 32Refer to imx35-pinfunc.h in device tree source folder for all available
330 MX35_PAD_CAPTURE__GPT_CAPIN1 33imx35 PIN_FUNC_ID.
341 MX35_PAD_CAPTURE__GPT_CMPOUT2
352 MX35_PAD_CAPTURE__CSPI2_SS1
363 MX35_PAD_CAPTURE__EPIT1_EPITO
374 MX35_PAD_CAPTURE__CCM_CLK32K
385 MX35_PAD_CAPTURE__GPIO1_4
396 MX35_PAD_COMPARE__GPT_CMPOUT1
407 MX35_PAD_COMPARE__GPT_CAPIN2
418 MX35_PAD_COMPARE__GPT_CMPOUT3
429 MX35_PAD_COMPARE__EPIT2_EPITO
4310 MX35_PAD_COMPARE__GPIO1_5
4411 MX35_PAD_COMPARE__SDMA_EXTDMA_2
4512 MX35_PAD_WDOG_RST__WDOG_WDOG_B
4613 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
4714 MX35_PAD_WDOG_RST__GPIO1_6
4815 MX35_PAD_GPIO1_0__GPIO1_0
4916 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
5017 MX35_PAD_GPIO1_0__OWIRE_LINE
5118 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
5219 MX35_PAD_GPIO1_1__GPIO1_1
5320 MX35_PAD_GPIO1_1__PWM_PWMO
5421 MX35_PAD_GPIO1_1__CSPI1_SS2
5522 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
5623 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
5724 MX35_PAD_GPIO2_0__GPIO2_0
5825 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
5926 MX35_PAD_GPIO3_0__GPIO3_0
6027 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
6128 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
6229 MX35_PAD_POR_B__CCM_POR_B
6330 MX35_PAD_CLKO__CCM_CLKO
6431 MX35_PAD_CLKO__GPIO1_8
6532 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
6633 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
6734 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
6835 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
6936 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
7037 MX35_PAD_VSTBY__CCM_VSTBY
7138 MX35_PAD_VSTBY__GPIO1_7
7239 MX35_PAD_A0__EMI_EIM_DA_L_0
7340 MX35_PAD_A1__EMI_EIM_DA_L_1
7441 MX35_PAD_A2__EMI_EIM_DA_L_2
7542 MX35_PAD_A3__EMI_EIM_DA_L_3
7643 MX35_PAD_A4__EMI_EIM_DA_L_4
7744 MX35_PAD_A5__EMI_EIM_DA_L_5
7845 MX35_PAD_A6__EMI_EIM_DA_L_6
7946 MX35_PAD_A7__EMI_EIM_DA_L_7
8047 MX35_PAD_A8__EMI_EIM_DA_H_8
8148 MX35_PAD_A9__EMI_EIM_DA_H_9
8249 MX35_PAD_A10__EMI_EIM_DA_H_10
8350 MX35_PAD_MA10__EMI_MA10
8451 MX35_PAD_A11__EMI_EIM_DA_H_11
8552 MX35_PAD_A12__EMI_EIM_DA_H_12
8653 MX35_PAD_A13__EMI_EIM_DA_H_13
8754 MX35_PAD_A14__EMI_EIM_DA_H2_14
8855 MX35_PAD_A15__EMI_EIM_DA_H2_15
8956 MX35_PAD_A16__EMI_EIM_A_16
9057 MX35_PAD_A17__EMI_EIM_A_17
9158 MX35_PAD_A18__EMI_EIM_A_18
9259 MX35_PAD_A19__EMI_EIM_A_19
9360 MX35_PAD_A20__EMI_EIM_A_20
9461 MX35_PAD_A21__EMI_EIM_A_21
9562 MX35_PAD_A22__EMI_EIM_A_22
9663 MX35_PAD_A23__EMI_EIM_A_23
9764 MX35_PAD_A24__EMI_EIM_A_24
9865 MX35_PAD_A25__EMI_EIM_A_25
9966 MX35_PAD_SDBA1__EMI_EIM_SDBA1
10067 MX35_PAD_SDBA0__EMI_EIM_SDBA0
10168 MX35_PAD_SD0__EMI_DRAM_D_0
10269 MX35_PAD_SD1__EMI_DRAM_D_1
10370 MX35_PAD_SD2__EMI_DRAM_D_2
10471 MX35_PAD_SD3__EMI_DRAM_D_3
10572 MX35_PAD_SD4__EMI_DRAM_D_4
10673 MX35_PAD_SD5__EMI_DRAM_D_5
10774 MX35_PAD_SD6__EMI_DRAM_D_6
10875 MX35_PAD_SD7__EMI_DRAM_D_7
10976 MX35_PAD_SD8__EMI_DRAM_D_8
11077 MX35_PAD_SD9__EMI_DRAM_D_9
11178 MX35_PAD_SD10__EMI_DRAM_D_10
11279 MX35_PAD_SD11__EMI_DRAM_D_11
11380 MX35_PAD_SD12__EMI_DRAM_D_12
11481 MX35_PAD_SD13__EMI_DRAM_D_13
11582 MX35_PAD_SD14__EMI_DRAM_D_14
11683 MX35_PAD_SD15__EMI_DRAM_D_15
11784 MX35_PAD_SD16__EMI_DRAM_D_16
11885 MX35_PAD_SD17__EMI_DRAM_D_17
11986 MX35_PAD_SD18__EMI_DRAM_D_18
12087 MX35_PAD_SD19__EMI_DRAM_D_19
12188 MX35_PAD_SD20__EMI_DRAM_D_20
12289 MX35_PAD_SD21__EMI_DRAM_D_21
12390 MX35_PAD_SD22__EMI_DRAM_D_22
12491 MX35_PAD_SD23__EMI_DRAM_D_23
12592 MX35_PAD_SD24__EMI_DRAM_D_24
12693 MX35_PAD_SD25__EMI_DRAM_D_25
12794 MX35_PAD_SD26__EMI_DRAM_D_26
12895 MX35_PAD_SD27__EMI_DRAM_D_27
12996 MX35_PAD_SD28__EMI_DRAM_D_28
13097 MX35_PAD_SD29__EMI_DRAM_D_29
13198 MX35_PAD_SD30__EMI_DRAM_D_30
13299 MX35_PAD_SD31__EMI_DRAM_D_31
133100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
134101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
135102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
136103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
137104 MX35_PAD_EB0__EMI_EIM_EB0_B
138105 MX35_PAD_EB1__EMI_EIM_EB1_B
139106 MX35_PAD_OE__EMI_EIM_OE
140107 MX35_PAD_CS0__EMI_EIM_CS0
141108 MX35_PAD_CS1__EMI_EIM_CS1
142109 MX35_PAD_CS1__EMI_NANDF_CE3
143110 MX35_PAD_CS2__EMI_EIM_CS2
144111 MX35_PAD_CS3__EMI_EIM_CS3
145112 MX35_PAD_CS4__EMI_EIM_CS4
146113 MX35_PAD_CS4__EMI_DTACK_B
147114 MX35_PAD_CS4__EMI_NANDF_CE1
148115 MX35_PAD_CS4__GPIO1_20
149116 MX35_PAD_CS5__EMI_EIM_CS5
150117 MX35_PAD_CS5__CSPI2_SS2
151118 MX35_PAD_CS5__CSPI1_SS2
152119 MX35_PAD_CS5__EMI_NANDF_CE2
153120 MX35_PAD_CS5__GPIO1_21
154121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
155122 MX35_PAD_NF_CE0__GPIO1_22
156123 MX35_PAD_ECB__EMI_EIM_ECB
157124 MX35_PAD_LBA__EMI_EIM_LBA
158125 MX35_PAD_BCLK__EMI_EIM_BCLK
159126 MX35_PAD_RW__EMI_EIM_RW
160127 MX35_PAD_RAS__EMI_DRAM_RAS
161128 MX35_PAD_CAS__EMI_DRAM_CAS
162129 MX35_PAD_SDWE__EMI_DRAM_SDWE
163130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
164131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
165132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
166133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
167134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
168135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
169136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
170137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
171138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
172139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
173140 MX35_PAD_NFWE_B__GPIO2_18
174141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
175142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
176143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
177144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
178145 MX35_PAD_NFRE_B__GPIO2_19
179146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
180147 MX35_PAD_NFALE__EMI_NANDF_ALE
181148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
182149 MX35_PAD_NFALE__IPU_DISPB_CS0
183150 MX35_PAD_NFALE__GPIO2_20
184151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
185152 MX35_PAD_NFCLE__EMI_NANDF_CLE
186153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
187154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
188155 MX35_PAD_NFCLE__GPIO2_21
189156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
190157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
191158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
192159 MX35_PAD_NFWP_B__IPU_DISPB_WR
193160 MX35_PAD_NFWP_B__GPIO2_22
194161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
195162 MX35_PAD_NFRB__EMI_NANDF_RB
196163 MX35_PAD_NFRB__IPU_DISPB_RD
197164 MX35_PAD_NFRB__GPIO2_23
198165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
199166 MX35_PAD_D15__EMI_EIM_D_15
200167 MX35_PAD_D14__EMI_EIM_D_14
201168 MX35_PAD_D13__EMI_EIM_D_13
202169 MX35_PAD_D12__EMI_EIM_D_12
203170 MX35_PAD_D11__EMI_EIM_D_11
204171 MX35_PAD_D10__EMI_EIM_D_10
205172 MX35_PAD_D9__EMI_EIM_D_9
206173 MX35_PAD_D8__EMI_EIM_D_8
207174 MX35_PAD_D7__EMI_EIM_D_7
208175 MX35_PAD_D6__EMI_EIM_D_6
209176 MX35_PAD_D5__EMI_EIM_D_5
210177 MX35_PAD_D4__EMI_EIM_D_4
211178 MX35_PAD_D3__EMI_EIM_D_3
212179 MX35_PAD_D2__EMI_EIM_D_2
213180 MX35_PAD_D1__EMI_EIM_D_1
214181 MX35_PAD_D0__EMI_EIM_D_0
215182 MX35_PAD_CSI_D8__IPU_CSI_D_8
216183 MX35_PAD_CSI_D8__KPP_COL_0
217184 MX35_PAD_CSI_D8__GPIO1_20
218185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
219186 MX35_PAD_CSI_D9__IPU_CSI_D_9
220187 MX35_PAD_CSI_D9__KPP_COL_1
221188 MX35_PAD_CSI_D9__GPIO1_21
222189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
223190 MX35_PAD_CSI_D10__IPU_CSI_D_10
224191 MX35_PAD_CSI_D10__KPP_COL_2
225192 MX35_PAD_CSI_D10__GPIO1_22
226193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
227194 MX35_PAD_CSI_D11__IPU_CSI_D_11
228195 MX35_PAD_CSI_D11__KPP_COL_3
229196 MX35_PAD_CSI_D11__GPIO1_23
230197 MX35_PAD_CSI_D12__IPU_CSI_D_12
231198 MX35_PAD_CSI_D12__KPP_ROW_0
232199 MX35_PAD_CSI_D12__GPIO1_24
233200 MX35_PAD_CSI_D13__IPU_CSI_D_13
234201 MX35_PAD_CSI_D13__KPP_ROW_1
235202 MX35_PAD_CSI_D13__GPIO1_25
236203 MX35_PAD_CSI_D14__IPU_CSI_D_14
237204 MX35_PAD_CSI_D14__KPP_ROW_2
238205 MX35_PAD_CSI_D14__GPIO1_26
239206 MX35_PAD_CSI_D15__IPU_CSI_D_15
240207 MX35_PAD_CSI_D15__KPP_ROW_3
241208 MX35_PAD_CSI_D15__GPIO1_27
242209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
243210 MX35_PAD_CSI_MCLK__GPIO1_28
244211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
245212 MX35_PAD_CSI_VSYNC__GPIO1_29
246213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
247214 MX35_PAD_CSI_HSYNC__GPIO1_30
248215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
249216 MX35_PAD_CSI_PIXCLK__GPIO1_31
250217 MX35_PAD_I2C1_CLK__I2C1_SCL
251218 MX35_PAD_I2C1_CLK__GPIO2_24
252219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
253220 MX35_PAD_I2C1_DAT__I2C1_SDA
254221 MX35_PAD_I2C1_DAT__GPIO2_25
255222 MX35_PAD_I2C2_CLK__I2C2_SCL
256223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
257224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
258225 MX35_PAD_I2C2_CLK__GPIO2_26
259226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
260227 MX35_PAD_I2C2_DAT__I2C2_SDA
261228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
262229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
263230 MX35_PAD_I2C2_DAT__GPIO2_27
264231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
265232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
266233 MX35_PAD_STXD4__GPIO2_28
267234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
268235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
269236 MX35_PAD_SRXD4__GPIO2_29
270237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
271238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
272239 MX35_PAD_SCK4__GPIO2_30
273240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
274241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
275242 MX35_PAD_STXFS4__GPIO2_31
276243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
277244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
278245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
279246 MX35_PAD_STXD5__CSPI2_MOSI
280247 MX35_PAD_STXD5__GPIO1_0
281248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
282249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
283250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
284251 MX35_PAD_SRXD5__CSPI2_MISO
285252 MX35_PAD_SRXD5__GPIO1_1
286253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
287254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
288255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
289256 MX35_PAD_SCK5__CSPI2_SCLK
290257 MX35_PAD_SCK5__GPIO1_2
291258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
292259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
293260 MX35_PAD_STXFS5__CSPI2_RDY
294261 MX35_PAD_STXFS5__GPIO1_3
295262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
296263 MX35_PAD_SCKR__ESAI_SCKR
297264 MX35_PAD_SCKR__GPIO1_4
298265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
299266 MX35_PAD_FSR__ESAI_FSR
300267 MX35_PAD_FSR__GPIO1_5
301268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
302269 MX35_PAD_HCKR__ESAI_HCKR
303270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
304271 MX35_PAD_HCKR__CSPI2_SS0
305272 MX35_PAD_HCKR__IPU_FLASH_STROBE
306273 MX35_PAD_HCKR__GPIO1_6
307274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
308275 MX35_PAD_SCKT__ESAI_SCKT
309276 MX35_PAD_SCKT__GPIO1_7
310277 MX35_PAD_SCKT__IPU_CSI_D_0
311278 MX35_PAD_SCKT__KPP_ROW_2
312279 MX35_PAD_FST__ESAI_FST
313280 MX35_PAD_FST__GPIO1_8
314281 MX35_PAD_FST__IPU_CSI_D_1
315282 MX35_PAD_FST__KPP_ROW_3
316283 MX35_PAD_HCKT__ESAI_HCKT
317284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
318285 MX35_PAD_HCKT__GPIO1_9
319286 MX35_PAD_HCKT__IPU_CSI_D_2
320287 MX35_PAD_HCKT__KPP_COL_3
321288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
322289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
323290 MX35_PAD_TX5_RX0__CSPI2_SS2
324291 MX35_PAD_TX5_RX0__CAN2_TXCAN
325292 MX35_PAD_TX5_RX0__UART2_DTR
326293 MX35_PAD_TX5_RX0__GPIO1_10
327294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
328295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
329296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
330297 MX35_PAD_TX4_RX1__CSPI2_SS3
331298 MX35_PAD_TX4_RX1__CAN2_RXCAN
332299 MX35_PAD_TX4_RX1__UART2_DSR
333300 MX35_PAD_TX4_RX1__GPIO1_11
334301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
335302 MX35_PAD_TX4_RX1__KPP_ROW_0
336303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
337304 MX35_PAD_TX3_RX2__I2C3_SCL
338305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
339306 MX35_PAD_TX3_RX2__GPIO1_12
340307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
341308 MX35_PAD_TX3_RX2__KPP_ROW_1
342309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
343310 MX35_PAD_TX2_RX3__I2C3_SDA
344311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
345312 MX35_PAD_TX2_RX3__GPIO1_13
346313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
347314 MX35_PAD_TX2_RX3__KPP_COL_0
348315 MX35_PAD_TX1__ESAI_TX1
349316 MX35_PAD_TX1__CCM_PMIC_RDY
350317 MX35_PAD_TX1__CSPI1_SS2
351318 MX35_PAD_TX1__EMI_NANDF_CE3
352319 MX35_PAD_TX1__UART2_RI
353320 MX35_PAD_TX1__GPIO1_14
354321 MX35_PAD_TX1__IPU_CSI_D_6
355322 MX35_PAD_TX1__KPP_COL_1
356323 MX35_PAD_TX0__ESAI_TX0
357324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
358325 MX35_PAD_TX0__CSPI1_SS3
359326 MX35_PAD_TX0__EMI_DTACK_B
360327 MX35_PAD_TX0__UART2_DCD
361328 MX35_PAD_TX0__GPIO1_15
362329 MX35_PAD_TX0__IPU_CSI_D_7
363330 MX35_PAD_TX0__KPP_COL_2
364331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
365332 MX35_PAD_CSPI1_MOSI__GPIO1_16
366333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
367334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
368335 MX35_PAD_CSPI1_MISO__GPIO1_17
369336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
370337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
371338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
372339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
373340 MX35_PAD_CSPI1_SS0__GPIO1_18
374341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
375342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
376343 MX35_PAD_CSPI1_SS1__PWM_PWMO
377344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
378345 MX35_PAD_CSPI1_SS1__GPIO1_19
379346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
380347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
381348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
382349 MX35_PAD_CSPI1_SCLK__GPIO3_4
383350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
384351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
385352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
386353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
387354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
388355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
389356 MX35_PAD_RXD1__UART1_RXD_MUX
390357 MX35_PAD_RXD1__CSPI2_MOSI
391358 MX35_PAD_RXD1__KPP_COL_4
392359 MX35_PAD_RXD1__GPIO3_6
393360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
394361 MX35_PAD_TXD1__UART1_TXD_MUX
395362 MX35_PAD_TXD1__CSPI2_MISO
396363 MX35_PAD_TXD1__KPP_COL_5
397364 MX35_PAD_TXD1__GPIO3_7
398365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
399366 MX35_PAD_RTS1__UART1_RTS
400367 MX35_PAD_RTS1__CSPI2_SCLK
401368 MX35_PAD_RTS1__I2C3_SCL
402369 MX35_PAD_RTS1__IPU_CSI_D_0
403370 MX35_PAD_RTS1__KPP_COL_6
404371 MX35_PAD_RTS1__GPIO3_8
405372 MX35_PAD_RTS1__EMI_NANDF_CE1
406373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
407374 MX35_PAD_CTS1__UART1_CTS
408375 MX35_PAD_CTS1__CSPI2_RDY
409376 MX35_PAD_CTS1__I2C3_SDA
410377 MX35_PAD_CTS1__IPU_CSI_D_1
411378 MX35_PAD_CTS1__KPP_COL_7
412379 MX35_PAD_CTS1__GPIO3_9
413380 MX35_PAD_CTS1__EMI_NANDF_CE2
414381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
415382 MX35_PAD_RXD2__UART2_RXD_MUX
416383 MX35_PAD_RXD2__KPP_ROW_4
417384 MX35_PAD_RXD2__GPIO3_10
418385 MX35_PAD_TXD2__UART2_TXD_MUX
419386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
420387 MX35_PAD_TXD2__KPP_ROW_5
421388 MX35_PAD_TXD2__GPIO3_11
422389 MX35_PAD_RTS2__UART2_RTS
423390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
424391 MX35_PAD_RTS2__CAN2_RXCAN
425392 MX35_PAD_RTS2__IPU_CSI_D_2
426393 MX35_PAD_RTS2__KPP_ROW_6
427394 MX35_PAD_RTS2__GPIO3_12
428395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
429396 MX35_PAD_RTS2__UART3_RXD_MUX
430397 MX35_PAD_CTS2__UART2_CTS
431398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
432399 MX35_PAD_CTS2__CAN2_TXCAN
433400 MX35_PAD_CTS2__IPU_CSI_D_3
434401 MX35_PAD_CTS2__KPP_ROW_7
435402 MX35_PAD_CTS2__GPIO3_13
436403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
437404 MX35_PAD_CTS2__UART3_TXD_MUX
438405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
439406 MX35_PAD_TCK__SJC_TCK
440407 MX35_PAD_TMS__SJC_TMS
441408 MX35_PAD_TDI__SJC_TDI
442409 MX35_PAD_TDO__SJC_TDO
443410 MX35_PAD_TRSTB__SJC_TRSTB
444411 MX35_PAD_DE_B__SJC_DE_B
445412 MX35_PAD_SJC_MOD__SJC_MOD
446413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
447414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
448415 MX35_PAD_USBOTG_PWR__GPIO3_14
449416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
450417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
451418 MX35_PAD_USBOTG_OC__GPIO3_15
452419 MX35_PAD_LD0__IPU_DISPB_DAT_0
453420 MX35_PAD_LD0__GPIO2_0
454421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
455422 MX35_PAD_LD1__IPU_DISPB_DAT_1
456423 MX35_PAD_LD1__GPIO2_1
457424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
458425 MX35_PAD_LD2__IPU_DISPB_DAT_2
459426 MX35_PAD_LD2__GPIO2_2
460427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
461428 MX35_PAD_LD3__IPU_DISPB_DAT_3
462429 MX35_PAD_LD3__GPIO2_3
463430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
464431 MX35_PAD_LD4__IPU_DISPB_DAT_4
465432 MX35_PAD_LD4__GPIO2_4
466433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
467434 MX35_PAD_LD5__IPU_DISPB_DAT_5
468435 MX35_PAD_LD5__GPIO2_5
469436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
470437 MX35_PAD_LD6__IPU_DISPB_DAT_6
471438 MX35_PAD_LD6__GPIO2_6
472439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
473440 MX35_PAD_LD7__IPU_DISPB_DAT_7
474441 MX35_PAD_LD7__GPIO2_7
475442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
476443 MX35_PAD_LD8__IPU_DISPB_DAT_8
477444 MX35_PAD_LD8__GPIO2_8
478445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
479446 MX35_PAD_LD9__IPU_DISPB_DAT_9
480447 MX35_PAD_LD9__GPIO2_9
481448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
482449 MX35_PAD_LD10__IPU_DISPB_DAT_10
483450 MX35_PAD_LD10__GPIO2_10
484451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
485452 MX35_PAD_LD11__IPU_DISPB_DAT_11
486453 MX35_PAD_LD11__GPIO2_11
487454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
488455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
489456 MX35_PAD_LD12__IPU_DISPB_DAT_12
490457 MX35_PAD_LD12__GPIO2_12
491458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
492459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
493460 MX35_PAD_LD13__IPU_DISPB_DAT_13
494461 MX35_PAD_LD13__GPIO2_13
495462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
496463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
497464 MX35_PAD_LD14__IPU_DISPB_DAT_14
498465 MX35_PAD_LD14__GPIO2_14
499466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
500467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
501468 MX35_PAD_LD15__IPU_DISPB_DAT_15
502469 MX35_PAD_LD15__GPIO2_15
503470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
504471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
505472 MX35_PAD_LD16__IPU_DISPB_DAT_16
506473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
507474 MX35_PAD_LD16__GPIO2_16
508475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
509476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
510477 MX35_PAD_LD17__IPU_DISPB_DAT_17
511478 MX35_PAD_LD17__IPU_DISPB_CS2
512479 MX35_PAD_LD17__GPIO2_17
513480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
514481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
515482 MX35_PAD_LD18__IPU_DISPB_DAT_18
516483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
517484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
518485 MX35_PAD_LD18__ESDHC3_CMD
519486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
520487 MX35_PAD_LD18__GPIO3_24
521488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
522489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
523490 MX35_PAD_LD19__IPU_DISPB_DAT_19
524491 MX35_PAD_LD19__IPU_DISPB_BCLK
525492 MX35_PAD_LD19__IPU_DISPB_CS1
526493 MX35_PAD_LD19__ESDHC3_CLK
527494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
528495 MX35_PAD_LD19__GPIO3_25
529496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
530497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
531498 MX35_PAD_LD20__IPU_DISPB_DAT_20
532499 MX35_PAD_LD20__IPU_DISPB_CS0
533500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
534501 MX35_PAD_LD20__ESDHC3_DAT0
535502 MX35_PAD_LD20__GPIO3_26
536503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
537504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
538505 MX35_PAD_LD21__IPU_DISPB_DAT_21
539506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
540507 MX35_PAD_LD21__IPU_DISPB_SER_RS
541508 MX35_PAD_LD21__ESDHC3_DAT1
542509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
543510 MX35_PAD_LD21__GPIO3_27
544511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
545512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
546513 MX35_PAD_LD22__IPU_DISPB_DAT_22
547514 MX35_PAD_LD22__IPU_DISPB_WR
548515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
549516 MX35_PAD_LD22__ESDHC3_DAT2
550517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
551518 MX35_PAD_LD22__GPIO3_28
552519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
553520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
554521 MX35_PAD_LD23__IPU_DISPB_DAT_23
555522 MX35_PAD_LD23__IPU_DISPB_RD
556523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
557524 MX35_PAD_LD23__ESDHC3_DAT3
558525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
559526 MX35_PAD_LD23__GPIO3_29
560527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
561528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
562529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
563530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
564531 MX35_PAD_D3_HSYNC__GPIO3_30
565532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
566533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
567534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
568535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
569536 MX35_PAD_D3_FPSHIFT__GPIO3_31
570537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
571538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
572539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
573540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
574541 MX35_PAD_D3_DRDY__GPIO1_0
575542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
576543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
577544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
578545 MX35_PAD_CONTRAST__GPIO1_1
579546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
580547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
581548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
582549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
583550 MX35_PAD_D3_VSYNC__GPIO1_2
584551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
585552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
586553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
587554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
588555 MX35_PAD_D3_REV__GPIO1_3
589556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
590557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
591558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
592559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
593560 MX35_PAD_D3_CLS__GPIO1_4
594561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
595562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
596563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
597564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
598565 MX35_PAD_D3_SPL__GPIO1_5
599566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
600567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
601568 MX35_PAD_SD1_CMD__ESDHC1_CMD
602569 MX35_PAD_SD1_CMD__MSHC_SCLK
603570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
604571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
605572 MX35_PAD_SD1_CMD__GPIO1_6
606573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
607574 MX35_PAD_SD1_CLK__ESDHC1_CLK
608575 MX35_PAD_SD1_CLK__MSHC_BS
609576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
610577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
611578 MX35_PAD_SD1_CLK__GPIO1_7
612579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
613580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
614581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
615582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
616583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
617584 MX35_PAD_SD1_DATA0__GPIO1_8
618585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
619586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
620587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
621588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
622589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
623590 MX35_PAD_SD1_DATA1__GPIO1_9
624591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
625592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
626593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
627594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
628595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
629596 MX35_PAD_SD1_DATA2__GPIO1_10
630597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
631598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
632599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
633600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
634601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
635602 MX35_PAD_SD1_DATA3__GPIO1_11
636603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
637604 MX35_PAD_SD2_CMD__ESDHC2_CMD
638605 MX35_PAD_SD2_CMD__I2C3_SCL
639606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
640607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
641608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
642609 MX35_PAD_SD2_CMD__GPIO2_0
643610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
644611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
645612 MX35_PAD_SD2_CLK__ESDHC2_CLK
646613 MX35_PAD_SD2_CLK__I2C3_SDA
647614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
648615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
649616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
650617 MX35_PAD_SD2_CLK__GPIO2_1
651618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
652619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
653620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
654621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
655622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
656623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
657624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
658625 MX35_PAD_SD2_DATA0__GPIO2_2
659626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
660627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
661628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
662629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
663630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
664631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
665632 MX35_PAD_SD2_DATA1__GPIO2_3
666633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
667634 MX35_PAD_SD2_DATA2__UART3_RTS
668635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
669636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
670637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
671638 MX35_PAD_SD2_DATA2__GPIO2_4
672639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
673640 MX35_PAD_SD2_DATA3__UART3_CTS
674641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
675642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
676643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
677644 MX35_PAD_SD2_DATA3__GPIO2_5
678645 MX35_PAD_ATA_CS0__ATA_CS0
679646 MX35_PAD_ATA_CS0__CSPI1_SS3
680647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
681648 MX35_PAD_ATA_CS0__GPIO2_6
682649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
683650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
684651 MX35_PAD_ATA_CS1__ATA_CS1
685652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
686653 MX35_PAD_ATA_CS1__CSPI2_SS0
687654 MX35_PAD_ATA_CS1__GPIO2_7
688655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
689656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
690657 MX35_PAD_ATA_DIOR__ATA_DIOR
691658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
692659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
693660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
694661 MX35_PAD_ATA_DIOR__CSPI2_SS1
695662 MX35_PAD_ATA_DIOR__GPIO2_8
696663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
697664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
698665 MX35_PAD_ATA_DIOW__ATA_DIOW
699666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
700667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
701668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
702669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
703670 MX35_PAD_ATA_DIOW__GPIO2_9
704671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
705672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
706673 MX35_PAD_ATA_DMACK__ATA_DMACK
707674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
708675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
709676 MX35_PAD_ATA_DMACK__CSPI2_MISO
710677 MX35_PAD_ATA_DMACK__GPIO2_10
711678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
712679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
713680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
714681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
715682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
716683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
717684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
718685 MX35_PAD_ATA_RESET_B__GPIO2_11
719686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
720687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
721688 MX35_PAD_ATA_IORDY__ATA_IORDY
722689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
723690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
724691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
725692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
726693 MX35_PAD_ATA_IORDY__GPIO2_12
727694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
728695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
729696 MX35_PAD_ATA_DATA0__ATA_DATA_0
730697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
731698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
732699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
733700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
734701 MX35_PAD_ATA_DATA0__GPIO2_13
735702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
736703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
737704 MX35_PAD_ATA_DATA1__ATA_DATA_1
738705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
739706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
740707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
741708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
742709 MX35_PAD_ATA_DATA1__GPIO2_14
743710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
744711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
745712 MX35_PAD_ATA_DATA2__ATA_DATA_2
746713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
747714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
748715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
749716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
750717 MX35_PAD_ATA_DATA2__GPIO2_15
751718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
752719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
753720 MX35_PAD_ATA_DATA3__ATA_DATA_3
754721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
755722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
756723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
757724 MX35_PAD_ATA_DATA3__GPIO2_16
758725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
759726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
760727 MX35_PAD_ATA_DATA4__ATA_DATA_4
761728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
762729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
763730 MX35_PAD_ATA_DATA4__GPIO2_17
764731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
765732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
766733 MX35_PAD_ATA_DATA5__ATA_DATA_5
767734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
768735 MX35_PAD_ATA_DATA5__GPIO2_18
769736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
770737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
771738 MX35_PAD_ATA_DATA6__ATA_DATA_6
772739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
773740 MX35_PAD_ATA_DATA6__UART1_DTR
774741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
775742 MX35_PAD_ATA_DATA6__GPIO2_19
776743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
777744 MX35_PAD_ATA_DATA7__ATA_DATA_7
778745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
779746 MX35_PAD_ATA_DATA7__UART1_DSR
780747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
781748 MX35_PAD_ATA_DATA7__GPIO2_20
782749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
783750 MX35_PAD_ATA_DATA8__ATA_DATA_8
784751 MX35_PAD_ATA_DATA8__UART3_RTS
785752 MX35_PAD_ATA_DATA8__UART1_RI
786753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
787754 MX35_PAD_ATA_DATA8__GPIO2_21
788755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
789756 MX35_PAD_ATA_DATA9__ATA_DATA_9
790757 MX35_PAD_ATA_DATA9__UART3_CTS
791758 MX35_PAD_ATA_DATA9__UART1_DCD
792759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
793760 MX35_PAD_ATA_DATA9__GPIO2_22
794761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
795762 MX35_PAD_ATA_DATA10__ATA_DATA_10
796763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
797764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
798765 MX35_PAD_ATA_DATA10__GPIO2_23
799766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
800767 MX35_PAD_ATA_DATA11__ATA_DATA_11
801768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
802769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
803770 MX35_PAD_ATA_DATA11__GPIO2_24
804771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
805772 MX35_PAD_ATA_DATA12__ATA_DATA_12
806773 MX35_PAD_ATA_DATA12__I2C3_SCL
807774 MX35_PAD_ATA_DATA12__GPIO2_25
808775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
809776 MX35_PAD_ATA_DATA13__ATA_DATA_13
810777 MX35_PAD_ATA_DATA13__I2C3_SDA
811778 MX35_PAD_ATA_DATA13__GPIO2_26
812779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
813780 MX35_PAD_ATA_DATA14__ATA_DATA_14
814781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
815782 MX35_PAD_ATA_DATA14__KPP_ROW_0
816783 MX35_PAD_ATA_DATA14__GPIO2_27
817784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
818785 MX35_PAD_ATA_DATA15__ATA_DATA_15
819786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
820787 MX35_PAD_ATA_DATA15__KPP_ROW_1
821788 MX35_PAD_ATA_DATA15__GPIO2_28
822789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
823790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
824791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
825792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
826793 MX35_PAD_ATA_INTRQ__GPIO2_29
827794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
828795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
829796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
830797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
831798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
832799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
833800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
834801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
835802 MX35_PAD_ATA_DMARQ__KPP_COL_0
836803 MX35_PAD_ATA_DMARQ__GPIO2_31
837804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
838805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
839806 MX35_PAD_ATA_DA0__ATA_DA_0
840807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
841808 MX35_PAD_ATA_DA0__KPP_COL_1
842809 MX35_PAD_ATA_DA0__GPIO3_0
843810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
844811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
845812 MX35_PAD_ATA_DA1__ATA_DA_1
846813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
847814 MX35_PAD_ATA_DA1__KPP_COL_2
848815 MX35_PAD_ATA_DA1__GPIO3_1
849816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
850817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
851818 MX35_PAD_ATA_DA2__ATA_DA_2
852819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
853820 MX35_PAD_ATA_DA2__KPP_COL_3
854821 MX35_PAD_ATA_DA2__GPIO3_2
855822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
856823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
857824 MX35_PAD_MLB_CLK__MLB_MLBCLK
858825 MX35_PAD_MLB_CLK__GPIO3_3
859826 MX35_PAD_MLB_DAT__MLB_MLBDAT
860827 MX35_PAD_MLB_DAT__GPIO3_4
861828 MX35_PAD_MLB_SIG__MLB_MLBSIG
862829 MX35_PAD_MLB_SIG__GPIO3_5
863830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
864831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
865832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
866833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
867834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
868835 MX35_PAD_FEC_TX_CLK__GPIO3_6
869836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
870837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
871838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
872839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
873840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
874841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
875842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
876843 MX35_PAD_FEC_RX_CLK__GPIO3_7
877844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
878845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
879846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
880847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
881848 MX35_PAD_FEC_RX_DV__UART3_RTS
882849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
883850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
884851 MX35_PAD_FEC_RX_DV__GPIO3_8
885852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
886853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
887854 MX35_PAD_FEC_COL__FEC_COL
888855 MX35_PAD_FEC_COL__ESDHC1_DAT7
889856 MX35_PAD_FEC_COL__UART3_CTS
890857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
891858 MX35_PAD_FEC_COL__CSPI2_RDY
892859 MX35_PAD_FEC_COL__GPIO3_9
893860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
894861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
895862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
896863 MX35_PAD_FEC_RDATA0__PWM_PWMO
897864 MX35_PAD_FEC_RDATA0__UART3_DTR
898865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
899866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
900867 MX35_PAD_FEC_RDATA0__GPIO3_10
901868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
902869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
903870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
904871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
905872 MX35_PAD_FEC_TDATA0__UART3_DSR
906873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
907874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
908875 MX35_PAD_FEC_TDATA0__GPIO3_11
909876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
910877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
911878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
912879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
913880 MX35_PAD_FEC_TX_EN__UART3_RI
914881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
915882 MX35_PAD_FEC_TX_EN__GPIO3_12
916883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
917884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
918885 MX35_PAD_FEC_MDC__FEC_MDC
919886 MX35_PAD_FEC_MDC__CAN2_TXCAN
920887 MX35_PAD_FEC_MDC__UART3_DCD
921888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
922889 MX35_PAD_FEC_MDC__GPIO3_13
923890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
924891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
925892 MX35_PAD_FEC_MDIO__FEC_MDIO
926893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
927894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
928895 MX35_PAD_FEC_MDIO__GPIO3_14
929896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
930897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
931898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
932899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
933900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
934901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
935902 MX35_PAD_FEC_TX_ERR__GPIO3_15
936903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
937904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
938905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
939906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
940907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
941908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
942909 MX35_PAD_FEC_RX_ERR__GPIO3_16
943910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
944911 MX35_PAD_FEC_CRS__FEC_CRS
945912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
946913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
947914 MX35_PAD_FEC_CRS__KPP_COL_5
948915 MX35_PAD_FEC_CRS__GPIO3_17
949916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
950917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
951918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
952919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
953920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
954921 MX35_PAD_FEC_RDATA1__KPP_COL_6
955922 MX35_PAD_FEC_RDATA1__GPIO3_18
956923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
957924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
958925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
959926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
960927 MX35_PAD_FEC_TDATA1__KPP_COL_7
961928 MX35_PAD_FEC_TDATA1__GPIO3_19
962929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
963930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
964931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
965932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
966933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
967934 MX35_PAD_FEC_RDATA2__GPIO3_20
968935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
969936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
970937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
971938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
972939 MX35_PAD_FEC_TDATA2__GPIO3_21
973940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
974941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
975942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
976943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
977944 MX35_PAD_FEC_RDATA3__GPIO3_22
978945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
979946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
980947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
981948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
982949 MX35_PAD_FEC_TDATA3__GPIO3_23
983950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
984951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
index b96fa4c31745..4d1408fcc99c 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
@@ -28,760 +28,5 @@ PAD_CTL_DSE_MAX (3 << 1)
28PAD_CTL_SRE_FAST (1 << 0) 28PAD_CTL_SRE_FAST (1 << 0)
29PAD_CTL_SRE_SLOW (0 << 0) 29PAD_CTL_SRE_SLOW (0 << 0)
30 30
31See below for available PIN_FUNC_ID for imx51: 31Refer to imx51-pinfunc.h in device tree source folder for all available
32MX51_PAD_EIM_D16__AUD4_RXFS 0 32imx51 PIN_FUNC_ID.
33MX51_PAD_EIM_D16__AUD5_TXD 1
34MX51_PAD_EIM_D16__EIM_D16 2
35MX51_PAD_EIM_D16__GPIO2_0 3
36MX51_PAD_EIM_D16__I2C1_SDA 4
37MX51_PAD_EIM_D16__UART2_CTS 5
38MX51_PAD_EIM_D16__USBH2_DATA0 6
39MX51_PAD_EIM_D17__AUD5_RXD 7
40MX51_PAD_EIM_D17__EIM_D17 8
41MX51_PAD_EIM_D17__GPIO2_1 9
42MX51_PAD_EIM_D17__UART2_RXD 10
43MX51_PAD_EIM_D17__UART3_CTS 11
44MX51_PAD_EIM_D17__USBH2_DATA1 12
45MX51_PAD_EIM_D18__AUD5_TXC 13
46MX51_PAD_EIM_D18__EIM_D18 14
47MX51_PAD_EIM_D18__GPIO2_2 15
48MX51_PAD_EIM_D18__UART2_TXD 16
49MX51_PAD_EIM_D18__UART3_RTS 17
50MX51_PAD_EIM_D18__USBH2_DATA2 18
51MX51_PAD_EIM_D19__AUD4_RXC 19
52MX51_PAD_EIM_D19__AUD5_TXFS 20
53MX51_PAD_EIM_D19__EIM_D19 21
54MX51_PAD_EIM_D19__GPIO2_3 22
55MX51_PAD_EIM_D19__I2C1_SCL 23
56MX51_PAD_EIM_D19__UART2_RTS 24
57MX51_PAD_EIM_D19__USBH2_DATA3 25
58MX51_PAD_EIM_D20__AUD4_TXD 26
59MX51_PAD_EIM_D20__EIM_D20 27
60MX51_PAD_EIM_D20__GPIO2_4 28
61MX51_PAD_EIM_D20__SRTC_ALARM_DEB 29
62MX51_PAD_EIM_D20__USBH2_DATA4 30
63MX51_PAD_EIM_D21__AUD4_RXD 31
64MX51_PAD_EIM_D21__EIM_D21 32
65MX51_PAD_EIM_D21__GPIO2_5 33
66MX51_PAD_EIM_D21__SRTC_ALARM_DEB 34
67MX51_PAD_EIM_D21__USBH2_DATA5 35
68MX51_PAD_EIM_D22__AUD4_TXC 36
69MX51_PAD_EIM_D22__EIM_D22 37
70MX51_PAD_EIM_D22__GPIO2_6 38
71MX51_PAD_EIM_D22__USBH2_DATA6 39
72MX51_PAD_EIM_D23__AUD4_TXFS 40
73MX51_PAD_EIM_D23__EIM_D23 41
74MX51_PAD_EIM_D23__GPIO2_7 42
75MX51_PAD_EIM_D23__SPDIF_OUT1 43
76MX51_PAD_EIM_D23__USBH2_DATA7 44
77MX51_PAD_EIM_D24__AUD6_RXFS 45
78MX51_PAD_EIM_D24__EIM_D24 46
79MX51_PAD_EIM_D24__GPIO2_8 47
80MX51_PAD_EIM_D24__I2C2_SDA 48
81MX51_PAD_EIM_D24__UART3_CTS 49
82MX51_PAD_EIM_D24__USBOTG_DATA0 50
83MX51_PAD_EIM_D25__EIM_D25 51
84MX51_PAD_EIM_D25__KEY_COL6 52
85MX51_PAD_EIM_D25__UART2_CTS 53
86MX51_PAD_EIM_D25__UART3_RXD 54
87MX51_PAD_EIM_D25__USBOTG_DATA1 55
88MX51_PAD_EIM_D26__EIM_D26 56
89MX51_PAD_EIM_D26__KEY_COL7 57
90MX51_PAD_EIM_D26__UART2_RTS 58
91MX51_PAD_EIM_D26__UART3_TXD 59
92MX51_PAD_EIM_D26__USBOTG_DATA2 60
93MX51_PAD_EIM_D27__AUD6_RXC 61
94MX51_PAD_EIM_D27__EIM_D27 62
95MX51_PAD_EIM_D27__GPIO2_9 63
96MX51_PAD_EIM_D27__I2C2_SCL 64
97MX51_PAD_EIM_D27__UART3_RTS 65
98MX51_PAD_EIM_D27__USBOTG_DATA3 66
99MX51_PAD_EIM_D28__AUD6_TXD 67
100MX51_PAD_EIM_D28__EIM_D28 68
101MX51_PAD_EIM_D28__KEY_ROW4 69
102MX51_PAD_EIM_D28__USBOTG_DATA4 70
103MX51_PAD_EIM_D29__AUD6_RXD 71
104MX51_PAD_EIM_D29__EIM_D29 72
105MX51_PAD_EIM_D29__KEY_ROW5 73
106MX51_PAD_EIM_D29__USBOTG_DATA5 74
107MX51_PAD_EIM_D30__AUD6_TXC 75
108MX51_PAD_EIM_D30__EIM_D30 76
109MX51_PAD_EIM_D30__KEY_ROW6 77
110MX51_PAD_EIM_D30__USBOTG_DATA6 78
111MX51_PAD_EIM_D31__AUD6_TXFS 79
112MX51_PAD_EIM_D31__EIM_D31 80
113MX51_PAD_EIM_D31__KEY_ROW7 81
114MX51_PAD_EIM_D31__USBOTG_DATA7 82
115MX51_PAD_EIM_A16__EIM_A16 83
116MX51_PAD_EIM_A16__GPIO2_10 84
117MX51_PAD_EIM_A16__OSC_FREQ_SEL0 85
118MX51_PAD_EIM_A17__EIM_A17 86
119MX51_PAD_EIM_A17__GPIO2_11 87
120MX51_PAD_EIM_A17__OSC_FREQ_SEL1 88
121MX51_PAD_EIM_A18__BOOT_LPB0 89
122MX51_PAD_EIM_A18__EIM_A18 90
123MX51_PAD_EIM_A18__GPIO2_12 91
124MX51_PAD_EIM_A19__BOOT_LPB1 92
125MX51_PAD_EIM_A19__EIM_A19 93
126MX51_PAD_EIM_A19__GPIO2_13 94
127MX51_PAD_EIM_A20__BOOT_UART_SRC0 95
128MX51_PAD_EIM_A20__EIM_A20 96
129MX51_PAD_EIM_A20__GPIO2_14 97
130MX51_PAD_EIM_A21__BOOT_UART_SRC1 98
131MX51_PAD_EIM_A21__EIM_A21 99
132MX51_PAD_EIM_A21__GPIO2_15 100
133MX51_PAD_EIM_A22__EIM_A22 101
134MX51_PAD_EIM_A22__GPIO2_16 102
135MX51_PAD_EIM_A23__BOOT_HPN_EN 103
136MX51_PAD_EIM_A23__EIM_A23 104
137MX51_PAD_EIM_A23__GPIO2_17 105
138MX51_PAD_EIM_A24__EIM_A24 106
139MX51_PAD_EIM_A24__GPIO2_18 107
140MX51_PAD_EIM_A24__USBH2_CLK 108
141MX51_PAD_EIM_A25__DISP1_PIN4 109
142MX51_PAD_EIM_A25__EIM_A25 110
143MX51_PAD_EIM_A25__GPIO2_19 111
144MX51_PAD_EIM_A25__USBH2_DIR 112
145MX51_PAD_EIM_A26__CSI1_DATA_EN 113
146MX51_PAD_EIM_A26__DISP2_EXT_CLK 114
147MX51_PAD_EIM_A26__EIM_A26 115
148MX51_PAD_EIM_A26__GPIO2_20 116
149MX51_PAD_EIM_A26__USBH2_STP 117
150MX51_PAD_EIM_A27__CSI2_DATA_EN 118
151MX51_PAD_EIM_A27__DISP1_PIN1 119
152MX51_PAD_EIM_A27__EIM_A27 120
153MX51_PAD_EIM_A27__GPIO2_21 121
154MX51_PAD_EIM_A27__USBH2_NXT 122
155MX51_PAD_EIM_EB0__EIM_EB0 123
156MX51_PAD_EIM_EB1__EIM_EB1 124
157MX51_PAD_EIM_EB2__AUD5_RXFS 125
158MX51_PAD_EIM_EB2__CSI1_D2 126
159MX51_PAD_EIM_EB2__EIM_EB2 127
160MX51_PAD_EIM_EB2__FEC_MDIO 128
161MX51_PAD_EIM_EB2__GPIO2_22 129
162MX51_PAD_EIM_EB2__GPT_CMPOUT1 130
163MX51_PAD_EIM_EB3__AUD5_RXC 131
164MX51_PAD_EIM_EB3__CSI1_D3 132
165MX51_PAD_EIM_EB3__EIM_EB3 133
166MX51_PAD_EIM_EB3__FEC_RDATA1 134
167MX51_PAD_EIM_EB3__GPIO2_23 135
168MX51_PAD_EIM_EB3__GPT_CMPOUT2 136
169MX51_PAD_EIM_OE__EIM_OE 137
170MX51_PAD_EIM_OE__GPIO2_24 138
171MX51_PAD_EIM_CS0__EIM_CS0 139
172MX51_PAD_EIM_CS0__GPIO2_25 140
173MX51_PAD_EIM_CS1__EIM_CS1 141
174MX51_PAD_EIM_CS1__GPIO2_26 142
175MX51_PAD_EIM_CS2__AUD5_TXD 143
176MX51_PAD_EIM_CS2__CSI1_D4 144
177MX51_PAD_EIM_CS2__EIM_CS2 145
178MX51_PAD_EIM_CS2__FEC_RDATA2 146
179MX51_PAD_EIM_CS2__GPIO2_27 147
180MX51_PAD_EIM_CS2__USBOTG_STP 148
181MX51_PAD_EIM_CS3__AUD5_RXD 149
182MX51_PAD_EIM_CS3__CSI1_D5 150
183MX51_PAD_EIM_CS3__EIM_CS3 151
184MX51_PAD_EIM_CS3__FEC_RDATA3 152
185MX51_PAD_EIM_CS3__GPIO2_28 153
186MX51_PAD_EIM_CS3__USBOTG_NXT 154
187MX51_PAD_EIM_CS4__AUD5_TXC 155
188MX51_PAD_EIM_CS4__CSI1_D6 156
189MX51_PAD_EIM_CS4__EIM_CS4 157
190MX51_PAD_EIM_CS4__FEC_RX_ER 158
191MX51_PAD_EIM_CS4__GPIO2_29 159
192MX51_PAD_EIM_CS4__USBOTG_CLK 160
193MX51_PAD_EIM_CS5__AUD5_TXFS 161
194MX51_PAD_EIM_CS5__CSI1_D7 162
195MX51_PAD_EIM_CS5__DISP1_EXT_CLK 163
196MX51_PAD_EIM_CS5__EIM_CS5 164
197MX51_PAD_EIM_CS5__FEC_CRS 165
198MX51_PAD_EIM_CS5__GPIO2_30 166
199MX51_PAD_EIM_CS5__USBOTG_DIR 167
200MX51_PAD_EIM_DTACK__EIM_DTACK 168
201MX51_PAD_EIM_DTACK__GPIO2_31 169
202MX51_PAD_EIM_LBA__EIM_LBA 170
203MX51_PAD_EIM_LBA__GPIO3_1 171
204MX51_PAD_EIM_CRE__EIM_CRE 172
205MX51_PAD_EIM_CRE__GPIO3_2 173
206MX51_PAD_DRAM_CS1__DRAM_CS1 174
207MX51_PAD_NANDF_WE_B__GPIO3_3 175
208MX51_PAD_NANDF_WE_B__NANDF_WE_B 176
209MX51_PAD_NANDF_WE_B__PATA_DIOW 177
210MX51_PAD_NANDF_WE_B__SD3_DATA0 178
211MX51_PAD_NANDF_RE_B__GPIO3_4 179
212MX51_PAD_NANDF_RE_B__NANDF_RE_B 180
213MX51_PAD_NANDF_RE_B__PATA_DIOR 181
214MX51_PAD_NANDF_RE_B__SD3_DATA1 182
215MX51_PAD_NANDF_ALE__GPIO3_5 183
216MX51_PAD_NANDF_ALE__NANDF_ALE 184
217MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 185
218MX51_PAD_NANDF_CLE__GPIO3_6 186
219MX51_PAD_NANDF_CLE__NANDF_CLE 187
220MX51_PAD_NANDF_CLE__PATA_RESET_B 188
221MX51_PAD_NANDF_WP_B__GPIO3_7 189
222MX51_PAD_NANDF_WP_B__NANDF_WP_B 190
223MX51_PAD_NANDF_WP_B__PATA_DMACK 191
224MX51_PAD_NANDF_WP_B__SD3_DATA2 192
225MX51_PAD_NANDF_RB0__ECSPI2_SS1 193
226MX51_PAD_NANDF_RB0__GPIO3_8 194
227MX51_PAD_NANDF_RB0__NANDF_RB0 195
228MX51_PAD_NANDF_RB0__PATA_DMARQ 196
229MX51_PAD_NANDF_RB0__SD3_DATA3 197
230MX51_PAD_NANDF_RB1__CSPI_MOSI 198
231MX51_PAD_NANDF_RB1__ECSPI2_RDY 199
232MX51_PAD_NANDF_RB1__GPIO3_9 200
233MX51_PAD_NANDF_RB1__NANDF_RB1 201
234MX51_PAD_NANDF_RB1__PATA_IORDY 202
235MX51_PAD_NANDF_RB1__SD4_CMD 203
236MX51_PAD_NANDF_RB2__DISP2_WAIT 204
237MX51_PAD_NANDF_RB2__ECSPI2_SCLK 205
238MX51_PAD_NANDF_RB2__FEC_COL 206
239MX51_PAD_NANDF_RB2__GPIO3_10 207
240MX51_PAD_NANDF_RB2__NANDF_RB2 208
241MX51_PAD_NANDF_RB2__USBH3_H3_DP 209
242MX51_PAD_NANDF_RB2__USBH3_NXT 210
243MX51_PAD_NANDF_RB3__DISP1_WAIT 211
244MX51_PAD_NANDF_RB3__ECSPI2_MISO 212
245MX51_PAD_NANDF_RB3__FEC_RX_CLK 213
246MX51_PAD_NANDF_RB3__GPIO3_11 214
247MX51_PAD_NANDF_RB3__NANDF_RB3 215
248MX51_PAD_NANDF_RB3__USBH3_CLK 216
249MX51_PAD_NANDF_RB3__USBH3_H3_DM 217
250MX51_PAD_GPIO_NAND__GPIO_NAND 218
251MX51_PAD_GPIO_NAND__PATA_INTRQ 219
252MX51_PAD_NANDF_CS0__GPIO3_16 220
253MX51_PAD_NANDF_CS0__NANDF_CS0 221
254MX51_PAD_NANDF_CS1__GPIO3_17 222
255MX51_PAD_NANDF_CS1__NANDF_CS1 223
256MX51_PAD_NANDF_CS2__CSPI_SCLK 224
257MX51_PAD_NANDF_CS2__FEC_TX_ER 225
258MX51_PAD_NANDF_CS2__GPIO3_18 226
259MX51_PAD_NANDF_CS2__NANDF_CS2 227
260MX51_PAD_NANDF_CS2__PATA_CS_0 228
261MX51_PAD_NANDF_CS2__SD4_CLK 229
262MX51_PAD_NANDF_CS2__USBH3_H1_DP 230
263MX51_PAD_NANDF_CS3__FEC_MDC 231
264MX51_PAD_NANDF_CS3__GPIO3_19 232
265MX51_PAD_NANDF_CS3__NANDF_CS3 233
266MX51_PAD_NANDF_CS3__PATA_CS_1 234
267MX51_PAD_NANDF_CS3__SD4_DAT0 235
268MX51_PAD_NANDF_CS3__USBH3_H1_DM 236
269MX51_PAD_NANDF_CS4__FEC_TDATA1 237
270MX51_PAD_NANDF_CS4__GPIO3_20 238
271MX51_PAD_NANDF_CS4__NANDF_CS4 239
272MX51_PAD_NANDF_CS4__PATA_DA_0 240
273MX51_PAD_NANDF_CS4__SD4_DAT1 241
274MX51_PAD_NANDF_CS4__USBH3_STP 242
275MX51_PAD_NANDF_CS5__FEC_TDATA2 243
276MX51_PAD_NANDF_CS5__GPIO3_21 244
277MX51_PAD_NANDF_CS5__NANDF_CS5 245
278MX51_PAD_NANDF_CS5__PATA_DA_1 246
279MX51_PAD_NANDF_CS5__SD4_DAT2 247
280MX51_PAD_NANDF_CS5__USBH3_DIR 248
281MX51_PAD_NANDF_CS6__CSPI_SS3 249
282MX51_PAD_NANDF_CS6__FEC_TDATA3 250
283MX51_PAD_NANDF_CS6__GPIO3_22 251
284MX51_PAD_NANDF_CS6__NANDF_CS6 252
285MX51_PAD_NANDF_CS6__PATA_DA_2 253
286MX51_PAD_NANDF_CS6__SD4_DAT3 254
287MX51_PAD_NANDF_CS7__FEC_TX_EN 255
288MX51_PAD_NANDF_CS7__GPIO3_23 256
289MX51_PAD_NANDF_CS7__NANDF_CS7 257
290MX51_PAD_NANDF_CS7__SD3_CLK 258
291MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 259
292MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 260
293MX51_PAD_NANDF_RDY_INT__GPIO3_24 261
294MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 262
295MX51_PAD_NANDF_RDY_INT__SD3_CMD 263
296MX51_PAD_NANDF_D15__ECSPI2_MOSI 264
297MX51_PAD_NANDF_D15__GPIO3_25 265
298MX51_PAD_NANDF_D15__NANDF_D15 266
299MX51_PAD_NANDF_D15__PATA_DATA15 267
300MX51_PAD_NANDF_D15__SD3_DAT7 268
301MX51_PAD_NANDF_D14__ECSPI2_SS3 269
302MX51_PAD_NANDF_D14__GPIO3_26 270
303MX51_PAD_NANDF_D14__NANDF_D14 271
304MX51_PAD_NANDF_D14__PATA_DATA14 272
305MX51_PAD_NANDF_D14__SD3_DAT6 273
306MX51_PAD_NANDF_D13__ECSPI2_SS2 274
307MX51_PAD_NANDF_D13__GPIO3_27 275
308MX51_PAD_NANDF_D13__NANDF_D13 276
309MX51_PAD_NANDF_D13__PATA_DATA13 277
310MX51_PAD_NANDF_D13__SD3_DAT5 278
311MX51_PAD_NANDF_D12__ECSPI2_SS1 279
312MX51_PAD_NANDF_D12__GPIO3_28 280
313MX51_PAD_NANDF_D12__NANDF_D12 281
314MX51_PAD_NANDF_D12__PATA_DATA12 282
315MX51_PAD_NANDF_D12__SD3_DAT4 283
316MX51_PAD_NANDF_D11__FEC_RX_DV 284
317MX51_PAD_NANDF_D11__GPIO3_29 285
318MX51_PAD_NANDF_D11__NANDF_D11 286
319MX51_PAD_NANDF_D11__PATA_DATA11 287
320MX51_PAD_NANDF_D11__SD3_DATA3 288
321MX51_PAD_NANDF_D10__GPIO3_30 289
322MX51_PAD_NANDF_D10__NANDF_D10 290
323MX51_PAD_NANDF_D10__PATA_DATA10 291
324MX51_PAD_NANDF_D10__SD3_DATA2 292
325MX51_PAD_NANDF_D9__FEC_RDATA0 293
326MX51_PAD_NANDF_D9__GPIO3_31 294
327MX51_PAD_NANDF_D9__NANDF_D9 295
328MX51_PAD_NANDF_D9__PATA_DATA9 296
329MX51_PAD_NANDF_D9__SD3_DATA1 297
330MX51_PAD_NANDF_D8__FEC_TDATA0 298
331MX51_PAD_NANDF_D8__GPIO4_0 299
332MX51_PAD_NANDF_D8__NANDF_D8 300
333MX51_PAD_NANDF_D8__PATA_DATA8 301
334MX51_PAD_NANDF_D8__SD3_DATA0 302
335MX51_PAD_NANDF_D7__GPIO4_1 303
336MX51_PAD_NANDF_D7__NANDF_D7 304
337MX51_PAD_NANDF_D7__PATA_DATA7 305
338MX51_PAD_NANDF_D7__USBH3_DATA0 306
339MX51_PAD_NANDF_D6__GPIO4_2 307
340MX51_PAD_NANDF_D6__NANDF_D6 308
341MX51_PAD_NANDF_D6__PATA_DATA6 309
342MX51_PAD_NANDF_D6__SD4_LCTL 310
343MX51_PAD_NANDF_D6__USBH3_DATA1 311
344MX51_PAD_NANDF_D5__GPIO4_3 312
345MX51_PAD_NANDF_D5__NANDF_D5 313
346MX51_PAD_NANDF_D5__PATA_DATA5 314
347MX51_PAD_NANDF_D5__SD4_WP 315
348MX51_PAD_NANDF_D5__USBH3_DATA2 316
349MX51_PAD_NANDF_D4__GPIO4_4 317
350MX51_PAD_NANDF_D4__NANDF_D4 318
351MX51_PAD_NANDF_D4__PATA_DATA4 319
352MX51_PAD_NANDF_D4__SD4_CD 320
353MX51_PAD_NANDF_D4__USBH3_DATA3 321
354MX51_PAD_NANDF_D3__GPIO4_5 322
355MX51_PAD_NANDF_D3__NANDF_D3 323
356MX51_PAD_NANDF_D3__PATA_DATA3 324
357MX51_PAD_NANDF_D3__SD4_DAT4 325
358MX51_PAD_NANDF_D3__USBH3_DATA4 326
359MX51_PAD_NANDF_D2__GPIO4_6 327
360MX51_PAD_NANDF_D2__NANDF_D2 328
361MX51_PAD_NANDF_D2__PATA_DATA2 329
362MX51_PAD_NANDF_D2__SD4_DAT5 330
363MX51_PAD_NANDF_D2__USBH3_DATA5 331
364MX51_PAD_NANDF_D1__GPIO4_7 332
365MX51_PAD_NANDF_D1__NANDF_D1 333
366MX51_PAD_NANDF_D1__PATA_DATA1 334
367MX51_PAD_NANDF_D1__SD4_DAT6 335
368MX51_PAD_NANDF_D1__USBH3_DATA6 336
369MX51_PAD_NANDF_D0__GPIO4_8 337
370MX51_PAD_NANDF_D0__NANDF_D0 338
371MX51_PAD_NANDF_D0__PATA_DATA0 339
372MX51_PAD_NANDF_D0__SD4_DAT7 340
373MX51_PAD_NANDF_D0__USBH3_DATA7 341
374MX51_PAD_CSI1_D8__CSI1_D8 342
375MX51_PAD_CSI1_D8__GPIO3_12 343
376MX51_PAD_CSI1_D9__CSI1_D9 344
377MX51_PAD_CSI1_D9__GPIO3_13 345
378MX51_PAD_CSI1_D10__CSI1_D10 346
379MX51_PAD_CSI1_D11__CSI1_D11 347
380MX51_PAD_CSI1_D12__CSI1_D12 348
381MX51_PAD_CSI1_D13__CSI1_D13 349
382MX51_PAD_CSI1_D14__CSI1_D14 350
383MX51_PAD_CSI1_D15__CSI1_D15 351
384MX51_PAD_CSI1_D16__CSI1_D16 352
385MX51_PAD_CSI1_D17__CSI1_D17 353
386MX51_PAD_CSI1_D18__CSI1_D18 354
387MX51_PAD_CSI1_D19__CSI1_D19 355
388MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 356
389MX51_PAD_CSI1_VSYNC__GPIO3_14 357
390MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 358
391MX51_PAD_CSI1_HSYNC__GPIO3_15 359
392MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 360
393MX51_PAD_CSI1_MCLK__CSI1_MCLK 361
394MX51_PAD_CSI2_D12__CSI2_D12 362
395MX51_PAD_CSI2_D12__GPIO4_9 363
396MX51_PAD_CSI2_D13__CSI2_D13 364
397MX51_PAD_CSI2_D13__GPIO4_10 365
398MX51_PAD_CSI2_D14__CSI2_D14 366
399MX51_PAD_CSI2_D15__CSI2_D15 367
400MX51_PAD_CSI2_D16__CSI2_D16 368
401MX51_PAD_CSI2_D17__CSI2_D17 369
402MX51_PAD_CSI2_D18__CSI2_D18 370
403MX51_PAD_CSI2_D18__GPIO4_11 371
404MX51_PAD_CSI2_D19__CSI2_D19 372
405MX51_PAD_CSI2_D19__GPIO4_12 373
406MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 374
407MX51_PAD_CSI2_VSYNC__GPIO4_13 375
408MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 376
409MX51_PAD_CSI2_HSYNC__GPIO4_14 377
410MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 378
411MX51_PAD_CSI2_PIXCLK__GPIO4_15 379
412MX51_PAD_I2C1_CLK__GPIO4_16 380
413MX51_PAD_I2C1_CLK__I2C1_CLK 381
414MX51_PAD_I2C1_DAT__GPIO4_17 382
415MX51_PAD_I2C1_DAT__I2C1_DAT 383
416MX51_PAD_AUD3_BB_TXD__AUD3_TXD 384
417MX51_PAD_AUD3_BB_TXD__GPIO4_18 385
418MX51_PAD_AUD3_BB_RXD__AUD3_RXD 386
419MX51_PAD_AUD3_BB_RXD__GPIO4_19 387
420MX51_PAD_AUD3_BB_RXD__UART3_RXD 388
421MX51_PAD_AUD3_BB_CK__AUD3_TXC 389
422MX51_PAD_AUD3_BB_CK__GPIO4_20 390
423MX51_PAD_AUD3_BB_FS__AUD3_TXFS 391
424MX51_PAD_AUD3_BB_FS__GPIO4_21 392
425MX51_PAD_AUD3_BB_FS__UART3_TXD 393
426MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 394
427MX51_PAD_CSPI1_MOSI__GPIO4_22 395
428MX51_PAD_CSPI1_MOSI__I2C1_SDA 396
429MX51_PAD_CSPI1_MISO__AUD4_RXD 397
430MX51_PAD_CSPI1_MISO__ECSPI1_MISO 398
431MX51_PAD_CSPI1_MISO__GPIO4_23 399
432MX51_PAD_CSPI1_SS0__AUD4_TXC 400
433MX51_PAD_CSPI1_SS0__ECSPI1_SS0 401
434MX51_PAD_CSPI1_SS0__GPIO4_24 402
435MX51_PAD_CSPI1_SS1__AUD4_TXD 403
436MX51_PAD_CSPI1_SS1__ECSPI1_SS1 404
437MX51_PAD_CSPI1_SS1__GPIO4_25 405
438MX51_PAD_CSPI1_RDY__AUD4_TXFS 406
439MX51_PAD_CSPI1_RDY__ECSPI1_RDY 407
440MX51_PAD_CSPI1_RDY__GPIO4_26 408
441MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 409
442MX51_PAD_CSPI1_SCLK__GPIO4_27 410
443MX51_PAD_CSPI1_SCLK__I2C1_SCL 411
444MX51_PAD_UART1_RXD__GPIO4_28 412
445MX51_PAD_UART1_RXD__UART1_RXD 413
446MX51_PAD_UART1_TXD__GPIO4_29 414
447MX51_PAD_UART1_TXD__PWM2_PWMO 415
448MX51_PAD_UART1_TXD__UART1_TXD 416
449MX51_PAD_UART1_RTS__GPIO4_30 417
450MX51_PAD_UART1_RTS__UART1_RTS 418
451MX51_PAD_UART1_CTS__GPIO4_31 419
452MX51_PAD_UART1_CTS__UART1_CTS 420
453MX51_PAD_UART2_RXD__FIRI_TXD 421
454MX51_PAD_UART2_RXD__GPIO1_20 422
455MX51_PAD_UART2_RXD__UART2_RXD 423
456MX51_PAD_UART2_TXD__FIRI_RXD 424
457MX51_PAD_UART2_TXD__GPIO1_21 425
458MX51_PAD_UART2_TXD__UART2_TXD 426
459MX51_PAD_UART3_RXD__CSI1_D0 427
460MX51_PAD_UART3_RXD__GPIO1_22 428
461MX51_PAD_UART3_RXD__UART1_DTR 429
462MX51_PAD_UART3_RXD__UART3_RXD 430
463MX51_PAD_UART3_TXD__CSI1_D1 431
464MX51_PAD_UART3_TXD__GPIO1_23 432
465MX51_PAD_UART3_TXD__UART1_DSR 433
466MX51_PAD_UART3_TXD__UART3_TXD 434
467MX51_PAD_OWIRE_LINE__GPIO1_24 435
468MX51_PAD_OWIRE_LINE__OWIRE_LINE 436
469MX51_PAD_OWIRE_LINE__SPDIF_OUT 437
470MX51_PAD_KEY_ROW0__KEY_ROW0 438
471MX51_PAD_KEY_ROW1__KEY_ROW1 439
472MX51_PAD_KEY_ROW2__KEY_ROW2 440
473MX51_PAD_KEY_ROW3__KEY_ROW3 441
474MX51_PAD_KEY_COL0__KEY_COL0 442
475MX51_PAD_KEY_COL0__PLL1_BYP 443
476MX51_PAD_KEY_COL1__KEY_COL1 444
477MX51_PAD_KEY_COL1__PLL2_BYP 445
478MX51_PAD_KEY_COL2__KEY_COL2 446
479MX51_PAD_KEY_COL2__PLL3_BYP 447
480MX51_PAD_KEY_COL3__KEY_COL3 448
481MX51_PAD_KEY_COL4__I2C2_SCL 449
482MX51_PAD_KEY_COL4__KEY_COL4 450
483MX51_PAD_KEY_COL4__SPDIF_OUT1 451
484MX51_PAD_KEY_COL4__UART1_RI 452
485MX51_PAD_KEY_COL4__UART3_RTS 453
486MX51_PAD_KEY_COL5__I2C2_SDA 454
487MX51_PAD_KEY_COL5__KEY_COL5 455
488MX51_PAD_KEY_COL5__UART1_DCD 456
489MX51_PAD_KEY_COL5__UART3_CTS 457
490MX51_PAD_USBH1_CLK__CSPI_SCLK 458
491MX51_PAD_USBH1_CLK__GPIO1_25 459
492MX51_PAD_USBH1_CLK__I2C2_SCL 460
493MX51_PAD_USBH1_CLK__USBH1_CLK 461
494MX51_PAD_USBH1_DIR__CSPI_MOSI 462
495MX51_PAD_USBH1_DIR__GPIO1_26 463
496MX51_PAD_USBH1_DIR__I2C2_SDA 464
497MX51_PAD_USBH1_DIR__USBH1_DIR 465
498MX51_PAD_USBH1_STP__CSPI_RDY 466
499MX51_PAD_USBH1_STP__GPIO1_27 467
500MX51_PAD_USBH1_STP__UART3_RXD 468
501MX51_PAD_USBH1_STP__USBH1_STP 469
502MX51_PAD_USBH1_NXT__CSPI_MISO 470
503MX51_PAD_USBH1_NXT__GPIO1_28 471
504MX51_PAD_USBH1_NXT__UART3_TXD 472
505MX51_PAD_USBH1_NXT__USBH1_NXT 473
506MX51_PAD_USBH1_DATA0__GPIO1_11 474
507MX51_PAD_USBH1_DATA0__UART2_CTS 475
508MX51_PAD_USBH1_DATA0__USBH1_DATA0 476
509MX51_PAD_USBH1_DATA1__GPIO1_12 477
510MX51_PAD_USBH1_DATA1__UART2_RXD 478
511MX51_PAD_USBH1_DATA1__USBH1_DATA1 479
512MX51_PAD_USBH1_DATA2__GPIO1_13 480
513MX51_PAD_USBH1_DATA2__UART2_TXD 481
514MX51_PAD_USBH1_DATA2__USBH1_DATA2 482
515MX51_PAD_USBH1_DATA3__GPIO1_14 483
516MX51_PAD_USBH1_DATA3__UART2_RTS 484
517MX51_PAD_USBH1_DATA3__USBH1_DATA3 485
518MX51_PAD_USBH1_DATA4__CSPI_SS0 486
519MX51_PAD_USBH1_DATA4__GPIO1_15 487
520MX51_PAD_USBH1_DATA4__USBH1_DATA4 488
521MX51_PAD_USBH1_DATA5__CSPI_SS1 489
522MX51_PAD_USBH1_DATA5__GPIO1_16 490
523MX51_PAD_USBH1_DATA5__USBH1_DATA5 491
524MX51_PAD_USBH1_DATA6__CSPI_SS3 492
525MX51_PAD_USBH1_DATA6__GPIO1_17 493
526MX51_PAD_USBH1_DATA6__USBH1_DATA6 494
527MX51_PAD_USBH1_DATA7__ECSPI1_SS3 495
528MX51_PAD_USBH1_DATA7__ECSPI2_SS3 496
529MX51_PAD_USBH1_DATA7__GPIO1_18 497
530MX51_PAD_USBH1_DATA7__USBH1_DATA7 498
531MX51_PAD_DI1_PIN11__DI1_PIN11 499
532MX51_PAD_DI1_PIN11__ECSPI1_SS2 500
533MX51_PAD_DI1_PIN11__GPIO3_0 501
534MX51_PAD_DI1_PIN12__DI1_PIN12 502
535MX51_PAD_DI1_PIN12__GPIO3_1 503
536MX51_PAD_DI1_PIN13__DI1_PIN13 504
537MX51_PAD_DI1_PIN13__GPIO3_2 505
538MX51_PAD_DI1_D0_CS__DI1_D0_CS 506
539MX51_PAD_DI1_D0_CS__GPIO3_3 507
540MX51_PAD_DI1_D1_CS__DI1_D1_CS 508
541MX51_PAD_DI1_D1_CS__DISP1_PIN14 509
542MX51_PAD_DI1_D1_CS__DISP1_PIN5 510
543MX51_PAD_DI1_D1_CS__GPIO3_4 511
544MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 512
545MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 513
546MX51_PAD_DISPB2_SER_DIN__GPIO3_5 514
547MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 515
548MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 516
549MX51_PAD_DISPB2_SER_DIO__GPIO3_6 517
550MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 518
551MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 519
552MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 520
553MX51_PAD_DISPB2_SER_CLK__GPIO3_7 521
554MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 522
555MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 523
556MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 524
557MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 525
558MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 526
559MX51_PAD_DISPB2_SER_RS__GPIO3_8 527
560MX51_PAD_DISP1_DAT0__DISP1_DAT0 528
561MX51_PAD_DISP1_DAT1__DISP1_DAT1 529
562MX51_PAD_DISP1_DAT2__DISP1_DAT2 530
563MX51_PAD_DISP1_DAT3__DISP1_DAT3 531
564MX51_PAD_DISP1_DAT4__DISP1_DAT4 532
565MX51_PAD_DISP1_DAT5__DISP1_DAT5 533
566MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 534
567MX51_PAD_DISP1_DAT6__DISP1_DAT6 535
568MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 536
569MX51_PAD_DISP1_DAT7__DISP1_DAT7 537
570MX51_PAD_DISP1_DAT8__BOOT_SRC0 538
571MX51_PAD_DISP1_DAT8__DISP1_DAT8 539
572MX51_PAD_DISP1_DAT9__BOOT_SRC1 540
573MX51_PAD_DISP1_DAT9__DISP1_DAT9 541
574MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 542
575MX51_PAD_DISP1_DAT10__DISP1_DAT10 543
576MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 544
577MX51_PAD_DISP1_DAT11__DISP1_DAT11 545
578MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 546
579MX51_PAD_DISP1_DAT12__DISP1_DAT12 547
580MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 548
581MX51_PAD_DISP1_DAT13__DISP1_DAT13 549
582MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 550
583MX51_PAD_DISP1_DAT14__DISP1_DAT14 551
584MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 552
585MX51_PAD_DISP1_DAT15__DISP1_DAT15 553
586MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 554
587MX51_PAD_DISP1_DAT16__DISP1_DAT16 555
588MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 556
589MX51_PAD_DISP1_DAT17__DISP1_DAT17 557
590MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 558
591MX51_PAD_DISP1_DAT18__DISP1_DAT18 559
592MX51_PAD_DISP1_DAT18__DISP2_PIN11 560
593MX51_PAD_DISP1_DAT18__DISP2_PIN5 561
594MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 562
595MX51_PAD_DISP1_DAT19__DISP1_DAT19 563
596MX51_PAD_DISP1_DAT19__DISP2_PIN12 564
597MX51_PAD_DISP1_DAT19__DISP2_PIN6 565
598MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 566
599MX51_PAD_DISP1_DAT20__DISP1_DAT20 567
600MX51_PAD_DISP1_DAT20__DISP2_PIN13 568
601MX51_PAD_DISP1_DAT20__DISP2_PIN7 569
602MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 570
603MX51_PAD_DISP1_DAT21__DISP1_DAT21 571
604MX51_PAD_DISP1_DAT21__DISP2_PIN14 572
605MX51_PAD_DISP1_DAT21__DISP2_PIN8 573
606MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 574
607MX51_PAD_DISP1_DAT22__DISP1_DAT22 575
608MX51_PAD_DISP1_DAT22__DISP2_D0_CS 576
609MX51_PAD_DISP1_DAT22__DISP2_DAT16 577
610MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 578
611MX51_PAD_DISP1_DAT23__DISP1_DAT23 579
612MX51_PAD_DISP1_DAT23__DISP2_D1_CS 580
613MX51_PAD_DISP1_DAT23__DISP2_DAT17 581
614MX51_PAD_DISP1_DAT23__DISP2_SER_CS 582
615MX51_PAD_DI1_PIN3__DI1_PIN3 583
616MX51_PAD_DI1_PIN2__DI1_PIN2 584
617MX51_PAD_DI_GP2__DISP1_SER_CLK 585
618MX51_PAD_DI_GP2__DISP2_WAIT 586
619MX51_PAD_DI_GP3__CSI1_DATA_EN 587
620MX51_PAD_DI_GP3__DISP1_SER_DIO 588
621MX51_PAD_DI_GP3__FEC_TX_ER 589
622MX51_PAD_DI2_PIN4__CSI2_DATA_EN 590
623MX51_PAD_DI2_PIN4__DI2_PIN4 591
624MX51_PAD_DI2_PIN4__FEC_CRS 592
625MX51_PAD_DI2_PIN2__DI2_PIN2 593
626MX51_PAD_DI2_PIN2__FEC_MDC 594
627MX51_PAD_DI2_PIN3__DI2_PIN3 595
628MX51_PAD_DI2_PIN3__FEC_MDIO 596
629MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 597
630MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 598
631MX51_PAD_DI_GP4__DI2_PIN15 599
632MX51_PAD_DI_GP4__DISP1_SER_DIN 600
633MX51_PAD_DI_GP4__DISP2_PIN1 601
634MX51_PAD_DI_GP4__FEC_RDATA2 602
635MX51_PAD_DISP2_DAT0__DISP2_DAT0 603
636MX51_PAD_DISP2_DAT0__FEC_RDATA3 604
637MX51_PAD_DISP2_DAT0__KEY_COL6 605
638MX51_PAD_DISP2_DAT0__UART3_RXD 606
639MX51_PAD_DISP2_DAT0__USBH3_CLK 607
640MX51_PAD_DISP2_DAT1__DISP2_DAT1 608
641MX51_PAD_DISP2_DAT1__FEC_RX_ER 609
642MX51_PAD_DISP2_DAT1__KEY_COL7 610
643MX51_PAD_DISP2_DAT1__UART3_TXD 611
644MX51_PAD_DISP2_DAT1__USBH3_DIR 612
645MX51_PAD_DISP2_DAT2__DISP2_DAT2 613
646MX51_PAD_DISP2_DAT3__DISP2_DAT3 614
647MX51_PAD_DISP2_DAT4__DISP2_DAT4 615
648MX51_PAD_DISP2_DAT5__DISP2_DAT5 616
649MX51_PAD_DISP2_DAT6__DISP2_DAT6 617
650MX51_PAD_DISP2_DAT6__FEC_TDATA1 618
651MX51_PAD_DISP2_DAT6__GPIO1_19 619
652MX51_PAD_DISP2_DAT6__KEY_ROW4 620
653MX51_PAD_DISP2_DAT6__USBH3_STP 621
654MX51_PAD_DISP2_DAT7__DISP2_DAT7 622
655MX51_PAD_DISP2_DAT7__FEC_TDATA2 623
656MX51_PAD_DISP2_DAT7__GPIO1_29 624
657MX51_PAD_DISP2_DAT7__KEY_ROW5 625
658MX51_PAD_DISP2_DAT7__USBH3_NXT 626
659MX51_PAD_DISP2_DAT8__DISP2_DAT8 627
660MX51_PAD_DISP2_DAT8__FEC_TDATA3 628
661MX51_PAD_DISP2_DAT8__GPIO1_30 629
662MX51_PAD_DISP2_DAT8__KEY_ROW6 630
663MX51_PAD_DISP2_DAT8__USBH3_DATA0 631
664MX51_PAD_DISP2_DAT9__AUD6_RXC 632
665MX51_PAD_DISP2_DAT9__DISP2_DAT9 633
666MX51_PAD_DISP2_DAT9__FEC_TX_EN 634
667MX51_PAD_DISP2_DAT9__GPIO1_31 635
668MX51_PAD_DISP2_DAT9__USBH3_DATA1 636
669MX51_PAD_DISP2_DAT10__DISP2_DAT10 637
670MX51_PAD_DISP2_DAT10__DISP2_SER_CS 638
671MX51_PAD_DISP2_DAT10__FEC_COL 639
672MX51_PAD_DISP2_DAT10__KEY_ROW7 640
673MX51_PAD_DISP2_DAT10__USBH3_DATA2 641
674MX51_PAD_DISP2_DAT11__AUD6_TXD 642
675MX51_PAD_DISP2_DAT11__DISP2_DAT11 643
676MX51_PAD_DISP2_DAT11__FEC_RX_CLK 644
677MX51_PAD_DISP2_DAT11__GPIO1_10 645
678MX51_PAD_DISP2_DAT11__USBH3_DATA3 646
679MX51_PAD_DISP2_DAT12__AUD6_RXD 647
680MX51_PAD_DISP2_DAT12__DISP2_DAT12 648
681MX51_PAD_DISP2_DAT12__FEC_RX_DV 649
682MX51_PAD_DISP2_DAT12__USBH3_DATA4 650
683MX51_PAD_DISP2_DAT13__AUD6_TXC 651
684MX51_PAD_DISP2_DAT13__DISP2_DAT13 652
685MX51_PAD_DISP2_DAT13__FEC_TX_CLK 653
686MX51_PAD_DISP2_DAT13__USBH3_DATA5 654
687MX51_PAD_DISP2_DAT14__AUD6_TXFS 655
688MX51_PAD_DISP2_DAT14__DISP2_DAT14 656
689MX51_PAD_DISP2_DAT14__FEC_RDATA0 657
690MX51_PAD_DISP2_DAT14__USBH3_DATA6 658
691MX51_PAD_DISP2_DAT15__AUD6_RXFS 659
692MX51_PAD_DISP2_DAT15__DISP1_SER_CS 660
693MX51_PAD_DISP2_DAT15__DISP2_DAT15 661
694MX51_PAD_DISP2_DAT15__FEC_TDATA0 662
695MX51_PAD_DISP2_DAT15__USBH3_DATA7 663
696MX51_PAD_SD1_CMD__AUD5_RXFS 664
697MX51_PAD_SD1_CMD__CSPI_MOSI 665
698MX51_PAD_SD1_CMD__SD1_CMD 666
699MX51_PAD_SD1_CLK__AUD5_RXC 667
700MX51_PAD_SD1_CLK__CSPI_SCLK 668
701MX51_PAD_SD1_CLK__SD1_CLK 669
702MX51_PAD_SD1_DATA0__AUD5_TXD 670
703MX51_PAD_SD1_DATA0__CSPI_MISO 671
704MX51_PAD_SD1_DATA0__SD1_DATA0 672
705MX51_PAD_EIM_DA0__EIM_DA0 673
706MX51_PAD_EIM_DA1__EIM_DA1 674
707MX51_PAD_EIM_DA2__EIM_DA2 675
708MX51_PAD_EIM_DA3__EIM_DA3 676
709MX51_PAD_SD1_DATA1__AUD5_RXD 677
710MX51_PAD_SD1_DATA1__SD1_DATA1 678
711MX51_PAD_EIM_DA4__EIM_DA4 679
712MX51_PAD_EIM_DA5__EIM_DA5 680
713MX51_PAD_EIM_DA6__EIM_DA6 681
714MX51_PAD_EIM_DA7__EIM_DA7 682
715MX51_PAD_SD1_DATA2__AUD5_TXC 683
716MX51_PAD_SD1_DATA2__SD1_DATA2 684
717MX51_PAD_EIM_DA10__EIM_DA10 685
718MX51_PAD_EIM_DA11__EIM_DA11 686
719MX51_PAD_EIM_DA8__EIM_DA8 687
720MX51_PAD_EIM_DA9__EIM_DA9 688
721MX51_PAD_SD1_DATA3__AUD5_TXFS 689
722MX51_PAD_SD1_DATA3__CSPI_SS1 690
723MX51_PAD_SD1_DATA3__SD1_DATA3 691
724MX51_PAD_GPIO1_0__CSPI_SS2 692
725MX51_PAD_GPIO1_0__GPIO1_0 693
726MX51_PAD_GPIO1_0__SD1_CD 694
727MX51_PAD_GPIO1_1__CSPI_MISO 695
728MX51_PAD_GPIO1_1__GPIO1_1 696
729MX51_PAD_GPIO1_1__SD1_WP 697
730MX51_PAD_EIM_DA12__EIM_DA12 698
731MX51_PAD_EIM_DA13__EIM_DA13 699
732MX51_PAD_EIM_DA14__EIM_DA14 700
733MX51_PAD_EIM_DA15__EIM_DA15 701
734MX51_PAD_SD2_CMD__CSPI_MOSI 702
735MX51_PAD_SD2_CMD__I2C1_SCL 703
736MX51_PAD_SD2_CMD__SD2_CMD 704
737MX51_PAD_SD2_CLK__CSPI_SCLK 705
738MX51_PAD_SD2_CLK__I2C1_SDA 706
739MX51_PAD_SD2_CLK__SD2_CLK 707
740MX51_PAD_SD2_DATA0__CSPI_MISO 708
741MX51_PAD_SD2_DATA0__SD1_DAT4 709
742MX51_PAD_SD2_DATA0__SD2_DATA0 710
743MX51_PAD_SD2_DATA1__SD1_DAT5 711
744MX51_PAD_SD2_DATA1__SD2_DATA1 712
745MX51_PAD_SD2_DATA1__USBH3_H2_DP 713
746MX51_PAD_SD2_DATA2__SD1_DAT6 714
747MX51_PAD_SD2_DATA2__SD2_DATA2 715
748MX51_PAD_SD2_DATA2__USBH3_H2_DM 716
749MX51_PAD_SD2_DATA3__CSPI_SS2 717
750MX51_PAD_SD2_DATA3__SD1_DAT7 718
751MX51_PAD_SD2_DATA3__SD2_DATA3 719
752MX51_PAD_GPIO1_2__CCM_OUT_2 720
753MX51_PAD_GPIO1_2__GPIO1_2 721
754MX51_PAD_GPIO1_2__I2C2_SCL 722
755MX51_PAD_GPIO1_2__PLL1_BYP 723
756MX51_PAD_GPIO1_2__PWM1_PWMO 724
757MX51_PAD_GPIO1_3__GPIO1_3 725
758MX51_PAD_GPIO1_3__I2C2_SDA 726
759MX51_PAD_GPIO1_3__PLL2_BYP 727
760MX51_PAD_GPIO1_3__PWM2_PWMO 728
761MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 729
762MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 730
763MX51_PAD_GPIO1_4__DISP2_EXT_CLK 731
764MX51_PAD_GPIO1_4__EIM_RDY 732
765MX51_PAD_GPIO1_4__GPIO1_4 733
766MX51_PAD_GPIO1_4__WDOG1_WDOG_B 734
767MX51_PAD_GPIO1_5__CSI2_MCLK 735
768MX51_PAD_GPIO1_5__DISP2_PIN16 736
769MX51_PAD_GPIO1_5__GPIO1_5 737
770MX51_PAD_GPIO1_5__WDOG2_WDOG_B 738
771MX51_PAD_GPIO1_6__DISP2_PIN17 739
772MX51_PAD_GPIO1_6__GPIO1_6 740
773MX51_PAD_GPIO1_6__REF_EN_B 741
774MX51_PAD_GPIO1_7__CCM_OUT_0 742
775MX51_PAD_GPIO1_7__GPIO1_7 743
776MX51_PAD_GPIO1_7__SD2_WP 744
777MX51_PAD_GPIO1_7__SPDIF_OUT1 745
778MX51_PAD_GPIO1_8__CSI2_DATA_EN 746
779MX51_PAD_GPIO1_8__GPIO1_8 747
780MX51_PAD_GPIO1_8__SD2_CD 748
781MX51_PAD_GPIO1_8__USBH3_PWR 749
782MX51_PAD_GPIO1_9__CCM_OUT_1 750
783MX51_PAD_GPIO1_9__DISP2_D1_CS 751
784MX51_PAD_GPIO1_9__DISP2_SER_CS 752
785MX51_PAD_GPIO1_9__GPIO1_9 753
786MX51_PAD_GPIO1_9__SD2_LCTL 754
787MX51_PAD_GPIO1_9__USBH3_OC 755
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
index ca85ca432ef0..25dcb77cfaf7 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
@@ -28,1175 +28,5 @@ PAD_CTL_DSE_MAX (3 << 1)
28PAD_CTL_SRE_FAST (1 << 0) 28PAD_CTL_SRE_FAST (1 << 0)
29PAD_CTL_SRE_SLOW (0 << 0) 29PAD_CTL_SRE_SLOW (0 << 0)
30 30
31See below for available PIN_FUNC_ID for imx53: 31Refer to imx53-pinfunc.h in device tree source folder for all available
32MX53_PAD_GPIO_19__KPP_COL_5 0 32imx53 PIN_FUNC_ID.
33MX53_PAD_GPIO_19__GPIO4_5 1
34MX53_PAD_GPIO_19__CCM_CLKO 2
35MX53_PAD_GPIO_19__SPDIF_OUT1 3
36MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 4
37MX53_PAD_GPIO_19__ECSPI1_RDY 5
38MX53_PAD_GPIO_19__FEC_TDATA_3 6
39MX53_PAD_GPIO_19__SRC_INT_BOOT 7
40MX53_PAD_KEY_COL0__KPP_COL_0 8
41MX53_PAD_KEY_COL0__GPIO4_6 9
42MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 10
43MX53_PAD_KEY_COL0__UART4_TXD_MUX 11
44MX53_PAD_KEY_COL0__ECSPI1_SCLK 12
45MX53_PAD_KEY_COL0__FEC_RDATA_3 13
46MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 14
47MX53_PAD_KEY_ROW0__KPP_ROW_0 15
48MX53_PAD_KEY_ROW0__GPIO4_7 16
49MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 17
50MX53_PAD_KEY_ROW0__UART4_RXD_MUX 18
51MX53_PAD_KEY_ROW0__ECSPI1_MOSI 19
52MX53_PAD_KEY_ROW0__FEC_TX_ER 20
53MX53_PAD_KEY_COL1__KPP_COL_1 21
54MX53_PAD_KEY_COL1__GPIO4_8 22
55MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 23
56MX53_PAD_KEY_COL1__UART5_TXD_MUX 24
57MX53_PAD_KEY_COL1__ECSPI1_MISO 25
58MX53_PAD_KEY_COL1__FEC_RX_CLK 26
59MX53_PAD_KEY_COL1__USBPHY1_TXREADY 27
60MX53_PAD_KEY_ROW1__KPP_ROW_1 28
61MX53_PAD_KEY_ROW1__GPIO4_9 29
62MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 30
63MX53_PAD_KEY_ROW1__UART5_RXD_MUX 31
64MX53_PAD_KEY_ROW1__ECSPI1_SS0 32
65MX53_PAD_KEY_ROW1__FEC_COL 33
66MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 34
67MX53_PAD_KEY_COL2__KPP_COL_2 35
68MX53_PAD_KEY_COL2__GPIO4_10 36
69MX53_PAD_KEY_COL2__CAN1_TXCAN 37
70MX53_PAD_KEY_COL2__FEC_MDIO 38
71MX53_PAD_KEY_COL2__ECSPI1_SS1 39
72MX53_PAD_KEY_COL2__FEC_RDATA_2 40
73MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 41
74MX53_PAD_KEY_ROW2__KPP_ROW_2 42
75MX53_PAD_KEY_ROW2__GPIO4_11 43
76MX53_PAD_KEY_ROW2__CAN1_RXCAN 44
77MX53_PAD_KEY_ROW2__FEC_MDC 45
78MX53_PAD_KEY_ROW2__ECSPI1_SS2 46
79MX53_PAD_KEY_ROW2__FEC_TDATA_2 47
80MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 48
81MX53_PAD_KEY_COL3__KPP_COL_3 49
82MX53_PAD_KEY_COL3__GPIO4_12 50
83MX53_PAD_KEY_COL3__USBOH3_H2_DP 51
84MX53_PAD_KEY_COL3__SPDIF_IN1 52
85MX53_PAD_KEY_COL3__I2C2_SCL 53
86MX53_PAD_KEY_COL3__ECSPI1_SS3 54
87MX53_PAD_KEY_COL3__FEC_CRS 55
88MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 56
89MX53_PAD_KEY_ROW3__KPP_ROW_3 57
90MX53_PAD_KEY_ROW3__GPIO4_13 58
91MX53_PAD_KEY_ROW3__USBOH3_H2_DM 59
92MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 60
93MX53_PAD_KEY_ROW3__I2C2_SDA 61
94MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 62
95MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 63
96MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 64
97MX53_PAD_KEY_COL4__KPP_COL_4 65
98MX53_PAD_KEY_COL4__GPIO4_14 66
99MX53_PAD_KEY_COL4__CAN2_TXCAN 67
100MX53_PAD_KEY_COL4__IPU_SISG_4 68
101MX53_PAD_KEY_COL4__UART5_RTS 69
102MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 70
103MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 71
104MX53_PAD_KEY_ROW4__KPP_ROW_4 72
105MX53_PAD_KEY_ROW4__GPIO4_15 73
106MX53_PAD_KEY_ROW4__CAN2_RXCAN 74
107MX53_PAD_KEY_ROW4__IPU_SISG_5 75
108MX53_PAD_KEY_ROW4__UART5_CTS 76
109MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 77
110MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 78
111MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 79
112MX53_PAD_DI0_DISP_CLK__GPIO4_16 80
113MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 81
114MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 82
115MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 83
116MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 84
117MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 85
118MX53_PAD_DI0_PIN15__GPIO4_17 86
119MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 87
120MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 88
121MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 89
122MX53_PAD_DI0_PIN15__USBPHY1_BVALID 90
123MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 91
124MX53_PAD_DI0_PIN2__GPIO4_18 92
125MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 93
126MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 94
127MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 95
128MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 96
129MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 97
130MX53_PAD_DI0_PIN3__GPIO4_19 98
131MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 99
132MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 100
133MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 101
134MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 102
135MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 103
136MX53_PAD_DI0_PIN4__GPIO4_20 104
137MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 105
138MX53_PAD_DI0_PIN4__ESDHC1_WP 106
139MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 107
140MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 108
141MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 109
142MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 110
143MX53_PAD_DISP0_DAT0__GPIO4_21 111
144MX53_PAD_DISP0_DAT0__CSPI_SCLK 112
145MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 113
146MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 114
147MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 115
148MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 116
149MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 117
150MX53_PAD_DISP0_DAT1__GPIO4_22 118
151MX53_PAD_DISP0_DAT1__CSPI_MOSI 119
152MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 120
153MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 121
154MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 122
155MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 123
156MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 124
157MX53_PAD_DISP0_DAT2__GPIO4_23 125
158MX53_PAD_DISP0_DAT2__CSPI_MISO 126
159MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 127
160MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 128
161MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 129
162MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 130
163MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 131
164MX53_PAD_DISP0_DAT3__GPIO4_24 132
165MX53_PAD_DISP0_DAT3__CSPI_SS0 133
166MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 134
167MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 135
168MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 136
169MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 137
170MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 138
171MX53_PAD_DISP0_DAT4__GPIO4_25 139
172MX53_PAD_DISP0_DAT4__CSPI_SS1 140
173MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 141
174MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 142
175MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 143
176MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 144
177MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 145
178MX53_PAD_DISP0_DAT5__GPIO4_26 146
179MX53_PAD_DISP0_DAT5__CSPI_SS2 147
180MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 148
181MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 149
182MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 150
183MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 151
184MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 152
185MX53_PAD_DISP0_DAT6__GPIO4_27 153
186MX53_PAD_DISP0_DAT6__CSPI_SS3 154
187MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 155
188MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 156
189MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 157
190MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 158
191MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 159
192MX53_PAD_DISP0_DAT7__GPIO4_28 160
193MX53_PAD_DISP0_DAT7__CSPI_RDY 161
194MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 162
195MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 163
196MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 164
197MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 165
198MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 166
199MX53_PAD_DISP0_DAT8__GPIO4_29 167
200MX53_PAD_DISP0_DAT8__PWM1_PWMO 168
201MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 169
202MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 170
203MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 171
204MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 172
205MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 173
206MX53_PAD_DISP0_DAT9__GPIO4_30 174
207MX53_PAD_DISP0_DAT9__PWM2_PWMO 175
208MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 176
209MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 177
210MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 178
211MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 179
212MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 180
213MX53_PAD_DISP0_DAT10__GPIO4_31 181
214MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 182
215MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 183
216MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 184
217MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 185
218MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 186
219MX53_PAD_DISP0_DAT11__GPIO5_5 187
220MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 188
221MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 189
222MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 190
223MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 191
224MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 192
225MX53_PAD_DISP0_DAT12__GPIO5_6 193
226MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 194
227MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 195
228MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 196
229MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 197
230MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 198
231MX53_PAD_DISP0_DAT13__GPIO5_7 199
232MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 200
233MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 201
234MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 202
235MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 203
236MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 204
237MX53_PAD_DISP0_DAT14__GPIO5_8 205
238MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 206
239MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 207
240MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 208
241MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 209
242MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 210
243MX53_PAD_DISP0_DAT15__GPIO5_9 211
244MX53_PAD_DISP0_DAT15__ECSPI1_SS1 212
245MX53_PAD_DISP0_DAT15__ECSPI2_SS1 213
246MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 214
247MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 215
248MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 216
249MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 217
250MX53_PAD_DISP0_DAT16__GPIO5_10 218
251MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 219
252MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 220
253MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 221
254MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 222
255MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 223
256MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 224
257MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 225
258MX53_PAD_DISP0_DAT17__GPIO5_11 226
259MX53_PAD_DISP0_DAT17__ECSPI2_MISO 227
260MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 228
261MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 229
262MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 230
263MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 231
264MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 232
265MX53_PAD_DISP0_DAT18__GPIO5_12 233
266MX53_PAD_DISP0_DAT18__ECSPI2_SS0 234
267MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 235
268MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 236
269MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 237
270MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 238
271MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 239
272MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 240
273MX53_PAD_DISP0_DAT19__GPIO5_13 241
274MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 242
275MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 243
276MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 244
277MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 245
278MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 246
279MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 247
280MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 248
281MX53_PAD_DISP0_DAT20__GPIO5_14 249
282MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 250
283MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 251
284MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 252
285MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 253
286MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 254
287MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 255
288MX53_PAD_DISP0_DAT21__GPIO5_15 256
289MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 257
290MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 258
291MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 259
292MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 260
293MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 261
294MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 262
295MX53_PAD_DISP0_DAT22__GPIO5_16 263
296MX53_PAD_DISP0_DAT22__ECSPI1_MISO 264
297MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 265
298MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 266
299MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 267
300MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 268
301MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 269
302MX53_PAD_DISP0_DAT23__GPIO5_17 270
303MX53_PAD_DISP0_DAT23__ECSPI1_SS0 271
304MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 272
305MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 273
306MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 274
307MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 275
308MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 276
309MX53_PAD_CSI0_PIXCLK__GPIO5_18 277
310MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 278
311MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 279
312MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 280
313MX53_PAD_CSI0_MCLK__GPIO5_19 281
314MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 282
315MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 283
316MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 284
317MX53_PAD_CSI0_MCLK__TPIU_TRCTL 285
318MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 286
319MX53_PAD_CSI0_DATA_EN__GPIO5_20 287
320MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 288
321MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 289
322MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 290
323MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 291
324MX53_PAD_CSI0_VSYNC__GPIO5_21 292
325MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 293
326MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 294
327MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 295
328MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 296
329MX53_PAD_CSI0_DAT4__GPIO5_22 297
330MX53_PAD_CSI0_DAT4__KPP_COL_5 298
331MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 299
332MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 300
333MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 301
334MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 302
335MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 303
336MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 304
337MX53_PAD_CSI0_DAT5__GPIO5_23 305
338MX53_PAD_CSI0_DAT5__KPP_ROW_5 306
339MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 307
340MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 308
341MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 309
342MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 310
343MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 311
344MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 312
345MX53_PAD_CSI0_DAT6__GPIO5_24 313
346MX53_PAD_CSI0_DAT6__KPP_COL_6 314
347MX53_PAD_CSI0_DAT6__ECSPI1_MISO 315
348MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 316
349MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 317
350MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 318
351MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 319
352MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 320
353MX53_PAD_CSI0_DAT7__GPIO5_25 321
354MX53_PAD_CSI0_DAT7__KPP_ROW_6 322
355MX53_PAD_CSI0_DAT7__ECSPI1_SS0 323
356MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 324
357MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 325
358MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 326
359MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 327
360MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 328
361MX53_PAD_CSI0_DAT8__GPIO5_26 329
362MX53_PAD_CSI0_DAT8__KPP_COL_7 330
363MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 331
364MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 332
365MX53_PAD_CSI0_DAT8__I2C1_SDA 333
366MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 334
367MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 335
368MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 336
369MX53_PAD_CSI0_DAT9__GPIO5_27 337
370MX53_PAD_CSI0_DAT9__KPP_ROW_7 338
371MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 339
372MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 340
373MX53_PAD_CSI0_DAT9__I2C1_SCL 341
374MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 342
375MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 343
376MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 344
377MX53_PAD_CSI0_DAT10__GPIO5_28 345
378MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 346
379MX53_PAD_CSI0_DAT10__ECSPI2_MISO 347
380MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 348
381MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 349
382MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 350
383MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 351
384MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 352
385MX53_PAD_CSI0_DAT11__GPIO5_29 353
386MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 354
387MX53_PAD_CSI0_DAT11__ECSPI2_SS0 355
388MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 356
389MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 357
390MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 358
391MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 359
392MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 360
393MX53_PAD_CSI0_DAT12__GPIO5_30 361
394MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 362
395MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 363
396MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 364
397MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 365
398MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 366
399MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 367
400MX53_PAD_CSI0_DAT13__GPIO5_31 368
401MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 369
402MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 370
403MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 371
404MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 372
405MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 373
406MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 374
407MX53_PAD_CSI0_DAT14__GPIO6_0 375
408MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 376
409MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 377
410MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 378
411MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 379
412MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 380
413MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 381
414MX53_PAD_CSI0_DAT15__GPIO6_1 382
415MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 383
416MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 384
417MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 385
418MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 386
419MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 387
420MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 388
421MX53_PAD_CSI0_DAT16__GPIO6_2 389
422MX53_PAD_CSI0_DAT16__UART4_RTS 390
423MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 391
424MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 392
425MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 393
426MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 394
427MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 395
428MX53_PAD_CSI0_DAT17__GPIO6_3 396
429MX53_PAD_CSI0_DAT17__UART4_CTS 397
430MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 398
431MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 399
432MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 400
433MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 401
434MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 402
435MX53_PAD_CSI0_DAT18__GPIO6_4 403
436MX53_PAD_CSI0_DAT18__UART5_RTS 404
437MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 405
438MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 406
439MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 407
440MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 408
441MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 409
442MX53_PAD_CSI0_DAT19__GPIO6_5 410
443MX53_PAD_CSI0_DAT19__UART5_CTS 411
444MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 412
445MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 413
446MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 414
447MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 415
448MX53_PAD_EIM_A25__EMI_WEIM_A_25 416
449MX53_PAD_EIM_A25__GPIO5_2 417
450MX53_PAD_EIM_A25__ECSPI2_RDY 418
451MX53_PAD_EIM_A25__IPU_DI1_PIN12 419
452MX53_PAD_EIM_A25__CSPI_SS1 420
453MX53_PAD_EIM_A25__IPU_DI0_D1_CS 421
454MX53_PAD_EIM_A25__USBPHY1_BISTOK 422
455MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 423
456MX53_PAD_EIM_EB2__GPIO2_30 424
457MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 425
458MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 426
459MX53_PAD_EIM_EB2__ECSPI1_SS0 427
460MX53_PAD_EIM_EB2__I2C2_SCL 428
461MX53_PAD_EIM_D16__EMI_WEIM_D_16 429
462MX53_PAD_EIM_D16__GPIO3_16 430
463MX53_PAD_EIM_D16__IPU_DI0_PIN5 431
464MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 432
465MX53_PAD_EIM_D16__ECSPI1_SCLK 433
466MX53_PAD_EIM_D16__I2C2_SDA 434
467MX53_PAD_EIM_D17__EMI_WEIM_D_17 435
468MX53_PAD_EIM_D17__GPIO3_17 436
469MX53_PAD_EIM_D17__IPU_DI0_PIN6 437
470MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 438
471MX53_PAD_EIM_D17__ECSPI1_MISO 439
472MX53_PAD_EIM_D17__I2C3_SCL 440
473MX53_PAD_EIM_D18__EMI_WEIM_D_18 441
474MX53_PAD_EIM_D18__GPIO3_18 442
475MX53_PAD_EIM_D18__IPU_DI0_PIN7 443
476MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 444
477MX53_PAD_EIM_D18__ECSPI1_MOSI 445
478MX53_PAD_EIM_D18__I2C3_SDA 446
479MX53_PAD_EIM_D18__IPU_DI1_D0_CS 447
480MX53_PAD_EIM_D19__EMI_WEIM_D_19 448
481MX53_PAD_EIM_D19__GPIO3_19 449
482MX53_PAD_EIM_D19__IPU_DI0_PIN8 450
483MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 451
484MX53_PAD_EIM_D19__ECSPI1_SS1 452
485MX53_PAD_EIM_D19__EPIT1_EPITO 453
486MX53_PAD_EIM_D19__UART1_CTS 454
487MX53_PAD_EIM_D19__USBOH3_USBH2_OC 455
488MX53_PAD_EIM_D20__EMI_WEIM_D_20 456
489MX53_PAD_EIM_D20__GPIO3_20 457
490MX53_PAD_EIM_D20__IPU_DI0_PIN16 458
491MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 459
492MX53_PAD_EIM_D20__CSPI_SS0 460
493MX53_PAD_EIM_D20__EPIT2_EPITO 461
494MX53_PAD_EIM_D20__UART1_RTS 462
495MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 463
496MX53_PAD_EIM_D21__EMI_WEIM_D_21 464
497MX53_PAD_EIM_D21__GPIO3_21 465
498MX53_PAD_EIM_D21__IPU_DI0_PIN17 466
499MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 467
500MX53_PAD_EIM_D21__CSPI_SCLK 468
501MX53_PAD_EIM_D21__I2C1_SCL 469
502MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 470
503MX53_PAD_EIM_D22__EMI_WEIM_D_22 471
504MX53_PAD_EIM_D22__GPIO3_22 472
505MX53_PAD_EIM_D22__IPU_DI0_PIN1 473
506MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 474
507MX53_PAD_EIM_D22__CSPI_MISO 475
508MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 476
509MX53_PAD_EIM_D23__EMI_WEIM_D_23 477
510MX53_PAD_EIM_D23__GPIO3_23 478
511MX53_PAD_EIM_D23__UART3_CTS 479
512MX53_PAD_EIM_D23__UART1_DCD 480
513MX53_PAD_EIM_D23__IPU_DI0_D0_CS 481
514MX53_PAD_EIM_D23__IPU_DI1_PIN2 482
515MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 483
516MX53_PAD_EIM_D23__IPU_DI1_PIN14 484
517MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 485
518MX53_PAD_EIM_EB3__GPIO2_31 486
519MX53_PAD_EIM_EB3__UART3_RTS 487
520MX53_PAD_EIM_EB3__UART1_RI 488
521MX53_PAD_EIM_EB3__IPU_DI1_PIN3 489
522MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 490
523MX53_PAD_EIM_EB3__IPU_DI1_PIN16 491
524MX53_PAD_EIM_D24__EMI_WEIM_D_24 492
525MX53_PAD_EIM_D24__GPIO3_24 493
526MX53_PAD_EIM_D24__UART3_TXD_MUX 494
527MX53_PAD_EIM_D24__ECSPI1_SS2 495
528MX53_PAD_EIM_D24__CSPI_SS2 496
529MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 497
530MX53_PAD_EIM_D24__ECSPI2_SS2 498
531MX53_PAD_EIM_D24__UART1_DTR 499
532MX53_PAD_EIM_D25__EMI_WEIM_D_25 500
533MX53_PAD_EIM_D25__GPIO3_25 501
534MX53_PAD_EIM_D25__UART3_RXD_MUX 502
535MX53_PAD_EIM_D25__ECSPI1_SS3 503
536MX53_PAD_EIM_D25__CSPI_SS3 504
537MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 505
538MX53_PAD_EIM_D25__ECSPI2_SS3 506
539MX53_PAD_EIM_D25__UART1_DSR 507
540MX53_PAD_EIM_D26__EMI_WEIM_D_26 508
541MX53_PAD_EIM_D26__GPIO3_26 509
542MX53_PAD_EIM_D26__UART2_TXD_MUX 510
543MX53_PAD_EIM_D26__FIRI_RXD 511
544MX53_PAD_EIM_D26__IPU_CSI0_D_1 512
545MX53_PAD_EIM_D26__IPU_DI1_PIN11 513
546MX53_PAD_EIM_D26__IPU_SISG_2 514
547MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 515
548MX53_PAD_EIM_D27__EMI_WEIM_D_27 516
549MX53_PAD_EIM_D27__GPIO3_27 517
550MX53_PAD_EIM_D27__UART2_RXD_MUX 518
551MX53_PAD_EIM_D27__FIRI_TXD 519
552MX53_PAD_EIM_D27__IPU_CSI0_D_0 520
553MX53_PAD_EIM_D27__IPU_DI1_PIN13 521
554MX53_PAD_EIM_D27__IPU_SISG_3 522
555MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 523
556MX53_PAD_EIM_D28__EMI_WEIM_D_28 524
557MX53_PAD_EIM_D28__GPIO3_28 525
558MX53_PAD_EIM_D28__UART2_CTS 526
559MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 527
560MX53_PAD_EIM_D28__CSPI_MOSI 528
561MX53_PAD_EIM_D28__I2C1_SDA 529
562MX53_PAD_EIM_D28__IPU_EXT_TRIG 530
563MX53_PAD_EIM_D28__IPU_DI0_PIN13 531
564MX53_PAD_EIM_D29__EMI_WEIM_D_29 532
565MX53_PAD_EIM_D29__GPIO3_29 533
566MX53_PAD_EIM_D29__UART2_RTS 534
567MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 535
568MX53_PAD_EIM_D29__CSPI_SS0 536
569MX53_PAD_EIM_D29__IPU_DI1_PIN15 537
570MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 538
571MX53_PAD_EIM_D29__IPU_DI0_PIN14 539
572MX53_PAD_EIM_D30__EMI_WEIM_D_30 540
573MX53_PAD_EIM_D30__GPIO3_30 541
574MX53_PAD_EIM_D30__UART3_CTS 542
575MX53_PAD_EIM_D30__IPU_CSI0_D_3 543
576MX53_PAD_EIM_D30__IPU_DI0_PIN11 544
577MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 545
578MX53_PAD_EIM_D30__USBOH3_USBH1_OC 546
579MX53_PAD_EIM_D30__USBOH3_USBH2_OC 547
580MX53_PAD_EIM_D31__EMI_WEIM_D_31 548
581MX53_PAD_EIM_D31__GPIO3_31 549
582MX53_PAD_EIM_D31__UART3_RTS 550
583MX53_PAD_EIM_D31__IPU_CSI0_D_2 551
584MX53_PAD_EIM_D31__IPU_DI0_PIN12 552
585MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 553
586MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 554
587MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 555
588MX53_PAD_EIM_A24__EMI_WEIM_A_24 556
589MX53_PAD_EIM_A24__GPIO5_4 557
590MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 558
591MX53_PAD_EIM_A24__IPU_CSI1_D_19 559
592MX53_PAD_EIM_A24__IPU_SISG_2 560
593MX53_PAD_EIM_A24__USBPHY2_BVALID 561
594MX53_PAD_EIM_A23__EMI_WEIM_A_23 562
595MX53_PAD_EIM_A23__GPIO6_6 563
596MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 564
597MX53_PAD_EIM_A23__IPU_CSI1_D_18 565
598MX53_PAD_EIM_A23__IPU_SISG_3 566
599MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 567
600MX53_PAD_EIM_A22__EMI_WEIM_A_22 568
601MX53_PAD_EIM_A22__GPIO2_16 569
602MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 570
603MX53_PAD_EIM_A22__IPU_CSI1_D_17 571
604MX53_PAD_EIM_A22__SRC_BT_CFG1_7 572
605MX53_PAD_EIM_A21__EMI_WEIM_A_21 573
606MX53_PAD_EIM_A21__GPIO2_17 574
607MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 575
608MX53_PAD_EIM_A21__IPU_CSI1_D_16 576
609MX53_PAD_EIM_A21__SRC_BT_CFG1_6 577
610MX53_PAD_EIM_A20__EMI_WEIM_A_20 578
611MX53_PAD_EIM_A20__GPIO2_18 579
612MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 580
613MX53_PAD_EIM_A20__IPU_CSI1_D_15 581
614MX53_PAD_EIM_A20__SRC_BT_CFG1_5 582
615MX53_PAD_EIM_A19__EMI_WEIM_A_19 583
616MX53_PAD_EIM_A19__GPIO2_19 584
617MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 585
618MX53_PAD_EIM_A19__IPU_CSI1_D_14 586
619MX53_PAD_EIM_A19__SRC_BT_CFG1_4 587
620MX53_PAD_EIM_A18__EMI_WEIM_A_18 588
621MX53_PAD_EIM_A18__GPIO2_20 589
622MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 590
623MX53_PAD_EIM_A18__IPU_CSI1_D_13 591
624MX53_PAD_EIM_A18__SRC_BT_CFG1_3 592
625MX53_PAD_EIM_A17__EMI_WEIM_A_17 593
626MX53_PAD_EIM_A17__GPIO2_21 594
627MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 595
628MX53_PAD_EIM_A17__IPU_CSI1_D_12 596
629MX53_PAD_EIM_A17__SRC_BT_CFG1_2 597
630MX53_PAD_EIM_A16__EMI_WEIM_A_16 598
631MX53_PAD_EIM_A16__GPIO2_22 599
632MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 600
633MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 601
634MX53_PAD_EIM_A16__SRC_BT_CFG1_1 602
635MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 603
636MX53_PAD_EIM_CS0__GPIO2_23 604
637MX53_PAD_EIM_CS0__ECSPI2_SCLK 605
638MX53_PAD_EIM_CS0__IPU_DI1_PIN5 606
639MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 607
640MX53_PAD_EIM_CS1__GPIO2_24 608
641MX53_PAD_EIM_CS1__ECSPI2_MOSI 609
642MX53_PAD_EIM_CS1__IPU_DI1_PIN6 610
643MX53_PAD_EIM_OE__EMI_WEIM_OE 611
644MX53_PAD_EIM_OE__GPIO2_25 612
645MX53_PAD_EIM_OE__ECSPI2_MISO 613
646MX53_PAD_EIM_OE__IPU_DI1_PIN7 614
647MX53_PAD_EIM_OE__USBPHY2_IDDIG 615
648MX53_PAD_EIM_RW__EMI_WEIM_RW 616
649MX53_PAD_EIM_RW__GPIO2_26 617
650MX53_PAD_EIM_RW__ECSPI2_SS0 618
651MX53_PAD_EIM_RW__IPU_DI1_PIN8 619
652MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 620
653MX53_PAD_EIM_LBA__EMI_WEIM_LBA 621
654MX53_PAD_EIM_LBA__GPIO2_27 622
655MX53_PAD_EIM_LBA__ECSPI2_SS1 623
656MX53_PAD_EIM_LBA__IPU_DI1_PIN17 624
657MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 625
658MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 626
659MX53_PAD_EIM_EB0__GPIO2_28 627
660MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 628
661MX53_PAD_EIM_EB0__IPU_CSI1_D_11 629
662MX53_PAD_EIM_EB0__GPC_PMIC_RDY 630
663MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 631
664MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 632
665MX53_PAD_EIM_EB1__GPIO2_29 633
666MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 634
667MX53_PAD_EIM_EB1__IPU_CSI1_D_10 635
668MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 636
669MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 637
670MX53_PAD_EIM_DA0__GPIO3_0 638
671MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 639
672MX53_PAD_EIM_DA0__IPU_CSI1_D_9 640
673MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 641
674MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 642
675MX53_PAD_EIM_DA1__GPIO3_1 643
676MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 644
677MX53_PAD_EIM_DA1__IPU_CSI1_D_8 645
678MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 646
679MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 647
680MX53_PAD_EIM_DA2__GPIO3_2 648
681MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 649
682MX53_PAD_EIM_DA2__IPU_CSI1_D_7 650
683MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 651
684MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 652
685MX53_PAD_EIM_DA3__GPIO3_3 653
686MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 654
687MX53_PAD_EIM_DA3__IPU_CSI1_D_6 655
688MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 656
689MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 657
690MX53_PAD_EIM_DA4__GPIO3_4 658
691MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 659
692MX53_PAD_EIM_DA4__IPU_CSI1_D_5 660
693MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 661
694MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 662
695MX53_PAD_EIM_DA5__GPIO3_5 663
696MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 664
697MX53_PAD_EIM_DA5__IPU_CSI1_D_4 665
698MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 666
699MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 667
700MX53_PAD_EIM_DA6__GPIO3_6 668
701MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 669
702MX53_PAD_EIM_DA6__IPU_CSI1_D_3 670
703MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 671
704MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 672
705MX53_PAD_EIM_DA7__GPIO3_7 673
706MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 674
707MX53_PAD_EIM_DA7__IPU_CSI1_D_2 675
708MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 676
709MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 677
710MX53_PAD_EIM_DA8__GPIO3_8 678
711MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 679
712MX53_PAD_EIM_DA8__IPU_CSI1_D_1 680
713MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 681
714MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 682
715MX53_PAD_EIM_DA9__GPIO3_9 683
716MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 684
717MX53_PAD_EIM_DA9__IPU_CSI1_D_0 685
718MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 686
719MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 687
720MX53_PAD_EIM_DA10__GPIO3_10 688
721MX53_PAD_EIM_DA10__IPU_DI1_PIN15 689
722MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 690
723MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 691
724MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 692
725MX53_PAD_EIM_DA11__GPIO3_11 693
726MX53_PAD_EIM_DA11__IPU_DI1_PIN2 694
727MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 695
728MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 696
729MX53_PAD_EIM_DA12__GPIO3_12 697
730MX53_PAD_EIM_DA12__IPU_DI1_PIN3 698
731MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 699
732MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 700
733MX53_PAD_EIM_DA13__GPIO3_13 701
734MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 702
735MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 703
736MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 704
737MX53_PAD_EIM_DA14__GPIO3_14 705
738MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 706
739MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 707
740MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 708
741MX53_PAD_EIM_DA15__GPIO3_15 709
742MX53_PAD_EIM_DA15__IPU_DI1_PIN1 710
743MX53_PAD_EIM_DA15__IPU_DI1_PIN4 711
744MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 712
745MX53_PAD_NANDF_WE_B__GPIO6_12 713
746MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 714
747MX53_PAD_NANDF_RE_B__GPIO6_13 715
748MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 716
749MX53_PAD_EIM_WAIT__GPIO5_0 717
750MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 718
751MX53_PAD_LVDS1_TX3_P__GPIO6_22 719
752MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 720
753MX53_PAD_LVDS1_TX2_P__GPIO6_24 721
754MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 722
755MX53_PAD_LVDS1_CLK_P__GPIO6_26 723
756MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 724
757MX53_PAD_LVDS1_TX1_P__GPIO6_28 725
758MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 726
759MX53_PAD_LVDS1_TX0_P__GPIO6_30 727
760MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 728
761MX53_PAD_LVDS0_TX3_P__GPIO7_22 729
762MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 730
763MX53_PAD_LVDS0_CLK_P__GPIO7_24 731
764MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 732
765MX53_PAD_LVDS0_TX2_P__GPIO7_26 733
766MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 734
767MX53_PAD_LVDS0_TX1_P__GPIO7_28 735
768MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 736
769MX53_PAD_LVDS0_TX0_P__GPIO7_30 737
770MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 738
771MX53_PAD_GPIO_10__GPIO4_0 739
772MX53_PAD_GPIO_10__OSC32k_32K_OUT 740
773MX53_PAD_GPIO_11__GPIO4_1 741
774MX53_PAD_GPIO_12__GPIO4_2 742
775MX53_PAD_GPIO_13__GPIO4_3 743
776MX53_PAD_GPIO_14__GPIO4_4 744
777MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 745
778MX53_PAD_NANDF_CLE__GPIO6_7 746
779MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 747
780MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 748
781MX53_PAD_NANDF_ALE__GPIO6_8 749
782MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 750
783MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 751
784MX53_PAD_NANDF_WP_B__GPIO6_9 752
785MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 753
786MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 754
787MX53_PAD_NANDF_RB0__GPIO6_10 755
788MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 756
789MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 757
790MX53_PAD_NANDF_CS0__GPIO6_11 758
791MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 759
792MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 760
793MX53_PAD_NANDF_CS1__GPIO6_14 761
794MX53_PAD_NANDF_CS1__MLB_MLBCLK 762
795MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 763
796MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 764
797MX53_PAD_NANDF_CS2__GPIO6_15 765
798MX53_PAD_NANDF_CS2__IPU_SISG_0 766
799MX53_PAD_NANDF_CS2__ESAI1_TX0 767
800MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 768
801MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 769
802MX53_PAD_NANDF_CS2__MLB_MLBSIG 770
803MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 771
804MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 772
805MX53_PAD_NANDF_CS3__GPIO6_16 773
806MX53_PAD_NANDF_CS3__IPU_SISG_1 774
807MX53_PAD_NANDF_CS3__ESAI1_TX1 775
808MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 776
809MX53_PAD_NANDF_CS3__MLB_MLBDAT 777
810MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 778
811MX53_PAD_FEC_MDIO__FEC_MDIO 779
812MX53_PAD_FEC_MDIO__GPIO1_22 780
813MX53_PAD_FEC_MDIO__ESAI1_SCKR 781
814MX53_PAD_FEC_MDIO__FEC_COL 782
815MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 783
816MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 784
817MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 785
818MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 786
819MX53_PAD_FEC_REF_CLK__GPIO1_23 787
820MX53_PAD_FEC_REF_CLK__ESAI1_FSR 788
821MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 789
822MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 790
823MX53_PAD_FEC_RX_ER__FEC_RX_ER 791
824MX53_PAD_FEC_RX_ER__GPIO1_24 792
825MX53_PAD_FEC_RX_ER__ESAI1_HCKR 793
826MX53_PAD_FEC_RX_ER__FEC_RX_CLK 794
827MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 795
828MX53_PAD_FEC_CRS_DV__FEC_RX_DV 796
829MX53_PAD_FEC_CRS_DV__GPIO1_25 797
830MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 798
831MX53_PAD_FEC_RXD1__FEC_RDATA_1 799
832MX53_PAD_FEC_RXD1__GPIO1_26 800
833MX53_PAD_FEC_RXD1__ESAI1_FST 801
834MX53_PAD_FEC_RXD1__MLB_MLBSIG 802
835MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 803
836MX53_PAD_FEC_RXD0__FEC_RDATA_0 804
837MX53_PAD_FEC_RXD0__GPIO1_27 805
838MX53_PAD_FEC_RXD0__ESAI1_HCKT 806
839MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 807
840MX53_PAD_FEC_TX_EN__FEC_TX_EN 808
841MX53_PAD_FEC_TX_EN__GPIO1_28 809
842MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 810
843MX53_PAD_FEC_TXD1__FEC_TDATA_1 811
844MX53_PAD_FEC_TXD1__GPIO1_29 812
845MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 813
846MX53_PAD_FEC_TXD1__MLB_MLBCLK 814
847MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 815
848MX53_PAD_FEC_TXD0__FEC_TDATA_0 816
849MX53_PAD_FEC_TXD0__GPIO1_30 817
850MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 818
851MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 819
852MX53_PAD_FEC_MDC__FEC_MDC 820
853MX53_PAD_FEC_MDC__GPIO1_31 821
854MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 822
855MX53_PAD_FEC_MDC__MLB_MLBDAT 823
856MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 824
857MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 825
858MX53_PAD_PATA_DIOW__PATA_DIOW 826
859MX53_PAD_PATA_DIOW__GPIO6_17 827
860MX53_PAD_PATA_DIOW__UART1_TXD_MUX 828
861MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 829
862MX53_PAD_PATA_DMACK__PATA_DMACK 830
863MX53_PAD_PATA_DMACK__GPIO6_18 831
864MX53_PAD_PATA_DMACK__UART1_RXD_MUX 832
865MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 833
866MX53_PAD_PATA_DMARQ__PATA_DMARQ 834
867MX53_PAD_PATA_DMARQ__GPIO7_0 835
868MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 836
869MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 837
870MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 838
871MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 839
872MX53_PAD_PATA_BUFFER_EN__GPIO7_1 840
873MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 841
874MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 842
875MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 843
876MX53_PAD_PATA_INTRQ__PATA_INTRQ 844
877MX53_PAD_PATA_INTRQ__GPIO7_2 845
878MX53_PAD_PATA_INTRQ__UART2_CTS 846
879MX53_PAD_PATA_INTRQ__CAN1_TXCAN 847
880MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 848
881MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 849
882MX53_PAD_PATA_DIOR__PATA_DIOR 850
883MX53_PAD_PATA_DIOR__GPIO7_3 851
884MX53_PAD_PATA_DIOR__UART2_RTS 852
885MX53_PAD_PATA_DIOR__CAN1_RXCAN 853
886MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 854
887MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 855
888MX53_PAD_PATA_RESET_B__GPIO7_4 856
889MX53_PAD_PATA_RESET_B__ESDHC3_CMD 857
890MX53_PAD_PATA_RESET_B__UART1_CTS 858
891MX53_PAD_PATA_RESET_B__CAN2_TXCAN 859
892MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 860
893MX53_PAD_PATA_IORDY__PATA_IORDY 861
894MX53_PAD_PATA_IORDY__GPIO7_5 862
895MX53_PAD_PATA_IORDY__ESDHC3_CLK 863
896MX53_PAD_PATA_IORDY__UART1_RTS 864
897MX53_PAD_PATA_IORDY__CAN2_RXCAN 865
898MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 866
899MX53_PAD_PATA_DA_0__PATA_DA_0 867
900MX53_PAD_PATA_DA_0__GPIO7_6 868
901MX53_PAD_PATA_DA_0__ESDHC3_RST 869
902MX53_PAD_PATA_DA_0__OWIRE_LINE 870
903MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 871
904MX53_PAD_PATA_DA_1__PATA_DA_1 872
905MX53_PAD_PATA_DA_1__GPIO7_7 873
906MX53_PAD_PATA_DA_1__ESDHC4_CMD 874
907MX53_PAD_PATA_DA_1__UART3_CTS 875
908MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 876
909MX53_PAD_PATA_DA_2__PATA_DA_2 877
910MX53_PAD_PATA_DA_2__GPIO7_8 878
911MX53_PAD_PATA_DA_2__ESDHC4_CLK 879
912MX53_PAD_PATA_DA_2__UART3_RTS 880
913MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 881
914MX53_PAD_PATA_CS_0__PATA_CS_0 882
915MX53_PAD_PATA_CS_0__GPIO7_9 883
916MX53_PAD_PATA_CS_0__UART3_TXD_MUX 884
917MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 885
918MX53_PAD_PATA_CS_1__PATA_CS_1 886
919MX53_PAD_PATA_CS_1__GPIO7_10 887
920MX53_PAD_PATA_CS_1__UART3_RXD_MUX 888
921MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 889
922MX53_PAD_PATA_DATA0__PATA_DATA_0 890
923MX53_PAD_PATA_DATA0__GPIO2_0 891
924MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 892
925MX53_PAD_PATA_DATA0__ESDHC3_DAT4 893
926MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 894
927MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 895
928MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 896
929MX53_PAD_PATA_DATA1__PATA_DATA_1 897
930MX53_PAD_PATA_DATA1__GPIO2_1 898
931MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 899
932MX53_PAD_PATA_DATA1__ESDHC3_DAT5 900
933MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 901
934MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 902
935MX53_PAD_PATA_DATA2__PATA_DATA_2 903
936MX53_PAD_PATA_DATA2__GPIO2_2 904
937MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 905
938MX53_PAD_PATA_DATA2__ESDHC3_DAT6 906
939MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 907
940MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 908
941MX53_PAD_PATA_DATA3__PATA_DATA_3 909
942MX53_PAD_PATA_DATA3__GPIO2_3 910
943MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 911
944MX53_PAD_PATA_DATA3__ESDHC3_DAT7 912
945MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 913
946MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 914
947MX53_PAD_PATA_DATA4__PATA_DATA_4 915
948MX53_PAD_PATA_DATA4__GPIO2_4 916
949MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 917
950MX53_PAD_PATA_DATA4__ESDHC4_DAT4 918
951MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 919
952MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 920
953MX53_PAD_PATA_DATA5__PATA_DATA_5 921
954MX53_PAD_PATA_DATA5__GPIO2_5 922
955MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 923
956MX53_PAD_PATA_DATA5__ESDHC4_DAT5 924
957MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 925
958MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 926
959MX53_PAD_PATA_DATA6__PATA_DATA_6 927
960MX53_PAD_PATA_DATA6__GPIO2_6 928
961MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 929
962MX53_PAD_PATA_DATA6__ESDHC4_DAT6 930
963MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 931
964MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 932
965MX53_PAD_PATA_DATA7__PATA_DATA_7 933
966MX53_PAD_PATA_DATA7__GPIO2_7 934
967MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 935
968MX53_PAD_PATA_DATA7__ESDHC4_DAT7 936
969MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 937
970MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 938
971MX53_PAD_PATA_DATA8__PATA_DATA_8 939
972MX53_PAD_PATA_DATA8__GPIO2_8 940
973MX53_PAD_PATA_DATA8__ESDHC1_DAT4 941
974MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 942
975MX53_PAD_PATA_DATA8__ESDHC3_DAT0 943
976MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 944
977MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 945
978MX53_PAD_PATA_DATA9__PATA_DATA_9 946
979MX53_PAD_PATA_DATA9__GPIO2_9 947
980MX53_PAD_PATA_DATA9__ESDHC1_DAT5 948
981MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 949
982MX53_PAD_PATA_DATA9__ESDHC3_DAT1 950
983MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 951
984MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 952
985MX53_PAD_PATA_DATA10__PATA_DATA_10 953
986MX53_PAD_PATA_DATA10__GPIO2_10 954
987MX53_PAD_PATA_DATA10__ESDHC1_DAT6 955
988MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 956
989MX53_PAD_PATA_DATA10__ESDHC3_DAT2 957
990MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 958
991MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 959
992MX53_PAD_PATA_DATA11__PATA_DATA_11 960
993MX53_PAD_PATA_DATA11__GPIO2_11 961
994MX53_PAD_PATA_DATA11__ESDHC1_DAT7 962
995MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 963
996MX53_PAD_PATA_DATA11__ESDHC3_DAT3 964
997MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 965
998MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 966
999MX53_PAD_PATA_DATA12__PATA_DATA_12 967
1000MX53_PAD_PATA_DATA12__GPIO2_12 968
1001MX53_PAD_PATA_DATA12__ESDHC2_DAT4 969
1002MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 970
1003MX53_PAD_PATA_DATA12__ESDHC4_DAT0 971
1004MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 972
1005MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 973
1006MX53_PAD_PATA_DATA13__PATA_DATA_13 974
1007MX53_PAD_PATA_DATA13__GPIO2_13 975
1008MX53_PAD_PATA_DATA13__ESDHC2_DAT5 976
1009MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 977
1010MX53_PAD_PATA_DATA13__ESDHC4_DAT1 978
1011MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 979
1012MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 980
1013MX53_PAD_PATA_DATA14__PATA_DATA_14 981
1014MX53_PAD_PATA_DATA14__GPIO2_14 982
1015MX53_PAD_PATA_DATA14__ESDHC2_DAT6 983
1016MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 984
1017MX53_PAD_PATA_DATA14__ESDHC4_DAT2 985
1018MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 986
1019MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 987
1020MX53_PAD_PATA_DATA15__PATA_DATA_15 988
1021MX53_PAD_PATA_DATA15__GPIO2_15 989
1022MX53_PAD_PATA_DATA15__ESDHC2_DAT7 990
1023MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 991
1024MX53_PAD_PATA_DATA15__ESDHC4_DAT3 992
1025MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 993
1026MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 994
1027MX53_PAD_SD1_DATA0__ESDHC1_DAT0 995
1028MX53_PAD_SD1_DATA0__GPIO1_16 996
1029MX53_PAD_SD1_DATA0__GPT_CAPIN1 997
1030MX53_PAD_SD1_DATA0__CSPI_MISO 998
1031MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 999
1032MX53_PAD_SD1_DATA1__ESDHC1_DAT1 1000
1033MX53_PAD_SD1_DATA1__GPIO1_17 1001
1034MX53_PAD_SD1_DATA1__GPT_CAPIN2 1002
1035MX53_PAD_SD1_DATA1__CSPI_SS0 1003
1036MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 1004
1037MX53_PAD_SD1_CMD__ESDHC1_CMD 1005
1038MX53_PAD_SD1_CMD__GPIO1_18 1006
1039MX53_PAD_SD1_CMD__GPT_CMPOUT1 1007
1040MX53_PAD_SD1_CMD__CSPI_MOSI 1008
1041MX53_PAD_SD1_CMD__CCM_PLL1_BYP 1009
1042MX53_PAD_SD1_DATA2__ESDHC1_DAT2 1010
1043MX53_PAD_SD1_DATA2__GPIO1_19 1011
1044MX53_PAD_SD1_DATA2__GPT_CMPOUT2 1012
1045MX53_PAD_SD1_DATA2__PWM2_PWMO 1013
1046MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 1014
1047MX53_PAD_SD1_DATA2__CSPI_SS1 1015
1048MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 1016
1049MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 1017
1050MX53_PAD_SD1_CLK__ESDHC1_CLK 1018
1051MX53_PAD_SD1_CLK__GPIO1_20 1019
1052MX53_PAD_SD1_CLK__OSC32k_32K_OUT 1020
1053MX53_PAD_SD1_CLK__GPT_CLKIN 1021
1054MX53_PAD_SD1_CLK__CSPI_SCLK 1022
1055MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 1023
1056MX53_PAD_SD1_DATA3__ESDHC1_DAT3 1024
1057MX53_PAD_SD1_DATA3__GPIO1_21 1025
1058MX53_PAD_SD1_DATA3__GPT_CMPOUT3 1026
1059MX53_PAD_SD1_DATA3__PWM1_PWMO 1027
1060MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 1028
1061MX53_PAD_SD1_DATA3__CSPI_SS2 1029
1062MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 1030
1063MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 1031
1064MX53_PAD_SD2_CLK__ESDHC2_CLK 1032
1065MX53_PAD_SD2_CLK__GPIO1_10 1033
1066MX53_PAD_SD2_CLK__KPP_COL_5 1034
1067MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1035
1068MX53_PAD_SD2_CLK__CSPI_SCLK 1036
1069MX53_PAD_SD2_CLK__SCC_RANDOM_V 1037
1070MX53_PAD_SD2_CMD__ESDHC2_CMD 1038
1071MX53_PAD_SD2_CMD__GPIO1_11 1039
1072MX53_PAD_SD2_CMD__KPP_ROW_5 1040
1073MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1041
1074MX53_PAD_SD2_CMD__CSPI_MOSI 1042
1075MX53_PAD_SD2_CMD__SCC_RANDOM 1043
1076MX53_PAD_SD2_DATA3__ESDHC2_DAT3 1044
1077MX53_PAD_SD2_DATA3__GPIO1_12 1045
1078MX53_PAD_SD2_DATA3__KPP_COL_6 1046
1079MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 1047
1080MX53_PAD_SD2_DATA3__CSPI_SS2 1048
1081MX53_PAD_SD2_DATA3__SJC_DONE 1049
1082MX53_PAD_SD2_DATA2__ESDHC2_DAT2 1050
1083MX53_PAD_SD2_DATA2__GPIO1_13 1051
1084MX53_PAD_SD2_DATA2__KPP_ROW_6 1052
1085MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 1053
1086MX53_PAD_SD2_DATA2__CSPI_SS1 1054
1087MX53_PAD_SD2_DATA2__SJC_FAIL 1055
1088MX53_PAD_SD2_DATA1__ESDHC2_DAT1 1056
1089MX53_PAD_SD2_DATA1__GPIO1_14 1057
1090MX53_PAD_SD2_DATA1__KPP_COL_7 1058
1091MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 1059
1092MX53_PAD_SD2_DATA1__CSPI_SS0 1060
1093MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 1061
1094MX53_PAD_SD2_DATA0__ESDHC2_DAT0 1062
1095MX53_PAD_SD2_DATA0__GPIO1_15 1063
1096MX53_PAD_SD2_DATA0__KPP_ROW_7 1064
1097MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 1065
1098MX53_PAD_SD2_DATA0__CSPI_MISO 1066
1099MX53_PAD_SD2_DATA0__RTIC_DONE_INT 1067
1100MX53_PAD_GPIO_0__CCM_CLKO 1068
1101MX53_PAD_GPIO_0__GPIO1_0 1069
1102MX53_PAD_GPIO_0__KPP_COL_5 1070
1103MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 1071
1104MX53_PAD_GPIO_0__EPIT1_EPITO 1072
1105MX53_PAD_GPIO_0__SRTC_ALARM_DEB 1073
1106MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 1074
1107MX53_PAD_GPIO_0__CSU_TD 1075
1108MX53_PAD_GPIO_1__ESAI1_SCKR 1076
1109MX53_PAD_GPIO_1__GPIO1_1 1077
1110MX53_PAD_GPIO_1__KPP_ROW_5 1078
1111MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 1079
1112MX53_PAD_GPIO_1__PWM2_PWMO 1080
1113MX53_PAD_GPIO_1__WDOG2_WDOG_B 1081
1114MX53_PAD_GPIO_1__ESDHC1_CD 1082
1115MX53_PAD_GPIO_1__SRC_TESTER_ACK 1083
1116MX53_PAD_GPIO_9__ESAI1_FSR 1084
1117MX53_PAD_GPIO_9__GPIO1_9 1085
1118MX53_PAD_GPIO_9__KPP_COL_6 1086
1119MX53_PAD_GPIO_9__CCM_REF_EN_B 1087
1120MX53_PAD_GPIO_9__PWM1_PWMO 1088
1121MX53_PAD_GPIO_9__WDOG1_WDOG_B 1089
1122MX53_PAD_GPIO_9__ESDHC1_WP 1090
1123MX53_PAD_GPIO_9__SCC_FAIL_STATE 1091
1124MX53_PAD_GPIO_3__ESAI1_HCKR 1092
1125MX53_PAD_GPIO_3__GPIO1_3 1093
1126MX53_PAD_GPIO_3__I2C3_SCL 1094
1127MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 1095
1128MX53_PAD_GPIO_3__CCM_CLKO2 1096
1129MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 1097
1130MX53_PAD_GPIO_3__USBOH3_USBH1_OC 1098
1131MX53_PAD_GPIO_3__MLB_MLBCLK 1099
1132MX53_PAD_GPIO_6__ESAI1_SCKT 1100
1133MX53_PAD_GPIO_6__GPIO1_6 1101
1134MX53_PAD_GPIO_6__I2C3_SDA 1102
1135MX53_PAD_GPIO_6__CCM_CCM_OUT_0 1103
1136MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 1104
1137MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 1105
1138MX53_PAD_GPIO_6__ESDHC2_LCTL 1106
1139MX53_PAD_GPIO_6__MLB_MLBSIG 1107
1140MX53_PAD_GPIO_2__ESAI1_FST 1108
1141MX53_PAD_GPIO_2__GPIO1_2 1109
1142MX53_PAD_GPIO_2__KPP_ROW_6 1110
1143MX53_PAD_GPIO_2__CCM_CCM_OUT_1 1111
1144MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 1112
1145MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 1113
1146MX53_PAD_GPIO_2__ESDHC2_WP 1114
1147MX53_PAD_GPIO_2__MLB_MLBDAT 1115
1148MX53_PAD_GPIO_4__ESAI1_HCKT 1116
1149MX53_PAD_GPIO_4__GPIO1_4 1117
1150MX53_PAD_GPIO_4__KPP_COL_7 1118
1151MX53_PAD_GPIO_4__CCM_CCM_OUT_2 1119
1152MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1120
1153MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 1121
1154MX53_PAD_GPIO_4__ESDHC2_CD 1122
1155MX53_PAD_GPIO_4__SCC_SEC_STATE 1123
1156MX53_PAD_GPIO_5__ESAI1_TX2_RX3 1124
1157MX53_PAD_GPIO_5__GPIO1_5 1125
1158MX53_PAD_GPIO_5__KPP_ROW_7 1126
1159MX53_PAD_GPIO_5__CCM_CLKO 1127
1160MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1128
1161MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 1129
1162MX53_PAD_GPIO_5__I2C3_SCL 1130
1163MX53_PAD_GPIO_5__CCM_PLL1_BYP 1131
1164MX53_PAD_GPIO_7__ESAI1_TX4_RX1 1132
1165MX53_PAD_GPIO_7__GPIO1_7 1133
1166MX53_PAD_GPIO_7__EPIT1_EPITO 1134
1167MX53_PAD_GPIO_7__CAN1_TXCAN 1135
1168MX53_PAD_GPIO_7__UART2_TXD_MUX 1136
1169MX53_PAD_GPIO_7__FIRI_RXD 1137
1170MX53_PAD_GPIO_7__SPDIF_PLOCK 1138
1171MX53_PAD_GPIO_7__CCM_PLL2_BYP 1139
1172MX53_PAD_GPIO_8__ESAI1_TX5_RX0 1140
1173MX53_PAD_GPIO_8__GPIO1_8 1141
1174MX53_PAD_GPIO_8__EPIT2_EPITO 1142
1175MX53_PAD_GPIO_8__CAN1_RXCAN 1143
1176MX53_PAD_GPIO_8__UART2_RXD_MUX 1144
1177MX53_PAD_GPIO_8__FIRI_TXD 1145
1178MX53_PAD_GPIO_8__SPDIF_SRCLK 1146
1179MX53_PAD_GPIO_8__CCM_PLL3_BYP 1147
1180MX53_PAD_GPIO_16__ESAI1_TX3_RX2 1148
1181MX53_PAD_GPIO_16__GPIO7_11 1149
1182MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 1150
1183MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 1151
1184MX53_PAD_GPIO_16__SPDIF_IN1 1152
1185MX53_PAD_GPIO_16__I2C3_SDA 1153
1186MX53_PAD_GPIO_16__SJC_DE_B 1154
1187MX53_PAD_GPIO_17__ESAI1_TX0 1155
1188MX53_PAD_GPIO_17__GPIO7_12 1156
1189MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 1157
1190MX53_PAD_GPIO_17__GPC_PMIC_RDY 1158
1191MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 1159
1192MX53_PAD_GPIO_17__SPDIF_OUT1 1160
1193MX53_PAD_GPIO_17__IPU_SNOOP2 1161
1194MX53_PAD_GPIO_17__SJC_JTAG_ACT 1162
1195MX53_PAD_GPIO_18__ESAI1_TX1 1163
1196MX53_PAD_GPIO_18__GPIO7_13 1164
1197MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 1165
1198MX53_PAD_GPIO_18__OWIRE_LINE 1166
1199MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 1167
1200MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 1168
1201MX53_PAD_GPIO_18__ESDHC1_LCTL 1169
1202MX53_PAD_GPIO_18__SRC_SYSTEM_RST 1170
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt
new file mode 100644
index 000000000000..0ac5bee87505
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt
@@ -0,0 +1,38 @@
1* Freescale IMX6 DualLite/Solo IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx6dl-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_HYS (1 << 16)
16PAD_CTL_PUS_100K_DOWN (0 << 14)
17PAD_CTL_PUS_47K_UP (1 << 14)
18PAD_CTL_PUS_100K_UP (2 << 14)
19PAD_CTL_PUS_22K_UP (3 << 14)
20PAD_CTL_PUE (1 << 13)
21PAD_CTL_PKE (1 << 12)
22PAD_CTL_ODE (1 << 11)
23PAD_CTL_SPEED_LOW (1 << 6)
24PAD_CTL_SPEED_MED (2 << 6)
25PAD_CTL_SPEED_HIGH (3 << 6)
26PAD_CTL_DSE_DISABLE (0 << 3)
27PAD_CTL_DSE_240ohm (1 << 3)
28PAD_CTL_DSE_120ohm (2 << 3)
29PAD_CTL_DSE_80ohm (3 << 3)
30PAD_CTL_DSE_60ohm (4 << 3)
31PAD_CTL_DSE_48ohm (5 << 3)
32PAD_CTL_DSE_40ohm (6 << 3)
33PAD_CTL_DSE_34ohm (7 << 3)
34PAD_CTL_SRE_FAST (1 << 0)
35PAD_CTL_SRE_SLOW (0 << 0)
36
37Refer to imx6dl-pinfunc.h in device tree source folder for all available
38imx6dl PIN_FUNC_ID.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
index a4119f6422d9..546610cf2ae7 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
@@ -34,1597 +34,5 @@ PAD_CTL_DSE_34ohm (7 << 3)
34PAD_CTL_SRE_FAST (1 << 0) 34PAD_CTL_SRE_FAST (1 << 0)
35PAD_CTL_SRE_SLOW (0 << 0) 35PAD_CTL_SRE_SLOW (0 << 0)
36 36
37See below for available PIN_FUNC_ID for imx6q: 37Refer to imx6q-pinfunc.h in device tree source folder for all available
38MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0 38imx6q PIN_FUNC_ID.
39MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1
40MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2
41MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3
42MX6Q_PAD_SD2_DAT1__KPP_COL_7 4
43MX6Q_PAD_SD2_DAT1__GPIO_1_14 5
44MX6Q_PAD_SD2_DAT1__CCM_WAIT 6
45MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7
46MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8
47MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9
48MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10
49MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11
50MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12
51MX6Q_PAD_SD2_DAT2__GPIO_1_13 13
52MX6Q_PAD_SD2_DAT2__CCM_STOP 14
53MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15
54MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16
55MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17
56MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18
57MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19
58MX6Q_PAD_SD2_DAT0__GPIO_1_15 20
59MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21
60MX6Q_PAD_SD2_DAT0__TESTO_2 22
61MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23
62MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24
63MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25
64MX6Q_PAD_RGMII_TXC__GPIO_6_19 26
65MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27
66MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28
67MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29
68MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30
69MX6Q_PAD_RGMII_TD0__GPIO_6_20 31
70MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32
71MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33
72MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34
73MX6Q_PAD_RGMII_TD1__GPIO_6_21 35
74MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36
75MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37
76MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38
77MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39
78MX6Q_PAD_RGMII_TD2__GPIO_6_22 40
79MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41
80MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42
81MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43
82MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44
83MX6Q_PAD_RGMII_TD3__GPIO_6_23 45
84MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46
85MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47
86MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48
87MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49
88MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50
89MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51
90MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52
91MX6Q_PAD_RGMII_RD0__GPIO_6_25 53
92MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54
93MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55
94MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56
95MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57
96MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58
97MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59
98MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60
99MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61
100MX6Q_PAD_RGMII_RD1__GPIO_6_27 62
101MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63
102MX6Q_PAD_RGMII_RD1__SJC_FAIL 64
103MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65
104MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66
105MX6Q_PAD_RGMII_RD2__GPIO_6_28 67
106MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68
107MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69
108MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70
109MX6Q_PAD_RGMII_RD3__GPIO_6_29 71
110MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72
111MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73
112MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74
113MX6Q_PAD_RGMII_RXC__GPIO_6_30 75
114MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76
115MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77
116MX6Q_PAD_EIM_A25__ECSPI4_SS1 78
117MX6Q_PAD_EIM_A25__ECSPI2_RDY 79
118MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80
119MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81
120MX6Q_PAD_EIM_A25__GPIO_5_2 82
121MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83
122MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84
123MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85
124MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86
125MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87
126MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88
127MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89
128MX6Q_PAD_EIM_EB2__GPIO_2_30 90
129MX6Q_PAD_EIM_EB2__I2C2_SCL 91
130MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92
131MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93
132MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94
133MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95
134MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96
135MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97
136MX6Q_PAD_EIM_D16__GPIO_3_16 98
137MX6Q_PAD_EIM_D16__I2C2_SDA 99
138MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100
139MX6Q_PAD_EIM_D17__ECSPI1_MISO 101
140MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102
141MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103
142MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104
143MX6Q_PAD_EIM_D17__GPIO_3_17 105
144MX6Q_PAD_EIM_D17__I2C3_SCL 106
145MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107
146MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108
147MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109
148MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110
149MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111
150MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112
151MX6Q_PAD_EIM_D18__GPIO_3_18 113
152MX6Q_PAD_EIM_D18__I2C3_SDA 114
153MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115
154MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116
155MX6Q_PAD_EIM_D19__ECSPI1_SS1 117
156MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118
157MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119
158MX6Q_PAD_EIM_D19__UART1_CTS 120
159MX6Q_PAD_EIM_D19__GPIO_3_19 121
160MX6Q_PAD_EIM_D19__EPIT1_EPITO 122
161MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123
162MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124
163MX6Q_PAD_EIM_D20__ECSPI4_SS0 125
164MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126
165MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127
166MX6Q_PAD_EIM_D20__UART1_RTS 128
167MX6Q_PAD_EIM_D20__GPIO_3_20 129
168MX6Q_PAD_EIM_D20__EPIT2_EPITO 130
169MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131
170MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132
171MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133
172MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134
173MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135
174MX6Q_PAD_EIM_D21__GPIO_3_21 136
175MX6Q_PAD_EIM_D21__I2C1_SCL 137
176MX6Q_PAD_EIM_D21__SPDIF_IN1 138
177MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139
178MX6Q_PAD_EIM_D22__ECSPI4_MISO 140
179MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141
180MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142
181MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143
182MX6Q_PAD_EIM_D22__GPIO_3_22 144
183MX6Q_PAD_EIM_D22__SPDIF_OUT1 145
184MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146
185MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147
186MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148
187MX6Q_PAD_EIM_D23__UART3_CTS 149
188MX6Q_PAD_EIM_D23__UART1_DCD 150
189MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151
190MX6Q_PAD_EIM_D23__GPIO_3_23 152
191MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153
192MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154
193MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155
194MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156
195MX6Q_PAD_EIM_EB3__UART3_RTS 157
196MX6Q_PAD_EIM_EB3__UART1_RI 158
197MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159
198MX6Q_PAD_EIM_EB3__GPIO_2_31 160
199MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161
200MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162
201MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163
202MX6Q_PAD_EIM_D24__ECSPI4_SS2 164
203MX6Q_PAD_EIM_D24__UART3_TXD 165
204MX6Q_PAD_EIM_D24__ECSPI1_SS2 166
205MX6Q_PAD_EIM_D24__ECSPI2_SS2 167
206MX6Q_PAD_EIM_D24__GPIO_3_24 168
207MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169
208MX6Q_PAD_EIM_D24__UART1_DTR 170
209MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171
210MX6Q_PAD_EIM_D25__ECSPI4_SS3 172
211MX6Q_PAD_EIM_D25__UART3_RXD 173
212MX6Q_PAD_EIM_D25__ECSPI1_SS3 174
213MX6Q_PAD_EIM_D25__ECSPI2_SS3 175
214MX6Q_PAD_EIM_D25__GPIO_3_25 176
215MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177
216MX6Q_PAD_EIM_D25__UART1_DSR 178
217MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179
218MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180
219MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181
220MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182
221MX6Q_PAD_EIM_D26__UART2_TXD 183
222MX6Q_PAD_EIM_D26__GPIO_3_26 184
223MX6Q_PAD_EIM_D26__IPU1_SISG_2 185
224MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186
225MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187
226MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188
227MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189
228MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190
229MX6Q_PAD_EIM_D27__UART2_RXD 191
230MX6Q_PAD_EIM_D27__GPIO_3_27 192
231MX6Q_PAD_EIM_D27__IPU1_SISG_3 193
232MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194
233MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195
234MX6Q_PAD_EIM_D28__I2C1_SDA 196
235MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197
236MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198
237MX6Q_PAD_EIM_D28__UART2_CTS 199
238MX6Q_PAD_EIM_D28__GPIO_3_28 200
239MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201
240MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202
241MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203
242MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204
243MX6Q_PAD_EIM_D29__ECSPI4_SS0 205
244MX6Q_PAD_EIM_D29__UART2_RTS 206
245MX6Q_PAD_EIM_D29__GPIO_3_29 207
246MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208
247MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209
248MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210
249MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211
250MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212
251MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213
252MX6Q_PAD_EIM_D30__UART3_CTS 214
253MX6Q_PAD_EIM_D30__GPIO_3_30 215
254MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216
255MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217
256MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218
257MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219
258MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220
259MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221
260MX6Q_PAD_EIM_D31__UART3_RTS 222
261MX6Q_PAD_EIM_D31__GPIO_3_31 223
262MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224
263MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225
264MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226
265MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227
266MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228
267MX6Q_PAD_EIM_A24__IPU2_SISG_2 229
268MX6Q_PAD_EIM_A24__IPU1_SISG_2 230
269MX6Q_PAD_EIM_A24__GPIO_5_4 231
270MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232
271MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233
272MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234
273MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235
274MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236
275MX6Q_PAD_EIM_A23__IPU2_SISG_3 237
276MX6Q_PAD_EIM_A23__IPU1_SISG_3 238
277MX6Q_PAD_EIM_A23__GPIO_6_6 239
278MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240
279MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241
280MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242
281MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243
282MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244
283MX6Q_PAD_EIM_A22__GPIO_2_16 245
284MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246
285MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247
286MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248
287MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249
288MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250
289MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251
290MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252
291MX6Q_PAD_EIM_A21__GPIO_2_17 253
292MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254
293MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255
294MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256
295MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257
296MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258
297MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259
298MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260
299MX6Q_PAD_EIM_A20__GPIO_2_18 261
300MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262
301MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263
302MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264
303MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265
304MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266
305MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267
306MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268
307MX6Q_PAD_EIM_A19__GPIO_2_19 269
308MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270
309MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271
310MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272
311MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273
312MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274
313MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275
314MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276
315MX6Q_PAD_EIM_A18__GPIO_2_20 277
316MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278
317MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279
318MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280
319MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281
320MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282
321MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283
322MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284
323MX6Q_PAD_EIM_A17__GPIO_2_21 285
324MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286
325MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287
326MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288
327MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289
328MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290
329MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291
330MX6Q_PAD_EIM_A16__GPIO_2_22 292
331MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293
332MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294
333MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295
334MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296
335MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297
336MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298
337MX6Q_PAD_EIM_CS0__GPIO_2_23 299
338MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300
339MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301
340MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302
341MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303
342MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304
343MX6Q_PAD_EIM_CS1__GPIO_2_24 305
344MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306
345MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307
346MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308
347MX6Q_PAD_EIM_OE__ECSPI2_MISO 309
348MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310
349MX6Q_PAD_EIM_OE__GPIO_2_25 311
350MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312
351MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313
352MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314
353MX6Q_PAD_EIM_RW__ECSPI2_SS0 315
354MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316
355MX6Q_PAD_EIM_RW__GPIO_2_26 317
356MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318
357MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319
358MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320
359MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321
360MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322
361MX6Q_PAD_EIM_LBA__GPIO_2_27 323
362MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324
363MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325
364MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326
365MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327
366MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328
367MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329
368MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330
369MX6Q_PAD_EIM_EB0__GPIO_2_28 331
370MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332
371MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333
372MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334
373MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335
374MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336
375MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337
376MX6Q_PAD_EIM_EB1__GPIO_2_29 338
377MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339
378MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340
379MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341
380MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342
381MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343
382MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344
383MX6Q_PAD_EIM_DA0__GPIO_3_0 345
384MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346
385MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347
386MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348
387MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349
388MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350
389MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351
390MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352
391MX6Q_PAD_EIM_DA1__GPIO_3_1 353
392MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354
393MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355
394MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356
395MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357
396MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358
397MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359
398MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360
399MX6Q_PAD_EIM_DA2__GPIO_3_2 361
400MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362
401MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363
402MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364
403MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365
404MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366
405MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367
406MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368
407MX6Q_PAD_EIM_DA3__GPIO_3_3 369
408MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370
409MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371
410MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372
411MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373
412MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374
413MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375
414MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376
415MX6Q_PAD_EIM_DA4__GPIO_3_4 377
416MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378
417MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379
418MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380
419MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381
420MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382
421MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383
422MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384
423MX6Q_PAD_EIM_DA5__GPIO_3_5 385
424MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386
425MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387
426MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388
427MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389
428MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390
429MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391
430MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392
431MX6Q_PAD_EIM_DA6__GPIO_3_6 393
432MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394
433MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395
434MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396
435MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397
436MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398
437MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399
438MX6Q_PAD_EIM_DA7__GPIO_3_7 400
439MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401
440MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402
441MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403
442MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404
443MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405
444MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406
445MX6Q_PAD_EIM_DA8__GPIO_3_8 407
446MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408
447MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409
448MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410
449MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411
450MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412
451MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413
452MX6Q_PAD_EIM_DA9__GPIO_3_9 414
453MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415
454MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416
455MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417
456MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418
457MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419
458MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420
459MX6Q_PAD_EIM_DA10__GPIO_3_10 421
460MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422
461MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423
462MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424
463MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425
464MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426
465MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427
466MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428
467MX6Q_PAD_EIM_DA11__GPIO_3_11 429
468MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430
469MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431
470MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432
471MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433
472MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434
473MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435
474MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436
475MX6Q_PAD_EIM_DA12__GPIO_3_12 437
476MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438
477MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439
478MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440
479MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441
480MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442
481MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443
482MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444
483MX6Q_PAD_EIM_DA13__GPIO_3_13 445
484MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446
485MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447
486MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448
487MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449
488MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450
489MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451
490MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452
491MX6Q_PAD_EIM_DA14__GPIO_3_14 453
492MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454
493MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455
494MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456
495MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457
496MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458
497MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459
498MX6Q_PAD_EIM_DA15__GPIO_3_15 460
499MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461
500MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462
501MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463
502MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464
503MX6Q_PAD_EIM_WAIT__GPIO_5_0 465
504MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466
505MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467
506MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468
507MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469
508MX6Q_PAD_EIM_BCLK__GPIO_6_31 470
509MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471
510MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472
511MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473
512MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474
513MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475
514MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476
515MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477
516MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478
517MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479
518MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480
519MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481
520MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482
521MX6Q_PAD_DI0_PIN15__GPIO_4_17 483
522MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484
523MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485
524MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486
525MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487
526MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488
527MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489
528MX6Q_PAD_DI0_PIN2__GPIO_4_18 490
529MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491
530MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492
531MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493
532MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494
533MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495
534MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496
535MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497
536MX6Q_PAD_DI0_PIN3__GPIO_4_19 498
537MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499
538MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500
539MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501
540MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502
541MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503
542MX6Q_PAD_DI0_PIN4__USDHC1_WP 504
543MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505
544MX6Q_PAD_DI0_PIN4__GPIO_4_20 506
545MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507
546MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508
547MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509
548MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510
549MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511
550MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512
551MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513
552MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514
553MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515
554MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516
555MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517
556MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518
557MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519
558MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520
559MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521
560MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522
561MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523
562MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524
563MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525
564MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526
565MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527
566MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528
567MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529
568MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530
569MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531
570MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532
571MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533
572MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534
573MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535
574MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536
575MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537
576MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538
577MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539
578MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540
579MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541
580MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542
581MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543
582MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544
583MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545
584MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546
585MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547
586MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548
587MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549
588MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550
589MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551
590MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552
591MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553
592MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554
593MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555
594MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556
595MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557
596MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558
597MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559
598MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560
599MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561
600MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562
601MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563
602MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564
603MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565
604MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566
605MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567
606MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568
607MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569
608MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570
609MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571
610MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572
611MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573
612MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574
613MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575
614MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576
615MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577
616MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578
617MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579
618MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580
619MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581
620MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582
621MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583
622MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584
623MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585
624MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586
625MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587
626MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588
627MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589
628MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590
629MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591
630MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592
631MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593
632MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594
633MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595
634MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596
635MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597
636MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598
637MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599
638MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600
639MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601
640MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602
641MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603
642MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604
643MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 605
644MX6Q_PAD_DISP0_DAT12__GPIO_5_6 606
645MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 607
646MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 608
647MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 609
648MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610
649MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 611
650MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 612
651MX6Q_PAD_DISP0_DAT13__GPIO_5_7 613
652MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 614
653MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 615
654MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 616
655MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 617
656MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 618
657MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 619
658MX6Q_PAD_DISP0_DAT14__GPIO_5_8 620
659MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 621
660MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 622
661MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 623
662MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624
663MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 625
664MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 626
665MX6Q_PAD_DISP0_DAT15__GPIO_5_9 627
666MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 628
667MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 629
668MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 630
669MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 631
670MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 632
671MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 633
672MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 634
673MX6Q_PAD_DISP0_DAT16__GPIO_5_10 635
674MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 636
675MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 637
676MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 638
677MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 639
678MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 640
679MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 641
680MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 642
681MX6Q_PAD_DISP0_DAT17__GPIO_5_11 643
682MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 644
683MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 645
684MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 646
685MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647
686MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 648
687MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 649
688MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650
689MX6Q_PAD_DISP0_DAT18__GPIO_5_12 651
690MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 652
691MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 653
692MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 654
693MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655
694MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656
695MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657
696MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 658
697MX6Q_PAD_DISP0_DAT19__GPIO_5_13 659
698MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 660
699MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 661
700MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 662
701MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663
702MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664
703MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 665
704MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 666
705MX6Q_PAD_DISP0_DAT20__GPIO_5_14 667
706MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 668
707MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 669
708MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 670
709MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671
710MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 672
711MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 673
712MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 674
713MX6Q_PAD_DISP0_DAT21__GPIO_5_15 675
714MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 676
715MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 677
716MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 678
717MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679
718MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680
719MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 681
720MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 682
721MX6Q_PAD_DISP0_DAT22__GPIO_5_16 683
722MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 684
723MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 685
724MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686
725MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687
726MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688
727MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 689
728MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 690
729MX6Q_PAD_DISP0_DAT23__GPIO_5_17 691
730MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 692
731MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 693
732MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694
733MX6Q_PAD_ENET_MDIO__ENET_MDIO 695
734MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696
735MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697
736MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698
737MX6Q_PAD_ENET_MDIO__GPIO_1_22 699
738MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700
739MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701
740MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702
741MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703
742MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704
743MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705
744MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706
745MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707
746MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708
747MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709
748MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710
749MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711
750MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712
751MX6Q_PAD_ENET_RX_ER__PHY_TDI 713
752MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714
753MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715
754MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716
755MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717
756MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718
757MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719
758MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720
759MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721
760MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722
761MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723
762MX6Q_PAD_ENET_RXD1__ESAI1_FST 724
763MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725
764MX6Q_PAD_ENET_RXD1__GPIO_1_26 726
765MX6Q_PAD_ENET_RXD1__PHY_TCK 727
766MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728
767MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729
768MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730
769MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731
770MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732
771MX6Q_PAD_ENET_RXD0__GPIO_1_27 733
772MX6Q_PAD_ENET_RXD0__PHY_TMS 734
773MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735
774MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736
775MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737
776MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738
777MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739
778MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740
779MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741
780MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742
781MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743
782MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744
783MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745
784MX6Q_PAD_ENET_TXD1__GPIO_1_29 746
785MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747
786MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748
787MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749
788MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750
789MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751
790MX6Q_PAD_ENET_TXD0__GPIO_1_30 752
791MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753
792MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754
793MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755
794MX6Q_PAD_ENET_MDC__ENET_MDC 756
795MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757
796MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758
797MX6Q_PAD_ENET_MDC__GPIO_1_31 759
798MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760
799MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761
800MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762
801MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763
802MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764
803MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765
804MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766
805MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767
806MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768
807MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769
808MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770
809MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771
810MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772
811MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773
812MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774
813MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775
814MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776
815MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777
816MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778
817MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779
818MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780
819MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781
820MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782
821MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783
822MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784
823MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785
824MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786
825MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787
826MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788
827MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789
828MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790
829MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791
830MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792
831MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793
832MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794
833MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795
834MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796
835MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797
836MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798
837MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799
838MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800
839MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801
840MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802
841MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803
842MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804
843MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805
844MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806
845MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807
846MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808
847MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809
848MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810
849MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811
850MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812
851MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813
852MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814
853MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815
854MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816
855MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817
856MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818
857MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819
858MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820
859MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821
860MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822
861MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823
862MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824
863MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825
864MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826
865MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827
866MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828
867MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829
868MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830
869MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831
870MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832
871MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833
872MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834
873MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835
874MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836
875MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837
876MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838
877MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839
878MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840
879MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841
880MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842
881MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843
882MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844
883MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845
884MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846
885MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847
886MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848
887MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849
888MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850
889MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851
890MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852
891MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853
892MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854
893MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855
894MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856
895MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857
896MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858
897MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859
898MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860
899MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861
900MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862
901MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863
902MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864
903MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865
904MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866
905MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867
906MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868
907MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869
908MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870
909MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871
910MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872
911MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873
912MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874
913MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875
914MX6Q_PAD_KEY_COL0__KPP_COL_0 876
915MX6Q_PAD_KEY_COL0__UART4_TXD 877
916MX6Q_PAD_KEY_COL0__GPIO_4_6 878
917MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879
918MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880
919MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881
920MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882
921MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883
922MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884
923MX6Q_PAD_KEY_ROW0__UART4_RXD 885
924MX6Q_PAD_KEY_ROW0__GPIO_4_7 886
925MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887
926MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888
927MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889
928MX6Q_PAD_KEY_COL1__ENET_MDIO 890
929MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891
930MX6Q_PAD_KEY_COL1__KPP_COL_1 892
931MX6Q_PAD_KEY_COL1__UART5_TXD 893
932MX6Q_PAD_KEY_COL1__GPIO_4_8 894
933MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895
934MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896
935MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897
936MX6Q_PAD_KEY_ROW1__ENET_COL 898
937MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899
938MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900
939MX6Q_PAD_KEY_ROW1__UART5_RXD 901
940MX6Q_PAD_KEY_ROW1__GPIO_4_9 902
941MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903
942MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904
943MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905
944MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906
945MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907
946MX6Q_PAD_KEY_COL2__KPP_COL_2 908
947MX6Q_PAD_KEY_COL2__ENET_MDC 909
948MX6Q_PAD_KEY_COL2__GPIO_4_10 910
949MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911
950MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912
951MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913
952MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914
953MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915
954MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916
955MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917
956MX6Q_PAD_KEY_ROW2__GPIO_4_11 918
957MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919
958MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920
959MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921
960MX6Q_PAD_KEY_COL3__ENET_CRS 922
961MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923
962MX6Q_PAD_KEY_COL3__KPP_COL_3 924
963MX6Q_PAD_KEY_COL3__I2C2_SCL 925
964MX6Q_PAD_KEY_COL3__GPIO_4_12 926
965MX6Q_PAD_KEY_COL3__SPDIF_IN1 927
966MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928
967MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929
968MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930
969MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931
970MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932
971MX6Q_PAD_KEY_ROW3__I2C2_SDA 933
972MX6Q_PAD_KEY_ROW3__GPIO_4_13 934
973MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935
974MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936
975MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937
976MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938
977MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939
978MX6Q_PAD_KEY_COL4__KPP_COL_4 940
979MX6Q_PAD_KEY_COL4__UART5_RTS 941
980MX6Q_PAD_KEY_COL4__GPIO_4_14 942
981MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943
982MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944
983MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945
984MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946
985MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947
986MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948
987MX6Q_PAD_KEY_ROW4__UART5_CTS 949
988MX6Q_PAD_KEY_ROW4__GPIO_4_15 950
989MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951
990MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952
991MX6Q_PAD_GPIO_0__CCM_CLKO 953
992MX6Q_PAD_GPIO_0__KPP_COL_5 954
993MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955
994MX6Q_PAD_GPIO_0__EPIT1_EPITO 956
995MX6Q_PAD_GPIO_0__GPIO_1_0 957
996MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958
997MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959
998MX6Q_PAD_GPIO_1__ESAI1_SCKR 960
999MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961
1000MX6Q_PAD_GPIO_1__KPP_ROW_5 962
1001MX6Q_PAD_GPIO_1__PWM2_PWMO 963
1002MX6Q_PAD_GPIO_1__GPIO_1_1 964
1003MX6Q_PAD_GPIO_1__USDHC1_CD 965
1004MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966
1005MX6Q_PAD_GPIO_9__ESAI1_FSR 967
1006MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968
1007MX6Q_PAD_GPIO_9__KPP_COL_6 969
1008MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970
1009MX6Q_PAD_GPIO_9__PWM1_PWMO 971
1010MX6Q_PAD_GPIO_9__GPIO_1_9 972
1011MX6Q_PAD_GPIO_9__USDHC1_WP 973
1012MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974
1013MX6Q_PAD_GPIO_3__ESAI1_HCKR 975
1014MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976
1015MX6Q_PAD_GPIO_3__I2C3_SCL 977
1016MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978
1017MX6Q_PAD_GPIO_3__CCM_CLKO2 979
1018MX6Q_PAD_GPIO_3__GPIO_1_3 980
1019MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981
1020MX6Q_PAD_GPIO_3__MLB_MLBCLK 982
1021MX6Q_PAD_GPIO_6__ESAI1_SCKT 983
1022MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984
1023MX6Q_PAD_GPIO_6__I2C3_SDA 985
1024MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986
1025MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987
1026MX6Q_PAD_GPIO_6__GPIO_1_6 988
1027MX6Q_PAD_GPIO_6__USDHC2_LCTL 989
1028MX6Q_PAD_GPIO_6__MLB_MLBSIG 990
1029MX6Q_PAD_GPIO_2__ESAI1_FST 991
1030MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992
1031MX6Q_PAD_GPIO_2__KPP_ROW_6 993
1032MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994
1033MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995
1034MX6Q_PAD_GPIO_2__GPIO_1_2 996
1035MX6Q_PAD_GPIO_2__USDHC2_WP 997
1036MX6Q_PAD_GPIO_2__MLB_MLBDAT 998
1037MX6Q_PAD_GPIO_4__ESAI1_HCKT 999
1038MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000
1039MX6Q_PAD_GPIO_4__KPP_COL_7 1001
1040MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002
1041MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003
1042MX6Q_PAD_GPIO_4__GPIO_1_4 1004
1043MX6Q_PAD_GPIO_4__USDHC2_CD 1005
1044MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006
1045MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007
1046MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008
1047MX6Q_PAD_GPIO_5__KPP_ROW_7 1009
1048MX6Q_PAD_GPIO_5__CCM_CLKO 1010
1049MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011
1050MX6Q_PAD_GPIO_5__GPIO_1_5 1012
1051MX6Q_PAD_GPIO_5__I2C3_SCL 1013
1052MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014
1053MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015
1054MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016
1055MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017
1056MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018
1057MX6Q_PAD_GPIO_7__UART2_TXD 1019
1058MX6Q_PAD_GPIO_7__GPIO_1_7 1020
1059MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021
1060MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022
1061MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023
1062MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024
1063MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025
1064MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026
1065MX6Q_PAD_GPIO_8__UART2_RXD 1027
1066MX6Q_PAD_GPIO_8__GPIO_1_8 1028
1067MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029
1068MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030
1069MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031
1070MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032
1071MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033
1072MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034
1073MX6Q_PAD_GPIO_16__SPDIF_IN1 1035
1074MX6Q_PAD_GPIO_16__GPIO_7_11 1036
1075MX6Q_PAD_GPIO_16__I2C3_SDA 1037
1076MX6Q_PAD_GPIO_16__SJC_DE_B 1038
1077MX6Q_PAD_GPIO_17__ESAI1_TX0 1039
1078MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040
1079MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041
1080MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042
1081MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043
1082MX6Q_PAD_GPIO_17__GPIO_7_12 1044
1083MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045
1084MX6Q_PAD_GPIO_18__ESAI1_TX1 1046
1085MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047
1086MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048
1087MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049
1088MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050
1089MX6Q_PAD_GPIO_18__GPIO_7_13 1051
1090MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052
1091MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053
1092MX6Q_PAD_GPIO_19__KPP_COL_5 1054
1093MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055
1094MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056
1095MX6Q_PAD_GPIO_19__CCM_CLKO 1057
1096MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058
1097MX6Q_PAD_GPIO_19__GPIO_4_5 1059
1098MX6Q_PAD_GPIO_19__ENET_TX_ER 1060
1099MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061
1100MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062
1101MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063
1102MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064
1103MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065
1104MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066
1105MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067
1106MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068
1107MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069
1108MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070
1109MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071
1110MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072
1111MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073
1112MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074
1113MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075
1114MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076
1115MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077
1116MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078
1117MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079
1118MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080
1119MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081
1120MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082
1121MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083
1122MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084
1123MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085
1124MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086
1125MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087
1126MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088
1127MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089
1128MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090
1129MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091
1130MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092
1131MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093
1132MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094
1133MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095
1134MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096
1135MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097
1136MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098
1137MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099
1138MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100
1139MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101
1140MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102
1141MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103
1142MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104
1143MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105
1144MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106
1145MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107
1146MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108
1147MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109
1148MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110
1149MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111
1150MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112
1151MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113
1152MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114
1153MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115
1154MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116
1155MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117
1156MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118
1157MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119
1158MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120
1159MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121
1160MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122
1161MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123
1162MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124
1163MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125
1164MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126
1165MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127
1166MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128
1167MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129
1168MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130
1169MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131
1170MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132
1171MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133
1172MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134
1173MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135
1174MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136
1175MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137
1176MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138
1177MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139
1178MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140
1179MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141
1180MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142
1181MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143
1182MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144
1183MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145
1184MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146
1185MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147
1186MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148
1187MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149
1188MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150
1189MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151
1190MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152
1191MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153
1192MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154
1193MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155
1194MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156
1195MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157
1196MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158
1197MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159
1198MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160
1199MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161
1200MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162
1201MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163
1202MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164
1203MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165
1204MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166
1205MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167
1206MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168
1207MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169
1208MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170
1209MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171
1210MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172
1211MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173
1212MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174
1213MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175
1214MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176
1215MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177
1216MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178
1217MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179
1218MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180
1219MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181
1220MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182
1221MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183
1222MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184
1223MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185
1224MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186
1225MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187
1226MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188
1227MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189
1228MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190
1229MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191
1230MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192
1231MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193
1232MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194
1233MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195
1234MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196
1235MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197
1236MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198
1237MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199
1238MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200
1239MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201
1240MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202
1241MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203
1242MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204
1243MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205
1244MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206
1245MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207
1246MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208
1247MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209
1248MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210
1249MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211
1250MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212
1251MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213
1252MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214
1253MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215
1254MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216
1255MX6Q_PAD_JTAG_TMS__SJC_TMS 1217
1256MX6Q_PAD_JTAG_MOD__SJC_MOD 1218
1257MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219
1258MX6Q_PAD_JTAG_TDI__SJC_TDI 1220
1259MX6Q_PAD_JTAG_TCK__SJC_TCK 1221
1260MX6Q_PAD_JTAG_TDO__SJC_TDO 1222
1261MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223
1262MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224
1263MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225
1264MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226
1265MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227
1266MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228
1267MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229
1268MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230
1269MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231
1270MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232
1271MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233
1272MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234
1273MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235
1274MX6Q_PAD_POR_B__SRC_POR_B 1236
1275MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237
1276MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238
1277MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239
1278MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240
1279MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241
1280MX6Q_PAD_SD3_DAT7__UART1_TXD 1242
1281MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243
1282MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244
1283MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245
1284MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246
1285MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247
1286MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248
1287MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249
1288MX6Q_PAD_SD3_DAT6__UART1_RXD 1250
1289MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251
1290MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252
1291MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253
1292MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254
1293MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255
1294MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256
1295MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257
1296MX6Q_PAD_SD3_DAT5__UART2_TXD 1258
1297MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259
1298MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260
1299MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261
1300MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262
1301MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263
1302MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264
1303MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265
1304MX6Q_PAD_SD3_DAT4__UART2_RXD 1266
1305MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267
1306MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268
1307MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269
1308MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270
1309MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271
1310MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272
1311MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273
1312MX6Q_PAD_SD3_CMD__UART2_CTS 1274
1313MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275
1314MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276
1315MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277
1316MX6Q_PAD_SD3_CMD__GPIO_7_2 1278
1317MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279
1318MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280
1319MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281
1320MX6Q_PAD_SD3_CLK__UART2_RTS 1282
1321MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283
1322MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284
1323MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285
1324MX6Q_PAD_SD3_CLK__GPIO_7_3 1286
1325MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287
1326MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288
1327MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289
1328MX6Q_PAD_SD3_DAT0__UART1_CTS 1290
1329MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291
1330MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292
1331MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293
1332MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294
1333MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295
1334MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296
1335MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297
1336MX6Q_PAD_SD3_DAT1__UART1_RTS 1298
1337MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299
1338MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300
1339MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301
1340MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302
1341MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303
1342MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304
1343MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305
1344MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306
1345MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307
1346MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308
1347MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309
1348MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310
1349MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311
1350MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312
1351MX6Q_PAD_SD3_DAT3__UART3_CTS 1313
1352MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314
1353MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315
1354MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316
1355MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317
1356MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318
1357MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319
1358MX6Q_PAD_SD3_RST__USDHC3_RST 1320
1359MX6Q_PAD_SD3_RST__UART3_RTS 1321
1360MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322
1361MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323
1362MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324
1363MX6Q_PAD_SD3_RST__GPIO_7_8 1325
1364MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326
1365MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327
1366MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328
1367MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329
1368MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330
1369MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331
1370MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332
1371MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333
1372MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334
1373MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335
1374MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336
1375MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337
1376MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338
1377MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339
1378MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340
1379MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341
1380MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342
1381MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343
1382MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344
1383MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345
1384MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346
1385MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347
1386MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348
1387MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349
1388MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350
1389MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351
1390MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352
1391MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353
1392MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354
1393MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355
1394MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356
1395MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357
1396MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358
1397MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359
1398MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360
1399MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361
1400MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362
1401MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363
1402MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364
1403MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365
1404MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366
1405MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367
1406MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368
1407MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369
1408MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370
1409MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371
1410MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372
1411MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373
1412MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374
1413MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375
1414MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376
1415MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377
1416MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378
1417MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379
1418MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380
1419MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381
1420MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382
1421MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383
1422MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384
1423MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385
1424MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386
1425MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387
1426MX6Q_PAD_SD4_CMD__UART3_TXD 1388
1427MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389
1428MX6Q_PAD_SD4_CMD__GPIO_7_9 1390
1429MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391
1430MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392
1431MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393
1432MX6Q_PAD_SD4_CLK__UART3_RXD 1394
1433MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395
1434MX6Q_PAD_SD4_CLK__GPIO_7_10 1396
1435MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397
1436MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398
1437MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399
1438MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400
1439MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401
1440MX6Q_PAD_NANDF_D0__GPIO_2_0 1402
1441MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403
1442MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404
1443MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405
1444MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406
1445MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407
1446MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408
1447MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409
1448MX6Q_PAD_NANDF_D1__GPIO_2_1 1410
1449MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411
1450MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412
1451MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413
1452MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414
1453MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415
1454MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416
1455MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417
1456MX6Q_PAD_NANDF_D2__GPIO_2_2 1418
1457MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419
1458MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420
1459MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421
1460MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422
1461MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423
1462MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424
1463MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425
1464MX6Q_PAD_NANDF_D3__GPIO_2_3 1426
1465MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427
1466MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428
1467MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429
1468MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430
1469MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431
1470MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432
1471MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433
1472MX6Q_PAD_NANDF_D4__GPIO_2_4 1434
1473MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435
1474MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436
1475MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437
1476MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438
1477MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439
1478MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440
1479MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441
1480MX6Q_PAD_NANDF_D5__GPIO_2_5 1442
1481MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443
1482MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444
1483MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445
1484MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446
1485MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447
1486MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448
1487MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449
1488MX6Q_PAD_NANDF_D6__GPIO_2_6 1450
1489MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451
1490MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452
1491MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453
1492MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454
1493MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455
1494MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456
1495MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457
1496MX6Q_PAD_NANDF_D7__GPIO_2_7 1458
1497MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459
1498MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460
1499MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461
1500MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462
1501MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463
1502MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464
1503MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465
1504MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466
1505MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467
1506MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468
1507MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469
1508MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470
1509MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471
1510MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472
1511MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473
1512MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474
1513MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475
1514MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476
1515MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477
1516MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478
1517MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479
1518MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480
1519MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481
1520MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482
1521MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483
1522MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484
1523MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485
1524MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486
1525MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487
1526MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488
1527MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489
1528MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490
1529MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491
1530MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492
1531MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493
1532MX6Q_PAD_SD4_DAT4__UART2_RXD 1494
1533MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495
1534MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496
1535MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497
1536MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498
1537MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499
1538MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500
1539MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501
1540MX6Q_PAD_SD4_DAT5__UART2_RTS 1502
1541MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503
1542MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504
1543MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505
1544MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506
1545MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507
1546MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508
1547MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509
1548MX6Q_PAD_SD4_DAT6__UART2_CTS 1510
1549MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511
1550MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512
1551MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513
1552MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514
1553MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515
1554MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516
1555MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517
1556MX6Q_PAD_SD4_DAT7__UART2_TXD 1518
1557MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519
1558MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520
1559MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521
1560MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522
1561MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523
1562MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524
1563MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525
1564MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526
1565MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527
1566MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528
1567MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529
1568MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530
1569MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531
1570MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532
1571MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533
1572MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534
1573MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535
1574MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536
1575MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537
1576MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538
1577MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539
1578MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540
1579MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541
1580MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542
1581MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543
1582MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544
1583MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545
1584MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546
1585MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547
1586MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548
1587MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549
1588MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550
1589MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551
1590MX6Q_PAD_SD1_CMD__GPIO_1_18 1552
1591MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553
1592MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554
1593MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555
1594MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556
1595MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557
1596MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558
1597MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559
1598MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560
1599MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561
1600MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562
1601MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563
1602MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564
1603MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565
1604MX6Q_PAD_SD1_CLK__GPIO_1_20 1566
1605MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567
1606MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568
1607MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569
1608MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570
1609MX6Q_PAD_SD2_CLK__KPP_COL_5 1571
1610MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572
1611MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573
1612MX6Q_PAD_SD2_CLK__GPIO_1_10 1574
1613MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575
1614MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576
1615MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577
1616MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578
1617MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579
1618MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580
1619MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581
1620MX6Q_PAD_SD2_CMD__GPIO_1_11 1582
1621MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583
1622MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584
1623MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585
1624MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586
1625MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
1626MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
1627MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
1628MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
1629MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID 1591
1630MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID 1592
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt
new file mode 100644
index 000000000000..e5f6d1f065a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt
@@ -0,0 +1,39 @@
1* Freescale IMX6 SoloLite IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx6sl-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_LVE (1 << 22)
16PAD_CTL_HYS (1 << 16)
17PAD_CTL_PUS_100K_DOWN (0 << 14)
18PAD_CTL_PUS_47K_UP (1 << 14)
19PAD_CTL_PUS_100K_UP (2 << 14)
20PAD_CTL_PUS_22K_UP (3 << 14)
21PAD_CTL_PUE (1 << 13)
22PAD_CTL_PKE (1 << 12)
23PAD_CTL_ODE (1 << 11)
24PAD_CTL_SPEED_LOW (1 << 6)
25PAD_CTL_SPEED_MED (2 << 6)
26PAD_CTL_SPEED_HIGH (3 << 6)
27PAD_CTL_DSE_DISABLE (0 << 3)
28PAD_CTL_DSE_240ohm (1 << 3)
29PAD_CTL_DSE_120ohm (2 << 3)
30PAD_CTL_DSE_80ohm (3 << 3)
31PAD_CTL_DSE_60ohm (4 << 3)
32PAD_CTL_DSE_48ohm (5 << 3)
33PAD_CTL_DSE_40ohm (6 << 3)
34PAD_CTL_DSE_34ohm (7 << 3)
35PAD_CTL_SRE_FAST (1 << 0)
36PAD_CTL_SRE_SLOW (0 << 0)
37
38Refer to imx6sl-pinfunc.h in device tree source folder for all available
39imx6sl PIN_FUNC_ID.
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
new file mode 100644
index 000000000000..9809b11f7180
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
@@ -0,0 +1,18 @@
1Freescale i.MX General Purpose Timer (GPT)
2
3Required properties:
4
5- compatible : should be "fsl,<soc>-gpt"
6- reg : Specifies base physical address and size of the registers.
7- interrupts : A list of 4 interrupts; one per timer channel.
8- clocks : The clocks provided by the SoC to drive the timer.
9
10Example:
11
12gpt1: timer@10003000 {
13 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
14 reg = <0x10003000 0x1000>;
15 interrupts = <26>;
16 clocks = <&clks 46>, <&clks 61>;
17 clock-names = "ipg", "per";
18};
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c6255884cbb..2be254709dcb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_OF),y)
3# Keep at91 dtb files sorted alphabetically for each SoC 3# Keep at91 dtb files sorted alphabetically for each SoC
4# rm9200 4# rm9200
5dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb 5dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
6dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb
6# sam9260 7# sam9260
7dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb 8dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
8dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb 9dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
@@ -26,6 +27,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
26# sam9n12 27# sam9n12
27dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb 28dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
28# sam9x5 29# sam9x5
30dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
29dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb 31dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
30dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb 32dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
31dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb 33dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
@@ -87,19 +89,26 @@ dtb-$(CONFIG_ARCH_MXC) += \
87 imx25-karo-tx25.dtb \ 89 imx25-karo-tx25.dtb \
88 imx25-pdk.dtb \ 90 imx25-pdk.dtb \
89 imx27-apf27.dtb \ 91 imx27-apf27.dtb \
92 imx27-apf27dev.dtb \
90 imx27-pdk.dtb \ 93 imx27-pdk.dtb \
94 imx27-phytec-phycore.dtb \
91 imx31-bug.dtb \ 95 imx31-bug.dtb \
92 imx51-apf51.dtb \ 96 imx51-apf51.dtb \
97 imx51-apf51dev.dtb \
93 imx51-babbage.dtb \ 98 imx51-babbage.dtb \
94 imx53-ard.dtb \ 99 imx53-ard.dtb \
95 imx53-evk.dtb \ 100 imx53-evk.dtb \
96 imx53-mba53.dtb \ 101 imx53-mba53.dtb \
97 imx53-qsb.dtb \ 102 imx53-qsb.dtb \
98 imx53-smd.dtb \ 103 imx53-smd.dtb \
104 imx6dl-sabreauto.dtb \
105 imx6dl-sabresd.dtb \
106 imx6dl-wandboard.dtb \
99 imx6q-arm2.dtb \ 107 imx6q-arm2.dtb \
100 imx6q-sabreauto.dtb \ 108 imx6q-sabreauto.dtb \
101 imx6q-sabrelite.dtb \ 109 imx6q-sabrelite.dtb \
102 imx6q-sabresd.dtb 110 imx6q-sabresd.dtb \
111 imx6q-sbc6x.dtb
103dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 112dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
104 imx23-olinuxino.dtb \ 113 imx23-olinuxino.dtb \
105 imx23-stmp378x_devb.dtb \ 114 imx23-stmp378x_devb.dtb \
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e34b280ce6ec..6403acdbb75f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -94,5 +94,22 @@
94 spi-max-frequency = <50000000>; 94 spi-max-frequency = <50000000>;
95 }; 95 };
96 }; 96 };
97
98 pcie-controller {
99 status = "okay";
100 /*
101 * The two PCIe units are accessible through
102 * both standard PCIe slots and mini-PCIe
103 * slots on the board.
104 */
105 pcie@1,0 {
106 /* Port 0, Lane 0 */
107 status = "okay";
108 };
109 pcie@2,0 {
110 /* Port 1, Lane 0 */
111 status = "okay";
112 };
113 };
97 }; 114 };
98}; 115};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 3234875824dc..58ee79372206 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -33,6 +33,43 @@
33 clock-frequency = <600000000>; 33 clock-frequency = <600000000>;
34 status = "okay"; 34 status = "okay";
35 }; 35 };
36
37 pinctrl {
38 pwr_led_pin: pwr-led-pin {
39 marvell,pins = "mpp63";
40 marvell,function = "gpo";
41 };
42
43 stat_led_pins: stat-led-pins {
44 marvell,pins = "mpp64", "mpp65";
45 marvell,function = "gpio";
46 };
47 };
48
49 gpio_leds {
50 compatible = "gpio-leds";
51 pinctrl-names = "default";
52 pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
53
54 green_pwr_led {
55 label = "mirabox:green:pwr";
56 gpios = <&gpio1 31 1>;
57 linux,default-trigger = "heartbeat";
58 };
59
60 blue_stat_led {
61 label = "mirabox:blue:stat";
62 gpios = <&gpio2 0 1>;
63 linux,default-trigger = "cpu0";
64 };
65
66 green_stat_led {
67 label = "mirabox:green:stat";
68 gpios = <&gpio2 1 1>;
69 default-state = "off";
70 };
71 };
72
36 mdio { 73 mdio {
37 phy0: ethernet-phy@0 { 74 phy0: ethernet-phy@0 {
38 reg = <0>; 75 reg = <0>;
@@ -70,5 +107,32 @@
70 usb@d0051000 { 107 usb@d0051000 {
71 status = "okay"; 108 status = "okay";
72 }; 109 };
110
111 i2c@d0011000 {
112 status = "okay";
113 clock-frequency = <100000>;
114 pca9505: pca9505@25 {
115 compatible = "nxp,pca9505";
116 gpio-controller;
117 #gpio-cells = <2>;
118 reg = <0x25>;
119 };
120 };
121
122 pcie-controller {
123 status = "okay";
124
125 /* Internal mini-PCIe connector */
126 pcie@1,0 {
127 /* Port 0, Lane 0 */
128 status = "okay";
129 };
130
131 /* Connected on the PCB to a USB 3.0 XHCI controller */
132 pcie@2,0 {
133 /* Port 1, Lane 0 */
134 status = "okay";
135 };
136 };
73 }; 137 };
74}; 138};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 070bba4f2585..516dec31b469 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -73,4 +73,15 @@
73 status = "okay"; 73 status = "okay";
74 }; 74 };
75 }; 75 };
76
77 gpio-keys {
78 compatible = "gpio-keys";
79 #address-cells = <1>;
80 #size-cells = <0>;
81 button@1 {
82 label = "Software Button";
83 linux,code = <116>;
84 gpios = <&gpio0 6 1>;
85 };
86 };
76}; 87};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 5b708208b607..758c4ea90344 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -181,6 +181,51 @@
181 clocks = <&coreclk 0>; 181 clocks = <&coreclk 0>;
182 status = "disabled"; 182 status = "disabled";
183 }; 183 };
184
185 devbus-bootcs@d0010400 {
186 compatible = "marvell,mvebu-devbus";
187 reg = <0xd0010400 0x8>;
188 #address-cells = <1>;
189 #size-cells = <1>;
190 clocks = <&coreclk 0>;
191 status = "disabled";
192 };
193
194 devbus-cs0@d0010408 {
195 compatible = "marvell,mvebu-devbus";
196 reg = <0xd0010408 0x8>;
197 #address-cells = <1>;
198 #size-cells = <1>;
199 clocks = <&coreclk 0>;
200 status = "disabled";
201 };
202
203 devbus-cs1@d0010410 {
204 compatible = "marvell,mvebu-devbus";
205 reg = <0xd0010410 0x8>;
206 #address-cells = <1>;
207 #size-cells = <1>;
208 clocks = <&coreclk 0>;
209 status = "disabled";
210 };
211
212 devbus-cs2@d0010418 {
213 compatible = "marvell,mvebu-devbus";
214 reg = <0xd0010418 0x8>;
215 #address-cells = <1>;
216 #size-cells = <1>;
217 clocks = <&coreclk 0>;
218 status = "disabled";
219 };
220
221 devbus-cs3@d0010420 {
222 compatible = "marvell,mvebu-devbus";
223 reg = <0xd0010420 0x8>;
224 #address-cells = <1>;
225 #size-cells = <1>;
226 clocks = <&coreclk 0>;
227 status = "disabled";
228 };
184 }; 229 };
185}; 230};
186 231
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index a195debb67d3..18f6eb47cc50 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -159,5 +159,63 @@
159 clocks = <&coreclk 0>; 159 clocks = <&coreclk 0>;
160 }; 160 };
161 161
162 thermal@d0018300 {
163 compatible = "marvell,armada370-thermal";
164 reg = <0xd0018300 0x4
165 0xd0018304 0x4>;
166 status = "okay";
167 };
168
169 pcie-controller {
170 compatible = "marvell,armada-370-pcie";
171 status = "disabled";
172 device_type = "pci";
173
174 #address-cells = <3>;
175 #size-cells = <2>;
176
177 bus-range = <0x00 0xff>;
178
179 reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
180
181 reg-names = "pcie0.0", "pcie1.0";
182
183 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
184 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
185 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
186 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
187
188 pcie@1,0 {
189 device_type = "pci";
190 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
191 reg = <0x0800 0 0 0 0>;
192 #address-cells = <3>;
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 ranges;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 58>;
198 marvell,pcie-port = <0>;
199 marvell,pcie-lane = <0>;
200 clocks = <&gateclk 5>;
201 status = "disabled";
202 };
203
204 pcie@2,0 {
205 device_type = "pci";
206 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
207 reg = <0x1000 0 0 0 0>;
208 #address-cells = <3>;
209 #size-cells = <2>;
210 #interrupt-cells = <1>;
211 ranges;
212 interrupt-map-mask = <0 0 0 0>;
213 interrupt-map = <0 0 0 0 &mpic 62>;
214 marvell,pcie-port = <1>;
215 marvell,pcie-lane = <0>;
216 clocks = <&gateclk 9>;
217 status = "disabled";
218 };
219 };
162 }; 220 };
163}; 221};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e83505e4c236..54cc5bb705fb 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -121,5 +121,38 @@
121 spi-max-frequency = <20000000>; 121 spi-max-frequency = <20000000>;
122 }; 122 };
123 }; 123 };
124
125 pcie-controller {
126 status = "okay";
127
128 /*
129 * All 6 slots are physically present as
130 * standard PCIe slots on the board.
131 */
132 pcie@1,0 {
133 /* Port 0, Lane 0 */
134 status = "okay";
135 };
136 pcie@2,0 {
137 /* Port 0, Lane 1 */
138 status = "okay";
139 };
140 pcie@3,0 {
141 /* Port 0, Lane 2 */
142 status = "okay";
143 };
144 pcie@4,0 {
145 /* Port 0, Lane 3 */
146 status = "okay";
147 };
148 pcie@9,0 {
149 /* Port 2, Lane 0 */
150 status = "okay";
151 };
152 pcie@10,0 {
153 /* Port 3, Lane 0 */
154 status = "okay";
155 };
156 };
124 }; 157 };
125}; 158};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1c8afe2ffebc..04f28a712b98 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -109,5 +109,55 @@
109 spi-max-frequency = <108000000>; 109 spi-max-frequency = <108000000>;
110 }; 110 };
111 }; 111 };
112
113 devbus-bootcs@d0010400 {
114 status = "okay";
115 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
116
117 /* Device Bus parameters are required */
118
119 /* Read parameters */
120 devbus,bus-width = <8>;
121 devbus,turn-off-ps = <60000>;
122 devbus,badr-skew-ps = <0>;
123 devbus,acc-first-ps = <124000>;
124 devbus,acc-next-ps = <248000>;
125 devbus,rd-setup-ps = <0>;
126 devbus,rd-hold-ps = <0>;
127
128 /* Write parameters */
129 devbus,sync-enable = <0>;
130 devbus,wr-high-ps = <60000>;
131 devbus,wr-low-ps = <60000>;
132 devbus,ale-wr-ps = <60000>;
133
134 /* NOR 16 MiB */
135 nor@0 {
136 compatible = "cfi-flash";
137 reg = <0 0x1000000>;
138 bank-width = <2>;
139 };
140 };
141
142 pcie-controller {
143 status = "okay";
144
145 /*
146 * The 3 slots are physically present as
147 * standard PCIe slots on the board.
148 */
149 pcie@1,0 {
150 /* Port 0, Lane 0 */
151 status = "okay";
152 };
153 pcie@9,0 {
154 /* Port 2, Lane 0 */
155 status = "okay";
156 };
157 pcie@10,0 {
158 /* Port 3, Lane 0 */
159 status = "okay";
160 };
161 };
112 }; 162 };
113}; 163};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f56c40599f5b..c2c78459a4d4 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -76,5 +76,109 @@
76 #interrupts-cells = <2>; 76 #interrupts-cells = <2>;
77 interrupts = <87>, <88>, <89>; 77 interrupts = <87>, <88>, <89>;
78 }; 78 };
79
80 /*
81 * MV78230 has 2 PCIe units Gen2.0: One unit can be
82 * configured as x4 or quad x1 lanes. One unit is
83 * x4/x1.
84 */
85 pcie-controller {
86 compatible = "marvell,armada-xp-pcie";
87 status = "disabled";
88 device_type = "pci";
89
90 #address-cells = <3>;
91 #size-cells = <2>;
92
93 bus-range = <0x00 0xff>;
94
95 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
96 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
97 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
98 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
99 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
100 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
101 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
102
103 pcie@1,0 {
104 device_type = "pci";
105 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
106 reg = <0x0800 0 0 0 0>;
107 #address-cells = <3>;
108 #size-cells = <2>;
109 #interrupt-cells = <1>;
110 ranges;
111 interrupt-map-mask = <0 0 0 0>;
112 interrupt-map = <0 0 0 0 &mpic 58>;
113 marvell,pcie-port = <0>;
114 marvell,pcie-lane = <0>;
115 clocks = <&gateclk 5>;
116 status = "disabled";
117 };
118
119 pcie@2,0 {
120 device_type = "pci";
121 assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
122 reg = <0x1000 0 0 0 0>;
123 #address-cells = <3>;
124 #size-cells = <2>;
125 #interrupt-cells = <1>;
126 ranges;
127 interrupt-map-mask = <0 0 0 0>;
128 interrupt-map = <0 0 0 0 &mpic 59>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <1>;
131 clocks = <&gateclk 6>;
132 status = "disabled";
133 };
134
135 pcie@3,0 {
136 device_type = "pci";
137 assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
138 reg = <0x1800 0 0 0 0>;
139 #address-cells = <3>;
140 #size-cells = <2>;
141 #interrupt-cells = <1>;
142 ranges;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &mpic 60>;
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <2>;
147 clocks = <&gateclk 7>;
148 status = "disabled";
149 };
150
151 pcie@4,0 {
152 device_type = "pci";
153 assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
154 reg = <0x2000 0 0 0 0>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 #interrupt-cells = <1>;
158 ranges;
159 interrupt-map-mask = <0 0 0 0>;
160 interrupt-map = <0 0 0 0 &mpic 61>;
161 marvell,pcie-port = <0>;
162 marvell,pcie-lane = <3>;
163 clocks = <&gateclk 8>;
164 status = "disabled";
165 };
166
167 pcie@9,0 {
168 device_type = "pci";
169 assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
170 reg = <0x4800 0 0 0 0>;
171 #address-cells = <3>;
172 #size-cells = <2>;
173 #interrupt-cells = <1>;
174 ranges;
175 interrupt-map-mask = <0 0 0 0>;
176 interrupt-map = <0 0 0 0 &mpic 99>;
177 marvell,pcie-port = <2>;
178 marvell,pcie-lane = <0>;
179 clocks = <&gateclk 26>;
180 status = "disabled";
181 };
182 };
79 }; 183 };
80}; 184};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f8f2b787d2b0..885bf229eef7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -96,5 +96,127 @@
96 clocks = <&gateclk 1>; 96 clocks = <&gateclk 1>;
97 status = "disabled"; 97 status = "disabled";
98 }; 98 };
99
100 /*
101 * MV78260 has 3 PCIe units Gen2.0: Two units can be
102 * configured as x4 or quad x1 lanes. One unit is
103 * x4/x1.
104 */
105 pcie-controller {
106 compatible = "marvell,armada-xp-pcie";
107 status = "disabled";
108 device_type = "pci";
109
110 #address-cells = <3>;
111 #size-cells = <2>;
112
113 bus-range = <0x00 0xff>;
114
115 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
116 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
117 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
118 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
119 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
120 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
121 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
122 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
123 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
124
125 pcie@1,0 {
126 device_type = "pci";
127 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
128 reg = <0x0800 0 0 0 0>;
129 #address-cells = <3>;
130 #size-cells = <2>;
131 #interrupt-cells = <1>;
132 ranges;
133 interrupt-map-mask = <0 0 0 0>;
134 interrupt-map = <0 0 0 0 &mpic 58>;
135 marvell,pcie-port = <0>;
136 marvell,pcie-lane = <0>;
137 clocks = <&gateclk 5>;
138 status = "disabled";
139 };
140
141 pcie@2,0 {
142 device_type = "pci";
143 assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
144 reg = <0x1000 0 0 0 0>;
145 #address-cells = <3>;
146 #size-cells = <2>;
147 #interrupt-cells = <1>;
148 ranges;
149 interrupt-map-mask = <0 0 0 0>;
150 interrupt-map = <0 0 0 0 &mpic 59>;
151 marvell,pcie-port = <0>;
152 marvell,pcie-lane = <1>;
153 clocks = <&gateclk 6>;
154 status = "disabled";
155 };
156
157 pcie@3,0 {
158 device_type = "pci";
159 assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
160 reg = <0x1800 0 0 0 0>;
161 #address-cells = <3>;
162 #size-cells = <2>;
163 #interrupt-cells = <1>;
164 ranges;
165 interrupt-map-mask = <0 0 0 0>;
166 interrupt-map = <0 0 0 0 &mpic 60>;
167 marvell,pcie-port = <0>;
168 marvell,pcie-lane = <2>;
169 clocks = <&gateclk 7>;
170 status = "disabled";
171 };
172
173 pcie@4,0 {
174 device_type = "pci";
175 assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
176 reg = <0x2000 0 0 0 0>;
177 #address-cells = <3>;
178 #size-cells = <2>;
179 #interrupt-cells = <1>;
180 ranges;
181 interrupt-map-mask = <0 0 0 0>;
182 interrupt-map = <0 0 0 0 &mpic 61>;
183 marvell,pcie-port = <0>;
184 marvell,pcie-lane = <3>;
185 clocks = <&gateclk 8>;
186 status = "disabled";
187 };
188
189 pcie@9,0 {
190 device_type = "pci";
191 assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
192 reg = <0x4800 0 0 0 0>;
193 #address-cells = <3>;
194 #size-cells = <2>;
195 #interrupt-cells = <1>;
196 ranges;
197 interrupt-map-mask = <0 0 0 0>;
198 interrupt-map = <0 0 0 0 &mpic 99>;
199 marvell,pcie-port = <2>;
200 marvell,pcie-lane = <0>;
201 clocks = <&gateclk 26>;
202 status = "disabled";
203 };
204
205 pcie@10,0 {
206 device_type = "pci";
207 assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>;
208 reg = <0x5000 0 0 0 0>;
209 #address-cells = <3>;
210 #size-cells = <2>;
211 #interrupt-cells = <1>;
212 ranges;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &mpic 103>;
215 marvell,pcie-port = <3>;
216 marvell,pcie-lane = <0>;
217 clocks = <&gateclk 27>;
218 status = "disabled";
219 };
220 };
99 }; 221 };
100}; 222};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 936c25dc32b0..23a5ac4490a8 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -111,5 +111,193 @@
111 clocks = <&gateclk 1>; 111 clocks = <&gateclk 1>;
112 status = "disabled"; 112 status = "disabled";
113 }; 113 };
114
115 /*
116 * MV78460 has 4 PCIe units Gen2.0: Two units can be
117 * configured as x4 or quad x1 lanes. Two units are
118 * x4/x1.
119 */
120 pcie-controller {
121 compatible = "marvell,armada-xp-pcie";
122 status = "disabled";
123 device_type = "pci";
124
125 #address-cells = <3>;
126 #size-cells = <2>;
127
128 bus-range = <0x00 0xff>;
129
130 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
131 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
132 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
133 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
134 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
135 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
136 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
137 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
138 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
139 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
140 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
141 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
142
143 pcie@1,0 {
144 device_type = "pci";
145 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
146 reg = <0x0800 0 0 0 0>;
147 #address-cells = <3>;
148 #size-cells = <2>;
149 #interrupt-cells = <1>;
150 ranges;
151 interrupt-map-mask = <0 0 0 0>;
152 interrupt-map = <0 0 0 0 &mpic 58>;
153 marvell,pcie-port = <0>;
154 marvell,pcie-lane = <0>;
155 clocks = <&gateclk 5>;
156 status = "disabled";
157 };
158
159 pcie@2,0 {
160 device_type = "pci";
161 assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
162 reg = <0x1000 0 0 0 0>;
163 #address-cells = <3>;
164 #size-cells = <2>;
165 #interrupt-cells = <1>;
166 ranges;
167 interrupt-map-mask = <0 0 0 0>;
168 interrupt-map = <0 0 0 0 &mpic 59>;
169 marvell,pcie-port = <0>;
170 marvell,pcie-lane = <1>;
171 clocks = <&gateclk 6>;
172 status = "disabled";
173 };
174
175 pcie@3,0 {
176 device_type = "pci";
177 assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
178 reg = <0x1800 0 0 0 0>;
179 #address-cells = <3>;
180 #size-cells = <2>;
181 #interrupt-cells = <1>;
182 ranges;
183 interrupt-map-mask = <0 0 0 0>;
184 interrupt-map = <0 0 0 0 &mpic 60>;
185 marvell,pcie-port = <0>;
186 marvell,pcie-lane = <2>;
187 clocks = <&gateclk 7>;
188 status = "disabled";
189 };
190
191 pcie@4,0 {
192 device_type = "pci";
193 assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
194 reg = <0x2000 0 0 0 0>;
195 #address-cells = <3>;
196 #size-cells = <2>;
197 #interrupt-cells = <1>;
198 ranges;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 61>;
201 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <3>;
203 clocks = <&gateclk 8>;
204 status = "disabled";
205 };
206
207 pcie@5,0 {
208 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
210 reg = <0x2800 0 0 0 0>;
211 #address-cells = <3>;
212 #size-cells = <2>;
213 #interrupt-cells = <1>;
214 ranges;
215 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>;
220 status = "disabled";
221 };
222
223 pcie@6,0 {
224 device_type = "pci";
225 assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
226 reg = <0x3000 0 0 0 0>;
227 #address-cells = <3>;
228 #size-cells = <2>;
229 #interrupt-cells = <1>;
230 ranges;
231 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 63>;
233 marvell,pcie-port = <1>;
234 marvell,pcie-lane = <1>;
235 clocks = <&gateclk 10>;
236 status = "disabled";
237 };
238
239 pcie@7,0 {
240 device_type = "pci";
241 assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
242 reg = <0x3800 0 0 0 0>;
243 #address-cells = <3>;
244 #size-cells = <2>;
245 #interrupt-cells = <1>;
246 ranges;
247 interrupt-map-mask = <0 0 0 0>;
248 interrupt-map = <0 0 0 0 &mpic 64>;
249 marvell,pcie-port = <1>;
250 marvell,pcie-lane = <2>;
251 clocks = <&gateclk 11>;
252 status = "disabled";
253 };
254
255 pcie@8,0 {
256 device_type = "pci";
257 assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
258 reg = <0x4000 0 0 0 0>;
259 #address-cells = <3>;
260 #size-cells = <2>;
261 #interrupt-cells = <1>;
262 ranges;
263 interrupt-map-mask = <0 0 0 0>;
264 interrupt-map = <0 0 0 0 &mpic 65>;
265 marvell,pcie-port = <1>;
266 marvell,pcie-lane = <3>;
267 clocks = <&gateclk 12>;
268 status = "disabled";
269 };
270 pcie@9,0 {
271 device_type = "pci";
272 assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
273 reg = <0x4800 0 0 0 0>;
274 #address-cells = <3>;
275 #size-cells = <2>;
276 #interrupt-cells = <1>;
277 ranges;
278 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map = <0 0 0 0 &mpic 99>;
280 marvell,pcie-port = <2>;
281 marvell,pcie-lane = <0>;
282 clocks = <&gateclk 26>;
283 status = "disabled";
284 };
285
286 pcie@10,0 {
287 device_type = "pci";
288 assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
289 reg = <0x5000 0 0 0 0>;
290 #address-cells = <3>;
291 #size-cells = <2>;
292 #interrupt-cells = <1>;
293 ranges;
294 interrupt-map-mask = <0 0 0 0>;
295 interrupt-map = <0 0 0 0 &mpic 103>;
296 marvell,pcie-port = <3>;
297 marvell,pcie-lane = <0>;
298 clocks = <&gateclk 27>;
299 status = "disabled";
300 };
301 };
114 }; 302 };
115 }; 303 };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 3818a82176a2..9d04f04d4e39 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -139,5 +139,43 @@
139 usb@d0051000 { 139 usb@d0051000 {
140 status = "okay"; 140 status = "okay";
141 }; 141 };
142
143 devbus-bootcs@d0010400 {
144 status = "okay";
145 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
146
147 /* Device Bus parameters are required */
148
149 /* Read parameters */
150 devbus,bus-width = <8>;
151 devbus,turn-off-ps = <60000>;
152 devbus,badr-skew-ps = <0>;
153 devbus,acc-first-ps = <124000>;
154 devbus,acc-next-ps = <248000>;
155 devbus,rd-setup-ps = <0>;
156 devbus,rd-hold-ps = <0>;
157
158 /* Write parameters */
159 devbus,sync-enable = <0>;
160 devbus,wr-high-ps = <60000>;
161 devbus,wr-low-ps = <60000>;
162 devbus,ale-wr-ps = <60000>;
163
164 /* NOR 128 MiB */
165 nor@0 {
166 compatible = "cfi-flash";
167 reg = <0 0x8000000>;
168 bank-width = <2>;
169 };
170 };
171
172 pcie-controller {
173 status = "okay";
174 /* Internal mini-PCIe connector */
175 pcie@1,0 {
176 /* Port 0, Lane 0 */
177 status = "okay";
178 };
179 };
142 }; 180 };
143}; 181};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ca00d8326c87..29dfeb6d4a26 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -151,5 +151,11 @@
151 status = "disabled"; 151 status = "disabled";
152 }; 152 };
153 153
154 thermal@d00182b0 {
155 compatible = "marvell,armadaxp-thermal";
156 reg = <0xd00182b0 0x4
157 0xd00184d0 0x4>;
158 status = "okay";
159 };
154 }; 160 };
155}; 161};
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
new file mode 100644
index 000000000000..c7aebba4e8e7
--- /dev/null
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -0,0 +1,171 @@
1/*
2 * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based)
3 *
4 * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>,
5 * Robert Nelson <robertcnelson@gmail.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g25.dtsi"
11
12/ {
13 model = "Acme Systems Aria G25";
14 compatible = "acme,ariag25", "atmel,at91sam9x5ek",
15 "atmel,at91sam9x5", "atmel,at91sam9";
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 serial4 = &usart3;
23 serial5 = &uart0;
24 };
25
26 chosen {
27 bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
28 };
29
30 memory {
31 /* 128 MB, change this for 256 MB revision */
32 reg = <0x20000000 0x8000000>;
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 main_clock: clock@0 {
41 compatible = "atmel,osc", "fixed-clock";
42 clock-frequency = <12000000>;
43 };
44 };
45
46 ahb {
47 apb {
48 mmc0: mmc@f0008000 {
49 /* N.B. Aria has no SD card detect (CD), assumed present */
50
51 pinctrl-0 = <
52 &pinctrl_mmc0_slot0_clk_cmd_dat0
53 &pinctrl_mmc0_slot0_dat1_3>;
54 status = "okay";
55 slot@0 {
56 reg = <0>;
57 bus-width = <4>;
58 };
59 };
60
61 i2c0: i2c@f8010000 {
62 status = "okay";
63 };
64
65 i2c1: i2c@f8014000 {
66 status = "okay";
67 };
68
69 /* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */
70
71 usart0: serial@f801c000 {
72 pinctrl-0 = <&pinctrl_usart0
73 &pinctrl_usart0_rts
74 &pinctrl_usart0_cts>;
75 status = "okay";
76 };
77
78 usart1: serial@f8020000 {
79 pinctrl-0 = <&pinctrl_usart1
80 /* &pinctrl_usart1_rts */
81 /* &pinctrl_usart1_cts */
82 >;
83 status = "okay";
84 };
85
86 usart2: serial@f8024000 {
87 /* cannot activate RTS2+CTS2, clash with
88 * ethernet on PB0 and PB1 */
89 pinctrl-0 = <&pinctrl_usart2>;
90 status = "okay";
91 };
92
93 usart3: serial@f8028000 {
94 compatible = "atmel,at91sam9260-usart";
95 reg = <0xf8028000 0x200>;
96 interrupts = <8 4 5>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_usart3
99 /* &pinctrl_usart3_rts */
100 /* &pinctrl_usart3_cts */
101 >;
102 status = "okay";
103 };
104
105 macb0: ethernet@f802c000 {
106 phy-mode = "rmii";
107 /*
108 * following can be overwritten by bootloader:
109 * for example u-boot 'ftd set' command
110 */
111 local-mac-address = [00 00 00 00 00 00];
112 status = "okay";
113 };
114
115 uart0: serial@f8040000 {
116 compatible = "atmel,at91sam9260-usart";
117 reg = <0xf8040000 0x200>;
118 interrupts = <15 4 5>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart0>;
121 status = "okay";
122 };
123
124 adc0: adc@f804c000 {
125 status = "okay";
126 atmel,adc-channels-used = <0xf>;
127 atmel,adc-num-channels = <4>;
128 };
129
130 dbgu: serial@fffff200 {
131 status = "okay";
132 };
133
134 pinctrl@fffff400 {
135 w1_0 {
136 pinctrl_w1_0: w1_0-0 {
137 atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */
138 };
139 };
140 };
141 };
142
143 usb0: ohci@00600000 {
144 status = "okay";
145 num-ports = <3>;
146 };
147
148 usb1: ehci@00700000 {
149 status = "okay";
150 };
151 };
152
153 leds {
154 compatible = "gpio-leds";
155
156 /* little green LED in middle of Aria G25 module */
157 aria_led {
158 label = "aria_led";
159 gpios = <&pioB 8 0>; /* PB8 */
160 linux,default-trigger = "heartbeat";
161 };
162
163 };
164
165 onewire@0 {
166 compatible = "w1-gpio";
167 gpios = <&pioA 21 1>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_w1_0>;
170 };
171};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index b0268a5f4b4e..5d3ed5aafc69 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -29,6 +29,7 @@
29 gpio3 = &pioD; 29 gpio3 = &pioD;
30 tcb0 = &tcb0; 30 tcb0 = &tcb0;
31 tcb1 = &tcb1; 31 tcb1 = &tcb1;
32 i2c0 = &i2c0;
32 ssc0 = &ssc0; 33 ssc0 = &ssc0;
33 ssc1 = &ssc1; 34 ssc1 = &ssc1;
34 ssc2 = &ssc2; 35 ssc2 = &ssc2;
@@ -91,6 +92,17 @@
91 interrupts = <20 4 0 21 4 0 22 4 0>; 92 interrupts = <20 4 0 21 4 0 22 4 0>;
92 }; 93 };
93 94
95 i2c0: i2c@fffb8000 {
96 compatible = "atmel,at91rm9200-i2c";
97 reg = <0xfffb8000 0x4000>;
98 interrupts = <12 4 6>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_twi>;
101 #address-cells = <1>;
102 #size-cells = <0>;
103 status = "disabled";
104 };
105
94 mmc0: mmc@fffb4000 { 106 mmc0: mmc@fffb4000 {
95 compatible = "atmel,hsmci"; 107 compatible = "atmel,hsmci";
96 reg = <0xfffb4000 0x4000>; 108 reg = <0xfffb4000 0x4000>;
@@ -365,6 +377,20 @@
365 }; 377 };
366 }; 378 };
367 379
380 twi {
381 pinctrl_twi: twi-0 {
382 atmel,pins =
383 <0 25 0x1 0x2 /* PA25 periph A with multi drive */
384 0 26 0x1 0x2>; /* PA26 periph A with multi drive */
385 };
386
387 pinctrl_twi_gpio: twi_gpio-0 {
388 atmel,pins =
389 <0 25 0x0 0x2 /* PA25 GPIO with multi drive */
390 0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
391 };
392 };
393
368 pioA: gpio@fffff400 { 394 pioA: gpio@fffff400 {
369 compatible = "atmel,at91rm9200-gpio"; 395 compatible = "atmel,at91rm9200-gpio";
370 reg = <0xfffff400 0x200>; 396 reg = <0xfffff400 0x200>;
@@ -500,6 +526,8 @@
500 i2c-gpio,sda-open-drain; 526 i2c-gpio,sda-open-drain;
501 i2c-gpio,scl-open-drain; 527 i2c-gpio,scl-open-drain;
502 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 528 i2c-gpio,delay-us = <2>; /* ~100 kHz */
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_twi_gpio>;
503 #address-cells = <1>; 531 #address-cells = <1>;
504 #size-cells = <0>; 532 #size-cells = <0>;
505 status = "disabled"; 533 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 39253b9aedd1..70b5ccbac234 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -158,8 +158,8 @@
158 usart1 { 158 usart1 {
159 pinctrl_usart1: usart1-0 { 159 pinctrl_usart1: usart1-0 {
160 atmel,pins = 160 atmel,pins =
161 <2 6 0x1 0x1 /* PB6 periph A with pullup */ 161 <1 6 0x1 0x1 /* PB6 periph A with pullup */
162 2 7 0x1 0x0>; /* PB7 periph A */ 162 1 7 0x1 0x0>; /* PB7 periph A */
163 }; 163 };
164 164
165 pinctrl_usart1_rts: usart1_rts-0 { 165 pinctrl_usart1_rts: usart1_rts-0 {
@@ -194,18 +194,18 @@
194 usart3 { 194 usart3 {
195 pinctrl_usart3: usart3-0 { 195 pinctrl_usart3: usart3-0 {
196 atmel,pins = 196 atmel,pins =
197 <2 10 0x1 0x1 /* PB10 periph A with pullup */ 197 <1 10 0x1 0x1 /* PB10 periph A with pullup */
198 2 11 0x1 0x0>; /* PB11 periph A */ 198 1 11 0x1 0x0>; /* PB11 periph A */
199 }; 199 };
200 200
201 pinctrl_usart3_rts: usart3_rts-0 { 201 pinctrl_usart3_rts: usart3_rts-0 {
202 atmel,pins = 202 atmel,pins =
203 <3 8 0x2 0x0>; /* PB8 periph B */ 203 <2 8 0x2 0x0>; /* PC8 periph B */
204 }; 204 };
205 205
206 pinctrl_usart3_cts: usart3_cts-0 { 206 pinctrl_usart3_cts: usart3_cts-0 {
207 atmel,pins = 207 atmel,pins =
208 <3 10 0x2 0x0>; /* PB10 periph B */ 208 <2 10 0x2 0x0>; /* PC10 periph B */
209 }; 209 };
210 }; 210 };
211 211
@@ -220,8 +220,8 @@
220 uart1 { 220 uart1 {
221 pinctrl_uart1: uart1-0 { 221 pinctrl_uart1: uart1-0 {
222 atmel,pins = 222 atmel,pins =
223 <2 12 0x1 0x1 /* PB12 periph A with pullup */ 223 <1 12 0x1 0x1 /* PB12 periph A with pullup */
224 2 13 0x1 0x0>; /* PB13 periph A */ 224 1 13 0x1 0x0>; /* PB13 periph A */
225 }; 225 };
226 }; 226 };
227 227
@@ -524,6 +524,9 @@
524 atmel,adc-drdy-mask = <0x10000>; 524 atmel,adc-drdy-mask = <0x10000>;
525 atmel,adc-status-register = <0x1c>; 525 atmel,adc-status-register = <0x1c>;
526 atmel,adc-trigger-register = <0x04>; 526 atmel,adc-trigger-register = <0x04>;
527 atmel,adc-res = <8 10>;
528 atmel,adc-res-names = "lowres", "highres";
529 atmel,adc-use-res = "highres";
527 530
528 trigger@0 { 531 trigger@0 {
529 trigger-name = "timer-counter-0"; 532 trigger-name = "timer-counter-0";
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index a14e424b2e81..3b82d91e7fcc 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -165,8 +165,6 @@
165 165
166 gpio_keys { 166 gpio_keys {
167 compatible = "gpio-keys"; 167 compatible = "gpio-keys";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 168
171 left_click { 169 left_click {
172 label = "left_click"; 170 label = "left_click";
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index fbe7a7089c2a..28467fd6bf96 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -10,7 +10,7 @@
10 10
11/ { 11/ {
12 model = "Atmel AT91SAM9G15 SoC"; 12 model = "Atmel AT91SAM9G15 SoC";
13 compatible = "atmel, at91sam9g15, atmel,at91sam9x5"; 13 compatible = "atmel,at91sam9g15", "atmel,at91sam9x5";
14 14
15 ahb { 15 ahb {
16 apb { 16 apb {
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
index 86dd3f6d938f..5427b2dba87e 100644
--- a/arch/arm/boot/dts/at91sam9g15ek.dts
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -11,6 +11,6 @@
11/include/ "at91sam9x5ek.dtsi" 11/include/ "at91sam9x5ek.dtsi"
12 12
13/ { 13/ {
14 model = "Atmel AT91SAM9G25-EK"; 14 model = "Atmel AT91SAM9G15-EK";
15 compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16}; 16};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 23d1f468f27f..6a92c5baef8c 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -177,8 +177,6 @@
177 177
178 gpio_keys { 178 gpio_keys {
179 compatible = "gpio-keys"; 179 compatible = "gpio-keys";
180 #address-cells = <1>;
181 #size-cells = <0>;
182 180
183 btn3 { 181 btn3 {
184 label = "Button 3"; 182 label = "Button 3";
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 05a718fb83c4..5fd32df03f25 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -10,7 +10,7 @@
10 10
11/ { 11/ {
12 model = "Atmel AT91SAM9G25 SoC"; 12 model = "Atmel AT91SAM9G25 SoC";
13 compatible = "atmel, at91sam9g25, atmel,at91sam9x5"; 13 compatible = "atmel,at91sam9g25", "atmel,at91sam9x5";
14 14
15 ahb { 15 ahb {
16 apb { 16 apb {
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index c5ab16fba059..a1c511fecdc1 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -13,4 +13,13 @@
13/ { 13/ {
14 model = "Atmel AT91SAM9G25-EK"; 14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 ahb {
18 apb {
19 macb0: ethernet@f802c000 {
20 phy-mode = "rmii";
21 status = "okay";
22 };
23 };
24 };
16}; 25};
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index f9d14a722794..d6fa8af50724 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -10,7 +10,7 @@
10 10
11/ { 11/ {
12 model = "Atmel AT91SAM9G35 SoC"; 12 model = "Atmel AT91SAM9G35 SoC";
13 compatible = "atmel, at91sam9g35, atmel,at91sam9x5"; 13 compatible = "atmel,at91sam9g35", "atmel,at91sam9x5";
14 14
15 ahb { 15 ahb {
16 apb { 16 apb {
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
index 95944bdd798d..6f58ab8d21f5 100644
--- a/arch/arm/boot/dts/at91sam9g35ek.dts
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -13,4 +13,13 @@
13/ { 13/ {
14 model = "Atmel AT91SAM9G35-EK"; 14 model = "Atmel AT91SAM9G35-EK";
15 compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 ahb {
18 apb {
19 macb0: ethernet@f802c000 {
20 phy-mode = "rmii";
21 status = "okay";
22 };
23 };
24 };
16}; 25};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index cfdf429578b5..f8f7370e8669 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -502,6 +502,9 @@
502 atmel,adc-drdy-mask = <0x10000>; 502 atmel,adc-drdy-mask = <0x10000>;
503 atmel,adc-status-register = <0x1c>; 503 atmel,adc-status-register = <0x1c>;
504 atmel,adc-trigger-register = <0x08>; 504 atmel,adc-trigger-register = <0x08>;
505 atmel,adc-res = <8 10>;
506 atmel,adc-res-names = "lowres", "highres";
507 atmel,adc-use-res = "highres";
505 508
506 trigger@0 { 509 trigger@0 {
507 trigger-name = "external-rising"; 510 trigger-name = "external-rising";
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 92c52a7d70bc..51d9251b5bbe 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -172,8 +172,6 @@
172 172
173 gpio_keys { 173 gpio_keys {
174 compatible = "gpio-keys"; 174 compatible = "gpio-keys";
175 #address-cells = <1>;
176 #size-cells = <0>;
177 175
178 left_click { 176 left_click {
179 label = "left_click"; 177 label = "left_click";
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 34c842b1efb2..d30e48bd1e9d 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -114,8 +114,6 @@
114 114
115 gpio_keys { 115 gpio_keys {
116 compatible = "gpio-keys"; 116 compatible = "gpio-keys";
117 #address-cells = <1>;
118 #size-cells = <0>;
119 117
120 enter { 118 enter {
121 label = "Enter"; 119 label = "Enter";
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 54eb33ba6d22..9ac2bc2b4f07 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -10,7 +10,7 @@
10 10
11/ { 11/ {
12 model = "Atmel AT91SAM9X25 SoC"; 12 model = "Atmel AT91SAM9X25 SoC";
13 compatible = "atmel, at91sam9x25, atmel,at91sam9x5"; 13 compatible = "atmel,at91sam9x25", "atmel,at91sam9x5";
14 14
15 ahb { 15 ahb {
16 apb { 16 apb {
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
index af907eaa1f25..3b40d11d65e7 100644
--- a/arch/arm/boot/dts/at91sam9x25ek.dts
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -13,4 +13,18 @@
13/ { 13/ {
14 model = "Atmel AT91SAM9G25-EK"; 14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 ahb {
18 apb {
19 macb0: ethernet@f802c000 {
20 phy-mode = "rmii";
21 status = "okay";
22 };
23
24 macb1: ethernet@f8030000 {
25 phy-mode = "rmii";
26 status = "okay";
27 };
28 };
29 };
16}; 30};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index fb102d6126ce..ba67d83d17ac 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -10,7 +10,7 @@
10 10
11/ { 11/ {
12 model = "Atmel AT91SAM9X35 SoC"; 12 model = "Atmel AT91SAM9X35 SoC";
13 compatible = "atmel, at91sam9x35, atmel,at91sam9x5"; 13 compatible = "atmel,at91sam9x35", "atmel,at91sam9x5";
14 14
15 ahb { 15 ahb {
16 apb { 16 apb {
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
index 5ccb607b5414..6ad19a0d5424 100644
--- a/arch/arm/boot/dts/at91sam9x35ek.dts
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -13,4 +13,13 @@
13/ { 13/ {
14 model = "Atmel AT91SAM9X35-EK"; 14 model = "Atmel AT91SAM9X35-EK";
15 compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 ahb {
18 apb {
19 macb0: ethernet@f802c000 {
20 phy-mode = "rmii";
21 status = "okay";
22 };
23 };
24 };
16}; 25};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 347b438d47fa..640b3bbbb706 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -361,6 +361,54 @@
361 }; 361 };
362 }; 362 };
363 363
364 i2c0 {
365 pinctrl_i2c0: i2c0-0 {
366 atmel,pins =
367 <0 30 0x1 0x0 /* PA30 periph A I2C0 data */
368 0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */
369 };
370 };
371
372 i2c1 {
373 pinctrl_i2c1: i2c1-0 {
374 atmel,pins =
375 <2 0 0x3 0x0 /* PC0 periph C I2C1 data */
376 2 1 0x3 0x0>; /* PC1 periph C I2C1 clock */
377 };
378 };
379
380 i2c2 {
381 pinctrl_i2c2: i2c2-0 {
382 atmel,pins =
383 <1 4 0x2 0x0 /* PB4 periph B I2C2 data */
384 1 5 0x2 0x0>; /* PB5 periph B I2C2 clock */
385 };
386 };
387
388 i2c_gpio0 {
389 pinctrl_i2c_gpio0: i2c_gpio0-0 {
390 atmel,pins =
391 <0 30 0x0 0x2 /* PA30 gpio multidrive I2C0 data */
392 0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */
393 };
394 };
395
396 i2c_gpio1 {
397 pinctrl_i2c_gpio1: i2c_gpio1-0 {
398 atmel,pins =
399 <2 0 0x0 0x2 /* PC0 gpio multidrive I2C1 data */
400 2 1 0x0 0x2>; /* PC1 gpio multidrive I2C1 clock */
401 };
402 };
403
404 i2c_gpio2 {
405 pinctrl_i2c_gpio2: i2c_gpio2-0 {
406 atmel,pins =
407 <1 4 0x0 0x2 /* PB4 gpio multidrive I2C2 data */
408 1 5 0x0 0x2>; /* PB5 gpio multidrive I2C2 clock */
409 };
410 };
411
364 pioA: gpio@fffff400 { 412 pioA: gpio@fffff400 {
365 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 413 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
366 reg = <0xfffff400 0x200>; 414 reg = <0xfffff400 0x200>;
@@ -489,6 +537,8 @@
489 interrupts = <9 4 6>; 537 interrupts = <9 4 6>;
490 #address-cells = <1>; 538 #address-cells = <1>;
491 #size-cells = <0>; 539 #size-cells = <0>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_i2c0>;
492 status = "disabled"; 542 status = "disabled";
493 }; 543 };
494 544
@@ -498,6 +548,8 @@
498 interrupts = <10 4 6>; 548 interrupts = <10 4 6>;
499 #address-cells = <1>; 549 #address-cells = <1>;
500 #size-cells = <0>; 550 #size-cells = <0>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_i2c1>;
501 status = "disabled"; 553 status = "disabled";
502 }; 554 };
503 555
@@ -507,6 +559,8 @@
507 interrupts = <11 4 6>; 559 interrupts = <11 4 6>;
508 #address-cells = <1>; 560 #address-cells = <1>;
509 #size-cells = <0>; 561 #size-cells = <0>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_i2c2>;
510 status = "disabled"; 564 status = "disabled";
511 }; 565 };
512 566
@@ -523,6 +577,9 @@
523 atmel,adc-drdy-mask = <0x1000000>; 577 atmel,adc-drdy-mask = <0x1000000>;
524 atmel,adc-status-register = <0x30>; 578 atmel,adc-status-register = <0x30>;
525 atmel,adc-trigger-register = <0xc0>; 579 atmel,adc-trigger-register = <0xc0>;
580 atmel,adc-res = <8 10>;
581 atmel,adc-res-names = "lowres", "highres";
582 atmel,adc-use-res = "highres";
526 583
527 trigger@0 { 584 trigger@0 {
528 trigger-name = "external-rising"; 585 trigger-name = "external-rising";
@@ -569,6 +626,13 @@
569 pinctrl-0 = <&pinctrl_spi1>; 626 pinctrl-0 = <&pinctrl_spi1>;
570 status = "disabled"; 627 status = "disabled";
571 }; 628 };
629
630 rtc@fffffeb0 {
631 compatible = "atmel,at91rm9200-rtc";
632 reg = <0xfffffeb0 0x40>;
633 interrupts = <1 4 7>;
634 status = "disabled";
635 };
572 }; 636 };
573 637
574 nand0: nand@40000000 { 638 nand0: nand@40000000 {
@@ -617,6 +681,8 @@
617 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 681 i2c-gpio,delay-us = <2>; /* ~100 kHz */
618 #address-cells = <1>; 682 #address-cells = <1>;
619 #size-cells = <0>; 683 #size-cells = <0>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&pinctrl_i2c_gpio0>;
620 status = "disabled"; 686 status = "disabled";
621 }; 687 };
622 688
@@ -630,6 +696,8 @@
630 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 696 i2c-gpio,delay-us = <2>; /* ~100 kHz */
631 #address-cells = <1>; 697 #address-cells = <1>;
632 #size-cells = <0>; 698 #size-cells = <0>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pinctrl_i2c_gpio1>;
633 status = "disabled"; 701 status = "disabled";
634 }; 702 };
635 703
@@ -643,6 +711,8 @@
643 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 711 i2c-gpio,delay-us = <2>; /* ~100 kHz */
644 #address-cells = <1>; 712 #address-cells = <1>;
645 #size-cells = <0>; 713 #size-cells = <0>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&pinctrl_i2c_gpio2>;
646 status = "disabled"; 716 status = "disabled";
647 }; 717 };
648}; 718};
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 4027ac7e4502..347a74a857f6 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -24,6 +24,16 @@
24 }; 24 };
25 25
26 ahb { 26 ahb {
27 apb {
28 pinctrl@fffff400 {
29 1wire_cm {
30 pinctrl_1wire_cm: 1wire_cm-0 {
31 atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */
32 };
33 };
34 };
35 };
36
27 nand0: nand@40000000 { 37 nand0: nand@40000000 {
28 nand-bus-width = <8>; 38 nand-bus-width = <8>;
29 nand-ecc-mode = "hw"; 39 nand-ecc-mode = "hw";
@@ -74,4 +84,14 @@
74 gpios = <&pioD 21 0>; 84 gpios = <&pioD 21 0>;
75 }; 85 };
76 }; 86 };
87
88 1wire_cm {
89 compatible = "w1-gpio";
90 gpios = <&pioB 18 0>;
91 linux,open-drain;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_1wire_cm>;
94 status = "okay";
95 };
96
77}; 97};
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 09f5e667ca7a..1fa48d2bfd80 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -13,7 +13,7 @@
13 compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 13 compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
14 14
15 chosen { 15 chosen {
16 bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; 16 bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
17 }; 17 };
18 18
19 ahb { 19 ahb {
@@ -52,23 +52,10 @@
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54 54
55 macb0: ethernet@f802c000 {
56 phy-mode = "rmii";
57 status = "okay";
58 };
59
60 i2c0: i2c@f8010000 { 55 i2c0: i2c@f8010000 {
61 status = "okay"; 56 status = "okay";
62 }; 57 };
63 58
64 i2c1: i2c@f8014000 {
65 status = "okay";
66 };
67
68 i2c2: i2c@f8018000 {
69 status = "okay";
70 };
71
72 pinctrl@fffff400 { 59 pinctrl@fffff400 {
73 mmc0 { 60 mmc0 {
74 pinctrl_board_mmc0: mmc0-board { 61 pinctrl_board_mmc0: mmc0-board {
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 7e0481e2441a..f0052dccf9a8 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -34,6 +34,11 @@
34 reg = <0x7e100000 0x28>; 34 reg = <0x7e100000 0x28>;
35 }; 35 };
36 36
37 rng {
38 compatible = "brcm,bcm2835-rng";
39 reg = <0x7e104000 0x10>;
40 };
41
37 uart@20201000 { 42 uart@20201000 {
38 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; 43 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
39 reg = <0x7e201000 0x1000>; 44 reg = <0x7e201000 0x1000>;
@@ -64,6 +69,16 @@
64 #interrupt-cells = <2>; 69 #interrupt-cells = <2>;
65 }; 70 };
66 71
72 spi: spi@20204000 {
73 compatible = "brcm,bcm2835-spi";
74 reg = <0x7e204000 0x1000>;
75 interrupts = <2 22>;
76 clocks = <&clk_spi>;
77 #address-cells = <1>;
78 #size-cells = <0>;
79 status = "disabled";
80 };
81
67 i2c0: i2c@20205000 { 82 i2c0: i2c@20205000 {
68 compatible = "brcm,bcm2835-i2c"; 83 compatible = "brcm,bcm2835-i2c";
69 reg = <0x7e205000 0x1000>; 84 reg = <0x7e205000 0x1000>;
@@ -107,5 +122,12 @@
107 #clock-cells = <0>; 122 #clock-cells = <0>;
108 clock-frequency = <250000000>; 123 clock-frequency = <250000000>;
109 }; 124 };
125
126 clk_spi: spi {
127 compatible = "fixed-clock";
128 reg = <2>;
129 #clock-cells = <0>;
130 clock-frequency = <250000000>;
131 };
110 }; 132 };
111}; 133};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index f7509cafc377..6cab46849cdb 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -50,6 +50,11 @@
50 #clock-cells = <1>; 50 #clock-cells = <1>;
51 }; 51 };
52 52
53 thermal: thermal@d001c {
54 compatible = "marvell,dove-thermal";
55 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
56 };
57
53 uart0: serial@12000 { 58 uart0: serial@12000 {
54 compatible = "ns16550a"; 59 compatible = "ns16550a";
55 reg = <0x12000 0x100>; 60 reg = <0x12000 0x100>;
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index 1a9d0491cdce..f8db366c46ff 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx25.dtsi" 13#include "imx25.dtsi"
14 14
15/ { 15/ {
16 model = "Ka-Ro TX25"; 16 model = "Ka-Ro TX25";
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index a02a860afd18..f607ce520eda 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx25.dtsi" 13#include "imx25.dtsi"
14 14
15/ { 15/ {
16 model = "Freescale i.MX25 Product Development Kit"; 16 model = "Freescale i.MX25 Product Development Kit";
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 94f33059158a..d2550e0bca24 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -9,7 +9,7 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12/include/ "skeleton.dtsi" 12#include "skeleton.dtsi"
13 13
14/ { 14/ {
15 aliases { 15 aliases {
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index b464c807d8d9..ba4c6df08ece 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -13,7 +13,7 @@
13 */ 13 */
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "imx27.dtsi" 16#include "imx27.dtsi"
17 17
18/ { 18/ {
19 model = "Armadeus Systems APF27 module"; 19 model = "Armadeus Systems APF27 module";
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
new file mode 100644
index 000000000000..66b8e1c1b0be
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -0,0 +1,60 @@
1/*
2 * Copyright 2013 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/* APF27Dev is a docking board for the APF27 SOM */
13#include "imx27-apf27.dts"
14
15/ {
16 model = "Armadeus Systems APF27Dev docking/development board";
17 compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27";
18
19 gpio-keys {
20 compatible = "gpio-keys";
21
22 user-key {
23 label = "user";
24 gpios = <&gpio6 13 0>;
25 linux,code = <276>; /* BTN_EXTRA */
26 };
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 user {
33 label = "Heartbeat";
34 gpios = <&gpio6 14 0>;
35 linux,default-trigger = "heartbeat";
36 };
37 };
38};
39
40&cspi1 {
41 fsl,spi-num-chipselects = <1>;
42 cs-gpios = <&gpio4 28 1>;
43 status = "okay";
44};
45
46&cspi2 {
47 fsl,spi-num-chipselects = <3>;
48 cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>,
49 <&gpio2 17 1>;
50 status = "okay";
51};
52
53&i2c1 {
54 clock-frequency = <400000>;
55 status = "okay";
56};
57
58&i2c2 {
59 status = "okay";
60};
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 41cd1105608e..5ce89aa275df 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx27.dtsi" 13#include "imx27.dtsi"
14 14
15/ { 15/ {
16 model = "Freescale i.MX27 Product Development Kit"; 16 model = "Freescale i.MX27 Product Development Kit";
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 53b0ec0c228e..fe64e3a91df0 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx27.dtsi" 13#include "imx27.dtsi"
14 14
15/ { 15/ {
16 model = "Phytec pcm038"; 16 model = "Phytec pcm038";
@@ -71,3 +71,9 @@
71 #size-cells = <1>; 71 #size-cells = <1>;
72 }; 72 };
73}; 73};
74
75&nfc {
76 nand-bus-width = <8>;
77 nand-ecc-mode = "hw";
78 status = "okay";
79};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 5a82cb5707a8..ff4bd4873edf 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -9,7 +9,7 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12/include/ "skeleton.dtsi" 12#include "skeleton.dtsi"
13 13
14/ { 14/ {
15 aliases { 15 aliases {
@@ -60,14 +60,41 @@
60 60
61 wdog: wdog@10002000 { 61 wdog: wdog@10002000 {
62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
63 reg = <0x10002000 0x4000>; 63 reg = <0x10002000 0x1000>;
64 interrupts = <27>; 64 interrupts = <27>;
65 clocks = <&clks 0>;
66 };
67
68 gpt1: timer@10003000 {
69 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
70 reg = <0x10003000 0x1000>;
71 interrupts = <26>;
72 clocks = <&clks 46>, <&clks 61>;
73 clock-names = "ipg", "per";
74 };
75
76 gpt2: timer@10004000 {
77 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
78 reg = <0x10004000 0x1000>;
79 interrupts = <25>;
80 clocks = <&clks 45>, <&clks 61>;
81 clock-names = "ipg", "per";
82 };
83
84 gpt3: timer@10005000 {
85 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
86 reg = <0x10005000 0x1000>;
87 interrupts = <24>;
88 clocks = <&clks 44>, <&clks 61>;
89 clock-names = "ipg", "per";
65 }; 90 };
66 91
67 uart1: serial@1000a000 { 92 uart1: serial@1000a000 {
68 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 93 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
69 reg = <0x1000a000 0x1000>; 94 reg = <0x1000a000 0x1000>;
70 interrupts = <20>; 95 interrupts = <20>;
96 clocks = <&clks 81>, <&clks 61>;
97 clock-names = "ipg", "per";
71 status = "disabled"; 98 status = "disabled";
72 }; 99 };
73 100
@@ -75,6 +102,8 @@
75 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 102 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
76 reg = <0x1000b000 0x1000>; 103 reg = <0x1000b000 0x1000>;
77 interrupts = <19>; 104 interrupts = <19>;
105 clocks = <&clks 80>, <&clks 61>;
106 clock-names = "ipg", "per";
78 status = "disabled"; 107 status = "disabled";
79 }; 108 };
80 109
@@ -82,6 +111,8 @@
82 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 111 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
83 reg = <0x1000c000 0x1000>; 112 reg = <0x1000c000 0x1000>;
84 interrupts = <18>; 113 interrupts = <18>;
114 clocks = <&clks 79>, <&clks 61>;
115 clock-names = "ipg", "per";
85 status = "disabled"; 116 status = "disabled";
86 }; 117 };
87 118
@@ -89,6 +120,8 @@
89 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 120 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
90 reg = <0x1000d000 0x1000>; 121 reg = <0x1000d000 0x1000>;
91 interrupts = <17>; 122 interrupts = <17>;
123 clocks = <&clks 78>, <&clks 61>;
124 clock-names = "ipg", "per";
92 status = "disabled"; 125 status = "disabled";
93 }; 126 };
94 127
@@ -98,6 +131,8 @@
98 compatible = "fsl,imx27-cspi"; 131 compatible = "fsl,imx27-cspi";
99 reg = <0x1000e000 0x1000>; 132 reg = <0x1000e000 0x1000>;
100 interrupts = <16>; 133 interrupts = <16>;
134 clocks = <&clks 53>, <&clks 0>;
135 clock-names = "ipg", "per";
101 status = "disabled"; 136 status = "disabled";
102 }; 137 };
103 138
@@ -107,6 +142,8 @@
107 compatible = "fsl,imx27-cspi"; 142 compatible = "fsl,imx27-cspi";
108 reg = <0x1000f000 0x1000>; 143 reg = <0x1000f000 0x1000>;
109 interrupts = <15>; 144 interrupts = <15>;
145 clocks = <&clks 52>, <&clks 0>;
146 clock-names = "ipg", "per";
110 status = "disabled"; 147 status = "disabled";
111 }; 148 };
112 149
@@ -116,6 +153,7 @@
116 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; 153 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
117 reg = <0x10012000 0x1000>; 154 reg = <0x10012000 0x1000>;
118 interrupts = <12>; 155 interrupts = <12>;
156 clocks = <&clks 40>;
119 status = "disabled"; 157 status = "disabled";
120 }; 158 };
121 159
@@ -185,13 +223,33 @@
185 compatible = "fsl,imx27-cspi"; 223 compatible = "fsl,imx27-cspi";
186 reg = <0x10017000 0x1000>; 224 reg = <0x10017000 0x1000>;
187 interrupts = <6>; 225 interrupts = <6>;
226 clocks = <&clks 51>, <&clks 0>;
227 clock-names = "ipg", "per";
188 status = "disabled"; 228 status = "disabled";
189 }; 229 };
190 230
231 gpt4: timer@10019000 {
232 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
233 reg = <0x10019000 0x1000>;
234 interrupts = <4>;
235 clocks = <&clks 43>, <&clks 61>;
236 clock-names = "ipg", "per";
237 };
238
239 gpt5: timer@1001a000 {
240 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
241 reg = <0x1001a000 0x1000>;
242 interrupts = <3>;
243 clocks = <&clks 42>, <&clks 61>;
244 clock-names = "ipg", "per";
245 };
246
191 uart5: serial@1001b000 { 247 uart5: serial@1001b000 {
192 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 248 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
193 reg = <0x1001b000 0x1000>; 249 reg = <0x1001b000 0x1000>;
194 interrupts = <49>; 250 interrupts = <49>;
251 clocks = <&clks 77>, <&clks 61>;
252 clock-names = "ipg", "per";
195 status = "disabled"; 253 status = "disabled";
196 }; 254 };
197 255
@@ -199,6 +257,8 @@
199 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 257 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
200 reg = <0x1001c000 0x1000>; 258 reg = <0x1001c000 0x1000>;
201 interrupts = <48>; 259 interrupts = <48>;
260 clocks = <&clks 78>, <&clks 61>;
261 clock-names = "ipg", "per";
202 status = "disabled"; 262 status = "disabled";
203 }; 263 };
204 264
@@ -208,9 +268,17 @@
208 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; 268 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
209 reg = <0x1001d000 0x1000>; 269 reg = <0x1001d000 0x1000>;
210 interrupts = <1>; 270 interrupts = <1>;
271 clocks = <&clks 39>;
211 status = "disabled"; 272 status = "disabled";
212 }; 273 };
213 274
275 gpt6: timer@1001f000 {
276 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
277 reg = <0x1001f000 0x1000>;
278 interrupts = <2>;
279 clocks = <&clks 41>, <&clks 61>;
280 clock-names = "ipg", "per";
281 };
214 }; 282 };
215 283
216 aipi@10020000 { /* AIPI2 */ 284 aipi@10020000 { /* AIPI2 */
@@ -224,10 +292,19 @@
224 compatible = "fsl,imx27-fec"; 292 compatible = "fsl,imx27-fec";
225 reg = <0x1002b000 0x4000>; 293 reg = <0x1002b000 0x4000>;
226 interrupts = <50>; 294 interrupts = <50>;
295 clocks = <&clks 48>, <&clks 67>, <&clks 0>;
296 clock-names = "ipg", "ahb", "ptp";
227 status = "disabled"; 297 status = "disabled";
228 }; 298 };
299
300 clks: ccm@10027000{
301 compatible = "fsl,imx27-ccm";
302 reg = <0x10027000 0x1000>;
303 #clock-cells = <1>;
304 };
229 }; 305 };
230 306
307
231 nfc: nand@d8000000 { 308 nfc: nand@d8000000 {
232 #address-cells = <1>; 309 #address-cells = <1>;
233 #size-cells = <1>; 310 #size-cells = <1>;
@@ -235,6 +312,7 @@
235 compatible = "fsl,imx27-nand"; 312 compatible = "fsl,imx27-nand";
236 reg = <0xd8000000 0x1000>; 313 reg = <0xd8000000 0x1000>;
237 interrupts = <29>; 314 interrupts = <29>;
315 clocks = <&clks 54>;
238 status = "disabled"; 316 status = "disabled";
239 }; 317 };
240 }; 318 };
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index 9ac6f6ba1d64..2424abfc9c7b 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx31.dtsi" 13#include "imx31.dtsi"
14 14
15/ { 15/ {
16 model = "Buglabs i.MX31 Bug 1.x"; 16 model = "Buglabs i.MX31 Bug 1.x";
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index 454c2d175402..c5449257ad9a 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -9,7 +9,7 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12/include/ "skeleton.dtsi" 12#include "skeleton.dtsi"
13 13
14/ { 14/ {
15 aliases { 15 aliases {
@@ -101,5 +101,21 @@
101 #clock-cells = <1>; 101 #clock-cells = <1>;
102 }; 102 };
103 }; 103 };
104
105 aips@53f00000 { /* AIPS2 */
106 compatible = "fsl,aips-bus", "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 reg = <0x53f00000 0x100000>;
110 ranges;
111
112 gpt: timer@53f90000 {
113 compatible = "fsl,imx31-gpt";
114 reg = <0x53f90000 0x4000>;
115 interrupts = <29>;
116 clocks = <&clks 10>, <&clks 22>;
117 clock-names = "ipg", "per";
118 };
119 };
104 }; 120 };
105}; 121};
diff --git a/arch/arm/boot/dts/imx35-pinfunc.h b/arch/arm/boot/dts/imx35-pinfunc.h
new file mode 100644
index 000000000000..4911f2c405fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx35-pinfunc.h
@@ -0,0 +1,970 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX35_PINFUNC_H
11#define __DTS_IMX35_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
18#define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
19#define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
20#define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
21#define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
22#define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
23#define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
24#define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
25#define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
26#define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
27#define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0
28#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0
29#define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0
30#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0
31#define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0
32#define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0
33#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0
34#define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0
35#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0
36#define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0
37#define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0
38#define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0
39#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0
40#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0
41#define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0
42#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0
43#define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0
44#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0
45#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0
46#define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0
47#define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0
48#define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0
49#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0
50#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0
51#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0
52#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0
53#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0
54#define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0
55#define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0
56#define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0
57#define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0
58#define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0
59#define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0
60#define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0
61#define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0
62#define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0
63#define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0
64#define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0
65#define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0
66#define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0
67#define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0
68#define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0
69#define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0
70#define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0
71#define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0
72#define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0
73#define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0
74#define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0
75#define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0
76#define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0
77#define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0
78#define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0
79#define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0
80#define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0
81#define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0
82#define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0
83#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0
84#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0
85#define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0
86#define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0
87#define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0
88#define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0
89#define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0
90#define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0
91#define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0
92#define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0
93#define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0
94#define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0
95#define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0
96#define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0
97#define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0
98#define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0
99#define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0
100#define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0
101#define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0
102#define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0
103#define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0
104#define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0
105#define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0
106#define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0
107#define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0
108#define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0
109#define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0
110#define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0
111#define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0
112#define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0
113#define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0
114#define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0
115#define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0
116#define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0
117#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0
118#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0
119#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0
120#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0
121#define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0
122#define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0
123#define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0
124#define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0
125#define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0
126#define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0
127#define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0
128#define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0
129#define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0
130#define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0
131#define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0
132#define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0
133#define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0
134#define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0
135#define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1
136#define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0
137#define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0
138#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0
139#define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0
140#define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0
141#define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0
142#define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0
143#define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0
144#define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0
145#define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0
146#define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0
147#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0
148#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0
149#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0
150#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0
151#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0
152#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0
153#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0
154#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0
155#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0
156#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0
157#define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0
158#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0
159#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0
160#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0
161#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0
162#define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0
163#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0
164#define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0
165#define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0
166#define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0
167#define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0
168#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0
169#define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0
170#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0
171#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0
172#define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0
173#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0
174#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0
175#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0
176#define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0
177#define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0
178#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0
179#define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0
180#define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0
181#define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0
182#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0
183#define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0
184#define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0
185#define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0
186#define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0
187#define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0
188#define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0
189#define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0
190#define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0
191#define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0
192#define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0
193#define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0
194#define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0
195#define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0
196#define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0
197#define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0
198#define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0
199#define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0
200#define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0
201#define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1
202#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0
203#define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0
204#define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0
205#define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1
206#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0
207#define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0
208#define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0
209#define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1
210#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0
211#define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0
212#define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0
213#define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0
214#define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0
215#define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0
216#define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0
217#define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0
218#define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0
219#define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0
220#define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0
221#define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0
222#define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0
223#define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0
224#define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0
225#define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0
226#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0
227#define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0
228#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0
229#define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0
230#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0
231#define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0
232#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0
233#define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0
234#define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0
235#define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0
236#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0
237#define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0
238#define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0
239#define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0
240#define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0
241#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0
242#define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0
243#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0
244#define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0
245#define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0
246#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0
247#define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0
248#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0
249#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0
250#define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0
251#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0
252#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0
253#define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0
254#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0
255#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0
256#define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0
257#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0
258#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0
259#define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0
260#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0
261#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0
262#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0
263#define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0
264#define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1
265#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0
266#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0
267#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0
268#define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0
269#define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1
270#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0
271#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0
272#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0
273#define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0
274#define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0
275#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0
276#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0
277#define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0
278#define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0
279#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0
280#define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0
281#define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1
282#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0
283#define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0
284#define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1
285#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0
286#define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0
287#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0
288#define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0
289#define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0
290#define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1
291#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0
292#define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0
293#define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1
294#define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0
295#define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1
296#define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0
297#define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1
298#define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0
299#define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1
300#define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0
301#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0
302#define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0
303#define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0
304#define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1
305#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0
306#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0
307#define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1
308#define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0
309#define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0
310#define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0
311#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0
312#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0
313#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0
314#define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0
315#define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0
316#define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0
317#define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0
318#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0
319#define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1
320#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0
321#define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0
322#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0
323#define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0
324#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0
325#define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1
326#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0
327#define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0
328#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0
329#define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0
330#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0
331#define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1
332#define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0
333#define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1
334#define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2
335#define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0
336#define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0
337#define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0
338#define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0
339#define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1
340#define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0
341#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1
342#define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0
343#define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1
344#define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0
345#define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0
346#define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0
347#define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1
348#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0
349#define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0
350#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0
351#define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0
352#define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0
353#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0
354#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0
355#define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1
356#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1
357#define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0
358#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0
359#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0
360#define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0
361#define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1
362#define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0
363#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0
364#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0
365#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0
366#define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0
367#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0
368#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0
369#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0
370#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0
371#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0
372#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0
373#define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0
374#define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1
375#define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0
376#define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0
377#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0
378#define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0
379#define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1
380#define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0
381#define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0
382#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0
383#define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0
384#define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1
385#define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1
386#define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1
387#define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0
388#define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0
389#define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0
390#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0
391#define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0
392#define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1
393#define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1
394#define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1
395#define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0
396#define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0
397#define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0
398#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0
399#define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0
400#define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0
401#define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0
402#define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0
403#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2
404#define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0
405#define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0
406#define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0
407#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1
408#define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1
409#define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1
410#define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0
411#define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0
412#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0
413#define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0
414#define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0
415#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0
416#define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0
417#define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1
418#define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0
419#define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0
420#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0
421#define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0
422#define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0
423#define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0
424#define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0
425#define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0
426#define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0
427#define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0
428#define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0
429#define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0
430#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0
431#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0
432#define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0
433#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0
434#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1
435#define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0
436#define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0
437#define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1
438#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0
439#define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0
440#define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0
441#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0
442#define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0
443#define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0
444#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0
445#define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0
446#define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0
447#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0
448#define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0
449#define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0
450#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0
451#define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0
452#define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0
453#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0
454#define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0
455#define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0
456#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0
457#define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0
458#define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0
459#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0
460#define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0
461#define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0
462#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0
463#define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0
464#define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0
465#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0
466#define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0
467#define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0
468#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0
469#define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0
470#define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0
471#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0
472#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0
473#define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0
474#define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0
475#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0
476#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0
477#define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0
478#define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0
479#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0
480#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0
481#define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0
482#define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0
483#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0
484#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0
485#define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0
486#define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0
487#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0
488#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0
489#define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0
490#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0
491#define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0
492#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0
493#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0
494#define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0
495#define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0
496#define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0
497#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0
498#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0
499#define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0
500#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1
501#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1
502#define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0
503#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0
504#define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0
505#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0
506#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0
507#define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0
508#define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0
509#define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0
510#define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0
511#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0
512#define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0
513#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0
514#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0
515#define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0
516#define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0
517#define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0
518#define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0
519#define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0
520#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0
521#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0
522#define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0
523#define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0
524#define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0
525#define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0
526#define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0
527#define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0
528#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0
529#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0
530#define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0
531#define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0
532#define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0
533#define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0
534#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0
535#define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0
536#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0
537#define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0
538#define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0
539#define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0
540#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1
541#define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0
542#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0
543#define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0
544#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0
545#define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0
546#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0
547#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2
548#define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0
549#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0
550#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0
551#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0
552#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0
553#define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0
554#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0
555#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0
556#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0
557#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0
558#define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2
559#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0
560#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0
561#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0
562#define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2
563#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0
564#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0
565#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0
566#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0
567#define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1
568#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0
569#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0
570#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0
571#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0
572#define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1
573#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0
574#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0
575#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0
576#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0
577#define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2
578#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0
579#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0
580#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0
581#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2
582#define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2
583#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0
584#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0
585#define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0
586#define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0
587#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2
588#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0
589#define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2
590#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0
591#define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0
592#define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0
593#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0
594#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0
595#define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2
596#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0
597#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0
598#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0
599#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0
600#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0
601#define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2
602#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0
603#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0
604#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0
605#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0
606#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0
607#define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1
608#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0
609#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0
610#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0
611#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0
612#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0
613#define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1
614#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0
615#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0
616#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0
617#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0
618#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0
619#define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1
620#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0
621#define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0
622#define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2
623#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0
624#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2
625#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0
626#define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2
627#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0
628#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3
629#define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0
630#define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2
631#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0
632#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2
633#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0
634#define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1
635#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2
636#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0
637#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0
638#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1
639#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0
640#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1
641#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0
642#define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1
643#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3
644#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0
645#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0
646#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0
647#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1
648#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0
649#define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1
650#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0
651#define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0
652#define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1
653#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1
654#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0
655#define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1
656#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0
657#define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0
658#define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0
659#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1
660#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0
661#define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1
662#define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0
663#define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1
664#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0
665#define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1
666#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0
667#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0
668#define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0
669#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0
670#define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1
671#define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1
672#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0
673#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0
674#define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0
675#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1
676#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1
677#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0
678#define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1
679#define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1
680#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0
681#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0
682#define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0
683#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1
684#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0
685#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0
686#define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2
687#define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1
688#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0
689#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0
690#define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0
691#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1
692#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1
693#define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2
694#define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1
695#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0
696#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0
697#define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0
698#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1
699#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1
700#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0
701#define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2
702#define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1
703#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0
704#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0
705#define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0
706#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0
707#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1
708#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3
709#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0
710#define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1
711#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0
712#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0
713#define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0
714#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0
715#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1
716#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4
717#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0
718#define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1
719#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0
720#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0
721#define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0
722#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0
723#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1
724#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0
725#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0
726#define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1
727#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0
728#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0
729#define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0
730#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0
731#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1
732#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0
733#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0
734#define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1
735#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0
736#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0
737#define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0
738#define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1
739#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1
740#define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2
741#define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1
742#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0
743#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0
744#define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0
745#define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1
746#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1
747#define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1
748#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0
749#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0
750#define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0
751#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1
752#define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1
753#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0
754#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0
755#define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0
756#define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0
757#define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0
758#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0
759#define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1
760#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0
761#define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0
762#define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2
763#define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0
764#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0
765#define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1
766#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0
767#define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0
768#define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1
769#define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0
770#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0
771#define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1
772#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0
773#define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0
774#define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0
775#define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0
776#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0
777#define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1
778#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0
779#define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0
780#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2
781#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0
782#define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1
783#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0
784#define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0
785#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0
786#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0
787#define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1
788#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0
789#define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0
790#define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3
791#define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1
792#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0
793#define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0
794#define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3
795#define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1
796#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0
797#define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0
798#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2
799#define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2
800#define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1
801#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0
802#define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0
803#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2
804#define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2
805#define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1
806#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0
807#define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0
808#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3
809#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2
810#define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1
811#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0
812#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0
813#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3
814#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2
815#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1
816#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0
817#define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0
818#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2
819#define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2
820#define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1
821#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0
822#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0
823#define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0
824#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2
825#define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2
826#define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1
827#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0
828#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0
829#define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0
830#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2
831#define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2
832#define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0
833#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0
834#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0
835#define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0
836#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2
837#define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2
838#define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0
839#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0
840#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0
841#define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0
842#define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0
843#define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0
844#define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1
845#define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0
846#define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1
847#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0
848#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1
849#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3
850#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1
851#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3
852#define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1
853#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5
854#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0
855#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0
856#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1
857#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0
858#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0
859#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3
860#define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1
861#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4
862#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0
863#define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0
864#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1
865#define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2
866#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1
867#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3
868#define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1
869#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0
870#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0
871#define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0
872#define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1
873#define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0
874#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1
875#define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3
876#define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1
877#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0
878#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0
879#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0
880#define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0
881#define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0
882#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1
883#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2
884#define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1
885#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0
886#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0
887#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0
888#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0
889#define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0
890#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1
891#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2
892#define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1
893#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0
894#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0
895#define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0
896#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3
897#define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0
898#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1
899#define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1
900#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0
901#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0
902#define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0
903#define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0
904#define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0
905#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1
906#define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1
907#define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0
908#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0
909#define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0
910#define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2
911#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1
912#define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1
913#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0
914#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0
915#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0
916#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2
917#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4
918#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1
919#define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1
920#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3
921#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0
922#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0
923#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3
924#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1
925#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1
926#define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0
927#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5
928#define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0
929#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3
930#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0
931#define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1
932#define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0
933#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0
934#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0
935#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4
936#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0
937#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2
938#define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1
939#define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0
940#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0
941#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0
942#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4
943#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1
944#define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1
945#define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0
946#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0
947#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0
948#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3
949#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1
950#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1
951#define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0
952#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0
953#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3
954#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1
955#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1
956#define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0
957#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0
958#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3
959#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1
960#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1
961#define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0
962#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0
963#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3
964#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1
965#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1
966#define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0
967#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0
968#define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0
969
970#endif /* __DTS_IMX35_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 92d3a66a69e2..2bcf6981d490 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -15,7 +15,7 @@
15 */ 15 */
16 16
17/dts-v1/; 17/dts-v1/;
18/include/ "imx51.dtsi" 18#include "imx51.dtsi"
19 19
20/ { 20/ {
21 model = "Armadeus Systems APF51 module"; 21 model = "Armadeus Systems APF51 module";
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
new file mode 100644
index 000000000000..123fe84e0e8c
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -0,0 +1,97 @@
1/*
2 * Copyright 2013 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/* APF51Dev is a docking board for the APF51 SOM */
13#include "imx51-apf51.dts"
14
15/ {
16 model = "Armadeus Systems APF51Dev docking/development board";
17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
18
19 gpio-keys {
20 compatible = "gpio-keys";
21
22 user-key {
23 label = "user";
24 gpios = <&gpio1 3 0>;
25 linux,code = <256>; /* BTN_0 */
26 };
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 user {
33 label = "Heartbeat";
34 gpios = <&gpio1 2 0>;
35 linux,default-trigger = "heartbeat";
36 };
37 };
38};
39
40&ecspi1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_ecspi1_1>;
43 fsl,spi-num-chipselects = <2>;
44 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
45 status = "okay";
46};
47
48&ecspi2 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_ecspi2_1>;
51 fsl,spi-num-chipselects = <2>;
52 cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>;
53 status = "okay";
54};
55
56&esdhc1 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_esdhc1_1>;
59 cd-gpios = <&gpio2 29 0>;
60 bus-width = <4>;
61 status = "okay";
62};
63
64&esdhc2 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_esdhc2_1>;
67 bus-width = <4>;
68 non-removable;
69 status = "okay";
70};
71
72&i2c2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_i2c2_2>;
75 status = "okay";
76};
77
78&iomuxc {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_hog>;
81
82 hog {
83 pinctrl_hog: hoggrp {
84 fsl,pins = <
85 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
86 MX51_PAD_EIM_EB3__GPIO2_23 0x0C5
87 MX51_PAD_EIM_CS4__GPIO2_29 0x100
88 MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
89 MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
90 MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
91 MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
92 MX51_PAD_GPIO1_2__GPIO1_2 0x0C5
93 MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
94 >;
95 };
96 };
97};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index aab6e43219af..6dd9486c755b 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx51.dtsi" 14#include "imx51.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX51 Babbage Board"; 17 model = "Freescale i.MX51 Babbage Board";
@@ -222,13 +222,13 @@
222 hog { 222 hog {
223 pinctrl_hog: hoggrp { 223 pinctrl_hog: hoggrp {
224 fsl,pins = < 224 fsl,pins = <
225 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */ 225 MX51_PAD_GPIO1_0__SD1_CD 0x20d5
226 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */ 226 MX51_PAD_GPIO1_1__SD1_WP 0x20d5
227 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */ 227 MX51_PAD_GPIO1_5__GPIO1_5 0x100
228 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */ 228 MX51_PAD_GPIO1_6__GPIO1_6 0x100
229 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */ 229 MX51_PAD_EIM_A27__GPIO2_21 0x5
230 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ 230 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
231 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ 231 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
232 >; 232 >;
233 }; 233 };
234 }; 234 };
diff --git a/arch/arm/boot/dts/imx51-pinfunc.h b/arch/arm/boot/dts/imx51-pinfunc.h
new file mode 100644
index 000000000000..9eb92abaeb6d
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-pinfunc.h
@@ -0,0 +1,773 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX51_PINFUNC_H
11#define __DTS_IMX51_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
18#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
19#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
20#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
21#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
22#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
23#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
24#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
25#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
26#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
27#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
28#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0
29#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0
30#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0
31#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0
32#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
33#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
34#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
35#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0
36#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0
37#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0
38#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0
39#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
40#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0
41#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
42#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0
43#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0
44#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0
45#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
46#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0
47#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0
48#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0
49#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0
50#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
51#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
52#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0
53#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0
54#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0
55#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
56#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0
57#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0
58#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0
59#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0
60#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0
61#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0
62#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0
63#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0
64#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0
65#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0
66#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
67#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0
68#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0
69#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0
70#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0
71#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
72#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0
73#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0
74#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0
75#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
76#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
77#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0
78#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0
79#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0
80#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0
81#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0
82#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
83#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0
84#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0
85#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0
86#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0
87#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0
88#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0
89#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0
90#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0
91#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0
92#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0
93#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0
94#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0
95#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0
96#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0
97#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0
98#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0
99#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0
100#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0
101#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0
102#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0
103#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0
104#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0
105#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0
106#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0
107#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0
108#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0
109#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0
110#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0
111#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0
112#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0
113#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0
114#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0
115#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0
116#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0
117#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0
118#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0
119#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0
120#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0
121#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0
122#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0
123#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0
124#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0
125#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0
126#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0
127#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0
128#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0
129#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0
130#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0
131#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0
132#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0
133#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0
134#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0
135#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0
136#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0
137#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0
138#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0
139#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0
140#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0
141#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0
142#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0
143#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0
144#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0
145#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0
146#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0
147#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0
148#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0
149#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0
150#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0
151#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0
152#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0
153#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0
154#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0
155#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0
156#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0
157#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0
158#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0
159#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0
160#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1
161#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0
162#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0
163#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0
164#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0
165#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0
166#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1
167#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0
168#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0
169#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0
170#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0
171#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0
172#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1
173#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0
174#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0
175#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0
176#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0
177#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0
178#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1
179#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0
180#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0
181#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0
182#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0
183#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0
184#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0
185#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0
186#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0
187#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0
188#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0
189#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0
190#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0
191#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0
192#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0
193#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0
194#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0
195#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0
196#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0
197#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0
198#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0
199#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0
200#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0
201#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0
202#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0
203#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0
204#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0
205#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0
206#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0
207#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0
208#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0
209#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0
210#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0
211#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0
212#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0
213#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0
214#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0
215#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0
216#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0
217#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0
218#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0
219#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0
220#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0
221#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0
222#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0
223#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0
224#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0
225#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0
226#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0
227#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0
228#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0
229#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0
230#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0
231#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0
232#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0
233#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0
234#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0
235#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0
236#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0
237#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0
238#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0
239#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0
240#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0
241#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0
242#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0
243#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0
244#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0
245#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0
246#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0
247#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0
248#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0
249#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0
250#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0
251#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0
252#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0
253#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0
254#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0
255#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0
256#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0
257#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0
258#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0
259#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0
260#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0
261#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0
262#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0
263#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0
264#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0
265#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0
266#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0
267#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0
268#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0
269#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0
270#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0
271#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0
272#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0
273#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0
274#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0
275#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0
276#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0
277#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0
278#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0
279#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0
280#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0
281#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0
282#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0
283#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0
284#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0
285#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0
286#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0
287#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0
288#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0
289#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0
290#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0
291#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0
292#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0
293#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0
294#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0
295#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0
296#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1
297#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0
298#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0
299#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0
300#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0
301#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0
302#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0
303#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0
304#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0
305#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1
306#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0
307#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0
308#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0
309#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1
310#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0
311#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0
312#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0
313#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0
314#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1
315#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0
316#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0
317#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0
318#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0
319#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1
320#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0
321#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0
322#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0
323#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0
324#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0
325#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0
326#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0
327#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0
328#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0
329#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0
330#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0
331#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0
332#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0
333#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0
334#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0
335#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0
336#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0
337#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0
338#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0
339#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0
340#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0
341#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0
342#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0
343#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0
344#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0
345#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0
346#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0
347#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0
348#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0
349#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0
350#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0
351#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0
352#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0
353#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0
354#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0
355#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0
356#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0
357#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0
358#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0
359#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0
360#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1
361#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0
362#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0
363#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0
364#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0
365#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0
366#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0
367#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0
368#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0
369#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0
370#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0
371#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0
372#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0
373#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0
374#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0
375#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0
376#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0
377#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0
378#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0
379#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0
380#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0
381#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0
382#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0
383#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0
384#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0
385#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0
386#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0
387#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0
388#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0
389#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0
390#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0
391#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0
392#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0
393#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0
394#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0
395#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0
396#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0
397#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0
398#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0
399#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0
400#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0
401#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0
402#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0
403#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0
404#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0
405#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2
406#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0
407#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0
408#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0
409#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0
410#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0
411#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0
412#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0
413#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1
414#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1
415#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0
416#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0
417#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1
418#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0
419#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0
420#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1
421#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0
422#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0
423#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1
424#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0
425#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0
426#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0
427#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0
428#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1
429#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0
430#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0
431#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0
432#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0
433#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0
434#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0
435#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0
436#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0
437#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0
438#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0
439#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0
440#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2
441#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0
442#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0
443#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0
444#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0
445#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0
446#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0
447#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4
448#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0
449#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0
450#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0
451#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0
452#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0
453#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0
454#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0
455#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0
456#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0
457#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0
458#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0
459#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0
460#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0
461#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0
462#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0
463#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0
464#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0
465#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0
466#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1
467#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0
468#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0
469#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0
470#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4
471#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1
472#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0
473#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0
474#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0
475#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1
476#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0
477#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2
478#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0
479#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1
480#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0
481#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2
482#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0
483#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0
484#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0
485#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6
486#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0
487#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0
488#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0
489#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0
490#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0
491#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0
492#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0
493#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0
494#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0
495#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4
496#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0
497#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0
498#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0
499#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0
500#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0
501#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5
502#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0
503#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0
504#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0
505#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0
506#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0
507#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0
508#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0
509#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1
510#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0
511#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0
512#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0
513#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1
514#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0
515#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0
516#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0
517#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0
518#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0
519#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0
520#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1
521#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0
522#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1
523#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0
524#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1
525#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0
526#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0
527#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0
528#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1
529#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1
530#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0
531#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1
532#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0
533#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1
534#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1
535#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0
536#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0
537#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0
538#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1
539#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 0x2c8 0x6c8 0x000 0x2 0x0
540#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0
541#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0
542#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0
543#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1
544#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0
545#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0
546#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0
547#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0
548#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0
549#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0
550#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0
551#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0
552#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0
553#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0
554#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0
555#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0
556#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0
557#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0
558#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0
559#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0
560#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0
561#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0
562#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0
563#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0
564#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0
565#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0
566#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0
567#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0
568#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0
569#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0
570#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0
571#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0
572#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0
573#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0
574#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0
575#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0
576#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0
577#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0
578#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0
579#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0
580#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0
581#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0
582#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0
583#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0
584#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0
585#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0
586#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0
587#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0
588#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0
589#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0
590#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0
591#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0
592#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0
593#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0
594#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0
595#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0
596#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0
597#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0
598#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0
599#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0
600#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0
601#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0
602#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1
603#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1
604#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0
605#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0
606#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1
607#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0
608#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1
609#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0
610#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0
611#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0
612#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1
613#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0
614#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1
615#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0
616#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1
617#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0
618#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1
619#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0
620#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1
621#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1
622#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8
623#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1
624#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0
625#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1
626#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1
627#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0
628#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1
629#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0
630#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0
631#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0
632#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0
633#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0
634#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0
635#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0
636#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1
637#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1
638#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0
639#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0
640#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0
641#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1
642#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1
643#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0
644#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0
645#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0
646#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1
647#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1
648#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1
649#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0
650#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0
651#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0
652#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1
653#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0
654#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0
655#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1
656#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1
657#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1
658#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1
659#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0
660#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1
661#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0
662#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1
663#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1
664#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0
665#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1
666#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1
667#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1
668#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0
669#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1
670#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1
671#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1
672#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0
673#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1
674#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1
675#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1
676#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0
677#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0
678#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0
679#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1
680#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1
681#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2
682#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0
683#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1
684#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2
685#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0
686#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2
687#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1
688#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0
689#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0
690#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0
691#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0
692#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0
693#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2
694#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0
695#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0
696#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0
697#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0
698#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0
699#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2
700#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0
701#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0
702#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0
703#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0
704#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0
705#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2
706#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1
707#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0
708#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0
709#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0
710#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0
711#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2
712#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0
713#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0
714#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0
715#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0
716#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0
717#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0
718#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3
719#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2
720#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0
721#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3
722#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2
723#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0
724#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3
725#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0
726#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0
727#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0
728#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0
729#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0
730#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0
731#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0
732#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0
733#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1
734#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0
735#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0
736#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0
737#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0
738#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3
739#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1
740#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0
741#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0
742#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3
743#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1
744#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0
745#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0
746#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0
747#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1
748#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1
749#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0
750#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0
751#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0
752#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0
753#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0
754#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0
755#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0
756#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0
757#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0
758#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0
759#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0
760#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0
761#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0
762#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2
763#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0
764#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0
765#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0
766#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0
767#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0
768#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0
769#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0
770#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0
771#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0
772
773#endif /* __DTS_IMX51_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index fcf035bf7c5a..21bb786c5b31 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -10,7 +10,8 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13/include/ "skeleton.dtsi" 13#include "skeleton.dtsi"
14#include "imx51-pinfunc.h"
14 15
15/ { 16/ {
16 aliases { 17 aliases {
@@ -55,6 +56,24 @@
55 }; 56 };
56 }; 57 };
57 58
59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 cpu@0 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a8";
65 reg = <0>;
66 clock-latency = <61036>; /* two CLK32 periods */
67 clocks = <&clks 24>;
68 clock-names = "cpu";
69 operating-points = <
70 /* kHz uV (No regulator support) */
71 160000 0
72 800000 0
73 >;
74 };
75 };
76
58 soc { 77 soc {
59 #address-cells = <1>; 78 #address-cells = <1>;
60 #size-cells = <1>; 79 #size-cells = <1>;
@@ -67,6 +86,9 @@
67 compatible = "fsl,imx51-ipu"; 86 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>; 87 reg = <0x40000000 0x20000000>;
69 interrupts = <11 10>; 88 interrupts = <11 10>;
89 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
90 clock-names = "bus", "di0", "di1";
91 resets = <&src 2>;
70 }; 92 };
71 93
72 aips@70000000 { /* AIPS1 */ 94 aips@70000000 { /* AIPS1 */
@@ -244,6 +266,14 @@
244 status = "disabled"; 266 status = "disabled";
245 }; 267 };
246 268
269 gpt: timer@73fa0000 {
270 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
271 reg = <0x73fa0000 0x4000>;
272 interrupts = <39>;
273 clocks = <&clks 36>, <&clks 41>;
274 clock-names = "ipg", "per";
275 };
276
247 iomuxc: iomuxc@73fa8000 { 277 iomuxc: iomuxc@73fa8000 {
248 compatible = "fsl,imx51-iomuxc"; 278 compatible = "fsl,imx51-iomuxc";
249 reg = <0x73fa8000 0x4000>; 279 reg = <0x73fa8000 0x4000>;
@@ -251,10 +281,10 @@
251 audmux { 281 audmux {
252 pinctrl_audmux_1: audmuxgrp-1 { 282 pinctrl_audmux_1: audmuxgrp-1 {
253 fsl,pins = < 283 fsl,pins = <
254 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ 284 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
255 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ 285 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
256 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ 286 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
257 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ 287 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
258 >; 288 >;
259 }; 289 };
260 }; 290 };
@@ -262,46 +292,46 @@
262 fec { 292 fec {
263 pinctrl_fec_1: fecgrp-1 { 293 pinctrl_fec_1: fecgrp-1 {
264 fsl,pins = < 294 fsl,pins = <
265 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ 295 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
266 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ 296 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
267 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ 297 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
268 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ 298 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
269 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ 299 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
270 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ 300 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
271 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ 301 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
272 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ 302 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
273 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ 303 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
274 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ 304 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
275 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ 305 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
276 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ 306 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
277 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ 307 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
278 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ 308 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
279 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ 309 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
280 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ 310 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
281 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ 311 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
282 >; 312 >;
283 }; 313 };
284 314
285 pinctrl_fec_2: fecgrp-2 { 315 pinctrl_fec_2: fecgrp-2 {
286 fsl,pins = < 316 fsl,pins = <
287 589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */ 317 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
288 592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */ 318 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
289 594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */ 319 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
290 596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */ 320 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
291 598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */ 321 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
292 602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */ 322 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
293 604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */ 323 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
294 609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */ 324 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
295 618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */ 325 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
296 623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */ 326 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
297 628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */ 327 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
298 634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */ 328 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
299 639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */ 329 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
300 644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */ 330 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
301 649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */ 331 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
302 653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */ 332 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
303 657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */ 333 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
304 662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */ 334 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
305 >; 335 >;
306 }; 336 };
307 }; 337 };
@@ -309,9 +339,19 @@
309 ecspi1 { 339 ecspi1 {
310 pinctrl_ecspi1_1: ecspi1grp-1 { 340 pinctrl_ecspi1_1: ecspi1grp-1 {
311 fsl,pins = < 341 fsl,pins = <
312 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ 342 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
313 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ 343 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
314 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ 344 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
345 >;
346 };
347 };
348
349 ecspi2 {
350 pinctrl_ecspi2_1: ecspi2grp-1 {
351 fsl,pins = <
352 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
353 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
354 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
315 >; 355 >;
316 }; 356 };
317 }; 357 };
@@ -319,12 +359,12 @@
319 esdhc1 { 359 esdhc1 {
320 pinctrl_esdhc1_1: esdhc1grp-1 { 360 pinctrl_esdhc1_1: esdhc1grp-1 {
321 fsl,pins = < 361 fsl,pins = <
322 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ 362 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
323 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ 363 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
324 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ 364 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
325 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ 365 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
326 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ 366 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
327 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ 367 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
328 >; 368 >;
329 }; 369 };
330 }; 370 };
@@ -332,12 +372,12 @@
332 esdhc2 { 372 esdhc2 {
333 pinctrl_esdhc2_1: esdhc2grp-1 { 373 pinctrl_esdhc2_1: esdhc2grp-1 {
334 fsl,pins = < 374 fsl,pins = <
335 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ 375 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
336 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ 376 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
337 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ 377 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
338 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ 378 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
339 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ 379 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
340 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ 380 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
341 >; 381 >;
342 }; 382 };
343 }; 383 };
@@ -345,8 +385,15 @@
345 i2c2 { 385 i2c2 {
346 pinctrl_i2c2_1: i2c2grp-1 { 386 pinctrl_i2c2_1: i2c2grp-1 {
347 fsl,pins = < 387 fsl,pins = <
348 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ 388 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
349 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ 389 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
390 >;
391 };
392
393 pinctrl_i2c2_2: i2c2grp-2 {
394 fsl,pins = <
395 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
396 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
350 >; 397 >;
351 }; 398 };
352 }; 399 };
@@ -354,32 +401,32 @@
354 ipu_disp1 { 401 ipu_disp1 {
355 pinctrl_ipu_disp1_1: ipudisp1grp-1 { 402 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
356 fsl,pins = < 403 fsl,pins = <
357 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */ 404 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
358 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */ 405 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
359 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */ 406 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
360 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */ 407 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
361 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */ 408 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
362 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */ 409 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
363 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */ 410 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
364 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */ 411 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
365 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */ 412 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
366 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */ 413 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
367 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */ 414 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
368 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */ 415 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
369 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */ 416 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
370 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */ 417 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
371 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */ 418 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
372 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */ 419 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
373 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */ 420 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
374 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */ 421 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
375 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */ 422 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
376 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */ 423 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
377 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */ 424 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
378 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */ 425 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
379 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */ 426 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
380 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */ 427 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
381 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */ 428 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
382 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */ 429 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
383 >; 430 >;
384 }; 431 };
385 }; 432 };
@@ -387,26 +434,62 @@
387 ipu_disp2 { 434 ipu_disp2 {
388 pinctrl_ipu_disp2_1: ipudisp2grp-1 { 435 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
389 fsl,pins = < 436 fsl,pins = <
390 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */ 437 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
391 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */ 438 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
392 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */ 439 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
393 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */ 440 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
394 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */ 441 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
395 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */ 442 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
396 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */ 443 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
397 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */ 444 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
398 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */ 445 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
399 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */ 446 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
400 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */ 447 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
401 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */ 448 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
402 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */ 449 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
403 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */ 450 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
404 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */ 451 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
405 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */ 452 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
406 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */ 453 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
407 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */ 454 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
408 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */ 455 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
409 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */ 456 MX51_PAD_DI_GP4__DI2_PIN15 0x5
457 >;
458 };
459 };
460
461 pata {
462 pinctrl_pata_1: patagrp-1 {
463 fsl,pins = <
464 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
465 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
466 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
467 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
468 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
469 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
470 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
471 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
472 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
473 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
474 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
475 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
476 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
477 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
478 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
479 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
480 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
481 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
482 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
483 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
484 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
485 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
486 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
487 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
488 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
489 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
490 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
491 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
492 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
410 >; 493 >;
411 }; 494 };
412 }; 495 };
@@ -414,10 +497,10 @@
414 uart1 { 497 uart1 {
415 pinctrl_uart1_1: uart1grp-1 { 498 pinctrl_uart1_1: uart1grp-1 {
416 fsl,pins = < 499 fsl,pins = <
417 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ 500 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
418 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ 501 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
419 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ 502 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
420 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ 503 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
421 >; 504 >;
422 }; 505 };
423 }; 506 };
@@ -425,8 +508,8 @@
425 uart2 { 508 uart2 {
426 pinctrl_uart2_1: uart2grp-1 { 509 pinctrl_uart2_1: uart2grp-1 {
427 fsl,pins = < 510 fsl,pins = <
428 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ 511 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
429 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ 512 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
430 >; 513 >;
431 }; 514 };
432 }; 515 };
@@ -434,17 +517,17 @@
434 uart3 { 517 uart3 {
435 pinctrl_uart3_1: uart3grp-1 { 518 pinctrl_uart3_1: uart3grp-1 {
436 fsl,pins = < 519 fsl,pins = <
437 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ 520 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
438 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ 521 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
439 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ 522 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
440 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ 523 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
441 >; 524 >;
442 }; 525 };
443 526
444 pinctrl_uart3_2: uart3grp-2 { 527 pinctrl_uart3_2: uart3grp-2 {
445 fsl,pins = < 528 fsl,pins = <
446 434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */ 529 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
447 430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */ 530 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
448 >; 531 >;
449 }; 532 };
450 }; 533 };
@@ -452,14 +535,14 @@
452 kpp { 535 kpp {
453 pinctrl_kpp_1: kppgrp-1 { 536 pinctrl_kpp_1: kppgrp-1 {
454 fsl,pins = < 537 fsl,pins = <
455 438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */ 538 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
456 439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */ 539 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
457 440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */ 540 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
458 441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */ 541 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
459 442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */ 542 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
460 444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */ 543 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
461 446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */ 544 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
462 448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */ 545 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
463 >; 546 >;
464 }; 547 };
465 }; 548 };
@@ -501,6 +584,12 @@
501 status = "disabled"; 584 status = "disabled";
502 }; 585 };
503 586
587 src: src@73fd0000 {
588 compatible = "fsl,imx51-src";
589 reg = <0x73fd0000 0x4000>;
590 #reset-cells = <1>;
591 };
592
504 clks: ccm@73fd4000{ 593 clks: ccm@73fd4000{
505 compatible = "fsl,imx51-ccm"; 594 compatible = "fsl,imx51-ccm";
506 reg = <0x73fd4000 0x4000>; 595 reg = <0x73fd4000 0x4000>;
@@ -591,6 +680,14 @@
591 status = "disabled"; 680 status = "disabled";
592 }; 681 };
593 682
683 pata: pata@83fe0000 {
684 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
685 reg = <0x83fe0000 0x4000>;
686 interrupts = <70>;
687 clocks = <&clks 161>;
688 status = "disabled";
689 };
690
594 ssi3: ssi@83fe8000 { 691 ssi3: ssi@83fe8000 {
595 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 692 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
596 reg = <0x83fe8000 0x4000>; 693 reg = <0x83fe8000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index e049fd0319e8..174f86938c89 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx53.dtsi" 14#include "imx53.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX53 Automotive Reference Design Board"; 17 model = "Freescale i.MX53 Automotive Reference Design Board";
@@ -112,40 +112,40 @@
112 hog { 112 hog {
113 pinctrl_hog: hoggrp { 113 pinctrl_hog: hoggrp {
114 fsl,pins = < 114 fsl,pins = <
115 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */ 115 MX53_PAD_GPIO_1__GPIO1_1 0x80000000
116 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */ 116 MX53_PAD_GPIO_9__GPIO1_9 0x80000000
117 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */ 117 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
118 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */ 118 MX53_PAD_GPIO_10__GPIO4_0 0x80000000
119 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */ 119 MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000
120 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */ 120 MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000
121 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */ 121 MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000
122 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */ 122 MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000
123 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */ 123 MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000
124 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */ 124 MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000
125 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */ 125 MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000
126 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */ 126 MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000
127 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */ 127 MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000
128 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */ 128 MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000
129 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */ 129 MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000
130 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */ 130 MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000
131 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */ 131 MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000
132 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */ 132 MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000
133 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */ 133 MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000
134 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */ 134 MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000
135 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */ 135 MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000
136 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */ 136 MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000
137 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */ 137 MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000
138 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */ 138 MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000
139 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */ 139 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000
140 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */ 140 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000
141 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */ 141 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000
142 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */ 142 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000
143 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */ 143 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000
144 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */ 144 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000
145 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */ 145 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000
146 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */ 146 MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
147 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */ 147 MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
148 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */ 148 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
149 >; 149 >;
150 }; 150 };
151 }; 151 };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 85a89b52f9b8..801fda728ed6 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx53.dtsi" 14#include "imx53.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX53 Evaluation Kit"; 17 model = "Freescale i.MX53 Evaluation Kit";
@@ -82,14 +82,14 @@
82 hog { 82 hog {
83 pinctrl_hog: hoggrp { 83 pinctrl_hog: hoggrp {
84 fsl,pins = < 84 fsl,pins = <
85 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ 85 MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
86 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ 86 MX53_PAD_EIM_D19__GPIO3_19 0x80000000
87 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ 87 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
88 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ 88 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
89 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ 89 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
90 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */ 90 MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
91 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ 91 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
92 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ 92 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
93 >; 93 >;
94 }; 94 };
95 }; 95 };
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 468c0a1d48d9..445a01119cc5 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx53-tqma53.dtsi" 14#include "imx53-tqma53.dtsi"
15 15
16/ { 16/ {
17 model = "TQ MBa53 starter kit"; 17 model = "TQ MBa53 starter kit";
@@ -21,51 +21,57 @@
21&iomuxc { 21&iomuxc {
22 lvds1 { 22 lvds1 {
23 pinctrl_lvds1_1: lvds1-grp1 { 23 pinctrl_lvds1_1: lvds1-grp1 {
24 fsl,pins = <730 0x10000 /* LVDS0_TX3 */ 24 fsl,pins = <
25 732 0x10000 /* LVDS0_CLK */ 25 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
26 734 0x10000 /* LVDS0_TX2 */ 26 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
27 736 0x10000 /* LVDS0_TX1 */ 27 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
28 738 0x10000>; /* LVDS0_TX0 */ 28 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
29 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
30 >;
29 }; 31 };
30 32
31 pinctrl_lvds1_2: lvds1-grp2 { 33 pinctrl_lvds1_2: lvds1-grp2 {
32 fsl,pins = <720 0x10000 /* LVDS1_TX3 */ 34 fsl,pins = <
33 722 0x10000 /* LVDS1_TX2 */ 35 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
34 724 0x10000 /* LVDS1_CLK */ 36 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
35 726 0x10000 /* LVDS1_TX1 */ 37 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
36 728 0x10000>; /* LVDS1_TX0 */ 38 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
39 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
40 >;
37 }; 41 };
38 }; 42 };
39 43
40 disp1 { 44 disp1 {
41 pinctrl_disp1_1: disp1-grp1 { 45 pinctrl_disp1_1: disp1-grp1 {
42 fsl,pins = <689 0x10000 /* DISP1_DRDY */ 46 fsl,pins = <
43 482 0x10000 /* DISP1_HSYNC */ 47 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */
44 489 0x10000 /* DISP1_VSYNC */ 48 MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */
45 515 0x10000 /* DISP1_DAT_22 */ 49 MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */
46 523 0x10000 /* DISP1_DAT_23 */ 50 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
47 545 0x10000 /* DISP1_DAT_21 */ 51 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
48 553 0x10000 /* DISP1_DAT_20 */ 52 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
49 558 0x10000 /* DISP1_DAT_19 */ 53 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
50 564 0x10000 /* DISP1_DAT_18 */ 54 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
51 570 0x10000 /* DISP1_DAT_17 */ 55 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
52 575 0x10000 /* DISP1_DAT_16 */ 56 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
53 580 0x10000 /* DISP1_DAT_15 */ 57 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
54 585 0x10000 /* DISP1_DAT_14 */ 58 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
55 590 0x10000 /* DISP1_DAT_13 */ 59 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
56 595 0x10000 /* DISP1_DAT_12 */ 60 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
57 628 0x10000 /* DISP1_DAT_11 */ 61 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
58 634 0x10000 /* DISP1_DAT_10 */ 62 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
59 639 0x10000 /* DISP1_DAT_9 */ 63 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
60 644 0x10000 /* DISP1_DAT_8 */ 64 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000
61 649 0x10000 /* DISP1_DAT_7 */ 65 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000
62 654 0x10000 /* DISP1_DAT_6 */ 66 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000
63 659 0x10000 /* DISP1_DAT_5 */ 67 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000
64 664 0x10000 /* DISP1_DAT_4 */ 68 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000
65 669 0x10000 /* DISP1_DAT_3 */ 69 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000
66 674 0x10000 /* DISP1_DAT_2 */ 70 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000
67 679 0x10000 /* DISP1_DAT_1 */ 71 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000
68 684 0x10000>; /* DISP1_DAT_0 */ 72 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000
73 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000
74 >;
69 }; 75 };
70 }; 76 };
71}; 77};
diff --git a/arch/arm/boot/dts/imx53-pinfunc.h b/arch/arm/boot/dts/imx53-pinfunc.h
new file mode 100644
index 000000000000..aec406bc65eb
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-pinfunc.h
@@ -0,0 +1,1189 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX53_PINFUNC_H
11#define __DTS_IMX53_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
18#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
19#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
20#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
21#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
22#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
23#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
24#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
25#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
26#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
27#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0
28#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0
29#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0
30#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0
31#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0
32#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0
33#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0
34#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0
35#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1
36#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0
37#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0
38#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0
39#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0
40#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0
41#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0
42#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0
43#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0
44#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0
45#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0
46#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0
47#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0
48#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1
49#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0
50#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0
51#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0
52#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0
53#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0
54#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0
55#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0
56#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0
57#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0
58#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0
59#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0
60#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0
61#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0
62#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0
63#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0
64#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0
65#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0
66#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0
67#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0
68#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0
69#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0
70#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0
71#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0
72#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0
73#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0
74#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0
75#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0
76#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0
77#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0
78#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0
79#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0
80#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0
81#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0
82#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0
83#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0
84#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0
85#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0
86#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0
87#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0
88#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0
89#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0
90#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0
91#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0
92#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0
93#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0
94#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0
95#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0
96#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0
97#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0
98#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0
99#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0
100#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0
101#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0
102#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0
103#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0
104#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0
105#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0
106#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0
107#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0
108#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0
109#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0
110#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0
111#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0
112#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0
113#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0
114#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0
115#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0
116#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0
117#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0
118#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0
119#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0
120#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0
121#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0
122#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0
123#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0
124#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0
125#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0
126#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0
127#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0
128#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0
129#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0
130#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0
131#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0
132#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0
133#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0
134#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0
135#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0
136#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0
137#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0
138#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0
139#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0
140#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0
141#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0
142#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0
143#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0
144#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0
145#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0
146#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0
147#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0
148#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0
149#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0
150#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0
151#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0
152#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0
153#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0
154#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0
155#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0
156#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0
157#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0
158#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0
159#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0
160#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0
161#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0
162#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0
163#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0
164#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0
165#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0
166#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0
167#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0
168#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0
169#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0
170#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0
171#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0
172#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0
173#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0
174#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0
175#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0
176#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0
177#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0
178#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0
179#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0
180#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0
181#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0
182#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0
183#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0
184#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0
185#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0
186#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0
187#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0
188#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0
189#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0
190#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0
191#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0
192#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0
193#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0
194#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0
195#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0
196#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0
197#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0
198#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0
199#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0
200#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0
201#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0
202#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0
203#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0
204#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0
205#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0
206#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0
207#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0
208#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0
209#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0
210#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0
211#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0
212#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0
213#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0
214#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0
215#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0
216#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0
217#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0
218#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0
219#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0
220#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0
221#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0
222#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0
223#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0
224#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0
225#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0
226#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0
227#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0
228#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0
229#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1
230#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0
231#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0
232#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0
233#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0
234#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0
235#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0
236#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0
237#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1
238#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0
239#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0
240#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0
241#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0
242#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0
243#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0
244#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0
245#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1
246#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0
247#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0
248#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0
249#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0
250#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0
251#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0
252#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1
253#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0
254#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0
255#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0
256#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0
257#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0
258#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0
259#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0
260#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1
261#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0
262#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0
263#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0
264#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0
265#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0
266#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0
267#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1
268#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0
269#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0
270#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0
271#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0
272#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0
273#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0
274#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1
275#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0
276#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0
277#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0
278#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0
279#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0
280#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0
281#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1
282#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0
283#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0
284#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0
285#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0
286#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0
287#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0
288#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1
289#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0
290#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0
291#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0
292#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0
293#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0
294#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0
295#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0
296#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0
297#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0
298#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0
299#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0
300#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0
301#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0
302#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0
303#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0
304#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0
305#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0
306#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0
307#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0
308#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0
309#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0
310#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0
311#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0
312#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0
313#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0
314#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0
315#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1
316#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2
317#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0
318#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0
319#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0
320#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0
321#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0
322#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0
323#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0
324#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2
325#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0
326#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0
327#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0
328#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0
329#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0
330#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0
331#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0
332#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2
333#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0
334#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0
335#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0
336#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0
337#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0
338#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0
339#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0
340#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2
341#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0
342#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0
343#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0
344#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0
345#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0
346#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0
347#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0
348#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1
349#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0
350#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0
351#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0
352#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0
353#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0
354#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0
355#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0
356#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1
357#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0
358#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0
359#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0
360#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0
361#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0
362#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0
363#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0
364#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1
365#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0
366#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0
367#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0
368#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0
369#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0
370#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0
371#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1
372#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1
373#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0
374#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0
375#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0
376#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0
377#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0
378#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0
379#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0
380#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0
381#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0
382#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0
383#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0
384#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0
385#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0
386#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3
387#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0
388#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0
389#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0
390#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0
391#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0
392#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0
393#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0
394#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0
395#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0
396#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0
397#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0
398#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0
399#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0
400#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3
401#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0
402#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0
403#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0
404#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0
405#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0
406#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0
407#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0
408#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0
409#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0
410#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0
411#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0
412#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0
413#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0
414#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0
415#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0
416#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0
417#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0
418#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0
419#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0
420#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0
421#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2
422#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0
423#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0
424#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0
425#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0
426#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0
427#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0
428#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0
429#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0
430#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0
431#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0
432#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0
433#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0
434#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0
435#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0
436#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0
437#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1
438#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0
439#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0
440#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0
441#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0
442#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0
443#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0
444#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3
445#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1
446#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0
447#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0
448#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0
449#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0
450#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3
451#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1
452#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0
453#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0
454#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0
455#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0
456#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3
457#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0
458#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0
459#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0
460#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0
461#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1
462#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3
463#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0
464#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0
465#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0
466#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0
467#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0
468#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0
469#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2
470#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0
471#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0
472#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0
473#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0
474#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0
475#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0
476#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0
477#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1
478#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0
479#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1
480#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0
481#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0
482#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0
483#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0
484#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0
485#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1
486#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1
487#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1
488#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0
489#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0
490#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0
491#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0
492#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1
493#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0
494#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0
495#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0
496#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0
497#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0
498#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0
499#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0
500#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0
501#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0
502#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0
503#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0
504#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1
505#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0
506#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0
507#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0
508#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0
509#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0
510#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0
511#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0
512#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1
513#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1
514#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1
515#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0
516#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0
517#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0
518#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0
519#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1
520#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1
521#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1
522#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1
523#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0
524#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0
525#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0
526#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0
527#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0
528#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0
529#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0
530#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0
531#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0
532#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0
533#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0
534#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0
535#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1
536#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0
537#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0
538#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0
539#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0
540#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0
541#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0
542#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0
543#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0
544#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1
545#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1
546#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1
547#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0
548#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0
549#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0
550#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0
551#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1
552#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0
553#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2
554#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0
555#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0
556#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0
557#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0
558#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0
559#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0
560#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0
561#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0
562#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0
563#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0
564#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1
565#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0
566#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0
567#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3
568#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0
569#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0
570#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0
571#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0
572#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0
573#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0
574#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0
575#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0
576#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0
577#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0
578#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0
579#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0
580#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0
581#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0
582#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0
583#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0
584#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0
585#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0
586#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0
587#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0
588#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0
589#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0
590#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0
591#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0
592#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0
593#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0
594#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0
595#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0
596#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0
597#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0
598#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0
599#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0
600#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0
601#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0
602#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0
603#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0
604#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0
605#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0
606#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0
607#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0
608#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0
609#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0
610#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0
611#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0
612#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0
613#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0
614#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0
615#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0
616#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0
617#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0
618#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0
619#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0
620#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0
621#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0
622#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2
623#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0
624#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0
625#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0
626#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2
627#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0
628#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0
629#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0
630#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2
631#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0
632#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0
633#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0
634#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0
635#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2
636#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0
637#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0
638#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0
639#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0
640#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1
641#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0
642#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0
643#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0
644#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0
645#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0
646#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0
647#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0
648#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0
649#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0
650#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0
651#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0
652#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0
653#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0
654#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0
655#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0
656#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0
657#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0
658#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0
659#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0
660#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0
661#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0
662#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0
663#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0
664#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0
665#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0
666#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0
667#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0
668#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0
669#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0
670#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0
671#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0
672#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0
673#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0
674#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0
675#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0
676#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0
677#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0
678#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0
679#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0
680#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0
681#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0
682#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0
683#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0
684#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0
685#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0
686#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0
687#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0
688#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0
689#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0
690#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0
691#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0
692#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0
693#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0
694#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0
695#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0
696#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0
697#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0
698#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0
699#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0
700#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0
701#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0
702#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0
703#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0
704#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0
705#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0
706#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0
707#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1
708#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0
709#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0
710#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0
711#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0
712#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1
713#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0
714#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0
715#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0
716#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1
717#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0
718#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0
719#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0
720#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1
721#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0
722#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0
723#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0
724#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0
725#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0
726#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0
727#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0
728#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0
729#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0
730#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0
731#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0
732#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0
733#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0
734#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0
735#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0
736#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0
737#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0
738#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0
739#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0
740#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0
741#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0
742#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0
743#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0
744#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0
745#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0
746#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0
747#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0
748#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0
749#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0
750#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0
751#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0
752#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0
753#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0
754#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0
755#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0
756#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0
757#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0
758#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0
759#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0
760#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0
761#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0
762#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0
763#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0
764#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0
765#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0
766#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0
767#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0
768#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0
769#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0
770#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0
771#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0
772#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0
773#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0
774#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0
775#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0
776#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0
777#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0
778#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0
779#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0
780#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0
781#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0
782#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0
783#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0
784#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0
785#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0
786#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0
787#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0
788#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0
789#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0
790#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0
791#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0
792#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0
793#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0
794#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0
795#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0
796#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1
797#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0
798#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0
799#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1
800#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0
801#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0
802#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0
803#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0
804#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0
805#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0
806#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0
807#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0
808#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0
809#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0
810#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0
811#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1
812#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0
813#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0
814#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0
815#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0
816#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0
817#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0
818#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0
819#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1
820#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0
821#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0
822#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0
823#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0
824#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0
825#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0
826#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0
827#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0
828#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0
829#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0
830#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0
831#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1
832#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0
833#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0
834#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0
835#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0
836#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0
837#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0
838#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0
839#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0
840#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1
841#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0
842#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0
843#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0
844#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0
845#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0
846#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0
847#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0
848#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0
849#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3
850#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0
851#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0
852#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0
853#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0
854#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0
855#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0
856#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0
857#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0
858#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3
859#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0
860#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0
861#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0
862#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0
863#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0
864#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0
865#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0
866#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0
867#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0
868#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0
869#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3
870#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1
871#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0
872#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0
873#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0
874#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0
875#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0
876#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0
877#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0
878#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0
879#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0
880#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0
881#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3
882#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1
883#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0
884#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0
885#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0
886#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0
887#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0
888#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0
889#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0
890#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0
891#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0
892#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0
893#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0
894#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0
895#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0
896#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0
897#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5
898#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0
899#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0
900#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0
901#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0
902#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0
903#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0
904#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0
905#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3
906#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0
907#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0
908#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0
909#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0
910#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0
911#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0
912#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0
913#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0
914#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0
915#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0
916#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0
917#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0
918#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0
919#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0
920#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0
921#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0
922#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0
923#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0
924#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0
925#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0
926#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0
927#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0
928#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0
929#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0
930#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0
931#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0
932#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0
933#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0
934#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0
935#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0
936#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0
937#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0
938#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0
939#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0
940#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0
941#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0
942#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0
943#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0
944#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0
945#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0
946#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0
947#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0
948#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0
949#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0
950#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0
951#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0
952#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0
953#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0
954#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0
955#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0
956#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0
957#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0
958#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0
959#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0
960#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0
961#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0
962#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0
963#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0
964#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0
965#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0
966#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0
967#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0
968#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0
969#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0
970#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0
971#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0
972#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0
973#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0
974#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0
975#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0
976#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0
977#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0
978#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0
979#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0
980#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0
981#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0
982#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0
983#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0
984#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0
985#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0
986#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0
987#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0
988#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0
989#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0
990#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0
991#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0
992#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0
993#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0
994#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0
995#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0
996#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0
997#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0
998#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0
999#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0
1000#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0
1001#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0
1002#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0
1003#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0
1004#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0
1005#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0
1006#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0
1007#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0
1008#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0
1009#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0
1010#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0
1011#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0
1012#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0
1013#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0
1014#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0
1015#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2
1016#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0
1017#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0
1018#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0
1019#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0
1020#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3
1021#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1
1022#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0
1023#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0
1024#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0
1025#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2
1026#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0
1027#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0
1028#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0
1029#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0
1030#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0
1031#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0
1032#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2
1033#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0
1034#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0
1035#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0
1036#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0
1037#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0
1038#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0
1039#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2
1040#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0
1041#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0
1042#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0
1043#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0
1044#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0
1045#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0
1046#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2
1047#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0
1048#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0
1049#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0
1050#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0
1051#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2
1052#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1
1053#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3
1054#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0
1055#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0
1056#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0
1057#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1
1058#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1
1059#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3
1060#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0
1061#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0
1062#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0
1063#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1
1064#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1
1065#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3
1066#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0
1067#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0
1068#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0
1069#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1
1070#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1
1071#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3
1072#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0
1073#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0
1074#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0
1075#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1
1076#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1
1077#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4
1078#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0
1079#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0
1080#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0
1081#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1
1082#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1
1083#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3
1084#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0
1085#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0
1086#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0
1087#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3
1088#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0
1089#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0
1090#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0
1091#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0
1092#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0
1093#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1
1094#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0
1095#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2
1096#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0
1097#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0
1098#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0
1099#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0
1100#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0
1101#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1
1102#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0
1103#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2
1104#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0
1105#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0
1106#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0
1107#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1
1108#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0
1109#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1
1110#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0
1111#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1
1112#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0
1113#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0
1114#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0
1115#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1
1116#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2
1117#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1
1118#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0
1119#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1
1120#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0
1121#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0
1122#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0
1123#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0
1124#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2
1125#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1
1126#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0
1127#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2
1128#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0
1129#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0
1130#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0
1131#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0
1132#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2
1133#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1
1134#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0
1135#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2
1136#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0
1137#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0
1138#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0
1139#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0
1140#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0
1141#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1
1142#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0
1143#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2
1144#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0
1145#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0
1146#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0
1147#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2
1148#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1
1149#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1
1150#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0
1151#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0
1152#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0
1153#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0
1154#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1
1155#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0
1156#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1
1157#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1
1158#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0
1159#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0
1160#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2
1161#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5
1162#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0
1163#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0
1164#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1
1165#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1
1166#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0
1167#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0
1168#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0
1169#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1
1170#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2
1171#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0
1172#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1
1173#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0
1174#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1
1175#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1
1176#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0
1177#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0
1178#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0
1179#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0
1180#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1
1181#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0
1182#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1
1183#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1
1184#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0
1185#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1
1186#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0
1187#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0
1188
1189#endif /* __DTS_IMX53_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 05cc5620436b..8f0e9ae0e3e6 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx53.dtsi" 14#include "imx53.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX53 Quick Start Board"; 17 model = "Freescale i.MX53 Quick Start Board";
@@ -110,21 +110,21 @@
110 hog { 110 hog {
111 pinctrl_hog: hoggrp { 111 pinctrl_hog: hoggrp {
112 fsl,pins = < 112 fsl,pins = <
113 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */ 113 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
114 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */ 114 MX53_PAD_GPIO_8__GPIO1_8 0x80000000
115 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ 115 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
116 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ 116 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
117 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ 117 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
118 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ 118 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
119 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ 119 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
120 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ 120 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
121 1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */ 121 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
122 >; 122 >;
123 }; 123 };
124 124
125 led_pin_gpio7_7: led_gpio7_7@0 { 125 led_pin_gpio7_7: led_gpio7_7@0 {
126 fsl,pins = < 126 fsl,pins = <
127 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ 127 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
128 >; 128 >;
129 }; 129 };
130 }; 130 };
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 995554c324b8..a9b6e10de0a5 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx53.dtsi" 14#include "imx53.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX53 Smart Mobile Reference Design Board"; 17 model = "Freescale i.MX53 Smart Mobile Reference Design Board";
@@ -107,13 +107,13 @@
107 hog { 107 hog {
108 pinctrl_hog: hoggrp { 108 pinctrl_hog: hoggrp {
109 fsl,pins = < 109 fsl,pins = <
110 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ 110 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
111 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ 111 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
112 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ 112 MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
113 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ 113 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
114 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ 114 MX53_PAD_EIM_D19__GPIO3_19 0x80000000
115 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */ 115 MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000
116 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ 116 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
117 >; 117 >;
118 }; 118 };
119 }; 119 };
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index 8278ec5ec222..38bed3ed7c1a 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -10,7 +10,7 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13/include/ "imx53.dtsi" 13#include "imx53.dtsi"
14 14
15/ { 15/ {
16 model = "TQ TQMa53"; 16 model = "TQ TQMa53";
@@ -72,11 +72,11 @@
72 i2s { 72 i2s {
73 pinctrl_i2s_1: i2s-grp1 { 73 pinctrl_i2s_1: i2s-grp1 {
74 fsl,pins = < 74 fsl,pins = <
75 1 0x10000 /* I2S_MCLK */ 75 MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */
76 10 0x10000 /* I2S_SCLK */ 76 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */
77 17 0x10000 /* I2S_DOUT */ 77 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */
78 23 0x10000 /* I2S_LRCLK*/ 78 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
79 30 0x10000 /* I2S_DIN */ 79 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */
80 >; 80 >;
81 }; 81 };
82 }; 82 };
@@ -84,16 +84,16 @@
84 hog { 84 hog {
85 pinctrl_hog: hoggrp { 85 pinctrl_hog: hoggrp {
86 fsl,pins = < 86 fsl,pins = <
87 610 0x10000 /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/ 87 MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */
88 711 0x10000 /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/ 88 MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
89 873 0x10000 /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/ 89 MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */
90 878 0x10000 /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/ 90 MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */
91 922 0x10000 /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/ 91 MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */
92 928 0x10000 /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/ 92 MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */
93 982 0x10000 /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/ 93 MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */
94 989 0x10000 /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/ 94 MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */
95 1069 0x10000 /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/ 95 MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */
96 1093 0x10000 /* MX53_PAD_GPIO_3__GPIO1_3 */ 96 MX53_PAD_GPIO_3__GPIO1_3 0x10000
97 >; 97 >;
98 }; 98 };
99 }; 99 };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index d05aa215c7f9..845982eaac22 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -10,7 +10,8 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13/include/ "skeleton.dtsi" 13#include "skeleton.dtsi"
14#include "imx53-pinfunc.h"
14 15
15/ { 16/ {
16 aliases { 17 aliases {
@@ -72,6 +73,9 @@
72 compatible = "fsl,imx53-ipu"; 73 compatible = "fsl,imx53-ipu";
73 reg = <0x18000000 0x080000000>; 74 reg = <0x18000000 0x080000000>;
74 interrupts = <11 10>; 75 interrupts = <11 10>;
76 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
77 clock-names = "bus", "di0", "di1";
78 resets = <&src 2>;
75 }; 79 };
76 80
77 aips@50000000 { /* AIPS1 */ 81 aips@50000000 { /* AIPS1 */
@@ -242,6 +246,14 @@
242 status = "disabled"; 246 status = "disabled";
243 }; 247 };
244 248
249 gpt: timer@53fa0000 {
250 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
251 reg = <0x53fa0000 0x4000>;
252 interrupts = <39>;
253 clocks = <&clks 36>, <&clks 41>;
254 clock-names = "ipg", "per";
255 };
256
245 iomuxc: iomuxc@53fa8000 { 257 iomuxc: iomuxc@53fa8000 {
246 compatible = "fsl,imx53-iomuxc"; 258 compatible = "fsl,imx53-iomuxc";
247 reg = <0x53fa8000 0x4000>; 259 reg = <0x53fa8000 0x4000>;
@@ -249,10 +261,10 @@
249 audmux { 261 audmux {
250 pinctrl_audmux_1: audmuxgrp-1 { 262 pinctrl_audmux_1: audmuxgrp-1 {
251 fsl,pins = < 263 fsl,pins = <
252 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ 264 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
253 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ 265 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
254 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ 266 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
255 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ 267 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
256 >; 268 >;
257 }; 269 };
258 }; 270 };
@@ -260,16 +272,16 @@
260 fec { 272 fec {
261 pinctrl_fec_1: fecgrp-1 { 273 pinctrl_fec_1: fecgrp-1 {
262 fsl,pins = < 274 fsl,pins = <
263 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ 275 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
264 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ 276 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
265 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ 277 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
266 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ 278 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
267 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ 279 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
268 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ 280 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
269 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ 281 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
270 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ 282 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
271 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ 283 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
272 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ 284 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
273 >; 285 >;
274 }; 286 };
275 }; 287 };
@@ -277,27 +289,27 @@
277 csi { 289 csi {
278 pinctrl_csi_1: csigrp-1 { 290 pinctrl_csi_1: csigrp-1 {
279 fsl,pins = < 291 fsl,pins = <
280 286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */ 292 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
281 291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */ 293 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
282 280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */ 294 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
283 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ 295 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
284 409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */ 296 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
285 402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */ 297 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
286 395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */ 298 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
287 388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */ 299 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
288 381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */ 300 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
289 374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */ 301 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
290 367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */ 302 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
291 360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */ 303 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
292 352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */ 304 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
293 344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */ 305 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
294 336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */ 306 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
295 328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */ 307 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
296 320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */ 308 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
297 312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */ 309 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
298 304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */ 310 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
299 296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */ 311 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
300 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ 312 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
301 >; 313 >;
302 }; 314 };
303 }; 315 };
@@ -305,9 +317,9 @@
305 cspi { 317 cspi {
306 pinctrl_cspi_1: cspigrp-1 { 318 pinctrl_cspi_1: cspigrp-1 {
307 fsl,pins = < 319 fsl,pins = <
308 998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */ 320 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
309 1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */ 321 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
310 1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */ 322 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
311 >; 323 >;
312 }; 324 };
313 }; 325 };
@@ -315,9 +327,9 @@
315 ecspi1 { 327 ecspi1 {
316 pinctrl_ecspi1_1: ecspi1grp-1 { 328 pinctrl_ecspi1_1: ecspi1grp-1 {
317 fsl,pins = < 329 fsl,pins = <
318 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ 330 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
319 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ 331 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
320 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ 332 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
321 >; 333 >;
322 }; 334 };
323 }; 335 };
@@ -325,27 +337,27 @@
325 esdhc1 { 337 esdhc1 {
326 pinctrl_esdhc1_1: esdhc1grp-1 { 338 pinctrl_esdhc1_1: esdhc1grp-1 {
327 fsl,pins = < 339 fsl,pins = <
328 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ 340 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
329 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ 341 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
330 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ 342 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
331 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ 343 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
332 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ 344 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
333 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ 345 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
334 >; 346 >;
335 }; 347 };
336 348
337 pinctrl_esdhc1_2: esdhc1grp-2 { 349 pinctrl_esdhc1_2: esdhc1grp-2 {
338 fsl,pins = < 350 fsl,pins = <
339 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ 351 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
340 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ 352 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
341 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ 353 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
342 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ 354 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
343 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ 355 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
344 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ 356 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
345 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ 357 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
346 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ 358 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
347 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ 359 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
348 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ 360 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
349 >; 361 >;
350 }; 362 };
351 }; 363 };
@@ -353,12 +365,12 @@
353 esdhc2 { 365 esdhc2 {
354 pinctrl_esdhc2_1: esdhc2grp-1 { 366 pinctrl_esdhc2_1: esdhc2grp-1 {
355 fsl,pins = < 367 fsl,pins = <
356 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ 368 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
357 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ 369 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
358 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ 370 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
359 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ 371 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
360 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ 372 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
361 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ 373 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
362 >; 374 >;
363 }; 375 };
364 }; 376 };
@@ -366,16 +378,16 @@
366 esdhc3 { 378 esdhc3 {
367 pinctrl_esdhc3_1: esdhc3grp-1 { 379 pinctrl_esdhc3_1: esdhc3grp-1 {
368 fsl,pins = < 380 fsl,pins = <
369 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ 381 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
370 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ 382 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
371 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ 383 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
372 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ 384 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
373 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ 385 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
374 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ 386 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
375 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ 387 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
376 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ 388 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
377 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ 389 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
378 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ 390 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
379 >; 391 >;
380 }; 392 };
381 }; 393 };
@@ -383,15 +395,15 @@
383 can1 { 395 can1 {
384 pinctrl_can1_1: can1grp-1 { 396 pinctrl_can1_1: can1grp-1 {
385 fsl,pins = < 397 fsl,pins = <
386 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */ 398 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
387 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */ 399 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
388 >; 400 >;
389 }; 401 };
390 402
391 pinctrl_can1_2: can1grp-2 { 403 pinctrl_can1_2: can1grp-2 {
392 fsl,pins = < 404 fsl,pins = <
393 37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */ 405 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
394 44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */ 406 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
395 >; 407 >;
396 }; 408 };
397 }; 409 };
@@ -399,8 +411,8 @@
399 can2 { 411 can2 {
400 pinctrl_can2_1: can2grp-1 { 412 pinctrl_can2_1: can2grp-1 {
401 fsl,pins = < 413 fsl,pins = <
402 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */ 414 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
403 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */ 415 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
404 >; 416 >;
405 }; 417 };
406 }; 418 };
@@ -408,8 +420,8 @@
408 i2c1 { 420 i2c1 {
409 pinctrl_i2c1_1: i2c1grp-1 { 421 pinctrl_i2c1_1: i2c1grp-1 {
410 fsl,pins = < 422 fsl,pins = <
411 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ 423 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
412 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ 424 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
413 >; 425 >;
414 }; 426 };
415 }; 427 };
@@ -417,8 +429,8 @@
417 i2c2 { 429 i2c2 {
418 pinctrl_i2c2_1: i2c2grp-1 { 430 pinctrl_i2c2_1: i2c2grp-1 {
419 fsl,pins = < 431 fsl,pins = <
420 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ 432 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
421 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ 433 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
422 >; 434 >;
423 }; 435 };
424 }; 436 };
@@ -426,8 +438,8 @@
426 i2c3 { 438 i2c3 {
427 pinctrl_i2c3_1: i2c3grp-1 { 439 pinctrl_i2c3_1: i2c3grp-1 {
428 fsl,pins = < 440 fsl,pins = <
429 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */ 441 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
430 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */ 442 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
431 >; 443 >;
432 }; 444 };
433 }; 445 };
@@ -435,7 +447,7 @@
435 owire { 447 owire {
436 pinctrl_owire_1: owiregrp-1 { 448 pinctrl_owire_1: owiregrp-1 {
437 fsl,pins = < 449 fsl,pins = <
438 1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */ 450 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
439 >; 451 >;
440 }; 452 };
441 }; 453 };
@@ -443,15 +455,15 @@
443 uart1 { 455 uart1 {
444 pinctrl_uart1_1: uart1grp-1 { 456 pinctrl_uart1_1: uart1grp-1 {
445 fsl,pins = < 457 fsl,pins = <
446 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ 458 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
447 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ 459 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
448 >; 460 >;
449 }; 461 };
450 462
451 pinctrl_uart1_2: uart1grp-2 { 463 pinctrl_uart1_2: uart1grp-2 {
452 fsl,pins = < 464 fsl,pins = <
453 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ 465 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
454 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ 466 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
455 >; 467 >;
456 }; 468 };
457 }; 469 };
@@ -459,8 +471,8 @@
459 uart2 { 471 uart2 {
460 pinctrl_uart2_1: uart2grp-1 { 472 pinctrl_uart2_1: uart2grp-1 {
461 fsl,pins = < 473 fsl,pins = <
462 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ 474 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
463 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ 475 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
464 >; 476 >;
465 }; 477 };
466 }; 478 };
@@ -468,17 +480,17 @@
468 uart3 { 480 uart3 {
469 pinctrl_uart3_1: uart3grp-1 { 481 pinctrl_uart3_1: uart3grp-1 {
470 fsl,pins = < 482 fsl,pins = <
471 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ 483 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
472 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ 484 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
473 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ 485 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
474 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ 486 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
475 >; 487 >;
476 }; 488 };
477 489
478 pinctrl_uart3_2: uart3grp-2 { 490 pinctrl_uart3_2: uart3grp-2 {
479 fsl,pins = < 491 fsl,pins = <
480 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ 492 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
481 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ 493 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
482 >; 494 >;
483 }; 495 };
484 496
@@ -487,8 +499,8 @@
487 uart4 { 499 uart4 {
488 pinctrl_uart4_1: uart4grp-1 { 500 pinctrl_uart4_1: uart4grp-1 {
489 fsl,pins = < 501 fsl,pins = <
490 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */ 502 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
491 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */ 503 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
492 >; 504 >;
493 }; 505 };
494 }; 506 };
@@ -496,14 +508,46 @@
496 uart5 { 508 uart5 {
497 pinctrl_uart5_1: uart5grp-1 { 509 pinctrl_uart5_1: uart5grp-1 {
498 fsl,pins = < 510 fsl,pins = <
499 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */ 511 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
500 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */ 512 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
501 >; 513 >;
502 }; 514 };
503 }; 515 };
504 516
505 }; 517 };
506 518
519 gpr: iomuxc-gpr@53fa8000 {
520 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
521 reg = <0x53fa8000 0xc>;
522 };
523
524 ldb: ldb@53fa8008 {
525 #address-cells = <1>;
526 #size-cells = <0>;
527 compatible = "fsl,imx53-ldb";
528 reg = <0x53fa8008 0x4>;
529 gpr = <&gpr>;
530 clocks = <&clks 122>, <&clks 120>,
531 <&clks 115>, <&clks 116>,
532 <&clks 123>, <&clks 85>;
533 clock-names = "di0_pll", "di1_pll",
534 "di0_sel", "di1_sel",
535 "di0", "di1";
536 status = "disabled";
537
538 lvds-channel@0 {
539 reg = <0>;
540 crtcs = <&ipu 0>;
541 status = "disabled";
542 };
543
544 lvds-channel@1 {
545 reg = <1>;
546 crtcs = <&ipu 1>;
547 status = "disabled";
548 };
549 };
550
507 pwm1: pwm@53fb4000 { 551 pwm1: pwm@53fb4000 {
508 #pwm-cells = <2>; 552 #pwm-cells = <2>;
509 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 553 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
@@ -558,6 +602,12 @@
558 status = "disabled"; 602 status = "disabled";
559 }; 603 };
560 604
605 src: src@53fd0000 {
606 compatible = "fsl,imx53-src", "fsl,imx51-src";
607 reg = <0x53fd0000 0x4000>;
608 #reset-cells = <1>;
609 };
610
561 clks: ccm@53fd4000{ 611 clks: ccm@53fd4000{
562 compatible = "fsl,imx53-ccm"; 612 compatible = "fsl,imx53-ccm";
563 reg = <0x53fd4000 0x4000>; 613 reg = <0x53fd4000 0x4000>;
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
new file mode 100644
index 000000000000..9aab950ec269
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
@@ -0,0 +1,1085 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX6DL_PINFUNC_H
11#define __DTS_IMX6DL_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
27#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1
28#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0
29#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0
30#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0
31#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
32#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0
33#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0
34#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0
35#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0
36#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0
37#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
38#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0
39#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1
40#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0
41#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0
42#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0
43#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
44#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0
45#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0
46#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0
47#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0
48#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0
49#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
50#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0
51#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1
52#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0
53#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0
54#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0
55#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
56#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0
57#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0
58#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0
59#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0
60#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0
61#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
62#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0
63#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0
64#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1
65#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0
66#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0
67#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0
68#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0
69#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0
70#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0
71#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0
72#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0
73#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0
74#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0
75#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0
76#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1
77#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0
78#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0
79#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0
80#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0
81#define MX6DL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0
82#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0
83#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0
84#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0
85#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0
86#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0
87#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0
88#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0
89#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0
90#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0
91#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0
92#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0
93#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0
94#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0
95#define MX6DL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0
96#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0
97#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0
98#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0
99#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0
100#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0
101#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0
102#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0
103#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0
104#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0
105#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0
106#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0
107#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0
108#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0
109#define MX6DL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0
110#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0
111#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0
112#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0
113#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0
114#define MX6DL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0
115#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0
116#define MX6DL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0
117#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0
118#define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0
119#define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0
120#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0
121#define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0
122#define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0
123#define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0
124#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0
125#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0
126#define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0
127#define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0
128#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0
129#define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0
130#define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0
131#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0
132#define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0
133#define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0
134#define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0
135#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0
136#define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0
137#define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0
138#define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0
139#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0
140#define MX6DL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0
141#define MX6DL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0
142#define MX6DL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0
143#define MX6DL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0
144#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0
145#define MX6DL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0
146#define MX6DL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0
147#define MX6DL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0
148#define MX6DL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0
149#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0
150#define MX6DL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0
151#define MX6DL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0
152#define MX6DL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0
153#define MX6DL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0
154#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0
155#define MX6DL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1
156#define MX6DL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0
157#define MX6DL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0
158#define MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0
159#define MX6DL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0
160#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0
161#define MX6DL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0
162#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0
163#define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0
164#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0
165#define MX6DL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0
166#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0
167#define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0
168#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0
169#define MX6DL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0
170#define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0
171#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0
172#define MX6DL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0
173#define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0
174#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0
175#define MX6DL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0
176#define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0
177#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0
178#define MX6DL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0
179#define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0
180#define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0
181#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0
182#define MX6DL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0
183#define MX6DL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0
184#define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0
185#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0
186#define MX6DL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0
187#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0
188#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0
189#define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0
190#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0
191#define MX6DL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0
192#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1
193#define MX6DL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0
194#define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0
195#define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0
196#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0
197#define MX6DL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0
198#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1
199#define MX6DL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0
200#define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0
201#define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0
202#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0
203#define MX6DL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
204#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1
205#define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0
206#define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0
207#define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0
208#define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0
209#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0
210#define MX6DL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0
211#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1
212#define MX6DL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0
213#define MX6DL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0
214#define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0
215#define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0
216#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0
217#define MX6DL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0
218#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0
219#define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0
220#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0
221#define MX6DL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0
222#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1
223#define MX6DL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0
224#define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0
225#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0
226#define MX6DL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0
227#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1
228#define MX6DL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0
229#define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0
230#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0
231#define MX6DL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0
232#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1
233#define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0
234#define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0
235#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0
236#define MX6DL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0
237#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1
238#define MX6DL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0
239#define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0
240#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0
241#define MX6DL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0
242#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0
243#define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0
244#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0
245#define MX6DL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0
246#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0
247#define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0
248#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0
249#define MX6DL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0
250#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0
251#define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0
252#define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0
253#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0
254#define MX6DL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0
255#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0
256#define MX6DL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0
257#define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0
258#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0
259#define MX6DL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0
260#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0
261#define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0
262#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0
263#define MX6DL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0
264#define MX6DL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0
265#define MX6DL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0
266#define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0
267#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0
268#define MX6DL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0
269#define MX6DL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0
270#define MX6DL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0
271#define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0
272#define MX6DL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0
273#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0
274#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0
275#define MX6DL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0
276#define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0
277#define MX6DL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0
278#define MX6DL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0
279#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0
280#define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0
281#define MX6DL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0
282#define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0
283#define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0
284#define MX6DL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0
285#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0
286#define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0
287#define MX6DL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0
288#define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0
289#define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0
290#define MX6DL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0
291#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0
292#define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0
293#define MX6DL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0
294#define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0
295#define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0
296#define MX6DL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0
297#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0
298#define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0
299#define MX6DL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0
300#define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0
301#define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0
302#define MX6DL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0
303#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0
304#define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0
305#define MX6DL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0
306#define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0
307#define MX6DL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0
308#define MX6DL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0
309#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0
310#define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
311#define MX6DL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0
312#define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0
313#define MX6DL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0
314#define MX6DL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0
315#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0
316#define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0
317#define MX6DL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0
318#define MX6DL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0
319#define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0
320#define MX6DL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0
321#define MX6DL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0
322#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0
323#define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0
324#define MX6DL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0
325#define MX6DL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0
326#define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0
327#define MX6DL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0
328#define MX6DL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0
329#define MX6DL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0
330#define MX6DL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0
331#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0
332#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0
333#define MX6DL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0
334#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0
335#define MX6DL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0
336#define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0
337#define MX6DL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0
338#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0
339#define MX6DL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0
340#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0
341#define MX6DL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0
342#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0
343#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2
344#define MX6DL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0
345#define MX6DL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0
346#define MX6DL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0
347#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0
348#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2
349#define MX6DL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0
350#define MX6DL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0
351#define MX6DL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0
352#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2
353#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0
354#define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1
355#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0
356#define MX6DL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0
357#define MX6DL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0
358#define MX6DL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0
359#define MX6DL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0
360#define MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2
361#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0
362#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1
363#define MX6DL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0
364#define MX6DL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0
365#define MX6DL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0
366#define MX6DL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0
367#define MX6DL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0
368#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2
369#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0
370#define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1
371#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0
372#define MX6DL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0
373#define MX6DL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0
374#define MX6DL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0
375#define MX6DL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0
376#define MX6DL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1
377#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0
378#define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1
379#define MX6DL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0
380#define MX6DL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0
381#define MX6DL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0
382#define MX6DL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0
383#define MX6DL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0
384#define MX6DL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0
385#define MX6DL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0
386#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0
387#define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1
388#define MX6DL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1
389#define MX6DL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0
390#define MX6DL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0
391#define MX6DL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0
392#define MX6DL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0
393#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0
394#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0
395#define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0
396#define MX6DL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0
397#define MX6DL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0
398#define MX6DL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1
399#define MX6DL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0
400#define MX6DL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0
401#define MX6DL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0
402#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0
403#define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0
404#define MX6DL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0
405#define MX6DL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0
406#define MX6DL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0
407#define MX6DL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0
408#define MX6DL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0
409#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0
410#define MX6DL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0
411#define MX6DL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0
412#define MX6DL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0
413#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0
414#define MX6DL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0
415#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0
416#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0
417#define MX6DL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0
418#define MX6DL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0
419#define MX6DL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0
420#define MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0
421#define MX6DL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0
422#define MX6DL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0
423#define MX6DL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0
424#define MX6DL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0
425#define MX6DL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1
426#define MX6DL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0
427#define MX6DL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0
428#define MX6DL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0
429#define MX6DL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0
430#define MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1
431#define MX6DL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0
432#define MX6DL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0
433#define MX6DL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0
434#define MX6DL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0
435#define MX6DL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1
436#define MX6DL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0
437#define MX6DL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0
438#define MX6DL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0
439#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0
440#define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0
441#define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1
442#define MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0
443#define MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0
444#define MX6DL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0
445#define MX6DL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0
446#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0
447#define MX6DL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0
448#define MX6DL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0
449#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0
450#define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0
451#define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1
452#define MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1
453#define MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0
454#define MX6DL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0
455#define MX6DL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0
456#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0
457#define MX6DL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0
458#define MX6DL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0
459#define MX6DL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1
460#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0
461#define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1
462#define MX6DL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0
463#define MX6DL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0
464#define MX6DL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0
465#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0
466#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0
467#define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0
468#define MX6DL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0
469#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0
470#define MX6DL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1
471#define MX6DL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1
472#define MX6DL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0
473#define MX6DL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0
474#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0
475#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0
476#define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0
477#define MX6DL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0
478#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0
479#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0
480#define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0
481#define MX6DL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0
482#define MX6DL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1
483#define MX6DL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0
484#define MX6DL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0
485#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0
486#define MX6DL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0
487#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0
488#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0
489#define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0
490#define MX6DL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2
491#define MX6DL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0
492#define MX6DL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0
493#define MX6DL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0
494#define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0
495#define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0
496#define MX6DL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0
497#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0
498#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0
499#define MX6DL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0
500#define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0
501#define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0
502#define MX6DL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0
503#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0
504#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0
505#define MX6DL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0
506#define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0
507#define MX6DL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0
508#define MX6DL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0
509#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0
510#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1
511#define MX6DL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0
512#define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0
513#define MX6DL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0
514#define MX6DL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0
515#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0
516#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0
517#define MX6DL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0
518#define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0
519#define MX6DL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0
520#define MX6DL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0
521#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0
522#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1
523#define MX6DL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0
524#define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0
525#define MX6DL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0
526#define MX6DL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0
527#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0
528#define MX6DL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0
529#define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0
530#define MX6DL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0
531#define MX6DL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0
532#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0
533#define MX6DL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0
534#define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0
535#define MX6DL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0
536#define MX6DL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0
537#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0
538#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0
539#define MX6DL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0
540#define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0
541#define MX6DL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0
542#define MX6DL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0
543#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0
544#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0
545#define MX6DL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0
546#define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0
547#define MX6DL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0
548#define MX6DL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0
549#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0
550#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0
551#define MX6DL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0
552#define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0
553#define MX6DL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0
554#define MX6DL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0
555#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0
556#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0
557#define MX6DL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0
558#define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0
559#define MX6DL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0
560#define MX6DL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0
561#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0
562#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0
563#define MX6DL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0
564#define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0
565#define MX6DL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0
566#define MX6DL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0
567#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0
568#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0
569#define MX6DL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0
570#define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0
571#define MX6DL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0
572#define MX6DL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0
573#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0
574#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0
575#define MX6DL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0
576#define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0
577#define MX6DL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0
578#define MX6DL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0
579#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0
580#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0
581#define MX6DL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0
582#define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0
583#define MX6DL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0
584#define MX6DL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0
585#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0
586#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0
587#define MX6DL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0
588#define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0
589#define MX6DL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0
590#define MX6DL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0
591#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0
592#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1
593#define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0
594#define MX6DL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0
595#define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0
596#define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0
597#define MX6DL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0
598#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0
599#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1
600#define MX6DL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0
601#define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0
602#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0
603#define MX6DL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0
604#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2
605#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1
606#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0
607#define MX6DL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0
608#define MX6DL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0
609#define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0
610#define MX6DL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0
611#define MX6DL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0
612#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0
613#define MX6DL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3
614#define MX6DL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0
615#define MX6DL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0
616#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1
617#define MX6DL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0
618#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0
619#define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0
620#define MX6DL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0
621#define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0
622#define MX6DL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0
623#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0
624#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1
625#define MX6DL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0
626#define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0
627#define MX6DL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0
628#define MX6DL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0
629#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0
630#define MX6DL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2
631#define MX6DL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0
632#define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0
633#define MX6DL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0
634#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0
635#define MX6DL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2
636#define MX6DL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0
637#define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0
638#define MX6DL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0
639#define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0
640#define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0
641#define MX6DL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0
642#define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0
643#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0
644#define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0
645#define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0
646#define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0
647#define MX6DL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0
648#define MX6DL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0
649#define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0
650#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0
651#define MX6DL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0
652#define MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0
653#define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0
654#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0
655#define MX6DL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0
656#define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0
657#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0
658#define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0
659#define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0
660#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0
661#define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0
662#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0
663#define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0
664#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1
665#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
666#define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0
667#define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0
668#define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0
669#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0
670#define MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0
671#define MX6DL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0
672#define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0
673#define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0
674#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0
675#define MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0
676#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0
677#define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0
678#define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0
679#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0
680#define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0
681#define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0
682#define MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0
683#define MX6DL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0
684#define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0
685#define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0
686#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0
687#define MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0
688#define MX6DL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0
689#define MX6DL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0
690#define MX6DL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1
691#define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0
692#define MX6DL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0
693#define MX6DL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0
694#define MX6DL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0
695#define MX6DL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0
696#define MX6DL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1
697#define MX6DL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0
698#define MX6DL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1
699#define MX6DL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1
700#define MX6DL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0
701#define MX6DL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0
702#define MX6DL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0
703#define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1
704#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0
705#define MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0
706#define MX6DL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0
707#define MX6DL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2
708#define MX6DL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0
709#define MX6DL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1
710#define MX6DL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0
711#define MX6DL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0
712#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0
713#define MX6DL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1
714#define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1
715#define MX6DL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0
716#define MX6DL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0
717#define MX6DL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0
718#define MX6DL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0
719#define MX6DL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0
720#define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1
721#define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1
722#define MX6DL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0
723#define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0
724#define MX6DL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2
725#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0
726#define MX6DL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0
727#define MX6DL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0
728#define MX6DL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0
729#define MX6DL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0
730#define MX6DL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0
731#define MX6DL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1
732#define MX6DL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1
733#define MX6DL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0
734#define MX6DL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0
735#define MX6DL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1
736#define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1
737#define MX6DL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1
738#define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0
739#define MX6DL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0
740#define MX6DL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0
741#define MX6DL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1
742#define MX6DL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1
743#define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1
744#define MX6DL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1
745#define MX6DL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0
746#define MX6DL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0
747#define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1
748#define MX6DL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1
749#define MX6DL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0
750#define MX6DL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0
751#define MX6DL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
752#define MX6DL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
753#define MX6DL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
754#define MX6DL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
755#define MX6DL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
756#define MX6DL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
757#define MX6DL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1
758#define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1
759#define MX6DL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0
760#define MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0
761#define MX6DL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0
762#define MX6DL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2
763#define MX6DL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0
764#define MX6DL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0
765#define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0
766#define MX6DL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1
767#define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1
768#define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0
769#define MX6DL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0
770#define MX6DL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0
771#define MX6DL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3
772#define MX6DL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0
773#define MX6DL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0
774#define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0
775#define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0
776#define MX6DL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1
777#define MX6DL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1
778#define MX6DL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0
779#define MX6DL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1
780#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0
781#define MX6DL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0
782#define MX6DL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0
783#define MX6DL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1
784#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3
785#define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0
786#define MX6DL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1
787#define MX6DL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0
788#define MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0
789#define MX6DL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2
790#define MX6DL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0
791#define MX6DL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0
792#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3
793#define MX6DL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1
794#define MX6DL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1
795#define MX6DL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0
796#define MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0
797#define MX6DL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2
798#define MX6DL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0
799#define MX6DL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0
800#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2
801#define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0
802#define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0
803#define MX6DL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0
804#define MX6DL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0
805#define MX6DL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0
806#define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0
807#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1
808#define MX6DL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0
809#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1
810#define MX6DL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0
811#define MX6DL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1
812#define MX6DL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0
813#define MX6DL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3
814#define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0
815#define MX6DL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0
816#define MX6DL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1
817#define MX6DL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0
818#define MX6DL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2
819#define MX6DL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0
820#define MX6DL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0
821#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3
822#define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0
823#define MX6DL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1
824#define MX6DL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0
825#define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3
826#define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0
827#define MX6DL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0
828#define MX6DL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0
829#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3
830#define MX6DL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0
831#define MX6DL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1
832#define MX6DL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0
833#define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3
834#define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0
835#define MX6DL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0
836#define MX6DL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0
837#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1
838#define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0
839#define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1
840#define MX6DL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0
841#define MX6DL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0
842#define MX6DL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0
843#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1
844#define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2
845#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1
846#define MX6DL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0
847#define MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1
848#define MX6DL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0
849#define MX6DL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0
850#define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0
851#define MX6DL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0
852#define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0
853#define MX6DL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0
854#define MX6DL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0
855#define MX6DL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3
856#define MX6DL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0
857#define MX6DL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0
858#define MX6DL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0
859#define MX6DL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0
860#define MX6DL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0
861#define MX6DL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0
862#define MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0
863#define MX6DL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0
864#define MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0
865#define MX6DL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0
866#define MX6DL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0
867#define MX6DL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0
868#define MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0
869#define MX6DL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0
870#define MX6DL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1
871#define MX6DL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0
872#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0
873#define MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0
874#define MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0
875#define MX6DL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0
876#define MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1
877#define MX6DL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0
878#define MX6DL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0
879#define MX6DL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2
880#define MX6DL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0
881#define MX6DL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0
882#define MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0
883#define MX6DL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0
884#define MX6DL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0
885#define MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0
886#define MX6DL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0
887#define MX6DL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0
888#define MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0
889#define MX6DL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0
890#define MX6DL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0
891#define MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0
892#define MX6DL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0
893#define MX6DL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0
894#define MX6DL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0
895#define MX6DL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0
896#define MX6DL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0
897#define MX6DL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0
898#define MX6DL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0
899#define MX6DL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0
900#define MX6DL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0
901#define MX6DL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0
902#define MX6DL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0
903#define MX6DL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0
904#define MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0
905#define MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0
906#define MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0
907#define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0
908#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2
909#define MX6DL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0
910#define MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1
911#define MX6DL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0
912#define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0
913#define MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1
914#define MX6DL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0
915#define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0
916#define MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1
917#define MX6DL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0
918#define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0
919#define MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1
920#define MX6DL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0
921#define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0
922#define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1
923#define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0
924#define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0
925#define MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1
926#define MX6DL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0
927#define MX6DL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0
928#define MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0
929#define MX6DL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0
930#define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0
931#define MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0
932#define MX6DL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0
933#define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0
934#define MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0
935#define MX6DL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0
936#define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0
937#define MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0
938#define MX6DL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0
939#define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0
940#define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0
941#define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0
942#define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1
943#define MX6DL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0
944#define MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0
945#define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1
946#define MX6DL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0
947#define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0
948#define MX6DL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1
949#define MX6DL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0
950#define MX6DL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0
951#define MX6DL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0
952#define MX6DL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0
953#define MX6DL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0
954#define MX6DL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0
955#define MX6DL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0
956#define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0
957#define MX6DL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0
958#define MX6DL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0
959#define MX6DL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0
960#define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0
961#define MX6DL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0
962#define MX6DL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0
963#define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0
964#define MX6DL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0
965#define MX6DL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0
966#define MX6DL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0
967#define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0
968#define MX6DL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0
969#define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0
970#define MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0
971#define MX6DL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0
972#define MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0
973#define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0
974#define MX6DL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1
975#define MX6DL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3
976#define MX6DL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1
977#define MX6DL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0
978#define MX6DL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0
979#define MX6DL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2
980#define MX6DL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1
981#define MX6DL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0
982#define MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0
983#define MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1
984#define MX6DL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2
985#define MX6DL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0
986#define MX6DL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0
987#define MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0
988#define MX6DL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0
989#define MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1
990#define MX6DL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2
991#define MX6DL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0
992#define MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0
993#define MX6DL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0
994#define MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1
995#define MX6DL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2
996#define MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0
997#define MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0
998#define MX6DL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2
999#define MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1
1000#define MX6DL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0
1001#define MX6DL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1
1002#define MX6DL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2
1003#define MX6DL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0
1004#define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2
1005#define MX6DL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0
1006#define MX6DL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0
1007#define MX6DL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0
1008#define MX6DL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3
1009#define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0
1010#define MX6DL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0
1011#define MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0
1012#define MX6DL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0
1013#define MX6DL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2
1014#define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0
1015#define MX6DL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0
1016#define MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0
1017#define MX6DL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3
1018#define MX6DL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0
1019#define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1
1020#define MX6DL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0
1021#define MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0
1022#define MX6DL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0
1023#define MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0
1024#define MX6DL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0
1025#define MX6DL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4
1026#define MX6DL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0
1027#define MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0
1028#define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4
1029#define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0
1030#define MX6DL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0
1031#define MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0
1032#define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0
1033#define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5
1034#define MX6DL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0
1035#define MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0
1036#define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2
1037#define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0
1038#define MX6DL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0
1039#define MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0
1040#define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0
1041#define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3
1042#define MX6DL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0
1043#define MX6DL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0
1044#define MX6DL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5
1045#define MX6DL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0
1046#define MX6DL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0
1047#define MX6DL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1
1048#define MX6DL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0
1049#define MX6DL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2
1050#define MX6DL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0
1051#define MX6DL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0
1052#define MX6DL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0
1053#define MX6DL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0
1054#define MX6DL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0
1055#define MX6DL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3
1056#define MX6DL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0
1057#define MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0
1058#define MX6DL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0
1059#define MX6DL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0
1060#define MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0
1061#define MX6DL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0
1062#define MX6DL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0
1063#define MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0
1064#define MX6DL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
1065#define MX6DL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0
1066#define MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0
1067#define MX6DL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0
1068#define MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0
1069#define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6
1070#define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0
1071#define MX6DL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0
1072#define MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0
1073#define MX6DL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4
1074#define MX6DL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0
1075#define MX6DL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0
1076#define MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0
1077#define MX6DL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0
1078#define MX6DL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5
1079#define MX6DL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0
1080#define MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0
1081#define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0
1082#define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7
1083#define MX6DL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0
1084
1085#endif /* __DTS_IMX6DL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
new file mode 100644
index 000000000000..7adcec360213
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -0,0 +1,31 @@
1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6dl.dtsi"
12#include "imx6qdl-sabreauto.dtsi"
13
14/ {
15 model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
16 compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
17};
18
19&iomuxc {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_hog>;
22
23 hog {
24 pinctrl_hog: hoggrp {
25 fsl,pins = <
26 MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
27 MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
28 >;
29 };
30 };
31};
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
new file mode 100644
index 000000000000..7efb05db4783
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -0,0 +1,35 @@
1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6dl.dtsi"
12#include "imx6qdl-sabresd.dtsi"
13
14/ {
15 model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
16 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
17};
18
19&iomuxc {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_hog>;
22
23 hog {
24 pinctrl_hog: hoggrp {
25 fsl,pins = <
26 MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000
27 MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000
28 MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
29 MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
30 MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
31 MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
32 >;
33 };
34 };
35};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
new file mode 100644
index 000000000000..bfc59c3566a4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13
14/ {
15 model = "Wandboard i.MX6 Dual Lite Board";
16 compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
17
18 memory {
19 reg = <0x10000000 0x40000000>;
20 };
21};
22
23&fec {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_enet_1>;
26 phy-mode = "rgmii";
27 status = "okay";
28};
29
30&uart1 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_uart1_1>;
33 status = "okay";
34};
35
36&usbh1 {
37 status = "okay";
38};
39
40&usdhc3 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_usdhc3_2>;
43 status = "okay";
44};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 63fafe2a606c..5bcdf3a90bb3 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -1,3 +1,4 @@
1
1/* 2/*
2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 4 *
@@ -7,7 +8,8 @@
7 * 8 *
8 */ 9 */
9 10
10/include/ "imx6qdl.dtsi" 11#include "imx6qdl.dtsi"
12#include "imx6dl-pinfunc.h"
11 13
12/ { 14/ {
13 cpus { 15 cpus {
@@ -29,6 +31,127 @@
29 31
30 soc { 32 soc {
31 aips1: aips-bus@02000000 { 33 aips1: aips-bus@02000000 {
34 iomuxc: iomuxc@020e0000 {
35 compatible = "fsl,imx6dl-iomuxc";
36 reg = <0x020e0000 0x4000>;
37
38 enet {
39 pinctrl_enet_1: enetgrp-1 {
40 fsl,pins = <
41 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
42 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
43 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
44 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
45 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
46 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
47 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
48 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
49 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
50 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
51 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
52 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
53 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
54 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
55 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
56 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
57 >;
58 };
59
60 pinctrl_enet_2: enetgrp-2 {
61 fsl,pins = <
62 MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
63 MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
64 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
65 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
66 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
67 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
68 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
69 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
70 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
71 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
72 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
73 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
74 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
75 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
76 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
77 >;
78 };
79 };
80
81 uart1 {
82 pinctrl_uart1_1: uart1grp-1 {
83 fsl,pins = <
84 MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
85 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
86 >;
87 };
88 };
89
90 uart4 {
91 pinctrl_uart4_1: uart4grp-1 {
92 fsl,pins = <
93 MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
94 MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
95 >;
96 };
97 };
98
99 usbotg {
100 pinctrl_usbotg_2: usbotggrp-2 {
101 fsl,pins = <
102 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
103 >;
104 };
105 };
106
107 usdhc2 {
108 pinctrl_usdhc2_1: usdhc2grp-1 {
109 fsl,pins = <
110 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
111 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
112 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
113 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
114 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
115 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
116 MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
117 MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
118 MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
119 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
120 >;
121 };
122 };
123
124 usdhc3 {
125 pinctrl_usdhc3_1: usdhc3grp-1 {
126 fsl,pins = <
127 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
128 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
129 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
130 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
131 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
132 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
133 MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
134 MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
135 MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
136 MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
137 >;
138 };
139
140 pinctrl_usdhc3_2: usdhc3grp_2 {
141 fsl,pins = <
142 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
143 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
144 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
145 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
146 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
147 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
148 >;
149 };
150 };
151
152
153 };
154
32 pxp: pxp@020f0000 { 155 pxp: pxp@020f0000 {
33 reg = <0x020f0000 0x4000>; 156 reg = <0x020f0000 0x4000>;
34 interrupts = <0 98 0x04>; 157 interrupts = <0 98 0x04>;
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 53eb241fa5ad..4e54fde591bd 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx6q.dtsi" 14#include "imx6q.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX6 Quad Armadillo2 Board"; 17 model = "Freescale i.MX6 Quad Armadillo2 Board";
@@ -57,7 +57,7 @@
57 hog { 57 hog {
58 pinctrl_hog: hoggrp { 58 pinctrl_hog: hoggrp {
59 fsl,pins = < 59 fsl,pins = <
60 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ 60 MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
61 >; 61 >;
62 }; 62 };
63 }; 63 };
@@ -65,8 +65,8 @@
65 arm2 { 65 arm2 {
66 pinctrl_usdhc3_arm2: usdhc3grp-arm2 { 66 pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
67 fsl,pins = < 67 fsl,pins = <
68 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ 68 MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
69 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ 69 MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
70 >; 70 >;
71 }; 71 };
72 }; 72 };
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
new file mode 100644
index 000000000000..faea6e1ada00
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -0,0 +1,1041 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX6Q_PINFUNC_H
11#define __DTS_IMX6Q_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
18#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
19#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
20#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
21#define MX6Q_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
22#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
23#define MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
24#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
25#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
26#define MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
27#define MX6Q_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0
28#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
29#define MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0
30#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
31#define MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0
32#define MX6Q_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0
33#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
34#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0
35#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0
36#define MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
37#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
38#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0
39#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0
40#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0
41#define MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
42#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0
43#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0
44#define MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
45#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0
46#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0
47#define MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
48#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0
49#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0
50#define MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
51#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0
52#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0
53#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
54#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
55#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0
56#define MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
57#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0
58#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0
59#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0
60#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
61#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0
62#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0
63#define MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
64#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0
65#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0
66#define MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
67#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0
68#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0
69#define MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0
70#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0
71#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0
72#define MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0
73#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0
74#define MX6Q_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0
75#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0
76#define MX6Q_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
77#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0
78#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0
79#define MX6Q_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0
80#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0
81#define MX6Q_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0
82#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0
83#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0
84#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0
85#define MX6Q_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0
86#define MX6Q_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0
87#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0
88#define MX6Q_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0
89#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0
90#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
91#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0
92#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0
93#define MX6Q_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0
94#define MX6Q_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0
95#define MX6Q_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0
96#define MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0
97#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
98#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0
99#define MX6Q_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0
100#define MX6Q_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0
101#define MX6Q_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0
102#define MX6Q_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0
103#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0
104#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
105#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0
106#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0
107#define MX6Q_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0
108#define MX6Q_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0
109#define MX6Q_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0
110#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0
111#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
112#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0
113#define MX6Q_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0
114#define MX6Q_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0
115#define MX6Q_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0
116#define MX6Q_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0
117#define MX6Q_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0
118#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0
119#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
120#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0
121#define MX6Q_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1
122#define MX6Q_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0
123#define MX6Q_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0
124#define MX6Q_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0
125#define MX6Q_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0
126#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0
127#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
128#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0
129#define MX6Q_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0
130#define MX6Q_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0
131#define MX6Q_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0
132#define MX6Q_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0
133#define MX6Q_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0
134#define MX6Q_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0
135#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
136#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0
137#define MX6Q_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0
138#define MX6Q_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0
139#define MX6Q_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0
140#define MX6Q_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0
141#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0
142#define MX6Q_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
143#define MX6Q_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
144#define MX6Q_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0
145#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0
146#define MX6Q_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0
147#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0
148#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0
149#define MX6Q_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0
150#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0
151#define MX6Q_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
152#define MX6Q_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
153#define MX6Q_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0
154#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0
155#define MX6Q_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0
156#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0
157#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0
158#define MX6Q_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0
159#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0
160#define MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
161#define MX6Q_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
162#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0
163#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0
164#define MX6Q_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0
165#define MX6Q_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0
166#define MX6Q_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0
167#define MX6Q_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0
168#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0
169#define MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
170#define MX6Q_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
171#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0
172#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0
173#define MX6Q_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0
174#define MX6Q_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0
175#define MX6Q_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0
176#define MX6Q_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0
177#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0
178#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
179#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0
180#define MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0
181#define MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0
182#define MX6Q_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0
183#define MX6Q_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0
184#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0
185#define MX6Q_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0
186#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0
187#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
188#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0
189#define MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1
190#define MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0
191#define MX6Q_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0
192#define MX6Q_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0
193#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0
194#define MX6Q_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0
195#define MX6Q_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0
196#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
197#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0
198#define MX6Q_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0
199#define MX6Q_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0
200#define MX6Q_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0
201#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0
202#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0
203#define MX6Q_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0
204#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0
205#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
206#define MX6Q_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
207#define MX6Q_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
208#define MX6Q_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
209#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
210#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
211#define MX6Q_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0
212#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0
213#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
214#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0
215#define MX6Q_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0
216#define MX6Q_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
217#define MX6Q_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0
218#define MX6Q_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0
219#define MX6Q_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0
220#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0
221#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
222#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0
223#define MX6Q_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3
224#define MX6Q_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0
225#define MX6Q_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0
226#define MX6Q_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0
227#define MX6Q_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0
228#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0
229#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
230#define MX6Q_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0
231#define MX6Q_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0
232#define MX6Q_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0
233#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0
234#define MX6Q_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0
235#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
236#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
237#define MX6Q_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0
238#define MX6Q_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0
239#define MX6Q_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0
240#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0
241#define MX6Q_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0
242#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0
243#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
244#define MX6Q_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0
245#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0
246#define MX6Q_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0
247#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0
248#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
249#define MX6Q_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0
250#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0
251#define MX6Q_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0
252#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0
253#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
254#define MX6Q_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0
255#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0
256#define MX6Q_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0
257#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0
258#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
259#define MX6Q_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0
260#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0
261#define MX6Q_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0
262#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0
263#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
264#define MX6Q_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0
265#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0
266#define MX6Q_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0
267#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0
268#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
269#define MX6Q_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0
270#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0
271#define MX6Q_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0
272#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0
273#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
274#define MX6Q_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0
275#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0
276#define MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0
277#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0
278#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
279#define MX6Q_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0
280#define MX6Q_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0
281#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0
282#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
283#define MX6Q_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0
284#define MX6Q_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0
285#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0
286#define MX6Q_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
287#define MX6Q_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0
288#define MX6Q_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0
289#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0
290#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
291#define MX6Q_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0
292#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0
293#define MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0
294#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0
295#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
296#define MX6Q_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0
297#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0
298#define MX6Q_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0
299#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0
300#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
301#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0
302#define MX6Q_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0
303#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0
304#define MX6Q_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0
305#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0
306#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
307#define MX6Q_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0
308#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0
309#define MX6Q_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0
310#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0
311#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
312#define MX6Q_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0
313#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0
314#define MX6Q_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0
315#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0
316#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
317#define MX6Q_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0
318#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0
319#define MX6Q_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0
320#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0
321#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
322#define MX6Q_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0
323#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0
324#define MX6Q_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0
325#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0
326#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
327#define MX6Q_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0
328#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0
329#define MX6Q_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0
330#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0
331#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
332#define MX6Q_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0
333#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0
334#define MX6Q_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
335#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
336#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
337#define MX6Q_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
338#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
339#define MX6Q_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0
340#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0
341#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
342#define MX6Q_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0
343#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0
344#define MX6Q_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0
345#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0
346#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
347#define MX6Q_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0
348#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0
349#define MX6Q_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0
350#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0
351#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
352#define MX6Q_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0
353#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0
354#define MX6Q_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0
355#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0
356#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
357#define MX6Q_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0
358#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0
359#define MX6Q_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0
360#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0
361#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
362#define MX6Q_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0
363#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0
364#define MX6Q_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0
365#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0
366#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
367#define MX6Q_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0
368#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0
369#define MX6Q_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0
370#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0
371#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
372#define MX6Q_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0
373#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0
374#define MX6Q_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0
375#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0
376#define MX6Q_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0
377#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0
378#define MX6Q_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0
379#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0
380#define MX6Q_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0
381#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0
382#define MX6Q_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0
383#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0
384#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
385#define MX6Q_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0
386#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0
387#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0
388#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0
389#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0
390#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0
391#define MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0
392#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0
393#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0
394#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0
395#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0
396#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0
397#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0
398#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0
399#define MX6Q_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
400#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0
401#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0
402#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0
403#define MX6Q_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
404#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0
405#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0
406#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0
407#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
408#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0
409#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0
410#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0
411#define MX6Q_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
412#define MX6Q_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0
413#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0
414#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0
415#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0
416#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
417#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0
418#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0
419#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0
420#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
421#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0
422#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0
423#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0
424#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
425#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0
426#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0
427#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0
428#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
429#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0
430#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0
431#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0
432#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
433#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0
434#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0
435#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0
436#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
437#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0
438#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0
439#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0
440#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0
441#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
442#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0
443#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0
444#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0
445#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0
446#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
447#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0
448#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0
449#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0
450#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
451#define MX6Q_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0
452#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0
453#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0
454#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0
455#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
456#define MX6Q_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0
457#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0
458#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0
459#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0
460#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0
461#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0
462#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0
463#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0
464#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0
465#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0
466#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0
467#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0
468#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0
469#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1
470#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0
471#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0
472#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0
473#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1
474#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0
475#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0
476#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0
477#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
478#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
479#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0
480#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0
481#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0
482#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
483#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0
484#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0
485#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0
486#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0
487#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0
488#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
489#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0
490#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0
491#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0
492#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0
493#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0
494#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
495#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0
496#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0
497#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0
498#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0
499#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0
500#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0
501#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
502#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0
503#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0
504#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0
505#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0
506#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0
507#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0
508#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
509#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0
510#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0
511#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0
512#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0
513#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
514#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1
515#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0
516#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0
517#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0
518#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
519#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1
520#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0
521#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0
522#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0
523#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
524#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1
525#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0
526#define MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0
527#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
528#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0
529#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0
530#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0
531#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0
532#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
533#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
534#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
535#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0
536#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
537#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
538#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
539#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
540#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0
541#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1
542#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
543#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1
544#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0
545#define MX6Q_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0
546#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1
547#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
548#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
549#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
550#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
551#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
552#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0
553#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0
554#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0
555#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
556#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0
557#define MX6Q_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0
558#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0
559#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
560#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0
561#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0
562#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0
563#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
564#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0
565#define MX6Q_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0
566#define MX6Q_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0
567#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
568#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0
569#define MX6Q_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0
570#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
571#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1
572#define MX6Q_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
573#define MX6Q_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0
574#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0
575#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0
576#define MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0
577#define MX6Q_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0
578#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
579#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0
580#define MX6Q_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
581#define MX6Q_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0
582#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1
583#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0
584#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0
585#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0
586#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
587#define MX6Q_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1
588#define MX6Q_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
589#define MX6Q_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0
590#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0
591#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0
592#define MX6Q_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0
593#define MX6Q_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0
594#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
595#define MX6Q_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0
596#define MX6Q_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
597#define MX6Q_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0
598#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1
599#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0
600#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0
601#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0
602#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
603#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1
604#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
605#define MX6Q_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0
606#define MX6Q_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0
607#define MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0
608#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0
609#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1
610#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0
611#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
612#define MX6Q_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0
613#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0
614#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0
615#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1
616#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1
617#define MX6Q_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0
618#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
619#define MX6Q_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0
620#define MX6Q_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1
621#define MX6Q_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0
622#define MX6Q_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
623#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0
624#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
625#define MX6Q_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0
626#define MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1
627#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0
628#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0
629#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0
630#define MX6Q_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0
631#define MX6Q_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
632#define MX6Q_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0
633#define MX6Q_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0
634#define MX6Q_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0
635#define MX6Q_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0
636#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0
637#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0
638#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
639#define MX6Q_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0
640#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0
641#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1
642#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0
643#define MX6Q_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0
644#define MX6Q_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
645#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1
646#define MX6Q_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0
647#define MX6Q_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0
648#define MX6Q_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0
649#define MX6Q_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0
650#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
651#define MX6Q_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
652#define MX6Q_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
653#define MX6Q_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0
654#define MX6Q_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
655#define MX6Q_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
656#define MX6Q_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
657#define MX6Q_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1
658#define MX6Q_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0
659#define MX6Q_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
660#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0
661#define MX6Q_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0
662#define MX6Q_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0
663#define MX6Q_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1
664#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1
665#define MX6Q_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
666#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0
667#define MX6Q_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0
668#define MX6Q_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0
669#define MX6Q_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
670#define MX6Q_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
671#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
672#define MX6Q_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
673#define MX6Q_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
674#define MX6Q_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
675#define MX6Q_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1
676#define MX6Q_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
677#define MX6Q_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
678#define MX6Q_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
679#define MX6Q_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
680#define MX6Q_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
681#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1
682#define MX6Q_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
683#define MX6Q_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0
684#define MX6Q_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0
685#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1
686#define MX6Q_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
687#define MX6Q_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0
688#define MX6Q_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0
689#define MX6Q_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
690#define MX6Q_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0
691#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
692#define MX6Q_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
693#define MX6Q_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
694#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
695#define MX6Q_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
696#define MX6Q_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
697#define MX6Q_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
698#define MX6Q_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
699#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
700#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1
701#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0
702#define MX6Q_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
703#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1
704#define MX6Q_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3
705#define MX6Q_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0
706#define MX6Q_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0
707#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0
708#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0
709#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
710#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
711#define MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
712#define MX6Q_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
713#define MX6Q_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
714#define MX6Q_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
715#define MX6Q_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
716#define MX6Q_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
717#define MX6Q_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0
718#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0
719#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
720#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1
721#define MX6Q_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0
722#define MX6Q_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0
723#define MX6Q_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
724#define MX6Q_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
725#define MX6Q_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
726#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
727#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
728#define MX6Q_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
729#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
730#define MX6Q_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
731#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
732#define MX6Q_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
733#define MX6Q_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
734#define MX6Q_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
735#define MX6Q_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
736#define MX6Q_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
737#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0
738#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0
739#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0
740#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0
741#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0
742#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0
743#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0
744#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0
745#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0
746#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0
747#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0
748#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0
749#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0
750#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0
751#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0
752#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0
753#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0
754#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
755#define MX6Q_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
756#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0
757#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0
758#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0
759#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0
760#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0
761#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
762#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1
763#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0
764#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0
765#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0
766#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0
767#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0
768#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
769#define MX6Q_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1
770#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0
771#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0
772#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0
773#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0
774#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0
775#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
776#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
777#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0
778#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0
779#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0
780#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0
781#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0
782#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
783#define MX6Q_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
784#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1
785#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0
786#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0
787#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0
788#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0
789#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
790#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
791#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1
792#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0
793#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0
794#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0
795#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0
796#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
797#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0
798#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0
799#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0
800#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0
801#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0
802#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0
803#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
804#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1
805#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0
806#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0
807#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0
808#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0
809#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0
810#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0
811#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
812#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0
813#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0
814#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0
815#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0
816#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3
817#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0
818#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0
819#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0
820#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0
821#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0
822#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0
823#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
824#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0
825#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0
826#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0
827#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0
828#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3
829#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0
830#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0
831#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0
832#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0
833#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0
834#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0
835#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0
836#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0
837#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0
838#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0
839#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0
840#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0
841#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1
842#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0
843#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0
844#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0
845#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0
846#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
847#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0
848#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0
849#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0
850#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0
851#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0
852#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0
853#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3
854#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0
855#define MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0
856#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0
857#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
858#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0
859#define MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0
860#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3
861#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0
862#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0
863#define MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0
864#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0
865#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4
866#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0
867#define MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0
868#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5
869#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0
870#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0
871#define MX6Q_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0
872#define MX6Q_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0
873#define MX6Q_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
874#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
875#define MX6Q_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0
876#define MX6Q_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0
877#define MX6Q_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3
878#define MX6Q_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0
879#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
880#define MX6Q_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0
881#define MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0
882#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0
883#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
884#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
885#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0
886#define MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0
887#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3
888#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0
889#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
890#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0
891#define MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0
892#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0
893#define MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0
894#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0
895#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4
896#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0
897#define MX6Q_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0
898#define MX6Q_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5
899#define MX6Q_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0
900#define MX6Q_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0
901#define MX6Q_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0
902#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0
903#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0
904#define MX6Q_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0
905#define MX6Q_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0
906#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0
907#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0
908#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0
909#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0
910#define MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0
911#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0
912#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0
913#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0
914#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0
915#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0
916#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0
917#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
918#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0
919#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0
920#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0
921#define MX6Q_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
922#define MX6Q_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0
923#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0
924#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0
925#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0
926#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0
927#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0
928#define MX6Q_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
929#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0
930#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0
931#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0
932#define MX6Q_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0
933#define MX6Q_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0
934#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
935#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
936#define MX6Q_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0
937#define MX6Q_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0
938#define MX6Q_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0
939#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
940#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
941#define MX6Q_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0
942#define MX6Q_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0
943#define MX6Q_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0
944#define MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0
945#define MX6Q_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0
946#define MX6Q_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0
947#define MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0
948#define MX6Q_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0
949#define MX6Q_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0
950#define MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0
951#define MX6Q_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0
952#define MX6Q_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0
953#define MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0
954#define MX6Q_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0
955#define MX6Q_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0
956#define MX6Q_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0
957#define MX6Q_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0
958#define MX6Q_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0
959#define MX6Q_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0
960#define MX6Q_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0
961#define MX6Q_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0
962#define MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0
963#define MX6Q_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0
964#define MX6Q_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0
965#define MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0
966#define MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0
967#define MX6Q_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
968#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0
969#define MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0
970#define MX6Q_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
971#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0
972#define MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0
973#define MX6Q_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
974#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0
975#define MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0
976#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0
977#define MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0
978#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
979#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
980#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0
981#define MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0
982#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
983#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
984#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0
985#define MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0
986#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
987#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
988#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0
989#define MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0
990#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
991#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
992#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0
993#define MX6Q_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0
994#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1
995#define MX6Q_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
996#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0
997#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0
998#define MX6Q_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0
999#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1
1000#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0
1001#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0
1002#define MX6Q_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0
1003#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0
1004#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
1005#define MX6Q_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0
1006#define MX6Q_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0
1007#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0
1008#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0
1009#define MX6Q_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0
1010#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0
1011#define MX6Q_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
1012#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0
1013#define MX6Q_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0
1014#define MX6Q_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0
1015#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1
1016#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
1017#define MX6Q_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0
1018#define MX6Q_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0
1019#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0
1020#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
1021#define MX6Q_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
1022#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
1023#define MX6Q_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
1024#define MX6Q_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
1025#define MX6Q_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
1026#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1
1027#define MX6Q_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
1028#define MX6Q_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1
1029#define MX6Q_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0
1030#define MX6Q_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0
1031#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1
1032#define MX6Q_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
1033#define MX6Q_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1
1034#define MX6Q_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0
1035#define MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0
1036#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0
1037#define MX6Q_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
1038#define MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1
1039#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0
1040
1041#endif /* __DTS_IMX6Q_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 656d489122fe..49d6f2831ec9 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -11,15 +11,13 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx6q.dtsi" 14
15#include "imx6q.dtsi"
16#include "imx6qdl-sabreauto.dtsi"
15 17
16/ { 18/ {
17 model = "Freescale i.MX6 Quad SABRE Automotive Board"; 19 model = "Freescale i.MX6 Quad SABRE Automotive Board";
18 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; 20 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x80000000>;
22 };
23}; 21};
24 22
25&iomuxc { 23&iomuxc {
@@ -29,30 +27,9 @@
29 hog { 27 hog {
30 pinctrl_hog: hoggrp { 28 pinctrl_hog: hoggrp {
31 fsl,pins = < 29 fsl,pins = <
32 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */ 30 MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
33 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */ 31 MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
34 >; 32 >;
35 }; 33 };
36 }; 34 };
37}; 35};
38
39&uart4 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_uart4_1>;
42 status = "okay";
43};
44
45&fec {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_enet_2>;
48 phy-mode = "rgmii";
49 status = "okay";
50};
51
52&usdhc3 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_usdhc3_1>;
55 cd-gpios = <&gpio6 15 0>;
56 wp-gpios = <&gpio1 13 0>;
57 status = "okay";
58};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 2ce355cd05e5..6a000666c147 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx6q.dtsi" 14#include "imx6q.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX6 Quad SABRE Lite Board"; 17 model = "Freescale i.MX6 Quad SABRE Lite Board";
@@ -91,14 +91,14 @@
91 hog { 91 hog {
92 pinctrl_hog: hoggrp { 92 pinctrl_hog: hoggrp {
93 fsl,pins = < 93 fsl,pins = <
94 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ 94 MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
95 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ 95 MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
96 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ 96 MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
97 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ 97 MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
98 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ 98 MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
99 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ 99 MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
100 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ 100 MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
101 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ 101 MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
102 >; 102 >;
103 }; 103 };
104 }; 104 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 2dea304a7980..442051350225 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -11,37 +11,13 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "imx6q.dtsi" 14
15#include "imx6q.dtsi"
16#include "imx6qdl-sabresd.dtsi"
15 17
16/ { 18/ {
17 model = "Freescale i.MX6Q SABRE Smart Device Board"; 19 model = "Freescale i.MX6 Quad SABRE Smart Device Board";
18 compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; 20 compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 gpio-keys {
25 compatible = "gpio-keys";
26
27 volume-up {
28 label = "Volume Up";
29 gpios = <&gpio1 4 0>;
30 linux,code = <115>; /* KEY_VOLUMEUP */
31 };
32
33 volume-down {
34 label = "Volume Down";
35 gpios = <&gpio1 5 0>;
36 linux,code = <114>; /* KEY_VOLUMEDOWN */
37 };
38 };
39};
40
41&uart1 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_uart1_1>;
44 status = "okay";
45}; 21};
46 22
47&iomuxc { 23&iomuxc {
@@ -51,36 +27,13 @@
51 hog { 27 hog {
52 pinctrl_hog: hoggrp { 28 pinctrl_hog: hoggrp {
53 fsl,pins = < 29 fsl,pins = <
54 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */ 30 MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000
55 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */ 31 MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000
56 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ 32 MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
57 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ 33 MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
58 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ 34 MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
59 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ 35 MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
60 >; 36 >;
61 }; 37 };
62 }; 38 };
63}; 39};
64
65&fec {
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_enet_1>;
68 phy-mode = "rgmii";
69 status = "okay";
70};
71
72&usdhc2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_usdhc2_1>;
75 cd-gpios = <&gpio2 2 0>;
76 wp-gpios = <&gpio2 3 0>;
77 status = "okay";
78};
79
80&usdhc3 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_usdhc3_1>;
83 cd-gpios = <&gpio2 0 0>;
84 wp-gpios = <&gpio2 1 0>;
85 status = "okay";
86};
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
new file mode 100644
index 000000000000..ee6addf149af
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2013 Pavel Machek <pavel@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License V2.
6 */
7
8/dts-v1/;
9#include "imx6q.dtsi"
10
11/ {
12 model = "MicroSys sbc6x board";
13 compatible = "microsys,sbc6x", "fsl,imx6q";
14
15 memory {
16 reg = <0x10000000 0x80000000>;
17 };
18};
19
20&fec {
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_enet_1>;
23 phy-mode = "rgmii";
24 status = "okay";
25};
26
27&uart1 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_uart1_1>;
30 status = "okay";
31};
32
33&usbotg {
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_usbotg_1>;
36 disable-over-current;
37 status = "okay";
38};
39
40&usdhc3 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_usdhc3_2>;
43 status = "okay";
44};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index cba021eb035e..21e675848bd1 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -8,7 +8,8 @@
8 * 8 *
9 */ 9 */
10 10
11/include/ "imx6qdl.dtsi" 11#include "imx6qdl.dtsi"
12#include "imx6q-pinfunc.h"
12 13
13/ { 14/ {
14 cpus { 15 cpus {
@@ -78,10 +79,19 @@
78 audmux { 79 audmux {
79 pinctrl_audmux_1: audmux-1 { 80 pinctrl_audmux_1: audmux-1 {
80 fsl,pins = < 81 fsl,pins = <
81 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ 82 MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
82 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ 83 MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
83 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ 84 MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
84 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ 85 MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
86 >;
87 };
88
89 pinctrl_audmux_2: audmux-2 {
90 fsl,pins = <
91 MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
92 MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
93 MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
94 MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
85 >; 95 >;
86 }; 96 };
87 }; 97 };
@@ -89,9 +99,19 @@
89 ecspi1 { 99 ecspi1 {
90 pinctrl_ecspi1_1: ecspi1grp-1 { 100 pinctrl_ecspi1_1: ecspi1grp-1 {
91 fsl,pins = < 101 fsl,pins = <
92 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ 102 MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
93 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ 103 MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
94 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ 104 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
105 >;
106 };
107 };
108
109 ecspi3 {
110 pinctrl_ecspi3_1: ecspi3grp-1 {
111 fsl,pins = <
112 MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
113 MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
114 MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
95 >; 115 >;
96 }; 116 };
97 }; 117 };
@@ -99,42 +119,42 @@
99 enet { 119 enet {
100 pinctrl_enet_1: enetgrp-1 { 120 pinctrl_enet_1: enetgrp-1 {
101 fsl,pins = < 121 fsl,pins = <
102 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ 122 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
103 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ 123 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
104 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ 124 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
105 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ 125 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
106 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ 126 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
107 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ 127 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
108 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ 128 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
109 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ 129 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
110 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ 130 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
111 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ 131 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
112 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ 132 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
113 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ 133 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
114 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ 134 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
115 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ 135 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
116 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ 136 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
117 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ 137 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
118 >; 138 >;
119 }; 139 };
120 140
121 pinctrl_enet_2: enetgrp-2 { 141 pinctrl_enet_2: enetgrp-2 {
122 fsl,pins = < 142 fsl,pins = <
123 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ 143 MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
124 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ 144 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
125 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ 145 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
126 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ 146 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
127 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ 147 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
128 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ 148 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
129 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ 149 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
130 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ 150 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
131 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ 151 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
132 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ 152 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
133 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ 153 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
134 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ 154 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
135 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ 155 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
136 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ 156 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
137 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ 157 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
138 >; 158 >;
139 }; 159 };
140 }; 160 };
@@ -142,25 +162,25 @@
142 gpmi-nand { 162 gpmi-nand {
143 pinctrl_gpmi_nand_1: gpmi-nand-1 { 163 pinctrl_gpmi_nand_1: gpmi-nand-1 {
144 fsl,pins = < 164 fsl,pins = <
145 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ 165 MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
146 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ 166 MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
147 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ 167 MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
148 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ 168 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
149 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ 169 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
150 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ 170 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
151 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ 171 MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
152 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ 172 MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
153 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ 173 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
154 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ 174 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
155 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ 175 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
156 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ 176 MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
157 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ 177 MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
158 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ 178 MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
159 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ 179 MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
160 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ 180 MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
161 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ 181 MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
162 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ 182 MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
163 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ 183 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
164 >; 184 >;
165 }; 185 };
166 }; 186 };
@@ -168,8 +188,26 @@
168 i2c1 { 188 i2c1 {
169 pinctrl_i2c1_1: i2c1grp-1 { 189 pinctrl_i2c1_1: i2c1grp-1 {
170 fsl,pins = < 190 fsl,pins = <
171 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ 191 MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
172 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ 192 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
193 >;
194 };
195 };
196
197 i2c2 {
198 pinctrl_i2c2_1: i2c2grp-1 {
199 fsl,pins = <
200 MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
201 MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
202 >;
203 };
204 };
205
206 i2c3 {
207 pinctrl_i2c3_1: i2c3grp-1 {
208 fsl,pins = <
209 MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
210 MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
173 >; 211 >;
174 }; 212 };
175 }; 213 };
@@ -177,8 +215,8 @@
177 uart1 { 215 uart1 {
178 pinctrl_uart1_1: uart1grp-1 { 216 pinctrl_uart1_1: uart1grp-1 {
179 fsl,pins = < 217 fsl,pins = <
180 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ 218 MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
181 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ 219 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
182 >; 220 >;
183 }; 221 };
184 }; 222 };
@@ -186,8 +224,8 @@
186 uart2 { 224 uart2 {
187 pinctrl_uart2_1: uart2grp-1 { 225 pinctrl_uart2_1: uart2grp-1 {
188 fsl,pins = < 226 fsl,pins = <
189 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ 227 MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
190 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ 228 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
191 >; 229 >;
192 }; 230 };
193 }; 231 };
@@ -195,8 +233,8 @@
195 uart4 { 233 uart4 {
196 pinctrl_uart4_1: uart4grp-1 { 234 pinctrl_uart4_1: uart4grp-1 {
197 fsl,pins = < 235 fsl,pins = <
198 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ 236 MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
199 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ 237 MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
200 >; 238 >;
201 }; 239 };
202 }; 240 };
@@ -204,7 +242,13 @@
204 usbotg { 242 usbotg {
205 pinctrl_usbotg_1: usbotggrp-1 { 243 pinctrl_usbotg_1: usbotggrp-1 {
206 fsl,pins = < 244 fsl,pins = <
207 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ 245 MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
246 >;
247 };
248
249 pinctrl_usbotg_2: usbotggrp-2 {
250 fsl,pins = <
251 MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
208 >; 252 >;
209 }; 253 };
210 }; 254 };
@@ -212,16 +256,16 @@
212 usdhc2 { 256 usdhc2 {
213 pinctrl_usdhc2_1: usdhc2grp-1 { 257 pinctrl_usdhc2_1: usdhc2grp-1 {
214 fsl,pins = < 258 fsl,pins = <
215 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ 259 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
216 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ 260 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
217 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ 261 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
218 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ 262 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
219 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ 263 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
220 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ 264 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
221 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ 265 MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
222 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ 266 MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
223 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ 267 MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
224 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ 268 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
225 >; 269 >;
226 }; 270 };
227 }; 271 };
@@ -229,27 +273,27 @@
229 usdhc3 { 273 usdhc3 {
230 pinctrl_usdhc3_1: usdhc3grp-1 { 274 pinctrl_usdhc3_1: usdhc3grp-1 {
231 fsl,pins = < 275 fsl,pins = <
232 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ 276 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
233 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ 277 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
234 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ 278 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
235 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ 279 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
236 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ 280 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
237 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ 281 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
238 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ 282 MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
239 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ 283 MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
240 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ 284 MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
241 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ 285 MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
242 >; 286 >;
243 }; 287 };
244 288
245 pinctrl_usdhc3_2: usdhc3grp-2 { 289 pinctrl_usdhc3_2: usdhc3grp-2 {
246 fsl,pins = < 290 fsl,pins = <
247 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ 291 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
248 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ 292 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
249 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ 293 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
250 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ 294 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
251 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ 295 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
252 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ 296 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
253 >; 297 >;
254 }; 298 };
255 }; 299 };
@@ -257,27 +301,27 @@
257 usdhc4 { 301 usdhc4 {
258 pinctrl_usdhc4_1: usdhc4grp-1 { 302 pinctrl_usdhc4_1: usdhc4grp-1 {
259 fsl,pins = < 303 fsl,pins = <
260 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ 304 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
261 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ 305 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
262 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ 306 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
263 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ 307 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
264 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ 308 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
265 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ 309 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
266 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ 310 MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
267 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ 311 MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
268 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ 312 MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
269 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ 313 MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
270 >; 314 >;
271 }; 315 };
272 316
273 pinctrl_usdhc4_2: usdhc4grp-2 { 317 pinctrl_usdhc4_2: usdhc4grp-2 {
274 fsl,pins = < 318 fsl,pins = <
275 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ 319 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
276 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ 320 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
277 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ 321 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
278 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ 322 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
279 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ 323 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
280 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ 324 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
281 >; 325 >;
282 }; 326 };
283 }; 327 };
@@ -291,6 +335,24 @@
291 interrupts = <0 8 0x4 0 7 0x4>; 335 interrupts = <0 8 0x4 0 7 0x4>;
292 clocks = <&clks 133>, <&clks 134>, <&clks 137>; 336 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
293 clock-names = "bus", "di0", "di1"; 337 clock-names = "bus", "di0", "di1";
338 resets = <&src 4>;
294 }; 339 };
295 }; 340 };
296}; 341};
342
343&ldb {
344 clocks = <&clks 33>, <&clks 34>,
345 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
346 <&clks 135>, <&clks 136>;
347 clock-names = "di0_pll", "di1_pll",
348 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
349 "di0", "di1";
350
351 lvds-channel@0 {
352 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
353 };
354
355 lvds-channel@1 {
356 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
357 };
358};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
new file mode 100644
index 000000000000..4d237cffcc41
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/ {
14 memory {
15 reg = <0x10000000 0x80000000>;
16 };
17};
18
19&fec {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_enet_2>;
22 phy-mode = "rgmii";
23 status = "okay";
24};
25
26&uart4 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_uart4_1>;
29 status = "okay";
30};
31
32&usdhc3 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_usdhc3_1>;
35 cd-gpios = <&gpio6 15 0>;
36 wp-gpios = <&gpio1 13 0>;
37 status = "okay";
38};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
new file mode 100644
index 000000000000..e21f6a89cf0f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -0,0 +1,87 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/ {
14 memory {
15 reg = <0x10000000 0x40000000>;
16 };
17
18 regulators {
19 compatible = "simple-bus";
20
21 reg_usb_otg_vbus: usb_otg_vbus {
22 compatible = "regulator-fixed";
23 regulator-name = "usb_otg_vbus";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 gpio = <&gpio3 22 0>;
27 enable-active-high;
28 };
29 };
30
31 gpio-keys {
32 compatible = "gpio-keys";
33
34 volume-up {
35 label = "Volume Up";
36 gpios = <&gpio1 4 0>;
37 linux,code = <115>; /* KEY_VOLUMEUP */
38 };
39
40 volume-down {
41 label = "Volume Down";
42 gpios = <&gpio1 5 0>;
43 linux,code = <114>; /* KEY_VOLUMEDOWN */
44 };
45 };
46};
47
48&fec {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_enet_1>;
51 phy-mode = "rgmii";
52 status = "okay";
53};
54
55&uart1 {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_uart1_1>;
58 status = "okay";
59};
60
61&usbh1 {
62 status = "okay";
63};
64
65&usbotg {
66 vbus-supply = <&reg_usb_otg_vbus>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_usbotg_2>;
69 disable-over-current;
70 status = "okay";
71};
72
73&usdhc2 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_usdhc2_1>;
76 cd-gpios = <&gpio2 2 0>;
77 wp-gpios = <&gpio2 3 0>;
78 status = "okay";
79};
80
81&usdhc3 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_usdhc3_1>;
84 cd-gpios = <&gpio2 0 0>;
85 wp-gpios = <&gpio2 1 0>;
86 status = "okay";
87};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 281a223591ff..3cca7d39529d 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -10,7 +10,7 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13/include/ "skeleton.dtsi" 13#include "skeleton.dtsi"
14 14
15/ { 15/ {
16 aliases { 16 aliases {
@@ -102,6 +102,11 @@
102 cache-level = <2>; 102 cache-level = <2>;
103 }; 103 };
104 104
105 pmu {
106 compatible = "arm,cortex-a9-pmu";
107 interrupts = <0 94 0x04>;
108 };
109
105 aips-bus@02000000 { /* AIPS1 */ 110 aips-bus@02000000 { /* AIPS1 */
106 compatible = "fsl,aips-bus", "simple-bus"; 111 compatible = "fsl,aips-bus", "simple-bus";
107 #address-cells = <1>; 112 #address-cells = <1>;
@@ -278,6 +283,8 @@
278 compatible = "fsl,imx6q-gpt"; 283 compatible = "fsl,imx6q-gpt";
279 reg = <0x02098000 0x4000>; 284 reg = <0x02098000 0x4000>;
280 interrupts = <0 55 0x04>; 285 interrupts = <0 55 0x04>;
286 clocks = <&clks 119>, <&clks 120>;
287 clock-names = "ipg", "per";
281 }; 288 };
282 289
283 gpio1: gpio@0209c000 { 290 gpio1: gpio@0209c000 {
@@ -514,9 +521,10 @@
514 }; 521 };
515 522
516 src: src@020d8000 { 523 src: src@020d8000 {
517 compatible = "fsl,imx6q-src"; 524 compatible = "fsl,imx6q-src", "fsl,imx51-src";
518 reg = <0x020d8000 0x4000>; 525 reg = <0x020d8000 0x4000>;
519 interrupts = <0 91 0x04 0 96 0x04>; 526 interrupts = <0 91 0x04 0 96 0x04>;
527 #reset-cells = <1>;
520 }; 528 };
521 529
522 gpc: gpc@020dc000 { 530 gpc: gpc@020dc000 {
@@ -530,6 +538,26 @@
530 reg = <0x020e0000 0x38>; 538 reg = <0x020e0000 0x38>;
531 }; 539 };
532 540
541 ldb: ldb@020e0008 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
545 gpr = <&gpr>;
546 status = "disabled";
547
548 lvds-channel@0 {
549 reg = <0>;
550 crtcs = <&ipu1 0>;
551 status = "disabled";
552 };
553
554 lvds-channel@1 {
555 reg = <1>;
556 crtcs = <&ipu1 1>;
557 status = "disabled";
558 };
559 };
560
533 dcic1: dcic@020e4000 { 561 dcic1: dcic@020e4000 {
534 reg = <0x020e4000 0x4000>; 562 reg = <0x020e4000 0x4000>;
535 interrupts = <0 124 0x04>; 563 interrupts = <0 124 0x04>;
@@ -796,6 +824,7 @@
796 interrupts = <0 6 0x4 0 5 0x4>; 824 interrupts = <0 6 0x4 0 5 0x4>;
797 clocks = <&clks 130>, <&clks 131>, <&clks 132>; 825 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
798 clock-names = "bus", "di0", "di1"; 826 clock-names = "bus", "di0", "di1";
827 resets = <&src 2>;
799 }; 828 };
800 }; 829 };
801}; 830};
diff --git a/arch/arm/boot/dts/imx6sl-pinfunc.h b/arch/arm/boot/dts/imx6sl-pinfunc.h
new file mode 100644
index 000000000000..77b17bcc7b70
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-pinfunc.h
@@ -0,0 +1,1077 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX6SL_PINFUNC_H
11#define __DTS_IMX6SL_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18#define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20#define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24#define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25#define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
27#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0
28#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0
29#define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0
30#define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0
31#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0
32#define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0
33#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0
34#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0
35#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0
36#define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0
37#define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0
38#define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0
39#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0
40#define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0
41#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1
42#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0
43#define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0
44#define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0
45#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0
46#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0
47#define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0
48#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0
49#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0
50#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1
51#define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0
52#define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0
53#define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0
54#define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0
55#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0
56#define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0
57#define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0
58#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0
59#define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0
60#define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0
61#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0
62#define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0
63#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1
64#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0
65#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0
66#define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0
67#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0
68#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0
69#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0
70#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0
71#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0
72#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0
73#define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0
74#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0
75#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0
76#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0
77#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0
78#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0
79#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0
80#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0
81#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0
82#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0
83#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0
84#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1
85#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0
86#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0
87#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0
88#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0
89#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0
90#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0
91#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0
92#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0
93#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1
94#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0
95#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0
96#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0
97#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0
98#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0
99#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0
100#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0
101#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0
102#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0
103#define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0
104#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0
105#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0
106#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0
107#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0
108#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0
109#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2
110#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0
111#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0
112#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0
113#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0
114#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1
115#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3
116#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0
117#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0
118#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0
119#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0
120#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1
121#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0
122#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0
123#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0
124#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1
125#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0
126#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0
127#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0
128#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0
129#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0
130#define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0
131#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2
132#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0
133#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0
134#define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0
135#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0
136#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0
137#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0
138#define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0
139#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0
140#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3
141#define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0
142#define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0
143#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0
144#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0
145#define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0
146#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0
147#define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0
148#define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0
149#define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0
150#define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0
151#define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0
152#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0
153#define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0
154#define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0
155#define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0
156#define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0
157#define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0
158#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1
159#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0
160#define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0
161#define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0
162#define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0
163#define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0
164#define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0
165#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1
166#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0
167#define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0
168#define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0
169#define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0
170#define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0
171#define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0
172#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0
173#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0
174#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0
175#define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0
176#define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0
177#define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0
178#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1
179#define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0
180#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0
181#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1
182#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0
183#define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0
184#define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0
185#define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0
186#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0
187#define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0
188#define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0
189#define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0
190#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0
191#define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0
192#define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0
193#define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0
194#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0
195#define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0
196#define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0
197#define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1
198#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0
199#define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0
200#define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0
201#define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0
202#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1
203#define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0
204#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0
205#define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0
206#define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0
207#define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0
208#define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0
209#define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0
210#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0
211#define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0
212#define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0
213#define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0
214#define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0
215#define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0
216#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0
217#define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0
218#define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0
219#define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0
220#define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0
221#define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0
222#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0
223#define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0
224#define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0
225#define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0
226#define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0
227#define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0
228#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0
229#define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0
230#define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0
231#define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0
232#define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0
233#define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0
234#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0
235#define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0
236#define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0
237#define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0
238#define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0
239#define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0
240#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1
241#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0
242#define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0
243#define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0
244#define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0
245#define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0
246#define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0
247#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1
248#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0
249#define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0
250#define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0
251#define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0
252#define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0
253#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0
254#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0
255#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0
256#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1
257#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0
258#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0
259#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0
260#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0
261#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0
262#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0
263#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1
264#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0
265#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0
266#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0
267#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0
268#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0
269#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0
270#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0
271#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0
272#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0
273#define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1
274#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0
275#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0
276#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0
277#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1
278#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0
279#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0
280#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1
281#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0
282#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0
283#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0
284#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0
285#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0
286#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0
287#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0
288#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0
289#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0
290#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0
291#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0
292#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0
293#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0
294#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0
295#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0
296#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0
297#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0
298#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0
299#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0
300#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0
301#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0
302#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0
303#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0
304#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0
305#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0
306#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0
307#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0
308#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1
309#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0
310#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0
311#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0
312#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0
313#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0
314#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0
315#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1
316#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1
317#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0
318#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0
319#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0
320#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0
321#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0
322#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0
323#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1
324#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0
325#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0
326#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0
327#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0
328#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0
329#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0
330#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0
331#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0
332#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0
333#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0
334#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0
335#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0
336#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0
337#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0
338#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0
339#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0
340#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0
341#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0
342#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0
343#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0
344#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0
345#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0
346#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0
347#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0
348#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0
349#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0
350#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1
351#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0
352#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0
353#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0
354#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0
355#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0
356#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1
357#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0
358#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0
359#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0
360#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0
361#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0
362#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1
363#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0
364#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0
365#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0
366#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0
367#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0
368#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1
369#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0
370#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0
371#define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0
372#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0
373#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0
374#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1
375#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0
376#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0
377#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0
378#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0
379#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0
380#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1
381#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0
382#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0
383#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0
384#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0
385#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0
386#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0
387#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4
388#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0
389#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0
390#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0
391#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0
392#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0
393#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0
394#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0
395#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0
396#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5
397#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0
398#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0
399#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0
400#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0
401#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1
402#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1
403#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0
404#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1
405#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0
406#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0
407#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0
408#define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0
409#define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0
410#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0
411#define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0
412#define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0
413#define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0
414#define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0
415#define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1
416#define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1
417#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0
418#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1
419#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0
420#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0
421#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0
422#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0
423#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0
424#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0
425#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0
426#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0
427#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0
428#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2
429#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1
430#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1
431#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0
432#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1
433#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0
434#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0
435#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0
436#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0
437#define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0
438#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1
439#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0
440#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0
441#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0
442#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0
443#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1
444#define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1
445#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0
446#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1
447#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0
448#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0
449#define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0
450#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1
451#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1
452#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0
453#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1
454#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0
455#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0
456#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0
457#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0
458#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0
459#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0
460#define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1
461#define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1
462#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0
463#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0
464#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0
465#define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1
466#define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0
467#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1
468#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0
469#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0
470#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0
471#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0
472#define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0
473#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0
474#define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1
475#define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1
476#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0
477#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0
478#define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0
479#define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1
480#define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0
481#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0
482#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0
483#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0
484#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1
485#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0
486#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0
487#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0
488#define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2
489#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0
490#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0
491#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1
492#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1
493#define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0
494#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0
495#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0
496#define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2
497#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0
498#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1
499#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1
500#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0
501#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0
502#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0
503#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0
504#define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1
505#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0
506#define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1
507#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0
508#define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2
509#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0
510#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0
511#define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1
512#define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0
513#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0
514#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0
515#define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2
516#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0
517#define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0
518#define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2
519#define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0
520#define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0
521#define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2
522#define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0
523#define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0
524#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2
525#define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0
526#define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0
527#define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0
528#define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0
529#define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0
530#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2
531#define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0
532#define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0
533#define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0
534#define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0
535#define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0
536#define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1
537#define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0
538#define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0
539#define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1
540#define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0
541#define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0
542#define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0
543#define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1
544#define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0
545#define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0
546#define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2
547#define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0
548#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0
549#define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0
550#define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1
551#define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0
552#define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0
553#define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2
554#define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0
555#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0
556#define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0
557#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2
558#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0
559#define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0
560#define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0
561#define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2
562#define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0
563#define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0
564#define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0
565#define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2
566#define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0
567#define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0
568#define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0
569#define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1
570#define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0
571#define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2
572#define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0
573#define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2
574#define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0
575#define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0
576#define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3
577#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0
578#define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0
579#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2
580#define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0
581#define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0
582#define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0
583#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0
584#define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0
585#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2
586#define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0
587#define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0
588#define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0
589#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0
590#define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0
591#define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1
592#define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0
593#define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0
594#define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1
595#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0
596#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0
597#define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0
598#define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1
599#define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0
600#define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0
601#define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2
602#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0
603#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1
604#define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0
605#define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1
606#define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0
607#define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0
608#define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2
609#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0
610#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2
611#define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0
612#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0
613#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3
614#define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0
615#define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0
616#define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2
617#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0
618#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0
619#define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0
620#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0
621#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3
622#define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0
623#define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0
624#define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1
625#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0
626#define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3
627#define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0
628#define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2
629#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0
630#define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0
631#define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0
632#define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0
633#define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1
634#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1
635#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1
636#define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0
637#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0
638#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0
639#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0
640#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0
641#define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1
642#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1
643#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2
644#define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0
645#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1
646#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0
647#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0
648#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0
649#define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1
650#define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1
651#define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1
652#define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0
653#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2
654#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0
655#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0
656#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0
657#define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1
658#define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1
659#define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1
660#define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0
661#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1
662#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0
663#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0
664#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0
665#define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1
666#define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1
667#define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1
668#define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0
669#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2
670#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0
671#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0
672#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0
673#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0
674#define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1
675#define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1
676#define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1
677#define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0
678#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0
679#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3
680#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0
681#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0
682#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0
683#define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1
684#define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1
685#define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1
686#define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0
687#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2
688#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0
689#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0
690#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0
691#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0
692#define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1
693#define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1
694#define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1
695#define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0
696#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0
697#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3
698#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0
699#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0
700#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0
701#define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1
702#define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1
703#define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1
704#define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0
705#define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3
706#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0
707#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0
708#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0
709#define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1
710#define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1
711#define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1
712#define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0
713#define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3
714#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0
715#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0
716#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0
717#define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1
718#define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1
719#define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0
720#define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0
721#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1
722#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0
723#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0
724#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0
725#define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1
726#define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1
727#define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0
728#define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0
729#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1
730#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0
731#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0
732#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0
733#define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1
734#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1
735#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0
736#define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0
737#define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1
738#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0
739#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0
740#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0
741#define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1
742#define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1
743#define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0
744#define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0
745#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0
746#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0
747#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0
748#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0
749#define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1
750#define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1
751#define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0
752#define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0
753#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0
754#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0
755#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0
756#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0
757#define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1
758#define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1
759#define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1
760#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0
761#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0
762#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0
763#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0
764#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0
765#define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1
766#define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1
767#define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1
768#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0
769#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1
770#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0
771#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0
772#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0
773#define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1
774#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1
775#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0
776#define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0
777#define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1
778#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0
779#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0
780#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0
781#define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1
782#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1
783#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2
784#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0
785#define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1
786#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0
787#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0
788#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0
789#define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1
790#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1
791#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2
792#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0
793#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1
794#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0
795#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0
796#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0
797#define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1
798#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1
799#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2
800#define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0
801#define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1
802#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0
803#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0
804#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0
805#define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1
806#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1
807#define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0
808#define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0
809#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0
810#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0
811#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0
812#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0
813#define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1
814#define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1
815#define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1
816#define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0
817#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2
818#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0
819#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0
820#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0
821#define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1
822#define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1
823#define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1
824#define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0
825#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2
826#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0
827#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0
828#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0
829#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0
830#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2
831#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0
832#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0
833#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2
834#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0
835#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0
836#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0
837#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2
838#define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0
839#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0
840#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0
841#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3
842#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0
843#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0
844#define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0
845#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1
846#define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1
847#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1
848#define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0
849#define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2
850#define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0
851#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1
852#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0
853#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2
854#define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0
855#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0
856#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3
857#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0
858#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0
859#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0
860#define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0
861#define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0
862#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0
863#define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0
864#define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0
865#define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0
866#define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0
867#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0
868#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2
869#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0
870#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2
871#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2
872#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0
873#define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3
874#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0
875#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2
876#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0
877#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3
878#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0
879#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0
880#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3
881#define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0
882#define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2
883#define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2
884#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0
885#define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0
886#define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0
887#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2
888#define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2
889#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0
890#define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0
891#define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0
892#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2
893#define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2
894#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0
895#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0
896#define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0
897#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2
898#define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2
899#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0
900#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0
901#define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0
902#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2
903#define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2
904#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0
905#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0
906#define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0
907#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0
908#define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2
909#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0
910#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0
911#define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0
912#define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0
913#define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2
914#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0
915#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4
916#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0
917#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0
918#define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0
919#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2
920#define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2
921#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0
922#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0
923#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5
924#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0
925#define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0
926#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0
927#define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2
928#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0
929#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4
930#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0
931#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0
932#define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0
933#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0
934#define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2
935#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3
936#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0
937#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5
938#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0
939#define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0
940#define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2
941#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2
942#define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2
943#define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0
944#define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0
945#define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2
946#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2
947#define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2
948#define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0
949#define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0
950#define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0
951#define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2
952#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2
953#define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2
954#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4
955#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0
956#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0
957#define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0
958#define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2
959#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2
960#define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2
961#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0
962#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5
963#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0
964#define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0
965#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2
966#define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1
967#define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2
968#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4
969#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0
970#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0
971#define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0
972#define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2
973#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1
974#define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2
975#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0
976#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5
977#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0
978#define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0
979#define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1
980#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4
981#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0
982#define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2
983#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0
984#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0
985#define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0
986#define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1
987#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0
988#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5
989#define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2
990#define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2
991#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0
992#define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0
993#define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1
994#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4
995#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0
996#define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2
997#define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2
998#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0
999#define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0
1000#define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1
1001#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0
1002#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5
1003#define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2
1004#define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2
1005#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0
1006#define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0
1007#define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0
1008#define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0
1009#define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0
1010#define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0
1011#define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0
1012#define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0
1013#define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1
1014#define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2
1015#define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2
1016#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0
1017#define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0
1018#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0
1019#define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0
1020#define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1
1021#define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2
1022#define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2
1023#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3
1024#define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0
1025#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0
1026#define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0
1027#define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1
1028#define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2
1029#define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1
1030#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4
1031#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0
1032#define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0
1033#define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1
1034#define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2
1035#define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1
1036#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0
1037#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0
1038#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0
1039#define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0
1040#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1
1041#define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2
1042#define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1
1043#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0
1044#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0
1045#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3
1046#define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0
1047#define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1
1048#define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2
1049#define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1
1050#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0
1051#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0
1052#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2
1053#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0
1054#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0
1055#define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0
1056#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6
1057#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0
1058#define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2
1059#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6
1060#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0
1061#define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0
1062#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0
1063#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1
1064#define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0
1065#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0
1066#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7
1067#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2
1068#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0
1069#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7
1070#define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0
1071#define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0
1072#define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0
1073#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0
1074#define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0
1075#define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0
1076
1077#endif /* __DTS_IMX6SL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/include/dt-bindings b/arch/arm/boot/dts/include/dt-bindings
new file mode 120000
index 000000000000..08c00e4972fa
--- /dev/null
+++ b/arch/arm/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
../../../../../include/dt-bindings \ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 192cf76fbf93..23991e45bc55 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,12 @@
49 }; 49 };
50 }; 50 };
51 51
52 thermal@10078 {
53 compatible = "marvell,kirkwood-thermal";
54 reg = <0x10078 0x4>;
55 status = "okay";
56 };
57
52 i2c@11100 { 58 i2c@11100 {
53 compatible = "marvell,mv64xxx-i2c"; 59 compatible = "marvell,mv64xxx-i2c";
54 reg = <0x11100 0x20>; 60 reg = <0x11100 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 9555a86297c2..44fd97dfc1f3 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -69,6 +69,10 @@
69 status = "okay"; 69 status = "okay";
70 nr-ports = <1>; 70 nr-ports = <1>;
71 }; 71 };
72
73 mvsdio@90000 {
74 status = "okay";
75 };
72 }; 76 };
73 77
74 gpio-leds { 78 gpio-leds {
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
new file mode 100644
index 000000000000..317300875f34
--- /dev/null
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -0,0 +1,69 @@
1/*
2 * mpa1600.dts - Device Tree file for Phontech MPA 1600
3 *
4 * Copyright (C) 2013 Joachim Eastwood <manabian@gmail.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91rm9200.dtsi"
10
11/ {
12 model = "Phontech MPA 1600";
13 compatible = "phontech,mpa1600", "atmel,at91rm9200";
14
15 memory {
16 reg = <0x20000000 0x4000000>;
17 };
18
19 clocks {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 main_clock: clock@0 {
25 compatible = "atmel,osc", "fixed-clock";
26 clock-frequency = <18432000>;
27 };
28 };
29
30 ahb {
31 apb {
32 dbgu: serial@fffff200 {
33 status = "okay";
34 };
35
36 macb0: ethernet@fffbc000 {
37 phy-mode = "rmii";
38 status = "okay";
39 };
40
41 ssc0: ssc@fffd0000 {
42 status = "okay";
43 };
44
45 ssc1: ssc@fffd4000 {
46 status = "okay";
47 };
48 };
49
50 usb0: ohci@00300000 {
51 num-ports = <1>;
52 status = "okay";
53 };
54 };
55
56 i2c@0 {
57 status = "okay";
58 };
59
60 gpio_keys {
61 compatible = "gpio-keys";
62
63 monitor_mute {
64 label = "Monitor mute";
65 gpios = <&pioC 1 1>;
66 linux,code = <113>;
67 };
68 };
69};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index f7bec3b1ba32..892c64e3f1e1 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -74,6 +74,20 @@
74 status = "okay"; 74 status = "okay";
75 }; 75 };
76 76
77 ehci@50000 {
78 compatible = "marvell,orion-ehci";
79 reg = <0x50000 0x1000>;
80 interrupts = <17>;
81 status = "disabled";
82 };
83
84 ehci@a0000 {
85 compatible = "marvell,orion-ehci";
86 reg = <0xa0000 0x1000>;
87 interrupts = <12>;
88 status = "disabled";
89 };
90
77 sata@80000 { 91 sata@80000 {
78 compatible = "marvell,orion-sata"; 92 compatible = "marvell,orion-sata";
79 reg = <0x80000 0x5000>; 93 reg = <0x80000 0x5000>;
@@ -91,6 +105,25 @@
91 status = "disabled"; 105 status = "disabled";
92 }; 106 };
93 107
108 xor@60900 {
109 compatible = "marvell,orion-xor";
110 reg = <0x60900 0x100
111 0x60b00 0x100>;
112 status = "okay";
113
114 xor00 {
115 interrupts = <30>;
116 dmacap,memcpy;
117 dmacap,xor;
118 };
119 xor01 {
120 interrupts = <31>;
121 dmacap,memcpy;
122 dmacap,xor;
123 dmacap,memset;
124 };
125 };
126
94 crypto@90000 { 127 crypto@90000 {
95 compatible = "marvell,orion-crypto"; 128 compatible = "marvell,orion-crypto";
96 reg = <0x90000 0x10000>, 129 reg = <0x90000 0x10000>,
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi
new file mode 100644
index 000000000000..15994158a998
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton64.dtsi
@@ -0,0 +1,13 @@
1/*
2 * Skeleton device tree in the 64 bits version; the bare minimum
3 * needed to boot; just include and add a compatible value. The
4 * bootloader will typically populate the memory node.
5 */
6
7/ {
8 #address-cells = <2>;
9 #size-cells = <2>;
10 chosen { };
11 aliases { };
12 memory { device_type = "memory"; reg = <0 0>; };
13};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 5cab82540437..b70fe0db6bb7 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -26,13 +26,37 @@
26 bootargs = "earlyprintk console=ttyS0,115200"; 26 bootargs = "earlyprintk console=ttyS0,115200";
27 }; 27 };
28 28
29 soc { 29 soc@01c20000 {
30 uart0: uart@01c28000 { 30 pinctrl@01c20800 {
31 status = "okay"; 31 led_pins_cubieboard: led_pins@0 {
32 allwinner,pins = "PH20", "PH21";
33 allwinner,function = "gpio_out";
34 allwinner,drive = <1>;
35 allwinner,pull = <0>;
36 };
32 }; 37 };
33 38
34 uart1: uart@01c28400 { 39 uart0: serial@01c28000 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&uart0_pins_a>;
35 status = "okay"; 42 status = "okay";
36 }; 43 };
37 }; 44 };
45
46 leds {
47 compatible = "gpio-leds";
48 pinctrl-names = "default";
49 pinctrl-0 = <&led_pins_cubieboard>;
50
51 blue {
52 label = "cubieboard::blue";
53 gpios = <&pio 7 21 0>; /* LED1 */
54 };
55
56 green {
57 label = "cubieboard::green";
58 gpios = <&pio 7 20 0>; /* LED2 */
59 linux,default-trigger = "heartbeat";
60 };
61 };
38}; 62};
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index f84549ad791e..b9efac100c85 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -22,8 +22,10 @@
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
23 }; 23 };
24 24
25 soc { 25 soc@01c20000 {
26 uart0: uart@01c28000 { 26 uart0: serial@01c28000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>;
27 status = "okay"; 29 status = "okay";
28 }; 30 };
29 }; 31 };
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
new file mode 100644
index 000000000000..4a7c35d6726a
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun4i-a10.dtsi"
16
17/ {
18 model = "PineRiver Mini X-Plus";
19 compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc {
26 uart0: uart@01c28000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>;
29 status = "okay";
30 };
31 };
32};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index f99f60dadf5d..e7ef619a70a2 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -10,19 +10,174 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13/include/ "sunxi.dtsi" 13/include/ "skeleton.dtsi"
14 14
15/ { 15/ {
16 interrupt-parent = <&intc>;
17
18 cpus {
19 cpu@0 {
20 compatible = "arm,cortex-a8";
21 };
22 };
23
16 memory { 24 memory {
17 reg = <0x40000000 0x80000000>; 25 reg = <0x40000000 0x80000000>;
18 }; 26 };
19 27
20 soc { 28 clocks {
21 pinctrl@01c20800 { 29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges;
32
33 /*
34 * This is a dummy clock, to be used as placeholder on
35 * other mux clocks when a specific parent clock is not
36 * yet implemented. It should be dropped when the driver
37 * is complete.
38 */
39 dummy: dummy {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <0>;
43 };
44
45 osc24M: osc24M@01c20050 {
46 #clock-cells = <0>;
47 compatible = "allwinner,sun4i-osc-clk";
48 reg = <0x01c20050 0x4>;
49 clock-frequency = <24000000>;
50 };
51
52 osc32k: osc32k {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <32768>;
56 };
57
58 pll1: pll1@01c20000 {
59 #clock-cells = <0>;
60 compatible = "allwinner,sun4i-pll1-clk";
61 reg = <0x01c20000 0x4>;
62 clocks = <&osc24M>;
63 };
64
65 /* dummy is 200M */
66 cpu: cpu@01c20054 {
67 #clock-cells = <0>;
68 compatible = "allwinner,sun4i-cpu-clk";
69 reg = <0x01c20054 0x4>;
70 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
71 };
72
73 axi: axi@01c20054 {
74 #clock-cells = <0>;
75 compatible = "allwinner,sun4i-axi-clk";
76 reg = <0x01c20054 0x4>;
77 clocks = <&cpu>;
78 };
79
80 axi_gates: axi_gates@01c2005c {
81 #clock-cells = <1>;
82 compatible = "allwinner,sun4i-axi-gates-clk";
83 reg = <0x01c2005c 0x4>;
84 clocks = <&axi>;
85 clock-output-names = "axi_dram";
86 };
87
88 ahb: ahb@01c20054 {
89 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-ahb-clk";
91 reg = <0x01c20054 0x4>;
92 clocks = <&axi>;
93 };
94
95 ahb_gates: ahb_gates@01c20060 {
96 #clock-cells = <1>;
97 compatible = "allwinner,sun4i-ahb-gates-clk";
98 reg = <0x01c20060 0x8>;
99 clocks = <&ahb>;
100 clock-output-names = "ahb_usb0", "ahb_ehci0",
101 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
102 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
103 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
104 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
105 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
106 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
107 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
108 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
109 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
110 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
111 };
112
113 apb0: apb0@01c20054 {
114 #clock-cells = <0>;
115 compatible = "allwinner,sun4i-apb0-clk";
116 reg = <0x01c20054 0x4>;
117 clocks = <&ahb>;
118 };
119
120 apb0_gates: apb0_gates@01c20068 {
121 #clock-cells = <1>;
122 compatible = "allwinner,sun4i-apb0-gates-clk";
123 reg = <0x01c20068 0x4>;
124 clocks = <&apb0>;
125 clock-output-names = "apb0_codec", "apb0_spdif",
126 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
127 "apb0_ir1", "apb0_keypad";
128 };
129
130 /* dummy is pll62 */
131 apb1_mux: apb1_mux@01c20058 {
132 #clock-cells = <0>;
133 compatible = "allwinner,sun4i-apb1-mux-clk";
134 reg = <0x01c20058 0x4>;
135 clocks = <&osc24M>, <&dummy>, <&osc32k>;
136 };
137
138 apb1: apb1@01c20058 {
139 #clock-cells = <0>;
140 compatible = "allwinner,sun4i-apb1-clk";
141 reg = <0x01c20058 0x4>;
142 clocks = <&apb1_mux>;
143 };
144
145 apb1_gates: apb1_gates@01c2006c {
146 #clock-cells = <1>;
147 compatible = "allwinner,sun4i-apb1-gates-clk";
148 reg = <0x01c2006c 0x4>;
149 clocks = <&apb1>;
150 clock-output-names = "apb1_i2c0", "apb1_i2c1",
151 "apb1_i2c2", "apb1_can", "apb1_scr",
152 "apb1_ps20", "apb1_ps21", "apb1_uart0",
153 "apb1_uart1", "apb1_uart2", "apb1_uart3",
154 "apb1_uart4", "apb1_uart5", "apb1_uart6",
155 "apb1_uart7";
156 };
157 };
158
159 soc@01c20000 {
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 reg = <0x01c20000 0x300000>;
164 ranges;
165
166 intc: interrupt-controller@01c20400 {
167 compatible = "allwinner,sun4i-ic";
168 reg = <0x01c20400 0x400>;
169 interrupt-controller;
170 #interrupt-cells = <1>;
171 };
172
173 pio: pinctrl@01c20800 {
22 compatible = "allwinner,sun4i-a10-pinctrl"; 174 compatible = "allwinner,sun4i-a10-pinctrl";
23 reg = <0x01c20800 0x400>; 175 reg = <0x01c20800 0x400>;
176 clocks = <&apb0_gates 5>;
177 gpio-controller;
24 #address-cells = <1>; 178 #address-cells = <1>;
25 #size-cells = <0>; 179 #size-cells = <0>;
180 #gpio-cells = <3>;
26 181
27 uart0_pins_a: uart0@0 { 182 uart0_pins_a: uart0@0 {
28 allwinner,pins = "PB22", "PB23"; 183 allwinner,pins = "PB22", "PB23";
@@ -45,5 +200,97 @@
45 allwinner,pull = <0>; 200 allwinner,pull = <0>;
46 }; 201 };
47 }; 202 };
203
204 timer@01c20c00 {
205 compatible = "allwinner,sun4i-timer";
206 reg = <0x01c20c00 0x90>;
207 interrupts = <22>;
208 clocks = <&osc24M>;
209 };
210
211 wdt: watchdog@01c20c90 {
212 compatible = "allwinner,sun4i-wdt";
213 reg = <0x01c20c90 0x10>;
214 };
215
216 uart0: serial@01c28000 {
217 compatible = "snps,dw-apb-uart";
218 reg = <0x01c28000 0x400>;
219 interrupts = <1>;
220 reg-shift = <2>;
221 reg-io-width = <4>;
222 clocks = <&apb1_gates 16>;
223 status = "disabled";
224 };
225
226 uart1: serial@01c28400 {
227 compatible = "snps,dw-apb-uart";
228 reg = <0x01c28400 0x400>;
229 interrupts = <2>;
230 reg-shift = <2>;
231 reg-io-width = <4>;
232 clocks = <&apb1_gates 17>;
233 status = "disabled";
234 };
235
236 uart2: serial@01c28800 {
237 compatible = "snps,dw-apb-uart";
238 reg = <0x01c28800 0x400>;
239 interrupts = <3>;
240 reg-shift = <2>;
241 reg-io-width = <4>;
242 clocks = <&apb1_gates 18>;
243 status = "disabled";
244 };
245
246 uart3: serial@01c28c00 {
247 compatible = "snps,dw-apb-uart";
248 reg = <0x01c28c00 0x400>;
249 interrupts = <4>;
250 reg-shift = <2>;
251 reg-io-width = <4>;
252 clocks = <&apb1_gates 19>;
253 status = "disabled";
254 };
255
256 uart4: serial@01c29000 {
257 compatible = "snps,dw-apb-uart";
258 reg = <0x01c29000 0x400>;
259 interrupts = <17>;
260 reg-shift = <2>;
261 reg-io-width = <4>;
262 clocks = <&apb1_gates 20>;
263 status = "disabled";
264 };
265
266 uart5: serial@01c29400 {
267 compatible = "snps,dw-apb-uart";
268 reg = <0x01c29400 0x400>;
269 interrupts = <18>;
270 reg-shift = <2>;
271 reg-io-width = <4>;
272 clocks = <&apb1_gates 21>;
273 status = "disabled";
274 };
275
276 uart6: serial@01c29800 {
277 compatible = "snps,dw-apb-uart";
278 reg = <0x01c29800 0x400>;
279 interrupts = <19>;
280 reg-shift = <2>;
281 reg-io-width = <4>;
282 clocks = <&apb1_gates 22>;
283 status = "disabled";
284 };
285
286 uart7: serial@01c29c00 {
287 compatible = "snps,dw-apb-uart";
288 reg = <0x01c29c00 0x400>;
289 interrupts = <20>;
290 reg-shift = <2>;
291 reg-io-width = <4>;
292 clocks = <&apb1_gates 23>;
293 status = "disabled";
294 };
48 }; 295 };
49}; 296};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 4a1e45d4aace..3ca55067f868 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -22,11 +22,31 @@
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
23 }; 23 };
24 24
25 soc { 25 soc@01c20000 {
26 uart1: uart@01c28400 { 26 pinctrl@01c20800 {
27 led_pins_olinuxino: led_pins@0 {
28 allwinner,pins = "PG9";
29 allwinner,function = "gpio_out";
30 allwinner,drive = <1>;
31 allwinner,pull = <0>;
32 };
33 };
34
35 uart1: serial@01c28400 {
27 pinctrl-names = "default"; 36 pinctrl-names = "default";
28 pinctrl-0 = <&uart1_pins_b>; 37 pinctrl-0 = <&uart1_pins_b>;
29 status = "okay"; 38 status = "okay";
30 }; 39 };
31 }; 40 };
41
42 leds {
43 compatible = "gpio-leds";
44 pinctrl-names = "default";
45 pinctrl-0 = <&led_pins_olinuxino>;
46
47 power {
48 gpios = <&pio 6 9 0>;
49 default-state = "on";
50 };
51 };
32}; 52};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index e1121890fb29..31fa38f8cc98 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -11,19 +11,174 @@
11 * http://www.gnu.org/copyleft/gpl.html 11 * http://www.gnu.org/copyleft/gpl.html
12 */ 12 */
13 13
14/include/ "sunxi.dtsi" 14/include/ "skeleton.dtsi"
15 15
16/ { 16/ {
17 interrupt-parent = <&intc>;
18
19 cpus {
20 cpu@0 {
21 compatible = "arm,cortex-a8";
22 };
23 };
24
17 memory { 25 memory {
18 reg = <0x40000000 0x20000000>; 26 reg = <0x40000000 0x20000000>;
19 }; 27 };
20 28
21 soc { 29 clocks {
22 pinctrl@01c20800 { 30 #address-cells = <1>;
31 #size-cells = <1>;
32 ranges;
33
34 /*
35 * This is a dummy clock, to be used as placeholder on
36 * other mux clocks when a specific parent clock is not
37 * yet implemented. It should be dropped when the driver
38 * is complete.
39 */
40 dummy: dummy {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <0>;
44 };
45
46 osc24M: osc24M@01c20050 {
47 #clock-cells = <0>;
48 compatible = "allwinner,sun4i-osc-clk";
49 reg = <0x01c20050 0x4>;
50 clock-frequency = <24000000>;
51 };
52
53 osc32k: osc32k {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
57 };
58
59 pll1: pll1@01c20000 {
60 #clock-cells = <0>;
61 compatible = "allwinner,sun4i-pll1-clk";
62 reg = <0x01c20000 0x4>;
63 clocks = <&osc24M>;
64 };
65
66 /* dummy is 200M */
67 cpu: cpu@01c20054 {
68 #clock-cells = <0>;
69 compatible = "allwinner,sun4i-cpu-clk";
70 reg = <0x01c20054 0x4>;
71 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
72 };
73
74 axi: axi@01c20054 {
75 #clock-cells = <0>;
76 compatible = "allwinner,sun4i-axi-clk";
77 reg = <0x01c20054 0x4>;
78 clocks = <&cpu>;
79 };
80
81 axi_gates: axi_gates@01c2005c {
82 #clock-cells = <1>;
83 compatible = "allwinner,sun4i-axi-gates-clk";
84 reg = <0x01c2005c 0x4>;
85 clocks = <&axi>;
86 clock-output-names = "axi_dram";
87 };
88
89 ahb: ahb@01c20054 {
90 #clock-cells = <0>;
91 compatible = "allwinner,sun4i-ahb-clk";
92 reg = <0x01c20054 0x4>;
93 clocks = <&axi>;
94 };
95
96 ahb_gates: ahb_gates@01c20060 {
97 #clock-cells = <1>;
98 compatible = "allwinner,sun4i-ahb-gates-clk";
99 reg = <0x01c20060 0x8>;
100 clocks = <&ahb>;
101 clock-output-names = "ahb_usb0", "ahb_ehci0",
102 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
103 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
104 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
105 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
106 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
107 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
108 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
109 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
110 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
111 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
112 };
113
114 apb0: apb0@01c20054 {
115 #clock-cells = <0>;
116 compatible = "allwinner,sun4i-apb0-clk";
117 reg = <0x01c20054 0x4>;
118 clocks = <&ahb>;
119 };
120
121 apb0_gates: apb0_gates@01c20068 {
122 #clock-cells = <1>;
123 compatible = "allwinner,sun4i-apb0-gates-clk";
124 reg = <0x01c20068 0x4>;
125 clocks = <&apb0>;
126 clock-output-names = "apb0_codec", "apb0_spdif",
127 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
128 "apb0_ir1", "apb0_keypad";
129 };
130
131 /* dummy is pll62 */
132 apb1_mux: apb1_mux@01c20058 {
133 #clock-cells = <0>;
134 compatible = "allwinner,sun4i-apb1-mux-clk";
135 reg = <0x01c20058 0x4>;
136 clocks = <&osc24M>, <&dummy>, <&osc32k>;
137 };
138
139 apb1: apb1@01c20058 {
140 #clock-cells = <0>;
141 compatible = "allwinner,sun4i-apb1-clk";
142 reg = <0x01c20058 0x4>;
143 clocks = <&apb1_mux>;
144 };
145
146 apb1_gates: apb1_gates@01c2006c {
147 #clock-cells = <1>;
148 compatible = "allwinner,sun4i-apb1-gates-clk";
149 reg = <0x01c2006c 0x4>;
150 clocks = <&apb1>;
151 clock-output-names = "apb1_i2c0", "apb1_i2c1",
152 "apb1_i2c2", "apb1_can", "apb1_scr",
153 "apb1_ps20", "apb1_ps21", "apb1_uart0",
154 "apb1_uart1", "apb1_uart2", "apb1_uart3",
155 "apb1_uart4", "apb1_uart5", "apb1_uart6",
156 "apb1_uart7";
157 };
158 };
159
160 soc@01c20000 {
161 compatible = "simple-bus";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 reg = <0x01c20000 0x300000>;
165 ranges;
166
167 intc: interrupt-controller@01c20400 {
168 compatible = "allwinner,sun4i-ic";
169 reg = <0x01c20400 0x400>;
170 interrupt-controller;
171 #interrupt-cells = <1>;
172 };
173
174 pio: pinctrl@01c20800 {
23 compatible = "allwinner,sun5i-a13-pinctrl"; 175 compatible = "allwinner,sun5i-a13-pinctrl";
24 reg = <0x01c20800 0x400>; 176 reg = <0x01c20800 0x400>;
177 clocks = <&apb0_gates 5>;
178 gpio-controller;
25 #address-cells = <1>; 179 #address-cells = <1>;
26 #size-cells = <0>; 180 #size-cells = <0>;
181 #gpio-cells = <3>;
27 182
28 uart1_pins_a: uart1@0 { 183 uart1_pins_a: uart1@0 {
29 allwinner,pins = "PE10", "PE11"; 184 allwinner,pins = "PE10", "PE11";
@@ -39,5 +194,37 @@
39 allwinner,pull = <0>; 194 allwinner,pull = <0>;
40 }; 195 };
41 }; 196 };
197
198 timer@01c20c00 {
199 compatible = "allwinner,sun4i-timer";
200 reg = <0x01c20c00 0x90>;
201 interrupts = <22>;
202 clocks = <&osc24M>;
203 };
204
205 wdt: watchdog@01c20c90 {
206 compatible = "allwinner,sun4i-wdt";
207 reg = <0x01c20c90 0x10>;
208 };
209
210 uart1: serial@01c28400 {
211 compatible = "snps,dw-apb-uart";
212 reg = <0x01c28400 0x400>;
213 interrupts = <2>;
214 reg-shift = <2>;
215 reg-io-width = <4>;
216 clocks = <&apb1_gates 17>;
217 status = "disabled";
218 };
219
220 uart3: serial@01c28c00 {
221 compatible = "snps,dw-apb-uart";
222 reg = <0x01c28c00 0x400>;
223 interrupts = <4>;
224 reg-shift = <2>;
225 reg-io-width = <4>;
226 clocks = <&apb1_gates 19>;
227 status = "disabled";
228 };
42 }; 229 };
43}; 230};
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
deleted file mode 100644
index 8b36abea9f2e..000000000000
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&intc>;
18
19 cpus {
20 cpu@0 {
21 compatible = "arm,cortex-a8";
22 };
23 };
24
25 clocks {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 osc: oscillator {
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 };
34 };
35
36 soc {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x01c20000 0x300000>;
41 ranges;
42
43 timer@01c20c00 {
44 compatible = "allwinner,sunxi-timer";
45 reg = <0x01c20c00 0x90>;
46 interrupts = <22>;
47 clocks = <&osc>;
48 };
49
50 wdt: watchdog@01c20c90 {
51 compatible = "allwinner,sunxi-wdt";
52 reg = <0x01c20c90 0x10>;
53 };
54
55 intc: interrupt-controller@01c20400 {
56 compatible = "allwinner,sunxi-ic";
57 reg = <0x01c20400 0x400>;
58 interrupt-controller;
59 #interrupt-cells = <1>;
60 };
61
62 uart0: uart@01c28000 {
63 compatible = "snps,dw-apb-uart";
64 reg = <0x01c28000 0x400>;
65 interrupts = <1>;
66 reg-shift = <2>;
67 reg-io-width = <4>;
68 clock-frequency = <24000000>;
69 status = "disabled";
70 };
71
72 uart1: uart@01c28400 {
73 compatible = "snps,dw-apb-uart";
74 reg = <0x01c28400 0x400>;
75 interrupts = <2>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 clock-frequency = <24000000>;
79 status = "disabled";
80 };
81 };
82};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index bcf668d31b28..398b8bca791e 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -60,6 +60,19 @@
60 clock-frequency = <24000000>; 60 clock-frequency = <24000000>;
61 }; 61 };
62 62
63 ref25: ref25M {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <25000000>;
67 };
68
69 pllb: pllb {
70 #clock-cells = <0>;
71 compatible = "via,vt8500-pll-clock";
72 clocks = <&ref25>;
73 reg = <0x204>;
74 };
75
63 clkuart0: uart0 { 76 clkuart0: uart0 {
64 #clock-cells = <0>; 77 #clock-cells = <0>;
65 compatible = "via,vt8500-device-clock"; 78 compatible = "via,vt8500-device-clock";
@@ -107,6 +120,16 @@
107 enable-reg = <0x250>; 120 enable-reg = <0x250>;
108 enable-bit = <23>; 121 enable-bit = <23>;
109 }; 122 };
123
124 clksdhc: sdhc {
125 #clock-cells = <0>;
126 compatible = "via,vt8500-device-clock";
127 clocks = <&pllb>;
128 divisor-reg = <0x328>;
129 divisor-mask = <0x3f>;
130 enable-reg = <0x254>;
131 enable-bit = <18>;
132 };
110 }; 133 };
111 }; 134 };
112 135
@@ -185,5 +208,13 @@
185 reg = <0xd8100000 0x10000>; 208 reg = <0xd8100000 0x10000>;
186 interrupts = <48>; 209 interrupts = <48>;
187 }; 210 };
211
212 sdhc@d800a000 {
213 compatible = "wm,wm8505-sdhc";
214 reg = <0xd800a000 0x1000>;
215 interrupts = <20 21>;
216 clocks = <&clksdhc>;
217 bus-width = <4>;
218 };
188 }; 219 };
189}; 220};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 5914b5654591..9e1c339c4491 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -15,6 +15,13 @@
15/ { 15/ {
16 compatible = "xlnx,zynq-7000"; 16 compatible = "xlnx,zynq-7000";
17 17
18 pmu {
19 compatible = "arm,cortex-a9-pmu";
20 interrupts = <0 5 4>, <0 6 4>;
21 interrupt-parent = <&intc>;
22 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
23 };
24
18 amba { 25 amba {
19 compatible = "simple-bus"; 26 compatible = "simple-bus";
20 #address-cells = <1>; 27 #address-cells = <1>;
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 3fe8dae8d32d..4364eff5b01e 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -75,6 +75,8 @@ CONFIG_I2C_MV64XXX=y
75CONFIG_SPI=y 75CONFIG_SPI=y
76CONFIG_SPI_ORION=y 76CONFIG_SPI_ORION=y
77# CONFIG_HWMON is not set 77# CONFIG_HWMON is not set
78CONFIG_THERMAL=y
79CONFIG_DOVE_THERMAL=y
78CONFIG_USB=y 80CONFIG_USB=y
79CONFIG_USB_EHCI_HCD=y 81CONFIG_USB_EHCI_HCD=y
80CONFIG_USB_EHCI_ROOT_HUB_TT=y 82CONFIG_USB_EHCI_ROOT_HUB_TT=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 93f3794ba5cb..3d8667f648b8 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -118,6 +118,8 @@ CONFIG_SPI=y
118CONFIG_SPI_ORION=y 118CONFIG_SPI_ORION=y
119CONFIG_GPIO_SYSFS=y 119CONFIG_GPIO_SYSFS=y
120# CONFIG_HWMON is not set 120# CONFIG_HWMON is not set
121CONFIG_THERMAL=y
122CONFIG_KIRKWOOD_THERMAL=y
121CONFIG_WATCHDOG=y 123CONFIG_WATCHDOG=y
122CONFIG_ORION_WATCHDOG=y 124CONFIG_ORION_WATCHDOG=y
123CONFIG_HID_DRAGONRISE=y 125CONFIG_HID_DRAGONRISE=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2ec8119cff73..f3e8ae001ff1 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -46,9 +46,16 @@ CONFIG_I2C_MV64XXX=y
46CONFIG_MTD=y 46CONFIG_MTD=y
47CONFIG_MTD_CHAR=y 47CONFIG_MTD_CHAR=y
48CONFIG_MTD_M25P80=y 48CONFIG_MTD_M25P80=y
49CONFIG_MTD_CFI=y
50CONFIG_MTD_CFI_INTELEXT=y
51CONFIG_MTD_CFI_AMDSTD=y
52CONFIG_MTD_CFI_STAA=y
53CONFIG_MTD_PHYSMAP_OF=y
49CONFIG_SERIAL_8250_DW=y 54CONFIG_SERIAL_8250_DW=y
50CONFIG_GPIOLIB=y 55CONFIG_GPIOLIB=y
51CONFIG_GPIO_SYSFS=y 56CONFIG_GPIO_SYSFS=y
57CONFIG_THERMAL=y
58CONFIG_ARMADA_THERMAL=y
52CONFIG_USB_SUPPORT=y 59CONFIG_USB_SUPPORT=y
53CONFIG_USB=y 60CONFIG_USB=y
54CONFIG_USB_EHCI_HCD=y 61CONFIG_USB_EHCI_HCD=y
@@ -65,6 +72,8 @@ CONFIG_RTC_DRV_S35390A=y
65CONFIG_RTC_DRV_MV=y 72CONFIG_RTC_DRV_MV=y
66CONFIG_DMADEVICES=y 73CONFIG_DMADEVICES=y
67CONFIG_MV_XOR=y 74CONFIG_MV_XOR=y
75CONFIG_MEMORY=y
76CONFIG_MVEBU_DEVBUS=y
68# CONFIG_IOMMU_SUPPORT is not set 77# CONFIG_IOMMU_SUPPORT is not set
69CONFIG_EXT2_FS=y 78CONFIG_EXT2_FS=y
70CONFIG_EXT3_FS=y 79CONFIG_EXT3_FS=y
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 9706c000f294..36b05fc28816 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -212,6 +212,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
212 CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk), 212 CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
213 CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk), 213 CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
214 CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk), 214 CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
215 CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
215 CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk), 216 CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
216 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk), 217 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
217 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk), 218 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 6575e4ebe26e..91571a16f986 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -149,6 +149,7 @@ config SOC_IMX5
149 149
150config SOC_IMX51 150config SOC_IMX51
151 bool 151 bool
152 select HAVE_IMX_SRC
152 select PINCTRL 153 select PINCTRL
153 select PINCTRL_IMX51 154 select PINCTRL_IMX51
154 select SOC_IMX5 155 select SOC_IMX5
@@ -774,6 +775,7 @@ comment "Device tree only"
774config SOC_IMX53 775config SOC_IMX53
775 bool "i.MX53 support" 776 bool "i.MX53 support"
776 select HAVE_CAN_FLEXCAN if CAN 777 select HAVE_CAN_FLEXCAN if CAN
778 select HAVE_IMX_SRC
777 select IMX_HAVE_PLATFORM_IMX2_WDT 779 select IMX_HAVE_PLATFORM_IMX2_WDT
778 select PINCTRL 780 select PINCTRL
779 select PINCTRL_IMX53 781 select PINCTRL_IMX53
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 8e3b65719106..c3cfa4116dc0 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -86,10 +86,12 @@ enum mx27_clks {
86}; 86};
87 87
88static struct clk *clk[clk_max]; 88static struct clk *clk[clk_max];
89static struct clk_onecell_data clk_data;
89 90
90int __init mx27_clocks_init(unsigned long fref) 91int __init mx27_clocks_init(unsigned long fref)
91{ 92{
92 int i; 93 int i;
94 struct device_node *np;
93 95
94 clk[dummy] = imx_clk_fixed("dummy", 0); 96 clk[dummy] = imx_clk_fixed("dummy", 0);
95 clk[ckih] = imx_clk_fixed("ckih", fref); 97 clk[ckih] = imx_clk_fixed("ckih", fref);
@@ -198,6 +200,13 @@ int __init mx27_clocks_init(unsigned long fref)
198 pr_err("i.MX27 clk %d: register failed with %ld\n", 200 pr_err("i.MX27 clk %d: register failed with %ld\n",
199 i, PTR_ERR(clk[i])); 201 i, PTR_ERR(clk[i]));
200 202
203 np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
204 if (np) {
205 clk_data.clks = clk;
206 clk_data.clk_num = ARRAY_SIZE(clk);
207 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
208 }
209
201 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); 210 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
202 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0"); 211 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
203 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); 212 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
@@ -276,7 +285,7 @@ int __init mx27_clocks_init(unsigned long fref)
276 clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL); 285 clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
277 clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc"); 286 clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
278 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL); 287 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
279 clk_register_clkdev(clk[cpu_div], "cpu", NULL); 288 clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0");
280 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL); 289 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
281 290
282 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); 291 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 0f39f8c93b94..2bc623b414c1 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -281,7 +281,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
281 clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL); 281 clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
282 clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL); 282 clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
283 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); 283 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
284 clk_register_clkdev(clk[cpu_podf], "cpu", NULL); 284 clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
285 clk_register_clkdev(clk[iim_gate], "iim", NULL); 285 clk_register_clkdev(clk[iim_gate], "iim", NULL);
286 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0"); 286 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
287 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1"); 287 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
@@ -362,9 +362,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
362 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL); 362 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
363 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0"); 363 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
364 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); 364 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
365 clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
366 clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
367 clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
368 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0"); 365 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
369 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0"); 366 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
370 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0"); 367 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -471,10 +468,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
471 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); 468 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
472 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); 469 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
473 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0"); 470 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
474 clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
475 clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
476 clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
477 clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
478 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0"); 471 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
479 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0"); 472 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
480 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0"); 473 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index c915a490a11c..4aaead0a77ff 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -18,25 +18,13 @@
18#include "common.h" 18#include "common.h"
19#include "mx27.h" 19#include "mx27.h"
20 20
21static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
22 OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
23 OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
24 OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
25 OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
26 OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
27 OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
28 OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
29 OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
30 OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
31 OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
32 OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "imx27-nand.0", NULL),
33 { /* sentinel */ }
34};
35
36static void __init imx27_dt_init(void) 21static void __init imx27_dt_init(void)
37{ 22{
38 of_platform_populate(NULL, of_default_bus_match_table, 23 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
39 imx27_auxdata_lookup, NULL); 24
25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
26
27 platform_device_register_full(&devinfo);
40} 28}
41 29
42static const char * const imx27_dt_board_compat[] __initconst = { 30static const char * const imx27_dt_board_compat[] __initconst = {
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index e2926a8863f8..ab24cc322111 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -21,7 +21,10 @@
21 21
22static void __init imx51_dt_init(void) 22static void __init imx51_dt_init(void)
23{ 23{
24 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
25
24 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 26 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
27 platform_device_register_full(&devinfo);
25} 28}
26 29
27static const char *imx51_dt_board_compat[] __initdata = { 30static const char *imx51_dt_board_compat[] __initdata = {
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index cf34994cfe28..b7c4e70e5081 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -84,6 +84,7 @@ void __init imx51_init_early(void)
84 mxc_set_cpu_type(MXC_CPU_MX51); 84 mxc_set_cpu_type(MXC_CPU_MX51);
85 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 85 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
86 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); 86 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
87 imx_src_init();
87} 88}
88 89
89void __init imx53_init_early(void) 90void __init imx53_init_early(void)
@@ -91,6 +92,7 @@ void __init imx53_init_early(void)
91 mxc_set_cpu_type(MXC_CPU_MX53); 92 mxc_set_cpu_type(MXC_CPU_MX53);
92 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); 93 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
93 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); 94 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
95 imx_src_init();
94} 96}
95 97
96void __init mx51_init_irq(void) 98void __init mx51_init_irq(void)
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 324731c2a441..97d086889481 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -74,7 +74,9 @@ void __init imx_src_init(void)
74 struct device_node *np; 74 struct device_node *np;
75 u32 val; 75 u32 val;
76 76
77 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); 77 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
78 if (!np)
79 return;
78 src_base = of_iomap(np, 0); 80 src_base = of_iomap(np, 0);
79 WARN_ON(!src_base); 81 WARN_ON(!src_base);
80 82
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
index 0a0df4554d8b..a857163954a5 100644
--- a/arch/arm/mach-kirkwood/board-guruplug.c
+++ b/arch/arm/mach-kirkwood/board-guruplug.c
@@ -13,7 +13,6 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/mv643xx_eth.h> 14#include <linux/mv643xx_eth.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/platform_data/mmc-mvsdio.h>
17#include "common.h" 16#include "common.h"
18 17
19static struct mv643xx_eth_platform_data guruplug_ge00_data = { 18static struct mv643xx_eth_platform_data guruplug_ge00_data = {
@@ -24,10 +23,6 @@ static struct mv643xx_eth_platform_data guruplug_ge01_data = {
24 .phy_addr = MV643XX_ETH_PHY_ADDR(1), 23 .phy_addr = MV643XX_ETH_PHY_ADDR(1),
25}; 24};
26 25
27static struct mvsdio_platform_data guruplug_mvsdio_data = {
28 /* unfortunately the CD signal has not been connected */
29};
30
31void __init guruplug_dt_init(void) 26void __init guruplug_dt_init(void)
32{ 27{
33 /* 28 /*
@@ -35,5 +30,4 @@ void __init guruplug_dt_init(void)
35 */ 30 */
36 kirkwood_ge00_init(&guruplug_ge00_data); 31 kirkwood_ge00_init(&guruplug_ge00_data);
37 kirkwood_ge01_init(&guruplug_ge01_data); 32 kirkwood_ge01_init(&guruplug_ge01_data);
38 kirkwood_sdio_init(&guruplug_mvsdio_data);
39} 33}
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f910962baaa7..51336b2aedc9 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -93,12 +93,20 @@ config PINCTRL_IMX53
93 Say Y here to enable the imx53 pinctrl driver 93 Say Y here to enable the imx53 pinctrl driver
94 94
95config PINCTRL_IMX6Q 95config PINCTRL_IMX6Q
96 bool "IMX6Q pinctrl driver" 96 bool "IMX6Q/DL pinctrl driver"
97 depends on OF 97 depends on OF
98 depends on SOC_IMX6Q 98 depends on SOC_IMX6Q
99 select PINCTRL_IMX 99 select PINCTRL_IMX
100 help 100 help
101 Say Y here to enable the imx6q pinctrl driver 101 Say Y here to enable the imx6q/dl pinctrl driver
102
103config PINCTRL_IMX6SL
104 bool "IMX6SL pinctrl driver"
105 depends on OF
106 depends on SOC_IMX6SL
107 select PINCTRL_IMX
108 help
109 Say Y here to enable the imx6sl pinctrl driver
102 110
103config PINCTRL_LANTIQ 111config PINCTRL_LANTIQ
104 bool 112 bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 988279ae23cd..b9aaa61facd1 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
21obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o 21obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
22obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o 22obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
23obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o 23obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
24obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
24obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 25obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
25obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 26obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
26obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 27obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 0ef190449eab..4fcfff9243be 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -54,32 +54,6 @@ struct imx_pinctrl {
54 const struct imx_pinctrl_soc_info *info; 54 const struct imx_pinctrl_soc_info *info;
55}; 55};
56 56
57static const struct imx_pin_reg *imx_find_pin_reg(
58 const struct imx_pinctrl_soc_info *info,
59 unsigned pin, bool is_mux, unsigned mux)
60{
61 const struct imx_pin_reg *pin_reg = NULL;
62 int i;
63
64 for (i = 0; i < info->npin_regs; i++) {
65 pin_reg = &info->pin_regs[i];
66 if (pin_reg->pid != pin)
67 continue;
68 if (!is_mux)
69 break;
70 else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
71 break;
72 }
73
74 if (i == info->npin_regs) {
75 dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
76 info->pins[pin].name);
77 return NULL;
78 }
79
80 return pin_reg;
81}
82
83static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( 57static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
84 const struct imx_pinctrl_soc_info *info, 58 const struct imx_pinctrl_soc_info *info,
85 const char *name) 59 const char *name)
@@ -223,7 +197,8 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
223 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 197 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
224 const struct imx_pinctrl_soc_info *info = ipctl->info; 198 const struct imx_pinctrl_soc_info *info = ipctl->info;
225 const struct imx_pin_reg *pin_reg; 199 const struct imx_pin_reg *pin_reg;
226 const unsigned *pins, *mux; 200 const unsigned *pins, *mux, *input_val;
201 u16 *input_reg;
227 unsigned int npins, pin_id; 202 unsigned int npins, pin_id;
228 int i; 203 int i;
229 204
@@ -234,18 +209,17 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
234 pins = info->groups[group].pins; 209 pins = info->groups[group].pins;
235 npins = info->groups[group].npins; 210 npins = info->groups[group].npins;
236 mux = info->groups[group].mux_mode; 211 mux = info->groups[group].mux_mode;
212 input_val = info->groups[group].input_val;
213 input_reg = info->groups[group].input_reg;
237 214
238 WARN_ON(!pins || !npins || !mux); 215 WARN_ON(!pins || !npins || !mux || !input_val || !input_reg);
239 216
240 dev_dbg(ipctl->dev, "enable function %s group %s\n", 217 dev_dbg(ipctl->dev, "enable function %s group %s\n",
241 info->functions[selector].name, info->groups[group].name); 218 info->functions[selector].name, info->groups[group].name);
242 219
243 for (i = 0; i < npins; i++) { 220 for (i = 0; i < npins; i++) {
244 pin_id = pins[i]; 221 pin_id = pins[i];
245 222 pin_reg = &info->pin_regs[pin_id];
246 pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
247 if (!pin_reg)
248 return -EINVAL;
249 223
250 if (!pin_reg->mux_reg) { 224 if (!pin_reg->mux_reg) {
251 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", 225 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
@@ -258,11 +232,11 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
258 pin_reg->mux_reg, mux[i]); 232 pin_reg->mux_reg, mux[i]);
259 233
260 /* some pins also need select input setting, set it if found */ 234 /* some pins also need select input setting, set it if found */
261 if (pin_reg->input_reg) { 235 if (input_reg[i]) {
262 writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg); 236 writel(input_val[i], ipctl->base + input_reg[i]);
263 dev_dbg(ipctl->dev, 237 dev_dbg(ipctl->dev,
264 "==>select_input: offset 0x%x val 0x%x\n", 238 "==>select_input: offset 0x%x val 0x%x\n",
265 pin_reg->input_reg, pin_reg->input_val); 239 input_reg[i], input_val[i]);
266 } 240 }
267 } 241 }
268 242
@@ -311,11 +285,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
311{ 285{
312 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 286 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
313 const struct imx_pinctrl_soc_info *info = ipctl->info; 287 const struct imx_pinctrl_soc_info *info = ipctl->info;
314 const struct imx_pin_reg *pin_reg; 288 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
315
316 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
317 if (!pin_reg)
318 return -EINVAL;
319 289
320 if (!pin_reg->conf_reg) { 290 if (!pin_reg->conf_reg) {
321 dev_err(info->dev, "Pin(%s) does not support config function\n", 291 dev_err(info->dev, "Pin(%s) does not support config function\n",
@@ -333,11 +303,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
333{ 303{
334 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 304 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
335 const struct imx_pinctrl_soc_info *info = ipctl->info; 305 const struct imx_pinctrl_soc_info *info = ipctl->info;
336 const struct imx_pin_reg *pin_reg; 306 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
337
338 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
339 if (!pin_reg)
340 return -EINVAL;
341 307
342 if (!pin_reg->conf_reg) { 308 if (!pin_reg->conf_reg) {
343 dev_err(info->dev, "Pin(%s) does not support config function\n", 309 dev_err(info->dev, "Pin(%s) does not support config function\n",
@@ -360,10 +326,9 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
360{ 326{
361 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 327 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
362 const struct imx_pinctrl_soc_info *info = ipctl->info; 328 const struct imx_pinctrl_soc_info *info = ipctl->info;
363 const struct imx_pin_reg *pin_reg; 329 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
364 unsigned long config; 330 unsigned long config;
365 331
366 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
367 if (!pin_reg || !pin_reg->conf_reg) { 332 if (!pin_reg || !pin_reg->conf_reg) {
368 seq_printf(s, "N/A"); 333 seq_printf(s, "N/A");
369 return; 334 return;
@@ -411,29 +376,20 @@ static struct pinctrl_desc imx_pinctrl_desc = {
411 .owner = THIS_MODULE, 376 .owner = THIS_MODULE,
412}; 377};
413 378
414/* decode pin id and mux from pin function id got from device tree*/ 379/*
415static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info, 380 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
416 unsigned int pin_func_id, unsigned int *pin_id, 381 * 1 u32 CONFIG, so 24 types in total for each pin.
417 unsigned int *mux) 382 */
418{ 383#define FSL_PIN_SIZE 24
419 if (pin_func_id > info->npin_regs)
420 return -EINVAL;
421
422 *pin_id = info->pin_regs[pin_func_id].pid;
423 *mux = info->pin_regs[pin_func_id].mux_mode;
424
425 return 0;
426}
427 384
428static int imx_pinctrl_parse_groups(struct device_node *np, 385static int imx_pinctrl_parse_groups(struct device_node *np,
429 struct imx_pin_group *grp, 386 struct imx_pin_group *grp,
430 struct imx_pinctrl_soc_info *info, 387 struct imx_pinctrl_soc_info *info,
431 u32 index) 388 u32 index)
432{ 389{
433 unsigned int pin_func_id; 390 int size;
434 int ret, size;
435 const __be32 *list; 391 const __be32 *list;
436 int i, j; 392 int i;
437 u32 config; 393 u32 config;
438 394
439 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 395 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
@@ -447,32 +403,40 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
447 */ 403 */
448 list = of_get_property(np, "fsl,pins", &size); 404 list = of_get_property(np, "fsl,pins", &size);
449 /* we do not check return since it's safe node passed down */ 405 /* we do not check return since it's safe node passed down */
450 size /= sizeof(*list); 406 if (!size || size % FSL_PIN_SIZE) {
451 if (!size || size % 2) { 407 dev_err(info->dev, "Invalid fsl,pins property\n");
452 dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
453 return -EINVAL; 408 return -EINVAL;
454 } 409 }
455 410
456 grp->npins = size / 2; 411 grp->npins = size / FSL_PIN_SIZE;
457 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 412 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
458 GFP_KERNEL); 413 GFP_KERNEL);
459 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 414 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
460 GFP_KERNEL); 415 GFP_KERNEL);
416 grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16),
417 GFP_KERNEL);
418 grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
419 GFP_KERNEL);
461 grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long), 420 grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
462 GFP_KERNEL); 421 GFP_KERNEL);
463 for (i = 0, j = 0; i < size; i += 2, j++) { 422 for (i = 0; i < grp->npins; i++) {
464 pin_func_id = be32_to_cpu(*list++); 423 u32 mux_reg = be32_to_cpu(*list++);
465 ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id, 424 u32 conf_reg = be32_to_cpu(*list++);
466 &grp->pins[j], &grp->mux_mode[j]); 425 unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
467 if (ret) { 426 struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
468 dev_err(info->dev, "get invalid pin function id\n"); 427
469 return -EINVAL; 428 grp->pins[i] = pin_id;
470 } 429 pin_reg->mux_reg = mux_reg;
430 pin_reg->conf_reg = conf_reg;
431 grp->input_reg[i] = be32_to_cpu(*list++);
432 grp->mux_mode[i] = be32_to_cpu(*list++);
433 grp->input_val[i] = be32_to_cpu(*list++);
434
471 /* SION bit is in mux register */ 435 /* SION bit is in mux register */
472 config = be32_to_cpu(*list++); 436 config = be32_to_cpu(*list++);
473 if (config & IMX_PAD_SION) 437 if (config & IMX_PAD_SION)
474 grp->mux_mode[j] |= IOMUXC_CONFIG_SION; 438 grp->mux_mode[i] |= IOMUXC_CONFIG_SION;
475 grp->configs[j] = config & ~IMX_PAD_SION; 439 grp->configs[i] = config & ~IMX_PAD_SION;
476 } 440 }
477 441
478#ifdef DEBUG 442#ifdef DEBUG
@@ -568,8 +532,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
568 struct resource *res; 532 struct resource *res;
569 int ret; 533 int ret;
570 534
571 if (!info || !info->pins || !info->npins 535 if (!info || !info->pins || !info->npins) {
572 || !info->pin_regs || !info->npin_regs) {
573 dev_err(&pdev->dev, "wrong pinctrl info\n"); 536 dev_err(&pdev->dev, "wrong pinctrl info\n");
574 return -EINVAL; 537 return -EINVAL;
575 } 538 }
@@ -580,6 +543,11 @@ int imx_pinctrl_probe(struct platform_device *pdev,
580 if (!ipctl) 543 if (!ipctl)
581 return -ENOMEM; 544 return -ENOMEM;
582 545
546 info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) *
547 info->npins, GFP_KERNEL);
548 if (!info->pin_regs)
549 return -ENOMEM;
550
583 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 551 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
584 if (!res) 552 if (!res)
585 return -ENOENT; 553 return -ENOENT;
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
index 9b65e7828f1d..607ef5497552 100644
--- a/drivers/pinctrl/pinctrl-imx.h
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -26,6 +26,10 @@ struct platform_device;
26 * elements in .pins so we can iterate over that array 26 * elements in .pins so we can iterate over that array
27 * @mux_mode: the mux mode for each pin in this group. The size of this 27 * @mux_mode: the mux mode for each pin in this group. The size of this
28 * array is the same as pins. 28 * array is the same as pins.
29 * @input_reg: select input register offset for this mux if any
30 * 0 if no select input setting needed.
31 * @input_val: the select input value for each pin in this group. The size of
32 * this array is the same as pins.
29 * @configs: the config for each pin in this group. The size of this 33 * @configs: the config for each pin in this group. The size of this
30 * array is the same as pins. 34 * array is the same as pins.
31 */ 35 */
@@ -34,6 +38,8 @@ struct imx_pin_group {
34 unsigned int *pins; 38 unsigned int *pins;
35 unsigned npins; 39 unsigned npins;
36 unsigned int *mux_mode; 40 unsigned int *mux_mode;
41 u16 *input_reg;
42 unsigned int *input_val;
37 unsigned long *configs; 43 unsigned long *configs;
38}; 44};
39 45
@@ -51,30 +57,19 @@ struct imx_pmx_func {
51 57
52/** 58/**
53 * struct imx_pin_reg - describe a pin reg map 59 * struct imx_pin_reg - describe a pin reg map
54 * The last 3 members are used for select input setting
55 * @pid: pin id
56 * @mux_reg: mux register offset 60 * @mux_reg: mux register offset
57 * @conf_reg: config register offset 61 * @conf_reg: config register offset
58 * @mux_mode: mux mode
59 * @input_reg: select input register offset for this mux if any
60 * 0 if no select input setting needed.
61 * @input_val: the value set to select input register
62 */ 62 */
63struct imx_pin_reg { 63struct imx_pin_reg {
64 u16 pid;
65 u16 mux_reg; 64 u16 mux_reg;
66 u16 conf_reg; 65 u16 conf_reg;
67 u8 mux_mode;
68 u16 input_reg;
69 u8 input_val;
70}; 66};
71 67
72struct imx_pinctrl_soc_info { 68struct imx_pinctrl_soc_info {
73 struct device *dev; 69 struct device *dev;
74 const struct pinctrl_pin_desc *pins; 70 const struct pinctrl_pin_desc *pins;
75 unsigned int npins; 71 unsigned int npins;
76 const struct imx_pin_reg *pin_regs; 72 struct imx_pin_reg *pin_regs;
77 unsigned int npin_regs;
78 struct imx_pin_group *groups; 73 struct imx_pin_group *groups;
79 unsigned int ngroups; 74 unsigned int ngroups;
80 struct imx_pmx_func *functions; 75 struct imx_pmx_func *functions;
@@ -84,16 +79,6 @@ struct imx_pinctrl_soc_info {
84#define NO_MUX 0x0 79#define NO_MUX 0x0
85#define NO_PAD 0x0 80#define NO_PAD 0x0
86 81
87#define IMX_PIN_REG(id, conf, mux, mode, input, val) \
88 { \
89 .pid = id, \
90 .conf_reg = conf, \
91 .mux_reg = mux, \
92 .mux_mode = mode, \
93 .input_reg = input, \
94 .input_val = val, \
95 }
96
97#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) 82#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
98 83
99#define PAD_CTL_MASK(len) ((1 << len) - 1) 84#define PAD_CTL_MASK(len) ((1 << len) - 1)
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c
index 6e214110e3d5..c4549829fc47 100644
--- a/drivers/pinctrl/pinctrl-imx35.c
+++ b/drivers/pinctrl/pinctrl-imx35.c
@@ -24,1249 +24,496 @@
24#include "pinctrl-imx.h" 24#include "pinctrl-imx.h"
25 25
26enum imx35_pads { 26enum imx35_pads {
27 MX35_PAD_CAPTURE = 0, 27 MX35_PAD_RESERVE0 = 0,
28 MX35_PAD_COMPARE = 1, 28 MX35_PAD_CAPTURE = 1,
29 MX35_PAD_WDOG_RST = 2, 29 MX35_PAD_COMPARE = 2,
30 MX35_PAD_GPIO1_0 = 3, 30 MX35_PAD_WDOG_RST = 3,
31 MX35_PAD_GPIO1_1 = 4, 31 MX35_PAD_GPIO1_0 = 4,
32 MX35_PAD_GPIO2_0 = 5, 32 MX35_PAD_GPIO1_1 = 5,
33 MX35_PAD_GPIO3_0 = 6, 33 MX35_PAD_GPIO2_0 = 6,
34 MX35_PAD_RESET_IN_B = 7, 34 MX35_PAD_GPIO3_0 = 7,
35 MX35_PAD_POR_B = 8, 35 MX35_PAD_CLKO = 8,
36 MX35_PAD_CLKO = 9, 36 MX35_PAD_VSTBY = 9,
37 MX35_PAD_BOOT_MODE0 = 10, 37 MX35_PAD_A0 = 10,
38 MX35_PAD_BOOT_MODE1 = 11, 38 MX35_PAD_A1 = 11,
39 MX35_PAD_CLK_MODE0 = 12, 39 MX35_PAD_A2 = 12,
40 MX35_PAD_CLK_MODE1 = 13, 40 MX35_PAD_A3 = 13,
41 MX35_PAD_POWER_FAIL = 14, 41 MX35_PAD_A4 = 14,
42 MX35_PAD_VSTBY = 15, 42 MX35_PAD_A5 = 15,
43 MX35_PAD_A0 = 16, 43 MX35_PAD_A6 = 16,
44 MX35_PAD_A1 = 17, 44 MX35_PAD_A7 = 17,
45 MX35_PAD_A2 = 18, 45 MX35_PAD_A8 = 18,
46 MX35_PAD_A3 = 19, 46 MX35_PAD_A9 = 19,
47 MX35_PAD_A4 = 20, 47 MX35_PAD_A10 = 20,
48 MX35_PAD_A5 = 21, 48 MX35_PAD_MA10 = 21,
49 MX35_PAD_A6 = 22, 49 MX35_PAD_A11 = 22,
50 MX35_PAD_A7 = 23, 50 MX35_PAD_A12 = 23,
51 MX35_PAD_A8 = 24, 51 MX35_PAD_A13 = 24,
52 MX35_PAD_A9 = 25, 52 MX35_PAD_A14 = 25,
53 MX35_PAD_A10 = 26, 53 MX35_PAD_A15 = 26,
54 MX35_PAD_MA10 = 27, 54 MX35_PAD_A16 = 27,
55 MX35_PAD_A11 = 28, 55 MX35_PAD_A17 = 28,
56 MX35_PAD_A12 = 29, 56 MX35_PAD_A18 = 29,
57 MX35_PAD_A13 = 30, 57 MX35_PAD_A19 = 30,
58 MX35_PAD_A14 = 31, 58 MX35_PAD_A20 = 31,
59 MX35_PAD_A15 = 32, 59 MX35_PAD_A21 = 32,
60 MX35_PAD_A16 = 33, 60 MX35_PAD_A22 = 33,
61 MX35_PAD_A17 = 34, 61 MX35_PAD_A23 = 34,
62 MX35_PAD_A18 = 35, 62 MX35_PAD_A24 = 35,
63 MX35_PAD_A19 = 36, 63 MX35_PAD_A25 = 36,
64 MX35_PAD_A20 = 37, 64 MX35_PAD_EB0 = 37,
65 MX35_PAD_A21 = 38, 65 MX35_PAD_EB1 = 38,
66 MX35_PAD_A22 = 39, 66 MX35_PAD_OE = 39,
67 MX35_PAD_A23 = 40, 67 MX35_PAD_CS0 = 40,
68 MX35_PAD_A24 = 41, 68 MX35_PAD_CS1 = 41,
69 MX35_PAD_A25 = 42, 69 MX35_PAD_CS2 = 42,
70 MX35_PAD_SDBA1 = 43, 70 MX35_PAD_CS3 = 43,
71 MX35_PAD_SDBA0 = 44, 71 MX35_PAD_CS4 = 44,
72 MX35_PAD_SD0 = 45, 72 MX35_PAD_CS5 = 45,
73 MX35_PAD_SD1 = 46, 73 MX35_PAD_NF_CE0 = 46,
74 MX35_PAD_SD2 = 47, 74 MX35_PAD_LBA = 47,
75 MX35_PAD_SD3 = 48, 75 MX35_PAD_BCLK = 48,
76 MX35_PAD_SD4 = 49, 76 MX35_PAD_RW = 49,
77 MX35_PAD_SD5 = 50, 77 MX35_PAD_NFWE_B = 50,
78 MX35_PAD_SD6 = 51, 78 MX35_PAD_NFRE_B = 51,
79 MX35_PAD_SD7 = 52, 79 MX35_PAD_NFALE = 52,
80 MX35_PAD_SD8 = 53, 80 MX35_PAD_NFCLE = 53,
81 MX35_PAD_SD9 = 54, 81 MX35_PAD_NFWP_B = 54,
82 MX35_PAD_SD10 = 55, 82 MX35_PAD_NFRB = 55,
83 MX35_PAD_SD11 = 56, 83 MX35_PAD_CSI_D8 = 56,
84 MX35_PAD_SD12 = 57, 84 MX35_PAD_CSI_D9 = 57,
85 MX35_PAD_SD13 = 58, 85 MX35_PAD_CSI_D10 = 58,
86 MX35_PAD_SD14 = 59, 86 MX35_PAD_CSI_D11 = 59,
87 MX35_PAD_SD15 = 60, 87 MX35_PAD_CSI_D12 = 60,
88 MX35_PAD_SD16 = 61, 88 MX35_PAD_CSI_D13 = 61,
89 MX35_PAD_SD17 = 62, 89 MX35_PAD_CSI_D14 = 62,
90 MX35_PAD_SD18 = 63, 90 MX35_PAD_CSI_D15 = 63,
91 MX35_PAD_SD19 = 64, 91 MX35_PAD_CSI_MCLK = 64,
92 MX35_PAD_SD20 = 65, 92 MX35_PAD_CSI_VSYNC = 65,
93 MX35_PAD_SD21 = 66, 93 MX35_PAD_CSI_HSYNC = 66,
94 MX35_PAD_SD22 = 67, 94 MX35_PAD_CSI_PIXCLK = 67,
95 MX35_PAD_SD23 = 68, 95 MX35_PAD_I2C1_CLK = 68,
96 MX35_PAD_SD24 = 69, 96 MX35_PAD_I2C1_DAT = 69,
97 MX35_PAD_SD25 = 70, 97 MX35_PAD_I2C2_CLK = 70,
98 MX35_PAD_SD26 = 71, 98 MX35_PAD_I2C2_DAT = 71,
99 MX35_PAD_SD27 = 72, 99 MX35_PAD_STXD4 = 72,
100 MX35_PAD_SD28 = 73, 100 MX35_PAD_SRXD4 = 73,
101 MX35_PAD_SD29 = 74, 101 MX35_PAD_SCK4 = 74,
102 MX35_PAD_SD30 = 75, 102 MX35_PAD_STXFS4 = 75,
103 MX35_PAD_SD31 = 76, 103 MX35_PAD_STXD5 = 76,
104 MX35_PAD_DQM0 = 77, 104 MX35_PAD_SRXD5 = 77,
105 MX35_PAD_DQM1 = 78, 105 MX35_PAD_SCK5 = 78,
106 MX35_PAD_DQM2 = 79, 106 MX35_PAD_STXFS5 = 79,
107 MX35_PAD_DQM3 = 80, 107 MX35_PAD_SCKR = 80,
108 MX35_PAD_EB0 = 81, 108 MX35_PAD_FSR = 81,
109 MX35_PAD_EB1 = 82, 109 MX35_PAD_HCKR = 82,
110 MX35_PAD_OE = 83, 110 MX35_PAD_SCKT = 83,
111 MX35_PAD_CS0 = 84, 111 MX35_PAD_FST = 84,
112 MX35_PAD_CS1 = 85, 112 MX35_PAD_HCKT = 85,
113 MX35_PAD_CS2 = 86, 113 MX35_PAD_TX5_RX0 = 86,
114 MX35_PAD_CS3 = 87, 114 MX35_PAD_TX4_RX1 = 87,
115 MX35_PAD_CS4 = 88, 115 MX35_PAD_TX3_RX2 = 88,
116 MX35_PAD_CS5 = 89, 116 MX35_PAD_TX2_RX3 = 89,
117 MX35_PAD_NF_CE0 = 90, 117 MX35_PAD_TX1 = 90,
118 MX35_PAD_ECB = 91, 118 MX35_PAD_TX0 = 91,
119 MX35_PAD_LBA = 92, 119 MX35_PAD_CSPI1_MOSI = 92,
120 MX35_PAD_BCLK = 93, 120 MX35_PAD_CSPI1_MISO = 93,
121 MX35_PAD_RW = 94, 121 MX35_PAD_CSPI1_SS0 = 94,
122 MX35_PAD_RAS = 95, 122 MX35_PAD_CSPI1_SS1 = 95,
123 MX35_PAD_CAS = 96, 123 MX35_PAD_CSPI1_SCLK = 96,
124 MX35_PAD_SDWE = 97, 124 MX35_PAD_CSPI1_SPI_RDY = 97,
125 MX35_PAD_SDCKE0 = 98, 125 MX35_PAD_RXD1 = 98,
126 MX35_PAD_SDCKE1 = 99, 126 MX35_PAD_TXD1 = 99,
127 MX35_PAD_SDCLK = 100, 127 MX35_PAD_RTS1 = 100,
128 MX35_PAD_SDQS0 = 101, 128 MX35_PAD_CTS1 = 101,
129 MX35_PAD_SDQS1 = 102, 129 MX35_PAD_RXD2 = 102,
130 MX35_PAD_SDQS2 = 103, 130 MX35_PAD_TXD2 = 103,
131 MX35_PAD_SDQS3 = 104, 131 MX35_PAD_RTS2 = 104,
132 MX35_PAD_NFWE_B = 105, 132 MX35_PAD_CTS2 = 105,
133 MX35_PAD_NFRE_B = 106, 133 MX35_PAD_USBOTG_PWR = 106,
134 MX35_PAD_NFALE = 107, 134 MX35_PAD_USBOTG_OC = 107,
135 MX35_PAD_NFCLE = 108, 135 MX35_PAD_LD0 = 108,
136 MX35_PAD_NFWP_B = 109, 136 MX35_PAD_LD1 = 109,
137 MX35_PAD_NFRB = 110, 137 MX35_PAD_LD2 = 110,
138 MX35_PAD_D15 = 111, 138 MX35_PAD_LD3 = 111,
139 MX35_PAD_D14 = 112, 139 MX35_PAD_LD4 = 112,
140 MX35_PAD_D13 = 113, 140 MX35_PAD_LD5 = 113,
141 MX35_PAD_D12 = 114, 141 MX35_PAD_LD6 = 114,
142 MX35_PAD_D11 = 115, 142 MX35_PAD_LD7 = 115,
143 MX35_PAD_D10 = 116, 143 MX35_PAD_LD8 = 116,
144 MX35_PAD_D9 = 117, 144 MX35_PAD_LD9 = 117,
145 MX35_PAD_D8 = 118, 145 MX35_PAD_LD10 = 118,
146 MX35_PAD_D7 = 119, 146 MX35_PAD_LD11 = 119,
147 MX35_PAD_D6 = 120, 147 MX35_PAD_LD12 = 120,
148 MX35_PAD_D5 = 121, 148 MX35_PAD_LD13 = 121,
149 MX35_PAD_D4 = 122, 149 MX35_PAD_LD14 = 122,
150 MX35_PAD_D3 = 123, 150 MX35_PAD_LD15 = 123,
151 MX35_PAD_D2 = 124, 151 MX35_PAD_LD16 = 124,
152 MX35_PAD_D1 = 125, 152 MX35_PAD_LD17 = 125,
153 MX35_PAD_D0 = 126, 153 MX35_PAD_LD18 = 126,
154 MX35_PAD_CSI_D8 = 127, 154 MX35_PAD_LD19 = 127,
155 MX35_PAD_CSI_D9 = 128, 155 MX35_PAD_LD20 = 128,
156 MX35_PAD_CSI_D10 = 129, 156 MX35_PAD_LD21 = 129,
157 MX35_PAD_CSI_D11 = 130, 157 MX35_PAD_LD22 = 130,
158 MX35_PAD_CSI_D12 = 131, 158 MX35_PAD_LD23 = 131,
159 MX35_PAD_CSI_D13 = 132, 159 MX35_PAD_D3_HSYNC = 132,
160 MX35_PAD_CSI_D14 = 133, 160 MX35_PAD_D3_FPSHIFT = 133,
161 MX35_PAD_CSI_D15 = 134, 161 MX35_PAD_D3_DRDY = 134,
162 MX35_PAD_CSI_MCLK = 135, 162 MX35_PAD_CONTRAST = 135,
163 MX35_PAD_CSI_VSYNC = 136, 163 MX35_PAD_D3_VSYNC = 136,
164 MX35_PAD_CSI_HSYNC = 137, 164 MX35_PAD_D3_REV = 137,
165 MX35_PAD_CSI_PIXCLK = 138, 165 MX35_PAD_D3_CLS = 138,
166 MX35_PAD_I2C1_CLK = 139, 166 MX35_PAD_D3_SPL = 139,
167 MX35_PAD_I2C1_DAT = 140, 167 MX35_PAD_SD1_CMD = 140,
168 MX35_PAD_I2C2_CLK = 141, 168 MX35_PAD_SD1_CLK = 141,
169 MX35_PAD_I2C2_DAT = 142, 169 MX35_PAD_SD1_DATA0 = 142,
170 MX35_PAD_STXD4 = 143, 170 MX35_PAD_SD1_DATA1 = 143,
171 MX35_PAD_SRXD4 = 144, 171 MX35_PAD_SD1_DATA2 = 144,
172 MX35_PAD_SCK4 = 145, 172 MX35_PAD_SD1_DATA3 = 145,
173 MX35_PAD_STXFS4 = 146, 173 MX35_PAD_SD2_CMD = 146,
174 MX35_PAD_STXD5 = 147, 174 MX35_PAD_SD2_CLK = 147,
175 MX35_PAD_SRXD5 = 148, 175 MX35_PAD_SD2_DATA0 = 148,
176 MX35_PAD_SCK5 = 149, 176 MX35_PAD_SD2_DATA1 = 149,
177 MX35_PAD_STXFS5 = 150, 177 MX35_PAD_SD2_DATA2 = 150,
178 MX35_PAD_SCKR = 151, 178 MX35_PAD_SD2_DATA3 = 151,
179 MX35_PAD_FSR = 152, 179 MX35_PAD_ATA_CS0 = 152,
180 MX35_PAD_HCKR = 153, 180 MX35_PAD_ATA_CS1 = 153,
181 MX35_PAD_SCKT = 154, 181 MX35_PAD_ATA_DIOR = 154,
182 MX35_PAD_FST = 155, 182 MX35_PAD_ATA_DIOW = 155,
183 MX35_PAD_HCKT = 156, 183 MX35_PAD_ATA_DMACK = 156,
184 MX35_PAD_TX5_RX0 = 157, 184 MX35_PAD_ATA_RESET_B = 157,
185 MX35_PAD_TX4_RX1 = 158, 185 MX35_PAD_ATA_IORDY = 158,
186 MX35_PAD_TX3_RX2 = 159, 186 MX35_PAD_ATA_DATA0 = 159,
187 MX35_PAD_TX2_RX3 = 160, 187 MX35_PAD_ATA_DATA1 = 160,
188 MX35_PAD_TX1 = 161, 188 MX35_PAD_ATA_DATA2 = 161,
189 MX35_PAD_TX0 = 162, 189 MX35_PAD_ATA_DATA3 = 162,
190 MX35_PAD_CSPI1_MOSI = 163, 190 MX35_PAD_ATA_DATA4 = 163,
191 MX35_PAD_CSPI1_MISO = 164, 191 MX35_PAD_ATA_DATA5 = 164,
192 MX35_PAD_CSPI1_SS0 = 165, 192 MX35_PAD_ATA_DATA6 = 165,
193 MX35_PAD_CSPI1_SS1 = 166, 193 MX35_PAD_ATA_DATA7 = 166,
194 MX35_PAD_CSPI1_SCLK = 167, 194 MX35_PAD_ATA_DATA8 = 167,
195 MX35_PAD_CSPI1_SPI_RDY = 168, 195 MX35_PAD_ATA_DATA9 = 168,
196 MX35_PAD_RXD1 = 169, 196 MX35_PAD_ATA_DATA10 = 169,
197 MX35_PAD_TXD1 = 170, 197 MX35_PAD_ATA_DATA11 = 170,
198 MX35_PAD_RTS1 = 171, 198 MX35_PAD_ATA_DATA12 = 171,
199 MX35_PAD_CTS1 = 172, 199 MX35_PAD_ATA_DATA13 = 172,
200 MX35_PAD_RXD2 = 173, 200 MX35_PAD_ATA_DATA14 = 173,
201 MX35_PAD_TXD2 = 174, 201 MX35_PAD_ATA_DATA15 = 174,
202 MX35_PAD_RTS2 = 175, 202 MX35_PAD_ATA_INTRQ = 175,
203 MX35_PAD_CTS2 = 176, 203 MX35_PAD_ATA_BUFF_EN = 176,
204 MX35_PAD_RTCK = 177, 204 MX35_PAD_ATA_DMARQ = 177,
205 MX35_PAD_TCK = 178, 205 MX35_PAD_ATA_DA0 = 178,
206 MX35_PAD_TMS = 179, 206 MX35_PAD_ATA_DA1 = 179,
207 MX35_PAD_TDI = 180, 207 MX35_PAD_ATA_DA2 = 180,
208 MX35_PAD_TDO = 181, 208 MX35_PAD_MLB_CLK = 181,
209 MX35_PAD_TRSTB = 182, 209 MX35_PAD_MLB_DAT = 182,
210 MX35_PAD_DE_B = 183, 210 MX35_PAD_MLB_SIG = 183,
211 MX35_PAD_SJC_MOD = 184, 211 MX35_PAD_FEC_TX_CLK = 184,
212 MX35_PAD_USBOTG_PWR = 185, 212 MX35_PAD_FEC_RX_CLK = 185,
213 MX35_PAD_USBOTG_OC = 186, 213 MX35_PAD_FEC_RX_DV = 186,
214 MX35_PAD_LD0 = 187, 214 MX35_PAD_FEC_COL = 187,
215 MX35_PAD_LD1 = 188, 215 MX35_PAD_FEC_RDATA0 = 188,
216 MX35_PAD_LD2 = 189, 216 MX35_PAD_FEC_TDATA0 = 189,
217 MX35_PAD_LD3 = 190, 217 MX35_PAD_FEC_TX_EN = 190,
218 MX35_PAD_LD4 = 191, 218 MX35_PAD_FEC_MDC = 191,
219 MX35_PAD_LD5 = 192, 219 MX35_PAD_FEC_MDIO = 192,
220 MX35_PAD_LD6 = 193, 220 MX35_PAD_FEC_TX_ERR = 193,
221 MX35_PAD_LD7 = 194, 221 MX35_PAD_FEC_RX_ERR = 194,
222 MX35_PAD_LD8 = 195, 222 MX35_PAD_FEC_CRS = 195,
223 MX35_PAD_LD9 = 196, 223 MX35_PAD_FEC_RDATA1 = 196,
224 MX35_PAD_LD10 = 197, 224 MX35_PAD_FEC_TDATA1 = 197,
225 MX35_PAD_LD11 = 198, 225 MX35_PAD_FEC_RDATA2 = 198,
226 MX35_PAD_LD12 = 199, 226 MX35_PAD_FEC_TDATA2 = 199,
227 MX35_PAD_LD13 = 200, 227 MX35_PAD_FEC_RDATA3 = 200,
228 MX35_PAD_LD14 = 201, 228 MX35_PAD_FEC_TDATA3 = 201,
229 MX35_PAD_LD15 = 202, 229 MX35_PAD_RESERVE1 = 202,
230 MX35_PAD_LD16 = 203, 230 MX35_PAD_RESERVE2 = 203,
231 MX35_PAD_LD17 = 204, 231 MX35_PAD_RESERVE3 = 204,
232 MX35_PAD_LD18 = 205, 232 MX35_PAD_RESERVE4 = 205,
233 MX35_PAD_LD19 = 206, 233 MX35_PAD_RESERVE5 = 206,
234 MX35_PAD_LD20 = 207, 234 MX35_PAD_RESERVE6 = 207,
235 MX35_PAD_LD21 = 208, 235 MX35_PAD_RESERVE7 = 208,
236 MX35_PAD_LD22 = 209, 236 MX35_PAD_RESET_IN_B = 209,
237 MX35_PAD_LD23 = 210, 237 MX35_PAD_POR_B = 210,
238 MX35_PAD_D3_HSYNC = 211, 238 MX35_PAD_RESERVE8 = 211,
239 MX35_PAD_D3_FPSHIFT = 212, 239 MX35_PAD_BOOT_MODE0 = 212,
240 MX35_PAD_D3_DRDY = 213, 240 MX35_PAD_BOOT_MODE1 = 213,
241 MX35_PAD_CONTRAST = 214, 241 MX35_PAD_CLK_MODE0 = 214,
242 MX35_PAD_D3_VSYNC = 215, 242 MX35_PAD_CLK_MODE1 = 215,
243 MX35_PAD_D3_REV = 216, 243 MX35_PAD_POWER_FAIL = 216,
244 MX35_PAD_D3_CLS = 217, 244 MX35_PAD_RESERVE9 = 217,
245 MX35_PAD_D3_SPL = 218, 245 MX35_PAD_RESERVE10 = 218,
246 MX35_PAD_SD1_CMD = 219, 246 MX35_PAD_RESERVE11 = 219,
247 MX35_PAD_SD1_CLK = 220, 247 MX35_PAD_RESERVE12 = 220,
248 MX35_PAD_SD1_DATA0 = 221, 248 MX35_PAD_RESERVE13 = 221,
249 MX35_PAD_SD1_DATA1 = 222, 249 MX35_PAD_RESERVE14 = 222,
250 MX35_PAD_SD1_DATA2 = 223, 250 MX35_PAD_RESERVE15 = 223,
251 MX35_PAD_SD1_DATA3 = 224, 251 MX35_PAD_RESERVE16 = 224,
252 MX35_PAD_SD2_CMD = 225, 252 MX35_PAD_RESERVE17 = 225,
253 MX35_PAD_SD2_CLK = 226, 253 MX35_PAD_RESERVE18 = 226,
254 MX35_PAD_SD2_DATA0 = 227, 254 MX35_PAD_RESERVE19 = 227,
255 MX35_PAD_SD2_DATA1 = 228, 255 MX35_PAD_RESERVE20 = 228,
256 MX35_PAD_SD2_DATA2 = 229, 256 MX35_PAD_RESERVE21 = 229,
257 MX35_PAD_SD2_DATA3 = 230, 257 MX35_PAD_RESERVE22 = 230,
258 MX35_PAD_ATA_CS0 = 231, 258 MX35_PAD_RESERVE23 = 231,
259 MX35_PAD_ATA_CS1 = 232, 259 MX35_PAD_RESERVE24 = 232,
260 MX35_PAD_ATA_DIOR = 233, 260 MX35_PAD_RESERVE25 = 233,
261 MX35_PAD_ATA_DIOW = 234, 261 MX35_PAD_RESERVE26 = 234,
262 MX35_PAD_ATA_DMACK = 235, 262 MX35_PAD_RESERVE27 = 235,
263 MX35_PAD_ATA_RESET_B = 236, 263 MX35_PAD_RESERVE28 = 236,
264 MX35_PAD_ATA_IORDY = 237, 264 MX35_PAD_RESERVE29 = 237,
265 MX35_PAD_ATA_DATA0 = 238, 265 MX35_PAD_RESERVE30 = 238,
266 MX35_PAD_ATA_DATA1 = 239, 266 MX35_PAD_RESERVE31 = 239,
267 MX35_PAD_ATA_DATA2 = 240, 267 MX35_PAD_RESERVE32 = 240,
268 MX35_PAD_ATA_DATA3 = 241, 268 MX35_PAD_RESERVE33 = 241,
269 MX35_PAD_ATA_DATA4 = 242, 269 MX35_PAD_RESERVE34 = 242,
270 MX35_PAD_ATA_DATA5 = 243, 270 MX35_PAD_RESERVE35 = 243,
271 MX35_PAD_ATA_DATA6 = 244, 271 MX35_PAD_RESERVE36 = 244,
272 MX35_PAD_ATA_DATA7 = 245, 272 MX35_PAD_SDBA1 = 245,
273 MX35_PAD_ATA_DATA8 = 246, 273 MX35_PAD_SDBA0 = 246,
274 MX35_PAD_ATA_DATA9 = 247, 274 MX35_PAD_SD0 = 247,
275 MX35_PAD_ATA_DATA10 = 248, 275 MX35_PAD_SD1 = 248,
276 MX35_PAD_ATA_DATA11 = 249, 276 MX35_PAD_SD2 = 249,
277 MX35_PAD_ATA_DATA12 = 250, 277 MX35_PAD_SD3 = 250,
278 MX35_PAD_ATA_DATA13 = 251, 278 MX35_PAD_SD4 = 251,
279 MX35_PAD_ATA_DATA14 = 252, 279 MX35_PAD_SD5 = 252,
280 MX35_PAD_ATA_DATA15 = 253, 280 MX35_PAD_SD6 = 253,
281 MX35_PAD_ATA_INTRQ = 254, 281 MX35_PAD_SD7 = 254,
282 MX35_PAD_ATA_BUFF_EN = 255, 282 MX35_PAD_SD8 = 255,
283 MX35_PAD_ATA_DMARQ = 256, 283 MX35_PAD_SD9 = 256,
284 MX35_PAD_ATA_DA0 = 257, 284 MX35_PAD_SD10 = 257,
285 MX35_PAD_ATA_DA1 = 258, 285 MX35_PAD_SD11 = 258,
286 MX35_PAD_ATA_DA2 = 259, 286 MX35_PAD_SD12 = 259,
287 MX35_PAD_MLB_CLK = 260, 287 MX35_PAD_SD13 = 260,
288 MX35_PAD_MLB_DAT = 261, 288 MX35_PAD_SD14 = 261,
289 MX35_PAD_MLB_SIG = 262, 289 MX35_PAD_SD15 = 262,
290 MX35_PAD_FEC_TX_CLK = 263, 290 MX35_PAD_SD16 = 263,
291 MX35_PAD_FEC_RX_CLK = 264, 291 MX35_PAD_SD17 = 264,
292 MX35_PAD_FEC_RX_DV = 265, 292 MX35_PAD_SD18 = 265,
293 MX35_PAD_FEC_COL = 266, 293 MX35_PAD_SD19 = 266,
294 MX35_PAD_FEC_RDATA0 = 267, 294 MX35_PAD_SD20 = 267,
295 MX35_PAD_FEC_TDATA0 = 268, 295 MX35_PAD_SD21 = 268,
296 MX35_PAD_FEC_TX_EN = 269, 296 MX35_PAD_SD22 = 269,
297 MX35_PAD_FEC_MDC = 270, 297 MX35_PAD_SD23 = 270,
298 MX35_PAD_FEC_MDIO = 271, 298 MX35_PAD_SD24 = 271,
299 MX35_PAD_FEC_TX_ERR = 272, 299 MX35_PAD_SD25 = 272,
300 MX35_PAD_FEC_RX_ERR = 273, 300 MX35_PAD_SD26 = 273,
301 MX35_PAD_FEC_CRS = 274, 301 MX35_PAD_SD27 = 274,
302 MX35_PAD_FEC_RDATA1 = 275, 302 MX35_PAD_SD28 = 275,
303 MX35_PAD_FEC_TDATA1 = 276, 303 MX35_PAD_SD29 = 276,
304 MX35_PAD_FEC_RDATA2 = 277, 304 MX35_PAD_SD30 = 277,
305 MX35_PAD_FEC_TDATA2 = 278, 305 MX35_PAD_SD31 = 278,
306 MX35_PAD_FEC_RDATA3 = 279, 306 MX35_PAD_DQM0 = 279,
307 MX35_PAD_FEC_TDATA3 = 280, 307 MX35_PAD_DQM1 = 280,
308 MX35_PAD_EXT_ARMCLK = 281, 308 MX35_PAD_DQM2 = 281,
309 MX35_PAD_TEST_MODE = 282, 309 MX35_PAD_DQM3 = 282,
310}; 310 MX35_PAD_RESERVE37 = 283,
311 311 MX35_PAD_RESERVE38 = 284,
312/* imx35 register maps */ 312 MX35_PAD_RESERVE39 = 285,
313static struct imx_pin_reg imx35_pin_regs[] = { 313 MX35_PAD_RESERVE40 = 286,
314 [0] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 0, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CAPIN1 */ 314 MX35_PAD_RESERVE41 = 287,
315 [1] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 1, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CMPOUT2 */ 315 MX35_PAD_RESERVE42 = 288,
316 [2] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 2, 0x7f4, 0), /* MX35_PAD_CAPTURE__CSPI2_SS1 */ 316 MX35_PAD_RESERVE43 = 289,
317 [3] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 3, 0x0, 0), /* MX35_PAD_CAPTURE__EPIT1_EPITO */ 317 MX35_PAD_RESERVE44 = 290,
318 [4] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 4, 0x7d0, 0), /* MX35_PAD_CAPTURE__CCM_CLK32K */ 318 MX35_PAD_RESERVE45 = 291,
319 [5] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 5, 0x850, 0), /* MX35_PAD_CAPTURE__GPIO1_4 */ 319 MX35_PAD_RESERVE46 = 292,
320 [6] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 0, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT1 */ 320 MX35_PAD_ECB = 293,
321 [7] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 1, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CAPIN2 */ 321 MX35_PAD_RESERVE47 = 294,
322 [8] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 2, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT3 */ 322 MX35_PAD_RESERVE48 = 295,
323 [9] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 3, 0x0, 0), /* MX35_PAD_COMPARE__EPIT2_EPITO */ 323 MX35_PAD_RESERVE49 = 296,
324 [10] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 5, 0x854, 0), /* MX35_PAD_COMPARE__GPIO1_5 */ 324 MX35_PAD_RAS = 297,
325 [11] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 7, 0x0, 0), /* MX35_PAD_COMPARE__SDMA_EXTDMA_2 */ 325 MX35_PAD_CAS = 298,
326 [12] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 0, 0x0, 0), /* MX35_PAD_WDOG_RST__WDOG_WDOG_B */ 326 MX35_PAD_SDWE = 299,
327 [13] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 3, 0x0, 0), /* MX35_PAD_WDOG_RST__IPU_FLASH_STROBE */ 327 MX35_PAD_SDCKE0 = 300,
328 [14] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 5, 0x858, 0), /* MX35_PAD_WDOG_RST__GPIO1_6 */ 328 MX35_PAD_SDCKE1 = 301,
329 [15] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 0, 0x82c, 0), /* MX35_PAD_GPIO1_0__GPIO1_0 */ 329 MX35_PAD_SDCLK = 302,
330 [16] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 1, 0x7d4, 0), /* MX35_PAD_GPIO1_0__CCM_PMIC_RDY */ 330 MX35_PAD_SDQS0 = 303,
331 [17] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 2, 0x990, 0), /* MX35_PAD_GPIO1_0__OWIRE_LINE */ 331 MX35_PAD_SDQS1 = 304,
332 [18] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 7, 0x0, 0), /* MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 */ 332 MX35_PAD_SDQS2 = 305,
333 [19] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 0, 0x838, 0), /* MX35_PAD_GPIO1_1__GPIO1_1 */ 333 MX35_PAD_SDQS3 = 306,
334 [20] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 2, 0x0, 0), /* MX35_PAD_GPIO1_1__PWM_PWMO */ 334 MX35_PAD_RESERVE50 = 307,
335 [21] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 3, 0x7d8, 0), /* MX35_PAD_GPIO1_1__CSPI1_SS2 */ 335 MX35_PAD_RESERVE51 = 308,
336 [22] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 6, 0x0, 0), /* MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT */ 336 MX35_PAD_RESERVE52 = 309,
337 [23] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 7, 0x0, 0), /* MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 */ 337 MX35_PAD_RESERVE53 = 310,
338 [24] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 0, 0x868, 0), /* MX35_PAD_GPIO2_0__GPIO2_0 */ 338 MX35_PAD_RESERVE54 = 311,
339 [25] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 1, 0x0, 0), /* MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK */ 339 MX35_PAD_RESERVE55 = 312,
340 [26] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 0, 0x8e8, 0), /* MX35_PAD_GPIO3_0__GPIO3_0 */ 340 MX35_PAD_D15 = 313,
341 [27] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 1, 0x0, 0), /* MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK */ 341 MX35_PAD_D14 = 314,
342 [28] = IMX_PIN_REG(MX35_PAD_RESET_IN_B, 0x344, 0x0, 0, 0x0, 0), /* MX35_PAD_RESET_IN_B__CCM_RESET_IN_B */ 342 MX35_PAD_D13 = 315,
343 [29] = IMX_PIN_REG(MX35_PAD_POR_B, 0x348, 0x0, 0, 0x0, 0), /* MX35_PAD_POR_B__CCM_POR_B */ 343 MX35_PAD_D12 = 316,
344 [30] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 0, 0x0, 0), /* MX35_PAD_CLKO__CCM_CLKO */ 344 MX35_PAD_D11 = 317,
345 [31] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 5, 0x860, 0), /* MX35_PAD_CLKO__GPIO1_8 */ 345 MX35_PAD_D10 = 318,
346 [32] = IMX_PIN_REG(MX35_PAD_BOOT_MODE0, 0x350, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 */ 346 MX35_PAD_D9 = 319,
347 [33] = IMX_PIN_REG(MX35_PAD_BOOT_MODE1, 0x354, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 */ 347 MX35_PAD_D8 = 320,
348 [34] = IMX_PIN_REG(MX35_PAD_CLK_MODE0, 0x358, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 */ 348 MX35_PAD_D7 = 321,
349 [35] = IMX_PIN_REG(MX35_PAD_CLK_MODE1, 0x35c, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 */ 349 MX35_PAD_D6 = 322,
350 [36] = IMX_PIN_REG(MX35_PAD_POWER_FAIL, 0x360, 0x0, 0, 0x0, 0), /* MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 */ 350 MX35_PAD_D5 = 323,
351 [37] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 0, 0x0, 0), /* MX35_PAD_VSTBY__CCM_VSTBY */ 351 MX35_PAD_D4 = 324,
352 [38] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 5, 0x85c, 0), /* MX35_PAD_VSTBY__GPIO1_7 */ 352 MX35_PAD_D3 = 325,
353 [39] = IMX_PIN_REG(MX35_PAD_A0, 0x368, 0x028, 0, 0x0, 0), /* MX35_PAD_A0__EMI_EIM_DA_L_0 */ 353 MX35_PAD_D2 = 326,
354 [40] = IMX_PIN_REG(MX35_PAD_A1, 0x36c, 0x02c, 0, 0x0, 0), /* MX35_PAD_A1__EMI_EIM_DA_L_1 */ 354 MX35_PAD_D1 = 327,
355 [41] = IMX_PIN_REG(MX35_PAD_A2, 0x370, 0x030, 0, 0x0, 0), /* MX35_PAD_A2__EMI_EIM_DA_L_2 */ 355 MX35_PAD_D0 = 328,
356 [42] = IMX_PIN_REG(MX35_PAD_A3, 0x374, 0x034, 0, 0x0, 0), /* MX35_PAD_A3__EMI_EIM_DA_L_3 */ 356 MX35_PAD_RESERVE56 = 329,
357 [43] = IMX_PIN_REG(MX35_PAD_A4, 0x378, 0x038, 0, 0x0, 0), /* MX35_PAD_A4__EMI_EIM_DA_L_4 */ 357 MX35_PAD_RESERVE57 = 330,
358 [44] = IMX_PIN_REG(MX35_PAD_A5, 0x37c, 0x03c, 0, 0x0, 0), /* MX35_PAD_A5__EMI_EIM_DA_L_5 */ 358 MX35_PAD_RESERVE58 = 331,
359 [45] = IMX_PIN_REG(MX35_PAD_A6, 0x380, 0x040, 0, 0x0, 0), /* MX35_PAD_A6__EMI_EIM_DA_L_6 */ 359 MX35_PAD_RESERVE59 = 332,
360 [46] = IMX_PIN_REG(MX35_PAD_A7, 0x384, 0x044, 0, 0x0, 0), /* MX35_PAD_A7__EMI_EIM_DA_L_7 */ 360 MX35_PAD_RESERVE60 = 333,
361 [47] = IMX_PIN_REG(MX35_PAD_A8, 0x388, 0x048, 0, 0x0, 0), /* MX35_PAD_A8__EMI_EIM_DA_H_8 */ 361 MX35_PAD_RESERVE61 = 334,
362 [48] = IMX_PIN_REG(MX35_PAD_A9, 0x38c, 0x04c, 0, 0x0, 0), /* MX35_PAD_A9__EMI_EIM_DA_H_9 */ 362 MX35_PAD_RESERVE62 = 335,
363 [49] = IMX_PIN_REG(MX35_PAD_A10, 0x390, 0x050, 0, 0x0, 0), /* MX35_PAD_A10__EMI_EIM_DA_H_10 */ 363 MX35_PAD_RESERVE63 = 336,
364 [50] = IMX_PIN_REG(MX35_PAD_MA10, 0x394, 0x054, 0, 0x0, 0), /* MX35_PAD_MA10__EMI_MA10 */ 364 MX35_PAD_RESERVE64 = 337,
365 [51] = IMX_PIN_REG(MX35_PAD_A11, 0x398, 0x058, 0, 0x0, 0), /* MX35_PAD_A11__EMI_EIM_DA_H_11 */ 365 MX35_PAD_RESERVE65 = 338,
366 [52] = IMX_PIN_REG(MX35_PAD_A12, 0x39c, 0x05c, 0, 0x0, 0), /* MX35_PAD_A12__EMI_EIM_DA_H_12 */ 366 MX35_PAD_RESERVE66 = 339,
367 [53] = IMX_PIN_REG(MX35_PAD_A13, 0x3a0, 0x060, 0, 0x0, 0), /* MX35_PAD_A13__EMI_EIM_DA_H_13 */ 367 MX35_PAD_RESERVE67 = 340,
368 [54] = IMX_PIN_REG(MX35_PAD_A14, 0x3a4, 0x064, 0, 0x0, 0), /* MX35_PAD_A14__EMI_EIM_DA_H2_14 */ 368 MX35_PAD_RESERVE68 = 341,
369 [55] = IMX_PIN_REG(MX35_PAD_A15, 0x3a8, 0x068, 0, 0x0, 0), /* MX35_PAD_A15__EMI_EIM_DA_H2_15 */ 369 MX35_PAD_RESERVE69 = 342,
370 [56] = IMX_PIN_REG(MX35_PAD_A16, 0x3ac, 0x06c, 0, 0x0, 0), /* MX35_PAD_A16__EMI_EIM_A_16 */ 370 MX35_PAD_RESERVE70 = 343,
371 [57] = IMX_PIN_REG(MX35_PAD_A17, 0x3b0, 0x070, 0, 0x0, 0), /* MX35_PAD_A17__EMI_EIM_A_17 */ 371 MX35_PAD_RESERVE71 = 344,
372 [58] = IMX_PIN_REG(MX35_PAD_A18, 0x3b4, 0x074, 0, 0x0, 0), /* MX35_PAD_A18__EMI_EIM_A_18 */ 372 MX35_PAD_RESERVE72 = 345,
373 [59] = IMX_PIN_REG(MX35_PAD_A19, 0x3b8, 0x078, 0, 0x0, 0), /* MX35_PAD_A19__EMI_EIM_A_19 */ 373 MX35_PAD_RESERVE73 = 346,
374 [60] = IMX_PIN_REG(MX35_PAD_A20, 0x3bc, 0x07c, 0, 0x0, 0), /* MX35_PAD_A20__EMI_EIM_A_20 */ 374 MX35_PAD_RESERVE74 = 347,
375 [61] = IMX_PIN_REG(MX35_PAD_A21, 0x3c0, 0x080, 0, 0x0, 0), /* MX35_PAD_A21__EMI_EIM_A_21 */ 375 MX35_PAD_RESERVE75 = 348,
376 [62] = IMX_PIN_REG(MX35_PAD_A22, 0x3c4, 0x084, 0, 0x0, 0), /* MX35_PAD_A22__EMI_EIM_A_22 */ 376 MX35_PAD_RESERVE76 = 349,
377 [63] = IMX_PIN_REG(MX35_PAD_A23, 0x3c8, 0x088, 0, 0x0, 0), /* MX35_PAD_A23__EMI_EIM_A_23 */ 377 MX35_PAD_RESERVE77 = 350,
378 [64] = IMX_PIN_REG(MX35_PAD_A24, 0x3cc, 0x08c, 0, 0x0, 0), /* MX35_PAD_A24__EMI_EIM_A_24 */ 378 MX35_PAD_RESERVE78 = 351,
379 [65] = IMX_PIN_REG(MX35_PAD_A25, 0x3d0, 0x090, 0, 0x0, 0), /* MX35_PAD_A25__EMI_EIM_A_25 */ 379 MX35_PAD_RESERVE79 = 352,
380 [66] = IMX_PIN_REG(MX35_PAD_SDBA1, 0x3d4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA1__EMI_EIM_SDBA1 */ 380 MX35_PAD_RESERVE80 = 353,
381 [67] = IMX_PIN_REG(MX35_PAD_SDBA0, 0x3d8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA0__EMI_EIM_SDBA0 */ 381 MX35_PAD_RESERVE81 = 354,
382 [68] = IMX_PIN_REG(MX35_PAD_SD0, 0x3dc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD0__EMI_DRAM_D_0 */ 382 MX35_PAD_RESERVE82 = 355,
383 [69] = IMX_PIN_REG(MX35_PAD_SD1, 0x3e0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD1__EMI_DRAM_D_1 */ 383 MX35_PAD_RESERVE83 = 356,
384 [70] = IMX_PIN_REG(MX35_PAD_SD2, 0x3e4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD2__EMI_DRAM_D_2 */ 384 MX35_PAD_RESERVE84 = 357,
385 [71] = IMX_PIN_REG(MX35_PAD_SD3, 0x3e8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD3__EMI_DRAM_D_3 */ 385 MX35_PAD_RESERVE85 = 358,
386 [72] = IMX_PIN_REG(MX35_PAD_SD4, 0x3ec, 0x0, 0, 0x0, 0), /* MX35_PAD_SD4__EMI_DRAM_D_4 */ 386 MX35_PAD_RESERVE86 = 359,
387 [73] = IMX_PIN_REG(MX35_PAD_SD5, 0x3f0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD5__EMI_DRAM_D_5 */ 387 MX35_PAD_RESERVE87 = 360,
388 [74] = IMX_PIN_REG(MX35_PAD_SD6, 0x3f4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD6__EMI_DRAM_D_6 */ 388 MX35_PAD_RESERVE88 = 361,
389 [75] = IMX_PIN_REG(MX35_PAD_SD7, 0x3f8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD7__EMI_DRAM_D_7 */ 389 MX35_PAD_RESERVE89 = 362,
390 [76] = IMX_PIN_REG(MX35_PAD_SD8, 0x3fc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD8__EMI_DRAM_D_8 */ 390 MX35_PAD_RESERVE90 = 363,
391 [77] = IMX_PIN_REG(MX35_PAD_SD9, 0x400, 0x0, 0, 0x0, 0), /* MX35_PAD_SD9__EMI_DRAM_D_9 */ 391 MX35_PAD_RESERVE91 = 364,
392 [78] = IMX_PIN_REG(MX35_PAD_SD10, 0x404, 0x0, 0, 0x0, 0), /* MX35_PAD_SD10__EMI_DRAM_D_10 */ 392 MX35_PAD_RESERVE92 = 365,
393 [79] = IMX_PIN_REG(MX35_PAD_SD11, 0x408, 0x0, 0, 0x0, 0), /* MX35_PAD_SD11__EMI_DRAM_D_11 */ 393 MX35_PAD_RESERVE93 = 366,
394 [80] = IMX_PIN_REG(MX35_PAD_SD12, 0x40c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD12__EMI_DRAM_D_12 */ 394 MX35_PAD_RESERVE94 = 367,
395 [81] = IMX_PIN_REG(MX35_PAD_SD13, 0x410, 0x0, 0, 0x0, 0), /* MX35_PAD_SD13__EMI_DRAM_D_13 */ 395 MX35_PAD_RESERVE95 = 368,
396 [82] = IMX_PIN_REG(MX35_PAD_SD14, 0x414, 0x0, 0, 0x0, 0), /* MX35_PAD_SD14__EMI_DRAM_D_14 */ 396 MX35_PAD_RESERVE96 = 369,
397 [83] = IMX_PIN_REG(MX35_PAD_SD15, 0x418, 0x0, 0, 0x0, 0), /* MX35_PAD_SD15__EMI_DRAM_D_15 */ 397 MX35_PAD_RESERVE97 = 370,
398 [84] = IMX_PIN_REG(MX35_PAD_SD16, 0x41c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD16__EMI_DRAM_D_16 */ 398 MX35_PAD_RESERVE98 = 371,
399 [85] = IMX_PIN_REG(MX35_PAD_SD17, 0x420, 0x0, 0, 0x0, 0), /* MX35_PAD_SD17__EMI_DRAM_D_17 */ 399 MX35_PAD_RESERVE99 = 372,
400 [86] = IMX_PIN_REG(MX35_PAD_SD18, 0x424, 0x0, 0, 0x0, 0), /* MX35_PAD_SD18__EMI_DRAM_D_18 */ 400 MX35_PAD_RESERVE100 = 373,
401 [87] = IMX_PIN_REG(MX35_PAD_SD19, 0x428, 0x0, 0, 0x0, 0), /* MX35_PAD_SD19__EMI_DRAM_D_19 */ 401 MX35_PAD_RESERVE101 = 374,
402 [88] = IMX_PIN_REG(MX35_PAD_SD20, 0x42c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD20__EMI_DRAM_D_20 */ 402 MX35_PAD_RESERVE102 = 375,
403 [89] = IMX_PIN_REG(MX35_PAD_SD21, 0x430, 0x0, 0, 0x0, 0), /* MX35_PAD_SD21__EMI_DRAM_D_21 */ 403 MX35_PAD_RESERVE103 = 376,
404 [90] = IMX_PIN_REG(MX35_PAD_SD22, 0x434, 0x0, 0, 0x0, 0), /* MX35_PAD_SD22__EMI_DRAM_D_22 */ 404 MX35_PAD_RESERVE104 = 377,
405 [91] = IMX_PIN_REG(MX35_PAD_SD23, 0x438, 0x0, 0, 0x0, 0), /* MX35_PAD_SD23__EMI_DRAM_D_23 */ 405 MX35_PAD_RESERVE105 = 378,
406 [92] = IMX_PIN_REG(MX35_PAD_SD24, 0x43c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD24__EMI_DRAM_D_24 */ 406 MX35_PAD_RTCK = 379,
407 [93] = IMX_PIN_REG(MX35_PAD_SD25, 0x440, 0x0, 0, 0x0, 0), /* MX35_PAD_SD25__EMI_DRAM_D_25 */ 407 MX35_PAD_TCK = 380,
408 [94] = IMX_PIN_REG(MX35_PAD_SD26, 0x444, 0x0, 0, 0x0, 0), /* MX35_PAD_SD26__EMI_DRAM_D_26 */ 408 MX35_PAD_TMS = 381,
409 [95] = IMX_PIN_REG(MX35_PAD_SD27, 0x448, 0x0, 0, 0x0, 0), /* MX35_PAD_SD27__EMI_DRAM_D_27 */ 409 MX35_PAD_TDI = 382,
410 [96] = IMX_PIN_REG(MX35_PAD_SD28, 0x44c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD28__EMI_DRAM_D_28 */ 410 MX35_PAD_TDO = 383,
411 [97] = IMX_PIN_REG(MX35_PAD_SD29, 0x450, 0x0, 0, 0x0, 0), /* MX35_PAD_SD29__EMI_DRAM_D_29 */ 411 MX35_PAD_TRSTB = 384,
412 [98] = IMX_PIN_REG(MX35_PAD_SD30, 0x454, 0x0, 0, 0x0, 0), /* MX35_PAD_SD30__EMI_DRAM_D_30 */ 412 MX35_PAD_DE_B = 385,
413 [99] = IMX_PIN_REG(MX35_PAD_SD31, 0x458, 0x0, 0, 0x0, 0), /* MX35_PAD_SD31__EMI_DRAM_D_31 */ 413 MX35_PAD_SJC_MOD = 386,
414 [100] = IMX_PIN_REG(MX35_PAD_DQM0, 0x45c, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM0__EMI_DRAM_DQM_0 */ 414 MX35_PAD_RESERVE106 = 387,
415 [101] = IMX_PIN_REG(MX35_PAD_DQM1, 0x460, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM1__EMI_DRAM_DQM_1 */ 415 MX35_PAD_RESERVE107 = 388,
416 [102] = IMX_PIN_REG(MX35_PAD_DQM2, 0x464, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM2__EMI_DRAM_DQM_2 */ 416 MX35_PAD_RESERVE108 = 389,
417 [103] = IMX_PIN_REG(MX35_PAD_DQM3, 0x468, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM3__EMI_DRAM_DQM_3 */ 417 MX35_PAD_RESERVE109 = 390,
418 [104] = IMX_PIN_REG(MX35_PAD_EB0, 0x46c, 0x094, 0, 0x0, 0), /* MX35_PAD_EB0__EMI_EIM_EB0_B */ 418 MX35_PAD_RESERVE110 = 391,
419 [105] = IMX_PIN_REG(MX35_PAD_EB1, 0x470, 0x098, 0, 0x0, 0), /* MX35_PAD_EB1__EMI_EIM_EB1_B */ 419 MX35_PAD_RESERVE111 = 392,
420 [106] = IMX_PIN_REG(MX35_PAD_OE, 0x474, 0x09c, 0, 0x0, 0), /* MX35_PAD_OE__EMI_EIM_OE */ 420 MX35_PAD_RESERVE112 = 393,
421 [107] = IMX_PIN_REG(MX35_PAD_CS0, 0x478, 0x0a0, 0, 0x0, 0), /* MX35_PAD_CS0__EMI_EIM_CS0 */ 421 MX35_PAD_RESERVE113 = 394,
422 [108] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 0, 0x0, 0), /* MX35_PAD_CS1__EMI_EIM_CS1 */ 422 MX35_PAD_RESERVE114 = 395,
423 [109] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 3, 0x0, 0), /* MX35_PAD_CS1__EMI_NANDF_CE3 */ 423 MX35_PAD_RESERVE115 = 396,
424 [110] = IMX_PIN_REG(MX35_PAD_CS2, 0x480, 0x0a8, 0, 0x0, 0), /* MX35_PAD_CS2__EMI_EIM_CS2 */ 424 MX35_PAD_RESERVE116 = 397,
425 [111] = IMX_PIN_REG(MX35_PAD_CS3, 0x484, 0x0ac, 0, 0x0, 0), /* MX35_PAD_CS3__EMI_EIM_CS3 */ 425 MX35_PAD_RESERVE117 = 398,
426 [112] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 0, 0x0, 0), /* MX35_PAD_CS4__EMI_EIM_CS4 */ 426 MX35_PAD_RESERVE118 = 399,
427 [113] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 1, 0x800, 0), /* MX35_PAD_CS4__EMI_DTACK_B */ 427 MX35_PAD_RESERVE119 = 400,
428 [114] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 3, 0x0, 0), /* MX35_PAD_CS4__EMI_NANDF_CE1 */ 428 MX35_PAD_RESERVE120 = 401,
429 [115] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 5, 0x83c, 0), /* MX35_PAD_CS4__GPIO1_20 */ 429 MX35_PAD_RESERVE121 = 402,
430 [116] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 0, 0x0, 0), /* MX35_PAD_CS5__EMI_EIM_CS5 */ 430 MX35_PAD_RESERVE122 = 403,
431 [117] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 1, 0x7f8, 0), /* MX35_PAD_CS5__CSPI2_SS2 */ 431 MX35_PAD_RESERVE123 = 404,
432 [118] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 2, 0x7d8, 1), /* MX35_PAD_CS5__CSPI1_SS2 */ 432 MX35_PAD_RESERVE124 = 405,
433 [119] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 3, 0x0, 0), /* MX35_PAD_CS5__EMI_NANDF_CE2 */ 433 MX35_PAD_RESERVE125 = 406,
434 [120] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 5, 0x840, 0), /* MX35_PAD_CS5__GPIO1_21 */ 434 MX35_PAD_RESERVE126 = 407,
435 [121] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 0, 0x0, 0), /* MX35_PAD_NF_CE0__EMI_NANDF_CE0 */ 435 MX35_PAD_RESERVE127 = 408,
436 [122] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 5, 0x844, 0), /* MX35_PAD_NF_CE0__GPIO1_22 */ 436 MX35_PAD_RESERVE128 = 409,
437 [123] = IMX_PIN_REG(MX35_PAD_ECB, 0x494, 0x0, 0, 0x0, 0), /* MX35_PAD_ECB__EMI_EIM_ECB */ 437 MX35_PAD_RESERVE129 = 410,
438 [124] = IMX_PIN_REG(MX35_PAD_LBA, 0x498, 0x0bc, 0, 0x0, 0), /* MX35_PAD_LBA__EMI_EIM_LBA */ 438 MX35_PAD_RESERVE130 = 411,
439 [125] = IMX_PIN_REG(MX35_PAD_BCLK, 0x49c, 0x0c0, 0, 0x0, 0), /* MX35_PAD_BCLK__EMI_EIM_BCLK */ 439 MX35_PAD_RESERVE131 = 412,
440 [126] = IMX_PIN_REG(MX35_PAD_RW, 0x4a0, 0x0c4, 0, 0x0, 0), /* MX35_PAD_RW__EMI_EIM_RW */ 440 MX35_PAD_RESERVE132 = 413,
441 [127] = IMX_PIN_REG(MX35_PAD_RAS, 0x4a4, 0x0, 0, 0x0, 0), /* MX35_PAD_RAS__EMI_DRAM_RAS */ 441 MX35_PAD_RESERVE133 = 414,
442 [128] = IMX_PIN_REG(MX35_PAD_CAS, 0x4a8, 0x0, 0, 0x0, 0), /* MX35_PAD_CAS__EMI_DRAM_CAS */ 442 MX35_PAD_RESERVE134 = 415,
443 [129] = IMX_PIN_REG(MX35_PAD_SDWE, 0x4ac, 0x0, 0, 0x0, 0), /* MX35_PAD_SDWE__EMI_DRAM_SDWE */ 443 MX35_PAD_RESERVE135 = 416,
444 [130] = IMX_PIN_REG(MX35_PAD_SDCKE0, 0x4b0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 */ 444 MX35_PAD_RESERVE136 = 417,
445 [131] = IMX_PIN_REG(MX35_PAD_SDCKE1, 0x4b4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 */ 445 MX35_PAD_RESERVE137 = 418,
446 [132] = IMX_PIN_REG(MX35_PAD_SDCLK, 0x4b8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCLK__EMI_DRAM_SDCLK */ 446 MX35_PAD_RESERVE138 = 419,
447 [133] = IMX_PIN_REG(MX35_PAD_SDQS0, 0x4bc, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 */ 447 MX35_PAD_RESERVE139 = 420,
448 [134] = IMX_PIN_REG(MX35_PAD_SDQS1, 0x4c0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 */ 448 MX35_PAD_RESERVE140 = 421,
449 [135] = IMX_PIN_REG(MX35_PAD_SDQS2, 0x4c4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 */ 449 MX35_PAD_RESERVE141 = 422,
450 [136] = IMX_PIN_REG(MX35_PAD_SDQS3, 0x4c8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 */ 450 MX35_PAD_RESERVE142 = 423,
451 [137] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 0, 0x0, 0), /* MX35_PAD_NFWE_B__EMI_NANDF_WE_B */ 451 MX35_PAD_RESERVE143 = 424,
452 [138] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 1, 0x9d8, 0), /* MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 */ 452 MX35_PAD_RESERVE144 = 425,
453 [139] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 2, 0x924, 0), /* MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC */ 453 MX35_PAD_RESERVE145 = 426,
454 [140] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 5, 0x88c, 0), /* MX35_PAD_NFWE_B__GPIO2_18 */ 454 MX35_PAD_RESERVE146 = 427,
455 [141] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 7, 0x0, 0), /* MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 */ 455 MX35_PAD_RESERVE147 = 428,
456 [142] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 0, 0x0, 0), /* MX35_PAD_NFRE_B__EMI_NANDF_RE_B */ 456 MX35_PAD_RESERVE148 = 429,
457 [143] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 1, 0x9ec, 0), /* MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR */ 457 MX35_PAD_RESERVE149 = 430,
458 [144] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 2, 0x0, 0), /* MX35_PAD_NFRE_B__IPU_DISPB_BCLK */ 458 MX35_PAD_RESERVE150 = 431,
459 [145] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 5, 0x890, 0), /* MX35_PAD_NFRE_B__GPIO2_19 */ 459 MX35_PAD_RESERVE151 = 432,
460 [146] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 7, 0x0, 0), /* MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 */ 460 MX35_PAD_RESERVE152 = 433,
461 [147] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 0, 0x0, 0), /* MX35_PAD_NFALE__EMI_NANDF_ALE */ 461 MX35_PAD_RESERVE153 = 434,
462 [148] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 1, 0x0, 0), /* MX35_PAD_NFALE__USB_TOP_USBH2_STP */ 462 MX35_PAD_RESERVE154 = 435,
463 [149] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 2, 0x0, 0), /* MX35_PAD_NFALE__IPU_DISPB_CS0 */ 463 MX35_PAD_RESERVE155 = 436,
464 [150] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 5, 0x898, 0), /* MX35_PAD_NFALE__GPIO2_20 */ 464 MX35_PAD_RESERVE156 = 437,
465 [151] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 7, 0x0, 0), /* MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 */ 465 MX35_PAD_RESERVE157 = 438,
466 [152] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 0, 0x0, 0), /* MX35_PAD_NFCLE__EMI_NANDF_CLE */ 466 MX35_PAD_RESERVE158 = 439,
467 [153] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 1, 0x9f0, 0), /* MX35_PAD_NFCLE__USB_TOP_USBH2_NXT */ 467 MX35_PAD_RESERVE159 = 440,
468 [154] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 2, 0x0, 0), /* MX35_PAD_NFCLE__IPU_DISPB_PAR_RS */ 468 MX35_PAD_RESERVE160 = 441,
469 [155] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 5, 0x89c, 0), /* MX35_PAD_NFCLE__GPIO2_21 */ 469 MX35_PAD_RESERVE161 = 442,
470 [156] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 7, 0x0, 0), /* MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 */ 470 MX35_PAD_RESERVE162 = 443,
471 [157] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 0, 0x0, 0), /* MX35_PAD_NFWP_B__EMI_NANDF_WP_B */ 471 MX35_PAD_RESERVE163 = 444,
472 [158] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 1, 0x9e8, 0), /* MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 */ 472 MX35_PAD_RESERVE164 = 445,
473 [159] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 2, 0x0, 0), /* MX35_PAD_NFWP_B__IPU_DISPB_WR */ 473 MX35_PAD_RESERVE165 = 446,
474 [160] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 5, 0x8a0, 0), /* MX35_PAD_NFWP_B__GPIO2_22 */ 474 MX35_PAD_RESERVE166 = 447,
475 [161] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 7, 0x0, 0), /* MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL */ 475 MX35_PAD_RESERVE167 = 448,
476 [162] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 0, 0x0, 0), /* MX35_PAD_NFRB__EMI_NANDF_RB */ 476 MX35_PAD_RESERVE168 = 449,
477 [163] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 2, 0x0, 0), /* MX35_PAD_NFRB__IPU_DISPB_RD */ 477 MX35_PAD_RESERVE169 = 450,
478 [164] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 5, 0x8a4, 0), /* MX35_PAD_NFRB__GPIO2_23 */ 478 MX35_PAD_RESERVE170 = 451,
479 [165] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 7, 0x0, 0), /* MX35_PAD_NFRB__ARM11P_TOP_TRCLK */ 479 MX35_PAD_RESERVE171 = 452,
480 [166] = IMX_PIN_REG(MX35_PAD_D15, 0x4e4, 0x0, 0, 0x0, 0), /* MX35_PAD_D15__EMI_EIM_D_15 */ 480 MX35_PAD_RESERVE172 = 453,
481 [167] = IMX_PIN_REG(MX35_PAD_D14, 0x4e8, 0x0, 0, 0x0, 0), /* MX35_PAD_D14__EMI_EIM_D_14 */ 481 MX35_PAD_RESERVE173 = 454,
482 [168] = IMX_PIN_REG(MX35_PAD_D13, 0x4ec, 0x0, 0, 0x0, 0), /* MX35_PAD_D13__EMI_EIM_D_13 */ 482 MX35_PAD_RESERVE174 = 455,
483 [169] = IMX_PIN_REG(MX35_PAD_D12, 0x4f0, 0x0, 0, 0x0, 0), /* MX35_PAD_D12__EMI_EIM_D_12 */ 483 MX35_PAD_RESERVE175 = 456,
484 [170] = IMX_PIN_REG(MX35_PAD_D11, 0x4f4, 0x0, 0, 0x0, 0), /* MX35_PAD_D11__EMI_EIM_D_11 */ 484 MX35_PAD_RESERVE176 = 457,
485 [171] = IMX_PIN_REG(MX35_PAD_D10, 0x4f8, 0x0, 0, 0x0, 0), /* MX35_PAD_D10__EMI_EIM_D_10 */ 485 MX35_PAD_RESERVE177 = 458,
486 [172] = IMX_PIN_REG(MX35_PAD_D9, 0x4fc, 0x0, 0, 0x0, 0), /* MX35_PAD_D9__EMI_EIM_D_9 */ 486 MX35_PAD_RESERVE178 = 459,
487 [173] = IMX_PIN_REG(MX35_PAD_D8, 0x500, 0x0, 0, 0x0, 0), /* MX35_PAD_D8__EMI_EIM_D_8 */ 487 MX35_PAD_RESERVE179 = 460,
488 [174] = IMX_PIN_REG(MX35_PAD_D7, 0x504, 0x0, 0, 0x0, 0), /* MX35_PAD_D7__EMI_EIM_D_7 */ 488 MX35_PAD_RESERVE180 = 461,
489 [175] = IMX_PIN_REG(MX35_PAD_D6, 0x508, 0x0, 0, 0x0, 0), /* MX35_PAD_D6__EMI_EIM_D_6 */ 489 MX35_PAD_RESERVE181 = 462,
490 [176] = IMX_PIN_REG(MX35_PAD_D5, 0x50c, 0x0, 0, 0x0, 0), /* MX35_PAD_D5__EMI_EIM_D_5 */ 490 MX35_PAD_RESERVE182 = 463,
491 [177] = IMX_PIN_REG(MX35_PAD_D4, 0x510, 0x0, 0, 0x0, 0), /* MX35_PAD_D4__EMI_EIM_D_4 */ 491 MX35_PAD_RESERVE183 = 464,
492 [178] = IMX_PIN_REG(MX35_PAD_D3, 0x514, 0x0, 0, 0x0, 0), /* MX35_PAD_D3__EMI_EIM_D_3 */ 492 MX35_PAD_RESERVE184 = 465,
493 [179] = IMX_PIN_REG(MX35_PAD_D2, 0x518, 0x0, 0, 0x0, 0), /* MX35_PAD_D2__EMI_EIM_D_2 */ 493 MX35_PAD_RESERVE185 = 466,
494 [180] = IMX_PIN_REG(MX35_PAD_D1, 0x51c, 0x0, 0, 0x0, 0), /* MX35_PAD_D1__EMI_EIM_D_1 */ 494 MX35_PAD_RESERVE186 = 467,
495 [181] = IMX_PIN_REG(MX35_PAD_D0, 0x520, 0x0, 0, 0x0, 0), /* MX35_PAD_D0__EMI_EIM_D_0 */ 495 MX35_PAD_RESERVE187 = 468,
496 [182] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 0, 0x0, 0), /* MX35_PAD_CSI_D8__IPU_CSI_D_8 */ 496 MX35_PAD_RESERVE188 = 469,
497 [183] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 1, 0x950, 0), /* MX35_PAD_CSI_D8__KPP_COL_0 */ 497 MX35_PAD_RESERVE189 = 470,
498 [184] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 5, 0x83c, 1), /* MX35_PAD_CSI_D8__GPIO1_20 */ 498 MX35_PAD_RESERVE190 = 471,
499 [185] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 7, 0x0, 0), /* MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 */ 499 MX35_PAD_RESERVE191 = 472,
500 [186] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 0, 0x0, 0), /* MX35_PAD_CSI_D9__IPU_CSI_D_9 */ 500 MX35_PAD_RESERVE192 = 473,
501 [187] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 1, 0x954, 0), /* MX35_PAD_CSI_D9__KPP_COL_1 */ 501 MX35_PAD_RESERVE193 = 474,
502 [188] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 5, 0x840, 1), /* MX35_PAD_CSI_D9__GPIO1_21 */ 502 MX35_PAD_RESERVE194 = 475,
503 [189] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 7, 0x0, 0), /* MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 */ 503 MX35_PAD_RESERVE195 = 476,
504 [190] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 0, 0x0, 0), /* MX35_PAD_CSI_D10__IPU_CSI_D_10 */ 504 MX35_PAD_RESERVE196 = 477,
505 [191] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 1, 0x958, 0), /* MX35_PAD_CSI_D10__KPP_COL_2 */ 505 MX35_PAD_RESERVE197 = 478,
506 [192] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 5, 0x844, 1), /* MX35_PAD_CSI_D10__GPIO1_22 */ 506 MX35_PAD_RESERVE198 = 479,
507 [193] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 7, 0x0, 0), /* MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 */ 507 MX35_PAD_RESERVE199 = 480,
508 [194] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 0, 0x0, 0), /* MX35_PAD_CSI_D11__IPU_CSI_D_11 */ 508 MX35_PAD_RESERVE200 = 481,
509 [195] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 1, 0x95c, 0), /* MX35_PAD_CSI_D11__KPP_COL_3 */ 509 MX35_PAD_RESERVE201 = 482,
510 [196] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 5, 0x0, 0), /* MX35_PAD_CSI_D11__GPIO1_23 */ 510 MX35_PAD_EXT_ARMCLK = 483,
511 [197] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 0, 0x0, 0), /* MX35_PAD_CSI_D12__IPU_CSI_D_12 */ 511 MX35_PAD_TEST_MODE = 484,
512 [198] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 1, 0x970, 0), /* MX35_PAD_CSI_D12__KPP_ROW_0 */
513 [199] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 5, 0x0, 0), /* MX35_PAD_CSI_D12__GPIO1_24 */
514 [200] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 0, 0x0, 0), /* MX35_PAD_CSI_D13__IPU_CSI_D_13 */
515 [201] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 1, 0x974, 0), /* MX35_PAD_CSI_D13__KPP_ROW_1 */
516 [202] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 5, 0x0, 0), /* MX35_PAD_CSI_D13__GPIO1_25 */
517 [203] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 0, 0x0, 0), /* MX35_PAD_CSI_D14__IPU_CSI_D_14 */
518 [204] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 1, 0x978, 0), /* MX35_PAD_CSI_D14__KPP_ROW_2 */
519 [205] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 5, 0x0, 0), /* MX35_PAD_CSI_D14__GPIO1_26 */
520 [206] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 0, 0x97c, 0), /* MX35_PAD_CSI_D15__IPU_CSI_D_15 */
521 [207] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 1, 0x0, 0), /* MX35_PAD_CSI_D15__KPP_ROW_3 */
522 [208] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 5, 0x0, 0), /* MX35_PAD_CSI_D15__GPIO1_27 */
523 [209] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 0, 0x0, 0), /* MX35_PAD_CSI_MCLK__IPU_CSI_MCLK */
524 [210] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 5, 0x0, 0), /* MX35_PAD_CSI_MCLK__GPIO1_28 */
525 [211] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 0, 0x0, 0), /* MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC */
526 [212] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 5, 0x0, 0), /* MX35_PAD_CSI_VSYNC__GPIO1_29 */
527 [213] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 0, 0x0, 0), /* MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC */
528 [214] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 5, 0x0, 0), /* MX35_PAD_CSI_HSYNC__GPIO1_30 */
529 [215] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 0, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK */
530 [216] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 5, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__GPIO1_31 */
531 [217] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 0, 0x0, 0), /* MX35_PAD_I2C1_CLK__I2C1_SCL */
532 [218] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 5, 0x8a8, 0), /* MX35_PAD_I2C1_CLK__GPIO2_24 */
533 [219] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 6, 0x0, 0), /* MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK */
534 [220] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 0, 0x0, 0), /* MX35_PAD_I2C1_DAT__I2C1_SDA */
535 [221] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 5, 0x8ac, 0), /* MX35_PAD_I2C1_DAT__GPIO2_25 */
536 [222] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 0, 0x0, 0), /* MX35_PAD_I2C2_CLK__I2C2_SCL */
537 [223] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 1, 0x0, 0), /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
538 [224] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 2, 0x0, 0), /* MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR */
539 [225] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 5, 0x8b0, 0), /* MX35_PAD_I2C2_CLK__GPIO2_26 */
540 [226] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 6, 0x0, 0), /* MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 */
541 [227] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 0, 0x0, 0), /* MX35_PAD_I2C2_DAT__I2C2_SDA */
542 [228] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 1, 0x7c8, 0), /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
543 [229] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 2, 0x9f4, 0), /* MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC */
544 [230] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 5, 0x8b4, 0), /* MX35_PAD_I2C2_DAT__GPIO2_27 */
545 [231] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 6, 0x0, 0), /* MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 */
546 [232] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 0, 0x0, 0), /* MX35_PAD_STXD4__AUDMUX_AUD4_TXD */
547 [233] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 5, 0x8b8, 0), /* MX35_PAD_STXD4__GPIO2_28 */
548 [234] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 7, 0x0, 0), /* MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 */
549 [235] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 0, 0x0, 0), /* MX35_PAD_SRXD4__AUDMUX_AUD4_RXD */
550 [236] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 5, 0x8bc, 0), /* MX35_PAD_SRXD4__GPIO2_29 */
551 [237] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 7, 0x0, 0), /* MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 */
552 [238] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 0, 0x0, 0), /* MX35_PAD_SCK4__AUDMUX_AUD4_TXC */
553 [239] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 5, 0x8c4, 0), /* MX35_PAD_SCK4__GPIO2_30 */
554 [240] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 7, 0x0, 0), /* MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 */
555 [241] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 0, 0x0, 0), /* MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS */
556 [242] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 5, 0x8c8, 0), /* MX35_PAD_STXFS4__GPIO2_31 */
557 [243] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 7, 0x0, 0), /* MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 */
558 [244] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 0, 0x0, 0), /* MX35_PAD_STXD5__AUDMUX_AUD5_TXD */
559 [245] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 1, 0x0, 0), /* MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 */
560 [246] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 2, 0x7ec, 0), /* MX35_PAD_STXD5__CSPI2_MOSI */
561 [247] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 5, 0x82c, 1), /* MX35_PAD_STXD5__GPIO1_0 */
562 [248] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 7, 0x0, 0), /* MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 */
563 [249] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 0, 0x0, 0), /* MX35_PAD_SRXD5__AUDMUX_AUD5_RXD */
564 [250] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 1, 0x998, 0), /* MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 */
565 [251] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 2, 0x7e8, 0), /* MX35_PAD_SRXD5__CSPI2_MISO */
566 [252] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 5, 0x838, 1), /* MX35_PAD_SRXD5__GPIO1_1 */
567 [253] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 7, 0x0, 0), /* MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 */
568 [254] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 0, 0x0, 0), /* MX35_PAD_SCK5__AUDMUX_AUD5_TXC */
569 [255] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 1, 0x994, 0), /* MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK */
570 [256] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 2, 0x7e0, 0), /* MX35_PAD_SCK5__CSPI2_SCLK */
571 [257] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 5, 0x848, 0), /* MX35_PAD_SCK5__GPIO1_2 */
572 [258] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 7, 0x0, 0), /* MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 */
573 [259] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 0, 0x0, 0), /* MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS */
574 [260] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 2, 0x7e4, 0), /* MX35_PAD_STXFS5__CSPI2_RDY */
575 [261] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 5, 0x84c, 0), /* MX35_PAD_STXFS5__GPIO1_3 */
576 [262] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 7, 0x0, 0), /* MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 */
577 [263] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 0, 0x0, 0), /* MX35_PAD_SCKR__ESAI_SCKR */
578 [264] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 5, 0x850, 1), /* MX35_PAD_SCKR__GPIO1_4 */
579 [265] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 7, 0x0, 0), /* MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 */
580 [266] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 0, 0x0, 0), /* MX35_PAD_FSR__ESAI_FSR */
581 [267] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 5, 0x854, 1), /* MX35_PAD_FSR__GPIO1_5 */
582 [268] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 7, 0x0, 0), /* MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 */
583 [269] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 0, 0x0, 0), /* MX35_PAD_HCKR__ESAI_HCKR */
584 [270] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 1, 0x0, 0), /* MX35_PAD_HCKR__AUDMUX_AUD5_RXFS */
585 [271] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 2, 0x7f0, 0), /* MX35_PAD_HCKR__CSPI2_SS0 */
586 [272] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 3, 0x0, 0), /* MX35_PAD_HCKR__IPU_FLASH_STROBE */
587 [273] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 5, 0x858, 1), /* MX35_PAD_HCKR__GPIO1_6 */
588 [274] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 7, 0x0, 0), /* MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 */
589 [275] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 0, 0x0, 0), /* MX35_PAD_SCKT__ESAI_SCKT */
590 [276] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 5, 0x85c, 1), /* MX35_PAD_SCKT__GPIO1_7 */
591 [277] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 6, 0x930, 0), /* MX35_PAD_SCKT__IPU_CSI_D_0 */
592 [278] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 7, 0x978, 1), /* MX35_PAD_SCKT__KPP_ROW_2 */
593 [279] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 0, 0x0, 0), /* MX35_PAD_FST__ESAI_FST */
594 [280] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 5, 0x860, 1), /* MX35_PAD_FST__GPIO1_8 */
595 [281] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 6, 0x934, 0), /* MX35_PAD_FST__IPU_CSI_D_1 */
596 [282] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 7, 0x97c, 1), /* MX35_PAD_FST__KPP_ROW_3 */
597 [283] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 0, 0x0, 0), /* MX35_PAD_HCKT__ESAI_HCKT */
598 [284] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 1, 0x7a8, 0), /* MX35_PAD_HCKT__AUDMUX_AUD5_RXC */
599 [285] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 5, 0x864, 0), /* MX35_PAD_HCKT__GPIO1_9 */
600 [286] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 6, 0x938, 0), /* MX35_PAD_HCKT__IPU_CSI_D_2 */
601 [287] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 7, 0x95c, 1), /* MX35_PAD_HCKT__KPP_COL_3 */
602 [288] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 0, 0x0, 0), /* MX35_PAD_TX5_RX0__ESAI_TX5_RX0 */
603 [289] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 1, 0x0, 0), /* MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC */
604 [290] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 2, 0x7f8, 1), /* MX35_PAD_TX5_RX0__CSPI2_SS2 */
605 [291] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 3, 0x0, 0), /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
606 [292] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 4, 0x0, 0), /* MX35_PAD_TX5_RX0__UART2_DTR */
607 [293] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 5, 0x830, 0), /* MX35_PAD_TX5_RX0__GPIO1_10 */
608 [294] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 7, 0x0, 0), /* MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 */
609 [295] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 0, 0x0, 0), /* MX35_PAD_TX4_RX1__ESAI_TX4_RX1 */
610 [296] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 1, 0x0, 0), /* MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS */
611 [297] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 2, 0x7fc, 0), /* MX35_PAD_TX4_RX1__CSPI2_SS3 */
612 [298] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 3, 0x7cc, 0), /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
613 [299] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 4, 0x0, 0), /* MX35_PAD_TX4_RX1__UART2_DSR */
614 [300] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 5, 0x834, 0), /* MX35_PAD_TX4_RX1__GPIO1_11 */
615 [301] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 6, 0x93c, 0), /* MX35_PAD_TX4_RX1__IPU_CSI_D_3 */
616 [302] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 7, 0x970, 1), /* MX35_PAD_TX4_RX1__KPP_ROW_0 */
617 [303] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 0, 0x0, 0), /* MX35_PAD_TX3_RX2__ESAI_TX3_RX2 */
618 [304] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 1, 0x91c, 0), /* MX35_PAD_TX3_RX2__I2C3_SCL */
619 [305] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 3, 0x0, 0), /* MX35_PAD_TX3_RX2__EMI_NANDF_CE1 */
620 [306] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 5, 0x0, 0), /* MX35_PAD_TX3_RX2__GPIO1_12 */
621 [307] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 6, 0x940, 0), /* MX35_PAD_TX3_RX2__IPU_CSI_D_4 */
622 [308] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 7, 0x974, 1), /* MX35_PAD_TX3_RX2__KPP_ROW_1 */
623 [309] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 0, 0x0, 0), /* MX35_PAD_TX2_RX3__ESAI_TX2_RX3 */
624 [310] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 1, 0x920, 0), /* MX35_PAD_TX2_RX3__I2C3_SDA */
625 [311] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 3, 0x0, 0), /* MX35_PAD_TX2_RX3__EMI_NANDF_CE2 */
626 [312] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 5, 0x0, 0), /* MX35_PAD_TX2_RX3__GPIO1_13 */
627 [313] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 6, 0x944, 0), /* MX35_PAD_TX2_RX3__IPU_CSI_D_5 */
628 [314] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 7, 0x950, 1), /* MX35_PAD_TX2_RX3__KPP_COL_0 */
629 [315] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 0, 0x0, 0), /* MX35_PAD_TX1__ESAI_TX1 */
630 [316] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 1, 0x7d4, 1), /* MX35_PAD_TX1__CCM_PMIC_RDY */
631 [317] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 2, 0x7d8, 2), /* MX35_PAD_TX1__CSPI1_SS2 */
632 [318] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 3, 0x0, 0), /* MX35_PAD_TX1__EMI_NANDF_CE3 */
633 [319] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 4, 0x0, 0), /* MX35_PAD_TX1__UART2_RI */
634 [320] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 5, 0x0, 0), /* MX35_PAD_TX1__GPIO1_14 */
635 [321] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 6, 0x948, 0), /* MX35_PAD_TX1__IPU_CSI_D_6 */
636 [322] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 7, 0x954, 1), /* MX35_PAD_TX1__KPP_COL_1 */
637 [323] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 0, 0x0, 0), /* MX35_PAD_TX0__ESAI_TX0 */
638 [324] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 1, 0x994, 1), /* MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK */
639 [325] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 2, 0x7dc, 0), /* MX35_PAD_TX0__CSPI1_SS3 */
640 [326] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 3, 0x800, 1), /* MX35_PAD_TX0__EMI_DTACK_B */
641 [327] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 4, 0x0, 0), /* MX35_PAD_TX0__UART2_DCD */
642 [328] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 5, 0x0, 0), /* MX35_PAD_TX0__GPIO1_15 */
643 [329] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 6, 0x94c, 0), /* MX35_PAD_TX0__IPU_CSI_D_7 */
644 [330] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 7, 0x958, 1), /* MX35_PAD_TX0__KPP_COL_2 */
645 [331] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 0, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__CSPI1_MOSI */
646 [332] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 5, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__GPIO1_16 */
647 [333] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 7, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 */
648 [334] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 0, 0x0, 0), /* MX35_PAD_CSPI1_MISO__CSPI1_MISO */
649 [335] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 5, 0x0, 0), /* MX35_PAD_CSPI1_MISO__GPIO1_17 */
650 [336] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 7, 0x0, 0), /* MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 */
651 [337] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS0__CSPI1_SS0 */
652 [338] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 1, 0x990, 1), /* MX35_PAD_CSPI1_SS0__OWIRE_LINE */
653 [339] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 2, 0x7fc, 1), /* MX35_PAD_CSPI1_SS0__CSPI2_SS3 */
654 [340] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS0__GPIO1_18 */
655 [341] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 */
656 [342] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS1__CSPI1_SS1 */
657 [343] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 1, 0x0, 0), /* MX35_PAD_CSPI1_SS1__PWM_PWMO */
658 [344] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 2, 0x7d0, 1), /* MX35_PAD_CSPI1_SS1__CCM_CLK32K */
659 [345] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS1__GPIO1_19 */
660 [346] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 6, 0x0, 0), /* MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 */
661 [347] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 */
662 [348] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 0, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__CSPI1_SCLK */
663 [349] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 5, 0x904, 0), /* MX35_PAD_CSPI1_SCLK__GPIO3_4 */
664 [350] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 6, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 */
665 [351] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 7, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 */
666 [352] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 0, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY */
667 [353] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 5, 0x908, 0), /* MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 */
668 [354] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 6, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 */
669 [355] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 7, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 */
670 [356] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 0, 0x0, 0), /* MX35_PAD_RXD1__UART1_RXD_MUX */
671 [357] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 1, 0x7ec, 1), /* MX35_PAD_RXD1__CSPI2_MOSI */
672 [358] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 4, 0x960, 0), /* MX35_PAD_RXD1__KPP_COL_4 */
673 [359] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 5, 0x90c, 0), /* MX35_PAD_RXD1__GPIO3_6 */
674 [360] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 7, 0x0, 0), /* MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 */
675 [361] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 0, 0x0, 0), /* MX35_PAD_TXD1__UART1_TXD_MUX */
676 [362] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 1, 0x7e8, 1), /* MX35_PAD_TXD1__CSPI2_MISO */
677 [363] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 4, 0x964, 0), /* MX35_PAD_TXD1__KPP_COL_5 */
678 [364] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 5, 0x910, 0), /* MX35_PAD_TXD1__GPIO3_7 */
679 [365] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 7, 0x0, 0), /* MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 */
680 [366] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 0, 0x0, 0), /* MX35_PAD_RTS1__UART1_RTS */
681 [367] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 1, 0x7e0, 1), /* MX35_PAD_RTS1__CSPI2_SCLK */
682 [368] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 2, 0x91c, 1), /* MX35_PAD_RTS1__I2C3_SCL */
683 [369] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 3, 0x930, 1), /* MX35_PAD_RTS1__IPU_CSI_D_0 */
684 [370] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 4, 0x968, 0), /* MX35_PAD_RTS1__KPP_COL_6 */
685 [371] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 5, 0x914, 0), /* MX35_PAD_RTS1__GPIO3_8 */
686 [372] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 6, 0x0, 0), /* MX35_PAD_RTS1__EMI_NANDF_CE1 */
687 [373] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 7, 0x0, 0), /* MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 */
688 [374] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 0, 0x0, 0), /* MX35_PAD_CTS1__UART1_CTS */
689 [375] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 1, 0x7e4, 1), /* MX35_PAD_CTS1__CSPI2_RDY */
690 [376] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 2, 0x920, 1), /* MX35_PAD_CTS1__I2C3_SDA */
691 [377] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 3, 0x934, 1), /* MX35_PAD_CTS1__IPU_CSI_D_1 */
692 [378] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 4, 0x96c, 0), /* MX35_PAD_CTS1__KPP_COL_7 */
693 [379] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 5, 0x918, 0), /* MX35_PAD_CTS1__GPIO3_9 */
694 [380] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 6, 0x0, 0), /* MX35_PAD_CTS1__EMI_NANDF_CE2 */
695 [381] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 7, 0x0, 0), /* MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 */
696 [382] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 0, 0x0, 0), /* MX35_PAD_RXD2__UART2_RXD_MUX */
697 [383] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 4, 0x980, 0), /* MX35_PAD_RXD2__KPP_ROW_4 */
698 [384] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 5, 0x8ec, 0), /* MX35_PAD_RXD2__GPIO3_10 */
699 [385] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 0, 0x0, 0), /* MX35_PAD_TXD2__UART2_TXD_MUX */
700 [386] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 1, 0x994, 2), /* MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK */
701 [387] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 4, 0x984, 0), /* MX35_PAD_TXD2__KPP_ROW_5 */
702 [388] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 5, 0x8f0, 0), /* MX35_PAD_TXD2__GPIO3_11 */
703 [389] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 0, 0x0, 0), /* MX35_PAD_RTS2__UART2_RTS */
704 [390] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 1, 0x998, 1), /* MX35_PAD_RTS2__SPDIF_SPDIF_IN1 */
705 [391] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 2, 0x7cc, 1), /* MX35_PAD_RTS2__CAN2_RXCAN */
706 [392] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 3, 0x938, 1), /* MX35_PAD_RTS2__IPU_CSI_D_2 */
707 [393] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 4, 0x988, 0), /* MX35_PAD_RTS2__KPP_ROW_6 */
708 [394] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 5, 0x8f4, 0), /* MX35_PAD_RTS2__GPIO3_12 */
709 [395] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 6, 0x0, 0), /* MX35_PAD_RTS2__AUDMUX_AUD5_RXC */
710 [396] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 7, 0x9a0, 0), /* MX35_PAD_RTS2__UART3_RXD_MUX */
711 [397] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 0, 0x0, 0), /* MX35_PAD_CTS2__UART2_CTS */
712 [398] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 1, 0x0, 0), /* MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 */
713 [399] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 2, 0x0, 0), /* MX35_PAD_CTS2__CAN2_TXCAN */
714 [400] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 3, 0x93c, 1), /* MX35_PAD_CTS2__IPU_CSI_D_3 */
715 [401] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 4, 0x98c, 0), /* MX35_PAD_CTS2__KPP_ROW_7 */
716 [402] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 5, 0x8f8, 0), /* MX35_PAD_CTS2__GPIO3_13 */
717 [403] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 6, 0x0, 0), /* MX35_PAD_CTS2__AUDMUX_AUD5_RXFS */
718 [404] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 7, 0x0, 0), /* MX35_PAD_CTS2__UART3_TXD_MUX */
719 [405] = IMX_PIN_REG(MX35_PAD_RTCK, 0x5ec, 0x0, 0, 0x0, 0), /* MX35_PAD_RTCK__ARM11P_TOP_RTCK */
720 [406] = IMX_PIN_REG(MX35_PAD_TCK, 0x5f0, 0x0, 0, 0x0, 0), /* MX35_PAD_TCK__SJC_TCK */
721 [407] = IMX_PIN_REG(MX35_PAD_TMS, 0x5f4, 0x0, 0, 0x0, 0), /* MX35_PAD_TMS__SJC_TMS */
722 [408] = IMX_PIN_REG(MX35_PAD_TDI, 0x5f8, 0x0, 0, 0x0, 0), /* MX35_PAD_TDI__SJC_TDI */
723 [409] = IMX_PIN_REG(MX35_PAD_TDO, 0x5fc, 0x0, 0, 0x0, 0), /* MX35_PAD_TDO__SJC_TDO */
724 [410] = IMX_PIN_REG(MX35_PAD_TRSTB, 0x600, 0x0, 0, 0x0, 0), /* MX35_PAD_TRSTB__SJC_TRSTB */
725 [411] = IMX_PIN_REG(MX35_PAD_DE_B, 0x604, 0x0, 0, 0x0, 0), /* MX35_PAD_DE_B__SJC_DE_B */
726 [412] = IMX_PIN_REG(MX35_PAD_SJC_MOD, 0x608, 0x0, 0, 0x0, 0), /* MX35_PAD_SJC_MOD__SJC_MOD */
727 [413] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 0, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR */
728 [414] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 1, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR */
729 [415] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 5, 0x8fc, 0), /* MX35_PAD_USBOTG_PWR__GPIO3_14 */
730 [416] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 0, 0x0, 0), /* MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC */
731 [417] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 1, 0x9f4, 1), /* MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC */
732 [418] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 5, 0x900, 0), /* MX35_PAD_USBOTG_OC__GPIO3_15 */
733 [419] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 0, 0x0, 0), /* MX35_PAD_LD0__IPU_DISPB_DAT_0 */
734 [420] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 5, 0x868, 1), /* MX35_PAD_LD0__GPIO2_0 */
735 [421] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 6, 0x0, 0), /* MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 */
736 [422] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 0, 0x0, 0), /* MX35_PAD_LD1__IPU_DISPB_DAT_1 */
737 [423] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 5, 0x894, 0), /* MX35_PAD_LD1__GPIO2_1 */
738 [424] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 6, 0x0, 0), /* MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 */
739 [425] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 0, 0x0, 0), /* MX35_PAD_LD2__IPU_DISPB_DAT_2 */
740 [426] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 5, 0x8c0, 0), /* MX35_PAD_LD2__GPIO2_2 */
741 [427] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 6, 0x0, 0), /* MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 */
742 [428] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 0, 0x0, 0), /* MX35_PAD_LD3__IPU_DISPB_DAT_3 */
743 [429] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 5, 0x8cc, 0), /* MX35_PAD_LD3__GPIO2_3 */
744 [430] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 6, 0x0, 0), /* MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 */
745 [431] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 0, 0x0, 0), /* MX35_PAD_LD4__IPU_DISPB_DAT_4 */
746 [432] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 5, 0x8d0, 0), /* MX35_PAD_LD4__GPIO2_4 */
747 [433] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 6, 0x0, 0), /* MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 */
748 [434] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 0, 0x0, 0), /* MX35_PAD_LD5__IPU_DISPB_DAT_5 */
749 [435] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 5, 0x8d4, 0), /* MX35_PAD_LD5__GPIO2_5 */
750 [436] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 6, 0x0, 0), /* MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 */
751 [437] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 0, 0x0, 0), /* MX35_PAD_LD6__IPU_DISPB_DAT_6 */
752 [438] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 5, 0x8d8, 0), /* MX35_PAD_LD6__GPIO2_6 */
753 [439] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 6, 0x0, 0), /* MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 */
754 [440] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 0, 0x0, 0), /* MX35_PAD_LD7__IPU_DISPB_DAT_7 */
755 [441] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 5, 0x8dc, 0), /* MX35_PAD_LD7__GPIO2_7 */
756 [442] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 6, 0x0, 0), /* MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 */
757 [443] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 0, 0x0, 0), /* MX35_PAD_LD8__IPU_DISPB_DAT_8 */
758 [444] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 5, 0x8e0, 0), /* MX35_PAD_LD8__GPIO2_8 */
759 [445] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 6, 0x0, 0), /* MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 */
760 [446] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 0, 0x0, 0), /* MX35_PAD_LD9__IPU_DISPB_DAT_9 */
761 [447] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 5, 0x8e4, 0), /* MX35_PAD_LD9__GPIO2_9 */
762 [448] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 6, 0x0, 0), /* MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 */
763 [449] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 0, 0x0, 0), /* MX35_PAD_LD10__IPU_DISPB_DAT_10 */
764 [450] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 5, 0x86c, 0), /* MX35_PAD_LD10__GPIO2_10 */
765 [451] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 6, 0x0, 0), /* MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 */
766 [452] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 0, 0x0, 0), /* MX35_PAD_LD11__IPU_DISPB_DAT_11 */
767 [453] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 5, 0x870, 0), /* MX35_PAD_LD11__GPIO2_11 */
768 [454] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 6, 0x0, 0), /* MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 */
769 [455] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 7, 0x0, 0), /* MX35_PAD_LD11__ARM11P_TOP_TRACE_4 */
770 [456] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 0, 0x0, 0), /* MX35_PAD_LD12__IPU_DISPB_DAT_12 */
771 [457] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 5, 0x874, 0), /* MX35_PAD_LD12__GPIO2_12 */
772 [458] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 6, 0x0, 0), /* MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 */
773 [459] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 7, 0x0, 0), /* MX35_PAD_LD12__ARM11P_TOP_TRACE_5 */
774 [460] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 0, 0x0, 0), /* MX35_PAD_LD13__IPU_DISPB_DAT_13 */
775 [461] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 5, 0x878, 0), /* MX35_PAD_LD13__GPIO2_13 */
776 [462] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 6, 0x0, 0), /* MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 */
777 [463] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 7, 0x0, 0), /* MX35_PAD_LD13__ARM11P_TOP_TRACE_6 */
778 [464] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 0, 0x0, 0), /* MX35_PAD_LD14__IPU_DISPB_DAT_14 */
779 [465] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 5, 0x87c, 0), /* MX35_PAD_LD14__GPIO2_14 */
780 [466] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 6, 0x0, 0), /* MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 */
781 [467] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 7, 0x0, 0), /* MX35_PAD_LD14__ARM11P_TOP_TRACE_7 */
782 [468] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 0, 0x0, 0), /* MX35_PAD_LD15__IPU_DISPB_DAT_15 */
783 [469] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 5, 0x880, 0), /* MX35_PAD_LD15__GPIO2_15 */
784 [470] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 6, 0x0, 0), /* MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 */
785 [471] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 7, 0x0, 0), /* MX35_PAD_LD15__ARM11P_TOP_TRACE_8 */
786 [472] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 0, 0x0, 0), /* MX35_PAD_LD16__IPU_DISPB_DAT_16 */
787 [473] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 2, 0x928, 0), /* MX35_PAD_LD16__IPU_DISPB_D12_VSYNC */
788 [474] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 5, 0x884, 0), /* MX35_PAD_LD16__GPIO2_16 */
789 [475] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 6, 0x0, 0), /* MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 */
790 [476] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 7, 0x0, 0), /* MX35_PAD_LD16__ARM11P_TOP_TRACE_9 */
791 [477] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 0, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_DAT_17 */
792 [478] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 2, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_CS2 */
793 [479] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 5, 0x888, 0), /* MX35_PAD_LD17__GPIO2_17 */
794 [480] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 6, 0x0, 0), /* MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 */
795 [481] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 7, 0x0, 0), /* MX35_PAD_LD17__ARM11P_TOP_TRACE_10 */
796 [482] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 0, 0x0, 0), /* MX35_PAD_LD18__IPU_DISPB_DAT_18 */
797 [483] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 1, 0x924, 1), /* MX35_PAD_LD18__IPU_DISPB_D0_VSYNC */
798 [484] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 2, 0x928, 1), /* MX35_PAD_LD18__IPU_DISPB_D12_VSYNC */
799 [485] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 3, 0x818, 0), /* MX35_PAD_LD18__ESDHC3_CMD */
800 [486] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 4, 0x9b0, 0), /* MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 */
801 [487] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 5, 0x0, 0), /* MX35_PAD_LD18__GPIO3_24 */
802 [488] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 6, 0x0, 0), /* MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 */
803 [489] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 7, 0x0, 0), /* MX35_PAD_LD18__ARM11P_TOP_TRACE_11 */
804 [490] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 0, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_DAT_19 */
805 [491] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 1, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_BCLK */
806 [492] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 2, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_CS1 */
807 [493] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 3, 0x814, 0), /* MX35_PAD_LD19__ESDHC3_CLK */
808 [494] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 4, 0x9c4, 0), /* MX35_PAD_LD19__USB_TOP_USBOTG_DIR */
809 [495] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 5, 0x0, 0), /* MX35_PAD_LD19__GPIO3_25 */
810 [496] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 6, 0x0, 0), /* MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 */
811 [497] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 7, 0x0, 0), /* MX35_PAD_LD19__ARM11P_TOP_TRACE_12 */
812 [498] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 0, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_DAT_20 */
813 [499] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 1, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_CS0 */
814 [500] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 2, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_SD_CLK */
815 [501] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 3, 0x81c, 0), /* MX35_PAD_LD20__ESDHC3_DAT0 */
816 [502] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 5, 0x0, 0), /* MX35_PAD_LD20__GPIO3_26 */
817 [503] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 6, 0x0, 0), /* MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 */
818 [504] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 7, 0x0, 0), /* MX35_PAD_LD20__ARM11P_TOP_TRACE_13 */
819 [505] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 0, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_DAT_21 */
820 [506] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 1, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_PAR_RS */
821 [507] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 2, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_SER_RS */
822 [508] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 3, 0x820, 0), /* MX35_PAD_LD21__ESDHC3_DAT1 */
823 [509] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 4, 0x0, 0), /* MX35_PAD_LD21__USB_TOP_USBOTG_STP */
824 [510] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 5, 0x0, 0), /* MX35_PAD_LD21__GPIO3_27 */
825 [511] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 6, 0x0, 0), /* MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL */
826 [512] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 7, 0x0, 0), /* MX35_PAD_LD21__ARM11P_TOP_TRACE_14 */
827 [513] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 0, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_DAT_22 */
828 [514] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 1, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_WR */
829 [515] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 2, 0x92c, 0), /* MX35_PAD_LD22__IPU_DISPB_SD_D_I */
830 [516] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 3, 0x824, 0), /* MX35_PAD_LD22__ESDHC3_DAT2 */
831 [517] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 4, 0x9c8, 0), /* MX35_PAD_LD22__USB_TOP_USBOTG_NXT */
832 [518] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 5, 0x0, 0), /* MX35_PAD_LD22__GPIO3_28 */
833 [519] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 6, 0x0, 0), /* MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR */
834 [520] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 7, 0x0, 0), /* MX35_PAD_LD22__ARM11P_TOP_TRCTL */
835 [521] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 0, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_DAT_23 */
836 [522] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 1, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_RD */
837 [523] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 2, 0x92c, 1), /* MX35_PAD_LD23__IPU_DISPB_SD_D_IO */
838 [524] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 3, 0x828, 0), /* MX35_PAD_LD23__ESDHC3_DAT3 */
839 [525] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 4, 0x9c0, 0), /* MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 */
840 [526] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 5, 0x0, 0), /* MX35_PAD_LD23__GPIO3_29 */
841 [527] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 6, 0x0, 0), /* MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS */
842 [528] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 7, 0x0, 0), /* MX35_PAD_LD23__ARM11P_TOP_TRCLK */
843 [529] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 0, 0x0, 0), /* MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC */
844 [530] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 2, 0x92c, 2), /* MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO */
845 [531] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 5, 0x0, 0), /* MX35_PAD_D3_HSYNC__GPIO3_30 */
846 [532] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 6, 0x0, 0), /* MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE */
847 [533] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 7, 0x0, 0), /* MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 */
848 [534] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 0, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK */
849 [535] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 2, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK */
850 [536] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 5, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__GPIO3_31 */
851 [537] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 6, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 */
852 [538] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 7, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 */
853 [539] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 0, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY */
854 [540] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 2, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O */
855 [541] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 5, 0x82c, 2), /* MX35_PAD_D3_DRDY__GPIO1_0 */
856 [542] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 6, 0x0, 0), /* MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 */
857 [543] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 7, 0x0, 0), /* MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 */
858 [544] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 0, 0x0, 0), /* MX35_PAD_CONTRAST__IPU_DISPB_CONTR */
859 [545] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 5, 0x838, 2), /* MX35_PAD_CONTRAST__GPIO1_1 */
860 [546] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 6, 0x0, 0), /* MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 */
861 [547] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 7, 0x0, 0), /* MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 */
862 [548] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 0, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC */
863 [549] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 2, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 */
864 [550] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 5, 0x848, 1), /* MX35_PAD_D3_VSYNC__GPIO1_2 */
865 [551] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 6, 0x0, 0), /* MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD */
866 [552] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 7, 0x0, 0), /* MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 */
867 [553] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 0, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_D3_REV */
868 [554] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 2, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_SER_RS */
869 [555] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 5, 0x84c, 1), /* MX35_PAD_D3_REV__GPIO1_3 */
870 [556] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 6, 0x0, 0), /* MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB */
871 [557] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 7, 0x0, 0), /* MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 */
872 [558] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 0, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS */
873 [559] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 2, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_CS2 */
874 [560] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 5, 0x850, 2), /* MX35_PAD_D3_CLS__GPIO1_4 */
875 [561] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 6, 0x0, 0), /* MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 */
876 [562] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 7, 0x0, 0), /* MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 */
877 [563] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 0, 0x0, 0), /* MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL */
878 [564] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 2, 0x928, 2), /* MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC */
879 [565] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 5, 0x854, 2), /* MX35_PAD_D3_SPL__GPIO1_5 */
880 [566] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 6, 0x0, 0), /* MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 */
881 [567] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 7, 0x0, 0), /* MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 */
882 [568] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 0, 0x0, 0), /* MX35_PAD_SD1_CMD__ESDHC1_CMD */
883 [569] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 1, 0x0, 0), /* MX35_PAD_SD1_CMD__MSHC_SCLK */
884 [570] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 3, 0x924, 2), /* MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC */
885 [571] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 4, 0x9b4, 0), /* MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 */
886 [572] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 5, 0x858, 2), /* MX35_PAD_SD1_CMD__GPIO1_6 */
887 [573] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 7, 0x0, 0), /* MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL */
888 [574] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 0, 0x0, 0), /* MX35_PAD_SD1_CLK__ESDHC1_CLK */
889 [575] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 1, 0x0, 0), /* MX35_PAD_SD1_CLK__MSHC_BS */
890 [576] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 3, 0x0, 0), /* MX35_PAD_SD1_CLK__IPU_DISPB_BCLK */
891 [577] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 4, 0x9b8, 0), /* MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 */
892 [578] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 5, 0x85c, 2), /* MX35_PAD_SD1_CLK__GPIO1_7 */
893 [579] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 7, 0x0, 0), /* MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK */
894 [580] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 0, 0x0, 0), /* MX35_PAD_SD1_DATA0__ESDHC1_DAT0 */
895 [581] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 1, 0x0, 0), /* MX35_PAD_SD1_DATA0__MSHC_DATA_0 */
896 [582] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 3, 0x0, 0), /* MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 */
897 [583] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 4, 0x9bc, 0), /* MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 */
898 [584] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 5, 0x860, 2), /* MX35_PAD_SD1_DATA0__GPIO1_8 */
899 [585] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 7, 0x0, 0), /* MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 */
900 [586] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 0, 0x0, 0), /* MX35_PAD_SD1_DATA1__ESDHC1_DAT1 */
901 [587] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 1, 0x0, 0), /* MX35_PAD_SD1_DATA1__MSHC_DATA_1 */
902 [588] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 3, 0x0, 0), /* MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS */
903 [589] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 4, 0x9a4, 0), /* MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 */
904 [590] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 5, 0x864, 1), /* MX35_PAD_SD1_DATA1__GPIO1_9 */
905 [591] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 7, 0x0, 0), /* MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 */
906 [592] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 0, 0x0, 0), /* MX35_PAD_SD1_DATA2__ESDHC1_DAT2 */
907 [593] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 1, 0x0, 0), /* MX35_PAD_SD1_DATA2__MSHC_DATA_2 */
908 [594] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 3, 0x0, 0), /* MX35_PAD_SD1_DATA2__IPU_DISPB_WR */
909 [595] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 4, 0x9a8, 0), /* MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 */
910 [596] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 5, 0x830, 1), /* MX35_PAD_SD1_DATA2__GPIO1_10 */
911 [597] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 7, 0x0, 0), /* MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 */
912 [598] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 0, 0x0, 0), /* MX35_PAD_SD1_DATA3__ESDHC1_DAT3 */
913 [599] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 1, 0x0, 0), /* MX35_PAD_SD1_DATA3__MSHC_DATA_3 */
914 [600] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 3, 0x0, 0), /* MX35_PAD_SD1_DATA3__IPU_DISPB_RD */
915 [601] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 4, 0x9ac, 0), /* MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 */
916 [602] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 5, 0x834, 1), /* MX35_PAD_SD1_DATA3__GPIO1_11 */
917 [603] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 7, 0x0, 0), /* MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 */
918 [604] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 0, 0x0, 0), /* MX35_PAD_SD2_CMD__ESDHC2_CMD */
919 [605] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 1, 0x91c, 2), /* MX35_PAD_SD2_CMD__I2C3_SCL */
920 [606] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 2, 0x804, 0), /* MX35_PAD_SD2_CMD__ESDHC1_DAT4 */
921 [607] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 3, 0x938, 2), /* MX35_PAD_SD2_CMD__IPU_CSI_D_2 */
922 [608] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 4, 0x9dc, 0), /* MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 */
923 [609] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 5, 0x868, 2), /* MX35_PAD_SD2_CMD__GPIO2_0 */
924 [610] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 6, 0x0, 0), /* MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 */
925 [611] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 7, 0x928, 3), /* MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC */
926 [612] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 0, 0x0, 0), /* MX35_PAD_SD2_CLK__ESDHC2_CLK */
927 [613] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 1, 0x920, 2), /* MX35_PAD_SD2_CLK__I2C3_SDA */
928 [614] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 2, 0x808, 0), /* MX35_PAD_SD2_CLK__ESDHC1_DAT5 */
929 [615] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 3, 0x93c, 2), /* MX35_PAD_SD2_CLK__IPU_CSI_D_3 */
930 [616] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 4, 0x9e0, 0), /* MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 */
931 [617] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 5, 0x894, 1), /* MX35_PAD_SD2_CLK__GPIO2_1 */
932 [618] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 6, 0x998, 2), /* MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 */
933 [619] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 7, 0x0, 0), /* MX35_PAD_SD2_CLK__IPU_DISPB_CS2 */
934 [620] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 0, 0x0, 0), /* MX35_PAD_SD2_DATA0__ESDHC2_DAT0 */
935 [621] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 1, 0x9a0, 1), /* MX35_PAD_SD2_DATA0__UART3_RXD_MUX */
936 [622] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 2, 0x80c, 0), /* MX35_PAD_SD2_DATA0__ESDHC1_DAT6 */
937 [623] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 3, 0x940, 1), /* MX35_PAD_SD2_DATA0__IPU_CSI_D_4 */
938 [624] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 4, 0x9e4, 0), /* MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 */
939 [625] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 5, 0x8c0, 1), /* MX35_PAD_SD2_DATA0__GPIO2_2 */
940 [626] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 6, 0x994, 3), /* MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK */
941 [627] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 0, 0x0, 0), /* MX35_PAD_SD2_DATA1__ESDHC2_DAT1 */
942 [628] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 1, 0x0, 0), /* MX35_PAD_SD2_DATA1__UART3_TXD_MUX */
943 [629] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 2, 0x810, 0), /* MX35_PAD_SD2_DATA1__ESDHC1_DAT7 */
944 [630] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 3, 0x944, 1), /* MX35_PAD_SD2_DATA1__IPU_CSI_D_5 */
945 [631] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 4, 0x9cc, 0), /* MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 */
946 [632] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 5, 0x8cc, 1), /* MX35_PAD_SD2_DATA1__GPIO2_3 */
947 [633] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 0, 0x0, 0), /* MX35_PAD_SD2_DATA2__ESDHC2_DAT2 */
948 [634] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 1, 0x99c, 0), /* MX35_PAD_SD2_DATA2__UART3_RTS */
949 [635] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 2, 0x7c8, 1), /* MX35_PAD_SD2_DATA2__CAN1_RXCAN */
950 [636] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 3, 0x948, 1), /* MX35_PAD_SD2_DATA2__IPU_CSI_D_6 */
951 [637] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 4, 0x9d0, 0), /* MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 */
952 [638] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 5, 0x8d0, 1), /* MX35_PAD_SD2_DATA2__GPIO2_4 */
953 [639] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 0, 0x0, 0), /* MX35_PAD_SD2_DATA3__ESDHC2_DAT3 */
954 [640] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 1, 0x0, 0), /* MX35_PAD_SD2_DATA3__UART3_CTS */
955 [641] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 2, 0x0, 0), /* MX35_PAD_SD2_DATA3__CAN1_TXCAN */
956 [642] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 3, 0x94c, 1), /* MX35_PAD_SD2_DATA3__IPU_CSI_D_7 */
957 [643] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 4, 0x9d4, 0), /* MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 */
958 [644] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 5, 0x8d4, 1), /* MX35_PAD_SD2_DATA3__GPIO2_5 */
959 [645] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 0, 0x0, 0), /* MX35_PAD_ATA_CS0__ATA_CS0 */
960 [646] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 1, 0x7dc, 1), /* MX35_PAD_ATA_CS0__CSPI1_SS3 */
961 [647] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 3, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DISPB_CS1 */
962 [648] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 5, 0x8d8, 1), /* MX35_PAD_ATA_CS0__GPIO2_6 */
963 [649] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 6, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DIAGB_0 */
964 [650] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 7, 0x0, 0), /* MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 */
965 [651] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 0, 0x0, 0), /* MX35_PAD_ATA_CS1__ATA_CS1 */
966 [652] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 3, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DISPB_CS2 */
967 [653] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 4, 0x7f0, 1), /* MX35_PAD_ATA_CS1__CSPI2_SS0 */
968 [654] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 5, 0x8dc, 1), /* MX35_PAD_ATA_CS1__GPIO2_7 */
969 [655] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 6, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DIAGB_1 */
970 [656] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 7, 0x0, 0), /* MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 */
971 [657] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 0, 0x0, 0), /* MX35_PAD_ATA_DIOR__ATA_DIOR */
972 [658] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 1, 0x81c, 1), /* MX35_PAD_ATA_DIOR__ESDHC3_DAT0 */
973 [659] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 2, 0x9c4, 1), /* MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR */
974 [660] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 3, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 */
975 [661] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 4, 0x7f4, 1), /* MX35_PAD_ATA_DIOR__CSPI2_SS1 */
976 [662] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 5, 0x8e0, 1), /* MX35_PAD_ATA_DIOR__GPIO2_8 */
977 [663] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 6, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DIAGB_2 */
978 [664] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 7, 0x0, 0), /* MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 */
979 [665] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 0, 0x0, 0), /* MX35_PAD_ATA_DIOW__ATA_DIOW */
980 [666] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 1, 0x820, 1), /* MX35_PAD_ATA_DIOW__ESDHC3_DAT1 */
981 [667] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 2, 0x0, 0), /* MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP */
982 [668] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 3, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 */
983 [669] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 4, 0x7ec, 2), /* MX35_PAD_ATA_DIOW__CSPI2_MOSI */
984 [670] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 5, 0x8e4, 1), /* MX35_PAD_ATA_DIOW__GPIO2_9 */
985 [671] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 6, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DIAGB_3 */
986 [672] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 7, 0x0, 0), /* MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 */
987 [673] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 0, 0x0, 0), /* MX35_PAD_ATA_DMACK__ATA_DMACK */
988 [674] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 1, 0x824, 1), /* MX35_PAD_ATA_DMACK__ESDHC3_DAT2 */
989 [675] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 2, 0x9c8, 1), /* MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT */
990 [676] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 4, 0x7e8, 2), /* MX35_PAD_ATA_DMACK__CSPI2_MISO */
991 [677] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 5, 0x86c, 1), /* MX35_PAD_ATA_DMACK__GPIO2_10 */
992 [678] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 6, 0x0, 0), /* MX35_PAD_ATA_DMACK__IPU_DIAGB_4 */
993 [679] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 7, 0x0, 0), /* MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 */
994 [680] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 0, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ATA_RESET_B */
995 [681] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 1, 0x828, 1), /* MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 */
996 [682] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 2, 0x9a4, 1), /* MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 */
997 [683] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 3, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O */
998 [684] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 4, 0x7e4, 2), /* MX35_PAD_ATA_RESET_B__CSPI2_RDY */
999 [685] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 5, 0x870, 1), /* MX35_PAD_ATA_RESET_B__GPIO2_11 */
1000 [686] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 6, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 */
1001 [687] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 7, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 */
1002 [688] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 0, 0x0, 0), /* MX35_PAD_ATA_IORDY__ATA_IORDY */
1003 [689] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 1, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC3_DAT4 */
1004 [690] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 2, 0x9a8, 1), /* MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 */
1005 [691] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 3, 0x92c, 3), /* MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO */
1006 [692] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 4, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC2_DAT4 */
1007 [693] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 5, 0x874, 1), /* MX35_PAD_ATA_IORDY__GPIO2_12 */
1008 [694] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 6, 0x0, 0), /* MX35_PAD_ATA_IORDY__IPU_DIAGB_6 */
1009 [695] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 7, 0x0, 0), /* MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 */
1010 [696] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA0__ATA_DATA_0 */
1011 [697] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 1, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC3_DAT5 */
1012 [698] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 2, 0x9ac, 1), /* MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 */
1013 [699] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 3, 0x928, 4), /* MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC */
1014 [700] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 4, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC2_DAT5 */
1015 [701] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 5, 0x878, 1), /* MX35_PAD_ATA_DATA0__GPIO2_13 */
1016 [702] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA0__IPU_DIAGB_7 */
1017 [703] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 */
1018 [704] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 0, 0x0, 0), /* MX35_PAD_ATA_DATA1__ATA_DATA_1 */
1019 [705] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 1, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC3_DAT6 */
1020 [706] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 2, 0x9b0, 1), /* MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 */
1021 [707] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 3, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK */
1022 [708] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 4, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC2_DAT6 */
1023 [709] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 5, 0x87c, 1), /* MX35_PAD_ATA_DATA1__GPIO2_14 */
1024 [710] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 6, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DIAGB_8 */
1025 [711] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 7, 0x0, 0), /* MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 */
1026 [712] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 0, 0x0, 0), /* MX35_PAD_ATA_DATA2__ATA_DATA_2 */
1027 [713] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 1, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC3_DAT7 */
1028 [714] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 2, 0x9b4, 1), /* MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 */
1029 [715] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 3, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS */
1030 [716] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 4, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC2_DAT7 */
1031 [717] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 5, 0x880, 1), /* MX35_PAD_ATA_DATA2__GPIO2_15 */
1032 [718] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 6, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DIAGB_9 */
1033 [719] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 7, 0x0, 0), /* MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 */
1034 [720] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 0, 0x0, 0), /* MX35_PAD_ATA_DATA3__ATA_DATA_3 */
1035 [721] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 1, 0x814, 1), /* MX35_PAD_ATA_DATA3__ESDHC3_CLK */
1036 [722] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 2, 0x9b8, 1), /* MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 */
1037 [723] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 4, 0x7e0, 2), /* MX35_PAD_ATA_DATA3__CSPI2_SCLK */
1038 [724] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 5, 0x884, 1), /* MX35_PAD_ATA_DATA3__GPIO2_16 */
1039 [725] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 6, 0x0, 0), /* MX35_PAD_ATA_DATA3__IPU_DIAGB_10 */
1040 [726] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 7, 0x0, 0), /* MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 */
1041 [727] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA4__ATA_DATA_4 */
1042 [728] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 1, 0x818, 1), /* MX35_PAD_ATA_DATA4__ESDHC3_CMD */
1043 [729] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 2, 0x9bc, 1), /* MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 */
1044 [730] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 5, 0x888, 1), /* MX35_PAD_ATA_DATA4__GPIO2_17 */
1045 [731] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA4__IPU_DIAGB_11 */
1046 [732] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 */
1047 [733] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 0, 0x0, 0), /* MX35_PAD_ATA_DATA5__ATA_DATA_5 */
1048 [734] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 2, 0x9c0, 1), /* MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 */
1049 [735] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 5, 0x88c, 1), /* MX35_PAD_ATA_DATA5__GPIO2_18 */
1050 [736] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 6, 0x0, 0), /* MX35_PAD_ATA_DATA5__IPU_DIAGB_12 */
1051 [737] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 7, 0x0, 0), /* MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 */
1052 [738] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 0, 0x0, 0), /* MX35_PAD_ATA_DATA6__ATA_DATA_6 */
1053 [739] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 1, 0x0, 0), /* MX35_PAD_ATA_DATA6__CAN1_TXCAN */
1054 [740] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 2, 0x0, 0), /* MX35_PAD_ATA_DATA6__UART1_DTR */
1055 [741] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 3, 0x7b4, 0), /* MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD */
1056 [742] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 5, 0x890, 1), /* MX35_PAD_ATA_DATA6__GPIO2_19 */
1057 [743] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 6, 0x0, 0), /* MX35_PAD_ATA_DATA6__IPU_DIAGB_13 */
1058 [744] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 0, 0x0, 0), /* MX35_PAD_ATA_DATA7__ATA_DATA_7 */
1059 [745] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 1, 0x7c8, 2), /* MX35_PAD_ATA_DATA7__CAN1_RXCAN */
1060 [746] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 2, 0x0, 0), /* MX35_PAD_ATA_DATA7__UART1_DSR */
1061 [747] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 3, 0x7b0, 0), /* MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD */
1062 [748] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 5, 0x898, 1), /* MX35_PAD_ATA_DATA7__GPIO2_20 */
1063 [749] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 6, 0x0, 0), /* MX35_PAD_ATA_DATA7__IPU_DIAGB_14 */
1064 [750] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA8__ATA_DATA_8 */
1065 [751] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 1, 0x99c, 1), /* MX35_PAD_ATA_DATA8__UART3_RTS */
1066 [752] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 2, 0x0, 0), /* MX35_PAD_ATA_DATA8__UART1_RI */
1067 [753] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 3, 0x7c0, 0), /* MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC */
1068 [754] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 5, 0x89c, 1), /* MX35_PAD_ATA_DATA8__GPIO2_21 */
1069 [755] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA8__IPU_DIAGB_15 */
1070 [756] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA9__ATA_DATA_9 */
1071 [757] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 1, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART3_CTS */
1072 [758] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 2, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART1_DCD */
1073 [759] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 3, 0x7c4, 0), /* MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS */
1074 [760] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 5, 0x8a0, 1), /* MX35_PAD_ATA_DATA9__GPIO2_22 */
1075 [761] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA9__IPU_DIAGB_16 */
1076 [762] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA10__ATA_DATA_10 */
1077 [763] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 1, 0x9a0, 2), /* MX35_PAD_ATA_DATA10__UART3_RXD_MUX */
1078 [764] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 3, 0x7b8, 0), /* MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC */
1079 [765] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 5, 0x8a4, 1), /* MX35_PAD_ATA_DATA10__GPIO2_23 */
1080 [766] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA10__IPU_DIAGB_17 */
1081 [767] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA11__ATA_DATA_11 */
1082 [768] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 1, 0x0, 0), /* MX35_PAD_ATA_DATA11__UART3_TXD_MUX */
1083 [769] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 3, 0x7bc, 0), /* MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS */
1084 [770] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 5, 0x8a8, 1), /* MX35_PAD_ATA_DATA11__GPIO2_24 */
1085 [771] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA11__IPU_DIAGB_18 */
1086 [772] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 0, 0x0, 0), /* MX35_PAD_ATA_DATA12__ATA_DATA_12 */
1087 [773] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 1, 0x91c, 3), /* MX35_PAD_ATA_DATA12__I2C3_SCL */
1088 [774] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 5, 0x8ac, 1), /* MX35_PAD_ATA_DATA12__GPIO2_25 */
1089 [775] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 6, 0x0, 0), /* MX35_PAD_ATA_DATA12__IPU_DIAGB_19 */
1090 [776] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA13__ATA_DATA_13 */
1091 [777] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 1, 0x920, 3), /* MX35_PAD_ATA_DATA13__I2C3_SDA */
1092 [778] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 5, 0x8b0, 1), /* MX35_PAD_ATA_DATA13__GPIO2_26 */
1093 [779] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA13__IPU_DIAGB_20 */
1094 [780] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA14__ATA_DATA_14 */
1095 [781] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 1, 0x930, 2), /* MX35_PAD_ATA_DATA14__IPU_CSI_D_0 */
1096 [782] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 3, 0x970, 2), /* MX35_PAD_ATA_DATA14__KPP_ROW_0 */
1097 [783] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 5, 0x8b4, 1), /* MX35_PAD_ATA_DATA14__GPIO2_27 */
1098 [784] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA14__IPU_DIAGB_21 */
1099 [785] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA15__ATA_DATA_15 */
1100 [786] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 1, 0x934, 2), /* MX35_PAD_ATA_DATA15__IPU_CSI_D_1 */
1101 [787] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 3, 0x974, 2), /* MX35_PAD_ATA_DATA15__KPP_ROW_1 */
1102 [788] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 5, 0x8b8, 1), /* MX35_PAD_ATA_DATA15__GPIO2_28 */
1103 [789] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA15__IPU_DIAGB_22 */
1104 [790] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 0, 0x0, 0), /* MX35_PAD_ATA_INTRQ__ATA_INTRQ */
1105 [791] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 1, 0x938, 3), /* MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 */
1106 [792] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 3, 0x978, 2), /* MX35_PAD_ATA_INTRQ__KPP_ROW_2 */
1107 [793] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 5, 0x8bc, 1), /* MX35_PAD_ATA_INTRQ__GPIO2_29 */
1108 [794] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 6, 0x0, 0), /* MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 */
1109 [795] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 0, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN */
1110 [796] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 1, 0x93c, 3), /* MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 */
1111 [797] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 3, 0x97c, 2), /* MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 */
1112 [798] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 5, 0x8c4, 1), /* MX35_PAD_ATA_BUFF_EN__GPIO2_30 */
1113 [799] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 6, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 */
1114 [800] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 0, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ATA_DMARQ */
1115 [801] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 1, 0x940, 2), /* MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 */
1116 [802] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 3, 0x950, 2), /* MX35_PAD_ATA_DMARQ__KPP_COL_0 */
1117 [803] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 5, 0x8c8, 1), /* MX35_PAD_ATA_DMARQ__GPIO2_31 */
1118 [804] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 6, 0x0, 0), /* MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 */
1119 [805] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 7, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 */
1120 [806] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 0, 0x0, 0), /* MX35_PAD_ATA_DA0__ATA_DA_0 */
1121 [807] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 1, 0x944, 2), /* MX35_PAD_ATA_DA0__IPU_CSI_D_5 */
1122 [808] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 3, 0x954, 2), /* MX35_PAD_ATA_DA0__KPP_COL_1 */
1123 [809] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 5, 0x8e8, 1), /* MX35_PAD_ATA_DA0__GPIO3_0 */
1124 [810] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 6, 0x0, 0), /* MX35_PAD_ATA_DA0__IPU_DIAGB_26 */
1125 [811] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 7, 0x0, 0), /* MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 */
1126 [812] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 0, 0x0, 0), /* MX35_PAD_ATA_DA1__ATA_DA_1 */
1127 [813] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 1, 0x948, 2), /* MX35_PAD_ATA_DA1__IPU_CSI_D_6 */
1128 [814] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 3, 0x958, 2), /* MX35_PAD_ATA_DA1__KPP_COL_2 */
1129 [815] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 5, 0x0, 0), /* MX35_PAD_ATA_DA1__GPIO3_1 */
1130 [816] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 6, 0x0, 0), /* MX35_PAD_ATA_DA1__IPU_DIAGB_27 */
1131 [817] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 7, 0x0, 0), /* MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 */
1132 [818] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 0, 0x0, 0), /* MX35_PAD_ATA_DA2__ATA_DA_2 */
1133 [819] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 1, 0x94c, 2), /* MX35_PAD_ATA_DA2__IPU_CSI_D_7 */
1134 [820] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 3, 0x95c, 2), /* MX35_PAD_ATA_DA2__KPP_COL_3 */
1135 [821] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 5, 0x0, 0), /* MX35_PAD_ATA_DA2__GPIO3_2 */
1136 [822] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 6, 0x0, 0), /* MX35_PAD_ATA_DA2__IPU_DIAGB_28 */
1137 [823] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 7, 0x0, 0), /* MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 */
1138 [824] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 0, 0x0, 0), /* MX35_PAD_MLB_CLK__MLB_MLBCLK */
1139 [825] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 5, 0x0, 0), /* MX35_PAD_MLB_CLK__GPIO3_3 */
1140 [826] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 0, 0x0, 0), /* MX35_PAD_MLB_DAT__MLB_MLBDAT */
1141 [827] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 5, 0x904, 1), /* MX35_PAD_MLB_DAT__GPIO3_4 */
1142 [828] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 0, 0x0, 0), /* MX35_PAD_MLB_SIG__MLB_MLBSIG */
1143 [829] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 5, 0x908, 1), /* MX35_PAD_MLB_SIG__GPIO3_5 */
1144 [830] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 0, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__FEC_TX_CLK */
1145 [831] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 1, 0x804, 1), /* MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 */
1146 [832] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 2, 0x9a0, 3), /* MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX */
1147 [833] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 3, 0x9ec, 1), /* MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR */
1148 [834] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 4, 0x7ec, 3), /* MX35_PAD_FEC_TX_CLK__CSPI2_MOSI */
1149 [835] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 5, 0x90c, 1), /* MX35_PAD_FEC_TX_CLK__GPIO3_6 */
1150 [836] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 6, 0x928, 5), /* MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC */
1151 [837] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 7, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 */
1152 [838] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 0, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__FEC_RX_CLK */
1153 [839] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 1, 0x808, 1), /* MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 */
1154 [840] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 2, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX */
1155 [841] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 3, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP */
1156 [842] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 4, 0x7e8, 3), /* MX35_PAD_FEC_RX_CLK__CSPI2_MISO */
1157 [843] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 5, 0x910, 1), /* MX35_PAD_FEC_RX_CLK__GPIO3_7 */
1158 [844] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 6, 0x92c, 4), /* MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I */
1159 [845] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 7, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 */
1160 [846] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 0, 0x0, 0), /* MX35_PAD_FEC_RX_DV__FEC_RX_DV */
1161 [847] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 1, 0x80c, 1), /* MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 */
1162 [848] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 2, 0x99c, 2), /* MX35_PAD_FEC_RX_DV__UART3_RTS */
1163 [849] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 3, 0x9f0, 1), /* MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT */
1164 [850] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 4, 0x7e0, 3), /* MX35_PAD_FEC_RX_DV__CSPI2_SCLK */
1165 [851] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 5, 0x914, 1), /* MX35_PAD_FEC_RX_DV__GPIO3_8 */
1166 [852] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 6, 0x0, 0), /* MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK */
1167 [853] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 7, 0x0, 0), /* MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 */
1168 [854] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 0, 0x0, 0), /* MX35_PAD_FEC_COL__FEC_COL */
1169 [855] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 1, 0x810, 1), /* MX35_PAD_FEC_COL__ESDHC1_DAT7 */
1170 [856] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 2, 0x0, 0), /* MX35_PAD_FEC_COL__UART3_CTS */
1171 [857] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 3, 0x9cc, 1), /* MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 */
1172 [858] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 4, 0x7e4, 3), /* MX35_PAD_FEC_COL__CSPI2_RDY */
1173 [859] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 5, 0x918, 1), /* MX35_PAD_FEC_COL__GPIO3_9 */
1174 [860] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 6, 0x0, 0), /* MX35_PAD_FEC_COL__IPU_DISPB_SER_RS */
1175 [861] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 7, 0x0, 0), /* MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 */
1176 [862] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA0__FEC_RDATA_0 */
1177 [863] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 1, 0x0, 0), /* MX35_PAD_FEC_RDATA0__PWM_PWMO */
1178 [864] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA0__UART3_DTR */
1179 [865] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 3, 0x9d0, 1), /* MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 */
1180 [866] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 4, 0x7f0, 2), /* MX35_PAD_FEC_RDATA0__CSPI2_SS0 */
1181 [867] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 5, 0x8ec, 1), /* MX35_PAD_FEC_RDATA0__GPIO3_10 */
1182 [868] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 */
1183 [869] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 7, 0x0, 0), /* MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 */
1184 [870] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA0__FEC_TDATA_0 */
1185 [871] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 1, 0x0, 0), /* MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 */
1186 [872] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 2, 0x0, 0), /* MX35_PAD_FEC_TDATA0__UART3_DSR */
1187 [873] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 3, 0x9d4, 1), /* MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 */
1188 [874] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 4, 0x7f4, 2), /* MX35_PAD_FEC_TDATA0__CSPI2_SS1 */
1189 [875] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 5, 0x8f0, 1), /* MX35_PAD_FEC_TDATA0__GPIO3_11 */
1190 [876] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 */
1191 [877] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 7, 0x0, 0), /* MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 */
1192 [878] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 0, 0x0, 0), /* MX35_PAD_FEC_TX_EN__FEC_TX_EN */
1193 [879] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 1, 0x998, 3), /* MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 */
1194 [880] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 2, 0x0, 0), /* MX35_PAD_FEC_TX_EN__UART3_RI */
1195 [881] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 3, 0x9d8, 1), /* MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 */
1196 [882] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 5, 0x8f4, 1), /* MX35_PAD_FEC_TX_EN__GPIO3_12 */
1197 [883] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 6, 0x0, 0), /* MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS */
1198 [884] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 7, 0x0, 0), /* MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 */
1199 [885] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 0, 0x0, 0), /* MX35_PAD_FEC_MDC__FEC_MDC */
1200 [886] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 1, 0x0, 0), /* MX35_PAD_FEC_MDC__CAN2_TXCAN */
1201 [887] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 2, 0x0, 0), /* MX35_PAD_FEC_MDC__UART3_DCD */
1202 [888] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 3, 0x9dc, 1), /* MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 */
1203 [889] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 5, 0x8f8, 1), /* MX35_PAD_FEC_MDC__GPIO3_13 */
1204 [890] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 6, 0x0, 0), /* MX35_PAD_FEC_MDC__IPU_DISPB_WR */
1205 [891] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 7, 0x0, 0), /* MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 */
1206 [892] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 0, 0x0, 0), /* MX35_PAD_FEC_MDIO__FEC_MDIO */
1207 [893] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 1, 0x7cc, 2), /* MX35_PAD_FEC_MDIO__CAN2_RXCAN */
1208 [894] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 3, 0x9e0, 1), /* MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 */
1209 [895] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 5, 0x8fc, 1), /* MX35_PAD_FEC_MDIO__GPIO3_14 */
1210 [896] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 6, 0x0, 0), /* MX35_PAD_FEC_MDIO__IPU_DISPB_RD */
1211 [897] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 7, 0x0, 0), /* MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 */
1212 [898] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 0, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__FEC_TX_ERR */
1213 [899] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 1, 0x990, 2), /* MX35_PAD_FEC_TX_ERR__OWIRE_LINE */
1214 [900] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 2, 0x994, 4), /* MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK */
1215 [901] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 3, 0x9e4, 1), /* MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 */
1216 [902] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 5, 0x900, 1), /* MX35_PAD_FEC_TX_ERR__GPIO3_15 */
1217 [903] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 6, 0x924, 3), /* MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC */
1218 [904] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 7, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 */
1219 [905] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 0, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__FEC_RX_ERR */
1220 [906] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 1, 0x930, 3), /* MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 */
1221 [907] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 3, 0x9e8, 1), /* MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 */
1222 [908] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 4, 0x960, 1), /* MX35_PAD_FEC_RX_ERR__KPP_COL_4 */
1223 [909] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 5, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__GPIO3_16 */
1224 [910] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 6, 0x92c, 5), /* MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO */
1225 [911] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 0, 0x0, 0), /* MX35_PAD_FEC_CRS__FEC_CRS */
1226 [912] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 1, 0x934, 3), /* MX35_PAD_FEC_CRS__IPU_CSI_D_1 */
1227 [913] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 3, 0x0, 0), /* MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR */
1228 [914] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 4, 0x964, 1), /* MX35_PAD_FEC_CRS__KPP_COL_5 */
1229 [915] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 5, 0x0, 0), /* MX35_PAD_FEC_CRS__GPIO3_17 */
1230 [916] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 6, 0x0, 0), /* MX35_PAD_FEC_CRS__IPU_FLASH_STROBE */
1231 [917] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA1__FEC_RDATA_1 */
1232 [918] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 1, 0x938, 4), /* MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 */
1233 [919] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC */
1234 [920] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 3, 0x9f4, 2), /* MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC */
1235 [921] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 4, 0x968, 1), /* MX35_PAD_FEC_RDATA1__KPP_COL_6 */
1236 [922] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA1__GPIO3_18 */
1237 [923] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 */
1238 [924] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA1__FEC_TDATA_1 */
1239 [925] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 1, 0x93c, 4), /* MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 */
1240 [926] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 2, 0x7bc, 1), /* MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS */
1241 [927] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 4, 0x96c, 1), /* MX35_PAD_FEC_TDATA1__KPP_COL_7 */
1242 [928] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA1__GPIO3_19 */
1243 [929] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 */
1244 [930] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA2__FEC_RDATA_2 */
1245 [931] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 1, 0x940, 3), /* MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 */
1246 [932] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 2, 0x7b4, 1), /* MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD */
1247 [933] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 4, 0x980, 1), /* MX35_PAD_FEC_RDATA2__KPP_ROW_4 */
1248 [934] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA2__GPIO3_20 */
1249 [935] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA2__FEC_TDATA_2 */
1250 [936] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 1, 0x944, 3), /* MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 */
1251 [937] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 2, 0x7b0, 1), /* MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD */
1252 [938] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 4, 0x984, 1), /* MX35_PAD_FEC_TDATA2__KPP_ROW_5 */
1253 [939] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA2__GPIO3_21 */
1254 [940] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA3__FEC_RDATA_3 */
1255 [941] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 1, 0x948, 3), /* MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 */
1256 [942] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 2, 0x7c0, 1), /* MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC */
1257 [943] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 4, 0x988, 1), /* MX35_PAD_FEC_RDATA3__KPP_ROW_6 */
1258 [944] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA3__GPIO3_22 */
1259 [945] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA3__FEC_TDATA_3 */
1260 [946] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 1, 0x94c, 3), /* MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 */
1261 [947] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 2, 0x7c4, 1), /* MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS */
1262 [948] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 4, 0x98c, 1), /* MX35_PAD_FEC_TDATA3__KPP_ROW_7 */
1263 [949] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA3__GPIO3_23 */
1264 [950] = IMX_PIN_REG(MX35_PAD_EXT_ARMCLK, 0x78c, 0x0, 0, 0x0, 0), /* MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK */
1265 [951] = IMX_PIN_REG(MX35_PAD_TEST_MODE, 0x790, 0x0, 0, 0x0, 0), /* MX35_PAD_TEST_MODE__TCU_TEST_MODE */
1266}; 512};
1267 513
1268/* Pad names for the pinmux subsystem */ 514/* Pad names for the pinmux subsystem */
1269static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { 515static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
516 IMX_PINCTRL_PIN(MX35_PAD_RESERVE0),
1270 IMX_PINCTRL_PIN(MX35_PAD_CAPTURE), 517 IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
1271 IMX_PINCTRL_PIN(MX35_PAD_COMPARE), 518 IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
1272 IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST), 519 IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
@@ -1274,14 +521,7 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
1274 IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1), 521 IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
1275 IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0), 522 IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
1276 IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0), 523 IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
1277 IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
1278 IMX_PINCTRL_PIN(MX35_PAD_POR_B),
1279 IMX_PINCTRL_PIN(MX35_PAD_CLKO), 524 IMX_PINCTRL_PIN(MX35_PAD_CLKO),
1280 IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
1281 IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
1282 IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
1283 IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
1284 IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
1285 IMX_PINCTRL_PIN(MX35_PAD_VSTBY), 525 IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
1286 IMX_PINCTRL_PIN(MX35_PAD_A0), 526 IMX_PINCTRL_PIN(MX35_PAD_A0),
1287 IMX_PINCTRL_PIN(MX35_PAD_A1), 527 IMX_PINCTRL_PIN(MX35_PAD_A1),
@@ -1310,44 +550,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
1310 IMX_PINCTRL_PIN(MX35_PAD_A23), 550 IMX_PINCTRL_PIN(MX35_PAD_A23),
1311 IMX_PINCTRL_PIN(MX35_PAD_A24), 551 IMX_PINCTRL_PIN(MX35_PAD_A24),
1312 IMX_PINCTRL_PIN(MX35_PAD_A25), 552 IMX_PINCTRL_PIN(MX35_PAD_A25),
1313 IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
1314 IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
1315 IMX_PINCTRL_PIN(MX35_PAD_SD0),
1316 IMX_PINCTRL_PIN(MX35_PAD_SD1),
1317 IMX_PINCTRL_PIN(MX35_PAD_SD2),
1318 IMX_PINCTRL_PIN(MX35_PAD_SD3),
1319 IMX_PINCTRL_PIN(MX35_PAD_SD4),
1320 IMX_PINCTRL_PIN(MX35_PAD_SD5),
1321 IMX_PINCTRL_PIN(MX35_PAD_SD6),
1322 IMX_PINCTRL_PIN(MX35_PAD_SD7),
1323 IMX_PINCTRL_PIN(MX35_PAD_SD8),
1324 IMX_PINCTRL_PIN(MX35_PAD_SD9),
1325 IMX_PINCTRL_PIN(MX35_PAD_SD10),
1326 IMX_PINCTRL_PIN(MX35_PAD_SD11),
1327 IMX_PINCTRL_PIN(MX35_PAD_SD12),
1328 IMX_PINCTRL_PIN(MX35_PAD_SD13),
1329 IMX_PINCTRL_PIN(MX35_PAD_SD14),
1330 IMX_PINCTRL_PIN(MX35_PAD_SD15),
1331 IMX_PINCTRL_PIN(MX35_PAD_SD16),
1332 IMX_PINCTRL_PIN(MX35_PAD_SD17),
1333 IMX_PINCTRL_PIN(MX35_PAD_SD18),
1334 IMX_PINCTRL_PIN(MX35_PAD_SD19),
1335 IMX_PINCTRL_PIN(MX35_PAD_SD20),
1336 IMX_PINCTRL_PIN(MX35_PAD_SD21),
1337 IMX_PINCTRL_PIN(MX35_PAD_SD22),
1338 IMX_PINCTRL_PIN(MX35_PAD_SD23),
1339 IMX_PINCTRL_PIN(MX35_PAD_SD24),
1340 IMX_PINCTRL_PIN(MX35_PAD_SD25),
1341 IMX_PINCTRL_PIN(MX35_PAD_SD26),
1342 IMX_PINCTRL_PIN(MX35_PAD_SD27),
1343 IMX_PINCTRL_PIN(MX35_PAD_SD28),
1344 IMX_PINCTRL_PIN(MX35_PAD_SD29),
1345 IMX_PINCTRL_PIN(MX35_PAD_SD30),
1346 IMX_PINCTRL_PIN(MX35_PAD_SD31),
1347 IMX_PINCTRL_PIN(MX35_PAD_DQM0),
1348 IMX_PINCTRL_PIN(MX35_PAD_DQM1),
1349 IMX_PINCTRL_PIN(MX35_PAD_DQM2),
1350 IMX_PINCTRL_PIN(MX35_PAD_DQM3),
1351 IMX_PINCTRL_PIN(MX35_PAD_EB0), 553 IMX_PINCTRL_PIN(MX35_PAD_EB0),
1352 IMX_PINCTRL_PIN(MX35_PAD_EB1), 554 IMX_PINCTRL_PIN(MX35_PAD_EB1),
1353 IMX_PINCTRL_PIN(MX35_PAD_OE), 555 IMX_PINCTRL_PIN(MX35_PAD_OE),
@@ -1358,42 +560,15 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
1358 IMX_PINCTRL_PIN(MX35_PAD_CS4), 560 IMX_PINCTRL_PIN(MX35_PAD_CS4),
1359 IMX_PINCTRL_PIN(MX35_PAD_CS5), 561 IMX_PINCTRL_PIN(MX35_PAD_CS5),
1360 IMX_PINCTRL_PIN(MX35_PAD_NF_CE0), 562 IMX_PINCTRL_PIN(MX35_PAD_NF_CE0),
1361 IMX_PINCTRL_PIN(MX35_PAD_ECB),
1362 IMX_PINCTRL_PIN(MX35_PAD_LBA), 563 IMX_PINCTRL_PIN(MX35_PAD_LBA),
1363 IMX_PINCTRL_PIN(MX35_PAD_BCLK), 564 IMX_PINCTRL_PIN(MX35_PAD_BCLK),
1364 IMX_PINCTRL_PIN(MX35_PAD_RW), 565 IMX_PINCTRL_PIN(MX35_PAD_RW),
1365 IMX_PINCTRL_PIN(MX35_PAD_RAS),
1366 IMX_PINCTRL_PIN(MX35_PAD_CAS),
1367 IMX_PINCTRL_PIN(MX35_PAD_SDWE),
1368 IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
1369 IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
1370 IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
1371 IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
1372 IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
1373 IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
1374 IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
1375 IMX_PINCTRL_PIN(MX35_PAD_NFWE_B), 566 IMX_PINCTRL_PIN(MX35_PAD_NFWE_B),
1376 IMX_PINCTRL_PIN(MX35_PAD_NFRE_B), 567 IMX_PINCTRL_PIN(MX35_PAD_NFRE_B),
1377 IMX_PINCTRL_PIN(MX35_PAD_NFALE), 568 IMX_PINCTRL_PIN(MX35_PAD_NFALE),
1378 IMX_PINCTRL_PIN(MX35_PAD_NFCLE), 569 IMX_PINCTRL_PIN(MX35_PAD_NFCLE),
1379 IMX_PINCTRL_PIN(MX35_PAD_NFWP_B), 570 IMX_PINCTRL_PIN(MX35_PAD_NFWP_B),
1380 IMX_PINCTRL_PIN(MX35_PAD_NFRB), 571 IMX_PINCTRL_PIN(MX35_PAD_NFRB),
1381 IMX_PINCTRL_PIN(MX35_PAD_D15),
1382 IMX_PINCTRL_PIN(MX35_PAD_D14),
1383 IMX_PINCTRL_PIN(MX35_PAD_D13),
1384 IMX_PINCTRL_PIN(MX35_PAD_D12),
1385 IMX_PINCTRL_PIN(MX35_PAD_D11),
1386 IMX_PINCTRL_PIN(MX35_PAD_D10),
1387 IMX_PINCTRL_PIN(MX35_PAD_D9),
1388 IMX_PINCTRL_PIN(MX35_PAD_D8),
1389 IMX_PINCTRL_PIN(MX35_PAD_D7),
1390 IMX_PINCTRL_PIN(MX35_PAD_D6),
1391 IMX_PINCTRL_PIN(MX35_PAD_D5),
1392 IMX_PINCTRL_PIN(MX35_PAD_D4),
1393 IMX_PINCTRL_PIN(MX35_PAD_D3),
1394 IMX_PINCTRL_PIN(MX35_PAD_D2),
1395 IMX_PINCTRL_PIN(MX35_PAD_D1),
1396 IMX_PINCTRL_PIN(MX35_PAD_D0),
1397 IMX_PINCTRL_PIN(MX35_PAD_CSI_D8), 572 IMX_PINCTRL_PIN(MX35_PAD_CSI_D8),
1398 IMX_PINCTRL_PIN(MX35_PAD_CSI_D9), 573 IMX_PINCTRL_PIN(MX35_PAD_CSI_D9),
1399 IMX_PINCTRL_PIN(MX35_PAD_CSI_D10), 574 IMX_PINCTRL_PIN(MX35_PAD_CSI_D10),
@@ -1444,14 +619,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
1444 IMX_PINCTRL_PIN(MX35_PAD_TXD2), 619 IMX_PINCTRL_PIN(MX35_PAD_TXD2),
1445 IMX_PINCTRL_PIN(MX35_PAD_RTS2), 620 IMX_PINCTRL_PIN(MX35_PAD_RTS2),
1446 IMX_PINCTRL_PIN(MX35_PAD_CTS2), 621 IMX_PINCTRL_PIN(MX35_PAD_CTS2),
1447 IMX_PINCTRL_PIN(MX35_PAD_RTCK),
1448 IMX_PINCTRL_PIN(MX35_PAD_TCK),
1449 IMX_PINCTRL_PIN(MX35_PAD_TMS),
1450 IMX_PINCTRL_PIN(MX35_PAD_TDI),
1451 IMX_PINCTRL_PIN(MX35_PAD_TDO),
1452 IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
1453 IMX_PINCTRL_PIN(MX35_PAD_DE_B),
1454 IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
1455 IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR), 622 IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR),
1456 IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC), 623 IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC),
1457 IMX_PINCTRL_PIN(MX35_PAD_LD0), 624 IMX_PINCTRL_PIN(MX35_PAD_LD0),
@@ -1548,6 +715,287 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
1548 IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2), 715 IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2),
1549 IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3), 716 IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3),
1550 IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3), 717 IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3),
718 IMX_PINCTRL_PIN(MX35_PAD_RESERVE1),
719 IMX_PINCTRL_PIN(MX35_PAD_RESERVE2),
720 IMX_PINCTRL_PIN(MX35_PAD_RESERVE3),
721 IMX_PINCTRL_PIN(MX35_PAD_RESERVE4),
722 IMX_PINCTRL_PIN(MX35_PAD_RESERVE5),
723 IMX_PINCTRL_PIN(MX35_PAD_RESERVE6),
724 IMX_PINCTRL_PIN(MX35_PAD_RESERVE7),
725 IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
726 IMX_PINCTRL_PIN(MX35_PAD_POR_B),
727 IMX_PINCTRL_PIN(MX35_PAD_RESERVE8),
728 IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
729 IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
730 IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
731 IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
732 IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
733 IMX_PINCTRL_PIN(MX35_PAD_RESERVE9),
734 IMX_PINCTRL_PIN(MX35_PAD_RESERVE10),
735 IMX_PINCTRL_PIN(MX35_PAD_RESERVE11),
736 IMX_PINCTRL_PIN(MX35_PAD_RESERVE12),
737 IMX_PINCTRL_PIN(MX35_PAD_RESERVE13),
738 IMX_PINCTRL_PIN(MX35_PAD_RESERVE14),
739 IMX_PINCTRL_PIN(MX35_PAD_RESERVE15),
740 IMX_PINCTRL_PIN(MX35_PAD_RESERVE16),
741 IMX_PINCTRL_PIN(MX35_PAD_RESERVE17),
742 IMX_PINCTRL_PIN(MX35_PAD_RESERVE18),
743 IMX_PINCTRL_PIN(MX35_PAD_RESERVE19),
744 IMX_PINCTRL_PIN(MX35_PAD_RESERVE20),
745 IMX_PINCTRL_PIN(MX35_PAD_RESERVE21),
746 IMX_PINCTRL_PIN(MX35_PAD_RESERVE22),
747 IMX_PINCTRL_PIN(MX35_PAD_RESERVE23),
748 IMX_PINCTRL_PIN(MX35_PAD_RESERVE24),
749 IMX_PINCTRL_PIN(MX35_PAD_RESERVE25),
750 IMX_PINCTRL_PIN(MX35_PAD_RESERVE26),
751 IMX_PINCTRL_PIN(MX35_PAD_RESERVE27),
752 IMX_PINCTRL_PIN(MX35_PAD_RESERVE28),
753 IMX_PINCTRL_PIN(MX35_PAD_RESERVE29),
754 IMX_PINCTRL_PIN(MX35_PAD_RESERVE30),
755 IMX_PINCTRL_PIN(MX35_PAD_RESERVE31),
756 IMX_PINCTRL_PIN(MX35_PAD_RESERVE32),
757 IMX_PINCTRL_PIN(MX35_PAD_RESERVE33),
758 IMX_PINCTRL_PIN(MX35_PAD_RESERVE34),
759 IMX_PINCTRL_PIN(MX35_PAD_RESERVE35),
760 IMX_PINCTRL_PIN(MX35_PAD_RESERVE36),
761 IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
762 IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
763 IMX_PINCTRL_PIN(MX35_PAD_SD0),
764 IMX_PINCTRL_PIN(MX35_PAD_SD1),
765 IMX_PINCTRL_PIN(MX35_PAD_SD2),
766 IMX_PINCTRL_PIN(MX35_PAD_SD3),
767 IMX_PINCTRL_PIN(MX35_PAD_SD4),
768 IMX_PINCTRL_PIN(MX35_PAD_SD5),
769 IMX_PINCTRL_PIN(MX35_PAD_SD6),
770 IMX_PINCTRL_PIN(MX35_PAD_SD7),
771 IMX_PINCTRL_PIN(MX35_PAD_SD8),
772 IMX_PINCTRL_PIN(MX35_PAD_SD9),
773 IMX_PINCTRL_PIN(MX35_PAD_SD10),
774 IMX_PINCTRL_PIN(MX35_PAD_SD11),
775 IMX_PINCTRL_PIN(MX35_PAD_SD12),
776 IMX_PINCTRL_PIN(MX35_PAD_SD13),
777 IMX_PINCTRL_PIN(MX35_PAD_SD14),
778 IMX_PINCTRL_PIN(MX35_PAD_SD15),
779 IMX_PINCTRL_PIN(MX35_PAD_SD16),
780 IMX_PINCTRL_PIN(MX35_PAD_SD17),
781 IMX_PINCTRL_PIN(MX35_PAD_SD18),
782 IMX_PINCTRL_PIN(MX35_PAD_SD19),
783 IMX_PINCTRL_PIN(MX35_PAD_SD20),
784 IMX_PINCTRL_PIN(MX35_PAD_SD21),
785 IMX_PINCTRL_PIN(MX35_PAD_SD22),
786 IMX_PINCTRL_PIN(MX35_PAD_SD23),
787 IMX_PINCTRL_PIN(MX35_PAD_SD24),
788 IMX_PINCTRL_PIN(MX35_PAD_SD25),
789 IMX_PINCTRL_PIN(MX35_PAD_SD26),
790 IMX_PINCTRL_PIN(MX35_PAD_SD27),
791 IMX_PINCTRL_PIN(MX35_PAD_SD28),
792 IMX_PINCTRL_PIN(MX35_PAD_SD29),
793 IMX_PINCTRL_PIN(MX35_PAD_SD30),
794 IMX_PINCTRL_PIN(MX35_PAD_SD31),
795 IMX_PINCTRL_PIN(MX35_PAD_DQM0),
796 IMX_PINCTRL_PIN(MX35_PAD_DQM1),
797 IMX_PINCTRL_PIN(MX35_PAD_DQM2),
798 IMX_PINCTRL_PIN(MX35_PAD_DQM3),
799 IMX_PINCTRL_PIN(MX35_PAD_RESERVE37),
800 IMX_PINCTRL_PIN(MX35_PAD_RESERVE38),
801 IMX_PINCTRL_PIN(MX35_PAD_RESERVE39),
802 IMX_PINCTRL_PIN(MX35_PAD_RESERVE40),
803 IMX_PINCTRL_PIN(MX35_PAD_RESERVE41),
804 IMX_PINCTRL_PIN(MX35_PAD_RESERVE42),
805 IMX_PINCTRL_PIN(MX35_PAD_RESERVE43),
806 IMX_PINCTRL_PIN(MX35_PAD_RESERVE44),
807 IMX_PINCTRL_PIN(MX35_PAD_RESERVE45),
808 IMX_PINCTRL_PIN(MX35_PAD_RESERVE46),
809 IMX_PINCTRL_PIN(MX35_PAD_ECB),
810 IMX_PINCTRL_PIN(MX35_PAD_RESERVE47),
811 IMX_PINCTRL_PIN(MX35_PAD_RESERVE48),
812 IMX_PINCTRL_PIN(MX35_PAD_RESERVE49),
813 IMX_PINCTRL_PIN(MX35_PAD_RAS),
814 IMX_PINCTRL_PIN(MX35_PAD_CAS),
815 IMX_PINCTRL_PIN(MX35_PAD_SDWE),
816 IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
817 IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
818 IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
819 IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
820 IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
821 IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
822 IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
823 IMX_PINCTRL_PIN(MX35_PAD_RESERVE50),
824 IMX_PINCTRL_PIN(MX35_PAD_RESERVE51),
825 IMX_PINCTRL_PIN(MX35_PAD_RESERVE52),
826 IMX_PINCTRL_PIN(MX35_PAD_RESERVE53),
827 IMX_PINCTRL_PIN(MX35_PAD_RESERVE54),
828 IMX_PINCTRL_PIN(MX35_PAD_RESERVE55),
829 IMX_PINCTRL_PIN(MX35_PAD_D15),
830 IMX_PINCTRL_PIN(MX35_PAD_D14),
831 IMX_PINCTRL_PIN(MX35_PAD_D13),
832 IMX_PINCTRL_PIN(MX35_PAD_D12),
833 IMX_PINCTRL_PIN(MX35_PAD_D11),
834 IMX_PINCTRL_PIN(MX35_PAD_D10),
835 IMX_PINCTRL_PIN(MX35_PAD_D9),
836 IMX_PINCTRL_PIN(MX35_PAD_D8),
837 IMX_PINCTRL_PIN(MX35_PAD_D7),
838 IMX_PINCTRL_PIN(MX35_PAD_D6),
839 IMX_PINCTRL_PIN(MX35_PAD_D5),
840 IMX_PINCTRL_PIN(MX35_PAD_D4),
841 IMX_PINCTRL_PIN(MX35_PAD_D3),
842 IMX_PINCTRL_PIN(MX35_PAD_D2),
843 IMX_PINCTRL_PIN(MX35_PAD_D1),
844 IMX_PINCTRL_PIN(MX35_PAD_D0),
845 IMX_PINCTRL_PIN(MX35_PAD_RESERVE56),
846 IMX_PINCTRL_PIN(MX35_PAD_RESERVE57),
847 IMX_PINCTRL_PIN(MX35_PAD_RESERVE58),
848 IMX_PINCTRL_PIN(MX35_PAD_RESERVE59),
849 IMX_PINCTRL_PIN(MX35_PAD_RESERVE60),
850 IMX_PINCTRL_PIN(MX35_PAD_RESERVE61),
851 IMX_PINCTRL_PIN(MX35_PAD_RESERVE62),
852 IMX_PINCTRL_PIN(MX35_PAD_RESERVE63),
853 IMX_PINCTRL_PIN(MX35_PAD_RESERVE64),
854 IMX_PINCTRL_PIN(MX35_PAD_RESERVE65),
855 IMX_PINCTRL_PIN(MX35_PAD_RESERVE66),
856 IMX_PINCTRL_PIN(MX35_PAD_RESERVE67),
857 IMX_PINCTRL_PIN(MX35_PAD_RESERVE68),
858 IMX_PINCTRL_PIN(MX35_PAD_RESERVE69),
859 IMX_PINCTRL_PIN(MX35_PAD_RESERVE70),
860 IMX_PINCTRL_PIN(MX35_PAD_RESERVE71),
861 IMX_PINCTRL_PIN(MX35_PAD_RESERVE72),
862 IMX_PINCTRL_PIN(MX35_PAD_RESERVE73),
863 IMX_PINCTRL_PIN(MX35_PAD_RESERVE74),
864 IMX_PINCTRL_PIN(MX35_PAD_RESERVE75),
865 IMX_PINCTRL_PIN(MX35_PAD_RESERVE76),
866 IMX_PINCTRL_PIN(MX35_PAD_RESERVE77),
867 IMX_PINCTRL_PIN(MX35_PAD_RESERVE78),
868 IMX_PINCTRL_PIN(MX35_PAD_RESERVE79),
869 IMX_PINCTRL_PIN(MX35_PAD_RESERVE80),
870 IMX_PINCTRL_PIN(MX35_PAD_RESERVE81),
871 IMX_PINCTRL_PIN(MX35_PAD_RESERVE82),
872 IMX_PINCTRL_PIN(MX35_PAD_RESERVE83),
873 IMX_PINCTRL_PIN(MX35_PAD_RESERVE84),
874 IMX_PINCTRL_PIN(MX35_PAD_RESERVE85),
875 IMX_PINCTRL_PIN(MX35_PAD_RESERVE86),
876 IMX_PINCTRL_PIN(MX35_PAD_RESERVE87),
877 IMX_PINCTRL_PIN(MX35_PAD_RESERVE88),
878 IMX_PINCTRL_PIN(MX35_PAD_RESERVE89),
879 IMX_PINCTRL_PIN(MX35_PAD_RESERVE90),
880 IMX_PINCTRL_PIN(MX35_PAD_RESERVE91),
881 IMX_PINCTRL_PIN(MX35_PAD_RESERVE92),
882 IMX_PINCTRL_PIN(MX35_PAD_RESERVE93),
883 IMX_PINCTRL_PIN(MX35_PAD_RESERVE94),
884 IMX_PINCTRL_PIN(MX35_PAD_RESERVE95),
885 IMX_PINCTRL_PIN(MX35_PAD_RESERVE96),
886 IMX_PINCTRL_PIN(MX35_PAD_RESERVE97),
887 IMX_PINCTRL_PIN(MX35_PAD_RESERVE98),
888 IMX_PINCTRL_PIN(MX35_PAD_RESERVE99),
889 IMX_PINCTRL_PIN(MX35_PAD_RESERVE100),
890 IMX_PINCTRL_PIN(MX35_PAD_RESERVE101),
891 IMX_PINCTRL_PIN(MX35_PAD_RESERVE102),
892 IMX_PINCTRL_PIN(MX35_PAD_RESERVE103),
893 IMX_PINCTRL_PIN(MX35_PAD_RESERVE104),
894 IMX_PINCTRL_PIN(MX35_PAD_RESERVE105),
895 IMX_PINCTRL_PIN(MX35_PAD_RTCK),
896 IMX_PINCTRL_PIN(MX35_PAD_TCK),
897 IMX_PINCTRL_PIN(MX35_PAD_TMS),
898 IMX_PINCTRL_PIN(MX35_PAD_TDI),
899 IMX_PINCTRL_PIN(MX35_PAD_TDO),
900 IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
901 IMX_PINCTRL_PIN(MX35_PAD_DE_B),
902 IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
903 IMX_PINCTRL_PIN(MX35_PAD_RESERVE106),
904 IMX_PINCTRL_PIN(MX35_PAD_RESERVE107),
905 IMX_PINCTRL_PIN(MX35_PAD_RESERVE108),
906 IMX_PINCTRL_PIN(MX35_PAD_RESERVE109),
907 IMX_PINCTRL_PIN(MX35_PAD_RESERVE110),
908 IMX_PINCTRL_PIN(MX35_PAD_RESERVE111),
909 IMX_PINCTRL_PIN(MX35_PAD_RESERVE112),
910 IMX_PINCTRL_PIN(MX35_PAD_RESERVE113),
911 IMX_PINCTRL_PIN(MX35_PAD_RESERVE114),
912 IMX_PINCTRL_PIN(MX35_PAD_RESERVE115),
913 IMX_PINCTRL_PIN(MX35_PAD_RESERVE116),
914 IMX_PINCTRL_PIN(MX35_PAD_RESERVE117),
915 IMX_PINCTRL_PIN(MX35_PAD_RESERVE118),
916 IMX_PINCTRL_PIN(MX35_PAD_RESERVE119),
917 IMX_PINCTRL_PIN(MX35_PAD_RESERVE120),
918 IMX_PINCTRL_PIN(MX35_PAD_RESERVE121),
919 IMX_PINCTRL_PIN(MX35_PAD_RESERVE122),
920 IMX_PINCTRL_PIN(MX35_PAD_RESERVE123),
921 IMX_PINCTRL_PIN(MX35_PAD_RESERVE124),
922 IMX_PINCTRL_PIN(MX35_PAD_RESERVE125),
923 IMX_PINCTRL_PIN(MX35_PAD_RESERVE126),
924 IMX_PINCTRL_PIN(MX35_PAD_RESERVE127),
925 IMX_PINCTRL_PIN(MX35_PAD_RESERVE128),
926 IMX_PINCTRL_PIN(MX35_PAD_RESERVE129),
927 IMX_PINCTRL_PIN(MX35_PAD_RESERVE130),
928 IMX_PINCTRL_PIN(MX35_PAD_RESERVE131),
929 IMX_PINCTRL_PIN(MX35_PAD_RESERVE132),
930 IMX_PINCTRL_PIN(MX35_PAD_RESERVE133),
931 IMX_PINCTRL_PIN(MX35_PAD_RESERVE134),
932 IMX_PINCTRL_PIN(MX35_PAD_RESERVE135),
933 IMX_PINCTRL_PIN(MX35_PAD_RESERVE136),
934 IMX_PINCTRL_PIN(MX35_PAD_RESERVE137),
935 IMX_PINCTRL_PIN(MX35_PAD_RESERVE138),
936 IMX_PINCTRL_PIN(MX35_PAD_RESERVE139),
937 IMX_PINCTRL_PIN(MX35_PAD_RESERVE140),
938 IMX_PINCTRL_PIN(MX35_PAD_RESERVE141),
939 IMX_PINCTRL_PIN(MX35_PAD_RESERVE142),
940 IMX_PINCTRL_PIN(MX35_PAD_RESERVE143),
941 IMX_PINCTRL_PIN(MX35_PAD_RESERVE144),
942 IMX_PINCTRL_PIN(MX35_PAD_RESERVE145),
943 IMX_PINCTRL_PIN(MX35_PAD_RESERVE146),
944 IMX_PINCTRL_PIN(MX35_PAD_RESERVE147),
945 IMX_PINCTRL_PIN(MX35_PAD_RESERVE148),
946 IMX_PINCTRL_PIN(MX35_PAD_RESERVE149),
947 IMX_PINCTRL_PIN(MX35_PAD_RESERVE150),
948 IMX_PINCTRL_PIN(MX35_PAD_RESERVE151),
949 IMX_PINCTRL_PIN(MX35_PAD_RESERVE152),
950 IMX_PINCTRL_PIN(MX35_PAD_RESERVE153),
951 IMX_PINCTRL_PIN(MX35_PAD_RESERVE154),
952 IMX_PINCTRL_PIN(MX35_PAD_RESERVE155),
953 IMX_PINCTRL_PIN(MX35_PAD_RESERVE156),
954 IMX_PINCTRL_PIN(MX35_PAD_RESERVE157),
955 IMX_PINCTRL_PIN(MX35_PAD_RESERVE158),
956 IMX_PINCTRL_PIN(MX35_PAD_RESERVE159),
957 IMX_PINCTRL_PIN(MX35_PAD_RESERVE160),
958 IMX_PINCTRL_PIN(MX35_PAD_RESERVE161),
959 IMX_PINCTRL_PIN(MX35_PAD_RESERVE162),
960 IMX_PINCTRL_PIN(MX35_PAD_RESERVE163),
961 IMX_PINCTRL_PIN(MX35_PAD_RESERVE164),
962 IMX_PINCTRL_PIN(MX35_PAD_RESERVE165),
963 IMX_PINCTRL_PIN(MX35_PAD_RESERVE166),
964 IMX_PINCTRL_PIN(MX35_PAD_RESERVE167),
965 IMX_PINCTRL_PIN(MX35_PAD_RESERVE168),
966 IMX_PINCTRL_PIN(MX35_PAD_RESERVE169),
967 IMX_PINCTRL_PIN(MX35_PAD_RESERVE170),
968 IMX_PINCTRL_PIN(MX35_PAD_RESERVE171),
969 IMX_PINCTRL_PIN(MX35_PAD_RESERVE172),
970 IMX_PINCTRL_PIN(MX35_PAD_RESERVE173),
971 IMX_PINCTRL_PIN(MX35_PAD_RESERVE174),
972 IMX_PINCTRL_PIN(MX35_PAD_RESERVE175),
973 IMX_PINCTRL_PIN(MX35_PAD_RESERVE176),
974 IMX_PINCTRL_PIN(MX35_PAD_RESERVE177),
975 IMX_PINCTRL_PIN(MX35_PAD_RESERVE178),
976 IMX_PINCTRL_PIN(MX35_PAD_RESERVE179),
977 IMX_PINCTRL_PIN(MX35_PAD_RESERVE180),
978 IMX_PINCTRL_PIN(MX35_PAD_RESERVE181),
979 IMX_PINCTRL_PIN(MX35_PAD_RESERVE182),
980 IMX_PINCTRL_PIN(MX35_PAD_RESERVE183),
981 IMX_PINCTRL_PIN(MX35_PAD_RESERVE184),
982 IMX_PINCTRL_PIN(MX35_PAD_RESERVE185),
983 IMX_PINCTRL_PIN(MX35_PAD_RESERVE186),
984 IMX_PINCTRL_PIN(MX35_PAD_RESERVE187),
985 IMX_PINCTRL_PIN(MX35_PAD_RESERVE188),
986 IMX_PINCTRL_PIN(MX35_PAD_RESERVE189),
987 IMX_PINCTRL_PIN(MX35_PAD_RESERVE190),
988 IMX_PINCTRL_PIN(MX35_PAD_RESERVE191),
989 IMX_PINCTRL_PIN(MX35_PAD_RESERVE192),
990 IMX_PINCTRL_PIN(MX35_PAD_RESERVE193),
991 IMX_PINCTRL_PIN(MX35_PAD_RESERVE194),
992 IMX_PINCTRL_PIN(MX35_PAD_RESERVE195),
993 IMX_PINCTRL_PIN(MX35_PAD_RESERVE196),
994 IMX_PINCTRL_PIN(MX35_PAD_RESERVE197),
995 IMX_PINCTRL_PIN(MX35_PAD_RESERVE198),
996 IMX_PINCTRL_PIN(MX35_PAD_RESERVE199),
997 IMX_PINCTRL_PIN(MX35_PAD_RESERVE200),
998 IMX_PINCTRL_PIN(MX35_PAD_RESERVE201),
1551 IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK), 999 IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK),
1552 IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE), 1000 IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
1553}; 1001};
@@ -1555,8 +1003,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
1555static struct imx_pinctrl_soc_info imx35_pinctrl_info = { 1003static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
1556 .pins = imx35_pinctrl_pads, 1004 .pins = imx35_pinctrl_pads,
1557 .npins = ARRAY_SIZE(imx35_pinctrl_pads), 1005 .npins = ARRAY_SIZE(imx35_pinctrl_pads),
1558 .pin_regs = imx35_pin_regs,
1559 .npin_regs = ARRAY_SIZE(imx35_pin_regs),
1560}; 1006};
1561 1007
1562static struct of_device_id imx35_pinctrl_of_match[] = { 1008static struct of_device_id imx35_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
index 9a92aaad150f..db268b920079 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -23,1015 +23,400 @@
23#include "pinctrl-imx.h" 23#include "pinctrl-imx.h"
24 24
25enum imx51_pads { 25enum imx51_pads {
26 MX51_PAD_EIM_D16 = 0, 26 MX51_PAD_RESERVE0 = 0,
27 MX51_PAD_EIM_D17 = 1, 27 MX51_PAD_RESERVE1 = 1,
28 MX51_PAD_EIM_D18 = 2, 28 MX51_PAD_RESERVE2 = 2,
29 MX51_PAD_EIM_D19 = 3, 29 MX51_PAD_RESERVE3 = 3,
30 MX51_PAD_EIM_D20 = 4, 30 MX51_PAD_RESERVE4 = 4,
31 MX51_PAD_EIM_D21 = 5, 31 MX51_PAD_RESERVE5 = 5,
32 MX51_PAD_EIM_D22 = 6, 32 MX51_PAD_RESERVE6 = 6,
33 MX51_PAD_EIM_D23 = 7, 33 MX51_PAD_EIM_DA0 = 7,
34 MX51_PAD_EIM_D24 = 8, 34 MX51_PAD_EIM_DA1 = 8,
35 MX51_PAD_EIM_D25 = 9, 35 MX51_PAD_EIM_DA2 = 9,
36 MX51_PAD_EIM_D26 = 10, 36 MX51_PAD_EIM_DA3 = 10,
37 MX51_PAD_EIM_D27 = 11, 37 MX51_PAD_EIM_DA4 = 11,
38 MX51_PAD_EIM_D28 = 12, 38 MX51_PAD_EIM_DA5 = 12,
39 MX51_PAD_EIM_D29 = 13, 39 MX51_PAD_EIM_DA6 = 13,
40 MX51_PAD_EIM_D30 = 14, 40 MX51_PAD_EIM_DA7 = 14,
41 MX51_PAD_EIM_D31 = 15, 41 MX51_PAD_EIM_DA8 = 15,
42 MX51_PAD_EIM_A16 = 16, 42 MX51_PAD_EIM_DA9 = 16,
43 MX51_PAD_EIM_A17 = 17, 43 MX51_PAD_EIM_DA10 = 17,
44 MX51_PAD_EIM_A18 = 18, 44 MX51_PAD_EIM_DA11 = 18,
45 MX51_PAD_EIM_A19 = 19, 45 MX51_PAD_EIM_DA12 = 19,
46 MX51_PAD_EIM_A20 = 20, 46 MX51_PAD_EIM_DA13 = 20,
47 MX51_PAD_EIM_A21 = 21, 47 MX51_PAD_EIM_DA14 = 21,
48 MX51_PAD_EIM_A22 = 22, 48 MX51_PAD_EIM_DA15 = 22,
49 MX51_PAD_EIM_A23 = 23, 49 MX51_PAD_EIM_D16 = 23,
50 MX51_PAD_EIM_A24 = 24, 50 MX51_PAD_EIM_D17 = 24,
51 MX51_PAD_EIM_A25 = 25, 51 MX51_PAD_EIM_D18 = 25,
52 MX51_PAD_EIM_A26 = 26, 52 MX51_PAD_EIM_D19 = 26,
53 MX51_PAD_EIM_A27 = 27, 53 MX51_PAD_EIM_D20 = 27,
54 MX51_PAD_EIM_EB0 = 28, 54 MX51_PAD_EIM_D21 = 28,
55 MX51_PAD_EIM_EB1 = 29, 55 MX51_PAD_EIM_D22 = 29,
56 MX51_PAD_EIM_EB2 = 30, 56 MX51_PAD_EIM_D23 = 30,
57 MX51_PAD_EIM_EB3 = 31, 57 MX51_PAD_EIM_D24 = 31,
58 MX51_PAD_EIM_OE = 32, 58 MX51_PAD_EIM_D25 = 32,
59 MX51_PAD_EIM_CS0 = 33, 59 MX51_PAD_EIM_D26 = 33,
60 MX51_PAD_EIM_CS1 = 34, 60 MX51_PAD_EIM_D27 = 34,
61 MX51_PAD_EIM_CS2 = 35, 61 MX51_PAD_EIM_D28 = 35,
62 MX51_PAD_EIM_CS3 = 36, 62 MX51_PAD_EIM_D29 = 36,
63 MX51_PAD_EIM_CS4 = 37, 63 MX51_PAD_EIM_D30 = 37,
64 MX51_PAD_EIM_CS5 = 38, 64 MX51_PAD_EIM_D31 = 38,
65 MX51_PAD_EIM_DTACK = 39, 65 MX51_PAD_EIM_A16 = 39,
66 MX51_PAD_EIM_LBA = 40, 66 MX51_PAD_EIM_A17 = 40,
67 MX51_PAD_EIM_CRE = 41, 67 MX51_PAD_EIM_A18 = 41,
68 MX51_PAD_DRAM_CS1 = 42, 68 MX51_PAD_EIM_A19 = 42,
69 MX51_PAD_NANDF_WE_B = 43, 69 MX51_PAD_EIM_A20 = 43,
70 MX51_PAD_NANDF_RE_B = 44, 70 MX51_PAD_EIM_A21 = 44,
71 MX51_PAD_NANDF_ALE = 45, 71 MX51_PAD_EIM_A22 = 45,
72 MX51_PAD_NANDF_CLE = 46, 72 MX51_PAD_EIM_A23 = 46,
73 MX51_PAD_NANDF_WP_B = 47, 73 MX51_PAD_EIM_A24 = 47,
74 MX51_PAD_NANDF_RB0 = 48, 74 MX51_PAD_EIM_A25 = 48,
75 MX51_PAD_NANDF_RB1 = 49, 75 MX51_PAD_EIM_A26 = 49,
76 MX51_PAD_NANDF_RB2 = 50, 76 MX51_PAD_EIM_A27 = 50,
77 MX51_PAD_NANDF_RB3 = 51, 77 MX51_PAD_EIM_EB0 = 51,
78 MX51_PAD_GPIO_NAND = 52, 78 MX51_PAD_EIM_EB1 = 52,
79 MX51_PAD_NANDF_CS0 = 53, 79 MX51_PAD_EIM_EB2 = 53,
80 MX51_PAD_NANDF_CS1 = 54, 80 MX51_PAD_EIM_EB3 = 54,
81 MX51_PAD_NANDF_CS2 = 55, 81 MX51_PAD_EIM_OE = 55,
82 MX51_PAD_NANDF_CS3 = 56, 82 MX51_PAD_EIM_CS0 = 56,
83 MX51_PAD_NANDF_CS4 = 57, 83 MX51_PAD_EIM_CS1 = 57,
84 MX51_PAD_NANDF_CS5 = 58, 84 MX51_PAD_EIM_CS2 = 58,
85 MX51_PAD_NANDF_CS6 = 59, 85 MX51_PAD_EIM_CS3 = 59,
86 MX51_PAD_NANDF_CS7 = 60, 86 MX51_PAD_EIM_CS4 = 60,
87 MX51_PAD_NANDF_RDY_INT = 61, 87 MX51_PAD_EIM_CS5 = 61,
88 MX51_PAD_NANDF_D15 = 62, 88 MX51_PAD_EIM_DTACK = 62,
89 MX51_PAD_NANDF_D14 = 63, 89 MX51_PAD_EIM_LBA = 63,
90 MX51_PAD_NANDF_D13 = 64, 90 MX51_PAD_EIM_CRE = 64,
91 MX51_PAD_NANDF_D12 = 65, 91 MX51_PAD_DRAM_CS1 = 65,
92 MX51_PAD_NANDF_D11 = 66, 92 MX51_PAD_NANDF_WE_B = 66,
93 MX51_PAD_NANDF_D10 = 67, 93 MX51_PAD_NANDF_RE_B = 67,
94 MX51_PAD_NANDF_D9 = 68, 94 MX51_PAD_NANDF_ALE = 68,
95 MX51_PAD_NANDF_D8 = 69, 95 MX51_PAD_NANDF_CLE = 69,
96 MX51_PAD_NANDF_D7 = 70, 96 MX51_PAD_NANDF_WP_B = 70,
97 MX51_PAD_NANDF_D6 = 71, 97 MX51_PAD_NANDF_RB0 = 71,
98 MX51_PAD_NANDF_D5 = 72, 98 MX51_PAD_NANDF_RB1 = 72,
99 MX51_PAD_NANDF_D4 = 73, 99 MX51_PAD_NANDF_RB2 = 73,
100 MX51_PAD_NANDF_D3 = 74, 100 MX51_PAD_NANDF_RB3 = 74,
101 MX51_PAD_NANDF_D2 = 75, 101 MX51_PAD_GPIO_NAND = 75,
102 MX51_PAD_NANDF_D1 = 76, 102 MX51_PAD_NANDF_CS0 = 76,
103 MX51_PAD_NANDF_D0 = 77, 103 MX51_PAD_NANDF_CS1 = 77,
104 MX51_PAD_CSI1_D8 = 78, 104 MX51_PAD_NANDF_CS2 = 78,
105 MX51_PAD_CSI1_D9 = 79, 105 MX51_PAD_NANDF_CS3 = 79,
106 MX51_PAD_CSI1_D10 = 80, 106 MX51_PAD_NANDF_CS4 = 80,
107 MX51_PAD_CSI1_D11 = 81, 107 MX51_PAD_NANDF_CS5 = 81,
108 MX51_PAD_CSI1_D12 = 82, 108 MX51_PAD_NANDF_CS6 = 82,
109 MX51_PAD_CSI1_D13 = 83, 109 MX51_PAD_NANDF_CS7 = 83,
110 MX51_PAD_CSI1_D14 = 84, 110 MX51_PAD_NANDF_RDY_INT = 84,
111 MX51_PAD_CSI1_D15 = 85, 111 MX51_PAD_NANDF_D15 = 85,
112 MX51_PAD_CSI1_D16 = 86, 112 MX51_PAD_NANDF_D14 = 86,
113 MX51_PAD_CSI1_D17 = 87, 113 MX51_PAD_NANDF_D13 = 87,
114 MX51_PAD_CSI1_D18 = 88, 114 MX51_PAD_NANDF_D12 = 88,
115 MX51_PAD_CSI1_D19 = 89, 115 MX51_PAD_NANDF_D11 = 89,
116 MX51_PAD_CSI1_VSYNC = 90, 116 MX51_PAD_NANDF_D10 = 90,
117 MX51_PAD_CSI1_HSYNC = 91, 117 MX51_PAD_NANDF_D9 = 91,
118 MX51_PAD_CSI1_PIXCLK = 92, 118 MX51_PAD_NANDF_D8 = 92,
119 MX51_PAD_CSI1_MCLK = 93, 119 MX51_PAD_NANDF_D7 = 93,
120 MX51_PAD_CSI2_D12 = 94, 120 MX51_PAD_NANDF_D6 = 94,
121 MX51_PAD_CSI2_D13 = 95, 121 MX51_PAD_NANDF_D5 = 95,
122 MX51_PAD_CSI2_D14 = 96, 122 MX51_PAD_NANDF_D4 = 96,
123 MX51_PAD_CSI2_D15 = 97, 123 MX51_PAD_NANDF_D3 = 97,
124 MX51_PAD_CSI2_D16 = 98, 124 MX51_PAD_NANDF_D2 = 98,
125 MX51_PAD_CSI2_D17 = 99, 125 MX51_PAD_NANDF_D1 = 99,
126 MX51_PAD_CSI2_D18 = 100, 126 MX51_PAD_NANDF_D0 = 100,
127 MX51_PAD_CSI2_D19 = 101, 127 MX51_PAD_CSI1_D8 = 101,
128 MX51_PAD_CSI2_VSYNC = 102, 128 MX51_PAD_CSI1_D9 = 102,
129 MX51_PAD_CSI2_HSYNC = 103, 129 MX51_PAD_CSI1_D10 = 103,
130 MX51_PAD_CSI2_PIXCLK = 104, 130 MX51_PAD_CSI1_D11 = 104,
131 MX51_PAD_I2C1_CLK = 105, 131 MX51_PAD_CSI1_D12 = 105,
132 MX51_PAD_I2C1_DAT = 106, 132 MX51_PAD_CSI1_D13 = 106,
133 MX51_PAD_AUD3_BB_TXD = 107, 133 MX51_PAD_CSI1_D14 = 107,
134 MX51_PAD_AUD3_BB_RXD = 108, 134 MX51_PAD_CSI1_D15 = 108,
135 MX51_PAD_AUD3_BB_CK = 109, 135 MX51_PAD_CSI1_D16 = 109,
136 MX51_PAD_AUD3_BB_FS = 110, 136 MX51_PAD_CSI1_D17 = 110,
137 MX51_PAD_CSPI1_MOSI = 111, 137 MX51_PAD_CSI1_D18 = 111,
138 MX51_PAD_CSPI1_MISO = 112, 138 MX51_PAD_CSI1_D19 = 112,
139 MX51_PAD_CSPI1_SS0 = 113, 139 MX51_PAD_CSI1_VSYNC = 113,
140 MX51_PAD_CSPI1_SS1 = 114, 140 MX51_PAD_CSI1_HSYNC = 114,
141 MX51_PAD_CSPI1_RDY = 115, 141 MX51_PAD_CSI2_D12 = 115,
142 MX51_PAD_CSPI1_SCLK = 116, 142 MX51_PAD_CSI2_D13 = 116,
143 MX51_PAD_UART1_RXD = 117, 143 MX51_PAD_CSI2_D14 = 117,
144 MX51_PAD_UART1_TXD = 118, 144 MX51_PAD_CSI2_D15 = 118,
145 MX51_PAD_UART1_RTS = 119, 145 MX51_PAD_CSI2_D16 = 119,
146 MX51_PAD_UART1_CTS = 120, 146 MX51_PAD_CSI2_D17 = 120,
147 MX51_PAD_UART2_RXD = 121, 147 MX51_PAD_CSI2_D18 = 121,
148 MX51_PAD_UART2_TXD = 122, 148 MX51_PAD_CSI2_D19 = 122,
149 MX51_PAD_UART3_RXD = 123, 149 MX51_PAD_CSI2_VSYNC = 123,
150 MX51_PAD_UART3_TXD = 124, 150 MX51_PAD_CSI2_HSYNC = 124,
151 MX51_PAD_OWIRE_LINE = 125, 151 MX51_PAD_CSI2_PIXCLK = 125,
152 MX51_PAD_KEY_ROW0 = 126, 152 MX51_PAD_I2C1_CLK = 126,
153 MX51_PAD_KEY_ROW1 = 127, 153 MX51_PAD_I2C1_DAT = 127,
154 MX51_PAD_KEY_ROW2 = 128, 154 MX51_PAD_AUD3_BB_TXD = 128,
155 MX51_PAD_KEY_ROW3 = 129, 155 MX51_PAD_AUD3_BB_RXD = 129,
156 MX51_PAD_KEY_COL0 = 130, 156 MX51_PAD_AUD3_BB_CK = 130,
157 MX51_PAD_KEY_COL1 = 131, 157 MX51_PAD_AUD3_BB_FS = 131,
158 MX51_PAD_KEY_COL2 = 132, 158 MX51_PAD_CSPI1_MOSI = 132,
159 MX51_PAD_KEY_COL3 = 133, 159 MX51_PAD_CSPI1_MISO = 133,
160 MX51_PAD_KEY_COL4 = 134, 160 MX51_PAD_CSPI1_SS0 = 134,
161 MX51_PAD_KEY_COL5 = 135, 161 MX51_PAD_CSPI1_SS1 = 135,
162 MX51_PAD_USBH1_CLK = 136, 162 MX51_PAD_CSPI1_RDY = 136,
163 MX51_PAD_USBH1_DIR = 137, 163 MX51_PAD_CSPI1_SCLK = 137,
164 MX51_PAD_USBH1_STP = 138, 164 MX51_PAD_UART1_RXD = 138,
165 MX51_PAD_USBH1_NXT = 139, 165 MX51_PAD_UART1_TXD = 139,
166 MX51_PAD_USBH1_DATA0 = 140, 166 MX51_PAD_UART1_RTS = 140,
167 MX51_PAD_USBH1_DATA1 = 141, 167 MX51_PAD_UART1_CTS = 141,
168 MX51_PAD_USBH1_DATA2 = 142, 168 MX51_PAD_UART2_RXD = 142,
169 MX51_PAD_USBH1_DATA3 = 143, 169 MX51_PAD_UART2_TXD = 143,
170 MX51_PAD_USBH1_DATA4 = 144, 170 MX51_PAD_UART3_RXD = 144,
171 MX51_PAD_USBH1_DATA5 = 145, 171 MX51_PAD_UART3_TXD = 145,
172 MX51_PAD_USBH1_DATA6 = 146, 172 MX51_PAD_OWIRE_LINE = 146,
173 MX51_PAD_USBH1_DATA7 = 147, 173 MX51_PAD_KEY_ROW0 = 147,
174 MX51_PAD_DI1_PIN11 = 148, 174 MX51_PAD_KEY_ROW1 = 148,
175 MX51_PAD_DI1_PIN12 = 149, 175 MX51_PAD_KEY_ROW2 = 149,
176 MX51_PAD_DI1_PIN13 = 150, 176 MX51_PAD_KEY_ROW3 = 150,
177 MX51_PAD_DI1_D0_CS = 151, 177 MX51_PAD_KEY_COL0 = 151,
178 MX51_PAD_DI1_D1_CS = 152, 178 MX51_PAD_KEY_COL1 = 152,
179 MX51_PAD_DISPB2_SER_DIN = 153, 179 MX51_PAD_KEY_COL2 = 153,
180 MX51_PAD_DISPB2_SER_DIO = 154, 180 MX51_PAD_KEY_COL3 = 154,
181 MX51_PAD_DISPB2_SER_CLK = 155, 181 MX51_PAD_KEY_COL4 = 155,
182 MX51_PAD_DISPB2_SER_RS = 156, 182 MX51_PAD_KEY_COL5 = 156,
183 MX51_PAD_DISP1_DAT0 = 157, 183 MX51_PAD_RESERVE7 = 157,
184 MX51_PAD_DISP1_DAT1 = 158, 184 MX51_PAD_USBH1_CLK = 158,
185 MX51_PAD_DISP1_DAT2 = 159, 185 MX51_PAD_USBH1_DIR = 159,
186 MX51_PAD_DISP1_DAT3 = 160, 186 MX51_PAD_USBH1_STP = 160,
187 MX51_PAD_DISP1_DAT4 = 161, 187 MX51_PAD_USBH1_NXT = 161,
188 MX51_PAD_DISP1_DAT5 = 162, 188 MX51_PAD_USBH1_DATA0 = 162,
189 MX51_PAD_DISP1_DAT6 = 163, 189 MX51_PAD_USBH1_DATA1 = 163,
190 MX51_PAD_DISP1_DAT7 = 164, 190 MX51_PAD_USBH1_DATA2 = 164,
191 MX51_PAD_DISP1_DAT8 = 165, 191 MX51_PAD_USBH1_DATA3 = 165,
192 MX51_PAD_DISP1_DAT9 = 166, 192 MX51_PAD_USBH1_DATA4 = 166,
193 MX51_PAD_DISP1_DAT10 = 167, 193 MX51_PAD_USBH1_DATA5 = 167,
194 MX51_PAD_DISP1_DAT11 = 168, 194 MX51_PAD_USBH1_DATA6 = 168,
195 MX51_PAD_DISP1_DAT12 = 169, 195 MX51_PAD_USBH1_DATA7 = 169,
196 MX51_PAD_DISP1_DAT13 = 170, 196 MX51_PAD_DI1_PIN11 = 170,
197 MX51_PAD_DISP1_DAT14 = 171, 197 MX51_PAD_DI1_PIN12 = 171,
198 MX51_PAD_DISP1_DAT15 = 172, 198 MX51_PAD_DI1_PIN13 = 172,
199 MX51_PAD_DISP1_DAT16 = 173, 199 MX51_PAD_DI1_D0_CS = 173,
200 MX51_PAD_DISP1_DAT17 = 174, 200 MX51_PAD_DI1_D1_CS = 174,
201 MX51_PAD_DISP1_DAT18 = 175, 201 MX51_PAD_DISPB2_SER_DIN = 175,
202 MX51_PAD_DISP1_DAT19 = 176, 202 MX51_PAD_DISPB2_SER_DIO = 176,
203 MX51_PAD_DISP1_DAT20 = 177, 203 MX51_PAD_DISPB2_SER_CLK = 177,
204 MX51_PAD_DISP1_DAT21 = 178, 204 MX51_PAD_DISPB2_SER_RS = 178,
205 MX51_PAD_DISP1_DAT22 = 179, 205 MX51_PAD_DISP1_DAT0 = 179,
206 MX51_PAD_DISP1_DAT23 = 180, 206 MX51_PAD_DISP1_DAT1 = 180,
207 MX51_PAD_DI1_PIN3 = 181, 207 MX51_PAD_DISP1_DAT2 = 181,
208 MX51_PAD_DI1_PIN2 = 182, 208 MX51_PAD_DISP1_DAT3 = 182,
209 MX51_PAD_DI_GP2 = 183, 209 MX51_PAD_DISP1_DAT4 = 183,
210 MX51_PAD_DI_GP3 = 184, 210 MX51_PAD_DISP1_DAT5 = 184,
211 MX51_PAD_DI2_PIN4 = 185, 211 MX51_PAD_DISP1_DAT6 = 185,
212 MX51_PAD_DI2_PIN2 = 186, 212 MX51_PAD_DISP1_DAT7 = 186,
213 MX51_PAD_DI2_PIN3 = 187, 213 MX51_PAD_DISP1_DAT8 = 187,
214 MX51_PAD_DI2_DISP_CLK = 188, 214 MX51_PAD_DISP1_DAT9 = 188,
215 MX51_PAD_DI_GP4 = 189, 215 MX51_PAD_DISP1_DAT10 = 189,
216 MX51_PAD_DISP2_DAT0 = 190, 216 MX51_PAD_DISP1_DAT11 = 190,
217 MX51_PAD_DISP2_DAT1 = 191, 217 MX51_PAD_DISP1_DAT12 = 191,
218 MX51_PAD_DISP2_DAT2 = 192, 218 MX51_PAD_DISP1_DAT13 = 192,
219 MX51_PAD_DISP2_DAT3 = 193, 219 MX51_PAD_DISP1_DAT14 = 193,
220 MX51_PAD_DISP2_DAT4 = 194, 220 MX51_PAD_DISP1_DAT15 = 194,
221 MX51_PAD_DISP2_DAT5 = 195, 221 MX51_PAD_DISP1_DAT16 = 195,
222 MX51_PAD_DISP2_DAT6 = 196, 222 MX51_PAD_DISP1_DAT17 = 196,
223 MX51_PAD_DISP2_DAT7 = 197, 223 MX51_PAD_DISP1_DAT18 = 197,
224 MX51_PAD_DISP2_DAT8 = 198, 224 MX51_PAD_DISP1_DAT19 = 198,
225 MX51_PAD_DISP2_DAT9 = 199, 225 MX51_PAD_DISP1_DAT20 = 199,
226 MX51_PAD_DISP2_DAT10 = 200, 226 MX51_PAD_DISP1_DAT21 = 200,
227 MX51_PAD_DISP2_DAT11 = 201, 227 MX51_PAD_DISP1_DAT22 = 201,
228 MX51_PAD_DISP2_DAT12 = 202, 228 MX51_PAD_DISP1_DAT23 = 202,
229 MX51_PAD_DISP2_DAT13 = 203, 229 MX51_PAD_DI1_PIN3 = 203,
230 MX51_PAD_DISP2_DAT14 = 204, 230 MX51_PAD_DI1_PIN2 = 204,
231 MX51_PAD_DISP2_DAT15 = 205, 231 MX51_PAD_RESERVE8 = 205,
232 MX51_PAD_SD1_CMD = 206, 232 MX51_PAD_DI_GP2 = 206,
233 MX51_PAD_SD1_CLK = 207, 233 MX51_PAD_DI_GP3 = 207,
234 MX51_PAD_SD1_DATA0 = 208, 234 MX51_PAD_DI2_PIN4 = 208,
235 MX51_PAD_EIM_DA0 = 209, 235 MX51_PAD_DI2_PIN2 = 209,
236 MX51_PAD_EIM_DA1 = 210, 236 MX51_PAD_DI2_PIN3 = 210,
237 MX51_PAD_EIM_DA2 = 211, 237 MX51_PAD_DI2_DISP_CLK = 211,
238 MX51_PAD_EIM_DA3 = 212, 238 MX51_PAD_DI_GP4 = 212,
239 MX51_PAD_SD1_DATA1 = 213, 239 MX51_PAD_DISP2_DAT0 = 213,
240 MX51_PAD_EIM_DA4 = 214, 240 MX51_PAD_DISP2_DAT1 = 214,
241 MX51_PAD_EIM_DA5 = 215, 241 MX51_PAD_DISP2_DAT2 = 215,
242 MX51_PAD_EIM_DA6 = 216, 242 MX51_PAD_DISP2_DAT3 = 216,
243 MX51_PAD_EIM_DA7 = 217, 243 MX51_PAD_DISP2_DAT4 = 217,
244 MX51_PAD_SD1_DATA2 = 218, 244 MX51_PAD_DISP2_DAT5 = 218,
245 MX51_PAD_EIM_DA10 = 219, 245 MX51_PAD_DISP2_DAT6 = 219,
246 MX51_PAD_EIM_DA11 = 220, 246 MX51_PAD_DISP2_DAT7 = 220,
247 MX51_PAD_EIM_DA8 = 221, 247 MX51_PAD_DISP2_DAT8 = 221,
248 MX51_PAD_EIM_DA9 = 222, 248 MX51_PAD_DISP2_DAT9 = 222,
249 MX51_PAD_SD1_DATA3 = 223, 249 MX51_PAD_DISP2_DAT10 = 223,
250 MX51_PAD_GPIO1_0 = 224, 250 MX51_PAD_DISP2_DAT11 = 224,
251 MX51_PAD_GPIO1_1 = 225, 251 MX51_PAD_DISP2_DAT12 = 225,
252 MX51_PAD_EIM_DA12 = 226, 252 MX51_PAD_DISP2_DAT13 = 226,
253 MX51_PAD_EIM_DA13 = 227, 253 MX51_PAD_DISP2_DAT14 = 227,
254 MX51_PAD_EIM_DA14 = 228, 254 MX51_PAD_DISP2_DAT15 = 228,
255 MX51_PAD_EIM_DA15 = 229, 255 MX51_PAD_SD1_CMD = 229,
256 MX51_PAD_SD2_CMD = 230, 256 MX51_PAD_SD1_CLK = 230,
257 MX51_PAD_SD2_CLK = 231, 257 MX51_PAD_SD1_DATA0 = 231,
258 MX51_PAD_SD2_DATA0 = 232, 258 MX51_PAD_SD1_DATA1 = 232,
259 MX51_PAD_SD2_DATA1 = 233, 259 MX51_PAD_SD1_DATA2 = 233,
260 MX51_PAD_SD2_DATA2 = 234, 260 MX51_PAD_SD1_DATA3 = 234,
261 MX51_PAD_SD2_DATA3 = 235, 261 MX51_PAD_GPIO1_0 = 235,
262 MX51_PAD_GPIO1_2 = 236, 262 MX51_PAD_GPIO1_1 = 236,
263 MX51_PAD_GPIO1_3 = 237, 263 MX51_PAD_SD2_CMD = 237,
264 MX51_PAD_PMIC_INT_REQ = 238, 264 MX51_PAD_SD2_CLK = 238,
265 MX51_PAD_GPIO1_4 = 239, 265 MX51_PAD_SD2_DATA0 = 239,
266 MX51_PAD_GPIO1_5 = 240, 266 MX51_PAD_SD2_DATA1 = 240,
267 MX51_PAD_GPIO1_6 = 241, 267 MX51_PAD_SD2_DATA2 = 241,
268 MX51_PAD_GPIO1_7 = 242, 268 MX51_PAD_SD2_DATA3 = 242,
269 MX51_PAD_GPIO1_8 = 243, 269 MX51_PAD_GPIO1_2 = 243,
270 MX51_PAD_GPIO1_9 = 244, 270 MX51_PAD_GPIO1_3 = 244,
271}; 271 MX51_PAD_PMIC_INT_REQ = 245,
272 272 MX51_PAD_GPIO1_4 = 246,
273/* imx51 register maps */ 273 MX51_PAD_GPIO1_5 = 247,
274static struct imx_pin_reg imx51_pin_regs[] = { 274 MX51_PAD_GPIO1_6 = 248,
275 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /* MX51_PAD_EIM_D16__AUD4_RXFS */ 275 MX51_PAD_GPIO1_7 = 249,
276 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 7, 0x8d8, 0), /* MX51_PAD_EIM_D16__AUD5_TXD */ 276 MX51_PAD_GPIO1_8 = 250,
277 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 0, 0x000, 0), /* MX51_PAD_EIM_D16__EIM_D16 */ 277 MX51_PAD_GPIO1_9 = 251,
278 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 1, 0x000, 0), /* MX51_PAD_EIM_D16__GPIO2_0 */ 278 MX51_PAD_RESERVE9 = 252,
279 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 4, 0x9b4, 0), /* MX51_PAD_EIM_D16__I2C1_SDA */ 279 MX51_PAD_RESERVE10 = 253,
280 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 3, 0x000, 0), /* MX51_PAD_EIM_D16__UART2_CTS */ 280 MX51_PAD_RESERVE11 = 254,
281 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 2, 0x000, 0), /* MX51_PAD_EIM_D16__USBH2_DATA0 */ 281 MX51_PAD_RESERVE12 = 255,
282 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 7, 0x8d4, 0), /* MX51_PAD_EIM_D17__AUD5_RXD */ 282 MX51_PAD_RESERVE13 = 256,
283 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 0, 0x000, 0), /* MX51_PAD_EIM_D17__EIM_D17 */ 283 MX51_PAD_RESERVE14 = 257,
284 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 1, 0x000, 0), /* MX51_PAD_EIM_D17__GPIO2_1 */ 284 MX51_PAD_RESERVE15 = 258,
285 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 3, 0x9ec, 0), /* MX51_PAD_EIM_D17__UART2_RXD */ 285 MX51_PAD_RESERVE16 = 259,
286 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 4, 0x000, 0), /* MX51_PAD_EIM_D17__UART3_CTS */ 286 MX51_PAD_RESERVE17 = 260,
287 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 2, 0x000, 0), /* MX51_PAD_EIM_D17__USBH2_DATA1 */ 287 MX51_PAD_RESERVE18 = 261,
288 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 7, 0x8e4, 0), /* MX51_PAD_EIM_D18__AUD5_TXC */ 288 MX51_PAD_RESERVE19 = 262,
289 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 0, 0x000, 0), /* MX51_PAD_EIM_D18__EIM_D18 */ 289 MX51_PAD_RESERVE20 = 263,
290 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 1, 0x000, 0), /* MX51_PAD_EIM_D18__GPIO2_2 */ 290 MX51_PAD_RESERVE21 = 264,
291 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 3, 0x000, 0), /* MX51_PAD_EIM_D18__UART2_TXD */ 291 MX51_PAD_RESERVE22 = 265,
292 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 4, 0x9f0, 1), /* MX51_PAD_EIM_D18__UART3_RTS */ 292 MX51_PAD_RESERVE23 = 266,
293 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 2, 0x000, 0), /* MX51_PAD_EIM_D18__USBH2_DATA2 */ 293 MX51_PAD_RESERVE24 = 267,
294 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 5, 0x000, 0), /* MX51_PAD_EIM_D19__AUD4_RXC */ 294 MX51_PAD_RESERVE25 = 268,
295 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 7, 0x8e8, 0), /* MX51_PAD_EIM_D19__AUD5_TXFS */ 295 MX51_PAD_RESERVE26 = 269,
296 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 0, 0x000, 0), /* MX51_PAD_EIM_D19__EIM_D19 */ 296 MX51_PAD_RESERVE27 = 270,
297 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 1, 0x000, 0), /* MX51_PAD_EIM_D19__GPIO2_3 */ 297 MX51_PAD_RESERVE28 = 271,
298 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 4, 0x9b0, 0), /* MX51_PAD_EIM_D19__I2C1_SCL */ 298 MX51_PAD_RESERVE29 = 272,
299 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 3, 0x9e8, 1), /* MX51_PAD_EIM_D19__UART2_RTS */ 299 MX51_PAD_RESERVE30 = 273,
300 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 2, 0x000, 0), /* MX51_PAD_EIM_D19__USBH2_DATA3 */ 300 MX51_PAD_RESERVE31 = 274,
301 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 5, 0x8c8, 0), /* MX51_PAD_EIM_D20__AUD4_TXD */ 301 MX51_PAD_RESERVE32 = 275,
302 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 0, 0x000, 0), /* MX51_PAD_EIM_D20__EIM_D20 */ 302 MX51_PAD_RESERVE33 = 276,
303 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 1, 0x000, 0), /* MX51_PAD_EIM_D20__GPIO2_4 */ 303 MX51_PAD_RESERVE34 = 277,
304 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 4, 0x000, 0), /* MX51_PAD_EIM_D20__SRTC_ALARM_DEB */ 304 MX51_PAD_RESERVE35 = 278,
305 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 2, 0x000, 0), /* MX51_PAD_EIM_D20__USBH2_DATA4 */ 305 MX51_PAD_RESERVE36 = 279,
306 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 5, 0x8c4, 0), /* MX51_PAD_EIM_D21__AUD4_RXD */ 306 MX51_PAD_RESERVE37 = 280,
307 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 0, 0x000, 0), /* MX51_PAD_EIM_D21__EIM_D21 */ 307 MX51_PAD_RESERVE38 = 281,
308 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 1, 0x000, 0), /* MX51_PAD_EIM_D21__GPIO2_5 */ 308 MX51_PAD_RESERVE39 = 282,
309 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 3, 0x000, 0), /* MX51_PAD_EIM_D21__SRTC_ALARM_DEB */ 309 MX51_PAD_RESERVE40 = 283,
310 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 2, 0x000, 0), /* MX51_PAD_EIM_D21__USBH2_DATA5 */ 310 MX51_PAD_RESERVE41 = 284,
311 IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 5, 0x8cc, 0), /* MX51_PAD_EIM_D22__AUD4_TXC */ 311 MX51_PAD_RESERVE42 = 285,
312 IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 0, 0x000, 0), /* MX51_PAD_EIM_D22__EIM_D22 */ 312 MX51_PAD_RESERVE43 = 286,
313 IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 1, 0x000, 0), /* MX51_PAD_EIM_D22__GPIO2_6 */ 313 MX51_PAD_RESERVE44 = 287,
314 IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 2, 0x000, 0), /* MX51_PAD_EIM_D22__USBH2_DATA6 */ 314 MX51_PAD_RESERVE45 = 288,
315 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 5, 0x8d0, 0), /* MX51_PAD_EIM_D23__AUD4_TXFS */ 315 MX51_PAD_RESERVE46 = 289,
316 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 0, 0x000, 0), /* MX51_PAD_EIM_D23__EIM_D23 */ 316 MX51_PAD_RESERVE47 = 290,
317 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 1, 0x000, 0), /* MX51_PAD_EIM_D23__GPIO2_7 */ 317 MX51_PAD_RESERVE48 = 291,
318 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 4, 0x000, 0), /* MX51_PAD_EIM_D23__SPDIF_OUT1 */ 318 MX51_PAD_RESERVE49 = 292,
319 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 2, 0x000, 0), /* MX51_PAD_EIM_D23__USBH2_DATA7 */ 319 MX51_PAD_RESERVE50 = 293,
320 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 5, 0x8f8, 0), /* MX51_PAD_EIM_D24__AUD6_RXFS */ 320 MX51_PAD_RESERVE51 = 294,
321 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 0, 0x000, 0), /* MX51_PAD_EIM_D24__EIM_D24 */ 321 MX51_PAD_RESERVE52 = 295,
322 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 1, 0x000, 0), /* MX51_PAD_EIM_D24__GPIO2_8 */ 322 MX51_PAD_RESERVE53 = 296,
323 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 4, 0x9bc, 0), /* MX51_PAD_EIM_D24__I2C2_SDA */ 323 MX51_PAD_RESERVE54 = 297,
324 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 3, 0x000, 0), /* MX51_PAD_EIM_D24__UART3_CTS */ 324 MX51_PAD_RESERVE55 = 298,
325 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 2, 0x000, 0), /* MX51_PAD_EIM_D24__USBOTG_DATA0 */ 325 MX51_PAD_RESERVE56 = 299,
326 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 0, 0x000, 0), /* MX51_PAD_EIM_D25__EIM_D25 */ 326 MX51_PAD_RESERVE57 = 300,
327 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 1, 0x9c8, 0), /* MX51_PAD_EIM_D25__KEY_COL6 */ 327 MX51_PAD_RESERVE58 = 301,
328 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 4, 0x000, 0), /* MX51_PAD_EIM_D25__UART2_CTS */ 328 MX51_PAD_RESERVE59 = 302,
329 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 3, 0x9f4, 0), /* MX51_PAD_EIM_D25__UART3_RXD */ 329 MX51_PAD_RESERVE60 = 303,
330 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 2, 0x000, 0), /* MX51_PAD_EIM_D25__USBOTG_DATA1 */ 330 MX51_PAD_RESERVE61 = 304,
331 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 0, 0x000, 0), /* MX51_PAD_EIM_D26__EIM_D26 */ 331 MX51_PAD_RESERVE62 = 305,
332 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 1, 0x9cc, 0), /* MX51_PAD_EIM_D26__KEY_COL7 */ 332 MX51_PAD_RESERVE63 = 306,
333 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 4, 0x9e8, 3), /* MX51_PAD_EIM_D26__UART2_RTS */ 333 MX51_PAD_RESERVE64 = 307,
334 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 3, 0x000, 0), /* MX51_PAD_EIM_D26__UART3_TXD */ 334 MX51_PAD_RESERVE65 = 308,
335 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 2, 0x000, 0), /* MX51_PAD_EIM_D26__USBOTG_DATA2 */ 335 MX51_PAD_RESERVE66 = 309,
336 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 5, 0x8f4, 0), /* MX51_PAD_EIM_D27__AUD6_RXC */ 336 MX51_PAD_RESERVE67 = 310,
337 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 0, 0x000, 0), /* MX51_PAD_EIM_D27__EIM_D27 */ 337 MX51_PAD_RESERVE68 = 311,
338 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 1, 0x000, 0), /* MX51_PAD_EIM_D27__GPIO2_9 */ 338 MX51_PAD_RESERVE69 = 312,
339 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 4, 0x9b8, 0), /* MX51_PAD_EIM_D27__I2C2_SCL */ 339 MX51_PAD_RESERVE70 = 313,
340 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 3, 0x9f0, 3), /* MX51_PAD_EIM_D27__UART3_RTS */ 340 MX51_PAD_RESERVE71 = 314,
341 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 2, 0x000, 0), /* MX51_PAD_EIM_D27__USBOTG_DATA3 */ 341 MX51_PAD_RESERVE72 = 315,
342 IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 5, 0x8f0, 0), /* MX51_PAD_EIM_D28__AUD6_TXD */ 342 MX51_PAD_RESERVE73 = 316,
343 IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 0, 0x000, 0), /* MX51_PAD_EIM_D28__EIM_D28 */ 343 MX51_PAD_RESERVE74 = 317,
344 IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 1, 0x9d0, 0), /* MX51_PAD_EIM_D28__KEY_ROW4 */ 344 MX51_PAD_RESERVE75 = 318,
345 IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 2, 0x000, 0), /* MX51_PAD_EIM_D28__USBOTG_DATA4 */ 345 MX51_PAD_RESERVE76 = 319,
346 IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 5, 0x8ec, 0), /* MX51_PAD_EIM_D29__AUD6_RXD */ 346 MX51_PAD_RESERVE77 = 320,
347 IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 0, 0x000, 0), /* MX51_PAD_EIM_D29__EIM_D29 */ 347 MX51_PAD_RESERVE78 = 321,
348 IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 1, 0x9d4, 0), /* MX51_PAD_EIM_D29__KEY_ROW5 */ 348 MX51_PAD_RESERVE79 = 322,
349 IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 2, 0x000, 0), /* MX51_PAD_EIM_D29__USBOTG_DATA5 */ 349 MX51_PAD_RESERVE80 = 323,
350 IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 5, 0x8fc, 0), /* MX51_PAD_EIM_D30__AUD6_TXC */ 350 MX51_PAD_RESERVE81 = 324,
351 IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 0, 0x000, 0), /* MX51_PAD_EIM_D30__EIM_D30 */ 351 MX51_PAD_RESERVE82 = 325,
352 IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 1, 0x9d8, 0), /* MX51_PAD_EIM_D30__KEY_ROW6 */ 352 MX51_PAD_RESERVE83 = 326,
353 IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 2, 0x000, 0), /* MX51_PAD_EIM_D30__USBOTG_DATA6 */ 353 MX51_PAD_RESERVE84 = 327,
354 IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 5, 0x900, 0), /* MX51_PAD_EIM_D31__AUD6_TXFS */ 354 MX51_PAD_RESERVE85 = 328,
355 IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 0, 0x000, 0), /* MX51_PAD_EIM_D31__EIM_D31 */ 355 MX51_PAD_RESERVE86 = 329,
356 IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 1, 0x9dc, 0), /* MX51_PAD_EIM_D31__KEY_ROW7 */ 356 MX51_PAD_RESERVE87 = 330,
357 IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 2, 0x000, 0), /* MX51_PAD_EIM_D31__USBOTG_DATA7 */ 357 MX51_PAD_RESERVE88 = 331,
358 IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 0, 0x000, 0), /* MX51_PAD_EIM_A16__EIM_A16 */ 358 MX51_PAD_RESERVE89 = 332,
359 IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 1, 0x000, 0), /* MX51_PAD_EIM_A16__GPIO2_10 */ 359 MX51_PAD_RESERVE90 = 333,
360 IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 7, 0x000, 0), /* MX51_PAD_EIM_A16__OSC_FREQ_SEL0 */ 360 MX51_PAD_RESERVE91 = 334,
361 IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 0, 0x000, 0), /* MX51_PAD_EIM_A17__EIM_A17 */ 361 MX51_PAD_RESERVE92 = 335,
362 IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 1, 0x000, 0), /* MX51_PAD_EIM_A17__GPIO2_11 */ 362 MX51_PAD_RESERVE93 = 336,
363 IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 7, 0x000, 0), /* MX51_PAD_EIM_A17__OSC_FREQ_SEL1 */ 363 MX51_PAD_RESERVE94 = 337,
364 IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 7, 0x000, 0), /* MX51_PAD_EIM_A18__BOOT_LPB0 */ 364 MX51_PAD_RESERVE95 = 338,
365 IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 0, 0x000, 0), /* MX51_PAD_EIM_A18__EIM_A18 */ 365 MX51_PAD_RESERVE96 = 339,
366 IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 1, 0x000, 0), /* MX51_PAD_EIM_A18__GPIO2_12 */ 366 MX51_PAD_RESERVE97 = 340,
367 IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 7, 0x000, 0), /* MX51_PAD_EIM_A19__BOOT_LPB1 */ 367 MX51_PAD_RESERVE98 = 341,
368 IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 0, 0x000, 0), /* MX51_PAD_EIM_A19__EIM_A19 */ 368 MX51_PAD_RESERVE99 = 342,
369 IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 1, 0x000, 0), /* MX51_PAD_EIM_A19__GPIO2_13 */ 369 MX51_PAD_RESERVE100 = 343,
370 IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 7, 0x000, 0), /* MX51_PAD_EIM_A20__BOOT_UART_SRC0 */ 370 MX51_PAD_RESERVE101 = 344,
371 IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 0, 0x000, 0), /* MX51_PAD_EIM_A20__EIM_A20 */ 371 MX51_PAD_RESERVE102 = 345,
372 IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 1, 0x000, 0), /* MX51_PAD_EIM_A20__GPIO2_14 */ 372 MX51_PAD_RESERVE103 = 346,
373 IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 7, 0x000, 0), /* MX51_PAD_EIM_A21__BOOT_UART_SRC1 */ 373 MX51_PAD_RESERVE104 = 347,
374 IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 0, 0x000, 0), /* MX51_PAD_EIM_A21__EIM_A21 */ 374 MX51_PAD_RESERVE105 = 348,
375 IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 1, 0x000, 0), /* MX51_PAD_EIM_A21__GPIO2_15 */ 375 MX51_PAD_RESERVE106 = 349,
376 IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 0, 0x000, 0), /* MX51_PAD_EIM_A22__EIM_A22 */ 376 MX51_PAD_RESERVE107 = 350,
377 IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 1, 0x000, 0), /* MX51_PAD_EIM_A22__GPIO2_16 */ 377 MX51_PAD_RESERVE108 = 351,
378 IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 7, 0x000, 0), /* MX51_PAD_EIM_A23__BOOT_HPN_EN */ 378 MX51_PAD_RESERVE109 = 352,
379 IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 0, 0x000, 0), /* MX51_PAD_EIM_A23__EIM_A23 */ 379 MX51_PAD_RESERVE110 = 353,
380 IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 1, 0x000, 0), /* MX51_PAD_EIM_A23__GPIO2_17 */ 380 MX51_PAD_RESERVE111 = 354,
381 IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 0, 0x000, 0), /* MX51_PAD_EIM_A24__EIM_A24 */ 381 MX51_PAD_RESERVE112 = 355,
382 IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 1, 0x000, 0), /* MX51_PAD_EIM_A24__GPIO2_18 */ 382 MX51_PAD_RESERVE113 = 356,
383 IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 2, 0x000, 0), /* MX51_PAD_EIM_A24__USBH2_CLK */ 383 MX51_PAD_RESERVE114 = 357,
384 IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 6, 0x000, 0), /* MX51_PAD_EIM_A25__DISP1_PIN4 */ 384 MX51_PAD_RESERVE115 = 358,
385 IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 0, 0x000, 0), /* MX51_PAD_EIM_A25__EIM_A25 */ 385 MX51_PAD_RESERVE116 = 359,
386 IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 1, 0x000, 0), /* MX51_PAD_EIM_A25__GPIO2_19 */ 386 MX51_PAD_RESERVE117 = 360,
387 IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 2, 0x000, 0), /* MX51_PAD_EIM_A25__USBH2_DIR */ 387 MX51_PAD_RESERVE118 = 361,
388 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 5, 0x9a0, 0), /* MX51_PAD_EIM_A26__CSI1_DATA_EN */ 388 MX51_PAD_RESERVE119 = 362,
389 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 6, 0x908, 0), /* MX51_PAD_EIM_A26__DISP2_EXT_CLK */ 389 MX51_PAD_RESERVE120 = 363,
390 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 0, 0x000, 0), /* MX51_PAD_EIM_A26__EIM_A26 */ 390 MX51_PAD_RESERVE121 = 364,
391 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 1, 0x000, 0), /* MX51_PAD_EIM_A26__GPIO2_20 */ 391 MX51_PAD_CSI1_PIXCLK = 365,
392 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 2, 0x000, 0), /* MX51_PAD_EIM_A26__USBH2_STP */ 392 MX51_PAD_CSI1_MCLK = 366,
393 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 5, 0x99c, 0), /* MX51_PAD_EIM_A27__CSI2_DATA_EN */
394 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 6, 0x9a4, 0), /* MX51_PAD_EIM_A27__DISP1_PIN1 */
395 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 0, 0x000, 0), /* MX51_PAD_EIM_A27__EIM_A27 */
396 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 1, 0x000, 0), /* MX51_PAD_EIM_A27__GPIO2_21 */
397 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 2, 0x000, 0), /* MX51_PAD_EIM_A27__USBH2_NXT */
398 IMX_PIN_REG(MX51_PAD_EIM_EB0, 0x460, 0x0cc, 0, 0x000, 0), /* MX51_PAD_EIM_EB0__EIM_EB0 */
399 IMX_PIN_REG(MX51_PAD_EIM_EB1, 0x464, 0x0d0, 0, 0x000, 0), /* MX51_PAD_EIM_EB1__EIM_EB1 */
400 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 6, 0x8e0, 0), /* MX51_PAD_EIM_EB2__AUD5_RXFS */
401 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 5, 0x000, 0), /* MX51_PAD_EIM_EB2__CSI1_D2 */
402 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 0, 0x000, 0), /* MX51_PAD_EIM_EB2__EIM_EB2 */
403 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 3, 0x954, 0), /* MX51_PAD_EIM_EB2__FEC_MDIO */
404 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 1, 0x000, 0), /* MX51_PAD_EIM_EB2__GPIO2_22 */
405 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 7, 0x000, 0), /* MX51_PAD_EIM_EB2__GPT_CMPOUT1 */
406 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 6, 0x8dc, 0), /* MX51_PAD_EIM_EB3__AUD5_RXC */
407 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 5, 0x000, 0), /* MX51_PAD_EIM_EB3__CSI1_D3 */
408 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 0, 0x000, 0), /* MX51_PAD_EIM_EB3__EIM_EB3 */
409 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 3, 0x95c, 0), /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
410 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 1, 0x000, 0), /* MX51_PAD_EIM_EB3__GPIO2_23 */
411 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 7, 0x000, 0), /* MX51_PAD_EIM_EB3__GPT_CMPOUT2 */
412 IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 0, 0x000, 0), /* MX51_PAD_EIM_OE__EIM_OE */
413 IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 1, 0x000, 0), /* MX51_PAD_EIM_OE__GPIO2_24 */
414 IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 0, 0x000, 0), /* MX51_PAD_EIM_CS0__EIM_CS0 */
415 IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 1, 0x000, 0), /* MX51_PAD_EIM_CS0__GPIO2_25 */
416 IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 0, 0x000, 0), /* MX51_PAD_EIM_CS1__EIM_CS1 */
417 IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 1, 0x000, 0), /* MX51_PAD_EIM_CS1__GPIO2_26 */
418 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 6, 0x8d8, 1), /* MX51_PAD_EIM_CS2__AUD5_TXD */
419 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 5, 0x000, 0), /* MX51_PAD_EIM_CS2__CSI1_D4 */
420 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 0, 0x000, 0), /* MX51_PAD_EIM_CS2__EIM_CS2 */
421 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 3, 0x960, 0), /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
422 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 1, 0x000, 0), /* MX51_PAD_EIM_CS2__GPIO2_27 */
423 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 2, 0x000, 0), /* MX51_PAD_EIM_CS2__USBOTG_STP */
424 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 6, 0x8d4, 1), /* MX51_PAD_EIM_CS3__AUD5_RXD */
425 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 5, 0x000, 0), /* MX51_PAD_EIM_CS3__CSI1_D5 */
426 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 0, 0x000, 0), /* MX51_PAD_EIM_CS3__EIM_CS3 */
427 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 3, 0x964, 0), /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
428 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 1, 0x000, 0), /* MX51_PAD_EIM_CS3__GPIO2_28 */
429 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 2, 0x000, 0), /* MX51_PAD_EIM_CS3__USBOTG_NXT */
430 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 6, 0x8e4, 1), /* MX51_PAD_EIM_CS4__AUD5_TXC */
431 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 5, 0x000, 0), /* MX51_PAD_EIM_CS4__CSI1_D6 */
432 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 0, 0x000, 0), /* MX51_PAD_EIM_CS4__EIM_CS4 */
433 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 3, 0x970, 0), /* MX51_PAD_EIM_CS4__FEC_RX_ER */
434 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 1, 0x000, 0), /* MX51_PAD_EIM_CS4__GPIO2_29 */
435 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 2, 0x000, 0), /* MX51_PAD_EIM_CS4__USBOTG_CLK */
436 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 6, 0x8e8, 1), /* MX51_PAD_EIM_CS5__AUD5_TXFS */
437 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 5, 0x000, 0), /* MX51_PAD_EIM_CS5__CSI1_D7 */
438 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 4, 0x904, 0), /* MX51_PAD_EIM_CS5__DISP1_EXT_CLK */
439 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 0, 0x000, 0), /* MX51_PAD_EIM_CS5__EIM_CS5 */
440 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 3, 0x950, 0), /* MX51_PAD_EIM_CS5__FEC_CRS */
441 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 1, 0x000, 0), /* MX51_PAD_EIM_CS5__GPIO2_30 */
442 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 2, 0x000, 0), /* MX51_PAD_EIM_CS5__USBOTG_DIR */
443 IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 0, 0x000, 0), /* MX51_PAD_EIM_DTACK__EIM_DTACK */
444 IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 1, 0x000, 0), /* MX51_PAD_EIM_DTACK__GPIO2_31 */
445 IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 0, 0x000, 0), /* MX51_PAD_EIM_LBA__EIM_LBA */
446 IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 1, 0x978, 0), /* MX51_PAD_EIM_LBA__GPIO3_1 */
447 IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 0, 0x000, 0), /* MX51_PAD_EIM_CRE__EIM_CRE */
448 IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 1, 0x97c, 0), /* MX51_PAD_EIM_CRE__GPIO3_2 */
449 IMX_PIN_REG(MX51_PAD_DRAM_CS1, 0x4d0, 0x104, 0, 0x000, 0), /* MX51_PAD_DRAM_CS1__DRAM_CS1 */
450 IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 3, 0x980, 0), /* MX51_PAD_NANDF_WE_B__GPIO3_3 */
451 IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 0, 0x000, 0), /* MX51_PAD_NANDF_WE_B__NANDF_WE_B */
452 IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 1, 0x000, 0), /* MX51_PAD_NANDF_WE_B__PATA_DIOW */
453 IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 2, 0x93c, 0), /* MX51_PAD_NANDF_WE_B__SD3_DATA0 */
454 IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 3, 0x984, 0), /* MX51_PAD_NANDF_RE_B__GPIO3_4 */
455 IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 0, 0x000, 0), /* MX51_PAD_NANDF_RE_B__NANDF_RE_B */
456 IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 1, 0x000, 0), /* MX51_PAD_NANDF_RE_B__PATA_DIOR */
457 IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 2, 0x940, 0), /* MX51_PAD_NANDF_RE_B__SD3_DATA1 */
458 IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 3, 0x988, 0), /* MX51_PAD_NANDF_ALE__GPIO3_5 */
459 IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 0, 0x000, 0), /* MX51_PAD_NANDF_ALE__NANDF_ALE */
460 IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 1, 0x000, 0), /* MX51_PAD_NANDF_ALE__PATA_BUFFER_EN */
461 IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 3, 0x98c, 0), /* MX51_PAD_NANDF_CLE__GPIO3_6 */
462 IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 0, 0x000, 0), /* MX51_PAD_NANDF_CLE__NANDF_CLE */
463 IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 1, 0x000, 0), /* MX51_PAD_NANDF_CLE__PATA_RESET_B */
464 IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 3, 0x990, 0), /* MX51_PAD_NANDF_WP_B__GPIO3_7 */
465 IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 0, 0x000, 0), /* MX51_PAD_NANDF_WP_B__NANDF_WP_B */
466 IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 1, 0x000, 0), /* MX51_PAD_NANDF_WP_B__PATA_DMACK */
467 IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 2, 0x944, 0), /* MX51_PAD_NANDF_WP_B__SD3_DATA2 */
468 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 5, 0x930, 0), /* MX51_PAD_NANDF_RB0__ECSPI2_SS1 */
469 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 3, 0x994, 0), /* MX51_PAD_NANDF_RB0__GPIO3_8 */
470 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 0, 0x000, 0), /* MX51_PAD_NANDF_RB0__NANDF_RB0 */
471 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 1, 0x000, 0), /* MX51_PAD_NANDF_RB0__PATA_DMARQ */
472 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 2, 0x948, 0), /* MX51_PAD_NANDF_RB0__SD3_DATA3 */
473 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 6, 0x91c, 0), /* MX51_PAD_NANDF_RB1__CSPI_MOSI */
474 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 2, 0x000, 0), /* MX51_PAD_NANDF_RB1__ECSPI2_RDY */
475 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 3, 0x000, 0), /* MX51_PAD_NANDF_RB1__GPIO3_9 */
476 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 0, 0x000, 0), /* MX51_PAD_NANDF_RB1__NANDF_RB1 */
477 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 1, 0x000, 0), /* MX51_PAD_NANDF_RB1__PATA_IORDY */
478 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 5, 0x000, 0), /* MX51_PAD_NANDF_RB1__SD4_CMD */
479 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 5, 0x9a8, 0), /* MX51_PAD_NANDF_RB2__DISP2_WAIT */
480 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 2, 0x000, 0), /* MX51_PAD_NANDF_RB2__ECSPI2_SCLK */
481 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 1, 0x94c, 0), /* MX51_PAD_NANDF_RB2__FEC_COL */
482 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 3, 0x000, 0), /* MX51_PAD_NANDF_RB2__GPIO3_10 */
483 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 0, 0x000, 0), /* MX51_PAD_NANDF_RB2__NANDF_RB2 */
484 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 7, 0x000, 0), /* MX51_PAD_NANDF_RB2__USBH3_H3_DP */
485 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 6, 0xa20, 0), /* MX51_PAD_NANDF_RB2__USBH3_NXT */
486 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 5, 0x000, 0), /* MX51_PAD_NANDF_RB3__DISP1_WAIT */
487 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 2, 0x000, 0), /* MX51_PAD_NANDF_RB3__ECSPI2_MISO */
488 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 1, 0x968, 0), /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
489 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 3, 0x000, 0), /* MX51_PAD_NANDF_RB3__GPIO3_11 */
490 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 0, 0x000, 0), /* MX51_PAD_NANDF_RB3__NANDF_RB3 */
491 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 6, 0x9f8, 0), /* MX51_PAD_NANDF_RB3__USBH3_CLK */
492 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 7, 0x000, 0), /* MX51_PAD_NANDF_RB3__USBH3_H3_DM */
493 IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 0, 0x998, 0), /* MX51_PAD_GPIO_NAND__GPIO_NAND */
494 IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 1, 0x000, 0), /* MX51_PAD_GPIO_NAND__PATA_INTRQ */
495 IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 3, 0x000, 0), /* MX51_PAD_NANDF_CS0__GPIO3_16 */
496 IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 0, 0x000, 0), /* MX51_PAD_NANDF_CS0__NANDF_CS0 */
497 IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 3, 0x000, 0), /* MX51_PAD_NANDF_CS1__GPIO3_17 */
498 IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 0, 0x000, 0), /* MX51_PAD_NANDF_CS1__NANDF_CS1 */
499 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 6, 0x914, 0), /* MX51_PAD_NANDF_CS2__CSPI_SCLK */
500 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 2, 0x000, 0), /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
501 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 3, 0x000, 0), /* MX51_PAD_NANDF_CS2__GPIO3_18 */
502 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 0, 0x000, 0), /* MX51_PAD_NANDF_CS2__NANDF_CS2 */
503 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 1, 0x000, 0), /* MX51_PAD_NANDF_CS2__PATA_CS_0 */
504 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 5, 0x000, 0), /* MX51_PAD_NANDF_CS2__SD4_CLK */
505 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 7, 0x000, 0), /* MX51_PAD_NANDF_CS2__USBH3_H1_DP */
506 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 2, 0x000, 0), /* MX51_PAD_NANDF_CS3__FEC_MDC */
507 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS3__GPIO3_19 */
508 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS3__NANDF_CS3 */
509 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS3__PATA_CS_1 */
510 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS3__SD4_DAT0 */
511 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 7, 0x000, 0), /* MX51_PAD_NANDF_CS3__USBH3_H1_DM */
512 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 2, 0x000, 0), /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
513 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 3, 0x000, 0), /* MX51_PAD_NANDF_CS4__GPIO3_20 */
514 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 0, 0x000, 0), /* MX51_PAD_NANDF_CS4__NANDF_CS4 */
515 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 1, 0x000, 0), /* MX51_PAD_NANDF_CS4__PATA_DA_0 */
516 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 5, 0x000, 0), /* MX51_PAD_NANDF_CS4__SD4_DAT1 */
517 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 7, 0xa24, 0), /* MX51_PAD_NANDF_CS4__USBH3_STP */
518 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 2, 0x000, 0), /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
519 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 3, 0x000, 0), /* MX51_PAD_NANDF_CS5__GPIO3_21 */
520 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 0, 0x000, 0), /* MX51_PAD_NANDF_CS5__NANDF_CS5 */
521 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 1, 0x000, 0), /* MX51_PAD_NANDF_CS5__PATA_DA_1 */
522 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 5, 0x000, 0), /* MX51_PAD_NANDF_CS5__SD4_DAT2 */
523 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 7, 0xa1c, 0), /* MX51_PAD_NANDF_CS5__USBH3_DIR */
524 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 7, 0x928, 0), /* MX51_PAD_NANDF_CS6__CSPI_SS3 */
525 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 2, 0x000, 0), /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
526 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 3, 0x000, 0), /* MX51_PAD_NANDF_CS6__GPIO3_22 */
527 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 0, 0x000, 0), /* MX51_PAD_NANDF_CS6__NANDF_CS6 */
528 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 1, 0x000, 0), /* MX51_PAD_NANDF_CS6__PATA_DA_2 */
529 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 5, 0x000, 0), /* MX51_PAD_NANDF_CS6__SD4_DAT3 */
530 IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
531 IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS7__GPIO3_23 */
532 IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS7__NANDF_CS7 */
533 IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS7__SD3_CLK */
534 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 2, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 */
535 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 1, 0x974, 0), /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
536 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 3, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__GPIO3_24 */
537 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 0, 0x938, 0), /* MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT */
538 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 5, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__SD3_CMD */
539 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 2, 0x000, 0), /* MX51_PAD_NANDF_D15__ECSPI2_MOSI */
540 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 3, 0x000, 0), /* MX51_PAD_NANDF_D15__GPIO3_25 */
541 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 0, 0x000, 0), /* MX51_PAD_NANDF_D15__NANDF_D15 */
542 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 1, 0x000, 0), /* MX51_PAD_NANDF_D15__PATA_DATA15 */
543 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 5, 0x000, 0), /* MX51_PAD_NANDF_D15__SD3_DAT7 */
544 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 2, 0x934, 0), /* MX51_PAD_NANDF_D14__ECSPI2_SS3 */
545 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 3, 0x000, 0), /* MX51_PAD_NANDF_D14__GPIO3_26 */
546 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 0, 0x000, 0), /* MX51_PAD_NANDF_D14__NANDF_D14 */
547 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 1, 0x000, 0), /* MX51_PAD_NANDF_D14__PATA_DATA14 */
548 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 5, 0x000, 0), /* MX51_PAD_NANDF_D14__SD3_DAT6 */
549 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 2, 0x000, 0), /* MX51_PAD_NANDF_D13__ECSPI2_SS2 */
550 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 3, 0x000, 0), /* MX51_PAD_NANDF_D13__GPIO3_27 */
551 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 0, 0x000, 0), /* MX51_PAD_NANDF_D13__NANDF_D13 */
552 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 1, 0x000, 0), /* MX51_PAD_NANDF_D13__PATA_DATA13 */
553 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 5, 0x000, 0), /* MX51_PAD_NANDF_D13__SD3_DAT5 */
554 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 2, 0x930, 1), /* MX51_PAD_NANDF_D12__ECSPI2_SS1 */
555 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 3, 0x000, 0), /* MX51_PAD_NANDF_D12__GPIO3_28 */
556 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 0, 0x000, 0), /* MX51_PAD_NANDF_D12__NANDF_D12 */
557 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 1, 0x000, 0), /* MX51_PAD_NANDF_D12__PATA_DATA12 */
558 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 5, 0x000, 0), /* MX51_PAD_NANDF_D12__SD3_DAT4 */
559 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 2, 0x96c, 0), /* MX51_PAD_NANDF_D11__FEC_RX_DV */
560 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 3, 0x000, 0), /* MX51_PAD_NANDF_D11__GPIO3_29 */
561 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 0, 0x000, 0), /* MX51_PAD_NANDF_D11__NANDF_D11 */
562 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 1, 0x000, 0), /* MX51_PAD_NANDF_D11__PATA_DATA11 */
563 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 5, 0x948, 1), /* MX51_PAD_NANDF_D11__SD3_DATA3 */
564 IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 3, 0x000, 0), /* MX51_PAD_NANDF_D10__GPIO3_30 */
565 IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 0, 0x000, 0), /* MX51_PAD_NANDF_D10__NANDF_D10 */
566 IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 1, 0x000, 0), /* MX51_PAD_NANDF_D10__PATA_DATA10 */
567 IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 5, 0x944, 1), /* MX51_PAD_NANDF_D10__SD3_DATA2 */
568 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 2, 0x958, 0), /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
569 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 3, 0x000, 0), /* MX51_PAD_NANDF_D9__GPIO3_31 */
570 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 0, 0x000, 0), /* MX51_PAD_NANDF_D9__NANDF_D9 */
571 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 1, 0x000, 0), /* MX51_PAD_NANDF_D9__PATA_DATA9 */
572 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 5, 0x940, 1), /* MX51_PAD_NANDF_D9__SD3_DATA1 */
573 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 2, 0x000, 0), /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
574 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 3, 0x000, 0), /* MX51_PAD_NANDF_D8__GPIO4_0 */
575 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 0, 0x000, 0), /* MX51_PAD_NANDF_D8__NANDF_D8 */
576 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 1, 0x000, 0), /* MX51_PAD_NANDF_D8__PATA_DATA8 */
577 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 5, 0x93c, 1), /* MX51_PAD_NANDF_D8__SD3_DATA0 */
578 IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 3, 0x000, 0), /* MX51_PAD_NANDF_D7__GPIO4_1 */
579 IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 0, 0x000, 0), /* MX51_PAD_NANDF_D7__NANDF_D7 */
580 IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 1, 0x000, 0), /* MX51_PAD_NANDF_D7__PATA_DATA7 */
581 IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 5, 0x9fc, 0), /* MX51_PAD_NANDF_D7__USBH3_DATA0 */
582 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 3, 0x000, 0), /* MX51_PAD_NANDF_D6__GPIO4_2 */
583 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 0, 0x000, 0), /* MX51_PAD_NANDF_D6__NANDF_D6 */
584 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 1, 0x000, 0), /* MX51_PAD_NANDF_D6__PATA_DATA6 */
585 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 2, 0x000, 0), /* MX51_PAD_NANDF_D6__SD4_LCTL */
586 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 5, 0xa00, 0), /* MX51_PAD_NANDF_D6__USBH3_DATA1 */
587 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 3, 0x000, 0), /* MX51_PAD_NANDF_D5__GPIO4_3 */
588 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 0, 0x000, 0), /* MX51_PAD_NANDF_D5__NANDF_D5 */
589 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 1, 0x000, 0), /* MX51_PAD_NANDF_D5__PATA_DATA5 */
590 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 2, 0x000, 0), /* MX51_PAD_NANDF_D5__SD4_WP */
591 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 5, 0xa04, 0), /* MX51_PAD_NANDF_D5__USBH3_DATA2 */
592 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 3, 0x000, 0), /* MX51_PAD_NANDF_D4__GPIO4_4 */
593 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 0, 0x000, 0), /* MX51_PAD_NANDF_D4__NANDF_D4 */
594 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 1, 0x000, 0), /* MX51_PAD_NANDF_D4__PATA_DATA4 */
595 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 2, 0x000, 0), /* MX51_PAD_NANDF_D4__SD4_CD */
596 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 5, 0xa08, 0), /* MX51_PAD_NANDF_D4__USBH3_DATA3 */
597 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 3, 0x000, 0), /* MX51_PAD_NANDF_D3__GPIO4_5 */
598 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 0, 0x000, 0), /* MX51_PAD_NANDF_D3__NANDF_D3 */
599 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 1, 0x000, 0), /* MX51_PAD_NANDF_D3__PATA_DATA3 */
600 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 2, 0x000, 0), /* MX51_PAD_NANDF_D3__SD4_DAT4 */
601 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 5, 0xa0c, 0), /* MX51_PAD_NANDF_D3__USBH3_DATA4 */
602 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 3, 0x000, 0), /* MX51_PAD_NANDF_D2__GPIO4_6 */
603 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 0, 0x000, 0), /* MX51_PAD_NANDF_D2__NANDF_D2 */
604 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 1, 0x000, 0), /* MX51_PAD_NANDF_D2__PATA_DATA2 */
605 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 2, 0x000, 0), /* MX51_PAD_NANDF_D2__SD4_DAT5 */
606 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 5, 0xa10, 0), /* MX51_PAD_NANDF_D2__USBH3_DATA5 */
607 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 3, 0x000, 0), /* MX51_PAD_NANDF_D1__GPIO4_7 */
608 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 0, 0x000, 0), /* MX51_PAD_NANDF_D1__NANDF_D1 */
609 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 1, 0x000, 0), /* MX51_PAD_NANDF_D1__PATA_DATA1 */
610 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 2, 0x000, 0), /* MX51_PAD_NANDF_D1__SD4_DAT6 */
611 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 5, 0xa14, 0), /* MX51_PAD_NANDF_D1__USBH3_DATA6 */
612 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 3, 0x000, 0), /* MX51_PAD_NANDF_D0__GPIO4_8 */
613 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 0, 0x000, 0), /* MX51_PAD_NANDF_D0__NANDF_D0 */
614 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 1, 0x000, 0), /* MX51_PAD_NANDF_D0__PATA_DATA0 */
615 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 2, 0x000, 0), /* MX51_PAD_NANDF_D0__SD4_DAT7 */
616 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 5, 0xa18, 0), /* MX51_PAD_NANDF_D0__USBH3_DATA7 */
617 IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 0, 0x000, 0), /* MX51_PAD_CSI1_D8__CSI1_D8 */
618 IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 3, 0x998, 1), /* MX51_PAD_CSI1_D8__GPIO3_12 */
619 IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 0, 0x000, 0), /* MX51_PAD_CSI1_D9__CSI1_D9 */
620 IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 3, 0x000, 0), /* MX51_PAD_CSI1_D9__GPIO3_13 */
621 IMX_PIN_REG(MX51_PAD_CSI1_D10, 0x584, 0x19c, 0, 0x000, 0), /* MX51_PAD_CSI1_D10__CSI1_D10 */
622 IMX_PIN_REG(MX51_PAD_CSI1_D11, 0x588, 0x1a0, 0, 0x000, 0), /* MX51_PAD_CSI1_D11__CSI1_D11 */
623 IMX_PIN_REG(MX51_PAD_CSI1_D12, 0x58c, 0x1a4, 0, 0x000, 0), /* MX51_PAD_CSI1_D12__CSI1_D12 */
624 IMX_PIN_REG(MX51_PAD_CSI1_D13, 0x590, 0x1a8, 0, 0x000, 0), /* MX51_PAD_CSI1_D13__CSI1_D13 */
625 IMX_PIN_REG(MX51_PAD_CSI1_D14, 0x594, 0x1ac, 0, 0x000, 0), /* MX51_PAD_CSI1_D14__CSI1_D14 */
626 IMX_PIN_REG(MX51_PAD_CSI1_D15, 0x598, 0x1b0, 0, 0x000, 0), /* MX51_PAD_CSI1_D15__CSI1_D15 */
627 IMX_PIN_REG(MX51_PAD_CSI1_D16, 0x59c, 0x1b4, 0, 0x000, 0), /* MX51_PAD_CSI1_D16__CSI1_D16 */
628 IMX_PIN_REG(MX51_PAD_CSI1_D17, 0x5a0, 0x1b8, 0, 0x000, 0), /* MX51_PAD_CSI1_D17__CSI1_D17 */
629 IMX_PIN_REG(MX51_PAD_CSI1_D18, 0x5a4, 0x1bc, 0, 0x000, 0), /* MX51_PAD_CSI1_D18__CSI1_D18 */
630 IMX_PIN_REG(MX51_PAD_CSI1_D19, 0x5a8, 0x1c0, 0, 0x000, 0), /* MX51_PAD_CSI1_D19__CSI1_D19 */
631 IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 0, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__CSI1_VSYNC */
632 IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 3, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__GPIO3_14 */
633 IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 0, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__CSI1_HSYNC */
634 IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 3, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__GPIO3_15 */
635 IMX_PIN_REG(MX51_PAD_CSI1_PIXCLK, 0x5b4, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK */
636 IMX_PIN_REG(MX51_PAD_CSI1_MCLK, 0x5b8, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_MCLK__CSI1_MCLK */
637 IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 0, 0x000, 0), /* MX51_PAD_CSI2_D12__CSI2_D12 */
638 IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 3, 0x000, 0), /* MX51_PAD_CSI2_D12__GPIO4_9 */
639 IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 0, 0x000, 0), /* MX51_PAD_CSI2_D13__CSI2_D13 */
640 IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 3, 0x000, 0), /* MX51_PAD_CSI2_D13__GPIO4_10 */
641 IMX_PIN_REG(MX51_PAD_CSI2_D14, 0x5c4, 0x1d4, 0, 0x000, 0), /* MX51_PAD_CSI2_D14__CSI2_D14 */
642 IMX_PIN_REG(MX51_PAD_CSI2_D15, 0x5c8, 0x1d8, 0, 0x000, 0), /* MX51_PAD_CSI2_D15__CSI2_D15 */
643 IMX_PIN_REG(MX51_PAD_CSI2_D16, 0x5cc, 0x1dc, 0, 0x000, 0), /* MX51_PAD_CSI2_D16__CSI2_D16 */
644 IMX_PIN_REG(MX51_PAD_CSI2_D17, 0x5d0, 0x1e0, 0, 0x000, 0), /* MX51_PAD_CSI2_D17__CSI2_D17 */
645 IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 0, 0x000, 0), /* MX51_PAD_CSI2_D18__CSI2_D18 */
646 IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 3, 0x000, 0), /* MX51_PAD_CSI2_D18__GPIO4_11 */
647 IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 0, 0x000, 0), /* MX51_PAD_CSI2_D19__CSI2_D19 */
648 IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 3, 0x000, 0), /* MX51_PAD_CSI2_D19__GPIO4_12 */
649 IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 0, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__CSI2_VSYNC */
650 IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 3, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__GPIO4_13 */
651 IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 0, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__CSI2_HSYNC */
652 IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 3, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__GPIO4_14 */
653 IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 0, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK */
654 IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 3, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__GPIO4_15 */
655 IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 3, 0x000, 0), /* MX51_PAD_I2C1_CLK__GPIO4_16 */
656 IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 0, 0x000, 0), /* MX51_PAD_I2C1_CLK__I2C1_CLK */
657 IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 3, 0x000, 0), /* MX51_PAD_I2C1_DAT__GPIO4_17 */
658 IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 0, 0x000, 0), /* MX51_PAD_I2C1_DAT__I2C1_DAT */
659 IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
660 IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__GPIO4_18 */
661 IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
662 IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__GPIO4_19 */
663 IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 1, 0x9f4, 2), /* MX51_PAD_AUD3_BB_RXD__UART3_RXD */
664 IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
665 IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__GPIO4_20 */
666 IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
667 IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__GPIO4_21 */
668 IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 1, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__UART3_TXD */
669 IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 0, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
670 IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 3, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__GPIO4_22 */
671 IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 1, 0x9b4, 1), /* MX51_PAD_CSPI1_MOSI__I2C1_SDA */
672 IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 1, 0x8c4, 1), /* MX51_PAD_CSPI1_MISO__AUD4_RXD */
673 IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 0, 0x000, 0), /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
674 IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 3, 0x000, 0), /* MX51_PAD_CSPI1_MISO__GPIO4_23 */
675 IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 1, 0x8cc, 1), /* MX51_PAD_CSPI1_SS0__AUD4_TXC */
676 IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS0__ECSPI1_SS0 */
677 IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
678 IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 1, 0x8c8, 1), /* MX51_PAD_CSPI1_SS1__AUD4_TXD */
679 IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS1__ECSPI1_SS1 */
680 IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
681 IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 1, 0x8d0, 1), /* MX51_PAD_CSPI1_RDY__AUD4_TXFS */
682 IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 0, 0x000, 0), /* MX51_PAD_CSPI1_RDY__ECSPI1_RDY */
683 IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 3, 0x000, 0), /* MX51_PAD_CSPI1_RDY__GPIO4_26 */
684 IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 0, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
685 IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 3, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__GPIO4_27 */
686 IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 1, 0x9b0, 1), /* MX51_PAD_CSPI1_SCLK__I2C1_SCL */
687 IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 3, 0x000, 0), /* MX51_PAD_UART1_RXD__GPIO4_28 */
688 IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 0, 0x9e4, 0), /* MX51_PAD_UART1_RXD__UART1_RXD */
689 IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 3, 0x000, 0), /* MX51_PAD_UART1_TXD__GPIO4_29 */
690 IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 1, 0x000, 0), /* MX51_PAD_UART1_TXD__PWM2_PWMO */
691 IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 0, 0x000, 0), /* MX51_PAD_UART1_TXD__UART1_TXD */
692 IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 3, 0x000, 0), /* MX51_PAD_UART1_RTS__GPIO4_30 */
693 IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 0, 0x9e0, 0), /* MX51_PAD_UART1_RTS__UART1_RTS */
694 IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 3, 0x000, 0), /* MX51_PAD_UART1_CTS__GPIO4_31 */
695 IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 0, 0x000, 0), /* MX51_PAD_UART1_CTS__UART1_CTS */
696 IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 1, 0x000, 0), /* MX51_PAD_UART2_RXD__FIRI_TXD */
697 IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 3, 0x000, 0), /* MX51_PAD_UART2_RXD__GPIO1_20 */
698 IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 0, 0x9ec, 2), /* MX51_PAD_UART2_RXD__UART2_RXD */
699 IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 1, 0x000, 0), /* MX51_PAD_UART2_TXD__FIRI_RXD */
700 IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 3, 0x000, 0), /* MX51_PAD_UART2_TXD__GPIO1_21 */
701 IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 0, 0x000, 0), /* MX51_PAD_UART2_TXD__UART2_TXD */
702 IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 2, 0x000, 0), /* MX51_PAD_UART3_RXD__CSI1_D0 */
703 IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 3, 0x000, 0), /* MX51_PAD_UART3_RXD__GPIO1_22 */
704 IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 0, 0x000, 0), /* MX51_PAD_UART3_RXD__UART1_DTR */
705 IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 1, 0x9f4, 4), /* MX51_PAD_UART3_RXD__UART3_RXD */
706 IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 2, 0x000, 0), /* MX51_PAD_UART3_TXD__CSI1_D1 */
707 IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 3, 0x000, 0), /* MX51_PAD_UART3_TXD__GPIO1_23 */
708 IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 0, 0x000, 0), /* MX51_PAD_UART3_TXD__UART1_DSR */
709 IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 1, 0x000, 0), /* MX51_PAD_UART3_TXD__UART3_TXD */
710 IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 3, 0x000, 0), /* MX51_PAD_OWIRE_LINE__GPIO1_24 */
711 IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 0, 0x000, 0), /* MX51_PAD_OWIRE_LINE__OWIRE_LINE */
712 IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 6, 0x000, 0), /* MX51_PAD_OWIRE_LINE__SPDIF_OUT */
713 IMX_PIN_REG(MX51_PAD_KEY_ROW0, 0x63c, 0x24c, 0, 0x000, 0), /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
714 IMX_PIN_REG(MX51_PAD_KEY_ROW1, 0x640, 0x250, 0, 0x000, 0), /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
715 IMX_PIN_REG(MX51_PAD_KEY_ROW2, 0x644, 0x254, 0, 0x000, 0), /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
716 IMX_PIN_REG(MX51_PAD_KEY_ROW3, 0x648, 0x258, 0, 0x000, 0), /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
717 IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 0, 0x000, 0), /* MX51_PAD_KEY_COL0__KEY_COL0 */
718 IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 7, 0x90c, 0), /* MX51_PAD_KEY_COL0__PLL1_BYP */
719 IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 0, 0x000, 0), /* MX51_PAD_KEY_COL1__KEY_COL1 */
720 IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 7, 0x910, 0), /* MX51_PAD_KEY_COL1__PLL2_BYP */
721 IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 0, 0x000, 0), /* MX51_PAD_KEY_COL2__KEY_COL2 */
722 IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 7, 0x000, 0), /* MX51_PAD_KEY_COL2__PLL3_BYP */
723 IMX_PIN_REG(MX51_PAD_KEY_COL3, 0x658, 0x268, 0, 0x000, 0), /* MX51_PAD_KEY_COL3__KEY_COL3 */
724 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 3, 0x9b8, 1), /* MX51_PAD_KEY_COL4__I2C2_SCL */
725 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 0, 0x000, 0), /* MX51_PAD_KEY_COL4__KEY_COL4 */
726 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 6, 0x000, 0), /* MX51_PAD_KEY_COL4__SPDIF_OUT1 */
727 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 1, 0x000, 0), /* MX51_PAD_KEY_COL4__UART1_RI */
728 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 2, 0x9f0, 4), /* MX51_PAD_KEY_COL4__UART3_RTS */
729 IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 3, 0x9bc, 1), /* MX51_PAD_KEY_COL5__I2C2_SDA */
730 IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 0, 0x000, 0), /* MX51_PAD_KEY_COL5__KEY_COL5 */
731 IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 1, 0x000, 0), /* MX51_PAD_KEY_COL5__UART1_DCD */
732 IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 2, 0x000, 0), /* MX51_PAD_KEY_COL5__UART3_CTS */
733 IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 1, 0x914, 1), /* MX51_PAD_USBH1_CLK__CSPI_SCLK */
734 IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 2, 0x000, 0), /* MX51_PAD_USBH1_CLK__GPIO1_25 */
735 IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 5, 0x9b8, 2), /* MX51_PAD_USBH1_CLK__I2C2_SCL */
736 IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 0, 0x000, 0), /* MX51_PAD_USBH1_CLK__USBH1_CLK */
737 IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 1, 0x91c, 1), /* MX51_PAD_USBH1_DIR__CSPI_MOSI */
738 IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 2, 0x000, 0), /* MX51_PAD_USBH1_DIR__GPIO1_26 */
739 IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 5, 0x9bc, 2), /* MX51_PAD_USBH1_DIR__I2C2_SDA */
740 IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 0, 0x000, 0), /* MX51_PAD_USBH1_DIR__USBH1_DIR */
741 IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 1, 0x000, 0), /* MX51_PAD_USBH1_STP__CSPI_RDY */
742 IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 2, 0x000, 0), /* MX51_PAD_USBH1_STP__GPIO1_27 */
743 IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 5, 0x9f4, 6), /* MX51_PAD_USBH1_STP__UART3_RXD */
744 IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 0, 0x000, 0), /* MX51_PAD_USBH1_STP__USBH1_STP */
745 IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 1, 0x918, 0), /* MX51_PAD_USBH1_NXT__CSPI_MISO */
746 IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 2, 0x000, 0), /* MX51_PAD_USBH1_NXT__GPIO1_28 */
747 IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 5, 0x000, 0), /* MX51_PAD_USBH1_NXT__UART3_TXD */
748 IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 0, 0x000, 0), /* MX51_PAD_USBH1_NXT__USBH1_NXT */
749 IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA0__GPIO1_11 */
750 IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA0__UART2_CTS */
751 IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA0__USBH1_DATA0 */
752 IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA1__GPIO1_12 */
753 IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 1, 0x9ec, 4), /* MX51_PAD_USBH1_DATA1__UART2_RXD */
754 IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA1__USBH1_DATA1 */
755 IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA2__GPIO1_13 */
756 IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA2__UART2_TXD */
757 IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA2__USBH1_DATA2 */
758 IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA3__GPIO1_14 */
759 IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 1, 0x9e8, 5), /* MX51_PAD_USBH1_DATA3__UART2_RTS */
760 IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA3__USBH1_DATA3 */
761 IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA4__CSPI_SS0 */
762 IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA4__GPIO1_15 */
763 IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA4__USBH1_DATA4 */
764 IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 1, 0x920, 0), /* MX51_PAD_USBH1_DATA5__CSPI_SS1 */
765 IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA5__GPIO1_16 */
766 IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA5__USBH1_DATA5 */
767 IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 1, 0x928, 1), /* MX51_PAD_USBH1_DATA6__CSPI_SS3 */
768 IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA6__GPIO1_17 */
769 IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA6__USBH1_DATA6 */
770 IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA7__ECSPI1_SS3 */
771 IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 5, 0x934, 1), /* MX51_PAD_USBH1_DATA7__ECSPI2_SS3 */
772 IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA7__GPIO1_18 */
773 IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA7__USBH1_DATA7 */
774 IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 0, 0x000, 0), /* MX51_PAD_DI1_PIN11__DI1_PIN11 */
775 IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 7, 0x000, 0), /* MX51_PAD_DI1_PIN11__ECSPI1_SS2 */
776 IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 4, 0x000, 0), /* MX51_PAD_DI1_PIN11__GPIO3_0 */
777 IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 0, 0x000, 0), /* MX51_PAD_DI1_PIN12__DI1_PIN12 */
778 IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 4, 0x978, 1), /* MX51_PAD_DI1_PIN12__GPIO3_1 */
779 IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 0, 0x000, 0), /* MX51_PAD_DI1_PIN13__DI1_PIN13 */
780 IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 4, 0x97c, 1), /* MX51_PAD_DI1_PIN13__GPIO3_2 */
781 IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 0, 0x000, 0), /* MX51_PAD_DI1_D0_CS__DI1_D0_CS */
782 IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 4, 0x980, 1), /* MX51_PAD_DI1_D0_CS__GPIO3_3 */
783 IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 0, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DI1_D1_CS */
784 IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 2, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN14 */
785 IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 3, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN5 */
786 IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 4, 0x984, 1), /* MX51_PAD_DI1_D1_CS__GPIO3_4 */
787 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 2, 0x9a4, 1), /* MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 */
788 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 0, 0x9c4, 0), /* MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN */
789 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 4, 0x988, 1), /* MX51_PAD_DISPB2_SER_DIN__GPIO3_5 */
790 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 */
791 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 0, 0x9c4, 1), /* MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO */
792 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 4, 0x98c, 1), /* MX51_PAD_DISPB2_SER_DIO__GPIO3_6 */
793 IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 */
794 IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 */
795 IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK */
796 IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 4, 0x990, 1), /* MX51_PAD_DISPB2_SER_CLK__GPIO3_7 */
797 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK */
798 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 */
799 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 */
800 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */
801 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */
802 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 4, 0x994, 1), /* MX51_PAD_DISPB2_SER_RS__GPIO3_8 */
803 IMX_PIN_REG(MX51_PAD_DISP1_DAT0, 0x6cc, 0x2cc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
804 IMX_PIN_REG(MX51_PAD_DISP1_DAT1, 0x6d0, 0x2d0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
805 IMX_PIN_REG(MX51_PAD_DISP1_DAT2, 0x6d4, 0x2d4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
806 IMX_PIN_REG(MX51_PAD_DISP1_DAT3, 0x6d8, 0x2d8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
807 IMX_PIN_REG(MX51_PAD_DISP1_DAT4, 0x6dc, 0x2dc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
808 IMX_PIN_REG(MX51_PAD_DISP1_DAT5, 0x6e0, 0x2e0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
809 IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT6__BOOT_USB_SRC */
810 IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
811 IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG */
812 IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
813 IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT8__BOOT_SRC0 */
814 IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
815 IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT9__BOOT_SRC1 */
816 IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
817 IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE */
818 IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
819 IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 */
820 IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
821 IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL */
822 IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
823 IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 */
824 IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
825 IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 */
826 IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
827 IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH */
828 IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
829 IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 */
830 IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
831 IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 */
832 IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
833 IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 */
834 IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
835 IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN11 */
836 IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN5 */
837 IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 */
838 IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
839 IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN12 */
840 IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN6 */
841 IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 */
842 IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
843 IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN13 */
844 IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN7 */
845 IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 */
846 IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
847 IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN14 */
848 IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN8 */
849 IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 */
850 IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
851 IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_D0_CS */
852 IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_DAT16 */
853 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 */
854 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
855 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_D1_CS */
856 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_DAT17 */
857 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_SER_CS */
858 IMX_PIN_REG(MX51_PAD_DI1_PIN3, 0x72c, 0x32c, 0, 0x000, 0), /* MX51_PAD_DI1_PIN3__DI1_PIN3 */
859 IMX_PIN_REG(MX51_PAD_DI1_PIN2, 0x734, 0x330, 0, 0x000, 0), /* MX51_PAD_DI1_PIN2__DI1_PIN2 */
860 IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 0, 0x000, 0), /* MX51_PAD_DI_GP2__DISP1_SER_CLK */
861 IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 2, 0x9a8, 1), /* MX51_PAD_DI_GP2__DISP2_WAIT */
862 IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 3, 0x9a0, 1), /* MX51_PAD_DI_GP3__CSI1_DATA_EN */
863 IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 0, 0x9c0, 0), /* MX51_PAD_DI_GP3__DISP1_SER_DIO */
864 IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 2, 0x000, 0), /* MX51_PAD_DI_GP3__FEC_TX_ER */
865 IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 3, 0x99c, 1), /* MX51_PAD_DI2_PIN4__CSI2_DATA_EN */
866 IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 0, 0x000, 0), /* MX51_PAD_DI2_PIN4__DI2_PIN4 */
867 IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 2, 0x950, 1), /* MX51_PAD_DI2_PIN4__FEC_CRS */
868 IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 0, 0x000, 0), /* MX51_PAD_DI2_PIN2__DI2_PIN2 */
869 IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 2, 0x000, 0), /* MX51_PAD_DI2_PIN2__FEC_MDC */
870 IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 0, 0x000, 0), /* MX51_PAD_DI2_PIN3__DI2_PIN3 */
871 IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 2, 0x954, 1), /* MX51_PAD_DI2_PIN3__FEC_MDIO */
872 IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 0, 0x000, 0), /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
873 IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 2, 0x95c, 1), /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
874 IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 4, 0x000, 0), /* MX51_PAD_DI_GP4__DI2_PIN15 */
875 IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 0, 0x9c0, 1), /* MX51_PAD_DI_GP4__DISP1_SER_DIN */
876 IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 3, 0x000, 0), /* MX51_PAD_DI_GP4__DISP2_PIN1 */
877 IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 2, 0x960, 1), /* MX51_PAD_DI_GP4__FEC_RDATA2 */
878 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
879 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 2, 0x964, 1), /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
880 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 4, 0x9c8, 1), /* MX51_PAD_DISP2_DAT0__KEY_COL6 */
881 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 5, 0x9f4, 8), /* MX51_PAD_DISP2_DAT0__UART3_RXD */
882 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 3, 0x9f8, 1), /* MX51_PAD_DISP2_DAT0__USBH3_CLK */
883 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
884 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 2, 0x970, 1), /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
885 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 4, 0x9cc, 1), /* MX51_PAD_DISP2_DAT1__KEY_COL7 */
886 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT1__UART3_TXD */
887 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 3, 0xa1c, 1), /* MX51_PAD_DISP2_DAT1__USBH3_DIR */
888 IMX_PIN_REG(MX51_PAD_DISP2_DAT2, 0x764, 0x35c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
889 IMX_PIN_REG(MX51_PAD_DISP2_DAT3, 0x768, 0x360, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
890 IMX_PIN_REG(MX51_PAD_DISP2_DAT4, 0x76c, 0x364, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
891 IMX_PIN_REG(MX51_PAD_DISP2_DAT5, 0x770, 0x368, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
892 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
893 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
894 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT6__GPIO1_19 */
895 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 4, 0x9d0, 1), /* MX51_PAD_DISP2_DAT6__KEY_ROW4 */
896 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 3, 0xa24, 1), /* MX51_PAD_DISP2_DAT6__USBH3_STP */
897 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
898 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
899 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT7__GPIO1_29 */
900 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 4, 0x9d4, 1), /* MX51_PAD_DISP2_DAT7__KEY_ROW5 */
901 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 3, 0xa20, 1), /* MX51_PAD_DISP2_DAT7__USBH3_NXT */
902 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
903 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
904 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT8__GPIO1_30 */
905 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 4, 0x9d8, 1), /* MX51_PAD_DISP2_DAT8__KEY_ROW6 */
906 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 3, 0x9fc, 1), /* MX51_PAD_DISP2_DAT8__USBH3_DATA0 */
907 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 4, 0x8f4, 1), /* MX51_PAD_DISP2_DAT9__AUD6_RXC */
908 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
909 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
910 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT9__GPIO1_31 */
911 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 3, 0xa00, 1), /* MX51_PAD_DISP2_DAT9__USBH3_DATA1 */
912 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
913 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_SER_CS */
914 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 2, 0x94c, 1), /* MX51_PAD_DISP2_DAT10__FEC_COL */
915 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 4, 0x9dc, 1), /* MX51_PAD_DISP2_DAT10__KEY_ROW7 */
916 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 3, 0xa04, 1), /* MX51_PAD_DISP2_DAT10__USBH3_DATA2 */
917 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 4, 0x8f0, 1), /* MX51_PAD_DISP2_DAT11__AUD6_TXD */
918 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
919 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 2, 0x968, 1), /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
920 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 7, 0x000, 0), /* MX51_PAD_DISP2_DAT11__GPIO1_10 */
921 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 3, 0xa08, 1), /* MX51_PAD_DISP2_DAT11__USBH3_DATA3 */
922 IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 4, 0x8ec, 1), /* MX51_PAD_DISP2_DAT12__AUD6_RXD */
923 IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
924 IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 2, 0x96c, 1), /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
925 IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 3, 0xa0c, 1), /* MX51_PAD_DISP2_DAT12__USBH3_DATA4 */
926 IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 4, 0x8fc, 1), /* MX51_PAD_DISP2_DAT13__AUD6_TXC */
927 IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
928 IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 2, 0x974, 1), /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
929 IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 3, 0xa10, 1), /* MX51_PAD_DISP2_DAT13__USBH3_DATA5 */
930 IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 4, 0x900, 1), /* MX51_PAD_DISP2_DAT14__AUD6_TXFS */
931 IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
932 IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 2, 0x958, 1), /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
933 IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 3, 0xa14, 1), /* MX51_PAD_DISP2_DAT14__USBH3_DATA6 */
934 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 4, 0x8f8, 1), /* MX51_PAD_DISP2_DAT15__AUD6_RXFS */
935 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP1_SER_CS */
936 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
937 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
938 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 3, 0xa18, 1), /* MX51_PAD_DISP2_DAT15__USBH3_DATA7 */
939 IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 1, 0x8e0, 1), /* MX51_PAD_SD1_CMD__AUD5_RXFS */
940 IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 2, 0x91c, 2), /* MX51_PAD_SD1_CMD__CSPI_MOSI */
941 IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 0, 0x000, 0), /* MX51_PAD_SD1_CMD__SD1_CMD */
942 IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 1, 0x8dc, 1), /* MX51_PAD_SD1_CLK__AUD5_RXC */
943 IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 2, 0x914, 2), /* MX51_PAD_SD1_CLK__CSPI_SCLK */
944 IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 0, 0x000, 0), /* MX51_PAD_SD1_CLK__SD1_CLK */
945 IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 1, 0x8d8, 2), /* MX51_PAD_SD1_DATA0__AUD5_TXD */
946 IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 2, 0x918, 1), /* MX51_PAD_SD1_DATA0__CSPI_MISO */
947 IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 0, 0x000, 0), /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
948 IMX_PIN_REG(MX51_PAD_EIM_DA0, NO_PAD, 0x01c, 0, 0x000, 0), /* MX51_PAD_EIM_DA0__EIM_DA0 */
949 IMX_PIN_REG(MX51_PAD_EIM_DA1, NO_PAD, 0x020, 0, 0x000, 0), /* MX51_PAD_EIM_DA1__EIM_DA1 */
950 IMX_PIN_REG(MX51_PAD_EIM_DA2, NO_PAD, 0x024, 0, 0x000, 0), /* MX51_PAD_EIM_DA2__EIM_DA2 */
951 IMX_PIN_REG(MX51_PAD_EIM_DA3, NO_PAD, 0x028, 0, 0x000, 0), /* MX51_PAD_EIM_DA3__EIM_DA3 */
952 IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 1, 0x8d4, 2), /* MX51_PAD_SD1_DATA1__AUD5_RXD */
953 IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 0, 0x000, 0), /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
954 IMX_PIN_REG(MX51_PAD_EIM_DA4, NO_PAD, 0x02c, 0, 0x000, 0), /* MX51_PAD_EIM_DA4__EIM_DA4 */
955 IMX_PIN_REG(MX51_PAD_EIM_DA5, NO_PAD, 0x030, 0, 0x000, 0), /* MX51_PAD_EIM_DA5__EIM_DA5 */
956 IMX_PIN_REG(MX51_PAD_EIM_DA6, NO_PAD, 0x034, 0, 0x000, 0), /* MX51_PAD_EIM_DA6__EIM_DA6 */
957 IMX_PIN_REG(MX51_PAD_EIM_DA7, NO_PAD, 0x038, 0, 0x000, 0), /* MX51_PAD_EIM_DA7__EIM_DA7 */
958 IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 1, 0x8e4, 2), /* MX51_PAD_SD1_DATA2__AUD5_TXC */
959 IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 0, 0x000, 0), /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
960 IMX_PIN_REG(MX51_PAD_EIM_DA10, NO_PAD, 0x044, 0, 0x000, 0), /* MX51_PAD_EIM_DA10__EIM_DA10 */
961 IMX_PIN_REG(MX51_PAD_EIM_DA11, NO_PAD, 0x048, 0, 0x000, 0), /* MX51_PAD_EIM_DA11__EIM_DA11 */
962 IMX_PIN_REG(MX51_PAD_EIM_DA8, NO_PAD, 0x03c, 0, 0x000, 0), /* MX51_PAD_EIM_DA8__EIM_DA8 */
963 IMX_PIN_REG(MX51_PAD_EIM_DA9, NO_PAD, 0x040, 0, 0x000, 0), /* MX51_PAD_EIM_DA9__EIM_DA9 */
964 IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 1, 0x8e8, 2), /* MX51_PAD_SD1_DATA3__AUD5_TXFS */
965 IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 2, 0x920, 1), /* MX51_PAD_SD1_DATA3__CSPI_SS1 */
966 IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 0, 0x000, 0), /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
967 IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 2, 0x924, 0), /* MX51_PAD_GPIO1_0__CSPI_SS2 */
968 IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 1, 0x000, 0), /* MX51_PAD_GPIO1_0__GPIO1_0 */
969 IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 0, 0x000, 0), /* MX51_PAD_GPIO1_0__SD1_CD */
970 IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 2, 0x918, 2), /* MX51_PAD_GPIO1_1__CSPI_MISO */
971 IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 1, 0x000, 0), /* MX51_PAD_GPIO1_1__GPIO1_1 */
972 IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 0, 0x000, 0), /* MX51_PAD_GPIO1_1__SD1_WP */
973 IMX_PIN_REG(MX51_PAD_EIM_DA12, NO_PAD, 0x04c, 0, 0x000, 0), /* MX51_PAD_EIM_DA12__EIM_DA12 */
974 IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */
975 IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */
976 IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */
977 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
978 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */
979 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */
980 IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */
981 IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 1, 0x9b4, 2), /* MX51_PAD_SD2_CLK__I2C1_SDA */
982 IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 0, 0x000, 0), /* MX51_PAD_SD2_CLK__SD2_CLK */
983 IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 2, 0x918, 3), /* MX51_PAD_SD2_DATA0__CSPI_MISO */
984 IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 1, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD1_DAT4 */
985 IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 0, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
986 IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 1, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD1_DAT5 */
987 IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 0, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
988 IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 2, 0x000, 0), /* MX51_PAD_SD2_DATA1__USBH3_H2_DP */
989 IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 1, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD1_DAT6 */
990 IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 0, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
991 IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 2, 0x000, 0), /* MX51_PAD_SD2_DATA2__USBH3_H2_DM */
992 IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 2, 0x924, 1), /* MX51_PAD_SD2_DATA3__CSPI_SS2 */
993 IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 1, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD1_DAT7 */
994 IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 0, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
995 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 5, 0x000, 0), /* MX51_PAD_GPIO1_2__CCM_OUT_2 */
996 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 0, 0x000, 0), /* MX51_PAD_GPIO1_2__GPIO1_2 */
997 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 2, 0x9b8, 3), /* MX51_PAD_GPIO1_2__I2C2_SCL */
998 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 7, 0x90c, 1), /* MX51_PAD_GPIO1_2__PLL1_BYP */
999 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 1, 0x000, 0), /* MX51_PAD_GPIO1_2__PWM1_PWMO */
1000 IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 0, 0x000, 0), /* MX51_PAD_GPIO1_3__GPIO1_3 */
1001 IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 2, 0x9bc, 3), /* MX51_PAD_GPIO1_3__I2C2_SDA */
1002 IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 7, 0x910, 1), /* MX51_PAD_GPIO1_3__PLL2_BYP */
1003 IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 1, 0x000, 0), /* MX51_PAD_GPIO1_3__PWM2_PWMO */
1004 IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 0, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ */
1005 IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 1, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B */
1006 IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 4, 0x908, 1), /* MX51_PAD_GPIO1_4__DISP2_EXT_CLK */
1007 IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 3, 0x938, 1), /* MX51_PAD_GPIO1_4__EIM_RDY */
1008 IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 0, 0x000, 0), /* MX51_PAD_GPIO1_4__GPIO1_4 */
1009 IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 2, 0x000, 0), /* MX51_PAD_GPIO1_4__WDOG1_WDOG_B */
1010 IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 6, 0x000, 0), /* MX51_PAD_GPIO1_5__CSI2_MCLK */
1011 IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 3, 0x000, 0), /* MX51_PAD_GPIO1_5__DISP2_PIN16 */
1012 IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 0, 0x000, 0), /* MX51_PAD_GPIO1_5__GPIO1_5 */
1013 IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 2, 0x000, 0), /* MX51_PAD_GPIO1_5__WDOG2_WDOG_B */
1014 IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 4, 0x000, 0), /* MX51_PAD_GPIO1_6__DISP2_PIN17 */
1015 IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 0, 0x000, 0), /* MX51_PAD_GPIO1_6__GPIO1_6 */
1016 IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 3, 0x000, 0), /* MX51_PAD_GPIO1_6__REF_EN_B */
1017 IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 3, 0x000, 0), /* MX51_PAD_GPIO1_7__CCM_OUT_0 */
1018 IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 0, 0x000, 0), /* MX51_PAD_GPIO1_7__GPIO1_7 */
1019 IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 6, 0x000, 0), /* MX51_PAD_GPIO1_7__SD2_WP */
1020 IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 2, 0x000, 0), /* MX51_PAD_GPIO1_7__SPDIF_OUT1 */
1021 IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 2, 0x99c, 2), /* MX51_PAD_GPIO1_8__CSI2_DATA_EN */
1022 IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 0, 0x000, 0), /* MX51_PAD_GPIO1_8__GPIO1_8 */
1023 IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 6, 0x000, 0), /* MX51_PAD_GPIO1_8__SD2_CD */
1024 IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 1, 0x000, 0), /* MX51_PAD_GPIO1_8__USBH3_PWR */
1025 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 3, 0x000, 0), /* MX51_PAD_GPIO1_9__CCM_OUT_1 */
1026 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 2, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_D1_CS */
1027 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 7, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_SER_CS */
1028 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 0, 0x000, 0), /* MX51_PAD_GPIO1_9__GPIO1_9 */
1029 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 6, 0x000, 0), /* MX51_PAD_GPIO1_9__SD2_LCTL */
1030 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 1, 0x000, 0), /* MX51_PAD_GPIO1_9__USBH3_OC */
1031}; 393};
1032 394
1033/* Pad names for the pinmux subsystem */ 395/* Pad names for the pinmux subsystem */
1034static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { 396static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
397 IMX_PINCTRL_PIN(MX51_PAD_RESERVE0),
398 IMX_PINCTRL_PIN(MX51_PAD_RESERVE1),
399 IMX_PINCTRL_PIN(MX51_PAD_RESERVE2),
400 IMX_PINCTRL_PIN(MX51_PAD_RESERVE3),
401 IMX_PINCTRL_PIN(MX51_PAD_RESERVE4),
402 IMX_PINCTRL_PIN(MX51_PAD_RESERVE5),
403 IMX_PINCTRL_PIN(MX51_PAD_RESERVE6),
404 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
405 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
406 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
407 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
408 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
409 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
410 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
411 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
412 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
413 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
414 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
415 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
416 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
417 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
418 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
419 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
1035 IMX_PINCTRL_PIN(MX51_PAD_EIM_D16), 420 IMX_PINCTRL_PIN(MX51_PAD_EIM_D16),
1036 IMX_PINCTRL_PIN(MX51_PAD_EIM_D17), 421 IMX_PINCTRL_PIN(MX51_PAD_EIM_D17),
1037 IMX_PINCTRL_PIN(MX51_PAD_EIM_D18), 422 IMX_PINCTRL_PIN(MX51_PAD_EIM_D18),
@@ -1124,8 +509,6 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
1124 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19), 509 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19),
1125 IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC), 510 IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC),
1126 IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC), 511 IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC),
1127 IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
1128 IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
1129 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12), 512 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12),
1130 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13), 513 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13),
1131 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14), 514 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14),
@@ -1168,6 +551,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
1168 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3), 551 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3),
1169 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4), 552 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4),
1170 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5), 553 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5),
554 IMX_PINCTRL_PIN(MX51_PAD_RESERVE7),
1171 IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK), 555 IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK),
1172 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR), 556 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR),
1173 IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP), 557 IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP),
@@ -1215,6 +599,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
1215 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23), 599 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23),
1216 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3), 600 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3),
1217 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2), 601 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2),
602 IMX_PINCTRL_PIN(MX51_PAD_RESERVE8),
1218 IMX_PINCTRL_PIN(MX51_PAD_DI_GP2), 603 IMX_PINCTRL_PIN(MX51_PAD_DI_GP2),
1219 IMX_PINCTRL_PIN(MX51_PAD_DI_GP3), 604 IMX_PINCTRL_PIN(MX51_PAD_DI_GP3),
1220 IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4), 605 IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4),
@@ -1241,27 +626,11 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
1241 IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD), 626 IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD),
1242 IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK), 627 IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK),
1243 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0), 628 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0),
1244 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
1245 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
1246 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
1247 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
1248 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1), 629 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1),
1249 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
1250 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
1251 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
1252 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
1253 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2), 630 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2),
1254 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
1255 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
1256 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
1257 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
1258 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3), 631 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3),
1259 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0), 632 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0),
1260 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1), 633 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1),
1261 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
1262 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
1263 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
1264 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
1265 IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD), 634 IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD),
1266 IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK), 635 IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK),
1267 IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0), 636 IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0),
@@ -1277,13 +646,126 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
1277 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7), 646 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7),
1278 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8), 647 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8),
1279 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9), 648 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9),
649 IMX_PINCTRL_PIN(MX51_PAD_RESERVE9),
650 IMX_PINCTRL_PIN(MX51_PAD_RESERVE10),
651 IMX_PINCTRL_PIN(MX51_PAD_RESERVE11),
652 IMX_PINCTRL_PIN(MX51_PAD_RESERVE12),
653 IMX_PINCTRL_PIN(MX51_PAD_RESERVE13),
654 IMX_PINCTRL_PIN(MX51_PAD_RESERVE14),
655 IMX_PINCTRL_PIN(MX51_PAD_RESERVE15),
656 IMX_PINCTRL_PIN(MX51_PAD_RESERVE16),
657 IMX_PINCTRL_PIN(MX51_PAD_RESERVE17),
658 IMX_PINCTRL_PIN(MX51_PAD_RESERVE18),
659 IMX_PINCTRL_PIN(MX51_PAD_RESERVE19),
660 IMX_PINCTRL_PIN(MX51_PAD_RESERVE20),
661 IMX_PINCTRL_PIN(MX51_PAD_RESERVE21),
662 IMX_PINCTRL_PIN(MX51_PAD_RESERVE22),
663 IMX_PINCTRL_PIN(MX51_PAD_RESERVE23),
664 IMX_PINCTRL_PIN(MX51_PAD_RESERVE24),
665 IMX_PINCTRL_PIN(MX51_PAD_RESERVE25),
666 IMX_PINCTRL_PIN(MX51_PAD_RESERVE26),
667 IMX_PINCTRL_PIN(MX51_PAD_RESERVE27),
668 IMX_PINCTRL_PIN(MX51_PAD_RESERVE28),
669 IMX_PINCTRL_PIN(MX51_PAD_RESERVE29),
670 IMX_PINCTRL_PIN(MX51_PAD_RESERVE30),
671 IMX_PINCTRL_PIN(MX51_PAD_RESERVE31),
672 IMX_PINCTRL_PIN(MX51_PAD_RESERVE32),
673 IMX_PINCTRL_PIN(MX51_PAD_RESERVE33),
674 IMX_PINCTRL_PIN(MX51_PAD_RESERVE34),
675 IMX_PINCTRL_PIN(MX51_PAD_RESERVE35),
676 IMX_PINCTRL_PIN(MX51_PAD_RESERVE36),
677 IMX_PINCTRL_PIN(MX51_PAD_RESERVE37),
678 IMX_PINCTRL_PIN(MX51_PAD_RESERVE38),
679 IMX_PINCTRL_PIN(MX51_PAD_RESERVE39),
680 IMX_PINCTRL_PIN(MX51_PAD_RESERVE40),
681 IMX_PINCTRL_PIN(MX51_PAD_RESERVE41),
682 IMX_PINCTRL_PIN(MX51_PAD_RESERVE42),
683 IMX_PINCTRL_PIN(MX51_PAD_RESERVE43),
684 IMX_PINCTRL_PIN(MX51_PAD_RESERVE44),
685 IMX_PINCTRL_PIN(MX51_PAD_RESERVE45),
686 IMX_PINCTRL_PIN(MX51_PAD_RESERVE46),
687 IMX_PINCTRL_PIN(MX51_PAD_RESERVE47),
688 IMX_PINCTRL_PIN(MX51_PAD_RESERVE48),
689 IMX_PINCTRL_PIN(MX51_PAD_RESERVE49),
690 IMX_PINCTRL_PIN(MX51_PAD_RESERVE50),
691 IMX_PINCTRL_PIN(MX51_PAD_RESERVE51),
692 IMX_PINCTRL_PIN(MX51_PAD_RESERVE52),
693 IMX_PINCTRL_PIN(MX51_PAD_RESERVE53),
694 IMX_PINCTRL_PIN(MX51_PAD_RESERVE54),
695 IMX_PINCTRL_PIN(MX51_PAD_RESERVE55),
696 IMX_PINCTRL_PIN(MX51_PAD_RESERVE56),
697 IMX_PINCTRL_PIN(MX51_PAD_RESERVE57),
698 IMX_PINCTRL_PIN(MX51_PAD_RESERVE58),
699 IMX_PINCTRL_PIN(MX51_PAD_RESERVE59),
700 IMX_PINCTRL_PIN(MX51_PAD_RESERVE60),
701 IMX_PINCTRL_PIN(MX51_PAD_RESERVE61),
702 IMX_PINCTRL_PIN(MX51_PAD_RESERVE62),
703 IMX_PINCTRL_PIN(MX51_PAD_RESERVE63),
704 IMX_PINCTRL_PIN(MX51_PAD_RESERVE64),
705 IMX_PINCTRL_PIN(MX51_PAD_RESERVE65),
706 IMX_PINCTRL_PIN(MX51_PAD_RESERVE66),
707 IMX_PINCTRL_PIN(MX51_PAD_RESERVE67),
708 IMX_PINCTRL_PIN(MX51_PAD_RESERVE68),
709 IMX_PINCTRL_PIN(MX51_PAD_RESERVE69),
710 IMX_PINCTRL_PIN(MX51_PAD_RESERVE70),
711 IMX_PINCTRL_PIN(MX51_PAD_RESERVE71),
712 IMX_PINCTRL_PIN(MX51_PAD_RESERVE72),
713 IMX_PINCTRL_PIN(MX51_PAD_RESERVE73),
714 IMX_PINCTRL_PIN(MX51_PAD_RESERVE74),
715 IMX_PINCTRL_PIN(MX51_PAD_RESERVE75),
716 IMX_PINCTRL_PIN(MX51_PAD_RESERVE76),
717 IMX_PINCTRL_PIN(MX51_PAD_RESERVE77),
718 IMX_PINCTRL_PIN(MX51_PAD_RESERVE78),
719 IMX_PINCTRL_PIN(MX51_PAD_RESERVE79),
720 IMX_PINCTRL_PIN(MX51_PAD_RESERVE80),
721 IMX_PINCTRL_PIN(MX51_PAD_RESERVE81),
722 IMX_PINCTRL_PIN(MX51_PAD_RESERVE82),
723 IMX_PINCTRL_PIN(MX51_PAD_RESERVE83),
724 IMX_PINCTRL_PIN(MX51_PAD_RESERVE84),
725 IMX_PINCTRL_PIN(MX51_PAD_RESERVE85),
726 IMX_PINCTRL_PIN(MX51_PAD_RESERVE86),
727 IMX_PINCTRL_PIN(MX51_PAD_RESERVE87),
728 IMX_PINCTRL_PIN(MX51_PAD_RESERVE88),
729 IMX_PINCTRL_PIN(MX51_PAD_RESERVE89),
730 IMX_PINCTRL_PIN(MX51_PAD_RESERVE90),
731 IMX_PINCTRL_PIN(MX51_PAD_RESERVE91),
732 IMX_PINCTRL_PIN(MX51_PAD_RESERVE92),
733 IMX_PINCTRL_PIN(MX51_PAD_RESERVE93),
734 IMX_PINCTRL_PIN(MX51_PAD_RESERVE94),
735 IMX_PINCTRL_PIN(MX51_PAD_RESERVE95),
736 IMX_PINCTRL_PIN(MX51_PAD_RESERVE96),
737 IMX_PINCTRL_PIN(MX51_PAD_RESERVE97),
738 IMX_PINCTRL_PIN(MX51_PAD_RESERVE98),
739 IMX_PINCTRL_PIN(MX51_PAD_RESERVE99),
740 IMX_PINCTRL_PIN(MX51_PAD_RESERVE100),
741 IMX_PINCTRL_PIN(MX51_PAD_RESERVE101),
742 IMX_PINCTRL_PIN(MX51_PAD_RESERVE102),
743 IMX_PINCTRL_PIN(MX51_PAD_RESERVE103),
744 IMX_PINCTRL_PIN(MX51_PAD_RESERVE104),
745 IMX_PINCTRL_PIN(MX51_PAD_RESERVE105),
746 IMX_PINCTRL_PIN(MX51_PAD_RESERVE106),
747 IMX_PINCTRL_PIN(MX51_PAD_RESERVE107),
748 IMX_PINCTRL_PIN(MX51_PAD_RESERVE108),
749 IMX_PINCTRL_PIN(MX51_PAD_RESERVE109),
750 IMX_PINCTRL_PIN(MX51_PAD_RESERVE110),
751 IMX_PINCTRL_PIN(MX51_PAD_RESERVE111),
752 IMX_PINCTRL_PIN(MX51_PAD_RESERVE112),
753 IMX_PINCTRL_PIN(MX51_PAD_RESERVE113),
754 IMX_PINCTRL_PIN(MX51_PAD_RESERVE114),
755 IMX_PINCTRL_PIN(MX51_PAD_RESERVE115),
756 IMX_PINCTRL_PIN(MX51_PAD_RESERVE116),
757 IMX_PINCTRL_PIN(MX51_PAD_RESERVE117),
758 IMX_PINCTRL_PIN(MX51_PAD_RESERVE118),
759 IMX_PINCTRL_PIN(MX51_PAD_RESERVE119),
760 IMX_PINCTRL_PIN(MX51_PAD_RESERVE120),
761 IMX_PINCTRL_PIN(MX51_PAD_RESERVE121),
762 IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
763 IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
1280}; 764};
1281 765
1282static struct imx_pinctrl_soc_info imx51_pinctrl_info = { 766static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
1283 .pins = imx51_pinctrl_pads, 767 .pins = imx51_pinctrl_pads,
1284 .npins = ARRAY_SIZE(imx51_pinctrl_pads), 768 .npins = ARRAY_SIZE(imx51_pinctrl_pads),
1285 .pin_regs = imx51_pin_regs,
1286 .npin_regs = ARRAY_SIZE(imx51_pin_regs),
1287}; 769};
1288 770
1289static struct of_device_id imx51_pinctrl_of_match[] = { 771static struct of_device_id imx51_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
index 2c9c8e2334da..17562ae9005c 100644
--- a/drivers/pinctrl/pinctrl-imx53.c
+++ b/drivers/pinctrl/pinctrl-imx53.c
@@ -23,1386 +23,228 @@
23#include "pinctrl-imx.h" 23#include "pinctrl-imx.h"
24 24
25enum imx53_pads { 25enum imx53_pads {
26 MX53_PAD_GPIO_19 = 0, 26 MX53_PAD_RESERVE0 = 0,
27 MX53_PAD_KEY_COL0 = 1, 27 MX53_PAD_RESERVE1 = 1,
28 MX53_PAD_KEY_ROW0 = 2, 28 MX53_PAD_RESERVE2 = 2,
29 MX53_PAD_KEY_COL1 = 3, 29 MX53_PAD_RESERVE3 = 3,
30 MX53_PAD_KEY_ROW1 = 4, 30 MX53_PAD_RESERVE4 = 4,
31 MX53_PAD_KEY_COL2 = 5, 31 MX53_PAD_RESERVE5 = 5,
32 MX53_PAD_KEY_ROW2 = 6, 32 MX53_PAD_RESERVE6 = 6,
33 MX53_PAD_KEY_COL3 = 7, 33 MX53_PAD_RESERVE7 = 7,
34 MX53_PAD_KEY_ROW3 = 8, 34 MX53_PAD_GPIO_19 = 8,
35 MX53_PAD_KEY_COL4 = 9, 35 MX53_PAD_KEY_COL0 = 9,
36 MX53_PAD_KEY_ROW4 = 10, 36 MX53_PAD_KEY_ROW0 = 10,
37 MX53_PAD_DI0_DISP_CLK = 11, 37 MX53_PAD_KEY_COL1 = 11,
38 MX53_PAD_DI0_PIN15 = 12, 38 MX53_PAD_KEY_ROW1 = 12,
39 MX53_PAD_DI0_PIN2 = 13, 39 MX53_PAD_KEY_COL2 = 13,
40 MX53_PAD_DI0_PIN3 = 14, 40 MX53_PAD_KEY_ROW2 = 14,
41 MX53_PAD_DI0_PIN4 = 15, 41 MX53_PAD_KEY_COL3 = 15,
42 MX53_PAD_DISP0_DAT0 = 16, 42 MX53_PAD_KEY_ROW3 = 16,
43 MX53_PAD_DISP0_DAT1 = 17, 43 MX53_PAD_KEY_COL4 = 17,
44 MX53_PAD_DISP0_DAT2 = 18, 44 MX53_PAD_KEY_ROW4 = 18,
45 MX53_PAD_DISP0_DAT3 = 19, 45 MX53_PAD_DI0_DISP_CLK = 19,
46 MX53_PAD_DISP0_DAT4 = 20, 46 MX53_PAD_DI0_PIN15 = 20,
47 MX53_PAD_DISP0_DAT5 = 21, 47 MX53_PAD_DI0_PIN2 = 21,
48 MX53_PAD_DISP0_DAT6 = 22, 48 MX53_PAD_DI0_PIN3 = 22,
49 MX53_PAD_DISP0_DAT7 = 23, 49 MX53_PAD_DI0_PIN4 = 23,
50 MX53_PAD_DISP0_DAT8 = 24, 50 MX53_PAD_DISP0_DAT0 = 24,
51 MX53_PAD_DISP0_DAT9 = 25, 51 MX53_PAD_DISP0_DAT1 = 25,
52 MX53_PAD_DISP0_DAT10 = 26, 52 MX53_PAD_DISP0_DAT2 = 26,
53 MX53_PAD_DISP0_DAT11 = 27, 53 MX53_PAD_DISP0_DAT3 = 27,
54 MX53_PAD_DISP0_DAT12 = 28, 54 MX53_PAD_DISP0_DAT4 = 28,
55 MX53_PAD_DISP0_DAT13 = 29, 55 MX53_PAD_DISP0_DAT5 = 29,
56 MX53_PAD_DISP0_DAT14 = 30, 56 MX53_PAD_DISP0_DAT6 = 30,
57 MX53_PAD_DISP0_DAT15 = 31, 57 MX53_PAD_DISP0_DAT7 = 31,
58 MX53_PAD_DISP0_DAT16 = 32, 58 MX53_PAD_DISP0_DAT8 = 32,
59 MX53_PAD_DISP0_DAT17 = 33, 59 MX53_PAD_DISP0_DAT9 = 33,
60 MX53_PAD_DISP0_DAT18 = 34, 60 MX53_PAD_DISP0_DAT10 = 34,
61 MX53_PAD_DISP0_DAT19 = 35, 61 MX53_PAD_DISP0_DAT11 = 35,
62 MX53_PAD_DISP0_DAT20 = 36, 62 MX53_PAD_DISP0_DAT12 = 36,
63 MX53_PAD_DISP0_DAT21 = 37, 63 MX53_PAD_DISP0_DAT13 = 37,
64 MX53_PAD_DISP0_DAT22 = 38, 64 MX53_PAD_DISP0_DAT14 = 38,
65 MX53_PAD_DISP0_DAT23 = 39, 65 MX53_PAD_DISP0_DAT15 = 39,
66 MX53_PAD_CSI0_PIXCLK = 40, 66 MX53_PAD_DISP0_DAT16 = 40,
67 MX53_PAD_CSI0_MCLK = 41, 67 MX53_PAD_DISP0_DAT17 = 41,
68 MX53_PAD_CSI0_DATA_EN = 42, 68 MX53_PAD_DISP0_DAT18 = 42,
69 MX53_PAD_CSI0_VSYNC = 43, 69 MX53_PAD_DISP0_DAT19 = 43,
70 MX53_PAD_CSI0_DAT4 = 44, 70 MX53_PAD_DISP0_DAT20 = 44,
71 MX53_PAD_CSI0_DAT5 = 45, 71 MX53_PAD_DISP0_DAT21 = 45,
72 MX53_PAD_CSI0_DAT6 = 46, 72 MX53_PAD_DISP0_DAT22 = 46,
73 MX53_PAD_CSI0_DAT7 = 47, 73 MX53_PAD_DISP0_DAT23 = 47,
74 MX53_PAD_CSI0_DAT8 = 48, 74 MX53_PAD_CSI0_PIXCLK = 48,
75 MX53_PAD_CSI0_DAT9 = 49, 75 MX53_PAD_CSI0_MCLK = 49,
76 MX53_PAD_CSI0_DAT10 = 50, 76 MX53_PAD_CSI0_DATA_EN = 50,
77 MX53_PAD_CSI0_DAT11 = 51, 77 MX53_PAD_CSI0_VSYNC = 51,
78 MX53_PAD_CSI0_DAT12 = 52, 78 MX53_PAD_CSI0_DAT4 = 52,
79 MX53_PAD_CSI0_DAT13 = 53, 79 MX53_PAD_CSI0_DAT5 = 53,
80 MX53_PAD_CSI0_DAT14 = 54, 80 MX53_PAD_CSI0_DAT6 = 54,
81 MX53_PAD_CSI0_DAT15 = 55, 81 MX53_PAD_CSI0_DAT7 = 55,
82 MX53_PAD_CSI0_DAT16 = 56, 82 MX53_PAD_CSI0_DAT8 = 56,
83 MX53_PAD_CSI0_DAT17 = 57, 83 MX53_PAD_CSI0_DAT9 = 57,
84 MX53_PAD_CSI0_DAT18 = 58, 84 MX53_PAD_CSI0_DAT10 = 58,
85 MX53_PAD_CSI0_DAT19 = 59, 85 MX53_PAD_CSI0_DAT11 = 59,
86 MX53_PAD_EIM_A25 = 60, 86 MX53_PAD_CSI0_DAT12 = 60,
87 MX53_PAD_EIM_EB2 = 61, 87 MX53_PAD_CSI0_DAT13 = 61,
88 MX53_PAD_EIM_D16 = 62, 88 MX53_PAD_CSI0_DAT14 = 62,
89 MX53_PAD_EIM_D17 = 63, 89 MX53_PAD_CSI0_DAT15 = 63,
90 MX53_PAD_EIM_D18 = 64, 90 MX53_PAD_CSI0_DAT16 = 64,
91 MX53_PAD_EIM_D19 = 65, 91 MX53_PAD_CSI0_DAT17 = 65,
92 MX53_PAD_EIM_D20 = 66, 92 MX53_PAD_CSI0_DAT18 = 66,
93 MX53_PAD_EIM_D21 = 67, 93 MX53_PAD_CSI0_DAT19 = 67,
94 MX53_PAD_EIM_D22 = 68, 94 MX53_PAD_EIM_A25 = 68,
95 MX53_PAD_EIM_D23 = 69, 95 MX53_PAD_EIM_EB2 = 69,
96 MX53_PAD_EIM_EB3 = 70, 96 MX53_PAD_EIM_D16 = 70,
97 MX53_PAD_EIM_D24 = 71, 97 MX53_PAD_EIM_D17 = 71,
98 MX53_PAD_EIM_D25 = 72, 98 MX53_PAD_EIM_D18 = 72,
99 MX53_PAD_EIM_D26 = 73, 99 MX53_PAD_EIM_D19 = 73,
100 MX53_PAD_EIM_D27 = 74, 100 MX53_PAD_EIM_D20 = 74,
101 MX53_PAD_EIM_D28 = 75, 101 MX53_PAD_EIM_D21 = 75,
102 MX53_PAD_EIM_D29 = 76, 102 MX53_PAD_EIM_D22 = 76,
103 MX53_PAD_EIM_D30 = 77, 103 MX53_PAD_EIM_D23 = 77,
104 MX53_PAD_EIM_D31 = 78, 104 MX53_PAD_EIM_EB3 = 78,
105 MX53_PAD_EIM_A24 = 79, 105 MX53_PAD_EIM_D24 = 79,
106 MX53_PAD_EIM_A23 = 80, 106 MX53_PAD_EIM_D25 = 80,
107 MX53_PAD_EIM_A22 = 81, 107 MX53_PAD_EIM_D26 = 81,
108 MX53_PAD_EIM_A21 = 82, 108 MX53_PAD_EIM_D27 = 82,
109 MX53_PAD_EIM_A20 = 83, 109 MX53_PAD_EIM_D28 = 83,
110 MX53_PAD_EIM_A19 = 84, 110 MX53_PAD_EIM_D29 = 84,
111 MX53_PAD_EIM_A18 = 85, 111 MX53_PAD_EIM_D30 = 85,
112 MX53_PAD_EIM_A17 = 86, 112 MX53_PAD_EIM_D31 = 86,
113 MX53_PAD_EIM_A16 = 87, 113 MX53_PAD_EIM_A24 = 87,
114 MX53_PAD_EIM_CS0 = 88, 114 MX53_PAD_EIM_A23 = 88,
115 MX53_PAD_EIM_CS1 = 89, 115 MX53_PAD_EIM_A22 = 89,
116 MX53_PAD_EIM_OE = 90, 116 MX53_PAD_EIM_A21 = 90,
117 MX53_PAD_EIM_RW = 91, 117 MX53_PAD_EIM_A20 = 91,
118 MX53_PAD_EIM_LBA = 92, 118 MX53_PAD_EIM_A19 = 92,
119 MX53_PAD_EIM_EB0 = 93, 119 MX53_PAD_EIM_A18 = 93,
120 MX53_PAD_EIM_EB1 = 94, 120 MX53_PAD_EIM_A17 = 94,
121 MX53_PAD_EIM_DA0 = 95, 121 MX53_PAD_EIM_A16 = 95,
122 MX53_PAD_EIM_DA1 = 96, 122 MX53_PAD_EIM_CS0 = 96,
123 MX53_PAD_EIM_DA2 = 97, 123 MX53_PAD_EIM_CS1 = 97,
124 MX53_PAD_EIM_DA3 = 98, 124 MX53_PAD_EIM_OE = 98,
125 MX53_PAD_EIM_DA4 = 99, 125 MX53_PAD_EIM_RW = 99,
126 MX53_PAD_EIM_DA5 = 100, 126 MX53_PAD_EIM_LBA = 100,
127 MX53_PAD_EIM_DA6 = 101, 127 MX53_PAD_EIM_EB0 = 101,
128 MX53_PAD_EIM_DA7 = 102, 128 MX53_PAD_EIM_EB1 = 102,
129 MX53_PAD_EIM_DA8 = 103, 129 MX53_PAD_EIM_DA0 = 103,
130 MX53_PAD_EIM_DA9 = 104, 130 MX53_PAD_EIM_DA1 = 104,
131 MX53_PAD_EIM_DA10 = 105, 131 MX53_PAD_EIM_DA2 = 105,
132 MX53_PAD_EIM_DA11 = 106, 132 MX53_PAD_EIM_DA3 = 106,
133 MX53_PAD_EIM_DA12 = 107, 133 MX53_PAD_EIM_DA4 = 107,
134 MX53_PAD_EIM_DA13 = 108, 134 MX53_PAD_EIM_DA5 = 108,
135 MX53_PAD_EIM_DA14 = 109, 135 MX53_PAD_EIM_DA6 = 109,
136 MX53_PAD_EIM_DA15 = 110, 136 MX53_PAD_EIM_DA7 = 110,
137 MX53_PAD_NANDF_WE_B = 111, 137 MX53_PAD_EIM_DA8 = 111,
138 MX53_PAD_NANDF_RE_B = 112, 138 MX53_PAD_EIM_DA9 = 112,
139 MX53_PAD_EIM_WAIT = 113, 139 MX53_PAD_EIM_DA10 = 113,
140 MX53_PAD_LVDS1_TX3_P = 114, 140 MX53_PAD_EIM_DA11 = 114,
141 MX53_PAD_LVDS1_TX2_P = 115, 141 MX53_PAD_EIM_DA12 = 115,
142 MX53_PAD_LVDS1_CLK_P = 116, 142 MX53_PAD_EIM_DA13 = 116,
143 MX53_PAD_LVDS1_TX1_P = 117, 143 MX53_PAD_EIM_DA14 = 117,
144 MX53_PAD_LVDS1_TX0_P = 118, 144 MX53_PAD_EIM_DA15 = 118,
145 MX53_PAD_LVDS0_TX3_P = 119, 145 MX53_PAD_NANDF_WE_B = 119,
146 MX53_PAD_LVDS0_CLK_P = 120, 146 MX53_PAD_NANDF_RE_B = 120,
147 MX53_PAD_LVDS0_TX2_P = 121, 147 MX53_PAD_EIM_WAIT = 121,
148 MX53_PAD_LVDS0_TX1_P = 122, 148 MX53_PAD_RESERVE8 = 122,
149 MX53_PAD_LVDS0_TX0_P = 123, 149 MX53_PAD_LVDS1_TX3_P = 123,
150 MX53_PAD_GPIO_10 = 124, 150 MX53_PAD_LVDS1_TX2_P = 124,
151 MX53_PAD_GPIO_11 = 125, 151 MX53_PAD_LVDS1_CLK_P = 125,
152 MX53_PAD_GPIO_12 = 126, 152 MX53_PAD_LVDS1_TX1_P = 126,
153 MX53_PAD_GPIO_13 = 127, 153 MX53_PAD_LVDS1_TX0_P = 127,
154 MX53_PAD_GPIO_14 = 128, 154 MX53_PAD_LVDS0_TX3_P = 128,
155 MX53_PAD_NANDF_CLE = 129, 155 MX53_PAD_LVDS0_CLK_P = 129,
156 MX53_PAD_NANDF_ALE = 130, 156 MX53_PAD_LVDS0_TX2_P = 130,
157 MX53_PAD_NANDF_WP_B = 131, 157 MX53_PAD_LVDS0_TX1_P = 131,
158 MX53_PAD_NANDF_RB0 = 132, 158 MX53_PAD_LVDS0_TX0_P = 132,
159 MX53_PAD_NANDF_CS0 = 133, 159 MX53_PAD_GPIO_10 = 133,
160 MX53_PAD_NANDF_CS1 = 134, 160 MX53_PAD_GPIO_11 = 134,
161 MX53_PAD_NANDF_CS2 = 135, 161 MX53_PAD_GPIO_12 = 135,
162 MX53_PAD_NANDF_CS3 = 136, 162 MX53_PAD_GPIO_13 = 136,
163 MX53_PAD_FEC_MDIO = 137, 163 MX53_PAD_GPIO_14 = 137,
164 MX53_PAD_FEC_REF_CLK = 138, 164 MX53_PAD_NANDF_CLE = 138,
165 MX53_PAD_FEC_RX_ER = 139, 165 MX53_PAD_NANDF_ALE = 139,
166 MX53_PAD_FEC_CRS_DV = 140, 166 MX53_PAD_NANDF_WP_B = 140,
167 MX53_PAD_FEC_RXD1 = 141, 167 MX53_PAD_NANDF_RB0 = 141,
168 MX53_PAD_FEC_RXD0 = 142, 168 MX53_PAD_NANDF_CS0 = 142,
169 MX53_PAD_FEC_TX_EN = 143, 169 MX53_PAD_NANDF_CS1 = 143,
170 MX53_PAD_FEC_TXD1 = 144, 170 MX53_PAD_NANDF_CS2 = 144,
171 MX53_PAD_FEC_TXD0 = 145, 171 MX53_PAD_NANDF_CS3 = 145,
172 MX53_PAD_FEC_MDC = 146, 172 MX53_PAD_FEC_MDIO = 146,
173 MX53_PAD_PATA_DIOW = 147, 173 MX53_PAD_FEC_REF_CLK = 147,
174 MX53_PAD_PATA_DMACK = 148, 174 MX53_PAD_FEC_RX_ER = 148,
175 MX53_PAD_PATA_DMARQ = 149, 175 MX53_PAD_FEC_CRS_DV = 149,
176 MX53_PAD_PATA_BUFFER_EN = 150, 176 MX53_PAD_FEC_RXD1 = 150,
177 MX53_PAD_PATA_INTRQ = 151, 177 MX53_PAD_FEC_RXD0 = 151,
178 MX53_PAD_PATA_DIOR = 152, 178 MX53_PAD_FEC_TX_EN = 152,
179 MX53_PAD_PATA_RESET_B = 153, 179 MX53_PAD_FEC_TXD1 = 153,
180 MX53_PAD_PATA_IORDY = 154, 180 MX53_PAD_FEC_TXD0 = 154,
181 MX53_PAD_PATA_DA_0 = 155, 181 MX53_PAD_FEC_MDC = 155,
182 MX53_PAD_PATA_DA_1 = 156, 182 MX53_PAD_PATA_DIOW = 156,
183 MX53_PAD_PATA_DA_2 = 157, 183 MX53_PAD_PATA_DMACK = 157,
184 MX53_PAD_PATA_CS_0 = 158, 184 MX53_PAD_PATA_DMARQ = 158,
185 MX53_PAD_PATA_CS_1 = 159, 185 MX53_PAD_PATA_BUFFER_EN = 159,
186 MX53_PAD_PATA_DATA0 = 160, 186 MX53_PAD_PATA_INTRQ = 160,
187 MX53_PAD_PATA_DATA1 = 161, 187 MX53_PAD_PATA_DIOR = 161,
188 MX53_PAD_PATA_DATA2 = 162, 188 MX53_PAD_PATA_RESET_B = 162,
189 MX53_PAD_PATA_DATA3 = 163, 189 MX53_PAD_PATA_IORDY = 163,
190 MX53_PAD_PATA_DATA4 = 164, 190 MX53_PAD_PATA_DA_0 = 164,
191 MX53_PAD_PATA_DATA5 = 165, 191 MX53_PAD_PATA_DA_1 = 165,
192 MX53_PAD_PATA_DATA6 = 166, 192 MX53_PAD_PATA_DA_2 = 166,
193 MX53_PAD_PATA_DATA7 = 167, 193 MX53_PAD_PATA_CS_0 = 167,
194 MX53_PAD_PATA_DATA8 = 168, 194 MX53_PAD_PATA_CS_1 = 168,
195 MX53_PAD_PATA_DATA9 = 169, 195 MX53_PAD_PATA_DATA0 = 169,
196 MX53_PAD_PATA_DATA10 = 170, 196 MX53_PAD_PATA_DATA1 = 170,
197 MX53_PAD_PATA_DATA11 = 171, 197 MX53_PAD_PATA_DATA2 = 171,
198 MX53_PAD_PATA_DATA12 = 172, 198 MX53_PAD_PATA_DATA3 = 172,
199 MX53_PAD_PATA_DATA13 = 173, 199 MX53_PAD_PATA_DATA4 = 173,
200 MX53_PAD_PATA_DATA14 = 174, 200 MX53_PAD_PATA_DATA5 = 174,
201 MX53_PAD_PATA_DATA15 = 175, 201 MX53_PAD_PATA_DATA6 = 175,
202 MX53_PAD_SD1_DATA0 = 176, 202 MX53_PAD_PATA_DATA7 = 176,
203 MX53_PAD_SD1_DATA1 = 177, 203 MX53_PAD_PATA_DATA8 = 177,
204 MX53_PAD_SD1_CMD = 178, 204 MX53_PAD_PATA_DATA9 = 178,
205 MX53_PAD_SD1_DATA2 = 179, 205 MX53_PAD_PATA_DATA10 = 179,
206 MX53_PAD_SD1_CLK = 180, 206 MX53_PAD_PATA_DATA11 = 180,
207 MX53_PAD_SD1_DATA3 = 181, 207 MX53_PAD_PATA_DATA12 = 181,
208 MX53_PAD_SD2_CLK = 182, 208 MX53_PAD_PATA_DATA13 = 182,
209 MX53_PAD_SD2_CMD = 183, 209 MX53_PAD_PATA_DATA14 = 183,
210 MX53_PAD_SD2_DATA3 = 184, 210 MX53_PAD_PATA_DATA15 = 184,
211 MX53_PAD_SD2_DATA2 = 185, 211 MX53_PAD_SD1_DATA0 = 185,
212 MX53_PAD_SD2_DATA1 = 186, 212 MX53_PAD_SD1_DATA1 = 186,
213 MX53_PAD_SD2_DATA0 = 187, 213 MX53_PAD_SD1_CMD = 187,
214 MX53_PAD_GPIO_0 = 188, 214 MX53_PAD_SD1_DATA2 = 188,
215 MX53_PAD_GPIO_1 = 189, 215 MX53_PAD_SD1_CLK = 189,
216 MX53_PAD_GPIO_9 = 190, 216 MX53_PAD_SD1_DATA3 = 190,
217 MX53_PAD_GPIO_3 = 191, 217 MX53_PAD_SD2_CLK = 191,
218 MX53_PAD_GPIO_6 = 192, 218 MX53_PAD_SD2_CMD = 192,
219 MX53_PAD_GPIO_2 = 193, 219 MX53_PAD_SD2_DATA3 = 193,
220 MX53_PAD_GPIO_4 = 194, 220 MX53_PAD_SD2_DATA2 = 194,
221 MX53_PAD_GPIO_5 = 195, 221 MX53_PAD_SD2_DATA1 = 195,
222 MX53_PAD_GPIO_7 = 196, 222 MX53_PAD_SD2_DATA0 = 196,
223 MX53_PAD_GPIO_8 = 197, 223 MX53_PAD_GPIO_0 = 197,
224 MX53_PAD_GPIO_16 = 198, 224 MX53_PAD_GPIO_1 = 198,
225 MX53_PAD_GPIO_17 = 199, 225 MX53_PAD_GPIO_9 = 199,
226 MX53_PAD_GPIO_18 = 200, 226 MX53_PAD_GPIO_3 = 200,
227}; 227 MX53_PAD_GPIO_6 = 201,
228 228 MX53_PAD_GPIO_2 = 202,
229/* imx53 register maps */ 229 MX53_PAD_GPIO_4 = 203,
230static struct imx_pin_reg imx53_pin_regs[] = { 230 MX53_PAD_GPIO_5 = 204,
231 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 0, 0x840, 0), /* MX53_PAD_GPIO_19__KPP_COL_5 */ 231 MX53_PAD_GPIO_7 = 205,
232 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 1, 0x000, 0), /* MX53_PAD_GPIO_19__GPIO4_5 */ 232 MX53_PAD_GPIO_8 = 206,
233 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 2, 0x000, 0), /* MX53_PAD_GPIO_19__CCM_CLKO */ 233 MX53_PAD_GPIO_16 = 207,
234 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 3, 0x000, 0), /* MX53_PAD_GPIO_19__SPDIF_OUT1 */ 234 MX53_PAD_GPIO_17 = 208,
235 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 4, 0x000, 0), /* MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 */ 235 MX53_PAD_GPIO_18 = 209,
236 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 5, 0x000, 0), /* MX53_PAD_GPIO_19__ECSPI1_RDY */
237 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 6, 0x000, 0), /* MX53_PAD_GPIO_19__FEC_TDATA_3 */
238 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 7, 0x000, 0), /* MX53_PAD_GPIO_19__SRC_INT_BOOT */
239 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 0, 0x000, 0), /* MX53_PAD_KEY_COL0__KPP_COL_0 */
240 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 1, 0x000, 0), /* MX53_PAD_KEY_COL0__GPIO4_6 */
241 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 2, 0x758, 0), /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
242 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 4, 0x000, 0), /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
243 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 5, 0x79C, 0), /* MX53_PAD_KEY_COL0__ECSPI1_SCLK */
244 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 6, 0x000, 0), /* MX53_PAD_KEY_COL0__FEC_RDATA_3 */
245 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 7, 0x000, 0), /* MX53_PAD_KEY_COL0__SRC_ANY_PU_RST */
246 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 0, 0x000, 0), /* MX53_PAD_KEY_ROW0__KPP_ROW_0 */
247 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 1, 0x000, 0), /* MX53_PAD_KEY_ROW0__GPIO4_7 */
248 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 2, 0x74C, 0), /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
249 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 4, 0x890, 1), /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
250 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 5, 0x7A4, 0), /* MX53_PAD_KEY_ROW0__ECSPI1_MOSI */
251 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 6, 0x000, 0), /* MX53_PAD_KEY_ROW0__FEC_TX_ER */
252 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 0, 0x000, 0), /* MX53_PAD_KEY_COL1__KPP_COL_1 */
253 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 1, 0x000, 0), /* MX53_PAD_KEY_COL1__GPIO4_8 */
254 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 2, 0x75C, 0), /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
255 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 4, 0x000, 0), /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
256 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 5, 0x7A0, 0), /* MX53_PAD_KEY_COL1__ECSPI1_MISO */
257 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 6, 0x808, 0), /* MX53_PAD_KEY_COL1__FEC_RX_CLK */
258 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 7, 0x000, 0), /* MX53_PAD_KEY_COL1__USBPHY1_TXREADY */
259 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 0, 0x000, 0), /* MX53_PAD_KEY_ROW1__KPP_ROW_1 */
260 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 1, 0x000, 0), /* MX53_PAD_KEY_ROW1__GPIO4_9 */
261 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 2, 0x748, 0), /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
262 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 4, 0x898, 1), /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
263 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 5, 0x7A8, 0), /* MX53_PAD_KEY_ROW1__ECSPI1_SS0 */
264 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 6, 0x800, 0), /* MX53_PAD_KEY_ROW1__FEC_COL */
265 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 7, 0x000, 0), /* MX53_PAD_KEY_ROW1__USBPHY1_RXVALID */
266 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 0, 0x000, 0), /* MX53_PAD_KEY_COL2__KPP_COL_2 */
267 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 1, 0x000, 0), /* MX53_PAD_KEY_COL2__GPIO4_10 */
268 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 2, 0x000, 0), /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
269 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 4, 0x804, 0), /* MX53_PAD_KEY_COL2__FEC_MDIO */
270 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 5, 0x7AC, 0), /* MX53_PAD_KEY_COL2__ECSPI1_SS1 */
271 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 6, 0x000, 0), /* MX53_PAD_KEY_COL2__FEC_RDATA_2 */
272 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 7, 0x000, 0), /* MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE */
273 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 0, 0x000, 0), /* MX53_PAD_KEY_ROW2__KPP_ROW_2 */
274 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 1, 0x000, 0), /* MX53_PAD_KEY_ROW2__GPIO4_11 */
275 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 2, 0x760, 0), /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
276 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 4, 0x000, 0), /* MX53_PAD_KEY_ROW2__FEC_MDC */
277 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 5, 0x7B0, 0), /* MX53_PAD_KEY_ROW2__ECSPI1_SS2 */
278 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 6, 0x000, 0), /* MX53_PAD_KEY_ROW2__FEC_TDATA_2 */
279 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 7, 0x000, 0), /* MX53_PAD_KEY_ROW2__USBPHY1_RXERROR */
280 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 0, 0x000, 0), /* MX53_PAD_KEY_COL3__KPP_COL_3 */
281 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 1, 0x000, 0), /* MX53_PAD_KEY_COL3__GPIO4_12 */
282 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 2, 0x000, 0), /* MX53_PAD_KEY_COL3__USBOH3_H2_DP */
283 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 3, 0x870, 0), /* MX53_PAD_KEY_COL3__SPDIF_IN1 */
284 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 4, 0x81C, 0), /* MX53_PAD_KEY_COL3__I2C2_SCL */
285 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 5, 0x7B4, 0), /* MX53_PAD_KEY_COL3__ECSPI1_SS3 */
286 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 6, 0x000, 0), /* MX53_PAD_KEY_COL3__FEC_CRS */
287 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 7, 0x000, 0), /* MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK */
288 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 0, 0x000, 0), /* MX53_PAD_KEY_ROW3__KPP_ROW_3 */
289 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 1, 0x000, 0), /* MX53_PAD_KEY_ROW3__GPIO4_13 */
290 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 2, 0x000, 0), /* MX53_PAD_KEY_ROW3__USBOH3_H2_DM */
291 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 3, 0x768, 0), /* MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK */
292 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 4, 0x820, 0), /* MX53_PAD_KEY_ROW3__I2C2_SDA */
293 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 5, 0x000, 0), /* MX53_PAD_KEY_ROW3__OSC32K_32K_OUT */
294 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 6, 0x77C, 0), /* MX53_PAD_KEY_ROW3__CCM_PLL4_BYP */
295 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 7, 0x000, 0), /* MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 */
296 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 0, 0x000, 0), /* MX53_PAD_KEY_COL4__KPP_COL_4 */
297 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 1, 0x000, 0), /* MX53_PAD_KEY_COL4__GPIO4_14 */
298 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 2, 0x000, 0), /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
299 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 3, 0x000, 0), /* MX53_PAD_KEY_COL4__IPU_SISG_4 */
300 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 4, 0x894, 0), /* MX53_PAD_KEY_COL4__UART5_RTS */
301 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 5, 0x89C, 0), /* MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC */
302 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 7, 0x000, 0), /* MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 */
303 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 0, 0x000, 0), /* MX53_PAD_KEY_ROW4__KPP_ROW_4 */
304 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 1, 0x000, 0), /* MX53_PAD_KEY_ROW4__GPIO4_15 */
305 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 2, 0x764, 0), /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
306 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 3, 0x000, 0), /* MX53_PAD_KEY_ROW4__IPU_SISG_5 */
307 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 4, 0x000, 0), /* MX53_PAD_KEY_ROW4__UART5_CTS */
308 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 5, 0x000, 0), /* MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
309 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 7, 0x000, 0), /* MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID */
310 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 0, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK */
311 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 1, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__GPIO4_16 */
312 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 2, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR */
313 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 5, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 */
314 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 6, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 */
315 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 7, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID */
316 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 0, 0x000, 0), /* MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 */
317 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 1, 0x000, 0), /* MX53_PAD_DI0_PIN15__GPIO4_17 */
318 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 2, 0x000, 0), /* MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
319 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 5, 0x000, 0), /* MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 */
320 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 6, 0x000, 0), /* MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 */
321 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 7, 0x000, 0), /* MX53_PAD_DI0_PIN15__USBPHY1_BVALID */
322 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 0, 0x000, 0), /* MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 */
323 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 1, 0x000, 0), /* MX53_PAD_DI0_PIN2__GPIO4_18 */
324 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 2, 0x000, 0), /* MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
325 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 5, 0x000, 0), /* MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 */
326 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 6, 0x000, 0), /* MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 */
327 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 7, 0x000, 0), /* MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION */
328 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 0, 0x000, 0), /* MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 */
329 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 1, 0x000, 0), /* MX53_PAD_DI0_PIN3__GPIO4_19 */
330 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 2, 0x000, 0), /* MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
331 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 5, 0x000, 0), /* MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 */
332 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 6, 0x000, 0), /* MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 */
333 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 7, 0x000, 0), /* MX53_PAD_DI0_PIN3__USBPHY1_IDDIG */
334 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 0, 0x000, 0), /* MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 */
335 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 1, 0x000, 0), /* MX53_PAD_DI0_PIN4__GPIO4_20 */
336 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 2, 0x000, 0), /* MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
337 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 3, 0x7FC, 0), /* MX53_PAD_DI0_PIN4__ESDHC1_WP */
338 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 5, 0x000, 0), /* MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
339 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 6, 0x000, 0), /* MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 */
340 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 7, 0x000, 0), /* MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT */
341 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 */
342 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT0__GPIO4_21 */
343 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 2, 0x780, 0), /* MX53_PAD_DISP0_DAT0__CSPI_SCLK */
344 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 */
345 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN */
346 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 */
347 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY */
348 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 */
349 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT1__GPIO4_22 */
350 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 2, 0x788, 0), /* MX53_PAD_DISP0_DAT1__CSPI_MOSI */
351 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 */
352 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL */
353 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 */
354 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID */
355 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 */
356 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT2__GPIO4_23 */
357 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 2, 0x784, 0), /* MX53_PAD_DISP0_DAT2__CSPI_MISO */
358 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 */
359 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
360 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 */
361 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE */
362 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 */
363 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT3__GPIO4_24 */
364 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 2, 0x78C, 0), /* MX53_PAD_DISP0_DAT3__CSPI_SS0 */
365 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 */
366 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR */
367 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 */
368 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR */
369 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 */
370 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT4__GPIO4_25 */
371 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 2, 0x790, 0), /* MX53_PAD_DISP0_DAT4__CSPI_SS1 */
372 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 */
373 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
374 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 */
375 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK */
376 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 */
377 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT5__GPIO4_26 */
378 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 2, 0x794, 0), /* MX53_PAD_DISP0_DAT5__CSPI_SS2 */
379 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 */
380 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS */
381 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 */
382 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 */
383 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 */
384 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT6__GPIO4_27 */
385 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 2, 0x798, 0), /* MX53_PAD_DISP0_DAT6__CSPI_SS3 */
386 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 */
387 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE */
388 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 */
389 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 */
390 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 */
391 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT7__GPIO4_28 */
392 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT7__CSPI_RDY */
393 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 */
394 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 */
395 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 */
396 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID */
397 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 */
398 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT8__GPIO4_29 */
399 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT8__PWM1_PWMO */
400 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B */
401 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 */
402 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 */
403 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT8__USBPHY2_AVALID */
404 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 */
405 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT9__GPIO4_30 */
406 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT9__PWM2_PWMO */
407 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B */
408 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 */
409 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 */
410 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 */
411 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 */
412 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT10__GPIO4_31 */
413 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP */
414 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 */
415 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 */
416 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 */
417 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 */
418 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT11__GPIO5_5 */
419 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT */
420 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 */
421 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 */
422 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 */
423 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 */
424 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT12__GPIO5_6 */
425 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK */
426 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 */
427 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 */
428 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 */
429 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 */
430 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT13__GPIO5_7 */
431 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 3, 0x754, 0), /* MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
432 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 */
433 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 */
434 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 */
435 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 */
436 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT14__GPIO5_8 */
437 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 3, 0x750, 0), /* MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
438 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 */
439 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 */
440 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 */
441 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 */
442 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT15__GPIO5_9 */
443 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 2, 0x7AC, 1), /* MX53_PAD_DISP0_DAT15__ECSPI1_SS1 */
444 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 3, 0x7C8, 0), /* MX53_PAD_DISP0_DAT15__ECSPI2_SS1 */
445 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 */
446 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 */
447 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 */
448 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 */
449 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
450 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 2, 0x7C0, 0), /* MX53_PAD_DISP0_DAT16__ECSPI2_MOSI */
451 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 3, 0x758, 1), /* MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
452 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 4, 0x868, 0), /* MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
453 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 */
454 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 */
455 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 */
456 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 */
457 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
458 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 2, 0x7BC, 0), /* MX53_PAD_DISP0_DAT17__ECSPI2_MISO */
459 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 3, 0x74C, 1), /* MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
460 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 4, 0x86C, 0), /* MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
461 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 */
462 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 */
463 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 */
464 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
465 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 2, 0x7C4, 0), /* MX53_PAD_DISP0_DAT18__ECSPI2_SS0 */
466 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 3, 0x75C, 1), /* MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
467 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 4, 0x73C, 0), /* MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
468 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 */
469 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 */
470 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 */
471 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 */
472 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
473 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 2, 0x7B8, 0), /* MX53_PAD_DISP0_DAT19__ECSPI2_SCLK */
474 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 3, 0x748, 1), /* MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
475 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 4, 0x738, 0), /* MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
476 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 */
477 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 */
478 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 */
479 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 */
480 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT20__GPIO5_14 */
481 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 2, 0x79C, 1), /* MX53_PAD_DISP0_DAT20__ECSPI1_SCLK */
482 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 3, 0x740, 0), /* MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
483 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 */
484 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 */
485 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT20__SATA_PHY_TDI */
486 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 */
487 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT21__GPIO5_15 */
488 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 2, 0x7A4, 1), /* MX53_PAD_DISP0_DAT21__ECSPI1_MOSI */
489 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 3, 0x734, 0), /* MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
490 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 */
491 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 */
492 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT21__SATA_PHY_TDO */
493 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 */
494 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT22__GPIO5_16 */
495 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 2, 0x7A0, 1), /* MX53_PAD_DISP0_DAT22__ECSPI1_MISO */
496 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 3, 0x744, 0), /* MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
497 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 */
498 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 */
499 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT22__SATA_PHY_TCK */
500 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 */
501 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT23__GPIO5_17 */
502 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 2, 0x7A8, 1), /* MX53_PAD_DISP0_DAT23__ECSPI1_SS0 */
503 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 3, 0x730, 0), /* MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
504 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 */
505 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 */
506 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT23__SATA_PHY_TMS */
507 IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 0, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
508 IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 1, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__GPIO5_18 */
509 IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 5, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
510 IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 6, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 */
511 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 0, 0x000, 0), /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
512 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 1, 0x000, 0), /* MX53_PAD_CSI0_MCLK__GPIO5_19 */
513 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 2, 0x000, 0), /* MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK */
514 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 5, 0x000, 0), /* MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
515 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 6, 0x000, 0), /* MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 */
516 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 7, 0x000, 0), /* MX53_PAD_CSI0_MCLK__TPIU_TRCTL */
517 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 0, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
518 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 1, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__GPIO5_20 */
519 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 5, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
520 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 6, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 */
521 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 7, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK */
522 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 0, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
523 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 1, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__GPIO5_21 */
524 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 5, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
525 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 6, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 */
526 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 7, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 */
527 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
528 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT4__GPIO5_22 */
529 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 2, 0x840, 1), /* MX53_PAD_CSI0_DAT4__KPP_COL_5 */
530 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 3, 0x79C, 2), /* MX53_PAD_CSI0_DAT4__ECSPI1_SCLK */
531 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP */
532 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
533 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 */
534 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 */
535 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
536 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT5__GPIO5_23 */
537 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 2, 0x84C, 0), /* MX53_PAD_CSI0_DAT5__KPP_ROW_5 */
538 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 3, 0x7A4, 2), /* MX53_PAD_CSI0_DAT5__ECSPI1_MOSI */
539 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT */
540 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
541 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 */
542 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 */
543 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
544 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT6__GPIO5_24 */
545 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 2, 0x844, 0), /* MX53_PAD_CSI0_DAT6__KPP_COL_6 */
546 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 3, 0x7A0, 2), /* MX53_PAD_CSI0_DAT6__ECSPI1_MISO */
547 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK */
548 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
549 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 */
550 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 */
551 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
552 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT7__GPIO5_25 */
553 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 2, 0x850, 0), /* MX53_PAD_CSI0_DAT7__KPP_ROW_6 */
554 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 3, 0x7A8, 2), /* MX53_PAD_CSI0_DAT7__ECSPI1_SS0 */
555 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR */
556 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
557 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 */
558 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 */
559 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
560 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT8__GPIO5_26 */
561 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 2, 0x848, 0), /* MX53_PAD_CSI0_DAT8__KPP_COL_7 */
562 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 3, 0x7B8, 1), /* MX53_PAD_CSI0_DAT8__ECSPI2_SCLK */
563 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC */
564 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 5, 0x818, 0), /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
565 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 */
566 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 */
567 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
568 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT9__GPIO5_27 */
569 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 2, 0x854, 0), /* MX53_PAD_CSI0_DAT9__KPP_ROW_7 */
570 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 3, 0x7C0, 1), /* MX53_PAD_CSI0_DAT9__ECSPI2_MOSI */
571 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR */
572 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 5, 0x814, 0), /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
573 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 */
574 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 */
575 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
576 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT10__GPIO5_28 */
577 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
578 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 3, 0x7BC, 1), /* MX53_PAD_CSI0_DAT10__ECSPI2_MISO */
579 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
580 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
581 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 */
582 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 */
583 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
584 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT11__GPIO5_29 */
585 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 2, 0x878, 1), /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
586 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 3, 0x7C4, 1), /* MX53_PAD_CSI0_DAT11__ECSPI2_SS0 */
587 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
588 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
589 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 */
590 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 */
591 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
592 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT12__GPIO5_30 */
593 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT12__UART4_TXD_MUX */
594 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 */
595 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
596 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 */
597 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 */
598 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
599 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT13__GPIO5_31 */
600 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 2, 0x890, 3), /* MX53_PAD_CSI0_DAT13__UART4_RXD_MUX */
601 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 */
602 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
603 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 */
604 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 */
605 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
606 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT14__GPIO6_0 */
607 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT14__UART5_TXD_MUX */
608 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 */
609 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
610 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 */
611 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 */
612 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
613 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT15__GPIO6_1 */
614 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 2, 0x898, 3), /* MX53_PAD_CSI0_DAT15__UART5_RXD_MUX */
615 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 */
616 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
617 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 */
618 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 */
619 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
620 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT16__GPIO6_2 */
621 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 2, 0x88C, 0), /* MX53_PAD_CSI0_DAT16__UART4_RTS */
622 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 */
623 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
624 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 */
625 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 */
626 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
627 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT17__GPIO6_3 */
628 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT17__UART4_CTS */
629 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 */
630 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
631 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 */
632 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 */
633 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
634 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT18__GPIO6_4 */
635 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 2, 0x894, 2), /* MX53_PAD_CSI0_DAT18__UART5_RTS */
636 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 */
637 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
638 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 */
639 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 */
640 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
641 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT19__GPIO6_5 */
642 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT19__UART5_CTS */
643 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 */
644 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
645 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 */
646 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK */
647 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 0, 0x000, 0), /* MX53_PAD_EIM_A25__EMI_WEIM_A_25 */
648 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 1, 0x000, 0), /* MX53_PAD_EIM_A25__GPIO5_2 */
649 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 2, 0x000, 0), /* MX53_PAD_EIM_A25__ECSPI2_RDY */
650 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 3, 0x000, 0), /* MX53_PAD_EIM_A25__IPU_DI1_PIN12 */
651 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 4, 0x790, 1), /* MX53_PAD_EIM_A25__CSPI_SS1 */
652 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 6, 0x000, 0), /* MX53_PAD_EIM_A25__IPU_DI0_D1_CS */
653 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 7, 0x000, 0), /* MX53_PAD_EIM_A25__USBPHY1_BISTOK */
654 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 0, 0x000, 0), /* MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 */
655 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 1, 0x000, 0), /* MX53_PAD_EIM_EB2__GPIO2_30 */
656 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 2, 0x76C, 0), /* MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
657 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 3, 0x000, 0), /* MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS */
658 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 4, 0x7A8, 3), /* MX53_PAD_EIM_EB2__ECSPI1_SS0 */
659 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 5, 0x81C, 1), /* MX53_PAD_EIM_EB2__I2C2_SCL */
660 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 0, 0x000, 0), /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
661 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 1, 0x000, 0), /* MX53_PAD_EIM_D16__GPIO3_16 */
662 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 2, 0x000, 0), /* MX53_PAD_EIM_D16__IPU_DI0_PIN5 */
663 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 3, 0x000, 0), /* MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK */
664 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 4, 0x79C, 3), /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
665 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 5, 0x820, 1), /* MX53_PAD_EIM_D16__I2C2_SDA */
666 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 0, 0x000, 0), /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
667 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 1, 0x000, 0), /* MX53_PAD_EIM_D17__GPIO3_17 */
668 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 2, 0x000, 0), /* MX53_PAD_EIM_D17__IPU_DI0_PIN6 */
669 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 3, 0x830, 0), /* MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN */
670 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 4, 0x7A0, 3), /* MX53_PAD_EIM_D17__ECSPI1_MISO */
671 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 5, 0x824, 0), /* MX53_PAD_EIM_D17__I2C3_SCL */
672 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 0, 0x000, 0), /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
673 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 1, 0x000, 0), /* MX53_PAD_EIM_D18__GPIO3_18 */
674 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 2, 0x000, 0), /* MX53_PAD_EIM_D18__IPU_DI0_PIN7 */
675 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 3, 0x830, 1), /* MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO */
676 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 4, 0x7A4, 3), /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
677 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 5, 0x828, 0), /* MX53_PAD_EIM_D18__I2C3_SDA */
678 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 6, 0x000, 0), /* MX53_PAD_EIM_D18__IPU_DI1_D0_CS */
679 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 0, 0x000, 0), /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
680 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 1, 0x000, 0), /* MX53_PAD_EIM_D19__GPIO3_19 */
681 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 2, 0x000, 0), /* MX53_PAD_EIM_D19__IPU_DI0_PIN8 */
682 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 3, 0x000, 0), /* MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS */
683 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 4, 0x7AC, 2), /* MX53_PAD_EIM_D19__ECSPI1_SS1 */
684 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 5, 0x000, 0), /* MX53_PAD_EIM_D19__EPIT1_EPITO */
685 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 6, 0x000, 0), /* MX53_PAD_EIM_D19__UART1_CTS */
686 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 7, 0x8A4, 0), /* MX53_PAD_EIM_D19__USBOH3_USBH2_OC */
687 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 0, 0x000, 0), /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
688 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 1, 0x000, 0), /* MX53_PAD_EIM_D20__GPIO3_20 */
689 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 2, 0x000, 0), /* MX53_PAD_EIM_D20__IPU_DI0_PIN16 */
690 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 3, 0x000, 0), /* MX53_PAD_EIM_D20__IPU_SER_DISP0_CS */
691 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 4, 0x78C, 1), /* MX53_PAD_EIM_D20__CSPI_SS0 */
692 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 5, 0x000, 0), /* MX53_PAD_EIM_D20__EPIT2_EPITO */
693 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 6, 0x874, 1), /* MX53_PAD_EIM_D20__UART1_RTS */
694 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 7, 0x000, 0), /* MX53_PAD_EIM_D20__USBOH3_USBH2_PWR */
695 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 0, 0x000, 0), /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
696 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 1, 0x000, 0), /* MX53_PAD_EIM_D21__GPIO3_21 */
697 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 2, 0x000, 0), /* MX53_PAD_EIM_D21__IPU_DI0_PIN17 */
698 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 3, 0x000, 0), /* MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK */
699 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 4, 0x780, 1), /* MX53_PAD_EIM_D21__CSPI_SCLK */
700 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 5, 0x814, 1), /* MX53_PAD_EIM_D21__I2C1_SCL */
701 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 6, 0x89C, 1), /* MX53_PAD_EIM_D21__USBOH3_USBOTG_OC */
702 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 0, 0x000, 0), /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
703 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 1, 0x000, 0), /* MX53_PAD_EIM_D22__GPIO3_22 */
704 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 2, 0x000, 0), /* MX53_PAD_EIM_D22__IPU_DI0_PIN1 */
705 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 3, 0x82C, 0), /* MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN */
706 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 4, 0x784, 1), /* MX53_PAD_EIM_D22__CSPI_MISO */
707 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 6, 0x000, 0), /* MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR */
708 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 0, 0x000, 0), /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
709 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 1, 0x000, 0), /* MX53_PAD_EIM_D23__GPIO3_23 */
710 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 2, 0x000, 0), /* MX53_PAD_EIM_D23__UART3_CTS */
711 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 3, 0x000, 0), /* MX53_PAD_EIM_D23__UART1_DCD */
712 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 4, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI0_D0_CS */
713 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 5, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI1_PIN2 */
714 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 6, 0x834, 0), /* MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN */
715 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 7, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI1_PIN14 */
716 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 0, 0x000, 0), /* MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 */
717 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 1, 0x000, 0), /* MX53_PAD_EIM_EB3__GPIO2_31 */
718 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 2, 0x884, 1), /* MX53_PAD_EIM_EB3__UART3_RTS */
719 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 3, 0x000, 0), /* MX53_PAD_EIM_EB3__UART1_RI */
720 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 5, 0x000, 0), /* MX53_PAD_EIM_EB3__IPU_DI1_PIN3 */
721 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 6, 0x838, 0), /* MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC */
722 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 7, 0x000, 0), /* MX53_PAD_EIM_EB3__IPU_DI1_PIN16 */
723 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 0, 0x000, 0), /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
724 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 1, 0x000, 0), /* MX53_PAD_EIM_D24__GPIO3_24 */
725 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 2, 0x000, 0), /* MX53_PAD_EIM_D24__UART3_TXD_MUX */
726 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 3, 0x7B0, 1), /* MX53_PAD_EIM_D24__ECSPI1_SS2 */
727 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 4, 0x794, 1), /* MX53_PAD_EIM_D24__CSPI_SS2 */
728 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 5, 0x754, 1), /* MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
729 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 6, 0x000, 0), /* MX53_PAD_EIM_D24__ECSPI2_SS2 */
730 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 7, 0x000, 0), /* MX53_PAD_EIM_D24__UART1_DTR */
731 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 0, 0x000, 0), /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
732 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 1, 0x000, 0), /* MX53_PAD_EIM_D25__GPIO3_25 */
733 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 2, 0x888, 1), /* MX53_PAD_EIM_D25__UART3_RXD_MUX */
734 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 3, 0x7B4, 1), /* MX53_PAD_EIM_D25__ECSPI1_SS3 */
735 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 4, 0x798, 1), /* MX53_PAD_EIM_D25__CSPI_SS3 */
736 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 5, 0x750, 1), /* MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC */
737 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 6, 0x000, 0), /* MX53_PAD_EIM_D25__ECSPI2_SS3 */
738 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 7, 0x000, 0), /* MX53_PAD_EIM_D25__UART1_DSR */
739 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 0, 0x000, 0), /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
740 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 1, 0x000, 0), /* MX53_PAD_EIM_D26__GPIO3_26 */
741 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 2, 0x000, 0), /* MX53_PAD_EIM_D26__UART2_TXD_MUX */
742 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 3, 0x80C, 0), /* MX53_PAD_EIM_D26__FIRI_RXD */
743 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 4, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_CSI0_D_1 */
744 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 5, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_DI1_PIN11 */
745 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 6, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_SISG_2 */
746 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 7, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 */
747 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 0, 0x000, 0), /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
748 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 1, 0x000, 0), /* MX53_PAD_EIM_D27__GPIO3_27 */
749 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 2, 0x880, 1), /* MX53_PAD_EIM_D27__UART2_RXD_MUX */
750 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 3, 0x000, 0), /* MX53_PAD_EIM_D27__FIRI_TXD */
751 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 4, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_CSI0_D_0 */
752 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 5, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_DI1_PIN13 */
753 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 6, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_SISG_3 */
754 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 7, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 */
755 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 0, 0x000, 0), /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
756 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 1, 0x000, 0), /* MX53_PAD_EIM_D28__GPIO3_28 */
757 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 2, 0x000, 0), /* MX53_PAD_EIM_D28__UART2_CTS */
758 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 3, 0x82C, 1), /* MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO */
759 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 4, 0x788, 1), /* MX53_PAD_EIM_D28__CSPI_MOSI */
760 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 5, 0x818, 1), /* MX53_PAD_EIM_D28__I2C1_SDA */
761 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 6, 0x000, 0), /* MX53_PAD_EIM_D28__IPU_EXT_TRIG */
762 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 7, 0x000, 0), /* MX53_PAD_EIM_D28__IPU_DI0_PIN13 */
763 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 0, 0x000, 0), /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
764 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 1, 0x000, 0), /* MX53_PAD_EIM_D29__GPIO3_29 */
765 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 2, 0x87C, 1), /* MX53_PAD_EIM_D29__UART2_RTS */
766 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 3, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS */
767 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 4, 0x78C, 2), /* MX53_PAD_EIM_D29__CSPI_SS0 */
768 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 5, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DI1_PIN15 */
769 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 6, 0x83C, 0), /* MX53_PAD_EIM_D29__IPU_CSI1_VSYNC */
770 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 7, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DI0_PIN14 */
771 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 0, 0x000, 0), /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
772 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 1, 0x000, 0), /* MX53_PAD_EIM_D30__GPIO3_30 */
773 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 2, 0x000, 0), /* MX53_PAD_EIM_D30__UART3_CTS */
774 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 3, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_CSI0_D_3 */
775 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 4, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_DI0_PIN11 */
776 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 5, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 */
777 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 6, 0x8A0, 0), /* MX53_PAD_EIM_D30__USBOH3_USBH1_OC */
778 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 7, 0x8A4, 1), /* MX53_PAD_EIM_D30__USBOH3_USBH2_OC */
779 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 0, 0x000, 0), /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
780 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 1, 0x000, 0), /* MX53_PAD_EIM_D31__GPIO3_31 */
781 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 2, 0x884, 3), /* MX53_PAD_EIM_D31__UART3_RTS */
782 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 3, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_CSI0_D_2 */
783 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 4, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_DI0_PIN12 */
784 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 5, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 */
785 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 6, 0x000, 0), /* MX53_PAD_EIM_D31__USBOH3_USBH1_PWR */
786 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 7, 0x000, 0), /* MX53_PAD_EIM_D31__USBOH3_USBH2_PWR */
787 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 0, 0x000, 0), /* MX53_PAD_EIM_A24__EMI_WEIM_A_24 */
788 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 1, 0x000, 0), /* MX53_PAD_EIM_A24__GPIO5_4 */
789 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 2, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 */
790 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 3, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_CSI1_D_19 */
791 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 6, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_SISG_2 */
792 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 7, 0x000, 0), /* MX53_PAD_EIM_A24__USBPHY2_BVALID */
793 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 0, 0x000, 0), /* MX53_PAD_EIM_A23__EMI_WEIM_A_23 */
794 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 1, 0x000, 0), /* MX53_PAD_EIM_A23__GPIO6_6 */
795 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 2, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 */
796 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 3, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_CSI1_D_18 */
797 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 6, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_SISG_3 */
798 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 7, 0x000, 0), /* MX53_PAD_EIM_A23__USBPHY2_ENDSESSION */
799 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 0, 0x000, 0), /* MX53_PAD_EIM_A22__EMI_WEIM_A_22 */
800 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 1, 0x000, 0), /* MX53_PAD_EIM_A22__GPIO2_16 */
801 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 2, 0x000, 0), /* MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 */
802 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 3, 0x000, 0), /* MX53_PAD_EIM_A22__IPU_CSI1_D_17 */
803 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 7, 0x000, 0), /* MX53_PAD_EIM_A22__SRC_BT_CFG1_7 */
804 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 0, 0x000, 0), /* MX53_PAD_EIM_A21__EMI_WEIM_A_21 */
805 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 1, 0x000, 0), /* MX53_PAD_EIM_A21__GPIO2_17 */
806 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 2, 0x000, 0), /* MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 */
807 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 3, 0x000, 0), /* MX53_PAD_EIM_A21__IPU_CSI1_D_16 */
808 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 7, 0x000, 0), /* MX53_PAD_EIM_A21__SRC_BT_CFG1_6 */
809 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 0, 0x000, 0), /* MX53_PAD_EIM_A20__EMI_WEIM_A_20 */
810 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 1, 0x000, 0), /* MX53_PAD_EIM_A20__GPIO2_18 */
811 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 2, 0x000, 0), /* MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 */
812 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 3, 0x000, 0), /* MX53_PAD_EIM_A20__IPU_CSI1_D_15 */
813 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 7, 0x000, 0), /* MX53_PAD_EIM_A20__SRC_BT_CFG1_5 */
814 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 0, 0x000, 0), /* MX53_PAD_EIM_A19__EMI_WEIM_A_19 */
815 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 1, 0x000, 0), /* MX53_PAD_EIM_A19__GPIO2_19 */
816 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 2, 0x000, 0), /* MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 */
817 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 3, 0x000, 0), /* MX53_PAD_EIM_A19__IPU_CSI1_D_14 */
818 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 7, 0x000, 0), /* MX53_PAD_EIM_A19__SRC_BT_CFG1_4 */
819 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 0, 0x000, 0), /* MX53_PAD_EIM_A18__EMI_WEIM_A_18 */
820 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 1, 0x000, 0), /* MX53_PAD_EIM_A18__GPIO2_20 */
821 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 2, 0x000, 0), /* MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 */
822 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 3, 0x000, 0), /* MX53_PAD_EIM_A18__IPU_CSI1_D_13 */
823 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 7, 0x000, 0), /* MX53_PAD_EIM_A18__SRC_BT_CFG1_3 */
824 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 0, 0x000, 0), /* MX53_PAD_EIM_A17__EMI_WEIM_A_17 */
825 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 1, 0x000, 0), /* MX53_PAD_EIM_A17__GPIO2_21 */
826 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 2, 0x000, 0), /* MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 */
827 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 3, 0x000, 0), /* MX53_PAD_EIM_A17__IPU_CSI1_D_12 */
828 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 7, 0x000, 0), /* MX53_PAD_EIM_A17__SRC_BT_CFG1_2 */
829 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 0, 0x000, 0), /* MX53_PAD_EIM_A16__EMI_WEIM_A_16 */
830 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 1, 0x000, 0), /* MX53_PAD_EIM_A16__GPIO2_22 */
831 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 2, 0x000, 0), /* MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK */
832 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 3, 0x000, 0), /* MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK */
833 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 7, 0x000, 0), /* MX53_PAD_EIM_A16__SRC_BT_CFG1_1 */
834 IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 0, 0x000, 0), /* MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 */
835 IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 1, 0x000, 0), /* MX53_PAD_EIM_CS0__GPIO2_23 */
836 IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 2, 0x7B8, 2), /* MX53_PAD_EIM_CS0__ECSPI2_SCLK */
837 IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 3, 0x000, 0), /* MX53_PAD_EIM_CS0__IPU_DI1_PIN5 */
838 IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 0, 0x000, 0), /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
839 IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 1, 0x000, 0), /* MX53_PAD_EIM_CS1__GPIO2_24 */
840 IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 2, 0x7C0, 2), /* MX53_PAD_EIM_CS1__ECSPI2_MOSI */
841 IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 3, 0x000, 0), /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 */
842 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 0, 0x000, 0), /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
843 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 1, 0x000, 0), /* MX53_PAD_EIM_OE__GPIO2_25 */
844 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 2, 0x7BC, 2), /* MX53_PAD_EIM_OE__ECSPI2_MISO */
845 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 3, 0x000, 0), /* MX53_PAD_EIM_OE__IPU_DI1_PIN7 */
846 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 7, 0x000, 0), /* MX53_PAD_EIM_OE__USBPHY2_IDDIG */
847 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 0, 0x000, 0), /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
848 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 1, 0x000, 0), /* MX53_PAD_EIM_RW__GPIO2_26 */
849 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 2, 0x7C4, 2), /* MX53_PAD_EIM_RW__ECSPI2_SS0 */
850 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 3, 0x000, 0), /* MX53_PAD_EIM_RW__IPU_DI1_PIN8 */
851 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 7, 0x000, 0), /* MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT */
852 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 0, 0x000, 0), /* MX53_PAD_EIM_LBA__EMI_WEIM_LBA */
853 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 1, 0x000, 0), /* MX53_PAD_EIM_LBA__GPIO2_27 */
854 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 2, 0x7C8, 1), /* MX53_PAD_EIM_LBA__ECSPI2_SS1 */
855 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 3, 0x000, 0), /* MX53_PAD_EIM_LBA__IPU_DI1_PIN17 */
856 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 7, 0x000, 0), /* MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 */
857 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 0, 0x000, 0), /* MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 */
858 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 1, 0x000, 0), /* MX53_PAD_EIM_EB0__GPIO2_28 */
859 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 3, 0x000, 0), /* MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 */
860 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 4, 0x000, 0), /* MX53_PAD_EIM_EB0__IPU_CSI1_D_11 */
861 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 5, 0x810, 0), /* MX53_PAD_EIM_EB0__GPC_PMIC_RDY */
862 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 7, 0x000, 0), /* MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 */
863 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 0, 0x000, 0), /* MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 */
864 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 1, 0x000, 0), /* MX53_PAD_EIM_EB1__GPIO2_29 */
865 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 3, 0x000, 0), /* MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 */
866 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 4, 0x000, 0), /* MX53_PAD_EIM_EB1__IPU_CSI1_D_10 */
867 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 7, 0x000, 0), /* MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 */
868 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 0, 0x000, 0), /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
869 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 1, 0x000, 0), /* MX53_PAD_EIM_DA0__GPIO3_0 */
870 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 3, 0x000, 0), /* MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 */
871 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 4, 0x000, 0), /* MX53_PAD_EIM_DA0__IPU_CSI1_D_9 */
872 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 7, 0x000, 0), /* MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 */
873 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 0, 0x000, 0), /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
874 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 1, 0x000, 0), /* MX53_PAD_EIM_DA1__GPIO3_1 */
875 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 3, 0x000, 0), /* MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 */
876 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 4, 0x000, 0), /* MX53_PAD_EIM_DA1__IPU_CSI1_D_8 */
877 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 7, 0x000, 0), /* MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 */
878 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 0, 0x000, 0), /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
879 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 1, 0x000, 0), /* MX53_PAD_EIM_DA2__GPIO3_2 */
880 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 3, 0x000, 0), /* MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 */
881 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 4, 0x000, 0), /* MX53_PAD_EIM_DA2__IPU_CSI1_D_7 */
882 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 7, 0x000, 0), /* MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 */
883 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 0, 0x000, 0), /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
884 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 1, 0x000, 0), /* MX53_PAD_EIM_DA3__GPIO3_3 */
885 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 3, 0x000, 0), /* MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 */
886 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 4, 0x000, 0), /* MX53_PAD_EIM_DA3__IPU_CSI1_D_6 */
887 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 7, 0x000, 0), /* MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 */
888 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 0, 0x000, 0), /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
889 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 1, 0x000, 0), /* MX53_PAD_EIM_DA4__GPIO3_4 */
890 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 3, 0x000, 0), /* MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 */
891 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 4, 0x000, 0), /* MX53_PAD_EIM_DA4__IPU_CSI1_D_5 */
892 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 7, 0x000, 0), /* MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 */
893 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 0, 0x000, 0), /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
894 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 1, 0x000, 0), /* MX53_PAD_EIM_DA5__GPIO3_5 */
895 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 3, 0x000, 0), /* MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 */
896 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 4, 0x000, 0), /* MX53_PAD_EIM_DA5__IPU_CSI1_D_4 */
897 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 7, 0x000, 0), /* MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 */
898 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 0, 0x000, 0), /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
899 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 1, 0x000, 0), /* MX53_PAD_EIM_DA6__GPIO3_6 */
900 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 3, 0x000, 0), /* MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 */
901 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 4, 0x000, 0), /* MX53_PAD_EIM_DA6__IPU_CSI1_D_3 */
902 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 7, 0x000, 0), /* MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 */
903 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 0, 0x000, 0), /* MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 */
904 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 1, 0x000, 0), /* MX53_PAD_EIM_DA7__GPIO3_7 */
905 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 3, 0x000, 0), /* MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 */
906 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 4, 0x000, 0), /* MX53_PAD_EIM_DA7__IPU_CSI1_D_2 */
907 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 7, 0x000, 0), /* MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 */
908 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 0, 0x000, 0), /* MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 */
909 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 1, 0x000, 0), /* MX53_PAD_EIM_DA8__GPIO3_8 */
910 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 3, 0x000, 0), /* MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 */
911 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 4, 0x000, 0), /* MX53_PAD_EIM_DA8__IPU_CSI1_D_1 */
912 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 7, 0x000, 0), /* MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 */
913 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 0, 0x000, 0), /* MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 */
914 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 1, 0x000, 0), /* MX53_PAD_EIM_DA9__GPIO3_9 */
915 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 3, 0x000, 0), /* MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 */
916 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 4, 0x000, 0), /* MX53_PAD_EIM_DA9__IPU_CSI1_D_0 */
917 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 7, 0x000, 0), /* MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 */
918 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 0, 0x000, 0), /* MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 */
919 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 1, 0x000, 0), /* MX53_PAD_EIM_DA10__GPIO3_10 */
920 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 3, 0x000, 0), /* MX53_PAD_EIM_DA10__IPU_DI1_PIN15 */
921 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 4, 0x834, 1), /* MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN */
922 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 7, 0x000, 0), /* MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 */
923 IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 0, 0x000, 0), /* MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 */
924 IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 1, 0x000, 0), /* MX53_PAD_EIM_DA11__GPIO3_11 */
925 IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 3, 0x000, 0), /* MX53_PAD_EIM_DA11__IPU_DI1_PIN2 */
926 IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 4, 0x838, 1), /* MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC */
927 IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 0, 0x000, 0), /* MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 */
928 IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 1, 0x000, 0), /* MX53_PAD_EIM_DA12__GPIO3_12 */
929 IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 3, 0x000, 0), /* MX53_PAD_EIM_DA12__IPU_DI1_PIN3 */
930 IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 4, 0x83C, 1), /* MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC */
931 IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 0, 0x000, 0), /* MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 */
932 IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 1, 0x000, 0), /* MX53_PAD_EIM_DA13__GPIO3_13 */
933 IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 3, 0x000, 0), /* MX53_PAD_EIM_DA13__IPU_DI1_D0_CS */
934 IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 4, 0x76C, 1), /* MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
935 IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 0, 0x000, 0), /* MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 */
936 IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 1, 0x000, 0), /* MX53_PAD_EIM_DA14__GPIO3_14 */
937 IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 3, 0x000, 0), /* MX53_PAD_EIM_DA14__IPU_DI1_D1_CS */
938 IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 4, 0x000, 0), /* MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
939 IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 0, 0x000, 0), /* MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 */
940 IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 1, 0x000, 0), /* MX53_PAD_EIM_DA15__GPIO3_15 */
941 IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 3, 0x000, 0), /* MX53_PAD_EIM_DA15__IPU_DI1_PIN1 */
942 IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 4, 0x000, 0), /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 */
943 IMX_PIN_REG(MX53_PAD_NANDF_WE_B, 0x52C, 0x1DC, 0, 0x000, 0), /* MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B */
944 IMX_PIN_REG(MX53_PAD_NANDF_WE_B, 0x52C, 0x1DC, 1, 0x000, 0), /* MX53_PAD_NANDF_WE_B__GPIO6_12 */
945 IMX_PIN_REG(MX53_PAD_NANDF_RE_B, 0x530, 0x1E0, 0, 0x000, 0), /* MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B */
946 IMX_PIN_REG(MX53_PAD_NANDF_RE_B, 0x530, 0x1E0, 1, 0x000, 0), /* MX53_PAD_NANDF_RE_B__GPIO6_13 */
947 IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 0, 0x000, 0), /* MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT */
948 IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 1, 0x000, 0), /* MX53_PAD_EIM_WAIT__GPIO5_0 */
949 IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 2, 0x000, 0), /* MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B */
950 IMX_PIN_REG(MX53_PAD_LVDS1_TX3_P, NO_PAD, 0x1EC, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX3_P__GPIO6_22 */
951 IMX_PIN_REG(MX53_PAD_LVDS1_TX3_P, NO_PAD, 0x1EC, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
952 IMX_PIN_REG(MX53_PAD_LVDS1_TX2_P, NO_PAD, 0x1F0, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX2_P__GPIO6_24 */
953 IMX_PIN_REG(MX53_PAD_LVDS1_TX2_P, NO_PAD, 0x1F0, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
954 IMX_PIN_REG(MX53_PAD_LVDS1_CLK_P, NO_PAD, 0x1F4, 0, 0x000, 0), /* MX53_PAD_LVDS1_CLK_P__GPIO6_26 */
955 IMX_PIN_REG(MX53_PAD_LVDS1_CLK_P, NO_PAD, 0x1F4, 1, 0x000, 0), /* MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
956 IMX_PIN_REG(MX53_PAD_LVDS1_TX1_P, NO_PAD, 0x1F8, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX1_P__GPIO6_28 */
957 IMX_PIN_REG(MX53_PAD_LVDS1_TX1_P, NO_PAD, 0x1F8, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
958 IMX_PIN_REG(MX53_PAD_LVDS1_TX0_P, NO_PAD, 0x1FC, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX0_P__GPIO6_30 */
959 IMX_PIN_REG(MX53_PAD_LVDS1_TX0_P, NO_PAD, 0x1FC, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
960 IMX_PIN_REG(MX53_PAD_LVDS0_TX3_P, NO_PAD, 0x200, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX3_P__GPIO7_22 */
961 IMX_PIN_REG(MX53_PAD_LVDS0_TX3_P, NO_PAD, 0x200, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
962 IMX_PIN_REG(MX53_PAD_LVDS0_CLK_P, NO_PAD, 0x204, 0, 0x000, 0), /* MX53_PAD_LVDS0_CLK_P__GPIO7_24 */
963 IMX_PIN_REG(MX53_PAD_LVDS0_CLK_P, NO_PAD, 0x204, 1, 0x000, 0), /* MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
964 IMX_PIN_REG(MX53_PAD_LVDS0_TX2_P, NO_PAD, 0x208, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX2_P__GPIO7_26 */
965 IMX_PIN_REG(MX53_PAD_LVDS0_TX2_P, NO_PAD, 0x208, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
966 IMX_PIN_REG(MX53_PAD_LVDS0_TX1_P, NO_PAD, 0x20C, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX1_P__GPIO7_28 */
967 IMX_PIN_REG(MX53_PAD_LVDS0_TX1_P, NO_PAD, 0x20C, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
968 IMX_PIN_REG(MX53_PAD_LVDS0_TX0_P, NO_PAD, 0x210, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX0_P__GPIO7_30 */
969 IMX_PIN_REG(MX53_PAD_LVDS0_TX0_P, NO_PAD, 0x210, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
970 IMX_PIN_REG(MX53_PAD_GPIO_10, 0x540, 0x214, 0, 0x000, 0), /* MX53_PAD_GPIO_10__GPIO4_0 */
971 IMX_PIN_REG(MX53_PAD_GPIO_10, 0x540, 0x214, 1, 0x000, 0), /* MX53_PAD_GPIO_10__OSC32k_32K_OUT */
972 IMX_PIN_REG(MX53_PAD_GPIO_11, 0x544, 0x218, 0, 0x000, 0), /* MX53_PAD_GPIO_11__GPIO4_1 */
973 IMX_PIN_REG(MX53_PAD_GPIO_12, 0x548, 0x21C, 0, 0x000, 0), /* MX53_PAD_GPIO_12__GPIO4_2 */
974 IMX_PIN_REG(MX53_PAD_GPIO_13, 0x54C, 0x220, 0, 0x000, 0), /* MX53_PAD_GPIO_13__GPIO4_3 */
975 IMX_PIN_REG(MX53_PAD_GPIO_14, 0x550, 0x224, 0, 0x000, 0), /* MX53_PAD_GPIO_14__GPIO4_4 */
976 IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 0, 0x000, 0), /* MX53_PAD_NANDF_CLE__EMI_NANDF_CLE */
977 IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 1, 0x000, 0), /* MX53_PAD_NANDF_CLE__GPIO6_7 */
978 IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 7, 0x000, 0), /* MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 */
979 IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 0, 0x000, 0), /* MX53_PAD_NANDF_ALE__EMI_NANDF_ALE */
980 IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 1, 0x000, 0), /* MX53_PAD_NANDF_ALE__GPIO6_8 */
981 IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 7, 0x000, 0), /* MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 */
982 IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 0, 0x000, 0), /* MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B */
983 IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 1, 0x000, 0), /* MX53_PAD_NANDF_WP_B__GPIO6_9 */
984 IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 7, 0x000, 0), /* MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 */
985 IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 0, 0x000, 0), /* MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 */
986 IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 1, 0x000, 0), /* MX53_PAD_NANDF_RB0__GPIO6_10 */
987 IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 7, 0x000, 0), /* MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 */
988 IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 0, 0x000, 0), /* MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 */
989 IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 1, 0x000, 0), /* MX53_PAD_NANDF_CS0__GPIO6_11 */
990 IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 7, 0x000, 0), /* MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 */
991 IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 0, 0x000, 0), /* MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 */
992 IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 1, 0x000, 0), /* MX53_PAD_NANDF_CS1__GPIO6_14 */
993 IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 6, 0x858, 0), /* MX53_PAD_NANDF_CS1__MLB_MLBCLK */
994 IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 7, 0x000, 0), /* MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 */
995 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 0, 0x000, 0), /* MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 */
996 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 1, 0x000, 0), /* MX53_PAD_NANDF_CS2__GPIO6_15 */
997 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 2, 0x000, 0), /* MX53_PAD_NANDF_CS2__IPU_SISG_0 */
998 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 3, 0x7E4, 0), /* MX53_PAD_NANDF_CS2__ESAI1_TX0 */
999 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 4, 0x000, 0), /* MX53_PAD_NANDF_CS2__EMI_WEIM_CRE */
1000 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 5, 0x000, 0), /* MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK */
1001 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 6, 0x860, 0), /* MX53_PAD_NANDF_CS2__MLB_MLBSIG */
1002 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 7, 0x000, 0), /* MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 */
1003 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 0, 0x000, 0), /* MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 */
1004 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 1, 0x000, 0), /* MX53_PAD_NANDF_CS3__GPIO6_16 */
1005 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 2, 0x000, 0), /* MX53_PAD_NANDF_CS3__IPU_SISG_1 */
1006 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 3, 0x7E8, 0), /* MX53_PAD_NANDF_CS3__ESAI1_TX1 */
1007 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 4, 0x000, 0), /* MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 */
1008 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 6, 0x85C, 0), /* MX53_PAD_NANDF_CS3__MLB_MLBDAT */
1009 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 7, 0x000, 0), /* MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 */
1010 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 0, 0x804, 1), /* MX53_PAD_FEC_MDIO__FEC_MDIO */
1011 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 1, 0x000, 0), /* MX53_PAD_FEC_MDIO__GPIO1_22 */
1012 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 2, 0x7DC, 0), /* MX53_PAD_FEC_MDIO__ESAI1_SCKR */
1013 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 3, 0x800, 1), /* MX53_PAD_FEC_MDIO__FEC_COL */
1014 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 4, 0x000, 0), /* MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 */
1015 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 5, 0x000, 0), /* MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 */
1016 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 6, 0x000, 0), /* MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 */
1017 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 0, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
1018 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 1, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__GPIO1_23 */
1019 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 2, 0x7CC, 0), /* MX53_PAD_FEC_REF_CLK__ESAI1_FSR */
1020 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 5, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 */
1021 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 6, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 */
1022 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 0, 0x000, 0), /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
1023 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 1, 0x000, 0), /* MX53_PAD_FEC_RX_ER__GPIO1_24 */
1024 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 2, 0x7D4, 0), /* MX53_PAD_FEC_RX_ER__ESAI1_HCKR */
1025 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 3, 0x808, 1), /* MX53_PAD_FEC_RX_ER__FEC_RX_CLK */
1026 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 4, 0x000, 0), /* MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 */
1027 IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 0, 0x000, 0), /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
1028 IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 1, 0x000, 0), /* MX53_PAD_FEC_CRS_DV__GPIO1_25 */
1029 IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 2, 0x7E0, 0), /* MX53_PAD_FEC_CRS_DV__ESAI1_SCKT */
1030 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 0, 0x000, 0), /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
1031 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 1, 0x000, 0), /* MX53_PAD_FEC_RXD1__GPIO1_26 */
1032 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 2, 0x7D0, 0), /* MX53_PAD_FEC_RXD1__ESAI1_FST */
1033 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 3, 0x860, 1), /* MX53_PAD_FEC_RXD1__MLB_MLBSIG */
1034 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 4, 0x000, 0), /* MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 */
1035 IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 0, 0x000, 0), /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
1036 IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 1, 0x000, 0), /* MX53_PAD_FEC_RXD0__GPIO1_27 */
1037 IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 2, 0x7D8, 0), /* MX53_PAD_FEC_RXD0__ESAI1_HCKT */
1038 IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 3, 0x000, 0), /* MX53_PAD_FEC_RXD0__OSC32k_32K_OUT */
1039 IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 0, 0x000, 0), /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
1040 IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 1, 0x000, 0), /* MX53_PAD_FEC_TX_EN__GPIO1_28 */
1041 IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 2, 0x7F0, 0), /* MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 */
1042 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 0, 0x000, 0), /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
1043 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 1, 0x000, 0), /* MX53_PAD_FEC_TXD1__GPIO1_29 */
1044 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 2, 0x7EC, 0), /* MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 */
1045 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 3, 0x858, 1), /* MX53_PAD_FEC_TXD1__MLB_MLBCLK */
1046 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 4, 0x000, 0), /* MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK */
1047 IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 0, 0x000, 0), /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
1048 IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 1, 0x000, 0), /* MX53_PAD_FEC_TXD0__GPIO1_30 */
1049 IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 2, 0x7F4, 0), /* MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 */
1050 IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 7, 0x000, 0), /* MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 */
1051 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 0, 0x000, 0), /* MX53_PAD_FEC_MDC__FEC_MDC */
1052 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 1, 0x000, 0), /* MX53_PAD_FEC_MDC__GPIO1_31 */
1053 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 2, 0x7F8, 0), /* MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 */
1054 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 3, 0x85C, 1), /* MX53_PAD_FEC_MDC__MLB_MLBDAT */
1055 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 4, 0x000, 0), /* MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG */
1056 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 7, 0x000, 0), /* MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 */
1057 IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 0, 0x000, 0), /* MX53_PAD_PATA_DIOW__PATA_DIOW */
1058 IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 1, 0x000, 0), /* MX53_PAD_PATA_DIOW__GPIO6_17 */
1059 IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 3, 0x000, 0), /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
1060 IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 7, 0x000, 0), /* MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 */
1061 IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 0, 0x000, 0), /* MX53_PAD_PATA_DMACK__PATA_DMACK */
1062 IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 1, 0x000, 0), /* MX53_PAD_PATA_DMACK__GPIO6_18 */
1063 IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 3, 0x878, 3), /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
1064 IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 7, 0x000, 0), /* MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 */
1065 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 0, 0x000, 0), /* MX53_PAD_PATA_DMARQ__PATA_DMARQ */
1066 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 1, 0x000, 0), /* MX53_PAD_PATA_DMARQ__GPIO7_0 */
1067 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 3, 0x000, 0), /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
1068 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 5, 0x000, 0), /* MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 */
1069 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 7, 0x000, 0), /* MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 */
1070 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 0, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN */
1071 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 1, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__GPIO7_1 */
1072 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 3, 0x880, 3), /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
1073 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 5, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 */
1074 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 7, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 */
1075 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 0, 0x000, 0), /* MX53_PAD_PATA_INTRQ__PATA_INTRQ */
1076 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 1, 0x000, 0), /* MX53_PAD_PATA_INTRQ__GPIO7_2 */
1077 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 3, 0x000, 0), /* MX53_PAD_PATA_INTRQ__UART2_CTS */
1078 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 4, 0x000, 0), /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
1079 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 5, 0x000, 0), /* MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 */
1080 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 7, 0x000, 0), /* MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 */
1081 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 0, 0x000, 0), /* MX53_PAD_PATA_DIOR__PATA_DIOR */
1082 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 1, 0x000, 0), /* MX53_PAD_PATA_DIOR__GPIO7_3 */
1083 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 3, 0x87C, 3), /* MX53_PAD_PATA_DIOR__UART2_RTS */
1084 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 4, 0x760, 1), /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
1085 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 7, 0x000, 0), /* MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 */
1086 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 0, 0x000, 0), /* MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B */
1087 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 1, 0x000, 0), /* MX53_PAD_PATA_RESET_B__GPIO7_4 */
1088 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 2, 0x000, 0), /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
1089 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 3, 0x000, 0), /* MX53_PAD_PATA_RESET_B__UART1_CTS */
1090 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 4, 0x000, 0), /* MX53_PAD_PATA_RESET_B__CAN2_TXCAN */
1091 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 7, 0x000, 0), /* MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 */
1092 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 0, 0x000, 0), /* MX53_PAD_PATA_IORDY__PATA_IORDY */
1093 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 1, 0x000, 0), /* MX53_PAD_PATA_IORDY__GPIO7_5 */
1094 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 2, 0x000, 0), /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
1095 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 3, 0x874, 3), /* MX53_PAD_PATA_IORDY__UART1_RTS */
1096 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 4, 0x764, 1), /* MX53_PAD_PATA_IORDY__CAN2_RXCAN */
1097 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 7, 0x000, 0), /* MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 */
1098 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 0, 0x000, 0), /* MX53_PAD_PATA_DA_0__PATA_DA_0 */
1099 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 1, 0x000, 0), /* MX53_PAD_PATA_DA_0__GPIO7_6 */
1100 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 2, 0x000, 0), /* MX53_PAD_PATA_DA_0__ESDHC3_RST */
1101 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 4, 0x864, 0), /* MX53_PAD_PATA_DA_0__OWIRE_LINE */
1102 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 7, 0x000, 0), /* MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 */
1103 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 0, 0x000, 0), /* MX53_PAD_PATA_DA_1__PATA_DA_1 */
1104 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 1, 0x000, 0), /* MX53_PAD_PATA_DA_1__GPIO7_7 */
1105 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 2, 0x000, 0), /* MX53_PAD_PATA_DA_1__ESDHC4_CMD */
1106 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 4, 0x000, 0), /* MX53_PAD_PATA_DA_1__UART3_CTS */
1107 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 7, 0x000, 0), /* MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 */
1108 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 0, 0x000, 0), /* MX53_PAD_PATA_DA_2__PATA_DA_2 */
1109 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 1, 0x000, 0), /* MX53_PAD_PATA_DA_2__GPIO7_8 */
1110 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 2, 0x000, 0), /* MX53_PAD_PATA_DA_2__ESDHC4_CLK */
1111 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 4, 0x884, 5), /* MX53_PAD_PATA_DA_2__UART3_RTS */
1112 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 7, 0x000, 0), /* MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 */
1113 IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 0, 0x000, 0), /* MX53_PAD_PATA_CS_0__PATA_CS_0 */
1114 IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 1, 0x000, 0), /* MX53_PAD_PATA_CS_0__GPIO7_9 */
1115 IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 4, 0x000, 0), /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
1116 IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 7, 0x000, 0), /* MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 */
1117 IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 0, 0x000, 0), /* MX53_PAD_PATA_CS_1__PATA_CS_1 */
1118 IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 1, 0x000, 0), /* MX53_PAD_PATA_CS_1__GPIO7_10 */
1119 IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 4, 0x888, 3), /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
1120 IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 7, 0x000, 0), /* MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 */
1121 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA0__PATA_DATA_0 */
1122 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA0__GPIO2_0 */
1123 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 */
1124 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
1125 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 */
1126 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 */
1127 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 7, 0x000, 0), /* MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 */
1128 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA1__PATA_DATA_1 */
1129 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA1__GPIO2_1 */
1130 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 */
1131 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
1132 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 */
1133 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 */
1134 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA2__PATA_DATA_2 */
1135 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA2__GPIO2_2 */
1136 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 */
1137 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
1138 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 */
1139 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 */
1140 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA3__PATA_DATA_3 */
1141 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA3__GPIO2_3 */
1142 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 */
1143 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
1144 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 */
1145 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 */
1146 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA4__PATA_DATA_4 */
1147 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA4__GPIO2_4 */
1148 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 */
1149 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA4__ESDHC4_DAT4 */
1150 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 */
1151 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 */
1152 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA5__PATA_DATA_5 */
1153 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA5__GPIO2_5 */
1154 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 */
1155 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA5__ESDHC4_DAT5 */
1156 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 */
1157 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 */
1158 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA6__PATA_DATA_6 */
1159 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA6__GPIO2_6 */
1160 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 */
1161 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA6__ESDHC4_DAT6 */
1162 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 */
1163 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 */
1164 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA7__PATA_DATA_7 */
1165 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA7__GPIO2_7 */
1166 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 */
1167 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA7__ESDHC4_DAT7 */
1168 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 */
1169 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 */
1170 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA8__PATA_DATA_8 */
1171 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA8__GPIO2_8 */
1172 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 2, 0x000, 0), /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
1173 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 */
1174 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
1175 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 */
1176 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 */
1177 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA9__PATA_DATA_9 */
1178 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA9__GPIO2_9 */
1179 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 2, 0x000, 0), /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
1180 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 */
1181 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
1182 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 */
1183 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 */
1184 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA10__PATA_DATA_10 */
1185 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA10__GPIO2_10 */
1186 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 2, 0x000, 0), /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
1187 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 */
1188 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
1189 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 */
1190 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 */
1191 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA11__PATA_DATA_11 */
1192 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA11__GPIO2_11 */
1193 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 2, 0x000, 0), /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
1194 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 */
1195 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
1196 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 */
1197 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 */
1198 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA12__PATA_DATA_12 */
1199 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA12__GPIO2_12 */
1200 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 2, 0x000, 0), /* MX53_PAD_PATA_DATA12__ESDHC2_DAT4 */
1201 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 */
1202 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA12__ESDHC4_DAT0 */
1203 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 */
1204 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 */
1205 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA13__PATA_DATA_13 */
1206 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA13__GPIO2_13 */
1207 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 2, 0x000, 0), /* MX53_PAD_PATA_DATA13__ESDHC2_DAT5 */
1208 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 */
1209 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA13__ESDHC4_DAT1 */
1210 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 */
1211 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 */
1212 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA14__PATA_DATA_14 */
1213 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA14__GPIO2_14 */
1214 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 2, 0x000, 0), /* MX53_PAD_PATA_DATA14__ESDHC2_DAT6 */
1215 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 */
1216 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA14__ESDHC4_DAT2 */
1217 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 */
1218 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 */
1219 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA15__PATA_DATA_15 */
1220 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA15__GPIO2_15 */
1221 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 2, 0x000, 0), /* MX53_PAD_PATA_DATA15__ESDHC2_DAT7 */
1222 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 */
1223 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA15__ESDHC4_DAT3 */
1224 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 */
1225 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 */
1226 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 0, 0x000, 0), /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1227 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 1, 0x000, 0), /* MX53_PAD_SD1_DATA0__GPIO1_16 */
1228 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 3, 0x000, 0), /* MX53_PAD_SD1_DATA0__GPT_CAPIN1 */
1229 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 5, 0x784, 2), /* MX53_PAD_SD1_DATA0__CSPI_MISO */
1230 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 7, 0x778, 0), /* MX53_PAD_SD1_DATA0__CCM_PLL3_BYP */
1231 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 0, 0x000, 0), /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1232 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 1, 0x000, 0), /* MX53_PAD_SD1_DATA1__GPIO1_17 */
1233 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 3, 0x000, 0), /* MX53_PAD_SD1_DATA1__GPT_CAPIN2 */
1234 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 5, 0x78C, 3), /* MX53_PAD_SD1_DATA1__CSPI_SS0 */
1235 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 7, 0x77C, 1), /* MX53_PAD_SD1_DATA1__CCM_PLL4_BYP */
1236 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 0, 0x000, 0), /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1237 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 1, 0x000, 0), /* MX53_PAD_SD1_CMD__GPIO1_18 */
1238 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 3, 0x000, 0), /* MX53_PAD_SD1_CMD__GPT_CMPOUT1 */
1239 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 5, 0x788, 2), /* MX53_PAD_SD1_CMD__CSPI_MOSI */
1240 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 7, 0x770, 0), /* MX53_PAD_SD1_CMD__CCM_PLL1_BYP */
1241 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 0, 0x000, 0), /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1242 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 1, 0x000, 0), /* MX53_PAD_SD1_DATA2__GPIO1_19 */
1243 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 2, 0x000, 0), /* MX53_PAD_SD1_DATA2__GPT_CMPOUT2 */
1244 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 3, 0x000, 0), /* MX53_PAD_SD1_DATA2__PWM2_PWMO */
1245 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 4, 0x000, 0), /* MX53_PAD_SD1_DATA2__WDOG1_WDOG_B */
1246 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 5, 0x790, 2), /* MX53_PAD_SD1_DATA2__CSPI_SS1 */
1247 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 6, 0x000, 0), /* MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB */
1248 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 7, 0x774, 0), /* MX53_PAD_SD1_DATA2__CCM_PLL2_BYP */
1249 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 0, 0x000, 0), /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
1250 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 1, 0x000, 0), /* MX53_PAD_SD1_CLK__GPIO1_20 */
1251 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 2, 0x000, 0), /* MX53_PAD_SD1_CLK__OSC32k_32K_OUT */
1252 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 3, 0x000, 0), /* MX53_PAD_SD1_CLK__GPT_CLKIN */
1253 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 5, 0x780, 2), /* MX53_PAD_SD1_CLK__CSPI_SCLK */
1254 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 7, 0x000, 0), /* MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 */
1255 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 0, 0x000, 0), /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
1256 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 1, 0x000, 0), /* MX53_PAD_SD1_DATA3__GPIO1_21 */
1257 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 2, 0x000, 0), /* MX53_PAD_SD1_DATA3__GPT_CMPOUT3 */
1258 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 3, 0x000, 0), /* MX53_PAD_SD1_DATA3__PWM1_PWMO */
1259 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 4, 0x000, 0), /* MX53_PAD_SD1_DATA3__WDOG2_WDOG_B */
1260 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 5, 0x794, 2), /* MX53_PAD_SD1_DATA3__CSPI_SS2 */
1261 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 6, 0x000, 0), /* MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB */
1262 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 7, 0x000, 0), /* MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 */
1263 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 0, 0x000, 0), /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
1264 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 1, 0x000, 0), /* MX53_PAD_SD2_CLK__GPIO1_10 */
1265 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 2, 0x840, 2), /* MX53_PAD_SD2_CLK__KPP_COL_5 */
1266 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 3, 0x73C, 1), /* MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
1267 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 5, 0x780, 3), /* MX53_PAD_SD2_CLK__CSPI_SCLK */
1268 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 7, 0x000, 0), /* MX53_PAD_SD2_CLK__SCC_RANDOM_V */
1269 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 0, 0x000, 0), /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
1270 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 1, 0x000, 0), /* MX53_PAD_SD2_CMD__GPIO1_11 */
1271 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 2, 0x84C, 1), /* MX53_PAD_SD2_CMD__KPP_ROW_5 */
1272 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 3, 0x738, 1), /* MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
1273 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 5, 0x788, 3), /* MX53_PAD_SD2_CMD__CSPI_MOSI */
1274 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 7, 0x000, 0), /* MX53_PAD_SD2_CMD__SCC_RANDOM */
1275 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 0, 0x000, 0), /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
1276 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 1, 0x000, 0), /* MX53_PAD_SD2_DATA3__GPIO1_12 */
1277 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 2, 0x844, 1), /* MX53_PAD_SD2_DATA3__KPP_COL_6 */
1278 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 3, 0x740, 1), /* MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC */
1279 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 5, 0x794, 3), /* MX53_PAD_SD2_DATA3__CSPI_SS2 */
1280 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 7, 0x000, 0), /* MX53_PAD_SD2_DATA3__SJC_DONE */
1281 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 0, 0x000, 0), /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
1282 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 1, 0x000, 0), /* MX53_PAD_SD2_DATA2__GPIO1_13 */
1283 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 2, 0x850, 1), /* MX53_PAD_SD2_DATA2__KPP_ROW_6 */
1284 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 3, 0x734, 1), /* MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD */
1285 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 5, 0x790, 3), /* MX53_PAD_SD2_DATA2__CSPI_SS1 */
1286 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 7, 0x000, 0), /* MX53_PAD_SD2_DATA2__SJC_FAIL */
1287 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 0, 0x000, 0), /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
1288 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 1, 0x000, 0), /* MX53_PAD_SD2_DATA1__GPIO1_14 */
1289 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 2, 0x848, 1), /* MX53_PAD_SD2_DATA1__KPP_COL_7 */
1290 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 3, 0x744, 0), /* MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS */
1291 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 5, 0x78C, 4), /* MX53_PAD_SD2_DATA1__CSPI_SS0 */
1292 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 7, 0x000, 0), /* MX53_PAD_SD2_DATA1__RTIC_SEC_VIO */
1293 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 0, 0x000, 0), /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
1294 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 1, 0x000, 0), /* MX53_PAD_SD2_DATA0__GPIO1_15 */
1295 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 2, 0x854, 1), /* MX53_PAD_SD2_DATA0__KPP_ROW_7 */
1296 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 3, 0x730, 1), /* MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD */
1297 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 5, 0x784, 3), /* MX53_PAD_SD2_DATA0__CSPI_MISO */
1298 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 7, 0x000, 0), /* MX53_PAD_SD2_DATA0__RTIC_DONE_INT */
1299 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 0, 0x000, 0), /* MX53_PAD_GPIO_0__CCM_CLKO */
1300 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 1, 0x000, 0), /* MX53_PAD_GPIO_0__GPIO1_0 */
1301 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 2, 0x840, 3), /* MX53_PAD_GPIO_0__KPP_COL_5 */
1302 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 3, 0x000, 0), /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
1303 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 4, 0x000, 0), /* MX53_PAD_GPIO_0__EPIT1_EPITO */
1304 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 5, 0x000, 0), /* MX53_PAD_GPIO_0__SRTC_ALARM_DEB */
1305 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 6, 0x000, 0), /* MX53_PAD_GPIO_0__USBOH3_USBH1_PWR */
1306 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 7, 0x000, 0), /* MX53_PAD_GPIO_0__CSU_TD */
1307 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 0, 0x7DC, 1), /* MX53_PAD_GPIO_1__ESAI1_SCKR */
1308 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 1, 0x000, 0), /* MX53_PAD_GPIO_1__GPIO1_1 */
1309 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 2, 0x84C, 2), /* MX53_PAD_GPIO_1__KPP_ROW_5 */
1310 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 3, 0x000, 0), /* MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK */
1311 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 4, 0x000, 0), /* MX53_PAD_GPIO_1__PWM2_PWMO */
1312 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 5, 0x000, 0), /* MX53_PAD_GPIO_1__WDOG2_WDOG_B */
1313 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 6, 0x000, 0), /* MX53_PAD_GPIO_1__ESDHC1_CD */
1314 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 7, 0x000, 0), /* MX53_PAD_GPIO_1__SRC_TESTER_ACK */
1315 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 0, 0x7CC, 1), /* MX53_PAD_GPIO_9__ESAI1_FSR */
1316 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 1, 0x000, 0), /* MX53_PAD_GPIO_9__GPIO1_9 */
1317 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 2, 0x844, 2), /* MX53_PAD_GPIO_9__KPP_COL_6 */
1318 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 3, 0x000, 0), /* MX53_PAD_GPIO_9__CCM_REF_EN_B */
1319 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 4, 0x000, 0), /* MX53_PAD_GPIO_9__PWM1_PWMO */
1320 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 5, 0x000, 0), /* MX53_PAD_GPIO_9__WDOG1_WDOG_B */
1321 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 6, 0x7FC, 1), /* MX53_PAD_GPIO_9__ESDHC1_WP */
1322 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 7, 0x000, 0), /* MX53_PAD_GPIO_9__SCC_FAIL_STATE */
1323 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 0, 0x7D4, 1), /* MX53_PAD_GPIO_3__ESAI1_HCKR */
1324 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 1, 0x000, 0), /* MX53_PAD_GPIO_3__GPIO1_3 */
1325 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 2, 0x824, 1), /* MX53_PAD_GPIO_3__I2C3_SCL */
1326 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 3, 0x000, 0), /* MX53_PAD_GPIO_3__DPLLIP1_TOG_EN */
1327 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 4, 0x000, 0), /* MX53_PAD_GPIO_3__CCM_CLKO2 */
1328 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 5, 0x000, 0), /* MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 */
1329 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 6, 0x8A0, 1), /* MX53_PAD_GPIO_3__USBOH3_USBH1_OC */
1330 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 7, 0x858, 2), /* MX53_PAD_GPIO_3__MLB_MLBCLK */
1331 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 0, 0x7E0, 1), /* MX53_PAD_GPIO_6__ESAI1_SCKT */
1332 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 1, 0x000, 0), /* MX53_PAD_GPIO_6__GPIO1_6 */
1333 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 2, 0x828, 1), /* MX53_PAD_GPIO_6__I2C3_SDA */
1334 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 3, 0x000, 0), /* MX53_PAD_GPIO_6__CCM_CCM_OUT_0 */
1335 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 4, 0x000, 0), /* MX53_PAD_GPIO_6__CSU_CSU_INT_DEB */
1336 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 5, 0x000, 0), /* MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 */
1337 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 6, 0x000, 0), /* MX53_PAD_GPIO_6__ESDHC2_LCTL */
1338 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 7, 0x860, 2), /* MX53_PAD_GPIO_6__MLB_MLBSIG */
1339 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 0, 0x7D0, 1), /* MX53_PAD_GPIO_2__ESAI1_FST */
1340 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 1, 0x000, 0), /* MX53_PAD_GPIO_2__GPIO1_2 */
1341 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 2, 0x850, 2), /* MX53_PAD_GPIO_2__KPP_ROW_6 */
1342 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 3, 0x000, 0), /* MX53_PAD_GPIO_2__CCM_CCM_OUT_1 */
1343 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 4, 0x000, 0), /* MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
1344 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 5, 0x000, 0), /* MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 */
1345 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 6, 0x000, 0), /* MX53_PAD_GPIO_2__ESDHC2_WP */
1346 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 7, 0x85C, 2), /* MX53_PAD_GPIO_2__MLB_MLBDAT */
1347 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 0, 0x7D8, 1), /* MX53_PAD_GPIO_4__ESAI1_HCKT */
1348 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 1, 0x000, 0), /* MX53_PAD_GPIO_4__GPIO1_4 */
1349 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 2, 0x848, 2), /* MX53_PAD_GPIO_4__KPP_COL_7 */
1350 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 3, 0x000, 0), /* MX53_PAD_GPIO_4__CCM_CCM_OUT_2 */
1351 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 4, 0x000, 0), /* MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
1352 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 5, 0x000, 0), /* MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 */
1353 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 6, 0x000, 0), /* MX53_PAD_GPIO_4__ESDHC2_CD */
1354 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 7, 0x000, 0), /* MX53_PAD_GPIO_4__SCC_SEC_STATE */
1355 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 0, 0x7EC, 1), /* MX53_PAD_GPIO_5__ESAI1_TX2_RX3 */
1356 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 1, 0x000, 0), /* MX53_PAD_GPIO_5__GPIO1_5 */
1357 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 2, 0x854, 2), /* MX53_PAD_GPIO_5__KPP_ROW_7 */
1358 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 3, 0x000, 0), /* MX53_PAD_GPIO_5__CCM_CLKO */
1359 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 4, 0x000, 0), /* MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
1360 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 5, 0x000, 0), /* MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 */
1361 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 6, 0x824, 2), /* MX53_PAD_GPIO_5__I2C3_SCL */
1362 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 7, 0x770, 1), /* MX53_PAD_GPIO_5__CCM_PLL1_BYP */
1363 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 0, 0x7F4, 1), /* MX53_PAD_GPIO_7__ESAI1_TX4_RX1 */
1364 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 1, 0x000, 0), /* MX53_PAD_GPIO_7__GPIO1_7 */
1365 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 2, 0x000, 0), /* MX53_PAD_GPIO_7__EPIT1_EPITO */
1366 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 3, 0x000, 0), /* MX53_PAD_GPIO_7__CAN1_TXCAN */
1367 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 4, 0x000, 0), /* MX53_PAD_GPIO_7__UART2_TXD_MUX */
1368 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 5, 0x80C, 1), /* MX53_PAD_GPIO_7__FIRI_RXD */
1369 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 6, 0x000, 0), /* MX53_PAD_GPIO_7__SPDIF_PLOCK */
1370 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 7, 0x774, 1), /* MX53_PAD_GPIO_7__CCM_PLL2_BYP */
1371 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 0, 0x7F8, 1), /* MX53_PAD_GPIO_8__ESAI1_TX5_RX0 */
1372 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 1, 0x000, 0), /* MX53_PAD_GPIO_8__GPIO1_8 */
1373 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 2, 0x000, 0), /* MX53_PAD_GPIO_8__EPIT2_EPITO */
1374 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 3, 0x760, 2), /* MX53_PAD_GPIO_8__CAN1_RXCAN */
1375 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 4, 0x880, 5), /* MX53_PAD_GPIO_8__UART2_RXD_MUX */
1376 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 5, 0x000, 0), /* MX53_PAD_GPIO_8__FIRI_TXD */
1377 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 6, 0x000, 0), /* MX53_PAD_GPIO_8__SPDIF_SRCLK */
1378 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 7, 0x778, 1), /* MX53_PAD_GPIO_8__CCM_PLL3_BYP */
1379 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 0, 0x7F0, 1), /* MX53_PAD_GPIO_16__ESAI1_TX3_RX2 */
1380 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 1, 0x000, 0), /* MX53_PAD_GPIO_16__GPIO7_11 */
1381 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 2, 0x000, 0), /* MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT */
1382 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 4, 0x000, 0), /* MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 */
1383 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 5, 0x870, 1), /* MX53_PAD_GPIO_16__SPDIF_IN1 */
1384 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 6, 0x828, 2), /* MX53_PAD_GPIO_16__I2C3_SDA */
1385 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 7, 0x000, 0), /* MX53_PAD_GPIO_16__SJC_DE_B */
1386 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 0, 0x7E4, 1), /* MX53_PAD_GPIO_17__ESAI1_TX0 */
1387 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 1, 0x000, 0), /* MX53_PAD_GPIO_17__GPIO7_12 */
1388 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 2, 0x868, 1), /* MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 */
1389 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 3, 0x810, 1), /* MX53_PAD_GPIO_17__GPC_PMIC_RDY */
1390 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 4, 0x000, 0), /* MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG */
1391 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 5, 0x000, 0), /* MX53_PAD_GPIO_17__SPDIF_OUT1 */
1392 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 6, 0x000, 0), /* MX53_PAD_GPIO_17__IPU_SNOOP2 */
1393 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 7, 0x000, 0), /* MX53_PAD_GPIO_17__SJC_JTAG_ACT */
1394 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 0, 0x7E8, 1), /* MX53_PAD_GPIO_18__ESAI1_TX1 */
1395 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 1, 0x000, 0), /* MX53_PAD_GPIO_18__GPIO7_13 */
1396 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 2, 0x86C, 1), /* MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 */
1397 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 3, 0x864, 1), /* MX53_PAD_GPIO_18__OWIRE_LINE */
1398 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 4, 0x000, 0), /* MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG */
1399 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 5, 0x768, 1), /* MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK */
1400 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 6, 0x000, 0), /* MX53_PAD_GPIO_18__ESDHC1_LCTL */
1401 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 7, 0x000, 0), /* MX53_PAD_GPIO_18__SRC_SYSTEM_RST */
1402}; 236};
1403 237
1404/* Pad names for the pinmux subsystem */ 238/* Pad names for the pinmux subsystem */
1405static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = { 239static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
240 IMX_PINCTRL_PIN(MX53_PAD_RESERVE0),
241 IMX_PINCTRL_PIN(MX53_PAD_RESERVE1),
242 IMX_PINCTRL_PIN(MX53_PAD_RESERVE2),
243 IMX_PINCTRL_PIN(MX53_PAD_RESERVE3),
244 IMX_PINCTRL_PIN(MX53_PAD_RESERVE4),
245 IMX_PINCTRL_PIN(MX53_PAD_RESERVE5),
246 IMX_PINCTRL_PIN(MX53_PAD_RESERVE6),
247 IMX_PINCTRL_PIN(MX53_PAD_RESERVE7),
1406 IMX_PINCTRL_PIN(MX53_PAD_GPIO_19), 248 IMX_PINCTRL_PIN(MX53_PAD_GPIO_19),
1407 IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0), 249 IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0),
1408 IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0), 250 IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0),
@@ -1517,6 +359,7 @@ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
1517 IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B), 359 IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B),
1518 IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B), 360 IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B),
1519 IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT), 361 IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT),
362 IMX_PINCTRL_PIN(MX53_PAD_RESERVE8),
1520 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P), 363 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P),
1521 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P), 364 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P),
1522 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P), 365 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P),
@@ -1609,8 +452,6 @@ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
1609static struct imx_pinctrl_soc_info imx53_pinctrl_info = { 452static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
1610 .pins = imx53_pinctrl_pads, 453 .pins = imx53_pinctrl_pads,
1611 .npins = ARRAY_SIZE(imx53_pinctrl_pads), 454 .npins = ARRAY_SIZE(imx53_pinctrl_pads),
1612 .pin_regs = imx53_pin_regs,
1613 .npin_regs = ARRAY_SIZE(imx53_pin_regs),
1614}; 455};
1615 456
1616static struct of_device_id imx53_pinctrl_of_match[] = { 457static struct of_device_id imx53_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/pinctrl-imx6dl.c
new file mode 100644
index 000000000000..a76b72427936
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx6dl.c
@@ -0,0 +1,497 @@
1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx.h"
18
19enum imx6dl_pads {
20 MX6DL_PAD_RESERVE0 = 0,
21 MX6DL_PAD_RESERVE1 = 1,
22 MX6DL_PAD_RESERVE2 = 2,
23 MX6DL_PAD_RESERVE3 = 3,
24 MX6DL_PAD_RESERVE4 = 4,
25 MX6DL_PAD_RESERVE5 = 5,
26 MX6DL_PAD_RESERVE6 = 6,
27 MX6DL_PAD_RESERVE7 = 7,
28 MX6DL_PAD_RESERVE8 = 8,
29 MX6DL_PAD_RESERVE9 = 9,
30 MX6DL_PAD_RESERVE10 = 10,
31 MX6DL_PAD_RESERVE11 = 11,
32 MX6DL_PAD_RESERVE12 = 12,
33 MX6DL_PAD_RESERVE13 = 13,
34 MX6DL_PAD_RESERVE14 = 14,
35 MX6DL_PAD_RESERVE15 = 15,
36 MX6DL_PAD_RESERVE16 = 16,
37 MX6DL_PAD_RESERVE17 = 17,
38 MX6DL_PAD_RESERVE18 = 18,
39 MX6DL_PAD_CSI0_DAT10 = 19,
40 MX6DL_PAD_CSI0_DAT11 = 20,
41 MX6DL_PAD_CSI0_DAT12 = 21,
42 MX6DL_PAD_CSI0_DAT13 = 22,
43 MX6DL_PAD_CSI0_DAT14 = 23,
44 MX6DL_PAD_CSI0_DAT15 = 24,
45 MX6DL_PAD_CSI0_DAT16 = 25,
46 MX6DL_PAD_CSI0_DAT17 = 26,
47 MX6DL_PAD_CSI0_DAT18 = 27,
48 MX6DL_PAD_CSI0_DAT19 = 28,
49 MX6DL_PAD_CSI0_DAT4 = 29,
50 MX6DL_PAD_CSI0_DAT5 = 30,
51 MX6DL_PAD_CSI0_DAT6 = 31,
52 MX6DL_PAD_CSI0_DAT7 = 32,
53 MX6DL_PAD_CSI0_DAT8 = 33,
54 MX6DL_PAD_CSI0_DAT9 = 34,
55 MX6DL_PAD_CSI0_DATA_EN = 35,
56 MX6DL_PAD_CSI0_MCLK = 36,
57 MX6DL_PAD_CSI0_PIXCLK = 37,
58 MX6DL_PAD_CSI0_VSYNC = 38,
59 MX6DL_PAD_DI0_DISP_CLK = 39,
60 MX6DL_PAD_DI0_PIN15 = 40,
61 MX6DL_PAD_DI0_PIN2 = 41,
62 MX6DL_PAD_DI0_PIN3 = 42,
63 MX6DL_PAD_DI0_PIN4 = 43,
64 MX6DL_PAD_DISP0_DAT0 = 44,
65 MX6DL_PAD_DISP0_DAT1 = 45,
66 MX6DL_PAD_DISP0_DAT10 = 46,
67 MX6DL_PAD_DISP0_DAT11 = 47,
68 MX6DL_PAD_DISP0_DAT12 = 48,
69 MX6DL_PAD_DISP0_DAT13 = 49,
70 MX6DL_PAD_DISP0_DAT14 = 50,
71 MX6DL_PAD_DISP0_DAT15 = 51,
72 MX6DL_PAD_DISP0_DAT16 = 52,
73 MX6DL_PAD_DISP0_DAT17 = 53,
74 MX6DL_PAD_DISP0_DAT18 = 54,
75 MX6DL_PAD_DISP0_DAT19 = 55,
76 MX6DL_PAD_DISP0_DAT2 = 56,
77 MX6DL_PAD_DISP0_DAT20 = 57,
78 MX6DL_PAD_DISP0_DAT21 = 58,
79 MX6DL_PAD_DISP0_DAT22 = 59,
80 MX6DL_PAD_DISP0_DAT23 = 60,
81 MX6DL_PAD_DISP0_DAT3 = 61,
82 MX6DL_PAD_DISP0_DAT4 = 62,
83 MX6DL_PAD_DISP0_DAT5 = 63,
84 MX6DL_PAD_DISP0_DAT6 = 64,
85 MX6DL_PAD_DISP0_DAT7 = 65,
86 MX6DL_PAD_DISP0_DAT8 = 66,
87 MX6DL_PAD_DISP0_DAT9 = 67,
88 MX6DL_PAD_EIM_A16 = 68,
89 MX6DL_PAD_EIM_A17 = 69,
90 MX6DL_PAD_EIM_A18 = 70,
91 MX6DL_PAD_EIM_A19 = 71,
92 MX6DL_PAD_EIM_A20 = 72,
93 MX6DL_PAD_EIM_A21 = 73,
94 MX6DL_PAD_EIM_A22 = 74,
95 MX6DL_PAD_EIM_A23 = 75,
96 MX6DL_PAD_EIM_A24 = 76,
97 MX6DL_PAD_EIM_A25 = 77,
98 MX6DL_PAD_EIM_BCLK = 78,
99 MX6DL_PAD_EIM_CS0 = 79,
100 MX6DL_PAD_EIM_CS1 = 80,
101 MX6DL_PAD_EIM_D16 = 81,
102 MX6DL_PAD_EIM_D17 = 82,
103 MX6DL_PAD_EIM_D18 = 83,
104 MX6DL_PAD_EIM_D19 = 84,
105 MX6DL_PAD_EIM_D20 = 85,
106 MX6DL_PAD_EIM_D21 = 86,
107 MX6DL_PAD_EIM_D22 = 87,
108 MX6DL_PAD_EIM_D23 = 88,
109 MX6DL_PAD_EIM_D24 = 89,
110 MX6DL_PAD_EIM_D25 = 90,
111 MX6DL_PAD_EIM_D26 = 91,
112 MX6DL_PAD_EIM_D27 = 92,
113 MX6DL_PAD_EIM_D28 = 93,
114 MX6DL_PAD_EIM_D29 = 94,
115 MX6DL_PAD_EIM_D30 = 95,
116 MX6DL_PAD_EIM_D31 = 96,
117 MX6DL_PAD_EIM_DA0 = 97,
118 MX6DL_PAD_EIM_DA1 = 98,
119 MX6DL_PAD_EIM_DA10 = 99,
120 MX6DL_PAD_EIM_DA11 = 100,
121 MX6DL_PAD_EIM_DA12 = 101,
122 MX6DL_PAD_EIM_DA13 = 102,
123 MX6DL_PAD_EIM_DA14 = 103,
124 MX6DL_PAD_EIM_DA15 = 104,
125 MX6DL_PAD_EIM_DA2 = 105,
126 MX6DL_PAD_EIM_DA3 = 106,
127 MX6DL_PAD_EIM_DA4 = 107,
128 MX6DL_PAD_EIM_DA5 = 108,
129 MX6DL_PAD_EIM_DA6 = 109,
130 MX6DL_PAD_EIM_DA7 = 110,
131 MX6DL_PAD_EIM_DA8 = 111,
132 MX6DL_PAD_EIM_DA9 = 112,
133 MX6DL_PAD_EIM_EB0 = 113,
134 MX6DL_PAD_EIM_EB1 = 114,
135 MX6DL_PAD_EIM_EB2 = 115,
136 MX6DL_PAD_EIM_EB3 = 116,
137 MX6DL_PAD_EIM_LBA = 117,
138 MX6DL_PAD_EIM_OE = 118,
139 MX6DL_PAD_EIM_RW = 119,
140 MX6DL_PAD_EIM_WAIT = 120,
141 MX6DL_PAD_ENET_CRS_DV = 121,
142 MX6DL_PAD_ENET_MDC = 122,
143 MX6DL_PAD_ENET_MDIO = 123,
144 MX6DL_PAD_ENET_REF_CLK = 124,
145 MX6DL_PAD_ENET_RX_ER = 125,
146 MX6DL_PAD_ENET_RXD0 = 126,
147 MX6DL_PAD_ENET_RXD1 = 127,
148 MX6DL_PAD_ENET_TX_EN = 128,
149 MX6DL_PAD_ENET_TXD0 = 129,
150 MX6DL_PAD_ENET_TXD1 = 130,
151 MX6DL_PAD_GPIO_0 = 131,
152 MX6DL_PAD_GPIO_1 = 132,
153 MX6DL_PAD_GPIO_16 = 133,
154 MX6DL_PAD_GPIO_17 = 134,
155 MX6DL_PAD_GPIO_18 = 135,
156 MX6DL_PAD_GPIO_19 = 136,
157 MX6DL_PAD_GPIO_2 = 137,
158 MX6DL_PAD_GPIO_3 = 138,
159 MX6DL_PAD_GPIO_4 = 139,
160 MX6DL_PAD_GPIO_5 = 140,
161 MX6DL_PAD_GPIO_6 = 141,
162 MX6DL_PAD_GPIO_7 = 142,
163 MX6DL_PAD_GPIO_8 = 143,
164 MX6DL_PAD_GPIO_9 = 144,
165 MX6DL_PAD_KEY_COL0 = 145,
166 MX6DL_PAD_KEY_COL1 = 146,
167 MX6DL_PAD_KEY_COL2 = 147,
168 MX6DL_PAD_KEY_COL3 = 148,
169 MX6DL_PAD_KEY_COL4 = 149,
170 MX6DL_PAD_KEY_ROW0 = 150,
171 MX6DL_PAD_KEY_ROW1 = 151,
172 MX6DL_PAD_KEY_ROW2 = 152,
173 MX6DL_PAD_KEY_ROW3 = 153,
174 MX6DL_PAD_KEY_ROW4 = 154,
175 MX6DL_PAD_NANDF_ALE = 155,
176 MX6DL_PAD_NANDF_CLE = 156,
177 MX6DL_PAD_NANDF_CS0 = 157,
178 MX6DL_PAD_NANDF_CS1 = 158,
179 MX6DL_PAD_NANDF_CS2 = 159,
180 MX6DL_PAD_NANDF_CS3 = 160,
181 MX6DL_PAD_NANDF_D0 = 161,
182 MX6DL_PAD_NANDF_D1 = 162,
183 MX6DL_PAD_NANDF_D2 = 163,
184 MX6DL_PAD_NANDF_D3 = 164,
185 MX6DL_PAD_NANDF_D4 = 165,
186 MX6DL_PAD_NANDF_D5 = 166,
187 MX6DL_PAD_NANDF_D6 = 167,
188 MX6DL_PAD_NANDF_D7 = 168,
189 MX6DL_PAD_NANDF_RB0 = 169,
190 MX6DL_PAD_NANDF_WP_B = 170,
191 MX6DL_PAD_RGMII_RD0 = 171,
192 MX6DL_PAD_RGMII_RD1 = 172,
193 MX6DL_PAD_RGMII_RD2 = 173,
194 MX6DL_PAD_RGMII_RD3 = 174,
195 MX6DL_PAD_RGMII_RX_CTL = 175,
196 MX6DL_PAD_RGMII_RXC = 176,
197 MX6DL_PAD_RGMII_TD0 = 177,
198 MX6DL_PAD_RGMII_TD1 = 178,
199 MX6DL_PAD_RGMII_TD2 = 179,
200 MX6DL_PAD_RGMII_TD3 = 180,
201 MX6DL_PAD_RGMII_TX_CTL = 181,
202 MX6DL_PAD_RGMII_TXC = 182,
203 MX6DL_PAD_SD1_CLK = 183,
204 MX6DL_PAD_SD1_CMD = 184,
205 MX6DL_PAD_SD1_DAT0 = 185,
206 MX6DL_PAD_SD1_DAT1 = 186,
207 MX6DL_PAD_SD1_DAT2 = 187,
208 MX6DL_PAD_SD1_DAT3 = 188,
209 MX6DL_PAD_SD2_CLK = 189,
210 MX6DL_PAD_SD2_CMD = 190,
211 MX6DL_PAD_SD2_DAT0 = 191,
212 MX6DL_PAD_SD2_DAT1 = 192,
213 MX6DL_PAD_SD2_DAT2 = 193,
214 MX6DL_PAD_SD2_DAT3 = 194,
215 MX6DL_PAD_SD3_CLK = 195,
216 MX6DL_PAD_SD3_CMD = 196,
217 MX6DL_PAD_SD3_DAT0 = 197,
218 MX6DL_PAD_SD3_DAT1 = 198,
219 MX6DL_PAD_SD3_DAT2 = 199,
220 MX6DL_PAD_SD3_DAT3 = 200,
221 MX6DL_PAD_SD3_DAT4 = 201,
222 MX6DL_PAD_SD3_DAT5 = 202,
223 MX6DL_PAD_SD3_DAT6 = 203,
224 MX6DL_PAD_SD3_DAT7 = 204,
225 MX6DL_PAD_SD3_RST = 205,
226 MX6DL_PAD_SD4_CLK = 206,
227 MX6DL_PAD_SD4_CMD = 207,
228 MX6DL_PAD_SD4_DAT0 = 208,
229 MX6DL_PAD_SD4_DAT1 = 209,
230 MX6DL_PAD_SD4_DAT2 = 210,
231 MX6DL_PAD_SD4_DAT3 = 211,
232 MX6DL_PAD_SD4_DAT4 = 212,
233 MX6DL_PAD_SD4_DAT5 = 213,
234 MX6DL_PAD_SD4_DAT6 = 214,
235 MX6DL_PAD_SD4_DAT7 = 215,
236};
237
238/* Pad names for the pinmux subsystem */
239static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
240 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0),
241 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1),
242 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2),
243 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3),
244 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4),
245 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5),
246 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6),
247 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7),
248 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8),
249 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9),
250 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10),
251 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11),
252 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12),
253 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13),
254 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14),
255 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15),
256 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE16),
257 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE17),
258 IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE18),
259 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT10),
260 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT11),
261 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT12),
262 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT13),
263 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT14),
264 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT15),
265 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT16),
266 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT17),
267 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT18),
268 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT19),
269 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT4),
270 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT5),
271 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT6),
272 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT7),
273 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT8),
274 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT9),
275 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DATA_EN),
276 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_MCLK),
277 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_PIXCLK),
278 IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_VSYNC),
279 IMX_PINCTRL_PIN(MX6DL_PAD_DI0_DISP_CLK),
280 IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN15),
281 IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN2),
282 IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN3),
283 IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN4),
284 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT0),
285 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT1),
286 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT10),
287 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT11),
288 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT12),
289 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT13),
290 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT14),
291 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT15),
292 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT16),
293 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT17),
294 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT18),
295 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT19),
296 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT2),
297 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT20),
298 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT21),
299 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT22),
300 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT23),
301 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT3),
302 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT4),
303 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT5),
304 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT6),
305 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT7),
306 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT8),
307 IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT9),
308 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A16),
309 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A17),
310 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A18),
311 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A19),
312 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A20),
313 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A21),
314 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A22),
315 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A23),
316 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A24),
317 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A25),
318 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_BCLK),
319 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS0),
320 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS1),
321 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D16),
322 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D17),
323 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D18),
324 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D19),
325 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D20),
326 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D21),
327 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D22),
328 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D23),
329 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D24),
330 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D25),
331 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D26),
332 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D27),
333 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D28),
334 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D29),
335 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D30),
336 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D31),
337 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA0),
338 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA1),
339 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA10),
340 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA11),
341 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA12),
342 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA13),
343 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA14),
344 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA15),
345 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA2),
346 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA3),
347 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA4),
348 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA5),
349 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA6),
350 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA7),
351 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA8),
352 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA9),
353 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB0),
354 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB1),
355 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB2),
356 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB3),
357 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_LBA),
358 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_OE),
359 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_RW),
360 IMX_PINCTRL_PIN(MX6DL_PAD_EIM_WAIT),
361 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_CRS_DV),
362 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDC),
363 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDIO),
364 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_REF_CLK),
365 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RX_ER),
366 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD0),
367 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD1),
368 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TX_EN),
369 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD0),
370 IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD1),
371 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_0),
372 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_1),
373 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_16),
374 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_17),
375 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_18),
376 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_19),
377 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_2),
378 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_3),
379 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_4),
380 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_5),
381 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_6),
382 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_7),
383 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_8),
384 IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_9),
385 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL0),
386 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL1),
387 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL2),
388 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL3),
389 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL4),
390 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW0),
391 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW1),
392 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW2),
393 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW3),
394 IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW4),
395 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_ALE),
396 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CLE),
397 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS0),
398 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS1),
399 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS2),
400 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS3),
401 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D0),
402 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D1),
403 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D2),
404 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D3),
405 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D4),
406 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D5),
407 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D6),
408 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D7),
409 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_RB0),
410 IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_WP_B),
411 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD0),
412 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD1),
413 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD2),
414 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD3),
415 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RX_CTL),
416 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RXC),
417 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD0),
418 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD1),
419 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD2),
420 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD3),
421 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TX_CTL),
422 IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TXC),
423 IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CLK),
424 IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CMD),
425 IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT0),
426 IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT1),
427 IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT2),
428 IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT3),
429 IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CLK),
430 IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CMD),
431 IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT0),
432 IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT1),
433 IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT2),
434 IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT3),
435 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CLK),
436 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CMD),
437 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT0),
438 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT1),
439 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT2),
440 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT3),
441 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT4),
442 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT5),
443 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT6),
444 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT7),
445 IMX_PINCTRL_PIN(MX6DL_PAD_SD3_RST),
446 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CLK),
447 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CMD),
448 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT0),
449 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT1),
450 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT2),
451 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT3),
452 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT4),
453 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5),
454 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6),
455 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),
456};
457
458static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
459 .pins = imx6dl_pinctrl_pads,
460 .npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
461};
462
463static struct of_device_id imx6dl_pinctrl_of_match[] = {
464 { .compatible = "fsl,imx6dl-iomuxc", },
465 { /* sentinel */ }
466};
467
468static int imx6dl_pinctrl_probe(struct platform_device *pdev)
469{
470 return imx_pinctrl_probe(pdev, &imx6dl_pinctrl_info);
471}
472
473static struct platform_driver imx6dl_pinctrl_driver = {
474 .driver = {
475 .name = "imx6dl-pinctrl",
476 .owner = THIS_MODULE,
477 .of_match_table = of_match_ptr(imx6dl_pinctrl_of_match),
478 },
479 .probe = imx6dl_pinctrl_probe,
480 .remove = imx_pinctrl_remove,
481};
482
483static int __init imx6dl_pinctrl_init(void)
484{
485 return platform_driver_register(&imx6dl_pinctrl_driver);
486}
487arch_initcall(imx6dl_pinctrl_init);
488
489static void __exit imx6dl_pinctrl_exit(void)
490{
491 platform_driver_unregister(&imx6dl_pinctrl_driver);
492}
493module_exit(imx6dl_pinctrl_exit);
494
495MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
496MODULE_DESCRIPTION("Freescale imx6dl pinctrl driver");
497MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
index 663346bb765e..76dd9c4949f4 100644
--- a/drivers/pinctrl/pinctrl-imx6q.c
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -23,1939 +23,245 @@
23#include "pinctrl-imx.h" 23#include "pinctrl-imx.h"
24 24
25enum imx6q_pads { 25enum imx6q_pads {
26 MX6Q_PAD_SD2_DAT1 = 0, 26 MX6Q_PAD_RESERVE0 = 0,
27 MX6Q_PAD_SD2_DAT2 = 1, 27 MX6Q_PAD_RESERVE1 = 1,
28 MX6Q_PAD_SD2_DAT0 = 2, 28 MX6Q_PAD_RESERVE2 = 2,
29 MX6Q_PAD_RGMII_TXC = 3, 29 MX6Q_PAD_RESERVE3 = 3,
30 MX6Q_PAD_RGMII_TD0 = 4, 30 MX6Q_PAD_RESERVE4 = 4,
31 MX6Q_PAD_RGMII_TD1 = 5, 31 MX6Q_PAD_RESERVE5 = 5,
32 MX6Q_PAD_RGMII_TD2 = 6, 32 MX6Q_PAD_RESERVE6 = 6,
33 MX6Q_PAD_RGMII_TD3 = 7, 33 MX6Q_PAD_RESERVE7 = 7,
34 MX6Q_PAD_RGMII_RX_CTL = 8, 34 MX6Q_PAD_RESERVE8 = 8,
35 MX6Q_PAD_RGMII_RD0 = 9, 35 MX6Q_PAD_RESERVE9 = 9,
36 MX6Q_PAD_RGMII_TX_CTL = 10, 36 MX6Q_PAD_RESERVE10 = 10,
37 MX6Q_PAD_RGMII_RD1 = 11, 37 MX6Q_PAD_RESERVE11 = 11,
38 MX6Q_PAD_RGMII_RD2 = 12, 38 MX6Q_PAD_RESERVE12 = 12,
39 MX6Q_PAD_RGMII_RD3 = 13, 39 MX6Q_PAD_RESERVE13 = 13,
40 MX6Q_PAD_RGMII_RXC = 14, 40 MX6Q_PAD_RESERVE14 = 14,
41 MX6Q_PAD_EIM_A25 = 15, 41 MX6Q_PAD_RESERVE15 = 15,
42 MX6Q_PAD_EIM_EB2 = 16, 42 MX6Q_PAD_RESERVE16 = 16,
43 MX6Q_PAD_EIM_D16 = 17, 43 MX6Q_PAD_RESERVE17 = 17,
44 MX6Q_PAD_EIM_D17 = 18, 44 MX6Q_PAD_RESERVE18 = 18,
45 MX6Q_PAD_EIM_D18 = 19, 45 MX6Q_PAD_SD2_DAT1 = 19,
46 MX6Q_PAD_EIM_D19 = 20, 46 MX6Q_PAD_SD2_DAT2 = 20,
47 MX6Q_PAD_EIM_D20 = 21, 47 MX6Q_PAD_SD2_DAT0 = 21,
48 MX6Q_PAD_EIM_D21 = 22, 48 MX6Q_PAD_RGMII_TXC = 22,
49 MX6Q_PAD_EIM_D22 = 23, 49 MX6Q_PAD_RGMII_TD0 = 23,
50 MX6Q_PAD_EIM_D23 = 24, 50 MX6Q_PAD_RGMII_TD1 = 24,
51 MX6Q_PAD_EIM_EB3 = 25, 51 MX6Q_PAD_RGMII_TD2 = 25,
52 MX6Q_PAD_EIM_D24 = 26, 52 MX6Q_PAD_RGMII_TD3 = 26,
53 MX6Q_PAD_EIM_D25 = 27, 53 MX6Q_PAD_RGMII_RX_CTL = 27,
54 MX6Q_PAD_EIM_D26 = 28, 54 MX6Q_PAD_RGMII_RD0 = 28,
55 MX6Q_PAD_EIM_D27 = 29, 55 MX6Q_PAD_RGMII_TX_CTL = 29,
56 MX6Q_PAD_EIM_D28 = 30, 56 MX6Q_PAD_RGMII_RD1 = 30,
57 MX6Q_PAD_EIM_D29 = 31, 57 MX6Q_PAD_RGMII_RD2 = 31,
58 MX6Q_PAD_EIM_D30 = 32, 58 MX6Q_PAD_RGMII_RD3 = 32,
59 MX6Q_PAD_EIM_D31 = 33, 59 MX6Q_PAD_RGMII_RXC = 33,
60 MX6Q_PAD_EIM_A24 = 34, 60 MX6Q_PAD_EIM_A25 = 34,
61 MX6Q_PAD_EIM_A23 = 35, 61 MX6Q_PAD_EIM_EB2 = 35,
62 MX6Q_PAD_EIM_A22 = 36, 62 MX6Q_PAD_EIM_D16 = 36,
63 MX6Q_PAD_EIM_A21 = 37, 63 MX6Q_PAD_EIM_D17 = 37,
64 MX6Q_PAD_EIM_A20 = 38, 64 MX6Q_PAD_EIM_D18 = 38,
65 MX6Q_PAD_EIM_A19 = 39, 65 MX6Q_PAD_EIM_D19 = 39,
66 MX6Q_PAD_EIM_A18 = 40, 66 MX6Q_PAD_EIM_D20 = 40,
67 MX6Q_PAD_EIM_A17 = 41, 67 MX6Q_PAD_EIM_D21 = 41,
68 MX6Q_PAD_EIM_A16 = 42, 68 MX6Q_PAD_EIM_D22 = 42,
69 MX6Q_PAD_EIM_CS0 = 43, 69 MX6Q_PAD_EIM_D23 = 43,
70 MX6Q_PAD_EIM_CS1 = 44, 70 MX6Q_PAD_EIM_EB3 = 44,
71 MX6Q_PAD_EIM_OE = 45, 71 MX6Q_PAD_EIM_D24 = 45,
72 MX6Q_PAD_EIM_RW = 46, 72 MX6Q_PAD_EIM_D25 = 46,
73 MX6Q_PAD_EIM_LBA = 47, 73 MX6Q_PAD_EIM_D26 = 47,
74 MX6Q_PAD_EIM_EB0 = 48, 74 MX6Q_PAD_EIM_D27 = 48,
75 MX6Q_PAD_EIM_EB1 = 49, 75 MX6Q_PAD_EIM_D28 = 49,
76 MX6Q_PAD_EIM_DA0 = 50, 76 MX6Q_PAD_EIM_D29 = 50,
77 MX6Q_PAD_EIM_DA1 = 51, 77 MX6Q_PAD_EIM_D30 = 51,
78 MX6Q_PAD_EIM_DA2 = 52, 78 MX6Q_PAD_EIM_D31 = 52,
79 MX6Q_PAD_EIM_DA3 = 53, 79 MX6Q_PAD_EIM_A24 = 53,
80 MX6Q_PAD_EIM_DA4 = 54, 80 MX6Q_PAD_EIM_A23 = 54,
81 MX6Q_PAD_EIM_DA5 = 55, 81 MX6Q_PAD_EIM_A22 = 55,
82 MX6Q_PAD_EIM_DA6 = 56, 82 MX6Q_PAD_EIM_A21 = 56,
83 MX6Q_PAD_EIM_DA7 = 57, 83 MX6Q_PAD_EIM_A20 = 57,
84 MX6Q_PAD_EIM_DA8 = 58, 84 MX6Q_PAD_EIM_A19 = 58,
85 MX6Q_PAD_EIM_DA9 = 59, 85 MX6Q_PAD_EIM_A18 = 59,
86 MX6Q_PAD_EIM_DA10 = 60, 86 MX6Q_PAD_EIM_A17 = 60,
87 MX6Q_PAD_EIM_DA11 = 61, 87 MX6Q_PAD_EIM_A16 = 61,
88 MX6Q_PAD_EIM_DA12 = 62, 88 MX6Q_PAD_EIM_CS0 = 62,
89 MX6Q_PAD_EIM_DA13 = 63, 89 MX6Q_PAD_EIM_CS1 = 63,
90 MX6Q_PAD_EIM_DA14 = 64, 90 MX6Q_PAD_EIM_OE = 64,
91 MX6Q_PAD_EIM_DA15 = 65, 91 MX6Q_PAD_EIM_RW = 65,
92 MX6Q_PAD_EIM_WAIT = 66, 92 MX6Q_PAD_EIM_LBA = 66,
93 MX6Q_PAD_EIM_BCLK = 67, 93 MX6Q_PAD_EIM_EB0 = 67,
94 MX6Q_PAD_DI0_DISP_CLK = 68, 94 MX6Q_PAD_EIM_EB1 = 68,
95 MX6Q_PAD_DI0_PIN15 = 69, 95 MX6Q_PAD_EIM_DA0 = 69,
96 MX6Q_PAD_DI0_PIN2 = 70, 96 MX6Q_PAD_EIM_DA1 = 70,
97 MX6Q_PAD_DI0_PIN3 = 71, 97 MX6Q_PAD_EIM_DA2 = 71,
98 MX6Q_PAD_DI0_PIN4 = 72, 98 MX6Q_PAD_EIM_DA3 = 72,
99 MX6Q_PAD_DISP0_DAT0 = 73, 99 MX6Q_PAD_EIM_DA4 = 73,
100 MX6Q_PAD_DISP0_DAT1 = 74, 100 MX6Q_PAD_EIM_DA5 = 74,
101 MX6Q_PAD_DISP0_DAT2 = 75, 101 MX6Q_PAD_EIM_DA6 = 75,
102 MX6Q_PAD_DISP0_DAT3 = 76, 102 MX6Q_PAD_EIM_DA7 = 76,
103 MX6Q_PAD_DISP0_DAT4 = 77, 103 MX6Q_PAD_EIM_DA8 = 77,
104 MX6Q_PAD_DISP0_DAT5 = 78, 104 MX6Q_PAD_EIM_DA9 = 78,
105 MX6Q_PAD_DISP0_DAT6 = 79, 105 MX6Q_PAD_EIM_DA10 = 79,
106 MX6Q_PAD_DISP0_DAT7 = 80, 106 MX6Q_PAD_EIM_DA11 = 80,
107 MX6Q_PAD_DISP0_DAT8 = 81, 107 MX6Q_PAD_EIM_DA12 = 81,
108 MX6Q_PAD_DISP0_DAT9 = 82, 108 MX6Q_PAD_EIM_DA13 = 82,
109 MX6Q_PAD_DISP0_DAT10 = 83, 109 MX6Q_PAD_EIM_DA14 = 83,
110 MX6Q_PAD_DISP0_DAT11 = 84, 110 MX6Q_PAD_EIM_DA15 = 84,
111 MX6Q_PAD_DISP0_DAT12 = 85, 111 MX6Q_PAD_EIM_WAIT = 85,
112 MX6Q_PAD_DISP0_DAT13 = 86, 112 MX6Q_PAD_EIM_BCLK = 86,
113 MX6Q_PAD_DISP0_DAT14 = 87, 113 MX6Q_PAD_DI0_DISP_CLK = 87,
114 MX6Q_PAD_DISP0_DAT15 = 88, 114 MX6Q_PAD_DI0_PIN15 = 88,
115 MX6Q_PAD_DISP0_DAT16 = 89, 115 MX6Q_PAD_DI0_PIN2 = 89,
116 MX6Q_PAD_DISP0_DAT17 = 90, 116 MX6Q_PAD_DI0_PIN3 = 90,
117 MX6Q_PAD_DISP0_DAT18 = 91, 117 MX6Q_PAD_DI0_PIN4 = 91,
118 MX6Q_PAD_DISP0_DAT19 = 92, 118 MX6Q_PAD_DISP0_DAT0 = 92,
119 MX6Q_PAD_DISP0_DAT20 = 93, 119 MX6Q_PAD_DISP0_DAT1 = 93,
120 MX6Q_PAD_DISP0_DAT21 = 94, 120 MX6Q_PAD_DISP0_DAT2 = 94,
121 MX6Q_PAD_DISP0_DAT22 = 95, 121 MX6Q_PAD_DISP0_DAT3 = 95,
122 MX6Q_PAD_DISP0_DAT23 = 96, 122 MX6Q_PAD_DISP0_DAT4 = 96,
123 MX6Q_PAD_ENET_MDIO = 97, 123 MX6Q_PAD_DISP0_DAT5 = 97,
124 MX6Q_PAD_ENET_REF_CLK = 98, 124 MX6Q_PAD_DISP0_DAT6 = 98,
125 MX6Q_PAD_ENET_RX_ER = 99, 125 MX6Q_PAD_DISP0_DAT7 = 99,
126 MX6Q_PAD_ENET_CRS_DV = 100, 126 MX6Q_PAD_DISP0_DAT8 = 100,
127 MX6Q_PAD_ENET_RXD1 = 101, 127 MX6Q_PAD_DISP0_DAT9 = 101,
128 MX6Q_PAD_ENET_RXD0 = 102, 128 MX6Q_PAD_DISP0_DAT10 = 102,
129 MX6Q_PAD_ENET_TX_EN = 103, 129 MX6Q_PAD_DISP0_DAT11 = 103,
130 MX6Q_PAD_ENET_TXD1 = 104, 130 MX6Q_PAD_DISP0_DAT12 = 104,
131 MX6Q_PAD_ENET_TXD0 = 105, 131 MX6Q_PAD_DISP0_DAT13 = 105,
132 MX6Q_PAD_ENET_MDC = 106, 132 MX6Q_PAD_DISP0_DAT14 = 106,
133 MX6Q_PAD_DRAM_D40 = 107, 133 MX6Q_PAD_DISP0_DAT15 = 107,
134 MX6Q_PAD_DRAM_D41 = 108, 134 MX6Q_PAD_DISP0_DAT16 = 108,
135 MX6Q_PAD_DRAM_D42 = 109, 135 MX6Q_PAD_DISP0_DAT17 = 109,
136 MX6Q_PAD_DRAM_D43 = 110, 136 MX6Q_PAD_DISP0_DAT18 = 110,
137 MX6Q_PAD_DRAM_D44 = 111, 137 MX6Q_PAD_DISP0_DAT19 = 111,
138 MX6Q_PAD_DRAM_D45 = 112, 138 MX6Q_PAD_DISP0_DAT20 = 112,
139 MX6Q_PAD_DRAM_D46 = 113, 139 MX6Q_PAD_DISP0_DAT21 = 113,
140 MX6Q_PAD_DRAM_D47 = 114, 140 MX6Q_PAD_DISP0_DAT22 = 114,
141 MX6Q_PAD_DRAM_SDQS5 = 115, 141 MX6Q_PAD_DISP0_DAT23 = 115,
142 MX6Q_PAD_DRAM_DQM5 = 116, 142 MX6Q_PAD_ENET_MDIO = 116,
143 MX6Q_PAD_DRAM_D32 = 117, 143 MX6Q_PAD_ENET_REF_CLK = 117,
144 MX6Q_PAD_DRAM_D33 = 118, 144 MX6Q_PAD_ENET_RX_ER = 118,
145 MX6Q_PAD_DRAM_D34 = 119, 145 MX6Q_PAD_ENET_CRS_DV = 119,
146 MX6Q_PAD_DRAM_D35 = 120, 146 MX6Q_PAD_ENET_RXD1 = 120,
147 MX6Q_PAD_DRAM_D36 = 121, 147 MX6Q_PAD_ENET_RXD0 = 121,
148 MX6Q_PAD_DRAM_D37 = 122, 148 MX6Q_PAD_ENET_TX_EN = 122,
149 MX6Q_PAD_DRAM_D38 = 123, 149 MX6Q_PAD_ENET_TXD1 = 123,
150 MX6Q_PAD_DRAM_D39 = 124, 150 MX6Q_PAD_ENET_TXD0 = 124,
151 MX6Q_PAD_DRAM_DQM4 = 125, 151 MX6Q_PAD_ENET_MDC = 125,
152 MX6Q_PAD_DRAM_SDQS4 = 126, 152 MX6Q_PAD_KEY_COL0 = 126,
153 MX6Q_PAD_DRAM_D24 = 127, 153 MX6Q_PAD_KEY_ROW0 = 127,
154 MX6Q_PAD_DRAM_D25 = 128, 154 MX6Q_PAD_KEY_COL1 = 128,
155 MX6Q_PAD_DRAM_D26 = 129, 155 MX6Q_PAD_KEY_ROW1 = 129,
156 MX6Q_PAD_DRAM_D27 = 130, 156 MX6Q_PAD_KEY_COL2 = 130,
157 MX6Q_PAD_DRAM_D28 = 131, 157 MX6Q_PAD_KEY_ROW2 = 131,
158 MX6Q_PAD_DRAM_D29 = 132, 158 MX6Q_PAD_KEY_COL3 = 132,
159 MX6Q_PAD_DRAM_SDQS3 = 133, 159 MX6Q_PAD_KEY_ROW3 = 133,
160 MX6Q_PAD_DRAM_D30 = 134, 160 MX6Q_PAD_KEY_COL4 = 134,
161 MX6Q_PAD_DRAM_D31 = 135, 161 MX6Q_PAD_KEY_ROW4 = 135,
162 MX6Q_PAD_DRAM_DQM3 = 136, 162 MX6Q_PAD_GPIO_0 = 136,
163 MX6Q_PAD_DRAM_D16 = 137, 163 MX6Q_PAD_GPIO_1 = 137,
164 MX6Q_PAD_DRAM_D17 = 138, 164 MX6Q_PAD_GPIO_9 = 138,
165 MX6Q_PAD_DRAM_D18 = 139, 165 MX6Q_PAD_GPIO_3 = 139,
166 MX6Q_PAD_DRAM_D19 = 140, 166 MX6Q_PAD_GPIO_6 = 140,
167 MX6Q_PAD_DRAM_D20 = 141, 167 MX6Q_PAD_GPIO_2 = 141,
168 MX6Q_PAD_DRAM_D21 = 142, 168 MX6Q_PAD_GPIO_4 = 142,
169 MX6Q_PAD_DRAM_D22 = 143, 169 MX6Q_PAD_GPIO_5 = 143,
170 MX6Q_PAD_DRAM_SDQS2 = 144, 170 MX6Q_PAD_GPIO_7 = 144,
171 MX6Q_PAD_DRAM_D23 = 145, 171 MX6Q_PAD_GPIO_8 = 145,
172 MX6Q_PAD_DRAM_DQM2 = 146, 172 MX6Q_PAD_GPIO_16 = 146,
173 MX6Q_PAD_DRAM_A0 = 147, 173 MX6Q_PAD_GPIO_17 = 147,
174 MX6Q_PAD_DRAM_A1 = 148, 174 MX6Q_PAD_GPIO_18 = 148,
175 MX6Q_PAD_DRAM_A2 = 149, 175 MX6Q_PAD_GPIO_19 = 149,
176 MX6Q_PAD_DRAM_A3 = 150, 176 MX6Q_PAD_CSI0_PIXCLK = 150,
177 MX6Q_PAD_DRAM_A4 = 151, 177 MX6Q_PAD_CSI0_MCLK = 151,
178 MX6Q_PAD_DRAM_A5 = 152, 178 MX6Q_PAD_CSI0_DATA_EN = 152,
179 MX6Q_PAD_DRAM_A6 = 153, 179 MX6Q_PAD_CSI0_VSYNC = 153,
180 MX6Q_PAD_DRAM_A7 = 154, 180 MX6Q_PAD_CSI0_DAT4 = 154,
181 MX6Q_PAD_DRAM_A8 = 155, 181 MX6Q_PAD_CSI0_DAT5 = 155,
182 MX6Q_PAD_DRAM_A9 = 156, 182 MX6Q_PAD_CSI0_DAT6 = 156,
183 MX6Q_PAD_DRAM_A10 = 157, 183 MX6Q_PAD_CSI0_DAT7 = 157,
184 MX6Q_PAD_DRAM_A11 = 158, 184 MX6Q_PAD_CSI0_DAT8 = 158,
185 MX6Q_PAD_DRAM_A12 = 159, 185 MX6Q_PAD_CSI0_DAT9 = 159,
186 MX6Q_PAD_DRAM_A13 = 160, 186 MX6Q_PAD_CSI0_DAT10 = 160,
187 MX6Q_PAD_DRAM_A14 = 161, 187 MX6Q_PAD_CSI0_DAT11 = 161,
188 MX6Q_PAD_DRAM_A15 = 162, 188 MX6Q_PAD_CSI0_DAT12 = 162,
189 MX6Q_PAD_DRAM_CAS = 163, 189 MX6Q_PAD_CSI0_DAT13 = 163,
190 MX6Q_PAD_DRAM_CS0 = 164, 190 MX6Q_PAD_CSI0_DAT14 = 164,
191 MX6Q_PAD_DRAM_CS1 = 165, 191 MX6Q_PAD_CSI0_DAT15 = 165,
192 MX6Q_PAD_DRAM_RAS = 166, 192 MX6Q_PAD_CSI0_DAT16 = 166,
193 MX6Q_PAD_DRAM_RESET = 167, 193 MX6Q_PAD_CSI0_DAT17 = 167,
194 MX6Q_PAD_DRAM_SDBA0 = 168, 194 MX6Q_PAD_CSI0_DAT18 = 168,
195 MX6Q_PAD_DRAM_SDBA1 = 169, 195 MX6Q_PAD_CSI0_DAT19 = 169,
196 MX6Q_PAD_DRAM_SDCLK_0 = 170, 196 MX6Q_PAD_SD3_DAT7 = 170,
197 MX6Q_PAD_DRAM_SDBA2 = 171, 197 MX6Q_PAD_SD3_DAT6 = 171,
198 MX6Q_PAD_DRAM_SDCKE0 = 172, 198 MX6Q_PAD_SD3_DAT5 = 172,
199 MX6Q_PAD_DRAM_SDCLK_1 = 173, 199 MX6Q_PAD_SD3_DAT4 = 173,
200 MX6Q_PAD_DRAM_SDCKE1 = 174, 200 MX6Q_PAD_SD3_CMD = 174,
201 MX6Q_PAD_DRAM_SDODT0 = 175, 201 MX6Q_PAD_SD3_CLK = 175,
202 MX6Q_PAD_DRAM_SDODT1 = 176, 202 MX6Q_PAD_SD3_DAT0 = 176,
203 MX6Q_PAD_DRAM_SDWE = 177, 203 MX6Q_PAD_SD3_DAT1 = 177,
204 MX6Q_PAD_DRAM_D0 = 178, 204 MX6Q_PAD_SD3_DAT2 = 178,
205 MX6Q_PAD_DRAM_D1 = 179, 205 MX6Q_PAD_SD3_DAT3 = 179,
206 MX6Q_PAD_DRAM_D2 = 180, 206 MX6Q_PAD_SD3_RST = 180,
207 MX6Q_PAD_DRAM_D3 = 181, 207 MX6Q_PAD_NANDF_CLE = 181,
208 MX6Q_PAD_DRAM_D4 = 182, 208 MX6Q_PAD_NANDF_ALE = 182,
209 MX6Q_PAD_DRAM_D5 = 183, 209 MX6Q_PAD_NANDF_WP_B = 183,
210 MX6Q_PAD_DRAM_SDQS0 = 184, 210 MX6Q_PAD_NANDF_RB0 = 184,
211 MX6Q_PAD_DRAM_D6 = 185, 211 MX6Q_PAD_NANDF_CS0 = 185,
212 MX6Q_PAD_DRAM_D7 = 186, 212 MX6Q_PAD_NANDF_CS1 = 186,
213 MX6Q_PAD_DRAM_DQM0 = 187, 213 MX6Q_PAD_NANDF_CS2 = 187,
214 MX6Q_PAD_DRAM_D8 = 188, 214 MX6Q_PAD_NANDF_CS3 = 188,
215 MX6Q_PAD_DRAM_D9 = 189, 215 MX6Q_PAD_SD4_CMD = 189,
216 MX6Q_PAD_DRAM_D10 = 190, 216 MX6Q_PAD_SD4_CLK = 190,
217 MX6Q_PAD_DRAM_D11 = 191, 217 MX6Q_PAD_NANDF_D0 = 191,
218 MX6Q_PAD_DRAM_D12 = 192, 218 MX6Q_PAD_NANDF_D1 = 192,
219 MX6Q_PAD_DRAM_D13 = 193, 219 MX6Q_PAD_NANDF_D2 = 193,
220 MX6Q_PAD_DRAM_D14 = 194, 220 MX6Q_PAD_NANDF_D3 = 194,
221 MX6Q_PAD_DRAM_SDQS1 = 195, 221 MX6Q_PAD_NANDF_D4 = 195,
222 MX6Q_PAD_DRAM_D15 = 196, 222 MX6Q_PAD_NANDF_D5 = 196,
223 MX6Q_PAD_DRAM_DQM1 = 197, 223 MX6Q_PAD_NANDF_D6 = 197,
224 MX6Q_PAD_DRAM_D48 = 198, 224 MX6Q_PAD_NANDF_D7 = 198,
225 MX6Q_PAD_DRAM_D49 = 199, 225 MX6Q_PAD_SD4_DAT0 = 199,
226 MX6Q_PAD_DRAM_D50 = 200, 226 MX6Q_PAD_SD4_DAT1 = 200,
227 MX6Q_PAD_DRAM_D51 = 201, 227 MX6Q_PAD_SD4_DAT2 = 201,
228 MX6Q_PAD_DRAM_D52 = 202, 228 MX6Q_PAD_SD4_DAT3 = 202,
229 MX6Q_PAD_DRAM_D53 = 203, 229 MX6Q_PAD_SD4_DAT4 = 203,
230 MX6Q_PAD_DRAM_D54 = 204, 230 MX6Q_PAD_SD4_DAT5 = 204,
231 MX6Q_PAD_DRAM_D55 = 205, 231 MX6Q_PAD_SD4_DAT6 = 205,
232 MX6Q_PAD_DRAM_SDQS6 = 206, 232 MX6Q_PAD_SD4_DAT7 = 206,
233 MX6Q_PAD_DRAM_DQM6 = 207, 233 MX6Q_PAD_SD1_DAT1 = 207,
234 MX6Q_PAD_DRAM_D56 = 208, 234 MX6Q_PAD_SD1_DAT0 = 208,
235 MX6Q_PAD_DRAM_SDQS7 = 209, 235 MX6Q_PAD_SD1_DAT3 = 209,
236 MX6Q_PAD_DRAM_D57 = 210, 236 MX6Q_PAD_SD1_CMD = 210,
237 MX6Q_PAD_DRAM_D58 = 211, 237 MX6Q_PAD_SD1_DAT2 = 211,
238 MX6Q_PAD_DRAM_D59 = 212, 238 MX6Q_PAD_SD1_CLK = 212,
239 MX6Q_PAD_DRAM_D60 = 213, 239 MX6Q_PAD_SD2_CLK = 213,
240 MX6Q_PAD_DRAM_DQM7 = 214, 240 MX6Q_PAD_SD2_CMD = 214,
241 MX6Q_PAD_DRAM_D61 = 215, 241 MX6Q_PAD_SD2_DAT3 = 215,
242 MX6Q_PAD_DRAM_D62 = 216,
243 MX6Q_PAD_DRAM_D63 = 217,
244 MX6Q_PAD_KEY_COL0 = 218,
245 MX6Q_PAD_KEY_ROW0 = 219,
246 MX6Q_PAD_KEY_COL1 = 220,
247 MX6Q_PAD_KEY_ROW1 = 221,
248 MX6Q_PAD_KEY_COL2 = 222,
249 MX6Q_PAD_KEY_ROW2 = 223,
250 MX6Q_PAD_KEY_COL3 = 224,
251 MX6Q_PAD_KEY_ROW3 = 225,
252 MX6Q_PAD_KEY_COL4 = 226,
253 MX6Q_PAD_KEY_ROW4 = 227,
254 MX6Q_PAD_GPIO_0 = 228,
255 MX6Q_PAD_GPIO_1 = 229,
256 MX6Q_PAD_GPIO_9 = 230,
257 MX6Q_PAD_GPIO_3 = 231,
258 MX6Q_PAD_GPIO_6 = 232,
259 MX6Q_PAD_GPIO_2 = 233,
260 MX6Q_PAD_GPIO_4 = 234,
261 MX6Q_PAD_GPIO_5 = 235,
262 MX6Q_PAD_GPIO_7 = 236,
263 MX6Q_PAD_GPIO_8 = 237,
264 MX6Q_PAD_GPIO_16 = 238,
265 MX6Q_PAD_GPIO_17 = 239,
266 MX6Q_PAD_GPIO_18 = 240,
267 MX6Q_PAD_GPIO_19 = 241,
268 MX6Q_PAD_CSI0_PIXCLK = 242,
269 MX6Q_PAD_CSI0_MCLK = 243,
270 MX6Q_PAD_CSI0_DATA_EN = 244,
271 MX6Q_PAD_CSI0_VSYNC = 245,
272 MX6Q_PAD_CSI0_DAT4 = 246,
273 MX6Q_PAD_CSI0_DAT5 = 247,
274 MX6Q_PAD_CSI0_DAT6 = 248,
275 MX6Q_PAD_CSI0_DAT7 = 249,
276 MX6Q_PAD_CSI0_DAT8 = 250,
277 MX6Q_PAD_CSI0_DAT9 = 251,
278 MX6Q_PAD_CSI0_DAT10 = 252,
279 MX6Q_PAD_CSI0_DAT11 = 253,
280 MX6Q_PAD_CSI0_DAT12 = 254,
281 MX6Q_PAD_CSI0_DAT13 = 255,
282 MX6Q_PAD_CSI0_DAT14 = 256,
283 MX6Q_PAD_CSI0_DAT15 = 257,
284 MX6Q_PAD_CSI0_DAT16 = 258,
285 MX6Q_PAD_CSI0_DAT17 = 259,
286 MX6Q_PAD_CSI0_DAT18 = 260,
287 MX6Q_PAD_CSI0_DAT19 = 261,
288 MX6Q_PAD_JTAG_TMS = 262,
289 MX6Q_PAD_JTAG_MOD = 263,
290 MX6Q_PAD_JTAG_TRSTB = 264,
291 MX6Q_PAD_JTAG_TDI = 265,
292 MX6Q_PAD_JTAG_TCK = 266,
293 MX6Q_PAD_JTAG_TDO = 267,
294 MX6Q_PAD_LVDS1_TX3_P = 268,
295 MX6Q_PAD_LVDS1_TX2_P = 269,
296 MX6Q_PAD_LVDS1_CLK_P = 270,
297 MX6Q_PAD_LVDS1_TX1_P = 271,
298 MX6Q_PAD_LVDS1_TX0_P = 272,
299 MX6Q_PAD_LVDS0_TX3_P = 273,
300 MX6Q_PAD_LVDS0_CLK_P = 274,
301 MX6Q_PAD_LVDS0_TX2_P = 275,
302 MX6Q_PAD_LVDS0_TX1_P = 276,
303 MX6Q_PAD_LVDS0_TX0_P = 277,
304 MX6Q_PAD_TAMPER = 278,
305 MX6Q_PAD_PMIC_ON_REQ = 279,
306 MX6Q_PAD_PMIC_STBY_REQ = 280,
307 MX6Q_PAD_POR_B = 281,
308 MX6Q_PAD_BOOT_MODE1 = 282,
309 MX6Q_PAD_RESET_IN_B = 283,
310 MX6Q_PAD_BOOT_MODE0 = 284,
311 MX6Q_PAD_TEST_MODE = 285,
312 MX6Q_PAD_SD3_DAT7 = 286,
313 MX6Q_PAD_SD3_DAT6 = 287,
314 MX6Q_PAD_SD3_DAT5 = 288,
315 MX6Q_PAD_SD3_DAT4 = 289,
316 MX6Q_PAD_SD3_CMD = 290,
317 MX6Q_PAD_SD3_CLK = 291,
318 MX6Q_PAD_SD3_DAT0 = 292,
319 MX6Q_PAD_SD3_DAT1 = 293,
320 MX6Q_PAD_SD3_DAT2 = 294,
321 MX6Q_PAD_SD3_DAT3 = 295,
322 MX6Q_PAD_SD3_RST = 296,
323 MX6Q_PAD_NANDF_CLE = 297,
324 MX6Q_PAD_NANDF_ALE = 298,
325 MX6Q_PAD_NANDF_WP_B = 299,
326 MX6Q_PAD_NANDF_RB0 = 300,
327 MX6Q_PAD_NANDF_CS0 = 301,
328 MX6Q_PAD_NANDF_CS1 = 302,
329 MX6Q_PAD_NANDF_CS2 = 303,
330 MX6Q_PAD_NANDF_CS3 = 304,
331 MX6Q_PAD_SD4_CMD = 305,
332 MX6Q_PAD_SD4_CLK = 306,
333 MX6Q_PAD_NANDF_D0 = 307,
334 MX6Q_PAD_NANDF_D1 = 308,
335 MX6Q_PAD_NANDF_D2 = 309,
336 MX6Q_PAD_NANDF_D3 = 310,
337 MX6Q_PAD_NANDF_D4 = 311,
338 MX6Q_PAD_NANDF_D5 = 312,
339 MX6Q_PAD_NANDF_D6 = 313,
340 MX6Q_PAD_NANDF_D7 = 314,
341 MX6Q_PAD_SD4_DAT0 = 315,
342 MX6Q_PAD_SD4_DAT1 = 316,
343 MX6Q_PAD_SD4_DAT2 = 317,
344 MX6Q_PAD_SD4_DAT3 = 318,
345 MX6Q_PAD_SD4_DAT4 = 319,
346 MX6Q_PAD_SD4_DAT5 = 320,
347 MX6Q_PAD_SD4_DAT6 = 321,
348 MX6Q_PAD_SD4_DAT7 = 322,
349 MX6Q_PAD_SD1_DAT1 = 323,
350 MX6Q_PAD_SD1_DAT0 = 324,
351 MX6Q_PAD_SD1_DAT3 = 325,
352 MX6Q_PAD_SD1_CMD = 326,
353 MX6Q_PAD_SD1_DAT2 = 327,
354 MX6Q_PAD_SD1_CLK = 328,
355 MX6Q_PAD_SD2_CLK = 329,
356 MX6Q_PAD_SD2_CMD = 330,
357 MX6Q_PAD_SD2_DAT3 = 331,
358};
359
360/* imx6q register maps */
361static struct imx_pin_reg imx6q_pin_regs[] = {
362 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
363 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
364 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
365 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
366 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
367 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
368 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
369 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
370 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
371 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
372 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
373 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
374 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
375 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
376 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
377 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
378 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
379 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
380 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
381 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
382 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
383 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
384 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
385 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
386 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
387 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
388 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
389 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
390 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
391 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
392 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
393 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
394 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
395 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
396 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
397 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
398 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
399 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
400 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
401 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
402 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
403 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
404 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
405 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
406 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
407 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
408 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
409 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
410 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
411 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
412 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
413 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
414 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
415 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
416 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
417 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
418 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
419 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
420 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
421 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
422 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
423 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
424 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
425 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
426 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
427 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
428 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
429 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
430 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
431 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
432 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
433 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
434 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
435 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
436 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
437 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
438 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
439 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
440 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
441 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
442 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
443 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
444 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
445 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
446 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
447 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
448 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
449 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
450 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
451 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
452 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
453 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
454 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
455 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
456 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
457 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
458 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
459 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
460 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
461 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
462 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
463 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
464 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
465 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
466 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
467 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
468 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
469 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
470 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
471 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
472 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
473 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
474 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
475 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
476 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
477 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
478 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
479 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
480 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
481 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
482 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
483 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
484 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
485 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
486 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
487 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
488 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
489 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
490 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
491 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
492 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
493 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
494 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
495 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
496 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
497 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
498 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
499 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
500 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
501 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
502 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
503 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
504 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
505 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
506 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
507 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
508 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
509 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
510 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
511 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
512 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
513 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
514 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
515 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
516 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
517 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
518 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
519 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
520 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
521 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
522 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
523 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
524 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
525 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
526 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
527 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
528 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
529 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
530 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
531 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
532 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
533 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
534 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
535 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
536 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
537 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
538 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
539 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
540 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
541 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
542 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
543 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
544 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
545 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
546 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
547 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
548 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
549 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
550 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
551 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
552 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
553 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
554 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
555 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
556 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
557 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
558 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
559 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
560 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
561 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
562 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
563 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
564 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
565 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
566 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
567 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
568 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
569 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
570 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
571 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
572 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
573 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
574 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
575 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
576 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
577 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
578 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
579 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
580 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
581 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
582 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
583 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
584 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
585 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
586 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
587 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
588 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
589 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
590 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
591 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
592 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
593 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
594 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
595 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
596 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
597 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
598 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
599 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
600 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
601 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
602 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
603 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
604 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
605 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
606 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
607 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
608 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
609 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
610 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
611 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
612 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
613 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
614 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
615 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
616 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
617 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
618 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
619 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
620 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
621 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
622 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
623 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
624 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
625 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
626 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
627 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
628 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
629 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
630 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
631 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
632 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
633 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
634 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
635 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
636 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
637 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
638 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
639 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
640 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
641 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
642 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
643 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
644 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
645 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
646 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
647 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
648 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
649 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
650 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
651 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
652 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
653 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
654 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
655 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
656 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
657 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
658 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
659 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
660 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
661 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
662 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
663 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
664 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
665 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
666 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
667 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
668 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
669 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
670 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
671 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
672 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
673 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
674 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
675 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
676 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
677 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
678 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
679 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
680 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
681 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
682 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
683 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
684 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
685 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
686 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
687 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
688 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
689 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
690 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
691 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
692 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
693 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
694 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
695 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
696 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
697 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
698 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
699 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
700 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
701 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
702 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
703 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
704 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
705 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
706 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
707 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
708 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
709 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
710 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
711 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
712 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
713 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
714 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
715 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
716 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
717 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
718 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
719 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
720 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
721 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
722 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
723 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
724 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
725 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
726 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
727 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
728 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
729 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
730 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
731 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
732 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
733 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
734 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
735 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
736 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
737 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
738 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
739 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
740 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
741 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
742 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
743 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
744 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
745 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
746 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
747 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
748 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
749 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
750 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
751 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
752 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
753 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
754 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
755 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
756 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
757 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
758 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
759 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
760 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
761 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
762 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
763 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
764 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
765 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
766 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
767 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
768 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
769 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
770 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
771 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
772 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
773 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
774 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
775 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
776 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
777 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
778 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
779 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
780 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
781 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
782 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
783 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
784 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
785 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
786 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
787 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
788 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
789 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
790 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
791 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
792 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
793 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
794 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
795 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
796 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
797 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
798 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
799 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
800 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
801 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
802 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
803 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
804 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
805 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
806 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
807 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
808 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
809 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
810 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
811 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
812 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
813 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
814 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
815 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
816 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
817 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
818 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
819 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
820 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
821 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
822 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
823 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
824 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
825 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
826 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
827 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
828 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
829 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
830 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
831 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
832 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
833 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
834 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
835 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
836 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
837 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
838 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
839 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
840 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
841 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
842 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
843 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
844 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
845 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
846 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
847 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
848 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
849 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
850 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
851 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
852 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
853 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
854 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
855 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
856 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
857 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
858 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
859 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
860 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
861 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
862 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
863 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
864 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
865 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
866 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
867 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
868 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
869 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
870 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
871 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
872 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
873 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
874 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
875 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
876 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
877 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
878 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
879 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
880 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
881 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
882 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
883 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
884 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
885 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
886 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
887 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
888 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
889 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
890 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
891 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
892 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
893 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
894 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
895 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
896 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
897 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
898 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
899 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
900 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
901 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
902 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
903 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
904 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
905 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
906 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
907 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
908 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
909 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
910 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
911 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
912 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
913 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
914 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
915 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
916 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
917 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
918 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
919 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
920 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
921 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
922 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
923 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
924 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
925 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
926 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
927 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
928 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
929 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
930 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
931 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
932 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
933 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
934 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
935 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
936 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
937 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
938 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
939 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
940 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
941 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
942 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
943 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
944 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
945 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
946 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
947 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
948 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
949 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
950 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
951 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
952 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
953 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
954 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
955 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
956 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
957 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
958 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
959 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
960 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
961 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
962 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
963 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
964 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
965 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
966 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
967 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
968 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
969 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
970 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
971 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
972 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
973 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
974 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
975 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
976 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
977 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
978 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
979 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
980 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
981 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
982 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
983 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
984 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
985 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
986 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
987 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
988 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
989 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
990 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
991 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
992 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
993 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
994 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
995 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
996 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
997 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
998 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
999 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
1000 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
1001 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
1002 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
1003 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
1004 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
1005 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
1006 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
1007 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
1008 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
1009 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
1010 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
1011 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
1012 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
1013 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
1014 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
1015 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
1016 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
1017 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
1018 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
1019 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
1020 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
1021 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
1022 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
1023 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
1024 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
1025 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
1026 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
1027 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
1028 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
1029 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
1030 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
1031 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
1032 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
1033 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
1034 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
1035 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
1036 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
1037 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
1038 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
1039 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
1040 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
1041 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
1042 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
1043 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
1044 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
1045 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
1046 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
1047 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
1048 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
1049 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
1050 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
1051 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
1052 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
1053 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
1054 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
1055 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
1056 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
1057 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
1058 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
1059 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
1060 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
1061 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
1062 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
1063 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
1064 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
1065 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
1066 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
1067 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
1068 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
1069 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
1070 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
1071 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
1072 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
1073 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
1074 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
1075 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
1076 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
1077 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
1078 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
1079 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
1080 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
1081 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
1082 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
1083 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
1084 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
1085 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
1086 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
1087 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
1088 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
1089 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
1090 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
1091 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
1092 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
1093 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
1094 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
1095 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
1096 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
1097 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
1098 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
1099 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
1100 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
1101 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
1102 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
1103 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
1104 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
1105 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
1106 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
1107 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
1108 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
1109 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
1110 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
1111 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
1112 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
1113 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
1114 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
1115 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
1116 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
1117 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
1118 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
1119 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
1120 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
1121 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
1122 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
1123 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
1124 IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
1125 IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
1126 IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
1127 IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
1128 IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
1129 IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
1130 IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
1131 IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
1132 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
1133 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
1134 IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
1135 IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
1136 IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
1137 IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
1138 IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
1139 IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
1140 IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
1141 IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
1142 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
1143 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
1144 IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
1145 IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
1146 IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
1147 IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
1148 IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
1149 IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
1150 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
1151 IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
1152 IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
1153 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
1154 IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
1155 IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
1156 IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
1157 IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
1158 IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
1159 IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
1160 IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
1161 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
1162 IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
1163 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
1164 IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
1165 IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
1166 IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
1167 IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
1168 IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
1169 IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
1170 IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
1171 IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
1172 IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
1173 IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
1174 IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
1175 IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
1176 IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
1177 IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
1178 IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
1179 IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
1180 IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
1181 IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
1182 IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
1183 IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
1184 IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
1185 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
1186 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
1187 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
1188 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
1189 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
1190 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
1191 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
1192 IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
1193 IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
1194 IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
1195 IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
1196 IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
1197 IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
1198 IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
1199 IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
1200 IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
1201 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
1202 IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
1203 IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
1204 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
1205 IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
1206 IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
1207 IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
1208 IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
1209 IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
1210 IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
1211 IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
1212 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
1213 IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
1214 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
1215 IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
1216 IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
1217 IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
1218 IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
1219 IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
1220 IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
1221 IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
1222 IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
1223 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
1224 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
1225 IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
1226 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
1227 IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
1228 IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
1229 IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
1230 IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
1231 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
1232 IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
1233 IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
1234 IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
1235 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
1236 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
1237 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
1238 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
1239 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
1240 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
1241 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
1242 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
1243 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
1244 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
1245 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
1246 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
1247 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
1248 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
1249 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
1250 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
1251 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
1252 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
1253 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
1254 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
1255 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
1256 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
1257 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
1258 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
1259 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
1260 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
1261 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
1262 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
1263 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
1264 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
1265 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
1266 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
1267 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
1268 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
1269 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
1270 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
1271 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
1272 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
1273 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
1274 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
1275 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
1276 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
1277 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
1278 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
1279 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
1280 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
1281 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
1282 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
1283 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
1284 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
1285 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
1286 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
1287 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
1288 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
1289 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
1290 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
1291 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
1292 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
1293 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
1294 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
1295 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
1296 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
1297 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
1298 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
1299 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
1300 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
1301 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
1302 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
1303 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
1304 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
1305 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
1306 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
1307 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
1308 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
1309 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
1310 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
1311 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
1312 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
1313 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
1314 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
1315 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
1316 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
1317 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
1318 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
1319 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
1320 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
1321 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
1322 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
1323 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
1324 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
1325 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
1326 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
1327 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
1328 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
1329 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
1330 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
1331 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
1332 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
1333 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
1334 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
1335 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
1336 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
1337 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
1338 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
1339 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
1340 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
1341 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
1342 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
1343 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
1344 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
1345 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
1346 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
1347 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
1348 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
1349 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
1350 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
1351 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
1352 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
1353 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
1354 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
1355 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
1356 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
1357 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
1358 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
1359 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
1360 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
1361 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
1362 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
1363 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
1364 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
1365 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
1366 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1367 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
1368 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
1369 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
1370 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
1371 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
1372 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
1373 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
1374 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1375 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
1376 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
1377 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
1378 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
1379 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
1380 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
1381 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
1382 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
1383 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
1384 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
1385 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
1386 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
1387 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
1388 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
1389 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
1390 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
1391 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
1392 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
1393 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
1394 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
1395 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
1396 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
1397 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
1398 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
1399 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
1400 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
1401 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
1402 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
1403 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
1404 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
1405 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
1406 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
1407 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
1408 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
1409 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
1410 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
1411 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
1412 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
1413 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
1414 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
1415 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
1416 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
1417 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
1418 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
1419 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
1420 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
1421 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
1422 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
1423 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
1424 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
1425 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
1426 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
1427 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
1428 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
1429 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
1430 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
1431 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
1432 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
1433 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
1434 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
1435 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
1436 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
1437 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
1438 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
1439 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
1440 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
1441 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
1442 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
1443 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
1444 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
1445 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
1446 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
1447 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
1448 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
1449 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
1450 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
1451 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
1452 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
1453 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
1454 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
1455 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
1456 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
1457 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
1458 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
1459 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
1460 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
1461 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
1462 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
1463 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
1464 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
1465 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
1466 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
1467 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
1468 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
1469 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
1470 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
1471 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
1472 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
1473 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
1474 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
1475 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
1476 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
1477 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
1478 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
1479 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
1480 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
1481 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
1482 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
1483 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
1484 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
1485 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
1486 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
1487 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
1488 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
1489 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
1490 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
1491 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
1492 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
1493 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
1494 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
1495 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
1496 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
1497 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
1498 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
1499 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
1500 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
1501 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
1502 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1503 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
1504 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
1505 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
1506 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
1507 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
1508 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
1509 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
1510 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
1511 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
1512 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
1513 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
1514 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
1515 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
1516 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
1517 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
1518 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
1519 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
1520 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
1521 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
1522 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
1523 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
1524 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
1525 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
1526 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
1527 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
1528 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
1529 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
1530 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
1531 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
1532 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
1533 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
1534 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
1535 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
1536 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
1537 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
1538 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
1539 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
1540 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
1541 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
1542 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
1543 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
1544 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
1545 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
1546 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
1547 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
1548 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
1549 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
1550 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
1551 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
1552 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
1553 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
1554 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
1555 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
1556 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
1557 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
1558 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
1559 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
1560 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
1561 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
1562 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
1563 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
1564 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
1565 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
1566 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
1567 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
1568 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
1569 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
1570 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
1571 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
1572 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
1573 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
1574 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
1575 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
1576 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
1577 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
1578 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
1579 IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
1580 IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
1581 IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
1582 IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
1583 IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
1584 IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
1585 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
1586 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
1587 IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
1588 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
1589 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
1590 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
1591 IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
1592 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
1593 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
1594 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
1595 IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
1596 IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
1597 IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
1598 IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
1599 IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
1600 IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
1601 IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
1602 IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
1603 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
1604 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
1605 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
1606 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
1607 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
1608 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
1609 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
1610 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
1611 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1612 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
1613 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
1614 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
1615 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
1616 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
1617 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
1618 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
1619 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1620 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
1621 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
1622 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
1623 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
1624 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1625 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
1626 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
1627 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1628 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
1629 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
1630 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
1631 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
1632 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
1633 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
1634 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
1635 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1636 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
1637 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
1638 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
1639 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
1640 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
1641 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
1642 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
1643 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1644 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
1645 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
1646 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
1647 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
1648 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
1649 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
1650 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
1651 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1652 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
1653 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
1654 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
1655 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
1656 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
1657 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
1658 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
1659 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1660 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
1661 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
1662 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
1663 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
1664 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
1665 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
1666 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
1667 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1668 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
1669 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
1670 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
1671 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
1672 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
1673 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
1674 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1675 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
1676 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
1677 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
1678 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
1679 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
1680 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
1681 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
1682 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
1683 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
1684 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
1685 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
1686 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
1687 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
1688 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
1689 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
1690 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1691 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
1692 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
1693 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
1694 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
1695 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
1696 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
1697 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
1698 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1699 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
1700 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
1701 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
1702 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
1703 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
1704 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
1705 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
1706 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1707 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
1708 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
1709 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
1710 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
1711 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
1712 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
1713 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
1714 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1715 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
1716 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
1717 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
1718 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
1719 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
1720 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
1721 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
1722 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1723 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
1724 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
1725 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1726 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
1727 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1728 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
1729 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
1730 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
1731 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
1732 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
1733 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1734 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
1735 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
1736 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
1737 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
1738 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
1739 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
1740 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1741 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
1742 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
1743 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
1744 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
1745 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
1746 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
1747 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
1748 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1749 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1750 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
1751 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
1752 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
1753 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
1754 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1755 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1756 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
1757 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
1758 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
1759 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1760 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
1761 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
1762 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
1763 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
1764 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1765 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
1766 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
1767 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1768 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
1769 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
1770 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
1771 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
1772 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1773 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
1774 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
1775 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1776 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
1777 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
1778 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
1779 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
1780 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1781 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
1782 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
1783 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1784 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
1785 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
1786 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
1787 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
1788 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
1789 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
1790 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
1791 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1792 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1793 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
1794 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
1795 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
1796 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
1797 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
1798 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
1799 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1800 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1801 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
1802 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
1803 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
1804 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
1805 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
1806 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
1807 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1808 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1809 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
1810 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
1811 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
1812 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1813 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
1814 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
1815 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1816 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
1817 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
1818 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
1819 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
1820 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
1821 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
1822 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
1823 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
1824 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1825 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
1826 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
1827 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
1828 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
1829 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
1830 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
1831 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
1832 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1833 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
1834 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
1835 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
1836 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
1837 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
1838 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
1839 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
1840 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1841 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
1842 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
1843 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
1844 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
1845 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
1846 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
1847 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
1848 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1849 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
1850 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
1851 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
1852 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
1853 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
1854 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
1855 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1856 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
1857 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
1858 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
1859 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
1860 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
1861 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
1862 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
1863 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1864 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
1865 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
1866 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
1867 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
1868 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
1869 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
1870 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
1871 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1872 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
1873 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
1874 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
1875 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
1876 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
1877 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
1878 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
1879 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
1880 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
1881 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
1882 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
1883 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
1884 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
1885 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
1886 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
1887 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
1888 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
1889 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
1890 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
1891 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
1892 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
1893 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
1894 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
1895 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
1896 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
1897 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
1898 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
1899 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
1900 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
1901 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
1902 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
1903 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
1904 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
1905 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
1906 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
1907 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
1908 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
1909 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
1910 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
1911 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
1912 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
1913 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
1914 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
1915 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
1916 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
1917 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
1918 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
1919 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
1920 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
1921 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
1922 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
1923 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
1924 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
1925 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
1926 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
1927 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
1928 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
1929 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
1930 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
1931 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
1932 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
1933 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
1934 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
1935 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
1936 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
1937 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
1938 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
1939 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1940 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
1941 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
1942 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
1943 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
1944 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
1945 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1946 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
1947 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
1948 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
1949 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
1950 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
1951 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
1952 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
1953 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID */
1954 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
1955}; 242};
1956 243
1957/* Pad names for the pinmux subsystem */ 244/* Pad names for the pinmux subsystem */
1958static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { 245static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
246 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0),
247 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1),
248 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2),
249 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3),
250 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4),
251 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5),
252 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6),
253 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7),
254 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8),
255 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9),
256 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10),
257 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11),
258 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12),
259 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13),
260 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14),
261 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15),
262 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16),
263 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17),
264 IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18),
1959 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1), 265 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
1960 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2), 266 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
1961 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0), 267 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
@@ -2063,117 +369,6 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
2063 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1), 369 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
2064 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0), 370 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
2065 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC), 371 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
2066 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
2067 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
2068 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
2069 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
2070 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
2071 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
2072 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
2073 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
2074 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
2075 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
2076 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
2077 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
2078 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
2079 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
2080 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
2081 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
2082 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
2083 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
2084 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
2085 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
2086 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
2087 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
2088 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
2089 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
2090 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
2091 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
2092 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
2093 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
2094 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
2095 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
2096 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
2097 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
2098 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
2099 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
2100 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
2101 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
2102 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
2103 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
2104 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
2105 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
2106 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
2107 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
2108 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
2109 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
2110 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
2111 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
2112 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
2113 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
2114 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
2115 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
2116 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
2117 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
2118 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
2119 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
2120 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
2121 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
2122 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
2123 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
2124 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
2125 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
2126 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
2127 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
2128 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
2129 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
2130 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
2131 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
2132 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
2133 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
2134 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
2135 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
2136 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
2137 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
2138 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
2139 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
2140 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
2141 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
2142 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
2143 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
2144 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
2145 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
2146 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
2147 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
2148 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
2149 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
2150 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
2151 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
2152 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
2153 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
2154 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
2155 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
2156 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
2157 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
2158 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
2159 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
2160 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
2161 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
2162 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
2163 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
2164 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
2165 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
2166 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
2167 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
2168 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
2169 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
2170 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
2171 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
2172 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
2173 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
2174 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
2175 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
2176 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
2177 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0), 372 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
2178 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0), 373 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
2179 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1), 374 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
@@ -2218,30 +413,6 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
2218 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17), 413 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
2219 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18), 414 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
2220 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19), 415 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
2221 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
2222 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
2223 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
2224 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
2225 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
2226 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
2227 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
2228 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
2229 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
2230 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
2231 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
2232 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
2233 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
2234 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
2235 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
2236 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
2237 IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
2238 IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
2239 IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
2240 IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
2241 IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
2242 IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
2243 IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
2244 IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
2245 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7), 416 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
2246 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6), 417 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
2247 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5), 418 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
@@ -2293,8 +464,6 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
2293static struct imx_pinctrl_soc_info imx6q_pinctrl_info = { 464static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
2294 .pins = imx6q_pinctrl_pads, 465 .pins = imx6q_pinctrl_pads,
2295 .npins = ARRAY_SIZE(imx6q_pinctrl_pads), 466 .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
2296 .pin_regs = imx6q_pin_regs,
2297 .npin_regs = ARRAY_SIZE(imx6q_pin_regs),
2298}; 467};
2299 468
2300static struct of_device_id imx6q_pinctrl_of_match[] = { 469static struct of_device_id imx6q_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/pinctrl-imx6sl.c
new file mode 100644
index 000000000000..4eb7ccab5f2d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx6sl.c
@@ -0,0 +1,403 @@
1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx.h"
18
19enum imx6sl_pads {
20 MX6SL_PAD_RESERVE0 = 0,
21 MX6SL_PAD_RESERVE1 = 1,
22 MX6SL_PAD_RESERVE2 = 2,
23 MX6SL_PAD_RESERVE3 = 3,
24 MX6SL_PAD_RESERVE4 = 4,
25 MX6SL_PAD_RESERVE5 = 5,
26 MX6SL_PAD_RESERVE6 = 6,
27 MX6SL_PAD_RESERVE7 = 7,
28 MX6SL_PAD_RESERVE8 = 8,
29 MX6SL_PAD_RESERVE9 = 9,
30 MX6SL_PAD_RESERVE10 = 10,
31 MX6SL_PAD_RESERVE11 = 11,
32 MX6SL_PAD_RESERVE12 = 12,
33 MX6SL_PAD_RESERVE13 = 13,
34 MX6SL_PAD_RESERVE14 = 14,
35 MX6SL_PAD_RESERVE15 = 15,
36 MX6SL_PAD_RESERVE16 = 16,
37 MX6SL_PAD_RESERVE17 = 17,
38 MX6SL_PAD_RESERVE18 = 18,
39 MX6SL_PAD_AUD_MCLK = 19,
40 MX6SL_PAD_AUD_RXC = 20,
41 MX6SL_PAD_AUD_RXD = 21,
42 MX6SL_PAD_AUD_RXFS = 22,
43 MX6SL_PAD_AUD_TXC = 23,
44 MX6SL_PAD_AUD_TXD = 24,
45 MX6SL_PAD_AUD_TXFS = 25,
46 MX6SL_PAD_ECSPI1_MISO = 26,
47 MX6SL_PAD_ECSPI1_MOSI = 27,
48 MX6SL_PAD_ECSPI1_SCLK = 28,
49 MX6SL_PAD_ECSPI1_SS0 = 29,
50 MX6SL_PAD_ECSPI2_MISO = 30,
51 MX6SL_PAD_ECSPI2_MOSI = 31,
52 MX6SL_PAD_ECSPI2_SCLK = 32,
53 MX6SL_PAD_ECSPI2_SS0 = 33,
54 MX6SL_PAD_EPDC_BDR0 = 34,
55 MX6SL_PAD_EPDC_BDR1 = 35,
56 MX6SL_PAD_EPDC_D0 = 36,
57 MX6SL_PAD_EPDC_D1 = 37,
58 MX6SL_PAD_EPDC_D10 = 38,
59 MX6SL_PAD_EPDC_D11 = 39,
60 MX6SL_PAD_EPDC_D12 = 40,
61 MX6SL_PAD_EPDC_D13 = 41,
62 MX6SL_PAD_EPDC_D14 = 42,
63 MX6SL_PAD_EPDC_D15 = 43,
64 MX6SL_PAD_EPDC_D2 = 44,
65 MX6SL_PAD_EPDC_D3 = 45,
66 MX6SL_PAD_EPDC_D4 = 46,
67 MX6SL_PAD_EPDC_D5 = 47,
68 MX6SL_PAD_EPDC_D6 = 48,
69 MX6SL_PAD_EPDC_D7 = 49,
70 MX6SL_PAD_EPDC_D8 = 50,
71 MX6SL_PAD_EPDC_D9 = 51,
72 MX6SL_PAD_EPDC_GDCLK = 52,
73 MX6SL_PAD_EPDC_GDOE = 53,
74 MX6SL_PAD_EPDC_GDRL = 54,
75 MX6SL_PAD_EPDC_GDSP = 55,
76 MX6SL_PAD_EPDC_PWRCOM = 56,
77 MX6SL_PAD_EPDC_PWRCTRL0 = 57,
78 MX6SL_PAD_EPDC_PWRCTRL1 = 58,
79 MX6SL_PAD_EPDC_PWRCTRL2 = 59,
80 MX6SL_PAD_EPDC_PWRCTRL3 = 60,
81 MX6SL_PAD_EPDC_PWRINT = 61,
82 MX6SL_PAD_EPDC_PWRSTAT = 62,
83 MX6SL_PAD_EPDC_PWRWAKEUP = 63,
84 MX6SL_PAD_EPDC_SDCE0 = 64,
85 MX6SL_PAD_EPDC_SDCE1 = 65,
86 MX6SL_PAD_EPDC_SDCE2 = 66,
87 MX6SL_PAD_EPDC_SDCE3 = 67,
88 MX6SL_PAD_EPDC_SDCLK = 68,
89 MX6SL_PAD_EPDC_SDLE = 69,
90 MX6SL_PAD_EPDC_SDOE = 70,
91 MX6SL_PAD_EPDC_SDSHR = 71,
92 MX6SL_PAD_EPDC_VCOM0 = 72,
93 MX6SL_PAD_EPDC_VCOM1 = 73,
94 MX6SL_PAD_FEC_CRS_DV = 74,
95 MX6SL_PAD_FEC_MDC = 75,
96 MX6SL_PAD_FEC_MDIO = 76,
97 MX6SL_PAD_FEC_REF_CLK = 77,
98 MX6SL_PAD_FEC_RX_ER = 78,
99 MX6SL_PAD_FEC_RXD0 = 79,
100 MX6SL_PAD_FEC_RXD1 = 80,
101 MX6SL_PAD_FEC_TX_CLK = 81,
102 MX6SL_PAD_FEC_TX_EN = 82,
103 MX6SL_PAD_FEC_TXD0 = 83,
104 MX6SL_PAD_FEC_TXD1 = 84,
105 MX6SL_PAD_HSIC_DAT = 85,
106 MX6SL_PAD_HSIC_STROBE = 86,
107 MX6SL_PAD_I2C1_SCL = 87,
108 MX6SL_PAD_I2C1_SDA = 88,
109 MX6SL_PAD_I2C2_SCL = 89,
110 MX6SL_PAD_I2C2_SDA = 90,
111 MX6SL_PAD_KEY_COL0 = 91,
112 MX6SL_PAD_KEY_COL1 = 92,
113 MX6SL_PAD_KEY_COL2 = 93,
114 MX6SL_PAD_KEY_COL3 = 94,
115 MX6SL_PAD_KEY_COL4 = 95,
116 MX6SL_PAD_KEY_COL5 = 96,
117 MX6SL_PAD_KEY_COL6 = 97,
118 MX6SL_PAD_KEY_COL7 = 98,
119 MX6SL_PAD_KEY_ROW0 = 99,
120 MX6SL_PAD_KEY_ROW1 = 100,
121 MX6SL_PAD_KEY_ROW2 = 101,
122 MX6SL_PAD_KEY_ROW3 = 102,
123 MX6SL_PAD_KEY_ROW4 = 103,
124 MX6SL_PAD_KEY_ROW5 = 104,
125 MX6SL_PAD_KEY_ROW6 = 105,
126 MX6SL_PAD_KEY_ROW7 = 106,
127 MX6SL_PAD_LCD_CLK = 107,
128 MX6SL_PAD_LCD_DAT0 = 108,
129 MX6SL_PAD_LCD_DAT1 = 109,
130 MX6SL_PAD_LCD_DAT10 = 110,
131 MX6SL_PAD_LCD_DAT11 = 111,
132 MX6SL_PAD_LCD_DAT12 = 112,
133 MX6SL_PAD_LCD_DAT13 = 113,
134 MX6SL_PAD_LCD_DAT14 = 114,
135 MX6SL_PAD_LCD_DAT15 = 115,
136 MX6SL_PAD_LCD_DAT16 = 116,
137 MX6SL_PAD_LCD_DAT17 = 117,
138 MX6SL_PAD_LCD_DAT18 = 118,
139 MX6SL_PAD_LCD_DAT19 = 119,
140 MX6SL_PAD_LCD_DAT2 = 120,
141 MX6SL_PAD_LCD_DAT20 = 121,
142 MX6SL_PAD_LCD_DAT21 = 122,
143 MX6SL_PAD_LCD_DAT22 = 123,
144 MX6SL_PAD_LCD_DAT23 = 124,
145 MX6SL_PAD_LCD_DAT3 = 125,
146 MX6SL_PAD_LCD_DAT4 = 126,
147 MX6SL_PAD_LCD_DAT5 = 127,
148 MX6SL_PAD_LCD_DAT6 = 128,
149 MX6SL_PAD_LCD_DAT7 = 129,
150 MX6SL_PAD_LCD_DAT8 = 130,
151 MX6SL_PAD_LCD_DAT9 = 131,
152 MX6SL_PAD_LCD_ENABLE = 132,
153 MX6SL_PAD_LCD_HSYNC = 133,
154 MX6SL_PAD_LCD_RESET = 134,
155 MX6SL_PAD_LCD_VSYNC = 135,
156 MX6SL_PAD_PWM1 = 136,
157 MX6SL_PAD_REF_CLK_24M = 137,
158 MX6SL_PAD_REF_CLK_32K = 138,
159 MX6SL_PAD_SD1_CLK = 139,
160 MX6SL_PAD_SD1_CMD = 140,
161 MX6SL_PAD_SD1_DAT0 = 141,
162 MX6SL_PAD_SD1_DAT1 = 142,
163 MX6SL_PAD_SD1_DAT2 = 143,
164 MX6SL_PAD_SD1_DAT3 = 144,
165 MX6SL_PAD_SD1_DAT4 = 145,
166 MX6SL_PAD_SD1_DAT5 = 146,
167 MX6SL_PAD_SD1_DAT6 = 147,
168 MX6SL_PAD_SD1_DAT7 = 148,
169 MX6SL_PAD_SD2_CLK = 149,
170 MX6SL_PAD_SD2_CMD = 150,
171 MX6SL_PAD_SD2_DAT0 = 151,
172 MX6SL_PAD_SD2_DAT1 = 152,
173 MX6SL_PAD_SD2_DAT2 = 153,
174 MX6SL_PAD_SD2_DAT3 = 154,
175 MX6SL_PAD_SD2_DAT4 = 155,
176 MX6SL_PAD_SD2_DAT5 = 156,
177 MX6SL_PAD_SD2_DAT6 = 157,
178 MX6SL_PAD_SD2_DAT7 = 158,
179 MX6SL_PAD_SD2_RST = 159,
180 MX6SL_PAD_SD3_CLK = 160,
181 MX6SL_PAD_SD3_CMD = 161,
182 MX6SL_PAD_SD3_DAT0 = 162,
183 MX6SL_PAD_SD3_DAT1 = 163,
184 MX6SL_PAD_SD3_DAT2 = 164,
185 MX6SL_PAD_SD3_DAT3 = 165,
186 MX6SL_PAD_UART1_RXD = 166,
187 MX6SL_PAD_UART1_TXD = 167,
188 MX6SL_PAD_WDOG_B = 168,
189};
190
191/* Pad names for the pinmux subsystem */
192static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
193 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0),
194 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1),
195 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2),
196 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3),
197 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4),
198 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5),
199 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6),
200 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7),
201 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8),
202 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9),
203 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10),
204 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11),
205 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12),
206 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13),
207 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14),
208 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15),
209 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16),
210 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17),
211 IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18),
212 IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK),
213 IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC),
214 IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD),
215 IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS),
216 IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC),
217 IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD),
218 IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS),
219 IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO),
220 IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI),
221 IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK),
222 IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0),
223 IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO),
224 IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI),
225 IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK),
226 IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0),
227 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0),
228 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1),
229 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0),
230 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1),
231 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10),
232 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11),
233 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12),
234 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13),
235 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14),
236 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15),
237 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2),
238 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3),
239 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4),
240 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5),
241 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6),
242 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7),
243 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8),
244 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9),
245 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK),
246 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE),
247 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL),
248 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP),
249 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM),
250 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0),
251 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1),
252 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2),
253 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3),
254 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT),
255 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT),
256 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP),
257 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0),
258 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1),
259 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2),
260 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3),
261 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK),
262 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE),
263 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE),
264 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR),
265 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0),
266 IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1),
267 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV),
268 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC),
269 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO),
270 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK),
271 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER),
272 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0),
273 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1),
274 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK),
275 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN),
276 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0),
277 IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1),
278 IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT),
279 IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE),
280 IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL),
281 IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA),
282 IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL),
283 IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA),
284 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0),
285 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1),
286 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2),
287 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3),
288 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4),
289 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5),
290 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6),
291 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7),
292 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0),
293 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1),
294 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2),
295 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3),
296 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4),
297 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5),
298 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6),
299 IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7),
300 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK),
301 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0),
302 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1),
303 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10),
304 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11),
305 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12),
306 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13),
307 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14),
308 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15),
309 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16),
310 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17),
311 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18),
312 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19),
313 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2),
314 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20),
315 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21),
316 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22),
317 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23),
318 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3),
319 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4),
320 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5),
321 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6),
322 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7),
323 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8),
324 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9),
325 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE),
326 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC),
327 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET),
328 IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC),
329 IMX_PINCTRL_PIN(MX6SL_PAD_PWM1),
330 IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M),
331 IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K),
332 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK),
333 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD),
334 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0),
335 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1),
336 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2),
337 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3),
338 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4),
339 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5),
340 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6),
341 IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7),
342 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK),
343 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD),
344 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0),
345 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1),
346 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2),
347 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3),
348 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4),
349 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5),
350 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6),
351 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7),
352 IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST),
353 IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK),
354 IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD),
355 IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0),
356 IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1),
357 IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2),
358 IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3),
359 IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD),
360 IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD),
361 IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B),
362};
363
364static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
365 .pins = imx6sl_pinctrl_pads,
366 .npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
367};
368
369static struct of_device_id imx6sl_pinctrl_of_match[] = {
370 { .compatible = "fsl,imx6sl-iomuxc", },
371 { /* sentinel */ }
372};
373
374static int imx6sl_pinctrl_probe(struct platform_device *pdev)
375{
376 return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info);
377}
378
379static struct platform_driver imx6sl_pinctrl_driver = {
380 .driver = {
381 .name = "imx6sl-pinctrl",
382 .owner = THIS_MODULE,
383 .of_match_table = of_match_ptr(imx6sl_pinctrl_of_match),
384 },
385 .probe = imx6sl_pinctrl_probe,
386 .remove = imx_pinctrl_remove,
387};
388
389static int __init imx6sl_pinctrl_init(void)
390{
391 return platform_driver_register(&imx6sl_pinctrl_driver);
392}
393arch_initcall(imx6sl_pinctrl_init);
394
395static void __exit imx6sl_pinctrl_exit(void)
396{
397 platform_driver_unregister(&imx6sl_pinctrl_driver);
398}
399module_exit(imx6sl_pinctrl_exit);
400
401MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
402MODULE_DESCRIPTION("Freescale imx6sl pinctrl driver");
403MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h
new file mode 100644
index 000000000000..e6b1e0a808ae
--- /dev/null
+++ b/include/dt-bindings/gpio/gpio.h
@@ -0,0 +1,15 @@
1/*
2 * This header provides constants for most GPIO bindings.
3 *
4 * Most GPIO bindings include a flags cell as part of the GPIO specifier.
5 * In most cases, the format of the flags cell uses the standard values
6 * defined in this header.
7 */
8
9#ifndef _DT_BINDINGS_GPIO_GPIO_H
10#define _DT_BINDINGS_GPIO_GPIO_H
11
12#define GPIO_ACTIVE_HIGH 0
13#define GPIO_ACTIVE_LOW 1
14
15#endif
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
new file mode 100644
index 000000000000..1ea1b702fec2
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -0,0 +1,22 @@
1/*
2 * This header provides constants for the ARM GIC.
3 */
4
5#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
6#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
7
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/* interrupt specific cell 0 */
11
12#define GIC_SPI 0
13#define GIC_PPI 1
14
15/*
16 * Interrupt specifier cell 2.
17 * The flaggs in irq.h are valid, plus those below.
18 */
19#define GIC_CPU_MASK_RAW(x) ((x) << 8)
20#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
21
22#endif
diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h
new file mode 100644
index 000000000000..33a1003c55aa
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/irq.h
@@ -0,0 +1,19 @@
1/*
2 * This header provides constants for most IRQ bindings.
3 *
4 * Most IRQ bindings include a flags cell as part of the IRQ specifier.
5 * In most cases, the format of the flags cell uses the standard values
6 * defined in this header.
7 */
8
9#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
10#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
11
12#define IRQ_TYPE_NONE 0
13#define IRQ_TYPE_EDGE_RISING 1
14#define IRQ_TYPE_EDGE_FALLING 2
15#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
16#define IRQ_TYPE_LEVEL_HIGH 4
17#define IRQ_TYPE_LEVEL_LOW 8
18
19#endif
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 07125e697d7a..3e73dfd838cd 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -156,9 +156,9 @@ cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \
156 156
157ld_flags = $(LDFLAGS) $(ldflags-y) 157ld_flags = $(LDFLAGS) $(ldflags-y)
158 158
159dtc_cpp_flags = -Wp,-MD,$(depfile) -nostdinc \ 159dtc_cpp_flags = -Wp,-MD,$(depfile).pre -nostdinc \
160 -I$(srctree)/arch/$(SRCARCH)/boot/dts \ 160 -I$(srctree)/arch/$(SRCARCH)/boot/dts \
161 -I$(srctree)/arch/$(SRCARCH)/include/dts \ 161 -I$(srctree)/arch/$(SRCARCH)/boot/dts/include \
162 -undef -D__DTS__ 162 -undef -D__DTS__
163 163
164# Finds the multi-part object the current object will be linked into 164# Finds the multi-part object the current object will be linked into
@@ -269,20 +269,17 @@ $(obj)/%.dtb.S: $(obj)/%.dtb
269 $(call cmd,dt_S_dtb) 269 $(call cmd,dt_S_dtb)
270 270
271quiet_cmd_dtc = DTC $@ 271quiet_cmd_dtc = DTC $@
272cmd_dtc = $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 $(DTC_FLAGS) -d $(depfile) $< 272cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
273 $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \
274 -i $(srctree)/arch/$(SRCARCH)/boot/dts $(DTC_FLAGS) \
275 -d $(depfile).dtc $(dtc-tmp) ; \
276 cat $(depfile).pre $(depfile).dtc > $(depfile)
273 277
274$(obj)/%.dtb: $(src)/%.dts FORCE 278$(obj)/%.dtb: $(src)/%.dts FORCE
275 $(call if_changed_dep,dtc) 279 $(call if_changed_dep,dtc)
276 280
277dtc-tmp = $(subst $(comma),_,$(dot-target).dts) 281dtc-tmp = $(subst $(comma),_,$(dot-target).dts)
278 282
279quiet_cmd_dtc_cpp = DTC+CPP $@
280cmd_dtc_cpp = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
281 $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 $(DTC_FLAGS) $(dtc-tmp)
282
283$(obj)/%.dtb: $(src)/%.dtsp FORCE
284 $(call if_changed_dep,dtc_cpp)
285
286# Bzip2 283# Bzip2
287# --------------------------------------------------------------------------- 284# ---------------------------------------------------------------------------
288 285
diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c
index 7f6425e24ce3..078fe1d64e7d 100644
--- a/scripts/basic/fixdep.c
+++ b/scripts/basic/fixdep.c
@@ -320,49 +320,78 @@ static void parse_dep_file(void *map, size_t len)
320 char *end = m + len; 320 char *end = m + len;
321 char *p; 321 char *p;
322 char s[PATH_MAX]; 322 char s[PATH_MAX];
323 int first; 323 int is_target;
324 324 int saw_any_target = 0;
325 p = strchr(m, ':'); 325 int is_first_dep = 0;
326 if (!p) {
327 fprintf(stderr, "fixdep: parse error\n");
328 exit(1);
329 }
330 memcpy(s, m, p-m); s[p-m] = 0;
331 m = p+1;
332 326
333 clear_config(); 327 clear_config();
334 328
335 first = 1;
336 while (m < end) { 329 while (m < end) {
330 /* Skip any "white space" */
337 while (m < end && (*m == ' ' || *m == '\\' || *m == '\n')) 331 while (m < end && (*m == ' ' || *m == '\\' || *m == '\n'))
338 m++; 332 m++;
333 /* Find next "white space" */
339 p = m; 334 p = m;
340 while (p < end && *p != ' ') p++; 335 while (p < end && *p != ' ' && *p != '\\' && *p != '\n')
341 if (p == end) {
342 do p--; while (!isalnum(*p));
343 p++; 336 p++;
337 /* Is the token we found a target name? */
338 is_target = (*(p-1) == ':');
339 /* Don't write any target names into the dependency file */
340 if (is_target) {
341 /* The /next/ file is the first dependency */
342 is_first_dep = 1;
343 } else {
344 /* Save this token/filename */
345 memcpy(s, m, p-m);
346 s[p - m] = 0;
347
348 /* Ignore certain dependencies */
349 if (strrcmp(s, "include/generated/autoconf.h") &&
350 strrcmp(s, "arch/um/include/uml-config.h") &&
351 strrcmp(s, "include/linux/kconfig.h") &&
352 strrcmp(s, ".ver")) {
353 /*
354 * Do not list the source file as dependency,
355 * so that kbuild is not confused if a .c file
356 * is rewritten into .S or vice versa. Storing
357 * it in source_* is needed for modpost to
358 * compute srcversions.
359 */
360 if (is_first_dep) {
361 /*
362 * If processing the concatenation of
363 * multiple dependency files, only
364 * process the first target name, which
365 * will be the original source name,
366 * and ignore any other target names,
367 * which will be intermediate temporary
368 * files.
369 */
370 if (!saw_any_target) {
371 saw_any_target = 1;
372 printf("source_%s := %s\n\n",
373 target, s);
374 printf("deps_%s := \\\n",
375 target);
376 }
377 is_first_dep = 0;
378 } else
379 printf(" %s \\\n", s);
380 do_config_file(s);
381 }
344 } 382 }
345 memcpy(s, m, p-m); s[p-m] = 0; 383 /*
346 if (strrcmp(s, "include/generated/autoconf.h") && 384 * Start searching for next token immediately after the first
347 strrcmp(s, "arch/um/include/uml-config.h") && 385 * "whitespace" character that follows this token.
348 strrcmp(s, "include/linux/kconfig.h") && 386 */
349 strrcmp(s, ".ver")) {
350 /*
351 * Do not list the source file as dependency, so that
352 * kbuild is not confused if a .c file is rewritten
353 * into .S or vice versa. Storing it in source_* is
354 * needed for modpost to compute srcversions.
355 */
356 if (first) {
357 printf("source_%s := %s\n\n", target, s);
358 printf("deps_%s := \\\n", target);
359 } else
360 printf(" %s \\\n", s);
361 do_config_file(s);
362 }
363 first = 0;
364 m = p + 1; 387 m = p + 1;
365 } 388 }
389
390 if (!saw_any_target) {
391 fprintf(stderr, "fixdep: parse error; no targets found\n");
392 exit(1);
393 }
394
366 printf("\n%s: $(deps_%s)\n\n", target, target); 395 printf("\n%s: $(deps_%s)\n\n", target, target);
367 printf("$(deps_%s):\n", target); 396 printf("$(deps_%s):\n", target);
368} 397}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-07 21:24:13 -0400