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-rw-r--r--arch/arm/boot/dts/armada-370.dtsi58
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index a195debb67d3..18f6eb47cc50 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -159,5 +159,63 @@
159 clocks = <&coreclk 0>; 159 clocks = <&coreclk 0>;
160 }; 160 };
161 161
162 thermal@d0018300 {
163 compatible = "marvell,armada370-thermal";
164 reg = <0xd0018300 0x4
165 0xd0018304 0x4>;
166 status = "okay";
167 };
168
169 pcie-controller {
170 compatible = "marvell,armada-370-pcie";
171 status = "disabled";
172 device_type = "pci";
173
174 #address-cells = <3>;
175 #size-cells = <2>;
176
177 bus-range = <0x00 0xff>;
178
179 reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
180
181 reg-names = "pcie0.0", "pcie1.0";
182
183 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
184 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
185 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
186 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
187
188 pcie@1,0 {
189 device_type = "pci";
190 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
191 reg = <0x0800 0 0 0 0>;
192 #address-cells = <3>;
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 ranges;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 58>;
198 marvell,pcie-port = <0>;
199 marvell,pcie-lane = <0>;
200 clocks = <&gateclk 5>;
201 status = "disabled";
202 };
203
204 pcie@2,0 {
205 device_type = "pci";
206 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
207 reg = <0x1000 0 0 0 0>;
208 #address-cells = <3>;
209 #size-cells = <2>;
210 #interrupt-cells = <1>;
211 ranges;
212 interrupt-map-mask = <0 0 0 0>;
213 interrupt-map = <0 0 0 0 &mpic 62>;
214 marvell,pcie-port = <1>;
215 marvell,pcie-lane = <0>;
216 clocks = <&gateclk 9>;
217 status = "disabled";
218 };
219 };
162 }; 220 };
163}; 221};