1 files changed, 122 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f8f2b787d2b0..885bf229eef7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -96,5 +96,127 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                 };
+
+                /*
+                 * MV78260 has 3 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
         };
 };