Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC multiplatform updates from Olof Johansson: "More multiplatform enablement for ARM platforms. The ones converted in this branch are: - bcm2835 - cns3xxx - sirf - nomadik - msx - spear - tegra - ux500 We're getting close to having most of them converted! One of the larger platforms remaining is Samsung Exynos, and there are a bunch of supporting patches in this merge window for it. There was a patch in this branch to a early version of multiplatform conversion, but it ended up being reverted due to need of more bake time. The revert commit is part of the branch since it would have required rebasing multiple dependent branches and they were stable by then" * tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits) mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms clocksource: nomadik-mtu: fix up clocksource/timer Revert "ARM: exynos: enable multiplatform support" ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ" ARM: exynos: enable multiplatform support rtc: s3c: make header file local mtd: onenand/samsung: make regs-onenand.h file local thermal/exynos: remove unnecessary header inclusions mmc: sdhci-s3c: remove platform dependencies ARM: samsung: move mfc device definition to s5p-dev-mfc.c ARM: exynos: move debug-macro.S to include/debug/ ARM: exynos: prepare for sparse IRQ ARM: exynos: introduce EXYNOS_ATAGS symbol ARM: tegra: build assembly files with -march=armv7-a ARM: Push selects for TWD/SCU into machine entries ARM: ux500: build hotplug.o for ARMv7-a ARM: ux500: move to multiplatform ARM: ux500: make remaining headers local ARM: ux500: make irqs.h local to platform ARM: ux500: get rid of <mach/[hardware|db8500-regs].h> ...
author: Linus Torvalds <torvalds@linux-foundation.org> 2013-05-02 12:38:16 -0400
committer: Linus Torvalds <torvalds@linux-foundation.org> 2013-05-02 12:38:16 -0400
commit: 99c6bcf46d2233d33e441834e958ed0bc22b190a (patch)
tree: 25abf5e856bc0f08d75e623715eb5acc4d4de2b2
parent: 97b1007a2924aaa9126398623f6755a8c3c6a616 (diff)
parent: 2fdfe1c26fb9f24cfdf124384abb35396ca2cd3f (diff)
236 files changed, 1834 insertions, 2887 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf11bf5427da..4ed24b4aa714 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -362,37 +362,6 @@ config ARCH_AT91
          This enables support for systems based on Atmel
          AT91RM9200 and AT91SAM9* processors.
-config ARCH_BCM2835
-        bool "Broadcom BCM2835 family"
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select ARM_ERRATA_411920
-        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select CLKSRC_OF
-        select COMMON_CLK
-        select CPU_V6
-        select GENERIC_CLOCKEVENTS
-        select MULTI_IRQ_HANDLER
-        select PINCTRL
-        select PINCTRL_BCM2835
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          This enables support for the Broadcom BCM2835 SoC. This SoC is
-          use in the Raspberry Pi, and Roku 2 devices.
-config ARCH_CNS3XXX
-        bool "Cavium Networks CNS3XXX family"
-        select ARM_GIC
-        select CPU_V6K
-        select GENERIC_CLOCKEVENTS
-        select MIGHT_HAVE_CACHE_L2X0
-        select MIGHT_HAVE_PCI
-        select PCI_DOMAINS if PCI
-        help
-          Support for Cavium Networks CNS3XXX platform.
 config ARCH_CLPS711X
        bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
        select ARCH_REQUIRE_GPIOLIB
@@ -416,21 +385,6 @@ config ARCH_GEMINI
        help
          Support for the Cortina Systems Gemini family SoCs
-config ARCH_SIRF
-        bool "CSR SiRF"
-        select ARCH_REQUIRE_GPIOLIB
-        select AUTO_ZRELADDR
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_IRQ_CHIP
-        select MIGHT_HAVE_CACHE_L2X0
-        select NO_IOPORT
-        select PINCTRL
-        select PINCTRL_SIRF
-        select USE_OF
-        help
-          Support for CSR SiRFprimaII/Marco/Polo platforms
 config ARCH_EBSA110
        bool "EBSA-110"
        select ARCH_USES_GETTIMEOFFSET
@@ -470,23 +424,6 @@ config ARCH_FOOTBRIDGE
          Support for systems based on the DC21285 companion chip
          ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
-config ARCH_MXS
-        bool "Freescale MXS-based"
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK_PREPARE
-        select MULTI_IRQ_HANDLER
-        select PINCTRL
-        select SPARSE_IRQ
-        select STMP_DEVICE
-        select USE_OF
-        help
-          Support for Freescale MXS-based family of processors
 config ARCH_NETX
        bool "Hilscher NetX based"
        select ARM_VIC
@@ -659,25 +596,6 @@ config ARCH_LPC32XX
        help
          Support for the NXP LPC32XX family of processors
-config ARCH_TEGRA
-        bool "NVIDIA Tegra"
-        select ARCH_HAS_CPUFREQ
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-        select SOC_BUS
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          This enables support for NVIDIA Tegra based systems (Tegra APX,
-          Tegra 6xx and Tegra 2 series).
 config ARCH_PXA
        bool "PXA2xx/PXA3xx-based"
        depends on MMU
@@ -715,6 +633,8 @@ config ARCH_SHMOBILE
        bool "Renesas SH-Mobile / R-Mobile"
        select CLKDEV_LOOKUP
        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_CLK
        select HAVE_MACH_CLKDEV
        select HAVE_SMP
@@ -900,51 +820,6 @@ config ARCH_U300
        help
          Support for ST-Ericsson U300 series mobile platforms.
-config ARCH_U8500
-        bool "ST-Ericsson U8500 Series"
-        depends on MMU
-        select ARCH_HAS_CPUFREQ
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select CLKDEV_LOOKUP
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-        select SPARSE_IRQ
-        help
-          Support for ST-Ericsson's Ux500 architecture
-config ARCH_NOMADIK
-        bool "STMicroelectronics Nomadik"
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select ARM_VIC
-        select CLKSRC_NOMADIK_MTU
-        select COMMON_CLK
-        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
-        select MIGHT_HAVE_CACHE_L2X0
-        select USE_OF
-        select PINCTRL
-        select PINCTRL_STN8815
-        select SPARSE_IRQ
-        help
-          Support for the Nomadik platform by ST-Ericsson
-config PLAT_SPEAR
-        bool "ST SPEAr"
-        select ARCH_HAS_CPUFREQ
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
-        help
-          Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 config ARCH_DAVINCI
        bool "TI DaVinci"
        select ARCH_HAS_HOLES_MEMORYMODEL
@@ -1036,6 +911,8 @@ source "arch/arm/mach-at91/Kconfig"
 source "arch/arm/mach-bcm/Kconfig"
+source "arch/arm/mach-bcm2835/Kconfig"
 source "arch/arm/mach-clps711x/Kconfig"
 source "arch/arm/mach-cns3xxx/Kconfig"
@@ -1101,7 +978,7 @@ source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/mach-socfpga/Kconfig"
-source "arch/arm/plat-spear/Kconfig"
+source "arch/arm/mach-spear/Kconfig"
 source "arch/arm/mach-s3c24xx/Kconfig"
@@ -1528,7 +1405,6 @@ config SMP
        depends on GENERIC_CLOCKEVENTS
        depends on HAVE_SMP
        depends on MMU
-        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
        select USE_GENERIC_SMP_HELPERS
        help
          This enables support for systems with more than one CPU. If you have
@@ -1653,7 +1529,6 @@ config LOCAL_TIMERS
        bool "Use local timer interrupts"
        depends on SMP
        default y
-        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
        help
          Enable support for local timers on SMP platforms, rather then the
          legacy IPI broadcast method.  Local timers allows the system
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9b31f4311ea2..54d6fdc03e04 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -89,6 +89,10 @@ choice
                bool "Kernel low-level debugging on 9263 and 9g45"
                depends on HAVE_AT91_DBGU1
+        config DEBUG_BCM2835
+                bool "Kernel low-level debugging on BCM2835 PL011 UART"
+                depends on ARCH_BCM2835
        config DEBUG_CLPS711X_UART1
                bool "Kernel low-level debugging messages via UART1"
                depends on ARCH_CLPS711X
@@ -103,6 +107,13 @@ choice
                  Say Y here if you want the debug print routines to direct
                  their output to the second serial port on these devices.
+        config DEBUG_CNS3XXX
+                bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx"
+                depends on ARCH_CNS3XXX
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the CNS3xxx UART0.
        config DEBUG_DAVINCI_DA8XX_UART1
                bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
                depends on ARCH_DAVINCI_DA8XX
@@ -298,6 +309,13 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on MVEBU based platforms.
+        config DEBUG_NOMADIK_UART
+                bool "Kernel low-level debugging messages via NOMADIK UART"
+                depends on ARCH_NOMADIK
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on NOMADIK based platforms.
        config DEBUG_OMAP2PLUS_UART
                bool "Kernel low-level debugging messages via OMAP2PLUS UART"
                depends on ARCH_OMAP2PLUS
@@ -330,6 +348,7 @@ choice
        config DEBUG_S3C_UART0
                depends on PLAT_SAMSUNG
+                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                bool "Use S3C UART 0 for low-level debug"
                help
                  Say Y here if you want the debug print routines to direct
@@ -341,6 +360,7 @@ choice
        config DEBUG_S3C_UART1
                depends on PLAT_SAMSUNG
+                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                bool "Use S3C UART 1 for low-level debug"
                help
                  Say Y here if you want the debug print routines to direct
@@ -352,6 +372,7 @@ choice
        config DEBUG_S3C_UART2
                depends on PLAT_SAMSUNG
+                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                bool "Use S3C UART 2 for low-level debug"
                help
                  Say Y here if you want the debug print routines to direct
@@ -363,6 +384,7 @@ choice
        config DEBUG_S3C_UART3
                depends on PLAT_SAMSUNG && ARCH_EXYNOS
+                select DEBUG_EXYNOS_UART
                bool "Use S3C UART 3 for low-level debug"
                help
                  Say Y here if you want the debug print routines to direct
@@ -414,6 +436,13 @@ choice
                  Say Y here if you want the debug print routines to direct
                  their output to the uart1 port on SiRFmarco devices.
+        config DEBUG_UX500_UART
+                depends on ARCH_U8500
+                bool "Use Ux500 UART for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Ux500 based platforms.
        config DEBUG_VEXPRESS_UART0_DETECT
                bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -485,6 +514,9 @@ choice
 endchoice
+config DEBUG_EXYNOS_UART
+        bool
 config DEBUG_IMX_UART_PORT
        int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
                                                DEBUG_IMX25_UART || \
@@ -580,6 +612,9 @@ endchoice
 config DEBUG_LL_INCLUDE
        string
+        default "debug/bcm2835.S" if DEBUG_BCM2835
+        default "debug/cns3xxx.S" if DEBUG_CNS3XXX
+        default "debug/exynos.S" if DEBUG_EXYNOS_UART
        default "debug/icedcc.S" if DEBUG_ICEDCC
        default "debug/imx.S" if DEBUG_IMX1_UART || \
                                 DEBUG_IMX25_UART || \
@@ -591,14 +626,18 @@ config DEBUG_LL_INCLUDE
                                 DEBUG_IMX6Q_UART
        default "debug/highbank.S" if DEBUG_HIGHBANK_UART
        default "debug/mvebu.S" if DEBUG_MVEBU_UART
+        default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
+        default "debug/nomadik.S" if DEBUG_NOMADIK_UART
        default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
        default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
+        default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
        default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
        default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
        default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
        default "debug/vt8500.S" if DEBUG_VT8500_UART0
        default "debug/tegra.S" if DEBUG_TEGRA_UART
+        default "debug/ux500.S" if DEBUG_UX500_UART
        default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
        default "mach/debug-macro.S"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e4d1d23916b0..47374085befd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,9 +190,7 @@ machine-$(CONFIG_ARCH_VT8500)		+= vt8500
 machine-$(CONFIG_ARCH_W90X900)          += w90x900
 machine-$(CONFIG_FOOTBRIDGE)            += footbridge
 machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
-machine-$(CONFIG_ARCH_SPEAR13XX)        += spear13xx
+machine-$(CONFIG_PLAT_SPEAR)            += spear
-machine-$(CONFIG_ARCH_SPEAR3XX)         += spear3xx
-machine-$(CONFIG_MACH_SPEAR600)         += spear6xx
 machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
 machine-$(CONFIG_ARCH_SUNXI)            += sunxi
@@ -206,7 +204,6 @@ plat-$(CONFIG_PLAT_ORION)	+= orion
 plat-$(CONFIG_PLAT_PXA)         += pxa
 plat-$(CONFIG_PLAT_S3C24XX)     += samsung
 plat-$(CONFIG_PLAT_S5P)         += samsung
-plat-$(CONFIG_PLAT_SPEAR)       += spear
 plat-$(CONFIG_PLAT_VERSATILE)   += versatile
 ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index abc7c8d4631b..ce987211a609 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -29,6 +29,8 @@ CONFIG_EMBEDDED=y
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_JUMP_LABEL=y
+CONFIG_ARCH_MULTI_V6=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_BCM2835=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
index 313627adf46c..b1ff5cdba9a1 100644
--- a/arch/arm/configs/cns3420vb_defconfig
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -19,8 +19,11 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_IOSCHED_CFQ=m
+CONFIG_ARCH_MULTI_V6=y
+#CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_CNS3XXX=y
 CONFIG_MACH_CNS3420VB=y
+CONFIG_DEBUG_CNS3XXX=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e31d442343c8..2e67a272df70 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -3,13 +3,19 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
+CONFIG_ARCH_SIRF=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_WM8850=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 CONFIG_ARCH_ZYNQ=y
 CONFIG_ARM_ERRATA_754322=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_MACH_SPEAR1310=y
+CONFIG_MACH_SPEAR1340=y
 CONFIG_SMP=y
 CONFIG_ARM_ARCH_TIMER=y
 CONFIG_AEABI=y
@@ -23,6 +29,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
+CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_CALXEDA_XGMAC=y
 CONFIG_SMSC911X=y
@@ -31,17 +38,26 @@ CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
+CONFIG_KEYBOARD_SPEAR=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SIRFSOC=y
+CONFIG_SERIAL_SIRFSOC_CONSOLE=y
+CONFIG_SERIAL_VT8500=y
+CONFIG_SERIAL_VT8500_CONSOLE=y
 CONFIG_IPMI_HANDLER=y
 CONFIG_IPMI_SI=y
 CONFIG_I2C=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_SIRF=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
+CONFIG_SPI_SIRF=y
+CONFIG_GPIO_PL061=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
+CONFIG_FB_WM8505=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_USB=y
 CONFIG_USB_ISP1760_HCD=y
@@ -50,11 +66,18 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_MMC_WMT=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_HIGHBANK_MC=y
 CONFIG_EDAC_HIGHBANK_L2=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_DRV_VT8500=y
+CONFIG_PWM=y
+CONFIG_PWM_VT8500=y
 CONFIG_DMADEVICES=y
 CONFIG_PL330_DMA=y
+CONFIG_SIRF_DMA=y
+CONFIG_DW_DMAC=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 7ba48d22bcd9..1d6d8fb7f4a1 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -22,8 +22,8 @@ CONFIG_MODVERSIONS=y
 CONFIG_BLK_DEV_INTEGRITY=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_MXS=y
-CONFIG_MACH_MXS_DT=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 86cfd2959c47..b01e7632ed2e 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -1,11 +1,9 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
@@ -13,6 +11,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_NOMADIK=y
 CONFIG_MACH_NOMADIK_8815NHK=y
 CONFIG_PREEMPT=y
@@ -20,7 +19,6 @@ CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -32,14 +30,10 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_NET_IPIP=y
-CONFIG_NET_IPGRE=y
-CONFIG_NET_IPGRE_BROADCAST=y
 CONFIG_IP_MROUTE=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
 CONFIG_BT_RFCOMM=m
 CONFIG_BT_RFCOMM_TTY=y
 CONFIG_BT_BNEP=m
@@ -53,14 +47,16 @@ CONFIG_BT_HCIVHCI=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_TESTS=m
+CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC_SMC=y
+CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_FSMC=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_GENERIC=y
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
@@ -72,47 +68,48 @@ CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_NETDEVICES=y
+CONFIG_NETCONSOLE=m
 CONFIG_TUN=y
-CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
 CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
-CONFIG_NETCONSOLE=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM_NOMADIK=y
-CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
+CONFIG_I2C_NOMADIK=y
 CONFIG_DEBUG_GPIO=y
-CONFIG_PINCTRL_NOMADIK=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_MMC=y
+CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
 CONFIG_FUSE_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_ROOT_NFS=y
-CONFIG_SMB_FS=m
 CONFIG_CIFS=m
 CONFIG_CIFS_WEAK_PW_HASH=y
 CONFIG_NLS_CODEPAGE_437=y
@@ -120,12 +117,11 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 # CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_DES=y
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index 865980c5f212..7ff23a077f5d 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -6,7 +6,9 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR3XX=y
 CONFIG_MACH_SPEAR300=y
 CONFIG_MACH_SPEAR310=y
 CONFIG_MACH_SPEAR320=y
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index a2a1265f86b6..7822980d7d55 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -6,6 +6,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
 CONFIG_BINFMT_MISC=y
diff --git a/arch/arm/mach-bcm2835/include/mach/debug-macro.S b/arch/arm/include/debug/bcm2835.S
index 8a161e44ae28..aed9199bd847 100644
--- a/arch/arm/mach-bcm2835/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/bcm2835.S
@@ -11,7 +11,8 @@
 *
 */
-#include <mach/bcm2835_soc.h>
+#define BCM2835_DEBUG_PHYS 0x20201000
+#define BCM2835_DEBUG_VIRT 0xf0201000
        .macro  addruart, rp, rv, tmp
        ldr     \rp, =BCM2835_DEBUG_PHYS
diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/include/debug/cns3xxx.S
index d04c150baa1c..d04c150baa1c 100644
--- a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/cns3xxx.S
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/include/debug/exynos.S
index e0c86ea475e7..b17fdb7fbd34 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/exynos.S
@@ -1,10 +1,7 @@
-/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
+/*
- *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
- * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
- *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
@@ -12,7 +9,10 @@
 /* pull in the relevant register and map files. */
-#include <mach/map.h>
+#define S3C_ADDR_BASE   0xF6000000
+#define S3C_VA_UART     S3C_ADDR_BASE + 0x01000000
+#define EXYNOS4_PA_UART 0x13800000
+#define EXYNOS5_PA_UART 0x12C00000
        /* note, for the boot process to work we have to keep the UART
         * virtual address aligned to an 1MiB boundary for the L1
@@ -36,4 +36,4 @@
 #define fifo_full fifo_full_s5pv210
 #define fifo_level fifo_level_s5pv210
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/include/debug/mxs.S
index d86951551ca1..d86951551ca1 100644
--- a/arch/arm/mach-mxs/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/mxs.S
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/include/debug/nomadik.S
index 735417922ce2..735417922ce2 100644
--- a/arch/arm/mach-nomadik/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/nomadik.S
diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/include/debug/samsung.S
index f3a9cff6d5d4..f3a9cff6d5d4 100644
--- a/arch/arm/plat-samsung/include/plat/debug-macro.S
+++ b/arch/arm/include/debug/samsung.S
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/include/debug/sirf.S
index c10510d01a44..dbf250cf18e6 100644
--- a/arch/arm/mach-prima2/include/mach/uart.h
+++ b/arch/arm/include/debug/sirf.S
@@ -1,15 +1,11 @@
 /*
- * arch/arm/mach-prima2/include/mach/uart.h
+ * arch/arm/mach-prima2/include/mach/debug-macro.S
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */
-#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
-#define __MACH_PRIMA2_SIRFSOC_UART_H
-/* UART-1: used as serial debug port */
 #if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
 #define SIRFSOC_UART1_PA_BASE          0xb0060000
 #elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
@@ -17,8 +13,8 @@
 #else
 #define SIRFSOC_UART1_PA_BASE          0
 #endif
-#define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
-#define SIRFSOC_UART1_SIZE              SZ_4K
+#define SIRFSOC_UART1_VA_BASE           0xFEC60000
 #define SIRFSOC_UART_TXFIFO_STATUS      0x0114
 #define SIRFSOC_UART_TXFIFO_DATA        0x0118
@@ -26,4 +22,21 @@
 #define SIRFSOC_UART1_TXFIFO_FULL                       (1 << 5)
 #define SIRFSOC_UART1_TXFIFO_EMPTY                      (1 << 6)
-#endif
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =SIRFSOC_UART1_PA_BASE             @ physical
+        ldr     \rv, =SIRFSOC_UART1_VA_BASE             @ virtual
+        .endm
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
+        .endm
+        .macro  busyuart,rd,rx
+        .endm
+        .macro  waituart,rd,rx
+1001:   ldr     \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
+        tst     \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
+        beq     1001b
+        .endm
diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S
new file mode 100644
index 000000000000..2848857f5b62
--- /dev/null
+++ b/arch/arm/include/debug/ux500.S
@@ -0,0 +1,48 @@
+/*
+ * Debugging macro include header
+ *
+ *  Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#if CONFIG_UX500_DEBUG_UART > 2
+#error Invalid Ux500 debug UART
+#endif
+/*
+ * DEBUG_LL only works if only one SOC is built in.  We don't use #else below
+ * in order to get "__UX500_UART redefined" warnings if more than one SOC is
+ * built, so that there's some hint during the build that something is wrong.
+ */
+#ifdef CONFIG_UX500_SOC_DB8500
+#define U8500_UART0_PHYS_BASE   (0x80120000)
+#define U8500_UART1_PHYS_BASE   (0x80121000)
+#define U8500_UART2_PHYS_BASE   (0x80007000)
+#define U8500_UART0_VIRT_BASE   (0xa8120000)
+#define U8500_UART1_VIRT_BASE   (0xa8121000)
+#define U8500_UART2_VIRT_BASE   (0xa8007000)
+#define __UX500_PHYS_UART(n)    U8500_UART##n##_PHYS_BASE
+#define __UX500_VIRT_UART(n)    U8500_UART##n##_VIRT_BASE
+#endif
+#if !defined(__UX500_PHYS_UART) || !defined(__UX500_VIRT_UART)
+#error Unknown SOC
+#endif
+#define UX500_PHYS_UART(n)      __UX500_PHYS_UART(n)
+#define UX500_VIRT_UART(n)      __UX500_VIRT_UART(n)
+#define UART_PHYS_BASE  UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART)
+#define UART_VIRT_BASE  UX500_VIRT_UART(CONFIG_UX500_DEBUG_UART)
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =UART_PHYS_BASE            @ no, physical address
+        ldr     \rv, =UART_VIRT_BASE            @ yes, virtual address
+        .endm
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
new file mode 100644
index 000000000000..560045cafc34
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_BCM2835
+        bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_ERRATA_411920
+        select ARM_TIMER_SP804
+        select CLKDEV_LOOKUP
+        select CLKSRC_OF
+        select CPU_V6
+        select GENERIC_CLOCKEVENTS
+        select PINCTRL
+        select PINCTRL_BCM2835
+        help
+          This enables support for the Broadcom BCM2835 SoC. This SoC is
+          use in the Raspberry Pi, and Roku 2 devices.
diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot
deleted file mode 100644
index b3271754e9fd..000000000000
--- a/arch/arm/mach-bcm2835/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 6f5785985dd1..740fa9ebe249 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -23,8 +23,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/bcm2835_soc.h>
 #define PM_RSTC                         0x1c
 #define PM_RSTS                         0x20
 #define PM_WDOG                         0x24
@@ -34,6 +32,10 @@
 #define PM_RSTC_WRCFG_FULL_RESET        0x00000020
 #define PM_RSTS_HADWRH_SET              0x00000040
+#define BCM2835_PERIPH_PHYS     0x20000000
+#define BCM2835_PERIPH_VIRT     0xf0000000
+#define BCM2835_PERIPH_SIZE     SZ_16M
 static void __iomem *wdt_regs;
 /*
diff --git a/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
deleted file mode 100644
index d4dfcf7a9cda..000000000000
--- a/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2012 Stephen Warren
- *
- * Derived from code:
- * Copyright (C) 2010 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_BCM2835_BCM2835_SOC_H__
-#define __MACH_BCM2835_BCM2835_SOC_H__
-#include <asm/sizes.h>
-#define BCM2835_PERIPH_PHYS     0x20000000
-#define BCM2835_PERIPH_VIRT     0xf0000000
-#define BCM2835_PERIPH_SIZE     SZ_16M
-#define BCM2835_DEBUG_PHYS      0x20201000
-#define BCM2835_DEBUG_VIRT      0xf0201000
-#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/gpio.h b/arch/arm/mach-bcm2835/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-bcm2835/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-bcm2835/include/mach/timex.h b/arch/arm/mach-bcm2835/include/mach/timex.h
deleted file mode 100644
index 6d021e136ae3..000000000000
--- a/arch/arm/mach-bcm2835/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  BCM2835 system clock frequency
- *
- *  Copyright (C) 2010 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-#define CLOCK_TICK_RATE         (1000000)
-#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h
deleted file mode 100644
index bf86dca3bf71..000000000000
--- a/arch/arm/mach-bcm2835/include/mach/uncompress.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2010 Broadcom
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/io.h>
-#include <linux/amba/serial.h>
-#include <mach/bcm2835_soc.h>
-#define UART0_BASE BCM2835_DEBUG_PHYS
-#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR)
-#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR)
-#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR)
-static inline void putc(int c)
-{
-        while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF)
-                barrier();
-        __raw_writel(c, BCM2835_UART_DR);
-}
-static inline void flush(void)
-{
-        int fr;
-        do {
-                fr = __raw_readl(BCM2835_UART_FR);
-                barrier();
-        } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
-}
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 9ebfcc46feb1..dbf0df8bb0ac 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,8 +1,20 @@
+config ARCH_CNS3XXX
+        bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
+        select ARM_GIC
+        select CPU_V6K
+        select GENERIC_CLOCKEVENTS
+        select MIGHT_HAVE_CACHE_L2X0
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
+        help
+          Support for Cavium Networks CNS3XXX platform.
 menu "CNS3XXX platform type"
        depends on ARCH_CNS3XXX
 config MACH_CNS3420VB
        bool "Support for CNS3420 Validation Board"
+        depends on ATAGS
        help
          Include support for the Cavium Networks CNS3420 MPCore Platform
          Baseboard.
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 11033f1c2e23..a1ff10848698 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,3 +1,5 @@
-obj-$(CONFIG_ARCH_CNS3XXX)              += core.o pm.o devices.o
+obj-$(CONFIG_ARCH_CNS3XXX)              += cns3xxx.o
-obj-$(CONFIG_PCI)                       += pcie.o
+cns3xxx-y                               += core.o pm.o
-obj-$(CONFIG_MACH_CNS3420VB)            += cns3420vb.o
+cns3xxx-$(CONFIG_ATAGS)                 += devices.o
+cns3xxx-$(CONFIG_PCI)                   += pcie.o
+cns3xxx-$(CONFIG_MACH_CNS3420VB)        += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index a71867e1d8d6..ce096d678aa4 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -31,9 +31,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
-#include <mach/irqs.h>
+#include "pm.h"
-#include <mach/pm.h>
 #include "core.h"
 #include "devices.h"
@@ -247,6 +246,7 @@ static void __init cns3420_map_io(void)
 MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
        .atag_offset    = 0x100,
+        .nr_irqs        = NR_IRQS_CNS3XXX,
        .map_io         = cns3420_map_io,
        .init_irq       = cns3xxx_init_irq,
        .init_time      = cns3xxx_timer_init,
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h
index 9b145b1e48ea..a0f5b60662ae 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
@@ -526,6 +526,8 @@ int cns3xxx_cpu_clock(void);
 /*
 * ARM11 MPCore interrupt sources (primary GIC)
 */
+#define IRQ_TC11MP_GIC_START    32
 #define IRQ_CNS3XXX_PMU                 (IRQ_TC11MP_GIC_START + 0)
 #define IRQ_CNS3XXX_SDIO                (IRQ_TC11MP_GIC_START + 1)
 #define IRQ_CNS3XXX_L2CC                (IRQ_TC11MP_GIC_START + 2)
@@ -597,9 +599,4 @@ int cns3xxx_cpu_clock(void);
 #define NR_IRQS_CNS3XXX                 (IRQ_TC11MP_GIC_START + 64)
-#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
-#undef NR_IRQS
-#define NR_IRQS                         NR_IRQS_CNS3XXX
-#endif
 #endif  /* __MACH_BOARD_CNS3XXX_H */
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 126f74f6087c..e38b279f402c 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -13,12 +13,18 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
 #include "core.h"
+#include "pm.h"
 static struct map_desc cns3xxx_io_desc[] __initdata = {
        {
@@ -256,3 +262,116 @@ void __init cns3xxx_l2x0_init(void)
 }
 #endif /* CONFIG_CACHE_L2X0 */
+static int csn3xxx_usb_power_on(struct platform_device *pdev)
+{
+        /*
+         * EHCI and OHCI share the same clock and power,
+         * resetting twice would cause the 1st controller been reset.
+         * Therefore only do power up  at the first up device, and
+         * power down at the last down device.
+         *
+         * Set USB AHB INCR length to 16
+         */
+        if (atomic_inc_return(&usb_pwr_ref) == 1) {
+                cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
+                cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
+                cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
+                __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
+                        MISC_CHIP_CONFIG_REG);
+        }
+        return 0;
+}
+static void csn3xxx_usb_power_off(struct platform_device *pdev)
+{
+        /*
+         * EHCI and OHCI share the same clock and power,
+         * resetting twice would cause the 1st controller been reset.
+         * Therefore only do power up  at the first up device, and
+         * power down at the last down device.
+         */
+        if (atomic_dec_return(&usb_pwr_ref) == 0)
+                cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
+}
+static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
+        .power_on       = csn3xxx_usb_power_on,
+        .power_off      = csn3xxx_usb_power_off,
+};
+static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
+        .num_ports      = 1,
+        .power_on       = csn3xxx_usb_power_on,
+        .power_off      = csn3xxx_usb_power_off,
+};
+static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
+        { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
+        { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
+        { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
+        { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
+        {},
+};
+static void __init cns3xxx_init(void)
+{
+        struct device_node *dn;
+        cns3xxx_l2x0_init();
+        dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
+        if (of_device_is_available(dn)) {
+                u32 tmp;
+        
+                tmp = __raw_readl(MISC_SATA_POWER_MODE);
+                tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+                tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+                __raw_writel(tmp, MISC_SATA_POWER_MODE);
+        
+                /* Enable SATA PHY */
+                cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+                cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+        
+                /* Enable SATA Clock */
+                cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+        
+                /* De-Asscer SATA Reset */
+                cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
+        }
+        dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
+        if (of_device_is_available(dn)) {
+                u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+                u32 gpioa_pins = __raw_readl(gpioa);
+        
+                /* MMC/SD pins share with GPIOA */
+                gpioa_pins |= 0x1fff0004;
+                __raw_writel(gpioa_pins, gpioa);
+        
+                cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+                cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+        }
+        pm_power_off = cns3xxx_power_off;
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        cns3xxx_auxdata, NULL);
+}
+static const char *cns3xxx_dt_compat[] __initdata = {
+        "cavium,cns3410",
+        "cavium,cns3420",
+        NULL,
+};
+DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
+        .dt_compat      = cns3xxx_dt_compat,
+        .nr_irqs        = NR_IRQS_CNS3XXX,
+        .map_io         = cns3xxx_map_io,
+        .init_irq       = cns3xxx_init_irq,
+        .init_time      = cns3xxx_timer_init,
+        .init_machine   = cns3xxx_init,
+        .restart        = cns3xxx_restart,
+MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 1e40c99b015f..7da78a2451f1 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -16,9 +16,8 @@
 #include <linux/compiler.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
-#include <mach/irqs.h>
+#include "pm.h"
-#include <mach/pm.h>
 #include "core.h"
 #include "devices.h"
diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h
deleted file mode 100644
index 2ab96f8085c8..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/irqs.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2000 Deep Blue Solutions Ltd.
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-#define IRQ_LOCALTIMER          29
-#define IRQ_LOCALWDOG           30
-#define IRQ_TC11MP_GIC_START    32
-#include <mach/cns3xxx.h>
-#ifndef NR_IRQS
-#error "NR_IRQS not defined by the board-specific files"
-#endif
-#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h
deleted file mode 100644
index 1fd04217cacb..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/timex.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Cavium Networks architecture timex specifications
- *
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
deleted file mode 100644
index 7a030b99df84..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-#include <asm/mach-types.h>
-#include <mach/cns3xxx.h>
-#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
-#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
-#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
-#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
-/*
- * Return the UART base address
- */
-static inline unsigned long get_uart_base(void)
-{
-        if (machine_is_cns3420vb())
-                return CNS3XXX_UART0_BASE;
-        else
-                return 0;
-}
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        unsigned long base = get_uart_base();
-        while (AMBA_UART_FR(base) & (1 << 5))
-                barrier();
-        AMBA_UART_DR(base) = c;
-}
-static inline void flush(void)
-{
-        unsigned long base = get_uart_base();
-        while (AMBA_UART_FR(base) & (1 << 3))
-                barrier();
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 311328314163..c7b204bff386 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -20,7 +20,7 @@
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
 #include <asm/mach/map.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
 #include "core.h"
 enum cns3xxx_access_type {
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 36458080332a..79e3d47aad65 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -11,8 +11,8 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/atomic.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
-#include <mach/pm.h>
+#include "pm.h"
 #include "core.h"
 void cns3xxx_pwr_clk_en(unsigned int block)
diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/pm.h
index c2588cc991d1..c2588cc991d1 100644
--- a/arch/arm/mach-cns3xxx/include/mach/pm.h
+++ b/arch/arm/mach-cns3xxx/pm.h
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 42378fb90167..f22f69e2d081 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -14,6 +14,7 @@ menu "SAMSUNG EXYNOS SoCs Support"
 config ARCH_EXYNOS4
        bool "SAMSUNG EXYNOS4"
        default y
+        select HAVE_ARM_SCU if SMP
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        help
@@ -21,6 +22,7 @@ config ARCH_EXYNOS4
 config ARCH_EXYNOS5
        bool "SAMSUNG EXYNOS5"
+        select HAVE_ARM_SCU if SMP
        select HAVE_SMP
        help
          Samsung EXYNOS5 (Cortex-A15) SoC based systems
@@ -87,6 +89,19 @@ config EXYNOS4_MCT
        help
          Use MCT (Multi Core Timer) as kernel timers
+config EXYNOS_ATAGS
+        bool "ATAGS based boot for EXYNOS (deprecated)"
+        depends on !ARCH_MULTIPLATFORM
+        depends on ATAGS
+        default y
+        help
+          The EXYNOS platform is moving towards being completely probed
+          through device tree. This enables support for board files using
+          the traditional ATAGS boot format.
+          Note that this option is not available for multiplatform builds.
+if EXYNOS_ATAGS
 config EXYNOS_DEV_DMA
        bool
        help
@@ -391,6 +406,8 @@ config MACH_SMDK4412
          Machine support for Samsung SMDK4412
 endif
+endif
 comment "Flattened Device Tree based board for EXYNOS SoCs"
 config MACH_EXYNOS4_DT
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
index 7c42f4b7c8be..c48aff02c786 100644
--- a/arch/arm/mach-exynos/dev-uart.c
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -20,6 +20,7 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1f4dc35cd4b9..8bd5dde5fc78 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -466,7 +466,10 @@
 #define IRQ_TIMER_BASE                  (IRQ_GPIO_END + 64)
 /* Set the default NR_IRQS */
+#define EXYNOS_NR_IRQS                  (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
-#define NR_IRQS                         (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+#ifndef CONFIG_SPARSE_IRQ
+#define NR_IRQS                         EXYNOS_NR_IRQS
+#endif
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 685f29173afa..2126f3503a3f 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -25,6 +25,7 @@
 #include <plat/regs-srom.h>
 #include <plat/sdhci.h>
+#include <mach/irqs.h>
 #include <mach/map.h>
 #include "common.h"
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 1ea79730187f..ab920e34bd0a 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -53,6 +53,7 @@
 #include <plat/fimc-core.h>
 #include <plat/camport.h>
+#include <mach/irqs.h>
 #include <mach/map.h>
 #include "common.h"
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index bf946931ab32..ec42024dd13f 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -46,6 +46,7 @@
 #include <plat/hdmi.h>
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <drm/exynos_drm.h>
 #include "common.h"
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fe6149624b84..5df91236dbb4 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -39,6 +39,7 @@
 #include <plat/regs-serial.h>
 #include <plat/sdhci.h>
+#include <mach/irqs.h>
 #include <mach/map.h>
 #include <drm/exynos_drm.h>
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 8270929d7b44..9680e1291065 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/hdmi.h>
+#include <mach/irqs.h>
 #include <mach/map.h>
 #include <drm/exynos_drm.h>
diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
index e8d08bf8965a..d5b98c866738 100644
--- a/arch/arm/mach-exynos/setup-sdhci-gpio.c
+++ b/arch/arm/mach-exynos/setup-sdhci-gpio.c
@@ -19,8 +19,8 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
+#include <mach/gpio.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
 void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 44b12f9c1584..cd9fcb1cd7ab 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -12,6 +12,7 @@ config ARCH_HIGHBANK
        select CPU_V7
        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_SMP
        select MAILBOX
        select PL320_MBOX
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 91571a16f986..d58ad4ff8d34 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -795,7 +795,8 @@ config SOC_IMX6Q
        select ARM_GIC
        select COMMON_CLK
        select CPU_V7
-        select HAVE_ARM_SCU
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_CAN_FLEXCAN if CAN
        select HAVE_IMX_GPC
        select HAVE_IMX_MMDC
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index b61908594b47..fceb093b9494 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -44,10 +44,10 @@ endchoice
 config ARCH_MSM8X60
        bool "MSM8X60"
-        select ARCH_MSM_SCORPIONMP
        select ARM_GIC
        select CPU_V7
        select GPIO_MSM_V2
+        select HAVE_SMP
        select MSM_GPIOMUX
        select MSM_SCM if SMP
        select MSM_V2_TLMM
@@ -55,9 +55,9 @@ config ARCH_MSM8X60
 config ARCH_MSM8960
        bool "MSM8960"
-        select ARCH_MSM_SCORPIONMP
        select ARM_GIC
        select CPU_V7
+        select HAVE_SMP
        select MSM_GPIOMUX
        select MSM_SCM if SMP
        select MSM_V2_TLMM
@@ -68,9 +68,6 @@ config MSM_HAS_DEBUG_UART_HS
 config MSM_SOC_REV_A
        bool
-config  ARCH_MSM_SCORPIONMP
-        bool
-        select HAVE_SMP
 config  ARCH_MSM_ARM11
        bool
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c4495a13751a..4dc2fbba0ecd 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -1,5 +1,3 @@
-if ARCH_MXS
 config SOC_IMX23
        bool
        select ARM_AMBA
@@ -17,14 +15,18 @@ config SOC_IMX28
        select HAVE_PWM
        select PINCTRL_IMX28
-comment "MXS platforms:"
+config ARCH_MXS
+        bool "Freescale MXS (i.MX23, i.MX28) support"
-config MACH_MXS_DT
+        depends on ARCH_MULTI_V5
-        bool "Support MXS platforms from device tree"
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select CLKSRC_OF
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK_PREPARE
+        select PINCTRL
        select SOC_IMX23
        select SOC_IMX28
+        select STMP_DEVICE
        help
-          Include support for Freescale MXS platforms(i.MX23 and i.MX28)
+          Support for Freescale MXS-based family of processors
-          using the device tree for discovery
-endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 80db7269760e..cc2bf6748ade 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,2 +1,2 @@
 obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
+obj-$(CONFIG_ARCH_MXS) += mach-mxs.o
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
deleted file mode 100644
index 07b11fe6453f..000000000000
--- a/arch/arm/mach-mxs/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y += 0x40008000
diff --git a/arch/arm/mach-mxs/include/mach/timex.h b/arch/arm/mach-mxs/include/mach/timex.h
deleted file mode 100644
index 734ce8984a64..000000000000
--- a/arch/arm/mach-mxs/include/mach/timex.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  Copyright (C) 1999 ARM Limited
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_MXS_TIMEX_H__
-#define __MACH_MXS_TIMEX_H__
-#define CLOCK_TICK_RATE         32000   /* 32K */
-#endif /* __MACH_MXS_TIMEX_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
deleted file mode 100644
index 533f5186e200..000000000000
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- *  arch/arm/mach-mxs/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) Shane Nay (shane@minirl.com)
- *  Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_MXS_UNCOMPRESS_H__
-#define __MACH_MXS_UNCOMPRESS_H__
-unsigned long mxs_duart_base;
-#define MXS_DUART(x)    (*(volatile unsigned long *)(mxs_duart_base + (x)))
-#define MXS_DUART_DR            0x00
-#define MXS_DUART_FR            0x18
-#define MXS_DUART_FR_TXFE       (1 << 7)
-#define MXS_DUART_CR            0x30
-#define MXS_DUART_CR_UARTEN     (1 << 0)
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader. If it's not, the output is
- * simply discarded.
- */
-static void putc(int ch)
-{
-        if (!mxs_duart_base)
-                return;
-        if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN))
-                return;
-        while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE))
-                barrier();
-        MXS_DUART(MXS_DUART_DR) = ch;
-}
-static inline void flush(void)
-{
-}
-#define MX23_DUART_BASE_ADDR    0x80070000
-#define MX28_DUART_BASE_ADDR    0x80074000
-#define MXS_DIGCTL_CHIPID       0x8001c310
-static inline void __arch_decomp_setup(unsigned long arch_id)
-{
-        u16 chipid = (*(volatile unsigned long *) MXS_DIGCTL_CHIPID) >> 16;
-        switch (chipid) {
-        case 0x3780:
-                mxs_duart_base = MX23_DUART_BASE_ADDR;
-                break;
-        case 0x2800:
-                mxs_duart_base = MX28_DUART_BASE_ADDR;
-                break;
-        default:
-                break;
-        }
-}
-#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#endif /* __MACH_MXS_UNCOMPRESS_H__ */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 16870bf853b8..b5c1bdd3dcdf 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -32,6 +32,8 @@
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
+#include "pm.h"
 /* MXS DIGCTL SAIF CLKMUX */
 #define MXS_DIGCTL_SAIF_CLKMUX_DIRECT           0x0
 #define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT       0x1
@@ -607,6 +609,7 @@ DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
        .handle_irq     = icoll_handle_irq,
        .init_time      = mxs_timer_init,
        .init_machine   = mxs_machine_init,
+        .init_late      = mxs_pm_init,
        .dt_compat      = mxs_dt_compat,
        .restart        = mxs_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
index a9b4bbcdafb4..b2494d2db2c4 100644
--- a/arch/arm/mach-mxs/pm.c
+++ b/arch/arm/mach-mxs/pm.c
@@ -34,9 +34,7 @@ static struct platform_suspend_ops mxs_suspend_ops = {
        .valid = suspend_valid_only_mem,
 };
-static int __init mxs_pm_init(void)
+void __init mxs_pm_init(void)
 {
        suspend_set_ops(&mxs_suspend_ops);
-        return 0;
 }
-device_initcall(mxs_pm_init);
diff --git a/arch/arm/mach-mxs/pm.h b/arch/arm/mach-mxs/pm.h
new file mode 100644
index 000000000000..f57e7cdece2e
--- /dev/null
+++ b/arch/arm/mach-mxs/pm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_MXS_PM_H
+#define __ARCH_MXS_PM_H
+void mxs_pm_init(void);
+#endif
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 82226a5d60ef..9b9d105f194c 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -1,5 +1,24 @@
-if ARCH_NOMADIK
+config ARCH_NOMADIK
+        bool "ST-Ericsson Nomadik"
+        depends on ARCH_MULTI_V5
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_VIC
+        select CLKSRC_NOMADIK_MTU
+        select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
+        select COMMON_CLK
+        select CPU_ARM926T
+        select GENERIC_CLOCKEVENTS
+        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
+        select PINCTRL_NOMADIK
+        select PINCTRL_STN8815
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          Support for the Nomadik platform by ST-Ericsson
+if ARCH_NOMADIK
 menu "Nomadik boards"
 config MACH_NOMADIK_8815NHK
@@ -9,8 +28,8 @@ config MACH_NOMADIK_8815NHK
        select I2C_ALGOBIT
 endmenu
+endif
 config NOMADIK_8815
+        depends on ARCH_NOMADIK
        bool
-endif
diff --git a/arch/arm/mach-nomadik/Makefile.boot b/arch/arm/mach-nomadik/Makefile.boot
deleted file mode 100644
index ff0a4b5b0a82..000000000000
--- a/arch/arm/mach-nomadik/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y   += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 21c1aa512640..59f6ff5c9bae 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -38,7 +38,6 @@
 #include <linux/gpio.h>
 #include <linux/amba/mmci.h>
-#include <mach/irqs.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
deleted file mode 100644
index 90ac965a92fe..000000000000
--- a/arch/arm/mach-nomadik/include/mach/irqs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  mach-nomadik/include/mach/irqs.h
- *
- *  Copyright (C) ST Microelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-#define IRQ_VIC_START           32      /* first VIC interrupt is 1 */
-/*
- * Interrupt numbers generic for all Nomadik Chip cuts
- */
-#define IRQ_WATCHDOG                    (IRQ_VIC_START+0)
-#define IRQ_SOFTINT                     (IRQ_VIC_START+1)
-#define IRQ_CRYPTO                      (IRQ_VIC_START+2)
-#define IRQ_OWM                         (IRQ_VIC_START+3)
-#define IRQ_MTU0                        (IRQ_VIC_START+4)
-#define IRQ_MTU1                        (IRQ_VIC_START+5)
-#define IRQ_GPIO0                       (IRQ_VIC_START+6)
-#define IRQ_GPIO1                       (IRQ_VIC_START+7)
-#define IRQ_GPIO2                       (IRQ_VIC_START+8)
-#define IRQ_GPIO3                       (IRQ_VIC_START+9)
-#define IRQ_RTC_RTT                     (IRQ_VIC_START+10)
-#define IRQ_SSP                         (IRQ_VIC_START+11)
-#define IRQ_UART0                       (IRQ_VIC_START+12)
-#define IRQ_DMA1                        (IRQ_VIC_START+13)
-#define IRQ_CLCD_MDIF                   (IRQ_VIC_START+14)
-#define IRQ_DMA0                        (IRQ_VIC_START+15)
-#define IRQ_PWRFAIL                     (IRQ_VIC_START+16)
-#define IRQ_UART1                       (IRQ_VIC_START+17)
-#define IRQ_FIRDA                       (IRQ_VIC_START+18)
-#define IRQ_MSP0                        (IRQ_VIC_START+19)
-#define IRQ_I2C0                        (IRQ_VIC_START+20)
-#define IRQ_I2C1                        (IRQ_VIC_START+21)
-#define IRQ_SDMMC                       (IRQ_VIC_START+22)
-#define IRQ_USBOTG                      (IRQ_VIC_START+23)
-#define IRQ_SVA_IT0                     (IRQ_VIC_START+24)
-#define IRQ_SVA_IT1                     (IRQ_VIC_START+25)
-#define IRQ_SAA_IT0                     (IRQ_VIC_START+26)
-#define IRQ_SAA_IT1                     (IRQ_VIC_START+27)
-#define IRQ_UART2                       (IRQ_VIC_START+28)
-#define IRQ_MSP2                        (IRQ_VIC_START+29)
-#define IRQ_L2CC                        (IRQ_VIC_START+30)
-#define IRQ_HPI                         (IRQ_VIC_START+31)
-#define IRQ_SKE                         (IRQ_VIC_START+32)
-#define IRQ_KP                          (IRQ_VIC_START+33)
-#define IRQ_MEMST                       (IRQ_VIC_START+34)
-#define IRQ_SGA_IT                      (IRQ_VIC_START+35)
-#define IRQ_USBM                        (IRQ_VIC_START+36)
-#define IRQ_MSP1                        (IRQ_VIC_START+37)
-#define NOMADIK_GPIO_OFFSET             (IRQ_VIC_START+64)
-/* After chip-specific IRQ numbers we have the GPIO ones */
-#define NOMADIK_NR_GPIO                 128 /* last 4 not wired to pins */
-#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_GPIO_OFFSET)
-#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_GPIO_OFFSET)
-#define NOMADIK_NR_IRQS                 NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
-/* Following two are used by entry_macro.S, to access our dual-vic */
-#define VIC_REG_IRQSR0          0
-#define VIC_REG_IRQSR1          0x20
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-nomadik/include/mach/timex.h b/arch/arm/mach-nomadik/include/mach/timex.h
deleted file mode 100644
index 318b8896ce96..000000000000
--- a/arch/arm/mach-nomadik/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-#define CLOCK_TICK_RATE         2400000
-#endif
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
deleted file mode 100644
index 106fccca2021..000000000000
--- a/arch/arm/mach-nomadik/include/mach/uncompress.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *  Copyright (C) 2008 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <asm/setup.h>
-#include <asm/io.h>
-/* we need the constants in amba/serial.h, but it refers to amba_device */
-struct amba_device;
-#include <linux/amba/serial.h>
-#define NOMADIK_UART_DR         (void __iomem *)0x101FB000
-#define NOMADIK_UART_LCRH       (void __iomem *)0x101FB02c
-#define NOMADIK_UART_CR         (void __iomem *)0x101FB030
-#define NOMADIK_UART_FR         (void __iomem *)0x101FB018
-static void putc(const char c)
-{
-        /* Do nothing if the UART is not enabled. */
-        if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
-                return;
-        if (c == '\n')
-                putc('\r');
-        while (readb(NOMADIK_UART_FR) & UART01x_FR_TXFF)
-                barrier();
-        writeb(c, NOMADIK_UART_DR);
-}
-static void flush(void)
-{
-        if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
-                return;
-        while (readb(NOMADIK_UART_FR) & UART01x_FR_BUSY)
-                barrier();
-}
-static inline void arch_decomp_setup(void)
-{
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 5c27c4747469..857b1f097fd8 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -91,6 +91,8 @@ config ARCH_OMAP4
        select ARM_GIC
        select CACHE_L2X0
        select CPU_V7
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_SMP
        select LOCAL_TIMERS if SMP
        select OMAP_INTERCONNECT
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index b3be7994a2b1..80ca974b2f82 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,3 +1,15 @@
+config ARCH_SIRF
+        bool "CSR SiRF" if ARCH_MULTI_V7
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select MIGHT_HAVE_CACHE_L2X0
+        select NO_IOPORT
+        select PINCTRL
+        select PINCTRL_SIRF
+        help
+          Support for CSR SiRFprimaII/Marco/Polo platforms
 if ARCH_SIRF
 menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
@@ -24,6 +36,7 @@ config ARCH_MARCO
        default y
        select ARM_GIC
        select CPU_V7
+        select HAVE_ARM_SCU if SMP
        select HAVE_SMP
        select SMP_ON_UP
        help
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index bfe360cbd177..7a6b4a323125 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -4,8 +4,7 @@ obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
-obj-$(CONFIG_SIRF_IRQ) += irq.o
 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
-obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
-obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
+CFLAGS_hotplug.o += -march=armv7-a
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 72efb4ff2803..4f94cd87972a 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -6,6 +6,7 @@
 * Licensed under GPLv2 or later.
 */
+#include <linux/clocksource.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/irqchip.h>
@@ -31,6 +32,13 @@ void __init sirfsoc_init_late(void)
        sirfsoc_pm_init();
 }
+static __init void sirfsoc_init_time(void)
+{
+        /* initialize clocking early, we want to set the OS timer */
+        sirfsoc_of_clk_init();
+        clocksource_of_init();
+}
 static __init void sirfsoc_map_io(void)
 {
        sirfsoc_map_lluart();
@@ -45,12 +53,10 @@ static const char *atlas6_dt_match[] __initdata = {
 DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .nr_irqs        = 128,
        .map_io         = sirfsoc_map_io,
-        .init_irq       = sirfsoc_of_irq_init,
+        .init_irq       = irqchip_init,
-        .init_time      = sirfsoc_prima2_timer_init,
+        .init_time      = sirfsoc_init_time,
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-        .handle_irq     = sirfsoc_handle_irq,
-#endif
        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = atlas6_dt_match,
@@ -66,12 +72,10 @@ static const char *prima2_dt_match[] __initdata = {
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .nr_irqs        = 128,
        .map_io         = sirfsoc_map_io,
-        .init_irq       = sirfsoc_of_irq_init,
+        .init_irq       = irqchip_init,
-        .init_time      = sirfsoc_prima2_timer_init,
+        .init_time      = sirfsoc_init_time,
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-        .handle_irq     = sirfsoc_handle_irq,
-#endif
        .dma_zone_size  = SZ_256M,
        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
@@ -91,7 +95,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
        .smp            = smp_ops(sirfsoc_smp_ops),
        .map_io         = sirfsoc_map_io,
        .init_irq       = irqchip_init,
-        .init_time      = sirfsoc_marco_timer_init,
+        .init_time      = sirfsoc_init_time,
        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = marco_dt_match,
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index b7c26b62e4a7..81135cd88e54 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -13,8 +13,8 @@
 #include <asm/mach/time.h>
 #include <asm/exception.h>
-extern void sirfsoc_prima2_timer_init(void);
+#define SIRFSOC_VA_BASE         _AC(0xFEC00000, UL)
-extern void sirfsoc_marco_timer_init(void);
+#define SIRFSOC_VA(x)           (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
 extern struct smp_operations   sirfsoc_smp_ops;
 extern void sirfsoc_secondary_startup(void);
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h
deleted file mode 100644
index 66932518b1b7..000000000000
--- a/arch/arm/mach-prima2/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/clkdev.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S
deleted file mode 100644
index cd97492bb075..000000000000
--- a/arch/arm/mach-prima2/include/mach/debug-macro.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/debug-macro.S
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#include <mach/hardware.h>
-#include <mach/uart.h>
-        .macro  addruart, rp, rv, tmp
-        ldr     \rp, =SIRFSOC_UART1_PA_BASE             @ physical
-        ldr     \rv, =SIRFSOC_UART1_VA_BASE             @ virtual
-        .endm
-        .macro  senduart,rd,rx
-        str     \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
-        .endm
-        .macro  busyuart,rd,rx
-        .endm
-        .macro  waituart,rd,rx
-1001:   ldr     \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
-        tst     \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
-        beq     1001b
-        .endm
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
deleted file mode 100644
index 86434e7a5be9..000000000000
--- a/arch/arm/mach-prima2/include/mach/entry-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/entry-macro.S
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#include <mach/hardware.h>
-#define SIRFSOC_INT_ID 0x38
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =sirfsoc_intc_base
-        ldr     \base, [\base]
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr \irqnr, [\base, #SIRFSOC_INT_ID]    @ Get the highest priority irq
-        cmp \irqnr, #0x40                       @ the irq num can't be larger than 0x3f
-        movges \irqnr, #0
-        .endm
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h
deleted file mode 100644
index 105b96964f25..000000000000
--- a/arch/arm/mach-prima2/include/mach/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/hardware.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef __MACH_HARDWARE_H__
-#define __MACH_HARDWARE_H__
-#include <asm/sizes.h>
-#include <mach/map.h>
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
deleted file mode 100644
index b778a0f248ed..000000000000
--- a/arch/arm/mach-prima2/include/mach/irqs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/irqs.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-#define SIRFSOC_INTENAL_IRQ_START  0
-#define SIRFSOC_INTENAL_IRQ_END    127
-#define SIRFSOC_GPIO_IRQ_START     (SIRFSOC_INTENAL_IRQ_END + 1)
-#define NR_IRQS 288
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
deleted file mode 100644
index 6f243532570c..000000000000
--- a/arch/arm/mach-prima2/include/mach/map.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * memory & I/O static mapping definitions for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef __MACH_PRIMA2_MAP_H__
-#define __MACH_PRIMA2_MAP_H__
-#include <linux/const.h>
-#define SIRFSOC_VA_BASE         _AC(0xFEC00000, UL)
-#define SIRFSOC_VA(x)           (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h
deleted file mode 100644
index d6f98a75e562..000000000000
--- a/arch/arm/mach-prima2/include/mach/timex.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/timex.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef __MACH_TIMEX_H__
-#define __MACH_TIMEX_H__
-#define CLOCK_TICK_RATE  1000000
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
deleted file mode 100644
index d1513a33709a..000000000000
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/uncompress.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/uart.h>
-void arch_decomp_setup(void)
-{
-}
-static __inline__ void putc(char c)
-{
-        /*
-         * during kernel decompression, all mappings are flat:
-         *  virt_addr == phys_addr
-         */
-        if (!SIRFSOC_UART1_PA_BASE)
-                return;
-        while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
-                & SIRFSOC_UART1_TXFIFO_FULL)
-                barrier();
-        __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
-}
-static inline void flush(void)
-{
-}
-#endif
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
deleted file mode 100644
index 6c0f3e9c43fb..000000000000
--- a/arch/arm/mach-prima2/irq.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * interrupt controller support for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/irqdomain.h>
-#include <linux/syscore_ops.h>
-#include <asm/mach/irq.h>
-#include <asm/exception.h>
-#include <mach/hardware.h>
-#define SIRFSOC_INT_RISC_MASK0          0x0018
-#define SIRFSOC_INT_RISC_MASK1          0x001C
-#define SIRFSOC_INT_RISC_LEVEL0         0x0020
-#define SIRFSOC_INT_RISC_LEVEL1         0x0024
-#define SIRFSOC_INIT_IRQ_ID             0x0038
-void __iomem *sirfsoc_intc_base;
-static __init void
-sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-        gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
-        ct = gc->chip_types;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
-        ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
-        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
-}
-static __init void sirfsoc_irq_init(void)
-{
-        sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
-        sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
-                        SIRFSOC_INTENAL_IRQ_END + 1 - 32);
-        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-}
-asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
-{
-        u32 irqstat, irqnr;
-        irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
-        irqnr = irqstat & 0xff;
-        handle_IRQ(irqnr, regs);
-}
-static struct of_device_id intc_ids[]  = {
-        { .compatible = "sirf,prima2-intc" },
-        {},
-};
-void __init sirfsoc_of_irq_init(void)
-{
-        struct device_node *np;
-        np = of_find_matching_node(NULL, intc_ids);
-        if (!np)
-                return;
-        sirfsoc_intc_base = of_iomap(np, 0);
-        if (!sirfsoc_intc_base)
-                panic("unable to map intc cpu registers\n");
-        irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
-                &irq_domain_simple_ops, NULL);
-        of_node_put(np);
-        sirfsoc_irq_init();
-}
-struct sirfsoc_irq_status {
-        u32 mask0;
-        u32 mask1;
-        u32 level0;
-        u32 level1;
-};
-static struct sirfsoc_irq_status sirfsoc_irq_st;
-static int sirfsoc_irq_suspend(void)
-{
-        sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-        sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-        sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-        sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-        return 0;
-}
-static void sirfsoc_irq_resume(void)
-{
-        writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-        writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-        writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-        writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-}
-static struct syscore_ops sirfsoc_irq_syscore_ops = {
-        .suspend        = sirfsoc_irq_suspend,
-        .resume         = sirfsoc_irq_resume,
-};
-static int __init sirfsoc_irq_pm_init(void)
-{
-        register_syscore_ops(&sirfsoc_irq_syscore_ops);
-        return 0;
-}
-device_initcall(sirfsoc_irq_pm_init);
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c
index a89f9b3c8cc5..99c0c927ca4a 100644
--- a/arch/arm/mach-prima2/lluart.c
+++ b/arch/arm/mach-prima2/lluart.c
@@ -9,8 +9,18 @@
 #include <linux/kernel.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
-#include <mach/map.h>
+#include "common.h"
-#include <mach/uart.h>
+#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xb0060000
+#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xcc060000
+#else
+#define SIRFSOC_UART1_PA_BASE          0
+#endif
+#define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
+#define SIRFSOC_UART1_SIZE              SZ_4K
 void __init sirfsoc_map_lluart(void)
 {
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index c7c92e78f0cf..1c3de7bed841 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -17,7 +17,6 @@
 #include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
-#include <mach/map.h>
 #include "common.h"
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 14c1d47e1abf..d210c0f9c2c4 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -12,6 +12,8 @@ config REALVIEW_EB_A9MP
        bool "Support Multicore Cortex-A9 Tile"
        depends on MACH_REALVIEW_EB
        select CPU_V7
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        help
@@ -23,6 +25,8 @@ config REALVIEW_EB_ARM11MP
        depends on MACH_REALVIEW_EB
        select ARCH_HAS_BARRIERS if SMP
        select CPU_V6K
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        help
@@ -43,6 +47,8 @@ config MACH_REALVIEW_PB11MP
        select ARCH_HAS_BARRIERS if SMP
        select ARM_GIC
        select CPU_V6K
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_PATA_PLATFORM
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
@@ -85,6 +91,8 @@ config MACH_REALVIEW_PBX
        bool "Support RealView(R) Platform Baseboard Explore"
        select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
        select ARM_GIC
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_PATA_PLATFORM
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 13ed33c69113..2558952e3147 100644
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -98,4 +98,4 @@
 /* include the reset of the code which will do the work */
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
index c0c076a90f27..dd9ccca5de1f 100644
--- a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -35,4 +35,4 @@
 * will be fine with us.
 */
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
index e80ba3c69814..5e2916fb19a9 100644
--- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -30,4 +30,4 @@
 #endif
        .endm
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index 694f75937000..66cb7f16bf2a 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -36,4 +36,4 @@
 * will be fine with us.
 */
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
index 03c02d04c68c..6010c0310cb5 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -19,7 +19,6 @@
 #include <linux/mmc/card.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
 void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
index 79e55597ab63..80c21996c943 100644
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
@@ -38,4 +38,4 @@
 * will be fine with us.
 */
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index 3e3ac05bb7b1..0512ada00522 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -20,7 +20,6 @@
 #include <linux/mmc/card.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
 void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
new file mode 100644
index 000000000000..442917eedff3
--- /dev/null
+++ b/arch/arm/mach-spear/Kconfig
@@ -0,0 +1,105 @@
+#
+# SPEAr Platform configuration file
+#
+menuconfig PLAT_SPEAR
+        bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5
+        default PLAT_SPEAR_SINGLE
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK
+if PLAT_SPEAR
+config ARCH_SPEAR13XX
+        bool "ST SPEAr13xx"
+        depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
+        select ARCH_HAS_CPUFREQ
+        select ARM_GIC
+        select CPU_V7
+        select GPIO_SPEAR_SPICS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
+        select USE_OF
+        help
+          Supports for ARM's SPEAR13XX family
+if ARCH_SPEAR13XX
+config MACH_SPEAR1310
+        bool "SPEAr1310 Machine support with Device Tree"
+        select PINCTRL_SPEAR1310
+        help
+          Supports ST SPEAr1310 machine configured via the device-tree
+config MACH_SPEAR1340
+        bool "SPEAr1340 Machine support with Device Tree"
+        select PINCTRL_SPEAR1340
+        help
+          Supports ST SPEAr1340 machine configured via the device-tree
+endif #ARCH_SPEAR13XX
+config ARCH_SPEAR3XX
+        bool "ST SPEAr3xx"
+        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX
+        select ARM_VIC
+        select CPU_ARM926T
+        select PINCTRL
+        select USE_OF
+        help
+          Supports for ARM's SPEAR3XX family
+if ARCH_SPEAR3XX
+config MACH_SPEAR300
+        bool "SPEAr300 Machine support with Device Tree"
+        select PINCTRL_SPEAR300
+        help
+          Supports ST SPEAr300 machine configured via the device-tree
+config MACH_SPEAR310
+        bool "SPEAr310 Machine support with Device Tree"
+        select PINCTRL_SPEAR310
+        help
+          Supports ST SPEAr310 machine configured via the device-tree
+config MACH_SPEAR320
+        bool "SPEAr320 Machine support with Device Tree"
+        select PINCTRL_SPEAR320
+        help
+          Supports ST SPEAr320 machine configured via the device-tree
+endif
+config ARCH_SPEAR6XX
+        bool "ST SPEAr6XX"
+        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX
+        select ARM_VIC
+        select CPU_ARM926T
+        help
+          Supports for ARM's SPEAR6XX family
+config MACH_SPEAR600
+        def_bool y
+        depends on ARCH_SPEAR6XX
+        select USE_OF
+        help
+          Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig"
+config ARCH_SPEAR_AUTO
+        def_bool PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX
+        select ARCH_SPEAR3XX
+endif
diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile
new file mode 100644
index 000000000000..af9bffb94f1c
--- /dev/null
+++ b/arch/arm/mach-spear/Makefile
@@ -0,0 +1,26 @@
+#
+# SPEAr Platform specific Makefile
+#
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+# Common support
+obj-y   := restart.o time.o
+obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+obj-$(CONFIG_ARCH_SPEAR13XX)    += spear13xx.o
+obj-$(CONFIG_MACH_SPEAR1310)    += spear1310.o
+obj-$(CONFIG_MACH_SPEAR1340)    += spear1340.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o
+obj-$(CONFIG_MACH_SPEAR300)     += spear300.o
+obj-$(CONFIG_MACH_SPEAR310)     += spear310.o
+obj-$(CONFIG_MACH_SPEAR320)     += spear320.o
+obj-$(CONFIG_ARCH_SPEAR6XX)     += spear6xx.o
+obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
+CFLAGS_hotplug.o                += -march=armv7-a
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear/Makefile.boot
index 4674a4c221db..4674a4c221db 100644
--- a/arch/arm/mach-spear13xx/Makefile.boot
+++ b/arch/arm/mach-spear/Makefile.boot
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear/generic.h
index 633e678e01a3..8ba7e75b648d 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -1,9 +1,8 @@
 /*
- * arch/arm/mach-spear13xx/include/mach/generic.h
+ * spear machine family generic header file
 *
- * spear13xx machine family generic header file
+ * Copyright (C) 2009-2012 ST Microelectronics
- *
+ * Rajeev Kumar <rajeev-dlh.kumar@st.com>
- * Copyright (C) 2012 ST Microelectronics
 * Viresh Kumar <viresh.linux@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
@@ -15,37 +14,46 @@
 #define __MACH_GENERIC_H
 #include <linux/dmaengine.h>
+#include <linux/amba/pl08x.h>
+#include <linux/init.h>
 #include <asm/mach/time.h>
-/* Add spear13xx structure declarations here */
 extern void spear13xx_timer_init(void);
+extern void spear3xx_timer_init(void);
 extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 extern struct dw_dma_platform_data dmac_plat_data;
 extern struct dw_dma_slave cf_dma_priv;
 extern struct dw_dma_slave nand_read_dma_priv;
 extern struct dw_dma_slave nand_write_dma_priv;
+bool dw_dma_filter(struct dma_chan *chan, void *slave);
-/* Add spear13xx family function declarations here */
 void __init spear_setup_of_timer(void);
+void __init spear3xx_clk_init(void __iomem *misc_base,
+                              void __iomem *soc_config_base);
+void __init spear3xx_map_io(void);
+void __init spear3xx_dt_init_irq(void);
+void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
-bool dw_dma_filter(struct dma_chan *chan, void *slave);
 void spear_restart(char, const char *);
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
 extern struct smp_operations spear13xx_smp_ops;
 #ifdef CONFIG_MACH_SPEAR1310
-void __init spear1310_clk_init(void);
+void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
 #else
-static inline void spear1310_clk_init(void) {}
+static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {}
 #endif
 #ifdef CONFIG_MACH_SPEAR1340
-void __init spear1340_clk_init(void);
+void __init spear1340_clk_init(void __iomem *misc_base);
 #else
-static inline void spear1340_clk_init(void) {}
+static inline void spear1340_clk_init(void __iomem *misc_base) {}
 #endif
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear/headsmp.S
index ed85473a047f..ed85473a047f 100644
--- a/arch/arm/mach-spear13xx/headsmp.S
+++ b/arch/arm/mach-spear/headsmp.S
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear/hotplug.c
index a7d2dd11a4f2..a7d2dd11a4f2 100644
--- a/arch/arm/mach-spear13xx/hotplug.c
+++ b/arch/arm/mach-spear/hotplug.c
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/mach-spear/include/mach/debug-macro.S
index 75b05ad0fbad..75b05ad0fbad 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/mach-spear/include/mach/debug-macro.S
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear/include/mach/irqs.h
index 37a5c411a866..92da0a8c6bce 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear/include/mach/irqs.h
@@ -1,10 +1,9 @@
 /*
- * arch/arm/mach-spear6xx/include/mach/irqs.h
+ * IRQ helper macros for spear machine family
 *
- * IRQ helper macros for SPEAr6xx machine family
+ * Copyright (C) 2009-2012 ST Microelectronics
- *
+ * Rajeev Kumar <rajeev-dlh.kumar@st.com>
- * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar <viresh.linux@gmail.com>
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
@@ -14,6 +13,11 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
+#ifdef CONFIG_ARCH_SPEAR3XX
+#define NR_IRQS                 256
+#endif
+#ifdef CONFIG_ARCH_SPEAR6XX
 /* IRQ definitions */
 /* VIC 1 */
 #define IRQ_VIC_END                             64
@@ -21,5 +25,11 @@
 /* GPIO pins virtual irqs */
 #define VIRTUAL_IRQS                            24
 #define NR_IRQS                                 (IRQ_VIC_END + VIRTUAL_IRQS)
+#endif
+#ifdef CONFIG_ARCH_SPEAR13XX
+#define IRQ_GIC_END                     160
+#define NR_IRQS                         IRQ_GIC_END
+#endif
-#endif  /* __MACH_IRQS_H */
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear/include/mach/misc_regs.h
index 6309bf68d6f8..935639ce59ba 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear/include/mach/misc_regs.h
@@ -16,7 +16,7 @@
 #include <mach/spear.h>
-#define MISC_BASE               IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
+#define MISC_BASE               (VA_SPEAR_ICM3_MISC_REG_BASE)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
new file mode 100644
index 000000000000..374ddc393df1
--- /dev/null
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -0,0 +1,95 @@
+/*
+ * SPEAr3xx/6xx Machine family specific definition
+ *
+ * Copyright (C) 2009,2012 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ * Viresh Kumar <viresh.linux@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __MACH_SPEAR_H
+#define __MACH_SPEAR_H
+#include <asm/memory.h>
+#if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX)
+/* ICM1 - Low speed connection */
+#define SPEAR_ICM1_2_BASE               UL(0xD0000000)
+#define VA_SPEAR_ICM1_2_BASE            IOMEM(0xFD000000)
+#define SPEAR_ICM1_UART_BASE            UL(0xD0000000)
+#define VA_SPEAR_ICM1_UART_BASE         (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE)
+#define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
+/* ML-1, 2 - Multi Layer CPU Subsystem */
+#define SPEAR_ICM3_ML1_2_BASE           UL(0xF0000000)
+#define VA_SPEAR6XX_ML_CPU_BASE         IOMEM(0xF0000000)
+/* ICM3 - Basic Subsystem */
+#define SPEAR_ICM3_SMI_CTRL_BASE        UL(0xFC000000)
+#define VA_SPEAR_ICM3_SMI_CTRL_BASE     IOMEM(0xFC000000)
+#define SPEAR_ICM3_DMA_BASE             UL(0xFC400000)
+#define SPEAR_ICM3_SYS_CTRL_BASE        UL(0xFCA00000)
+#define VA_SPEAR_ICM3_SYS_CTRL_BASE     (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE)
+#define SPEAR_ICM3_MISC_REG_BASE        UL(0xFCA80000)
+#define VA_SPEAR_ICM3_MISC_REG_BASE     (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE)
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE             SPEAR_ICM1_UART_BASE
+#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR_ICM1_UART_BASE
+/* Sysctl base for spear platform */
+#define SPEAR_SYS_CTRL_BASE             SPEAR_ICM3_SYS_CTRL_BASE
+#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR_ICM3_SYS_CTRL_BASE
+#endif /* SPEAR3xx || SPEAR6XX */
+/* SPEAr320 Macros */
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
+#define VA_SPEAR320_SOC_CONFIG_BASE     IOMEM(0xFE000000)
+#ifdef CONFIG_ARCH_SPEAR13XX
+#define PERIP_GRP2_BASE                         UL(0xB3000000)
+#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
+#define MCIF_SDHCI_BASE                         UL(0xB3000000)
+#define SYSRAM0_BASE                            UL(0xB3800000)
+#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
+#define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
+#define PERIP_GRP1_BASE                         UL(0xE0000000)
+#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
+#define UART_BASE                               UL(0xE0000000)
+#define VA_UART_BASE                            IOMEM(0xFD000000)
+#define SSP_BASE                                UL(0xE0100000)
+#define MISC_BASE                               UL(0xE0700000)
+#define VA_MISC_BASE                            IOMEM(0xFD700000)
+#define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
+#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
+#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
+/* A9SM peripheral offsets */
+#define A9SM_PERIP_BASE                         UL(0xEC800000)
+#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
+#define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
+#define L2CC_BASE                               UL(0xED000000)
+#define VA_L2CC_BASE                            IOMEM(UL(0xFB000000))
+/* others */
+#define DMAC0_BASE                              UL(0xEA800000)
+#define DMAC1_BASE                              UL(0xEB000000)
+#define MCIF_CF_BASE                            UL(0xB2800000)
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE                     UART_BASE
+#define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
+#endif /* SPEAR13XX */
+#endif /* __MACH_SPEAR_H */
diff --git a/arch/arm/plat-spear/include/plat/timex.h b/arch/arm/mach-spear/include/mach/timex.h
index ef95e5b780bd..ef95e5b780bd 100644
--- a/arch/arm/plat-spear/include/plat/timex.h
+++ b/arch/arm/mach-spear/include/mach/timex.h
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/mach-spear/include/mach/uncompress.h
index 51b2dc93e4da..51b2dc93e4da 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/mach-spear/include/mach/uncompress.h
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/mach-spear/pl080.c
index cfa1199d0f4a..cfa1199d0f4a 100644
--- a/arch/arm/plat-spear/pl080.c
+++ b/arch/arm/mach-spear/pl080.c
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/mach-spear/pl080.h
index eb6590ded40d..eb6590ded40d 100644
--- a/arch/arm/plat-spear/include/plat/pl080.h
+++ b/arch/arm/mach-spear/pl080.h
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear/platsmp.c
index 551c69c9a228..9c4c722c954e 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -18,7 +18,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 #include <mach/spear.h>
-#include <mach/generic.h>
+#include "generic.h"
 static DEFINE_SPINLOCK(boot_lock);
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/mach-spear/restart.c
index 7d4616d5df11..2b44500bb718 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -14,7 +14,7 @@
 #include <linux/amba/sp810.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
-#include <mach/generic.h>
+#include "generic.h"
 #define SPEAR13XX_SYS_SW_RES                    (VA_MISC_BASE + 0x204)
 void spear_restart(char mode, const char *cmd)
@@ -26,7 +26,8 @@ void spear_restart(char mode, const char *cmd)
                /* hardware reset, Use on-chip reset capability */
 #ifdef CONFIG_ARCH_SPEAR13XX
                writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
-#else
+#endif
+#if defined(CONFIG_ARCH_SPEAR3XX) || defined(CONFIG_ARCH_SPEAR6XX)
                sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
 #endif
        }
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 56214d1076ef..ed3b5c287a7b 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -19,7 +19,7 @@
 #include <linux/pata_arasan_cf_data.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 /* Base addresses */
@@ -30,8 +30,6 @@
 #define SPEAR1310_RAS_GRP1_BASE                 UL(0xD8000000)
 #define VA_SPEAR1310_RAS_GRP1_BASE              UL(0xFA000000)
-#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
-#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
 static struct arasan_cf_pdata cf_pdata = {
        .cf_if_clk = CF_IF_CLK_166M,
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 9a28beb2a113..75e38644bbfb 100644
--- a/arch/arm/mach-spear13xx/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -20,10 +20,11 @@
 #include <linux/of_platform.h>
 #include <linux/irqchip.h>
 #include <asm/mach/arch.h>
-#include <mach/dma.h>
+#include "generic.h"
-#include <mach/generic.h>
 #include <mach/spear.h>
+#include "spear13xx-dma.h"
 /* Base addresses */
 #define SPEAR1340_SATA_BASE                     UL(0xB1000000)
 #define SPEAR1340_UART1_BASE                    UL(0xB4100000)
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear/spear13xx-dma.h
index d50bdb605925..d50bdb605925 100644
--- a/arch/arm/mach-spear13xx/include/mach/dma.h
+++ b/arch/arm/mach-spear/spear13xx-dma.h
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 25a10191b021..6dd208997176 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -21,10 +21,11 @@
 #include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
-#include <mach/dma.h>
+#include "generic.h"
-#include <mach/generic.h>
 #include <mach/spear.h>
+#include "spear13xx-dma.h"
 /* common dw_dma filter routine to be used by peripherals */
 bool dw_dma_filter(struct dma_chan *chan, void *slave)
 {
@@ -145,9 +146,9 @@ void __init spear13xx_map_io(void)
 static void __init spear13xx_clk_init(void)
 {
        if (of_machine_is_compatible("st,spear1310"))
-                spear1310_clk_init();
+                spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
        else if (of_machine_is_compatible("st,spear1340"))
-                spear1340_clk_init();
+                spear1340_clk_init(VA_MISC_BASE);
        else
                pr_err("%s: Unknown machine\n", __func__);
 }
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear/spear300.c
index bbc9b7e9c62c..bac56e845f7a 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear/spear300.c
@@ -17,7 +17,7 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 /* DMAC platform data's slave info */
@@ -185,7 +185,7 @@ struct pl08x_channel_data spear300_dma_info[] = {
 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                        &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                        &pl080_plat_data),
        {}
 };
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear/spear310.c
index c13a434a8195..6ffbc63d516d 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear/spear310.c
@@ -18,7 +18,7 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 #define SPEAR310_UART1_BASE             UL(0xB2000000)
@@ -217,7 +217,7 @@ static struct amba_pl011_data spear310_uart_data[] = {
 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                        &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                        &pl080_plat_data),
        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
                        &spear310_uart_data[0]),
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear/spear320.c
index e1c77079a3e5..6eb3eec65f96 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear/spear320.c
@@ -19,7 +19,8 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include <asm/mach/map.h>
+#include "generic.h"
 #include <mach/spear.h>
 #define SPEAR320_UART1_BASE             UL(0xA3000000)
@@ -222,7 +223,7 @@ static struct amba_pl011_data spear320_uart_data[] = {
 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                        &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                        &pl080_plat_data),
        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
                        &spear320_ssp_data[0]),
@@ -253,7 +254,7 @@ static const char * const spear320_dt_board_compat[] = {
 struct map_desc spear320_io_desc[] __initdata = {
        {
-                .virtual        = VA_SPEAR320_SOC_CONFIG_BASE,
+                .virtual        = (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE,
                .pfn            = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear/spear3xx.c
index d2b3937c4014..0227c97797cd 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear/spear3xx.c
@@ -15,10 +15,13 @@
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl080.h>
+#include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/pl080.h>
+#include <asm/mach/map.h>
-#include <mach/generic.h>
+#include "pl080.h"
+#include "generic.h"
 #include <mach/spear.h>
+#include <mach/misc_regs.h>
 /* ssp device registration */
 struct pl022_ssp_controller pl022_plat_data = {
@@ -65,13 +68,13 @@ struct pl08x_platform_data pl080_plat_data = {
 */
 struct map_desc spear3xx_io_desc[] __initdata = {
        {
-                .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
+                .virtual        = (unsigned long)VA_SPEAR_ICM1_2_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+                .pfn            = __phys_to_pfn(SPEAR_ICM1_2_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-                .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
+                .virtual        = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        },
@@ -88,7 +91,7 @@ void __init spear3xx_timer_init(void)
        char pclk_name[] = "pll3_clk";
        struct clk *gpt_clk, *pclk;
-        spear3xx_clk_init();
+        spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);
        /* get the system timer clock */
        gpt_clk = clk_get_sys("gpt0", NULL);
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear/spear6xx.c
index 8904d8a52d84..ec8eefbbdfad 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear/spear6xx.c
@@ -24,9 +24,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <plat/pl080.h>
+#include "pl080.h"
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
+#include <mach/misc_regs.h>
 /* dmac device registration */
 static struct pl08x_channel_data spear600_dma_info[] = {
@@ -321,7 +322,7 @@ static struct pl08x_channel_data spear600_dma_info[] = {
        },
 };
-struct pl08x_platform_data pl080_plat_data = {
+static struct pl08x_platform_data spear6xx_pl080_plat_data = {
        .memcpy_channel = {
                .bus_id = "memcpy",
                .cctl_memcpy =
@@ -350,18 +351,18 @@ struct pl08x_platform_data pl080_plat_data = {
 */
 struct map_desc spear6xx_io_desc[] __initdata = {
        {
-                .virtual        = VA_SPEAR6XX_ML_CPU_BASE,
+                .virtual        = (unsigned long)VA_SPEAR6XX_ML_CPU_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE),
                .length         = 2 * SZ_16M,
                .type           = MT_DEVICE
        },      {
-                .virtual        = VA_SPEAR6XX_ICM1_BASE,
+                .virtual        = (unsigned long)VA_SPEAR_ICM1_2_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+                .pfn            = __phys_to_pfn(SPEAR_ICM1_2_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-                .virtual        = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
+                .virtual        = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        },
@@ -378,7 +379,7 @@ void __init spear6xx_timer_init(void)
        char pclk_name[] = "pll3_clk";
        struct clk *gpt_clk, *pclk;
-        spear6xx_clk_init();
+        spear6xx_clk_init(MISC_BASE);
        /* get the system timer clock */
        gpt_clk = clk_get_sys("gpt0", NULL);
@@ -404,8 +405,8 @@ void __init spear6xx_timer_init(void)
 /* Add auxdata to pass platform data */
 struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
-                        &pl080_plat_data),
+                        &spear6xx_pl080_plat_data),
        {}
 };
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/mach-spear/time.c
index bd5c53cd6962..d449673e40f7 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@@ -23,7 +23,7 @@
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
-#include <mach/generic.h>
+#include "generic.h"
 /*
 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
deleted file mode 100644
index eaadc66d96b3..000000000000
--- a/arch/arm/mach-spear13xx/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# SPEAr13XX Machine configuration file
-#
-if ARCH_SPEAR13XX
-menu "SPEAr13xx Implementations"
-config MACH_SPEAR1310
-        bool "SPEAr1310 Machine support with Device Tree"
-        select PINCTRL_SPEAR1310
-        help
-          Supports ST SPEAr1310 machine configured via the device-tree
-config MACH_SPEAR1340
-        bool "SPEAr1340 Machine support with Device Tree"
-        select PINCTRL_SPEAR1340
-        help
-          Supports ST SPEAr1340 machine configured via the device-tree
-endmenu
-endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
deleted file mode 100644
index 3435ea78c15d..000000000000
--- a/arch/arm/mach-spear13xx/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Makefile for SPEAr13XX machine series
-#
-obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-obj-$(CONFIG_ARCH_SPEAR13XX)    += spear13xx.o
-obj-$(CONFIG_MACH_SPEAR1310)    += spear1310.o
-obj-$(CONFIG_MACH_SPEAR1340)    += spear1340.o
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
deleted file mode 100644
index 9e3ae6bfe50d..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/debug-macro.S
- *
- * Debugging macro include header spear13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
deleted file mode 100644
index 271a62b4cd31..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/irqs.h
- *
- * IRQ helper macros for spear13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-#define IRQ_GIC_END                     160
-#define NR_IRQS                         IRQ_GIC_END
-#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
deleted file mode 100644
index 7cfa6818865a..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/spear.h
- *
- * spear13xx Machine family specific definition
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_SPEAR13XX_H
-#define __MACH_SPEAR13XX_H
-#include <asm/memory.h>
-#define PERIP_GRP2_BASE                         UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
-#define MCIF_SDHCI_BASE                         UL(0xB3000000)
-#define SYSRAM0_BASE                            UL(0xB3800000)
-#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
-#define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
-#define PERIP_GRP1_BASE                         UL(0xE0000000)
-#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
-#define UART_BASE                               UL(0xE0000000)
-#define VA_UART_BASE                            IOMEM(0xFD000000)
-#define SSP_BASE                                UL(0xE0100000)
-#define MISC_BASE                               UL(0xE0700000)
-#define VA_MISC_BASE                            IOMEM(0xFD700000)
-#define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
-#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
-/* A9SM peripheral offsets */
-#define A9SM_PERIP_BASE                         UL(0xEC800000)
-#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
-#define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
-#define L2CC_BASE                               UL(0xED000000)
-#define VA_L2CC_BASE                            IOMEM(UL(0xFB000000))
-/* others */
-#define DMAC0_BASE                              UL(0xEA800000)
-#define DMAC1_BASE                              UL(0xEB000000)
-#define MCIF_CF_BASE                            UL(0xB2800000)
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE                     UART_BASE
-#define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
-#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
deleted file mode 100644
index 3a58b8284a6a..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/timex.h
- *
- * SPEAr3XX machine family specific timex definitions
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-#include <plat/timex.h>
-#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
deleted file mode 100644
index 70fe72f05dea..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-#include <plat/uncompress.h>
-#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
deleted file mode 100644
index 8bd37291fa4f..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# SPEAr3XX Machine configuration file
-#
-if ARCH_SPEAR3XX
-menu "SPEAr3xx Implementations"
-config MACH_SPEAR300
-        bool "SPEAr300 Machine support with Device Tree"
-        select PINCTRL_SPEAR300
-        help
-          Supports ST SPEAr300 machine configured via the device-tree
-config MACH_SPEAR310
-        bool "SPEAr310 Machine support with Device Tree"
-        select PINCTRL_SPEAR310
-        help
-          Supports ST SPEAr310 machine configured via the device-tree
-config MACH_SPEAR320
-        bool "SPEAr320 Machine support with Device Tree"
-        select PINCTRL_SPEAR320
-        help
-          Supports ST SPEAr320 machine configured via the device-tree
-endmenu
-endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
deleted file mode 100644
index 8d12faa178fd..000000000000
--- a/arch/arm/mach-spear3xx/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Makefile for SPEAr3XX machine series
-#
-# common files
-obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o
-# spear300 specific files
-obj-$(CONFIG_MACH_SPEAR300) += spear300.o
-# spear310 specific files
-obj-$(CONFIG_MACH_SPEAR310) += spear310.o
-# spear320 specific files
-obj-$(CONFIG_MACH_SPEAR320) += spear320.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
deleted file mode 100644
index 4674a4c221db..000000000000
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y      += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S
deleted file mode 100644
index 0a6381fad5d9..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/debug-macro.S
- *
- * Debugging macro include header spear3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
deleted file mode 100644
index df310799e416..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/generic.h
- *
- * SPEAr3XX machine family generic header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_GENERIC_H
-#define __MACH_GENERIC_H
-#include <linux/amba/pl08x.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-/* Add spear3xx family device structure declarations here */
-extern void spear3xx_timer_init(void);
-extern struct pl022_ssp_controller pl022_plat_data;
-extern struct pl08x_platform_data pl080_plat_data;
-/* Add spear3xx family function declarations here */
-void __init spear_setup_of_timer(void);
-void __init spear3xx_clk_init(void);
-void __init spear3xx_map_io(void);
-void spear_restart(char, const char *);
-#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
deleted file mode 100644
index f95e5b2b6686..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/irqs.h
- *
- * IRQ helper macros for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-#define NR_IRQS                 256
-#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
deleted file mode 100644
index 8cca95193d4d..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear.h
- *
- * SPEAr3xx Machine family specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_SPEAR3XX_H
-#define __MACH_SPEAR3XX_H
-#include <asm/memory.h>
-/* ICM1 - Low speed connection */
-#define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_2_BASE         UL(0xFD000000)
-#define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE      (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
-/* ML1 - Multi Layer CPU Subsystem */
-#define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
-#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
-/* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
-#define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
-#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR3XX_ICM1_UART_BASE
-/* Sysctl base for spear platform */
-#define SPEAR_SYS_CTRL_BASE             SPEAR3XX_ICM3_SYS_CTRL_BASE
-#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
-/* SPEAr320 Macros */
-#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
-#define VA_SPEAR320_SOC_CONFIG_BASE     UL(0xFE000000)
-#define SPEAR320_CONTROL_REG            IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
-#define SPEAR320_EXT_CTRL_REG           IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
-        #define SPEAR320_UARTX_PCLK_MASK                0x1
-        #define SPEAR320_UART2_PCLK_SHIFT               8
-        #define SPEAR320_UART3_PCLK_SHIFT               9
-        #define SPEAR320_UART4_PCLK_SHIFT               10
-        #define SPEAR320_UART5_PCLK_SHIFT               11
-        #define SPEAR320_UART6_PCLK_SHIFT               12
-        #define SPEAR320_RS485_PCLK_SHIFT               13
-#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h
deleted file mode 100644
index 9f5d08bd0c44..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/timex.h
- *
- * SPEAr3XX machine family specific timex definitions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-#include <plat/timex.h>
-#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h
deleted file mode 100644
index b909b011f7c8..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-#include <plat/uncompress.h>
-#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
deleted file mode 100644
index 339f397dea70..000000000000
--- a/arch/arm/mach-spear6xx/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# SPEAr6XX Machine configuration file
-#
-config MACH_SPEAR600
-        def_bool y
-        depends on ARCH_SPEAR6XX
-        select USE_OF
-        help
-          Supports ST SPEAr600 boards configured via the device-tree
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
deleted file mode 100644
index 898831d93f37..000000000000
--- a/arch/arm/mach-spear6xx/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for SPEAr6XX machine series
-#
-# common files
-obj-y   += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
deleted file mode 100644
index 4674a4c221db..000000000000
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y      += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S
deleted file mode 100644
index 0f3ea39edd96..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/debug-macro.S
- *
- * Debugging macro include header for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
deleted file mode 100644
index 65514b159370..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/generic.h
- *
- * SPEAr6XX machine family specific generic header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_GENERIC_H
-#define __MACH_GENERIC_H
-#include <linux/init.h>
-void __init spear_setup_of_timer(void);
-void spear_restart(char, const char *);
-void __init spear6xx_clk_init(void);
-#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
deleted file mode 100644
index c34acc201d34..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/misc_regs.h
- *
- * Miscellaneous registers definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_MISC_REGS_H
-#define __MACH_MISC_REGS_H
-#include <mach/spear.h>
-#define MISC_BASE               IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-#define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
deleted file mode 100644
index cb8ed2f4dc85..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/spear.h
- *
- * SPEAr6xx Machine family specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_SPEAR6XX_H
-#define __MACH_SPEAR6XX_H
-#include <asm/memory.h>
-/* ICM1 - Low speed connection */
-#define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_BASE           UL(0xFD000000)
-#define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE     (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
-/* ML-1, 2 - Multi Layer CPU Subsystem */
-#define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
-#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
-/* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
-#define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE
-#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR6XX_ICM1_UART0_BASE
-/* Sysctl base for spear platform */
-#define SPEAR_SYS_CTRL_BASE             SPEAR6XX_ICM3_SYS_CTRL_BASE
-#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR6XX_ICM3_SYS_CTRL_BASE
-#endif /* __MACH_SPEAR6XX_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h
deleted file mode 100644
index ac1c5b005695..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/timex.h
- *
- * SPEAr6XX machine family specific timex definitions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-#include <plat/timex.h>
-#endif  /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h
deleted file mode 100644
index 77f0765e21e1..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-#include <plat/uncompress.h>
-#endif  /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index dbc653ea851c..20c3b372cdf5 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -1,13 +1,30 @@
-if ARCH_TEGRA
+config ARCH_TEGRA
+        bool "NVIDIA Tegra" if ARCH_MULTI_V7
+        select ARCH_HAS_CPUFREQ
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select CLKSRC_OF
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_CLK
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        select SOC_BUS
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          This enables support for NVIDIA Tegra based systems.
-comment "NVIDIA Tegra options"
+menu "NVIDIA Tegra options"
+        depends on ARCH_TEGRA
 config ARCH_TEGRA_2x_SOC
        bool "Enable support for Tegra20 family"
        select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
        select ARM_ERRATA_720789
-        select ARM_ERRATA_742230 if SMP
-        select ARM_ERRATA_751472
        select ARM_ERRATA_754327 if SMP
        select ARM_ERRATA_764369 if SMP
        select ARM_GIC
@@ -26,8 +43,6 @@ config ARCH_TEGRA_2x_SOC
 config ARCH_TEGRA_3x_SOC
        bool "Enable support for Tegra30 family"
-        select ARM_ERRATA_743622
-        select ARM_ERRATA_751472
        select ARM_ERRATA_754322
        select ARM_ERRATA_764369 if SMP
        select ARM_GIC
@@ -71,4 +86,4 @@ config TEGRA_AHB
 config TEGRA_EMC_SCALING_ENABLE
        bool "Enable scaling the memory frequency"
-endif
+endmenu
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b78f0d71b328..d011f0ad49c4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,5 @@
+asflags-y                               += -march=armv7-a
 obj-y                                   += common.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
deleted file mode 100644
index 29433816233c..000000000000
--- a/arch/arm/mach-tegra/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)    += 0x00008000
-params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
-initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 60431de585ca..1787327fae3a 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -40,6 +40,7 @@ int tegra_clk_debugfs_init(void);
 static inline int tegra_clk_debugfs_init(void) { return 0; }
 #endif
+int __init tegra_powergate_init(void);
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS)
 int __init tegra_powergate_debugfs_init(void);
 #else
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index eb1f3c8c74cc..9f852c6fe5b9 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -27,8 +27,6 @@
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/powergate.h>
 #include "board.h"
 #include "common.h"
 #include "fuse.h"
diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h
deleted file mode 100644
index a44ccbdb7dbf..000000000000
--- a/arch/arm/mach-tegra/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/timex.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_TIMEX_H
-#define __MACH_TEGRA_TIMEX_H
-#define CLOCK_TICK_RATE         1000000
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
deleted file mode 100644
index 08386418196f..000000000000
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/uncompress.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 Google, Inc.
- * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *      Doug Anderson <dianders@chromium.org>
- *      Stephen Warren <swarren@nvidia.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_UNCOMPRESS_H
-#define __MACH_TEGRA_UNCOMPRESS_H
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-#include "../../iomap.h"
-#define BIT(x) (1 << (x))
-#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-#define DEBUG_UART_SHIFT 2
-volatile u8 *uart;
-static void putc(int c)
-{
-        if (uart == NULL)
-                return;
-        while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE))
-                barrier();
-        uart[UART_TX << DEBUG_UART_SHIFT] = c;
-}
-static inline void flush(void)
-{
-}
-static const struct {
-        u32 base;
-        u32 reset_reg;
-        u32 clock_reg;
-        u32 bit;
-} uarts[] = {
-        {
-                TEGRA_UARTA_BASE,
-                TEGRA_CLK_RESET_BASE + 0x04,
-                TEGRA_CLK_RESET_BASE + 0x10,
-                6,
-        },
-        {
-                TEGRA_UARTB_BASE,
-                TEGRA_CLK_RESET_BASE + 0x04,
-                TEGRA_CLK_RESET_BASE + 0x10,
-                7,
-        },
-        {
-                TEGRA_UARTC_BASE,
-                TEGRA_CLK_RESET_BASE + 0x08,
-                TEGRA_CLK_RESET_BASE + 0x14,
-                23,
-        },
-        {
-                TEGRA_UARTD_BASE,
-                TEGRA_CLK_RESET_BASE + 0x0c,
-                TEGRA_CLK_RESET_BASE + 0x18,
-                1,
-        },
-        {
-                TEGRA_UARTE_BASE,
-                TEGRA_CLK_RESET_BASE + 0x0c,
-                TEGRA_CLK_RESET_BASE + 0x18,
-                2,
-        },
-};
-static inline bool uart_clocked(int i)
-{
-        if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit))
-                return false;
-        if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit)))
-                return false;
-        return true;
-}
-#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
-int auto_odmdata(void)
-{
-        volatile u32 *pmc = (volatile u32 *)TEGRA_PMC_BASE;
-        u32 odmdata = pmc[0xa0 / 4];
-        /*
-         * Bits 19:18 are the console type: 0=default, 1=none, 2==DCC, 3==UART
-         * Some boards apparently swap the last two values, but we don't have
-         * any way of catering for that here, so we just accept either. If this
-         * doesn't make sense for your board, just don't enable this feature.
-         *
-         * Bits 17:15 indicate the UART to use, 0/1/2/3/4 are UART A/B/C/D/E.
-         */
-        switch  ((odmdata >> 18) & 3) {
-        case 2:
-        case 3:
-                break;
-        default:
-                return -1;
-        }
-        return (odmdata >> 15) & 7;
-}
-#endif
-/*
- * Setup before decompression.  This is where we do UART selection for
- * earlyprintk and init the uart_base register.
- */
-static inline void arch_decomp_setup(void)
-{
-        int uart_id;
-        volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
-        u32 chip, div;
-#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
-        uart_id = auto_odmdata();
-#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-        uart_id = 0;
-#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-        uart_id = 1;
-#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-        uart_id = 2;
-#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-        uart_id = 3;
-#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-        uart_id = 4;
-#endif
-        if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
-            !uart_clocked(uart_id))
-                uart = NULL;
-        else
-                uart = (volatile u8 *)uarts[uart_id].base;
-        if (uart == NULL)
-                return;
-        chip = (apb_misc[0x804 / 4] >> 8) & 0xff;
-        if (chip == 0x20)
-                div = 0x0075;
-        else
-                div = 0x00dd;
-        uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB;
-        uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff;
-        uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8;
-        uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
-}
-#endif
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index b60165f1ca02..46144a19a7e7 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -34,12 +34,11 @@
 #include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/clk/tegra.h>
+#include <linux/tegra-powergate.h>
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
-#include <mach/powergate.h>
 #include "board.h"
 #include "iomap.h"
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index af9067e2867c..f076f0f80fcd 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -28,8 +28,7 @@
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/clk/tegra.h>
+#include <linux/tegra-powergate.h>
-#include <mach/powergate.h>
 #include "fuse.h"
 #include "iomap.h"
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 3e5bbd0e5b23..f66d7deae46d 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -1,3 +1,19 @@
+config ARCH_U8500
+        bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7
+        depends on MMU
+        select ARCH_HAS_CPUFREQ
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select CLKDEV_LOOKUP
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        help
+          Support for ST-Ericsson's Ux500 architecture
 if ARCH_U8500
 config UX500_SOC_COMMON
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index f24710dfc395..bf9b6be5b180 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,7 +3,7 @@
 #
 obj-y                           := cpu.o devices.o devices-common.o \
-                                   id.o usb.o timer.o
+                                   id.o usb.o timer.o pm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
@@ -15,3 +15,5 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
                                board-mop500-audio.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+CFLAGS_hotplug.o                += -march=armv7-a
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 7209db7cdc72..aba9e5692958 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -10,10 +10,9 @@
 #include <linux/platform_data/pinctrl-nomadik.h>
 #include <linux/platform_data/dma-ste-dma40.h>
-#include <mach/devices.h>
+#include "devices.h"
-#include <mach/hardware.h>
+#include "irqs.h"
-#include <mach/irqs.h>
+#include <linux/platform_data/asoc-ux500-msp.h>
-#include <mach/msp.h>
 #include "ste-dma40-db8500.h"
 #include "board-mop500.h"
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 0a3f30df1eb8..f3976f9c404a 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -13,8 +13,6 @@
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 #include "pins-db8500.h"
 #include "board-mop500.h"
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 6db0740128de..0ef38775a0c1 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -14,9 +14,9 @@
 #include <linux/platform_data/dma-ste-dma40.h>
 #include <asm/mach-types.h>
-#include <mach/devices.h>
+#include "devices.h"
-#include <mach/hardware.h>
+#include "db8500-regs.h"
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "ste-dma40-db8500.h"
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
index ead91c968ff4..d397c19570af 100644
--- a/arch/arm/mach-ux500/board-mop500-u8500uib.c
+++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c
@@ -12,12 +12,15 @@
 #include <linux/mfd/tc3589x.h>
 #include <linux/input/matrix_keypad.h>
-#include <mach/irqs.h>
+#include "irqs.h"
 #include "board-mop500.h"
-/* Dummy data that can be overridden by staging driver */
+static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
-struct i2c_board_info __initdata __weak mop500_i2c3_devices_u8500[] = {
+        {
+                I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
+                .irq = NOMADIK_GPIO_TO_IRQ(84),
+        },
 };
 /*
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
index 7037d3687e9f..bdaa422da028 100644
--- a/arch/arm/mach-ux500/board-mop500-uib.c
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -11,7 +11,6 @@
 #include <linux/init.h>
 #include <linux/i2c.h>
-#include <mach/hardware.h>
 #include "board-mop500.h"
 #include "id.h"
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 574916b70b2e..a15dd6b63a8f 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -44,13 +44,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/hardware.h>
+#include "setup.h"
-#include <mach/setup.h>
+#include "devices.h"
-#include <mach/devices.h>
+#include "irqs.h"
-#include <mach/irqs.h>
 #include <linux/platform_data/crypto-ux500.h>
 #include "ste-dma40-db8500.h"
+#include "db8500-regs.h"
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
@@ -237,63 +237,6 @@ struct ab8500_platform_data ab8500_platdata = {
        .codec          = &ab8500_codec_pdata,
 };
-/*
- * Thermal Sensor
- */
-static struct resource db8500_thsens_resources[] = {
-        {
-                .name = "IRQ_HOTMON_LOW",
-                .start  = IRQ_PRCMU_HOTMON_LOW,
-                .end    = IRQ_PRCMU_HOTMON_LOW,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .name = "IRQ_HOTMON_HIGH",
-                .start  = IRQ_PRCMU_HOTMON_HIGH,
-                .end    = IRQ_PRCMU_HOTMON_HIGH,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct db8500_thsens_platform_data db8500_thsens_data = {
-        .trip_points[0] = {
-                .temp = 70000,
-                .type = THERMAL_TRIP_ACTIVE,
-                .cdev_name = {
-                        [0] = "thermal-cpufreq-0",
-                },
-        },
-        .trip_points[1] = {
-                .temp = 75000,
-                .type = THERMAL_TRIP_ACTIVE,
-                .cdev_name = {
-                        [0] = "thermal-cpufreq-0",
-                },
-        },
-        .trip_points[2] = {
-                .temp = 80000,
-                .type = THERMAL_TRIP_ACTIVE,
-                .cdev_name = {
-                        [0] = "thermal-cpufreq-0",
-                },
-        },
-        .trip_points[3] = {
-                .temp = 85000,
-                .type = THERMAL_TRIP_CRITICAL,
-        },
-        .num_trips = 4,
-};
-static struct platform_device u8500_thsens_device = {
-        .name           = "db8500-thermal",
-        .resource       = db8500_thsens_resources,
-        .num_resources  = ARRAY_SIZE(db8500_thsens_resources),
-        .dev    = {
-                .platform_data  = &db8500_thsens_data,
-        },
-};
 static struct platform_device u8500_cpufreq_cooling_device = {
        .name           = "db8500-cpufreq-cooling",
 };
@@ -663,7 +606,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
        &snowball_key_dev,
        &snowball_sbnet_dev,
        &snowball_gpio_en_3v3_regulator_dev,
-        &u8500_thsens_device,
        &u8500_cpufreq_cooling_device,
        &sdi0_regulator,
 };
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index d38951be70df..49514b825034 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -8,8 +8,8 @@
 #define __BOARD_MOP500_H
 /* For NOMADIK_NR_GPIO */
-#include <mach/irqs.h>
+#include "irqs.h"
-#include <mach/msp.h>
+#include <linux/platform_data/asoc-ux500-msp.h>
 #include <linux/amba/mmci.h>
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index f815efe54c73..f58615b5c601 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -9,8 +9,8 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/hardware.h>
+#include "db8500-regs.h"
 #include "id.h"
 static void __iomem *l2x0_base;
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 5c6c2e633868..995928ba22fd 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -28,15 +28,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
-#include <mach/hardware.h>
+#include "setup.h"
-#include <mach/setup.h>
+#include "devices.h"
-#include <mach/devices.h>
+#include "irqs.h"
-#include <mach/db8500-regs.h>
-#include <mach/irqs.h>
 #include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
+#include "db8500-regs.h"
 #include "board-mop500.h"
 #include "id.h"
@@ -94,8 +92,6 @@ void __init u8500_map_io(void)
                iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
        else
                iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
-        _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
 }
 static struct resource db8500_pmu_resources[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 537870d3fea8..915e2636cbaa 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/mfd/db8500-prcmu.h>
+#include <linux/mfd/dbx500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/sys_soc.h>
 #include <linux/err.h>
@@ -20,18 +20,17 @@
 #include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-ux500.h>
+#include <linux/platform_data/arm-ux500-pm.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "setup.h"
-#include <mach/setup.h>
+#include "devices.h"
-#include <mach/devices.h>
 #include "board-mop500.h"
+#include "db8500-regs.h"
 #include "id.h"
-void __iomem *_PRCMU_BASE;
 /*
 * FIXME: Should we set up the GPIO domain here?
 *
@@ -68,13 +67,23 @@ void __init ux500_init_irq(void)
         * Init clocks here so that they are available for system timer
         * initialization.
         */
-        if (cpu_is_u8500_family() || cpu_is_u9540())
+        if (cpu_is_u8500_family()) {
-                db8500_prcmu_early_init();
+                prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
+                ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
-        if (cpu_is_u8500_family() || cpu_is_u9540())
+                u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
-                u8500_clk_init();
+                               U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
-        else if (cpu_is_u8540())
+                               U8500_CLKRST6_BASE);
+        } else if (cpu_is_u9540()) {
+                prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
+                ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
+                u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                               U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+                               U8500_CLKRST6_BASE);
+        } else if (cpu_is_u8540()) {
+                prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
+                ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
                u8540_clk_init();
+        }
 }
 void __init ux500_init_late(void)
diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c
index 488e07472d98..317a2be129fb 100644
--- a/arch/arm/mach-ux500/cpuidle.c
+++ b/arch/arm/mach-ux500/cpuidle.c
@@ -15,10 +15,13 @@
 #include <linux/atomic.h>
 #include <linux/smp.h>
 #include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/arm-ux500-pm.h>
 #include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
+#include "db8500-regs.h"
 static atomic_t master = ATOMIC_INIT(0);
 static DEFINE_SPINLOCK(master_lock);
@@ -111,7 +114,7 @@ static struct cpuidle_driver ux500_idle_driver = {
 int __init ux500_idle_init(void)
 {
-        /* Configure wake up reasons */
+        /* Configure wake up reasons */
        prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
                             PRCMU_WAKEUP(ABB));
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h
index 1530d493879d..b2d7a0b98629 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/db8500-regs.h
@@ -170,4 +170,32 @@
 /* SoC identification number information */
 #define U8500_BB_UID_BASE      (U8500_BACKUPRAM1_BASE + 0xFC0)
+/* Offsets to specific addresses in some IP blocks for DMA */
+#define MSP_TX_RX_REG_OFFSET    0
+#define CRYP1_RX_REG_OFFSET     0x10
+#define CRYP1_TX_REG_OFFSET     0x8
+#define HASH1_TX_REG_OFFSET     0x4
+/*
+ * Macros to get at IO space when running virtually
+ * We dont map all the peripherals, let ioremap do
+ * this for us. We map only very basic peripherals here.
+ */
+#define U8500_IO_VIRTUAL        0xf0000000
+#define U8500_IO_PHYSICAL       0xa0000000
+/* This is where we map in the ROM to check ASIC IDs */
+#define UX500_VIRT_ROM          0xf0000000
+/* This macro is used in assembly, so no cast */
+#define IO_ADDRESS(x)           \
+        (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
+/* typesafe io address */
+#define __io_address(n)         IOMEM(IO_ADDRESS(n))
+/* Used by some plat-nomadik code */
+#define io_p2v(n)               __io_address(n)
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 #endif
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index 16b5f71e6974..f71b3d7bd4fb 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -13,8 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
-#include <mach/hardware.h>
+#include "irqs.h"
-#include <mach/irqs.h>
 #include "devices-common.h"
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index f3d9419f75d3..1cf94ce0feec 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -15,10 +15,10 @@
 #include <linux/platform_data/dma-ste-dma40.h>
 #include <linux/mfd/dbx500-prcmu.h>
-#include <mach/hardware.h>
+#include "setup.h"
-#include <mach/setup.h>
+#include "irqs.h"
-#include <mach/irqs.h>
+#include "db8500-regs.h"
 #include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
@@ -199,6 +199,8 @@ struct platform_device u8500_ske_keypad_device = {
 struct prcmu_pdata db8500_prcmu_pdata = {
        .ab_platdata    = &ab8500_platdata,
+        .ab_irq         = IRQ_DB8500_AB8500,
+        .irq_base       = IRQ_PRCMU_BASE,
        .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
        .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
 };
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index dbcb35c48f06..321998320f98 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -9,7 +9,8 @@
 #define __DEVICES_DB8500_H
 #include <linux/platform_data/usb-musb-ux500.h>
-#include <mach/irqs.h>
+#include "irqs.h"
+#include "db8500-regs.h"
 #include "devices-common.h"
 struct ske_keypad_platform_data;
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
index ea0a2f92ca70..0f9e52b95935 100644
--- a/arch/arm/mach-ux500/devices.c
+++ b/arch/arm/mach-ux500/devices.c
@@ -11,8 +11,9 @@
 #include <linux/io.h>
 #include <linux/amba/bus.h>
-#include <mach/hardware.h>
+#include "setup.h"
-#include <mach/setup.h>
+#include "db8500-regs.h"
 void __init amba_add_devices(struct amba_device *devs[], int num)
 {
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/devices.h
index cbc6f1e4104d..cbc6f1e4104d 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/devices.h
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index 2f6af259015d..87abcf278432 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -15,7 +15,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-#include <mach/setup.h>
+#include "setup.h"
 /*
 * platform-specific code to shutdown a CPU
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index 9f951842e1e5..0d33d1a06955 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -14,9 +14,9 @@
 #include <asm/cacheflush.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "setup.h"
-#include <mach/setup.h>
+#include "db8500-regs.h"
 #include "id.h"
 struct dbx500_asic_id dbx500_id;
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
deleted file mode 100644
index 67035223334a..000000000000
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Debugging macro include header
- *
- *  Copyright (C) 2009 ST-Ericsson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <mach/hardware.h>
-#if CONFIG_UX500_DEBUG_UART > 2
-#error Invalid Ux500 debug UART
-#endif
-/*
- * DEBUG_LL only works if only one SOC is built in.  We don't use #else below
- * in order to get "__UX500_UART redefined" warnings if more than one SOC is
- * built, so that there's some hint during the build that something is wrong.
- */
-#ifdef CONFIG_UX500_SOC_DB8500
-#define __UX500_UART(n) U8500_UART##n##_BASE
-#endif
-#ifndef __UX500_UART
-#error Unknown SOC
-#endif
-#define UX500_UART(n)   __UX500_UART(n)
-#define UART_BASE       UX500_UART(CONFIG_UX500_DEBUG_UART)
-        .macro  addruart, rp, rv, tmp
-        ldr     \rp, =UART_BASE                         @ no, physical address
-        ldr     \rv, =IO_ADDRESS(UART_BASE)             @ yes, virtual address
-        .endm
-#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
deleted file mode 100644
index 5201ddace503..000000000000
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson.
- *
- * U8500 hardware definitions
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-/*
- * Macros to get at IO space when running virtually
- * We dont map all the peripherals, let ioremap do
- * this for us. We map only very basic peripherals here.
- */
-#define U8500_IO_VIRTUAL        0xf0000000
-#define U8500_IO_PHYSICAL       0xa0000000
-/* This is where we map in the ROM to check ASIC IDs */
-#define UX500_VIRT_ROM          0xf0000000
-/* This macro is used in assembly, so no cast */
-#define IO_ADDRESS(x)           \
-        (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
-/* typesafe io address */
-#define __io_address(n)         IOMEM(IO_ADDRESS(n))
-/* Used by some plat-nomadik code */
-#define io_p2v(n)               __io_address(n)
-#include <mach/db8500-regs.h>
-#define MSP_TX_RX_REG_OFFSET    0
-#define CRYP1_RX_REG_OFFSET     0x10
-#define CRYP1_TX_REG_OFFSET     0x8
-#define HASH1_TX_REG_OFFSET     0x4
-#ifndef __ASSEMBLY__
-extern void __iomem *_PRCMU_BASE;
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
-#endif                          /* __ASSEMBLY__ */
-#endif                          /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/timex.h b/arch/arm/mach-ux500/include/mach/timex.h
deleted file mode 100644
index d0942c174018..000000000000
--- a/arch/arm/mach-ux500/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-#define CLOCK_TICK_RATE         110000000
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
deleted file mode 100644
index 36969d52e53a..000000000000
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *  Copyright (C) 2009 ST-Ericsson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <linux/io.h>
-#include <linux/amba/serial.h>
-#include <mach/hardware.h>
-void __iomem *ux500_uart_base;
-static void putc(const char c)
-{
-        /* Do nothing if the UART is not enabled. */
-        if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
-                return;
-        if (c == '\n')
-                putc('\r');
-        while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5))
-                barrier();
-        __raw_writeb(c, ux500_uart_base + UART01x_DR);
-}
-static void flush(void)
-{
-        if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
-                return;
-        while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3))
-                barrier();
-}
-static inline void arch_decomp_setup(void)
-{
-        /* Use machine_is_foo() macro if you need to switch base someday */
-        ux500_uart_base = (void __iomem *)U8500_UART2_BASE;
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/irqs-board-mop500.h
index d526dd8e87d3..d526dd8e87d3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/irqs-board-mop500.h
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/irqs-db8500.h
index 68bc14974608..f3a9d5947ef3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h
+++ b/arch/arm/mach-ux500/irqs-db8500.h
@@ -109,31 +109,6 @@
 /* Virtual interrupts corresponding to the PRCMU wakeups.  */
 #define IRQ_PRCMU_BASE IRQ_SOC_START
-#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE)
-#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE)
-#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1)
-#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2)
-#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3)
-#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4)
-#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5)
-#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6)
-#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7)
-#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8)
-#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9)
-#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10)
-#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11)
-#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12)
-#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13)
-#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14)
-#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15)
-#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16)
-#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17)
-#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18)
-#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19)
-#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20)
-#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21)
-#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22)
 #define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
 /*
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/irqs.h
index fc77b4274c8d..15b2af698ed7 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/irqs.h
@@ -10,8 +10,6 @@
 #ifndef ASM_ARCH_IRQS_H
 #define ASM_ARCH_IRQS_H
-#include <mach/hardware.h>
 #define IRQ_LOCALTIMER                  29
 #define IRQ_LOCALWDOG                   30
@@ -36,14 +34,14 @@
 /* This will be overridden by SoC-specific irq headers */
 #define IRQ_SOC_END             IRQ_SOC_START
-#include <mach/irqs-db8500.h>
+#include "irqs-db8500.h"
 #define IRQ_BOARD_START         IRQ_SOC_END
 /* This will be overridden by board-specific irq headers */
 #define IRQ_BOARD_END           IRQ_BOARD_START
 #ifdef CONFIG_MACH_MOP500
-#include <mach/irqs-board-mop500.h>
+#include "irqs-board-mop500.h"
 #endif
 #define UX500_NR_IRQS           IRQ_BOARD_END
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 152b1309b9af..14d90469392f 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -21,9 +21,9 @@
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <mach/hardware.h>
+#include "setup.h"
-#include <mach/setup.h>
+#include "db8500-regs.h"
 #include "id.h"
 /* This is called from headsmp.S to wakeup the secondary core */
diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c
new file mode 100644
index 000000000000..1a468f0fd22e
--- /dev/null
+++ b/arch/arm/mach-ux500/pm.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010-2013
+ * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
+ *         ST-Ericsson.
+ * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/platform_data/arm-ux500-pm.h>
+#include "db8500-regs.h"
+/* ARM WFI Standby signal register */
+#define PRCM_ARM_WFI_STANDBY    (prcmu_base + 0x130)
+#define PRCM_ARM_WFI_STANDBY_WFI0               0x08
+#define PRCM_ARM_WFI_STANDBY_WFI1               0x10
+#define PRCM_IOCR               (prcmu_base + 0x310)
+#define PRCM_IOCR_IOFORCE                       0x1
+/* Dual A9 core interrupt management unit registers */
+#define PRCM_A9_MASK_REQ        (prcmu_base + 0x328)
+#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ       0x1
+#define PRCM_A9_MASK_ACK        (prcmu_base + 0x32c)
+#define PRCM_ARMITMSK31TO0      (prcmu_base + 0x11c)
+#define PRCM_ARMITMSK63TO32     (prcmu_base + 0x120)
+#define PRCM_ARMITMSK95TO64     (prcmu_base + 0x124)
+#define PRCM_ARMITMSK127TO96    (prcmu_base + 0x128)
+#define PRCM_POWER_STATE_VAL    (prcmu_base + 0x25C)
+#define PRCM_ARMITVAL31TO0      (prcmu_base + 0x260)
+#define PRCM_ARMITVAL63TO32     (prcmu_base + 0x264)
+#define PRCM_ARMITVAL95TO64     (prcmu_base + 0x268)
+#define PRCM_ARMITVAL127TO96    (prcmu_base + 0x26C)
+static void __iomem *prcmu_base;
+/* This function decouple the gic from the prcmu */
+int prcmu_gic_decouple(void)
+{
+        u32 val = readl(PRCM_A9_MASK_REQ);
+        /* Set bit 0 register value to 1 */
+        writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
+               PRCM_A9_MASK_REQ);
+        /* Make sure the register is updated */
+        readl(PRCM_A9_MASK_REQ);
+        /* Wait a few cycles for the gic mask completion */
+        udelay(1);
+        return 0;
+}
+/* This function recouple the gic with the prcmu */
+int prcmu_gic_recouple(void)
+{
+        u32 val = readl(PRCM_A9_MASK_REQ);
+        /* Set bit 0 register value to 0 */
+        writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
+        return 0;
+}
+#define PRCMU_GIC_NUMBER_REGS 5
+/*
+ * This function checks if there are pending irq on the gic. It only
+ * makes sense if the gic has been decoupled before with the
+ * db8500_prcmu_gic_decouple function. Disabling an interrupt only
+ * disables the forwarding of the interrupt to any CPU interface. It
+ * does not prevent the interrupt from changing state, for example
+ * becoming pending, or active and pending if it is already
+ * active. Hence, we have to check the interrupt is pending *and* is
+ * active.
+ */
+bool prcmu_gic_pending_irq(void)
+{
+        u32 pr; /* Pending register */
+        u32 er; /* Enable register */
+        void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
+        int i;
+        /* 5 registers. STI & PPI not skipped */
+        for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
+                pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
+                er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
+                if (pr & er)
+                        return true; /* There is a pending interrupt */
+        }
+        return false;
+}
+/*
+ * This function checks if there are pending interrupt on the
+ * prcmu which has been delegated to monitor the irqs with the
+ * db8500_prcmu_copy_gic_settings function.
+ */
+bool prcmu_pending_irq(void)
+{
+        u32 it, im;
+        int i;
+        for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
+                it = readl(PRCM_ARMITVAL31TO0 + i * 4);
+                im = readl(PRCM_ARMITMSK31TO0 + i * 4);
+                if (it & im)
+                        return true; /* There is a pending interrupt */
+        }
+        return false;
+}
+/*
+ * This function checks if the specified cpu is in in WFI. It's usage
+ * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
+ * function. Of course passing smp_processor_id() to this function will
+ * always return false...
+ */
+bool prcmu_is_cpu_in_wfi(int cpu)
+{
+        return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
+                     PRCM_ARM_WFI_STANDBY_WFI0;
+}
+/*
+ * This function copies the gic SPI settings to the prcmu in order to
+ * monitor them and abort/finish the retention/off sequence or state.
+ */
+int prcmu_copy_gic_settings(void)
+{
+        u32 er; /* Enable register */
+        void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
+        int i;
+        /* We skip the STI and PPI */
+        for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
+                er = readl_relaxed(dist_base +
+                                   GIC_DIST_ENABLE_SET + (i + 1) * 4);
+                writel(er, PRCM_ARMITMSK31TO0 + i * 4);
+        }
+        return 0;
+}
+void __init ux500_pm_init(u32 phy_base, u32 size)
+{
+        prcmu_base = ioremap(phy_base, size);
+        if (!prcmu_base) {
+                pr_err("could not remap PRCMU for PM functions\n");
+                return;
+        }
+        /*
+         * On watchdog reboot the GIC is in some cases decoupled.
+         * This will make sure that the GIC is correctly configured.
+         */
+        prcmu_gic_recouple();
+}
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/setup.h
index bddce2b49372..bddce2b49372 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/setup.h
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index d07bbe7f04a6..b6bd0efcbe64 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -14,10 +14,10 @@
 #include <asm/smp_twd.h>
-#include <mach/setup.h>
+#include "setup.h"
-#include <mach/hardware.h>
+#include "irqs.h"
-#include <mach/irqs.h>
+#include "db8500-regs.h"
 #include "id.h"
 #ifdef CONFIG_HAVE_ARM_TWD
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 78ac65f62e87..2dfc72f7cd8a 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -10,7 +10,7 @@
 #include <linux/platform_data/usb-musb-ux500.h>
 #include <linux/platform_data/dma-ste-dma40.h>
-#include <mach/hardware.h>
+#include "db8500-regs.h"
 #define MUSB_DMA40_RX_CH { \
                .mode = STEDMA40_MODE_LOGICAL, \
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 0f1c5e53fb27..5907e10c37fd 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -9,6 +9,8 @@ config ARCH_VEXPRESS
        select COMMON_CLK_VERSATILE
        select CPU_V7
        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_CLK
        select HAVE_PATA_PLATFORM
        select HAVE_SMP
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index adb6c0ea0e53..138b5891f4ef 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -5,6 +5,8 @@ config ARCH_ZYNQ
        select COMMON_CLK
        select CPU_V7
        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select ICST
        select MIGHT_HAVE_CACHE_L2X0
        select USE_OF
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 03db14d8ace9..f55d3f9b508d 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -879,51 +879,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
 }
 #endif /* CONFIG_PLAT_S3C24XX */
-/* MFC */
-#ifdef CONFIG_S5P_DEV_MFC
-static struct resource s5p_mfc_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
-        [1] = DEFINE_RES_IRQ(IRQ_MFC),
-};
-struct platform_device s5p_device_mfc = {
-        .name           = "s5p-mfc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_mfc_resource),
-        .resource       = s5p_mfc_resource,
-};
-/*
- * MFC hardware has 2 memory interfaces which are modelled as two separate
- * platform devices to let dma-mapping distinguish between them.
- *
- * MFC parent device (s5p_device_mfc) must be registered before memory
- * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
- */
-struct platform_device s5p_device_mfc_l = {
-        .name           = "s5p-mfc-l",
-        .id             = -1,
-        .dev            = {
-                .parent                 = &s5p_device_mfc.dev,
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-struct platform_device s5p_device_mfc_r = {
-        .name           = "s5p-mfc-r",
-        .id             = -1,
-        .dev            = {
-                .parent                 = &s5p_device_mfc.dev,
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-#endif /* CONFIG_S5P_DEV_MFC */
 /* MIPI CSIS */
 #ifdef CONFIG_S5P_DEV_CSIS0
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 5560586abec0..ce1d0f785efd 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -18,62 +18,9 @@
 #ifndef __PLAT_S3C_SDHCI_H
 #define __PLAT_S3C_SDHCI_H __FILE__
+#include <linux/platform_data/mmc-sdhci-s3c.h>
 #include <plat/devs.h>
-struct platform_device;
-struct mmc_host;
-struct mmc_card;
-struct mmc_ios;
-enum cd_types {
-        S3C_SDHCI_CD_INTERNAL,  /* use mmc internal CD line */
-        S3C_SDHCI_CD_EXTERNAL,  /* use external callback */
-        S3C_SDHCI_CD_GPIO,      /* use external gpio pin for CD line */
-        S3C_SDHCI_CD_NONE,      /* no CD line, use polling to detect card */
-        S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
-};
-/**
- * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
- * @max_width: The maximum number of data bits supported.
- * @host_caps: Standard MMC host capabilities bit field.
- * @host_caps2: The second standard MMC host capabilities bit field.
- * @cd_type: Type of Card Detection method (see cd_types enum above)
- * @ext_cd_init: Initialize external card detect subsystem. Called on
- *               sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
- *               notify_func argument is a callback to the sdhci-s3c driver
- *               that triggers the card detection event. Callback arguments:
- *               dev is pointer to platform device of the host controller,
- *               state is new state of the card (0 - removed, 1 - inserted).
- * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on
- *               sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL.
- *               notify_func argument is the same callback as for ext_cd_init.
- * @ext_cd_gpio: gpio pin used for external CD line, valid only if
- *               cd_type == S3C_SDHCI_CD_GPIO
- * @ext_cd_gpio_invert: invert values for external CD gpio line
- * @cfg_gpio: Configure the GPIO for a specific card bit-width
- *
- * Initialisation data specific to either the machine or the platform
- * for the device driver to use or call-back when configuring gpio or
- * card speed information.
-*/
-struct s3c_sdhci_platdata {
-        unsigned int    max_width;
-        unsigned int    host_caps;
-        unsigned int    host_caps2;
-        unsigned int    pm_caps;
-        enum cd_types   cd_type;
-        int             ext_cd_gpio;
-        bool            ext_cd_gpio_invert;
-        int     (*ext_cd_init)(void (*notify_func)(struct platform_device *,
-                                                   int state));
-        int     (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
-                                                      int state));
-        void    (*cfg_gpio)(struct platform_device *dev, int width);
-};
 /* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
 * @pd: The default platform data for this device.
 * @set: Pointer to the platform data to fill in.
@@ -378,5 +325,4 @@ static inline void s3c_sdhci_setname(int id, char *name)
                break;
        }
 }
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index 5d205e74e495..0fceb4273824 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -20,6 +20,7 @@
 #include <linux/io.h>
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/irq-vic-timer.h>
 #include <plat/regs-timer.h>
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 002b1472293b..53210ec4e8ec 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -27,6 +27,7 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-irq.h>
+#include <mach/irqs.h>
 #include <asm/irq.h>
 #include <plat/pm.h>
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index 5ec104b5408b..a93fb6fb6606 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -18,10 +18,50 @@
 #include <linux/of.h>
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <plat/devs.h>
-#include <plat/irqs.h>
 #include <plat/mfc.h>
+static struct resource s5p_mfc_resource[] = {
+        [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
+        [1] = DEFINE_RES_IRQ(IRQ_MFC),
+};
+struct platform_device s5p_device_mfc = {
+        .name           = "s5p-mfc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_mfc_resource),
+        .resource       = s5p_mfc_resource,
+};
+/*
+ * MFC hardware has 2 memory interfaces which are modelled as two separate
+ * platform devices to let dma-mapping distinguish between them.
+ *
+ * MFC parent device (s5p_device_mfc) must be registered before memory
+ * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
+ */
+struct platform_device s5p_device_mfc_l = {
+        .name           = "s5p-mfc-l",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_device_mfc_l.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+struct platform_device s5p_device_mfc_r = {
+        .name           = "s5p-mfc-r",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_device_mfc_r.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
 struct s5p_mfc_reserved_mem {
        phys_addr_t     base;
        unsigned long   size;
diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c
index 103e371f5e35..ff1a76011b1e 100644
--- a/arch/arm/plat-samsung/s5p-irq.c
+++ b/arch/arm/plat-samsung/s5p-irq.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
+#include <mach/irqs.h>
 #include <mach/map.h>
 #include <plat/regs-timer.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
deleted file mode 100644
index 8a08c31b5e20..000000000000
--- a/arch/arm/plat-spear/Kconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# SPEAr Platform configuration file
-#
-if PLAT_SPEAR
-choice
-        prompt "ST SPEAr Family"
-        default ARCH_SPEAR3XX
-config ARCH_SPEAR13XX
-        bool "ST SPEAr13xx with Device Tree"
-        select ARCH_HAS_CPUFREQ
-        select ARM_GIC
-        select CPU_V7
-        select GPIO_SPEAR_SPICS
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-        select PINCTRL
-        select USE_OF
-        help
-          Supports for ARM's SPEAR13XX family
-config ARCH_SPEAR3XX
-        bool "ST SPEAr3xx with Device Tree"
-        select ARM_VIC
-        select CPU_ARM926T
-        select PINCTRL
-        select USE_OF
-        help
-          Supports for ARM's SPEAR3XX family
-config ARCH_SPEAR6XX
-        bool "SPEAr6XX"
-        select ARM_VIC
-        select CPU_ARM926T
-        help
-          Supports for ARM's SPEAR6XX family
-endchoice
-# Adding SPEAr machine specific configuration files
-source "arch/arm/mach-spear13xx/Kconfig"
-source "arch/arm/mach-spear3xx/Kconfig"
-source "arch/arm/mach-spear6xx/Kconfig"
-endif
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
deleted file mode 100644
index 01e88532a5db..000000000000
--- a/arch/arm/plat-spear/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# SPEAr Platform specific Makefile
-#
-# Common support
-obj-y   := restart.o time.o
-obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o
-obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index ed9af4278619..aedbbe12f321 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -17,12 +17,10 @@
 #include <linux/io.h>
 #include <linux/of_platform.h>
 #include <linux/spinlock_types.h>
-#include <mach/spear.h>
 #include "clk.h"
-#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
 /* PLL related registers and bit values */
-#define SPEAR1310_PLL_CFG                       (VA_MISC_BASE + 0x210)
+#define SPEAR1310_PLL_CFG                       (misc_base + 0x210)
        /* PLL_CFG bit values */
        #define SPEAR1310_CLCD_SYNT_CLK_MASK            1
        #define SPEAR1310_CLCD_SYNT_CLK_SHIFT           31
@@ -35,15 +33,15 @@
        #define SPEAR1310_PLL2_CLK_SHIFT                22
        #define SPEAR1310_PLL1_CLK_SHIFT                20
-#define SPEAR1310_PLL1_CTR                      (VA_MISC_BASE + 0x214)
+#define SPEAR1310_PLL1_CTR                      (misc_base + 0x214)
-#define SPEAR1310_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
+#define SPEAR1310_PLL1_FRQ                      (misc_base + 0x218)
-#define SPEAR1310_PLL2_CTR                      (VA_MISC_BASE + 0x220)
+#define SPEAR1310_PLL2_CTR                      (misc_base + 0x220)
-#define SPEAR1310_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
+#define SPEAR1310_PLL2_FRQ                      (misc_base + 0x224)
-#define SPEAR1310_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
+#define SPEAR1310_PLL3_CTR                      (misc_base + 0x22C)
-#define SPEAR1310_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
+#define SPEAR1310_PLL3_FRQ                      (misc_base + 0x230)
-#define SPEAR1310_PLL4_CTR                      (VA_MISC_BASE + 0x238)
+#define SPEAR1310_PLL4_CTR                      (misc_base + 0x238)
-#define SPEAR1310_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
+#define SPEAR1310_PLL4_FRQ                      (misc_base + 0x23C)
-#define SPEAR1310_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
+#define SPEAR1310_PERIP_CLK_CFG                 (misc_base + 0x244)
        /* PERIP_CLK_CFG bit values */
        #define SPEAR1310_GPT_OSC24_VAL                 0
        #define SPEAR1310_GPT_APB_VAL                   1
@@ -65,7 +63,7 @@
        #define SPEAR1310_C3_CLK_MASK                   1
        #define SPEAR1310_C3_CLK_SHIFT                  1
-#define SPEAR1310_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
+#define SPEAR1310_GMAC_CLK_CFG                  (misc_base + 0x248)
        #define SPEAR1310_GMAC_PHY_IF_SEL_MASK          3
        #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT         4
        #define SPEAR1310_GMAC_PHY_CLK_MASK             1
@@ -73,7 +71,7 @@
        #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK       2
        #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT      1
-#define SPEAR1310_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
+#define SPEAR1310_I2S_CLK_CFG                   (misc_base + 0x24C)
        /* I2S_CLK_CFG register mask */
        #define SPEAR1310_I2S_SCLK_X_MASK               0x1F
        #define SPEAR1310_I2S_SCLK_X_SHIFT              27
@@ -91,21 +89,21 @@
        #define SPEAR1310_I2S_SRC_CLK_MASK              2
        #define SPEAR1310_I2S_SRC_CLK_SHIFT             0
-#define SPEAR1310_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
+#define SPEAR1310_C3_CLK_SYNT                   (misc_base + 0x250)
-#define SPEAR1310_UART_CLK_SYNT                 (VA_MISC_BASE + 0x254)
+#define SPEAR1310_UART_CLK_SYNT                 (misc_base + 0x254)
-#define SPEAR1310_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x258)
+#define SPEAR1310_GMAC_CLK_SYNT                 (misc_base + 0x258)
-#define SPEAR1310_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x25C)
+#define SPEAR1310_SDHCI_CLK_SYNT                (misc_base + 0x25C)
-#define SPEAR1310_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x260)
+#define SPEAR1310_CFXD_CLK_SYNT                 (misc_base + 0x260)
-#define SPEAR1310_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x264)
+#define SPEAR1310_ADC_CLK_SYNT                  (misc_base + 0x264)
-#define SPEAR1310_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x268)
+#define SPEAR1310_AMBA_CLK_SYNT                 (misc_base + 0x268)
-#define SPEAR1310_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x270)
+#define SPEAR1310_CLCD_CLK_SYNT                 (misc_base + 0x270)
-#define SPEAR1310_RAS_CLK_SYNT0                 (VA_MISC_BASE + 0x280)
+#define SPEAR1310_RAS_CLK_SYNT0                 (misc_base + 0x280)
-#define SPEAR1310_RAS_CLK_SYNT1                 (VA_MISC_BASE + 0x288)
+#define SPEAR1310_RAS_CLK_SYNT1                 (misc_base + 0x288)
-#define SPEAR1310_RAS_CLK_SYNT2                 (VA_MISC_BASE + 0x290)
+#define SPEAR1310_RAS_CLK_SYNT2                 (misc_base + 0x290)
-#define SPEAR1310_RAS_CLK_SYNT3                 (VA_MISC_BASE + 0x298)
+#define SPEAR1310_RAS_CLK_SYNT3                 (misc_base + 0x298)
        /* Check Fractional synthesizer reg masks */
-#define SPEAR1310_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x300)
+#define SPEAR1310_PERIP1_CLK_ENB                (misc_base + 0x300)
        /* PERIP1_CLK_ENB register masks */
        #define SPEAR1310_RTC_CLK_ENB                   31
        #define SPEAR1310_ADC_CLK_ENB                   30
@@ -138,7 +136,7 @@
        #define SPEAR1310_SYSROM_CLK_ENB                1
        #define SPEAR1310_BUS_CLK_ENB                   0
-#define SPEAR1310_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x304)
+#define SPEAR1310_PERIP2_CLK_ENB                (misc_base + 0x304)
        /* PERIP2_CLK_ENB register masks */
        #define SPEAR1310_THSENS_CLK_ENB                8
        #define SPEAR1310_I2S_REF_PAD_CLK_ENB           7
@@ -150,7 +148,7 @@
        #define SPEAR1310_DDR_CORE_CLK_ENB              1
        #define SPEAR1310_DDR_CTRL_CLK_ENB              0
-#define SPEAR1310_RAS_CLK_ENB                   (VA_MISC_BASE + 0x310)
+#define SPEAR1310_RAS_CLK_ENB                   (misc_base + 0x310)
        /* RAS_CLK_ENB register masks */
        #define SPEAR1310_SYNT3_CLK_ENB                 17
        #define SPEAR1310_SYNT2_CLK_ENB                 16
@@ -172,7 +170,7 @@
        #define SPEAR1310_ACLK_CLK_ENB                  0
 /* RAS Area Control Register */
-#define SPEAR1310_RAS_CTRL_REG0                 (VA_SPEAR1310_RAS_BASE + 0x000)
+#define SPEAR1310_RAS_CTRL_REG0                 (ras_base + 0x000)
        #define SPEAR1310_SSP1_CLK_MASK                 3
        #define SPEAR1310_SSP1_CLK_SHIFT                26
        #define SPEAR1310_TDM_CLK_MASK                  1
@@ -197,12 +195,12 @@
        #define SPEAR1310_PCI_CLK_MASK                  1
        #define SPEAR1310_PCI_CLK_SHIFT                 0
-#define SPEAR1310_RAS_CTRL_REG1                 (VA_SPEAR1310_RAS_BASE + 0x004)
+#define SPEAR1310_RAS_CTRL_REG1                 (ras_base + 0x004)
        #define SPEAR1310_PHY_CLK_MASK                  0x3
        #define SPEAR1310_RMII_PHY_CLK_SHIFT            0
        #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT      2
-#define SPEAR1310_RAS_SW_CLK_CTRL               (VA_SPEAR1310_RAS_BASE + 0x0148)
+#define SPEAR1310_RAS_SW_CLK_CTRL               (ras_base + 0x0148)
        #define SPEAR1310_CAN1_CLK_ENB                  25
        #define SPEAR1310_CAN0_CLK_ENB                  24
        #define SPEAR1310_GPT64_CLK_ENB                 23
@@ -385,7 +383,7 @@ static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
-void __init spear1310_clk_init(void)
+void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 {
        struct clk *clk, *clk1;
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 35e7e2698e10..9d0b3949db30 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -17,18 +17,17 @@
 #include <linux/io.h>
 #include <linux/of_platform.h>
 #include <linux/spinlock_types.h>
-#include <mach/spear.h>
 #include "clk.h"
 /* Clock Configuration Registers */
-#define SPEAR1340_SYS_CLK_CTRL                  (VA_MISC_BASE + 0x200)
+#define SPEAR1340_SYS_CLK_CTRL                  (misc_base + 0x200)
        #define SPEAR1340_HCLK_SRC_SEL_SHIFT    27
        #define SPEAR1340_HCLK_SRC_SEL_MASK     1
        #define SPEAR1340_SCLK_SRC_SEL_SHIFT    23
        #define SPEAR1340_SCLK_SRC_SEL_MASK     3
 /* PLL related registers and bit values */
-#define SPEAR1340_PLL_CFG                       (VA_MISC_BASE + 0x210)
+#define SPEAR1340_PLL_CFG                       (misc_base + 0x210)
        /* PLL_CFG bit values */
        #define SPEAR1340_CLCD_SYNT_CLK_MASK            1
        #define SPEAR1340_CLCD_SYNT_CLK_SHIFT           31
@@ -40,15 +39,15 @@
        #define SPEAR1340_PLL2_CLK_SHIFT                22
        #define SPEAR1340_PLL1_CLK_SHIFT                20
-#define SPEAR1340_PLL1_CTR                      (VA_MISC_BASE + 0x214)
+#define SPEAR1340_PLL1_CTR                      (misc_base + 0x214)
-#define SPEAR1340_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
+#define SPEAR1340_PLL1_FRQ                      (misc_base + 0x218)
-#define SPEAR1340_PLL2_CTR                      (VA_MISC_BASE + 0x220)
+#define SPEAR1340_PLL2_CTR                      (misc_base + 0x220)
-#define SPEAR1340_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
+#define SPEAR1340_PLL2_FRQ                      (misc_base + 0x224)
-#define SPEAR1340_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
+#define SPEAR1340_PLL3_CTR                      (misc_base + 0x22C)
-#define SPEAR1340_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
+#define SPEAR1340_PLL3_FRQ                      (misc_base + 0x230)
-#define SPEAR1340_PLL4_CTR                      (VA_MISC_BASE + 0x238)
+#define SPEAR1340_PLL4_CTR                      (misc_base + 0x238)
-#define SPEAR1340_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
+#define SPEAR1340_PLL4_FRQ                      (misc_base + 0x23C)
-#define SPEAR1340_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
+#define SPEAR1340_PERIP_CLK_CFG                 (misc_base + 0x244)
        /* PERIP_CLK_CFG bit values */
        #define SPEAR1340_SPDIF_CLK_MASK                1
        #define SPEAR1340_SPDIF_OUT_CLK_SHIFT           15
@@ -66,13 +65,13 @@
        #define SPEAR1340_C3_CLK_MASK                   1
        #define SPEAR1340_C3_CLK_SHIFT                  1
-#define SPEAR1340_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
+#define SPEAR1340_GMAC_CLK_CFG                  (misc_base + 0x248)
        #define SPEAR1340_GMAC_PHY_CLK_MASK             1
        #define SPEAR1340_GMAC_PHY_CLK_SHIFT            2
        #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK       2
        #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT      0
-#define SPEAR1340_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
+#define SPEAR1340_I2S_CLK_CFG                   (misc_base + 0x24C)
        /* I2S_CLK_CFG register mask */
        #define SPEAR1340_I2S_SCLK_X_MASK               0x1F
        #define SPEAR1340_I2S_SCLK_X_SHIFT              27
@@ -90,21 +89,21 @@
        #define SPEAR1340_I2S_SRC_CLK_MASK              2
        #define SPEAR1340_I2S_SRC_CLK_SHIFT             0
-#define SPEAR1340_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
+#define SPEAR1340_C3_CLK_SYNT                   (misc_base + 0x250)
-#define SPEAR1340_UART0_CLK_SYNT                (VA_MISC_BASE + 0x254)
+#define SPEAR1340_UART0_CLK_SYNT                (misc_base + 0x254)
-#define SPEAR1340_UART1_CLK_SYNT                (VA_MISC_BASE + 0x258)
+#define SPEAR1340_UART1_CLK_SYNT                (misc_base + 0x258)
-#define SPEAR1340_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x25C)
+#define SPEAR1340_GMAC_CLK_SYNT                 (misc_base + 0x25C)
-#define SPEAR1340_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x260)
+#define SPEAR1340_SDHCI_CLK_SYNT                (misc_base + 0x260)
-#define SPEAR1340_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x264)
+#define SPEAR1340_CFXD_CLK_SYNT                 (misc_base + 0x264)
-#define SPEAR1340_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x270)
+#define SPEAR1340_ADC_CLK_SYNT                  (misc_base + 0x270)
-#define SPEAR1340_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x274)
+#define SPEAR1340_AMBA_CLK_SYNT                 (misc_base + 0x274)
-#define SPEAR1340_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x27C)
+#define SPEAR1340_CLCD_CLK_SYNT                 (misc_base + 0x27C)
-#define SPEAR1340_SYS_CLK_SYNT                  (VA_MISC_BASE + 0x284)
+#define SPEAR1340_SYS_CLK_SYNT                  (misc_base + 0x284)
-#define SPEAR1340_GEN_CLK_SYNT0                 (VA_MISC_BASE + 0x28C)
+#define SPEAR1340_GEN_CLK_SYNT0                 (misc_base + 0x28C)
-#define SPEAR1340_GEN_CLK_SYNT1                 (VA_MISC_BASE + 0x294)
+#define SPEAR1340_GEN_CLK_SYNT1                 (misc_base + 0x294)
-#define SPEAR1340_GEN_CLK_SYNT2                 (VA_MISC_BASE + 0x29C)
+#define SPEAR1340_GEN_CLK_SYNT2                 (misc_base + 0x29C)
-#define SPEAR1340_GEN_CLK_SYNT3                 (VA_MISC_BASE + 0x304)
+#define SPEAR1340_GEN_CLK_SYNT3                 (misc_base + 0x304)
-#define SPEAR1340_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x30C)
+#define SPEAR1340_PERIP1_CLK_ENB                (misc_base + 0x30C)
        #define SPEAR1340_RTC_CLK_ENB                   31
        #define SPEAR1340_ADC_CLK_ENB                   30
        #define SPEAR1340_C3_CLK_ENB                    29
@@ -133,7 +132,7 @@
        #define SPEAR1340_SYSROM_CLK_ENB                1
        #define SPEAR1340_BUS_CLK_ENB                   0
-#define SPEAR1340_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x310)
+#define SPEAR1340_PERIP2_CLK_ENB                (misc_base + 0x310)
        #define SPEAR1340_THSENS_CLK_ENB                8
        #define SPEAR1340_I2S_REF_PAD_CLK_ENB           7
        #define SPEAR1340_ACP_CLK_ENB                   6
@@ -144,7 +143,7 @@
        #define SPEAR1340_DDR_CORE_CLK_ENB              1
        #define SPEAR1340_DDR_CTRL_CLK_ENB              0
-#define SPEAR1340_PERIP3_CLK_ENB                (VA_MISC_BASE + 0x314)
+#define SPEAR1340_PERIP3_CLK_ENB                (misc_base + 0x314)
        #define SPEAR1340_PLGPIO_CLK_ENB                18
        #define SPEAR1340_VIDEO_DEC_CLK_ENB             16
        #define SPEAR1340_VIDEO_ENC_CLK_ENB             15
@@ -441,7 +440,7 @@ static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
        "pll2_clk", };
-void __init spear1340_clk_init(void)
+void __init spear1340_clk_init(void __iomem *misc_base)
 {
        struct clk *clk, *clk1;
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index 33d3ac588da7..f9ec43fd1320 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -15,21 +15,20 @@
 #include <linux/io.h>
 #include <linux/of_platform.h>
 #include <linux/spinlock_types.h>
-#include <mach/misc_regs.h>
 #include "clk.h"
 static DEFINE_SPINLOCK(_lock);
-#define PLL1_CTR                        (MISC_BASE + 0x008)
+#define PLL1_CTR                        (misc_base + 0x008)
-#define PLL1_FRQ                        (MISC_BASE + 0x00C)
+#define PLL1_FRQ                        (misc_base + 0x00C)
-#define PLL2_CTR                        (MISC_BASE + 0x014)
+#define PLL2_CTR                        (misc_base + 0x014)
-#define PLL2_FRQ                        (MISC_BASE + 0x018)
+#define PLL2_FRQ                        (misc_base + 0x018)
-#define PLL_CLK_CFG                     (MISC_BASE + 0x020)
+#define PLL_CLK_CFG                     (misc_base + 0x020)
        /* PLL_CLK_CFG register masks */
        #define MCTR_CLK_SHIFT          28
        #define MCTR_CLK_MASK           3
-#define CORE_CLK_CFG                    (MISC_BASE + 0x024)
+#define CORE_CLK_CFG                    (misc_base + 0x024)
        /* CORE CLK CFG register masks */
        #define GEN_SYNTH2_3_CLK_SHIFT  18
        #define GEN_SYNTH2_3_CLK_MASK   1
@@ -39,7 +38,7 @@ static DEFINE_SPINLOCK(_lock);
        #define PCLK_RATIO_SHIFT        8
        #define PCLK_RATIO_MASK         2
-#define PERIP_CLK_CFG                   (MISC_BASE + 0x028)
+#define PERIP_CLK_CFG                   (misc_base + 0x028)
        /* PERIP_CLK_CFG register masks */
        #define UART_CLK_SHIFT          4
        #define UART_CLK_MASK           1
@@ -50,7 +49,7 @@ static DEFINE_SPINLOCK(_lock);
        #define GPT2_CLK_SHIFT          12
        #define GPT_CLK_MASK            1
-#define PERIP1_CLK_ENB                  (MISC_BASE + 0x02C)
+#define PERIP1_CLK_ENB                  (misc_base + 0x02C)
        /* PERIP1_CLK_ENB register masks */
        #define UART_CLK_ENB            3
        #define SSP_CLK_ENB             5
@@ -69,7 +68,7 @@ static DEFINE_SPINLOCK(_lock);
        #define USBH_CLK_ENB            25
        #define C3_CLK_ENB              31
-#define RAS_CLK_ENB                     (MISC_BASE + 0x034)
+#define RAS_CLK_ENB                     (misc_base + 0x034)
        #define RAS_AHB_CLK_ENB         0
        #define RAS_PLL1_CLK_ENB        1
        #define RAS_APB_CLK_ENB         2
@@ -82,20 +81,20 @@ static DEFINE_SPINLOCK(_lock);
        #define RAS_SYNT2_CLK_ENB       10
        #define RAS_SYNT3_CLK_ENB       11
-#define PRSC0_CLK_CFG                   (MISC_BASE + 0x044)
+#define PRSC0_CLK_CFG                   (misc_base + 0x044)
-#define PRSC1_CLK_CFG                   (MISC_BASE + 0x048)
+#define PRSC1_CLK_CFG                   (misc_base + 0x048)
-#define PRSC2_CLK_CFG                   (MISC_BASE + 0x04C)
+#define PRSC2_CLK_CFG                   (misc_base + 0x04C)
-#define AMEM_CLK_CFG                    (MISC_BASE + 0x050)
+#define AMEM_CLK_CFG                    (misc_base + 0x050)
        #define AMEM_CLK_ENB            0
-#define CLCD_CLK_SYNT                   (MISC_BASE + 0x05C)
+#define CLCD_CLK_SYNT                   (misc_base + 0x05C)
-#define FIRDA_CLK_SYNT                  (MISC_BASE + 0x060)
+#define FIRDA_CLK_SYNT                  (misc_base + 0x060)
-#define UART_CLK_SYNT                   (MISC_BASE + 0x064)
+#define UART_CLK_SYNT                   (misc_base + 0x064)
-#define GMAC_CLK_SYNT                   (MISC_BASE + 0x068)
+#define GMAC_CLK_SYNT                   (misc_base + 0x068)
-#define GEN0_CLK_SYNT                   (MISC_BASE + 0x06C)
+#define GEN0_CLK_SYNT                   (misc_base + 0x06C)
-#define GEN1_CLK_SYNT                   (MISC_BASE + 0x070)
+#define GEN1_CLK_SYNT                   (misc_base + 0x070)
-#define GEN2_CLK_SYNT                   (MISC_BASE + 0x074)
+#define GEN2_CLK_SYNT                   (misc_base + 0x074)
-#define GEN3_CLK_SYNT                   (MISC_BASE + 0x078)
+#define GEN3_CLK_SYNT                   (misc_base + 0x078)
 /* pll rate configuration table, in ascending order of rates */
 static struct pll_rate_tbl pll_rtbl[] = {
@@ -211,6 +210,17 @@ static inline void spear310_clk_init(void) { }
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
+#define SPEAR320_CONTROL_REG            (soc_config_base + 0x0000)
+#define SPEAR320_EXT_CTRL_REG           (soc_config_base + 0x0018)
+        #define SPEAR320_UARTX_PCLK_MASK                0x1
+        #define SPEAR320_UART2_PCLK_SHIFT               8
+        #define SPEAR320_UART3_PCLK_SHIFT               9
+        #define SPEAR320_UART4_PCLK_SHIFT               10
+        #define SPEAR320_UART5_PCLK_SHIFT               11
+        #define SPEAR320_UART6_PCLK_SHIFT               12
+        #define SPEAR320_RS485_PCLK_SHIFT               13
        #define SMII_PCLK_SHIFT                         18
        #define SMII_PCLK_MASK                          2
        #define SMII_PCLK_VAL_PAD                       0x0
@@ -235,7 +245,7 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
        "ras_syn0_gclk", };
 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
-static void __init spear320_clk_init(void)
+static void __init spear320_clk_init(void __iomem *soc_config_base)
 {
        struct clk *clk;
@@ -362,7 +372,7 @@ static void __init spear320_clk_init(void)
 static inline void spear320_clk_init(void) { }
 #endif
-void __init spear3xx_clk_init(void)
+void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
 {
        struct clk *clk, *clk1;
@@ -634,5 +644,5 @@ void __init spear3xx_clk_init(void)
        else if (of_machine_is_compatible("st,spear310"))
                spear310_clk_init();
        else if (of_machine_is_compatible("st,spear320"))
-                spear320_clk_init();
+                spear320_clk_init(soc_config_base);
 }
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index e862a333ad30..9406f2426d64 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -13,28 +13,27 @@
 #include <linux/clkdev.h>
 #include <linux/io.h>
 #include <linux/spinlock_types.h>
-#include <mach/misc_regs.h>
 #include "clk.h"
 static DEFINE_SPINLOCK(_lock);
-#define PLL1_CTR                        (MISC_BASE + 0x008)
+#define PLL1_CTR                        (misc_base + 0x008)
-#define PLL1_FRQ                        (MISC_BASE + 0x00C)
+#define PLL1_FRQ                        (misc_base + 0x00C)
-#define PLL2_CTR                        (MISC_BASE + 0x014)
+#define PLL2_CTR                        (misc_base + 0x014)
-#define PLL2_FRQ                        (MISC_BASE + 0x018)
+#define PLL2_FRQ                        (misc_base + 0x018)
-#define PLL_CLK_CFG                     (MISC_BASE + 0x020)
+#define PLL_CLK_CFG                     (misc_base + 0x020)
        /* PLL_CLK_CFG register masks */
        #define MCTR_CLK_SHIFT          28
        #define MCTR_CLK_MASK           3
-#define CORE_CLK_CFG                    (MISC_BASE + 0x024)
+#define CORE_CLK_CFG                    (misc_base + 0x024)
        /* CORE CLK CFG register masks */
        #define HCLK_RATIO_SHIFT        10
        #define HCLK_RATIO_MASK         2
        #define PCLK_RATIO_SHIFT        8
        #define PCLK_RATIO_MASK         2
-#define PERIP_CLK_CFG                   (MISC_BASE + 0x028)
+#define PERIP_CLK_CFG                   (misc_base + 0x028)
        /* PERIP_CLK_CFG register masks */
        #define CLCD_CLK_SHIFT          2
        #define CLCD_CLK_MASK           2
@@ -48,7 +47,7 @@ static DEFINE_SPINLOCK(_lock);
        #define GPT3_CLK_SHIFT          12
        #define GPT_CLK_MASK            1
-#define PERIP1_CLK_ENB                  (MISC_BASE + 0x02C)
+#define PERIP1_CLK_ENB                  (misc_base + 0x02C)
        /* PERIP1_CLK_ENB register masks */
        #define UART0_CLK_ENB           3
        #define UART1_CLK_ENB           4
@@ -74,13 +73,13 @@ static DEFINE_SPINLOCK(_lock);
        #define USBH0_CLK_ENB           25
        #define USBH1_CLK_ENB           26
-#define PRSC0_CLK_CFG                   (MISC_BASE + 0x044)
+#define PRSC0_CLK_CFG                   (misc_base + 0x044)
-#define PRSC1_CLK_CFG                   (MISC_BASE + 0x048)
+#define PRSC1_CLK_CFG                   (misc_base + 0x048)
-#define PRSC2_CLK_CFG                   (MISC_BASE + 0x04C)
+#define PRSC2_CLK_CFG                   (misc_base + 0x04C)
-#define CLCD_CLK_SYNT                   (MISC_BASE + 0x05C)
+#define CLCD_CLK_SYNT                   (misc_base + 0x05C)
-#define FIRDA_CLK_SYNT                  (MISC_BASE + 0x060)
+#define FIRDA_CLK_SYNT                  (misc_base + 0x060)
-#define UART_CLK_SYNT                   (MISC_BASE + 0x064)
+#define UART_CLK_SYNT                   (misc_base + 0x064)
 /* vco rate configuration table, in ascending order of rates */
 static struct pll_rate_tbl pll_rtbl[] = {
@@ -115,7 +114,7 @@ static struct gpt_rate_tbl gpt_rtbl[] = {
        {.mscale = 1, .nscale = 0}, /* 83 MHz */
 };
-void __init spear6xx_clk_init(void)
+void __init spear6xx_clk_init(void __iomem *misc_base)
 {
        struct clk *clk, *clk1;
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba6f51bc9f3b..f15f147d473c 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -22,8 +22,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/clk/tegra.h>
+#include <linux/tegra-powergate.h>
-#include <mach/powergate.h>
 #include "clk.h"
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
index 7eee7f768355..bd4769a84485 100644
--- a/drivers/clk/ux500/clk-prcc.c
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -13,7 +13,6 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/types.h>
-#include <mach/hardware.h>
 #include "clk.h"
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 9d9add1e816d..0b4f35a5ffc2 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -12,10 +12,10 @@
 #include <linux/clk-provider.h>
 #include <linux/mfd/dbx500-prcmu.h>
 #include <linux/platform_data/clk-ux500.h>
-#include <mach/db8500-regs.h>
 #include "clk.h"
-void u8500_clk_init(void)
+void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+                    u32 clkrst5_base, u32 clkrst6_base)
 {
        struct prcmu_fw_version *fw_version;
        const char *sgaclk_parent = NULL;
@@ -215,148 +215,148 @@ void u8500_clk_init(void)
         */
        /* PRCC P-clocks */
-        clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
                                BIT(0), 0);
        clk_register_clkdev(clk, "apb_pclk", "uart0");
-        clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
                                BIT(1), 0);
        clk_register_clkdev(clk, "apb_pclk", "uart1");
-        clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
                                BIT(2), 0);
        clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
-        clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
                                BIT(3), 0);
        clk_register_clkdev(clk, "apb_pclk", "msp0");
        clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
-        clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
                                BIT(4), 0);
        clk_register_clkdev(clk, "apb_pclk", "msp1");
        clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
-        clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
                                BIT(5), 0);
        clk_register_clkdev(clk, "apb_pclk", "sdi0");
-        clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
                                BIT(6), 0);
        clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
-        clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
                                BIT(7), 0);
        clk_register_clkdev(clk, NULL, "spi3");
-        clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
                                BIT(8), 0);
        clk_register_clkdev(clk, "apb_pclk", "slimbus0");
-        clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
                                BIT(9), 0);
        clk_register_clkdev(clk, NULL, "gpio.0");
        clk_register_clkdev(clk, NULL, "gpio.1");
        clk_register_clkdev(clk, NULL, "gpioblock0");
-        clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
                                BIT(10), 0);
        clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
-        clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
+        clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
                                BIT(11), 0);
        clk_register_clkdev(clk, "apb_pclk", "msp3");
        clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
-        clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
                                BIT(0), 0);
        clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
-        clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
                                BIT(1), 0);
        clk_register_clkdev(clk, NULL, "spi2");
-        clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
                                BIT(2), 0);
        clk_register_clkdev(clk, NULL, "spi1");
-        clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
                                BIT(3), 0);
        clk_register_clkdev(clk, NULL, "pwl");
-        clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
                                BIT(4), 0);
        clk_register_clkdev(clk, "apb_pclk", "sdi4");
-        clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
                                BIT(5), 0);
        clk_register_clkdev(clk, "apb_pclk", "msp2");
        clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
-        clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
                                BIT(6), 0);
        clk_register_clkdev(clk, "apb_pclk", "sdi1");
-        clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
                                BIT(7), 0);
        clk_register_clkdev(clk, "apb_pclk", "sdi3");
-        clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
                                BIT(8), 0);
        clk_register_clkdev(clk, NULL, "spi0");
-        clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
                                BIT(9), 0);
        clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
-        clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
                                BIT(10), 0);
        clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
-        clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
                                BIT(11), 0);
        clk_register_clkdev(clk, NULL, "gpio.6");
        clk_register_clkdev(clk, NULL, "gpio.7");
        clk_register_clkdev(clk, NULL, "gpioblock1");
-        clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
+        clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
                                BIT(12), 0);
-        clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
                                BIT(0), 0);
        clk_register_clkdev(clk, "fsmc", NULL);
        clk_register_clkdev(clk, NULL, "smsc911x");
-        clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
                                BIT(1), 0);
        clk_register_clkdev(clk, "apb_pclk", "ssp0");
-        clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
                                BIT(2), 0);
        clk_register_clkdev(clk, "apb_pclk", "ssp1");
-        clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
                                BIT(3), 0);
        clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
-        clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
                                BIT(4), 0);
        clk_register_clkdev(clk, "apb_pclk", "sdi2");
-        clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
                                BIT(5), 0);
        clk_register_clkdev(clk, "apb_pclk", "ske");
        clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
-        clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
                                BIT(6), 0);
        clk_register_clkdev(clk, "apb_pclk", "uart2");
-        clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
                                BIT(7), 0);
        clk_register_clkdev(clk, "apb_pclk", "sdi5");
-        clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE,
+        clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
                                BIT(8), 0);
        clk_register_clkdev(clk, NULL, "gpio.2");
        clk_register_clkdev(clk, NULL, "gpio.3");
@@ -364,45 +364,45 @@ void u8500_clk_init(void)
        clk_register_clkdev(clk, NULL, "gpio.5");
        clk_register_clkdev(clk, NULL, "gpioblock2");
-        clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE,
+        clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
                                BIT(0), 0);
        clk_register_clkdev(clk, "usb", "musb-ux500.0");
-        clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE,
+        clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
                                BIT(1), 0);
        clk_register_clkdev(clk, NULL, "gpio.8");
        clk_register_clkdev(clk, NULL, "gpioblock3");
-        clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
+        clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
                                BIT(0), 0);
        clk_register_clkdev(clk, "apb_pclk", "rng");
-        clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
+        clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
                                BIT(1), 0);
        clk_register_clkdev(clk, NULL, "cryp0");
        clk_register_clkdev(clk, NULL, "cryp1");
-        clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE,
+        clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
                                BIT(2), 0);
        clk_register_clkdev(clk, NULL, "hash0");
-        clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE,
+        clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
                                BIT(3), 0);
        clk_register_clkdev(clk, NULL, "pka");
-        clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE,
+        clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
                                BIT(4), 0);
        clk_register_clkdev(clk, NULL, "hash1");
-        clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE,
+        clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
                                BIT(5), 0);
        clk_register_clkdev(clk, NULL, "cfgreg");
-        clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
+        clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
                                BIT(6), 0);
        clk_register_clkdev(clk, "apb_pclk", "mtu0");
-        clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
+        clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
                                BIT(7), 0);
        clk_register_clkdev(clk, "apb_pclk", "mtu1");
@@ -416,110 +416,110 @@ void u8500_clk_init(void)
        /* Periph1 */
        clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
-                        U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "uart0");
        clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
-                        U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "uart1");
        clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
-                        U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "nmk-i2c.1");
        clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
-                        U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "msp0");
        clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
        clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
-                        U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "msp1");
        clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
        clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
-                        U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "sdi0");
        clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
-                        U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "nmk-i2c.2");
        clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
-                        U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "slimbus0");
        clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
-                        U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "nmk-i2c.4");
        clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
-                        U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
+                        clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "msp3");
        clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
        /* Periph2 */
        clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
-                        U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
+                        clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "nmk-i2c.3");
        clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
-                        U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
+                        clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "sdi4");
        clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
-                        U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
+                        clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "msp2");
        clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
        clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
-                        U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
+                        clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "sdi1");
        clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
-                        U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE);
+                        clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "sdi3");
        /* Note that rate is received from parent. */
        clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
-                        U8500_CLKRST2_BASE, BIT(6),
+                        clkrst2_base, BIT(6),
                        CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
        clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
-                        U8500_CLKRST2_BASE, BIT(7),
+                        clkrst2_base, BIT(7),
                        CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
        /* Periph3 */
        clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
-                        U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
+                        clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "ssp0");
        clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
-                        U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
+                        clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "ssp1");
        clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
-                        U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
+                        clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "nmk-i2c.0");
        clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
-                        U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
+                        clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "sdi2");
        clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
-                        U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
+                        clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "ske");
        clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
        clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
-                        U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
+                        clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "uart2");
        clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
-                        U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE);
+                        clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "sdi5");
        /* Periph6 */
        clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
-                        U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
+                        clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
        clk_register_clkdev(clk, NULL, "rng");
 }
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 4897f243a000..682d48d08164 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -16,7 +16,9 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU)	+= nomadik-mtu.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)       += time-armada-370-xp.o
 obj-$(CONFIG_ARCH_BCM2835)      += bcm2835_timer.o
+obj-$(CONFIG_ARCH_MARCO)        += timer-marco.o
 obj-$(CONFIG_ARCH_MXS)          += mxs_timer.o
+obj-$(CONFIG_ARCH_PRIMA2)       += timer-prima2.o
 obj-$(CONFIG_SUN4I_TIMER)       += sun4i_timer.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)      += vt8500_timer.o
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c
index c26c369eb9e6..54f3d119d99c 100644
--- a/drivers/clocksource/clksrc-dbx500-prcmu.c
+++ b/drivers/clocksource/clksrc-dbx500-prcmu.c
@@ -17,9 +17,6 @@
 #include <asm/sched_clock.h>
-#include <mach/setup.h>
-#include <mach/hardware.h>
 #define RATE_32K                32768
 #define TIMER_MODE_CONTINOUS    0x1
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index 071f6eadfea2..e405531e1cc5 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -67,7 +67,7 @@ static u32 clk_prescale;
 static u32 nmdk_cycle;          /* write-once */
 static struct delay_timer mtu_delay_timer;
-#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
+#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
 /*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
@@ -233,7 +233,7 @@ void __init nmdk_timer_init(void __iomem *base, int irq)
                pr_err("timer: failed to initialize clock source %s\n",
                       "mtu_0");
-#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
+#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
        setup_sched_clock(nomadik_read_sched_clock, 32, rate);
 #endif
diff --git a/arch/arm/mach-prima2/timer-marco.c b/drivers/clocksource/timer-marco.c
index f4eea2e97eb0..97738dbf3e3b 100644
--- a/arch/arm/mach-prima2/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -21,8 +21,6 @@
 #include <asm/localtimer.h>
 #include <asm/mach/time.h>
-#include "common.h"
 #define SIRFSOC_TIMER_32COUNTER_0_CTRL                  0x0000
 #define SIRFSOC_TIMER_32COUNTER_1_CTRL                  0x0004
 #define SIRFSOC_TIMER_MATCH_0                           0x0018
@@ -53,7 +51,6 @@ static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
 static void __iomem *sirfsoc_timer_base;
-static void __init sirfsoc_of_timer_map(void);
 /* disable count and interrupt */
 static inline void sirfsoc_timer_count_disable(int idx)
@@ -242,15 +239,12 @@ static void __init sirfsoc_clockevent_init(void)
 }
 /* initialize the kernel jiffy timer source */
-void __init sirfsoc_marco_timer_init(void)
+static void __init sirfsoc_marco_timer_init(void)
 {
        unsigned long rate;
        u32 timer_div;
        struct clk *clk;
-        /* initialize clocking early, we want to set the OS timer */
-        sirfsoc_of_clk_init();
        /* timer's input clock is io clock */
        clk = clk_get_sys("io", NULL);
@@ -260,8 +254,6 @@ void __init sirfsoc_marco_timer_init(void)
        BUG_ON(rate < CLOCK_TICK_RATE);
        BUG_ON(rate % CLOCK_TICK_RATE);
-        sirfsoc_of_timer_map();
        /* Initialize the timer dividers */
        timer_div = rate / CLOCK_TICK_RATE - 1;
        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
@@ -286,18 +278,8 @@ void __init sirfsoc_marco_timer_init(void)
        sirfsoc_clockevent_init();
 }
-static struct of_device_id timer_ids[] = {
+static void __init sirfsoc_of_timer_init(struct device_node *np)
-        { .compatible = "sirf,marco-tick" },
-        {},
-};
-static void __init sirfsoc_of_timer_map(void)
 {
-        struct device_node *np;
-        np = of_find_matching_node(NULL, timer_ids);
-        if (!np)
-                return;
        sirfsoc_timer_base = of_iomap(np, 0);
        if (!sirfsoc_timer_base)
                panic("unable to map timer cpu registers\n");
@@ -312,5 +294,6 @@ static void __init sirfsoc_of_timer_map(void)
                panic("No irq passed for timer1 via DT\n");
 #endif
-        of_node_put(np);
+        sirfsoc_marco_timer_init();
 }
+CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );
diff --git a/arch/arm/mach-prima2/timer-prima2.c b/drivers/clocksource/timer-prima2.c
index 6da584f8a949..760882665d7a 100644
--- a/arch/arm/mach-prima2/timer-prima2.c
+++ b/drivers/clocksource/timer-prima2.c
@@ -16,13 +16,11 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/of_address.h>
-#include <mach/map.h>
 #include <asm/sched_clock.h>
 #include <asm/mach/time.h>
-#include "common.h"
 #define SIRFSOC_TIMER_COUNTER_LO        0x0000
 #define SIRFSOC_TIMER_COUNTER_HI        0x0004
 #define SIRFSOC_TIMER_MATCH_0           0x0008
@@ -55,7 +53,6 @@ static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
 static void __iomem *sirfsoc_timer_base;
-static void __init sirfsoc_of_timer_map(void);
 /* timer0 interrupt handler */
 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
@@ -181,14 +178,11 @@ static void __init sirfsoc_clockevent_init(void)
 }
 /* initialize the kernel jiffy timer source */
-void __init sirfsoc_prima2_timer_init(void)
+static void __init sirfsoc_prima2_timer_init(struct device_node *np)
 {
        unsigned long rate;
        struct clk *clk;
-        /* initialize clocking early, we want to set the OS timer */
-        sirfsoc_of_clk_init();
        /* timer's input clock is io clock */
        clk = clk_get_sys("io", NULL);
@@ -199,7 +193,11 @@ void __init sirfsoc_prima2_timer_init(void)
        BUG_ON(rate < CLOCK_TICK_RATE);
        BUG_ON(rate % CLOCK_TICK_RATE);
-        sirfsoc_of_timer_map();
+        sirfsoc_timer_base = of_iomap(np, 0);
+        if (!sirfsoc_timer_base)
+                panic("unable to map timer cpu registers\n");
+        sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
        writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
@@ -214,28 +212,4 @@ void __init sirfsoc_prima2_timer_init(void)
        sirfsoc_clockevent_init();
 }
+CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick", sirfsoc_prima2_timer_init);
-static struct of_device_id timer_ids[] = {
-        { .compatible = "sirf,prima2-tick" },
-        {},
-};
-static void __init sirfsoc_of_timer_map(void)
-{
-        struct device_node *np;
-        const unsigned int *intspec;
-        np = of_find_matching_node(NULL, timer_ids);
-        if (!np)
-                return;
-        sirfsoc_timer_base = of_iomap(np, 0);
-        if (!sirfsoc_timer_base)
-                panic("unable to map timer cpu registers\n");
-        /* Get the interrupts property */
-        intspec = of_get_property(np, "interrupts", NULL);
-        BUG_ON(!intspec);
-        sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
-        of_node_put(np);
-}
diff --git a/drivers/crypto/ux500/cryp/cryp.c b/drivers/crypto/ux500/cryp/cryp.c
index e208ceaf81c9..3eafa903ebcd 100644
--- a/drivers/crypto/ux500/cryp/cryp.c
+++ b/drivers/crypto/ux500/cryp/cryp.c
@@ -12,8 +12,6 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <mach/hardware.h>
 #include "cryp_p.h"
 #include "cryp.h"
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 22c9063e0120..32f480622b97 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -32,7 +32,6 @@
 #include <crypto/scatterwalk.h>
 #include <linux/platform_data/crypto-ux500.h>
-#include <mach/hardware.h>
 #include "cryp_p.h"
 #include "cryp.h"
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 632c3339895f..1827e9f1f873 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -32,7 +32,6 @@
 #include <crypto/algapi.h>
 #include <linux/platform_data/crypto-ux500.h>
-#include <mach/hardware.h>
 #include "hash_alg.h"
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d5e119ca9425..10ef57f35a6e 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o
 obj-$(CONFIG_ARCH_SPEAR3XX)             += spear-shirq.o
 obj-$(CONFIG_ARM_GIC)                   += irq-gic.o
 obj-$(CONFIG_ARM_VIC)                   += irq-vic.o
+obj-$(CONFIG_SIRF_IRQ)                  += irq-sirfsoc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)        += irq-versatile-fpga.o
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c
new file mode 100644
index 000000000000..69ea44ebcf61
--- /dev/null
+++ b/drivers/irqchip/irq-sirfsoc.c
@@ -0,0 +1,126 @@
+/*
+ * interrupt controller support for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/irqdomain.h>
+#include <linux/syscore_ops.h>
+#include <asm/mach/irq.h>
+#include <asm/exception.h>
+#include "irqchip.h"
+#define SIRFSOC_INT_RISC_MASK0          0x0018
+#define SIRFSOC_INT_RISC_MASK1          0x001C
+#define SIRFSOC_INT_RISC_LEVEL0         0x0020
+#define SIRFSOC_INT_RISC_LEVEL1         0x0024
+#define SIRFSOC_INIT_IRQ_ID             0x0038
+#define SIRFSOC_NUM_IRQS                128
+static struct irq_domain *sirfsoc_irqdomain;
+static __init void
+sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
+        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
+}
+static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
+{
+        void __iomem *base = sirfsoc_irqdomain->host_data;
+        u32 irqstat, irqnr;
+        irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
+        irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);
+        handle_IRQ(irqnr, regs);
+}
+static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *parent)
+{
+        void __iomem *base = of_iomap(np, 0);
+        if (!base)
+                panic("unable to map intc cpu registers\n");
+        /* using legacy because irqchip_generic does not work with linear */
+        sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,
+                                 &irq_domain_simple_ops, base);
+        sirfsoc_alloc_gc(base, 0, 32);
+        sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
+        writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
+        writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
+        writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
+        writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
+        set_handle_irq(sirfsoc_handle_irq);
+        return 0;
+}
+IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
+struct sirfsoc_irq_status {
+        u32 mask0;
+        u32 mask1;
+        u32 level0;
+        u32 level1;
+};
+static struct sirfsoc_irq_status sirfsoc_irq_st;
+static int sirfsoc_irq_suspend(void)
+{
+        void __iomem *base = sirfsoc_irqdomain->host_data;
+        sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
+        sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
+        sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
+        sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
+        return 0;
+}
+static void sirfsoc_irq_resume(void)
+{
+        void __iomem *base = sirfsoc_irqdomain->host_data;
+        writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
+        writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
+        writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
+        writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
+}
+static struct syscore_ops sirfsoc_irq_syscore_ops = {
+        .suspend        = sirfsoc_irq_suspend,
+        .resume         = sirfsoc_irq_resume,
+};
+static int __init sirfsoc_irq_pm_init(void)
+{
+        if (!sirfsoc_irqdomain)
+                return 0;
+        register_syscore_ops(&sirfsoc_irq_syscore_ops);
+        return 0;
+}
+device_initcall(sirfsoc_irq_pm_init);
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 21f261bf9e95..21434beb420a 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -26,7 +26,6 @@
 #include <linux/fs.h>
 #include <linux/platform_device.h>
 #include <linux/uaccess.h>
-#include <linux/irqchip/arm-gic.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/dbx500-prcmu.h>
 #include <linux/mfd/abx500/ab8500.h>
@@ -34,9 +33,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/cpufreq.h>
 #include <linux/platform_data/ux500_wdt.h>
-#include <mach/hardware.h>
+#include <linux/platform_data/db8500_thermal.h>
-#include <mach/irqs.h>
-#include <mach/db8500-regs.h>
 #include "dbx500-prcmu-regs.h"
 /* Index of different voltages to be used when accessing AVSData */
@@ -276,8 +273,34 @@ static struct irq_domain *db8500_irq_domain;
 * the bits in the bit field are not. (The bits also have a tendency to move
 * around, to further complicate matters.)
 */
-#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
+#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
+#define IRQ_PRCMU_RTC 0
+#define IRQ_PRCMU_RTT0 1
+#define IRQ_PRCMU_RTT1 2
+#define IRQ_PRCMU_HSI0 3
+#define IRQ_PRCMU_HSI1 4
+#define IRQ_PRCMU_CA_WAKE 5
+#define IRQ_PRCMU_USB 6
+#define IRQ_PRCMU_ABB 7
+#define IRQ_PRCMU_ABB_FIFO 8
+#define IRQ_PRCMU_ARM 9
+#define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
+#define IRQ_PRCMU_GPIO0 11
+#define IRQ_PRCMU_GPIO1 12
+#define IRQ_PRCMU_GPIO2 13
+#define IRQ_PRCMU_GPIO3 14
+#define IRQ_PRCMU_GPIO4 15
+#define IRQ_PRCMU_GPIO5 16
+#define IRQ_PRCMU_GPIO6 17
+#define IRQ_PRCMU_GPIO7 18
+#define IRQ_PRCMU_GPIO8 19
+#define IRQ_PRCMU_CA_SLEEP 20
+#define IRQ_PRCMU_HOTMON_LOW 21
+#define IRQ_PRCMU_HOTMON_HIGH 22
+#define NUM_PRCMU_WAKEUPS 23
 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
        IRQ_ENTRY(RTC),
        IRQ_ENTRY(RTT0),
@@ -422,9 +445,10 @@ static DEFINE_SPINLOCK(clkout_lock);
 /* Global var to runtime determine TCDM base for v2 or v1 */
 static __iomem void *tcdm_base;
+static __iomem void *prcmu_base;
 struct clk_mgt {
-        void __iomem *reg;
+        u32 offset;
        u32 pllsw;
        int branch;
        bool clk38div;
@@ -599,9 +623,9 @@ int db8500_prcmu_set_display_clocks(void)
        while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
                cpu_relax();
-        writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
+        writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
-        writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
+        writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
-        writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
+        writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
        /* Release the HW semaphore. */
        writel(0, PRCM_SEM);
@@ -613,7 +637,7 @@ int db8500_prcmu_set_display_clocks(void)
 u32 db8500_prcmu_read(unsigned int reg)
 {
-        return readl(_PRCMU_BASE + reg);
+        return readl(prcmu_base + reg);
 }
 void db8500_prcmu_write(unsigned int reg, u32 value)
@@ -621,7 +645,7 @@ void db8500_prcmu_write(unsigned int reg, u32 value)
        unsigned long flags;
        spin_lock_irqsave(&prcmu_lock, flags);
-        writel(value, (_PRCMU_BASE + reg));
+        writel(value, (prcmu_base + reg));
        spin_unlock_irqrestore(&prcmu_lock, flags);
 }
@@ -631,9 +655,9 @@ void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
        unsigned long flags;
        spin_lock_irqsave(&prcmu_lock, flags);
-        val = readl(_PRCMU_BASE + reg);
+        val = readl(prcmu_base + reg);
        val = ((val & ~mask) | (value & mask));
-        writel(val, (_PRCMU_BASE + reg));
+        writel(val, (prcmu_base + reg));
        spin_unlock_irqrestore(&prcmu_lock, flags);
 }
@@ -793,119 +817,6 @@ u8 db8500_prcmu_get_power_state_result(void)
        return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
 }
-/* This function decouple the gic from the prcmu */
-int db8500_prcmu_gic_decouple(void)
-{
-        u32 val = readl(PRCM_A9_MASK_REQ);
-        /* Set bit 0 register value to 1 */
-        writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
-               PRCM_A9_MASK_REQ);
-        /* Make sure the register is updated */
-        readl(PRCM_A9_MASK_REQ);
-        /* Wait a few cycles for the gic mask completion */
-        udelay(1);
-        return 0;
-}
-/* This function recouple the gic with the prcmu */
-int db8500_prcmu_gic_recouple(void)
-{
-        u32 val = readl(PRCM_A9_MASK_REQ);
-        /* Set bit 0 register value to 0 */
-        writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
-        return 0;
-}
-#define PRCMU_GIC_NUMBER_REGS 5
-/*
- * This function checks if there are pending irq on the gic. It only
- * makes sense if the gic has been decoupled before with the
- * db8500_prcmu_gic_decouple function. Disabling an interrupt only
- * disables the forwarding of the interrupt to any CPU interface. It
- * does not prevent the interrupt from changing state, for example
- * becoming pending, or active and pending if it is already
- * active. Hence, we have to check the interrupt is pending *and* is
- * active.
- */
-bool db8500_prcmu_gic_pending_irq(void)
-{
-        u32 pr; /* Pending register */
-        u32 er; /* Enable register */
-        void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
-        int i;
-        /* 5 registers. STI & PPI not skipped */
-        for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
-                pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
-                er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
-                if (pr & er)
-                        return true; /* There is a pending interrupt */
-        }
-        return false;
-}
-/*
- * This function checks if there are pending interrupt on the
- * prcmu which has been delegated to monitor the irqs with the
- * db8500_prcmu_copy_gic_settings function.
- */
-bool db8500_prcmu_pending_irq(void)
-{
-        u32 it, im;
-        int i;
-        for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
-                it = readl(PRCM_ARMITVAL31TO0 + i * 4);
-                im = readl(PRCM_ARMITMSK31TO0 + i * 4);
-                if (it & im)
-                        return true; /* There is a pending interrupt */
-        }
-        return false;
-}
-/*
- * This function checks if the specified cpu is in in WFI. It's usage
- * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
- * function. Of course passing smp_processor_id() to this function will
- * always return false...
- */
-bool db8500_prcmu_is_cpu_in_wfi(int cpu)
-{
-        return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
-                     PRCM_ARM_WFI_STANDBY_WFI0;
-}
-/*
- * This function copies the gic SPI settings to the prcmu in order to
- * monitor them and abort/finish the retention/off sequence or state.
- */
-int db8500_prcmu_copy_gic_settings(void)
-{
-        u32 er; /* Enable register */
-        void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
-        int i;
-        /* We skip the STI and PPI */
-        for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
-                er = readl_relaxed(dist_base +
-                                   GIC_DIST_ENABLE_SET + (i + 1) * 4);
-                writel(er, PRCM_ARMITMSK31TO0 + i * 4);
-        }
-        return 0;
-}
 /* This function should only be called while mb0_transfer.lock is held. */
 static void config_wakeups(void)
 {
@@ -1059,7 +970,7 @@ int db8500_prcmu_set_ddr_opp(u8 opp)
 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
 static void request_even_slower_clocks(bool enable)
 {
-        void __iomem *clock_reg[] = {
+        u32 clock_reg[] = {
                PRCM_ACLK_MGT,
                PRCM_DMACLK_MGT
        };
@@ -1076,7 +987,7 @@ static void request_even_slower_clocks(bool enable)
                u32 val;
                u32 div;
-                val = readl(clock_reg[i]);
+                val = readl(prcmu_base + clock_reg[i]);
                div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
                if (enable) {
                        if ((div <= 1) || (div > 15)) {
@@ -1092,7 +1003,7 @@ static void request_even_slower_clocks(bool enable)
                }
                val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
                        (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
-                writel(val, clock_reg[i]);
+                writel(val, prcmu_base + clock_reg[i]);
        }
 unlock_and_return:
@@ -1446,14 +1357,14 @@ static int request_clock(u8 clock, bool enable)
        while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
                cpu_relax();
-        val = readl(clk_mgt[clock].reg);
+        val = readl(prcmu_base + clk_mgt[clock].offset);
        if (enable) {
                val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
        } else {
                clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
                val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
        }
-        writel(val, clk_mgt[clock].reg);
+        writel(val, prcmu_base + clk_mgt[clock].offset);
        /* Release the HW semaphore. */
        writel(0, PRCM_SEM);
@@ -1629,7 +1540,7 @@ static unsigned long clock_rate(u8 clock)
        u32 pllsw;
        unsigned long rate = ROOT_CLOCK_RATE;
-        val = readl(clk_mgt[clock].reg);
+        val = readl(prcmu_base + clk_mgt[clock].offset);
        if (val & PRCM_CLK_MGT_CLK38) {
                if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
@@ -1785,7 +1696,7 @@ static long round_clock_rate(u8 clock, unsigned long rate)
        unsigned long src_rate;
        long rounded_rate;
-        val = readl(clk_mgt[clock].reg);
+        val = readl(prcmu_base + clk_mgt[clock].offset);
        src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
                clk_mgt[clock].branch);
        div = clock_divider(src_rate, rate);
@@ -1933,7 +1844,7 @@ static void set_clock_rate(u8 clock, unsigned long rate)
        while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
                cpu_relax();
-        val = readl(clk_mgt[clock].reg);
+        val = readl(prcmu_base + clk_mgt[clock].offset);
        src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
                clk_mgt[clock].branch);
        div = clock_divider(src_rate, rate);
@@ -1961,7 +1872,7 @@ static void set_clock_rate(u8 clock, unsigned long rate)
                val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
                val |= min(div, (u32)31);
        }
-        writel(val, clk_mgt[clock].reg);
+        writel(val, prcmu_base + clk_mgt[clock].offset);
        /* Release the HW semaphore. */
        writel(0, PRCM_SEM);
@@ -2764,14 +2675,13 @@ static struct irq_domain_ops db8500_irq_ops = {
        .xlate  = irq_domain_xlate_twocell,
 };
-static int db8500_irq_init(struct device_node *np)
+static int db8500_irq_init(struct device_node *np, int irq_base)
 {
-        int irq_base = 0;
        int i;
        /* In the device tree case, just take some IRQs */
-        if (!np)
+        if (np)
-                irq_base = IRQ_PRCMU_BASE;
+                irq_base = 0;
        db8500_irq_domain = irq_domain_add_simple(
                np, NUM_PRCMU_WAKEUPS, irq_base,
@@ -2825,8 +2735,19 @@ static void dbx500_fw_version_init(struct platform_device *pdev,
        }
 }
-void __init db8500_prcmu_early_init(void)
+void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
 {
+        /*
+         * This is a temporary remap to bring up the clocks. It is
+         * subsequently replaces with a real remap. After the merge of
+         * the mailbox subsystem all of this early code goes away, and the
+         * clock driver can probe independently. An early initcall will
+         * still be needed, but it can be diverted into drivers/clk/ux500.
+         */
+        prcmu_base = ioremap(phy_base, size);
+        if (!prcmu_base)
+                pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
        spin_lock_init(&mb0_transfer.lock);
        spin_lock_init(&mb0_transfer.dbb_irqs_lock);
        mutex_init(&mb0_transfer.ac_wake_lock);
@@ -3092,18 +3013,57 @@ static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
        },
 };
-static struct resource ab8500_resources[] = {
-        [0] = {
-                .start  = IRQ_DB8500_AB8500,
-                .end    = IRQ_DB8500_AB8500,
-                .flags  = IORESOURCE_IRQ
-        }
-};
 static struct ux500_wdt_data db8500_wdt_pdata = {
        .timeout = 600, /* 10 minutes */
        .has_28_bits_resolution = true,
 };
+/*
+ * Thermal Sensor
+ */
+static struct resource db8500_thsens_resources[] = {
+        {
+                .name = "IRQ_HOTMON_LOW",
+                .start  = IRQ_PRCMU_HOTMON_LOW,
+                .end    = IRQ_PRCMU_HOTMON_LOW,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name = "IRQ_HOTMON_HIGH",
+                .start  = IRQ_PRCMU_HOTMON_HIGH,
+                .end    = IRQ_PRCMU_HOTMON_HIGH,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct db8500_thsens_platform_data db8500_thsens_data = {
+        .trip_points[0] = {
+                .temp = 70000,
+                .type = THERMAL_TRIP_ACTIVE,
+                .cdev_name = {
+                        [0] = "thermal-cpufreq-0",
+                },
+        },
+        .trip_points[1] = {
+                .temp = 75000,
+                .type = THERMAL_TRIP_ACTIVE,
+                .cdev_name = {
+                        [0] = "thermal-cpufreq-0",
+                },
+        },
+        .trip_points[2] = {
+                .temp = 80000,
+                .type = THERMAL_TRIP_ACTIVE,
+                .cdev_name = {
+                        [0] = "thermal-cpufreq-0",
+                },
+        },
+        .trip_points[3] = {
+                .temp = 85000,
+                .type = THERMAL_TRIP_CRITICAL,
+        },
+        .num_trips = 4,
+};
 static struct mfd_cell db8500_prcmu_devs[] = {
        {
@@ -3125,11 +3085,10 @@ static struct mfd_cell db8500_prcmu_devs[] = {
                .id = -1,
        },
        {
-                .name = "ab8500-core",
+                .name = "db8500-thermal",
-                .of_compatible = "stericsson,ab8500",
+                .num_resources = ARRAY_SIZE(db8500_thsens_resources),
-                .num_resources = ARRAY_SIZE(ab8500_resources),
+                .resources = db8500_thsens_resources,
-                .resources = ab8500_resources,
+                .platform_data = &db8500_thsens_data,
-                .id = AB8500_VERSION_AB8500,
        },
 };
@@ -3141,6 +3100,24 @@ static void db8500_prcmu_update_cpufreq(void)
        }
 }
+static int db8500_prcmu_register_ab8500(struct device *parent,
+                                        struct ab8500_platform_data *pdata,
+                                        int irq)
+{
+        struct resource ab8500_resource = DEFINE_RES_IRQ(irq);
+        struct mfd_cell ab8500_cell = {
+                .name = "ab8500-core",
+                .of_compatible = "stericsson,ab8500",
+                .id = AB8500_VERSION_AB8500,
+                .platform_data = pdata,
+                .pdata_size = sizeof(struct ab8500_platform_data),
+                .resources = &ab8500_resource,
+                .num_resources = 1,
+        };
+        return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
+}
 /**
 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
 *
@@ -3149,11 +3126,21 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
 {
        struct device_node *np = pdev->dev.of_node;
        struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
-        int irq = 0, err = 0, i;
+        int irq = 0, err = 0;
        struct resource *res;
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
+        if (!res) {
+                dev_err(&pdev->dev, "no prcmu memory region provided\n");
+                return -ENOENT;
+        }
+        prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+        if (!prcmu_base) {
+                dev_err(&pdev->dev,
+                        "failed to ioremap prcmu register memory\n");
+                return -ENOENT;
+        }
        init_prcm_registers();
        dbx500_fw_version_init(pdev, pdata->version_offset);
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
        if (!res) {
@@ -3180,26 +3167,27 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
                goto no_irq_return;
        }
-        db8500_irq_init(np);
+        db8500_irq_init(np, pdata->irq_base);
-        for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
-                if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
-                        db8500_prcmu_devs[i].platform_data = pdata->ab_platdata;
-                        db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data);
-                }
-        }
        prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
        db8500_prcmu_update_cpufreq();
        err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
-                              ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL);
+                              ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, db8500_irq_domain);
        if (err) {
                pr_err("prcmu: Failed to add subdevices\n");
                return err;
        }
+        err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata,
+                                           pdata->ab_irq);
+        if (err) {
+                mfd_remove_devices(&pdev->dev);
+                pr_err("prcmu: Failed to add ab8500 subdevice\n");
+                goto no_irq_return;
+        }
        pr_info("DB8500 PRCMU initialized\n");
 no_irq_return:
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 79c76ebdba52..d14836ed2114 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -13,136 +13,110 @@
 #ifndef __DB8500_PRCMU_REGS_H
 #define __DB8500_PRCMU_REGS_H
-#include <mach/hardware.h>
 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
-#define PRCM_CLK_MGT(_offset) (void __iomem *)(IO_ADDRESS(U8500_PRCMU_BASE) \
+#define PRCM_ACLK_MGT           (0x004)
-        + _offset)
+#define PRCM_SVACLK_MGT         (0x008)
-#define PRCM_ACLK_MGT           PRCM_CLK_MGT(0x004)
+#define PRCM_SIACLK_MGT         (0x00C)
-#define PRCM_SVACLK_MGT         PRCM_CLK_MGT(0x008)
+#define PRCM_SGACLK_MGT         (0x014)
-#define PRCM_SIACLK_MGT         PRCM_CLK_MGT(0x00C)
+#define PRCM_UARTCLK_MGT        (0x018)
-#define PRCM_SGACLK_MGT         PRCM_CLK_MGT(0x014)
+#define PRCM_MSP02CLK_MGT       (0x01C)
-#define PRCM_UARTCLK_MGT        PRCM_CLK_MGT(0x018)
+#define PRCM_I2CCLK_MGT         (0x020)
-#define PRCM_MSP02CLK_MGT       PRCM_CLK_MGT(0x01C)
+#define PRCM_SDMMCCLK_MGT       (0x024)
-#define PRCM_I2CCLK_MGT         PRCM_CLK_MGT(0x020)
+#define PRCM_SLIMCLK_MGT        (0x028)
-#define PRCM_SDMMCCLK_MGT       PRCM_CLK_MGT(0x024)
+#define PRCM_PER1CLK_MGT        (0x02C)
-#define PRCM_SLIMCLK_MGT        PRCM_CLK_MGT(0x028)
+#define PRCM_PER2CLK_MGT        (0x030)
-#define PRCM_PER1CLK_MGT        PRCM_CLK_MGT(0x02C)
+#define PRCM_PER3CLK_MGT        (0x034)
-#define PRCM_PER2CLK_MGT        PRCM_CLK_MGT(0x030)
+#define PRCM_PER5CLK_MGT        (0x038)
-#define PRCM_PER3CLK_MGT        PRCM_CLK_MGT(0x034)
+#define PRCM_PER6CLK_MGT        (0x03C)
-#define PRCM_PER5CLK_MGT        PRCM_CLK_MGT(0x038)
+#define PRCM_PER7CLK_MGT        (0x040)
-#define PRCM_PER6CLK_MGT        PRCM_CLK_MGT(0x03C)
+#define PRCM_LCDCLK_MGT         (0x044)
-#define PRCM_PER7CLK_MGT        PRCM_CLK_MGT(0x040)
+#define PRCM_BMLCLK_MGT         (0x04C)
-#define PRCM_LCDCLK_MGT         PRCM_CLK_MGT(0x044)
+#define PRCM_HSITXCLK_MGT       (0x050)
-#define PRCM_BMLCLK_MGT         PRCM_CLK_MGT(0x04C)
+#define PRCM_HSIRXCLK_MGT       (0x054)
-#define PRCM_HSITXCLK_MGT       PRCM_CLK_MGT(0x050)
+#define PRCM_HDMICLK_MGT        (0x058)
-#define PRCM_HSIRXCLK_MGT       PRCM_CLK_MGT(0x054)
+#define PRCM_APEATCLK_MGT       (0x05C)
-#define PRCM_HDMICLK_MGT        PRCM_CLK_MGT(0x058)
+#define PRCM_APETRACECLK_MGT    (0x060)
-#define PRCM_APEATCLK_MGT       PRCM_CLK_MGT(0x05C)
+#define PRCM_MCDECLK_MGT        (0x064)
-#define PRCM_APETRACECLK_MGT    PRCM_CLK_MGT(0x060)
+#define PRCM_IPI2CCLK_MGT       (0x068)
-#define PRCM_MCDECLK_MGT        PRCM_CLK_MGT(0x064)
+#define PRCM_DSIALTCLK_MGT      (0x06C)
-#define PRCM_IPI2CCLK_MGT       PRCM_CLK_MGT(0x068)
+#define PRCM_DMACLK_MGT         (0x074)
-#define PRCM_DSIALTCLK_MGT      PRCM_CLK_MGT(0x06C)
+#define PRCM_B2R2CLK_MGT        (0x078)
-#define PRCM_DMACLK_MGT         PRCM_CLK_MGT(0x074)
+#define PRCM_TVCLK_MGT          (0x07C)
-#define PRCM_B2R2CLK_MGT        PRCM_CLK_MGT(0x078)
+#define PRCM_UNIPROCLK_MGT      (0x278)
-#define PRCM_TVCLK_MGT          PRCM_CLK_MGT(0x07C)
+#define PRCM_SSPCLK_MGT         (0x280)
-#define PRCM_UNIPROCLK_MGT      PRCM_CLK_MGT(0x278)
+#define PRCM_RNGCLK_MGT         (0x284)
-#define PRCM_SSPCLK_MGT         PRCM_CLK_MGT(0x280)
+#define PRCM_UICCCLK_MGT        (0x27C)
-#define PRCM_RNGCLK_MGT         PRCM_CLK_MGT(0x284)
+#define PRCM_MSP1CLK_MGT        (0x288)
-#define PRCM_UICCCLK_MGT        PRCM_CLK_MGT(0x27C)
-#define PRCM_MSP1CLK_MGT        PRCM_CLK_MGT(0x288)
+#define PRCM_ARM_PLLDIVPS       (prcmu_base + 0x118)
-#define PRCM_ARM_PLLDIVPS       (_PRCMU_BASE + 0x118)
 #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE          0x3f
 #define PRCM_ARM_PLLDIVPS_MAX_MASK              0xf
-#define PRCM_PLLARM_LOCKP       (_PRCMU_BASE + 0x0a8)
+#define PRCM_PLLARM_LOCKP       (prcmu_base + 0x0a8)
 #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3    0x2
-#define PRCM_ARM_CHGCLKREQ      (_PRCMU_BASE + 0x114)
+#define PRCM_ARM_CHGCLKREQ      (prcmu_base + 0x114)
 #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ   BIT(0)
 #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL      BIT(16)
-#define PRCM_PLLARM_ENABLE      (_PRCMU_BASE + 0x98)
+#define PRCM_PLLARM_ENABLE      (prcmu_base + 0x98)
 #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE   0x1
 #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON  0x100
-#define PRCM_ARMCLKFIX_MGT      (_PRCMU_BASE + 0x0)
+#define PRCM_ARMCLKFIX_MGT      (prcmu_base + 0x0)
-#define PRCM_A9PL_FORCE_CLKEN   (_PRCMU_BASE + 0x19C)
+#define PRCM_A9PL_FORCE_CLKEN   (prcmu_base + 0x19C)
-#define PRCM_A9_RESETN_CLR      (_PRCMU_BASE + 0x1f4)
+#define PRCM_A9_RESETN_CLR      (prcmu_base + 0x1f4)
-#define PRCM_A9_RESETN_SET      (_PRCMU_BASE + 0x1f0)
+#define PRCM_A9_RESETN_SET      (prcmu_base + 0x1f0)
-#define PRCM_ARM_LS_CLAMP       (_PRCMU_BASE + 0x30c)
+#define PRCM_ARM_LS_CLAMP       (prcmu_base + 0x30c)
-#define PRCM_SRAM_A9            (_PRCMU_BASE + 0x308)
+#define PRCM_SRAM_A9            (prcmu_base + 0x308)
 #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
 #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
-/* ARM WFI Standby signal register */
-#define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)
-#define PRCM_ARM_WFI_STANDBY_WFI0               0x08
-#define PRCM_ARM_WFI_STANDBY_WFI1               0x10
-#define PRCM_IOCR               (_PRCMU_BASE + 0x310)
-#define PRCM_IOCR_IOFORCE                       0x1
 /* CPU mailbox registers */
-#define PRCM_MBOX_CPU_VAL       (_PRCMU_BASE + 0x0fc)
+#define PRCM_MBOX_CPU_VAL       (prcmu_base + 0x0fc)
-#define PRCM_MBOX_CPU_SET       (_PRCMU_BASE + 0x100)
+#define PRCM_MBOX_CPU_SET       (prcmu_base + 0x100)
-#define PRCM_MBOX_CPU_CLR       (_PRCMU_BASE + 0x104)
+#define PRCM_MBOX_CPU_CLR       (prcmu_base + 0x104)
-/* Dual A9 core interrupt management unit registers */
+#define PRCM_HOSTACCESS_REQ     (prcmu_base + 0x334)
-#define PRCM_A9_MASK_REQ        (_PRCMU_BASE + 0x328)
-#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ       0x1
-#define PRCM_A9_MASK_ACK        (_PRCMU_BASE + 0x32c)
-#define PRCM_ARMITMSK31TO0      (_PRCMU_BASE + 0x11c)
-#define PRCM_ARMITMSK63TO32     (_PRCMU_BASE + 0x120)
-#define PRCM_ARMITMSK95TO64     (_PRCMU_BASE + 0x124)
-#define PRCM_ARMITMSK127TO96    (_PRCMU_BASE + 0x128)
-#define PRCM_POWER_STATE_VAL    (_PRCMU_BASE + 0x25C)
-#define PRCM_ARMITVAL31TO0      (_PRCMU_BASE + 0x260)
-#define PRCM_ARMITVAL63TO32     (_PRCMU_BASE + 0x264)
-#define PRCM_ARMITVAL95TO64     (_PRCMU_BASE + 0x268)
-#define PRCM_ARMITVAL127TO96    (_PRCMU_BASE + 0x26C)
-#define PRCM_HOSTACCESS_REQ     (_PRCMU_BASE + 0x334)
 #define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
 #define PRCM_HOSTACCESS_REQ_WAKE_REQ    BIT(16)
 #define ARM_WAKEUP_MODEM        0x1
-#define PRCM_ARM_IT1_CLR        (_PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_CLR        (prcmu_base + 0x48C)
-#define PRCM_ARM_IT1_VAL        (_PRCMU_BASE + 0x494)
+#define PRCM_ARM_IT1_VAL        (prcmu_base + 0x494)
-#define PRCM_HOLD_EVT           (_PRCMU_BASE + 0x174)
+#define PRCM_HOLD_EVT           (prcmu_base + 0x174)
-#define PRCM_MOD_AWAKE_STATUS   (_PRCMU_BASE + 0x4A0)
+#define PRCM_MOD_AWAKE_STATUS   (prcmu_base + 0x4A0)
 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE     BIT(0)
 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE       BIT(1)
 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO   BIT(2)
-#define PRCM_ITSTATUS0          (_PRCMU_BASE + 0x148)
+#define PRCM_ITSTATUS0          (prcmu_base + 0x148)
-#define PRCM_ITSTATUS1          (_PRCMU_BASE + 0x150)
+#define PRCM_ITSTATUS1          (prcmu_base + 0x150)
-#define PRCM_ITSTATUS2          (_PRCMU_BASE + 0x158)
+#define PRCM_ITSTATUS2          (prcmu_base + 0x158)
-#define PRCM_ITSTATUS3          (_PRCMU_BASE + 0x160)
+#define PRCM_ITSTATUS3          (prcmu_base + 0x160)
-#define PRCM_ITSTATUS4          (_PRCMU_BASE + 0x168)
+#define PRCM_ITSTATUS4          (prcmu_base + 0x168)
-#define PRCM_ITSTATUS5          (_PRCMU_BASE + 0x484)
+#define PRCM_ITSTATUS5          (prcmu_base + 0x484)
-#define PRCM_ITCLEAR5           (_PRCMU_BASE + 0x488)
+#define PRCM_ITCLEAR5           (prcmu_base + 0x488)
-#define PRCM_ARMIT_MASKXP70_IT  (_PRCMU_BASE + 0x1018)
+#define PRCM_ARMIT_MASKXP70_IT  (prcmu_base + 0x1018)
 /* System reset register */
-#define PRCM_APE_SOFTRST        (_PRCMU_BASE + 0x228)
+#define PRCM_APE_SOFTRST        (prcmu_base + 0x228)
 /* Level shifter and clamp control registers */
-#define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)
+#define PRCM_MMIP_LS_CLAMP_SET     (prcmu_base + 0x420)
-#define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)
+#define PRCM_MMIP_LS_CLAMP_CLR     (prcmu_base + 0x424)
 #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP         BIT(11)
 #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI        BIT(22)
 /* PRCMU clock/PLL/reset registers */
-#define PRCM_PLLSOC0_FREQ          (_PRCMU_BASE + 0x080)
+#define PRCM_PLLSOC0_FREQ          (prcmu_base + 0x080)
-#define PRCM_PLLSOC1_FREQ          (_PRCMU_BASE + 0x084)
+#define PRCM_PLLSOC1_FREQ          (prcmu_base + 0x084)
-#define PRCM_PLLARM_FREQ           (_PRCMU_BASE + 0x088)
+#define PRCM_PLLARM_FREQ           (prcmu_base + 0x088)
-#define PRCM_PLLDDR_FREQ           (_PRCMU_BASE + 0x08C)
+#define PRCM_PLLDDR_FREQ           (prcmu_base + 0x08C)
 #define PRCM_PLL_FREQ_D_SHIFT   0
 #define PRCM_PLL_FREQ_D_MASK    BITS(0, 7)
 #define PRCM_PLL_FREQ_N_SHIFT   8
@@ -152,14 +126,14 @@
 #define PRCM_PLL_FREQ_SELDIV2   BIT(24)
 #define PRCM_PLL_FREQ_DIV2EN    BIT(25)
-#define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)
+#define PRCM_PLLDSI_FREQ           (prcmu_base + 0x500)
-#define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)
+#define PRCM_PLLDSI_ENABLE         (prcmu_base + 0x504)
-#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
+#define PRCM_PLLDSI_LOCKP          (prcmu_base + 0x508)
-#define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)
+#define PRCM_DSI_PLLOUT_SEL        (prcmu_base + 0x530)
-#define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)
+#define PRCM_DSITVCLK_DIV          (prcmu_base + 0x52C)
-#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
+#define PRCM_PLLDSI_LOCKP          (prcmu_base + 0x508)
-#define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
+#define PRCM_APE_RESETN_SET        (prcmu_base + 0x1E4)
-#define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
+#define PRCM_APE_RESETN_CLR        (prcmu_base + 0x1E8)
 #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0)
@@ -188,30 +162,30 @@
 #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14)
-#define PRCM_CLKOCR                (_PRCMU_BASE + 0x1CC)
+#define PRCM_CLKOCR                (prcmu_base + 0x1CC)
 #define PRCM_CLKOCR_CLKOUT0_REF_CLK     (1 << 0)
 #define PRCM_CLKOCR_CLKOUT0_MASK        BITS(0, 13)
 #define PRCM_CLKOCR_CLKOUT1_REF_CLK     (1 << 16)
 #define PRCM_CLKOCR_CLKOUT1_MASK        BITS(16, 29)
 /* ePOD and memory power signal control registers */
-#define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)
+#define PRCM_EPOD_C_SET            (prcmu_base + 0x410)
-#define PRCM_SRAM_LS_SLEEP         (_PRCMU_BASE + 0x304)
+#define PRCM_SRAM_LS_SLEEP         (prcmu_base + 0x304)
 /* Debug power control unit registers */
-#define PRCM_POWER_STATE_SET       (_PRCMU_BASE + 0x254)
+#define PRCM_POWER_STATE_SET       (prcmu_base + 0x254)
 /* Miscellaneous unit registers */
-#define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)
+#define PRCM_DSI_SW_RESET          (prcmu_base + 0x324)
-#define PRCM_GPIOCR                (_PRCMU_BASE + 0x138)
+#define PRCM_GPIOCR                (prcmu_base + 0x138)
 #define PRCM_GPIOCR_DBG_STM_MOD_CMD1            0x800
 #define PRCM_GPIOCR_DBG_UARTMOD_CMD0            0x1
 /* PRCMU HW semaphore */
-#define PRCM_SEM                   (_PRCMU_BASE + 0x400)
+#define PRCM_SEM                   (prcmu_base + 0x400)
 #define PRCM_SEM_PRCM_SEM BIT(0)
-#define PRCM_TCR                   (_PRCMU_BASE + 0x1C8)
+#define PRCM_TCR                   (prcmu_base + 0x1C8)
 #define PRCM_TCR_TENSEL_MASK       BITS(0, 7)
 #define PRCM_TCR_STOP_TIMERS       BIT(16)
 #define PRCM_TCR_DOZE_MODE         BIT(17)
@@ -239,15 +213,15 @@
 /* GPIOCR register */
 #define PRCM_GPIOCR_SPI2_SELECT BIT(23)
-#define PRCM_DDR_SUBSYS_APE_MINBW       (_PRCMU_BASE + 0x438)
+#define PRCM_DDR_SUBSYS_APE_MINBW       (prcmu_base + 0x438)
-#define PRCM_CGATING_BYPASS             (_PRCMU_BASE + 0x134)
+#define PRCM_CGATING_BYPASS             (prcmu_base + 0x134)
 #define PRCM_CGATING_BYPASS_ICN2        BIT(6)
 /* Miscellaneous unit registers */
-#define PRCM_RESOUTN_SET                (_PRCMU_BASE + 0x214)
+#define PRCM_RESOUTN_SET                (prcmu_base + 0x214)
-#define PRCM_RESOUTN_CLR                (_PRCMU_BASE + 0x218)
+#define PRCM_RESOUTN_CLR                (prcmu_base + 0x218)
 /* System reset register */
-#define PRCM_APE_SOFTRST                (_PRCMU_BASE + 0x228)
+#define PRCM_APE_SOFTRST                (prcmu_base + 0x228)
 #endif /* __DB8500_PRCMU_REGS_H */
diff --git a/drivers/mmc/host/sdhci-cns3xxx.c b/drivers/mmc/host/sdhci-cns3xxx.c
index 30bfdc4ae52a..6ba8502c1ee2 100644
--- a/drivers/mmc/host/sdhci-cns3xxx.c
+++ b/drivers/mmc/host/sdhci-cns3xxx.c
@@ -16,7 +16,6 @@
 #include <linux/device.h>
 #include <linux/mmc/host.h>
 #include <linux/module.h>
-#include <mach/cns3xxx.h>
 #include "sdhci-pltfm.h"
 static unsigned int sdhci_cns3xxx_get_max_clk(struct sdhci_host *host)
diff --git a/arch/arm/plat-samsung/include/plat/regs-sdhci.h b/drivers/mmc/host/sdhci-s3c-regs.h
index e34049ad44cc..e34049ad44cc 100644
--- a/arch/arm/plat-samsung/include/plat/regs-sdhci.h
+++ b/drivers/mmc/host/sdhci-s3c-regs.h
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 7363efe72287..e4f52b5c2592 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -15,6 +15,7 @@
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/mmc-sdhci-s3c.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -28,9 +29,7 @@
 #include <linux/mmc/host.h>
-#include <plat/sdhci.h>
+#include "sdhci-s3c-regs.h"
-#include <plat/regs-sdhci.h>
 #include "sdhci.h"
 #define MAX_BUS_CLK     (4)
diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c
index 33f2a8fb8df9..2cf74085f935 100644
--- a/drivers/mtd/onenand/samsung.c
+++ b/drivers/mtd/onenand/samsung.c
@@ -23,11 +23,11 @@
 #include <linux/mtd/partitions.h>
 #include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 #include <asm/mach/flash.h>
-#include <plat/regs-onenand.h>
-#include <linux/io.h>
+#include "samsung.h"
 enum soc_type {
        TYPE_S3C6400,
diff --git a/arch/arm/plat-samsung/include/plat/regs-onenand.h b/drivers/mtd/onenand/samsung.h
index 930ea8b88ed3..c4a80e67e438 100644
--- a/arch/arm/plat-samsung/include/plat/regs-onenand.h
+++ b/drivers/mtd/onenand/samsung.h
@@ -11,8 +11,6 @@
 #ifndef __SAMSUNG_ONENAND_H__
 #define __SAMSUNG_ONENAND_H__
-#include <mach/hardware.h>
 /*
 * OneNAND Controller
 */
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 1ed23d02011e..bc9d1be27fb0 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -1347,7 +1347,7 @@ static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
        struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
                struct sirfsoc_gpio_bank, chip);
-        return irq_find_mapping(bank->domain, offset);
+        return irq_create_mapping(bank->domain, offset);
 }
 static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
@@ -1485,7 +1485,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
        struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
        u32 status, ctrl;
        int idx = 0;
-        unsigned int first_irq;
        struct irq_chip *chip = irq_get_chip(irq);
        chained_irq_enter(chip, desc);
@@ -1499,8 +1498,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
                return;
        }
-        first_irq = bank->domain->revmap_data.legacy.first_irq;
        while (status) {
                ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
@@ -1511,7 +1508,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
                if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
                        pr_debug("%s: gpio id %d idx %d happens\n",
                                __func__, bank->id, idx);
-                        generic_handle_irq(first_irq + idx);
+                        generic_handle_irq(irq_find_mapping(bank->domain, idx));
                }
                idx++;
@@ -1764,9 +1761,8 @@ static int sirfsoc_gpio_probe(struct device_node *np)
                        goto out;
                }
-                bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
+                bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
-                        SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
+                                                &sirfsoc_gpio_irq_simple_ops, bank);
-                        &sirfsoc_gpio_irq_simple_ops, bank);
                if (!bank->domain) {
                        pr_err("%s: Failed to create irqdomain\n", np->full_name);
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 8e96c00936be..14040b22888d 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -29,9 +29,8 @@
 #include <linux/uaccess.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <plat/regs-rtc.h>
+#include "rtc-s3c.h"
 enum s3c_cpu_type {
        TYPE_S3C2410,
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/drivers/rtc/rtc-s3c.h
index 0f8263e93eea..004b61a8343f 100644
--- a/arch/arm/plat-samsung/include/plat/regs-rtc.h
+++ b/drivers/rtc/rtc-s3c.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
+/*
- *
 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
 *                    http://www.simtec.co.uk/products/SWLINUX/
 *
diff --git a/drivers/staging/ste_rmi4/Makefile b/drivers/staging/ste_rmi4/Makefile
index e4c03351420f..6cce2ed187ef 100644
--- a/drivers/staging/ste_rmi4/Makefile
+++ b/drivers/staging/ste_rmi4/Makefile
@@ -2,4 +2,3 @@
 # Makefile for the RMI4 touchscreen driver.
 #
 obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += synaptics_i2c_rmi4.o
-obj-$(CONFIG_MACH_MOP500) += board-mop500-u8500uib-rmi4.o
diff --git a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
deleted file mode 100644
index 47439c3f7258..000000000000
--- a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Some platform data for the RMI4 touchscreen that will override the __weak
- * platform data in the Ux500 machine if this driver is activated.
- */
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <mach/irqs.h>
-#include "synaptics_i2c_rmi4.h"
-/*
- * Synaptics RMI4 touchscreen interface on the U8500 UIB
- */
-/*
- * Descriptor structure.
- * Describes the number of i2c devices on the bus that speak RMI.
- */
-static struct synaptics_rmi4_platform_data rmi4_i2c_dev_platformdata = {
-        .irq_number     = NOMADIK_GPIO_TO_IRQ(84),
-        .irq_type       = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
-        .x_flip         = false,
-        .y_flip         = true,
-};
-struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
-        {
-                I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
-                .platform_data = &rmi4_i2c_dev_platformdata,
-        },
-};
diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
index a126b25c82d5..fe667dde43ce 100644
--- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
+++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
@@ -864,6 +864,16 @@ static int synaptics_rmi4_i2c_query_device(struct synaptics_rmi4_data *pdata)
        return 0;
 }
+/*
+ * Descriptor structure.
+ * Describes the number of i2c devices on the bus that speak RMI.
+ */
+static struct synaptics_rmi4_platform_data synaptics_rmi4_platformdata = {
+        .irq_type       = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
+        .x_flip         = false,
+        .y_flip         = true,
+};
 /**
 * synaptics_rmi4_probe() - Initialze the i2c-client touchscreen driver
 * @i2c: i2c client structure pointer
@@ -890,10 +900,8 @@ static int synaptics_rmi4_probe
                return -EIO;
        }
-        if (!platformdata) {
+        if (!platformdata)
-                dev_err(&client->dev, "%s: no platform data\n", __func__);
+                platformdata = &synaptics_rmi4_platformdata;
-                return -EINVAL;
-        }
        /* Allocate and initialize the instance data for this client */
        rmi4_data = kcalloc(2, sizeof(struct synaptics_rmi4_data),
@@ -977,13 +985,13 @@ static int synaptics_rmi4_probe
        synaptics_rmi4_i2c_block_read(rmi4_data,
                        rmi4_data->fn01_data_base_addr + 1, intr_status,
                                rmi4_data->number_of_interrupt_register);
-        retval = request_threaded_irq(platformdata->irq_number, NULL,
+        retval = request_threaded_irq(client->irq, NULL,
                                        synaptics_rmi4_irq,
                                        platformdata->irq_type,
                                        DRIVER_NAME, rmi4_data);
        if (retval) {
                dev_err(&client->dev, "%s:Unable to get attn irq %d\n",
-                                __func__, platformdata->irq_number);
+                                __func__, client->irq);
                goto err_query_dev;
        }
@@ -996,7 +1004,7 @@ static int synaptics_rmi4_probe
        return retval;
 err_free_irq:
-        free_irq(platformdata->irq_number, rmi4_data);
+        free_irq(client->irq, rmi4_data);
 err_query_dev:
        regulator_disable(rmi4_data->regulator);
 err_regulator_enable:
@@ -1019,11 +1027,10 @@ err_input:
 static int synaptics_rmi4_remove(struct i2c_client *client)
 {
        struct synaptics_rmi4_data *rmi4_data = i2c_get_clientdata(client);
-        const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
        rmi4_data->touch_stopped = true;
        wake_up(&rmi4_data->wait);
-        free_irq(pdata->irq_number, rmi4_data);
+        free_irq(client->irq, rmi4_data);
        input_unregister_device(rmi4_data->input_dev);
        regulator_disable(rmi4_data->regulator);
        regulator_put(rmi4_data->regulator);
@@ -1046,10 +1053,9 @@ static int synaptics_rmi4_suspend(struct device *dev)
        int retval;
        unsigned char intr_status;
        struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
-        const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
        rmi4_data->touch_stopped = true;
-        disable_irq(pdata->irq_number);
+        disable_irq(rmi4_data->i2c_client->irq);
        retval = synaptics_rmi4_i2c_block_read(rmi4_data,
                                rmi4_data->fn01_data_base_addr + 1,
@@ -1080,11 +1086,10 @@ static int synaptics_rmi4_resume(struct device *dev)
        int retval;
        unsigned char intr_status;
        struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
-        const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
        regulator_enable(rmi4_data->regulator);
-        enable_irq(pdata->irq_number);
+        enable_irq(rmi4_data->i2c_client->irq);
        rmi4_data->touch_stopped = false;
        retval = synaptics_rmi4_i2c_block_read(rmi4_data,
diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h
index 384436ef8068..8c9166ba71c7 100644
--- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h
+++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h
@@ -38,7 +38,6 @@
 * This structure gives platform data for rmi4.
 */
 struct synaptics_rmi4_platform_data {
-        int irq_number;
        int irq_type;
        bool x_flip;
        bool y_flip;
diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index 46568c078dee..b777ae6f0a8f 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -39,8 +39,6 @@
 #include <linux/cpu_cooling.h>
 #include <linux/of.h>
-#include <plat/cpu.h>
 /* Exynos generic registers */
 #define EXYNOS_TMU_REG_TRIMINFO         0x0
 #define EXYNOS_TMU_REG_CONTROL          0x20
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index 77a46ae2fc17..0bd69446bb05 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -489,7 +489,7 @@ struct prcmu_auto_pm_config {
 #ifdef CONFIG_MFD_DB8500_PRCMU
-void db8500_prcmu_early_init(void);
+void db8500_prcmu_early_init(u32 phy_base, u32 size);
 int prcmu_set_rc_a2p(enum romcode_write);
 enum romcode_read prcmu_get_rc_p2a(void);
 enum ap_pwrst prcmu_get_xp70_current_state(void);
@@ -522,12 +522,6 @@ int db8500_prcmu_load_a9wdog(u8 id, u32 val);
 void db8500_prcmu_system_reset(u16 reset_code);
 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
 u8 db8500_prcmu_get_power_state_result(void);
-int db8500_prcmu_gic_decouple(void);
-int db8500_prcmu_gic_recouple(void);
-int db8500_prcmu_copy_gic_settings(void);
-bool db8500_prcmu_gic_pending_irq(void);
-bool db8500_prcmu_pending_irq(void);
-bool db8500_prcmu_is_cpu_in_wfi(int cpu);
 void db8500_prcmu_enable_wakeups(u32 wakeups);
 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
 int db8500_prcmu_request_clock(u8 clock, bool enable);
@@ -553,7 +547,7 @@ void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
 #else /* !CONFIG_MFD_DB8500_PRCMU */
-static inline void db8500_prcmu_early_init(void) {}
+static inline void db8500_prcmu_early_init(u32 phy_base, u32 size) {}
 static inline int prcmu_set_rc_a2p(enum romcode_write code)
 {
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 3abcca91eecd..689e6a0d9c99 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -237,6 +237,8 @@ struct prcmu_pdata
        bool enable_set_ddr_opp;
        bool enable_ape_opp_100_voltage;
        struct ab8500_platform_data *ab_platdata;
+        int ab_irq;
+        int irq_base;
        u32 version_offset;
        u32 legacy_offset;
        u32 adt_offset;
@@ -276,9 +278,9 @@ struct prcmu_fw_version {
 #if defined(CONFIG_UX500_SOC_DB8500)
-static inline void __init prcmu_early_init(void)
+static inline void prcmu_early_init(u32 phy_base, u32 size)
 {
-        return db8500_prcmu_early_init();
+        return db8500_prcmu_early_init(phy_base, size);
 }
 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
@@ -293,36 +295,6 @@ static inline u8 prcmu_get_power_state_result(void)
        return db8500_prcmu_get_power_state_result();
 }
-static inline int prcmu_gic_decouple(void)
-{
-        return db8500_prcmu_gic_decouple();
-}
-static inline int prcmu_gic_recouple(void)
-{
-        return db8500_prcmu_gic_recouple();
-}
-static inline bool prcmu_gic_pending_irq(void)
-{
-        return db8500_prcmu_gic_pending_irq();
-}
-static inline bool prcmu_is_cpu_in_wfi(int cpu)
-{
-        return db8500_prcmu_is_cpu_in_wfi(cpu);
-}
-static inline int prcmu_copy_gic_settings(void)
-{
-        return db8500_prcmu_copy_gic_settings();
-}
-static inline bool prcmu_pending_irq(void)
-{
-        return db8500_prcmu_pending_irq();
-}
 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
 {
        return db8500_prcmu_set_epod(epod_id, epod_state);
@@ -500,7 +472,7 @@ static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
 }
 #else
-static inline void __init prcmu_early_init(void) {}
+static inline void prcmu_early_init(u32 phy_base, u32 size) {}
 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
        bool keep_ap_pll)
diff --git a/include/linux/platform_data/arm-ux500-pm.h b/include/linux/platform_data/arm-ux500-pm.h
new file mode 100644
index 000000000000..8dff64b29ec0
--- /dev/null
+++ b/include/linux/platform_data/arm-ux500-pm.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010-2013
+ * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
+ *         ST-Ericsson.
+ * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ */
+#ifndef ARM_UX500_PM_H
+#define ARM_UX500_PM_H
+int prcmu_gic_decouple(void);
+int prcmu_gic_recouple(void);
+bool prcmu_gic_pending_irq(void);
+bool prcmu_pending_irq(void);
+bool prcmu_is_cpu_in_wfi(int cpu);
+int prcmu_copy_gic_settings(void);
+void ux500_pm_init(u32 phy_base, u32 size);
+#endif /* ARM_UX500_PM_H */
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/include/linux/platform_data/asoc-ux500-msp.h
index 9991aea3d577..9991aea3d577 100644
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ b/include/linux/platform_data/asoc-ux500-msp.h
diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h
index 3af0da1f3be5..320d9c39ea0a 100644
--- a/include/linux/platform_data/clk-ux500.h
+++ b/include/linux/platform_data/clk-ux500.h
@@ -10,7 +10,8 @@
 #ifndef __CLK_UX500_H
 #define __CLK_UX500_H
-void u8500_clk_init(void);
+void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
+                    u32 clkrst5_base, u32 clkrst6_base);
 void u9540_clk_init(void);
 void u8540_clk_init(void);
diff --git a/include/linux/platform_data/mmc-sdhci-s3c.h b/include/linux/platform_data/mmc-sdhci-s3c.h
new file mode 100644
index 000000000000..249f02387a35
--- /dev/null
+++ b/include/linux/platform_data/mmc-sdhci-s3c.h
@@ -0,0 +1,56 @@
+#ifndef __PLATFORM_DATA_SDHCI_S3C_H
+#define __PLATFORM_DATA_SDHCI_S3C_H
+struct platform_device;
+enum cd_types {
+        S3C_SDHCI_CD_INTERNAL,  /* use mmc internal CD line */
+        S3C_SDHCI_CD_EXTERNAL,  /* use external callback */
+        S3C_SDHCI_CD_GPIO,      /* use external gpio pin for CD line */
+        S3C_SDHCI_CD_NONE,      /* no CD line, use polling to detect card */
+        S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
+};
+/**
+ * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
+ * @max_width: The maximum number of data bits supported.
+ * @host_caps: Standard MMC host capabilities bit field.
+ * @host_caps2: The second standard MMC host capabilities bit field.
+ * @cd_type: Type of Card Detection method (see cd_types enum above)
+ * @ext_cd_init: Initialize external card detect subsystem. Called on
+ *               sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
+ *               notify_func argument is a callback to the sdhci-s3c driver
+ *               that triggers the card detection event. Callback arguments:
+ *               dev is pointer to platform device of the host controller,
+ *               state is new state of the card (0 - removed, 1 - inserted).
+ * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on
+ *               sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL.
+ *               notify_func argument is the same callback as for ext_cd_init.
+ * @ext_cd_gpio: gpio pin used for external CD line, valid only if
+ *               cd_type == S3C_SDHCI_CD_GPIO
+ * @ext_cd_gpio_invert: invert values for external CD gpio line
+ * @cfg_gpio: Configure the GPIO for a specific card bit-width
+ *
+ * Initialisation data specific to either the machine or the platform
+ * for the device driver to use or call-back when configuring gpio or
+ * card speed information.
+*/
+struct s3c_sdhci_platdata {
+        unsigned int    max_width;
+        unsigned int    host_caps;
+        unsigned int    host_caps2;
+        unsigned int    pm_caps;
+        enum cd_types   cd_type;
+        int             ext_cd_gpio;
+        bool            ext_cd_gpio_invert;
+        int     (*ext_cd_init)(void (*notify_func)(struct platform_device *,
+                                                   int state));
+        int     (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
+                                                      int state));
+        void    (*cfg_gpio)(struct platform_device *dev, int width);
+};
+#endif /* __PLATFORM_DATA_SDHCI_S3C_H */
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/include/linux/tegra-powergate.h
index 06763fe7529d..55c29a8d5015 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/include/linux/tegra-powergate.h
@@ -1,6 +1,4 @@
 /*
- * drivers/regulator/tegra-regulator.c
- *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
@@ -40,9 +38,6 @@ struct clk;
 #define TEGRA_POWERGATE_CPU0    TEGRA_POWERGATE_CPU
 #define TEGRA_POWERGATE_3D0     TEGRA_POWERGATE_3D
-int  __init tegra_powergate_init(void);
-int tegra_cpu_powergate_id(int cpuid);
 int tegra_powergate_is_powered(int id);
 int tegra_powergate_power_on(int id);
 int tegra_powergate_power_off(int id);
diff --git a/sound/soc/ux500/mop500_ab8500.c b/sound/soc/ux500/mop500_ab8500.c
index 78cce236693e..892ad9a05c9f 100644
--- a/sound/soc/ux500/mop500_ab8500.c
+++ b/sound/soc/ux500/mop500_ab8500.c
@@ -17,8 +17,6 @@
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <mach/hardware.h>
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
 #include <sound/pcm.h>
diff --git a/sound/soc/ux500/ux500_msp_dai.c b/sound/soc/ux500/ux500_msp_dai.c
index 94a3e5705aaa..54028cf76511 100644
--- a/sound/soc/ux500/ux500_msp_dai.c
+++ b/sound/soc/ux500/ux500_msp_dai.c
@@ -19,9 +19,7 @@
 #include <linux/clk.h>
 #include <linux/regulator/consumer.h>
 #include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/asoc-ux500-msp.h>
-#include <mach/hardware.h>
-#include <mach/msp.h>
 #include <sound/soc.h>
 #include <sound/soc-dai.h>
diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c
index a26c6bf0a29b..f2db6c90a9e2 100644
--- a/sound/soc/ux500/ux500_msp_i2s.c
+++ b/sound/soc/ux500/ux500_msp_i2s.c
@@ -20,9 +20,7 @@
 #include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/platform_data/asoc-ux500-msp.h>
-#include <mach/hardware.h>
-#include <mach/msp.h>
 #include <sound/soc.h>
diff --git a/sound/soc/ux500/ux500_msp_i2s.h b/sound/soc/ux500/ux500_msp_i2s.h
index 1311c0df7628..437f0c032c58 100644
--- a/sound/soc/ux500/ux500_msp_i2s.h
+++ b/sound/soc/ux500/ux500_msp_i2s.h
@@ -17,8 +17,6 @@
 #include <linux/platform_device.h>
-#include <mach/msp.h>
 #define MSP_INPUT_FREQ_APB 48000000
 /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono),
author	Linus Torvalds <torvalds@linux-foundation.org>	2013-05-02 12:38:16 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2013-05-02 12:38:16 -0400
commit	99c6bcf46d2233d33e441834e958ed0bc22b190a (patch)
tree	25abf5e856bc0f08d75e623715eb5acc4d4de2b2
parent	97b1007a2924aaa9126398623f6755a8c3c6a616 (diff)
parent	2fdfe1c26fb9f24cfdf124384abb35396ca2cd3f (diff)