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-rw-r--r--arch/arm/mach-spear/spear320.c277
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diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c
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1/*
2 * arch/arm/mach-spear3xx/spear320.c
3 *
4 * SPEAr320 machine source file
5 *
6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define pr_fmt(fmt) "SPEAr320: " fmt
15
16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/amba/serial.h>
19#include <linux/irqchip.h>
20#include <linux/of_platform.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/map.h>
23#include "generic.h"
24#include <mach/spear.h>
25
26#define SPEAR320_UART1_BASE UL(0xA3000000)
27#define SPEAR320_UART2_BASE UL(0xA4000000)
28#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000)
30
31/* DMAC platform data's slave info */
32struct pl08x_channel_data spear320_dma_info[] = {
33 {
34 .bus_id = "uart0_rx",
35 .min_signal = 2,
36 .max_signal = 2,
37 .muxval = 0,
38 .periph_buses = PL08X_AHB1,
39 }, {
40 .bus_id = "uart0_tx",
41 .min_signal = 3,
42 .max_signal = 3,
43 .muxval = 0,
44 .periph_buses = PL08X_AHB1,
45 }, {
46 .bus_id = "ssp0_rx",
47 .min_signal = 8,
48 .max_signal = 8,
49 .muxval = 0,
50 .periph_buses = PL08X_AHB1,
51 }, {
52 .bus_id = "ssp0_tx",
53 .min_signal = 9,
54 .max_signal = 9,
55 .muxval = 0,
56 .periph_buses = PL08X_AHB1,
57 }, {
58 .bus_id = "i2c0_rx",
59 .min_signal = 10,
60 .max_signal = 10,
61 .muxval = 0,
62 .periph_buses = PL08X_AHB1,
63 }, {
64 .bus_id = "i2c0_tx",
65 .min_signal = 11,
66 .max_signal = 11,
67 .muxval = 0,
68 .periph_buses = PL08X_AHB1,
69 }, {
70 .bus_id = "irda",
71 .min_signal = 12,
72 .max_signal = 12,
73 .muxval = 0,
74 .periph_buses = PL08X_AHB1,
75 }, {
76 .bus_id = "adc",
77 .min_signal = 13,
78 .max_signal = 13,
79 .muxval = 0,
80 .periph_buses = PL08X_AHB1,
81 }, {
82 .bus_id = "to_jpeg",
83 .min_signal = 14,
84 .max_signal = 14,
85 .muxval = 0,
86 .periph_buses = PL08X_AHB1,
87 }, {
88 .bus_id = "from_jpeg",
89 .min_signal = 15,
90 .max_signal = 15,
91 .muxval = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp1_rx",
95 .min_signal = 0,
96 .max_signal = 0,
97 .muxval = 1,
98 .periph_buses = PL08X_AHB2,
99 }, {
100 .bus_id = "ssp1_tx",
101 .min_signal = 1,
102 .max_signal = 1,
103 .muxval = 1,
104 .periph_buses = PL08X_AHB2,
105 }, {
106 .bus_id = "ssp2_rx",
107 .min_signal = 2,
108 .max_signal = 2,
109 .muxval = 1,
110 .periph_buses = PL08X_AHB2,
111 }, {
112 .bus_id = "ssp2_tx",
113 .min_signal = 3,
114 .max_signal = 3,
115 .muxval = 1,
116 .periph_buses = PL08X_AHB2,
117 }, {
118 .bus_id = "uart1_rx",
119 .min_signal = 4,
120 .max_signal = 4,
121 .muxval = 1,
122 .periph_buses = PL08X_AHB2,
123 }, {
124 .bus_id = "uart1_tx",
125 .min_signal = 5,
126 .max_signal = 5,
127 .muxval = 1,
128 .periph_buses = PL08X_AHB2,
129 }, {
130 .bus_id = "uart2_rx",
131 .min_signal = 6,
132 .max_signal = 6,
133 .muxval = 1,
134 .periph_buses = PL08X_AHB2,
135 }, {
136 .bus_id = "uart2_tx",
137 .min_signal = 7,
138 .max_signal = 7,
139 .muxval = 1,
140 .periph_buses = PL08X_AHB2,
141 }, {
142 .bus_id = "i2c1_rx",
143 .min_signal = 8,
144 .max_signal = 8,
145 .muxval = 1,
146 .periph_buses = PL08X_AHB2,
147 }, {
148 .bus_id = "i2c1_tx",
149 .min_signal = 9,
150 .max_signal = 9,
151 .muxval = 1,
152 .periph_buses = PL08X_AHB2,
153 }, {
154 .bus_id = "i2c2_rx",
155 .min_signal = 10,
156 .max_signal = 10,
157 .muxval = 1,
158 .periph_buses = PL08X_AHB2,
159 }, {
160 .bus_id = "i2c2_tx",
161 .min_signal = 11,
162 .max_signal = 11,
163 .muxval = 1,
164 .periph_buses = PL08X_AHB2,
165 }, {
166 .bus_id = "i2s_rx",
167 .min_signal = 12,
168 .max_signal = 12,
169 .muxval = 1,
170 .periph_buses = PL08X_AHB2,
171 }, {
172 .bus_id = "i2s_tx",
173 .min_signal = 13,
174 .max_signal = 13,
175 .muxval = 1,
176 .periph_buses = PL08X_AHB2,
177 }, {
178 .bus_id = "rs485_rx",
179 .min_signal = 14,
180 .max_signal = 14,
181 .muxval = 1,
182 .periph_buses = PL08X_AHB2,
183 }, {
184 .bus_id = "rs485_tx",
185 .min_signal = 15,
186 .max_signal = 15,
187 .muxval = 1,
188 .periph_buses = PL08X_AHB2,
189 },
190};
191
192static struct pl022_ssp_controller spear320_ssp_data[] = {
193 {
194 .bus_id = 1,
195 .enable_dma = 1,
196 .dma_filter = pl08x_filter_id,
197 .dma_tx_param = "ssp1_tx",
198 .dma_rx_param = "ssp1_rx",
199 .num_chipselect = 2,
200 }, {
201 .bus_id = 2,
202 .enable_dma = 1,
203 .dma_filter = pl08x_filter_id,
204 .dma_tx_param = "ssp2_tx",
205 .dma_rx_param = "ssp2_rx",
206 .num_chipselect = 2,
207 }
208};
209
210static struct amba_pl011_data spear320_uart_data[] = {
211 {
212 .dma_filter = pl08x_filter_id,
213 .dma_tx_param = "uart1_tx",
214 .dma_rx_param = "uart1_rx",
215 }, {
216 .dma_filter = pl08x_filter_id,
217 .dma_tx_param = "uart2_tx",
218 .dma_rx_param = "uart2_rx",
219 },
220};
221
222/* Add SPEAr310 auxdata to pass platform data */
223static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
224 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
225 &pl022_plat_data),
226 OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
227 &pl080_plat_data),
228 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
229 &spear320_ssp_data[0]),
230 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
231 &spear320_ssp_data[1]),
232 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
233 &spear320_uart_data[0]),
234 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
235 &spear320_uart_data[1]),
236 {}
237};
238
239static void __init spear320_dt_init(void)
240{
241 pl080_plat_data.slave_channels = spear320_dma_info;
242 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
243
244 of_platform_populate(NULL, of_default_bus_match_table,
245 spear320_auxdata_lookup, NULL);
246}
247
248static const char * const spear320_dt_board_compat[] = {
249 "st,spear320",
250 "st,spear320-evb",
251 "st,spear320-hmi",
252 NULL,
253};
254
255struct map_desc spear320_io_desc[] __initdata = {
256 {
257 .virtual = (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE,
258 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
259 .length = SZ_16M,
260 .type = MT_DEVICE
261 },
262};
263
264static void __init spear320_map_io(void)
265{
266 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
267 spear3xx_map_io();
268}
269
270DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
271 .map_io = spear320_map_io,
272 .init_irq = irqchip_init,
273 .init_time = spear3xx_timer_init,
274 .init_machine = spear320_dt_init,
275 .restart = spear_restart,
276 .dt_compat = spear320_dt_board_compat,
277MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 21:52:22 -0500