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-rw-r--r--drivers/tty/serial/68328serial.h187
-rw-r--r--drivers/tty/serial/68360serial.c2979
-rw-r--r--drivers/tty/serial/8250.c3452
-rw-r--r--drivers/tty/serial/8250.h80
-rw-r--r--drivers/tty/serial/8250_accent.c45
-rw-r--r--drivers/tty/serial/8250_acorn.c141
-rw-r--r--drivers/tty/serial/8250_boca.c59
-rw-r--r--drivers/tty/serial/8250_early.c287
-rw-r--r--drivers/tty/serial/8250_exar_st16c554.c50
-rw-r--r--drivers/tty/serial/8250_fourport.c51
-rw-r--r--drivers/tty/serial/8250_gsc.c122
-rw-r--r--drivers/tty/serial/8250_hp300.c327
-rw-r--r--drivers/tty/serial/8250_hub6.c56
-rw-r--r--drivers/tty/serial/8250_mca.c61
-rw-r--r--drivers/tty/serial/8250_pci.c4136
-rw-r--r--drivers/tty/serial/8250_pnp.c524
-rw-r--r--drivers/tty/serial/bfin_5xx.c1596
-rw-r--r--drivers/tty/serial/max3107-aava.c344
-rw-r--r--drivers/tty/serial/max3107.c1213
-rw-r--r--drivers/tty/serial/max3107.h441
-rw-r--r--drivers/tty/serial/s3c2410.c115
-rw-r--r--drivers/tty/serial/s3c2412.c149
-rw-r--r--drivers/tty/serial/s3c2440.c178
-rw-r--r--drivers/tty/serial/s3c6400.c149
-rw-r--r--drivers/tty/serial/s5pv210.c158
-rw-r--r--drivers/tty/serial/serial_cs.c870
-rw-r--r--drivers/tty/serial/suncore.h33
-rw-r--r--drivers/tty/serial/tegra_hsuart.c1682
28 files changed, 19485 insertions, 0 deletions
diff --git a/drivers/tty/serial/68328serial.h b/drivers/tty/serial/68328serial.h
new file mode 100644
index 00000000000..8c9c3c0745d
--- /dev/null
+++ b/drivers/tty/serial/68328serial.h
@@ -0,0 +1,187 @@
1/* 68328serial.h: Definitions for the mc68328 serial driver.
2 *
3 * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
4 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
5 * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
6 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
7 *
8 * VZ Support/Fixes Evan Stawnyczy <e@lineo.ca>
9 */
10
11#ifndef _MC683XX_SERIAL_H
12#define _MC683XX_SERIAL_H
13
14
15struct serial_struct {
16 int type;
17 int line;
18 int port;
19 int irq;
20 int flags;
21 int xmit_fifo_size;
22 int custom_divisor;
23 int baud_base;
24 unsigned short close_delay;
25 char reserved_char[2];
26 int hub6; /* FIXME: We don't have AT&T Hub6 boards! */
27 unsigned short closing_wait; /* time to wait before closing */
28 unsigned short closing_wait2; /* no longer used... */
29 int reserved[4];
30};
31
32/*
33 * For the close wait times, 0 means wait forever for serial port to
34 * flush its output. 65535 means don't wait at all.
35 */
36#define S_CLOSING_WAIT_INF 0
37#define S_CLOSING_WAIT_NONE 65535
38
39/*
40 * Definitions for S_struct (and serial_struct) flags field
41 */
42#define S_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes
43 on the callout port */
44#define S_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */
45#define S_SAK 0x0004 /* Secure Attention Key (Orange book) */
46#define S_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
47
48#define S_SPD_MASK 0x0030
49#define S_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */
50
51#define S_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */
52#define S_SPD_CUST 0x0030 /* Use user-specified divisor */
53
54#define S_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
55#define S_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */
56#define S_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
57#define S_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */
58#define S_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */
59
60#define S_FLAGS 0x0FFF /* Possible legal S flags */
61#define S_USR_MASK 0x0430 /* Legal flags that non-privileged
62 * users can set or reset */
63
64/* Internal flags used only by kernel/chr_drv/serial.c */
65#define S_INITIALIZED 0x80000000 /* Serial port was initialized */
66#define S_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
67#define S_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
68#define S_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
69#define S_CLOSING 0x08000000 /* Serial port is closing */
70#define S_CTS_FLOW 0x04000000 /* Do CTS flow control */
71#define S_CHECK_CD 0x02000000 /* i.e., CLOCAL */
72
73/* Software state per channel */
74
75#ifdef __KERNEL__
76
77/*
78 * I believe this is the optimal setting that reduces the number of interrupts.
79 * At high speeds the output might become a little "bursted" (use USTCNT_TXHE
80 * if that bothers you), but in most cases it will not, since we try to
81 * transmit characters every time rs_interrupt is called. Thus, quite often
82 * you'll see that a receive interrupt occures before the transmit one.
83 * -- Vladimir Gurevich
84 */
85#define USTCNT_TX_INTR_MASK (USTCNT_TXEE)
86
87/*
88 * 68328 and 68EZ328 UARTS are a little bit different. EZ328 has special
89 * "Old data interrupt" which occures whenever the data stay in the FIFO
90 * longer than 30 bits time. This allows us to use FIFO without compromising
91 * latency. '328 does not have this feature and without the real 328-based
92 * board I would assume that RXRE is the safest setting.
93 *
94 * For EZ328 I use RXHE (Half empty) interrupt to reduce the number of
95 * interrupts. RXFE (receive queue full) causes the system to lose data
96 * at least at 115200 baud
97 *
98 * If your board is busy doing other stuff, you might consider to use
99 * RXRE (data ready intrrupt) instead.
100 *
101 * The other option is to make these INTR masks run-time configurable, so
102 * that people can dynamically adapt them according to the current usage.
103 * -- Vladimir Gurevich
104 */
105
106/* (es) */
107#if defined(CONFIG_M68EZ328) || defined(CONFIG_M68VZ328)
108#define USTCNT_RX_INTR_MASK (USTCNT_RXHE | USTCNT_ODEN)
109#elif defined(CONFIG_M68328)
110#define USTCNT_RX_INTR_MASK (USTCNT_RXRE)
111#else
112#error Please, define the Rx interrupt events for your CPU
113#endif
114/* (/es) */
115
116/*
117 * This is our internal structure for each serial port's state.
118 *
119 * Many fields are paralleled by the structure used by the serial_struct
120 * structure.
121 *
122 * For definitions of the flags field, see tty.h
123 */
124
125struct m68k_serial {
126 char soft_carrier; /* Use soft carrier on this channel */
127 char break_abort; /* Is serial console in, so process brk/abrt */
128 char is_cons; /* Is this our console. */
129
130 /* We need to know the current clock divisor
131 * to read the bps rate the chip has currently
132 * loaded.
133 */
134 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */
135 int baud;
136 int magic;
137 int baud_base;
138 int port;
139 int irq;
140 int flags; /* defined in tty.h */
141 int type; /* UART type */
142 struct tty_struct *tty;
143 int read_status_mask;
144 int ignore_status_mask;
145 int timeout;
146 int xmit_fifo_size;
147 int custom_divisor;
148 int x_char; /* xon/xoff character */
149 int close_delay;
150 unsigned short closing_wait;
151 unsigned short closing_wait2;
152 unsigned long event;
153 unsigned long last_active;
154 int line;
155 int count; /* # of fd on device */
156 int blocked_open; /* # of blocked opens */
157 unsigned char *xmit_buf;
158 int xmit_head;
159 int xmit_tail;
160 int xmit_cnt;
161 struct work_struct tqueue;
162 wait_queue_head_t open_wait;
163 wait_queue_head_t close_wait;
164};
165
166
167#define SERIAL_MAGIC 0x5301
168
169/*
170 * The size of the serial xmit buffer is 1 page, or 4096 bytes
171 */
172#define SERIAL_XMIT_SIZE 4096
173
174/*
175 * Events are used to schedule things to happen at timer-interrupt
176 * time, instead of at rs interrupt time.
177 */
178#define RS_EVENT_WRITE_WAKEUP 0
179
180/*
181 * Define the number of ports supported and their irqs.
182 */
183#define NR_PORTS 1
184#define UART_IRQ_DEFNS {UART_IRQ_NUM}
185
186#endif /* __KERNEL__ */
187#endif /* !(_MC683XX_SERIAL_H) */
diff --git a/drivers/tty/serial/68360serial.c b/drivers/tty/serial/68360serial.c
new file mode 100644
index 00000000000..0a3e8787ed5
--- /dev/null
+++ b/drivers/tty/serial/68360serial.c
@@ -0,0 +1,2979 @@
1/*
2 * UART driver for 68360 CPM SCC or SMC
3 * Copyright (c) 2000 D. Jeff Dionne <jeff@uclinux.org>,
4 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.ca>
5 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
6 *
7 * I used the serial.c driver as the framework for this driver.
8 * Give credit to those guys.
9 * The original code was written for the MBX860 board. I tried to make
10 * it generic, but there may be some assumptions in the structures that
11 * have to be fixed later.
12 * To save porting time, I did not bother to change any object names
13 * that are not accessed outside of this file.
14 * It still needs lots of work........When it was easy, I included code
15 * to support the SCCs, but this has never been tested, nor is it complete.
16 * Only the SCCs support modem control, so that is not complete either.
17 *
18 * This module exports the following rs232 io functions:
19 *
20 * int rs_360_init(void);
21 */
22
23#include <linux/module.h>
24#include <linux/errno.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/timer.h>
28#include <linux/interrupt.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/serial.h>
32#include <linux/serialP.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/fcntl.h>
36#include <linux/ptrace.h>
37#include <linux/mm.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <asm/irq.h>
41#include <asm/m68360.h>
42#include <asm/commproc.h>
43
44
45#ifdef CONFIG_KGDB
46extern void breakpoint(void);
47extern void set_debug_traps(void);
48extern int kgdb_output_string (const char* s, unsigned int count);
49#endif
50
51
52/* #ifdef CONFIG_SERIAL_CONSOLE */ /* This seems to be a post 2.0 thing - mles */
53#include <linux/console.h>
54#include <linux/jiffies.h>
55
56/* this defines the index into rs_table for the port to use
57 */
58#ifndef CONFIG_SERIAL_CONSOLE_PORT
59#define CONFIG_SERIAL_CONSOLE_PORT 1 /* ie SMC2 - note USE_SMC2 must be defined */
60#endif
61/* #endif */
62
63#if 0
64/* SCC2 for console
65 */
66#undef CONFIG_SERIAL_CONSOLE_PORT
67#define CONFIG_SERIAL_CONSOLE_PORT 2
68#endif
69
70
71#define TX_WAKEUP ASYNC_SHARE_IRQ
72
73static char *serial_name = "CPM UART driver";
74static char *serial_version = "0.03";
75
76static struct tty_driver *serial_driver;
77int serial_console_setup(struct console *co, char *options);
78
79/*
80 * Serial driver configuration section. Here are the various options:
81 */
82#define SERIAL_PARANOIA_CHECK
83#define CONFIG_SERIAL_NOPAUSE_IO
84#define SERIAL_DO_RESTART
85
86/* Set of debugging defines */
87
88#undef SERIAL_DEBUG_INTR
89#undef SERIAL_DEBUG_OPEN
90#undef SERIAL_DEBUG_FLOW
91#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
92
93#define _INLINE_ inline
94
95#define DBG_CNT(s)
96
97/* We overload some of the items in the data structure to meet our
98 * needs. For example, the port address is the CPM parameter ram
99 * offset for the SCC or SMC. The maximum number of ports is 4 SCCs and
100 * 2 SMCs. The "hub6" field is used to indicate the channel number, with
101 * a flag indicating SCC or SMC, and the number is used as an index into
102 * the CPM parameter area for this device.
103 * The "type" field is currently set to 0, for PORT_UNKNOWN. It is
104 * not currently used. I should probably use it to indicate the port
105 * type of SMC or SCC.
106 * The SMCs do not support any modem control signals.
107 */
108#define smc_scc_num hub6
109#define NUM_IS_SCC ((int)0x00010000)
110#define PORT_NUM(P) ((P) & 0x0000ffff)
111
112
113#if defined (CONFIG_UCQUICC)
114
115volatile extern void *_periph_base;
116/* sipex transceiver
117 * mode bits for are on pins
118 *
119 * SCC2 d16..19
120 * SCC3 d20..23
121 * SCC4 d24..27
122 */
123#define SIPEX_MODE(n,m) ((m & 0x0f)<<(16+4*(n-1)))
124
125static uint sipex_mode_bits = 0x00000000;
126
127#endif
128
129/* There is no `serial_state' defined back here in 2.0.
130 * Try to get by with serial_struct
131 */
132/* #define serial_state serial_struct */
133
134/* 2.4 -> 2.0 portability problem: async_icount in 2.4 has a few
135 * extras: */
136
137#if 0
138struct async_icount_24 {
139 __u32 cts, dsr, rng, dcd, tx, rx;
140 __u32 frame, parity, overrun, brk;
141 __u32 buf_overrun;
142} icount;
143#endif
144
145#if 0
146
147struct serial_state {
148 int magic;
149 int baud_base;
150 unsigned long port;
151 int irq;
152 int flags;
153 int hub6;
154 int type;
155 int line;
156 int revision; /* Chip revision (950) */
157 int xmit_fifo_size;
158 int custom_divisor;
159 int count;
160 u8 *iomem_base;
161 u16 iomem_reg_shift;
162 unsigned short close_delay;
163 unsigned short closing_wait; /* time to wait before closing */
164 struct async_icount_24 icount;
165 int io_type;
166 struct async_struct *info;
167};
168#endif
169
170#define SSTATE_MAGIC 0x5302
171
172
173
174/* SMC2 is sometimes used for low performance TDM interfaces. Define
175 * this as 1 if you want SMC2 as a serial port UART managed by this driver.
176 * Define this as 0 if you wish to use SMC2 for something else.
177 */
178#define USE_SMC2 1
179
180#if 0
181/* Define SCC to ttySx mapping. */
182#define SCC_NUM_BASE (USE_SMC2 + 1) /* SCC base tty "number" */
183
184/* Define which SCC is the first one to use for a serial port. These
185 * are 0-based numbers, i.e. this assumes the first SCC (SCC1) is used
186 * for Ethernet, and the first available SCC for serial UART is SCC2.
187 * NOTE: IF YOU CHANGE THIS, you have to change the PROFF_xxx and
188 * interrupt vectors in the table below to match.
189 */
190#define SCC_IDX_BASE 1 /* table index */
191#endif
192
193
194/* Processors other than the 860 only get SMCs configured by default.
195 * Either they don't have SCCs or they are allocated somewhere else.
196 * Of course, there are now 860s without some SCCs, so we will need to
197 * address that someday.
198 * The Embedded Planet Multimedia I/O cards use TDM interfaces to the
199 * stereo codec parts, and we use SMC2 to help support that.
200 */
201static struct serial_state rs_table[] = {
202/* type line PORT IRQ FLAGS smc_scc_num (F.K.A. hub6) */
203 { 0, 0, PRSLOT_SMC1, CPMVEC_SMC1, 0, 0 } /* SMC1 ttyS0 */
204#if USE_SMC2
205 ,{ 0, 0, PRSLOT_SMC2, CPMVEC_SMC2, 0, 1 } /* SMC2 ttyS1 */
206#endif
207
208#if defined(CONFIG_SERIAL_68360_SCC)
209 ,{ 0, 0, PRSLOT_SCC2, CPMVEC_SCC2, 0, (NUM_IS_SCC | 1) } /* SCC2 ttyS2 */
210 ,{ 0, 0, PRSLOT_SCC3, CPMVEC_SCC3, 0, (NUM_IS_SCC | 2) } /* SCC3 ttyS3 */
211 ,{ 0, 0, PRSLOT_SCC4, CPMVEC_SCC4, 0, (NUM_IS_SCC | 3) } /* SCC4 ttyS4 */
212#endif
213};
214
215#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state))
216
217/* The number of buffer descriptors and their sizes.
218 */
219#define RX_NUM_FIFO 4
220#define RX_BUF_SIZE 32
221#define TX_NUM_FIFO 4
222#define TX_BUF_SIZE 32
223
224#define CONSOLE_NUM_FIFO 2
225#define CONSOLE_BUF_SIZE 4
226
227char *console_fifos[CONSOLE_NUM_FIFO * CONSOLE_BUF_SIZE];
228
229/* The async_struct in serial.h does not really give us what we
230 * need, so define our own here.
231 */
232typedef struct serial_info {
233 int magic;
234 int flags;
235
236 struct serial_state *state;
237 /* struct serial_struct *state; */
238 /* struct async_struct *state; */
239
240 struct tty_struct *tty;
241 int read_status_mask;
242 int ignore_status_mask;
243 int timeout;
244 int line;
245 int x_char; /* xon/xoff character */
246 int close_delay;
247 unsigned short closing_wait;
248 unsigned short closing_wait2;
249 unsigned long event;
250 unsigned long last_active;
251 int blocked_open; /* # of blocked opens */
252 struct work_struct tqueue;
253 struct work_struct tqueue_hangup;
254 wait_queue_head_t open_wait;
255 wait_queue_head_t close_wait;
256
257
258/* CPM Buffer Descriptor pointers.
259 */
260 QUICC_BD *rx_bd_base;
261 QUICC_BD *rx_cur;
262 QUICC_BD *tx_bd_base;
263 QUICC_BD *tx_cur;
264} ser_info_t;
265
266
267/* since kmalloc_init() does not get called until much after this initialization: */
268static ser_info_t quicc_ser_info[NR_PORTS];
269static char rx_buf_pool[NR_PORTS * RX_NUM_FIFO * RX_BUF_SIZE];
270static char tx_buf_pool[NR_PORTS * TX_NUM_FIFO * TX_BUF_SIZE];
271
272static void change_speed(ser_info_t *info);
273static void rs_360_wait_until_sent(struct tty_struct *tty, int timeout);
274
275static inline int serial_paranoia_check(ser_info_t *info,
276 char *name, const char *routine)
277{
278#ifdef SERIAL_PARANOIA_CHECK
279 static const char *badmagic =
280 "Warning: bad magic number for serial struct (%s) in %s\n";
281 static const char *badinfo =
282 "Warning: null async_struct for (%s) in %s\n";
283
284 if (!info) {
285 printk(badinfo, name, routine);
286 return 1;
287 }
288 if (info->magic != SERIAL_MAGIC) {
289 printk(badmagic, name, routine);
290 return 1;
291 }
292#endif
293 return 0;
294}
295
296/*
297 * This is used to figure out the divisor speeds and the timeouts,
298 * indexed by the termio value. The generic CPM functions are responsible
299 * for setting and assigning baud rate generators for us.
300 */
301static int baud_table[] = {
302 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800,
303 9600, 19200, 38400, 57600, 115200, 230400, 460800, 0 };
304
305/* This sucks. There is a better way: */
306#if defined(CONFIG_CONSOLE_9600)
307 #define CONSOLE_BAUDRATE 9600
308#elif defined(CONFIG_CONSOLE_19200)
309 #define CONSOLE_BAUDRATE 19200
310#elif defined(CONFIG_CONSOLE_115200)
311 #define CONSOLE_BAUDRATE 115200
312#else
313 #warning "console baud rate undefined"
314 #define CONSOLE_BAUDRATE 9600
315#endif
316
317/*
318 * ------------------------------------------------------------
319 * rs_stop() and rs_start()
320 *
321 * This routines are called before setting or resetting tty->stopped.
322 * They enable or disable transmitter interrupts, as necessary.
323 * ------------------------------------------------------------
324 */
325static void rs_360_stop(struct tty_struct *tty)
326{
327 ser_info_t *info = (ser_info_t *)tty->driver_data;
328 int idx;
329 unsigned long flags;
330 volatile struct scc_regs *sccp;
331 volatile struct smc_regs *smcp;
332
333 if (serial_paranoia_check(info, tty->name, "rs_stop"))
334 return;
335
336 local_irq_save(flags);
337 idx = PORT_NUM(info->state->smc_scc_num);
338 if (info->state->smc_scc_num & NUM_IS_SCC) {
339 sccp = &pquicc->scc_regs[idx];
340 sccp->scc_sccm &= ~UART_SCCM_TX;
341 } else {
342 /* smcp = &cpmp->cp_smc[idx]; */
343 smcp = &pquicc->smc_regs[idx];
344 smcp->smc_smcm &= ~SMCM_TX;
345 }
346 local_irq_restore(flags);
347}
348
349
350static void rs_360_start(struct tty_struct *tty)
351{
352 ser_info_t *info = (ser_info_t *)tty->driver_data;
353 int idx;
354 unsigned long flags;
355 volatile struct scc_regs *sccp;
356 volatile struct smc_regs *smcp;
357
358 if (serial_paranoia_check(info, tty->name, "rs_stop"))
359 return;
360
361 local_irq_save(flags);
362 idx = PORT_NUM(info->state->smc_scc_num);
363 if (info->state->smc_scc_num & NUM_IS_SCC) {
364 sccp = &pquicc->scc_regs[idx];
365 sccp->scc_sccm |= UART_SCCM_TX;
366 } else {
367 smcp = &pquicc->smc_regs[idx];
368 smcp->smc_smcm |= SMCM_TX;
369 }
370 local_irq_restore(flags);
371}
372
373/*
374 * ----------------------------------------------------------------------
375 *
376 * Here starts the interrupt handling routines. All of the following
377 * subroutines are declared as inline and are folded into
378 * rs_interrupt(). They were separated out for readability's sake.
379 *
380 * Note: rs_interrupt() is a "fast" interrupt, which means that it
381 * runs with interrupts turned off. People who may want to modify
382 * rs_interrupt() should try to keep the interrupt handler as fast as
383 * possible. After you are done making modifications, it is not a bad
384 * idea to do:
385 *
386 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
387 *
388 * and look at the resulting assemble code in serial.s.
389 *
390 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
391 * -----------------------------------------------------------------------
392 */
393
394static _INLINE_ void receive_chars(ser_info_t *info)
395{
396 struct tty_struct *tty = info->port.tty;
397 unsigned char ch, flag, *cp;
398 /*int ignored = 0;*/
399 int i;
400 ushort status;
401 struct async_icount *icount;
402 /* struct async_icount_24 *icount; */
403 volatile QUICC_BD *bdp;
404
405 icount = &info->state->icount;
406
407 /* Just loop through the closed BDs and copy the characters into
408 * the buffer.
409 */
410 bdp = info->rx_cur;
411 for (;;) {
412 if (bdp->status & BD_SC_EMPTY) /* If this one is empty */
413 break; /* we are all done */
414
415 /* The read status mask tell us what we should do with
416 * incoming characters, especially if errors occur.
417 * One special case is the use of BD_SC_EMPTY. If
418 * this is not set, we are supposed to be ignoring
419 * inputs. In this case, just mark the buffer empty and
420 * continue.
421 */
422 if (!(info->read_status_mask & BD_SC_EMPTY)) {
423 bdp->status |= BD_SC_EMPTY;
424 bdp->status &=
425 ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV);
426
427 if (bdp->status & BD_SC_WRAP)
428 bdp = info->rx_bd_base;
429 else
430 bdp++;
431 continue;
432 }
433
434 /* Get the number of characters and the buffer pointer.
435 */
436 i = bdp->length;
437 /* cp = (unsigned char *)__va(bdp->buf); */
438 cp = (char *)bdp->buf;
439 status = bdp->status;
440
441 while (i-- > 0) {
442 ch = *cp++;
443 icount->rx++;
444
445#ifdef SERIAL_DEBUG_INTR
446 printk("DR%02x:%02x...", ch, status);
447#endif
448 flag = TTY_NORMAL;
449
450 if (status & (BD_SC_BR | BD_SC_FR |
451 BD_SC_PR | BD_SC_OV)) {
452 /*
453 * For statistics only
454 */
455 if (status & BD_SC_BR)
456 icount->brk++;
457 else if (status & BD_SC_PR)
458 icount->parity++;
459 else if (status & BD_SC_FR)
460 icount->frame++;
461 if (status & BD_SC_OV)
462 icount->overrun++;
463
464 /*
465 * Now check to see if character should be
466 * ignored, and mask off conditions which
467 * should be ignored.
468 if (status & info->ignore_status_mask) {
469 if (++ignored > 100)
470 break;
471 continue;
472 }
473 */
474 status &= info->read_status_mask;
475
476 if (status & (BD_SC_BR)) {
477#ifdef SERIAL_DEBUG_INTR
478 printk("handling break....");
479#endif
480 *tty->flip.flag_buf_ptr = TTY_BREAK;
481 if (info->flags & ASYNC_SAK)
482 do_SAK(tty);
483 } else if (status & BD_SC_PR)
484 flag = TTY_PARITY;
485 else if (status & BD_SC_FR)
486 flag = TTY_FRAME;
487 }
488 tty_insert_flip_char(tty, ch, flag);
489 if (status & BD_SC_OV)
490 /*
491 * Overrun is special, since it's
492 * reported immediately, and doesn't
493 * affect the current character
494 */
495 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
496 }
497
498 /* This BD is ready to be used again. Clear status.
499 * Get next BD.
500 */
501 bdp->status |= BD_SC_EMPTY;
502 bdp->status &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV);
503
504 if (bdp->status & BD_SC_WRAP)
505 bdp = info->rx_bd_base;
506 else
507 bdp++;
508 }
509
510 info->rx_cur = (QUICC_BD *)bdp;
511
512 tty_schedule_flip(tty);
513}
514
515static _INLINE_ void receive_break(ser_info_t *info)
516{
517 struct tty_struct *tty = info->port.tty;
518
519 info->state->icount.brk++;
520 /* Check to see if there is room in the tty buffer for
521 * the break. If not, we exit now, losing the break. FIXME
522 */
523 tty_insert_flip_char(tty, 0, TTY_BREAK);
524 tty_schedule_flip(tty);
525}
526
527static _INLINE_ void transmit_chars(ser_info_t *info)
528{
529
530 if ((info->flags & TX_WAKEUP) ||
531 (info->port.tty->flags & (1 << TTY_DO_WRITE_WAKEUP))) {
532 schedule_work(&info->tqueue);
533 }
534
535#ifdef SERIAL_DEBUG_INTR
536 printk("THRE...");
537#endif
538}
539
540#ifdef notdef
541 /* I need to do this for the SCCs, so it is left as a reminder.
542 */
543static _INLINE_ void check_modem_status(struct async_struct *info)
544{
545 int status;
546 /* struct async_icount *icount; */
547 struct async_icount_24 *icount;
548
549 status = serial_in(info, UART_MSR);
550
551 if (status & UART_MSR_ANY_DELTA) {
552 icount = &info->state->icount;
553 /* update input line counters */
554 if (status & UART_MSR_TERI)
555 icount->rng++;
556 if (status & UART_MSR_DDSR)
557 icount->dsr++;
558 if (status & UART_MSR_DDCD) {
559 icount->dcd++;
560#ifdef CONFIG_HARD_PPS
561 if ((info->flags & ASYNC_HARDPPS_CD) &&
562 (status & UART_MSR_DCD))
563 hardpps();
564#endif
565 }
566 if (status & UART_MSR_DCTS)
567 icount->cts++;
568 wake_up_interruptible(&info->delta_msr_wait);
569 }
570
571 if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
572#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR))
573 printk("ttys%d CD now %s...", info->line,
574 (status & UART_MSR_DCD) ? "on" : "off");
575#endif
576 if (status & UART_MSR_DCD)
577 wake_up_interruptible(&info->open_wait);
578 else {
579#ifdef SERIAL_DEBUG_OPEN
580 printk("scheduling hangup...");
581#endif
582 queue_task(&info->tqueue_hangup,
583 &tq_scheduler);
584 }
585 }
586 if (info->flags & ASYNC_CTS_FLOW) {
587 if (info->port.tty->hw_stopped) {
588 if (status & UART_MSR_CTS) {
589#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
590 printk("CTS tx start...");
591#endif
592 info->port.tty->hw_stopped = 0;
593 info->IER |= UART_IER_THRI;
594 serial_out(info, UART_IER, info->IER);
595 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
596 return;
597 }
598 } else {
599 if (!(status & UART_MSR_CTS)) {
600#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
601 printk("CTS tx stop...");
602#endif
603 info->port.tty->hw_stopped = 1;
604 info->IER &= ~UART_IER_THRI;
605 serial_out(info, UART_IER, info->IER);
606 }
607 }
608 }
609}
610#endif
611
612/*
613 * This is the serial driver's interrupt routine for a single port
614 */
615/* static void rs_360_interrupt(void *dev_id) */ /* until and if we start servicing irqs here */
616static void rs_360_interrupt(int vec, void *dev_id)
617{
618 u_char events;
619 int idx;
620 ser_info_t *info;
621 volatile struct smc_regs *smcp;
622 volatile struct scc_regs *sccp;
623
624 info = dev_id;
625
626 idx = PORT_NUM(info->state->smc_scc_num);
627 if (info->state->smc_scc_num & NUM_IS_SCC) {
628 sccp = &pquicc->scc_regs[idx];
629 events = sccp->scc_scce;
630 if (events & SCCM_RX)
631 receive_chars(info);
632 if (events & SCCM_TX)
633 transmit_chars(info);
634 sccp->scc_scce = events;
635 } else {
636 smcp = &pquicc->smc_regs[idx];
637 events = smcp->smc_smce;
638 if (events & SMCM_BRKE)
639 receive_break(info);
640 if (events & SMCM_RX)
641 receive_chars(info);
642 if (events & SMCM_TX)
643 transmit_chars(info);
644 smcp->smc_smce = events;
645 }
646
647#ifdef SERIAL_DEBUG_INTR
648 printk("rs_interrupt_single(%d, %x)...",
649 info->state->smc_scc_num, events);
650#endif
651#ifdef modem_control
652 check_modem_status(info);
653#endif
654 info->last_active = jiffies;
655#ifdef SERIAL_DEBUG_INTR
656 printk("end.\n");
657#endif
658}
659
660
661/*
662 * -------------------------------------------------------------------
663 * Here ends the serial interrupt routines.
664 * -------------------------------------------------------------------
665 */
666
667
668static void do_softint(void *private_)
669{
670 ser_info_t *info = (ser_info_t *) private_;
671 struct tty_struct *tty;
672
673 tty = info->port.tty;
674 if (!tty)
675 return;
676
677 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
678 tty_wakeup(tty);
679}
680
681
682/*
683 * This routine is called from the scheduler tqueue when the interrupt
684 * routine has signalled that a hangup has occurred. The path of
685 * hangup processing is:
686 *
687 * serial interrupt routine -> (scheduler tqueue) ->
688 * do_serial_hangup() -> tty->hangup() -> rs_hangup()
689 *
690 */
691static void do_serial_hangup(void *private_)
692{
693 struct async_struct *info = (struct async_struct *) private_;
694 struct tty_struct *tty;
695
696 tty = info->port.tty;
697 if (!tty)
698 return;
699
700 tty_hangup(tty);
701}
702
703
704static int startup(ser_info_t *info)
705{
706 unsigned long flags;
707 int retval=0;
708 int idx;
709 /*struct serial_state *state = info->state;*/
710 volatile struct smc_regs *smcp;
711 volatile struct scc_regs *sccp;
712 volatile struct smc_uart_pram *up;
713 volatile struct uart_pram *scup;
714
715
716 local_irq_save(flags);
717
718 if (info->flags & ASYNC_INITIALIZED) {
719 goto errout;
720 }
721
722#ifdef maybe
723 if (!state->port || !state->type) {
724 if (info->port.tty)
725 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
726 goto errout;
727 }
728#endif
729
730#ifdef SERIAL_DEBUG_OPEN
731 printk("starting up ttys%d (irq %d)...", info->line, state->irq);
732#endif
733
734
735#ifdef modem_control
736 info->MCR = 0;
737 if (info->port.tty->termios->c_cflag & CBAUD)
738 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
739#endif
740
741 if (info->port.tty)
742 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
743
744 /*
745 * and set the speed of the serial port
746 */
747 change_speed(info);
748
749 idx = PORT_NUM(info->state->smc_scc_num);
750 if (info->state->smc_scc_num & NUM_IS_SCC) {
751 sccp = &pquicc->scc_regs[idx];
752 scup = &pquicc->pram[info->state->port].scc.pscc.u;
753
754 scup->mrblr = RX_BUF_SIZE;
755 scup->max_idl = RX_BUF_SIZE;
756
757 sccp->scc_sccm |= (UART_SCCM_TX | UART_SCCM_RX);
758 sccp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
759
760 } else {
761 smcp = &pquicc->smc_regs[idx];
762
763 /* Enable interrupts and I/O.
764 */
765 smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
766 smcp->smc_smcmr |= (SMCMR_REN | SMCMR_TEN);
767
768 /* We can tune the buffer length and idle characters
769 * to take advantage of the entire incoming buffer size.
770 * If mrblr is something other than 1, maxidl has to be
771 * non-zero or we never get an interrupt. The maxidl
772 * is the number of character times we wait after reception
773 * of the last character before we decide no more characters
774 * are coming.
775 */
776 /* up = (smc_uart_t *)&pquicc->cp_dparam[state->port]; */
777 /* holy unionized structures, Batman: */
778 up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
779
780 up->mrblr = RX_BUF_SIZE;
781 up->max_idl = RX_BUF_SIZE;
782
783 up->brkcr = 1; /* number of break chars */
784 }
785
786 info->flags |= ASYNC_INITIALIZED;
787 local_irq_restore(flags);
788 return 0;
789
790errout:
791 local_irq_restore(flags);
792 return retval;
793}
794
795/*
796 * This routine will shutdown a serial port; interrupts are disabled, and
797 * DTR is dropped if the hangup on close termio flag is on.
798 */
799static void shutdown(ser_info_t *info)
800{
801 unsigned long flags;
802 struct serial_state *state;
803 int idx;
804 volatile struct smc_regs *smcp;
805 volatile struct scc_regs *sccp;
806
807 if (!(info->flags & ASYNC_INITIALIZED))
808 return;
809
810 state = info->state;
811
812#ifdef SERIAL_DEBUG_OPEN
813 printk("Shutting down serial port %d (irq %d)....", info->line,
814 state->irq);
815#endif
816
817 local_irq_save(flags);
818
819 idx = PORT_NUM(state->smc_scc_num);
820 if (state->smc_scc_num & NUM_IS_SCC) {
821 sccp = &pquicc->scc_regs[idx];
822 sccp->scc_gsmr.w.low &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
823#ifdef CONFIG_SERIAL_CONSOLE
824 /* We can't disable the transmitter if this is the
825 * system console.
826 */
827 if ((state - rs_table) != CONFIG_SERIAL_CONSOLE_PORT)
828#endif
829 sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
830 } else {
831 smcp = &pquicc->smc_regs[idx];
832
833 /* Disable interrupts and I/O.
834 */
835 smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX);
836#ifdef CONFIG_SERIAL_CONSOLE
837 /* We can't disable the transmitter if this is the
838 * system console.
839 */
840 if ((state - rs_table) != CONFIG_SERIAL_CONSOLE_PORT)
841#endif
842 smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
843 }
844
845 if (info->port.tty)
846 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
847
848 info->flags &= ~ASYNC_INITIALIZED;
849 local_irq_restore(flags);
850}
851
852/*
853 * This routine is called to set the UART divisor registers to match
854 * the specified baud rate for a serial port.
855 */
856static void change_speed(ser_info_t *info)
857{
858 int baud_rate;
859 unsigned cflag, cval, scval, prev_mode;
860 int i, bits, sbits, idx;
861 unsigned long flags;
862 struct serial_state *state;
863 volatile struct smc_regs *smcp;
864 volatile struct scc_regs *sccp;
865
866 if (!info->port.tty || !info->port.tty->termios)
867 return;
868 cflag = info->port.tty->termios->c_cflag;
869
870 state = info->state;
871
872 /* Character length programmed into the mode register is the
873 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
874 * 1 or 2 stop bits, minus 1.
875 * The value 'bits' counts this for us.
876 */
877 cval = 0;
878 scval = 0;
879
880 /* byte size and parity */
881 switch (cflag & CSIZE) {
882 case CS5: bits = 5; break;
883 case CS6: bits = 6; break;
884 case CS7: bits = 7; break;
885 case CS8: bits = 8; break;
886 /* Never happens, but GCC is too dumb to figure it out */
887 default: bits = 8; break;
888 }
889 sbits = bits - 5;
890
891 if (cflag & CSTOPB) {
892 cval |= SMCMR_SL; /* Two stops */
893 scval |= SCU_PMSR_SL;
894 bits++;
895 }
896 if (cflag & PARENB) {
897 cval |= SMCMR_PEN;
898 scval |= SCU_PMSR_PEN;
899 bits++;
900 }
901 if (!(cflag & PARODD)) {
902 cval |= SMCMR_PM_EVEN;
903 scval |= (SCU_PMSR_REVP | SCU_PMSR_TEVP);
904 }
905
906 /* Determine divisor based on baud rate */
907 i = cflag & CBAUD;
908 if (i >= (sizeof(baud_table)/sizeof(int)))
909 baud_rate = 9600;
910 else
911 baud_rate = baud_table[i];
912
913 info->timeout = (TX_BUF_SIZE*HZ*bits);
914 info->timeout += HZ/50; /* Add .02 seconds of slop */
915
916#ifdef modem_control
917 /* CTS flow control flag and modem status interrupts */
918 info->IER &= ~UART_IER_MSI;
919 if (info->flags & ASYNC_HARDPPS_CD)
920 info->IER |= UART_IER_MSI;
921 if (cflag & CRTSCTS) {
922 info->flags |= ASYNC_CTS_FLOW;
923 info->IER |= UART_IER_MSI;
924 } else
925 info->flags &= ~ASYNC_CTS_FLOW;
926 if (cflag & CLOCAL)
927 info->flags &= ~ASYNC_CHECK_CD;
928 else {
929 info->flags |= ASYNC_CHECK_CD;
930 info->IER |= UART_IER_MSI;
931 }
932 serial_out(info, UART_IER, info->IER);
933#endif
934
935 /*
936 * Set up parity check flag
937 */
938 info->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
939 if (I_INPCK(info->port.tty))
940 info->read_status_mask |= BD_SC_FR | BD_SC_PR;
941 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
942 info->read_status_mask |= BD_SC_BR;
943
944 /*
945 * Characters to ignore
946 */
947 info->ignore_status_mask = 0;
948 if (I_IGNPAR(info->port.tty))
949 info->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
950 if (I_IGNBRK(info->port.tty)) {
951 info->ignore_status_mask |= BD_SC_BR;
952 /*
953 * If we're ignore parity and break indicators, ignore
954 * overruns too. (For real raw support).
955 */
956 if (I_IGNPAR(info->port.tty))
957 info->ignore_status_mask |= BD_SC_OV;
958 }
959 /*
960 * !!! ignore all characters if CREAD is not set
961 */
962 if ((cflag & CREAD) == 0)
963 info->read_status_mask &= ~BD_SC_EMPTY;
964 local_irq_save(flags);
965
966 /* Start bit has not been added (so don't, because we would just
967 * subtract it later), and we need to add one for the number of
968 * stops bits (there is always at least one).
969 */
970 bits++;
971 idx = PORT_NUM(state->smc_scc_num);
972 if (state->smc_scc_num & NUM_IS_SCC) {
973 sccp = &pquicc->scc_regs[idx];
974 sccp->scc_psmr = (sbits << 12) | scval;
975 } else {
976 smcp = &pquicc->smc_regs[idx];
977
978 /* Set the mode register. We want to keep a copy of the
979 * enables, because we want to put them back if they were
980 * present.
981 */
982 prev_mode = smcp->smc_smcmr;
983 smcp->smc_smcmr = smcr_mk_clen(bits) | cval | SMCMR_SM_UART;
984 smcp->smc_smcmr |= (prev_mode & (SMCMR_REN | SMCMR_TEN));
985 }
986
987 m360_cpm_setbrg((state - rs_table), baud_rate);
988
989 local_irq_restore(flags);
990}
991
992static void rs_360_put_char(struct tty_struct *tty, unsigned char ch)
993{
994 ser_info_t *info = (ser_info_t *)tty->driver_data;
995 volatile QUICC_BD *bdp;
996
997 if (serial_paranoia_check(info, tty->name, "rs_put_char"))
998 return 0;
999
1000 if (!tty)
1001 return 0;
1002
1003 bdp = info->tx_cur;
1004 while (bdp->status & BD_SC_READY);
1005
1006 /* *((char *)__va(bdp->buf)) = ch; */
1007 *((char *)bdp->buf) = ch;
1008 bdp->length = 1;
1009 bdp->status |= BD_SC_READY;
1010
1011 /* Get next BD.
1012 */
1013 if (bdp->status & BD_SC_WRAP)
1014 bdp = info->tx_bd_base;
1015 else
1016 bdp++;
1017
1018 info->tx_cur = (QUICC_BD *)bdp;
1019 return 1;
1020
1021}
1022
1023static int rs_360_write(struct tty_struct * tty,
1024 const unsigned char *buf, int count)
1025{
1026 int c, ret = 0;
1027 ser_info_t *info = (ser_info_t *)tty->driver_data;
1028 volatile QUICC_BD *bdp;
1029
1030#ifdef CONFIG_KGDB
1031 /* Try to let stub handle output. Returns true if it did. */
1032 if (kgdb_output_string(buf, count))
1033 return ret;
1034#endif
1035
1036 if (serial_paranoia_check(info, tty->name, "rs_write"))
1037 return 0;
1038
1039 if (!tty)
1040 return 0;
1041
1042 bdp = info->tx_cur;
1043
1044 while (1) {
1045 c = min(count, TX_BUF_SIZE);
1046
1047 if (c <= 0)
1048 break;
1049
1050 if (bdp->status & BD_SC_READY) {
1051 info->flags |= TX_WAKEUP;
1052 break;
1053 }
1054
1055 /* memcpy(__va(bdp->buf), buf, c); */
1056 memcpy((void *)bdp->buf, buf, c);
1057
1058 bdp->length = c;
1059 bdp->status |= BD_SC_READY;
1060
1061 buf += c;
1062 count -= c;
1063 ret += c;
1064
1065 /* Get next BD.
1066 */
1067 if (bdp->status & BD_SC_WRAP)
1068 bdp = info->tx_bd_base;
1069 else
1070 bdp++;
1071 info->tx_cur = (QUICC_BD *)bdp;
1072 }
1073 return ret;
1074}
1075
1076static int rs_360_write_room(struct tty_struct *tty)
1077{
1078 ser_info_t *info = (ser_info_t *)tty->driver_data;
1079 int ret;
1080
1081 if (serial_paranoia_check(info, tty->name, "rs_write_room"))
1082 return 0;
1083
1084 if ((info->tx_cur->status & BD_SC_READY) == 0) {
1085 info->flags &= ~TX_WAKEUP;
1086 ret = TX_BUF_SIZE;
1087 }
1088 else {
1089 info->flags |= TX_WAKEUP;
1090 ret = 0;
1091 }
1092 return ret;
1093}
1094
1095/* I could track this with transmit counters....maybe later.
1096*/
1097static int rs_360_chars_in_buffer(struct tty_struct *tty)
1098{
1099 ser_info_t *info = (ser_info_t *)tty->driver_data;
1100
1101 if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer"))
1102 return 0;
1103 return 0;
1104}
1105
1106static void rs_360_flush_buffer(struct tty_struct *tty)
1107{
1108 ser_info_t *info = (ser_info_t *)tty->driver_data;
1109
1110 if (serial_paranoia_check(info, tty->name, "rs_flush_buffer"))
1111 return;
1112
1113 /* There is nothing to "flush", whatever we gave the CPM
1114 * is on its way out.
1115 */
1116 tty_wakeup(tty);
1117 info->flags &= ~TX_WAKEUP;
1118}
1119
1120/*
1121 * This function is used to send a high-priority XON/XOFF character to
1122 * the device
1123 */
1124static void rs_360_send_xchar(struct tty_struct *tty, char ch)
1125{
1126 volatile QUICC_BD *bdp;
1127
1128 ser_info_t *info = (ser_info_t *)tty->driver_data;
1129
1130 if (serial_paranoia_check(info, tty->name, "rs_send_char"))
1131 return;
1132
1133 bdp = info->tx_cur;
1134 while (bdp->status & BD_SC_READY);
1135
1136 /* *((char *)__va(bdp->buf)) = ch; */
1137 *((char *)bdp->buf) = ch;
1138 bdp->length = 1;
1139 bdp->status |= BD_SC_READY;
1140
1141 /* Get next BD.
1142 */
1143 if (bdp->status & BD_SC_WRAP)
1144 bdp = info->tx_bd_base;
1145 else
1146 bdp++;
1147
1148 info->tx_cur = (QUICC_BD *)bdp;
1149}
1150
1151/*
1152 * ------------------------------------------------------------
1153 * rs_throttle()
1154 *
1155 * This routine is called by the upper-layer tty layer to signal that
1156 * incoming characters should be throttled.
1157 * ------------------------------------------------------------
1158 */
1159static void rs_360_throttle(struct tty_struct * tty)
1160{
1161 ser_info_t *info = (ser_info_t *)tty->driver_data;
1162#ifdef SERIAL_DEBUG_THROTTLE
1163 char buf[64];
1164
1165 printk("throttle %s: %d....\n", _tty_name(tty, buf),
1166 tty->ldisc.chars_in_buffer(tty));
1167#endif
1168
1169 if (serial_paranoia_check(info, tty->name, "rs_throttle"))
1170 return;
1171
1172 if (I_IXOFF(tty))
1173 rs_360_send_xchar(tty, STOP_CHAR(tty));
1174
1175#ifdef modem_control
1176 if (tty->termios->c_cflag & CRTSCTS)
1177 info->MCR &= ~UART_MCR_RTS;
1178
1179 local_irq_disable();
1180 serial_out(info, UART_MCR, info->MCR);
1181 local_irq_enable();
1182#endif
1183}
1184
1185static void rs_360_unthrottle(struct tty_struct * tty)
1186{
1187 ser_info_t *info = (ser_info_t *)tty->driver_data;
1188#ifdef SERIAL_DEBUG_THROTTLE
1189 char buf[64];
1190
1191 printk("unthrottle %s: %d....\n", _tty_name(tty, buf),
1192 tty->ldisc.chars_in_buffer(tty));
1193#endif
1194
1195 if (serial_paranoia_check(info, tty->name, "rs_unthrottle"))
1196 return;
1197
1198 if (I_IXOFF(tty)) {
1199 if (info->x_char)
1200 info->x_char = 0;
1201 else
1202 rs_360_send_xchar(tty, START_CHAR(tty));
1203 }
1204#ifdef modem_control
1205 if (tty->termios->c_cflag & CRTSCTS)
1206 info->MCR |= UART_MCR_RTS;
1207 local_irq_disable();
1208 serial_out(info, UART_MCR, info->MCR);
1209 local_irq_enable();
1210#endif
1211}
1212
1213/*
1214 * ------------------------------------------------------------
1215 * rs_ioctl() and friends
1216 * ------------------------------------------------------------
1217 */
1218
1219#ifdef maybe
1220/*
1221 * get_lsr_info - get line status register info
1222 *
1223 * Purpose: Let user call ioctl() to get info when the UART physically
1224 * is emptied. On bus types like RS485, the transmitter must
1225 * release the bus after transmitting. This must be done when
1226 * the transmit shift register is empty, not be done when the
1227 * transmit holding register is empty. This functionality
1228 * allows an RS485 driver to be written in user space.
1229 */
1230static int get_lsr_info(struct async_struct * info, unsigned int *value)
1231{
1232 unsigned char status;
1233 unsigned int result;
1234
1235 local_irq_disable();
1236 status = serial_in(info, UART_LSR);
1237 local_irq_enable();
1238 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1239 return put_user(result,value);
1240}
1241#endif
1242
1243static int rs_360_tiocmget(struct tty_struct *tty)
1244{
1245 ser_info_t *info = (ser_info_t *)tty->driver_data;
1246 unsigned int result = 0;
1247#ifdef modem_control
1248 unsigned char control, status;
1249
1250 if (serial_paranoia_check(info, tty->name, __func__))
1251 return -ENODEV;
1252
1253 if (tty->flags & (1 << TTY_IO_ERROR))
1254 return -EIO;
1255
1256 control = info->MCR;
1257 local_irq_disable();
1258 status = serial_in(info, UART_MSR);
1259 local_irq_enable();
1260 result = ((control & UART_MCR_RTS) ? TIOCM_RTS : 0)
1261 | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0)
1262#ifdef TIOCM_OUT1
1263 | ((control & UART_MCR_OUT1) ? TIOCM_OUT1 : 0)
1264 | ((control & UART_MCR_OUT2) ? TIOCM_OUT2 : 0)
1265#endif
1266 | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0)
1267 | ((status & UART_MSR_RI) ? TIOCM_RNG : 0)
1268 | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0)
1269 | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1270#endif
1271 return result;
1272}
1273
1274static int rs_360_tiocmset(struct tty_struct *tty,
1275 unsigned int set, unsigned int clear)
1276{
1277#ifdef modem_control
1278 ser_info_t *info = (ser_info_t *)tty->driver_data;
1279 unsigned int arg;
1280
1281 if (serial_paranoia_check(info, tty->name, __func__))
1282 return -ENODEV;
1283
1284 if (tty->flags & (1 << TTY_IO_ERROR))
1285 return -EIO;
1286 /* FIXME: locking on info->mcr */
1287 if (set & TIOCM_RTS)
1288 info->mcr |= UART_MCR_RTS;
1289 if (set & TIOCM_DTR)
1290 info->mcr |= UART_MCR_DTR;
1291 if (clear & TIOCM_RTS)
1292 info->MCR &= ~UART_MCR_RTS;
1293 if (clear & TIOCM_DTR)
1294 info->MCR &= ~UART_MCR_DTR;
1295
1296#ifdef TIOCM_OUT1
1297 if (set & TIOCM_OUT1)
1298 info->MCR |= UART_MCR_OUT1;
1299 if (set & TIOCM_OUT2)
1300 info->MCR |= UART_MCR_OUT2;
1301 if (clear & TIOCM_OUT1)
1302 info->MCR &= ~UART_MCR_OUT1;
1303 if (clear & TIOCM_OUT2)
1304 info->MCR &= ~UART_MCR_OUT2;
1305#endif
1306
1307 local_irq_disable();
1308 serial_out(info, UART_MCR, info->MCR);
1309 local_irq_enable();
1310#endif
1311 return 0;
1312}
1313
1314/* Sending a break is a two step process on the SMC/SCC. It is accomplished
1315 * by sending a STOP TRANSMIT command followed by a RESTART TRANSMIT
1316 * command. We take advantage of the begin/end functions to make this
1317 * happen.
1318 */
1319static ushort smc_chan_map[] = {
1320 CPM_CR_CH_SMC1,
1321 CPM_CR_CH_SMC2
1322};
1323
1324static ushort scc_chan_map[] = {
1325 CPM_CR_CH_SCC1,
1326 CPM_CR_CH_SCC2,
1327 CPM_CR_CH_SCC3,
1328 CPM_CR_CH_SCC4
1329};
1330
1331static void begin_break(ser_info_t *info)
1332{
1333 volatile QUICC *cp;
1334 ushort chan;
1335 int idx;
1336
1337 cp = pquicc;
1338
1339 idx = PORT_NUM(info->state->smc_scc_num);
1340 if (info->state->smc_scc_num & NUM_IS_SCC)
1341 chan = scc_chan_map[idx];
1342 else
1343 chan = smc_chan_map[idx];
1344
1345 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_STOP_TX) | CPM_CR_FLG;
1346 while (cp->cp_cr & CPM_CR_FLG);
1347}
1348
1349static void end_break(ser_info_t *info)
1350{
1351 volatile QUICC *cp;
1352 ushort chan;
1353 int idx;
1354
1355 cp = pquicc;
1356
1357 idx = PORT_NUM(info->state->smc_scc_num);
1358 if (info->state->smc_scc_num & NUM_IS_SCC)
1359 chan = scc_chan_map[idx];
1360 else
1361 chan = smc_chan_map[idx];
1362
1363 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_RESTART_TX) | CPM_CR_FLG;
1364 while (cp->cp_cr & CPM_CR_FLG);
1365}
1366
1367/*
1368 * This routine sends a break character out the serial port.
1369 */
1370static void send_break(ser_info_t *info, unsigned int duration)
1371{
1372#ifdef SERIAL_DEBUG_SEND_BREAK
1373 printk("rs_send_break(%d) jiff=%lu...", duration, jiffies);
1374#endif
1375 begin_break(info);
1376 msleep_interruptible(duration);
1377 end_break(info);
1378#ifdef SERIAL_DEBUG_SEND_BREAK
1379 printk("done jiffies=%lu\n", jiffies);
1380#endif
1381}
1382
1383
1384/*
1385 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1386 * Return: write counters to the user passed counter struct
1387 * NB: both 1->0 and 0->1 transitions are counted except for
1388 * RI where only 0->1 is counted.
1389 */
1390static int rs_360_get_icount(struct tty_struct *tty,
1391 struct serial_icounter_struct *icount)
1392{
1393 ser_info_t *info = (ser_info_t *)tty->driver_data;
1394 struct async_icount cnow;
1395
1396 local_irq_disable();
1397 cnow = info->state->icount;
1398 local_irq_enable();
1399
1400 icount->cts = cnow.cts;
1401 icount->dsr = cnow.dsr;
1402 icount->rng = cnow.rng;
1403 icount->dcd = cnow.dcd;
1404
1405 return 0;
1406}
1407
1408static int rs_360_ioctl(struct tty_struct *tty,
1409 unsigned int cmd, unsigned long arg)
1410{
1411 int error;
1412 ser_info_t *info = (ser_info_t *)tty->driver_data;
1413 int retval;
1414 struct async_icount cnow;
1415 /* struct async_icount_24 cnow;*/ /* kernel counter temps */
1416 struct serial_icounter_struct *p_cuser; /* user space */
1417
1418 if (serial_paranoia_check(info, tty->name, "rs_ioctl"))
1419 return -ENODEV;
1420
1421 if (cmd != TIOCMIWAIT) {
1422 if (tty->flags & (1 << TTY_IO_ERROR))
1423 return -EIO;
1424 }
1425
1426 switch (cmd) {
1427 case TCSBRK: /* SVID version: non-zero arg --> no break */
1428 retval = tty_check_change(tty);
1429 if (retval)
1430 return retval;
1431 tty_wait_until_sent(tty, 0);
1432 if (signal_pending(current))
1433 return -EINTR;
1434 if (!arg) {
1435 send_break(info, 250); /* 1/4 second */
1436 if (signal_pending(current))
1437 return -EINTR;
1438 }
1439 return 0;
1440 case TCSBRKP: /* support for POSIX tcsendbreak() */
1441 retval = tty_check_change(tty);
1442 if (retval)
1443 return retval;
1444 tty_wait_until_sent(tty, 0);
1445 if (signal_pending(current))
1446 return -EINTR;
1447 send_break(info, arg ? arg*100 : 250);
1448 if (signal_pending(current))
1449 return -EINTR;
1450 return 0;
1451 case TIOCSBRK:
1452 retval = tty_check_change(tty);
1453 if (retval)
1454 return retval;
1455 tty_wait_until_sent(tty, 0);
1456 begin_break(info);
1457 return 0;
1458 case TIOCCBRK:
1459 retval = tty_check_change(tty);
1460 if (retval)
1461 return retval;
1462 end_break(info);
1463 return 0;
1464#ifdef maybe
1465 case TIOCSERGETLSR: /* Get line status register */
1466 return get_lsr_info(info, (unsigned int *) arg);
1467#endif
1468 /*
1469 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1470 * - mask passed in arg for lines of interest
1471 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1472 * Caller should use TIOCGICOUNT to see which one it was
1473 */
1474 case TIOCMIWAIT:
1475#ifdef modem_control
1476 local_irq_disable();
1477 /* note the counters on entry */
1478 cprev = info->state->icount;
1479 local_irq_enable();
1480 while (1) {
1481 interruptible_sleep_on(&info->delta_msr_wait);
1482 /* see if a signal did it */
1483 if (signal_pending(current))
1484 return -ERESTARTSYS;
1485 local_irq_disable();
1486 cnow = info->state->icount; /* atomic copy */
1487 local_irq_enable();
1488 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
1489 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
1490 return -EIO; /* no change => error */
1491 if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
1492 ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
1493 ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
1494 ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) {
1495 return 0;
1496 }
1497 cprev = cnow;
1498 }
1499 /* NOTREACHED */
1500#else
1501 return 0;
1502#endif
1503
1504
1505 default:
1506 return -ENOIOCTLCMD;
1507 }
1508 return 0;
1509}
1510
1511/* FIX UP modem control here someday......
1512*/
1513static void rs_360_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1514{
1515 ser_info_t *info = (ser_info_t *)tty->driver_data;
1516
1517 change_speed(info);
1518
1519#ifdef modem_control
1520 /* Handle transition to B0 status */
1521 if ((old_termios->c_cflag & CBAUD) &&
1522 !(tty->termios->c_cflag & CBAUD)) {
1523 info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
1524 local_irq_disable();
1525 serial_out(info, UART_MCR, info->MCR);
1526 local_irq_enable();
1527 }
1528
1529 /* Handle transition away from B0 status */
1530 if (!(old_termios->c_cflag & CBAUD) &&
1531 (tty->termios->c_cflag & CBAUD)) {
1532 info->MCR |= UART_MCR_DTR;
1533 if (!tty->hw_stopped ||
1534 !(tty->termios->c_cflag & CRTSCTS)) {
1535 info->MCR |= UART_MCR_RTS;
1536 }
1537 local_irq_disable();
1538 serial_out(info, UART_MCR, info->MCR);
1539 local_irq_enable();
1540 }
1541
1542 /* Handle turning off CRTSCTS */
1543 if ((old_termios->c_cflag & CRTSCTS) &&
1544 !(tty->termios->c_cflag & CRTSCTS)) {
1545 tty->hw_stopped = 0;
1546 rs_360_start(tty);
1547 }
1548#endif
1549
1550#if 0
1551 /*
1552 * No need to wake up processes in open wait, since they
1553 * sample the CLOCAL flag once, and don't recheck it.
1554 * XXX It's not clear whether the current behavior is correct
1555 * or not. Hence, this may change.....
1556 */
1557 if (!(old_termios->c_cflag & CLOCAL) &&
1558 (tty->termios->c_cflag & CLOCAL))
1559 wake_up_interruptible(&info->open_wait);
1560#endif
1561}
1562
1563/*
1564 * ------------------------------------------------------------
1565 * rs_close()
1566 *
1567 * This routine is called when the serial port gets closed. First, we
1568 * wait for the last remaining data to be sent. Then, we unlink its
1569 * async structure from the interrupt chain if necessary, and we free
1570 * that IRQ if nothing is left in the chain.
1571 * ------------------------------------------------------------
1572 */
1573static void rs_360_close(struct tty_struct *tty, struct file * filp)
1574{
1575 ser_info_t *info = (ser_info_t *)tty->driver_data;
1576 /* struct async_state *state; */
1577 struct serial_state *state;
1578 unsigned long flags;
1579 int idx;
1580 volatile struct smc_regs *smcp;
1581 volatile struct scc_regs *sccp;
1582
1583 if (!info || serial_paranoia_check(info, tty->name, "rs_close"))
1584 return;
1585
1586 state = info->state;
1587
1588 local_irq_save(flags);
1589
1590 if (tty_hung_up_p(filp)) {
1591 DBG_CNT("before DEC-hung");
1592 local_irq_restore(flags);
1593 return;
1594 }
1595
1596#ifdef SERIAL_DEBUG_OPEN
1597 printk("rs_close ttys%d, count = %d\n", info->line, state->count);
1598#endif
1599 if ((tty->count == 1) && (state->count != 1)) {
1600 /*
1601 * Uh, oh. tty->count is 1, which means that the tty
1602 * structure will be freed. state->count should always
1603 * be one in these conditions. If it's greater than
1604 * one, we've got real problems, since it means the
1605 * serial port won't be shutdown.
1606 */
1607 printk("rs_close: bad serial port count; tty->count is 1, "
1608 "state->count is %d\n", state->count);
1609 state->count = 1;
1610 }
1611 if (--state->count < 0) {
1612 printk("rs_close: bad serial port count for ttys%d: %d\n",
1613 info->line, state->count);
1614 state->count = 0;
1615 }
1616 if (state->count) {
1617 DBG_CNT("before DEC-2");
1618 local_irq_restore(flags);
1619 return;
1620 }
1621 info->flags |= ASYNC_CLOSING;
1622 /*
1623 * Now we wait for the transmit buffer to clear; and we notify
1624 * the line discipline to only process XON/XOFF characters.
1625 */
1626 tty->closing = 1;
1627 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
1628 tty_wait_until_sent(tty, info->closing_wait);
1629 /*
1630 * At this point we stop accepting input. To do this, we
1631 * disable the receive line status interrupts, and tell the
1632 * interrupt driver to stop checking the data ready bit in the
1633 * line status register.
1634 */
1635 info->read_status_mask &= ~BD_SC_EMPTY;
1636 if (info->flags & ASYNC_INITIALIZED) {
1637
1638 idx = PORT_NUM(info->state->smc_scc_num);
1639 if (info->state->smc_scc_num & NUM_IS_SCC) {
1640 sccp = &pquicc->scc_regs[idx];
1641 sccp->scc_sccm &= ~UART_SCCM_RX;
1642 sccp->scc_gsmr.w.low &= ~SCC_GSMRL_ENR;
1643 } else {
1644 smcp = &pquicc->smc_regs[idx];
1645 smcp->smc_smcm &= ~SMCM_RX;
1646 smcp->smc_smcmr &= ~SMCMR_REN;
1647 }
1648 /*
1649 * Before we drop DTR, make sure the UART transmitter
1650 * has completely drained; this is especially
1651 * important if there is a transmit FIFO!
1652 */
1653 rs_360_wait_until_sent(tty, info->timeout);
1654 }
1655 shutdown(info);
1656 rs_360_flush_buffer(tty);
1657 tty_ldisc_flush(tty);
1658 tty->closing = 0;
1659 info->event = 0;
1660 info->port.tty = NULL;
1661 if (info->blocked_open) {
1662 if (info->close_delay) {
1663 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1664 }
1665 wake_up_interruptible(&info->open_wait);
1666 }
1667 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
1668 wake_up_interruptible(&info->close_wait);
1669 local_irq_restore(flags);
1670}
1671
1672/*
1673 * rs_wait_until_sent() --- wait until the transmitter is empty
1674 */
1675static void rs_360_wait_until_sent(struct tty_struct *tty, int timeout)
1676{
1677 ser_info_t *info = (ser_info_t *)tty->driver_data;
1678 unsigned long orig_jiffies, char_time;
1679 /*int lsr;*/
1680 volatile QUICC_BD *bdp;
1681
1682 if (serial_paranoia_check(info, tty->name, "rs_wait_until_sent"))
1683 return;
1684
1685#ifdef maybe
1686 if (info->state->type == PORT_UNKNOWN)
1687 return;
1688#endif
1689
1690 orig_jiffies = jiffies;
1691 /*
1692 * Set the check interval to be 1/5 of the estimated time to
1693 * send a single character, and make it at least 1. The check
1694 * interval should also be less than the timeout.
1695 *
1696 * Note: we have to use pretty tight timings here to satisfy
1697 * the NIST-PCTS.
1698 */
1699 char_time = 1;
1700 if (timeout)
1701 char_time = min(char_time, (unsigned long)timeout);
1702#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1703 printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
1704 printk("jiff=%lu...", jiffies);
1705#endif
1706
1707 /* We go through the loop at least once because we can't tell
1708 * exactly when the last character exits the shifter. There can
1709 * be at least two characters waiting to be sent after the buffers
1710 * are empty.
1711 */
1712 do {
1713#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1714 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
1715#endif
1716/* current->counter = 0; make us low-priority */
1717 msleep_interruptible(jiffies_to_msecs(char_time));
1718 if (signal_pending(current))
1719 break;
1720 if (timeout && (time_after(jiffies, orig_jiffies + timeout)))
1721 break;
1722 /* The 'tx_cur' is really the next buffer to send. We
1723 * have to back up to the previous BD and wait for it
1724 * to go. This isn't perfect, because all this indicates
1725 * is the buffer is available. There are still characters
1726 * in the CPM FIFO.
1727 */
1728 bdp = info->tx_cur;
1729 if (bdp == info->tx_bd_base)
1730 bdp += (TX_NUM_FIFO-1);
1731 else
1732 bdp--;
1733 } while (bdp->status & BD_SC_READY);
1734 current->state = TASK_RUNNING;
1735#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1736 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
1737#endif
1738}
1739
1740/*
1741 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
1742 */
1743static void rs_360_hangup(struct tty_struct *tty)
1744{
1745 ser_info_t *info = (ser_info_t *)tty->driver_data;
1746 struct serial_state *state = info->state;
1747
1748 if (serial_paranoia_check(info, tty->name, "rs_hangup"))
1749 return;
1750
1751 state = info->state;
1752
1753 rs_360_flush_buffer(tty);
1754 shutdown(info);
1755 info->event = 0;
1756 state->count = 0;
1757 info->flags &= ~ASYNC_NORMAL_ACTIVE;
1758 info->port.tty = NULL;
1759 wake_up_interruptible(&info->open_wait);
1760}
1761
1762/*
1763 * ------------------------------------------------------------
1764 * rs_open() and friends
1765 * ------------------------------------------------------------
1766 */
1767static int block_til_ready(struct tty_struct *tty, struct file * filp,
1768 ser_info_t *info)
1769{
1770#ifdef DO_THIS_LATER
1771 DECLARE_WAITQUEUE(wait, current);
1772#endif
1773 struct serial_state *state = info->state;
1774 int retval;
1775 int do_clocal = 0;
1776
1777 /*
1778 * If the device is in the middle of being closed, then block
1779 * until it's done, and then try again.
1780 */
1781 if (tty_hung_up_p(filp) ||
1782 (info->flags & ASYNC_CLOSING)) {
1783 if (info->flags & ASYNC_CLOSING)
1784 interruptible_sleep_on(&info->close_wait);
1785#ifdef SERIAL_DO_RESTART
1786 if (info->flags & ASYNC_HUP_NOTIFY)
1787 return -EAGAIN;
1788 else
1789 return -ERESTARTSYS;
1790#else
1791 return -EAGAIN;
1792#endif
1793 }
1794
1795 /*
1796 * If non-blocking mode is set, or the port is not enabled,
1797 * then make the check up front and then exit.
1798 * If this is an SMC port, we don't have modem control to wait
1799 * for, so just get out here.
1800 */
1801 if ((filp->f_flags & O_NONBLOCK) ||
1802 (tty->flags & (1 << TTY_IO_ERROR)) ||
1803 !(info->state->smc_scc_num & NUM_IS_SCC)) {
1804 info->flags |= ASYNC_NORMAL_ACTIVE;
1805 return 0;
1806 }
1807
1808 if (tty->termios->c_cflag & CLOCAL)
1809 do_clocal = 1;
1810
1811 /*
1812 * Block waiting for the carrier detect and the line to become
1813 * free (i.e., not in use by the callout). While we are in
1814 * this loop, state->count is dropped by one, so that
1815 * rs_close() knows when to free things. We restore it upon
1816 * exit, either normal or abnormal.
1817 */
1818 retval = 0;
1819#ifdef DO_THIS_LATER
1820 add_wait_queue(&info->open_wait, &wait);
1821#ifdef SERIAL_DEBUG_OPEN
1822 printk("block_til_ready before block: ttys%d, count = %d\n",
1823 state->line, state->count);
1824#endif
1825 local_irq_disable();
1826 if (!tty_hung_up_p(filp))
1827 state->count--;
1828 local_irq_enable();
1829 info->blocked_open++;
1830 while (1) {
1831 local_irq_disable();
1832 if (tty->termios->c_cflag & CBAUD)
1833 serial_out(info, UART_MCR,
1834 serial_inp(info, UART_MCR) |
1835 (UART_MCR_DTR | UART_MCR_RTS));
1836 local_irq_enable();
1837 set_current_state(TASK_INTERRUPTIBLE);
1838 if (tty_hung_up_p(filp) ||
1839 !(info->flags & ASYNC_INITIALIZED)) {
1840#ifdef SERIAL_DO_RESTART
1841 if (info->flags & ASYNC_HUP_NOTIFY)
1842 retval = -EAGAIN;
1843 else
1844 retval = -ERESTARTSYS;
1845#else
1846 retval = -EAGAIN;
1847#endif
1848 break;
1849 }
1850 if (!(info->flags & ASYNC_CLOSING) &&
1851 (do_clocal || (serial_in(info, UART_MSR) &
1852 UART_MSR_DCD)))
1853 break;
1854 if (signal_pending(current)) {
1855 retval = -ERESTARTSYS;
1856 break;
1857 }
1858#ifdef SERIAL_DEBUG_OPEN
1859 printk("block_til_ready blocking: ttys%d, count = %d\n",
1860 info->line, state->count);
1861#endif
1862 tty_unlock();
1863 schedule();
1864 tty_lock();
1865 }
1866 current->state = TASK_RUNNING;
1867 remove_wait_queue(&info->open_wait, &wait);
1868 if (!tty_hung_up_p(filp))
1869 state->count++;
1870 info->blocked_open--;
1871#ifdef SERIAL_DEBUG_OPEN
1872 printk("block_til_ready after blocking: ttys%d, count = %d\n",
1873 info->line, state->count);
1874#endif
1875#endif /* DO_THIS_LATER */
1876 if (retval)
1877 return retval;
1878 info->flags |= ASYNC_NORMAL_ACTIVE;
1879 return 0;
1880}
1881
1882static int get_async_struct(int line, ser_info_t **ret_info)
1883{
1884 struct serial_state *sstate;
1885
1886 sstate = rs_table + line;
1887 if (sstate->info) {
1888 sstate->count++;
1889 *ret_info = (ser_info_t *)sstate->info;
1890 return 0;
1891 }
1892 else {
1893 return -ENOMEM;
1894 }
1895}
1896
1897/*
1898 * This routine is called whenever a serial port is opened. It
1899 * enables interrupts for a serial port, linking in its async structure into
1900 * the IRQ chain. It also performs the serial-specific
1901 * initialization for the tty structure.
1902 */
1903static int rs_360_open(struct tty_struct *tty, struct file * filp)
1904{
1905 ser_info_t *info;
1906 int retval, line;
1907
1908 line = tty->index;
1909 if ((line < 0) || (line >= NR_PORTS))
1910 return -ENODEV;
1911 retval = get_async_struct(line, &info);
1912 if (retval)
1913 return retval;
1914 if (serial_paranoia_check(info, tty->name, "rs_open"))
1915 return -ENODEV;
1916
1917#ifdef SERIAL_DEBUG_OPEN
1918 printk("rs_open %s, count = %d\n", tty->name, info->state->count);
1919#endif
1920 tty->driver_data = info;
1921 info->port.tty = tty;
1922
1923 /*
1924 * Start up serial port
1925 */
1926 retval = startup(info);
1927 if (retval)
1928 return retval;
1929
1930 retval = block_til_ready(tty, filp, info);
1931 if (retval) {
1932#ifdef SERIAL_DEBUG_OPEN
1933 printk("rs_open returning after block_til_ready with %d\n",
1934 retval);
1935#endif
1936 return retval;
1937 }
1938
1939#ifdef SERIAL_DEBUG_OPEN
1940 printk("rs_open %s successful...", tty->name);
1941#endif
1942 return 0;
1943}
1944
1945/*
1946 * /proc fs routines....
1947 */
1948
1949static inline int line_info(char *buf, struct serial_state *state)
1950{
1951#ifdef notdef
1952 struct async_struct *info = state->info, scr_info;
1953 char stat_buf[30], control, status;
1954#endif
1955 int ret;
1956
1957 ret = sprintf(buf, "%d: uart:%s port:%X irq:%d",
1958 state->line,
1959 (state->smc_scc_num & NUM_IS_SCC) ? "SCC" : "SMC",
1960 (unsigned int)(state->port), state->irq);
1961
1962 if (!state->port || (state->type == PORT_UNKNOWN)) {
1963 ret += sprintf(buf+ret, "\n");
1964 return ret;
1965 }
1966
1967#ifdef notdef
1968 /*
1969 * Figure out the current RS-232 lines
1970 */
1971 if (!info) {
1972 info = &scr_info; /* This is just for serial_{in,out} */
1973
1974 info->magic = SERIAL_MAGIC;
1975 info->port = state->port;
1976 info->flags = state->flags;
1977 info->quot = 0;
1978 info->port.tty = NULL;
1979 }
1980 local_irq_disable();
1981 status = serial_in(info, UART_MSR);
1982 control = info ? info->MCR : serial_in(info, UART_MCR);
1983 local_irq_enable();
1984
1985 stat_buf[0] = 0;
1986 stat_buf[1] = 0;
1987 if (control & UART_MCR_RTS)
1988 strcat(stat_buf, "|RTS");
1989 if (status & UART_MSR_CTS)
1990 strcat(stat_buf, "|CTS");
1991 if (control & UART_MCR_DTR)
1992 strcat(stat_buf, "|DTR");
1993 if (status & UART_MSR_DSR)
1994 strcat(stat_buf, "|DSR");
1995 if (status & UART_MSR_DCD)
1996 strcat(stat_buf, "|CD");
1997 if (status & UART_MSR_RI)
1998 strcat(stat_buf, "|RI");
1999
2000 if (info->quot) {
2001 ret += sprintf(buf+ret, " baud:%d",
2002 state->baud_base / info->quot);
2003 }
2004
2005 ret += sprintf(buf+ret, " tx:%d rx:%d",
2006 state->icount.tx, state->icount.rx);
2007
2008 if (state->icount.frame)
2009 ret += sprintf(buf+ret, " fe:%d", state->icount.frame);
2010
2011 if (state->icount.parity)
2012 ret += sprintf(buf+ret, " pe:%d", state->icount.parity);
2013
2014 if (state->icount.brk)
2015 ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
2016
2017 if (state->icount.overrun)
2018 ret += sprintf(buf+ret, " oe:%d", state->icount.overrun);
2019
2020 /*
2021 * Last thing is the RS-232 status lines
2022 */
2023 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
2024#endif
2025 return ret;
2026}
2027
2028int rs_360_read_proc(char *page, char **start, off_t off, int count,
2029 int *eof, void *data)
2030{
2031 int i, len = 0;
2032 off_t begin = 0;
2033
2034 len += sprintf(page, "serinfo:1.0 driver:%s\n", serial_version);
2035 for (i = 0; i < NR_PORTS && len < 4000; i++) {
2036 len += line_info(page + len, &rs_table[i]);
2037 if (len+begin > off+count)
2038 goto done;
2039 if (len+begin < off) {
2040 begin += len;
2041 len = 0;
2042 }
2043 }
2044 *eof = 1;
2045done:
2046 if (off >= len+begin)
2047 return 0;
2048 *start = page + (begin-off);
2049 return ((count < begin+len-off) ? count : begin+len-off);
2050}
2051
2052/*
2053 * ---------------------------------------------------------------------
2054 * rs_init() and friends
2055 *
2056 * rs_init() is called at boot-time to initialize the serial driver.
2057 * ---------------------------------------------------------------------
2058 */
2059
2060/*
2061 * This routine prints out the appropriate serial driver version
2062 * number, and identifies which options were configured into this
2063 * driver.
2064 */
2065static _INLINE_ void show_serial_version(void)
2066{
2067 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
2068}
2069
2070
2071/*
2072 * The serial console driver used during boot. Note that these names
2073 * clash with those found in "serial.c", so we currently can't support
2074 * the 16xxx uarts and these at the same time. I will fix this to become
2075 * an indirect function call from tty_io.c (or something).
2076 */
2077
2078#ifdef CONFIG_SERIAL_CONSOLE
2079
2080/*
2081 * Print a string to the serial port trying not to disturb any possible
2082 * real use of the port...
2083 */
2084static void my_console_write(int idx, const char *s,
2085 unsigned count)
2086{
2087 struct serial_state *ser;
2088 ser_info_t *info;
2089 unsigned i;
2090 QUICC_BD *bdp, *bdbase;
2091 volatile struct smc_uart_pram *up;
2092 volatile u_char *cp;
2093
2094 ser = rs_table + idx;
2095
2096
2097 /* If the port has been initialized for general use, we have
2098 * to use the buffer descriptors allocated there. Otherwise,
2099 * we simply use the single buffer allocated.
2100 */
2101 if ((info = (ser_info_t *)ser->info) != NULL) {
2102 bdp = info->tx_cur;
2103 bdbase = info->tx_bd_base;
2104 }
2105 else {
2106 /* Pointer to UART in parameter ram.
2107 */
2108 /* up = (smc_uart_t *)&cpmp->cp_dparam[ser->port]; */
2109 up = &pquicc->pram[ser->port].scc.pothers.idma_smc.psmc.u;
2110
2111 /* Get the address of the host memory buffer.
2112 */
2113 bdp = bdbase = (QUICC_BD *)((uint)pquicc + (uint)up->tbase);
2114 }
2115
2116 /*
2117 * We need to gracefully shut down the transmitter, disable
2118 * interrupts, then send our bytes out.
2119 */
2120
2121 /*
2122 * Now, do each character. This is not as bad as it looks
2123 * since this is a holding FIFO and not a transmitting FIFO.
2124 * We could add the complexity of filling the entire transmit
2125 * buffer, but we would just wait longer between accesses......
2126 */
2127 for (i = 0; i < count; i++, s++) {
2128 /* Wait for transmitter fifo to empty.
2129 * Ready indicates output is ready, and xmt is doing
2130 * that, not that it is ready for us to send.
2131 */
2132 while (bdp->status & BD_SC_READY);
2133
2134 /* Send the character out.
2135 */
2136 cp = bdp->buf;
2137 *cp = *s;
2138
2139 bdp->length = 1;
2140 bdp->status |= BD_SC_READY;
2141
2142 if (bdp->status & BD_SC_WRAP)
2143 bdp = bdbase;
2144 else
2145 bdp++;
2146
2147 /* if a LF, also do CR... */
2148 if (*s == 10) {
2149 while (bdp->status & BD_SC_READY);
2150 /* cp = __va(bdp->buf); */
2151 cp = bdp->buf;
2152 *cp = 13;
2153 bdp->length = 1;
2154 bdp->status |= BD_SC_READY;
2155
2156 if (bdp->status & BD_SC_WRAP) {
2157 bdp = bdbase;
2158 }
2159 else {
2160 bdp++;
2161 }
2162 }
2163 }
2164
2165 /*
2166 * Finally, Wait for transmitter & holding register to empty
2167 * and restore the IER
2168 */
2169 while (bdp->status & BD_SC_READY);
2170
2171 if (info)
2172 info->tx_cur = (QUICC_BD *)bdp;
2173}
2174
2175static void serial_console_write(struct console *c, const char *s,
2176 unsigned count)
2177{
2178#ifdef CONFIG_KGDB
2179 /* Try to let stub handle output. Returns true if it did. */
2180 if (kgdb_output_string(s, count))
2181 return;
2182#endif
2183 my_console_write(c->index, s, count);
2184}
2185
2186
2187
2188/*void console_print_68360(const char *p)
2189{
2190 const char *cp = p;
2191 int i;
2192
2193 for (i=0;cp[i]!=0;i++);
2194
2195 serial_console_write (p, i);
2196
2197 //Comment this if you want to have a strict interrupt-driven output
2198 //rs_fair_output();
2199
2200 return;
2201}*/
2202
2203
2204
2205
2206
2207
2208#ifdef CONFIG_XMON
2209int
2210xmon_360_write(const char *s, unsigned count)
2211{
2212 my_console_write(0, s, count);
2213 return(count);
2214}
2215#endif
2216
2217#ifdef CONFIG_KGDB
2218void
2219putDebugChar(char ch)
2220{
2221 my_console_write(0, &ch, 1);
2222}
2223#endif
2224
2225/*
2226 * Receive character from the serial port. This only works well
2227 * before the port is initialized for real use.
2228 */
2229static int my_console_wait_key(int idx, int xmon, char *obuf)
2230{
2231 struct serial_state *ser;
2232 u_char c, *cp;
2233 ser_info_t *info;
2234 QUICC_BD *bdp;
2235 volatile struct smc_uart_pram *up;
2236 int i;
2237
2238 ser = rs_table + idx;
2239
2240 /* Get the address of the host memory buffer.
2241 * If the port has been initialized for general use, we must
2242 * use information from the port structure.
2243 */
2244 if ((info = (ser_info_t *)ser->info))
2245 bdp = info->rx_cur;
2246 else
2247 /* bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_rbase]; */
2248 bdp = (QUICC_BD *)((uint)pquicc + (uint)up->tbase);
2249
2250 /* Pointer to UART in parameter ram.
2251 */
2252 /* up = (smc_uart_t *)&cpmp->cp_dparam[ser->port]; */
2253 up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
2254
2255 /*
2256 * We need to gracefully shut down the receiver, disable
2257 * interrupts, then read the input.
2258 * XMON just wants a poll. If no character, return -1, else
2259 * return the character.
2260 */
2261 if (!xmon) {
2262 while (bdp->status & BD_SC_EMPTY);
2263 }
2264 else {
2265 if (bdp->status & BD_SC_EMPTY)
2266 return -1;
2267 }
2268
2269 cp = (char *)bdp->buf;
2270
2271 if (obuf) {
2272 i = c = bdp->length;
2273 while (i-- > 0)
2274 *obuf++ = *cp++;
2275 }
2276 else {
2277 c = *cp;
2278 }
2279 bdp->status |= BD_SC_EMPTY;
2280
2281 if (info) {
2282 if (bdp->status & BD_SC_WRAP) {
2283 bdp = info->rx_bd_base;
2284 }
2285 else {
2286 bdp++;
2287 }
2288 info->rx_cur = (QUICC_BD *)bdp;
2289 }
2290
2291 return((int)c);
2292}
2293
2294static int serial_console_wait_key(struct console *co)
2295{
2296 return(my_console_wait_key(co->index, 0, NULL));
2297}
2298
2299#ifdef CONFIG_XMON
2300int
2301xmon_360_read_poll(void)
2302{
2303 return(my_console_wait_key(0, 1, NULL));
2304}
2305
2306int
2307xmon_360_read_char(void)
2308{
2309 return(my_console_wait_key(0, 0, NULL));
2310}
2311#endif
2312
2313#ifdef CONFIG_KGDB
2314static char kgdb_buf[RX_BUF_SIZE], *kgdp;
2315static int kgdb_chars;
2316
2317unsigned char
2318getDebugChar(void)
2319{
2320 if (kgdb_chars <= 0) {
2321 kgdb_chars = my_console_wait_key(0, 0, kgdb_buf);
2322 kgdp = kgdb_buf;
2323 }
2324 kgdb_chars--;
2325
2326 return(*kgdp++);
2327}
2328
2329void kgdb_interruptible(int state)
2330{
2331}
2332void kgdb_map_scc(void)
2333{
2334 struct serial_state *ser;
2335 uint mem_addr;
2336 volatile QUICC_BD *bdp;
2337 volatile smc_uart_t *up;
2338
2339 cpmp = (cpm360_t *)&(((immap_t *)IMAP_ADDR)->im_cpm);
2340
2341 /* To avoid data cache CPM DMA coherency problems, allocate a
2342 * buffer in the CPM DPRAM. This will work until the CPM and
2343 * serial ports are initialized. At that time a memory buffer
2344 * will be allocated.
2345 * The port is already initialized from the boot procedure, all
2346 * we do here is give it a different buffer and make it a FIFO.
2347 */
2348
2349 ser = rs_table;
2350
2351 /* Right now, assume we are using SMCs.
2352 */
2353 up = (smc_uart_t *)&cpmp->cp_dparam[ser->port];
2354
2355 /* Allocate space for an input FIFO, plus a few bytes for output.
2356 * Allocate bytes to maintain word alignment.
2357 */
2358 mem_addr = (uint)(&cpmp->cp_dpmem[0x1000]);
2359
2360 /* Set the physical address of the host memory buffers in
2361 * the buffer descriptors.
2362 */
2363 bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_rbase];
2364 bdp->buf = mem_addr;
2365
2366 bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_tbase];
2367 bdp->buf = mem_addr+RX_BUF_SIZE;
2368
2369 up->smc_mrblr = RX_BUF_SIZE; /* receive buffer length */
2370 up->smc_maxidl = RX_BUF_SIZE;
2371}
2372#endif
2373
2374static struct tty_struct *serial_console_device(struct console *c, int *index)
2375{
2376 *index = c->index;
2377 return serial_driver;
2378}
2379
2380
2381struct console sercons = {
2382 .name = "ttyS",
2383 .write = serial_console_write,
2384 .device = serial_console_device,
2385 .wait_key = serial_console_wait_key,
2386 .setup = serial_console_setup,
2387 .flags = CON_PRINTBUFFER,
2388 .index = CONFIG_SERIAL_CONSOLE_PORT,
2389};
2390
2391
2392
2393/*
2394 * Register console.
2395 */
2396long console_360_init(long kmem_start, long kmem_end)
2397{
2398 register_console(&sercons);
2399 /*register_console (console_print_68360); - 2.0.38 only required a write
2400 function pointer. */
2401 return kmem_start;
2402}
2403
2404#endif
2405
2406/* Index in baud rate table of the default console baud rate.
2407*/
2408static int baud_idx;
2409
2410static const struct tty_operations rs_360_ops = {
2411 .owner = THIS_MODULE,
2412 .open = rs_360_open,
2413 .close = rs_360_close,
2414 .write = rs_360_write,
2415 .put_char = rs_360_put_char,
2416 .write_room = rs_360_write_room,
2417 .chars_in_buffer = rs_360_chars_in_buffer,
2418 .flush_buffer = rs_360_flush_buffer,
2419 .ioctl = rs_360_ioctl,
2420 .throttle = rs_360_throttle,
2421 .unthrottle = rs_360_unthrottle,
2422 /* .send_xchar = rs_360_send_xchar, */
2423 .set_termios = rs_360_set_termios,
2424 .stop = rs_360_stop,
2425 .start = rs_360_start,
2426 .hangup = rs_360_hangup,
2427 /* .wait_until_sent = rs_360_wait_until_sent, */
2428 /* .read_proc = rs_360_read_proc, */
2429 .tiocmget = rs_360_tiocmget,
2430 .tiocmset = rs_360_tiocmset,
2431 .get_icount = rs_360_get_icount,
2432};
2433
2434static int __init rs_360_init(void)
2435{
2436 struct serial_state * state;
2437 ser_info_t *info;
2438 void *mem_addr;
2439 uint dp_addr, iobits;
2440 int i, j, idx;
2441 ushort chan;
2442 QUICC_BD *bdp;
2443 volatile QUICC *cp;
2444 volatile struct smc_regs *sp;
2445 volatile struct smc_uart_pram *up;
2446 volatile struct scc_regs *scp;
2447 volatile struct uart_pram *sup;
2448 /* volatile immap_t *immap; */
2449
2450 serial_driver = alloc_tty_driver(NR_PORTS);
2451 if (!serial_driver)
2452 return -1;
2453
2454 show_serial_version();
2455
2456 serial_driver->name = "ttyS";
2457 serial_driver->major = TTY_MAJOR;
2458 serial_driver->minor_start = 64;
2459 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2460 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2461 serial_driver->init_termios = tty_std_termios;
2462 serial_driver->init_termios.c_cflag =
2463 baud_idx | CS8 | CREAD | HUPCL | CLOCAL;
2464 serial_driver->flags = TTY_DRIVER_REAL_RAW;
2465 tty_set_operations(serial_driver, &rs_360_ops);
2466
2467 if (tty_register_driver(serial_driver))
2468 panic("Couldn't register serial driver\n");
2469
2470 cp = pquicc; /* Get pointer to Communication Processor */
2471 /* immap = (immap_t *)IMAP_ADDR; */ /* and to internal registers */
2472
2473
2474 /* Configure SCC2, SCC3, and SCC4 instead of port A parallel I/O.
2475 */
2476 /* The "standard" configuration through the 860.
2477 */
2478/* immap->im_ioport.iop_papar |= 0x00fc; */
2479/* immap->im_ioport.iop_padir &= ~0x00fc; */
2480/* immap->im_ioport.iop_paodr &= ~0x00fc; */
2481 cp->pio_papar |= 0x00fc;
2482 cp->pio_padir &= ~0x00fc;
2483 /* cp->pio_paodr &= ~0x00fc; */
2484
2485
2486 /* Since we don't yet do modem control, connect the port C pins
2487 * as general purpose I/O. This will assert CTS and CD for the
2488 * SCC ports.
2489 */
2490 /* FIXME: see 360um p.7-365 and 860um p.34-12
2491 * I can't make sense of these bits - mleslie*/
2492/* immap->im_ioport.iop_pcdir |= 0x03c6; */
2493/* immap->im_ioport.iop_pcpar &= ~0x03c6; */
2494
2495/* cp->pio_pcdir |= 0x03c6; */
2496/* cp->pio_pcpar &= ~0x03c6; */
2497
2498
2499
2500 /* Connect SCC2 and SCC3 to NMSI. Connect BRG3 to SCC2 and
2501 * BRG4 to SCC3.
2502 */
2503 cp->si_sicr &= ~0x00ffff00;
2504 cp->si_sicr |= 0x001b1200;
2505
2506#ifdef CONFIG_PP04
2507 /* Frequentis PP04 forced to RS-232 until we know better.
2508 * Port C 12 and 13 low enables RS-232 on SCC3 and SCC4.
2509 */
2510 immap->im_ioport.iop_pcdir |= 0x000c;
2511 immap->im_ioport.iop_pcpar &= ~0x000c;
2512 immap->im_ioport.iop_pcdat &= ~0x000c;
2513
2514 /* This enables the TX driver.
2515 */
2516 cp->cp_pbpar &= ~0x6000;
2517 cp->cp_pbdat &= ~0x6000;
2518#endif
2519
2520 for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
2521 state->magic = SSTATE_MAGIC;
2522 state->line = i;
2523 state->type = PORT_UNKNOWN;
2524 state->custom_divisor = 0;
2525 state->close_delay = 5*HZ/10;
2526 state->closing_wait = 30*HZ;
2527 state->icount.cts = state->icount.dsr =
2528 state->icount.rng = state->icount.dcd = 0;
2529 state->icount.rx = state->icount.tx = 0;
2530 state->icount.frame = state->icount.parity = 0;
2531 state->icount.overrun = state->icount.brk = 0;
2532 printk(KERN_INFO "ttyS%d at irq 0x%02x is an %s\n",
2533 i, (unsigned int)(state->irq),
2534 (state->smc_scc_num & NUM_IS_SCC) ? "SCC" : "SMC");
2535
2536#ifdef CONFIG_SERIAL_CONSOLE
2537 /* If we just printed the message on the console port, and
2538 * we are about to initialize it for general use, we have
2539 * to wait a couple of character times for the CR/NL to
2540 * make it out of the transmit buffer.
2541 */
2542 if (i == CONFIG_SERIAL_CONSOLE_PORT)
2543 mdelay(8);
2544
2545
2546/* idx = PORT_NUM(info->state->smc_scc_num); */
2547/* if (info->state->smc_scc_num & NUM_IS_SCC) */
2548/* chan = scc_chan_map[idx]; */
2549/* else */
2550/* chan = smc_chan_map[idx]; */
2551
2552/* cp->cp_cr = mk_cr_cmd(chan, CPM_CR_STOP_TX) | CPM_CR_FLG; */
2553/* while (cp->cp_cr & CPM_CR_FLG); */
2554
2555#endif
2556 /* info = kmalloc(sizeof(ser_info_t), GFP_KERNEL); */
2557 info = &quicc_ser_info[i];
2558 if (info) {
2559 memset (info, 0, sizeof(ser_info_t));
2560 info->magic = SERIAL_MAGIC;
2561 info->line = i;
2562 info->flags = state->flags;
2563 INIT_WORK(&info->tqueue, do_softint, info);
2564 INIT_WORK(&info->tqueue_hangup, do_serial_hangup, info);
2565 init_waitqueue_head(&info->open_wait);
2566 init_waitqueue_head(&info->close_wait);
2567 info->state = state;
2568 state->info = (struct async_struct *)info;
2569
2570 /* We need to allocate a transmit and receive buffer
2571 * descriptors from dual port ram, and a character
2572 * buffer area from host mem.
2573 */
2574 dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * RX_NUM_FIFO);
2575
2576 /* Allocate space for FIFOs in the host memory.
2577 * (for now this is from a static array of buffers :(
2578 */
2579 /* mem_addr = m360_cpm_hostalloc(RX_NUM_FIFO * RX_BUF_SIZE); */
2580 /* mem_addr = kmalloc (RX_NUM_FIFO * RX_BUF_SIZE, GFP_BUFFER); */
2581 mem_addr = &rx_buf_pool[i * RX_NUM_FIFO * RX_BUF_SIZE];
2582
2583 /* Set the physical address of the host memory
2584 * buffers in the buffer descriptors, and the
2585 * virtual address for us to work with.
2586 */
2587 bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
2588 info->rx_cur = info->rx_bd_base = bdp;
2589
2590 /* initialize rx buffer descriptors */
2591 for (j=0; j<(RX_NUM_FIFO-1); j++) {
2592 bdp->buf = &rx_buf_pool[(i * RX_NUM_FIFO + j ) * RX_BUF_SIZE];
2593 bdp->status = BD_SC_EMPTY | BD_SC_INTRPT;
2594 mem_addr += RX_BUF_SIZE;
2595 bdp++;
2596 }
2597 bdp->buf = &rx_buf_pool[(i * RX_NUM_FIFO + j ) * RX_BUF_SIZE];
2598 bdp->status = BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT;
2599
2600
2601 idx = PORT_NUM(info->state->smc_scc_num);
2602 if (info->state->smc_scc_num & NUM_IS_SCC) {
2603
2604#if defined (CONFIG_UCQUICC) && 1
2605 /* set the transceiver mode to RS232 */
2606 sipex_mode_bits &= ~(uint)SIPEX_MODE(idx,0x0f); /* clear current mode */
2607 sipex_mode_bits |= (uint)SIPEX_MODE(idx,0x02);
2608 *(uint *)_periph_base = sipex_mode_bits;
2609 /* printk ("sipex bits = 0x%08x\n", sipex_mode_bits); */
2610#endif
2611 }
2612
2613 dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * TX_NUM_FIFO);
2614
2615 /* Allocate space for FIFOs in the host memory.
2616 */
2617 /* mem_addr = m360_cpm_hostalloc(TX_NUM_FIFO * TX_BUF_SIZE); */
2618 /* mem_addr = kmalloc (TX_NUM_FIFO * TX_BUF_SIZE, GFP_BUFFER); */
2619 mem_addr = &tx_buf_pool[i * TX_NUM_FIFO * TX_BUF_SIZE];
2620
2621 /* Set the physical address of the host memory
2622 * buffers in the buffer descriptors, and the
2623 * virtual address for us to work with.
2624 */
2625 /* bdp = (QUICC_BD *)&cp->cp_dpmem[dp_addr]; */
2626 bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
2627 info->tx_cur = info->tx_bd_base = (QUICC_BD *)bdp;
2628
2629 /* initialize tx buffer descriptors */
2630 for (j=0; j<(TX_NUM_FIFO-1); j++) {
2631 bdp->buf = &tx_buf_pool[(i * TX_NUM_FIFO + j ) * TX_BUF_SIZE];
2632 bdp->status = BD_SC_INTRPT;
2633 mem_addr += TX_BUF_SIZE;
2634 bdp++;
2635 }
2636 bdp->buf = &tx_buf_pool[(i * TX_NUM_FIFO + j ) * TX_BUF_SIZE];
2637 bdp->status = (BD_SC_WRAP | BD_SC_INTRPT);
2638
2639 if (info->state->smc_scc_num & NUM_IS_SCC) {
2640 scp = &pquicc->scc_regs[idx];
2641 sup = &pquicc->pram[info->state->port].scc.pscc.u;
2642 sup->rbase = dp_addr;
2643 sup->tbase = dp_addr;
2644
2645 /* Set up the uart parameters in the
2646 * parameter ram.
2647 */
2648 sup->rfcr = SMC_EB;
2649 sup->tfcr = SMC_EB;
2650
2651 /* Set this to 1 for now, so we get single
2652 * character interrupts. Using idle character
2653 * time requires some additional tuning.
2654 */
2655 sup->mrblr = 1;
2656 sup->max_idl = 0;
2657 sup->brkcr = 1;
2658 sup->parec = 0;
2659 sup->frmer = 0;
2660 sup->nosec = 0;
2661 sup->brkec = 0;
2662 sup->uaddr1 = 0;
2663 sup->uaddr2 = 0;
2664 sup->toseq = 0;
2665 {
2666 int i;
2667 for (i=0;i<8;i++)
2668 sup->cc[i] = 0x8000;
2669 }
2670 sup->rccm = 0xc0ff;
2671
2672 /* Send the CPM an initialize command.
2673 */
2674 chan = scc_chan_map[idx];
2675
2676 /* execute the INIT RX & TX PARAMS command for this channel. */
2677 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
2678 while (cp->cp_cr & CPM_CR_FLG);
2679
2680 /* Set UART mode, 8 bit, no parity, one stop.
2681 * Enable receive and transmit.
2682 */
2683 scp->scc_gsmr.w.high = 0;
2684 scp->scc_gsmr.w.low =
2685 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
2686
2687 /* Disable all interrupts and clear all pending
2688 * events.
2689 */
2690 scp->scc_sccm = 0;
2691 scp->scc_scce = 0xffff;
2692 scp->scc_dsr = 0x7e7e;
2693 scp->scc_psmr = 0x3000;
2694
2695 /* If the port is the console, enable Rx and Tx.
2696 */
2697#ifdef CONFIG_SERIAL_CONSOLE
2698 if (i == CONFIG_SERIAL_CONSOLE_PORT)
2699 scp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
2700#endif
2701 }
2702 else {
2703 /* Configure SMCs Tx/Rx instead of port B
2704 * parallel I/O.
2705 */
2706 up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
2707 up->rbase = dp_addr;
2708
2709 iobits = 0xc0 << (idx * 4);
2710 cp->pip_pbpar |= iobits;
2711 cp->pip_pbdir &= ~iobits;
2712 cp->pip_pbodr &= ~iobits;
2713
2714
2715 /* Connect the baud rate generator to the
2716 * SMC based upon index in rs_table. Also
2717 * make sure it is connected to NMSI.
2718 */
2719 cp->si_simode &= ~(0xffff << (idx * 16));
2720 cp->si_simode |= (i << ((idx * 16) + 12));
2721
2722 up->tbase = dp_addr;
2723
2724 /* Set up the uart parameters in the
2725 * parameter ram.
2726 */
2727 up->rfcr = SMC_EB;
2728 up->tfcr = SMC_EB;
2729
2730 /* Set this to 1 for now, so we get single
2731 * character interrupts. Using idle character
2732 * time requires some additional tuning.
2733 */
2734 up->mrblr = 1;
2735 up->max_idl = 0;
2736 up->brkcr = 1;
2737
2738 /* Send the CPM an initialize command.
2739 */
2740 chan = smc_chan_map[idx];
2741
2742 cp->cp_cr = mk_cr_cmd(chan,
2743 CPM_CR_INIT_TRX) | CPM_CR_FLG;
2744#ifdef CONFIG_SERIAL_CONSOLE
2745 if (i == CONFIG_SERIAL_CONSOLE_PORT)
2746 printk("");
2747#endif
2748 while (cp->cp_cr & CPM_CR_FLG);
2749
2750 /* Set UART mode, 8 bit, no parity, one stop.
2751 * Enable receive and transmit.
2752 */
2753 sp = &cp->smc_regs[idx];
2754 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
2755
2756 /* Disable all interrupts and clear all pending
2757 * events.
2758 */
2759 sp->smc_smcm = 0;
2760 sp->smc_smce = 0xff;
2761
2762 /* If the port is the console, enable Rx and Tx.
2763 */
2764#ifdef CONFIG_SERIAL_CONSOLE
2765 if (i == CONFIG_SERIAL_CONSOLE_PORT)
2766 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
2767#endif
2768 }
2769
2770 /* Install interrupt handler.
2771 */
2772 /* cpm_install_handler(IRQ_MACHSPEC | state->irq, rs_360_interrupt, info); */
2773 /*request_irq(IRQ_MACHSPEC | state->irq, rs_360_interrupt, */
2774 request_irq(state->irq, rs_360_interrupt,
2775 IRQ_FLG_LOCK, "ttyS", (void *)info);
2776
2777 /* Set up the baud rate generator.
2778 */
2779 m360_cpm_setbrg(i, baud_table[baud_idx]);
2780
2781 }
2782 }
2783
2784 return 0;
2785}
2786module_init(rs_360_init);
2787
2788/* This must always be called before the rs_360_init() function, otherwise
2789 * it blows away the port control information.
2790 */
2791//static int __init serial_console_setup( struct console *co, char *options)
2792int serial_console_setup( struct console *co, char *options)
2793{
2794 struct serial_state *ser;
2795 uint mem_addr, dp_addr, bidx, idx, iobits;
2796 ushort chan;
2797 QUICC_BD *bdp;
2798 volatile QUICC *cp;
2799 volatile struct smc_regs *sp;
2800 volatile struct scc_regs *scp;
2801 volatile struct smc_uart_pram *up;
2802 volatile struct uart_pram *sup;
2803
2804/* mleslie TODO:
2805 * add something to the 68k bootloader to store a desired initial console baud rate */
2806
2807/* bd_t *bd; */ /* a board info struct used by EPPC-bug */
2808/* bd = (bd_t *)__res; */
2809
2810 for (bidx = 0; bidx < (sizeof(baud_table) / sizeof(int)); bidx++)
2811 /* if (bd->bi_baudrate == baud_table[bidx]) */
2812 if (CONSOLE_BAUDRATE == baud_table[bidx])
2813 break;
2814
2815 /* co->cflag = CREAD|CLOCAL|bidx|CS8; */
2816 baud_idx = bidx;
2817
2818 ser = rs_table + CONFIG_SERIAL_CONSOLE_PORT;
2819
2820 cp = pquicc; /* Get pointer to Communication Processor */
2821
2822 idx = PORT_NUM(ser->smc_scc_num);
2823 if (ser->smc_scc_num & NUM_IS_SCC) {
2824
2825 /* TODO: need to set up SCC pin assignment etc. here */
2826
2827 }
2828 else {
2829 iobits = 0xc0 << (idx * 4);
2830 cp->pip_pbpar |= iobits;
2831 cp->pip_pbdir &= ~iobits;
2832 cp->pip_pbodr &= ~iobits;
2833
2834 /* Connect the baud rate generator to the
2835 * SMC based upon index in rs_table. Also
2836 * make sure it is connected to NMSI.
2837 */
2838 cp->si_simode &= ~(0xffff << (idx * 16));
2839 cp->si_simode |= (idx << ((idx * 16) + 12));
2840 }
2841
2842 /* When we get here, the CPM has been reset, so we need
2843 * to configure the port.
2844 * We need to allocate a transmit and receive buffer descriptor
2845 * from dual port ram, and a character buffer area from host mem.
2846 */
2847
2848 /* Allocate space for two buffer descriptors in the DP ram.
2849 */
2850 dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * CONSOLE_NUM_FIFO);
2851
2852 /* Allocate space for two 2 byte FIFOs in the host memory.
2853 */
2854 /* mem_addr = m360_cpm_hostalloc(8); */
2855 mem_addr = (uint)console_fifos;
2856
2857
2858 /* Set the physical address of the host memory buffers in
2859 * the buffer descriptors.
2860 */
2861 /* bdp = (QUICC_BD *)&cp->cp_dpmem[dp_addr]; */
2862 bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
2863 bdp->buf = (char *)mem_addr;
2864 (bdp+1)->buf = (char *)(mem_addr+4);
2865
2866 /* For the receive, set empty and wrap.
2867 * For transmit, set wrap.
2868 */
2869 bdp->status = BD_SC_EMPTY | BD_SC_WRAP;
2870 (bdp+1)->status = BD_SC_WRAP;
2871
2872 /* Set up the uart parameters in the parameter ram.
2873 */
2874 if (ser->smc_scc_num & NUM_IS_SCC) {
2875 scp = &cp->scc_regs[idx];
2876 /* sup = (scc_uart_t *)&cp->cp_dparam[ser->port]; */
2877 sup = &pquicc->pram[ser->port].scc.pscc.u;
2878
2879 sup->rbase = dp_addr;
2880 sup->tbase = dp_addr + sizeof(QUICC_BD);
2881
2882 /* Set up the uart parameters in the
2883 * parameter ram.
2884 */
2885 sup->rfcr = SMC_EB;
2886 sup->tfcr = SMC_EB;
2887
2888 /* Set this to 1 for now, so we get single
2889 * character interrupts. Using idle character
2890 * time requires some additional tuning.
2891 */
2892 sup->mrblr = 1;
2893 sup->max_idl = 0;
2894 sup->brkcr = 1;
2895 sup->parec = 0;
2896 sup->frmer = 0;
2897 sup->nosec = 0;
2898 sup->brkec = 0;
2899 sup->uaddr1 = 0;
2900 sup->uaddr2 = 0;
2901 sup->toseq = 0;
2902 {
2903 int i;
2904 for (i=0;i<8;i++)
2905 sup->cc[i] = 0x8000;
2906 }
2907 sup->rccm = 0xc0ff;
2908
2909 /* Send the CPM an initialize command.
2910 */
2911 chan = scc_chan_map[idx];
2912
2913 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
2914 while (cp->cp_cr & CPM_CR_FLG);
2915
2916 /* Set UART mode, 8 bit, no parity, one stop.
2917 * Enable receive and transmit.
2918 */
2919 scp->scc_gsmr.w.high = 0;
2920 scp->scc_gsmr.w.low =
2921 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
2922
2923 /* Disable all interrupts and clear all pending
2924 * events.
2925 */
2926 scp->scc_sccm = 0;
2927 scp->scc_scce = 0xffff;
2928 scp->scc_dsr = 0x7e7e;
2929 scp->scc_psmr = 0x3000;
2930
2931 scp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
2932
2933 }
2934 else {
2935 /* up = (smc_uart_t *)&cp->cp_dparam[ser->port]; */
2936 up = &pquicc->pram[ser->port].scc.pothers.idma_smc.psmc.u;
2937
2938 up->rbase = dp_addr; /* Base of receive buffer desc. */
2939 up->tbase = dp_addr+sizeof(QUICC_BD); /* Base of xmt buffer desc. */
2940 up->rfcr = SMC_EB;
2941 up->tfcr = SMC_EB;
2942
2943 /* Set this to 1 for now, so we get single character interrupts.
2944 */
2945 up->mrblr = 1; /* receive buffer length */
2946 up->max_idl = 0; /* wait forever for next char */
2947
2948 /* Send the CPM an initialize command.
2949 */
2950 chan = smc_chan_map[idx];
2951 cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
2952 while (cp->cp_cr & CPM_CR_FLG);
2953
2954 /* Set UART mode, 8 bit, no parity, one stop.
2955 * Enable receive and transmit.
2956 */
2957 sp = &cp->smc_regs[idx];
2958 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
2959
2960 /* And finally, enable Rx and Tx.
2961 */
2962 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
2963 }
2964
2965 /* Set up the baud rate generator.
2966 */
2967 /* m360_cpm_setbrg((ser - rs_table), bd->bi_baudrate); */
2968 m360_cpm_setbrg((ser - rs_table), CONSOLE_BAUDRATE);
2969
2970 return 0;
2971}
2972
2973/*
2974 * Local variables:
2975 * c-indent-level: 4
2976 * c-basic-offset: 4
2977 * tab-width: 4
2978 * End:
2979 */
diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
new file mode 100644
index 00000000000..a3f966b3986
--- /dev/null
+++ b/drivers/tty/serial/8250.c
@@ -0,0 +1,3452 @@
1/*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/delay.h>
30#include <linux/platform_device.h>
31#include <linux/tty.h>
32#include <linux/ratelimit.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
38#include <linux/nmi.h>
39#include <linux/mutex.h>
40#include <linux/slab.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
51/*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
84#define PASS_LIMIT 512
85
86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
109#include <asm/serial.h>
110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
119static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
132struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
156};
157
158struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163};
164
165#define NR_IRQ_HASH 32 /* Can be adjusted later */
166static struct hlist_head irq_lists[NR_IRQ_HASH];
167static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169/*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
275 },
276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
289 },
290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
297 [PORT_U6_16550A] = {
298 .name = "U6_16550A",
299 .fifo_size = 64,
300 .tx_loadsz = 64,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE |
311 UART_CAP_HW_CTSRTS,
312 },
313};
314
315#if defined(CONFIG_MIPS_ALCHEMY)
316
317/* Au1x00 UART hardware has a weird register layout */
318static const u8 au_io_in_map[] = {
319 [UART_RX] = 0,
320 [UART_IER] = 2,
321 [UART_IIR] = 3,
322 [UART_LCR] = 5,
323 [UART_MCR] = 6,
324 [UART_LSR] = 7,
325 [UART_MSR] = 8,
326};
327
328static const u8 au_io_out_map[] = {
329 [UART_TX] = 1,
330 [UART_IER] = 2,
331 [UART_FCR] = 4,
332 [UART_LCR] = 5,
333 [UART_MCR] = 6,
334};
335
336/* sane hardware needs no mapping */
337static inline int map_8250_in_reg(struct uart_port *p, int offset)
338{
339 if (p->iotype != UPIO_AU)
340 return offset;
341 return au_io_in_map[offset];
342}
343
344static inline int map_8250_out_reg(struct uart_port *p, int offset)
345{
346 if (p->iotype != UPIO_AU)
347 return offset;
348 return au_io_out_map[offset];
349}
350
351#elif defined(CONFIG_SERIAL_8250_RM9K)
352
353static const u8
354 regmap_in[8] = {
355 [UART_RX] = 0x00,
356 [UART_IER] = 0x0c,
357 [UART_IIR] = 0x14,
358 [UART_LCR] = 0x1c,
359 [UART_MCR] = 0x20,
360 [UART_LSR] = 0x24,
361 [UART_MSR] = 0x28,
362 [UART_SCR] = 0x2c
363 },
364 regmap_out[8] = {
365 [UART_TX] = 0x04,
366 [UART_IER] = 0x0c,
367 [UART_FCR] = 0x18,
368 [UART_LCR] = 0x1c,
369 [UART_MCR] = 0x20,
370 [UART_LSR] = 0x24,
371 [UART_MSR] = 0x28,
372 [UART_SCR] = 0x2c
373 };
374
375static inline int map_8250_in_reg(struct uart_port *p, int offset)
376{
377 if (p->iotype != UPIO_RM9000)
378 return offset;
379 return regmap_in[offset];
380}
381
382static inline int map_8250_out_reg(struct uart_port *p, int offset)
383{
384 if (p->iotype != UPIO_RM9000)
385 return offset;
386 return regmap_out[offset];
387}
388
389#else
390
391/* sane hardware needs no mapping */
392#define map_8250_in_reg(up, offset) (offset)
393#define map_8250_out_reg(up, offset) (offset)
394
395#endif
396
397static unsigned int hub6_serial_in(struct uart_port *p, int offset)
398{
399 offset = map_8250_in_reg(p, offset) << p->regshift;
400 outb(p->hub6 - 1 + offset, p->iobase);
401 return inb(p->iobase + 1);
402}
403
404static void hub6_serial_out(struct uart_port *p, int offset, int value)
405{
406 offset = map_8250_out_reg(p, offset) << p->regshift;
407 outb(p->hub6 - 1 + offset, p->iobase);
408 outb(value, p->iobase + 1);
409}
410
411static unsigned int mem_serial_in(struct uart_port *p, int offset)
412{
413 offset = map_8250_in_reg(p, offset) << p->regshift;
414 return readb(p->membase + offset);
415}
416
417static void mem_serial_out(struct uart_port *p, int offset, int value)
418{
419 offset = map_8250_out_reg(p, offset) << p->regshift;
420 writeb(value, p->membase + offset);
421}
422
423static void mem32_serial_out(struct uart_port *p, int offset, int value)
424{
425 offset = map_8250_out_reg(p, offset) << p->regshift;
426 writel(value, p->membase + offset);
427}
428
429static unsigned int mem32_serial_in(struct uart_port *p, int offset)
430{
431 offset = map_8250_in_reg(p, offset) << p->regshift;
432 return readl(p->membase + offset);
433}
434
435static unsigned int au_serial_in(struct uart_port *p, int offset)
436{
437 offset = map_8250_in_reg(p, offset) << p->regshift;
438 return __raw_readl(p->membase + offset);
439}
440
441static void au_serial_out(struct uart_port *p, int offset, int value)
442{
443 offset = map_8250_out_reg(p, offset) << p->regshift;
444 __raw_writel(value, p->membase + offset);
445}
446
447static unsigned int tsi_serial_in(struct uart_port *p, int offset)
448{
449 unsigned int tmp;
450 offset = map_8250_in_reg(p, offset) << p->regshift;
451 if (offset == UART_IIR) {
452 tmp = readl(p->membase + (UART_IIR & ~3));
453 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
454 } else
455 return readb(p->membase + offset);
456}
457
458static void tsi_serial_out(struct uart_port *p, int offset, int value)
459{
460 offset = map_8250_out_reg(p, offset) << p->regshift;
461 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
462 writeb(value, p->membase + offset);
463}
464
465/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
466static inline void dwapb_save_out_value(struct uart_port *p, int offset,
467 int value)
468{
469 struct uart_8250_port *up =
470 container_of(p, struct uart_8250_port, port);
471
472 if (offset == UART_LCR)
473 up->lcr = value;
474}
475
476/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
477static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
478{
479 if (offset == UART_TX || offset == UART_IER)
480 p->serial_in(p, UART_IER);
481}
482
483static void dwapb_serial_out(struct uart_port *p, int offset, int value)
484{
485 int save_offset = offset;
486 offset = map_8250_out_reg(p, offset) << p->regshift;
487 dwapb_save_out_value(p, save_offset, value);
488 writeb(value, p->membase + offset);
489 dwapb_check_clear_ier(p, save_offset);
490}
491
492static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
493{
494 int save_offset = offset;
495 offset = map_8250_out_reg(p, offset) << p->regshift;
496 dwapb_save_out_value(p, save_offset, value);
497 writel(value, p->membase + offset);
498 dwapb_check_clear_ier(p, save_offset);
499}
500
501static unsigned int io_serial_in(struct uart_port *p, int offset)
502{
503 offset = map_8250_in_reg(p, offset) << p->regshift;
504 return inb(p->iobase + offset);
505}
506
507static void io_serial_out(struct uart_port *p, int offset, int value)
508{
509 offset = map_8250_out_reg(p, offset) << p->regshift;
510 outb(value, p->iobase + offset);
511}
512
513static void set_io_from_upio(struct uart_port *p)
514{
515 struct uart_8250_port *up =
516 container_of(p, struct uart_8250_port, port);
517 switch (p->iotype) {
518 case UPIO_HUB6:
519 p->serial_in = hub6_serial_in;
520 p->serial_out = hub6_serial_out;
521 break;
522
523 case UPIO_MEM:
524 p->serial_in = mem_serial_in;
525 p->serial_out = mem_serial_out;
526 break;
527
528 case UPIO_RM9000:
529 case UPIO_MEM32:
530 p->serial_in = mem32_serial_in;
531 p->serial_out = mem32_serial_out;
532 break;
533
534 case UPIO_AU:
535 p->serial_in = au_serial_in;
536 p->serial_out = au_serial_out;
537 break;
538
539 case UPIO_TSI:
540 p->serial_in = tsi_serial_in;
541 p->serial_out = tsi_serial_out;
542 break;
543
544 case UPIO_DWAPB:
545 p->serial_in = mem_serial_in;
546 p->serial_out = dwapb_serial_out;
547 break;
548
549 case UPIO_DWAPB32:
550 p->serial_in = mem32_serial_in;
551 p->serial_out = dwapb32_serial_out;
552 break;
553
554 default:
555 p->serial_in = io_serial_in;
556 p->serial_out = io_serial_out;
557 break;
558 }
559 /* Remember loaded iotype */
560 up->cur_iotype = p->iotype;
561}
562
563static void
564serial_out_sync(struct uart_8250_port *up, int offset, int value)
565{
566 struct uart_port *p = &up->port;
567 switch (p->iotype) {
568 case UPIO_MEM:
569 case UPIO_MEM32:
570 case UPIO_AU:
571 case UPIO_DWAPB:
572 case UPIO_DWAPB32:
573 p->serial_out(p, offset, value);
574 p->serial_in(p, UART_LCR); /* safe, no side-effects */
575 break;
576 default:
577 p->serial_out(p, offset, value);
578 }
579}
580
581#define serial_in(up, offset) \
582 (up->port.serial_in(&(up)->port, (offset)))
583#define serial_out(up, offset, value) \
584 (up->port.serial_out(&(up)->port, (offset), (value)))
585/*
586 * We used to support using pause I/O for certain machines. We
587 * haven't supported this for a while, but just in case it's badly
588 * needed for certain old 386 machines, I've left these #define's
589 * in....
590 */
591#define serial_inp(up, offset) serial_in(up, offset)
592#define serial_outp(up, offset, value) serial_out(up, offset, value)
593
594/* Uart divisor latch read */
595static inline int _serial_dl_read(struct uart_8250_port *up)
596{
597 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
598}
599
600/* Uart divisor latch write */
601static inline void _serial_dl_write(struct uart_8250_port *up, int value)
602{
603 serial_outp(up, UART_DLL, value & 0xff);
604 serial_outp(up, UART_DLM, value >> 8 & 0xff);
605}
606
607#if defined(CONFIG_MIPS_ALCHEMY)
608/* Au1x00 haven't got a standard divisor latch */
609static int serial_dl_read(struct uart_8250_port *up)
610{
611 if (up->port.iotype == UPIO_AU)
612 return __raw_readl(up->port.membase + 0x28);
613 else
614 return _serial_dl_read(up);
615}
616
617static void serial_dl_write(struct uart_8250_port *up, int value)
618{
619 if (up->port.iotype == UPIO_AU)
620 __raw_writel(value, up->port.membase + 0x28);
621 else
622 _serial_dl_write(up, value);
623}
624#elif defined(CONFIG_SERIAL_8250_RM9K)
625static int serial_dl_read(struct uart_8250_port *up)
626{
627 return (up->port.iotype == UPIO_RM9000) ?
628 (((__raw_readl(up->port.membase + 0x10) << 8) |
629 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
630 _serial_dl_read(up);
631}
632
633static void serial_dl_write(struct uart_8250_port *up, int value)
634{
635 if (up->port.iotype == UPIO_RM9000) {
636 __raw_writel(value, up->port.membase + 0x08);
637 __raw_writel(value >> 8, up->port.membase + 0x10);
638 } else {
639 _serial_dl_write(up, value);
640 }
641}
642#else
643#define serial_dl_read(up) _serial_dl_read(up)
644#define serial_dl_write(up, value) _serial_dl_write(up, value)
645#endif
646
647/*
648 * For the 16C950
649 */
650static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
651{
652 serial_out(up, UART_SCR, offset);
653 serial_out(up, UART_ICR, value);
654}
655
656static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
657{
658 unsigned int value;
659
660 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
661 serial_out(up, UART_SCR, offset);
662 value = serial_in(up, UART_ICR);
663 serial_icr_write(up, UART_ACR, up->acr);
664
665 return value;
666}
667
668/*
669 * FIFO support.
670 */
671static void serial8250_clear_fifos(struct uart_8250_port *p)
672{
673 if (p->capabilities & UART_CAP_FIFO) {
674 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
675 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
676 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
677 serial_outp(p, UART_FCR, 0);
678 }
679}
680
681/*
682 * IER sleep support. UARTs which have EFRs need the "extended
683 * capability" bit enabled. Note that on XR16C850s, we need to
684 * reset LCR to write to IER.
685 */
686static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
687{
688 if (p->capabilities & UART_CAP_SLEEP) {
689 if (p->capabilities & UART_CAP_EFR) {
690 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
691 serial_outp(p, UART_EFR, UART_EFR_ECB);
692 serial_outp(p, UART_LCR, 0);
693 }
694 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
695 if (p->capabilities & UART_CAP_EFR) {
696 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
697 serial_outp(p, UART_EFR, 0);
698 serial_outp(p, UART_LCR, 0);
699 }
700 }
701}
702
703#ifdef CONFIG_SERIAL_8250_RSA
704/*
705 * Attempts to turn on the RSA FIFO. Returns zero on failure.
706 * We set the port uart clock rate if we succeed.
707 */
708static int __enable_rsa(struct uart_8250_port *up)
709{
710 unsigned char mode;
711 int result;
712
713 mode = serial_inp(up, UART_RSA_MSR);
714 result = mode & UART_RSA_MSR_FIFO;
715
716 if (!result) {
717 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
718 mode = serial_inp(up, UART_RSA_MSR);
719 result = mode & UART_RSA_MSR_FIFO;
720 }
721
722 if (result)
723 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
724
725 return result;
726}
727
728static void enable_rsa(struct uart_8250_port *up)
729{
730 if (up->port.type == PORT_RSA) {
731 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
732 spin_lock_irq(&up->port.lock);
733 __enable_rsa(up);
734 spin_unlock_irq(&up->port.lock);
735 }
736 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
737 serial_outp(up, UART_RSA_FRR, 0);
738 }
739}
740
741/*
742 * Attempts to turn off the RSA FIFO. Returns zero on failure.
743 * It is unknown why interrupts were disabled in here. However,
744 * the caller is expected to preserve this behaviour by grabbing
745 * the spinlock before calling this function.
746 */
747static void disable_rsa(struct uart_8250_port *up)
748{
749 unsigned char mode;
750 int result;
751
752 if (up->port.type == PORT_RSA &&
753 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
754 spin_lock_irq(&up->port.lock);
755
756 mode = serial_inp(up, UART_RSA_MSR);
757 result = !(mode & UART_RSA_MSR_FIFO);
758
759 if (!result) {
760 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
761 mode = serial_inp(up, UART_RSA_MSR);
762 result = !(mode & UART_RSA_MSR_FIFO);
763 }
764
765 if (result)
766 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
767 spin_unlock_irq(&up->port.lock);
768 }
769}
770#endif /* CONFIG_SERIAL_8250_RSA */
771
772/*
773 * This is a quickie test to see how big the FIFO is.
774 * It doesn't work at all the time, more's the pity.
775 */
776static int size_fifo(struct uart_8250_port *up)
777{
778 unsigned char old_fcr, old_mcr, old_lcr;
779 unsigned short old_dl;
780 int count;
781
782 old_lcr = serial_inp(up, UART_LCR);
783 serial_outp(up, UART_LCR, 0);
784 old_fcr = serial_inp(up, UART_FCR);
785 old_mcr = serial_inp(up, UART_MCR);
786 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
787 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
788 serial_outp(up, UART_MCR, UART_MCR_LOOP);
789 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
790 old_dl = serial_dl_read(up);
791 serial_dl_write(up, 0x0001);
792 serial_outp(up, UART_LCR, 0x03);
793 for (count = 0; count < 256; count++)
794 serial_outp(up, UART_TX, count);
795 mdelay(20);/* FIXME - schedule_timeout */
796 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
797 (count < 256); count++)
798 serial_inp(up, UART_RX);
799 serial_outp(up, UART_FCR, old_fcr);
800 serial_outp(up, UART_MCR, old_mcr);
801 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
802 serial_dl_write(up, old_dl);
803 serial_outp(up, UART_LCR, old_lcr);
804
805 return count;
806}
807
808/*
809 * Read UART ID using the divisor method - set DLL and DLM to zero
810 * and the revision will be in DLL and device type in DLM. We
811 * preserve the device state across this.
812 */
813static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
814{
815 unsigned char old_dll, old_dlm, old_lcr;
816 unsigned int id;
817
818 old_lcr = serial_inp(p, UART_LCR);
819 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
820
821 old_dll = serial_inp(p, UART_DLL);
822 old_dlm = serial_inp(p, UART_DLM);
823
824 serial_outp(p, UART_DLL, 0);
825 serial_outp(p, UART_DLM, 0);
826
827 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
828
829 serial_outp(p, UART_DLL, old_dll);
830 serial_outp(p, UART_DLM, old_dlm);
831 serial_outp(p, UART_LCR, old_lcr);
832
833 return id;
834}
835
836/*
837 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
838 * When this function is called we know it is at least a StarTech
839 * 16650 V2, but it might be one of several StarTech UARTs, or one of
840 * its clones. (We treat the broken original StarTech 16650 V1 as a
841 * 16550, and why not? Startech doesn't seem to even acknowledge its
842 * existence.)
843 *
844 * What evil have men's minds wrought...
845 */
846static void autoconfig_has_efr(struct uart_8250_port *up)
847{
848 unsigned int id1, id2, id3, rev;
849
850 /*
851 * Everything with an EFR has SLEEP
852 */
853 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
854
855 /*
856 * First we check to see if it's an Oxford Semiconductor UART.
857 *
858 * If we have to do this here because some non-National
859 * Semiconductor clone chips lock up if you try writing to the
860 * LSR register (which serial_icr_read does)
861 */
862
863 /*
864 * Check for Oxford Semiconductor 16C950.
865 *
866 * EFR [4] must be set else this test fails.
867 *
868 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
869 * claims that it's needed for 952 dual UART's (which are not
870 * recommended for new designs).
871 */
872 up->acr = 0;
873 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
874 serial_out(up, UART_EFR, UART_EFR_ECB);
875 serial_out(up, UART_LCR, 0x00);
876 id1 = serial_icr_read(up, UART_ID1);
877 id2 = serial_icr_read(up, UART_ID2);
878 id3 = serial_icr_read(up, UART_ID3);
879 rev = serial_icr_read(up, UART_REV);
880
881 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
882
883 if (id1 == 0x16 && id2 == 0xC9 &&
884 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
885 up->port.type = PORT_16C950;
886
887 /*
888 * Enable work around for the Oxford Semiconductor 952 rev B
889 * chip which causes it to seriously miscalculate baud rates
890 * when DLL is 0.
891 */
892 if (id3 == 0x52 && rev == 0x01)
893 up->bugs |= UART_BUG_QUOT;
894 return;
895 }
896
897 /*
898 * We check for a XR16C850 by setting DLL and DLM to 0, and then
899 * reading back DLL and DLM. The chip type depends on the DLM
900 * value read back:
901 * 0x10 - XR16C850 and the DLL contains the chip revision.
902 * 0x12 - XR16C2850.
903 * 0x14 - XR16C854.
904 */
905 id1 = autoconfig_read_divisor_id(up);
906 DEBUG_AUTOCONF("850id=%04x ", id1);
907
908 id2 = id1 >> 8;
909 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
910 up->port.type = PORT_16850;
911 return;
912 }
913
914 /*
915 * It wasn't an XR16C850.
916 *
917 * We distinguish between the '654 and the '650 by counting
918 * how many bytes are in the FIFO. I'm using this for now,
919 * since that's the technique that was sent to me in the
920 * serial driver update, but I'm not convinced this works.
921 * I've had problems doing this in the past. -TYT
922 */
923 if (size_fifo(up) == 64)
924 up->port.type = PORT_16654;
925 else
926 up->port.type = PORT_16650V2;
927}
928
929/*
930 * We detected a chip without a FIFO. Only two fall into
931 * this category - the original 8250 and the 16450. The
932 * 16450 has a scratch register (accessible with LCR=0)
933 */
934static void autoconfig_8250(struct uart_8250_port *up)
935{
936 unsigned char scratch, status1, status2;
937
938 up->port.type = PORT_8250;
939
940 scratch = serial_in(up, UART_SCR);
941 serial_outp(up, UART_SCR, 0xa5);
942 status1 = serial_in(up, UART_SCR);
943 serial_outp(up, UART_SCR, 0x5a);
944 status2 = serial_in(up, UART_SCR);
945 serial_outp(up, UART_SCR, scratch);
946
947 if (status1 == 0xa5 && status2 == 0x5a)
948 up->port.type = PORT_16450;
949}
950
951static int broken_efr(struct uart_8250_port *up)
952{
953 /*
954 * Exar ST16C2550 "A2" devices incorrectly detect as
955 * having an EFR, and report an ID of 0x0201. See
956 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
957 */
958 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
959 return 1;
960
961 return 0;
962}
963
964static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
965{
966 unsigned char status;
967
968 status = serial_in(up, 0x04); /* EXCR2 */
969#define PRESL(x) ((x) & 0x30)
970 if (PRESL(status) == 0x10) {
971 /* already in high speed mode */
972 return 0;
973 } else {
974 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
975 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
976 serial_outp(up, 0x04, status);
977 }
978 return 1;
979}
980
981/*
982 * We know that the chip has FIFOs. Does it have an EFR? The
983 * EFR is located in the same register position as the IIR and
984 * we know the top two bits of the IIR are currently set. The
985 * EFR should contain zero. Try to read the EFR.
986 */
987static void autoconfig_16550a(struct uart_8250_port *up)
988{
989 unsigned char status1, status2;
990 unsigned int iersave;
991
992 up->port.type = PORT_16550A;
993 up->capabilities |= UART_CAP_FIFO;
994
995 /*
996 * Check for presence of the EFR when DLAB is set.
997 * Only ST16C650V1 UARTs pass this test.
998 */
999 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1000 if (serial_in(up, UART_EFR) == 0) {
1001 serial_outp(up, UART_EFR, 0xA8);
1002 if (serial_in(up, UART_EFR) != 0) {
1003 DEBUG_AUTOCONF("EFRv1 ");
1004 up->port.type = PORT_16650;
1005 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1006 } else {
1007 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1008 }
1009 serial_outp(up, UART_EFR, 0);
1010 return;
1011 }
1012
1013 /*
1014 * Maybe it requires 0xbf to be written to the LCR.
1015 * (other ST16C650V2 UARTs, TI16C752A, etc)
1016 */
1017 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1018 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1019 DEBUG_AUTOCONF("EFRv2 ");
1020 autoconfig_has_efr(up);
1021 return;
1022 }
1023
1024 /*
1025 * Check for a National Semiconductor SuperIO chip.
1026 * Attempt to switch to bank 2, read the value of the LOOP bit
1027 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1028 * switch back to bank 2, read it from EXCR1 again and check
1029 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1030 */
1031 serial_outp(up, UART_LCR, 0);
1032 status1 = serial_in(up, UART_MCR);
1033 serial_outp(up, UART_LCR, 0xE0);
1034 status2 = serial_in(up, 0x02); /* EXCR1 */
1035
1036 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1037 serial_outp(up, UART_LCR, 0);
1038 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1039 serial_outp(up, UART_LCR, 0xE0);
1040 status2 = serial_in(up, 0x02); /* EXCR1 */
1041 serial_outp(up, UART_LCR, 0);
1042 serial_outp(up, UART_MCR, status1);
1043
1044 if ((status2 ^ status1) & UART_MCR_LOOP) {
1045 unsigned short quot;
1046
1047 serial_outp(up, UART_LCR, 0xE0);
1048
1049 quot = serial_dl_read(up);
1050 quot <<= 3;
1051
1052 if (ns16550a_goto_highspeed(up))
1053 serial_dl_write(up, quot);
1054
1055 serial_outp(up, UART_LCR, 0);
1056
1057 up->port.uartclk = 921600*16;
1058 up->port.type = PORT_NS16550A;
1059 up->capabilities |= UART_NATSEMI;
1060 return;
1061 }
1062 }
1063
1064 /*
1065 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1066 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1067 * Try setting it with and without DLAB set. Cheap clones
1068 * set bit 5 without DLAB set.
1069 */
1070 serial_outp(up, UART_LCR, 0);
1071 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1072 status1 = serial_in(up, UART_IIR) >> 5;
1073 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1074 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1075 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1076 status2 = serial_in(up, UART_IIR) >> 5;
1077 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1078 serial_outp(up, UART_LCR, 0);
1079
1080 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1081
1082 if (status1 == 6 && status2 == 7) {
1083 up->port.type = PORT_16750;
1084 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1085 return;
1086 }
1087
1088 /*
1089 * Try writing and reading the UART_IER_UUE bit (b6).
1090 * If it works, this is probably one of the Xscale platform's
1091 * internal UARTs.
1092 * We're going to explicitly set the UUE bit to 0 before
1093 * trying to write and read a 1 just to make sure it's not
1094 * already a 1 and maybe locked there before we even start start.
1095 */
1096 iersave = serial_in(up, UART_IER);
1097 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1098 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1099 /*
1100 * OK it's in a known zero state, try writing and reading
1101 * without disturbing the current state of the other bits.
1102 */
1103 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1104 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1105 /*
1106 * It's an Xscale.
1107 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1108 */
1109 DEBUG_AUTOCONF("Xscale ");
1110 up->port.type = PORT_XSCALE;
1111 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1112 return;
1113 }
1114 } else {
1115 /*
1116 * If we got here we couldn't force the IER_UUE bit to 0.
1117 * Log it and continue.
1118 */
1119 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1120 }
1121 serial_outp(up, UART_IER, iersave);
1122
1123 /*
1124 * We distinguish between 16550A and U6 16550A by counting
1125 * how many bytes are in the FIFO.
1126 */
1127 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1128 up->port.type = PORT_U6_16550A;
1129 up->capabilities |= UART_CAP_AFE;
1130 }
1131}
1132
1133/*
1134 * This routine is called by rs_init() to initialize a specific serial
1135 * port. It determines what type of UART chip this serial port is
1136 * using: 8250, 16450, 16550, 16550A. The important question is
1137 * whether or not this UART is a 16550A or not, since this will
1138 * determine whether or not we can use its FIFO features or not.
1139 */
1140static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1141{
1142 unsigned char status1, scratch, scratch2, scratch3;
1143 unsigned char save_lcr, save_mcr;
1144 unsigned long flags;
1145
1146 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1147 return;
1148
1149 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1150 serial_index(&up->port), up->port.iobase, up->port.membase);
1151
1152 /*
1153 * We really do need global IRQs disabled here - we're going to
1154 * be frobbing the chips IRQ enable register to see if it exists.
1155 */
1156 spin_lock_irqsave(&up->port.lock, flags);
1157
1158 up->capabilities = 0;
1159 up->bugs = 0;
1160
1161 if (!(up->port.flags & UPF_BUGGY_UART)) {
1162 /*
1163 * Do a simple existence test first; if we fail this,
1164 * there's no point trying anything else.
1165 *
1166 * 0x80 is used as a nonsense port to prevent against
1167 * false positives due to ISA bus float. The
1168 * assumption is that 0x80 is a non-existent port;
1169 * which should be safe since include/asm/io.h also
1170 * makes this assumption.
1171 *
1172 * Note: this is safe as long as MCR bit 4 is clear
1173 * and the device is in "PC" mode.
1174 */
1175 scratch = serial_inp(up, UART_IER);
1176 serial_outp(up, UART_IER, 0);
1177#ifdef __i386__
1178 outb(0xff, 0x080);
1179#endif
1180 /*
1181 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1182 * 16C754B) allow only to modify them if an EFR bit is set.
1183 */
1184 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1185 serial_outp(up, UART_IER, 0x0F);
1186#ifdef __i386__
1187 outb(0, 0x080);
1188#endif
1189 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1190 serial_outp(up, UART_IER, scratch);
1191 if (scratch2 != 0 || scratch3 != 0x0F) {
1192 /*
1193 * We failed; there's nothing here
1194 */
1195 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1196 scratch2, scratch3);
1197 goto out;
1198 }
1199 }
1200
1201 save_mcr = serial_in(up, UART_MCR);
1202 save_lcr = serial_in(up, UART_LCR);
1203
1204 /*
1205 * Check to see if a UART is really there. Certain broken
1206 * internal modems based on the Rockwell chipset fail this
1207 * test, because they apparently don't implement the loopback
1208 * test mode. So this test is skipped on the COM 1 through
1209 * COM 4 ports. This *should* be safe, since no board
1210 * manufacturer would be stupid enough to design a board
1211 * that conflicts with COM 1-4 --- we hope!
1212 */
1213 if (!(up->port.flags & UPF_SKIP_TEST)) {
1214 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1215 status1 = serial_inp(up, UART_MSR) & 0xF0;
1216 serial_outp(up, UART_MCR, save_mcr);
1217 if (status1 != 0x90) {
1218 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1219 status1);
1220 goto out;
1221 }
1222 }
1223
1224 /*
1225 * We're pretty sure there's a port here. Lets find out what
1226 * type of port it is. The IIR top two bits allows us to find
1227 * out if it's 8250 or 16450, 16550, 16550A or later. This
1228 * determines what we test for next.
1229 *
1230 * We also initialise the EFR (if any) to zero for later. The
1231 * EFR occupies the same register location as the FCR and IIR.
1232 */
1233 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1234 serial_outp(up, UART_EFR, 0);
1235 serial_outp(up, UART_LCR, 0);
1236
1237 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1238 scratch = serial_in(up, UART_IIR) >> 6;
1239
1240 DEBUG_AUTOCONF("iir=%d ", scratch);
1241
1242 switch (scratch) {
1243 case 0:
1244 autoconfig_8250(up);
1245 break;
1246 case 1:
1247 up->port.type = PORT_UNKNOWN;
1248 break;
1249 case 2:
1250 up->port.type = PORT_16550;
1251 break;
1252 case 3:
1253 autoconfig_16550a(up);
1254 break;
1255 }
1256
1257#ifdef CONFIG_SERIAL_8250_RSA
1258 /*
1259 * Only probe for RSA ports if we got the region.
1260 */
1261 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1262 int i;
1263
1264 for (i = 0 ; i < probe_rsa_count; ++i) {
1265 if (probe_rsa[i] == up->port.iobase &&
1266 __enable_rsa(up)) {
1267 up->port.type = PORT_RSA;
1268 break;
1269 }
1270 }
1271 }
1272#endif
1273
1274 serial_outp(up, UART_LCR, save_lcr);
1275
1276 if (up->capabilities != uart_config[up->port.type].flags) {
1277 printk(KERN_WARNING
1278 "ttyS%d: detected caps %08x should be %08x\n",
1279 serial_index(&up->port), up->capabilities,
1280 uart_config[up->port.type].flags);
1281 }
1282
1283 up->port.fifosize = uart_config[up->port.type].fifo_size;
1284 up->capabilities = uart_config[up->port.type].flags;
1285 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1286
1287 if (up->port.type == PORT_UNKNOWN)
1288 goto out;
1289
1290 /*
1291 * Reset the UART.
1292 */
1293#ifdef CONFIG_SERIAL_8250_RSA
1294 if (up->port.type == PORT_RSA)
1295 serial_outp(up, UART_RSA_FRR, 0);
1296#endif
1297 serial_outp(up, UART_MCR, save_mcr);
1298 serial8250_clear_fifos(up);
1299 serial_in(up, UART_RX);
1300 if (up->capabilities & UART_CAP_UUE)
1301 serial_outp(up, UART_IER, UART_IER_UUE);
1302 else
1303 serial_outp(up, UART_IER, 0);
1304
1305 out:
1306 spin_unlock_irqrestore(&up->port.lock, flags);
1307 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1308}
1309
1310static void autoconfig_irq(struct uart_8250_port *up)
1311{
1312 unsigned char save_mcr, save_ier;
1313 unsigned char save_ICP = 0;
1314 unsigned int ICP = 0;
1315 unsigned long irqs;
1316 int irq;
1317
1318 if (up->port.flags & UPF_FOURPORT) {
1319 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1320 save_ICP = inb_p(ICP);
1321 outb_p(0x80, ICP);
1322 (void) inb_p(ICP);
1323 }
1324
1325 /* forget possible initially masked and pending IRQ */
1326 probe_irq_off(probe_irq_on());
1327 save_mcr = serial_inp(up, UART_MCR);
1328 save_ier = serial_inp(up, UART_IER);
1329 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1330
1331 irqs = probe_irq_on();
1332 serial_outp(up, UART_MCR, 0);
1333 udelay(10);
1334 if (up->port.flags & UPF_FOURPORT) {
1335 serial_outp(up, UART_MCR,
1336 UART_MCR_DTR | UART_MCR_RTS);
1337 } else {
1338 serial_outp(up, UART_MCR,
1339 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1340 }
1341 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1342 (void)serial_inp(up, UART_LSR);
1343 (void)serial_inp(up, UART_RX);
1344 (void)serial_inp(up, UART_IIR);
1345 (void)serial_inp(up, UART_MSR);
1346 serial_outp(up, UART_TX, 0xFF);
1347 udelay(20);
1348 irq = probe_irq_off(irqs);
1349
1350 serial_outp(up, UART_MCR, save_mcr);
1351 serial_outp(up, UART_IER, save_ier);
1352
1353 if (up->port.flags & UPF_FOURPORT)
1354 outb_p(save_ICP, ICP);
1355
1356 up->port.irq = (irq > 0) ? irq : 0;
1357}
1358
1359static inline void __stop_tx(struct uart_8250_port *p)
1360{
1361 if (p->ier & UART_IER_THRI) {
1362 p->ier &= ~UART_IER_THRI;
1363 serial_out(p, UART_IER, p->ier);
1364 }
1365}
1366
1367static void serial8250_stop_tx(struct uart_port *port)
1368{
1369 struct uart_8250_port *up =
1370 container_of(port, struct uart_8250_port, port);
1371
1372 __stop_tx(up);
1373
1374 /*
1375 * We really want to stop the transmitter from sending.
1376 */
1377 if (up->port.type == PORT_16C950) {
1378 up->acr |= UART_ACR_TXDIS;
1379 serial_icr_write(up, UART_ACR, up->acr);
1380 }
1381}
1382
1383static void transmit_chars(struct uart_8250_port *up);
1384
1385static void serial8250_start_tx(struct uart_port *port)
1386{
1387 struct uart_8250_port *up =
1388 container_of(port, struct uart_8250_port, port);
1389
1390 if (!(up->ier & UART_IER_THRI)) {
1391 up->ier |= UART_IER_THRI;
1392 serial_out(up, UART_IER, up->ier);
1393
1394 if (up->bugs & UART_BUG_TXEN) {
1395 unsigned char lsr;
1396 lsr = serial_in(up, UART_LSR);
1397 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1398 if ((up->port.type == PORT_RM9000) ?
1399 (lsr & UART_LSR_THRE) :
1400 (lsr & UART_LSR_TEMT))
1401 transmit_chars(up);
1402 }
1403 }
1404
1405 /*
1406 * Re-enable the transmitter if we disabled it.
1407 */
1408 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1409 up->acr &= ~UART_ACR_TXDIS;
1410 serial_icr_write(up, UART_ACR, up->acr);
1411 }
1412}
1413
1414static void serial8250_stop_rx(struct uart_port *port)
1415{
1416 struct uart_8250_port *up =
1417 container_of(port, struct uart_8250_port, port);
1418
1419 up->ier &= ~UART_IER_RLSI;
1420 up->port.read_status_mask &= ~UART_LSR_DR;
1421 serial_out(up, UART_IER, up->ier);
1422}
1423
1424static void serial8250_enable_ms(struct uart_port *port)
1425{
1426 struct uart_8250_port *up =
1427 container_of(port, struct uart_8250_port, port);
1428
1429 /* no MSR capabilities */
1430 if (up->bugs & UART_BUG_NOMSR)
1431 return;
1432
1433 up->ier |= UART_IER_MSI;
1434 serial_out(up, UART_IER, up->ier);
1435}
1436
1437/*
1438 * Clear the Tegra rx fifo after a break
1439 *
1440 * FIXME: This needs to become a port specific callback once we have a
1441 * framework for this
1442 */
1443static void clear_rx_fifo(struct uart_8250_port *up)
1444{
1445 unsigned int status, tmout = 10000;
1446 do {
1447 status = serial_in(up, UART_LSR);
1448 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1449 status = serial_in(up, UART_RX);
1450 else
1451 break;
1452 if (--tmout == 0)
1453 break;
1454 udelay(1);
1455 } while (1);
1456}
1457
1458static void
1459receive_chars(struct uart_8250_port *up, unsigned int *status)
1460{
1461 struct tty_struct *tty = up->port.state->port.tty;
1462 unsigned char ch, lsr = *status;
1463 int max_count = 256;
1464 char flag;
1465
1466 do {
1467 if (likely(lsr & UART_LSR_DR))
1468 ch = serial_inp(up, UART_RX);
1469 else
1470 /*
1471 * Intel 82571 has a Serial Over Lan device that will
1472 * set UART_LSR_BI without setting UART_LSR_DR when
1473 * it receives a break. To avoid reading from the
1474 * receive buffer without UART_LSR_DR bit set, we
1475 * just force the read character to be 0
1476 */
1477 ch = 0;
1478
1479 flag = TTY_NORMAL;
1480 up->port.icount.rx++;
1481
1482 lsr |= up->lsr_saved_flags;
1483 up->lsr_saved_flags = 0;
1484
1485 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1486 /*
1487 * For statistics only
1488 */
1489 if (lsr & UART_LSR_BI) {
1490 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1491 up->port.icount.brk++;
1492 /*
1493 * If tegra port then clear the rx fifo to
1494 * accept another break/character.
1495 */
1496 if (up->port.type == PORT_TEGRA)
1497 clear_rx_fifo(up);
1498
1499 /*
1500 * We do the SysRQ and SAK checking
1501 * here because otherwise the break
1502 * may get masked by ignore_status_mask
1503 * or read_status_mask.
1504 */
1505 if (uart_handle_break(&up->port))
1506 goto ignore_char;
1507 } else if (lsr & UART_LSR_PE)
1508 up->port.icount.parity++;
1509 else if (lsr & UART_LSR_FE)
1510 up->port.icount.frame++;
1511 if (lsr & UART_LSR_OE)
1512 up->port.icount.overrun++;
1513
1514 /*
1515 * Mask off conditions which should be ignored.
1516 */
1517 lsr &= up->port.read_status_mask;
1518
1519 if (lsr & UART_LSR_BI) {
1520 DEBUG_INTR("handling break....");
1521 flag = TTY_BREAK;
1522 } else if (lsr & UART_LSR_PE)
1523 flag = TTY_PARITY;
1524 else if (lsr & UART_LSR_FE)
1525 flag = TTY_FRAME;
1526 }
1527 if (uart_handle_sysrq_char(&up->port, ch))
1528 goto ignore_char;
1529
1530 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1531
1532ignore_char:
1533 lsr = serial_inp(up, UART_LSR);
1534 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1535 spin_unlock(&up->port.lock);
1536 tty_flip_buffer_push(tty);
1537 spin_lock(&up->port.lock);
1538 *status = lsr;
1539}
1540
1541static void transmit_chars(struct uart_8250_port *up)
1542{
1543 struct circ_buf *xmit = &up->port.state->xmit;
1544 int count;
1545
1546 if (up->port.x_char) {
1547 serial_outp(up, UART_TX, up->port.x_char);
1548 up->port.icount.tx++;
1549 up->port.x_char = 0;
1550 return;
1551 }
1552 if (uart_tx_stopped(&up->port)) {
1553 serial8250_stop_tx(&up->port);
1554 return;
1555 }
1556 if (uart_circ_empty(xmit)) {
1557 __stop_tx(up);
1558 return;
1559 }
1560
1561 count = up->tx_loadsz;
1562 do {
1563 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1564 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1565 up->port.icount.tx++;
1566 if (uart_circ_empty(xmit))
1567 break;
1568 } while (--count > 0);
1569
1570 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1571 uart_write_wakeup(&up->port);
1572
1573 DEBUG_INTR("THRE...");
1574
1575 if (uart_circ_empty(xmit))
1576 __stop_tx(up);
1577}
1578
1579static unsigned int check_modem_status(struct uart_8250_port *up)
1580{
1581 unsigned int status = serial_in(up, UART_MSR);
1582
1583 status |= up->msr_saved_flags;
1584 up->msr_saved_flags = 0;
1585 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1586 up->port.state != NULL) {
1587 if (status & UART_MSR_TERI)
1588 up->port.icount.rng++;
1589 if (status & UART_MSR_DDSR)
1590 up->port.icount.dsr++;
1591 if (status & UART_MSR_DDCD)
1592 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1593 if (status & UART_MSR_DCTS)
1594 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1595
1596 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1597 }
1598
1599 return status;
1600}
1601
1602/*
1603 * This handles the interrupt from one port.
1604 */
1605static void serial8250_handle_port(struct uart_8250_port *up)
1606{
1607 unsigned int status;
1608 unsigned long flags;
1609
1610 spin_lock_irqsave(&up->port.lock, flags);
1611
1612 status = serial_inp(up, UART_LSR);
1613
1614 DEBUG_INTR("status = %x...", status);
1615
1616 if (status & (UART_LSR_DR | UART_LSR_BI))
1617 receive_chars(up, &status);
1618 check_modem_status(up);
1619 if (status & UART_LSR_THRE)
1620 transmit_chars(up);
1621
1622 spin_unlock_irqrestore(&up->port.lock, flags);
1623}
1624
1625/*
1626 * This is the serial driver's interrupt routine.
1627 *
1628 * Arjan thinks the old way was overly complex, so it got simplified.
1629 * Alan disagrees, saying that need the complexity to handle the weird
1630 * nature of ISA shared interrupts. (This is a special exception.)
1631 *
1632 * In order to handle ISA shared interrupts properly, we need to check
1633 * that all ports have been serviced, and therefore the ISA interrupt
1634 * line has been de-asserted.
1635 *
1636 * This means we need to loop through all ports. checking that they
1637 * don't have an interrupt pending.
1638 */
1639static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1640{
1641 struct irq_info *i = dev_id;
1642 struct list_head *l, *end = NULL;
1643 int pass_counter = 0, handled = 0;
1644
1645 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1646
1647 spin_lock(&i->lock);
1648
1649 l = i->head;
1650 do {
1651 struct uart_8250_port *up;
1652 unsigned int iir;
1653
1654 up = list_entry(l, struct uart_8250_port, list);
1655
1656 iir = serial_in(up, UART_IIR);
1657 if (!(iir & UART_IIR_NO_INT)) {
1658 serial8250_handle_port(up);
1659
1660 handled = 1;
1661
1662 end = NULL;
1663 } else if ((up->port.iotype == UPIO_DWAPB ||
1664 up->port.iotype == UPIO_DWAPB32) &&
1665 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1666 /* The DesignWare APB UART has an Busy Detect (0x07)
1667 * interrupt meaning an LCR write attempt occurred while the
1668 * UART was busy. The interrupt must be cleared by reading
1669 * the UART status register (USR) and the LCR re-written. */
1670 unsigned int status;
1671 status = *(volatile u32 *)up->port.private_data;
1672 serial_out(up, UART_LCR, up->lcr);
1673
1674 handled = 1;
1675
1676 end = NULL;
1677 } else if (end == NULL)
1678 end = l;
1679
1680 l = l->next;
1681
1682 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1683 /* If we hit this, we're dead. */
1684 printk_ratelimited(KERN_ERR
1685 "serial8250: too much work for irq%d\n", irq);
1686 break;
1687 }
1688 } while (l != end);
1689
1690 spin_unlock(&i->lock);
1691
1692 DEBUG_INTR("end.\n");
1693
1694 return IRQ_RETVAL(handled);
1695}
1696
1697/*
1698 * To support ISA shared interrupts, we need to have one interrupt
1699 * handler that ensures that the IRQ line has been deasserted
1700 * before returning. Failing to do this will result in the IRQ
1701 * line being stuck active, and, since ISA irqs are edge triggered,
1702 * no more IRQs will be seen.
1703 */
1704static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1705{
1706 spin_lock_irq(&i->lock);
1707
1708 if (!list_empty(i->head)) {
1709 if (i->head == &up->list)
1710 i->head = i->head->next;
1711 list_del(&up->list);
1712 } else {
1713 BUG_ON(i->head != &up->list);
1714 i->head = NULL;
1715 }
1716 spin_unlock_irq(&i->lock);
1717 /* List empty so throw away the hash node */
1718 if (i->head == NULL) {
1719 hlist_del(&i->node);
1720 kfree(i);
1721 }
1722}
1723
1724static int serial_link_irq_chain(struct uart_8250_port *up)
1725{
1726 struct hlist_head *h;
1727 struct hlist_node *n;
1728 struct irq_info *i;
1729 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1730
1731 mutex_lock(&hash_mutex);
1732
1733 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1734
1735 hlist_for_each(n, h) {
1736 i = hlist_entry(n, struct irq_info, node);
1737 if (i->irq == up->port.irq)
1738 break;
1739 }
1740
1741 if (n == NULL) {
1742 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1743 if (i == NULL) {
1744 mutex_unlock(&hash_mutex);
1745 return -ENOMEM;
1746 }
1747 spin_lock_init(&i->lock);
1748 i->irq = up->port.irq;
1749 hlist_add_head(&i->node, h);
1750 }
1751 mutex_unlock(&hash_mutex);
1752
1753 spin_lock_irq(&i->lock);
1754
1755 if (i->head) {
1756 list_add(&up->list, i->head);
1757 spin_unlock_irq(&i->lock);
1758
1759 ret = 0;
1760 } else {
1761 INIT_LIST_HEAD(&up->list);
1762 i->head = &up->list;
1763 spin_unlock_irq(&i->lock);
1764 irq_flags |= up->port.irqflags;
1765 ret = request_irq(up->port.irq, serial8250_interrupt,
1766 irq_flags, "serial", i);
1767 if (ret < 0)
1768 serial_do_unlink(i, up);
1769 }
1770
1771 return ret;
1772}
1773
1774static void serial_unlink_irq_chain(struct uart_8250_port *up)
1775{
1776 struct irq_info *i;
1777 struct hlist_node *n;
1778 struct hlist_head *h;
1779
1780 mutex_lock(&hash_mutex);
1781
1782 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1783
1784 hlist_for_each(n, h) {
1785 i = hlist_entry(n, struct irq_info, node);
1786 if (i->irq == up->port.irq)
1787 break;
1788 }
1789
1790 BUG_ON(n == NULL);
1791 BUG_ON(i->head == NULL);
1792
1793 if (list_empty(i->head))
1794 free_irq(up->port.irq, i);
1795
1796 serial_do_unlink(i, up);
1797 mutex_unlock(&hash_mutex);
1798}
1799
1800/*
1801 * This function is used to handle ports that do not have an
1802 * interrupt. This doesn't work very well for 16450's, but gives
1803 * barely passable results for a 16550A. (Although at the expense
1804 * of much CPU overhead).
1805 */
1806static void serial8250_timeout(unsigned long data)
1807{
1808 struct uart_8250_port *up = (struct uart_8250_port *)data;
1809 unsigned int iir;
1810
1811 iir = serial_in(up, UART_IIR);
1812 if (!(iir & UART_IIR_NO_INT))
1813 serial8250_handle_port(up);
1814 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1815}
1816
1817static void serial8250_backup_timeout(unsigned long data)
1818{
1819 struct uart_8250_port *up = (struct uart_8250_port *)data;
1820 unsigned int iir, ier = 0, lsr;
1821 unsigned long flags;
1822
1823 spin_lock_irqsave(&up->port.lock, flags);
1824
1825 /*
1826 * Must disable interrupts or else we risk racing with the interrupt
1827 * based handler.
1828 */
1829 if (is_real_interrupt(up->port.irq)) {
1830 ier = serial_in(up, UART_IER);
1831 serial_out(up, UART_IER, 0);
1832 }
1833
1834 iir = serial_in(up, UART_IIR);
1835
1836 /*
1837 * This should be a safe test for anyone who doesn't trust the
1838 * IIR bits on their UART, but it's specifically designed for
1839 * the "Diva" UART used on the management processor on many HP
1840 * ia64 and parisc boxes.
1841 */
1842 lsr = serial_in(up, UART_LSR);
1843 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1844 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1845 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1846 (lsr & UART_LSR_THRE)) {
1847 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1848 iir |= UART_IIR_THRI;
1849 }
1850
1851 if (!(iir & UART_IIR_NO_INT))
1852 transmit_chars(up);
1853
1854 if (is_real_interrupt(up->port.irq))
1855 serial_out(up, UART_IER, ier);
1856
1857 spin_unlock_irqrestore(&up->port.lock, flags);
1858
1859 /* Standard timer interval plus 0.2s to keep the port running */
1860 mod_timer(&up->timer,
1861 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1862}
1863
1864static unsigned int serial8250_tx_empty(struct uart_port *port)
1865{
1866 struct uart_8250_port *up =
1867 container_of(port, struct uart_8250_port, port);
1868 unsigned long flags;
1869 unsigned int lsr;
1870
1871 spin_lock_irqsave(&up->port.lock, flags);
1872 lsr = serial_in(up, UART_LSR);
1873 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1874 spin_unlock_irqrestore(&up->port.lock, flags);
1875
1876 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1877}
1878
1879static unsigned int serial8250_get_mctrl(struct uart_port *port)
1880{
1881 struct uart_8250_port *up =
1882 container_of(port, struct uart_8250_port, port);
1883 unsigned int status;
1884 unsigned int ret;
1885
1886 status = check_modem_status(up);
1887
1888 ret = 0;
1889 if (status & UART_MSR_DCD)
1890 ret |= TIOCM_CAR;
1891 if (status & UART_MSR_RI)
1892 ret |= TIOCM_RNG;
1893 if (status & UART_MSR_DSR)
1894 ret |= TIOCM_DSR;
1895 if (status & UART_MSR_CTS)
1896 ret |= TIOCM_CTS;
1897 return ret;
1898}
1899
1900static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1901{
1902 struct uart_8250_port *up =
1903 container_of(port, struct uart_8250_port, port);
1904 unsigned char mcr = 0;
1905
1906 if (up->port.type == PORT_TEGRA) {
1907 if (mctrl & TIOCM_RTS)
1908 mcr |= UART_MCR_HW_RTS;
1909 } else {
1910 if (mctrl & TIOCM_RTS)
1911 mcr |= UART_MCR_RTS;
1912 }
1913 if (mctrl & TIOCM_DTR)
1914 mcr |= UART_MCR_DTR;
1915 if (mctrl & TIOCM_OUT1)
1916 mcr |= UART_MCR_OUT1;
1917 if (mctrl & TIOCM_OUT2)
1918 mcr |= UART_MCR_OUT2;
1919 if (mctrl & TIOCM_LOOP)
1920 mcr |= UART_MCR_LOOP;
1921
1922 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1923
1924 serial_out(up, UART_MCR, mcr);
1925}
1926
1927static void serial8250_break_ctl(struct uart_port *port, int break_state)
1928{
1929 struct uart_8250_port *up =
1930 container_of(port, struct uart_8250_port, port);
1931 unsigned long flags;
1932
1933 spin_lock_irqsave(&up->port.lock, flags);
1934 if (break_state == -1)
1935 up->lcr |= UART_LCR_SBC;
1936 else
1937 up->lcr &= ~UART_LCR_SBC;
1938 serial_out(up, UART_LCR, up->lcr);
1939 spin_unlock_irqrestore(&up->port.lock, flags);
1940}
1941
1942/*
1943 * Wait for transmitter & holding register to empty
1944 */
1945static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1946{
1947 unsigned int status, tmout = 10000;
1948
1949 /* Wait up to 10ms for the character(s) to be sent. */
1950 for (;;) {
1951 status = serial_in(up, UART_LSR);
1952
1953 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1954
1955 if ((status & bits) == bits)
1956 break;
1957 if (--tmout == 0)
1958 break;
1959 udelay(1);
1960 }
1961
1962 /* Wait up to 1s for flow control if necessary */
1963 if (up->port.flags & UPF_CONS_FLOW) {
1964 unsigned int tmout;
1965 for (tmout = 1000000; tmout; tmout--) {
1966 unsigned int msr = serial_in(up, UART_MSR);
1967 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1968 if (msr & UART_MSR_CTS)
1969 break;
1970 udelay(1);
1971 touch_nmi_watchdog();
1972 }
1973 }
1974}
1975
1976#ifdef CONFIG_CONSOLE_POLL
1977/*
1978 * Console polling routines for writing and reading from the uart while
1979 * in an interrupt or debug context.
1980 */
1981
1982static int serial8250_get_poll_char(struct uart_port *port)
1983{
1984 struct uart_8250_port *up =
1985 container_of(port, struct uart_8250_port, port);
1986 unsigned char lsr = serial_inp(up, UART_LSR);
1987
1988 if (!(lsr & UART_LSR_DR))
1989 return NO_POLL_CHAR;
1990
1991 return serial_inp(up, UART_RX);
1992}
1993
1994
1995static void serial8250_put_poll_char(struct uart_port *port,
1996 unsigned char c)
1997{
1998 unsigned int ier;
1999 struct uart_8250_port *up =
2000 container_of(port, struct uart_8250_port, port);
2001
2002 /*
2003 * First save the IER then disable the interrupts
2004 */
2005 ier = serial_in(up, UART_IER);
2006 if (up->capabilities & UART_CAP_UUE)
2007 serial_out(up, UART_IER, UART_IER_UUE);
2008 else
2009 serial_out(up, UART_IER, 0);
2010
2011 wait_for_xmitr(up, BOTH_EMPTY);
2012 /*
2013 * Send the character out.
2014 * If a LF, also do CR...
2015 */
2016 serial_out(up, UART_TX, c);
2017 if (c == 10) {
2018 wait_for_xmitr(up, BOTH_EMPTY);
2019 serial_out(up, UART_TX, 13);
2020 }
2021
2022 /*
2023 * Finally, wait for transmitter to become empty
2024 * and restore the IER
2025 */
2026 wait_for_xmitr(up, BOTH_EMPTY);
2027 serial_out(up, UART_IER, ier);
2028}
2029
2030#endif /* CONFIG_CONSOLE_POLL */
2031
2032static int serial8250_startup(struct uart_port *port)
2033{
2034 struct uart_8250_port *up =
2035 container_of(port, struct uart_8250_port, port);
2036 unsigned long flags;
2037 unsigned char lsr, iir;
2038 int retval;
2039
2040 up->port.fifosize = uart_config[up->port.type].fifo_size;
2041 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
2042 up->capabilities = uart_config[up->port.type].flags;
2043 up->mcr = 0;
2044
2045 if (up->port.iotype != up->cur_iotype)
2046 set_io_from_upio(port);
2047
2048 if (up->port.type == PORT_16C950) {
2049 /* Wake up and initialize UART */
2050 up->acr = 0;
2051 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2052 serial_outp(up, UART_EFR, UART_EFR_ECB);
2053 serial_outp(up, UART_IER, 0);
2054 serial_outp(up, UART_LCR, 0);
2055 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2056 serial_outp(up, UART_LCR, 0xBF);
2057 serial_outp(up, UART_EFR, UART_EFR_ECB);
2058 serial_outp(up, UART_LCR, 0);
2059 }
2060
2061#ifdef CONFIG_SERIAL_8250_RSA
2062 /*
2063 * If this is an RSA port, see if we can kick it up to the
2064 * higher speed clock.
2065 */
2066 enable_rsa(up);
2067#endif
2068
2069 /*
2070 * Clear the FIFO buffers and disable them.
2071 * (they will be reenabled in set_termios())
2072 */
2073 serial8250_clear_fifos(up);
2074
2075 /*
2076 * Clear the interrupt registers.
2077 */
2078 (void) serial_inp(up, UART_LSR);
2079 (void) serial_inp(up, UART_RX);
2080 (void) serial_inp(up, UART_IIR);
2081 (void) serial_inp(up, UART_MSR);
2082
2083 /*
2084 * At this point, there's no way the LSR could still be 0xff;
2085 * if it is, then bail out, because there's likely no UART
2086 * here.
2087 */
2088 if (!(up->port.flags & UPF_BUGGY_UART) &&
2089 (serial_inp(up, UART_LSR) == 0xff)) {
2090 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2091 serial_index(&up->port));
2092 return -ENODEV;
2093 }
2094
2095 /*
2096 * For a XR16C850, we need to set the trigger levels
2097 */
2098 if (up->port.type == PORT_16850) {
2099 unsigned char fctr;
2100
2101 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2102
2103 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2104 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2105 serial_outp(up, UART_TRG, UART_TRG_96);
2106 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2107 serial_outp(up, UART_TRG, UART_TRG_96);
2108
2109 serial_outp(up, UART_LCR, 0);
2110 }
2111
2112 if (is_real_interrupt(up->port.irq)) {
2113 unsigned char iir1;
2114 /*
2115 * Test for UARTs that do not reassert THRE when the
2116 * transmitter is idle and the interrupt has already
2117 * been cleared. Real 16550s should always reassert
2118 * this interrupt whenever the transmitter is idle and
2119 * the interrupt is enabled. Delays are necessary to
2120 * allow register changes to become visible.
2121 */
2122 spin_lock_irqsave(&up->port.lock, flags);
2123 if (up->port.irqflags & IRQF_SHARED)
2124 disable_irq_nosync(up->port.irq);
2125
2126 wait_for_xmitr(up, UART_LSR_THRE);
2127 serial_out_sync(up, UART_IER, UART_IER_THRI);
2128 udelay(1); /* allow THRE to set */
2129 iir1 = serial_in(up, UART_IIR);
2130 serial_out(up, UART_IER, 0);
2131 serial_out_sync(up, UART_IER, UART_IER_THRI);
2132 udelay(1); /* allow a working UART time to re-assert THRE */
2133 iir = serial_in(up, UART_IIR);
2134 serial_out(up, UART_IER, 0);
2135
2136 if (up->port.irqflags & IRQF_SHARED)
2137 enable_irq(up->port.irq);
2138 spin_unlock_irqrestore(&up->port.lock, flags);
2139
2140 /*
2141 * If the interrupt is not reasserted, setup a timer to
2142 * kick the UART on a regular basis.
2143 */
2144 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2145 up->bugs |= UART_BUG_THRE;
2146 pr_debug("ttyS%d - using backup timer\n",
2147 serial_index(port));
2148 }
2149 }
2150
2151 /*
2152 * The above check will only give an accurate result the first time
2153 * the port is opened so this value needs to be preserved.
2154 */
2155 if (up->bugs & UART_BUG_THRE) {
2156 up->timer.function = serial8250_backup_timeout;
2157 up->timer.data = (unsigned long)up;
2158 mod_timer(&up->timer, jiffies +
2159 uart_poll_timeout(port) + HZ / 5);
2160 }
2161
2162 /*
2163 * If the "interrupt" for this port doesn't correspond with any
2164 * hardware interrupt, we use a timer-based system. The original
2165 * driver used to do this with IRQ0.
2166 */
2167 if (!is_real_interrupt(up->port.irq)) {
2168 up->timer.data = (unsigned long)up;
2169 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2170 } else {
2171 retval = serial_link_irq_chain(up);
2172 if (retval)
2173 return retval;
2174 }
2175
2176 /*
2177 * Now, initialize the UART
2178 */
2179 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2180
2181 spin_lock_irqsave(&up->port.lock, flags);
2182 if (up->port.flags & UPF_FOURPORT) {
2183 if (!is_real_interrupt(up->port.irq))
2184 up->port.mctrl |= TIOCM_OUT1;
2185 } else
2186 /*
2187 * Most PC uarts need OUT2 raised to enable interrupts.
2188 */
2189 if (is_real_interrupt(up->port.irq))
2190 up->port.mctrl |= TIOCM_OUT2;
2191
2192 serial8250_set_mctrl(&up->port, up->port.mctrl);
2193
2194 /* Serial over Lan (SoL) hack:
2195 Intel 8257x Gigabit ethernet chips have a
2196 16550 emulation, to be used for Serial Over Lan.
2197 Those chips take a longer time than a normal
2198 serial device to signalize that a transmission
2199 data was queued. Due to that, the above test generally
2200 fails. One solution would be to delay the reading of
2201 iir. However, this is not reliable, since the timeout
2202 is variable. So, let's just don't test if we receive
2203 TX irq. This way, we'll never enable UART_BUG_TXEN.
2204 */
2205 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2206 goto dont_test_tx_en;
2207
2208 /*
2209 * Do a quick test to see if we receive an
2210 * interrupt when we enable the TX irq.
2211 */
2212 serial_outp(up, UART_IER, UART_IER_THRI);
2213 lsr = serial_in(up, UART_LSR);
2214 iir = serial_in(up, UART_IIR);
2215 serial_outp(up, UART_IER, 0);
2216
2217 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2218 if (!(up->bugs & UART_BUG_TXEN)) {
2219 up->bugs |= UART_BUG_TXEN;
2220 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2221 serial_index(port));
2222 }
2223 } else {
2224 up->bugs &= ~UART_BUG_TXEN;
2225 }
2226
2227dont_test_tx_en:
2228 spin_unlock_irqrestore(&up->port.lock, flags);
2229
2230 /*
2231 * Clear the interrupt registers again for luck, and clear the
2232 * saved flags to avoid getting false values from polling
2233 * routines or the previous session.
2234 */
2235 serial_inp(up, UART_LSR);
2236 serial_inp(up, UART_RX);
2237 serial_inp(up, UART_IIR);
2238 serial_inp(up, UART_MSR);
2239 up->lsr_saved_flags = 0;
2240 up->msr_saved_flags = 0;
2241
2242 /*
2243 * Finally, enable interrupts. Note: Modem status interrupts
2244 * are set via set_termios(), which will be occurring imminently
2245 * anyway, so we don't enable them here.
2246 */
2247 up->ier = UART_IER_RLSI | UART_IER_RDI;
2248 serial_outp(up, UART_IER, up->ier);
2249
2250 if (up->port.flags & UPF_FOURPORT) {
2251 unsigned int icp;
2252 /*
2253 * Enable interrupts on the AST Fourport board
2254 */
2255 icp = (up->port.iobase & 0xfe0) | 0x01f;
2256 outb_p(0x80, icp);
2257 (void) inb_p(icp);
2258 }
2259
2260 return 0;
2261}
2262
2263static void serial8250_shutdown(struct uart_port *port)
2264{
2265 struct uart_8250_port *up =
2266 container_of(port, struct uart_8250_port, port);
2267 unsigned long flags;
2268
2269 /*
2270 * Disable interrupts from this port
2271 */
2272 up->ier = 0;
2273 serial_outp(up, UART_IER, 0);
2274
2275 spin_lock_irqsave(&up->port.lock, flags);
2276 if (up->port.flags & UPF_FOURPORT) {
2277 /* reset interrupts on the AST Fourport board */
2278 inb((up->port.iobase & 0xfe0) | 0x1f);
2279 up->port.mctrl |= TIOCM_OUT1;
2280 } else
2281 up->port.mctrl &= ~TIOCM_OUT2;
2282
2283 serial8250_set_mctrl(&up->port, up->port.mctrl);
2284 spin_unlock_irqrestore(&up->port.lock, flags);
2285
2286 /*
2287 * Disable break condition and FIFOs
2288 */
2289 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2290 serial8250_clear_fifos(up);
2291
2292#ifdef CONFIG_SERIAL_8250_RSA
2293 /*
2294 * Reset the RSA board back to 115kbps compat mode.
2295 */
2296 disable_rsa(up);
2297#endif
2298
2299 /*
2300 * Read data port to reset things, and then unlink from
2301 * the IRQ chain.
2302 */
2303 (void) serial_in(up, UART_RX);
2304
2305 del_timer_sync(&up->timer);
2306 up->timer.function = serial8250_timeout;
2307 if (is_real_interrupt(up->port.irq))
2308 serial_unlink_irq_chain(up);
2309}
2310
2311static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2312{
2313 unsigned int quot;
2314
2315 /*
2316 * Handle magic divisors for baud rates above baud_base on
2317 * SMSC SuperIO chips.
2318 */
2319 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2320 baud == (port->uartclk/4))
2321 quot = 0x8001;
2322 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2323 baud == (port->uartclk/8))
2324 quot = 0x8002;
2325 else
2326 quot = uart_get_divisor(port, baud);
2327
2328 return quot;
2329}
2330
2331void
2332serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2333 struct ktermios *old)
2334{
2335 struct uart_8250_port *up =
2336 container_of(port, struct uart_8250_port, port);
2337 unsigned char cval, fcr = 0;
2338 unsigned long flags;
2339 unsigned int baud, quot;
2340
2341 switch (termios->c_cflag & CSIZE) {
2342 case CS5:
2343 cval = UART_LCR_WLEN5;
2344 break;
2345 case CS6:
2346 cval = UART_LCR_WLEN6;
2347 break;
2348 case CS7:
2349 cval = UART_LCR_WLEN7;
2350 break;
2351 default:
2352 case CS8:
2353 cval = UART_LCR_WLEN8;
2354 break;
2355 }
2356
2357 if (termios->c_cflag & CSTOPB)
2358 cval |= UART_LCR_STOP;
2359 if (termios->c_cflag & PARENB)
2360 cval |= UART_LCR_PARITY;
2361 if (!(termios->c_cflag & PARODD))
2362 cval |= UART_LCR_EPAR;
2363#ifdef CMSPAR
2364 if (termios->c_cflag & CMSPAR)
2365 cval |= UART_LCR_SPAR;
2366#endif
2367
2368 /*
2369 * Ask the core to calculate the divisor for us.
2370 */
2371 baud = uart_get_baud_rate(port, termios, old,
2372 port->uartclk / 16 / 0xffff,
2373 port->uartclk / 16);
2374 quot = serial8250_get_divisor(port, baud);
2375
2376 /*
2377 * Oxford Semi 952 rev B workaround
2378 */
2379 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2380 quot++;
2381
2382 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2383 if (baud < 2400)
2384 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2385 else
2386 fcr = uart_config[up->port.type].fcr;
2387 }
2388
2389 /*
2390 * MCR-based auto flow control. When AFE is enabled, RTS will be
2391 * deasserted when the receive FIFO contains more characters than
2392 * the trigger, or the MCR RTS bit is cleared. In the case where
2393 * the remote UART is not using CTS auto flow control, we must
2394 * have sufficient FIFO entries for the latency of the remote
2395 * UART to respond. IOW, at least 32 bytes of FIFO.
2396 */
2397 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2398 up->mcr &= ~UART_MCR_AFE;
2399 if (termios->c_cflag & CRTSCTS)
2400 up->mcr |= UART_MCR_AFE;
2401 }
2402
2403 /*
2404 * Ok, we're now changing the port state. Do it with
2405 * interrupts disabled.
2406 */
2407 spin_lock_irqsave(&up->port.lock, flags);
2408
2409 /*
2410 * Update the per-port timeout.
2411 */
2412 uart_update_timeout(port, termios->c_cflag, baud);
2413
2414 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2415 if (termios->c_iflag & INPCK)
2416 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2417 if (termios->c_iflag & (BRKINT | PARMRK))
2418 up->port.read_status_mask |= UART_LSR_BI;
2419
2420 /*
2421 * Characteres to ignore
2422 */
2423 up->port.ignore_status_mask = 0;
2424 if (termios->c_iflag & IGNPAR)
2425 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2426 if (termios->c_iflag & IGNBRK) {
2427 up->port.ignore_status_mask |= UART_LSR_BI;
2428 /*
2429 * If we're ignoring parity and break indicators,
2430 * ignore overruns too (for real raw support).
2431 */
2432 if (termios->c_iflag & IGNPAR)
2433 up->port.ignore_status_mask |= UART_LSR_OE;
2434 }
2435
2436 /*
2437 * ignore all characters if CREAD is not set
2438 */
2439 if ((termios->c_cflag & CREAD) == 0)
2440 up->port.ignore_status_mask |= UART_LSR_DR;
2441
2442 /*
2443 * CTS flow control flag and modem status interrupts
2444 */
2445 up->ier &= ~UART_IER_MSI;
2446 if (!(up->bugs & UART_BUG_NOMSR) &&
2447 UART_ENABLE_MS(&up->port, termios->c_cflag))
2448 up->ier |= UART_IER_MSI;
2449 if (up->capabilities & UART_CAP_UUE)
2450 up->ier |= UART_IER_UUE;
2451 if (up->capabilities & UART_CAP_RTOIE)
2452 up->ier |= UART_IER_RTOIE;
2453
2454 serial_out(up, UART_IER, up->ier);
2455
2456 if (up->capabilities & UART_CAP_EFR) {
2457 unsigned char efr = 0;
2458 /*
2459 * TI16C752/Startech hardware flow control. FIXME:
2460 * - TI16C752 requires control thresholds to be set.
2461 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2462 */
2463 if (termios->c_cflag & CRTSCTS)
2464 efr |= UART_EFR_CTS;
2465
2466 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2467 serial_outp(up, UART_EFR, efr);
2468 }
2469
2470 if (up->capabilities & UART_CAP_HW_CTSRTS) {
2471 unsigned char mcr = serial_inp(up, UART_MCR);
2472 /*
2473 * TEGRA UART core support the auto control of the RTS and CTS
2474 * flow control.
2475 */
2476 if (termios->c_cflag & CRTSCTS)
2477 mcr |= UART_MCR_HW_CTS;
2478 else
2479 mcr &= ~UART_MCR_HW_CTS;
2480 serial_outp(up, UART_MCR, mcr);
2481 }
2482
2483#ifdef CONFIG_ARCH_OMAP
2484 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2485 if (cpu_is_omap1510() && is_omap_port(up)) {
2486 if (baud == 115200) {
2487 quot = 1;
2488 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2489 } else
2490 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2491 }
2492#endif
2493
2494 if (up->capabilities & UART_NATSEMI) {
2495 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2496 serial_outp(up, UART_LCR, 0xe0);
2497 } else {
2498 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2499 }
2500
2501 serial_dl_write(up, quot);
2502
2503 /*
2504 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2505 * is written without DLAB set, this mode will be disabled.
2506 */
2507 if (up->port.type == PORT_16750)
2508 serial_outp(up, UART_FCR, fcr);
2509
2510 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2511 up->lcr = cval; /* Save LCR */
2512 if (up->port.type != PORT_16750) {
2513 if (fcr & UART_FCR_ENABLE_FIFO) {
2514 /* emulated UARTs (Lucent Venus 167x) need two steps */
2515 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2516 }
2517 serial_outp(up, UART_FCR, fcr); /* set fcr */
2518 }
2519 serial8250_set_mctrl(&up->port, up->port.mctrl);
2520 spin_unlock_irqrestore(&up->port.lock, flags);
2521 /* Don't rewrite B0 */
2522 if (tty_termios_baud_rate(termios))
2523 tty_termios_encode_baud_rate(termios, baud, baud);
2524}
2525EXPORT_SYMBOL(serial8250_do_set_termios);
2526
2527static void
2528serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2529 struct ktermios *old)
2530{
2531 if (port->set_termios)
2532 port->set_termios(port, termios, old);
2533 else
2534 serial8250_do_set_termios(port, termios, old);
2535}
2536
2537static void
2538serial8250_set_ldisc(struct uart_port *port, int new)
2539{
2540 if (new == N_PPS) {
2541 port->flags |= UPF_HARDPPS_CD;
2542 serial8250_enable_ms(port);
2543 } else
2544 port->flags &= ~UPF_HARDPPS_CD;
2545}
2546
2547
2548void serial8250_do_pm(struct uart_port *port, unsigned int state,
2549 unsigned int oldstate)
2550{
2551 struct uart_8250_port *p =
2552 container_of(port, struct uart_8250_port, port);
2553
2554 serial8250_set_sleep(p, state != 0);
2555}
2556EXPORT_SYMBOL(serial8250_do_pm);
2557
2558static void
2559serial8250_pm(struct uart_port *port, unsigned int state,
2560 unsigned int oldstate)
2561{
2562 if (port->pm)
2563 port->pm(port, state, oldstate);
2564 else
2565 serial8250_do_pm(port, state, oldstate);
2566}
2567
2568static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2569{
2570 if (pt->port.iotype == UPIO_AU)
2571 return 0x1000;
2572#ifdef CONFIG_ARCH_OMAP
2573 if (is_omap_port(pt))
2574 return 0x16 << pt->port.regshift;
2575#endif
2576 return 8 << pt->port.regshift;
2577}
2578
2579/*
2580 * Resource handling.
2581 */
2582static int serial8250_request_std_resource(struct uart_8250_port *up)
2583{
2584 unsigned int size = serial8250_port_size(up);
2585 int ret = 0;
2586
2587 switch (up->port.iotype) {
2588 case UPIO_AU:
2589 case UPIO_TSI:
2590 case UPIO_MEM32:
2591 case UPIO_MEM:
2592 case UPIO_DWAPB:
2593 case UPIO_DWAPB32:
2594 if (!up->port.mapbase)
2595 break;
2596
2597 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2598 ret = -EBUSY;
2599 break;
2600 }
2601
2602 if (up->port.flags & UPF_IOREMAP) {
2603 up->port.membase = ioremap_nocache(up->port.mapbase,
2604 size);
2605 if (!up->port.membase) {
2606 release_mem_region(up->port.mapbase, size);
2607 ret = -ENOMEM;
2608 }
2609 }
2610 break;
2611
2612 case UPIO_HUB6:
2613 case UPIO_PORT:
2614 if (!request_region(up->port.iobase, size, "serial"))
2615 ret = -EBUSY;
2616 break;
2617 }
2618 return ret;
2619}
2620
2621static void serial8250_release_std_resource(struct uart_8250_port *up)
2622{
2623 unsigned int size = serial8250_port_size(up);
2624
2625 switch (up->port.iotype) {
2626 case UPIO_AU:
2627 case UPIO_TSI:
2628 case UPIO_MEM32:
2629 case UPIO_MEM:
2630 case UPIO_DWAPB:
2631 case UPIO_DWAPB32:
2632 if (!up->port.mapbase)
2633 break;
2634
2635 if (up->port.flags & UPF_IOREMAP) {
2636 iounmap(up->port.membase);
2637 up->port.membase = NULL;
2638 }
2639
2640 release_mem_region(up->port.mapbase, size);
2641 break;
2642
2643 case UPIO_HUB6:
2644 case UPIO_PORT:
2645 release_region(up->port.iobase, size);
2646 break;
2647 }
2648}
2649
2650static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2651{
2652 unsigned long start = UART_RSA_BASE << up->port.regshift;
2653 unsigned int size = 8 << up->port.regshift;
2654 int ret = -EINVAL;
2655
2656 switch (up->port.iotype) {
2657 case UPIO_HUB6:
2658 case UPIO_PORT:
2659 start += up->port.iobase;
2660 if (request_region(start, size, "serial-rsa"))
2661 ret = 0;
2662 else
2663 ret = -EBUSY;
2664 break;
2665 }
2666
2667 return ret;
2668}
2669
2670static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2671{
2672 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2673 unsigned int size = 8 << up->port.regshift;
2674
2675 switch (up->port.iotype) {
2676 case UPIO_HUB6:
2677 case UPIO_PORT:
2678 release_region(up->port.iobase + offset, size);
2679 break;
2680 }
2681}
2682
2683static void serial8250_release_port(struct uart_port *port)
2684{
2685 struct uart_8250_port *up =
2686 container_of(port, struct uart_8250_port, port);
2687
2688 serial8250_release_std_resource(up);
2689 if (up->port.type == PORT_RSA)
2690 serial8250_release_rsa_resource(up);
2691}
2692
2693static int serial8250_request_port(struct uart_port *port)
2694{
2695 struct uart_8250_port *up =
2696 container_of(port, struct uart_8250_port, port);
2697 int ret = 0;
2698
2699 ret = serial8250_request_std_resource(up);
2700 if (ret == 0 && up->port.type == PORT_RSA) {
2701 ret = serial8250_request_rsa_resource(up);
2702 if (ret < 0)
2703 serial8250_release_std_resource(up);
2704 }
2705
2706 return ret;
2707}
2708
2709static void serial8250_config_port(struct uart_port *port, int flags)
2710{
2711 struct uart_8250_port *up =
2712 container_of(port, struct uart_8250_port, port);
2713 int probeflags = PROBE_ANY;
2714 int ret;
2715
2716 /*
2717 * Find the region that we can probe for. This in turn
2718 * tells us whether we can probe for the type of port.
2719 */
2720 ret = serial8250_request_std_resource(up);
2721 if (ret < 0)
2722 return;
2723
2724 ret = serial8250_request_rsa_resource(up);
2725 if (ret < 0)
2726 probeflags &= ~PROBE_RSA;
2727
2728 if (up->port.iotype != up->cur_iotype)
2729 set_io_from_upio(port);
2730
2731 if (flags & UART_CONFIG_TYPE)
2732 autoconfig(up, probeflags);
2733
2734 /* if access method is AU, it is a 16550 with a quirk */
2735 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2736 up->bugs |= UART_BUG_NOMSR;
2737
2738 if (up->port.type == PORT_TEGRA)
2739 up->bugs |= UART_BUG_NOMSR;
2740
2741 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2742 autoconfig_irq(up);
2743
2744 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2745 serial8250_release_rsa_resource(up);
2746 if (up->port.type == PORT_UNKNOWN)
2747 serial8250_release_std_resource(up);
2748}
2749
2750static int
2751serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2752{
2753 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2754 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2755 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2756 ser->type == PORT_STARTECH)
2757 return -EINVAL;
2758 return 0;
2759}
2760
2761static const char *
2762serial8250_type(struct uart_port *port)
2763{
2764 int type = port->type;
2765
2766 if (type >= ARRAY_SIZE(uart_config))
2767 type = 0;
2768 return uart_config[type].name;
2769}
2770
2771static struct uart_ops serial8250_pops = {
2772 .tx_empty = serial8250_tx_empty,
2773 .set_mctrl = serial8250_set_mctrl,
2774 .get_mctrl = serial8250_get_mctrl,
2775 .stop_tx = serial8250_stop_tx,
2776 .start_tx = serial8250_start_tx,
2777 .stop_rx = serial8250_stop_rx,
2778 .enable_ms = serial8250_enable_ms,
2779 .break_ctl = serial8250_break_ctl,
2780 .startup = serial8250_startup,
2781 .shutdown = serial8250_shutdown,
2782 .set_termios = serial8250_set_termios,
2783 .set_ldisc = serial8250_set_ldisc,
2784 .pm = serial8250_pm,
2785 .type = serial8250_type,
2786 .release_port = serial8250_release_port,
2787 .request_port = serial8250_request_port,
2788 .config_port = serial8250_config_port,
2789 .verify_port = serial8250_verify_port,
2790#ifdef CONFIG_CONSOLE_POLL
2791 .poll_get_char = serial8250_get_poll_char,
2792 .poll_put_char = serial8250_put_poll_char,
2793#endif
2794};
2795
2796static struct uart_8250_port serial8250_ports[UART_NR];
2797
2798static void (*serial8250_isa_config)(int port, struct uart_port *up,
2799 unsigned short *capabilities);
2800
2801void serial8250_set_isa_configurator(
2802 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2803{
2804 serial8250_isa_config = v;
2805}
2806EXPORT_SYMBOL(serial8250_set_isa_configurator);
2807
2808static void __init serial8250_isa_init_ports(void)
2809{
2810 struct uart_8250_port *up;
2811 static int first = 1;
2812 int i, irqflag = 0;
2813
2814 if (!first)
2815 return;
2816 first = 0;
2817
2818 for (i = 0; i < nr_uarts; i++) {
2819 struct uart_8250_port *up = &serial8250_ports[i];
2820
2821 up->port.line = i;
2822 spin_lock_init(&up->port.lock);
2823
2824 init_timer(&up->timer);
2825 up->timer.function = serial8250_timeout;
2826
2827 /*
2828 * ALPHA_KLUDGE_MCR needs to be killed.
2829 */
2830 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2831 up->mcr_force = ALPHA_KLUDGE_MCR;
2832
2833 up->port.ops = &serial8250_pops;
2834 }
2835
2836 if (share_irqs)
2837 irqflag = IRQF_SHARED;
2838
2839 for (i = 0, up = serial8250_ports;
2840 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2841 i++, up++) {
2842 up->port.iobase = old_serial_port[i].port;
2843 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2844 up->port.irqflags = old_serial_port[i].irqflags;
2845 up->port.uartclk = old_serial_port[i].baud_base * 16;
2846 up->port.flags = old_serial_port[i].flags;
2847 up->port.hub6 = old_serial_port[i].hub6;
2848 up->port.membase = old_serial_port[i].iomem_base;
2849 up->port.iotype = old_serial_port[i].io_type;
2850 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2851 set_io_from_upio(&up->port);
2852 up->port.irqflags |= irqflag;
2853 if (serial8250_isa_config != NULL)
2854 serial8250_isa_config(i, &up->port, &up->capabilities);
2855
2856 }
2857}
2858
2859static void
2860serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2861{
2862 up->port.type = type;
2863 up->port.fifosize = uart_config[type].fifo_size;
2864 up->capabilities = uart_config[type].flags;
2865 up->tx_loadsz = uart_config[type].tx_loadsz;
2866}
2867
2868static void __init
2869serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2870{
2871 int i;
2872
2873 for (i = 0; i < nr_uarts; i++) {
2874 struct uart_8250_port *up = &serial8250_ports[i];
2875 up->cur_iotype = 0xFF;
2876 }
2877
2878 serial8250_isa_init_ports();
2879
2880 for (i = 0; i < nr_uarts; i++) {
2881 struct uart_8250_port *up = &serial8250_ports[i];
2882
2883 up->port.dev = dev;
2884
2885 if (up->port.flags & UPF_FIXED_TYPE)
2886 serial8250_init_fixed_type_port(up, up->port.type);
2887
2888 uart_add_one_port(drv, &up->port);
2889 }
2890}
2891
2892#ifdef CONFIG_SERIAL_8250_CONSOLE
2893
2894static void serial8250_console_putchar(struct uart_port *port, int ch)
2895{
2896 struct uart_8250_port *up =
2897 container_of(port, struct uart_8250_port, port);
2898
2899 wait_for_xmitr(up, UART_LSR_THRE);
2900 serial_out(up, UART_TX, ch);
2901}
2902
2903/*
2904 * Print a string to the serial port trying not to disturb
2905 * any possible real use of the port...
2906 *
2907 * The console_lock must be held when we get here.
2908 */
2909static void
2910serial8250_console_write(struct console *co, const char *s, unsigned int count)
2911{
2912 struct uart_8250_port *up = &serial8250_ports[co->index];
2913 unsigned long flags;
2914 unsigned int ier;
2915 int locked = 1;
2916
2917 touch_nmi_watchdog();
2918
2919 local_irq_save(flags);
2920 if (up->port.sysrq) {
2921 /* serial8250_handle_port() already took the lock */
2922 locked = 0;
2923 } else if (oops_in_progress) {
2924 locked = spin_trylock(&up->port.lock);
2925 } else
2926 spin_lock(&up->port.lock);
2927
2928 /*
2929 * First save the IER then disable the interrupts
2930 */
2931 ier = serial_in(up, UART_IER);
2932
2933 if (up->capabilities & UART_CAP_UUE)
2934 serial_out(up, UART_IER, UART_IER_UUE);
2935 else
2936 serial_out(up, UART_IER, 0);
2937
2938 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2939
2940 /*
2941 * Finally, wait for transmitter to become empty
2942 * and restore the IER
2943 */
2944 wait_for_xmitr(up, BOTH_EMPTY);
2945 serial_out(up, UART_IER, ier);
2946
2947 /*
2948 * The receive handling will happen properly because the
2949 * receive ready bit will still be set; it is not cleared
2950 * on read. However, modem control will not, we must
2951 * call it if we have saved something in the saved flags
2952 * while processing with interrupts off.
2953 */
2954 if (up->msr_saved_flags)
2955 check_modem_status(up);
2956
2957 if (locked)
2958 spin_unlock(&up->port.lock);
2959 local_irq_restore(flags);
2960}
2961
2962static int __init serial8250_console_setup(struct console *co, char *options)
2963{
2964 struct uart_port *port;
2965 int baud = 9600;
2966 int bits = 8;
2967 int parity = 'n';
2968 int flow = 'n';
2969
2970 /*
2971 * Check whether an invalid uart number has been specified, and
2972 * if so, search for the first available port that does have
2973 * console support.
2974 */
2975 if (co->index >= nr_uarts)
2976 co->index = 0;
2977 port = &serial8250_ports[co->index].port;
2978 if (!port->iobase && !port->membase)
2979 return -ENODEV;
2980
2981 if (options)
2982 uart_parse_options(options, &baud, &parity, &bits, &flow);
2983
2984 return uart_set_options(port, co, baud, parity, bits, flow);
2985}
2986
2987static int serial8250_console_early_setup(void)
2988{
2989 return serial8250_find_port_for_earlycon();
2990}
2991
2992static struct console serial8250_console = {
2993 .name = "ttyS",
2994 .write = serial8250_console_write,
2995 .device = uart_console_device,
2996 .setup = serial8250_console_setup,
2997 .early_setup = serial8250_console_early_setup,
2998 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2999 .index = -1,
3000 .data = &serial8250_reg,
3001};
3002
3003static int __init serial8250_console_init(void)
3004{
3005 if (nr_uarts > UART_NR)
3006 nr_uarts = UART_NR;
3007
3008 serial8250_isa_init_ports();
3009 register_console(&serial8250_console);
3010 return 0;
3011}
3012console_initcall(serial8250_console_init);
3013
3014int serial8250_find_port(struct uart_port *p)
3015{
3016 int line;
3017 struct uart_port *port;
3018
3019 for (line = 0; line < nr_uarts; line++) {
3020 port = &serial8250_ports[line].port;
3021 if (uart_match_port(p, port))
3022 return line;
3023 }
3024 return -ENODEV;
3025}
3026
3027#define SERIAL8250_CONSOLE &serial8250_console
3028#else
3029#define SERIAL8250_CONSOLE NULL
3030#endif
3031
3032static struct uart_driver serial8250_reg = {
3033 .owner = THIS_MODULE,
3034 .driver_name = "serial",
3035 .dev_name = "ttyS",
3036 .major = TTY_MAJOR,
3037 .minor = 64,
3038 .cons = SERIAL8250_CONSOLE,
3039};
3040
3041/*
3042 * early_serial_setup - early registration for 8250 ports
3043 *
3044 * Setup an 8250 port structure prior to console initialisation. Use
3045 * after console initialisation will cause undefined behaviour.
3046 */
3047int __init early_serial_setup(struct uart_port *port)
3048{
3049 struct uart_port *p;
3050
3051 if (port->line >= ARRAY_SIZE(serial8250_ports))
3052 return -ENODEV;
3053
3054 serial8250_isa_init_ports();
3055 p = &serial8250_ports[port->line].port;
3056 p->iobase = port->iobase;
3057 p->membase = port->membase;
3058 p->irq = port->irq;
3059 p->irqflags = port->irqflags;
3060 p->uartclk = port->uartclk;
3061 p->fifosize = port->fifosize;
3062 p->regshift = port->regshift;
3063 p->iotype = port->iotype;
3064 p->flags = port->flags;
3065 p->mapbase = port->mapbase;
3066 p->private_data = port->private_data;
3067 p->type = port->type;
3068 p->line = port->line;
3069
3070 set_io_from_upio(p);
3071 if (port->serial_in)
3072 p->serial_in = port->serial_in;
3073 if (port->serial_out)
3074 p->serial_out = port->serial_out;
3075
3076 return 0;
3077}
3078
3079/**
3080 * serial8250_suspend_port - suspend one serial port
3081 * @line: serial line number
3082 *
3083 * Suspend one serial port.
3084 */
3085void serial8250_suspend_port(int line)
3086{
3087 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3088}
3089
3090/**
3091 * serial8250_resume_port - resume one serial port
3092 * @line: serial line number
3093 *
3094 * Resume one serial port.
3095 */
3096void serial8250_resume_port(int line)
3097{
3098 struct uart_8250_port *up = &serial8250_ports[line];
3099
3100 if (up->capabilities & UART_NATSEMI) {
3101 /* Ensure it's still in high speed mode */
3102 serial_outp(up, UART_LCR, 0xE0);
3103
3104 ns16550a_goto_highspeed(up);
3105
3106 serial_outp(up, UART_LCR, 0);
3107 up->port.uartclk = 921600*16;
3108 }
3109 uart_resume_port(&serial8250_reg, &up->port);
3110}
3111
3112/*
3113 * Register a set of serial devices attached to a platform device. The
3114 * list is terminated with a zero flags entry, which means we expect
3115 * all entries to have at least UPF_BOOT_AUTOCONF set.
3116 */
3117static int __devinit serial8250_probe(struct platform_device *dev)
3118{
3119 struct plat_serial8250_port *p = dev->dev.platform_data;
3120 struct uart_port port;
3121 int ret, i, irqflag = 0;
3122
3123 memset(&port, 0, sizeof(struct uart_port));
3124
3125 if (share_irqs)
3126 irqflag = IRQF_SHARED;
3127
3128 for (i = 0; p && p->flags != 0; p++, i++) {
3129 port.iobase = p->iobase;
3130 port.membase = p->membase;
3131 port.irq = p->irq;
3132 port.irqflags = p->irqflags;
3133 port.uartclk = p->uartclk;
3134 port.regshift = p->regshift;
3135 port.iotype = p->iotype;
3136 port.flags = p->flags;
3137 port.mapbase = p->mapbase;
3138 port.hub6 = p->hub6;
3139 port.private_data = p->private_data;
3140 port.type = p->type;
3141 port.serial_in = p->serial_in;
3142 port.serial_out = p->serial_out;
3143 port.set_termios = p->set_termios;
3144 port.pm = p->pm;
3145 port.dev = &dev->dev;
3146 port.irqflags |= irqflag;
3147 ret = serial8250_register_port(&port);
3148 if (ret < 0) {
3149 dev_err(&dev->dev, "unable to register port at index %d "
3150 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3151 p->iobase, (unsigned long long)p->mapbase,
3152 p->irq, ret);
3153 }
3154 }
3155 return 0;
3156}
3157
3158/*
3159 * Remove serial ports registered against a platform device.
3160 */
3161static int __devexit serial8250_remove(struct platform_device *dev)
3162{
3163 int i;
3164
3165 for (i = 0; i < nr_uarts; i++) {
3166 struct uart_8250_port *up = &serial8250_ports[i];
3167
3168 if (up->port.dev == &dev->dev)
3169 serial8250_unregister_port(i);
3170 }
3171 return 0;
3172}
3173
3174static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3175{
3176 int i;
3177
3178 for (i = 0; i < UART_NR; i++) {
3179 struct uart_8250_port *up = &serial8250_ports[i];
3180
3181 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3182 uart_suspend_port(&serial8250_reg, &up->port);
3183 }
3184
3185 return 0;
3186}
3187
3188static int serial8250_resume(struct platform_device *dev)
3189{
3190 int i;
3191
3192 for (i = 0; i < UART_NR; i++) {
3193 struct uart_8250_port *up = &serial8250_ports[i];
3194
3195 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3196 serial8250_resume_port(i);
3197 }
3198
3199 return 0;
3200}
3201
3202static struct platform_driver serial8250_isa_driver = {
3203 .probe = serial8250_probe,
3204 .remove = __devexit_p(serial8250_remove),
3205 .suspend = serial8250_suspend,
3206 .resume = serial8250_resume,
3207 .driver = {
3208 .name = "serial8250",
3209 .owner = THIS_MODULE,
3210 },
3211};
3212
3213/*
3214 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3215 * in the table in include/asm/serial.h
3216 */
3217static struct platform_device *serial8250_isa_devs;
3218
3219/*
3220 * serial8250_register_port and serial8250_unregister_port allows for
3221 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3222 * modems and PCI multiport cards.
3223 */
3224static DEFINE_MUTEX(serial_mutex);
3225
3226static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3227{
3228 int i;
3229
3230 /*
3231 * First, find a port entry which matches.
3232 */
3233 for (i = 0; i < nr_uarts; i++)
3234 if (uart_match_port(&serial8250_ports[i].port, port))
3235 return &serial8250_ports[i];
3236
3237 /*
3238 * We didn't find a matching entry, so look for the first
3239 * free entry. We look for one which hasn't been previously
3240 * used (indicated by zero iobase).
3241 */
3242 for (i = 0; i < nr_uarts; i++)
3243 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3244 serial8250_ports[i].port.iobase == 0)
3245 return &serial8250_ports[i];
3246
3247 /*
3248 * That also failed. Last resort is to find any entry which
3249 * doesn't have a real port associated with it.
3250 */
3251 for (i = 0; i < nr_uarts; i++)
3252 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3253 return &serial8250_ports[i];
3254
3255 return NULL;
3256}
3257
3258/**
3259 * serial8250_register_port - register a serial port
3260 * @port: serial port template
3261 *
3262 * Configure the serial port specified by the request. If the
3263 * port exists and is in use, it is hung up and unregistered
3264 * first.
3265 *
3266 * The port is then probed and if necessary the IRQ is autodetected
3267 * If this fails an error is returned.
3268 *
3269 * On success the port is ready to use and the line number is returned.
3270 */
3271int serial8250_register_port(struct uart_port *port)
3272{
3273 struct uart_8250_port *uart;
3274 int ret = -ENOSPC;
3275
3276 if (port->uartclk == 0)
3277 return -EINVAL;
3278
3279 mutex_lock(&serial_mutex);
3280
3281 uart = serial8250_find_match_or_unused(port);
3282 if (uart) {
3283 uart_remove_one_port(&serial8250_reg, &uart->port);
3284
3285 uart->port.iobase = port->iobase;
3286 uart->port.membase = port->membase;
3287 uart->port.irq = port->irq;
3288 uart->port.irqflags = port->irqflags;
3289 uart->port.uartclk = port->uartclk;
3290 uart->port.fifosize = port->fifosize;
3291 uart->port.regshift = port->regshift;
3292 uart->port.iotype = port->iotype;
3293 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3294 uart->port.mapbase = port->mapbase;
3295 uart->port.private_data = port->private_data;
3296 if (port->dev)
3297 uart->port.dev = port->dev;
3298
3299 if (port->flags & UPF_FIXED_TYPE)
3300 serial8250_init_fixed_type_port(uart, port->type);
3301
3302 set_io_from_upio(&uart->port);
3303 /* Possibly override default I/O functions. */
3304 if (port->serial_in)
3305 uart->port.serial_in = port->serial_in;
3306 if (port->serial_out)
3307 uart->port.serial_out = port->serial_out;
3308 /* Possibly override set_termios call */
3309 if (port->set_termios)
3310 uart->port.set_termios = port->set_termios;
3311 if (port->pm)
3312 uart->port.pm = port->pm;
3313
3314 if (serial8250_isa_config != NULL)
3315 serial8250_isa_config(0, &uart->port,
3316 &uart->capabilities);
3317
3318 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3319 if (ret == 0)
3320 ret = uart->port.line;
3321 }
3322 mutex_unlock(&serial_mutex);
3323
3324 return ret;
3325}
3326EXPORT_SYMBOL(serial8250_register_port);
3327
3328/**
3329 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3330 * @line: serial line number
3331 *
3332 * Remove one serial port. This may not be called from interrupt
3333 * context. We hand the port back to the our control.
3334 */
3335void serial8250_unregister_port(int line)
3336{
3337 struct uart_8250_port *uart = &serial8250_ports[line];
3338
3339 mutex_lock(&serial_mutex);
3340 uart_remove_one_port(&serial8250_reg, &uart->port);
3341 if (serial8250_isa_devs) {
3342 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3343 uart->port.type = PORT_UNKNOWN;
3344 uart->port.dev = &serial8250_isa_devs->dev;
3345 uart->capabilities = uart_config[uart->port.type].flags;
3346 uart_add_one_port(&serial8250_reg, &uart->port);
3347 } else {
3348 uart->port.dev = NULL;
3349 }
3350 mutex_unlock(&serial_mutex);
3351}
3352EXPORT_SYMBOL(serial8250_unregister_port);
3353
3354static int __init serial8250_init(void)
3355{
3356 int ret;
3357
3358 if (nr_uarts > UART_NR)
3359 nr_uarts = UART_NR;
3360
3361 printk(KERN_INFO "Serial: 8250/16550 driver, "
3362 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3363 share_irqs ? "en" : "dis");
3364
3365#ifdef CONFIG_SPARC
3366 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3367#else
3368 serial8250_reg.nr = UART_NR;
3369 ret = uart_register_driver(&serial8250_reg);
3370#endif
3371 if (ret)
3372 goto out;
3373
3374 serial8250_isa_devs = platform_device_alloc("serial8250",
3375 PLAT8250_DEV_LEGACY);
3376 if (!serial8250_isa_devs) {
3377 ret = -ENOMEM;
3378 goto unreg_uart_drv;
3379 }
3380
3381 ret = platform_device_add(serial8250_isa_devs);
3382 if (ret)
3383 goto put_dev;
3384
3385 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3386
3387 ret = platform_driver_register(&serial8250_isa_driver);
3388 if (ret == 0)
3389 goto out;
3390
3391 platform_device_del(serial8250_isa_devs);
3392put_dev:
3393 platform_device_put(serial8250_isa_devs);
3394unreg_uart_drv:
3395#ifdef CONFIG_SPARC
3396 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3397#else
3398 uart_unregister_driver(&serial8250_reg);
3399#endif
3400out:
3401 return ret;
3402}
3403
3404#ifdef MODULE
3405static void __exit serial8250_exit(void)
3406{
3407 struct platform_device *isa_dev = serial8250_isa_devs;
3408
3409 /*
3410 * This tells serial8250_unregister_port() not to re-register
3411 * the ports (thereby making serial8250_isa_driver permanently
3412 * in use.)
3413 */
3414 serial8250_isa_devs = NULL;
3415
3416 platform_driver_unregister(&serial8250_isa_driver);
3417 platform_device_unregister(isa_dev);
3418
3419#ifdef CONFIG_SPARC
3420 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3421#else
3422 uart_unregister_driver(&serial8250_reg);
3423#endif
3424}
3425
3426module_init(serial8250_init);
3427module_exit(serial8250_exit);
3428#else
3429postcore_initcall(serial8250_init);
3430#endif
3431
3432EXPORT_SYMBOL(serial8250_suspend_port);
3433EXPORT_SYMBOL(serial8250_resume_port);
3434
3435MODULE_LICENSE("GPL");
3436MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3437
3438module_param(share_irqs, uint, 0644);
3439MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3440 " (unsafe)");
3441
3442module_param(nr_uarts, uint, 0644);
3443MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3444
3445module_param(skip_txen_test, uint, 0644);
3446MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3447
3448#ifdef CONFIG_SERIAL_8250_RSA
3449module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3450MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3451#endif
3452MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
diff --git a/drivers/tty/serial/8250.h b/drivers/tty/serial/8250.h
new file mode 100644
index 00000000000..66a0c936b93
--- /dev/null
+++ b/drivers/tty/serial/8250.h
@@ -0,0 +1,80 @@
1/*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/serial_8250.h>
15
16struct old_serial_port {
17 unsigned int uart;
18 unsigned int baud_base;
19 unsigned int port;
20 unsigned int irq;
21 unsigned int flags;
22 unsigned char hub6;
23 unsigned char io_type;
24 unsigned char *iomem_base;
25 unsigned short iomem_reg_shift;
26 unsigned long irqflags;
27};
28
29/*
30 * This replaces serial_uart_config in include/linux/serial.h
31 */
32struct serial8250_config {
33 const char *name;
34 unsigned short fifo_size;
35 unsigned short tx_loadsz;
36 unsigned char fcr;
37 unsigned int flags;
38};
39
40#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
41#define UART_CAP_EFR (1 << 9) /* UART has EFR */
42#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
43#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
44#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
45#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
46#define UART_CAP_HW_CTSRTS (1 << 14) /* UART core support hw control of RTS and CTS */
47
48#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
49#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
50#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
51#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
52
53#define PROBE_RSA (1 << 0)
54#define PROBE_ANY (~0)
55
56#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
57
58#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
59#define SERIAL8250_SHARE_IRQS 1
60#else
61#define SERIAL8250_SHARE_IRQS 0
62#endif
63
64#if defined(__alpha__) && !defined(CONFIG_PCI)
65/*
66 * Digital did something really horribly wrong with the OUT1 and OUT2
67 * lines on at least some ALPHA's. The failure mode is that if either
68 * is cleared, the machine locks up with endless interrupts.
69 */
70#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
71#elif defined(CONFIG_SBC8560)
72/*
73 * WindRiver did something similarly broken on their SBC8560 board. The
74 * UART tristates its IRQ output while OUT2 is clear, but they pulled
75 * the interrupt line _up_ instead of down, so if we register the IRQ
76 * while the UART is in that state, we die in an IRQ storm. */
77#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2)
78#else
79#define ALPHA_KLUDGE_MCR 0
80#endif
diff --git a/drivers/tty/serial/8250_accent.c b/drivers/tty/serial/8250_accent.c
new file mode 100644
index 00000000000..34b51c65119
--- /dev/null
+++ b/drivers/tty/serial/8250_accent.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial_8250.h>
12
13#define PORT(_base,_irq) \
14 { \
15 .iobase = _base, \
16 .irq = _irq, \
17 .uartclk = 1843200, \
18 .iotype = UPIO_PORT, \
19 .flags = UPF_BOOT_AUTOCONF, \
20 }
21
22static struct plat_serial8250_port accent_data[] = {
23 PORT(0x330, 4),
24 PORT(0x338, 4),
25 { },
26};
27
28static struct platform_device accent_device = {
29 .name = "serial8250",
30 .id = PLAT8250_DEV_ACCENT,
31 .dev = {
32 .platform_data = accent_data,
33 },
34};
35
36static int __init accent_init(void)
37{
38 return platform_device_register(&accent_device);
39}
40
41module_init(accent_init);
42
43MODULE_AUTHOR("Russell King");
44MODULE_DESCRIPTION("8250 serial probe module for Accent Async cards");
45MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_acorn.c b/drivers/tty/serial/8250_acorn.c
new file mode 100644
index 00000000000..b0ce8c56f1a
--- /dev/null
+++ b/drivers/tty/serial/8250_acorn.c
@@ -0,0 +1,141 @@
1/*
2 * linux/drivers/serial/acorn.c
3 *
4 * Copyright (C) 1996-2003 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/tty.h>
13#include <linux/serial_core.h>
14#include <linux/errno.h>
15#include <linux/ioport.h>
16#include <linux/slab.h>
17#include <linux/device.h>
18#include <linux/init.h>
19
20#include <asm/io.h>
21#include <asm/ecard.h>
22#include <asm/string.h>
23
24#include "8250.h"
25
26#define MAX_PORTS 3
27
28struct serial_card_type {
29 unsigned int num_ports;
30 unsigned int uartclk;
31 unsigned int type;
32 unsigned int offset[MAX_PORTS];
33};
34
35struct serial_card_info {
36 unsigned int num_ports;
37 int ports[MAX_PORTS];
38 void __iomem *vaddr;
39};
40
41static int __devinit
42serial_card_probe(struct expansion_card *ec, const struct ecard_id *id)
43{
44 struct serial_card_info *info;
45 struct serial_card_type *type = id->data;
46 struct uart_port port;
47 unsigned long bus_addr;
48 unsigned int i;
49
50 info = kzalloc(sizeof(struct serial_card_info), GFP_KERNEL);
51 if (!info)
52 return -ENOMEM;
53
54 info->num_ports = type->num_ports;
55
56 bus_addr = ecard_resource_start(ec, type->type);
57 info->vaddr = ecardm_iomap(ec, type->type, 0, 0);
58 if (!info->vaddr) {
59 kfree(info);
60 return -ENOMEM;
61 }
62
63 ecard_set_drvdata(ec, info);
64
65 memset(&port, 0, sizeof(struct uart_port));
66 port.irq = ec->irq;
67 port.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
68 port.uartclk = type->uartclk;
69 port.iotype = UPIO_MEM;
70 port.regshift = 2;
71 port.dev = &ec->dev;
72
73 for (i = 0; i < info->num_ports; i ++) {
74 port.membase = info->vaddr + type->offset[i];
75 port.mapbase = bus_addr + type->offset[i];
76
77 info->ports[i] = serial8250_register_port(&port);
78 }
79
80 return 0;
81}
82
83static void __devexit serial_card_remove(struct expansion_card *ec)
84{
85 struct serial_card_info *info = ecard_get_drvdata(ec);
86 int i;
87
88 ecard_set_drvdata(ec, NULL);
89
90 for (i = 0; i < info->num_ports; i++)
91 if (info->ports[i] > 0)
92 serial8250_unregister_port(info->ports[i]);
93
94 kfree(info);
95}
96
97static struct serial_card_type atomwide_type = {
98 .num_ports = 3,
99 .uartclk = 7372800,
100 .type = ECARD_RES_IOCSLOW,
101 .offset = { 0x2800, 0x2400, 0x2000 },
102};
103
104static struct serial_card_type serport_type = {
105 .num_ports = 2,
106 .uartclk = 3686400,
107 .type = ECARD_RES_IOCSLOW,
108 .offset = { 0x2000, 0x2020 },
109};
110
111static const struct ecard_id serial_cids[] = {
112 { MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, &atomwide_type },
113 { MANU_SERPORT, PROD_SERPORT_DSPORT, &serport_type },
114 { 0xffff, 0xffff }
115};
116
117static struct ecard_driver serial_card_driver = {
118 .probe = serial_card_probe,
119 .remove = __devexit_p(serial_card_remove),
120 .id_table = serial_cids,
121 .drv = {
122 .name = "8250_acorn",
123 },
124};
125
126static int __init serial_card_init(void)
127{
128 return ecard_register_driver(&serial_card_driver);
129}
130
131static void __exit serial_card_exit(void)
132{
133 ecard_remove_driver(&serial_card_driver);
134}
135
136MODULE_AUTHOR("Russell King");
137MODULE_DESCRIPTION("Acorn 8250-compatible serial port expansion card driver");
138MODULE_LICENSE("GPL");
139
140module_init(serial_card_init);
141module_exit(serial_card_exit);
diff --git a/drivers/tty/serial/8250_boca.c b/drivers/tty/serial/8250_boca.c
new file mode 100644
index 00000000000..d125dc10798
--- /dev/null
+++ b/drivers/tty/serial/8250_boca.c
@@ -0,0 +1,59 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial_8250.h>
12
13#define PORT(_base,_irq) \
14 { \
15 .iobase = _base, \
16 .irq = _irq, \
17 .uartclk = 1843200, \
18 .iotype = UPIO_PORT, \
19 .flags = UPF_BOOT_AUTOCONF, \
20 }
21
22static struct plat_serial8250_port boca_data[] = {
23 PORT(0x100, 12),
24 PORT(0x108, 12),
25 PORT(0x110, 12),
26 PORT(0x118, 12),
27 PORT(0x120, 12),
28 PORT(0x128, 12),
29 PORT(0x130, 12),
30 PORT(0x138, 12),
31 PORT(0x140, 12),
32 PORT(0x148, 12),
33 PORT(0x150, 12),
34 PORT(0x158, 12),
35 PORT(0x160, 12),
36 PORT(0x168, 12),
37 PORT(0x170, 12),
38 PORT(0x178, 12),
39 { },
40};
41
42static struct platform_device boca_device = {
43 .name = "serial8250",
44 .id = PLAT8250_DEV_BOCA,
45 .dev = {
46 .platform_data = boca_data,
47 },
48};
49
50static int __init boca_init(void)
51{
52 return platform_device_register(&boca_device);
53}
54
55module_init(boca_init);
56
57MODULE_AUTHOR("Russell King");
58MODULE_DESCRIPTION("8250 serial probe module for Boca cards");
59MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_early.c b/drivers/tty/serial/8250_early.c
new file mode 100644
index 00000000000..eaafb98debe
--- /dev/null
+++ b/drivers/tty/serial/8250_early.c
@@ -0,0 +1,287 @@
1/*
2 * Early serial console for 8250/16550 devices
3 *
4 * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
5 * Bjorn Helgaas <bjorn.helgaas@hp.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Based on the 8250.c serial driver, Copyright (C) 2001 Russell King,
12 * and on early_printk.c by Andi Kleen.
13 *
14 * This is for use before the serial driver has initialized, in
15 * particular, before the UARTs have been discovered and named.
16 * Instead of specifying the console device as, e.g., "ttyS0",
17 * we locate the device directly by its MMIO or I/O port address.
18 *
19 * The user can specify the device directly, e.g.,
20 * earlycon=uart8250,io,0x3f8,9600n8
21 * earlycon=uart8250,mmio,0xff5e0000,115200n8
22 * earlycon=uart8250,mmio32,0xff5e0000,115200n8
23 * or
24 * console=uart8250,io,0x3f8,9600n8
25 * console=uart8250,mmio,0xff5e0000,115200n8
26 * console=uart8250,mmio32,0xff5e0000,115200n8
27 */
28
29#include <linux/tty.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/serial_core.h>
33#include <linux/serial_reg.h>
34#include <linux/serial.h>
35#include <linux/serial_8250.h>
36#include <asm/io.h>
37#include <asm/serial.h>
38#ifdef CONFIG_FIX_EARLYCON_MEM
39#include <asm/pgtable.h>
40#include <asm/fixmap.h>
41#endif
42
43struct early_serial8250_device {
44 struct uart_port port;
45 char options[16]; /* e.g., 115200n8 */
46 unsigned int baud;
47};
48
49static struct early_serial8250_device early_device;
50
51static unsigned int __init serial_in(struct uart_port *port, int offset)
52{
53 switch (port->iotype) {
54 case UPIO_MEM:
55 return readb(port->membase + offset);
56 case UPIO_MEM32:
57 return readl(port->membase + (offset << 2));
58 case UPIO_PORT:
59 return inb(port->iobase + offset);
60 default:
61 return 0;
62 }
63}
64
65static void __init serial_out(struct uart_port *port, int offset, int value)
66{
67 switch (port->iotype) {
68 case UPIO_MEM:
69 writeb(value, port->membase + offset);
70 break;
71 case UPIO_MEM32:
72 writel(value, port->membase + (offset << 2));
73 break;
74 case UPIO_PORT:
75 outb(value, port->iobase + offset);
76 break;
77 }
78}
79
80#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
81
82static void __init wait_for_xmitr(struct uart_port *port)
83{
84 unsigned int status;
85
86 for (;;) {
87 status = serial_in(port, UART_LSR);
88 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
89 return;
90 cpu_relax();
91 }
92}
93
94static void __init serial_putc(struct uart_port *port, int c)
95{
96 wait_for_xmitr(port);
97 serial_out(port, UART_TX, c);
98}
99
100static void __init early_serial8250_write(struct console *console,
101 const char *s, unsigned int count)
102{
103 struct uart_port *port = &early_device.port;
104 unsigned int ier;
105
106 /* Save the IER and disable interrupts */
107 ier = serial_in(port, UART_IER);
108 serial_out(port, UART_IER, 0);
109
110 uart_console_write(port, s, count, serial_putc);
111
112 /* Wait for transmitter to become empty and restore the IER */
113 wait_for_xmitr(port);
114 serial_out(port, UART_IER, ier);
115}
116
117static unsigned int __init probe_baud(struct uart_port *port)
118{
119 unsigned char lcr, dll, dlm;
120 unsigned int quot;
121
122 lcr = serial_in(port, UART_LCR);
123 serial_out(port, UART_LCR, lcr | UART_LCR_DLAB);
124 dll = serial_in(port, UART_DLL);
125 dlm = serial_in(port, UART_DLM);
126 serial_out(port, UART_LCR, lcr);
127
128 quot = (dlm << 8) | dll;
129 return (port->uartclk / 16) / quot;
130}
131
132static void __init init_port(struct early_serial8250_device *device)
133{
134 struct uart_port *port = &device->port;
135 unsigned int divisor;
136 unsigned char c;
137
138 serial_out(port, UART_LCR, 0x3); /* 8n1 */
139 serial_out(port, UART_IER, 0); /* no interrupt */
140 serial_out(port, UART_FCR, 0); /* no fifo */
141 serial_out(port, UART_MCR, 0x3); /* DTR + RTS */
142
143 divisor = port->uartclk / (16 * device->baud);
144 c = serial_in(port, UART_LCR);
145 serial_out(port, UART_LCR, c | UART_LCR_DLAB);
146 serial_out(port, UART_DLL, divisor & 0xff);
147 serial_out(port, UART_DLM, (divisor >> 8) & 0xff);
148 serial_out(port, UART_LCR, c & ~UART_LCR_DLAB);
149}
150
151static int __init parse_options(struct early_serial8250_device *device,
152 char *options)
153{
154 struct uart_port *port = &device->port;
155 int mmio, mmio32, length;
156
157 if (!options)
158 return -ENODEV;
159
160 port->uartclk = BASE_BAUD * 16;
161
162 mmio = !strncmp(options, "mmio,", 5);
163 mmio32 = !strncmp(options, "mmio32,", 7);
164 if (mmio || mmio32) {
165 port->iotype = (mmio ? UPIO_MEM : UPIO_MEM32);
166 port->mapbase = simple_strtoul(options + (mmio ? 5 : 7),
167 &options, 0);
168 if (mmio32)
169 port->regshift = 2;
170#ifdef CONFIG_FIX_EARLYCON_MEM
171 set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
172 port->mapbase & PAGE_MASK);
173 port->membase =
174 (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
175 port->membase += port->mapbase & ~PAGE_MASK;
176#else
177 port->membase = ioremap_nocache(port->mapbase, 64);
178 if (!port->membase) {
179 printk(KERN_ERR "%s: Couldn't ioremap 0x%llx\n",
180 __func__,
181 (unsigned long long) port->mapbase);
182 return -ENOMEM;
183 }
184#endif
185 } else if (!strncmp(options, "io,", 3)) {
186 port->iotype = UPIO_PORT;
187 port->iobase = simple_strtoul(options + 3, &options, 0);
188 mmio = 0;
189 } else
190 return -EINVAL;
191
192 options = strchr(options, ',');
193 if (options) {
194 options++;
195 device->baud = simple_strtoul(options, NULL, 0);
196 length = min(strcspn(options, " "), sizeof(device->options));
197 strncpy(device->options, options, length);
198 } else {
199 device->baud = probe_baud(port);
200 snprintf(device->options, sizeof(device->options), "%u",
201 device->baud);
202 }
203
204 if (mmio || mmio32)
205 printk(KERN_INFO
206 "Early serial console at MMIO%s 0x%llx (options '%s')\n",
207 mmio32 ? "32" : "",
208 (unsigned long long)port->mapbase,
209 device->options);
210 else
211 printk(KERN_INFO
212 "Early serial console at I/O port 0x%lx (options '%s')\n",
213 port->iobase,
214 device->options);
215
216 return 0;
217}
218
219static struct console early_serial8250_console __initdata = {
220 .name = "uart",
221 .write = early_serial8250_write,
222 .flags = CON_PRINTBUFFER | CON_BOOT,
223 .index = -1,
224};
225
226static int __init early_serial8250_setup(char *options)
227{
228 struct early_serial8250_device *device = &early_device;
229 int err;
230
231 if (device->port.membase || device->port.iobase)
232 return 0;
233
234 err = parse_options(device, options);
235 if (err < 0)
236 return err;
237
238 init_port(device);
239 return 0;
240}
241
242int __init setup_early_serial8250_console(char *cmdline)
243{
244 char *options;
245 int err;
246
247 options = strstr(cmdline, "uart8250,");
248 if (!options) {
249 options = strstr(cmdline, "uart,");
250 if (!options)
251 return 0;
252 }
253
254 options = strchr(cmdline, ',') + 1;
255 err = early_serial8250_setup(options);
256 if (err < 0)
257 return err;
258
259 register_console(&early_serial8250_console);
260
261 return 0;
262}
263
264int serial8250_find_port_for_earlycon(void)
265{
266 struct early_serial8250_device *device = &early_device;
267 struct uart_port *port = &device->port;
268 int line;
269 int ret;
270
271 if (!device->port.membase && !device->port.iobase)
272 return -ENODEV;
273
274 line = serial8250_find_port(port);
275 if (line < 0)
276 return -ENODEV;
277
278 ret = update_console_cmdline("uart", 8250,
279 "ttyS", line, device->options);
280 if (ret < 0)
281 ret = update_console_cmdline("uart", 0,
282 "ttyS", line, device->options);
283
284 return ret;
285}
286
287early_param("earlycon", setup_early_serial8250_console);
diff --git a/drivers/tty/serial/8250_exar_st16c554.c b/drivers/tty/serial/8250_exar_st16c554.c
new file mode 100644
index 00000000000..bf53aabf9b5
--- /dev/null
+++ b/drivers/tty/serial/8250_exar_st16c554.c
@@ -0,0 +1,50 @@
1/*
2 * Written by Paul B Schroeder < pschroeder "at" uplogix "dot" com >
3 * Based on 8250_boca.
4 *
5 * Copyright (C) 2005 Russell King.
6 * Data taken from include/asm-i386/serial.h
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/serial_8250.h>
15
16#define PORT(_base,_irq) \
17 { \
18 .iobase = _base, \
19 .irq = _irq, \
20 .uartclk = 1843200, \
21 .iotype = UPIO_PORT, \
22 .flags = UPF_BOOT_AUTOCONF, \
23 }
24
25static struct plat_serial8250_port exar_data[] = {
26 PORT(0x100, 5),
27 PORT(0x108, 5),
28 PORT(0x110, 5),
29 PORT(0x118, 5),
30 { },
31};
32
33static struct platform_device exar_device = {
34 .name = "serial8250",
35 .id = PLAT8250_DEV_EXAR_ST16C554,
36 .dev = {
37 .platform_data = exar_data,
38 },
39};
40
41static int __init exar_init(void)
42{
43 return platform_device_register(&exar_device);
44}
45
46module_init(exar_init);
47
48MODULE_AUTHOR("Paul B Schroeder");
49MODULE_DESCRIPTION("8250 serial probe module for Exar cards");
50MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_fourport.c b/drivers/tty/serial/8250_fourport.c
new file mode 100644
index 00000000000..be158260962
--- /dev/null
+++ b/drivers/tty/serial/8250_fourport.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial_8250.h>
12
13#define PORT(_base,_irq) \
14 { \
15 .iobase = _base, \
16 .irq = _irq, \
17 .uartclk = 1843200, \
18 .iotype = UPIO_PORT, \
19 .flags = UPF_BOOT_AUTOCONF | UPF_FOURPORT, \
20 }
21
22static struct plat_serial8250_port fourport_data[] = {
23 PORT(0x1a0, 9),
24 PORT(0x1a8, 9),
25 PORT(0x1b0, 9),
26 PORT(0x1b8, 9),
27 PORT(0x2a0, 5),
28 PORT(0x2a8, 5),
29 PORT(0x2b0, 5),
30 PORT(0x2b8, 5),
31 { },
32};
33
34static struct platform_device fourport_device = {
35 .name = "serial8250",
36 .id = PLAT8250_DEV_FOURPORT,
37 .dev = {
38 .platform_data = fourport_data,
39 },
40};
41
42static int __init fourport_init(void)
43{
44 return platform_device_register(&fourport_device);
45}
46
47module_init(fourport_init);
48
49MODULE_AUTHOR("Russell King");
50MODULE_DESCRIPTION("8250 serial probe module for AST Fourport cards");
51MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_gsc.c b/drivers/tty/serial/8250_gsc.c
new file mode 100644
index 00000000000..d8c0ffbfa6e
--- /dev/null
+++ b/drivers/tty/serial/8250_gsc.c
@@ -0,0 +1,122 @@
1/*
2 * Serial Device Initialisation for Lasi/Asp/Wax/Dino
3 *
4 * (c) Copyright Matthew Wilcox <willy@debian.org> 2001-2002
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/module.h>
17#include <linux/serial_core.h>
18#include <linux/signal.h>
19#include <linux/types.h>
20
21#include <asm/hardware.h>
22#include <asm/parisc-device.h>
23#include <asm/io.h>
24
25#include "8250.h"
26
27static int __init serial_init_chip(struct parisc_device *dev)
28{
29 struct uart_port port;
30 unsigned long address;
31 int err;
32
33 if (!dev->irq) {
34 /* We find some unattached serial ports by walking native
35 * busses. These should be silently ignored. Otherwise,
36 * what we have here is a missing parent device, so tell
37 * the user what they're missing.
38 */
39 if (parisc_parent(dev)->id.hw_type != HPHW_IOA)
40 printk(KERN_INFO
41 "Serial: device 0x%llx not configured.\n"
42 "Enable support for Wax, Lasi, Asp or Dino.\n",
43 (unsigned long long)dev->hpa.start);
44 return -ENODEV;
45 }
46
47 address = dev->hpa.start;
48 if (dev->id.sversion != 0x8d)
49 address += 0x800;
50
51 memset(&port, 0, sizeof(port));
52 port.iotype = UPIO_MEM;
53 /* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */
54 port.uartclk = 7272727;
55 port.mapbase = address;
56 port.membase = ioremap_nocache(address, 16);
57 port.irq = dev->irq;
58 port.flags = UPF_BOOT_AUTOCONF;
59 port.dev = &dev->dev;
60
61 err = serial8250_register_port(&port);
62 if (err < 0) {
63 printk(KERN_WARNING
64 "serial8250_register_port returned error %d\n", err);
65 iounmap(port.membase);
66 return err;
67 }
68
69 return 0;
70}
71
72static struct parisc_device_id serial_tbl[] = {
73 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00075 },
74 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008c },
75 { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008d },
76 { 0 }
77};
78
79/* Hack. Some machines have SERIAL_0 attached to Lasi and SERIAL_1
80 * attached to Dino. Unfortunately, Dino appears before Lasi in the device
81 * tree. To ensure that ttyS0 == SERIAL_0, we register two drivers; one
82 * which only knows about Lasi and then a second which will find all the
83 * other serial ports. HPUX ignores this problem.
84 */
85static struct parisc_device_id lasi_tbl[] = {
86 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03B, 0x0008C }, /* C1xx/C1xxL */
87 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03C, 0x0008C }, /* B132L */
88 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03D, 0x0008C }, /* B160L */
89 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03E, 0x0008C }, /* B132L+ */
90 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03F, 0x0008C }, /* B180L+ */
91 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x046, 0x0008C }, /* Rocky2 120 */
92 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x047, 0x0008C }, /* Rocky2 150 */
93 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x04E, 0x0008C }, /* Kiji L2 132 */
94 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x056, 0x0008C }, /* Raven+ */
95 { 0 }
96};
97
98
99MODULE_DEVICE_TABLE(parisc, serial_tbl);
100
101static struct parisc_driver lasi_driver = {
102 .name = "serial_1",
103 .id_table = lasi_tbl,
104 .probe = serial_init_chip,
105};
106
107static struct parisc_driver serial_driver = {
108 .name = "serial",
109 .id_table = serial_tbl,
110 .probe = serial_init_chip,
111};
112
113static int __init probe_serial_gsc(void)
114{
115 register_parisc_driver(&lasi_driver);
116 register_parisc_driver(&serial_driver);
117 return 0;
118}
119
120module_init(probe_serial_gsc);
121
122MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_hp300.c b/drivers/tty/serial/8250_hp300.c
new file mode 100644
index 00000000000..c13438c9301
--- /dev/null
+++ b/drivers/tty/serial/8250_hp300.c
@@ -0,0 +1,327 @@
1/*
2 * Driver for the 98626/98644/internal serial interface on hp300/hp400
3 * (based on the National Semiconductor INS8250/NS16550AF/WD16C552 UARTs)
4 *
5 * Ported from 2.2 and modified to use the normal 8250 driver
6 * by Kars de Jong <jongk@linux-m68k.org>, May 2004.
7 */
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/string.h>
11#include <linux/kernel.h>
12#include <linux/serial.h>
13#include <linux/serial_core.h>
14#include <linux/serial_8250.h>
15#include <linux/delay.h>
16#include <linux/dio.h>
17#include <linux/console.h>
18#include <linux/slab.h>
19#include <asm/io.h>
20
21#include "8250.h"
22
23#if !defined(CONFIG_HPDCA) && !defined(CONFIG_HPAPCI)
24#warning CONFIG_8250 defined but neither CONFIG_HPDCA nor CONFIG_HPAPCI defined, are you sure?
25#endif
26
27#ifdef CONFIG_HPAPCI
28struct hp300_port
29{
30 struct hp300_port *next; /* next port */
31 int line; /* line (tty) number */
32};
33
34static struct hp300_port *hp300_ports;
35#endif
36
37#ifdef CONFIG_HPDCA
38
39static int __devinit hpdca_init_one(struct dio_dev *d,
40 const struct dio_device_id *ent);
41static void __devexit hpdca_remove_one(struct dio_dev *d);
42
43static struct dio_device_id hpdca_dio_tbl[] = {
44 { DIO_ID_DCA0 },
45 { DIO_ID_DCA0REM },
46 { DIO_ID_DCA1 },
47 { DIO_ID_DCA1REM },
48 { 0 }
49};
50
51static struct dio_driver hpdca_driver = {
52 .name = "hpdca",
53 .id_table = hpdca_dio_tbl,
54 .probe = hpdca_init_one,
55 .remove = __devexit_p(hpdca_remove_one),
56};
57
58#endif
59
60static unsigned int num_ports;
61
62extern int hp300_uart_scode;
63
64/* Offset to UART registers from base of DCA */
65#define UART_OFFSET 17
66
67#define DCA_ID 0x01 /* ID (read), reset (write) */
68#define DCA_IC 0x03 /* Interrupt control */
69
70/* Interrupt control */
71#define DCA_IC_IE 0x80 /* Master interrupt enable */
72
73#define HPDCA_BAUD_BASE 153600
74
75/* Base address of the Frodo part */
76#define FRODO_BASE (0x41c000)
77
78/*
79 * Where we find the 8250-like APCI ports, and how far apart they are.
80 */
81#define FRODO_APCIBASE 0x0
82#define FRODO_APCISPACE 0x20
83#define FRODO_APCI_OFFSET(x) (FRODO_APCIBASE + ((x) * FRODO_APCISPACE))
84
85#define HPAPCI_BAUD_BASE 500400
86
87#ifdef CONFIG_SERIAL_8250_CONSOLE
88/*
89 * Parse the bootinfo to find descriptions for headless console and
90 * debug serial ports and register them with the 8250 driver.
91 * This function should be called before serial_console_init() is called
92 * to make sure the serial console will be available for use. IA-64 kernel
93 * calls this function from setup_arch() after the EFI and ACPI tables have
94 * been parsed.
95 */
96int __init hp300_setup_serial_console(void)
97{
98 int scode;
99 struct uart_port port;
100
101 memset(&port, 0, sizeof(port));
102
103 if (hp300_uart_scode < 0 || hp300_uart_scode > DIO_SCMAX)
104 return 0;
105
106 if (DIO_SCINHOLE(hp300_uart_scode))
107 return 0;
108
109 scode = hp300_uart_scode;
110
111 /* Memory mapped I/O */
112 port.iotype = UPIO_MEM;
113 port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
114 port.type = PORT_UNKNOWN;
115
116 /* Check for APCI console */
117 if (scode == 256) {
118#ifdef CONFIG_HPAPCI
119 printk(KERN_INFO "Serial console is HP APCI 1\n");
120
121 port.uartclk = HPAPCI_BAUD_BASE * 16;
122 port.mapbase = (FRODO_BASE + FRODO_APCI_OFFSET(1));
123 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
124 port.regshift = 2;
125 add_preferred_console("ttyS", port.line, "9600n8");
126#else
127 printk(KERN_WARNING "Serial console is APCI but support is disabled (CONFIG_HPAPCI)!\n");
128 return 0;
129#endif
130 } else {
131#ifdef CONFIG_HPDCA
132 unsigned long pa = dio_scodetophysaddr(scode);
133 if (!pa)
134 return 0;
135
136 printk(KERN_INFO "Serial console is HP DCA at select code %d\n", scode);
137
138 port.uartclk = HPDCA_BAUD_BASE * 16;
139 port.mapbase = (pa + UART_OFFSET);
140 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
141 port.regshift = 1;
142 port.irq = DIO_IPL(pa + DIO_VIRADDRBASE);
143
144 /* Enable board-interrupts */
145 out_8(pa + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
146
147 if (DIO_ID(pa + DIO_VIRADDRBASE) & 0x80)
148 add_preferred_console("ttyS", port.line, "9600n8");
149#else
150 printk(KERN_WARNING "Serial console is DCA but support is disabled (CONFIG_HPDCA)!\n");
151 return 0;
152#endif
153 }
154
155 if (early_serial_setup(&port) < 0)
156 printk(KERN_WARNING "hp300_setup_serial_console(): early_serial_setup() failed.\n");
157 return 0;
158}
159#endif /* CONFIG_SERIAL_8250_CONSOLE */
160
161#ifdef CONFIG_HPDCA
162static int __devinit hpdca_init_one(struct dio_dev *d,
163 const struct dio_device_id *ent)
164{
165 struct uart_port port;
166 int line;
167
168#ifdef CONFIG_SERIAL_8250_CONSOLE
169 if (hp300_uart_scode == d->scode) {
170 /* Already got it. */
171 return 0;
172 }
173#endif
174 memset(&port, 0, sizeof(struct uart_port));
175
176 /* Memory mapped I/O */
177 port.iotype = UPIO_MEM;
178 port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
179 port.irq = d->ipl;
180 port.uartclk = HPDCA_BAUD_BASE * 16;
181 port.mapbase = (d->resource.start + UART_OFFSET);
182 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
183 port.regshift = 1;
184 port.dev = &d->dev;
185 line = serial8250_register_port(&port);
186
187 if (line < 0) {
188 printk(KERN_NOTICE "8250_hp300: register_serial() DCA scode %d"
189 " irq %d failed\n", d->scode, port.irq);
190 return -ENOMEM;
191 }
192
193 /* Enable board-interrupts */
194 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
195 dio_set_drvdata(d, (void *)line);
196
197 /* Reset the DCA */
198 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff);
199 udelay(100);
200
201 num_ports++;
202
203 return 0;
204}
205#endif
206
207static int __init hp300_8250_init(void)
208{
209 static int called;
210#ifdef CONFIG_HPAPCI
211 int line;
212 unsigned long base;
213 struct uart_port uport;
214 struct hp300_port *port;
215 int i;
216#endif
217 if (called)
218 return -ENODEV;
219 called = 1;
220
221 if (!MACH_IS_HP300)
222 return -ENODEV;
223
224#ifdef CONFIG_HPDCA
225 dio_register_driver(&hpdca_driver);
226#endif
227#ifdef CONFIG_HPAPCI
228 if (hp300_model < HP_400) {
229 if (!num_ports)
230 return -ENODEV;
231 return 0;
232 }
233 /* These models have the Frodo chip.
234 * Port 0 is reserved for the Apollo Domain keyboard.
235 * Port 1 is either the console or the DCA.
236 */
237 for (i = 1; i < 4; i++) {
238 /* Port 1 is the console on a 425e, on other machines it's
239 * mapped to DCA.
240 */
241#ifdef CONFIG_SERIAL_8250_CONSOLE
242 if (i == 1)
243 continue;
244#endif
245
246 /* Create new serial device */
247 port = kmalloc(sizeof(struct hp300_port), GFP_KERNEL);
248 if (!port)
249 return -ENOMEM;
250
251 memset(&uport, 0, sizeof(struct uart_port));
252
253 base = (FRODO_BASE + FRODO_APCI_OFFSET(i));
254
255 /* Memory mapped I/O */
256 uport.iotype = UPIO_MEM;
257 uport.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ \
258 | UPF_BOOT_AUTOCONF;
259 /* XXX - no interrupt support yet */
260 uport.irq = 0;
261 uport.uartclk = HPAPCI_BAUD_BASE * 16;
262 uport.mapbase = base;
263 uport.membase = (char *)(base + DIO_VIRADDRBASE);
264 uport.regshift = 2;
265
266 line = serial8250_register_port(&uport);
267
268 if (line < 0) {
269 printk(KERN_NOTICE "8250_hp300: register_serial() APCI"
270 " %d irq %d failed\n", i, uport.irq);
271 kfree(port);
272 continue;
273 }
274
275 port->line = line;
276 port->next = hp300_ports;
277 hp300_ports = port;
278
279 num_ports++;
280 }
281#endif
282
283 /* Any boards found? */
284 if (!num_ports)
285 return -ENODEV;
286
287 return 0;
288}
289
290#ifdef CONFIG_HPDCA
291static void __devexit hpdca_remove_one(struct dio_dev *d)
292{
293 int line;
294
295 line = (int) dio_get_drvdata(d);
296 if (d->resource.start) {
297 /* Disable board-interrupts */
298 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, 0);
299 }
300 serial8250_unregister_port(line);
301}
302#endif
303
304static void __exit hp300_8250_exit(void)
305{
306#ifdef CONFIG_HPAPCI
307 struct hp300_port *port, *to_free;
308
309 for (port = hp300_ports; port; ) {
310 serial8250_unregister_port(port->line);
311 to_free = port;
312 port = port->next;
313 kfree(to_free);
314 }
315
316 hp300_ports = NULL;
317#endif
318#ifdef CONFIG_HPDCA
319 dio_unregister_driver(&hpdca_driver);
320#endif
321}
322
323module_init(hp300_8250_init);
324module_exit(hp300_8250_exit);
325MODULE_DESCRIPTION("HP DCA/APCI serial driver");
326MODULE_AUTHOR("Kars de Jong <jongk@linux-m68k.org>");
327MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_hub6.c b/drivers/tty/serial/8250_hub6.c
new file mode 100644
index 00000000000..a5c778e83de
--- /dev/null
+++ b/drivers/tty/serial/8250_hub6.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial_8250.h>
12
13#define HUB6(card,port) \
14 { \
15 .iobase = 0x302, \
16 .irq = 3, \
17 .uartclk = 1843200, \
18 .iotype = UPIO_HUB6, \
19 .flags = UPF_BOOT_AUTOCONF, \
20 .hub6 = (card) << 6 | (port) << 3 | 1, \
21 }
22
23static struct plat_serial8250_port hub6_data[] = {
24 HUB6(0, 0),
25 HUB6(0, 1),
26 HUB6(0, 2),
27 HUB6(0, 3),
28 HUB6(0, 4),
29 HUB6(0, 5),
30 HUB6(1, 0),
31 HUB6(1, 1),
32 HUB6(1, 2),
33 HUB6(1, 3),
34 HUB6(1, 4),
35 HUB6(1, 5),
36 { },
37};
38
39static struct platform_device hub6_device = {
40 .name = "serial8250",
41 .id = PLAT8250_DEV_HUB6,
42 .dev = {
43 .platform_data = hub6_data,
44 },
45};
46
47static int __init hub6_init(void)
48{
49 return platform_device_register(&hub6_device);
50}
51
52module_init(hub6_init);
53
54MODULE_AUTHOR("Russell King");
55MODULE_DESCRIPTION("8250 serial probe module for Hub6 cards");
56MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_mca.c b/drivers/tty/serial/8250_mca.c
new file mode 100644
index 00000000000..d20abf04541
--- /dev/null
+++ b/drivers/tty/serial/8250_mca.c
@@ -0,0 +1,61 @@
1/*
2 * Copyright (C) 2005 Russell King.
3 * Data taken from include/asm-i386/serial.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/mca.h>
12#include <linux/serial_8250.h>
13
14/*
15 * FIXME: Should we be doing AUTO_IRQ here?
16 */
17#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
18#define MCA_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ
19#else
20#define MCA_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
21#endif
22
23#define PORT(_base,_irq) \
24 { \
25 .iobase = _base, \
26 .irq = _irq, \
27 .uartclk = 1843200, \
28 .iotype = UPIO_PORT, \
29 .flags = MCA_FLAGS, \
30 }
31
32static struct plat_serial8250_port mca_data[] = {
33 PORT(0x3220, 3),
34 PORT(0x3228, 3),
35 PORT(0x4220, 3),
36 PORT(0x4228, 3),
37 PORT(0x5220, 3),
38 PORT(0x5228, 3),
39 { },
40};
41
42static struct platform_device mca_device = {
43 .name = "serial8250",
44 .id = PLAT8250_DEV_MCA,
45 .dev = {
46 .platform_data = mca_data,
47 },
48};
49
50static int __init mca_init(void)
51{
52 if (!MCA_bus)
53 return -ENODEV;
54 return platform_device_register(&mca_device);
55}
56
57module_init(mca_init);
58
59MODULE_AUTHOR("Russell King");
60MODULE_DESCRIPTION("8250 serial probe module for MCA ports");
61MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_pci.c b/drivers/tty/serial/8250_pci.c
new file mode 100644
index 00000000000..3abeca2a2a1
--- /dev/null
+++ b/drivers/tty/serial/8250_pci.c
@@ -0,0 +1,4136 @@
1/*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <linux/8250_pci.h>
22#include <linux/bitops.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28
29#undef SERIAL_DEBUG_PCI
30
31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
42 int (*probe)(struct pci_dev *dev);
43 int (*init)(struct pci_dev *dev);
44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
46 struct uart_port *, int);
47 void (*exit)(struct pci_dev *dev);
48};
49
50#define PCI_NUM_BAR_RESOURCES 6
51
52struct serial_private {
53 struct pci_dev *dev;
54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58};
59
60static int pci_default_setup(struct serial_private*,
61 const struct pciserial_board*, struct uart_port*, int);
62
63static void moan_device(const char *str, struct pci_dev *dev)
64{
65 printk(KERN_WARNING
66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73}
74
75static int
76setup_port(struct serial_private *priv, struct uart_port *port,
77 int bar, int offset, int regshift)
78{
79 struct pci_dev *dev = priv->dev;
80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
85 base = pci_resource_start(dev, bar);
86
87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
95 port->iotype = UPIO_MEM;
96 port->iobase = 0;
97 port->mapbase = base + offset;
98 port->membase = priv->remapped_bar[bar] + offset;
99 port->regshift = regshift;
100 } else {
101 port->iotype = UPIO_PORT;
102 port->iobase = base + offset;
103 port->mapbase = 0;
104 port->membase = NULL;
105 port->regshift = 0;
106 }
107 return 0;
108}
109
110/*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113static int addidata_apci7800_setup(struct serial_private *priv,
114 const struct pciserial_board *board,
115 struct uart_port *port, int idx)
116{
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134}
135
136/*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140static int
141afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
142 struct uart_port *port, int idx)
143{
144 unsigned int bar, offset = board->first_offset;
145
146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
154 return setup_port(priv, port, bar, offset, board->reg_shift);
155}
156
157/*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
164static int pci_hp_diva_init(struct pci_dev *dev)
165{
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
183 rc = 1;
184 break;
185 }
186
187 return rc;
188}
189
190/*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194static int
195pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
197 struct uart_port *port, int idx)
198{
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
202 switch (priv->dev->subsystem_device) {
203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
219 return setup_port(priv, port, bar, offset, board->reg_shift);
220}
221
222/*
223 * Added for EKF Intel i960 serial boards
224 */
225static int pci_inteli960ni_init(struct pci_dev *dev)
226{
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239}
240
241/*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
247static int pci_plx9050_init(struct pci_dev *dev)
248{
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260 irq_config = 0x43;
261
262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
273 /*
274 * enable/disable interrupts
275 */
276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288}
289
290static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291{
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310}
311
312#define NI8420_INT_ENABLE_REG 0x38
313#define NI8420_INT_ENABLE_BIT 0x2000
314
315static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316{
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336}
337
338
339/* MITE registers */
340#define MITE_IOWBSR1 0xc4
341#define MITE_IOWCR1 0xf4
342#define MITE_LCIMR1 0x08
343#define MITE_LCIMR2 0x10
344
345#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
347static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348{
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367}
368
369/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370static int
371sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
372 struct uart_port *port, int idx)
373{
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
387 return setup_port(priv, port, bar, offset, board->reg_shift);
388}
389
390/*
391* This does initialization for PMC OCTALPRO cards:
392* maps the device memory, resets the UARTs (needed, bc
393* if the module is removed and inserted again, the card
394* is in the sleep mode) and enables global interrupt.
395*/
396
397/* global control register offset for SBS PMC-OctalPro */
398#define OCT_REG_CR_OFF 0x500
399
400static int sbs_init(struct pci_dev *dev)
401{
402 u8 __iomem *p;
403
404 p = pci_ioremap_bar(dev, 0);
405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
409 writeb(0x10, p + OCT_REG_CR_OFF);
410 udelay(50);
411 writeb(0x0, p + OCT_REG_CR_OFF);
412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418}
419
420/*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424static void __devexit sbs_exit(struct pci_dev *dev)
425{
426 u8 __iomem *p;
427
428 p = pci_ioremap_bar(dev, 0);
429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
431 writeb(0, p + OCT_REG_CR_OFF);
432 iounmap(p);
433}
434
435/*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
438 * (except cards equipped with 4 UARTs) and initial clocking settings
439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447 *
448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465static int pci_siig10x_init(struct pci_dev *dev)
466{
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490}
491
492#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495static int pci_siig20x_init(struct pci_dev *dev)
496{
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510}
511
512static int pci_siig_init(struct pci_dev *dev)
513{
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523}
524
525static int pci_siig_setup(struct serial_private *priv,
526 const struct pciserial_board *board,
527 struct uart_port *port, int idx)
528{
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537}
538
539/*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
544static const unsigned short timedia_single_port[] = {
545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546};
547
548static const unsigned short timedia_dual_port[] = {
549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554};
555
556static const unsigned short timedia_quad_port[] = {
557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561};
562
563static const unsigned short timedia_eight_port[] = {
564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566};
567
568static const struct timedia_struct {
569 int num;
570 const unsigned short *ids;
571} timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
575 { 8, timedia_eight_port }
576};
577
578/*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584static int pci_timedia_probe(struct pci_dev *dev)
585{
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598}
599
600static int pci_timedia_init(struct pci_dev *dev)
601{
602 const unsigned short *ids;
603 int i, j;
604
605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612}
613
614/*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618static int
619pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
621 struct uart_port *port, int idx)
622{
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
638 /* FALLTHROUGH */
639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
646 return setup_port(priv, port, bar, offset, board->reg_shift);
647}
648
649/*
650 * Some Titan cards are also a little weird
651 */
652static int
653titan_400l_800l_setup(struct serial_private *priv,
654 const struct pciserial_board *board,
655 struct uart_port *port, int idx)
656{
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
671 return setup_port(priv, port, bar, offset, board->reg_shift);
672}
673
674static int pci_xircom_init(struct pci_dev *dev)
675{
676 msleep(100);
677 return 0;
678}
679
680static int pci_ni8420_init(struct pci_dev *dev)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703}
704
705#define MITE_IOWBSR1_WSIZE 0xa
706#define MITE_IOWBSR1_WIN_OFFSET 0x800
707#define MITE_IOWBSR1_WENAB (1 << 7)
708#define MITE_LCIMR1_IO_IE_0 (1 << 24)
709#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712static int pci_ni8430_init(struct pci_dev *dev)
713{
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747}
748
749/* UART Port Control Register */
750#define NI8430_PORTCON 0x0f
751#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753static int
754pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
756 struct uart_port *port, int idx)
757{
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
772 /* enable the transceiver */
773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779}
780
781static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_port *port, int idx)
784{
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
837
838static int pci_netmos_init(struct pci_dev *dev)
839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
845 return 0;
846
847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
865 if (num_serial == 0)
866 return -ENODEV;
867
868 return num_serial;
869}
870
871/*
872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
899static int pci_ite887x_init(struct pci_dev *dev)
900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 printk(KERN_ERR "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
993static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 printk(KERN_DEBUG
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
1034static int
1035pci_default_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_port *port, int idx)
1038{
1039 unsigned int bar, offset = board->first_offset, maxnr;
1040
1041 bar = FL_GET_BASE(board->flags);
1042 if (board->flags & FL_BASE_BARS)
1043 bar += idx;
1044 else
1045 offset += idx * board->uart_offset;
1046
1047 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048 (board->reg_shift + 3);
1049
1050 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051 return 1;
1052
1053 return setup_port(priv, port, bar, offset, board->reg_shift);
1054}
1055
1056static int
1057ce4100_serial_setup(struct serial_private *priv,
1058 const struct pciserial_board *board,
1059 struct uart_port *port, int idx)
1060{
1061 int ret;
1062
1063 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064 port->iotype = UPIO_MEM32;
1065 port->type = PORT_XSCALE;
1066 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067 port->regshift = 2;
1068
1069 return ret;
1070}
1071
1072static int
1073pci_omegapci_setup(struct serial_private *priv,
1074 const struct pciserial_board *board,
1075 struct uart_port *port, int idx)
1076{
1077 return setup_port(priv, port, 2, idx * 8, 0);
1078}
1079
1080static int skip_tx_en_setup(struct serial_private *priv,
1081 const struct pciserial_board *board,
1082 struct uart_port *port, int idx)
1083{
1084 port->flags |= UPF_NO_TXEN_TEST;
1085 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086 "[%04x:%04x] subsystem [%04x:%04x]\n",
1087 priv->dev->vendor,
1088 priv->dev->device,
1089 priv->dev->subsystem_vendor,
1090 priv->dev->subsystem_device);
1091
1092 return pci_default_setup(priv, board, port, idx);
1093}
1094
1095static int pci_eg20t_init(struct pci_dev *dev)
1096{
1097#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1098 return -ENODEV;
1099#else
1100 return 0;
1101#endif
1102}
1103
1104/* This should be in linux/pci_ids.h */
1105#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1106#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1107#define PCI_DEVICE_ID_OCTPRO 0x0001
1108#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1109#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1110#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1111#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1112#define PCI_VENDOR_ID_ADVANTECH 0x13fe
1113#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1114#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1115#define PCI_DEVICE_ID_TITAN_200I 0x8028
1116#define PCI_DEVICE_ID_TITAN_400I 0x8048
1117#define PCI_DEVICE_ID_TITAN_800I 0x8088
1118#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1119#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1120#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1121#define PCI_DEVICE_ID_TITAN_100E 0xA010
1122#define PCI_DEVICE_ID_TITAN_200E 0xA012
1123#define PCI_DEVICE_ID_TITAN_400E 0xA013
1124#define PCI_DEVICE_ID_TITAN_800E 0xA014
1125#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1126#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1127#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1128#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1129#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1130
1131/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1132#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1133
1134/*
1135 * Master list of serial port init/setup/exit quirks.
1136 * This does not describe the general nature of the port.
1137 * (ie, baud base, number and location of ports, etc)
1138 *
1139 * This list is ordered alphabetically by vendor then device.
1140 * Specific entries must come before more generic entries.
1141 */
1142static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1143 /*
1144 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1145 */
1146 {
1147 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1148 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1149 .subvendor = PCI_ANY_ID,
1150 .subdevice = PCI_ANY_ID,
1151 .setup = addidata_apci7800_setup,
1152 },
1153 /*
1154 * AFAVLAB cards - these may be called via parport_serial
1155 * It is not clear whether this applies to all products.
1156 */
1157 {
1158 .vendor = PCI_VENDOR_ID_AFAVLAB,
1159 .device = PCI_ANY_ID,
1160 .subvendor = PCI_ANY_ID,
1161 .subdevice = PCI_ANY_ID,
1162 .setup = afavlab_setup,
1163 },
1164 /*
1165 * HP Diva
1166 */
1167 {
1168 .vendor = PCI_VENDOR_ID_HP,
1169 .device = PCI_DEVICE_ID_HP_DIVA,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .init = pci_hp_diva_init,
1173 .setup = pci_hp_diva_setup,
1174 },
1175 /*
1176 * Intel
1177 */
1178 {
1179 .vendor = PCI_VENDOR_ID_INTEL,
1180 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1181 .subvendor = 0xe4bf,
1182 .subdevice = PCI_ANY_ID,
1183 .init = pci_inteli960ni_init,
1184 .setup = pci_default_setup,
1185 },
1186 {
1187 .vendor = PCI_VENDOR_ID_INTEL,
1188 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1189 .subvendor = PCI_ANY_ID,
1190 .subdevice = PCI_ANY_ID,
1191 .setup = skip_tx_en_setup,
1192 },
1193 {
1194 .vendor = PCI_VENDOR_ID_INTEL,
1195 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1196 .subvendor = PCI_ANY_ID,
1197 .subdevice = PCI_ANY_ID,
1198 .setup = skip_tx_en_setup,
1199 },
1200 {
1201 .vendor = PCI_VENDOR_ID_INTEL,
1202 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1203 .subvendor = PCI_ANY_ID,
1204 .subdevice = PCI_ANY_ID,
1205 .setup = skip_tx_en_setup,
1206 },
1207 {
1208 .vendor = PCI_VENDOR_ID_INTEL,
1209 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1210 .subvendor = PCI_ANY_ID,
1211 .subdevice = PCI_ANY_ID,
1212 .setup = ce4100_serial_setup,
1213 },
1214 /*
1215 * ITE
1216 */
1217 {
1218 .vendor = PCI_VENDOR_ID_ITE,
1219 .device = PCI_DEVICE_ID_ITE_8872,
1220 .subvendor = PCI_ANY_ID,
1221 .subdevice = PCI_ANY_ID,
1222 .init = pci_ite887x_init,
1223 .setup = pci_default_setup,
1224 .exit = __devexit_p(pci_ite887x_exit),
1225 },
1226 /*
1227 * National Instruments
1228 */
1229 {
1230 .vendor = PCI_VENDOR_ID_NI,
1231 .device = PCI_DEVICE_ID_NI_PCI23216,
1232 .subvendor = PCI_ANY_ID,
1233 .subdevice = PCI_ANY_ID,
1234 .init = pci_ni8420_init,
1235 .setup = pci_default_setup,
1236 .exit = __devexit_p(pci_ni8420_exit),
1237 },
1238 {
1239 .vendor = PCI_VENDOR_ID_NI,
1240 .device = PCI_DEVICE_ID_NI_PCI2328,
1241 .subvendor = PCI_ANY_ID,
1242 .subdevice = PCI_ANY_ID,
1243 .init = pci_ni8420_init,
1244 .setup = pci_default_setup,
1245 .exit = __devexit_p(pci_ni8420_exit),
1246 },
1247 {
1248 .vendor = PCI_VENDOR_ID_NI,
1249 .device = PCI_DEVICE_ID_NI_PCI2324,
1250 .subvendor = PCI_ANY_ID,
1251 .subdevice = PCI_ANY_ID,
1252 .init = pci_ni8420_init,
1253 .setup = pci_default_setup,
1254 .exit = __devexit_p(pci_ni8420_exit),
1255 },
1256 {
1257 .vendor = PCI_VENDOR_ID_NI,
1258 .device = PCI_DEVICE_ID_NI_PCI2322,
1259 .subvendor = PCI_ANY_ID,
1260 .subdevice = PCI_ANY_ID,
1261 .init = pci_ni8420_init,
1262 .setup = pci_default_setup,
1263 .exit = __devexit_p(pci_ni8420_exit),
1264 },
1265 {
1266 .vendor = PCI_VENDOR_ID_NI,
1267 .device = PCI_DEVICE_ID_NI_PCI2324I,
1268 .subvendor = PCI_ANY_ID,
1269 .subdevice = PCI_ANY_ID,
1270 .init = pci_ni8420_init,
1271 .setup = pci_default_setup,
1272 .exit = __devexit_p(pci_ni8420_exit),
1273 },
1274 {
1275 .vendor = PCI_VENDOR_ID_NI,
1276 .device = PCI_DEVICE_ID_NI_PCI2322I,
1277 .subvendor = PCI_ANY_ID,
1278 .subdevice = PCI_ANY_ID,
1279 .init = pci_ni8420_init,
1280 .setup = pci_default_setup,
1281 .exit = __devexit_p(pci_ni8420_exit),
1282 },
1283 {
1284 .vendor = PCI_VENDOR_ID_NI,
1285 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1286 .subvendor = PCI_ANY_ID,
1287 .subdevice = PCI_ANY_ID,
1288 .init = pci_ni8420_init,
1289 .setup = pci_default_setup,
1290 .exit = __devexit_p(pci_ni8420_exit),
1291 },
1292 {
1293 .vendor = PCI_VENDOR_ID_NI,
1294 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1295 .subvendor = PCI_ANY_ID,
1296 .subdevice = PCI_ANY_ID,
1297 .init = pci_ni8420_init,
1298 .setup = pci_default_setup,
1299 .exit = __devexit_p(pci_ni8420_exit),
1300 },
1301 {
1302 .vendor = PCI_VENDOR_ID_NI,
1303 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1304 .subvendor = PCI_ANY_ID,
1305 .subdevice = PCI_ANY_ID,
1306 .init = pci_ni8420_init,
1307 .setup = pci_default_setup,
1308 .exit = __devexit_p(pci_ni8420_exit),
1309 },
1310 {
1311 .vendor = PCI_VENDOR_ID_NI,
1312 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1313 .subvendor = PCI_ANY_ID,
1314 .subdevice = PCI_ANY_ID,
1315 .init = pci_ni8420_init,
1316 .setup = pci_default_setup,
1317 .exit = __devexit_p(pci_ni8420_exit),
1318 },
1319 {
1320 .vendor = PCI_VENDOR_ID_NI,
1321 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1322 .subvendor = PCI_ANY_ID,
1323 .subdevice = PCI_ANY_ID,
1324 .init = pci_ni8420_init,
1325 .setup = pci_default_setup,
1326 .exit = __devexit_p(pci_ni8420_exit),
1327 },
1328 {
1329 .vendor = PCI_VENDOR_ID_NI,
1330 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1331 .subvendor = PCI_ANY_ID,
1332 .subdevice = PCI_ANY_ID,
1333 .init = pci_ni8420_init,
1334 .setup = pci_default_setup,
1335 .exit = __devexit_p(pci_ni8420_exit),
1336 },
1337 {
1338 .vendor = PCI_VENDOR_ID_NI,
1339 .device = PCI_ANY_ID,
1340 .subvendor = PCI_ANY_ID,
1341 .subdevice = PCI_ANY_ID,
1342 .init = pci_ni8430_init,
1343 .setup = pci_ni8430_setup,
1344 .exit = __devexit_p(pci_ni8430_exit),
1345 },
1346 /*
1347 * Panacom
1348 */
1349 {
1350 .vendor = PCI_VENDOR_ID_PANACOM,
1351 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1352 .subvendor = PCI_ANY_ID,
1353 .subdevice = PCI_ANY_ID,
1354 .init = pci_plx9050_init,
1355 .setup = pci_default_setup,
1356 .exit = __devexit_p(pci_plx9050_exit),
1357 },
1358 {
1359 .vendor = PCI_VENDOR_ID_PANACOM,
1360 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1361 .subvendor = PCI_ANY_ID,
1362 .subdevice = PCI_ANY_ID,
1363 .init = pci_plx9050_init,
1364 .setup = pci_default_setup,
1365 .exit = __devexit_p(pci_plx9050_exit),
1366 },
1367 /*
1368 * PLX
1369 */
1370 {
1371 .vendor = PCI_VENDOR_ID_PLX,
1372 .device = PCI_DEVICE_ID_PLX_9030,
1373 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1374 .subdevice = PCI_ANY_ID,
1375 .setup = pci_default_setup,
1376 },
1377 {
1378 .vendor = PCI_VENDOR_ID_PLX,
1379 .device = PCI_DEVICE_ID_PLX_9050,
1380 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1381 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1382 .init = pci_plx9050_init,
1383 .setup = pci_default_setup,
1384 .exit = __devexit_p(pci_plx9050_exit),
1385 },
1386 {
1387 .vendor = PCI_VENDOR_ID_PLX,
1388 .device = PCI_DEVICE_ID_PLX_9050,
1389 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1390 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1391 .init = pci_plx9050_init,
1392 .setup = pci_default_setup,
1393 .exit = __devexit_p(pci_plx9050_exit),
1394 },
1395 {
1396 .vendor = PCI_VENDOR_ID_PLX,
1397 .device = PCI_DEVICE_ID_PLX_9050,
1398 .subvendor = PCI_VENDOR_ID_PLX,
1399 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1400 .init = pci_plx9050_init,
1401 .setup = pci_default_setup,
1402 .exit = __devexit_p(pci_plx9050_exit),
1403 },
1404 {
1405 .vendor = PCI_VENDOR_ID_PLX,
1406 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1407 .subvendor = PCI_VENDOR_ID_PLX,
1408 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1409 .init = pci_plx9050_init,
1410 .setup = pci_default_setup,
1411 .exit = __devexit_p(pci_plx9050_exit),
1412 },
1413 /*
1414 * SBS Technologies, Inc., PMC-OCTALPRO 232
1415 */
1416 {
1417 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1418 .device = PCI_DEVICE_ID_OCTPRO,
1419 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1420 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1421 .init = sbs_init,
1422 .setup = sbs_setup,
1423 .exit = __devexit_p(sbs_exit),
1424 },
1425 /*
1426 * SBS Technologies, Inc., PMC-OCTALPRO 422
1427 */
1428 {
1429 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1430 .device = PCI_DEVICE_ID_OCTPRO,
1431 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1432 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1433 .init = sbs_init,
1434 .setup = sbs_setup,
1435 .exit = __devexit_p(sbs_exit),
1436 },
1437 /*
1438 * SBS Technologies, Inc., P-Octal 232
1439 */
1440 {
1441 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1442 .device = PCI_DEVICE_ID_OCTPRO,
1443 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1444 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1445 .init = sbs_init,
1446 .setup = sbs_setup,
1447 .exit = __devexit_p(sbs_exit),
1448 },
1449 /*
1450 * SBS Technologies, Inc., P-Octal 422
1451 */
1452 {
1453 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1454 .device = PCI_DEVICE_ID_OCTPRO,
1455 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1456 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1457 .init = sbs_init,
1458 .setup = sbs_setup,
1459 .exit = __devexit_p(sbs_exit),
1460 },
1461 /*
1462 * SIIG cards - these may be called via parport_serial
1463 */
1464 {
1465 .vendor = PCI_VENDOR_ID_SIIG,
1466 .device = PCI_ANY_ID,
1467 .subvendor = PCI_ANY_ID,
1468 .subdevice = PCI_ANY_ID,
1469 .init = pci_siig_init,
1470 .setup = pci_siig_setup,
1471 },
1472 /*
1473 * Titan cards
1474 */
1475 {
1476 .vendor = PCI_VENDOR_ID_TITAN,
1477 .device = PCI_DEVICE_ID_TITAN_400L,
1478 .subvendor = PCI_ANY_ID,
1479 .subdevice = PCI_ANY_ID,
1480 .setup = titan_400l_800l_setup,
1481 },
1482 {
1483 .vendor = PCI_VENDOR_ID_TITAN,
1484 .device = PCI_DEVICE_ID_TITAN_800L,
1485 .subvendor = PCI_ANY_ID,
1486 .subdevice = PCI_ANY_ID,
1487 .setup = titan_400l_800l_setup,
1488 },
1489 /*
1490 * Timedia cards
1491 */
1492 {
1493 .vendor = PCI_VENDOR_ID_TIMEDIA,
1494 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1495 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1496 .subdevice = PCI_ANY_ID,
1497 .probe = pci_timedia_probe,
1498 .init = pci_timedia_init,
1499 .setup = pci_timedia_setup,
1500 },
1501 {
1502 .vendor = PCI_VENDOR_ID_TIMEDIA,
1503 .device = PCI_ANY_ID,
1504 .subvendor = PCI_ANY_ID,
1505 .subdevice = PCI_ANY_ID,
1506 .setup = pci_timedia_setup,
1507 },
1508 /*
1509 * Xircom cards
1510 */
1511 {
1512 .vendor = PCI_VENDOR_ID_XIRCOM,
1513 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1514 .subvendor = PCI_ANY_ID,
1515 .subdevice = PCI_ANY_ID,
1516 .init = pci_xircom_init,
1517 .setup = pci_default_setup,
1518 },
1519 /*
1520 * Netmos cards - these may be called via parport_serial
1521 */
1522 {
1523 .vendor = PCI_VENDOR_ID_NETMOS,
1524 .device = PCI_ANY_ID,
1525 .subvendor = PCI_ANY_ID,
1526 .subdevice = PCI_ANY_ID,
1527 .init = pci_netmos_init,
1528 .setup = pci_netmos_9900_setup,
1529 },
1530 /*
1531 * For Oxford Semiconductor Tornado based devices
1532 */
1533 {
1534 .vendor = PCI_VENDOR_ID_OXSEMI,
1535 .device = PCI_ANY_ID,
1536 .subvendor = PCI_ANY_ID,
1537 .subdevice = PCI_ANY_ID,
1538 .init = pci_oxsemi_tornado_init,
1539 .setup = pci_default_setup,
1540 },
1541 {
1542 .vendor = PCI_VENDOR_ID_MAINPINE,
1543 .device = PCI_ANY_ID,
1544 .subvendor = PCI_ANY_ID,
1545 .subdevice = PCI_ANY_ID,
1546 .init = pci_oxsemi_tornado_init,
1547 .setup = pci_default_setup,
1548 },
1549 {
1550 .vendor = PCI_VENDOR_ID_DIGI,
1551 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1552 .subvendor = PCI_SUBVENDOR_ID_IBM,
1553 .subdevice = PCI_ANY_ID,
1554 .init = pci_oxsemi_tornado_init,
1555 .setup = pci_default_setup,
1556 },
1557 {
1558 .vendor = PCI_VENDOR_ID_INTEL,
1559 .device = 0x8811,
1560 .init = pci_eg20t_init,
1561 },
1562 {
1563 .vendor = PCI_VENDOR_ID_INTEL,
1564 .device = 0x8812,
1565 .init = pci_eg20t_init,
1566 },
1567 {
1568 .vendor = PCI_VENDOR_ID_INTEL,
1569 .device = 0x8813,
1570 .init = pci_eg20t_init,
1571 },
1572 {
1573 .vendor = PCI_VENDOR_ID_INTEL,
1574 .device = 0x8814,
1575 .init = pci_eg20t_init,
1576 },
1577 {
1578 .vendor = 0x10DB,
1579 .device = 0x8027,
1580 .init = pci_eg20t_init,
1581 },
1582 {
1583 .vendor = 0x10DB,
1584 .device = 0x8028,
1585 .init = pci_eg20t_init,
1586 },
1587 {
1588 .vendor = 0x10DB,
1589 .device = 0x8029,
1590 .init = pci_eg20t_init,
1591 },
1592 {
1593 .vendor = 0x10DB,
1594 .device = 0x800C,
1595 .init = pci_eg20t_init,
1596 },
1597 {
1598 .vendor = 0x10DB,
1599 .device = 0x800D,
1600 .init = pci_eg20t_init,
1601 },
1602 /*
1603 * Cronyx Omega PCI (PLX-chip based)
1604 */
1605 {
1606 .vendor = PCI_VENDOR_ID_PLX,
1607 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1608 .subvendor = PCI_ANY_ID,
1609 .subdevice = PCI_ANY_ID,
1610 .setup = pci_omegapci_setup,
1611 },
1612 /*
1613 * Default "match everything" terminator entry
1614 */
1615 {
1616 .vendor = PCI_ANY_ID,
1617 .device = PCI_ANY_ID,
1618 .subvendor = PCI_ANY_ID,
1619 .subdevice = PCI_ANY_ID,
1620 .setup = pci_default_setup,
1621 }
1622};
1623
1624static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1625{
1626 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1627}
1628
1629static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1630{
1631 struct pci_serial_quirk *quirk;
1632
1633 for (quirk = pci_serial_quirks; ; quirk++)
1634 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1635 quirk_id_matches(quirk->device, dev->device) &&
1636 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1637 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1638 break;
1639 return quirk;
1640}
1641
1642static inline int get_pci_irq(struct pci_dev *dev,
1643 const struct pciserial_board *board)
1644{
1645 if (board->flags & FL_NOIRQ)
1646 return 0;
1647 else
1648 return dev->irq;
1649}
1650
1651/*
1652 * This is the configuration table for all of the PCI serial boards
1653 * which we support. It is directly indexed by the pci_board_num_t enum
1654 * value, which is encoded in the pci_device_id PCI probe table's
1655 * driver_data member.
1656 *
1657 * The makeup of these names are:
1658 * pbn_bn{_bt}_n_baud{_offsetinhex}
1659 *
1660 * bn = PCI BAR number
1661 * bt = Index using PCI BARs
1662 * n = number of serial ports
1663 * baud = baud rate
1664 * offsetinhex = offset for each sequential port (in hex)
1665 *
1666 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1667 *
1668 * Please note: in theory if n = 1, _bt infix should make no difference.
1669 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1670 */
1671enum pci_board_num_t {
1672 pbn_default = 0,
1673
1674 pbn_b0_1_115200,
1675 pbn_b0_2_115200,
1676 pbn_b0_4_115200,
1677 pbn_b0_5_115200,
1678 pbn_b0_8_115200,
1679
1680 pbn_b0_1_921600,
1681 pbn_b0_2_921600,
1682 pbn_b0_4_921600,
1683
1684 pbn_b0_2_1130000,
1685
1686 pbn_b0_4_1152000,
1687
1688 pbn_b0_2_1843200,
1689 pbn_b0_4_1843200,
1690
1691 pbn_b0_2_1843200_200,
1692 pbn_b0_4_1843200_200,
1693 pbn_b0_8_1843200_200,
1694
1695 pbn_b0_1_4000000,
1696
1697 pbn_b0_bt_1_115200,
1698 pbn_b0_bt_2_115200,
1699 pbn_b0_bt_4_115200,
1700 pbn_b0_bt_8_115200,
1701
1702 pbn_b0_bt_1_460800,
1703 pbn_b0_bt_2_460800,
1704 pbn_b0_bt_4_460800,
1705
1706 pbn_b0_bt_1_921600,
1707 pbn_b0_bt_2_921600,
1708 pbn_b0_bt_4_921600,
1709 pbn_b0_bt_8_921600,
1710
1711 pbn_b1_1_115200,
1712 pbn_b1_2_115200,
1713 pbn_b1_4_115200,
1714 pbn_b1_8_115200,
1715 pbn_b1_16_115200,
1716
1717 pbn_b1_1_921600,
1718 pbn_b1_2_921600,
1719 pbn_b1_4_921600,
1720 pbn_b1_8_921600,
1721
1722 pbn_b1_2_1250000,
1723
1724 pbn_b1_bt_1_115200,
1725 pbn_b1_bt_2_115200,
1726 pbn_b1_bt_4_115200,
1727
1728 pbn_b1_bt_2_921600,
1729
1730 pbn_b1_1_1382400,
1731 pbn_b1_2_1382400,
1732 pbn_b1_4_1382400,
1733 pbn_b1_8_1382400,
1734
1735 pbn_b2_1_115200,
1736 pbn_b2_2_115200,
1737 pbn_b2_4_115200,
1738 pbn_b2_8_115200,
1739
1740 pbn_b2_1_460800,
1741 pbn_b2_4_460800,
1742 pbn_b2_8_460800,
1743 pbn_b2_16_460800,
1744
1745 pbn_b2_1_921600,
1746 pbn_b2_4_921600,
1747 pbn_b2_8_921600,
1748
1749 pbn_b2_8_1152000,
1750
1751 pbn_b2_bt_1_115200,
1752 pbn_b2_bt_2_115200,
1753 pbn_b2_bt_4_115200,
1754
1755 pbn_b2_bt_2_921600,
1756 pbn_b2_bt_4_921600,
1757
1758 pbn_b3_2_115200,
1759 pbn_b3_4_115200,
1760 pbn_b3_8_115200,
1761
1762 pbn_b4_bt_2_921600,
1763 pbn_b4_bt_4_921600,
1764 pbn_b4_bt_8_921600,
1765
1766 /*
1767 * Board-specific versions.
1768 */
1769 pbn_panacom,
1770 pbn_panacom2,
1771 pbn_panacom4,
1772 pbn_exsys_4055,
1773 pbn_plx_romulus,
1774 pbn_oxsemi,
1775 pbn_oxsemi_1_4000000,
1776 pbn_oxsemi_2_4000000,
1777 pbn_oxsemi_4_4000000,
1778 pbn_oxsemi_8_4000000,
1779 pbn_intel_i960,
1780 pbn_sgi_ioc3,
1781 pbn_computone_4,
1782 pbn_computone_6,
1783 pbn_computone_8,
1784 pbn_sbsxrsio,
1785 pbn_exar_XR17C152,
1786 pbn_exar_XR17C154,
1787 pbn_exar_XR17C158,
1788 pbn_exar_ibm_saturn,
1789 pbn_pasemi_1682M,
1790 pbn_ni8430_2,
1791 pbn_ni8430_4,
1792 pbn_ni8430_8,
1793 pbn_ni8430_16,
1794 pbn_ADDIDATA_PCIe_1_3906250,
1795 pbn_ADDIDATA_PCIe_2_3906250,
1796 pbn_ADDIDATA_PCIe_4_3906250,
1797 pbn_ADDIDATA_PCIe_8_3906250,
1798 pbn_ce4100_1_115200,
1799 pbn_omegapci,
1800 pbn_NETMOS9900_2s_115200,
1801};
1802
1803/*
1804 * uart_offset - the space between channels
1805 * reg_shift - describes how the UART registers are mapped
1806 * to PCI memory by the card.
1807 * For example IER register on SBS, Inc. PMC-OctPro is located at
1808 * offset 0x10 from the UART base, while UART_IER is defined as 1
1809 * in include/linux/serial_reg.h,
1810 * see first lines of serial_in() and serial_out() in 8250.c
1811*/
1812
1813static struct pciserial_board pci_boards[] __devinitdata = {
1814 [pbn_default] = {
1815 .flags = FL_BASE0,
1816 .num_ports = 1,
1817 .base_baud = 115200,
1818 .uart_offset = 8,
1819 },
1820 [pbn_b0_1_115200] = {
1821 .flags = FL_BASE0,
1822 .num_ports = 1,
1823 .base_baud = 115200,
1824 .uart_offset = 8,
1825 },
1826 [pbn_b0_2_115200] = {
1827 .flags = FL_BASE0,
1828 .num_ports = 2,
1829 .base_baud = 115200,
1830 .uart_offset = 8,
1831 },
1832 [pbn_b0_4_115200] = {
1833 .flags = FL_BASE0,
1834 .num_ports = 4,
1835 .base_baud = 115200,
1836 .uart_offset = 8,
1837 },
1838 [pbn_b0_5_115200] = {
1839 .flags = FL_BASE0,
1840 .num_ports = 5,
1841 .base_baud = 115200,
1842 .uart_offset = 8,
1843 },
1844 [pbn_b0_8_115200] = {
1845 .flags = FL_BASE0,
1846 .num_ports = 8,
1847 .base_baud = 115200,
1848 .uart_offset = 8,
1849 },
1850 [pbn_b0_1_921600] = {
1851 .flags = FL_BASE0,
1852 .num_ports = 1,
1853 .base_baud = 921600,
1854 .uart_offset = 8,
1855 },
1856 [pbn_b0_2_921600] = {
1857 .flags = FL_BASE0,
1858 .num_ports = 2,
1859 .base_baud = 921600,
1860 .uart_offset = 8,
1861 },
1862 [pbn_b0_4_921600] = {
1863 .flags = FL_BASE0,
1864 .num_ports = 4,
1865 .base_baud = 921600,
1866 .uart_offset = 8,
1867 },
1868
1869 [pbn_b0_2_1130000] = {
1870 .flags = FL_BASE0,
1871 .num_ports = 2,
1872 .base_baud = 1130000,
1873 .uart_offset = 8,
1874 },
1875
1876 [pbn_b0_4_1152000] = {
1877 .flags = FL_BASE0,
1878 .num_ports = 4,
1879 .base_baud = 1152000,
1880 .uart_offset = 8,
1881 },
1882
1883 [pbn_b0_2_1843200] = {
1884 .flags = FL_BASE0,
1885 .num_ports = 2,
1886 .base_baud = 1843200,
1887 .uart_offset = 8,
1888 },
1889 [pbn_b0_4_1843200] = {
1890 .flags = FL_BASE0,
1891 .num_ports = 4,
1892 .base_baud = 1843200,
1893 .uart_offset = 8,
1894 },
1895
1896 [pbn_b0_2_1843200_200] = {
1897 .flags = FL_BASE0,
1898 .num_ports = 2,
1899 .base_baud = 1843200,
1900 .uart_offset = 0x200,
1901 },
1902 [pbn_b0_4_1843200_200] = {
1903 .flags = FL_BASE0,
1904 .num_ports = 4,
1905 .base_baud = 1843200,
1906 .uart_offset = 0x200,
1907 },
1908 [pbn_b0_8_1843200_200] = {
1909 .flags = FL_BASE0,
1910 .num_ports = 8,
1911 .base_baud = 1843200,
1912 .uart_offset = 0x200,
1913 },
1914 [pbn_b0_1_4000000] = {
1915 .flags = FL_BASE0,
1916 .num_ports = 1,
1917 .base_baud = 4000000,
1918 .uart_offset = 8,
1919 },
1920
1921 [pbn_b0_bt_1_115200] = {
1922 .flags = FL_BASE0|FL_BASE_BARS,
1923 .num_ports = 1,
1924 .base_baud = 115200,
1925 .uart_offset = 8,
1926 },
1927 [pbn_b0_bt_2_115200] = {
1928 .flags = FL_BASE0|FL_BASE_BARS,
1929 .num_ports = 2,
1930 .base_baud = 115200,
1931 .uart_offset = 8,
1932 },
1933 [pbn_b0_bt_4_115200] = {
1934 .flags = FL_BASE0|FL_BASE_BARS,
1935 .num_ports = 4,
1936 .base_baud = 115200,
1937 .uart_offset = 8,
1938 },
1939 [pbn_b0_bt_8_115200] = {
1940 .flags = FL_BASE0|FL_BASE_BARS,
1941 .num_ports = 8,
1942 .base_baud = 115200,
1943 .uart_offset = 8,
1944 },
1945
1946 [pbn_b0_bt_1_460800] = {
1947 .flags = FL_BASE0|FL_BASE_BARS,
1948 .num_ports = 1,
1949 .base_baud = 460800,
1950 .uart_offset = 8,
1951 },
1952 [pbn_b0_bt_2_460800] = {
1953 .flags = FL_BASE0|FL_BASE_BARS,
1954 .num_ports = 2,
1955 .base_baud = 460800,
1956 .uart_offset = 8,
1957 },
1958 [pbn_b0_bt_4_460800] = {
1959 .flags = FL_BASE0|FL_BASE_BARS,
1960 .num_ports = 4,
1961 .base_baud = 460800,
1962 .uart_offset = 8,
1963 },
1964
1965 [pbn_b0_bt_1_921600] = {
1966 .flags = FL_BASE0|FL_BASE_BARS,
1967 .num_ports = 1,
1968 .base_baud = 921600,
1969 .uart_offset = 8,
1970 },
1971 [pbn_b0_bt_2_921600] = {
1972 .flags = FL_BASE0|FL_BASE_BARS,
1973 .num_ports = 2,
1974 .base_baud = 921600,
1975 .uart_offset = 8,
1976 },
1977 [pbn_b0_bt_4_921600] = {
1978 .flags = FL_BASE0|FL_BASE_BARS,
1979 .num_ports = 4,
1980 .base_baud = 921600,
1981 .uart_offset = 8,
1982 },
1983 [pbn_b0_bt_8_921600] = {
1984 .flags = FL_BASE0|FL_BASE_BARS,
1985 .num_ports = 8,
1986 .base_baud = 921600,
1987 .uart_offset = 8,
1988 },
1989
1990 [pbn_b1_1_115200] = {
1991 .flags = FL_BASE1,
1992 .num_ports = 1,
1993 .base_baud = 115200,
1994 .uart_offset = 8,
1995 },
1996 [pbn_b1_2_115200] = {
1997 .flags = FL_BASE1,
1998 .num_ports = 2,
1999 .base_baud = 115200,
2000 .uart_offset = 8,
2001 },
2002 [pbn_b1_4_115200] = {
2003 .flags = FL_BASE1,
2004 .num_ports = 4,
2005 .base_baud = 115200,
2006 .uart_offset = 8,
2007 },
2008 [pbn_b1_8_115200] = {
2009 .flags = FL_BASE1,
2010 .num_ports = 8,
2011 .base_baud = 115200,
2012 .uart_offset = 8,
2013 },
2014 [pbn_b1_16_115200] = {
2015 .flags = FL_BASE1,
2016 .num_ports = 16,
2017 .base_baud = 115200,
2018 .uart_offset = 8,
2019 },
2020
2021 [pbn_b1_1_921600] = {
2022 .flags = FL_BASE1,
2023 .num_ports = 1,
2024 .base_baud = 921600,
2025 .uart_offset = 8,
2026 },
2027 [pbn_b1_2_921600] = {
2028 .flags = FL_BASE1,
2029 .num_ports = 2,
2030 .base_baud = 921600,
2031 .uart_offset = 8,
2032 },
2033 [pbn_b1_4_921600] = {
2034 .flags = FL_BASE1,
2035 .num_ports = 4,
2036 .base_baud = 921600,
2037 .uart_offset = 8,
2038 },
2039 [pbn_b1_8_921600] = {
2040 .flags = FL_BASE1,
2041 .num_ports = 8,
2042 .base_baud = 921600,
2043 .uart_offset = 8,
2044 },
2045 [pbn_b1_2_1250000] = {
2046 .flags = FL_BASE1,
2047 .num_ports = 2,
2048 .base_baud = 1250000,
2049 .uart_offset = 8,
2050 },
2051
2052 [pbn_b1_bt_1_115200] = {
2053 .flags = FL_BASE1|FL_BASE_BARS,
2054 .num_ports = 1,
2055 .base_baud = 115200,
2056 .uart_offset = 8,
2057 },
2058 [pbn_b1_bt_2_115200] = {
2059 .flags = FL_BASE1|FL_BASE_BARS,
2060 .num_ports = 2,
2061 .base_baud = 115200,
2062 .uart_offset = 8,
2063 },
2064 [pbn_b1_bt_4_115200] = {
2065 .flags = FL_BASE1|FL_BASE_BARS,
2066 .num_ports = 4,
2067 .base_baud = 115200,
2068 .uart_offset = 8,
2069 },
2070
2071 [pbn_b1_bt_2_921600] = {
2072 .flags = FL_BASE1|FL_BASE_BARS,
2073 .num_ports = 2,
2074 .base_baud = 921600,
2075 .uart_offset = 8,
2076 },
2077
2078 [pbn_b1_1_1382400] = {
2079 .flags = FL_BASE1,
2080 .num_ports = 1,
2081 .base_baud = 1382400,
2082 .uart_offset = 8,
2083 },
2084 [pbn_b1_2_1382400] = {
2085 .flags = FL_BASE1,
2086 .num_ports = 2,
2087 .base_baud = 1382400,
2088 .uart_offset = 8,
2089 },
2090 [pbn_b1_4_1382400] = {
2091 .flags = FL_BASE1,
2092 .num_ports = 4,
2093 .base_baud = 1382400,
2094 .uart_offset = 8,
2095 },
2096 [pbn_b1_8_1382400] = {
2097 .flags = FL_BASE1,
2098 .num_ports = 8,
2099 .base_baud = 1382400,
2100 .uart_offset = 8,
2101 },
2102
2103 [pbn_b2_1_115200] = {
2104 .flags = FL_BASE2,
2105 .num_ports = 1,
2106 .base_baud = 115200,
2107 .uart_offset = 8,
2108 },
2109 [pbn_b2_2_115200] = {
2110 .flags = FL_BASE2,
2111 .num_ports = 2,
2112 .base_baud = 115200,
2113 .uart_offset = 8,
2114 },
2115 [pbn_b2_4_115200] = {
2116 .flags = FL_BASE2,
2117 .num_ports = 4,
2118 .base_baud = 115200,
2119 .uart_offset = 8,
2120 },
2121 [pbn_b2_8_115200] = {
2122 .flags = FL_BASE2,
2123 .num_ports = 8,
2124 .base_baud = 115200,
2125 .uart_offset = 8,
2126 },
2127
2128 [pbn_b2_1_460800] = {
2129 .flags = FL_BASE2,
2130 .num_ports = 1,
2131 .base_baud = 460800,
2132 .uart_offset = 8,
2133 },
2134 [pbn_b2_4_460800] = {
2135 .flags = FL_BASE2,
2136 .num_ports = 4,
2137 .base_baud = 460800,
2138 .uart_offset = 8,
2139 },
2140 [pbn_b2_8_460800] = {
2141 .flags = FL_BASE2,
2142 .num_ports = 8,
2143 .base_baud = 460800,
2144 .uart_offset = 8,
2145 },
2146 [pbn_b2_16_460800] = {
2147 .flags = FL_BASE2,
2148 .num_ports = 16,
2149 .base_baud = 460800,
2150 .uart_offset = 8,
2151 },
2152
2153 [pbn_b2_1_921600] = {
2154 .flags = FL_BASE2,
2155 .num_ports = 1,
2156 .base_baud = 921600,
2157 .uart_offset = 8,
2158 },
2159 [pbn_b2_4_921600] = {
2160 .flags = FL_BASE2,
2161 .num_ports = 4,
2162 .base_baud = 921600,
2163 .uart_offset = 8,
2164 },
2165 [pbn_b2_8_921600] = {
2166 .flags = FL_BASE2,
2167 .num_ports = 8,
2168 .base_baud = 921600,
2169 .uart_offset = 8,
2170 },
2171
2172 [pbn_b2_8_1152000] = {
2173 .flags = FL_BASE2,
2174 .num_ports = 8,
2175 .base_baud = 1152000,
2176 .uart_offset = 8,
2177 },
2178
2179 [pbn_b2_bt_1_115200] = {
2180 .flags = FL_BASE2|FL_BASE_BARS,
2181 .num_ports = 1,
2182 .base_baud = 115200,
2183 .uart_offset = 8,
2184 },
2185 [pbn_b2_bt_2_115200] = {
2186 .flags = FL_BASE2|FL_BASE_BARS,
2187 .num_ports = 2,
2188 .base_baud = 115200,
2189 .uart_offset = 8,
2190 },
2191 [pbn_b2_bt_4_115200] = {
2192 .flags = FL_BASE2|FL_BASE_BARS,
2193 .num_ports = 4,
2194 .base_baud = 115200,
2195 .uart_offset = 8,
2196 },
2197
2198 [pbn_b2_bt_2_921600] = {
2199 .flags = FL_BASE2|FL_BASE_BARS,
2200 .num_ports = 2,
2201 .base_baud = 921600,
2202 .uart_offset = 8,
2203 },
2204 [pbn_b2_bt_4_921600] = {
2205 .flags = FL_BASE2|FL_BASE_BARS,
2206 .num_ports = 4,
2207 .base_baud = 921600,
2208 .uart_offset = 8,
2209 },
2210
2211 [pbn_b3_2_115200] = {
2212 .flags = FL_BASE3,
2213 .num_ports = 2,
2214 .base_baud = 115200,
2215 .uart_offset = 8,
2216 },
2217 [pbn_b3_4_115200] = {
2218 .flags = FL_BASE3,
2219 .num_ports = 4,
2220 .base_baud = 115200,
2221 .uart_offset = 8,
2222 },
2223 [pbn_b3_8_115200] = {
2224 .flags = FL_BASE3,
2225 .num_ports = 8,
2226 .base_baud = 115200,
2227 .uart_offset = 8,
2228 },
2229
2230 [pbn_b4_bt_2_921600] = {
2231 .flags = FL_BASE4,
2232 .num_ports = 2,
2233 .base_baud = 921600,
2234 .uart_offset = 8,
2235 },
2236 [pbn_b4_bt_4_921600] = {
2237 .flags = FL_BASE4,
2238 .num_ports = 4,
2239 .base_baud = 921600,
2240 .uart_offset = 8,
2241 },
2242 [pbn_b4_bt_8_921600] = {
2243 .flags = FL_BASE4,
2244 .num_ports = 8,
2245 .base_baud = 921600,
2246 .uart_offset = 8,
2247 },
2248
2249 /*
2250 * Entries following this are board-specific.
2251 */
2252
2253 /*
2254 * Panacom - IOMEM
2255 */
2256 [pbn_panacom] = {
2257 .flags = FL_BASE2,
2258 .num_ports = 2,
2259 .base_baud = 921600,
2260 .uart_offset = 0x400,
2261 .reg_shift = 7,
2262 },
2263 [pbn_panacom2] = {
2264 .flags = FL_BASE2|FL_BASE_BARS,
2265 .num_ports = 2,
2266 .base_baud = 921600,
2267 .uart_offset = 0x400,
2268 .reg_shift = 7,
2269 },
2270 [pbn_panacom4] = {
2271 .flags = FL_BASE2|FL_BASE_BARS,
2272 .num_ports = 4,
2273 .base_baud = 921600,
2274 .uart_offset = 0x400,
2275 .reg_shift = 7,
2276 },
2277
2278 [pbn_exsys_4055] = {
2279 .flags = FL_BASE2,
2280 .num_ports = 4,
2281 .base_baud = 115200,
2282 .uart_offset = 8,
2283 },
2284
2285 /* I think this entry is broken - the first_offset looks wrong --rmk */
2286 [pbn_plx_romulus] = {
2287 .flags = FL_BASE2,
2288 .num_ports = 4,
2289 .base_baud = 921600,
2290 .uart_offset = 8 << 2,
2291 .reg_shift = 2,
2292 .first_offset = 0x03,
2293 },
2294
2295 /*
2296 * This board uses the size of PCI Base region 0 to
2297 * signal now many ports are available
2298 */
2299 [pbn_oxsemi] = {
2300 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2301 .num_ports = 32,
2302 .base_baud = 115200,
2303 .uart_offset = 8,
2304 },
2305 [pbn_oxsemi_1_4000000] = {
2306 .flags = FL_BASE0,
2307 .num_ports = 1,
2308 .base_baud = 4000000,
2309 .uart_offset = 0x200,
2310 .first_offset = 0x1000,
2311 },
2312 [pbn_oxsemi_2_4000000] = {
2313 .flags = FL_BASE0,
2314 .num_ports = 2,
2315 .base_baud = 4000000,
2316 .uart_offset = 0x200,
2317 .first_offset = 0x1000,
2318 },
2319 [pbn_oxsemi_4_4000000] = {
2320 .flags = FL_BASE0,
2321 .num_ports = 4,
2322 .base_baud = 4000000,
2323 .uart_offset = 0x200,
2324 .first_offset = 0x1000,
2325 },
2326 [pbn_oxsemi_8_4000000] = {
2327 .flags = FL_BASE0,
2328 .num_ports = 8,
2329 .base_baud = 4000000,
2330 .uart_offset = 0x200,
2331 .first_offset = 0x1000,
2332 },
2333
2334
2335 /*
2336 * EKF addition for i960 Boards form EKF with serial port.
2337 * Max 256 ports.
2338 */
2339 [pbn_intel_i960] = {
2340 .flags = FL_BASE0,
2341 .num_ports = 32,
2342 .base_baud = 921600,
2343 .uart_offset = 8 << 2,
2344 .reg_shift = 2,
2345 .first_offset = 0x10000,
2346 },
2347 [pbn_sgi_ioc3] = {
2348 .flags = FL_BASE0|FL_NOIRQ,
2349 .num_ports = 1,
2350 .base_baud = 458333,
2351 .uart_offset = 8,
2352 .reg_shift = 0,
2353 .first_offset = 0x20178,
2354 },
2355
2356 /*
2357 * Computone - uses IOMEM.
2358 */
2359 [pbn_computone_4] = {
2360 .flags = FL_BASE0,
2361 .num_ports = 4,
2362 .base_baud = 921600,
2363 .uart_offset = 0x40,
2364 .reg_shift = 2,
2365 .first_offset = 0x200,
2366 },
2367 [pbn_computone_6] = {
2368 .flags = FL_BASE0,
2369 .num_ports = 6,
2370 .base_baud = 921600,
2371 .uart_offset = 0x40,
2372 .reg_shift = 2,
2373 .first_offset = 0x200,
2374 },
2375 [pbn_computone_8] = {
2376 .flags = FL_BASE0,
2377 .num_ports = 8,
2378 .base_baud = 921600,
2379 .uart_offset = 0x40,
2380 .reg_shift = 2,
2381 .first_offset = 0x200,
2382 },
2383 [pbn_sbsxrsio] = {
2384 .flags = FL_BASE0,
2385 .num_ports = 8,
2386 .base_baud = 460800,
2387 .uart_offset = 256,
2388 .reg_shift = 4,
2389 },
2390 /*
2391 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2392 * Only basic 16550A support.
2393 * XR17C15[24] are not tested, but they should work.
2394 */
2395 [pbn_exar_XR17C152] = {
2396 .flags = FL_BASE0,
2397 .num_ports = 2,
2398 .base_baud = 921600,
2399 .uart_offset = 0x200,
2400 },
2401 [pbn_exar_XR17C154] = {
2402 .flags = FL_BASE0,
2403 .num_ports = 4,
2404 .base_baud = 921600,
2405 .uart_offset = 0x200,
2406 },
2407 [pbn_exar_XR17C158] = {
2408 .flags = FL_BASE0,
2409 .num_ports = 8,
2410 .base_baud = 921600,
2411 .uart_offset = 0x200,
2412 },
2413 [pbn_exar_ibm_saturn] = {
2414 .flags = FL_BASE0,
2415 .num_ports = 1,
2416 .base_baud = 921600,
2417 .uart_offset = 0x200,
2418 },
2419
2420 /*
2421 * PA Semi PWRficient PA6T-1682M on-chip UART
2422 */
2423 [pbn_pasemi_1682M] = {
2424 .flags = FL_BASE0,
2425 .num_ports = 1,
2426 .base_baud = 8333333,
2427 },
2428 /*
2429 * National Instruments 843x
2430 */
2431 [pbn_ni8430_16] = {
2432 .flags = FL_BASE0,
2433 .num_ports = 16,
2434 .base_baud = 3686400,
2435 .uart_offset = 0x10,
2436 .first_offset = 0x800,
2437 },
2438 [pbn_ni8430_8] = {
2439 .flags = FL_BASE0,
2440 .num_ports = 8,
2441 .base_baud = 3686400,
2442 .uart_offset = 0x10,
2443 .first_offset = 0x800,
2444 },
2445 [pbn_ni8430_4] = {
2446 .flags = FL_BASE0,
2447 .num_ports = 4,
2448 .base_baud = 3686400,
2449 .uart_offset = 0x10,
2450 .first_offset = 0x800,
2451 },
2452 [pbn_ni8430_2] = {
2453 .flags = FL_BASE0,
2454 .num_ports = 2,
2455 .base_baud = 3686400,
2456 .uart_offset = 0x10,
2457 .first_offset = 0x800,
2458 },
2459 /*
2460 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2461 */
2462 [pbn_ADDIDATA_PCIe_1_3906250] = {
2463 .flags = FL_BASE0,
2464 .num_ports = 1,
2465 .base_baud = 3906250,
2466 .uart_offset = 0x200,
2467 .first_offset = 0x1000,
2468 },
2469 [pbn_ADDIDATA_PCIe_2_3906250] = {
2470 .flags = FL_BASE0,
2471 .num_ports = 2,
2472 .base_baud = 3906250,
2473 .uart_offset = 0x200,
2474 .first_offset = 0x1000,
2475 },
2476 [pbn_ADDIDATA_PCIe_4_3906250] = {
2477 .flags = FL_BASE0,
2478 .num_ports = 4,
2479 .base_baud = 3906250,
2480 .uart_offset = 0x200,
2481 .first_offset = 0x1000,
2482 },
2483 [pbn_ADDIDATA_PCIe_8_3906250] = {
2484 .flags = FL_BASE0,
2485 .num_ports = 8,
2486 .base_baud = 3906250,
2487 .uart_offset = 0x200,
2488 .first_offset = 0x1000,
2489 },
2490 [pbn_ce4100_1_115200] = {
2491 .flags = FL_BASE0,
2492 .num_ports = 1,
2493 .base_baud = 921600,
2494 .reg_shift = 2,
2495 },
2496 [pbn_omegapci] = {
2497 .flags = FL_BASE0,
2498 .num_ports = 8,
2499 .base_baud = 115200,
2500 .uart_offset = 0x200,
2501 },
2502 [pbn_NETMOS9900_2s_115200] = {
2503 .flags = FL_BASE0,
2504 .num_ports = 2,
2505 .base_baud = 115200,
2506 },
2507};
2508
2509static const struct pci_device_id softmodem_blacklist[] = {
2510 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2511 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2512 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2513};
2514
2515/*
2516 * Given a complete unknown PCI device, try to use some heuristics to
2517 * guess what the configuration might be, based on the pitiful PCI
2518 * serial specs. Returns 0 on success, 1 on failure.
2519 */
2520static int __devinit
2521serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2522{
2523 const struct pci_device_id *blacklist;
2524 int num_iomem, num_port, first_port = -1, i;
2525
2526 /*
2527 * If it is not a communications device or the programming
2528 * interface is greater than 6, give up.
2529 *
2530 * (Should we try to make guesses for multiport serial devices
2531 * later?)
2532 */
2533 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2534 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2535 (dev->class & 0xff) > 6)
2536 return -ENODEV;
2537
2538 /*
2539 * Do not access blacklisted devices that are known not to
2540 * feature serial ports.
2541 */
2542 for (blacklist = softmodem_blacklist;
2543 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2544 blacklist++) {
2545 if (dev->vendor == blacklist->vendor &&
2546 dev->device == blacklist->device)
2547 return -ENODEV;
2548 }
2549
2550 num_iomem = num_port = 0;
2551 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2552 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2553 num_port++;
2554 if (first_port == -1)
2555 first_port = i;
2556 }
2557 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2558 num_iomem++;
2559 }
2560
2561 /*
2562 * If there is 1 or 0 iomem regions, and exactly one port,
2563 * use it. We guess the number of ports based on the IO
2564 * region size.
2565 */
2566 if (num_iomem <= 1 && num_port == 1) {
2567 board->flags = first_port;
2568 board->num_ports = pci_resource_len(dev, first_port) / 8;
2569 return 0;
2570 }
2571
2572 /*
2573 * Now guess if we've got a board which indexes by BARs.
2574 * Each IO BAR should be 8 bytes, and they should follow
2575 * consecutively.
2576 */
2577 first_port = -1;
2578 num_port = 0;
2579 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2580 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2581 pci_resource_len(dev, i) == 8 &&
2582 (first_port == -1 || (first_port + num_port) == i)) {
2583 num_port++;
2584 if (first_port == -1)
2585 first_port = i;
2586 }
2587 }
2588
2589 if (num_port > 1) {
2590 board->flags = first_port | FL_BASE_BARS;
2591 board->num_ports = num_port;
2592 return 0;
2593 }
2594
2595 return -ENODEV;
2596}
2597
2598static inline int
2599serial_pci_matches(const struct pciserial_board *board,
2600 const struct pciserial_board *guessed)
2601{
2602 return
2603 board->num_ports == guessed->num_ports &&
2604 board->base_baud == guessed->base_baud &&
2605 board->uart_offset == guessed->uart_offset &&
2606 board->reg_shift == guessed->reg_shift &&
2607 board->first_offset == guessed->first_offset;
2608}
2609
2610struct serial_private *
2611pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2612{
2613 struct uart_port serial_port;
2614 struct serial_private *priv;
2615 struct pci_serial_quirk *quirk;
2616 int rc, nr_ports, i;
2617
2618 nr_ports = board->num_ports;
2619
2620 /*
2621 * Find an init and setup quirks.
2622 */
2623 quirk = find_quirk(dev);
2624
2625 /*
2626 * Run the new-style initialization function.
2627 * The initialization function returns:
2628 * <0 - error
2629 * 0 - use board->num_ports
2630 * >0 - number of ports
2631 */
2632 if (quirk->init) {
2633 rc = quirk->init(dev);
2634 if (rc < 0) {
2635 priv = ERR_PTR(rc);
2636 goto err_out;
2637 }
2638 if (rc)
2639 nr_ports = rc;
2640 }
2641
2642 priv = kzalloc(sizeof(struct serial_private) +
2643 sizeof(unsigned int) * nr_ports,
2644 GFP_KERNEL);
2645 if (!priv) {
2646 priv = ERR_PTR(-ENOMEM);
2647 goto err_deinit;
2648 }
2649
2650 priv->dev = dev;
2651 priv->quirk = quirk;
2652
2653 memset(&serial_port, 0, sizeof(struct uart_port));
2654 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2655 serial_port.uartclk = board->base_baud * 16;
2656 serial_port.irq = get_pci_irq(dev, board);
2657 serial_port.dev = &dev->dev;
2658
2659 for (i = 0; i < nr_ports; i++) {
2660 if (quirk->setup(priv, board, &serial_port, i))
2661 break;
2662
2663#ifdef SERIAL_DEBUG_PCI
2664 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2665 serial_port.iobase, serial_port.irq, serial_port.iotype);
2666#endif
2667
2668 priv->line[i] = serial8250_register_port(&serial_port);
2669 if (priv->line[i] < 0) {
2670 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2671 break;
2672 }
2673 }
2674 priv->nr = i;
2675 return priv;
2676
2677err_deinit:
2678 if (quirk->exit)
2679 quirk->exit(dev);
2680err_out:
2681 return priv;
2682}
2683EXPORT_SYMBOL_GPL(pciserial_init_ports);
2684
2685void pciserial_remove_ports(struct serial_private *priv)
2686{
2687 struct pci_serial_quirk *quirk;
2688 int i;
2689
2690 for (i = 0; i < priv->nr; i++)
2691 serial8250_unregister_port(priv->line[i]);
2692
2693 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2694 if (priv->remapped_bar[i])
2695 iounmap(priv->remapped_bar[i]);
2696 priv->remapped_bar[i] = NULL;
2697 }
2698
2699 /*
2700 * Find the exit quirks.
2701 */
2702 quirk = find_quirk(priv->dev);
2703 if (quirk->exit)
2704 quirk->exit(priv->dev);
2705
2706 kfree(priv);
2707}
2708EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2709
2710void pciserial_suspend_ports(struct serial_private *priv)
2711{
2712 int i;
2713
2714 for (i = 0; i < priv->nr; i++)
2715 if (priv->line[i] >= 0)
2716 serial8250_suspend_port(priv->line[i]);
2717}
2718EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2719
2720void pciserial_resume_ports(struct serial_private *priv)
2721{
2722 int i;
2723
2724 /*
2725 * Ensure that the board is correctly configured.
2726 */
2727 if (priv->quirk->init)
2728 priv->quirk->init(priv->dev);
2729
2730 for (i = 0; i < priv->nr; i++)
2731 if (priv->line[i] >= 0)
2732 serial8250_resume_port(priv->line[i]);
2733}
2734EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2735
2736/*
2737 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2738 * to the arrangement of serial ports on a PCI card.
2739 */
2740static int __devinit
2741pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2742{
2743 struct pci_serial_quirk *quirk;
2744 struct serial_private *priv;
2745 const struct pciserial_board *board;
2746 struct pciserial_board tmp;
2747 int rc;
2748
2749 quirk = find_quirk(dev);
2750 if (quirk->probe) {
2751 rc = quirk->probe(dev);
2752 if (rc)
2753 return rc;
2754 }
2755
2756 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2757 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2758 ent->driver_data);
2759 return -EINVAL;
2760 }
2761
2762 board = &pci_boards[ent->driver_data];
2763
2764 rc = pci_enable_device(dev);
2765 pci_save_state(dev);
2766 if (rc)
2767 return rc;
2768
2769 if (ent->driver_data == pbn_default) {
2770 /*
2771 * Use a copy of the pci_board entry for this;
2772 * avoid changing entries in the table.
2773 */
2774 memcpy(&tmp, board, sizeof(struct pciserial_board));
2775 board = &tmp;
2776
2777 /*
2778 * We matched one of our class entries. Try to
2779 * determine the parameters of this board.
2780 */
2781 rc = serial_pci_guess_board(dev, &tmp);
2782 if (rc)
2783 goto disable;
2784 } else {
2785 /*
2786 * We matched an explicit entry. If we are able to
2787 * detect this boards settings with our heuristic,
2788 * then we no longer need this entry.
2789 */
2790 memcpy(&tmp, &pci_boards[pbn_default],
2791 sizeof(struct pciserial_board));
2792 rc = serial_pci_guess_board(dev, &tmp);
2793 if (rc == 0 && serial_pci_matches(board, &tmp))
2794 moan_device("Redundant entry in serial pci_table.",
2795 dev);
2796 }
2797
2798 priv = pciserial_init_ports(dev, board);
2799 if (!IS_ERR(priv)) {
2800 pci_set_drvdata(dev, priv);
2801 return 0;
2802 }
2803
2804 rc = PTR_ERR(priv);
2805
2806 disable:
2807 pci_disable_device(dev);
2808 return rc;
2809}
2810
2811static void __devexit pciserial_remove_one(struct pci_dev *dev)
2812{
2813 struct serial_private *priv = pci_get_drvdata(dev);
2814
2815 pci_set_drvdata(dev, NULL);
2816
2817 pciserial_remove_ports(priv);
2818
2819 pci_disable_device(dev);
2820}
2821
2822#ifdef CONFIG_PM
2823static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2824{
2825 struct serial_private *priv = pci_get_drvdata(dev);
2826
2827 if (priv)
2828 pciserial_suspend_ports(priv);
2829
2830 pci_save_state(dev);
2831 pci_set_power_state(dev, pci_choose_state(dev, state));
2832 return 0;
2833}
2834
2835static int pciserial_resume_one(struct pci_dev *dev)
2836{
2837 int err;
2838 struct serial_private *priv = pci_get_drvdata(dev);
2839
2840 pci_set_power_state(dev, PCI_D0);
2841 pci_restore_state(dev);
2842
2843 if (priv) {
2844 /*
2845 * The device may have been disabled. Re-enable it.
2846 */
2847 err = pci_enable_device(dev);
2848 /* FIXME: We cannot simply error out here */
2849 if (err)
2850 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2851 pciserial_resume_ports(priv);
2852 }
2853 return 0;
2854}
2855#endif
2856
2857static struct pci_device_id serial_pci_tbl[] = {
2858 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2859 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2860 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2861 pbn_b2_8_921600 },
2862 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2863 PCI_SUBVENDOR_ID_CONNECT_TECH,
2864 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2865 pbn_b1_8_1382400 },
2866 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2867 PCI_SUBVENDOR_ID_CONNECT_TECH,
2868 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2869 pbn_b1_4_1382400 },
2870 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2871 PCI_SUBVENDOR_ID_CONNECT_TECH,
2872 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2873 pbn_b1_2_1382400 },
2874 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2875 PCI_SUBVENDOR_ID_CONNECT_TECH,
2876 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2877 pbn_b1_8_1382400 },
2878 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2879 PCI_SUBVENDOR_ID_CONNECT_TECH,
2880 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2881 pbn_b1_4_1382400 },
2882 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2883 PCI_SUBVENDOR_ID_CONNECT_TECH,
2884 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2885 pbn_b1_2_1382400 },
2886 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2887 PCI_SUBVENDOR_ID_CONNECT_TECH,
2888 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2889 pbn_b1_8_921600 },
2890 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2891 PCI_SUBVENDOR_ID_CONNECT_TECH,
2892 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2893 pbn_b1_8_921600 },
2894 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2895 PCI_SUBVENDOR_ID_CONNECT_TECH,
2896 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2897 pbn_b1_4_921600 },
2898 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2899 PCI_SUBVENDOR_ID_CONNECT_TECH,
2900 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2901 pbn_b1_4_921600 },
2902 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2903 PCI_SUBVENDOR_ID_CONNECT_TECH,
2904 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2905 pbn_b1_2_921600 },
2906 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2907 PCI_SUBVENDOR_ID_CONNECT_TECH,
2908 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2909 pbn_b1_8_921600 },
2910 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2911 PCI_SUBVENDOR_ID_CONNECT_TECH,
2912 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2913 pbn_b1_8_921600 },
2914 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2915 PCI_SUBVENDOR_ID_CONNECT_TECH,
2916 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2917 pbn_b1_4_921600 },
2918 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2919 PCI_SUBVENDOR_ID_CONNECT_TECH,
2920 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2921 pbn_b1_2_1250000 },
2922 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2923 PCI_SUBVENDOR_ID_CONNECT_TECH,
2924 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2925 pbn_b0_2_1843200 },
2926 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2927 PCI_SUBVENDOR_ID_CONNECT_TECH,
2928 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2929 pbn_b0_4_1843200 },
2930 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2931 PCI_VENDOR_ID_AFAVLAB,
2932 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2933 pbn_b0_4_1152000 },
2934 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2935 PCI_SUBVENDOR_ID_CONNECT_TECH,
2936 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2937 pbn_b0_2_1843200_200 },
2938 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2939 PCI_SUBVENDOR_ID_CONNECT_TECH,
2940 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2941 pbn_b0_4_1843200_200 },
2942 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2943 PCI_SUBVENDOR_ID_CONNECT_TECH,
2944 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2945 pbn_b0_8_1843200_200 },
2946 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2947 PCI_SUBVENDOR_ID_CONNECT_TECH,
2948 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2949 pbn_b0_2_1843200_200 },
2950 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2951 PCI_SUBVENDOR_ID_CONNECT_TECH,
2952 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2953 pbn_b0_4_1843200_200 },
2954 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2955 PCI_SUBVENDOR_ID_CONNECT_TECH,
2956 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2957 pbn_b0_8_1843200_200 },
2958 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2959 PCI_SUBVENDOR_ID_CONNECT_TECH,
2960 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2961 pbn_b0_2_1843200_200 },
2962 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2963 PCI_SUBVENDOR_ID_CONNECT_TECH,
2964 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2965 pbn_b0_4_1843200_200 },
2966 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2967 PCI_SUBVENDOR_ID_CONNECT_TECH,
2968 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2969 pbn_b0_8_1843200_200 },
2970 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2971 PCI_SUBVENDOR_ID_CONNECT_TECH,
2972 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2973 pbn_b0_2_1843200_200 },
2974 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2975 PCI_SUBVENDOR_ID_CONNECT_TECH,
2976 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2977 pbn_b0_4_1843200_200 },
2978 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2979 PCI_SUBVENDOR_ID_CONNECT_TECH,
2980 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2981 pbn_b0_8_1843200_200 },
2982 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2983 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2984 0, 0, pbn_exar_ibm_saturn },
2985
2986 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2988 pbn_b2_bt_1_115200 },
2989 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2991 pbn_b2_bt_2_115200 },
2992 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2994 pbn_b2_bt_4_115200 },
2995 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2997 pbn_b2_bt_2_115200 },
2998 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3000 pbn_b2_bt_4_115200 },
3001 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3003 pbn_b2_8_115200 },
3004 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3006 pbn_b2_8_460800 },
3007 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3009 pbn_b2_8_115200 },
3010
3011 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3013 pbn_b2_bt_2_115200 },
3014 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3016 pbn_b2_bt_2_921600 },
3017 /*
3018 * VScom SPCOM800, from sl@s.pl
3019 */
3020 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3022 pbn_b2_8_921600 },
3023 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3025 pbn_b2_4_921600 },
3026 /* Unknown card - subdevice 0x1584 */
3027 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3028 PCI_VENDOR_ID_PLX,
3029 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3030 pbn_b0_4_115200 },
3031 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3032 PCI_SUBVENDOR_ID_KEYSPAN,
3033 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3034 pbn_panacom },
3035 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3037 pbn_panacom4 },
3038 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3040 pbn_panacom2 },
3041 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3042 PCI_VENDOR_ID_ESDGMBH,
3043 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3044 pbn_b2_4_115200 },
3045 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3046 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3047 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3048 pbn_b2_4_460800 },
3049 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3050 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3051 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3052 pbn_b2_8_460800 },
3053 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3054 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3055 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3056 pbn_b2_16_460800 },
3057 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3058 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3059 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3060 pbn_b2_16_460800 },
3061 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3062 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3063 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3064 pbn_b2_4_460800 },
3065 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3066 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3067 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3068 pbn_b2_8_460800 },
3069 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3070 PCI_SUBVENDOR_ID_EXSYS,
3071 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3072 pbn_exsys_4055 },
3073 /*
3074 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3075 * (Exoray@isys.ca)
3076 */
3077 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3078 0x10b5, 0x106a, 0, 0,
3079 pbn_plx_romulus },
3080 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3082 pbn_b1_4_115200 },
3083 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3085 pbn_b1_2_115200 },
3086 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3088 pbn_b1_8_115200 },
3089 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3091 pbn_b1_8_115200 },
3092 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3093 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3094 0, 0,
3095 pbn_b0_4_921600 },
3096 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3097 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3098 0, 0,
3099 pbn_b0_4_1152000 },
3100 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3102 pbn_b0_bt_2_921600 },
3103
3104 /*
3105 * The below card is a little controversial since it is the
3106 * subject of a PCI vendor/device ID clash. (See
3107 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3108 * For now just used the hex ID 0x950a.
3109 */
3110 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3111 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3112 pbn_b0_2_115200 },
3113 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115 pbn_b0_2_1130000 },
3116 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3117 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3118 pbn_b0_1_921600 },
3119 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3121 pbn_b0_4_115200 },
3122 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124 pbn_b0_bt_2_921600 },
3125 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3126 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3127 pbn_b2_8_1152000 },
3128
3129 /*
3130 * Oxford Semiconductor Inc. Tornado PCI express device range.
3131 */
3132 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3134 pbn_b0_1_4000000 },
3135 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3137 pbn_b0_1_4000000 },
3138 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3140 pbn_oxsemi_1_4000000 },
3141 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3143 pbn_oxsemi_1_4000000 },
3144 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3146 pbn_b0_1_4000000 },
3147 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149 pbn_b0_1_4000000 },
3150 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152 pbn_oxsemi_1_4000000 },
3153 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3155 pbn_oxsemi_1_4000000 },
3156 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3158 pbn_b0_1_4000000 },
3159 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161 pbn_b0_1_4000000 },
3162 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3164 pbn_b0_1_4000000 },
3165 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167 pbn_b0_1_4000000 },
3168 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3170 pbn_oxsemi_2_4000000 },
3171 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173 pbn_oxsemi_2_4000000 },
3174 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176 pbn_oxsemi_4_4000000 },
3177 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3179 pbn_oxsemi_4_4000000 },
3180 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3182 pbn_oxsemi_8_4000000 },
3183 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3185 pbn_oxsemi_8_4000000 },
3186 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3188 pbn_oxsemi_1_4000000 },
3189 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3191 pbn_oxsemi_1_4000000 },
3192 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3194 pbn_oxsemi_1_4000000 },
3195 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3197 pbn_oxsemi_1_4000000 },
3198 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3200 pbn_oxsemi_1_4000000 },
3201 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3203 pbn_oxsemi_1_4000000 },
3204 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206 pbn_oxsemi_1_4000000 },
3207 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3209 pbn_oxsemi_1_4000000 },
3210 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_oxsemi_1_4000000 },
3213 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215 pbn_oxsemi_1_4000000 },
3216 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_oxsemi_1_4000000 },
3219 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221 pbn_oxsemi_1_4000000 },
3222 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3224 pbn_oxsemi_1_4000000 },
3225 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227 pbn_oxsemi_1_4000000 },
3228 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230 pbn_oxsemi_1_4000000 },
3231 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233 pbn_oxsemi_1_4000000 },
3234 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236 pbn_oxsemi_1_4000000 },
3237 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239 pbn_oxsemi_1_4000000 },
3240 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242 pbn_oxsemi_1_4000000 },
3243 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245 pbn_oxsemi_1_4000000 },
3246 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248 pbn_oxsemi_1_4000000 },
3249 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251 pbn_oxsemi_1_4000000 },
3252 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254 pbn_oxsemi_1_4000000 },
3255 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257 pbn_oxsemi_1_4000000 },
3258 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260 pbn_oxsemi_1_4000000 },
3261 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263 pbn_oxsemi_1_4000000 },
3264 /*
3265 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3266 */
3267 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3268 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3269 pbn_oxsemi_1_4000000 },
3270 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3271 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3272 pbn_oxsemi_2_4000000 },
3273 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3274 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3275 pbn_oxsemi_4_4000000 },
3276 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3277 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3278 pbn_oxsemi_8_4000000 },
3279
3280 /*
3281 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3282 */
3283 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3284 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3285 pbn_oxsemi_2_4000000 },
3286
3287 /*
3288 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3289 * from skokodyn@yahoo.com
3290 */
3291 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3292 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3293 pbn_sbsxrsio },
3294 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3295 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3296 pbn_sbsxrsio },
3297 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3298 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3299 pbn_sbsxrsio },
3300 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3301 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3302 pbn_sbsxrsio },
3303
3304 /*
3305 * Digitan DS560-558, from jimd@esoft.com
3306 */
3307 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3309 pbn_b1_1_115200 },
3310
3311 /*
3312 * Titan Electronic cards
3313 * The 400L and 800L have a custom setup quirk.
3314 */
3315 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317 pbn_b0_1_921600 },
3318 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320 pbn_b0_2_921600 },
3321 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3323 pbn_b0_4_921600 },
3324 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326 pbn_b0_4_921600 },
3327 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3329 pbn_b1_1_921600 },
3330 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3332 pbn_b1_bt_2_921600 },
3333 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3335 pbn_b0_bt_4_921600 },
3336 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3338 pbn_b0_bt_8_921600 },
3339 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3341 pbn_b4_bt_2_921600 },
3342 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3344 pbn_b4_bt_4_921600 },
3345 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3347 pbn_b4_bt_8_921600 },
3348 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3350 pbn_b0_4_921600 },
3351 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3353 pbn_b0_4_921600 },
3354 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3356 pbn_b0_4_921600 },
3357 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359 pbn_oxsemi_1_4000000 },
3360 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3362 pbn_oxsemi_2_4000000 },
3363 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3365 pbn_oxsemi_4_4000000 },
3366 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3368 pbn_oxsemi_8_4000000 },
3369 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3371 pbn_oxsemi_2_4000000 },
3372 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3374 pbn_oxsemi_2_4000000 },
3375
3376 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3378 pbn_b2_1_460800 },
3379 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3381 pbn_b2_1_460800 },
3382 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384 pbn_b2_1_460800 },
3385 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387 pbn_b2_bt_2_921600 },
3388 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3390 pbn_b2_bt_2_921600 },
3391 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3393 pbn_b2_bt_2_921600 },
3394 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3396 pbn_b2_bt_4_921600 },
3397 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3399 pbn_b2_bt_4_921600 },
3400 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3402 pbn_b2_bt_4_921600 },
3403 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405 pbn_b0_1_921600 },
3406 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3408 pbn_b0_1_921600 },
3409 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3411 pbn_b0_1_921600 },
3412 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3414 pbn_b0_bt_2_921600 },
3415 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3417 pbn_b0_bt_2_921600 },
3418 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420 pbn_b0_bt_2_921600 },
3421 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423 pbn_b0_bt_4_921600 },
3424 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3426 pbn_b0_bt_4_921600 },
3427 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3429 pbn_b0_bt_4_921600 },
3430 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3432 pbn_b0_bt_8_921600 },
3433 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435 pbn_b0_bt_8_921600 },
3436 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438 pbn_b0_bt_8_921600 },
3439
3440 /*
3441 * Computone devices submitted by Doug McNash dmcnash@computone.com
3442 */
3443 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3444 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3445 0, 0, pbn_computone_4 },
3446 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3447 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3448 0, 0, pbn_computone_8 },
3449 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3450 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3451 0, 0, pbn_computone_6 },
3452
3453 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_oxsemi },
3456 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3457 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3458 pbn_b0_bt_1_921600 },
3459
3460 /*
3461 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3462 */
3463 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465 pbn_b0_bt_8_115200 },
3466 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468 pbn_b0_bt_8_115200 },
3469
3470 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472 pbn_b0_bt_2_115200 },
3473 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475 pbn_b0_bt_2_115200 },
3476 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478 pbn_b0_bt_2_115200 },
3479 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481 pbn_b0_bt_2_115200 },
3482 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3484 pbn_b0_bt_2_115200 },
3485 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487 pbn_b0_bt_4_460800 },
3488 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490 pbn_b0_bt_4_460800 },
3491 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493 pbn_b0_bt_2_460800 },
3494 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3496 pbn_b0_bt_2_460800 },
3497 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3499 pbn_b0_bt_2_460800 },
3500 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3502 pbn_b0_bt_1_115200 },
3503 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3505 pbn_b0_bt_1_460800 },
3506
3507 /*
3508 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3509 * Cards are identified by their subsystem vendor IDs, which
3510 * (in hex) match the model number.
3511 *
3512 * Note that JC140x are RS422/485 cards which require ox950
3513 * ACR = 0x10, and as such are not currently fully supported.
3514 */
3515 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3516 0x1204, 0x0004, 0, 0,
3517 pbn_b0_4_921600 },
3518 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3519 0x1208, 0x0004, 0, 0,
3520 pbn_b0_4_921600 },
3521/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3522 0x1402, 0x0002, 0, 0,
3523 pbn_b0_2_921600 }, */
3524/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3525 0x1404, 0x0004, 0, 0,
3526 pbn_b0_4_921600 }, */
3527 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3528 0x1208, 0x0004, 0, 0,
3529 pbn_b0_4_921600 },
3530
3531 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3532 0x1204, 0x0004, 0, 0,
3533 pbn_b0_4_921600 },
3534 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3535 0x1208, 0x0004, 0, 0,
3536 pbn_b0_4_921600 },
3537 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3538 0x1208, 0x0004, 0, 0,
3539 pbn_b0_4_921600 },
3540 /*
3541 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3542 */
3543 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3545 pbn_b1_1_1382400 },
3546
3547 /*
3548 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3549 */
3550 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3552 pbn_b1_1_1382400 },
3553
3554 /*
3555 * RAStel 2 port modem, gerg@moreton.com.au
3556 */
3557 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3559 pbn_b2_bt_2_115200 },
3560
3561 /*
3562 * EKF addition for i960 Boards form EKF with serial port
3563 */
3564 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3565 0xE4BF, PCI_ANY_ID, 0, 0,
3566 pbn_intel_i960 },
3567
3568 /*
3569 * Xircom Cardbus/Ethernet combos
3570 */
3571 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3573 pbn_b0_1_115200 },
3574 /*
3575 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3576 */
3577 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3579 pbn_b0_1_115200 },
3580
3581 /*
3582 * Untested PCI modems, sent in from various folks...
3583 */
3584
3585 /*
3586 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3587 */
3588 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3589 0x1048, 0x1500, 0, 0,
3590 pbn_b1_1_115200 },
3591
3592 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3593 0xFF00, 0, 0, 0,
3594 pbn_sgi_ioc3 },
3595
3596 /*
3597 * HP Diva card
3598 */
3599 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3600 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3601 pbn_b1_1_115200 },
3602 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604 pbn_b0_5_115200 },
3605 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3607 pbn_b2_1_115200 },
3608
3609 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3611 pbn_b3_2_115200 },
3612 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3614 pbn_b3_4_115200 },
3615 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3617 pbn_b3_8_115200 },
3618
3619 /*
3620 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3621 */
3622 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3623 PCI_ANY_ID, PCI_ANY_ID,
3624 0,
3625 0, pbn_exar_XR17C152 },
3626 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3627 PCI_ANY_ID, PCI_ANY_ID,
3628 0,
3629 0, pbn_exar_XR17C154 },
3630 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3631 PCI_ANY_ID, PCI_ANY_ID,
3632 0,
3633 0, pbn_exar_XR17C158 },
3634
3635 /*
3636 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3637 */
3638 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3640 pbn_b0_1_115200 },
3641 /*
3642 * ITE
3643 */
3644 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3645 PCI_ANY_ID, PCI_ANY_ID,
3646 0, 0,
3647 pbn_b1_bt_1_115200 },
3648
3649 /*
3650 * IntaShield IS-200
3651 */
3652 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3654 pbn_b2_2_115200 },
3655 /*
3656 * IntaShield IS-400
3657 */
3658 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3660 pbn_b2_4_115200 },
3661 /*
3662 * Perle PCI-RAS cards
3663 */
3664 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3665 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3666 0, 0, pbn_b2_4_921600 },
3667 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3668 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3669 0, 0, pbn_b2_8_921600 },
3670
3671 /*
3672 * Mainpine series cards: Fairly standard layout but fools
3673 * parts of the autodetect in some cases and uses otherwise
3674 * unmatched communications subclasses in the PCI Express case
3675 */
3676
3677 { /* RockForceDUO */
3678 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3679 PCI_VENDOR_ID_MAINPINE, 0x0200,
3680 0, 0, pbn_b0_2_115200 },
3681 { /* RockForceQUATRO */
3682 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3683 PCI_VENDOR_ID_MAINPINE, 0x0300,
3684 0, 0, pbn_b0_4_115200 },
3685 { /* RockForceDUO+ */
3686 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3687 PCI_VENDOR_ID_MAINPINE, 0x0400,
3688 0, 0, pbn_b0_2_115200 },
3689 { /* RockForceQUATRO+ */
3690 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3691 PCI_VENDOR_ID_MAINPINE, 0x0500,
3692 0, 0, pbn_b0_4_115200 },
3693 { /* RockForce+ */
3694 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3695 PCI_VENDOR_ID_MAINPINE, 0x0600,
3696 0, 0, pbn_b0_2_115200 },
3697 { /* RockForce+ */
3698 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3699 PCI_VENDOR_ID_MAINPINE, 0x0700,
3700 0, 0, pbn_b0_4_115200 },
3701 { /* RockForceOCTO+ */
3702 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3703 PCI_VENDOR_ID_MAINPINE, 0x0800,
3704 0, 0, pbn_b0_8_115200 },
3705 { /* RockForceDUO+ */
3706 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3707 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3708 0, 0, pbn_b0_2_115200 },
3709 { /* RockForceQUARTRO+ */
3710 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3711 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3712 0, 0, pbn_b0_4_115200 },
3713 { /* RockForceOCTO+ */
3714 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3715 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3716 0, 0, pbn_b0_8_115200 },
3717 { /* RockForceD1 */
3718 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3719 PCI_VENDOR_ID_MAINPINE, 0x2000,
3720 0, 0, pbn_b0_1_115200 },
3721 { /* RockForceF1 */
3722 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3723 PCI_VENDOR_ID_MAINPINE, 0x2100,
3724 0, 0, pbn_b0_1_115200 },
3725 { /* RockForceD2 */
3726 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3727 PCI_VENDOR_ID_MAINPINE, 0x2200,
3728 0, 0, pbn_b0_2_115200 },
3729 { /* RockForceF2 */
3730 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3731 PCI_VENDOR_ID_MAINPINE, 0x2300,
3732 0, 0, pbn_b0_2_115200 },
3733 { /* RockForceD4 */
3734 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3735 PCI_VENDOR_ID_MAINPINE, 0x2400,
3736 0, 0, pbn_b0_4_115200 },
3737 { /* RockForceF4 */
3738 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3739 PCI_VENDOR_ID_MAINPINE, 0x2500,
3740 0, 0, pbn_b0_4_115200 },
3741 { /* RockForceD8 */
3742 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3743 PCI_VENDOR_ID_MAINPINE, 0x2600,
3744 0, 0, pbn_b0_8_115200 },
3745 { /* RockForceF8 */
3746 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3747 PCI_VENDOR_ID_MAINPINE, 0x2700,
3748 0, 0, pbn_b0_8_115200 },
3749 { /* IQ Express D1 */
3750 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3751 PCI_VENDOR_ID_MAINPINE, 0x3000,
3752 0, 0, pbn_b0_1_115200 },
3753 { /* IQ Express F1 */
3754 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3755 PCI_VENDOR_ID_MAINPINE, 0x3100,
3756 0, 0, pbn_b0_1_115200 },
3757 { /* IQ Express D2 */
3758 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3759 PCI_VENDOR_ID_MAINPINE, 0x3200,
3760 0, 0, pbn_b0_2_115200 },
3761 { /* IQ Express F2 */
3762 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3763 PCI_VENDOR_ID_MAINPINE, 0x3300,
3764 0, 0, pbn_b0_2_115200 },
3765 { /* IQ Express D4 */
3766 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3767 PCI_VENDOR_ID_MAINPINE, 0x3400,
3768 0, 0, pbn_b0_4_115200 },
3769 { /* IQ Express F4 */
3770 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3771 PCI_VENDOR_ID_MAINPINE, 0x3500,
3772 0, 0, pbn_b0_4_115200 },
3773 { /* IQ Express D8 */
3774 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3775 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3776 0, 0, pbn_b0_8_115200 },
3777 { /* IQ Express F8 */
3778 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3779 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3780 0, 0, pbn_b0_8_115200 },
3781
3782
3783 /*
3784 * PA Semi PA6T-1682M on-chip UART
3785 */
3786 { PCI_VENDOR_ID_PASEMI, 0xa004,
3787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3788 pbn_pasemi_1682M },
3789
3790 /*
3791 * National Instruments
3792 */
3793 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3795 pbn_b1_16_115200 },
3796 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3798 pbn_b1_8_115200 },
3799 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3801 pbn_b1_bt_4_115200 },
3802 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3804 pbn_b1_bt_2_115200 },
3805 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3807 pbn_b1_bt_4_115200 },
3808 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3810 pbn_b1_bt_2_115200 },
3811 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3813 pbn_b1_16_115200 },
3814 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3816 pbn_b1_8_115200 },
3817 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3819 pbn_b1_bt_4_115200 },
3820 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3822 pbn_b1_bt_2_115200 },
3823 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3825 pbn_b1_bt_4_115200 },
3826 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3828 pbn_b1_bt_2_115200 },
3829 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3831 pbn_ni8430_2 },
3832 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3834 pbn_ni8430_2 },
3835 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3837 pbn_ni8430_4 },
3838 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3840 pbn_ni8430_4 },
3841 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3843 pbn_ni8430_8 },
3844 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3846 pbn_ni8430_8 },
3847 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3849 pbn_ni8430_16 },
3850 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3852 pbn_ni8430_16 },
3853 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3855 pbn_ni8430_2 },
3856 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3858 pbn_ni8430_2 },
3859 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3861 pbn_ni8430_4 },
3862 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3864 pbn_ni8430_4 },
3865
3866 /*
3867 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3868 */
3869 { PCI_VENDOR_ID_ADDIDATA,
3870 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3871 PCI_ANY_ID,
3872 PCI_ANY_ID,
3873 0,
3874 0,
3875 pbn_b0_4_115200 },
3876
3877 { PCI_VENDOR_ID_ADDIDATA,
3878 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3879 PCI_ANY_ID,
3880 PCI_ANY_ID,
3881 0,
3882 0,
3883 pbn_b0_2_115200 },
3884
3885 { PCI_VENDOR_ID_ADDIDATA,
3886 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3887 PCI_ANY_ID,
3888 PCI_ANY_ID,
3889 0,
3890 0,
3891 pbn_b0_1_115200 },
3892
3893 { PCI_VENDOR_ID_ADDIDATA_OLD,
3894 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3895 PCI_ANY_ID,
3896 PCI_ANY_ID,
3897 0,
3898 0,
3899 pbn_b1_8_115200 },
3900
3901 { PCI_VENDOR_ID_ADDIDATA,
3902 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3903 PCI_ANY_ID,
3904 PCI_ANY_ID,
3905 0,
3906 0,
3907 pbn_b0_4_115200 },
3908
3909 { PCI_VENDOR_ID_ADDIDATA,
3910 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3911 PCI_ANY_ID,
3912 PCI_ANY_ID,
3913 0,
3914 0,
3915 pbn_b0_2_115200 },
3916
3917 { PCI_VENDOR_ID_ADDIDATA,
3918 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3919 PCI_ANY_ID,
3920 PCI_ANY_ID,
3921 0,
3922 0,
3923 pbn_b0_1_115200 },
3924
3925 { PCI_VENDOR_ID_ADDIDATA,
3926 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3927 PCI_ANY_ID,
3928 PCI_ANY_ID,
3929 0,
3930 0,
3931 pbn_b0_4_115200 },
3932
3933 { PCI_VENDOR_ID_ADDIDATA,
3934 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3935 PCI_ANY_ID,
3936 PCI_ANY_ID,
3937 0,
3938 0,
3939 pbn_b0_2_115200 },
3940
3941 { PCI_VENDOR_ID_ADDIDATA,
3942 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3943 PCI_ANY_ID,
3944 PCI_ANY_ID,
3945 0,
3946 0,
3947 pbn_b0_1_115200 },
3948
3949 { PCI_VENDOR_ID_ADDIDATA,
3950 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3951 PCI_ANY_ID,
3952 PCI_ANY_ID,
3953 0,
3954 0,
3955 pbn_b0_8_115200 },
3956
3957 { PCI_VENDOR_ID_ADDIDATA,
3958 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3959 PCI_ANY_ID,
3960 PCI_ANY_ID,
3961 0,
3962 0,
3963 pbn_ADDIDATA_PCIe_4_3906250 },
3964
3965 { PCI_VENDOR_ID_ADDIDATA,
3966 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3967 PCI_ANY_ID,
3968 PCI_ANY_ID,
3969 0,
3970 0,
3971 pbn_ADDIDATA_PCIe_2_3906250 },
3972
3973 { PCI_VENDOR_ID_ADDIDATA,
3974 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3975 PCI_ANY_ID,
3976 PCI_ANY_ID,
3977 0,
3978 0,
3979 pbn_ADDIDATA_PCIe_1_3906250 },
3980
3981 { PCI_VENDOR_ID_ADDIDATA,
3982 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3983 PCI_ANY_ID,
3984 PCI_ANY_ID,
3985 0,
3986 0,
3987 pbn_ADDIDATA_PCIe_8_3906250 },
3988
3989 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3990 PCI_VENDOR_ID_IBM, 0x0299,
3991 0, 0, pbn_b0_bt_2_115200 },
3992
3993 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3994 0xA000, 0x1000,
3995 0, 0, pbn_b0_1_115200 },
3996
3997 /* the 9901 is a rebranded 9912 */
3998 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
3999 0xA000, 0x1000,
4000 0, 0, pbn_b0_1_115200 },
4001
4002 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4003 0xA000, 0x1000,
4004 0, 0, pbn_b0_1_115200 },
4005
4006 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4007 0xA000, 0x1000,
4008 0, 0, pbn_b0_1_115200 },
4009
4010 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4011 0xA000, 0x1000,
4012 0, 0, pbn_b0_1_115200 },
4013
4014 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4015 0xA000, 0x3002,
4016 0, 0, pbn_NETMOS9900_2s_115200 },
4017
4018 /*
4019 * Best Connectivity and Rosewill PCI Multi I/O cards
4020 */
4021
4022 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4023 0xA000, 0x1000,
4024 0, 0, pbn_b0_1_115200 },
4025
4026 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4027 0xA000, 0x3002,
4028 0, 0, pbn_b0_bt_2_115200 },
4029
4030 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4031 0xA000, 0x3004,
4032 0, 0, pbn_b0_bt_4_115200 },
4033 /* Intel CE4100 */
4034 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4036 pbn_ce4100_1_115200 },
4037
4038 /*
4039 * Cronyx Omega PCI
4040 */
4041 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4043 pbn_omegapci },
4044
4045 /*
4046 * These entries match devices with class COMMUNICATION_SERIAL,
4047 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4048 */
4049 { PCI_ANY_ID, PCI_ANY_ID,
4050 PCI_ANY_ID, PCI_ANY_ID,
4051 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4052 0xffff00, pbn_default },
4053 { PCI_ANY_ID, PCI_ANY_ID,
4054 PCI_ANY_ID, PCI_ANY_ID,
4055 PCI_CLASS_COMMUNICATION_MODEM << 8,
4056 0xffff00, pbn_default },
4057 { PCI_ANY_ID, PCI_ANY_ID,
4058 PCI_ANY_ID, PCI_ANY_ID,
4059 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4060 0xffff00, pbn_default },
4061 { 0, }
4062};
4063
4064static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4065 pci_channel_state_t state)
4066{
4067 struct serial_private *priv = pci_get_drvdata(dev);
4068
4069 if (state == pci_channel_io_perm_failure)
4070 return PCI_ERS_RESULT_DISCONNECT;
4071
4072 if (priv)
4073 pciserial_suspend_ports(priv);
4074
4075 pci_disable_device(dev);
4076
4077 return PCI_ERS_RESULT_NEED_RESET;
4078}
4079
4080static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4081{
4082 int rc;
4083
4084 rc = pci_enable_device(dev);
4085
4086 if (rc)
4087 return PCI_ERS_RESULT_DISCONNECT;
4088
4089 pci_restore_state(dev);
4090 pci_save_state(dev);
4091
4092 return PCI_ERS_RESULT_RECOVERED;
4093}
4094
4095static void serial8250_io_resume(struct pci_dev *dev)
4096{
4097 struct serial_private *priv = pci_get_drvdata(dev);
4098
4099 if (priv)
4100 pciserial_resume_ports(priv);
4101}
4102
4103static struct pci_error_handlers serial8250_err_handler = {
4104 .error_detected = serial8250_io_error_detected,
4105 .slot_reset = serial8250_io_slot_reset,
4106 .resume = serial8250_io_resume,
4107};
4108
4109static struct pci_driver serial_pci_driver = {
4110 .name = "serial",
4111 .probe = pciserial_init_one,
4112 .remove = __devexit_p(pciserial_remove_one),
4113#ifdef CONFIG_PM
4114 .suspend = pciserial_suspend_one,
4115 .resume = pciserial_resume_one,
4116#endif
4117 .id_table = serial_pci_tbl,
4118 .err_handler = &serial8250_err_handler,
4119};
4120
4121static int __init serial8250_pci_init(void)
4122{
4123 return pci_register_driver(&serial_pci_driver);
4124}
4125
4126static void __exit serial8250_pci_exit(void)
4127{
4128 pci_unregister_driver(&serial_pci_driver);
4129}
4130
4131module_init(serial8250_pci_init);
4132module_exit(serial8250_pci_exit);
4133
4134MODULE_LICENSE("GPL");
4135MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4136MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
diff --git a/drivers/tty/serial/8250_pnp.c b/drivers/tty/serial/8250_pnp.c
new file mode 100644
index 00000000000..a2f236510ff
--- /dev/null
+++ b/drivers/tty/serial/8250_pnp.c
@@ -0,0 +1,524 @@
1/*
2 * Probe module for 8250/16550-type ISAPNP serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * Ported to the Linux PnP Layer - (C) Adam Belay.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/pnp.h>
18#include <linux/string.h>
19#include <linux/kernel.h>
20#include <linux/serial_core.h>
21#include <linux/bitops.h>
22
23#include <asm/byteorder.h>
24
25#include "8250.h"
26
27#define UNKNOWN_DEV 0x3000
28
29
30static const struct pnp_device_id pnp_dev_table[] = {
31 /* Archtek America Corp. */
32 /* Archtek SmartLink Modem 3334BT Plug & Play */
33 { "AAC000F", 0 },
34 /* Anchor Datacomm BV */
35 /* SXPro 144 External Data Fax Modem Plug & Play */
36 { "ADC0001", 0 },
37 /* SXPro 288 External Data Fax Modem Plug & Play */
38 { "ADC0002", 0 },
39 /* PROLiNK 1456VH ISA PnP K56flex Fax Modem */
40 { "AEI0250", 0 },
41 /* Actiontec ISA PNP 56K X2 Fax Modem */
42 { "AEI1240", 0 },
43 /* Rockwell 56K ACF II Fax+Data+Voice Modem */
44 { "AKY1021", 0 /*SPCI_FL_NO_SHIRQ*/ },
45 /* AZT3005 PnP SOUND DEVICE */
46 { "AZT4001", 0 },
47 /* Best Data Products Inc. Smart One 336F PnP Modem */
48 { "BDP3336", 0 },
49 /* Boca Research */
50 /* Boca Complete Ofc Communicator 14.4 Data-FAX */
51 { "BRI0A49", 0 },
52 /* Boca Research 33,600 ACF Modem */
53 { "BRI1400", 0 },
54 /* Boca 33.6 Kbps Internal FD34FSVD */
55 { "BRI3400", 0 },
56 /* Boca 33.6 Kbps Internal FD34FSVD */
57 { "BRI0A49", 0 },
58 /* Best Data Products Inc. Smart One 336F PnP Modem */
59 { "BDP3336", 0 },
60 /* Computer Peripherals Inc */
61 /* EuroViVa CommCenter-33.6 SP PnP */
62 { "CPI4050", 0 },
63 /* Creative Labs */
64 /* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
65 { "CTL3001", 0 },
66 /* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
67 { "CTL3011", 0 },
68 /* Davicom ISA 33.6K Modem */
69 { "DAV0336", 0 },
70 /* Creative */
71 /* Creative Modem Blaster Flash56 DI5601-1 */
72 { "DMB1032", 0 },
73 /* Creative Modem Blaster V.90 DI5660 */
74 { "DMB2001", 0 },
75 /* E-Tech */
76 /* E-Tech CyberBULLET PC56RVP */
77 { "ETT0002", 0 },
78 /* FUJITSU */
79 /* Fujitsu 33600 PnP-I2 R Plug & Play */
80 { "FUJ0202", 0 },
81 /* Fujitsu FMV-FX431 Plug & Play */
82 { "FUJ0205", 0 },
83 /* Fujitsu 33600 PnP-I4 R Plug & Play */
84 { "FUJ0206", 0 },
85 /* Fujitsu Fax Voice 33600 PNP-I5 R Plug & Play */
86 { "FUJ0209", 0 },
87 /* Archtek America Corp. */
88 /* Archtek SmartLink Modem 3334BT Plug & Play */
89 { "GVC000F", 0 },
90 /* Archtek SmartLink Modem 3334BRV 33.6K Data Fax Voice */
91 { "GVC0303", 0 },
92 /* Hayes */
93 /* Hayes Optima 288 V.34-V.FC + FAX + Voice Plug & Play */
94 { "HAY0001", 0 },
95 /* Hayes Optima 336 V.34 + FAX + Voice PnP */
96 { "HAY000C", 0 },
97 /* Hayes Optima 336B V.34 + FAX + Voice PnP */
98 { "HAY000D", 0 },
99 /* Hayes Accura 56K Ext Fax Modem PnP */
100 { "HAY5670", 0 },
101 /* Hayes Accura 56K Ext Fax Modem PnP */
102 { "HAY5674", 0 },
103 /* Hayes Accura 56K Fax Modem PnP */
104 { "HAY5675", 0 },
105 /* Hayes 288, V.34 + FAX */
106 { "HAYF000", 0 },
107 /* Hayes Optima 288 V.34 + FAX + Voice, Plug & Play */
108 { "HAYF001", 0 },
109 /* IBM */
110 /* IBM Thinkpad 701 Internal Modem Voice */
111 { "IBM0033", 0 },
112 /* Intermec */
113 /* Intermec CV60 touchscreen port */
114 { "PNP4972", 0 },
115 /* Intertex */
116 /* Intertex 28k8 33k6 Voice EXT PnP */
117 { "IXDC801", 0 },
118 /* Intertex 33k6 56k Voice EXT PnP */
119 { "IXDC901", 0 },
120 /* Intertex 28k8 33k6 Voice SP EXT PnP */
121 { "IXDD801", 0 },
122 /* Intertex 33k6 56k Voice SP EXT PnP */
123 { "IXDD901", 0 },
124 /* Intertex 28k8 33k6 Voice SP INT PnP */
125 { "IXDF401", 0 },
126 /* Intertex 28k8 33k6 Voice SP EXT PnP */
127 { "IXDF801", 0 },
128 /* Intertex 33k6 56k Voice SP EXT PnP */
129 { "IXDF901", 0 },
130 /* Kortex International */
131 /* KORTEX 28800 Externe PnP */
132 { "KOR4522", 0 },
133 /* KXPro 33.6 Vocal ASVD PnP */
134 { "KORF661", 0 },
135 /* Lasat */
136 /* LASAT Internet 33600 PnP */
137 { "LAS4040", 0 },
138 /* Lasat Safire 560 PnP */
139 { "LAS4540", 0 },
140 /* Lasat Safire 336 PnP */
141 { "LAS5440", 0 },
142 /* Microcom, Inc. */
143 /* Microcom TravelPorte FAST V.34 Plug & Play */
144 { "MNP0281", 0 },
145 /* Microcom DeskPorte V.34 FAST or FAST+ Plug & Play */
146 { "MNP0336", 0 },
147 /* Microcom DeskPorte FAST EP 28.8 Plug & Play */
148 { "MNP0339", 0 },
149 /* Microcom DeskPorte 28.8P Plug & Play */
150 { "MNP0342", 0 },
151 /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
152 { "MNP0500", 0 },
153 /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
154 { "MNP0501", 0 },
155 /* Microcom DeskPorte 28.8S Internal Plug & Play */
156 { "MNP0502", 0 },
157 /* Motorola */
158 /* Motorola BitSURFR Plug & Play */
159 { "MOT1105", 0 },
160 /* Motorola TA210 Plug & Play */
161 { "MOT1111", 0 },
162 /* Motorola HMTA 200 (ISDN) Plug & Play */
163 { "MOT1114", 0 },
164 /* Motorola BitSURFR Plug & Play */
165 { "MOT1115", 0 },
166 /* Motorola Lifestyle 28.8 Internal */
167 { "MOT1190", 0 },
168 /* Motorola V.3400 Plug & Play */
169 { "MOT1501", 0 },
170 /* Motorola Lifestyle 28.8 V.34 Plug & Play */
171 { "MOT1502", 0 },
172 /* Motorola Power 28.8 V.34 Plug & Play */
173 { "MOT1505", 0 },
174 /* Motorola ModemSURFR External 28.8 Plug & Play */
175 { "MOT1509", 0 },
176 /* Motorola Premier 33.6 Desktop Plug & Play */
177 { "MOT150A", 0 },
178 /* Motorola VoiceSURFR 56K External PnP */
179 { "MOT150F", 0 },
180 /* Motorola ModemSURFR 56K External PnP */
181 { "MOT1510", 0 },
182 /* Motorola ModemSURFR 56K Internal PnP */
183 { "MOT1550", 0 },
184 /* Motorola ModemSURFR Internal 28.8 Plug & Play */
185 { "MOT1560", 0 },
186 /* Motorola Premier 33.6 Internal Plug & Play */
187 { "MOT1580", 0 },
188 /* Motorola OnlineSURFR 28.8 Internal Plug & Play */
189 { "MOT15B0", 0 },
190 /* Motorola VoiceSURFR 56K Internal PnP */
191 { "MOT15F0", 0 },
192 /* Com 1 */
193 /* Deskline K56 Phone System PnP */
194 { "MVX00A1", 0 },
195 /* PC Rider K56 Phone System PnP */
196 { "MVX00F2", 0 },
197 /* NEC 98NOTE SPEAKER PHONE FAX MODEM(33600bps) */
198 { "nEC8241", 0 },
199 /* Pace 56 Voice Internal Plug & Play Modem */
200 { "PMC2430", 0 },
201 /* Generic */
202 /* Generic standard PC COM port */
203 { "PNP0500", 0 },
204 /* Generic 16550A-compatible COM port */
205 { "PNP0501", 0 },
206 /* Compaq 14400 Modem */
207 { "PNPC000", 0 },
208 /* Compaq 2400/9600 Modem */
209 { "PNPC001", 0 },
210 /* Dial-Up Networking Serial Cable between 2 PCs */
211 { "PNPC031", 0 },
212 /* Dial-Up Networking Parallel Cable between 2 PCs */
213 { "PNPC032", 0 },
214 /* Standard 9600 bps Modem */
215 { "PNPC100", 0 },
216 /* Standard 14400 bps Modem */
217 { "PNPC101", 0 },
218 /* Standard 28800 bps Modem*/
219 { "PNPC102", 0 },
220 /* Standard Modem*/
221 { "PNPC103", 0 },
222 /* Standard 9600 bps Modem*/
223 { "PNPC104", 0 },
224 /* Standard 14400 bps Modem*/
225 { "PNPC105", 0 },
226 /* Standard 28800 bps Modem*/
227 { "PNPC106", 0 },
228 /* Standard Modem */
229 { "PNPC107", 0 },
230 /* Standard 9600 bps Modem */
231 { "PNPC108", 0 },
232 /* Standard 14400 bps Modem */
233 { "PNPC109", 0 },
234 /* Standard 28800 bps Modem */
235 { "PNPC10A", 0 },
236 /* Standard Modem */
237 { "PNPC10B", 0 },
238 /* Standard 9600 bps Modem */
239 { "PNPC10C", 0 },
240 /* Standard 14400 bps Modem */
241 { "PNPC10D", 0 },
242 /* Standard 28800 bps Modem */
243 { "PNPC10E", 0 },
244 /* Standard Modem */
245 { "PNPC10F", 0 },
246 /* Standard PCMCIA Card Modem */
247 { "PNP2000", 0 },
248 /* Rockwell */
249 /* Modular Technology */
250 /* Rockwell 33.6 DPF Internal PnP */
251 /* Modular Technology 33.6 Internal PnP */
252 { "ROK0030", 0 },
253 /* Kortex International */
254 /* KORTEX 14400 Externe PnP */
255 { "ROK0100", 0 },
256 /* Rockwell 28.8 */
257 { "ROK4120", 0 },
258 /* Viking Components, Inc */
259 /* Viking 28.8 INTERNAL Fax+Data+Voice PnP */
260 { "ROK4920", 0 },
261 /* Rockwell */
262 /* British Telecom */
263 /* Modular Technology */
264 /* Rockwell 33.6 DPF External PnP */
265 /* BT Prologue 33.6 External PnP */
266 /* Modular Technology 33.6 External PnP */
267 { "RSS00A0", 0 },
268 /* Viking 56K FAX INT */
269 { "RSS0262", 0 },
270 /* K56 par,VV,Voice,Speakphone,AudioSpan,PnP */
271 { "RSS0250", 0 },
272 /* SupraExpress 28.8 Data/Fax PnP modem */
273 { "SUP1310", 0 },
274 /* SupraExpress 336i PnP Voice Modem */
275 { "SUP1381", 0 },
276 /* SupraExpress 33.6 Data/Fax PnP modem */
277 { "SUP1421", 0 },
278 /* SupraExpress 33.6 Data/Fax PnP modem */
279 { "SUP1590", 0 },
280 /* SupraExpress 336i Sp ASVD */
281 { "SUP1620", 0 },
282 /* SupraExpress 33.6 Data/Fax PnP modem */
283 { "SUP1760", 0 },
284 /* SupraExpress 56i Sp Intl */
285 { "SUP2171", 0 },
286 /* Phoebe Micro */
287 /* Phoebe Micro 33.6 Data Fax 1433VQH Plug & Play */
288 { "TEX0011", 0 },
289 /* Archtek America Corp. */
290 /* Archtek SmartLink Modem 3334BT Plug & Play */
291 { "UAC000F", 0 },
292 /* 3Com Corp. */
293 /* Gateway Telepath IIvi 33.6 */
294 { "USR0000", 0 },
295 /* U.S. Robotics Sporster 33.6K Fax INT PnP */
296 { "USR0002", 0 },
297 /* Sportster Vi 14.4 PnP FAX Voicemail */
298 { "USR0004", 0 },
299 /* U.S. Robotics 33.6K Voice INT PnP */
300 { "USR0006", 0 },
301 /* U.S. Robotics 33.6K Voice EXT PnP */
302 { "USR0007", 0 },
303 /* U.S. Robotics Courier V.Everything INT PnP */
304 { "USR0009", 0 },
305 /* U.S. Robotics 33.6K Voice INT PnP */
306 { "USR2002", 0 },
307 /* U.S. Robotics 56K Voice INT PnP */
308 { "USR2070", 0 },
309 /* U.S. Robotics 56K Voice EXT PnP */
310 { "USR2080", 0 },
311 /* U.S. Robotics 56K FAX INT */
312 { "USR3031", 0 },
313 /* U.S. Robotics 56K FAX INT */
314 { "USR3050", 0 },
315 /* U.S. Robotics 56K Voice INT PnP */
316 { "USR3070", 0 },
317 /* U.S. Robotics 56K Voice EXT PnP */
318 { "USR3080", 0 },
319 /* U.S. Robotics 56K Voice INT PnP */
320 { "USR3090", 0 },
321 /* U.S. Robotics 56K Message */
322 { "USR9100", 0 },
323 /* U.S. Robotics 56K FAX EXT PnP*/
324 { "USR9160", 0 },
325 /* U.S. Robotics 56K FAX INT PnP*/
326 { "USR9170", 0 },
327 /* U.S. Robotics 56K Voice EXT PnP*/
328 { "USR9180", 0 },
329 /* U.S. Robotics 56K Voice INT PnP*/
330 { "USR9190", 0 },
331 /* Wacom tablets */
332 { "WACFXXX", 0 },
333 /* Compaq touchscreen */
334 { "FPI2002", 0 },
335 /* Fujitsu Stylistic touchscreens */
336 { "FUJ02B2", 0 },
337 { "FUJ02B3", 0 },
338 /* Fujitsu Stylistic LT touchscreens */
339 { "FUJ02B4", 0 },
340 /* Passive Fujitsu Stylistic touchscreens */
341 { "FUJ02B6", 0 },
342 { "FUJ02B7", 0 },
343 { "FUJ02B8", 0 },
344 { "FUJ02B9", 0 },
345 { "FUJ02BC", 0 },
346 /* Fujitsu Wacom Tablet PC device */
347 { "FUJ02E5", 0 },
348 /* Fujitsu P-series tablet PC device */
349 { "FUJ02E6", 0 },
350 /* Fujitsu Wacom 2FGT Tablet PC device */
351 { "FUJ02E7", 0 },
352 /* Fujitsu Wacom 1FGT Tablet PC device */
353 { "FUJ02E9", 0 },
354 /*
355 * LG C1 EXPRESS DUAL (C1-PB11A3) touch screen (actually a FUJ02E6 in
356 * disguise)
357 */
358 { "LTS0001", 0 },
359 /* Rockwell's (PORALiNK) 33600 INT PNP */
360 { "WCI0003", 0 },
361 /* Unknown PnP modems */
362 { "PNPCXXX", UNKNOWN_DEV },
363 /* More unknown PnP modems */
364 { "PNPDXXX", UNKNOWN_DEV },
365 { "", 0 }
366};
367
368MODULE_DEVICE_TABLE(pnp, pnp_dev_table);
369
370static char *modem_names[] __devinitdata = {
371 "MODEM", "Modem", "modem", "FAX", "Fax", "fax",
372 "56K", "56k", "K56", "33.6", "28.8", "14.4",
373 "33,600", "28,800", "14,400", "33.600", "28.800", "14.400",
374 "33600", "28800", "14400", "V.90", "V.34", "V.32", NULL
375};
376
377static int __devinit check_name(char *name)
378{
379 char **tmp;
380
381 for (tmp = modem_names; *tmp; tmp++)
382 if (strstr(name, *tmp))
383 return 1;
384
385 return 0;
386}
387
388static int __devinit check_resources(struct pnp_dev *dev)
389{
390 resource_size_t base[] = {0x2f8, 0x3f8, 0x2e8, 0x3e8};
391 int i;
392
393 for (i = 0; i < ARRAY_SIZE(base); i++) {
394 if (pnp_possible_config(dev, IORESOURCE_IO, base[i], 8))
395 return 1;
396 }
397
398 return 0;
399}
400
401/*
402 * Given a complete unknown PnP device, try to use some heuristics to
403 * detect modems. Currently use such heuristic set:
404 * - dev->name or dev->bus->name must contain "modem" substring;
405 * - device must have only one IO region (8 byte long) with base address
406 * 0x2e8, 0x3e8, 0x2f8 or 0x3f8.
407 *
408 * Such detection looks very ugly, but can detect at least some of numerous
409 * PnP modems, alternatively we must hardcode all modems in pnp_devices[]
410 * table.
411 */
412static int __devinit serial_pnp_guess_board(struct pnp_dev *dev, int *flags)
413{
414 if (!(check_name(pnp_dev_name(dev)) ||
415 (dev->card && check_name(dev->card->name))))
416 return -ENODEV;
417
418 if (check_resources(dev))
419 return 0;
420
421 return -ENODEV;
422}
423
424static int __devinit
425serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id)
426{
427 struct uart_port port;
428 int ret, line, flags = dev_id->driver_data;
429
430 if (flags & UNKNOWN_DEV) {
431 ret = serial_pnp_guess_board(dev, &flags);
432 if (ret < 0)
433 return ret;
434 }
435
436 memset(&port, 0, sizeof(struct uart_port));
437 if (pnp_irq_valid(dev, 0))
438 port.irq = pnp_irq(dev, 0);
439 if (pnp_port_valid(dev, 0)) {
440 port.iobase = pnp_port_start(dev, 0);
441 port.iotype = UPIO_PORT;
442 } else if (pnp_mem_valid(dev, 0)) {
443 port.mapbase = pnp_mem_start(dev, 0);
444 port.iotype = UPIO_MEM;
445 port.flags = UPF_IOREMAP;
446 } else
447 return -ENODEV;
448
449#ifdef SERIAL_DEBUG_PNP
450 printk(KERN_DEBUG
451 "Setup PNP port: port %x, mem 0x%lx, irq %d, type %d\n",
452 port.iobase, port.mapbase, port.irq, port.iotype);
453#endif
454
455 port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
456 if (pnp_irq_flags(dev, 0) & IORESOURCE_IRQ_SHAREABLE)
457 port.flags |= UPF_SHARE_IRQ;
458 port.uartclk = 1843200;
459 port.dev = &dev->dev;
460
461 line = serial8250_register_port(&port);
462 if (line < 0)
463 return -ENODEV;
464
465 pnp_set_drvdata(dev, (void *)((long)line + 1));
466 return 0;
467}
468
469static void __devexit serial_pnp_remove(struct pnp_dev *dev)
470{
471 long line = (long)pnp_get_drvdata(dev);
472 if (line)
473 serial8250_unregister_port(line - 1);
474}
475
476#ifdef CONFIG_PM
477static int serial_pnp_suspend(struct pnp_dev *dev, pm_message_t state)
478{
479 long line = (long)pnp_get_drvdata(dev);
480
481 if (!line)
482 return -ENODEV;
483 serial8250_suspend_port(line - 1);
484 return 0;
485}
486
487static int serial_pnp_resume(struct pnp_dev *dev)
488{
489 long line = (long)pnp_get_drvdata(dev);
490
491 if (!line)
492 return -ENODEV;
493 serial8250_resume_port(line - 1);
494 return 0;
495}
496#else
497#define serial_pnp_suspend NULL
498#define serial_pnp_resume NULL
499#endif /* CONFIG_PM */
500
501static struct pnp_driver serial_pnp_driver = {
502 .name = "serial",
503 .probe = serial_pnp_probe,
504 .remove = __devexit_p(serial_pnp_remove),
505 .suspend = serial_pnp_suspend,
506 .resume = serial_pnp_resume,
507 .id_table = pnp_dev_table,
508};
509
510static int __init serial8250_pnp_init(void)
511{
512 return pnp_register_driver(&serial_pnp_driver);
513}
514
515static void __exit serial8250_pnp_exit(void)
516{
517 pnp_unregister_driver(&serial_pnp_driver);
518}
519
520module_init(serial8250_pnp_init);
521module_exit(serial8250_pnp_exit);
522
523MODULE_LICENSE("GPL");
524MODULE_DESCRIPTION("Generic 8250/16x50 PnP serial driver");
diff --git a/drivers/tty/serial/bfin_5xx.c b/drivers/tty/serial/bfin_5xx.c
new file mode 100644
index 00000000000..ff6979181ac
--- /dev/null
+++ b/drivers/tty/serial/bfin_5xx.c
@@ -0,0 +1,1596 @@
1/*
2 * Blackfin On-Chip Serial Driver
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#define DRIVER_NAME "bfin-uart"
16#define pr_fmt(fmt) DRIVER_NAME ": " fmt
17
18#include <linux/module.h>
19#include <linux/ioport.h>
20#include <linux/gfp.h>
21#include <linux/io.h>
22#include <linux/init.h>
23#include <linux/console.h>
24#include <linux/sysrq.h>
25#include <linux/platform_device.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/serial_core.h>
29#include <linux/gpio.h>
30#include <linux/irq.h>
31#include <linux/kgdb.h>
32#include <linux/slab.h>
33#include <linux/dma-mapping.h>
34
35#include <asm/portmux.h>
36#include <asm/cacheflush.h>
37#include <asm/dma.h>
38
39#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
40#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
41#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
42#include <asm/bfin_serial.h>
43
44#ifdef CONFIG_SERIAL_BFIN_MODULE
45# undef CONFIG_EARLY_PRINTK
46#endif
47
48#ifdef CONFIG_SERIAL_BFIN_MODULE
49# undef CONFIG_EARLY_PRINTK
50#endif
51
52/* UART name and device definitions */
53#define BFIN_SERIAL_DEV_NAME "ttyBF"
54#define BFIN_SERIAL_MAJOR 204
55#define BFIN_SERIAL_MINOR 64
56
57static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS];
58
59#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
60 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
61
62# ifndef CONFIG_SERIAL_BFIN_PIO
63# error KGDB only support UART in PIO mode.
64# endif
65
66static int kgdboc_port_line;
67static int kgdboc_break_enabled;
68#endif
69/*
70 * Setup for console. Argument comes from the menuconfig
71 */
72#define DMA_RX_XCOUNT 512
73#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
74
75#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
76
77#ifdef CONFIG_SERIAL_BFIN_DMA
78static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
79#else
80static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
81#endif
82
83static void bfin_serial_reset_irda(struct uart_port *port);
84
85#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
86 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
87static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
88{
89 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
90 if (uart->cts_pin < 0)
91 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
92
93 /* CTS PIN is negative assertive. */
94 if (UART_GET_CTS(uart))
95 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
96 else
97 return TIOCM_DSR | TIOCM_CAR;
98}
99
100static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
101{
102 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
103 if (uart->rts_pin < 0)
104 return;
105
106 /* RTS PIN is negative assertive. */
107 if (mctrl & TIOCM_RTS)
108 UART_ENABLE_RTS(uart);
109 else
110 UART_DISABLE_RTS(uart);
111}
112
113/*
114 * Handle any change of modem status signal.
115 */
116static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
117{
118 struct bfin_serial_port *uart = dev_id;
119 unsigned int status;
120
121 status = bfin_serial_get_mctrl(&uart->port);
122 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
123#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
124 uart->scts = 1;
125 UART_CLEAR_SCTS(uart);
126 UART_CLEAR_IER(uart, EDSSI);
127#endif
128
129 return IRQ_HANDLED;
130}
131#else
132static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
133{
134 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
135}
136
137static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
138{
139}
140#endif
141
142/*
143 * interrupts are disabled on entry
144 */
145static void bfin_serial_stop_tx(struct uart_port *port)
146{
147 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
148#ifdef CONFIG_SERIAL_BFIN_DMA
149 struct circ_buf *xmit = &uart->port.state->xmit;
150#endif
151
152 while (!(UART_GET_LSR(uart) & TEMT))
153 cpu_relax();
154
155#ifdef CONFIG_SERIAL_BFIN_DMA
156 disable_dma(uart->tx_dma_channel);
157 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
158 uart->port.icount.tx += uart->tx_count;
159 uart->tx_count = 0;
160 uart->tx_done = 1;
161#else
162#ifdef CONFIG_BF54x
163 /* Clear TFI bit */
164 UART_PUT_LSR(uart, TFI);
165#endif
166 UART_CLEAR_IER(uart, ETBEI);
167#endif
168}
169
170/*
171 * port is locked and interrupts are disabled
172 */
173static void bfin_serial_start_tx(struct uart_port *port)
174{
175 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
176 struct tty_struct *tty = uart->port.state->port.tty;
177
178#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
179 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
180 uart->scts = 0;
181 uart_handle_cts_change(&uart->port, uart->scts);
182 }
183#endif
184
185 /*
186 * To avoid losting RX interrupt, we reset IR function
187 * before sending data.
188 */
189 if (tty->termios->c_line == N_IRDA)
190 bfin_serial_reset_irda(port);
191
192#ifdef CONFIG_SERIAL_BFIN_DMA
193 if (uart->tx_done)
194 bfin_serial_dma_tx_chars(uart);
195#else
196 UART_SET_IER(uart, ETBEI);
197 bfin_serial_tx_chars(uart);
198#endif
199}
200
201/*
202 * Interrupts are enabled
203 */
204static void bfin_serial_stop_rx(struct uart_port *port)
205{
206 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
207
208 UART_CLEAR_IER(uart, ERBFI);
209}
210
211/*
212 * Set the modem control timer to fire immediately.
213 */
214static void bfin_serial_enable_ms(struct uart_port *port)
215{
216}
217
218
219#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
220# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
221# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
222#else
223# define UART_GET_ANOMALY_THRESHOLD(uart) 0
224# define UART_SET_ANOMALY_THRESHOLD(uart, v)
225#endif
226
227#ifdef CONFIG_SERIAL_BFIN_PIO
228static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
229{
230 struct tty_struct *tty = NULL;
231 unsigned int status, ch, flg;
232 static struct timeval anomaly_start = { .tv_sec = 0 };
233
234 status = UART_GET_LSR(uart);
235 UART_CLEAR_LSR(uart);
236
237 ch = UART_GET_CHAR(uart);
238 uart->port.icount.rx++;
239
240#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
241 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
242 if (kgdb_connected && kgdboc_port_line == uart->port.line
243 && kgdboc_break_enabled)
244 if (ch == 0x3) {/* Ctrl + C */
245 kgdb_breakpoint();
246 return;
247 }
248
249 if (!uart->port.state || !uart->port.state->port.tty)
250 return;
251#endif
252 tty = uart->port.state->port.tty;
253
254 if (ANOMALY_05000363) {
255 /* The BF533 (and BF561) family of processors have a nice anomaly
256 * where they continuously generate characters for a "single" break.
257 * We have to basically ignore this flood until the "next" valid
258 * character comes across. Due to the nature of the flood, it is
259 * not possible to reliably catch bytes that are sent too quickly
260 * after this break. So application code talking to the Blackfin
261 * which sends a break signal must allow at least 1.5 character
262 * times after the end of the break for things to stabilize. This
263 * timeout was picked as it must absolutely be larger than 1
264 * character time +/- some percent. So 1.5 sounds good. All other
265 * Blackfin families operate properly. Woo.
266 */
267 if (anomaly_start.tv_sec) {
268 struct timeval curr;
269 suseconds_t usecs;
270
271 if ((~ch & (~ch + 1)) & 0xff)
272 goto known_good_char;
273
274 do_gettimeofday(&curr);
275 if (curr.tv_sec - anomaly_start.tv_sec > 1)
276 goto known_good_char;
277
278 usecs = 0;
279 if (curr.tv_sec != anomaly_start.tv_sec)
280 usecs += USEC_PER_SEC;
281 usecs += curr.tv_usec - anomaly_start.tv_usec;
282
283 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
284 goto known_good_char;
285
286 if (ch)
287 anomaly_start.tv_sec = 0;
288 else
289 anomaly_start = curr;
290
291 return;
292
293 known_good_char:
294 status &= ~BI;
295 anomaly_start.tv_sec = 0;
296 }
297 }
298
299 if (status & BI) {
300 if (ANOMALY_05000363)
301 if (bfin_revid() < 5)
302 do_gettimeofday(&anomaly_start);
303 uart->port.icount.brk++;
304 if (uart_handle_break(&uart->port))
305 goto ignore_char;
306 status &= ~(PE | FE);
307 }
308 if (status & PE)
309 uart->port.icount.parity++;
310 if (status & OE)
311 uart->port.icount.overrun++;
312 if (status & FE)
313 uart->port.icount.frame++;
314
315 status &= uart->port.read_status_mask;
316
317 if (status & BI)
318 flg = TTY_BREAK;
319 else if (status & PE)
320 flg = TTY_PARITY;
321 else if (status & FE)
322 flg = TTY_FRAME;
323 else
324 flg = TTY_NORMAL;
325
326 if (uart_handle_sysrq_char(&uart->port, ch))
327 goto ignore_char;
328
329 uart_insert_char(&uart->port, status, OE, ch, flg);
330
331 ignore_char:
332 tty_flip_buffer_push(tty);
333}
334
335static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
336{
337 struct circ_buf *xmit = &uart->port.state->xmit;
338
339 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
340#ifdef CONFIG_BF54x
341 /* Clear TFI bit */
342 UART_PUT_LSR(uart, TFI);
343#endif
344 /* Anomaly notes:
345 * 05000215 - we always clear ETBEI within last UART TX
346 * interrupt to end a string. It is always set
347 * when start a new tx.
348 */
349 UART_CLEAR_IER(uart, ETBEI);
350 return;
351 }
352
353 if (uart->port.x_char) {
354 UART_PUT_CHAR(uart, uart->port.x_char);
355 uart->port.icount.tx++;
356 uart->port.x_char = 0;
357 }
358
359 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
360 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
361 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
362 uart->port.icount.tx++;
363 }
364
365 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
366 uart_write_wakeup(&uart->port);
367}
368
369static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
370{
371 struct bfin_serial_port *uart = dev_id;
372
373 while (UART_GET_LSR(uart) & DR)
374 bfin_serial_rx_chars(uart);
375
376 return IRQ_HANDLED;
377}
378
379static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
380{
381 struct bfin_serial_port *uart = dev_id;
382
383#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
384 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
385 uart->scts = 0;
386 uart_handle_cts_change(&uart->port, uart->scts);
387 }
388#endif
389 spin_lock(&uart->port.lock);
390 if (UART_GET_LSR(uart) & THRE)
391 bfin_serial_tx_chars(uart);
392 spin_unlock(&uart->port.lock);
393
394 return IRQ_HANDLED;
395}
396#endif
397
398#ifdef CONFIG_SERIAL_BFIN_DMA
399static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
400{
401 struct circ_buf *xmit = &uart->port.state->xmit;
402
403 uart->tx_done = 0;
404
405 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
406 uart->tx_count = 0;
407 uart->tx_done = 1;
408 return;
409 }
410
411 if (uart->port.x_char) {
412 UART_PUT_CHAR(uart, uart->port.x_char);
413 uart->port.icount.tx++;
414 uart->port.x_char = 0;
415 }
416
417 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
418 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
419 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
420 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
421 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
422 set_dma_config(uart->tx_dma_channel,
423 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
424 INTR_ON_BUF,
425 DIMENSION_LINEAR,
426 DATA_SIZE_8,
427 DMA_SYNC_RESTART));
428 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
429 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
430 set_dma_x_modify(uart->tx_dma_channel, 1);
431 SSYNC();
432 enable_dma(uart->tx_dma_channel);
433
434 UART_SET_IER(uart, ETBEI);
435}
436
437static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
438{
439 struct tty_struct *tty = uart->port.state->port.tty;
440 int i, flg, status;
441
442 status = UART_GET_LSR(uart);
443 UART_CLEAR_LSR(uart);
444
445 uart->port.icount.rx +=
446 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
447 UART_XMIT_SIZE);
448
449 if (status & BI) {
450 uart->port.icount.brk++;
451 if (uart_handle_break(&uart->port))
452 goto dma_ignore_char;
453 status &= ~(PE | FE);
454 }
455 if (status & PE)
456 uart->port.icount.parity++;
457 if (status & OE)
458 uart->port.icount.overrun++;
459 if (status & FE)
460 uart->port.icount.frame++;
461
462 status &= uart->port.read_status_mask;
463
464 if (status & BI)
465 flg = TTY_BREAK;
466 else if (status & PE)
467 flg = TTY_PARITY;
468 else if (status & FE)
469 flg = TTY_FRAME;
470 else
471 flg = TTY_NORMAL;
472
473 for (i = uart->rx_dma_buf.tail; ; i++) {
474 if (i >= UART_XMIT_SIZE)
475 i = 0;
476 if (i == uart->rx_dma_buf.head)
477 break;
478 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
479 uart_insert_char(&uart->port, status, OE,
480 uart->rx_dma_buf.buf[i], flg);
481 }
482
483 dma_ignore_char:
484 tty_flip_buffer_push(tty);
485}
486
487void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
488{
489 int x_pos, pos;
490
491 dma_disable_irq_nosync(uart->rx_dma_channel);
492 spin_lock_bh(&uart->rx_lock);
493
494 /* 2D DMA RX buffer ring is used. Because curr_y_count and
495 * curr_x_count can't be read as an atomic operation,
496 * curr_y_count should be read before curr_x_count. When
497 * curr_x_count is read, curr_y_count may already indicate
498 * next buffer line. But, the position calculated here is
499 * still indicate the old line. The wrong position data may
500 * be smaller than current buffer tail, which cause garbages
501 * are received if it is not prohibit.
502 */
503 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
504 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
505 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
506 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
507 uart->rx_dma_nrows = 0;
508 x_pos = DMA_RX_XCOUNT - x_pos;
509 if (x_pos == DMA_RX_XCOUNT)
510 x_pos = 0;
511
512 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
513 /* Ignore receiving data if new position is in the same line of
514 * current buffer tail and small.
515 */
516 if (pos > uart->rx_dma_buf.tail ||
517 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
518 uart->rx_dma_buf.head = pos;
519 bfin_serial_dma_rx_chars(uart);
520 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
521 }
522
523 spin_unlock_bh(&uart->rx_lock);
524 dma_enable_irq(uart->rx_dma_channel);
525
526 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
527}
528
529static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
530{
531 struct bfin_serial_port *uart = dev_id;
532 struct circ_buf *xmit = &uart->port.state->xmit;
533
534#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
535 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
536 uart->scts = 0;
537 uart_handle_cts_change(&uart->port, uart->scts);
538 }
539#endif
540
541 spin_lock(&uart->port.lock);
542 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
543 disable_dma(uart->tx_dma_channel);
544 clear_dma_irqstat(uart->tx_dma_channel);
545 /* Anomaly notes:
546 * 05000215 - we always clear ETBEI within last UART TX
547 * interrupt to end a string. It is always set
548 * when start a new tx.
549 */
550 UART_CLEAR_IER(uart, ETBEI);
551 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
552 uart->port.icount.tx += uart->tx_count;
553
554 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
555 uart_write_wakeup(&uart->port);
556
557 bfin_serial_dma_tx_chars(uart);
558 }
559
560 spin_unlock(&uart->port.lock);
561 return IRQ_HANDLED;
562}
563
564static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
565{
566 struct bfin_serial_port *uart = dev_id;
567 unsigned short irqstat;
568 int x_pos, pos;
569
570 spin_lock(&uart->rx_lock);
571 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
572 clear_dma_irqstat(uart->rx_dma_channel);
573
574 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
575 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
576 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
577 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
578 uart->rx_dma_nrows = 0;
579
580 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
581 if (pos > uart->rx_dma_buf.tail ||
582 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
583 uart->rx_dma_buf.head = pos;
584 bfin_serial_dma_rx_chars(uart);
585 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
586 }
587
588 spin_unlock(&uart->rx_lock);
589
590 return IRQ_HANDLED;
591}
592#endif
593
594/*
595 * Return TIOCSER_TEMT when transmitter is not busy.
596 */
597static unsigned int bfin_serial_tx_empty(struct uart_port *port)
598{
599 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
600 unsigned short lsr;
601
602 lsr = UART_GET_LSR(uart);
603 if (lsr & TEMT)
604 return TIOCSER_TEMT;
605 else
606 return 0;
607}
608
609static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
610{
611 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
612 u16 lcr = UART_GET_LCR(uart);
613 if (break_state)
614 lcr |= SB;
615 else
616 lcr &= ~SB;
617 UART_PUT_LCR(uart, lcr);
618 SSYNC();
619}
620
621static int bfin_serial_startup(struct uart_port *port)
622{
623 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
624
625#ifdef CONFIG_SERIAL_BFIN_DMA
626 dma_addr_t dma_handle;
627
628 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
629 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
630 return -EBUSY;
631 }
632
633 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
634 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
635 free_dma(uart->rx_dma_channel);
636 return -EBUSY;
637 }
638
639 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
640 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
641
642 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
643 uart->rx_dma_buf.head = 0;
644 uart->rx_dma_buf.tail = 0;
645 uart->rx_dma_nrows = 0;
646
647 set_dma_config(uart->rx_dma_channel,
648 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
649 INTR_ON_ROW, DIMENSION_2D,
650 DATA_SIZE_8,
651 DMA_SYNC_RESTART));
652 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
653 set_dma_x_modify(uart->rx_dma_channel, 1);
654 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
655 set_dma_y_modify(uart->rx_dma_channel, 1);
656 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
657 enable_dma(uart->rx_dma_channel);
658
659 uart->rx_dma_timer.data = (unsigned long)(uart);
660 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
661 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
662 add_timer(&(uart->rx_dma_timer));
663#else
664# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
665 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
666 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
667 kgdboc_break_enabled = 0;
668 else {
669# endif
670 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
671 "BFIN_UART_RX", uart)) {
672 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
673 return -EBUSY;
674 }
675
676 if (request_irq
677 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
678 "BFIN_UART_TX", uart)) {
679 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
680 free_irq(uart->port.irq, uart);
681 return -EBUSY;
682 }
683
684# ifdef CONFIG_BF54x
685 {
686 /*
687 * UART2 and UART3 on BF548 share interrupt PINs and DMA
688 * controllers with SPORT2 and SPORT3. UART rx and tx
689 * interrupts are generated in PIO mode only when configure
690 * their peripheral mapping registers properly, which means
691 * request corresponding DMA channels in PIO mode as well.
692 */
693 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
694
695 switch (uart->port.irq) {
696 case IRQ_UART3_RX:
697 uart_dma_ch_rx = CH_UART3_RX;
698 uart_dma_ch_tx = CH_UART3_TX;
699 break;
700 case IRQ_UART2_RX:
701 uart_dma_ch_rx = CH_UART2_RX;
702 uart_dma_ch_tx = CH_UART2_TX;
703 break;
704 default:
705 uart_dma_ch_rx = uart_dma_ch_tx = 0;
706 break;
707 };
708
709 if (uart_dma_ch_rx &&
710 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
711 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
712 free_irq(uart->port.irq, uart);
713 free_irq(uart->port.irq + 1, uart);
714 return -EBUSY;
715 }
716 if (uart_dma_ch_tx &&
717 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
718 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
719 free_dma(uart_dma_ch_rx);
720 free_irq(uart->port.irq, uart);
721 free_irq(uart->port.irq + 1, uart);
722 return -EBUSY;
723 }
724 }
725# endif
726# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
727 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
728 }
729# endif
730#endif
731
732#ifdef CONFIG_SERIAL_BFIN_CTSRTS
733 if (uart->cts_pin >= 0) {
734 if (request_irq(gpio_to_irq(uart->cts_pin),
735 bfin_serial_mctrl_cts_int,
736 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
737 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
738 uart->cts_pin = -1;
739 pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n");
740 }
741 }
742 if (uart->rts_pin >= 0) {
743 gpio_direction_output(uart->rts_pin, 0);
744 }
745#endif
746#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
747 if (uart->cts_pin >= 0 && request_irq(uart->status_irq,
748 bfin_serial_mctrl_cts_int,
749 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
750 uart->cts_pin = -1;
751 pr_info("Unable to attach BlackFin UART Modem Status interrupt.\n");
752 }
753
754 /* CTS RTS PINs are negative assertive. */
755 UART_PUT_MCR(uart, ACTS);
756 UART_SET_IER(uart, EDSSI);
757#endif
758
759 UART_SET_IER(uart, ERBFI);
760 return 0;
761}
762
763static void bfin_serial_shutdown(struct uart_port *port)
764{
765 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
766
767#ifdef CONFIG_SERIAL_BFIN_DMA
768 disable_dma(uart->tx_dma_channel);
769 free_dma(uart->tx_dma_channel);
770 disable_dma(uart->rx_dma_channel);
771 free_dma(uart->rx_dma_channel);
772 del_timer(&(uart->rx_dma_timer));
773 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
774#else
775#ifdef CONFIG_BF54x
776 switch (uart->port.irq) {
777 case IRQ_UART3_RX:
778 free_dma(CH_UART3_RX);
779 free_dma(CH_UART3_TX);
780 break;
781 case IRQ_UART2_RX:
782 free_dma(CH_UART2_RX);
783 free_dma(CH_UART2_TX);
784 break;
785 default:
786 break;
787 };
788#endif
789 free_irq(uart->port.irq, uart);
790 free_irq(uart->port.irq+1, uart);
791#endif
792
793#ifdef CONFIG_SERIAL_BFIN_CTSRTS
794 if (uart->cts_pin >= 0)
795 free_irq(gpio_to_irq(uart->cts_pin), uart);
796#endif
797#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
798 if (uart->cts_pin >= 0)
799 free_irq(uart->status_irq, uart);
800#endif
801}
802
803static void
804bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
805 struct ktermios *old)
806{
807 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
808 unsigned long flags;
809 unsigned int baud, quot;
810 unsigned short val, ier, lcr = 0;
811
812 switch (termios->c_cflag & CSIZE) {
813 case CS8:
814 lcr = WLS(8);
815 break;
816 case CS7:
817 lcr = WLS(7);
818 break;
819 case CS6:
820 lcr = WLS(6);
821 break;
822 case CS5:
823 lcr = WLS(5);
824 break;
825 default:
826 printk(KERN_ERR "%s: word lengh not supported\n",
827 __func__);
828 }
829
830 /* Anomaly notes:
831 * 05000231 - STOP bit is always set to 1 whatever the user is set.
832 */
833 if (termios->c_cflag & CSTOPB) {
834 if (ANOMALY_05000231)
835 printk(KERN_WARNING "STOP bits other than 1 is not "
836 "supported in case of anomaly 05000231.\n");
837 else
838 lcr |= STB;
839 }
840 if (termios->c_cflag & PARENB)
841 lcr |= PEN;
842 if (!(termios->c_cflag & PARODD))
843 lcr |= EPS;
844 if (termios->c_cflag & CMSPAR)
845 lcr |= STP;
846
847 spin_lock_irqsave(&uart->port.lock, flags);
848
849 port->read_status_mask = OE;
850 if (termios->c_iflag & INPCK)
851 port->read_status_mask |= (FE | PE);
852 if (termios->c_iflag & (BRKINT | PARMRK))
853 port->read_status_mask |= BI;
854
855 /*
856 * Characters to ignore
857 */
858 port->ignore_status_mask = 0;
859 if (termios->c_iflag & IGNPAR)
860 port->ignore_status_mask |= FE | PE;
861 if (termios->c_iflag & IGNBRK) {
862 port->ignore_status_mask |= BI;
863 /*
864 * If we're ignoring parity and break indicators,
865 * ignore overruns too (for real raw support).
866 */
867 if (termios->c_iflag & IGNPAR)
868 port->ignore_status_mask |= OE;
869 }
870
871 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
872 quot = uart_get_divisor(port, baud);
873
874 /* If discipline is not IRDA, apply ANOMALY_05000230 */
875 if (termios->c_line != N_IRDA)
876 quot -= ANOMALY_05000230;
877
878 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
879
880 /* Disable UART */
881 ier = UART_GET_IER(uart);
882 UART_DISABLE_INTS(uart);
883
884 /* Set DLAB in LCR to Access DLL and DLH */
885 UART_SET_DLAB(uart);
886
887 UART_PUT_DLL(uart, quot & 0xFF);
888 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
889 SSYNC();
890
891 /* Clear DLAB in LCR to Access THR RBR IER */
892 UART_CLEAR_DLAB(uart);
893
894 UART_PUT_LCR(uart, lcr);
895
896 /* Enable UART */
897 UART_ENABLE_INTS(uart, ier);
898
899 val = UART_GET_GCTL(uart);
900 val |= UCEN;
901 UART_PUT_GCTL(uart, val);
902
903 /* Port speed changed, update the per-port timeout. */
904 uart_update_timeout(port, termios->c_cflag, baud);
905
906 spin_unlock_irqrestore(&uart->port.lock, flags);
907}
908
909static const char *bfin_serial_type(struct uart_port *port)
910{
911 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
912
913 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
914}
915
916/*
917 * Release the memory region(s) being used by 'port'.
918 */
919static void bfin_serial_release_port(struct uart_port *port)
920{
921}
922
923/*
924 * Request the memory region(s) being used by 'port'.
925 */
926static int bfin_serial_request_port(struct uart_port *port)
927{
928 return 0;
929}
930
931/*
932 * Configure/autoconfigure the port.
933 */
934static void bfin_serial_config_port(struct uart_port *port, int flags)
935{
936 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
937
938 if (flags & UART_CONFIG_TYPE &&
939 bfin_serial_request_port(&uart->port) == 0)
940 uart->port.type = PORT_BFIN;
941}
942
943/*
944 * Verify the new serial_struct (for TIOCSSERIAL).
945 * The only change we allow are to the flags and type, and
946 * even then only between PORT_BFIN and PORT_UNKNOWN
947 */
948static int
949bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
950{
951 return 0;
952}
953
954/*
955 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
956 * In other cases, disable IrDA function.
957 */
958static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
959{
960 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
961 unsigned short val;
962
963 switch (ld) {
964 case N_IRDA:
965 val = UART_GET_GCTL(uart);
966 val |= (IREN | RPOLC);
967 UART_PUT_GCTL(uart, val);
968 break;
969 default:
970 val = UART_GET_GCTL(uart);
971 val &= ~(IREN | RPOLC);
972 UART_PUT_GCTL(uart, val);
973 }
974}
975
976static void bfin_serial_reset_irda(struct uart_port *port)
977{
978 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
979 unsigned short val;
980
981 val = UART_GET_GCTL(uart);
982 val &= ~(IREN | RPOLC);
983 UART_PUT_GCTL(uart, val);
984 SSYNC();
985 val |= (IREN | RPOLC);
986 UART_PUT_GCTL(uart, val);
987 SSYNC();
988}
989
990#ifdef CONFIG_CONSOLE_POLL
991/* Anomaly notes:
992 * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
993 * losing other bits of UART_LSR is not a problem here.
994 */
995static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
996{
997 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
998
999 while (!(UART_GET_LSR(uart) & THRE))
1000 cpu_relax();
1001
1002 UART_CLEAR_DLAB(uart);
1003 UART_PUT_CHAR(uart, (unsigned char)chr);
1004}
1005
1006static int bfin_serial_poll_get_char(struct uart_port *port)
1007{
1008 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1009 unsigned char chr;
1010
1011 while (!(UART_GET_LSR(uart) & DR))
1012 cpu_relax();
1013
1014 UART_CLEAR_DLAB(uart);
1015 chr = UART_GET_CHAR(uart);
1016
1017 return chr;
1018}
1019#endif
1020
1021#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1022 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1023static void bfin_kgdboc_port_shutdown(struct uart_port *port)
1024{
1025 if (kgdboc_break_enabled) {
1026 kgdboc_break_enabled = 0;
1027 bfin_serial_shutdown(port);
1028 }
1029}
1030
1031static int bfin_kgdboc_port_startup(struct uart_port *port)
1032{
1033 kgdboc_port_line = port->line;
1034 kgdboc_break_enabled = !bfin_serial_startup(port);
1035 return 0;
1036}
1037#endif
1038
1039static struct uart_ops bfin_serial_pops = {
1040 .tx_empty = bfin_serial_tx_empty,
1041 .set_mctrl = bfin_serial_set_mctrl,
1042 .get_mctrl = bfin_serial_get_mctrl,
1043 .stop_tx = bfin_serial_stop_tx,
1044 .start_tx = bfin_serial_start_tx,
1045 .stop_rx = bfin_serial_stop_rx,
1046 .enable_ms = bfin_serial_enable_ms,
1047 .break_ctl = bfin_serial_break_ctl,
1048 .startup = bfin_serial_startup,
1049 .shutdown = bfin_serial_shutdown,
1050 .set_termios = bfin_serial_set_termios,
1051 .set_ldisc = bfin_serial_set_ldisc,
1052 .type = bfin_serial_type,
1053 .release_port = bfin_serial_release_port,
1054 .request_port = bfin_serial_request_port,
1055 .config_port = bfin_serial_config_port,
1056 .verify_port = bfin_serial_verify_port,
1057#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1058 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1059 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1060 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1061#endif
1062#ifdef CONFIG_CONSOLE_POLL
1063 .poll_put_char = bfin_serial_poll_put_char,
1064 .poll_get_char = bfin_serial_poll_get_char,
1065#endif
1066};
1067
1068#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1069/*
1070 * If the port was already initialised (eg, by a boot loader),
1071 * try to determine the current setup.
1072 */
1073static void __init
1074bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1075 int *parity, int *bits)
1076{
1077 unsigned short status;
1078
1079 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1080 if (status == (ERBFI | ETBEI)) {
1081 /* ok, the port was enabled */
1082 u16 lcr, dlh, dll;
1083
1084 lcr = UART_GET_LCR(uart);
1085
1086 *parity = 'n';
1087 if (lcr & PEN) {
1088 if (lcr & EPS)
1089 *parity = 'e';
1090 else
1091 *parity = 'o';
1092 }
1093 switch (lcr & 0x03) {
1094 case 0: *bits = 5; break;
1095 case 1: *bits = 6; break;
1096 case 2: *bits = 7; break;
1097 case 3: *bits = 8; break;
1098 }
1099 /* Set DLAB in LCR to Access DLL and DLH */
1100 UART_SET_DLAB(uart);
1101
1102 dll = UART_GET_DLL(uart);
1103 dlh = UART_GET_DLH(uart);
1104
1105 /* Clear DLAB in LCR to Access THR RBR IER */
1106 UART_CLEAR_DLAB(uart);
1107
1108 *baud = get_sclk() / (16*(dll | dlh << 8));
1109 }
1110 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1111}
1112
1113static struct uart_driver bfin_serial_reg;
1114
1115static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1116{
1117 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1118 while (!(UART_GET_LSR(uart) & THRE))
1119 barrier();
1120 UART_PUT_CHAR(uart, ch);
1121}
1122
1123#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1124 defined (CONFIG_EARLY_PRINTK) */
1125
1126#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1127#define CLASS_BFIN_CONSOLE "bfin-console"
1128/*
1129 * Interrupts are disabled on entering
1130 */
1131static void
1132bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1133{
1134 struct bfin_serial_port *uart = bfin_serial_ports[co->index];
1135 unsigned long flags;
1136
1137 spin_lock_irqsave(&uart->port.lock, flags);
1138 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1139 spin_unlock_irqrestore(&uart->port.lock, flags);
1140
1141}
1142
1143static int __init
1144bfin_serial_console_setup(struct console *co, char *options)
1145{
1146 struct bfin_serial_port *uart;
1147 int baud = 57600;
1148 int bits = 8;
1149 int parity = 'n';
1150# if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1151 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1152 int flow = 'r';
1153# else
1154 int flow = 'n';
1155# endif
1156
1157 /*
1158 * Check whether an invalid uart number has been specified, and
1159 * if so, search for the first available port that does have
1160 * console support.
1161 */
1162 if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS)
1163 return -ENODEV;
1164
1165 uart = bfin_serial_ports[co->index];
1166 if (!uart)
1167 return -ENODEV;
1168
1169 if (options)
1170 uart_parse_options(options, &baud, &parity, &bits, &flow);
1171 else
1172 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1173
1174 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
1175}
1176
1177static struct console bfin_serial_console = {
1178 .name = BFIN_SERIAL_DEV_NAME,
1179 .write = bfin_serial_console_write,
1180 .device = uart_console_device,
1181 .setup = bfin_serial_console_setup,
1182 .flags = CON_PRINTBUFFER,
1183 .index = -1,
1184 .data = &bfin_serial_reg,
1185};
1186#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1187#else
1188#define BFIN_SERIAL_CONSOLE NULL
1189#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1190
1191#ifdef CONFIG_EARLY_PRINTK
1192static struct bfin_serial_port bfin_earlyprintk_port;
1193#define CLASS_BFIN_EARLYPRINTK "bfin-earlyprintk"
1194
1195/*
1196 * Interrupts are disabled on entering
1197 */
1198static void
1199bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count)
1200{
1201 unsigned long flags;
1202
1203 if (bfin_earlyprintk_port.port.line != co->index)
1204 return;
1205
1206 spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags);
1207 uart_console_write(&bfin_earlyprintk_port.port, s, count,
1208 bfin_serial_console_putchar);
1209 spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags);
1210}
1211
1212/*
1213 * This should have a .setup or .early_setup in it, but then things get called
1214 * without the command line options, and the baud rate gets messed up - so
1215 * don't let the common infrastructure play with things. (see calls to setup
1216 * & earlysetup in ./kernel/printk.c:register_console()
1217 */
1218static struct __initdata console bfin_early_serial_console = {
1219 .name = "early_BFuart",
1220 .write = bfin_earlyprintk_console_write,
1221 .device = uart_console_device,
1222 .flags = CON_PRINTBUFFER,
1223 .index = -1,
1224 .data = &bfin_serial_reg,
1225};
1226#endif
1227
1228static struct uart_driver bfin_serial_reg = {
1229 .owner = THIS_MODULE,
1230 .driver_name = DRIVER_NAME,
1231 .dev_name = BFIN_SERIAL_DEV_NAME,
1232 .major = BFIN_SERIAL_MAJOR,
1233 .minor = BFIN_SERIAL_MINOR,
1234 .nr = BFIN_UART_NR_PORTS,
1235 .cons = BFIN_SERIAL_CONSOLE,
1236};
1237
1238static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state)
1239{
1240 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1241
1242 return uart_suspend_port(&bfin_serial_reg, &uart->port);
1243}
1244
1245static int bfin_serial_resume(struct platform_device *pdev)
1246{
1247 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1248
1249 return uart_resume_port(&bfin_serial_reg, &uart->port);
1250}
1251
1252static int bfin_serial_probe(struct platform_device *pdev)
1253{
1254 struct resource *res;
1255 struct bfin_serial_port *uart = NULL;
1256 int ret = 0;
1257
1258 if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
1259 dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n");
1260 return -ENOENT;
1261 }
1262
1263 if (bfin_serial_ports[pdev->id] == NULL) {
1264
1265 uart = kzalloc(sizeof(*uart), GFP_KERNEL);
1266 if (!uart) {
1267 dev_err(&pdev->dev,
1268 "fail to malloc bfin_serial_port\n");
1269 return -ENOMEM;
1270 }
1271 bfin_serial_ports[pdev->id] = uart;
1272
1273#ifdef CONFIG_EARLY_PRINTK
1274 if (!(bfin_earlyprintk_port.port.membase
1275 && bfin_earlyprintk_port.port.line == pdev->id)) {
1276 /*
1277 * If the peripheral PINs of current port is allocated
1278 * in earlyprintk probe stage, don't do it again.
1279 */
1280#endif
1281 ret = peripheral_request_list(
1282 (unsigned short *)pdev->dev.platform_data, DRIVER_NAME);
1283 if (ret) {
1284 dev_err(&pdev->dev,
1285 "fail to request bfin serial peripherals\n");
1286 goto out_error_free_mem;
1287 }
1288#ifdef CONFIG_EARLY_PRINTK
1289 }
1290#endif
1291
1292 spin_lock_init(&uart->port.lock);
1293 uart->port.uartclk = get_sclk();
1294 uart->port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1295 uart->port.ops = &bfin_serial_pops;
1296 uart->port.line = pdev->id;
1297 uart->port.iotype = UPIO_MEM;
1298 uart->port.flags = UPF_BOOT_AUTOCONF;
1299
1300 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1301 if (res == NULL) {
1302 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
1303 ret = -ENOENT;
1304 goto out_error_free_peripherals;
1305 }
1306
1307 uart->port.membase = ioremap(res->start, resource_size(res));
1308 if (!uart->port.membase) {
1309 dev_err(&pdev->dev, "Cannot map uart IO\n");
1310 ret = -ENXIO;
1311 goto out_error_free_peripherals;
1312 }
1313 uart->port.mapbase = res->start;
1314
1315 uart->port.irq = platform_get_irq(pdev, 0);
1316 if (uart->port.irq < 0) {
1317 dev_err(&pdev->dev, "No uart RX/TX IRQ specified\n");
1318 ret = -ENOENT;
1319 goto out_error_unmap;
1320 }
1321
1322 uart->status_irq = platform_get_irq(pdev, 1);
1323 if (uart->status_irq < 0) {
1324 dev_err(&pdev->dev, "No uart status IRQ specified\n");
1325 ret = -ENOENT;
1326 goto out_error_unmap;
1327 }
1328
1329#ifdef CONFIG_SERIAL_BFIN_DMA
1330 spin_lock_init(&uart->rx_lock);
1331 uart->tx_done = 1;
1332 uart->tx_count = 0;
1333
1334 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1335 if (res == NULL) {
1336 dev_err(&pdev->dev, "No uart TX DMA channel specified\n");
1337 ret = -ENOENT;
1338 goto out_error_unmap;
1339 }
1340 uart->tx_dma_channel = res->start;
1341
1342 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1343 if (res == NULL) {
1344 dev_err(&pdev->dev, "No uart RX DMA channel specified\n");
1345 ret = -ENOENT;
1346 goto out_error_unmap;
1347 }
1348 uart->rx_dma_channel = res->start;
1349
1350 init_timer(&(uart->rx_dma_timer));
1351#endif
1352
1353#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1354 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1355 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1356 if (res == NULL)
1357 uart->cts_pin = -1;
1358 else
1359 uart->cts_pin = res->start;
1360
1361 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
1362 if (res == NULL)
1363 uart->rts_pin = -1;
1364 else
1365 uart->rts_pin = res->start;
1366# if defined(CONFIG_SERIAL_BFIN_CTSRTS)
1367 if (uart->rts_pin >= 0)
1368 gpio_request(uart->rts_pin, DRIVER_NAME);
1369# endif
1370#endif
1371 }
1372
1373#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1374 if (!is_early_platform_device(pdev)) {
1375#endif
1376 uart = bfin_serial_ports[pdev->id];
1377 uart->port.dev = &pdev->dev;
1378 dev_set_drvdata(&pdev->dev, uart);
1379 ret = uart_add_one_port(&bfin_serial_reg, &uart->port);
1380#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1381 }
1382#endif
1383
1384 if (!ret)
1385 return 0;
1386
1387 if (uart) {
1388out_error_unmap:
1389 iounmap(uart->port.membase);
1390out_error_free_peripherals:
1391 peripheral_free_list(
1392 (unsigned short *)pdev->dev.platform_data);
1393out_error_free_mem:
1394 kfree(uart);
1395 bfin_serial_ports[pdev->id] = NULL;
1396 }
1397
1398 return ret;
1399}
1400
1401static int __devexit bfin_serial_remove(struct platform_device *pdev)
1402{
1403 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1404
1405 dev_set_drvdata(&pdev->dev, NULL);
1406
1407 if (uart) {
1408 uart_remove_one_port(&bfin_serial_reg, &uart->port);
1409#ifdef CONFIG_SERIAL_BFIN_CTSRTS
1410 if (uart->rts_pin >= 0)
1411 gpio_free(uart->rts_pin);
1412#endif
1413 iounmap(uart->port.membase);
1414 peripheral_free_list(
1415 (unsigned short *)pdev->dev.platform_data);
1416 kfree(uart);
1417 bfin_serial_ports[pdev->id] = NULL;
1418 }
1419
1420 return 0;
1421}
1422
1423static struct platform_driver bfin_serial_driver = {
1424 .probe = bfin_serial_probe,
1425 .remove = __devexit_p(bfin_serial_remove),
1426 .suspend = bfin_serial_suspend,
1427 .resume = bfin_serial_resume,
1428 .driver = {
1429 .name = DRIVER_NAME,
1430 .owner = THIS_MODULE,
1431 },
1432};
1433
1434#if defined(CONFIG_SERIAL_BFIN_CONSOLE)
1435static __initdata struct early_platform_driver early_bfin_serial_driver = {
1436 .class_str = CLASS_BFIN_CONSOLE,
1437 .pdrv = &bfin_serial_driver,
1438 .requested_id = EARLY_PLATFORM_ID_UNSET,
1439};
1440
1441static int __init bfin_serial_rs_console_init(void)
1442{
1443 early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME);
1444
1445 early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0);
1446
1447 register_console(&bfin_serial_console);
1448
1449 return 0;
1450}
1451console_initcall(bfin_serial_rs_console_init);
1452#endif
1453
1454#ifdef CONFIG_EARLY_PRINTK
1455/*
1456 * Memory can't be allocated dynamically during earlyprink init stage.
1457 * So, do individual probe for earlyprink with a static uart port variable.
1458 */
1459static int bfin_earlyprintk_probe(struct platform_device *pdev)
1460{
1461 struct resource *res;
1462 int ret;
1463
1464 if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
1465 dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n");
1466 return -ENOENT;
1467 }
1468
1469 ret = peripheral_request_list(
1470 (unsigned short *)pdev->dev.platform_data, DRIVER_NAME);
1471 if (ret) {
1472 dev_err(&pdev->dev,
1473 "fail to request bfin serial peripherals\n");
1474 return ret;
1475 }
1476
1477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1478 if (res == NULL) {
1479 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
1480 ret = -ENOENT;
1481 goto out_error_free_peripherals;
1482 }
1483
1484 bfin_earlyprintk_port.port.membase = ioremap(res->start,
1485 resource_size(res));
1486 if (!bfin_earlyprintk_port.port.membase) {
1487 dev_err(&pdev->dev, "Cannot map uart IO\n");
1488 ret = -ENXIO;
1489 goto out_error_free_peripherals;
1490 }
1491 bfin_earlyprintk_port.port.mapbase = res->start;
1492 bfin_earlyprintk_port.port.line = pdev->id;
1493 bfin_earlyprintk_port.port.uartclk = get_sclk();
1494 bfin_earlyprintk_port.port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1495 spin_lock_init(&bfin_earlyprintk_port.port.lock);
1496
1497 return 0;
1498
1499out_error_free_peripherals:
1500 peripheral_free_list(
1501 (unsigned short *)pdev->dev.platform_data);
1502
1503 return ret;
1504}
1505
1506static struct platform_driver bfin_earlyprintk_driver = {
1507 .probe = bfin_earlyprintk_probe,
1508 .driver = {
1509 .name = DRIVER_NAME,
1510 .owner = THIS_MODULE,
1511 },
1512};
1513
1514static __initdata struct early_platform_driver early_bfin_earlyprintk_driver = {
1515 .class_str = CLASS_BFIN_EARLYPRINTK,
1516 .pdrv = &bfin_earlyprintk_driver,
1517 .requested_id = EARLY_PLATFORM_ID_UNSET,
1518};
1519
1520struct console __init *bfin_earlyserial_init(unsigned int port,
1521 unsigned int cflag)
1522{
1523 struct ktermios t;
1524 char port_name[20];
1525
1526 if (port < 0 || port >= BFIN_UART_NR_PORTS)
1527 return NULL;
1528
1529 /*
1530 * Only probe resource of the given port in earlyprintk boot arg.
1531 * The expected port id should be indicated in port name string.
1532 */
1533 snprintf(port_name, 20, DRIVER_NAME ".%d", port);
1534 early_platform_driver_register(&early_bfin_earlyprintk_driver,
1535 port_name);
1536 early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0);
1537
1538 if (!bfin_earlyprintk_port.port.membase)
1539 return NULL;
1540
1541#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1542 /*
1543 * If we are using early serial, don't let the normal console rewind
1544 * log buffer, since that causes things to be printed multiple times
1545 */
1546 bfin_serial_console.flags &= ~CON_PRINTBUFFER;
1547#endif
1548
1549 bfin_early_serial_console.index = port;
1550 t.c_cflag = cflag;
1551 t.c_iflag = 0;
1552 t.c_oflag = 0;
1553 t.c_lflag = ICANON;
1554 t.c_line = port;
1555 bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t);
1556
1557 return &bfin_early_serial_console;
1558}
1559#endif /* CONFIG_EARLY_PRINTK */
1560
1561static int __init bfin_serial_init(void)
1562{
1563 int ret;
1564
1565 pr_info("Blackfin serial driver\n");
1566
1567 ret = uart_register_driver(&bfin_serial_reg);
1568 if (ret) {
1569 pr_err("failed to register %s:%d\n",
1570 bfin_serial_reg.driver_name, ret);
1571 }
1572
1573 ret = platform_driver_register(&bfin_serial_driver);
1574 if (ret) {
1575 pr_err("fail to register bfin uart\n");
1576 uart_unregister_driver(&bfin_serial_reg);
1577 }
1578
1579 return ret;
1580}
1581
1582static void __exit bfin_serial_exit(void)
1583{
1584 platform_driver_unregister(&bfin_serial_driver);
1585 uart_unregister_driver(&bfin_serial_reg);
1586}
1587
1588
1589module_init(bfin_serial_init);
1590module_exit(bfin_serial_exit);
1591
1592MODULE_AUTHOR("Sonic Zhang, Aubrey Li");
1593MODULE_DESCRIPTION("Blackfin generic serial port driver");
1594MODULE_LICENSE("GPL");
1595MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
1596MODULE_ALIAS("platform:bfin-uart");
diff --git a/drivers/tty/serial/max3107-aava.c b/drivers/tty/serial/max3107-aava.c
new file mode 100644
index 00000000000..d73aadd7a9a
--- /dev/null
+++ b/drivers/tty/serial/max3107-aava.c
@@ -0,0 +1,344 @@
1/*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/spi/spi.h>
35#include <linux/freezer.h>
36#include <linux/platform_device.h>
37#include <linux/gpio.h>
38#include <linux/sfi.h>
39#include <asm/mrst.h>
40#include "max3107.h"
41
42/* GPIO direction to input function */
43static int max3107_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
44{
45 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
46 u16 buf[1]; /* Buffer for SPI transfer */
47
48 if (offset >= MAX3107_GPIO_COUNT) {
49 dev_err(&s->spi->dev, "Invalid GPIO\n");
50 return -EINVAL;
51 }
52
53 /* Read current GPIO configuration register */
54 buf[0] = MAX3107_GPIOCFG_REG;
55 /* Perform SPI transfer */
56 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
57 dev_err(&s->spi->dev, "SPI transfer GPIO read failed\n");
58 return -EIO;
59 }
60 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
61
62 /* Set GPIO to input */
63 buf[0] &= ~(0x0001 << offset);
64
65 /* Write new GPIO configuration register value */
66 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
67 /* Perform SPI transfer */
68 if (max3107_rw(s, (u8 *)buf, NULL, 2)) {
69 dev_err(&s->spi->dev, "SPI transfer GPIO write failed\n");
70 return -EIO;
71 }
72 return 0;
73}
74
75/* GPIO direction to output function */
76static int max3107_gpio_direction_out(struct gpio_chip *chip, unsigned offset,
77 int value)
78{
79 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
80 u16 buf[2]; /* Buffer for SPI transfers */
81
82 if (offset >= MAX3107_GPIO_COUNT) {
83 dev_err(&s->spi->dev, "Invalid GPIO\n");
84 return -EINVAL;
85 }
86
87 /* Read current GPIO configuration and data registers */
88 buf[0] = MAX3107_GPIOCFG_REG;
89 buf[1] = MAX3107_GPIODATA_REG;
90 /* Perform SPI transfer */
91 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
92 dev_err(&s->spi->dev, "SPI transfer gpio failed\n");
93 return -EIO;
94 }
95 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
96 buf[1] &= MAX3107_SPI_RX_DATA_MASK;
97
98 /* Set GPIO to output */
99 buf[0] |= (0x0001 << offset);
100 /* Set value */
101 if (value)
102 buf[1] |= (0x0001 << offset);
103 else
104 buf[1] &= ~(0x0001 << offset);
105
106 /* Write new GPIO configuration and data register values */
107 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
108 buf[1] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
109 /* Perform SPI transfer */
110 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
111 dev_err(&s->spi->dev,
112 "SPI transfer for GPIO conf data w failed\n");
113 return -EIO;
114 }
115 return 0;
116}
117
118/* GPIO value query function */
119static int max3107_gpio_get(struct gpio_chip *chip, unsigned offset)
120{
121 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
122 u16 buf[1]; /* Buffer for SPI transfer */
123
124 if (offset >= MAX3107_GPIO_COUNT) {
125 dev_err(&s->spi->dev, "Invalid GPIO\n");
126 return -EINVAL;
127 }
128
129 /* Read current GPIO data register */
130 buf[0] = MAX3107_GPIODATA_REG;
131 /* Perform SPI transfer */
132 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
133 dev_err(&s->spi->dev, "SPI transfer GPIO data r failed\n");
134 return -EIO;
135 }
136 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
137
138 /* Return value */
139 return buf[0] & (0x0001 << offset);
140}
141
142/* GPIO value set function */
143static void max3107_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
144{
145 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
146 u16 buf[2]; /* Buffer for SPI transfers */
147
148 if (offset >= MAX3107_GPIO_COUNT) {
149 dev_err(&s->spi->dev, "Invalid GPIO\n");
150 return;
151 }
152
153 /* Read current GPIO configuration registers*/
154 buf[0] = MAX3107_GPIODATA_REG;
155 buf[1] = MAX3107_GPIOCFG_REG;
156 /* Perform SPI transfer */
157 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
158 dev_err(&s->spi->dev,
159 "SPI transfer for GPIO data and config read failed\n");
160 return;
161 }
162 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
163 buf[1] &= MAX3107_SPI_RX_DATA_MASK;
164
165 if (!(buf[1] & (0x0001 << offset))) {
166 /* Configured as input, can't set value */
167 dev_warn(&s->spi->dev,
168 "Trying to set value for input GPIO\n");
169 return;
170 }
171
172 /* Set value */
173 if (value)
174 buf[0] |= (0x0001 << offset);
175 else
176 buf[0] &= ~(0x0001 << offset);
177
178 /* Write new GPIO data register value */
179 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
180 /* Perform SPI transfer */
181 if (max3107_rw(s, (u8 *)buf, NULL, 2))
182 dev_err(&s->spi->dev, "SPI transfer GPIO data w failed\n");
183}
184
185/* GPIO chip data */
186static struct gpio_chip max3107_gpio_chip = {
187 .owner = THIS_MODULE,
188 .direction_input = max3107_gpio_direction_in,
189 .direction_output = max3107_gpio_direction_out,
190 .get = max3107_gpio_get,
191 .set = max3107_gpio_set,
192 .can_sleep = 1,
193 .base = MAX3107_GPIO_BASE,
194 .ngpio = MAX3107_GPIO_COUNT,
195};
196
197/**
198 * max3107_aava_reset - reset on AAVA systems
199 * @spi: The SPI device we are probing
200 *
201 * Reset the device ready for probing.
202 */
203
204static int max3107_aava_reset(struct spi_device *spi)
205{
206 /* Reset the chip */
207 if (gpio_request(MAX3107_RESET_GPIO, "max3107")) {
208 pr_err("Requesting RESET GPIO failed\n");
209 return -EIO;
210 }
211 if (gpio_direction_output(MAX3107_RESET_GPIO, 0)) {
212 pr_err("Setting RESET GPIO to 0 failed\n");
213 gpio_free(MAX3107_RESET_GPIO);
214 return -EIO;
215 }
216 msleep(MAX3107_RESET_DELAY);
217 if (gpio_direction_output(MAX3107_RESET_GPIO, 1)) {
218 pr_err("Setting RESET GPIO to 1 failed\n");
219 gpio_free(MAX3107_RESET_GPIO);
220 return -EIO;
221 }
222 gpio_free(MAX3107_RESET_GPIO);
223 msleep(MAX3107_WAKEUP_DELAY);
224 return 0;
225}
226
227static int max3107_aava_configure(struct max3107_port *s)
228{
229 int retval;
230
231 /* Initialize GPIO chip data */
232 s->chip = max3107_gpio_chip;
233 s->chip.label = s->spi->modalias;
234 s->chip.dev = &s->spi->dev;
235
236 /* Add GPIO chip */
237 retval = gpiochip_add(&s->chip);
238 if (retval) {
239 dev_err(&s->spi->dev, "Adding GPIO chip failed\n");
240 return retval;
241 }
242
243 /* Temporary fix for EV2 boot problems, set modem reset to 0 */
244 max3107_gpio_direction_out(&s->chip, 3, 0);
245 return 0;
246}
247
248#if 0
249/* This will get enabled once we have the board stuff merged for this
250 specific case */
251
252static const struct baud_table brg13_ext[] = {
253 { 300, MAX3107_BRG13_B300 },
254 { 600, MAX3107_BRG13_B600 },
255 { 1200, MAX3107_BRG13_B1200 },
256 { 2400, MAX3107_BRG13_B2400 },
257 { 4800, MAX3107_BRG13_B4800 },
258 { 9600, MAX3107_BRG13_B9600 },
259 { 19200, MAX3107_BRG13_B19200 },
260 { 57600, MAX3107_BRG13_B57600 },
261 { 115200, MAX3107_BRG13_B115200 },
262 { 230400, MAX3107_BRG13_B230400 },
263 { 460800, MAX3107_BRG13_B460800 },
264 { 921600, MAX3107_BRG13_B921600 },
265 { 0, 0 }
266};
267
268static void max3107_aava_init(struct max3107_port *s)
269{
270 /*override for AAVA SC specific*/
271 if (mrst_platform_id() == MRST_PLATFORM_AAVA_SC) {
272 if (get_koski_build_id() <= KOSKI_EV2)
273 if (s->ext_clk) {
274 s->brg_cfg = MAX3107_BRG13_B9600;
275 s->baud_tbl = (struct baud_table *)brg13_ext;
276 }
277 }
278}
279#endif
280
281static int __devexit max3107_aava_remove(struct spi_device *spi)
282{
283 struct max3107_port *s = dev_get_drvdata(&spi->dev);
284
285 /* Remove GPIO chip */
286 if (gpiochip_remove(&s->chip))
287 dev_warn(&spi->dev, "Removing GPIO chip failed\n");
288
289 /* Then do the default remove */
290 return max3107_remove(spi);
291}
292
293/* Platform data */
294static struct max3107_plat aava_plat_data = {
295 .loopback = 0,
296 .ext_clk = 1,
297/* .init = max3107_aava_init, */
298 .configure = max3107_aava_configure,
299 .hw_suspend = max3107_hw_susp,
300 .polled_mode = 0,
301 .poll_time = 0,
302};
303
304
305static int __devinit max3107_probe_aava(struct spi_device *spi)
306{
307 int err = max3107_aava_reset(spi);
308 if (err < 0)
309 return err;
310 return max3107_probe(spi, &aava_plat_data);
311}
312
313/* Spi driver data */
314static struct spi_driver max3107_driver = {
315 .driver = {
316 .name = "aava-max3107",
317 .bus = &spi_bus_type,
318 .owner = THIS_MODULE,
319 },
320 .probe = max3107_probe_aava,
321 .remove = __devexit_p(max3107_aava_remove),
322 .suspend = max3107_suspend,
323 .resume = max3107_resume,
324};
325
326/* Driver init function */
327static int __init max3107_init(void)
328{
329 return spi_register_driver(&max3107_driver);
330}
331
332/* Driver exit function */
333static void __exit max3107_exit(void)
334{
335 spi_unregister_driver(&max3107_driver);
336}
337
338module_init(max3107_init);
339module_exit(max3107_exit);
340
341MODULE_DESCRIPTION("MAX3107 driver");
342MODULE_AUTHOR("Aavamobile");
343MODULE_ALIAS("spi:aava-max3107");
344MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/max3107.c b/drivers/tty/serial/max3107.c
new file mode 100644
index 00000000000..a8164601c0e
--- /dev/null
+++ b/drivers/tty/serial/max3107.c
@@ -0,0 +1,1213 @@
1/*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/gpio.h>
35#include <linux/spi/spi.h>
36#include <linux/freezer.h>
37#include "max3107.h"
38
39static const struct baud_table brg26_ext[] = {
40 { 300, MAX3107_BRG26_B300 },
41 { 600, MAX3107_BRG26_B600 },
42 { 1200, MAX3107_BRG26_B1200 },
43 { 2400, MAX3107_BRG26_B2400 },
44 { 4800, MAX3107_BRG26_B4800 },
45 { 9600, MAX3107_BRG26_B9600 },
46 { 19200, MAX3107_BRG26_B19200 },
47 { 57600, MAX3107_BRG26_B57600 },
48 { 115200, MAX3107_BRG26_B115200 },
49 { 230400, MAX3107_BRG26_B230400 },
50 { 460800, MAX3107_BRG26_B460800 },
51 { 921600, MAX3107_BRG26_B921600 },
52 { 0, 0 }
53};
54
55static const struct baud_table brg13_int[] = {
56 { 300, MAX3107_BRG13_IB300 },
57 { 600, MAX3107_BRG13_IB600 },
58 { 1200, MAX3107_BRG13_IB1200 },
59 { 2400, MAX3107_BRG13_IB2400 },
60 { 4800, MAX3107_BRG13_IB4800 },
61 { 9600, MAX3107_BRG13_IB9600 },
62 { 19200, MAX3107_BRG13_IB19200 },
63 { 57600, MAX3107_BRG13_IB57600 },
64 { 115200, MAX3107_BRG13_IB115200 },
65 { 230400, MAX3107_BRG13_IB230400 },
66 { 460800, MAX3107_BRG13_IB460800 },
67 { 921600, MAX3107_BRG13_IB921600 },
68 { 0, 0 }
69};
70
71static u32 get_new_brg(int baud, struct max3107_port *s)
72{
73 int i;
74 const struct baud_table *baud_tbl = s->baud_tbl;
75
76 for (i = 0; i < 13; i++) {
77 if (baud == baud_tbl[i].baud)
78 return baud_tbl[i].new_brg;
79 }
80
81 return 0;
82}
83
84/* Perform SPI transfer for write/read of device register(s) */
85int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
86{
87 struct spi_message spi_msg;
88 struct spi_transfer spi_xfer;
89
90 /* Initialize SPI ,message */
91 spi_message_init(&spi_msg);
92
93 /* Initialize SPI transfer */
94 memset(&spi_xfer, 0, sizeof spi_xfer);
95 spi_xfer.len = len;
96 spi_xfer.tx_buf = tx;
97 spi_xfer.rx_buf = rx;
98 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
99
100 /* Add SPI transfer to SPI message */
101 spi_message_add_tail(&spi_xfer, &spi_msg);
102
103#ifdef DBG_TRACE_SPI_DATA
104 {
105 int i;
106 pr_info("tx len %d:\n", spi_xfer.len);
107 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
108 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
109 pr_info("\n");
110 }
111#endif
112
113 /* Perform synchronous SPI transfer */
114 if (spi_sync(s->spi, &spi_msg)) {
115 dev_err(&s->spi->dev, "spi_sync failure\n");
116 return -EIO;
117 }
118
119#ifdef DBG_TRACE_SPI_DATA
120 if (spi_xfer.rx_buf) {
121 int i;
122 pr_info("rx len %d:\n", spi_xfer.len);
123 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
124 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
125 pr_info("\n");
126 }
127#endif
128 return 0;
129}
130EXPORT_SYMBOL_GPL(max3107_rw);
131
132/* Puts received data to circular buffer */
133static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
134 int len)
135{
136 struct uart_port *port = &s->port;
137 struct tty_struct *tty;
138
139 if (!port->state)
140 return;
141
142 tty = port->state->port.tty;
143 if (!tty)
144 return;
145
146 /* Insert received data */
147 tty_insert_flip_string(tty, data, len);
148 /* Update RX counter */
149 port->icount.rx += len;
150}
151
152/* Handle data receiving */
153static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
154{
155 int i;
156 int j;
157 int len; /* SPI transfer buffer length */
158 u16 *buf;
159 u8 *valid_str;
160
161 if (!s->rx_enabled)
162 /* RX is disabled */
163 return;
164
165 if (rxlvl == 0) {
166 /* RX fifo is empty */
167 return;
168 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
169 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
170 /* Ensure sanity of RX level */
171 rxlvl = MAX3107_RX_FIFO_SIZE;
172 }
173 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
174 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
175 return;
176 }
177 buf = s->rxbuf;
178 valid_str = s->rxstr;
179 while (rxlvl) {
180 pr_debug("rxlvl %d\n", rxlvl);
181 /* Clear buffer */
182 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
183 len = 0;
184 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
185 /* First disable RX FIFO interrupt */
186 pr_debug("Disabling RX INT\n");
187 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
188 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
189 buf[0] |= s->irqen_reg;
190 len++;
191 }
192 /* Just increase the length by amount of words in FIFO since
193 * buffer was zeroed and SPI transfer of 0x0000 means reading
194 * from RX FIFO
195 */
196 len += rxlvl;
197 /* Append RX level query */
198 buf[len] = MAX3107_RXFIFOLVL_REG;
199 len++;
200
201 /* Perform the SPI transfer */
202 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
203 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
204 return;
205 }
206
207 /* Skip RX FIFO interrupt disabling word if it was added */
208 j = ((len - 1) - rxlvl);
209 /* Read received words */
210 for (i = 0; i < rxlvl; i++, j++)
211 valid_str[i] = (u8)buf[j];
212 put_data_to_circ_buf(s, valid_str, rxlvl);
213 /* Get new RX level */
214 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
215 }
216
217 if (s->rx_enabled) {
218 /* RX still enabled, re-enable RX FIFO interrupt */
219 pr_debug("Enabling RX INT\n");
220 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
221 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
222 buf[0] |= s->irqen_reg;
223 if (max3107_rw(s, (u8 *)buf, NULL, 2))
224 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
225 }
226
227 /* Push the received data to receivers */
228 if (s->port.state->port.tty)
229 tty_flip_buffer_push(s->port.state->port.tty);
230}
231
232
233/* Handle data sending */
234static void max3107_handletx(struct max3107_port *s)
235{
236 struct circ_buf *xmit = &s->port.state->xmit;
237 int i;
238 unsigned long flags;
239 int len; /* SPI transfer buffer length */
240 u16 *buf;
241
242 if (!s->tx_fifo_empty)
243 /* Don't send more data before previous data is sent */
244 return;
245
246 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
247 /* No data to send or TX is stopped */
248 return;
249
250 if (!s->txbuf) {
251 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
252 return;
253 }
254 buf = s->txbuf;
255 /* Get length of data pending in circular buffer */
256 len = uart_circ_chars_pending(xmit);
257 if (len) {
258 /* Limit to size of TX FIFO */
259 if (len > MAX3107_TX_FIFO_SIZE)
260 len = MAX3107_TX_FIFO_SIZE;
261
262 pr_debug("txlen %d\n", len);
263
264 /* Update TX counter */
265 s->port.icount.tx += len;
266
267 /* TX FIFO will no longer be empty */
268 s->tx_fifo_empty = 0;
269
270 i = 0;
271 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
272 /* First disable TX empty interrupt */
273 pr_debug("Disabling TE INT\n");
274 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
275 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
276 buf[i] |= s->irqen_reg;
277 i++;
278 len++;
279 }
280 /* Add data to send */
281 spin_lock_irqsave(&s->port.lock, flags);
282 for ( ; i < len ; i++) {
283 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
284 buf[i] |= ((u16)xmit->buf[xmit->tail] &
285 MAX3107_SPI_TX_DATA_MASK);
286 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
287 }
288 spin_unlock_irqrestore(&s->port.lock, flags);
289 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
290 /* Enable TX empty interrupt */
291 pr_debug("Enabling TE INT\n");
292 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
293 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
294 buf[i] |= s->irqen_reg;
295 i++;
296 len++;
297 }
298 if (!s->tx_enabled) {
299 /* Enable TX */
300 pr_debug("Enable TX\n");
301 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
302 spin_lock_irqsave(&s->data_lock, flags);
303 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
304 buf[i] |= s->mode1_reg;
305 spin_unlock_irqrestore(&s->data_lock, flags);
306 s->tx_enabled = 1;
307 i++;
308 len++;
309 }
310
311 /* Perform the SPI transfer */
312 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
313 dev_err(&s->spi->dev,
314 "SPI transfer TX handling failed\n");
315 return;
316 }
317 }
318
319 /* Indicate wake up if circular buffer is getting low on data */
320 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
321 uart_write_wakeup(&s->port);
322
323}
324
325/* Handle interrupts
326 * Also reads and returns current RX FIFO level
327 */
328static u16 handle_interrupt(struct max3107_port *s)
329{
330 u16 buf[4]; /* Buffer for SPI transfers */
331 u8 irq_status;
332 u16 rx_level;
333 unsigned long flags;
334
335 /* Read IRQ status register */
336 buf[0] = MAX3107_IRQSTS_REG;
337 /* Read status IRQ status register */
338 buf[1] = MAX3107_STS_IRQSTS_REG;
339 /* Read LSR IRQ status register */
340 buf[2] = MAX3107_LSR_IRQSTS_REG;
341 /* Query RX level */
342 buf[3] = MAX3107_RXFIFOLVL_REG;
343
344 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
345 dev_err(&s->spi->dev,
346 "SPI transfer for INTR handling failed\n");
347 return 0;
348 }
349
350 irq_status = (u8)buf[0];
351 pr_debug("IRQSTS %x\n", irq_status);
352 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
353
354 if (irq_status & MAX3107_IRQ_LSR_BIT) {
355 /* LSR interrupt */
356 if (buf[2] & MAX3107_LSR_RXTO_BIT)
357 /* RX timeout interrupt,
358 * handled by normal RX handling
359 */
360 pr_debug("RX TO INT\n");
361 }
362
363 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
364 /* Tx empty interrupt,
365 * disable TX and set tx_fifo_empty flag
366 */
367 pr_debug("TE INT, disabling TX\n");
368 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
369 spin_lock_irqsave(&s->data_lock, flags);
370 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
371 buf[0] |= s->mode1_reg;
372 spin_unlock_irqrestore(&s->data_lock, flags);
373 if (max3107_rw(s, (u8 *)buf, NULL, 2))
374 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
375 s->tx_enabled = 0;
376 s->tx_fifo_empty = 1;
377 }
378
379 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
380 /* RX FIFO interrupt,
381 * handled by normal RX handling
382 */
383 pr_debug("RFIFO INT\n");
384
385 /* Return RX level */
386 return rx_level;
387}
388
389/* Trigger work thread*/
390static void max3107_dowork(struct max3107_port *s)
391{
392 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
393 queue_work(s->workqueue, &s->work);
394 else
395 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
396}
397
398/* Work thread */
399static void max3107_work(struct work_struct *w)
400{
401 struct max3107_port *s = container_of(w, struct max3107_port, work);
402 u16 rxlvl = 0;
403 int len; /* SPI transfer buffer length */
404 u16 buf[5]; /* Buffer for SPI transfers */
405 unsigned long flags;
406
407 /* Start by reading current RX FIFO level */
408 buf[0] = MAX3107_RXFIFOLVL_REG;
409 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
410 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
411 rxlvl = 0;
412 } else {
413 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
414 }
415
416 do {
417 pr_debug("rxlvl %d\n", rxlvl);
418
419 /* Handle RX */
420 max3107_handlerx(s, rxlvl);
421 rxlvl = 0;
422
423 if (s->handle_irq) {
424 /* Handle pending interrupts
425 * We also get new RX FIFO level since new data may
426 * have been received while pushing received data to
427 * receivers
428 */
429 s->handle_irq = 0;
430 rxlvl = handle_interrupt(s);
431 }
432
433 /* Handle TX */
434 max3107_handletx(s);
435
436 /* Handle configuration changes */
437 len = 0;
438 spin_lock_irqsave(&s->data_lock, flags);
439 if (s->mode1_commit) {
440 pr_debug("mode1_commit\n");
441 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
442 buf[len++] |= s->mode1_reg;
443 s->mode1_commit = 0;
444 }
445 if (s->lcr_commit) {
446 pr_debug("lcr_commit\n");
447 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
448 buf[len++] |= s->lcr_reg;
449 s->lcr_commit = 0;
450 }
451 if (s->brg_commit) {
452 pr_debug("brg_commit\n");
453 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
454 buf[len++] |= ((s->brg_cfg >> 16) &
455 MAX3107_SPI_TX_DATA_MASK);
456 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
457 buf[len++] |= ((s->brg_cfg >> 8) &
458 MAX3107_SPI_TX_DATA_MASK);
459 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
460 buf[len++] |= ((s->brg_cfg) & 0xff);
461 s->brg_commit = 0;
462 }
463 spin_unlock_irqrestore(&s->data_lock, flags);
464
465 if (len > 0) {
466 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
467 dev_err(&s->spi->dev,
468 "SPI transfer config failed\n");
469 }
470
471 /* Reloop if interrupt handling indicated data in RX FIFO */
472 } while (rxlvl);
473
474}
475
476/* Set sleep mode */
477static void max3107_set_sleep(struct max3107_port *s, int mode)
478{
479 u16 buf[1]; /* Buffer for SPI transfer */
480 unsigned long flags;
481 pr_debug("enter, mode %d\n", mode);
482
483 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
484 spin_lock_irqsave(&s->data_lock, flags);
485 switch (mode) {
486 case MAX3107_DISABLE_FORCED_SLEEP:
487 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
488 break;
489 case MAX3107_ENABLE_FORCED_SLEEP:
490 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
491 break;
492 case MAX3107_DISABLE_AUTOSLEEP:
493 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
494 break;
495 case MAX3107_ENABLE_AUTOSLEEP:
496 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
497 break;
498 default:
499 spin_unlock_irqrestore(&s->data_lock, flags);
500 dev_warn(&s->spi->dev, "invalid sleep mode\n");
501 return;
502 }
503 buf[0] |= s->mode1_reg;
504 spin_unlock_irqrestore(&s->data_lock, flags);
505
506 if (max3107_rw(s, (u8 *)buf, NULL, 2))
507 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
508
509 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
510 mode == MAX3107_DISABLE_FORCED_SLEEP)
511 msleep(MAX3107_WAKEUP_DELAY);
512}
513
514/* Perform full register initialization */
515static void max3107_register_init(struct max3107_port *s)
516{
517 u16 buf[11]; /* Buffer for SPI transfers */
518
519 /* 1. Configure baud rate, 9600 as default */
520 s->baud = 9600;
521 /* the below is default*/
522 if (s->ext_clk) {
523 s->brg_cfg = MAX3107_BRG26_B9600;
524 s->baud_tbl = (struct baud_table *)brg26_ext;
525 } else {
526 s->brg_cfg = MAX3107_BRG13_IB9600;
527 s->baud_tbl = (struct baud_table *)brg13_int;
528 }
529
530 if (s->pdata->init)
531 s->pdata->init(s);
532
533 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
534 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
535 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
536 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
537 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
538 | ((s->brg_cfg) & 0xff);
539
540 /* 2. Configure LCR register, 8N1 mode by default */
541 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
542 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
543 | s->lcr_reg;
544
545 /* 3. Configure MODE 1 register */
546 s->mode1_reg = 0;
547 /* Enable IRQ pin */
548 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
549 /* Disable TX */
550 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
551 s->tx_enabled = 0;
552 /* RX is enabled */
553 s->rx_enabled = 1;
554 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
555 | s->mode1_reg;
556
557 /* 4. Configure MODE 2 register */
558 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
559 if (s->loopback) {
560 /* Enable loopback */
561 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
562 }
563 /* Reset FIFOs */
564 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
565 s->tx_fifo_empty = 1;
566
567 /* 5. Configure FIFO trigger level register */
568 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
569 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
570 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
571
572 /* 6. Configure flow control levels */
573 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
574 /* Flow control halt level 96, resume level 48 */
575 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
576
577 /* 7. Configure flow control */
578 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
579 /* Enable auto CTS and auto RTS flow control */
580 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
581
582 /* 8. Configure RX timeout register */
583 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
584 /* Timeout after 48 character intervals */
585 buf[9] |= 0x0030;
586
587 /* 9. Configure LSR interrupt enable register */
588 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
589 /* Enable RX timeout interrupt */
590 buf[10] |= MAX3107_LSR_RXTO_BIT;
591
592 /* Perform SPI transfer */
593 if (max3107_rw(s, (u8 *)buf, NULL, 22))
594 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
595
596 /* 10. Clear IRQ status register by reading it */
597 buf[0] = MAX3107_IRQSTS_REG;
598
599 /* 11. Configure interrupt enable register */
600 /* Enable LSR interrupt */
601 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
602 /* Enable RX FIFO interrupt */
603 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
604 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
605 | s->irqen_reg;
606
607 /* 12. Clear FIFO reset that was set in step 6 */
608 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
609 if (s->loopback) {
610 /* Keep loopback enabled */
611 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
612 }
613
614 /* Perform SPI transfer */
615 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
616 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
617
618}
619
620/* IRQ handler */
621static irqreturn_t max3107_irq(int irqno, void *dev_id)
622{
623 struct max3107_port *s = dev_id;
624
625 if (irqno != s->spi->irq) {
626 /* Unexpected IRQ */
627 return IRQ_NONE;
628 }
629
630 /* Indicate irq */
631 s->handle_irq = 1;
632
633 /* Trigger work thread */
634 max3107_dowork(s);
635
636 return IRQ_HANDLED;
637}
638
639/* HW suspension function
640 *
641 * Currently autosleep is used to decrease current consumption, alternative
642 * approach would be to set the chip to reset mode if UART is not being
643 * used but that would mess the GPIOs
644 *
645 */
646void max3107_hw_susp(struct max3107_port *s, int suspend)
647{
648 pr_debug("enter, suspend %d\n", suspend);
649
650 if (suspend) {
651 /* Suspend requested,
652 * enable autosleep to decrease current consumption
653 */
654 s->suspended = 1;
655 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
656 } else {
657 /* Resume requested,
658 * disable autosleep
659 */
660 s->suspended = 0;
661 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
662 }
663}
664EXPORT_SYMBOL_GPL(max3107_hw_susp);
665
666/* Modem status IRQ enabling */
667static void max3107_enable_ms(struct uart_port *port)
668{
669 /* Modem status not supported */
670}
671
672/* Data send function */
673static void max3107_start_tx(struct uart_port *port)
674{
675 struct max3107_port *s = container_of(port, struct max3107_port, port);
676
677 /* Trigger work thread for sending data */
678 max3107_dowork(s);
679}
680
681/* Function for checking that there is no pending transfers */
682static unsigned int max3107_tx_empty(struct uart_port *port)
683{
684 struct max3107_port *s = container_of(port, struct max3107_port, port);
685
686 pr_debug("returning %d\n",
687 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
688 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
689}
690
691/* Function for stopping RX */
692static void max3107_stop_rx(struct uart_port *port)
693{
694 struct max3107_port *s = container_of(port, struct max3107_port, port);
695 unsigned long flags;
696
697 /* Set RX disabled in MODE 1 register */
698 spin_lock_irqsave(&s->data_lock, flags);
699 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
700 s->mode1_commit = 1;
701 spin_unlock_irqrestore(&s->data_lock, flags);
702 /* Set RX disabled */
703 s->rx_enabled = 0;
704 /* Trigger work thread for doing the actual configuration change */
705 max3107_dowork(s);
706}
707
708/* Function for returning control pin states */
709static unsigned int max3107_get_mctrl(struct uart_port *port)
710{
711 /* DCD and DSR are not wired and CTS/RTS is handled automatically
712 * so just indicate DSR and CAR asserted
713 */
714 return TIOCM_DSR | TIOCM_CAR;
715}
716
717/* Function for setting control pin states */
718static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
719{
720 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
721 * so do nothing
722 */
723}
724
725/* Function for configuring UART parameters */
726static void max3107_set_termios(struct uart_port *port,
727 struct ktermios *termios,
728 struct ktermios *old)
729{
730 struct max3107_port *s = container_of(port, struct max3107_port, port);
731 struct tty_struct *tty;
732 int baud;
733 u16 new_lcr = 0;
734 u32 new_brg = 0;
735 unsigned long flags;
736
737 if (!port->state)
738 return;
739
740 tty = port->state->port.tty;
741 if (!tty)
742 return;
743
744 /* Get new LCR register values */
745 /* Word size */
746 if ((termios->c_cflag & CSIZE) == CS7)
747 new_lcr |= MAX3107_LCR_WORD_LEN_7;
748 else
749 new_lcr |= MAX3107_LCR_WORD_LEN_8;
750
751 /* Parity */
752 if (termios->c_cflag & PARENB) {
753 new_lcr |= MAX3107_LCR_PARITY_BIT;
754 if (!(termios->c_cflag & PARODD))
755 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
756 }
757
758 /* Stop bits */
759 if (termios->c_cflag & CSTOPB) {
760 /* 2 stop bits */
761 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
762 }
763
764 /* Mask termios capabilities we don't support */
765 termios->c_cflag &= ~CMSPAR;
766
767 /* Set status ignore mask */
768 s->port.ignore_status_mask = 0;
769 if (termios->c_iflag & IGNPAR)
770 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
771
772 /* Set low latency to immediately handle pushed data */
773 s->port.state->port.tty->low_latency = 1;
774
775 /* Get new baud rate generator configuration */
776 baud = tty_get_baud_rate(tty);
777
778 spin_lock_irqsave(&s->data_lock, flags);
779 new_brg = get_new_brg(baud, s);
780 /* if can't find the corrent config, use previous */
781 if (!new_brg) {
782 baud = s->baud;
783 new_brg = s->brg_cfg;
784 }
785 spin_unlock_irqrestore(&s->data_lock, flags);
786 tty_termios_encode_baud_rate(termios, baud, baud);
787 s->baud = baud;
788
789 /* Update timeout according to new baud rate */
790 uart_update_timeout(port, termios->c_cflag, baud);
791
792 spin_lock_irqsave(&s->data_lock, flags);
793 if (s->lcr_reg != new_lcr) {
794 s->lcr_reg = new_lcr;
795 s->lcr_commit = 1;
796 }
797 if (s->brg_cfg != new_brg) {
798 s->brg_cfg = new_brg;
799 s->brg_commit = 1;
800 }
801 spin_unlock_irqrestore(&s->data_lock, flags);
802
803 /* Trigger work thread for doing the actual configuration change */
804 max3107_dowork(s);
805}
806
807/* Port shutdown function */
808static void max3107_shutdown(struct uart_port *port)
809{
810 struct max3107_port *s = container_of(port, struct max3107_port, port);
811
812 if (s->suspended && s->pdata->hw_suspend)
813 s->pdata->hw_suspend(s, 0);
814
815 /* Free the interrupt */
816 free_irq(s->spi->irq, s);
817
818 if (s->workqueue) {
819 /* Flush and destroy work queue */
820 flush_workqueue(s->workqueue);
821 destroy_workqueue(s->workqueue);
822 s->workqueue = NULL;
823 }
824
825 /* Suspend HW */
826 if (s->pdata->hw_suspend)
827 s->pdata->hw_suspend(s, 1);
828}
829
830/* Port startup function */
831static int max3107_startup(struct uart_port *port)
832{
833 struct max3107_port *s = container_of(port, struct max3107_port, port);
834
835 /* Initialize work queue */
836 s->workqueue = create_freezable_workqueue("max3107");
837 if (!s->workqueue) {
838 dev_err(&s->spi->dev, "Workqueue creation failed\n");
839 return -EBUSY;
840 }
841 INIT_WORK(&s->work, max3107_work);
842
843 /* Setup IRQ */
844 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
845 "max3107", s)) {
846 dev_err(&s->spi->dev, "IRQ reguest failed\n");
847 destroy_workqueue(s->workqueue);
848 s->workqueue = NULL;
849 return -EBUSY;
850 }
851
852 /* Resume HW */
853 if (s->pdata->hw_suspend)
854 s->pdata->hw_suspend(s, 0);
855
856 /* Init registers */
857 max3107_register_init(s);
858
859 return 0;
860}
861
862/* Port type function */
863static const char *max3107_type(struct uart_port *port)
864{
865 struct max3107_port *s = container_of(port, struct max3107_port, port);
866 return s->spi->modalias;
867}
868
869/* Port release function */
870static void max3107_release_port(struct uart_port *port)
871{
872 /* Do nothing */
873}
874
875/* Port request function */
876static int max3107_request_port(struct uart_port *port)
877{
878 /* Do nothing */
879 return 0;
880}
881
882/* Port config function */
883static void max3107_config_port(struct uart_port *port, int flags)
884{
885 struct max3107_port *s = container_of(port, struct max3107_port, port);
886 s->port.type = PORT_MAX3107;
887}
888
889/* Port verify function */
890static int max3107_verify_port(struct uart_port *port,
891 struct serial_struct *ser)
892{
893 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
894 return 0;
895
896 return -EINVAL;
897}
898
899/* Port stop TX function */
900static void max3107_stop_tx(struct uart_port *port)
901{
902 /* Do nothing */
903}
904
905/* Port break control function */
906static void max3107_break_ctl(struct uart_port *port, int break_state)
907{
908 /* We don't support break control, do nothing */
909}
910
911
912/* Port functions */
913static struct uart_ops max3107_ops = {
914 .tx_empty = max3107_tx_empty,
915 .set_mctrl = max3107_set_mctrl,
916 .get_mctrl = max3107_get_mctrl,
917 .stop_tx = max3107_stop_tx,
918 .start_tx = max3107_start_tx,
919 .stop_rx = max3107_stop_rx,
920 .enable_ms = max3107_enable_ms,
921 .break_ctl = max3107_break_ctl,
922 .startup = max3107_startup,
923 .shutdown = max3107_shutdown,
924 .set_termios = max3107_set_termios,
925 .type = max3107_type,
926 .release_port = max3107_release_port,
927 .request_port = max3107_request_port,
928 .config_port = max3107_config_port,
929 .verify_port = max3107_verify_port,
930};
931
932/* UART driver data */
933static struct uart_driver max3107_uart_driver = {
934 .owner = THIS_MODULE,
935 .driver_name = "ttyMAX",
936 .dev_name = "ttyMAX",
937 .nr = 1,
938};
939
940static int driver_registered = 0;
941
942
943
944/* 'Generic' platform data */
945static struct max3107_plat generic_plat_data = {
946 .loopback = 0,
947 .ext_clk = 1,
948 .hw_suspend = max3107_hw_susp,
949 .polled_mode = 0,
950 .poll_time = 0,
951};
952
953
954/*******************************************************************/
955
956/**
957 * max3107_probe - SPI bus probe entry point
958 * @spi: the spi device
959 *
960 * SPI wants us to probe this device and if appropriate claim it.
961 * Perform any platform specific requirements and then initialise
962 * the device.
963 */
964
965int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
966{
967 struct max3107_port *s;
968 u16 buf[2]; /* Buffer for SPI transfers */
969 int retval;
970
971 pr_info("enter max3107 probe\n");
972
973 /* Allocate port structure */
974 s = kzalloc(sizeof(*s), GFP_KERNEL);
975 if (!s) {
976 pr_err("Allocating port structure failed\n");
977 return -ENOMEM;
978 }
979
980 s->pdata = pdata;
981
982 /* SPI Rx buffer
983 * +2 for RX FIFO interrupt
984 * disabling and RX level query
985 */
986 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
987 if (!s->rxbuf) {
988 pr_err("Allocating RX buffer failed\n");
989 retval = -ENOMEM;
990 goto err_free4;
991 }
992 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
993 if (!s->rxstr) {
994 pr_err("Allocating RX buffer failed\n");
995 retval = -ENOMEM;
996 goto err_free3;
997 }
998 /* SPI Tx buffer
999 * SPI transfer buffer
1000 * +3 for TX FIFO empty
1001 * interrupt disabling and
1002 * enabling and TX enabling
1003 */
1004 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1005 if (!s->txbuf) {
1006 pr_err("Allocating TX buffer failed\n");
1007 retval = -ENOMEM;
1008 goto err_free2;
1009 }
1010 /* Initialize shared data lock */
1011 spin_lock_init(&s->data_lock);
1012
1013 /* SPI intializations */
1014 dev_set_drvdata(&spi->dev, s);
1015 spi->mode = SPI_MODE_0;
1016 spi->dev.platform_data = pdata;
1017 spi->bits_per_word = 16;
1018 s->ext_clk = pdata->ext_clk;
1019 s->loopback = pdata->loopback;
1020 spi_setup(spi);
1021 s->spi = spi;
1022
1023 /* Check REV ID to ensure we are talking to what we expect */
1024 buf[0] = MAX3107_REVID_REG;
1025 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1026 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1027 retval = -EIO;
1028 goto err_free1;
1029 }
1030 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1031 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1032 dev_err(&s->spi->dev, "REVID %x does not match\n",
1033 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1034 retval = -ENODEV;
1035 goto err_free1;
1036 }
1037
1038 /* Disable all interrupts */
1039 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1040 buf[0] |= 0x0000;
1041
1042 /* Configure clock source */
1043 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1044 if (s->ext_clk) {
1045 /* External clock */
1046 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1047 }
1048
1049 /* PLL bypass ON */
1050 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1051
1052 /* Perform SPI transfer */
1053 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1054 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1055 retval = -EIO;
1056 goto err_free1;
1057 }
1058
1059 /* Register UART driver */
1060 if (!driver_registered) {
1061 retval = uart_register_driver(&max3107_uart_driver);
1062 if (retval) {
1063 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1064 goto err_free1;
1065 }
1066 driver_registered = 1;
1067 }
1068
1069 /* Initialize UART port data */
1070 s->port.fifosize = 128;
1071 s->port.ops = &max3107_ops;
1072 s->port.line = 0;
1073 s->port.dev = &spi->dev;
1074 s->port.uartclk = 9600;
1075 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1076 s->port.irq = s->spi->irq;
1077 s->port.type = PORT_MAX3107;
1078
1079 /* Add UART port */
1080 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1081 if (retval < 0) {
1082 dev_err(&s->spi->dev, "Adding UART port failed\n");
1083 goto err_free1;
1084 }
1085
1086 if (pdata->configure) {
1087 retval = pdata->configure(s);
1088 if (retval < 0)
1089 goto err_free1;
1090 }
1091
1092 /* Go to suspend mode */
1093 if (pdata->hw_suspend)
1094 pdata->hw_suspend(s, 1);
1095
1096 return 0;
1097
1098err_free1:
1099 kfree(s->txbuf);
1100err_free2:
1101 kfree(s->rxstr);
1102err_free3:
1103 kfree(s->rxbuf);
1104err_free4:
1105 kfree(s);
1106 return retval;
1107}
1108EXPORT_SYMBOL_GPL(max3107_probe);
1109
1110/* Driver remove function */
1111int max3107_remove(struct spi_device *spi)
1112{
1113 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1114
1115 pr_info("enter max3107 remove\n");
1116
1117 /* Remove port */
1118 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1119 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1120
1121
1122 /* Free TxRx buffer */
1123 kfree(s->rxbuf);
1124 kfree(s->rxstr);
1125 kfree(s->txbuf);
1126
1127 /* Free port structure */
1128 kfree(s);
1129
1130 return 0;
1131}
1132EXPORT_SYMBOL_GPL(max3107_remove);
1133
1134/* Driver suspend function */
1135int max3107_suspend(struct spi_device *spi, pm_message_t state)
1136{
1137#ifdef CONFIG_PM
1138 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1139
1140 pr_debug("enter suspend\n");
1141
1142 /* Suspend UART port */
1143 uart_suspend_port(&max3107_uart_driver, &s->port);
1144
1145 /* Go to suspend mode */
1146 if (s->pdata->hw_suspend)
1147 s->pdata->hw_suspend(s, 1);
1148#endif /* CONFIG_PM */
1149 return 0;
1150}
1151EXPORT_SYMBOL_GPL(max3107_suspend);
1152
1153/* Driver resume function */
1154int max3107_resume(struct spi_device *spi)
1155{
1156#ifdef CONFIG_PM
1157 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1158
1159 pr_debug("enter resume\n");
1160
1161 /* Resume from suspend */
1162 if (s->pdata->hw_suspend)
1163 s->pdata->hw_suspend(s, 0);
1164
1165 /* Resume UART port */
1166 uart_resume_port(&max3107_uart_driver, &s->port);
1167#endif /* CONFIG_PM */
1168 return 0;
1169}
1170EXPORT_SYMBOL_GPL(max3107_resume);
1171
1172static int max3107_probe_generic(struct spi_device *spi)
1173{
1174 return max3107_probe(spi, &generic_plat_data);
1175}
1176
1177/* Spi driver data */
1178static struct spi_driver max3107_driver = {
1179 .driver = {
1180 .name = "max3107",
1181 .bus = &spi_bus_type,
1182 .owner = THIS_MODULE,
1183 },
1184 .probe = max3107_probe_generic,
1185 .remove = __devexit_p(max3107_remove),
1186 .suspend = max3107_suspend,
1187 .resume = max3107_resume,
1188};
1189
1190/* Driver init function */
1191static int __init max3107_init(void)
1192{
1193 pr_info("enter max3107 init\n");
1194 return spi_register_driver(&max3107_driver);
1195}
1196
1197/* Driver exit function */
1198static void __exit max3107_exit(void)
1199{
1200 pr_info("enter max3107 exit\n");
1201 /* Unregister UART driver */
1202 if (driver_registered)
1203 uart_unregister_driver(&max3107_uart_driver);
1204 spi_unregister_driver(&max3107_driver);
1205}
1206
1207module_init(max3107_init);
1208module_exit(max3107_exit);
1209
1210MODULE_DESCRIPTION("MAX3107 driver");
1211MODULE_AUTHOR("Aavamobile");
1212MODULE_ALIAS("spi:max3107");
1213MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/max3107.h b/drivers/tty/serial/max3107.h
new file mode 100644
index 00000000000..8415fc723b9
--- /dev/null
+++ b/drivers/tty/serial/max3107.h
@@ -0,0 +1,441 @@
1/*
2 * max3107.h - spi uart protocol driver header for Maxim 3107
3 *
4 * Copyright (C) Aavamobile 2009
5 * Based on serial_max3100.h by Christian Pellegrin
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef _MAX3107_H
14#define _MAX3107_H
15
16/* Serial error status definitions */
17#define MAX3107_PARITY_ERROR 1
18#define MAX3107_FRAME_ERROR 2
19#define MAX3107_OVERRUN_ERROR 4
20#define MAX3107_ALL_ERRORS (MAX3107_PARITY_ERROR | \
21 MAX3107_FRAME_ERROR | \
22 MAX3107_OVERRUN_ERROR)
23
24/* GPIO definitions */
25#define MAX3107_GPIO_BASE 88
26#define MAX3107_GPIO_COUNT 4
27
28
29/* GPIO connected to chip's reset pin */
30#define MAX3107_RESET_GPIO 87
31
32
33/* Chip reset delay */
34#define MAX3107_RESET_DELAY 10
35
36/* Chip wakeup delay */
37#define MAX3107_WAKEUP_DELAY 50
38
39
40/* Sleep mode definitions */
41#define MAX3107_DISABLE_FORCED_SLEEP 0
42#define MAX3107_ENABLE_FORCED_SLEEP 1
43#define MAX3107_DISABLE_AUTOSLEEP 2
44#define MAX3107_ENABLE_AUTOSLEEP 3
45
46
47/* Definitions for register access with SPI transfers
48 *
49 * SPI transfer format:
50 *
51 * Master to slave bits xzzzzzzzyyyyyyyy
52 * Slave to master bits aaaaaaaabbbbbbbb
53 *
54 * where:
55 * x = 0 for reads, 1 for writes
56 * z = register address
57 * y = new register value if write, 0 if read
58 * a = unspecified
59 * b = register value if read, unspecified if write
60 */
61
62/* SPI speed */
63#define MAX3107_SPI_SPEED (3125000 * 2)
64
65/* Write bit */
66#define MAX3107_WRITE_BIT (1 << 15)
67
68/* SPI TX data mask */
69#define MAX3107_SPI_RX_DATA_MASK (0x00ff)
70
71/* SPI RX data mask */
72#define MAX3107_SPI_TX_DATA_MASK (0x00ff)
73
74/* Register access masks */
75#define MAX3107_RHR_REG (0x0000) /* RX FIFO */
76#define MAX3107_THR_REG (0x0000) /* TX FIFO */
77#define MAX3107_IRQEN_REG (0x0100) /* IRQ enable */
78#define MAX3107_IRQSTS_REG (0x0200) /* IRQ status */
79#define MAX3107_LSR_IRQEN_REG (0x0300) /* LSR IRQ enable */
80#define MAX3107_LSR_IRQSTS_REG (0x0400) /* LSR IRQ status */
81#define MAX3107_SPCHR_IRQEN_REG (0x0500) /* Special char IRQ enable */
82#define MAX3107_SPCHR_IRQSTS_REG (0x0600) /* Special char IRQ status */
83#define MAX3107_STS_IRQEN_REG (0x0700) /* Status IRQ enable */
84#define MAX3107_STS_IRQSTS_REG (0x0800) /* Status IRQ status */
85#define MAX3107_MODE1_REG (0x0900) /* MODE1 */
86#define MAX3107_MODE2_REG (0x0a00) /* MODE2 */
87#define MAX3107_LCR_REG (0x0b00) /* LCR */
88#define MAX3107_RXTO_REG (0x0c00) /* RX timeout */
89#define MAX3107_HDPIXDELAY_REG (0x0d00) /* Auto transceiver delays */
90#define MAX3107_IRDA_REG (0x0e00) /* IRDA settings */
91#define MAX3107_FLOWLVL_REG (0x0f00) /* Flow control levels */
92#define MAX3107_FIFOTRIGLVL_REG (0x1000) /* FIFO IRQ trigger levels */
93#define MAX3107_TXFIFOLVL_REG (0x1100) /* TX FIFO level */
94#define MAX3107_RXFIFOLVL_REG (0x1200) /* RX FIFO level */
95#define MAX3107_FLOWCTRL_REG (0x1300) /* Flow control */
96#define MAX3107_XON1_REG (0x1400) /* XON1 character */
97#define MAX3107_XON2_REG (0x1500) /* XON2 character */
98#define MAX3107_XOFF1_REG (0x1600) /* XOFF1 character */
99#define MAX3107_XOFF2_REG (0x1700) /* XOFF2 character */
100#define MAX3107_GPIOCFG_REG (0x1800) /* GPIO config */
101#define MAX3107_GPIODATA_REG (0x1900) /* GPIO data */
102#define MAX3107_PLLCFG_REG (0x1a00) /* PLL config */
103#define MAX3107_BRGCFG_REG (0x1b00) /* Baud rate generator conf */
104#define MAX3107_BRGDIVLSB_REG (0x1c00) /* Baud rate divisor LSB */
105#define MAX3107_BRGDIVMSB_REG (0x1d00) /* Baud rate divisor MSB */
106#define MAX3107_CLKSRC_REG (0x1e00) /* Clock source */
107#define MAX3107_REVID_REG (0x1f00) /* Revision identification */
108
109/* IRQ register bits */
110#define MAX3107_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
111#define MAX3107_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
112#define MAX3107_IRQ_STS_BIT (1 << 2) /* Status interrupt */
113#define MAX3107_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
114#define MAX3107_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
115#define MAX3107_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
116#define MAX3107_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
117#define MAX3107_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
118
119/* LSR register bits */
120#define MAX3107_LSR_RXTO_BIT (1 << 0) /* RX timeout */
121#define MAX3107_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
122#define MAX3107_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
123#define MAX3107_LSR_FRERR_BIT (1 << 3) /* Frame error */
124#define MAX3107_LSR_RXBRK_BIT (1 << 4) /* RX break */
125#define MAX3107_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
126#define MAX3107_LSR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
127#define MAX3107_LSR_CTS_BIT (1 << 7) /* CTS pin state */
128
129/* Special character register bits */
130#define MAX3107_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
131#define MAX3107_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
132#define MAX3107_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
133#define MAX3107_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
134#define MAX3107_SPCHR_BREAK_BIT (1 << 4) /* RX break */
135#define MAX3107_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
136#define MAX3107_SPCHR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
137#define MAX3107_SPCHR_UNDEF7_BIT (1 << 7) /* Undefined/not used */
138
139/* Status register bits */
140#define MAX3107_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
141#define MAX3107_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
142#define MAX3107_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
143#define MAX3107_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
144#define MAX3107_STS_UNDEF4_BIT (1 << 4) /* Undefined/not used */
145#define MAX3107_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
146#define MAX3107_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
147#define MAX3107_STS_UNDEF7_BIT (1 << 7) /* Undefined/not used */
148
149/* MODE1 register bits */
150#define MAX3107_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
151#define MAX3107_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
152#define MAX3107_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
153#define MAX3107_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
154#define MAX3107_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
155#define MAX3107_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
156#define MAX3107_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
157#define MAX3107_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
158
159/* MODE2 register bits */
160#define MAX3107_MODE2_RST_BIT (1 << 0) /* Chip reset */
161#define MAX3107_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
162#define MAX3107_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
163#define MAX3107_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
164#define MAX3107_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
165#define MAX3107_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
166#define MAX3107_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
167#define MAX3107_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
168
169/* LCR register bits */
170#define MAX3107_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
171#define MAX3107_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
172 *
173 * Word length bits table:
174 * 00 -> 5 bit words
175 * 01 -> 6 bit words
176 * 10 -> 7 bit words
177 * 11 -> 8 bit words
178 */
179#define MAX3107_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
180 *
181 * STOP length bit table:
182 * 0 -> 1 stop bit
183 * 1 -> 1-1.5 stop bits if
184 * word length is 5,
185 * 2 stop bits otherwise
186 */
187#define MAX3107_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
188#define MAX3107_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
189#define MAX3107_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
190#define MAX3107_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
191#define MAX3107_LCR_RTS_BIT (1 << 7) /* RTS pin control */
192#define MAX3107_LCR_WORD_LEN_5 (0x0000)
193#define MAX3107_LCR_WORD_LEN_6 (0x0001)
194#define MAX3107_LCR_WORD_LEN_7 (0x0002)
195#define MAX3107_LCR_WORD_LEN_8 (0x0003)
196
197
198/* IRDA register bits */
199#define MAX3107_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
200#define MAX3107_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
201#define MAX3107_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
202#define MAX3107_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
203#define MAX3107_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
204#define MAX3107_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
205#define MAX3107_IRDA_UNDEF6_BIT (1 << 6) /* Undefined/not used */
206#define MAX3107_IRDA_UNDEF7_BIT (1 << 7) /* Undefined/not used */
207
208/* Flow control trigger level register masks */
209#define MAX3107_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
210#define MAX3107_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
211#define MAX3107_FLOWLVL_HALT(words) ((words/8) & 0x000f)
212#define MAX3107_FLOWLVL_RES(words) (((words/8) & 0x000f) << 4)
213
214/* FIFO interrupt trigger level register masks */
215#define MAX3107_FIFOTRIGLVL_TX_MASK (0x000f) /* TX FIFO trigger level */
216#define MAX3107_FIFOTRIGLVL_RX_MASK (0x00f0) /* RX FIFO trigger level */
217#define MAX3107_FIFOTRIGLVL_TX(words) ((words/8) & 0x000f)
218#define MAX3107_FIFOTRIGLVL_RX(words) (((words/8) & 0x000f) << 4)
219
220/* Flow control register bits */
221#define MAX3107_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
222#define MAX3107_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
223#define MAX3107_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
224 * are used in conjunction with
225 * XOFF2 for definition of
226 * special character */
227#define MAX3107_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
228#define MAX3107_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
229#define MAX3107_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
230 *
231 * SWFLOW bits 1 & 0 table:
232 * 00 -> no transmitter flow
233 * control
234 * 01 -> receiver compares
235 * XON2 and XOFF2
236 * and controls
237 * transmitter
238 * 10 -> receiver compares
239 * XON1 and XOFF1
240 * and controls
241 * transmitter
242 * 11 -> receiver compares
243 * XON1, XON2, XOFF1 and
244 * XOFF2 and controls
245 * transmitter
246 */
247#define MAX3107_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
248#define MAX3107_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
249 *
250 * SWFLOW bits 3 & 2 table:
251 * 00 -> no received flow
252 * control
253 * 01 -> transmitter generates
254 * XON2 and XOFF2
255 * 10 -> transmitter generates
256 * XON1 and XOFF1
257 * 11 -> transmitter generates
258 * XON1, XON2, XOFF1 and
259 * XOFF2
260 */
261
262/* GPIO configuration register bits */
263#define MAX3107_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
264#define MAX3107_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
265#define MAX3107_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
266#define MAX3107_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
267#define MAX3107_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
268#define MAX3107_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
269#define MAX3107_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
270#define MAX3107_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
271
272/* GPIO DATA register bits */
273#define MAX3107_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
274#define MAX3107_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
275#define MAX3107_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
276#define MAX3107_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
277#define MAX3107_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
278#define MAX3107_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
279#define MAX3107_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
280#define MAX3107_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
281
282/* PLL configuration register masks */
283#define MAX3107_PLLCFG_PREDIV_MASK (0x003f) /* PLL predivision value */
284#define MAX3107_PLLCFG_PLLFACTOR_MASK (0x00c0) /* PLL multiplication factor */
285
286/* Baud rate generator configuration register masks and bits */
287#define MAX3107_BRGCFG_FRACT_MASK (0x000f) /* Fractional portion of
288 * Baud rate generator divisor
289 */
290#define MAX3107_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
291#define MAX3107_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
292#define MAX3107_BRGCFG_UNDEF6_BIT (1 << 6) /* Undefined/not used */
293#define MAX3107_BRGCFG_UNDEF7_BIT (1 << 7) /* Undefined/not used */
294
295/* Clock source register bits */
296#define MAX3107_CLKSRC_INTOSC_BIT (1 << 0) /* Internal osc enable */
297#define MAX3107_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
298#define MAX3107_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
299#define MAX3107_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
300#define MAX3107_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
301#define MAX3107_CLKSRC_UNDEF5_BIT (1 << 5) /* Undefined/not used */
302#define MAX3107_CLKSRC_UNDEF6_BIT (1 << 6) /* Undefined/not used */
303#define MAX3107_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
304
305
306/* HW definitions */
307#define MAX3107_RX_FIFO_SIZE 128
308#define MAX3107_TX_FIFO_SIZE 128
309#define MAX3107_REVID1 0x00a0
310#define MAX3107_REVID2 0x00a1
311
312
313/* Baud rate generator configuration values for external clock 13MHz */
314#define MAX3107_BRG13_B300 (0x0A9400 | 0x05)
315#define MAX3107_BRG13_B600 (0x054A00 | 0x03)
316#define MAX3107_BRG13_B1200 (0x02A500 | 0x01)
317#define MAX3107_BRG13_B2400 (0x015200 | 0x09)
318#define MAX3107_BRG13_B4800 (0x00A900 | 0x04)
319#define MAX3107_BRG13_B9600 (0x005400 | 0x0A)
320#define MAX3107_BRG13_B19200 (0x002A00 | 0x05)
321#define MAX3107_BRG13_B38400 (0x001500 | 0x03)
322#define MAX3107_BRG13_B57600 (0x000E00 | 0x02)
323#define MAX3107_BRG13_B115200 (0x000700 | 0x01)
324#define MAX3107_BRG13_B230400 (0x000300 | 0x08)
325#define MAX3107_BRG13_B460800 (0x000100 | 0x0c)
326#define MAX3107_BRG13_B921600 (0x000100 | 0x1c)
327
328/* Baud rate generator configuration values for external clock 26MHz */
329#define MAX3107_BRG26_B300 (0x152800 | 0x0A)
330#define MAX3107_BRG26_B600 (0x0A9400 | 0x05)
331#define MAX3107_BRG26_B1200 (0x054A00 | 0x03)
332#define MAX3107_BRG26_B2400 (0x02A500 | 0x01)
333#define MAX3107_BRG26_B4800 (0x015200 | 0x09)
334#define MAX3107_BRG26_B9600 (0x00A900 | 0x04)
335#define MAX3107_BRG26_B19200 (0x005400 | 0x0A)
336#define MAX3107_BRG26_B38400 (0x002A00 | 0x05)
337#define MAX3107_BRG26_B57600 (0x001C00 | 0x03)
338#define MAX3107_BRG26_B115200 (0x000E00 | 0x02)
339#define MAX3107_BRG26_B230400 (0x000700 | 0x01)
340#define MAX3107_BRG26_B460800 (0x000300 | 0x08)
341#define MAX3107_BRG26_B921600 (0x000100 | 0x0C)
342
343/* Baud rate generator configuration values for internal clock */
344#define MAX3107_BRG13_IB300 (0x008000 | 0x00)
345#define MAX3107_BRG13_IB600 (0x004000 | 0x00)
346#define MAX3107_BRG13_IB1200 (0x002000 | 0x00)
347#define MAX3107_BRG13_IB2400 (0x001000 | 0x00)
348#define MAX3107_BRG13_IB4800 (0x000800 | 0x00)
349#define MAX3107_BRG13_IB9600 (0x000400 | 0x00)
350#define MAX3107_BRG13_IB19200 (0x000200 | 0x00)
351#define MAX3107_BRG13_IB38400 (0x000100 | 0x00)
352#define MAX3107_BRG13_IB57600 (0x000000 | 0x0B)
353#define MAX3107_BRG13_IB115200 (0x000000 | 0x05)
354#define MAX3107_BRG13_IB230400 (0x000000 | 0x03)
355#define MAX3107_BRG13_IB460800 (0x000000 | 0x00)
356#define MAX3107_BRG13_IB921600 (0x000000 | 0x00)
357
358
359struct baud_table {
360 int baud;
361 u32 new_brg;
362};
363
364struct max3107_port {
365 /* UART port structure */
366 struct uart_port port;
367
368 /* SPI device structure */
369 struct spi_device *spi;
370
371#if defined(CONFIG_GPIOLIB)
372 /* GPIO chip structure */
373 struct gpio_chip chip;
374#endif
375
376 /* Workqueue that does all the magic */
377 struct workqueue_struct *workqueue;
378 struct work_struct work;
379
380 /* Lock for shared data */
381 spinlock_t data_lock;
382
383 /* Device configuration */
384 int ext_clk; /* 1 if external clock used */
385 int loopback; /* Current loopback mode state */
386 int baud; /* Current baud rate */
387
388 /* State flags */
389 int suspended; /* Indicates suspend mode */
390 int tx_fifo_empty; /* Flag for TX FIFO state */
391 int rx_enabled; /* Flag for receiver state */
392 int tx_enabled; /* Flag for transmitter state */
393
394 u16 irqen_reg; /* Current IRQ enable register value */
395 /* Shared data */
396 u16 mode1_reg; /* Current mode1 register value*/
397 int mode1_commit; /* Flag for setting new mode1 register value */
398 u16 lcr_reg; /* Current LCR register value */
399 int lcr_commit; /* Flag for setting new LCR register value */
400 u32 brg_cfg; /* Current Baud rate generator config */
401 int brg_commit; /* Flag for setting new baud rate generator
402 * config
403 */
404 struct baud_table *baud_tbl;
405 int handle_irq; /* Indicates that IRQ should be handled */
406
407 /* Rx buffer and str*/
408 u16 *rxbuf;
409 u8 *rxstr;
410 /* Tx buffer*/
411 u16 *txbuf;
412
413 struct max3107_plat *pdata; /* Platform data */
414};
415
416/* Platform data structure */
417struct max3107_plat {
418 /* Loopback mode enable */
419 int loopback;
420 /* External clock enable */
421 int ext_clk;
422 /* Called during the register initialisation */
423 void (*init)(struct max3107_port *s);
424 /* Called when the port is found and configured */
425 int (*configure)(struct max3107_port *s);
426 /* HW suspend function */
427 void (*hw_suspend) (struct max3107_port *s, int suspend);
428 /* Polling mode enable */
429 int polled_mode;
430 /* Polling period if polling mode enabled */
431 int poll_time;
432};
433
434extern int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len);
435extern void max3107_hw_susp(struct max3107_port *s, int suspend);
436extern int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata);
437extern int max3107_remove(struct spi_device *spi);
438extern int max3107_suspend(struct spi_device *spi, pm_message_t state);
439extern int max3107_resume(struct spi_device *spi);
440
441#endif /* _LINUX_SERIAL_MAX3107_H */
diff --git a/drivers/tty/serial/s3c2410.c b/drivers/tty/serial/s3c2410.c
new file mode 100644
index 00000000000..b1d7e7c1849
--- /dev/null
+++ b/drivers/tty/serial/s3c2410.c
@@ -0,0 +1,115 @@
1/*
2 * Driver for Samsung S3C2410 SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/module.h>
13#include <linux/ioport.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial_core.h>
18#include <linux/serial.h>
19
20#include <asm/irq.h>
21#include <mach/hardware.h>
22
23#include <plat/regs-serial.h>
24#include <mach/regs-gpio.h>
25
26#include "samsung.h"
27
28static int s3c2410_serial_setsource(struct uart_port *port,
29 struct s3c24xx_uart_clksrc *clk)
30{
31 unsigned long ucon = rd_regl(port, S3C2410_UCON);
32
33 if (strcmp(clk->name, "uclk") == 0)
34 ucon |= S3C2410_UCON_UCLK;
35 else
36 ucon &= ~S3C2410_UCON_UCLK;
37
38 wr_regl(port, S3C2410_UCON, ucon);
39 return 0;
40}
41
42static int s3c2410_serial_getsource(struct uart_port *port,
43 struct s3c24xx_uart_clksrc *clk)
44{
45 unsigned long ucon = rd_regl(port, S3C2410_UCON);
46
47 clk->divisor = 1;
48 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
49
50 return 0;
51}
52
53static int s3c2410_serial_resetport(struct uart_port *port,
54 struct s3c2410_uartcfg *cfg)
55{
56 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
57 port, port->mapbase, cfg);
58
59 wr_regl(port, S3C2410_UCON, cfg->ucon);
60 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
61
62 /* reset both fifos */
63
64 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
65 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
66
67 return 0;
68}
69
70static struct s3c24xx_uart_info s3c2410_uart_inf = {
71 .name = "Samsung S3C2410 UART",
72 .type = PORT_S3C2410,
73 .fifosize = 16,
74 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
75 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
76 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
77 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
78 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
79 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
80 .get_clksrc = s3c2410_serial_getsource,
81 .set_clksrc = s3c2410_serial_setsource,
82 .reset_port = s3c2410_serial_resetport,
83};
84
85static int s3c2410_serial_probe(struct platform_device *dev)
86{
87 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
88}
89
90static struct platform_driver s3c2410_serial_driver = {
91 .probe = s3c2410_serial_probe,
92 .remove = __devexit_p(s3c24xx_serial_remove),
93 .driver = {
94 .name = "s3c2410-uart",
95 .owner = THIS_MODULE,
96 },
97};
98
99static int __init s3c2410_serial_init(void)
100{
101 return s3c24xx_serial_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
102}
103
104static void __exit s3c2410_serial_exit(void)
105{
106 platform_driver_unregister(&s3c2410_serial_driver);
107}
108
109module_init(s3c2410_serial_init);
110module_exit(s3c2410_serial_exit);
111
112MODULE_LICENSE("GPL v2");
113MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
114MODULE_DESCRIPTION("Samsung S3C2410 SoC Serial port driver");
115MODULE_ALIAS("platform:s3c2410-uart");
diff --git a/drivers/tty/serial/s3c2412.c b/drivers/tty/serial/s3c2412.c
new file mode 100644
index 00000000000..2234bf9ced4
--- /dev/null
+++ b/drivers/tty/serial/s3c2412.c
@@ -0,0 +1,149 @@
1/*
2 * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/module.h>
13#include <linux/ioport.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial_core.h>
18#include <linux/serial.h>
19
20#include <asm/irq.h>
21#include <mach/hardware.h>
22
23#include <plat/regs-serial.h>
24#include <mach/regs-gpio.h>
25
26#include "samsung.h"
27
28static int s3c2412_serial_setsource(struct uart_port *port,
29 struct s3c24xx_uart_clksrc *clk)
30{
31 unsigned long ucon = rd_regl(port, S3C2410_UCON);
32
33 ucon &= ~S3C2412_UCON_CLKMASK;
34
35 if (strcmp(clk->name, "uclk") == 0)
36 ucon |= S3C2440_UCON_UCLK;
37 else if (strcmp(clk->name, "pclk") == 0)
38 ucon |= S3C2440_UCON_PCLK;
39 else if (strcmp(clk->name, "usysclk") == 0)
40 ucon |= S3C2412_UCON_USYSCLK;
41 else {
42 printk(KERN_ERR "unknown clock source %s\n", clk->name);
43 return -EINVAL;
44 }
45
46 wr_regl(port, S3C2410_UCON, ucon);
47 return 0;
48}
49
50
51static int s3c2412_serial_getsource(struct uart_port *port,
52 struct s3c24xx_uart_clksrc *clk)
53{
54 unsigned long ucon = rd_regl(port, S3C2410_UCON);
55
56 switch (ucon & S3C2412_UCON_CLKMASK) {
57 case S3C2412_UCON_UCLK:
58 clk->divisor = 1;
59 clk->name = "uclk";
60 break;
61
62 case S3C2412_UCON_PCLK:
63 case S3C2412_UCON_PCLK2:
64 clk->divisor = 1;
65 clk->name = "pclk";
66 break;
67
68 case S3C2412_UCON_USYSCLK:
69 clk->divisor = 1;
70 clk->name = "usysclk";
71 break;
72 }
73
74 return 0;
75}
76
77static int s3c2412_serial_resetport(struct uart_port *port,
78 struct s3c2410_uartcfg *cfg)
79{
80 unsigned long ucon = rd_regl(port, S3C2410_UCON);
81
82 dbg("%s: port=%p (%08lx), cfg=%p\n",
83 __func__, port, port->mapbase, cfg);
84
85 /* ensure we don't change the clock settings... */
86
87 ucon &= S3C2412_UCON_CLKMASK;
88
89 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
90 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
91
92 /* reset both fifos */
93
94 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
95 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
96
97 return 0;
98}
99
100static struct s3c24xx_uart_info s3c2412_uart_inf = {
101 .name = "Samsung S3C2412 UART",
102 .type = PORT_S3C2412,
103 .fifosize = 64,
104 .has_divslot = 1,
105 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
106 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
107 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
108 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
109 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
110 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
111 .get_clksrc = s3c2412_serial_getsource,
112 .set_clksrc = s3c2412_serial_setsource,
113 .reset_port = s3c2412_serial_resetport,
114};
115
116/* device management */
117
118static int s3c2412_serial_probe(struct platform_device *dev)
119{
120 dbg("s3c2440_serial_probe: dev=%p\n", dev);
121 return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
122}
123
124static struct platform_driver s3c2412_serial_driver = {
125 .probe = s3c2412_serial_probe,
126 .remove = __devexit_p(s3c24xx_serial_remove),
127 .driver = {
128 .name = "s3c2412-uart",
129 .owner = THIS_MODULE,
130 },
131};
132
133static inline int s3c2412_serial_init(void)
134{
135 return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
136}
137
138static inline void s3c2412_serial_exit(void)
139{
140 platform_driver_unregister(&s3c2412_serial_driver);
141}
142
143module_init(s3c2412_serial_init);
144module_exit(s3c2412_serial_exit);
145
146MODULE_DESCRIPTION("Samsung S3C2412,S3C2413 SoC Serial port driver");
147MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
148MODULE_LICENSE("GPL v2");
149MODULE_ALIAS("platform:s3c2412-uart");
diff --git a/drivers/tty/serial/s3c2440.c b/drivers/tty/serial/s3c2440.c
new file mode 100644
index 00000000000..1d0c324b813
--- /dev/null
+++ b/drivers/tty/serial/s3c2440.c
@@ -0,0 +1,178 @@
1/*
2 * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/module.h>
13#include <linux/ioport.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial_core.h>
18#include <linux/serial.h>
19
20#include <asm/irq.h>
21#include <mach/hardware.h>
22
23#include <plat/regs-serial.h>
24#include <mach/regs-gpio.h>
25
26#include "samsung.h"
27
28
29static int s3c2440_serial_setsource(struct uart_port *port,
30 struct s3c24xx_uart_clksrc *clk)
31{
32 unsigned long ucon = rd_regl(port, S3C2410_UCON);
33
34 /* todo - proper fclk<>nonfclk switch. */
35
36 ucon &= ~S3C2440_UCON_CLKMASK;
37
38 if (strcmp(clk->name, "uclk") == 0)
39 ucon |= S3C2440_UCON_UCLK;
40 else if (strcmp(clk->name, "pclk") == 0)
41 ucon |= S3C2440_UCON_PCLK;
42 else if (strcmp(clk->name, "fclk") == 0)
43 ucon |= S3C2440_UCON_FCLK;
44 else {
45 printk(KERN_ERR "unknown clock source %s\n", clk->name);
46 return -EINVAL;
47 }
48
49 wr_regl(port, S3C2410_UCON, ucon);
50 return 0;
51}
52
53
54static int s3c2440_serial_getsource(struct uart_port *port,
55 struct s3c24xx_uart_clksrc *clk)
56{
57 unsigned long ucon = rd_regl(port, S3C2410_UCON);
58 unsigned long ucon0, ucon1, ucon2;
59
60 switch (ucon & S3C2440_UCON_CLKMASK) {
61 case S3C2440_UCON_UCLK:
62 clk->divisor = 1;
63 clk->name = "uclk";
64 break;
65
66 case S3C2440_UCON_PCLK:
67 case S3C2440_UCON_PCLK2:
68 clk->divisor = 1;
69 clk->name = "pclk";
70 break;
71
72 case S3C2440_UCON_FCLK:
73 /* the fun of calculating the uart divisors on
74 * the s3c2440 */
75
76 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
77 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
78 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
79
80 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
81
82 ucon0 &= S3C2440_UCON0_DIVMASK;
83 ucon1 &= S3C2440_UCON1_DIVMASK;
84 ucon2 &= S3C2440_UCON2_DIVMASK;
85
86 if (ucon0 != 0) {
87 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
88 clk->divisor += 6;
89 } else if (ucon1 != 0) {
90 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
91 clk->divisor += 21;
92 } else if (ucon2 != 0) {
93 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
94 clk->divisor += 36;
95 } else {
96 /* manual calims 44, seems to be 9 */
97 clk->divisor = 9;
98 }
99
100 clk->name = "fclk";
101 break;
102 }
103
104 return 0;
105}
106
107static int s3c2440_serial_resetport(struct uart_port *port,
108 struct s3c2410_uartcfg *cfg)
109{
110 unsigned long ucon = rd_regl(port, S3C2410_UCON);
111
112 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
113 port, port->mapbase, cfg);
114
115 /* ensure we don't change the clock settings... */
116
117 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
118
119 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
120 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
121
122 /* reset both fifos */
123
124 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
125 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
126
127 return 0;
128}
129
130static struct s3c24xx_uart_info s3c2440_uart_inf = {
131 .name = "Samsung S3C2440 UART",
132 .type = PORT_S3C2440,
133 .fifosize = 64,
134 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
135 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
136 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
137 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
138 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
139 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
140 .get_clksrc = s3c2440_serial_getsource,
141 .set_clksrc = s3c2440_serial_setsource,
142 .reset_port = s3c2440_serial_resetport,
143};
144
145/* device management */
146
147static int s3c2440_serial_probe(struct platform_device *dev)
148{
149 dbg("s3c2440_serial_probe: dev=%p\n", dev);
150 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
151}
152
153static struct platform_driver s3c2440_serial_driver = {
154 .probe = s3c2440_serial_probe,
155 .remove = __devexit_p(s3c24xx_serial_remove),
156 .driver = {
157 .name = "s3c2440-uart",
158 .owner = THIS_MODULE,
159 },
160};
161
162static int __init s3c2440_serial_init(void)
163{
164 return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
165}
166
167static void __exit s3c2440_serial_exit(void)
168{
169 platform_driver_unregister(&s3c2440_serial_driver);
170}
171
172module_init(s3c2440_serial_init);
173module_exit(s3c2440_serial_exit);
174
175MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver");
176MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
177MODULE_LICENSE("GPL v2");
178MODULE_ALIAS("platform:s3c2440-uart");
diff --git a/drivers/tty/serial/s3c6400.c b/drivers/tty/serial/s3c6400.c
new file mode 100644
index 00000000000..e2f6913d84d
--- /dev/null
+++ b/drivers/tty/serial/s3c6400.c
@@ -0,0 +1,149 @@
1/*
2 * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/module.h>
15#include <linux/ioport.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21
22#include <asm/irq.h>
23#include <mach/hardware.h>
24
25#include <plat/regs-serial.h>
26
27#include "samsung.h"
28
29static int s3c6400_serial_setsource(struct uart_port *port,
30 struct s3c24xx_uart_clksrc *clk)
31{
32 unsigned long ucon = rd_regl(port, S3C2410_UCON);
33
34 if (strcmp(clk->name, "uclk0") == 0) {
35 ucon &= ~S3C6400_UCON_CLKMASK;
36 ucon |= S3C6400_UCON_UCLK0;
37 } else if (strcmp(clk->name, "uclk1") == 0)
38 ucon |= S3C6400_UCON_UCLK1;
39 else if (strcmp(clk->name, "pclk") == 0) {
40 /* See notes about transitioning from UCLK to PCLK */
41 ucon &= ~S3C6400_UCON_UCLK0;
42 } else {
43 printk(KERN_ERR "unknown clock source %s\n", clk->name);
44 return -EINVAL;
45 }
46
47 wr_regl(port, S3C2410_UCON, ucon);
48 return 0;
49}
50
51
52static int s3c6400_serial_getsource(struct uart_port *port,
53 struct s3c24xx_uart_clksrc *clk)
54{
55 u32 ucon = rd_regl(port, S3C2410_UCON);
56
57 clk->divisor = 1;
58
59 switch (ucon & S3C6400_UCON_CLKMASK) {
60 case S3C6400_UCON_UCLK0:
61 clk->name = "uclk0";
62 break;
63
64 case S3C6400_UCON_UCLK1:
65 clk->name = "uclk1";
66 break;
67
68 case S3C6400_UCON_PCLK:
69 case S3C6400_UCON_PCLK2:
70 clk->name = "pclk";
71 break;
72 }
73
74 return 0;
75}
76
77static int s3c6400_serial_resetport(struct uart_port *port,
78 struct s3c2410_uartcfg *cfg)
79{
80 unsigned long ucon = rd_regl(port, S3C2410_UCON);
81
82 dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
83 port, port->mapbase, cfg);
84
85 /* ensure we don't change the clock settings... */
86
87 ucon &= S3C6400_UCON_CLKMASK;
88
89 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
90 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
91
92 /* reset both fifos */
93
94 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
95 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
96
97 return 0;
98}
99
100static struct s3c24xx_uart_info s3c6400_uart_inf = {
101 .name = "Samsung S3C6400 UART",
102 .type = PORT_S3C6400,
103 .fifosize = 64,
104 .has_divslot = 1,
105 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
106 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
107 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
108 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
109 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
110 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
111 .get_clksrc = s3c6400_serial_getsource,
112 .set_clksrc = s3c6400_serial_setsource,
113 .reset_port = s3c6400_serial_resetport,
114};
115
116/* device management */
117
118static int s3c6400_serial_probe(struct platform_device *dev)
119{
120 dbg("s3c6400_serial_probe: dev=%p\n", dev);
121 return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
122}
123
124static struct platform_driver s3c6400_serial_driver = {
125 .probe = s3c6400_serial_probe,
126 .remove = __devexit_p(s3c24xx_serial_remove),
127 .driver = {
128 .name = "s3c6400-uart",
129 .owner = THIS_MODULE,
130 },
131};
132
133static int __init s3c6400_serial_init(void)
134{
135 return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
136}
137
138static void __exit s3c6400_serial_exit(void)
139{
140 platform_driver_unregister(&s3c6400_serial_driver);
141}
142
143module_init(s3c6400_serial_init);
144module_exit(s3c6400_serial_exit);
145
146MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
147MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
148MODULE_LICENSE("GPL v2");
149MODULE_ALIAS("platform:s3c6400-uart");
diff --git a/drivers/tty/serial/s5pv210.c b/drivers/tty/serial/s5pv210.c
new file mode 100644
index 00000000000..8b0b888a1b7
--- /dev/null
+++ b/drivers/tty/serial/s5pv210.c
@@ -0,0 +1,158 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Based on drivers/serial/s3c6400.c
6 *
7 * Driver for Samsung S5PV210 SoC UARTs.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/module.h>
15#include <linux/ioport.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/delay.h>
22
23#include <asm/irq.h>
24#include <mach/hardware.h>
25#include <plat/regs-serial.h>
26#include "samsung.h"
27
28static int s5pv210_serial_setsource(struct uart_port *port,
29 struct s3c24xx_uart_clksrc *clk)
30{
31 struct s3c2410_uartcfg *cfg = port->dev->platform_data;
32 unsigned long ucon = rd_regl(port, S3C2410_UCON);
33
34 if (cfg->flags & NO_NEED_CHECK_CLKSRC)
35 return 0;
36
37 if (strcmp(clk->name, "pclk") == 0)
38 ucon &= ~S5PV210_UCON_CLKMASK;
39 else if (strcmp(clk->name, "uclk1") == 0)
40 ucon |= S5PV210_UCON_CLKMASK;
41 else {
42 printk(KERN_ERR "unknown clock source %s\n", clk->name);
43 return -EINVAL;
44 }
45
46 wr_regl(port, S3C2410_UCON, ucon);
47 return 0;
48}
49
50
51static int s5pv210_serial_getsource(struct uart_port *port,
52 struct s3c24xx_uart_clksrc *clk)
53{
54 struct s3c2410_uartcfg *cfg = port->dev->platform_data;
55 u32 ucon = rd_regl(port, S3C2410_UCON);
56
57 clk->divisor = 1;
58
59 if (cfg->flags & NO_NEED_CHECK_CLKSRC)
60 return 0;
61
62 switch (ucon & S5PV210_UCON_CLKMASK) {
63 case S5PV210_UCON_PCLK:
64 clk->name = "pclk";
65 break;
66 case S5PV210_UCON_UCLK:
67 clk->name = "uclk1";
68 break;
69 }
70
71 return 0;
72}
73
74static int s5pv210_serial_resetport(struct uart_port *port,
75 struct s3c2410_uartcfg *cfg)
76{
77 unsigned long ucon = rd_regl(port, S3C2410_UCON);
78
79 ucon &= S5PV210_UCON_CLKMASK;
80 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
81 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
82
83 /* reset both fifos */
84 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
85 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
86
87 /* It is need to delay When reset FIFO register */
88 udelay(1);
89
90 return 0;
91}
92
93#define S5PV210_UART_DEFAULT_INFO(fifo_size) \
94 .name = "Samsung S5PV210 UART0", \
95 .type = PORT_S3C6400, \
96 .fifosize = fifo_size, \
97 .has_divslot = 1, \
98 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
99 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
100 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
101 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
102 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
103 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
104 .get_clksrc = s5pv210_serial_getsource, \
105 .set_clksrc = s5pv210_serial_setsource, \
106 .reset_port = s5pv210_serial_resetport
107
108static struct s3c24xx_uart_info s5p_port_fifo256 = {
109 S5PV210_UART_DEFAULT_INFO(256),
110};
111
112static struct s3c24xx_uart_info s5p_port_fifo64 = {
113 S5PV210_UART_DEFAULT_INFO(64),
114};
115
116static struct s3c24xx_uart_info s5p_port_fifo16 = {
117 S5PV210_UART_DEFAULT_INFO(16),
118};
119
120static struct s3c24xx_uart_info *s5p_uart_inf[] = {
121 [0] = &s5p_port_fifo256,
122 [1] = &s5p_port_fifo64,
123 [2] = &s5p_port_fifo16,
124 [3] = &s5p_port_fifo16,
125};
126
127/* device management */
128static int s5p_serial_probe(struct platform_device *pdev)
129{
130 return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev->id]);
131}
132
133static struct platform_driver s5p_serial_driver = {
134 .probe = s5p_serial_probe,
135 .remove = __devexit_p(s3c24xx_serial_remove),
136 .driver = {
137 .name = "s5pv210-uart",
138 .owner = THIS_MODULE,
139 },
140};
141
142static int __init s5p_serial_init(void)
143{
144 return s3c24xx_serial_init(&s5p_serial_driver, *s5p_uart_inf);
145}
146
147static void __exit s5p_serial_exit(void)
148{
149 platform_driver_unregister(&s5p_serial_driver);
150}
151
152module_init(s5p_serial_init);
153module_exit(s5p_serial_exit);
154
155MODULE_LICENSE("GPL");
156MODULE_ALIAS("platform:s5pv210-uart");
157MODULE_DESCRIPTION("Samsung S5PV210 UART Driver support");
158MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
diff --git a/drivers/tty/serial/serial_cs.c b/drivers/tty/serial/serial_cs.c
new file mode 100644
index 00000000000..eef736ff810
--- /dev/null
+++ b/drivers/tty/serial/serial_cs.c
@@ -0,0 +1,870 @@
1/*======================================================================
2
3 A driver for PCMCIA serial devices
4
5 serial_cs.c 1.134 2002/05/04 05:48:53
6
7 The contents of this file are subject to the Mozilla Public
8 License Version 1.1 (the "License"); you may not use this file
9 except in compliance with the License. You may obtain a copy of
10 the License at http://www.mozilla.org/MPL/
11
12 Software distributed under the License is distributed on an "AS
13 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
14 implied. See the License for the specific language governing
15 rights and limitations under the License.
16
17 The initial developer of the original code is David A. Hinds
18 <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
19 are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
20
21 Alternatively, the contents of this file may be used under the
22 terms of the GNU General Public License version 2 (the "GPL"), in which
23 case the provisions of the GPL are applicable instead of the
24 above. If you wish to allow the use of your version of this file
25 only under the terms of the GPL and not to allow others to use
26 your version of this file under the MPL, indicate your decision
27 by deleting the provisions above and replace them with the notice
28 and other provisions required by the GPL. If you do not delete
29 the provisions above, a recipient may use your version of this
30 file under either the MPL or the GPL.
31
32======================================================================*/
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/ptrace.h>
39#include <linux/slab.h>
40#include <linux/string.h>
41#include <linux/timer.h>
42#include <linux/serial_core.h>
43#include <linux/delay.h>
44#include <linux/major.h>
45#include <asm/io.h>
46#include <asm/system.h>
47
48#include <pcmcia/cistpl.h>
49#include <pcmcia/ciscode.h>
50#include <pcmcia/ds.h>
51#include <pcmcia/cisreg.h>
52
53#include "8250.h"
54
55
56/*====================================================================*/
57
58/* Parameters that can be set with 'insmod' */
59
60/* Enable the speaker? */
61static int do_sound = 1;
62/* Skip strict UART tests? */
63static int buggy_uart;
64
65module_param(do_sound, int, 0444);
66module_param(buggy_uart, int, 0444);
67
68/*====================================================================*/
69
70/* Table of multi-port card ID's */
71
72struct serial_quirk {
73 unsigned int manfid;
74 unsigned int prodid;
75 int multi; /* 1 = multifunction, > 1 = # ports */
76 void (*config)(struct pcmcia_device *);
77 void (*setup)(struct pcmcia_device *, struct uart_port *);
78 void (*wakeup)(struct pcmcia_device *);
79 int (*post)(struct pcmcia_device *);
80};
81
82struct serial_info {
83 struct pcmcia_device *p_dev;
84 int ndev;
85 int multi;
86 int slave;
87 int manfid;
88 int prodid;
89 int c950ctrl;
90 int line[4];
91 const struct serial_quirk *quirk;
92};
93
94struct serial_cfg_mem {
95 tuple_t tuple;
96 cisparse_t parse;
97 u_char buf[256];
98};
99
100/*
101 * vers_1 5.0, "Brain Boxes", "2-Port RS232 card", "r6"
102 * manfid 0x0160, 0x0104
103 * This card appears to have a 14.7456MHz clock.
104 */
105/* Generic Modem: MD55x (GPRS/EDGE) have
106 * Elan VPU16551 UART with 14.7456MHz oscillator
107 * manfid 0x015D, 0x4C45
108 */
109static void quirk_setup_brainboxes_0104(struct pcmcia_device *link, struct uart_port *port)
110{
111 port->uartclk = 14745600;
112}
113
114static int quirk_post_ibm(struct pcmcia_device *link)
115{
116 u8 val;
117 int ret;
118
119 ret = pcmcia_read_config_byte(link, 0x800, &val);
120 if (ret)
121 goto failed;
122
123 ret = pcmcia_write_config_byte(link, 0x800, val | 1);
124 if (ret)
125 goto failed;
126 return 0;
127
128 failed:
129 return -ENODEV;
130}
131
132/*
133 * Nokia cards are not really multiport cards. Shouldn't this
134 * be handled by setting the quirk entry .multi = 0 | 1 ?
135 */
136static void quirk_config_nokia(struct pcmcia_device *link)
137{
138 struct serial_info *info = link->priv;
139
140 if (info->multi > 1)
141 info->multi = 1;
142}
143
144static void quirk_wakeup_oxsemi(struct pcmcia_device *link)
145{
146 struct serial_info *info = link->priv;
147
148 if (info->c950ctrl)
149 outb(12, info->c950ctrl + 1);
150}
151
152/* request_region? oxsemi branch does no request_region too... */
153/*
154 * This sequence is needed to properly initialize MC45 attached to OXCF950.
155 * I tried decreasing these msleep()s, but it worked properly (survived
156 * 1000 stop/start operations) with these timeouts (or bigger).
157 */
158static void quirk_wakeup_possio_gcc(struct pcmcia_device *link)
159{
160 struct serial_info *info = link->priv;
161 unsigned int ctrl = info->c950ctrl;
162
163 outb(0xA, ctrl + 1);
164 msleep(100);
165 outb(0xE, ctrl + 1);
166 msleep(300);
167 outb(0xC, ctrl + 1);
168 msleep(100);
169 outb(0xE, ctrl + 1);
170 msleep(200);
171 outb(0xF, ctrl + 1);
172 msleep(100);
173 outb(0xE, ctrl + 1);
174 msleep(100);
175 outb(0xC, ctrl + 1);
176}
177
178/*
179 * Socket Dual IO: this enables irq's for second port
180 */
181static void quirk_config_socket(struct pcmcia_device *link)
182{
183 struct serial_info *info = link->priv;
184
185 if (info->multi)
186 link->config_flags |= CONF_ENABLE_ESR;
187}
188
189static const struct serial_quirk quirks[] = {
190 {
191 .manfid = 0x0160,
192 .prodid = 0x0104,
193 .multi = -1,
194 .setup = quirk_setup_brainboxes_0104,
195 }, {
196 .manfid = 0x015D,
197 .prodid = 0x4C45,
198 .multi = -1,
199 .setup = quirk_setup_brainboxes_0104,
200 }, {
201 .manfid = MANFID_IBM,
202 .prodid = ~0,
203 .multi = -1,
204 .post = quirk_post_ibm,
205 }, {
206 .manfid = MANFID_INTEL,
207 .prodid = PRODID_INTEL_DUAL_RS232,
208 .multi = 2,
209 }, {
210 .manfid = MANFID_NATINST,
211 .prodid = PRODID_NATINST_QUAD_RS232,
212 .multi = 4,
213 }, {
214 .manfid = MANFID_NOKIA,
215 .prodid = ~0,
216 .multi = -1,
217 .config = quirk_config_nokia,
218 }, {
219 .manfid = MANFID_OMEGA,
220 .prodid = PRODID_OMEGA_QSP_100,
221 .multi = 4,
222 }, {
223 .manfid = MANFID_OXSEMI,
224 .prodid = ~0,
225 .multi = -1,
226 .wakeup = quirk_wakeup_oxsemi,
227 }, {
228 .manfid = MANFID_POSSIO,
229 .prodid = PRODID_POSSIO_GCC,
230 .multi = -1,
231 .wakeup = quirk_wakeup_possio_gcc,
232 }, {
233 .manfid = MANFID_QUATECH,
234 .prodid = PRODID_QUATECH_DUAL_RS232,
235 .multi = 2,
236 }, {
237 .manfid = MANFID_QUATECH,
238 .prodid = PRODID_QUATECH_DUAL_RS232_D1,
239 .multi = 2,
240 }, {
241 .manfid = MANFID_QUATECH,
242 .prodid = PRODID_QUATECH_DUAL_RS232_G,
243 .multi = 2,
244 }, {
245 .manfid = MANFID_QUATECH,
246 .prodid = PRODID_QUATECH_QUAD_RS232,
247 .multi = 4,
248 }, {
249 .manfid = MANFID_SOCKET,
250 .prodid = PRODID_SOCKET_DUAL_RS232,
251 .multi = 2,
252 .config = quirk_config_socket,
253 }, {
254 .manfid = MANFID_SOCKET,
255 .prodid = ~0,
256 .multi = -1,
257 .config = quirk_config_socket,
258 }
259};
260
261
262static int serial_config(struct pcmcia_device * link);
263
264
265static void serial_remove(struct pcmcia_device *link)
266{
267 struct serial_info *info = link->priv;
268 int i;
269
270 dev_dbg(&link->dev, "serial_release\n");
271
272 /*
273 * Recheck to see if the device is still configured.
274 */
275 for (i = 0; i < info->ndev; i++)
276 serial8250_unregister_port(info->line[i]);
277
278 if (!info->slave)
279 pcmcia_disable_device(link);
280}
281
282static int serial_suspend(struct pcmcia_device *link)
283{
284 struct serial_info *info = link->priv;
285 int i;
286
287 for (i = 0; i < info->ndev; i++)
288 serial8250_suspend_port(info->line[i]);
289
290 return 0;
291}
292
293static int serial_resume(struct pcmcia_device *link)
294{
295 struct serial_info *info = link->priv;
296 int i;
297
298 for (i = 0; i < info->ndev; i++)
299 serial8250_resume_port(info->line[i]);
300
301 if (info->quirk && info->quirk->wakeup)
302 info->quirk->wakeup(link);
303
304 return 0;
305}
306
307static int serial_probe(struct pcmcia_device *link)
308{
309 struct serial_info *info;
310
311 dev_dbg(&link->dev, "serial_attach()\n");
312
313 /* Create new serial device */
314 info = kzalloc(sizeof (*info), GFP_KERNEL);
315 if (!info)
316 return -ENOMEM;
317 info->p_dev = link;
318 link->priv = info;
319
320 link->config_flags |= CONF_ENABLE_IRQ;
321 if (do_sound)
322 link->config_flags |= CONF_ENABLE_SPKR;
323
324 return serial_config(link);
325}
326
327static void serial_detach(struct pcmcia_device *link)
328{
329 struct serial_info *info = link->priv;
330
331 dev_dbg(&link->dev, "serial_detach\n");
332
333 /*
334 * Ensure that the ports have been released.
335 */
336 serial_remove(link);
337
338 /* free bits */
339 kfree(info);
340}
341
342/*====================================================================*/
343
344static int setup_serial(struct pcmcia_device *handle, struct serial_info * info,
345 unsigned int iobase, int irq)
346{
347 struct uart_port port;
348 int line;
349
350 memset(&port, 0, sizeof (struct uart_port));
351 port.iobase = iobase;
352 port.irq = irq;
353 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
354 port.uartclk = 1843200;
355 port.dev = &handle->dev;
356 if (buggy_uart)
357 port.flags |= UPF_BUGGY_UART;
358
359 if (info->quirk && info->quirk->setup)
360 info->quirk->setup(handle, &port);
361
362 line = serial8250_register_port(&port);
363 if (line < 0) {
364 printk(KERN_NOTICE "serial_cs: serial8250_register_port() at "
365 "0x%04lx, irq %d failed\n", (u_long)iobase, irq);
366 return -EINVAL;
367 }
368
369 info->line[info->ndev] = line;
370 info->ndev++;
371
372 return 0;
373}
374
375/*====================================================================*/
376
377static int pfc_config(struct pcmcia_device *p_dev)
378{
379 unsigned int port = 0;
380 struct serial_info *info = p_dev->priv;
381
382 if ((p_dev->resource[1]->end != 0) &&
383 (resource_size(p_dev->resource[1]) == 8)) {
384 port = p_dev->resource[1]->start;
385 info->slave = 1;
386 } else if ((info->manfid == MANFID_OSITECH) &&
387 (resource_size(p_dev->resource[0]) == 0x40)) {
388 port = p_dev->resource[0]->start + 0x28;
389 info->slave = 1;
390 }
391 if (info->slave)
392 return setup_serial(p_dev, info, port, p_dev->irq);
393
394 dev_warn(&p_dev->dev, "no usable port range found, giving up\n");
395 return -ENODEV;
396}
397
398static int simple_config_check(struct pcmcia_device *p_dev, void *priv_data)
399{
400 static const int size_table[2] = { 8, 16 };
401 int *try = priv_data;
402
403 if (p_dev->resource[0]->start == 0)
404 return -ENODEV;
405
406 if ((*try & 0x1) == 0)
407 p_dev->io_lines = 16;
408
409 if (p_dev->resource[0]->end != size_table[(*try >> 1)])
410 return -ENODEV;
411
412 p_dev->resource[0]->end = 8;
413 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
414 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
415
416 return pcmcia_request_io(p_dev);
417}
418
419static int simple_config_check_notpicky(struct pcmcia_device *p_dev,
420 void *priv_data)
421{
422 static const unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
423 int j;
424
425 if (p_dev->io_lines > 3)
426 return -ENODEV;
427
428 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
429 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
430 p_dev->resource[0]->end = 8;
431
432 for (j = 0; j < 5; j++) {
433 p_dev->resource[0]->start = base[j];
434 p_dev->io_lines = base[j] ? 16 : 3;
435 if (!pcmcia_request_io(p_dev))
436 return 0;
437 }
438 return -ENODEV;
439}
440
441static int simple_config(struct pcmcia_device *link)
442{
443 struct serial_info *info = link->priv;
444 int i = -ENODEV, try;
445
446 /* First pass: look for a config entry that looks normal.
447 * Two tries: without IO aliases, then with aliases */
448 link->config_flags |= CONF_AUTO_SET_VPP | CONF_AUTO_SET_IO;
449 for (try = 0; try < 4; try++)
450 if (!pcmcia_loop_config(link, simple_config_check, &try))
451 goto found_port;
452
453 /* Second pass: try to find an entry that isn't picky about
454 its base address, then try to grab any standard serial port
455 address, and finally try to get any free port. */
456 if (!pcmcia_loop_config(link, simple_config_check_notpicky, NULL))
457 goto found_port;
458
459 dev_warn(&link->dev, "no usable port range found, giving up\n");
460 return -1;
461
462found_port:
463 if (info->multi && (info->manfid == MANFID_3COM))
464 link->config_index &= ~(0x08);
465
466 /*
467 * Apply any configuration quirks.
468 */
469 if (info->quirk && info->quirk->config)
470 info->quirk->config(link);
471
472 i = pcmcia_enable_device(link);
473 if (i != 0)
474 return -1;
475 return setup_serial(link, info, link->resource[0]->start, link->irq);
476}
477
478static int multi_config_check(struct pcmcia_device *p_dev, void *priv_data)
479{
480 int *multi = priv_data;
481
482 if (p_dev->resource[1]->end)
483 return -EINVAL;
484
485 /* The quad port cards have bad CIS's, so just look for a
486 window larger than 8 ports and assume it will be right */
487 if (p_dev->resource[0]->end <= 8)
488 return -EINVAL;
489
490 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
491 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
492 p_dev->resource[0]->end = *multi * 8;
493
494 if (pcmcia_request_io(p_dev))
495 return -ENODEV;
496 return 0;
497}
498
499static int multi_config_check_notpicky(struct pcmcia_device *p_dev,
500 void *priv_data)
501{
502 int *base2 = priv_data;
503
504 if (!p_dev->resource[0]->end || !p_dev->resource[1]->end)
505 return -ENODEV;
506
507 p_dev->resource[0]->end = p_dev->resource[1]->end = 8;
508 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
509 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
510
511 if (pcmcia_request_io(p_dev))
512 return -ENODEV;
513
514 *base2 = p_dev->resource[0]->start + 8;
515 return 0;
516}
517
518static int multi_config(struct pcmcia_device *link)
519{
520 struct serial_info *info = link->priv;
521 int i, base2 = 0;
522
523 link->config_flags |= CONF_AUTO_SET_IO;
524 /* First, look for a generic full-sized window */
525 if (!pcmcia_loop_config(link, multi_config_check, &info->multi))
526 base2 = link->resource[0]->start + 8;
527 else {
528 /* If that didn't work, look for two windows */
529 info->multi = 2;
530 if (pcmcia_loop_config(link, multi_config_check_notpicky,
531 &base2)) {
532 dev_warn(&link->dev, "no usable port range "
533 "found, giving up\n");
534 return -ENODEV;
535 }
536 }
537
538 if (!link->irq)
539 dev_warn(&link->dev, "no usable IRQ found, continuing...\n");
540
541 /*
542 * Apply any configuration quirks.
543 */
544 if (info->quirk && info->quirk->config)
545 info->quirk->config(link);
546
547 i = pcmcia_enable_device(link);
548 if (i != 0)
549 return -ENODEV;
550
551 /* The Oxford Semiconductor OXCF950 cards are in fact single-port:
552 * 8 registers are for the UART, the others are extra registers.
553 * Siemen's MC45 PCMCIA (Possio's GCC) is OXCF950 based too.
554 */
555 if (info->manfid == MANFID_OXSEMI || (info->manfid == MANFID_POSSIO &&
556 info->prodid == PRODID_POSSIO_GCC)) {
557 int err;
558
559 if (link->config_index == 1 ||
560 link->config_index == 3) {
561 err = setup_serial(link, info, base2,
562 link->irq);
563 base2 = link->resource[0]->start;
564 } else {
565 err = setup_serial(link, info, link->resource[0]->start,
566 link->irq);
567 }
568 info->c950ctrl = base2;
569
570 /*
571 * FIXME: We really should wake up the port prior to
572 * handing it over to the serial layer.
573 */
574 if (info->quirk && info->quirk->wakeup)
575 info->quirk->wakeup(link);
576
577 return 0;
578 }
579
580 setup_serial(link, info, link->resource[0]->start, link->irq);
581 for (i = 0; i < info->multi - 1; i++)
582 setup_serial(link, info, base2 + (8 * i),
583 link->irq);
584 return 0;
585}
586
587static int serial_check_for_multi(struct pcmcia_device *p_dev, void *priv_data)
588{
589 struct serial_info *info = p_dev->priv;
590
591 if (!p_dev->resource[0]->end)
592 return -EINVAL;
593
594 if ((!p_dev->resource[1]->end) && (p_dev->resource[0]->end % 8 == 0))
595 info->multi = p_dev->resource[0]->end >> 3;
596
597 if ((p_dev->resource[1]->end) && (p_dev->resource[0]->end == 8)
598 && (p_dev->resource[1]->end == 8))
599 info->multi = 2;
600
601 return 0; /* break */
602}
603
604
605static int serial_config(struct pcmcia_device * link)
606{
607 struct serial_info *info = link->priv;
608 int i;
609
610 dev_dbg(&link->dev, "serial_config\n");
611
612 /* Is this a compliant multifunction card? */
613 info->multi = (link->socket->functions > 1);
614
615 /* Is this a multiport card? */
616 info->manfid = link->manf_id;
617 info->prodid = link->card_id;
618
619 for (i = 0; i < ARRAY_SIZE(quirks); i++)
620 if ((quirks[i].manfid == ~0 ||
621 quirks[i].manfid == info->manfid) &&
622 (quirks[i].prodid == ~0 ||
623 quirks[i].prodid == info->prodid)) {
624 info->quirk = &quirks[i];
625 break;
626 }
627
628 /* Another check for dual-serial cards: look for either serial or
629 multifunction cards that ask for appropriate IO port ranges */
630 if ((info->multi == 0) &&
631 (link->has_func_id) &&
632 (link->socket->pcmcia_pfc == 0) &&
633 ((link->func_id == CISTPL_FUNCID_MULTI) ||
634 (link->func_id == CISTPL_FUNCID_SERIAL)))
635 pcmcia_loop_config(link, serial_check_for_multi, info);
636
637 /*
638 * Apply any multi-port quirk.
639 */
640 if (info->quirk && info->quirk->multi != -1)
641 info->multi = info->quirk->multi;
642
643 dev_info(&link->dev,
644 "trying to set up [0x%04x:0x%04x] (pfc: %d, multi: %d, quirk: %p)\n",
645 link->manf_id, link->card_id,
646 link->socket->pcmcia_pfc, info->multi, info->quirk);
647 if (link->socket->pcmcia_pfc)
648 i = pfc_config(link);
649 else if (info->multi > 1)
650 i = multi_config(link);
651 else
652 i = simple_config(link);
653
654 if (i || info->ndev == 0)
655 goto failed;
656
657 /*
658 * Apply any post-init quirk. FIXME: This should really happen
659 * before we register the port, since it might already be in use.
660 */
661 if (info->quirk && info->quirk->post)
662 if (info->quirk->post(link))
663 goto failed;
664
665 return 0;
666
667failed:
668 dev_warn(&link->dev, "failed to initialize\n");
669 serial_remove(link);
670 return -ENODEV;
671}
672
673static const struct pcmcia_device_id serial_ids[] = {
674 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0057, 0x0021),
675 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0089, 0x110a),
676 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0104, 0x000a),
677 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0d0a),
678 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0e0a),
679 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0xea15),
680 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0109, 0x0501),
681 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0138, 0x110a),
682 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0140, 0x000a),
683 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0x3341),
684 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0xc0ab),
685 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x016c, 0x0081),
686 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x021b, 0x0101),
687 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x08a1, 0xc0ab),
688 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3288", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x04cd2988, 0x46a52d63),
689 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3336", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x0143b773, 0x46a52d63),
690 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "EM1144T", "PCMCIA MODEM", 0xf510db04, 0x856d66c8, 0xbd6c43ef),
691 PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "XJEM1144/CCEM1144", "PCMCIA MODEM", 0xf510db04, 0x52d21e1e, 0xbd6c43ef),
692 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM28", 0x2e3ee845, 0x0ea978ea),
693 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM33", 0x2e3ee845, 0x80609023),
694 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM56", 0x2e3ee845, 0xa650c32a),
695 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "REM10", 0x2e3ee845, 0x76df1d29),
696 PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "XEM5600", 0x2e3ee845, 0xf1403719),
697 PCMCIA_PFC_DEVICE_PROD_ID12(1, "AnyCom", "Fast Ethernet + 56K COMBO", 0x578ba6e7, 0xb0ac62c4),
698 PCMCIA_PFC_DEVICE_PROD_ID12(1, "ATKK", "LM33-PCM-T", 0xba9eb7e2, 0x077c174e),
699 PCMCIA_PFC_DEVICE_PROD_ID12(1, "D-Link", "DME336T", 0x1a424a1c, 0xb23897ff),
700 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Gateway 2000", "XJEM3336", 0xdd9989be, 0x662c394c),
701 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Grey Cell", "GCS3000", 0x2a151fac, 0x48b932ae),
702 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Linksys", "EtherFast 10&100 + 56K PC Card (PCMLM56)", 0x0733cc81, 0xb3765033),
703 PCMCIA_PFC_DEVICE_PROD_ID12(1, "LINKSYS", "PCMLM336", 0xf7cb0b07, 0x7a821b58),
704 PCMCIA_PFC_DEVICE_PROD_ID12(1, "MEGAHERTZ", "XJEM1144/CCEM1144", 0xf510db04, 0x52d21e1e),
705 PCMCIA_PFC_DEVICE_PROD_ID12(1, "MICRO RESEARCH", "COMBO-L/M-336", 0xb2ced065, 0x3ced0555),
706 PCMCIA_PFC_DEVICE_PROD_ID12(1, "NEC", "PK-UG-J001" ,0x18df0ba0 ,0x831b1064),
707 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Diamonds Modem+Ethernet", 0xc2f80cd, 0x656947b9),
708 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Hearts Modem+Ethernet", 0xc2f80cd, 0xdc9ba5ed),
709 PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "ComboCard", 0xdcfe12d3, 0xcd8906cc),
710 PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "LanModem", 0xdcfe12d3, 0xc67c648f),
711 PCMCIA_PFC_DEVICE_PROD_ID12(1, "TDK", "GlobalNetworker 3410/3412", 0x1eae9475, 0xd9a93bed),
712 PCMCIA_PFC_DEVICE_PROD_ID12(1, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
713 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0e01),
714 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0a05),
715 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0b05),
716 PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x1101),
717 PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0104, 0x0070),
718 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0101, 0x0562),
719 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0104, 0x0070),
720 PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x016c, 0x0020),
721 PCMCIA_MFC_DEVICE_PROD_ID123(1, "APEX DATA", "MULTICARD", "ETHERNET-MODEM", 0x11c2da09, 0x7289dc5d, 0xaad95e1f),
722 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away 28.8 PC Card ", 0xb569a6e5, 0x5bd4ff2c),
723 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away Credit Card Adapter", 0xb569a6e5, 0x4bdf15c3),
724 PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "w95 Home and Away Credit Card ", 0xb569a6e5, 0xae911c15),
725 PCMCIA_MFC_DEVICE_PROD_ID1(1, "Motorola MARQUIS", 0xf03e4e77),
726 PCMCIA_MFC_DEVICE_PROD_ID2(1, "FAX/Modem/Ethernet Combo Card ", 0x1ed59302),
727 PCMCIA_DEVICE_MANF_CARD(0x0089, 0x0301),
728 PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x0276),
729 PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0039),
730 PCMCIA_DEVICE_MANF_CARD(0x0104, 0x0006),
731 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x0101), /* TDK DF2814 */
732 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x100a), /* Xircom CM-56G */
733 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x3e0a), /* TDK DF5660 */
734 PCMCIA_DEVICE_MANF_CARD(0x0105, 0x410a),
735 PCMCIA_DEVICE_MANF_CARD(0x0107, 0x0002), /* USRobotics 14,400 */
736 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d50),
737 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d51),
738 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d52),
739 PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d53),
740 PCMCIA_DEVICE_MANF_CARD(0x010b, 0xd180),
741 PCMCIA_DEVICE_MANF_CARD(0x0115, 0x3330), /* USRobotics/SUN 14,400 */
742 PCMCIA_DEVICE_MANF_CARD(0x0124, 0x0100), /* Nokia DTP-2 ver II */
743 PCMCIA_DEVICE_MANF_CARD(0x0134, 0x5600), /* LASAT COMMUNICATIONS A/S */
744 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x000e),
745 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x001b),
746 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025),
747 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045),
748 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052),
749 PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */
750 PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */
751 PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae),
752 PCMCIA_DEVICE_PROD_ID124("GATEWAY2000", "CC3144", "PCMCIA MODEM", 0x506bccae, 0xcb3685f1, 0xbd6c43ef),
753 PCMCIA_DEVICE_PROD_ID14("MEGAHERTZ", "PCMCIA MODEM", 0xf510db04, 0xbd6c43ef),
754 PCMCIA_DEVICE_PROD_ID124("TOSHIBA", "T144PF", "PCMCIA MODEM", 0xb4585a1a, 0x7271409c, 0xbd6c43ef),
755 PCMCIA_DEVICE_PROD_ID123("FUJITSU", "FC14F ", "MBH10213", 0x6ee5a3d8, 0x30ead12b, 0xb00f05a0),
756 PCMCIA_DEVICE_PROD_ID123("Novatel Wireless", "Merlin UMTS Modem", "U630", 0x32607776, 0xd9e73b13, 0xe87332e),
757 PCMCIA_DEVICE_PROD_ID13("MEGAHERTZ", "V.34 PCMCIA MODEM", 0xf510db04, 0xbb2cce4a),
758 PCMCIA_DEVICE_PROD_ID12("Brain Boxes", "Bluetooth PC Card", 0xee138382, 0xd4ce9b02),
759 PCMCIA_DEVICE_PROD_ID12("CIRRUS LOGIC", "FAX MODEM", 0xe625f451, 0xcecd6dfa),
760 PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 28800 FAX/DATA MODEM", 0xa3a3062c, 0x8cbd7c76),
761 PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 33600 FAX/DATA MODEM", 0xa3a3062c, 0x5a00ce95),
762 PCMCIA_DEVICE_PROD_ID12("Computerboards, Inc.", "PCM-COM422", 0xd0b78f51, 0x7e2d49ed),
763 PCMCIA_DEVICE_PROD_ID12("Dr. Neuhaus", "FURY CARD 14K4", 0x76942813, 0x8b96ce65),
764 PCMCIA_DEVICE_PROD_ID12("IBM", "ISDN/56K/GSM", 0xb569a6e5, 0xfee5297b),
765 PCMCIA_DEVICE_PROD_ID12("Intelligent", "ANGIA FAX/MODEM", 0xb496e65e, 0xf31602a6),
766 PCMCIA_DEVICE_PROD_ID12("Intel", "MODEM 2400+", 0x816cc815, 0x412729fb),
767 PCMCIA_DEVICE_PROD_ID12("Intertex", "IX34-PCMCIA", 0xf8a097e3, 0x97880447),
768 PCMCIA_DEVICE_PROD_ID12("IOTech Inc ", "PCMCIA Dual RS-232 Serial Port Card", 0x3bd2d898, 0x92abc92f),
769 PCMCIA_DEVICE_PROD_ID12("MACRONIX", "FAX/MODEM", 0x668388b3, 0x3f9bdf2f),
770 PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT1432LT", 0x5f73be51, 0x0b3e2383),
771 PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT2834LT", 0x5f73be51, 0x4cd7c09e),
772 PCMCIA_DEVICE_PROD_ID12("OEM ", "C288MX ", 0xb572d360, 0xd2385b7a),
773 PCMCIA_DEVICE_PROD_ID12("Option International", "V34bis GSM/PSTN Data/Fax Modem", 0x9d7cd6f5, 0x5cb8bf41),
774 PCMCIA_DEVICE_PROD_ID12("PCMCIA ", "C336MX ", 0x99bcafe9, 0xaa25bcab),
775 PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "PCMCIA Dual RS-232 Serial Port Card", 0xc4420b35, 0x92abc92f),
776 PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "Dual RS-232 Serial Port PC Card", 0xc4420b35, 0x031a380d),
777 PCMCIA_DEVICE_PROD_ID12("Telia", "SurfinBird 560P/A+", 0xe2cdd5e, 0xc9314b38),
778 PCMCIA_DEVICE_PROD_ID1("Smart Serial Port", 0x2d8ce292),
779 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "EN2218-LAN/MODEM", 0x281f1c5d, 0x570f348e, "cis/PCMLM28.cis"),
780 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "UE2218-LAN/MODEM", 0x281f1c5d, 0x6fdcacee, "cis/PCMLM28.cis"),
781 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet", 0xf5f025c2, 0x338e8155, "cis/PCMLM28.cis"),
782 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet GSM", 0xf5f025c2, 0x4ae85d35, "cis/PCMLM28.cis"),
783 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "LINKSYS", "PCMLM28", 0xf7cb0b07, 0x66881874, "cis/PCMLM28.cis"),
784 PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "TOSHIBA", "Modem/LAN Card", 0xb4585a1a, 0x53f922f8, "cis/PCMLM28.cis"),
785 PCMCIA_MFC_DEVICE_CIS_PROD_ID12(1, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "cis/DP83903.cis"),
786 PCMCIA_MFC_DEVICE_CIS_PROD_ID4(1, "NSC MF LAN/Modem", 0x58fc6056, "cis/DP83903.cis"),
787 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0556, "cis/3CCFEM556.cis"),
788 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0175, 0x0000, "cis/DP83903.cis"),
789 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0035, "cis/3CXEM556.cis"),
790 PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x003d, "cis/3CXEM556.cis"),
791 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC850", 0xd85f6206, 0x42a2c018, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC850 3G Network Adapter R1 */
792 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC860", 0xd85f6206, 0x698f93db, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC860 3G Network Adapter R1 */
793 PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC710/AC750", 0xd85f6206, 0x761b11e0, "cis/SW_7xx_SER.cis"), /* Sierra Wireless AC710/AC750 GPRS Network Adapter R1 */
794 PCMCIA_DEVICE_CIS_MANF_CARD(0x0192, 0xa555, "cis/SW_555_SER.cis"), /* Sierra Aircard 555 CDMA 1xrtt Modem -- pre update */
795 PCMCIA_DEVICE_CIS_MANF_CARD(0x013f, 0xa555, "cis/SW_555_SER.cis"), /* Sierra Aircard 555 CDMA 1xrtt Modem -- post update */
796 PCMCIA_DEVICE_CIS_PROD_ID12("MultiTech", "PCMCIA 56K DataFax", 0x842047ee, 0xc2efcf03, "cis/MT5634ZLX.cis"),
797 PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-2", 0x96913a85, 0x27ab5437, "cis/COMpad2.cis"),
798 PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-4", 0x96913a85, 0xcec8f102, "cis/COMpad4.cis"),
799 PCMCIA_DEVICE_CIS_PROD_ID123("ADVANTECH", "COMpad-32/85", "1.0", 0x96913a85, 0x8fbe92ae, 0x0877b627, "cis/COMpad2.cis"),
800 PCMCIA_DEVICE_CIS_PROD_ID2("RS-COM 2P", 0xad20b156, "cis/RS-COM-2P.cis"),
801 PCMCIA_DEVICE_CIS_MANF_CARD(0x0013, 0x0000, "cis/GLOBETROTTER.cis"),
802 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100 1.00.",0x19ca78af,0xf964f42b),
803 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100",0x19ca78af,0x71d98e83),
804 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL232 1.00.",0x19ca78af,0x69fb7490),
805 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL232",0x19ca78af,0xb6bc0235),
806 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.","SERIAL CARD: CF232",0x63f2e0bd,0xb9e175d3),
807 PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.","SERIAL CARD: CF232-5",0x63f2e0bd,0xfce33442),
808 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF232",0x3beb8cf2,0x171e7190),
809 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF232-5",0x3beb8cf2,0x20da4262),
810 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF428",0x3beb8cf2,0xea5dd57d),
811 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF500",0x3beb8cf2,0xd77255fa),
812 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: IC232",0x3beb8cf2,0x6a709903),
813 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: SL232",0x3beb8cf2,0x18430676),
814 PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: XL232",0x3beb8cf2,0x6f933767),
815 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: CF332",0x3beb8cf2,0x16dc1ba7),
816 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL332",0x3beb8cf2,0x19816c41),
817 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL385",0x3beb8cf2,0x64112029),
818 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
819 PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial+Parallel Port: SP230",0x3beb8cf2,0xdb9e58bc),
820 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: CF332",0x3beb8cf2,0x16dc1ba7),
821 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL332",0x3beb8cf2,0x19816c41),
822 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL385",0x3beb8cf2,0x64112029),
823 PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
824 PCMCIA_MFC_DEVICE_PROD_ID12(2,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
825 PCMCIA_MFC_DEVICE_PROD_ID12(3,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
826 PCMCIA_DEVICE_MANF_CARD(0x0279, 0x950b),
827 /* too generic */
828 /* PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0160, 0x0002), */
829 /* PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0160, 0x0002), */
830 PCMCIA_DEVICE_FUNC_ID(2),
831 PCMCIA_DEVICE_NULL,
832};
833MODULE_DEVICE_TABLE(pcmcia, serial_ids);
834
835MODULE_FIRMWARE("cis/PCMLM28.cis");
836MODULE_FIRMWARE("cis/DP83903.cis");
837MODULE_FIRMWARE("cis/3CCFEM556.cis");
838MODULE_FIRMWARE("cis/3CXEM556.cis");
839MODULE_FIRMWARE("cis/SW_8xx_SER.cis");
840MODULE_FIRMWARE("cis/SW_7xx_SER.cis");
841MODULE_FIRMWARE("cis/SW_555_SER.cis");
842MODULE_FIRMWARE("cis/MT5634ZLX.cis");
843MODULE_FIRMWARE("cis/COMpad2.cis");
844MODULE_FIRMWARE("cis/COMpad4.cis");
845MODULE_FIRMWARE("cis/RS-COM-2P.cis");
846
847static struct pcmcia_driver serial_cs_driver = {
848 .owner = THIS_MODULE,
849 .name = "serial_cs",
850 .probe = serial_probe,
851 .remove = serial_detach,
852 .id_table = serial_ids,
853 .suspend = serial_suspend,
854 .resume = serial_resume,
855};
856
857static int __init init_serial_cs(void)
858{
859 return pcmcia_register_driver(&serial_cs_driver);
860}
861
862static void __exit exit_serial_cs(void)
863{
864 pcmcia_unregister_driver(&serial_cs_driver);
865}
866
867module_init(init_serial_cs);
868module_exit(exit_serial_cs);
869
870MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/suncore.h b/drivers/tty/serial/suncore.h
new file mode 100644
index 00000000000..db2057936c3
--- /dev/null
+++ b/drivers/tty/serial/suncore.h
@@ -0,0 +1,33 @@
1/* suncore.h
2 *
3 * Generic SUN serial/kbd/ms layer. Based entirely
4 * upon drivers/sbus/char/sunserial.h which is:
5 *
6 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
7 *
8 * Port to new UART layer is:
9 *
10 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
11 */
12
13#ifndef _SERIAL_SUN_H
14#define _SERIAL_SUN_H
15
16/* Serial keyboard defines for L1-A processing... */
17#define SUNKBD_RESET 0xff
18#define SUNKBD_L1 0x01
19#define SUNKBD_UP 0x80
20#define SUNKBD_A 0x4d
21
22extern unsigned int suncore_mouse_baud_cflag_next(unsigned int, int *);
23extern int suncore_mouse_baud_detection(unsigned char, int);
24
25extern int sunserial_register_minors(struct uart_driver *, int);
26extern void sunserial_unregister_minors(struct uart_driver *, int);
27
28extern int sunserial_console_match(struct console *, struct device_node *,
29 struct uart_driver *, int, bool);
30extern void sunserial_console_termios(struct console *,
31 struct device_node *);
32
33#endif /* !(_SERIAL_SUN_H) */
diff --git a/drivers/tty/serial/tegra_hsuart.c b/drivers/tty/serial/tegra_hsuart.c
new file mode 100644
index 00000000000..4169cbcbf29
--- /dev/null
+++ b/drivers/tty/serial/tegra_hsuart.c
@@ -0,0 +1,1682 @@
1/*
2 * drivers/serial/tegra_hsuart.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (C) 2009-2011 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/serial.h>
25#include <linux/serial_core.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmapool.h>
30#include <linux/termios.h>
31#include <linux/irq.h>
32#include <linux/delay.h>
33#include <linux/clk.h>
34#include <linux/string.h>
35#include <linux/pagemap.h>
36#include <linux/serial_reg.h>
37#include <linux/serial_8250.h>
38#include <linux/debugfs.h>
39#include <linux/slab.h>
40#include <linux/workqueue.h>
41#include <linux/tegra_uart.h>
42
43#include <mach/dma.h>
44#include <mach/clk.h>
45
46#define TEGRA_UART_TYPE "TEGRA_UART"
47
48#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
49
50#define BYTES_TO_ALIGN(x) ((unsigned long)(ALIGN((x), sizeof(u32))) - \
51 (unsigned long)(x))
52
53#define UART_RX_DMA_BUFFER_SIZE (2048*8)
54
55#define UART_LSR_FIFOE 0x80
56#define UART_LSR_TXFIFO_FULL 0x100
57#define UART_IER_EORD 0x20
58#define UART_MCR_RTS_EN 0x40
59#define UART_MCR_CTS_EN 0x20
60#define UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
61 UART_LSR_PE | UART_LSR_FE)
62
63#define TX_FORCE_PIO 0
64#define RX_FORCE_PIO 0
65
66const int dma_req_sel[] = {
67 TEGRA_DMA_REQ_SEL_UARTA,
68 TEGRA_DMA_REQ_SEL_UARTB,
69 TEGRA_DMA_REQ_SEL_UARTC,
70 TEGRA_DMA_REQ_SEL_UARTD,
71 TEGRA_DMA_REQ_SEL_UARTE,
72};
73
74#define TEGRA_TX_PIO 1
75#define TEGRA_TX_DMA 2
76
77#define TEGRA_UART_MIN_DMA 16
78#define TEGRA_UART_FIFO_SIZE 8
79
80#define TEGRA_UART_CLOSED 0
81#define TEGRA_UART_OPENED 1
82#define TEGRA_UART_CLOCK_OFF 2
83#define TEGRA_UART_SUSPEND 3
84
85/* Tx fifo trigger level setting in tegra uart is in
86 * reverse way then conventional uart */
87#define TEGRA_UART_TX_TRIG_16B 0x00
88#define TEGRA_UART_TX_TRIG_8B 0x10
89#define TEGRA_UART_TX_TRIG_4B 0x20
90#define TEGRA_UART_TX_TRIG_1B 0x30
91
92struct tegra_uart_port {
93 struct uart_port uport;
94 char port_name[32];
95
96 /* Module info */
97 unsigned long size;
98 struct clk *clk;
99 unsigned int baud;
100
101 /* Register shadow */
102 unsigned char fcr_shadow;
103 unsigned char mcr_shadow;
104 unsigned char lcr_shadow;
105 unsigned char ier_shadow;
106 bool use_cts_control;
107 bool rts_active;
108
109 int tx_in_progress;
110 unsigned int tx_bytes;
111
112 dma_addr_t xmit_dma_addr;
113
114 /* TX DMA */
115 struct tegra_dma_req tx_dma_req;
116 struct tegra_dma_channel *tx_dma;
117
118 /* RX DMA */
119 struct tegra_dma_req rx_dma_req;
120 struct tegra_dma_channel *rx_dma;
121
122 bool use_rx_dma;
123 bool use_tx_dma;
124 int uart_state;
125 bool rx_timeout;
126 int rx_in_progress;
127};
128
129static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud);
130static void do_handle_rx_pio(struct tegra_uart_port *t);
131static void do_handle_rx_dma(struct tegra_uart_port *t);
132static void set_rts(struct tegra_uart_port *t, bool active);
133
134static inline u8 uart_readb(struct tegra_uart_port *t, unsigned long reg)
135{
136 u8 val = readb(t->uport.membase + (reg << t->uport.regshift));
137 dev_vdbg(t->uport.dev, "%s: %p %03lx = %02x\n", __func__,
138 t->uport.membase, reg << t->uport.regshift, val);
139 return val;
140}
141
142static inline u32 uart_readl(struct tegra_uart_port *t, unsigned long reg)
143{
144 u32 val = readl(t->uport.membase + (reg << t->uport.regshift));
145 dev_vdbg(t->uport.dev, "%s: %p %03lx = %02x\n", __func__,
146 t->uport.membase, reg << t->uport.regshift, val);
147 return val;
148}
149
150static inline void uart_writeb(struct tegra_uart_port *t, u8 val,
151 unsigned long reg)
152{
153 dev_vdbg(t->uport.dev, "%s: %p %03lx %02x\n",
154 __func__, t->uport.membase, reg << t->uport.regshift, val);
155 writeb(val, t->uport.membase + (reg << t->uport.regshift));
156}
157
158static inline void uart_writel(struct tegra_uart_port *t, u32 val,
159 unsigned long reg)
160{
161 dev_vdbg(t->uport.dev, "%s: %p %03lx %08x\n",
162 __func__, t->uport.membase, reg << t->uport.regshift, val);
163 writel(val, t->uport.membase + (reg << t->uport.regshift));
164}
165
166static void fill_tx_fifo(struct tegra_uart_port *t, int max_bytes)
167{
168 int i;
169 struct circ_buf *xmit = &t->uport.state->xmit;
170#ifndef CONFIG_ARCH_TEGRA_2x_SOC
171 unsigned long lsr;
172#endif
173
174 for (i = 0; i < max_bytes; i++) {
175 BUG_ON(uart_circ_empty(xmit));
176#ifndef CONFIG_ARCH_TEGRA_2x_SOC
177 lsr = uart_readl(t, UART_LSR);
178 if ((lsr & UART_LSR_TXFIFO_FULL))
179 break;
180#endif
181 uart_writeb(t, xmit->buf[xmit->tail], UART_TX);
182 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
183 t->uport.icount.tx++;
184 }
185}
186
187static void tegra_start_pio_tx(struct tegra_uart_port *t, unsigned int bytes)
188{
189 if (bytes > TEGRA_UART_FIFO_SIZE)
190 bytes = TEGRA_UART_FIFO_SIZE;
191
192 t->fcr_shadow &= ~UART_FCR_T_TRIG_11;
193 t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
194 uart_writeb(t, t->fcr_shadow, UART_FCR);
195 t->tx_in_progress = TEGRA_TX_PIO;
196 t->tx_bytes = bytes;
197 t->ier_shadow |= UART_IER_THRI;
198 uart_writeb(t, t->ier_shadow, UART_IER);
199}
200
201static void tegra_start_dma_tx(struct tegra_uart_port *t, unsigned long bytes)
202{
203 struct circ_buf *xmit;
204 xmit = &t->uport.state->xmit;
205
206 dma_sync_single_for_device(t->uport.dev, t->xmit_dma_addr,
207 UART_XMIT_SIZE, DMA_TO_DEVICE);
208
209 t->fcr_shadow &= ~UART_FCR_T_TRIG_11;
210 t->fcr_shadow |= TEGRA_UART_TX_TRIG_4B;
211 uart_writeb(t, t->fcr_shadow, UART_FCR);
212
213 t->tx_bytes = bytes & ~(sizeof(u32)-1);
214 t->tx_dma_req.source_addr = t->xmit_dma_addr + xmit->tail;
215 t->tx_dma_req.size = t->tx_bytes;
216
217 t->tx_in_progress = TEGRA_TX_DMA;
218
219 tegra_dma_enqueue_req(t->tx_dma, &t->tx_dma_req);
220}
221
222/* Called with u->lock taken */
223static void tegra_start_next_tx(struct tegra_uart_port *t)
224{
225 unsigned long tail;
226 unsigned long count;
227
228 struct circ_buf *xmit;
229
230 xmit = &t->uport.state->xmit;
231 tail = (unsigned long)&xmit->buf[xmit->tail];
232 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
233
234
235 dev_vdbg(t->uport.dev, "+%s %lu %d\n", __func__, count,
236 t->tx_in_progress);
237
238 if (count == 0)
239 goto out;
240
241 if (!t->use_tx_dma || count < TEGRA_UART_MIN_DMA)
242 tegra_start_pio_tx(t, count);
243 else if (BYTES_TO_ALIGN(tail) > 0)
244 tegra_start_pio_tx(t, BYTES_TO_ALIGN(tail));
245 else
246 tegra_start_dma_tx(t, count);
247
248out:
249 dev_vdbg(t->uport.dev, "-%s", __func__);
250}
251
252/* Called by serial core driver with u->lock taken. */
253static void tegra_start_tx(struct uart_port *u)
254{
255 struct tegra_uart_port *t;
256 struct circ_buf *xmit;
257
258 t = container_of(u, struct tegra_uart_port, uport);
259 xmit = &u->state->xmit;
260
261 if (!uart_circ_empty(xmit) && !t->tx_in_progress)
262 tegra_start_next_tx(t);
263}
264
265static int tegra_start_dma_rx(struct tegra_uart_port *t)
266{
267 wmb();
268 dma_sync_single_for_device(t->uport.dev, t->rx_dma_req.dest_addr,
269 t->rx_dma_req.size, DMA_TO_DEVICE);
270 if (tegra_dma_enqueue_req(t->rx_dma, &t->rx_dma_req)) {
271 dev_err(t->uport.dev, "Could not enqueue Rx DMA req\n");
272 return -EINVAL;
273 }
274 return 0;
275}
276
277static void tegra_rx_dma_threshold_callback(struct tegra_dma_req *req)
278{
279 struct tegra_uart_port *t = req->dev;
280 struct uart_port *u = &t->uport;
281 unsigned long flags;
282
283 spin_lock_irqsave(&u->lock, flags);
284
285 do_handle_rx_dma(t);
286
287 spin_unlock_irqrestore(&u->lock, flags);
288}
289
290/*
291 * It is expected that the callers take the UART lock when this API is called.
292 *
293 * There are 2 contexts when this function is called:
294 *
295 * 1. DMA ISR - DMA ISR triggers the threshold complete calback, which calls the
296 * dequue API which in-turn calls this callback. UART lock is taken during
297 * the call to the threshold callback.
298 *
299 * 2. UART ISR - UART calls the dequue API which in-turn will call this API.
300 * In this case, UART ISR takes the UART lock.
301 */
302static void tegra_rx_dma_complete_callback(struct tegra_dma_req *req)
303{
304 struct tegra_uart_port *t = req->dev;
305 struct uart_port *u = &t->uport;
306 struct tty_struct *tty = u->state->port.tty;
307 int copied;
308
309 /* If we are here, DMA is stopped */
310
311 dev_dbg(t->uport.dev, "%s: %d %d\n", __func__, req->bytes_transferred,
312 req->status);
313 if (req->bytes_transferred) {
314 t->uport.icount.rx += req->bytes_transferred;
315 dma_sync_single_for_cpu(t->uport.dev, req->dest_addr,
316 req->size, DMA_FROM_DEVICE);
317 copied = tty_insert_flip_string(tty,
318 ((unsigned char *)(req->virt_addr)),
319 req->bytes_transferred);
320 if (copied != req->bytes_transferred) {
321 WARN_ON(1);
322 dev_err(t->uport.dev, "Not able to copy uart data "
323 "to tty layer Req %d and coped %d\n",
324 req->bytes_transferred, copied);
325 }
326 dma_sync_single_for_device(t->uport.dev, req->dest_addr,
327 req->size, DMA_TO_DEVICE);
328 }
329
330 do_handle_rx_pio(t);
331
332 /* Push the read data later in caller place. */
333 if (req->status == -TEGRA_DMA_REQ_ERROR_ABORTED)
334 return;
335
336 spin_unlock(&u->lock);
337 tty_flip_buffer_push(u->state->port.tty);
338 spin_lock(&u->lock);
339}
340
341/* Lock already taken */
342static void do_handle_rx_dma(struct tegra_uart_port *t)
343{
344 struct uart_port *u = &t->uport;
345 if (t->rts_active)
346 set_rts(t, false);
347 tegra_dma_dequeue_req(t->rx_dma, &t->rx_dma_req);
348 tty_flip_buffer_push(u->state->port.tty);
349 /* enqueue the request again */
350 tegra_start_dma_rx(t);
351 if (t->rts_active)
352 set_rts(t, true);
353}
354
355/* Wait for a symbol-time. */
356static void wait_sym_time(struct tegra_uart_port *t, unsigned int syms)
357{
358
359 /* Definitely have a start bit. */
360 unsigned int bits = 1;
361 switch (t->lcr_shadow & 3) {
362 case UART_LCR_WLEN5:
363 bits += 5;
364 break;
365 case UART_LCR_WLEN6:
366 bits += 6;
367 break;
368 case UART_LCR_WLEN7:
369 bits += 7;
370 break;
371 default:
372 bits += 8;
373 break;
374 }
375
376 /* Technically 5 bits gets 1.5 bits of stop... */
377 if (t->lcr_shadow & UART_LCR_STOP)
378 bits += 2;
379 else
380 bits++;
381
382 if (t->lcr_shadow & UART_LCR_PARITY)
383 bits++;
384
385 if (likely(t->baud))
386 udelay(DIV_ROUND_UP(syms * bits * 1000000, t->baud));
387}
388
389/* Flush desired FIFO. */
390static void tegra_fifo_reset(struct tegra_uart_port *t, u8 fcr_bits)
391{
392 unsigned char fcr = t->fcr_shadow;
393#ifdef CONFIG_ARCH_TEGRA_2x_SOC
394 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
395 uart_writeb(t, fcr, UART_FCR);
396#else
397 /*Hw issue: Resetting tx fifo with non-fifo
398 mode to avoid any extra character to be sent*/
399 fcr &= ~UART_FCR_ENABLE_FIFO;
400 uart_writeb(t, fcr, UART_FCR);
401 udelay(60);
402 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
403 uart_writeb(t, fcr, UART_FCR);
404 fcr |= UART_FCR_ENABLE_FIFO;
405 uart_writeb(t, fcr, UART_FCR);
406#endif
407 uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */
408 wait_sym_time(t, 1); /* Wait for the flush to propagate. */
409}
410
411static char do_decode_rx_error(struct tegra_uart_port *t, u8 lsr)
412{
413 char flag = TTY_NORMAL;
414
415 if (unlikely(lsr & UART_LSR_ANY)) {
416 if (lsr & UART_LSR_OE) {
417 /* Overrrun error */
418 flag |= TTY_OVERRUN;
419 t->uport.icount.overrun++;
420 dev_err(t->uport.dev, "Got overrun errors\n");
421 } else if (lsr & UART_LSR_PE) {
422 /* Parity error */
423 flag |= TTY_PARITY;
424 t->uport.icount.parity++;
425 dev_err(t->uport.dev, "Got Parity errors\n");
426 } else if (lsr & UART_LSR_FE) {
427 flag |= TTY_FRAME;
428 t->uport.icount.frame++;
429 dev_err(t->uport.dev, "Got frame errors\n");
430 } else if (lsr & UART_LSR_BI) {
431 dev_err(t->uport.dev, "Got Break\n");
432 t->uport.icount.brk++;
433 /* If FIFO read error without any data, reset Rx FIFO */
434 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
435 tegra_fifo_reset(t, UART_FCR_CLEAR_RCVR);
436 }
437 }
438 return flag;
439}
440
441static void do_handle_rx_pio(struct tegra_uart_port *t)
442{
443 int count = 0;
444 do {
445 char flag = TTY_NORMAL;
446 unsigned char lsr = 0;
447 unsigned char ch;
448
449
450 lsr = uart_readb(t, UART_LSR);
451 if (!(lsr & UART_LSR_DR))
452 break;
453
454 flag = do_decode_rx_error(t, lsr);
455 ch = uart_readb(t, UART_RX);
456 t->uport.icount.rx++;
457 count++;
458
459 if (!uart_handle_sysrq_char(&t->uport, c))
460 uart_insert_char(&t->uport, lsr, UART_LSR_OE, ch, flag);
461 } while (1);
462
463 dev_dbg(t->uport.dev, "PIO received %d bytes\n", count);
464 return;
465}
466
467static void do_handle_modem_signal(struct uart_port *u)
468{
469 unsigned char msr;
470 struct tegra_uart_port *t;
471
472 t = container_of(u, struct tegra_uart_port, uport);
473 msr = uart_readb(t, UART_MSR);
474 if (msr & UART_MSR_CTS)
475 dev_dbg(u->dev, "CTS triggered\n");
476 if (msr & UART_MSR_DSR)
477 dev_dbg(u->dev, "DSR enabled\n");
478 if (msr & UART_MSR_DCD)
479 dev_dbg(u->dev, "CD enabled\n");
480 if (msr & UART_MSR_RI)
481 dev_dbg(u->dev, "RI enabled\n");
482 return;
483}
484
485static void do_handle_tx_pio(struct tegra_uart_port *t)
486{
487 struct circ_buf *xmit = &t->uport.state->xmit;
488
489 fill_tx_fifo(t, t->tx_bytes);
490
491 t->tx_in_progress = 0;
492
493 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
494 uart_write_wakeup(&t->uport);
495
496 tegra_start_next_tx(t);
497 return;
498}
499
500static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req)
501{
502 struct tegra_uart_port *t = req->dev;
503 struct circ_buf *xmit = &t->uport.state->xmit;
504 int count = req->bytes_transferred;
505 unsigned long flags;
506
507 dev_vdbg(t->uport.dev, "%s: %d\n", __func__, count);
508
509 /* Update xmit pointers without lock if dma aborted. */
510 if (req->status == -TEGRA_DMA_REQ_ERROR_ABORTED) {
511 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
512 t->tx_in_progress = 0;
513 return;
514 }
515
516 spin_lock_irqsave(&t->uport.lock, flags);
517 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
518 t->tx_in_progress = 0;
519
520 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
521 uart_write_wakeup(&t->uport);
522
523 tegra_start_next_tx(t);
524
525 spin_unlock_irqrestore(&t->uport.lock, flags);
526}
527
528static irqreturn_t tegra_uart_isr(int irq, void *data)
529{
530 struct tegra_uart_port *t = data;
531 struct uart_port *u = &t->uport;
532 unsigned char iir;
533 unsigned char ier;
534 bool is_rx_int = false;
535 unsigned long flags;
536
537 spin_lock_irqsave(&u->lock, flags);
538 t = container_of(u, struct tegra_uart_port, uport);
539 while (1) {
540 iir = uart_readb(t, UART_IIR);
541 if (iir & UART_IIR_NO_INT) {
542 if (likely(t->use_rx_dma) && is_rx_int) {
543 do_handle_rx_dma(t);
544
545 if (t->rx_in_progress) {
546 ier = t->ier_shadow;
547 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
548 UART_IER_EORD);
549 t->ier_shadow = ier;
550 uart_writeb(t, ier, UART_IER);
551 }
552 }
553 spin_unlock_irqrestore(&u->lock, flags);
554 return IRQ_HANDLED;
555 }
556
557 dev_dbg(u->dev, "tegra_uart_isr iir = 0x%x (%d)\n", iir,
558 (iir >> 1) & 0x7);
559 switch ((iir >> 1) & 0x7) {
560 case 0: /* Modem signal change interrupt */
561 do_handle_modem_signal(u);
562 break;
563 case 1: /* Transmit interrupt only triggered when using PIO */
564 t->ier_shadow &= ~UART_IER_THRI;
565 uart_writeb(t, t->ier_shadow, UART_IER);
566 do_handle_tx_pio(t);
567 break;
568 case 4: /* End of data */
569 case 6: /* Rx timeout */
570 case 2: /* Receive */
571 if (likely(t->use_rx_dma)) {
572 if (!is_rx_int) {
573 is_rx_int = true;
574 /* Disable interrups */
575 ier = t->ier_shadow;
576 ier |= UART_IER_RDI;
577 uart_writeb(t, ier, UART_IER);
578 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
579 UART_IER_RTOIE | UART_IER_EORD);
580 t->ier_shadow = ier;
581 uart_writeb(t, ier, UART_IER);
582 }
583 } else {
584 do_handle_rx_pio(t);
585
586 spin_unlock_irqrestore(&u->lock, flags);
587 tty_flip_buffer_push(u->state->port.tty);
588 spin_lock_irqsave(&u->lock, flags);
589 }
590 break;
591 case 3: /* Receive error */
592 /* FIXME how to handle this? Why do we get here */
593 do_decode_rx_error(t, uart_readb(t, UART_LSR));
594 break;
595 case 5: /* break nothing to handle */
596 case 7: /* break nothing to handle */
597 break;
598 }
599 }
600}
601
602static void tegra_stop_rx(struct uart_port *u)
603{
604 struct tegra_uart_port *t;
605 unsigned char ier;
606
607 t = container_of(u, struct tegra_uart_port, uport);
608
609 if (t->rts_active)
610 set_rts(t, false);
611
612 if (t->rx_in_progress) {
613 wait_sym_time(t, 1); /* wait a character interval */
614
615 ier = t->ier_shadow;
616 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
617 UART_IER_EORD);
618 t->ier_shadow = ier;
619 uart_writeb(t, ier, UART_IER);
620 t->rx_in_progress = 0;
621
622 if (t->use_rx_dma && t->rx_dma)
623 tegra_dma_dequeue_req(t->rx_dma, &t->rx_dma_req);
624 else
625 do_handle_rx_pio(t);
626
627 tty_flip_buffer_push(u->state->port.tty);
628 }
629
630 return;
631}
632
633static void tegra_uart_hw_deinit(struct tegra_uart_port *t)
634{
635 unsigned long flags;
636 unsigned long char_time = DIV_ROUND_UP(10000000, t->baud);
637 unsigned long fifo_empty_time = t->uport.fifosize * char_time;
638 unsigned long wait_time;
639 unsigned char lsr;
640 unsigned char msr;
641 unsigned char mcr;
642
643 /* Disable interrupts */
644 uart_writeb(t, 0, UART_IER);
645
646 lsr = uart_readb(t, UART_LSR);
647 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
648 msr = uart_readb(t, UART_MSR);
649 mcr = uart_readb(t, UART_MCR);
650 if ((mcr & UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
651 dev_err(t->uport.dev, "%s: Tx fifo not empty and "
652 "slave disabled CTS, Waiting for slave to"
653 " be ready\n", __func__);
654
655 /* Wait for Tx fifo to be empty */
656 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
657 wait_time = min(fifo_empty_time, 100lu);
658 udelay(wait_time);
659 fifo_empty_time -= wait_time;
660 if (!fifo_empty_time) {
661 msr = uart_readb(t, UART_MSR);
662 mcr = uart_readb(t, UART_MCR);
663 if ((mcr & UART_MCR_CTS_EN) &&
664 (msr & UART_MSR_CTS))
665 dev_err(t->uport.dev, "%s: Slave is "
666 "still not ready!\n", __func__);
667 break;
668 }
669 lsr = uart_readb(t, UART_LSR);
670 }
671 }
672
673 spin_lock_irqsave(&t->uport.lock, flags);
674
675 /* Reset the Rx and Tx FIFOs */
676 tegra_fifo_reset(t, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
677
678 t->baud = 0;
679 t->uart_state = TEGRA_UART_CLOSED;
680
681 spin_unlock_irqrestore(&t->uport.lock, flags);
682
683 clk_disable(t->clk);
684}
685
686static void tegra_uart_free_rx_dma_buffer(struct tegra_uart_port *t)
687{
688 if (likely(t->rx_dma_req.dest_addr))
689 dma_free_coherent(t->uport.dev, t->rx_dma_req.size,
690 t->rx_dma_req.virt_addr, t->rx_dma_req.dest_addr);
691 t->rx_dma_req.dest_addr = 0;
692 t->rx_dma_req.virt_addr = NULL;
693}
694
695static void tegra_uart_free_rx_dma(struct tegra_uart_port *t)
696{
697 if (!t->use_rx_dma)
698 return;
699
700 tegra_dma_free_channel(t->rx_dma);
701 t->rx_dma = NULL;
702 t->use_rx_dma = false;
703}
704
705static int tegra_uart_hw_init(struct tegra_uart_port *t)
706{
707 unsigned char ier;
708
709 dev_vdbg(t->uport.dev, "+tegra_uart_hw_init\n");
710
711 t->fcr_shadow = 0;
712 t->mcr_shadow = 0;
713 t->lcr_shadow = 0;
714 t->ier_shadow = 0;
715 t->baud = 0;
716
717 clk_enable(t->clk);
718
719 /* Reset the UART controller to clear all previous status.*/
720 tegra_periph_reset_assert(t->clk);
721 udelay(100);
722 tegra_periph_reset_deassert(t->clk);
723 udelay(100);
724
725 t->rx_in_progress = 0;
726
727 /*
728 * Set the trigger level
729 *
730 * For PIO mode:
731 *
732 * For receive, this will interrupt the CPU after that many number of
733 * bytes are received, for the remaining bytes the receive timeout
734 * interrupt is received.
735 *
736 * Rx high watermark is set to 4.
737 *
738 * For transmit, if the trasnmit interrupt is enabled, this will
739 * interrupt the CPU when the number of entries in the FIFO reaches the
740 * low watermark.
741 *
742 * Tx low watermark is set to 8.
743 *
744 * For DMA mode:
745 *
746 * Set the Tx trigger to 4. This should match the DMA burst size that
747 * programmed in the DMA registers.
748 */
749 t->fcr_shadow = UART_FCR_ENABLE_FIFO;
750 t->fcr_shadow |= UART_FCR_R_TRIG_01;
751 t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
752 uart_writeb(t, t->fcr_shadow, UART_FCR);
753
754 if (t->use_rx_dma) {
755 /*
756 * Initialize the UART for a simple default configuration
757 * so that the receive DMA buffer may be enqueued */
758 t->lcr_shadow = 3; /* no parity, stop, 8 data bits */
759 tegra_set_baudrate(t, 115200);
760 t->fcr_shadow |= UART_FCR_DMA_SELECT;
761 uart_writeb(t, t->fcr_shadow, UART_FCR);
762 if (tegra_start_dma_rx(t)) {
763 dev_err(t->uport.dev, "Rx DMA enqueue failed\n");
764 tegra_uart_free_rx_dma(t);
765 t->fcr_shadow &= ~UART_FCR_DMA_SELECT;
766 uart_writeb(t, t->fcr_shadow, UART_FCR);
767 }
768 } else {
769 uart_writeb(t, t->fcr_shadow, UART_FCR);
770 }
771
772 t->rx_in_progress = 1;
773
774 /*
775 * Enable IE_RXS for the receive status interrupts like line errros.
776 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
777 *
778 * If using DMA mode, enable EORD instead of receive interrupt which
779 * will interrupt after the UART is done with the receive instead of
780 * the interrupt when the FIFO "threshold" is reached.
781 *
782 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
783 * the DATA is sitting in the FIFO and couldn't be transferred to the
784 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
785 * triggered when there is a pause of the incomming data stream for 4
786 * characters long.
787 *
788 * For pauses in the data which is not aligned to 4 bytes, we get
789 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
790 * then the EORD.
791 *
792 * Don't get confused, believe in the magic of nvidia hw...:-)
793 */
794 ier = 0;
795 ier |= UART_IER_RLSI | UART_IER_RTOIE;
796 if (t->use_rx_dma)
797 ier |= UART_IER_EORD;
798 else
799 ier |= UART_IER_RDI;
800 t->ier_shadow = ier;
801 uart_writeb(t, ier, UART_IER);
802
803 t->uart_state = TEGRA_UART_OPENED;
804 dev_vdbg(t->uport.dev, "-tegra_uart_hw_init\n");
805 return 0;
806}
807
808static int tegra_uart_init_rx_dma_buffer(struct tegra_uart_port *t)
809{
810 dma_addr_t rx_dma_phys;
811 void *rx_dma_virt;
812
813 t->rx_dma_req.size = UART_RX_DMA_BUFFER_SIZE;
814 rx_dma_virt = dma_alloc_coherent(t->uport.dev,
815 t->rx_dma_req.size, &rx_dma_phys, GFP_KERNEL);
816 if (!rx_dma_virt) {
817 dev_err(t->uport.dev, "DMA buffers allocate failed\n");
818 return -ENOMEM;
819 }
820 t->rx_dma_req.dest_addr = rx_dma_phys;
821 t->rx_dma_req.virt_addr = rx_dma_virt;
822
823 t->rx_dma_req.source_addr = (unsigned long)t->uport.mapbase;
824 t->rx_dma_req.source_wrap = 4;
825 t->rx_dma_req.dest_wrap = 0;
826 t->rx_dma_req.to_memory = 1;
827 t->rx_dma_req.source_bus_width = 8;
828 t->rx_dma_req.dest_bus_width = 32;
829 t->rx_dma_req.req_sel = dma_req_sel[t->uport.line];
830 t->rx_dma_req.complete = tegra_rx_dma_complete_callback;
831 t->rx_dma_req.threshold = tegra_rx_dma_threshold_callback;
832 t->rx_dma_req.dev = t;
833
834 return 0;
835}
836
837static int tegra_uart_init_rx_dma(struct tegra_uart_port *t)
838{
839 t->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_CONTINUOUS,
840 "uart_rx_%d", t->uport.line);
841 if (!t->rx_dma) {
842 dev_err(t->uport.dev, "%s: failed to allocate RX DMA.\n",
843 __func__);
844 return -ENODEV;
845 }
846 return 0;
847}
848
849static int tegra_startup(struct uart_port *u)
850{
851 struct tegra_uart_port *t = container_of(u,
852 struct tegra_uart_port, uport);
853 int ret = 0;
854 struct tegra_uart_platform_data *pdata;
855
856 t = container_of(u, struct tegra_uart_port, uport);
857 sprintf(t->port_name, "tegra_uart_%d", u->line);
858
859 t->use_tx_dma = false;
860 if (!TX_FORCE_PIO) {
861 t->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT,
862 "uart_tx_%d", u->line);
863 if (t->tx_dma)
864 t->use_tx_dma = true;
865 else
866 pr_err("%s: failed to allocate TX DMA.\n", __func__);
867 }
868 if (t->use_tx_dma) {
869 t->tx_dma_req.instance = u->line;
870 t->tx_dma_req.complete = tegra_tx_dma_complete_callback;
871 t->tx_dma_req.to_memory = 0;
872
873 t->tx_dma_req.dest_addr = (unsigned long)t->uport.mapbase;
874 t->tx_dma_req.dest_wrap = 4;
875 t->tx_dma_req.source_wrap = 0;
876 t->tx_dma_req.source_bus_width = 32;
877 t->tx_dma_req.dest_bus_width = 8;
878 t->tx_dma_req.req_sel = dma_req_sel[t->uport.line];
879 t->tx_dma_req.dev = t;
880 t->tx_dma_req.size = 0;
881 t->xmit_dma_addr = dma_map_single(t->uport.dev,
882 t->uport.state->xmit.buf, UART_XMIT_SIZE,
883 DMA_TO_DEVICE);
884 }
885 t->tx_in_progress = 0;
886
887 t->use_rx_dma = false;
888 if (!RX_FORCE_PIO && t->rx_dma_req.virt_addr) {
889 if (!tegra_uart_init_rx_dma(t))
890 t->use_rx_dma = true;
891 }
892
893 ret = tegra_uart_hw_init(t);
894 if (ret)
895 goto fail;
896
897 pdata = u->dev->platform_data;
898 if (pdata->is_loopback)
899 t->mcr_shadow |= UART_MCR_LOOP;
900
901 dev_dbg(u->dev, "Requesting IRQ %d\n", u->irq);
902 ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED,
903 t->port_name, t);
904 if (ret) {
905 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
906 goto fail;
907 }
908
909 dev_dbg(u->dev, "Started UART port %d\n", u->line);
910 return 0;
911fail:
912 dev_err(u->dev, "Tegra UART startup failed\n");
913 return ret;
914}
915
916static void tegra_shutdown(struct uart_port *u)
917{
918 struct tegra_uart_port *t;
919
920 t = container_of(u, struct tegra_uart_port, uport);
921 dev_vdbg(u->dev, "+tegra_shutdown\n");
922
923 tegra_uart_hw_deinit(t);
924
925 t->rx_in_progress = 0;
926 t->tx_in_progress = 0;
927
928 tegra_uart_free_rx_dma(t);
929 if (t->use_tx_dma) {
930 tegra_dma_free_channel(t->tx_dma);
931 t->tx_dma = NULL;
932 t->use_tx_dma = false;
933 dma_unmap_single(t->uport.dev, t->xmit_dma_addr, UART_XMIT_SIZE,
934 DMA_TO_DEVICE);
935 t->xmit_dma_addr = 0;
936 }
937
938 free_irq(u->irq, t);
939 dev_vdbg(u->dev, "-tegra_shutdown\n");
940}
941
942static void tegra_wake_peer(struct uart_port *u)
943{
944 struct tegra_uart_platform_data *pdata = u->dev->platform_data;
945
946 if (pdata && pdata->wake_peer)
947 pdata->wake_peer(u);
948}
949
950static unsigned int tegra_get_mctrl(struct uart_port *u)
951{
952 /*
953 * RI - Ring detector is active
954 * CD/DCD/CAR - Carrier detect is always active. For some reason
955 * linux has different names for carrier detect.
956 * DSR - Data Set ready is active as the hardware doesn't support it.
957 * Don't know if the linux support this yet?
958 * CTS - Clear to send. Always set to active, as the hardware handles
959 * CTS automatically.
960 */
961 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
962}
963
964static void set_rts(struct tegra_uart_port *t, bool active)
965{
966 unsigned char mcr;
967 mcr = t->mcr_shadow;
968 if (active)
969 mcr |= UART_MCR_RTS_EN;
970 else
971 mcr &= ~UART_MCR_RTS_EN;
972 if (mcr != t->mcr_shadow) {
973 uart_writeb(t, mcr, UART_MCR);
974 t->mcr_shadow = mcr;
975 }
976 return;
977}
978
979static void set_dtr(struct tegra_uart_port *t, bool active)
980{
981 unsigned char mcr;
982 mcr = t->mcr_shadow;
983 if (active)
984 mcr |= UART_MCR_DTR;
985 else
986 mcr &= ~UART_MCR_DTR;
987 if (mcr != t->mcr_shadow) {
988 uart_writeb(t, mcr, UART_MCR);
989 t->mcr_shadow = mcr;
990 }
991 return;
992}
993
994static void tegra_set_mctrl(struct uart_port *u, unsigned int mctrl)
995{
996 unsigned char mcr;
997 struct tegra_uart_port *t;
998
999 dev_dbg(u->dev, "tegra_set_mctrl called with %d\n", mctrl);
1000 t = container_of(u, struct tegra_uart_port, uport);
1001
1002 mcr = t->mcr_shadow;
1003 if (mctrl & TIOCM_RTS) {
1004 t->rts_active = true;
1005 set_rts(t, true);
1006 } else {
1007 t->rts_active = false;
1008 set_rts(t, false);
1009 }
1010
1011 if (mctrl & TIOCM_DTR)
1012 set_dtr(t, true);
1013 else
1014 set_dtr(t, false);
1015 return;
1016}
1017
1018static void tegra_break_ctl(struct uart_port *u, int break_ctl)
1019{
1020 struct tegra_uart_port *t;
1021 unsigned char lcr;
1022
1023 t = container_of(u, struct tegra_uart_port, uport);
1024 lcr = t->lcr_shadow;
1025 if (break_ctl)
1026 lcr |= UART_LCR_SBC;
1027 else
1028 lcr &= ~UART_LCR_SBC;
1029 uart_writeb(t, lcr, UART_LCR);
1030 t->lcr_shadow = lcr;
1031}
1032
1033static int tegra_request_port(struct uart_port *u)
1034{
1035 return 0;
1036}
1037
1038static void tegra_release_port(struct uart_port *u)
1039{
1040 /* Nothing to do here */
1041}
1042
1043static unsigned int tegra_tx_empty(struct uart_port *u)
1044{
1045 struct tegra_uart_port *t;
1046 unsigned int ret = 0;
1047 unsigned long flags;
1048 unsigned char lsr;
1049
1050 t = container_of(u, struct tegra_uart_port, uport);
1051 dev_vdbg(u->dev, "+tegra_tx_empty\n");
1052
1053 spin_lock_irqsave(&u->lock, flags);
1054 if (!t->tx_in_progress) {
1055 lsr = uart_readb(t, UART_LSR);
1056 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
1057 ret = TIOCSER_TEMT;
1058 }
1059 spin_unlock_irqrestore(&u->lock, flags);
1060
1061 dev_vdbg(u->dev, "-tegra_tx_empty\n");
1062 return ret;
1063}
1064
1065static void tegra_stop_tx(struct uart_port *u)
1066{
1067 struct tegra_uart_port *t;
1068
1069 t = container_of(u, struct tegra_uart_port, uport);
1070
1071 if (t->use_tx_dma)
1072 tegra_dma_dequeue_req(t->tx_dma, &t->tx_dma_req);
1073
1074 return;
1075}
1076
1077static void tegra_enable_ms(struct uart_port *u)
1078{
1079}
1080
1081#ifndef CONFIG_ARCH_TEGRA_2x_SOC
1082static int clk_div71_get_divider(unsigned long parent_rate,
1083 unsigned long rate)
1084{
1085 s64 divider_u71 = parent_rate;
1086 if (!rate)
1087 return -EINVAL;
1088
1089 divider_u71 *= 2;
1090 divider_u71 += rate - 1;
1091 do_div(divider_u71, rate);
1092
1093 if ((divider_u71 - 2) < 0)
1094 return 0;
1095
1096 if ((divider_u71 - 2) > 255)
1097 return -EINVAL;
1098
1099 return divider_u71 - 2;
1100}
1101#endif
1102
1103static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
1104{
1105 s64 divider_u16;
1106
1107 divider_u16 = parent_rate;
1108 if (!rate)
1109 return -EINVAL;
1110 divider_u16 += rate - 1;
1111 do_div(divider_u16, rate);
1112
1113 if (divider_u16 > 0xFFFF)
1114 return -EINVAL;
1115
1116 return divider_u16;
1117}
1118
1119static unsigned long find_best_clock_source(struct tegra_uart_port *t,
1120 unsigned long rate)
1121{
1122 struct uart_port *u = &t->uport;
1123 struct tegra_uart_platform_data *pdata;
1124 int i;
1125 int divider;
1126 unsigned long parent_rate;
1127 unsigned long new_rate;
1128 unsigned long err_rate;
1129 unsigned int fin_err = rate;
1130 unsigned long fin_rate = rate;
1131 int final_index = -1;
1132 int count;
1133 unsigned long error_2perc;
1134
1135 pdata = u->dev->platform_data;
1136 if (!pdata || !pdata->parent_clk_count)
1137 return fin_rate;
1138
1139 error_2perc = (rate / 50);
1140
1141 for (count = 0; count < pdata->parent_clk_count; ++count) {
1142 parent_rate = pdata->parent_clk_list[count].fixed_clk_rate;
1143
1144 if (parent_rate < rate)
1145 continue;
1146
1147#ifndef CONFIG_ARCH_TEGRA_2x_SOC
1148 divider = clk_div71_get_divider(parent_rate, rate);
1149
1150 /* Get the best divider around calculated value */
1151 if (divider > 2) {
1152 for (i = divider - 2; i < (divider + 2); ++i) {
1153 new_rate = ((parent_rate << 1) + i + 1) /
1154 (i + 2);
1155 err_rate = abs(new_rate - rate);
1156 if (err_rate < fin_err) {
1157 final_index = count;
1158 fin_err = err_rate;
1159 fin_rate = new_rate;
1160 if (fin_err < error_2perc)
1161 break;
1162 }
1163 }
1164 if (fin_err < error_2perc)
1165 break;
1166 }
1167#endif
1168 /* Get the divisor by uart controller dll/dlm */
1169 divider = clk_div16_get_divider(parent_rate, rate);
1170
1171 /* Get the best divider around calculated value */
1172 if (divider > 2) {
1173 for (i = divider - 2; i < (divider + 2); ++i) {
1174 new_rate = parent_rate/i;
1175 err_rate = abs(new_rate - rate);
1176 if (err_rate < fin_err) {
1177 final_index = count;
1178 fin_err = err_rate;
1179 fin_rate = parent_rate;
1180 if (fin_err < error_2perc)
1181 break;
1182 }
1183 }
1184 if (fin_err < error_2perc)
1185 break;
1186 }
1187 }
1188
1189 if (final_index >= 0) {
1190 dev_info(t->uport.dev, "Setting clk_src %s\n",
1191 pdata->parent_clk_list[final_index].name);
1192 clk_set_parent(t->clk,
1193 pdata->parent_clk_list[final_index].parent_clk);
1194 }
1195 return fin_rate;
1196}
1197
1198#define UART_CLOCK_ACCURACY 5
1199static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud)
1200{
1201 unsigned long rate;
1202 unsigned int divisor;
1203 unsigned char lcr;
1204 unsigned int baud_actual;
1205 unsigned int baud_delta;
1206 unsigned long best_rate;
1207
1208 if (t->baud == baud)
1209 return;
1210
1211 rate = baud * 16;
1212 best_rate = find_best_clock_source(t, rate);
1213 clk_set_rate(t->clk, best_rate);
1214
1215 rate = clk_get_rate(t->clk);
1216
1217 divisor = rate;
1218 do_div(divisor, 16);
1219 divisor += baud/2;
1220 do_div(divisor, baud);
1221
1222 /* The allowable baudrate error from desired baudrate is 5% */
1223 baud_actual = divisor ? rate / (16 * divisor) : 0;
1224 baud_delta = abs(baud_actual - baud);
1225 if (WARN_ON(baud_delta * 20 > baud)) {
1226 dev_err(t->uport.dev, "requested baud %u, actual %u\n",
1227 baud, baud_actual);
1228 }
1229
1230 lcr = t->lcr_shadow;
1231 lcr |= UART_LCR_DLAB;
1232 uart_writeb(t, lcr, UART_LCR);
1233
1234 uart_writel(t, divisor & 0xFF, UART_TX);
1235 uart_writel(t, ((divisor >> 8) & 0xFF), UART_IER);
1236
1237 lcr &= ~UART_LCR_DLAB;
1238 uart_writeb(t, lcr, UART_LCR);
1239 uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */
1240
1241 t->baud = baud;
1242 wait_sym_time(t, 2); /* wait two character intervals at new rate */
1243 dev_dbg(t->uport.dev, "Baud %u clock freq %lu and divisor of %u\n",
1244 baud, rate, divisor);
1245}
1246
1247static void tegra_set_termios(struct uart_port *u, struct ktermios *termios,
1248 struct ktermios *oldtermios)
1249{
1250 struct tegra_uart_port *t;
1251 unsigned int baud;
1252 unsigned long flags;
1253 unsigned int lcr;
1254 unsigned int c_cflag = termios->c_cflag;
1255 unsigned char mcr;
1256
1257 t = container_of(u, struct tegra_uart_port, uport);
1258 dev_vdbg(t->uport.dev, "+tegra_set_termios\n");
1259
1260 spin_lock_irqsave(&u->lock, flags);
1261
1262 /* Changing configuration, it is safe to stop any rx now */
1263 if (t->rts_active)
1264 set_rts(t, false);
1265
1266 /* Parity */
1267 lcr = t->lcr_shadow;
1268 lcr &= ~UART_LCR_PARITY;
1269 if (PARENB == (c_cflag & PARENB)) {
1270 if (CMSPAR == (c_cflag & CMSPAR)) {
1271 /* FIXME What is space parity? */
1272 /* data |= SPACE_PARITY; */
1273 } else if (c_cflag & PARODD) {
1274 lcr |= UART_LCR_PARITY;
1275 lcr &= ~UART_LCR_EPAR;
1276 lcr &= ~UART_LCR_SPAR;
1277 } else {
1278 lcr |= UART_LCR_PARITY;
1279 lcr |= UART_LCR_EPAR;
1280 lcr &= ~UART_LCR_SPAR;
1281 }
1282 }
1283
1284 lcr &= ~UART_LCR_WLEN8;
1285 switch (c_cflag & CSIZE) {
1286 case CS5:
1287 lcr |= UART_LCR_WLEN5;
1288 break;
1289 case CS6:
1290 lcr |= UART_LCR_WLEN6;
1291 break;
1292 case CS7:
1293 lcr |= UART_LCR_WLEN7;
1294 break;
1295 default:
1296 lcr |= UART_LCR_WLEN8;
1297 break;
1298 }
1299
1300 /* Stop bits */
1301 if (termios->c_cflag & CSTOPB)
1302 lcr |= UART_LCR_STOP;
1303 else
1304 lcr &= ~UART_LCR_STOP;
1305
1306 uart_writeb(t, lcr, UART_LCR);
1307 t->lcr_shadow = lcr;
1308
1309 /* Baud rate. */
1310 baud = uart_get_baud_rate(u, termios, oldtermios, 200, 4000000);
1311 spin_unlock_irqrestore(&u->lock, flags);
1312 tegra_set_baudrate(t, baud);
1313 spin_lock_irqsave(&u->lock, flags);
1314
1315 /* Flow control */
1316 if (termios->c_cflag & CRTSCTS) {
1317 mcr = t->mcr_shadow;
1318 mcr |= UART_MCR_CTS_EN;
1319 mcr &= ~UART_MCR_RTS_EN;
1320 t->mcr_shadow = mcr;
1321 uart_writeb(t, mcr, UART_MCR);
1322 t->use_cts_control = true;
1323 /* if top layer has asked to set rts active then do so here */
1324 if (t->rts_active)
1325 set_rts(t, true);
1326 } else {
1327 mcr = t->mcr_shadow;
1328 mcr &= ~UART_MCR_CTS_EN;
1329 mcr &= ~UART_MCR_RTS_EN;
1330 t->mcr_shadow = mcr;
1331 uart_writeb(t, mcr, UART_MCR);
1332 t->use_cts_control = false;
1333 }
1334
1335 /* update the port timeout based on new settings */
1336 uart_update_timeout(u, termios->c_cflag, baud);
1337
1338 spin_unlock_irqrestore(&u->lock, flags);
1339 dev_vdbg(t->uport.dev, "-tegra_set_termios\n");
1340 return;
1341}
1342
1343/*
1344 * Flush any TX data submitted for DMA and PIO. Called when the
1345 * TX circular buffer is reset.
1346 */
1347static void tegra_flush_buffer(struct uart_port *u)
1348{
1349 struct tegra_uart_port *t;
1350
1351 dev_vdbg(u->dev, "%s called", __func__);
1352
1353 t = container_of(u, struct tegra_uart_port, uport);
1354
1355 t->tx_bytes = 0;
1356
1357 if (t->use_tx_dma) {
1358 tegra_dma_dequeue_req(t->tx_dma, &t->tx_dma_req);
1359 t->tx_dma_req.size = 0;
1360 }
1361 return;
1362}
1363
1364
1365static void tegra_pm(struct uart_port *u, unsigned int state,
1366 unsigned int oldstate)
1367{
1368
1369}
1370
1371static const char *tegra_type(struct uart_port *u)
1372{
1373 return TEGRA_UART_TYPE;
1374}
1375
1376static struct uart_ops tegra_uart_ops = {
1377 .tx_empty = tegra_tx_empty,
1378 .set_mctrl = tegra_set_mctrl,
1379 .get_mctrl = tegra_get_mctrl,
1380 .stop_tx = tegra_stop_tx,
1381 .start_tx = tegra_start_tx,
1382 .stop_rx = tegra_stop_rx,
1383 .flush_buffer = tegra_flush_buffer,
1384 .enable_ms = tegra_enable_ms,
1385 .break_ctl = tegra_break_ctl,
1386 .startup = tegra_startup,
1387 .shutdown = tegra_shutdown,
1388 .wake_peer = tegra_wake_peer,
1389 .set_termios = tegra_set_termios,
1390 .pm = tegra_pm,
1391 .type = tegra_type,
1392 .request_port = tegra_request_port,
1393 .release_port = tegra_release_port,
1394};
1395
1396static struct uart_driver tegra_uart_driver = {
1397 .owner = THIS_MODULE,
1398 .driver_name = "tegra_uart",
1399 .dev_name = "ttyHS",
1400 .cons = 0,
1401 .nr = 5,
1402};
1403
1404static int __init tegra_uart_probe(struct platform_device *pdev)
1405{
1406 struct tegra_uart_port *t;
1407 struct uart_port *u;
1408 struct resource *resource;
1409 int ret;
1410 char name[64];
1411 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr) {
1412 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1413 return -ENODEV;
1414 }
1415
1416 t = kzalloc(sizeof(struct tegra_uart_port), GFP_KERNEL);
1417 if (!t) {
1418 pr_err("%s: Failed to allocate memory\n", __func__);
1419 return -ENOMEM;
1420 }
1421 u = &t->uport;
1422 u->dev = &pdev->dev;
1423 platform_set_drvdata(pdev, u);
1424 u->line = pdev->id;
1425 u->ops = &tegra_uart_ops;
1426 u->type = PORT_TEGRA;
1427 u->fifosize = 32;
1428
1429 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1430 if (unlikely(!resource)) {
1431 ret = -ENXIO;
1432 goto fail;
1433 }
1434
1435 u->mapbase = resource->start;
1436 u->membase = IO_ADDRESS(u->mapbase);
1437 if (unlikely(!u->membase)) {
1438 ret = -ENOMEM;
1439 goto fail;
1440 }
1441 u->iotype = UPIO_MEM32;
1442
1443 u->irq = platform_get_irq(pdev, 0);
1444 if (unlikely(u->irq < 0)) {
1445 ret = -ENXIO;
1446 goto fail;
1447 }
1448
1449 u->regshift = 2;
1450
1451 t->clk = clk_get(&pdev->dev, NULL);
1452 if (IS_ERR_OR_NULL(t->clk)) {
1453 dev_err(&pdev->dev, "Couldn't get the clock\n");
1454 ret = -ENODEV;
1455 goto fail;
1456 }
1457
1458 ret = uart_add_one_port(&tegra_uart_driver, u);
1459 if (ret) {
1460 pr_err("%s: Failed(%d) to add uart port %s%d\n",
1461 __func__, ret, tegra_uart_driver.dev_name, u->line);
1462 goto fail;
1463 }
1464
1465 snprintf(name, sizeof(name), "tegra_hsuart_%d", u->line);
1466 pr_info("Registered UART port %s%d\n",
1467 tegra_uart_driver.dev_name, u->line);
1468 t->uart_state = TEGRA_UART_CLOSED;
1469
1470 if (!RX_FORCE_PIO) {
1471 ret = tegra_uart_init_rx_dma_buffer(t);
1472 if (ret < 0) {
1473 pr_err("%s: Failed(%d) to allocate rx dma buffer "
1474 "%s%d\n", __func__, ret,
1475 tegra_uart_driver.dev_name, u->line);
1476 goto rx_dma_buff_fail;
1477 }
1478 }
1479 return ret;
1480
1481rx_dma_buff_fail:
1482 uart_remove_one_port(&tegra_uart_driver, u);
1483fail:
1484 if (t->clk)
1485 clk_put(t->clk);
1486 platform_set_drvdata(pdev, NULL);
1487 kfree(t);
1488 return ret;
1489}
1490
1491static int __devexit tegra_uart_remove(struct platform_device *pdev)
1492{
1493 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1494 struct uart_port *u;
1495
1496 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1497 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1498
1499 u = &t->uport;
1500 uart_remove_one_port(&tegra_uart_driver, u);
1501
1502 tegra_uart_free_rx_dma_buffer(t);
1503
1504 platform_set_drvdata(pdev, NULL);
1505
1506 pr_info("Unregistered UART port %s%d\n",
1507 tegra_uart_driver.dev_name, u->line);
1508 kfree(t);
1509 return 0;
1510}
1511
1512static int tegra_uart_suspend(struct platform_device *pdev, pm_message_t state)
1513{
1514 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1515 struct uart_port *u;
1516
1517 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1518 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1519
1520 u = &t->uport;
1521 dev_dbg(t->uport.dev, "tegra_uart_suspend called\n");
1522
1523 /* enable clock before calling suspend so that controller
1524 register can be accessible */
1525 if (t->uart_state == TEGRA_UART_CLOCK_OFF) {
1526 clk_enable(t->clk);
1527 t->uart_state = TEGRA_UART_OPENED;
1528 }
1529
1530 uart_suspend_port(&tegra_uart_driver, u);
1531 t->uart_state = TEGRA_UART_SUSPEND;
1532
1533 return 0;
1534}
1535
1536static int tegra_uart_resume(struct platform_device *pdev)
1537{
1538 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1539 struct uart_port *u;
1540
1541 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1542 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1543
1544 u = &t->uport;
1545 dev_dbg(t->uport.dev, "tegra_uart_resume called\n");
1546
1547 if (t->uart_state == TEGRA_UART_SUSPEND)
1548 uart_resume_port(&tegra_uart_driver, u);
1549 return 0;
1550}
1551
1552/* Switch off the clock of the uart controller. */
1553void tegra_uart_request_clock_off(struct uart_port *uport)
1554{
1555 unsigned long flags;
1556 struct tegra_uart_port *t;
1557 bool is_clk_disable = false;
1558
1559 if (IS_ERR_OR_NULL(uport))
1560 BUG();
1561
1562 dev_vdbg(uport->dev, "tegra_uart_request_clock_off");
1563
1564 t = container_of(uport, struct tegra_uart_port, uport);
1565 spin_lock_irqsave(&uport->lock, flags);
1566 if (t->uart_state == TEGRA_UART_OPENED) {
1567 is_clk_disable = true;
1568 t->uart_state = TEGRA_UART_CLOCK_OFF;
1569 }
1570 spin_unlock_irqrestore(&uport->lock, flags);
1571
1572 if (is_clk_disable)
1573 clk_disable(t->clk);
1574
1575 return;
1576}
1577
1578/* Switch on the clock of the uart controller */
1579void tegra_uart_request_clock_on(struct uart_port *uport)
1580{
1581 unsigned long flags;
1582 struct tegra_uart_port *t;
1583 bool is_clk_enable = false;
1584
1585 if (IS_ERR_OR_NULL(uport))
1586 BUG();
1587
1588 t = container_of(uport, struct tegra_uart_port, uport);
1589 spin_lock_irqsave(&uport->lock, flags);
1590 if (t->uart_state == TEGRA_UART_CLOCK_OFF) {
1591 is_clk_enable = true;
1592 t->uart_state = TEGRA_UART_OPENED;
1593 }
1594 spin_unlock_irqrestore(&uport->lock, flags);
1595
1596 if (is_clk_enable)
1597 clk_enable(t->clk);
1598
1599 return;
1600}
1601
1602/* Set the modem control signals state of uart controller. */
1603void tegra_uart_set_mctrl(struct uart_port *uport, unsigned int mctrl)
1604{
1605 unsigned long flags;
1606 struct tegra_uart_port *t;
1607
1608 t = container_of(uport, struct tegra_uart_port, uport);
1609 if (t->uart_state != TEGRA_UART_OPENED) {
1610 dev_err(t->uport.dev, "Uart is in invalid state\n");
1611 return;
1612 }
1613
1614 spin_lock_irqsave(&uport->lock, flags);
1615 if (mctrl & TIOCM_RTS) {
1616 t->rts_active = true;
1617 set_rts(t, true);
1618 } else {
1619 t->rts_active = false;
1620 set_rts(t, false);
1621 }
1622
1623 if (mctrl & TIOCM_DTR)
1624 set_dtr(t, true);
1625 else
1626 set_dtr(t, false);
1627 spin_unlock_irqrestore(&uport->lock, flags);
1628 return;
1629}
1630
1631/*
1632 * Return the status of the transmit fifo whether empty or not.
1633 * Return 0 if tx fifo is not empty.
1634 * Return TIOCSER_TEMT if tx fifo is empty.
1635 */
1636int tegra_uart_is_tx_empty(struct uart_port *uport)
1637{
1638 return tegra_tx_empty(uport);
1639}
1640
1641static struct platform_driver tegra_uart_platform_driver = {
1642 .probe = tegra_uart_probe,
1643 .remove = __devexit_p(tegra_uart_remove),
1644 .suspend = tegra_uart_suspend,
1645 .resume = tegra_uart_resume,
1646 .driver = {
1647 .name = "tegra_uart"
1648 }
1649};
1650
1651static int __init tegra_uart_init(void)
1652{
1653 int ret;
1654
1655 ret = uart_register_driver(&tegra_uart_driver);
1656 if (unlikely(ret)) {
1657 pr_err("Could not register %s driver\n",
1658 tegra_uart_driver.driver_name);
1659 return ret;
1660 }
1661
1662 ret = platform_driver_register(&tegra_uart_platform_driver);
1663 if (unlikely(ret)) {
1664 pr_err("Could not register the UART platfrom driver\n");
1665 uart_unregister_driver(&tegra_uart_driver);
1666 return ret;
1667 }
1668
1669 pr_info("Initialized tegra uart driver\n");
1670 return 0;
1671}
1672
1673static void __exit tegra_uart_exit(void)
1674{
1675 pr_info("Unloading tegra uart driver\n");
1676 platform_driver_unregister(&tegra_uart_platform_driver);
1677 uart_unregister_driver(&tegra_uart_driver);
1678}
1679
1680module_init(tegra_uart_init);
1681module_exit(tegra_uart_exit);
1682MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 02:54:18 -0400