diff options
Diffstat (limited to 'drivers/tty/serial/8250_pci.c')
-rw-r--r-- | drivers/tty/serial/8250_pci.c | 4136 |
1 files changed, 4136 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250_pci.c b/drivers/tty/serial/8250_pci.c new file mode 100644 index 00000000000..3abeca2a2a1 --- /dev/null +++ b/drivers/tty/serial/8250_pci.c | |||
@@ -0,0 +1,4136 @@ | |||
1 | /* | ||
2 | * Probe module for 8250/16550-type PCI serial ports. | ||
3 | * | ||
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | ||
5 | * | ||
6 | * Copyright (C) 2001 Russell King, All Rights Reserved. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License. | ||
11 | */ | ||
12 | #include <linux/module.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/pci.h> | ||
15 | #include <linux/string.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/slab.h> | ||
18 | #include <linux/delay.h> | ||
19 | #include <linux/tty.h> | ||
20 | #include <linux/serial_core.h> | ||
21 | #include <linux/8250_pci.h> | ||
22 | #include <linux/bitops.h> | ||
23 | |||
24 | #include <asm/byteorder.h> | ||
25 | #include <asm/io.h> | ||
26 | |||
27 | #include "8250.h" | ||
28 | |||
29 | #undef SERIAL_DEBUG_PCI | ||
30 | |||
31 | /* | ||
32 | * init function returns: | ||
33 | * > 0 - number of ports | ||
34 | * = 0 - use board->num_ports | ||
35 | * < 0 - error | ||
36 | */ | ||
37 | struct pci_serial_quirk { | ||
38 | u32 vendor; | ||
39 | u32 device; | ||
40 | u32 subvendor; | ||
41 | u32 subdevice; | ||
42 | int (*probe)(struct pci_dev *dev); | ||
43 | int (*init)(struct pci_dev *dev); | ||
44 | int (*setup)(struct serial_private *, | ||
45 | const struct pciserial_board *, | ||
46 | struct uart_port *, int); | ||
47 | void (*exit)(struct pci_dev *dev); | ||
48 | }; | ||
49 | |||
50 | #define PCI_NUM_BAR_RESOURCES 6 | ||
51 | |||
52 | struct serial_private { | ||
53 | struct pci_dev *dev; | ||
54 | unsigned int nr; | ||
55 | void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; | ||
56 | struct pci_serial_quirk *quirk; | ||
57 | int line[0]; | ||
58 | }; | ||
59 | |||
60 | static int pci_default_setup(struct serial_private*, | ||
61 | const struct pciserial_board*, struct uart_port*, int); | ||
62 | |||
63 | static void moan_device(const char *str, struct pci_dev *dev) | ||
64 | { | ||
65 | printk(KERN_WARNING | ||
66 | "%s: %s\n" | ||
67 | "Please send the output of lspci -vv, this\n" | ||
68 | "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" | ||
69 | "manufacturer and name of serial board or\n" | ||
70 | "modem board to rmk+serial@arm.linux.org.uk.\n", | ||
71 | pci_name(dev), str, dev->vendor, dev->device, | ||
72 | dev->subsystem_vendor, dev->subsystem_device); | ||
73 | } | ||
74 | |||
75 | static int | ||
76 | setup_port(struct serial_private *priv, struct uart_port *port, | ||
77 | int bar, int offset, int regshift) | ||
78 | { | ||
79 | struct pci_dev *dev = priv->dev; | ||
80 | unsigned long base, len; | ||
81 | |||
82 | if (bar >= PCI_NUM_BAR_RESOURCES) | ||
83 | return -EINVAL; | ||
84 | |||
85 | base = pci_resource_start(dev, bar); | ||
86 | |||
87 | if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { | ||
88 | len = pci_resource_len(dev, bar); | ||
89 | |||
90 | if (!priv->remapped_bar[bar]) | ||
91 | priv->remapped_bar[bar] = ioremap_nocache(base, len); | ||
92 | if (!priv->remapped_bar[bar]) | ||
93 | return -ENOMEM; | ||
94 | |||
95 | port->iotype = UPIO_MEM; | ||
96 | port->iobase = 0; | ||
97 | port->mapbase = base + offset; | ||
98 | port->membase = priv->remapped_bar[bar] + offset; | ||
99 | port->regshift = regshift; | ||
100 | } else { | ||
101 | port->iotype = UPIO_PORT; | ||
102 | port->iobase = base + offset; | ||
103 | port->mapbase = 0; | ||
104 | port->membase = NULL; | ||
105 | port->regshift = 0; | ||
106 | } | ||
107 | return 0; | ||
108 | } | ||
109 | |||
110 | /* | ||
111 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | ||
112 | */ | ||
113 | static int addidata_apci7800_setup(struct serial_private *priv, | ||
114 | const struct pciserial_board *board, | ||
115 | struct uart_port *port, int idx) | ||
116 | { | ||
117 | unsigned int bar = 0, offset = board->first_offset; | ||
118 | bar = FL_GET_BASE(board->flags); | ||
119 | |||
120 | if (idx < 2) { | ||
121 | offset += idx * board->uart_offset; | ||
122 | } else if ((idx >= 2) && (idx < 4)) { | ||
123 | bar += 1; | ||
124 | offset += ((idx - 2) * board->uart_offset); | ||
125 | } else if ((idx >= 4) && (idx < 6)) { | ||
126 | bar += 2; | ||
127 | offset += ((idx - 4) * board->uart_offset); | ||
128 | } else if (idx >= 6) { | ||
129 | bar += 3; | ||
130 | offset += ((idx - 6) * board->uart_offset); | ||
131 | } | ||
132 | |||
133 | return setup_port(priv, port, bar, offset, board->reg_shift); | ||
134 | } | ||
135 | |||
136 | /* | ||
137 | * AFAVLAB uses a different mixture of BARs and offsets | ||
138 | * Not that ugly ;) -- HW | ||
139 | */ | ||
140 | static int | ||
141 | afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, | ||
142 | struct uart_port *port, int idx) | ||
143 | { | ||
144 | unsigned int bar, offset = board->first_offset; | ||
145 | |||
146 | bar = FL_GET_BASE(board->flags); | ||
147 | if (idx < 4) | ||
148 | bar += idx; | ||
149 | else { | ||
150 | bar = 4; | ||
151 | offset += (idx - 4) * board->uart_offset; | ||
152 | } | ||
153 | |||
154 | return setup_port(priv, port, bar, offset, board->reg_shift); | ||
155 | } | ||
156 | |||
157 | /* | ||
158 | * HP's Remote Management Console. The Diva chip came in several | ||
159 | * different versions. N-class, L2000 and A500 have two Diva chips, each | ||
160 | * with 3 UARTs (the third UART on the second chip is unused). Superdome | ||
161 | * and Keystone have one Diva chip with 3 UARTs. Some later machines have | ||
162 | * one Diva chip, but it has been expanded to 5 UARTs. | ||
163 | */ | ||
164 | static int pci_hp_diva_init(struct pci_dev *dev) | ||
165 | { | ||
166 | int rc = 0; | ||
167 | |||
168 | switch (dev->subsystem_device) { | ||
169 | case PCI_DEVICE_ID_HP_DIVA_TOSCA1: | ||
170 | case PCI_DEVICE_ID_HP_DIVA_HALFDOME: | ||
171 | case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: | ||
172 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | ||
173 | rc = 3; | ||
174 | break; | ||
175 | case PCI_DEVICE_ID_HP_DIVA_TOSCA2: | ||
176 | rc = 2; | ||
177 | break; | ||
178 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: | ||
179 | rc = 4; | ||
180 | break; | ||
181 | case PCI_DEVICE_ID_HP_DIVA_POWERBAR: | ||
182 | case PCI_DEVICE_ID_HP_DIVA_HURRICANE: | ||
183 | rc = 1; | ||
184 | break; | ||
185 | } | ||
186 | |||
187 | return rc; | ||
188 | } | ||
189 | |||
190 | /* | ||
191 | * HP's Diva chip puts the 4th/5th serial port further out, and | ||
192 | * some serial ports are supposed to be hidden on certain models. | ||
193 | */ | ||
194 | static int | ||
195 | pci_hp_diva_setup(struct serial_private *priv, | ||
196 | const struct pciserial_board *board, | ||
197 | struct uart_port *port, int idx) | ||
198 | { | ||
199 | unsigned int offset = board->first_offset; | ||
200 | unsigned int bar = FL_GET_BASE(board->flags); | ||
201 | |||
202 | switch (priv->dev->subsystem_device) { | ||
203 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: | ||
204 | if (idx == 3) | ||
205 | idx++; | ||
206 | break; | ||
207 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | ||
208 | if (idx > 0) | ||
209 | idx++; | ||
210 | if (idx > 2) | ||
211 | idx++; | ||
212 | break; | ||
213 | } | ||
214 | if (idx > 2) | ||
215 | offset = 0x18; | ||
216 | |||
217 | offset += idx * board->uart_offset; | ||
218 | |||
219 | return setup_port(priv, port, bar, offset, board->reg_shift); | ||
220 | } | ||
221 | |||
222 | /* | ||
223 | * Added for EKF Intel i960 serial boards | ||
224 | */ | ||
225 | static int pci_inteli960ni_init(struct pci_dev *dev) | ||
226 | { | ||
227 | unsigned long oldval; | ||
228 | |||
229 | if (!(dev->subsystem_device & 0x1000)) | ||
230 | return -ENODEV; | ||
231 | |||
232 | /* is firmware started? */ | ||
233 | pci_read_config_dword(dev, 0x44, (void *)&oldval); | ||
234 | if (oldval == 0x00001000L) { /* RESET value */ | ||
235 | printk(KERN_DEBUG "Local i960 firmware missing"); | ||
236 | return -ENODEV; | ||
237 | } | ||
238 | return 0; | ||
239 | } | ||
240 | |||
241 | /* | ||
242 | * Some PCI serial cards using the PLX 9050 PCI interface chip require | ||
243 | * that the card interrupt be explicitly enabled or disabled. This | ||
244 | * seems to be mainly needed on card using the PLX which also use I/O | ||
245 | * mapped memory. | ||
246 | */ | ||
247 | static int pci_plx9050_init(struct pci_dev *dev) | ||
248 | { | ||
249 | u8 irq_config; | ||
250 | void __iomem *p; | ||
251 | |||
252 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { | ||
253 | moan_device("no memory in bar 0", dev); | ||
254 | return 0; | ||
255 | } | ||
256 | |||
257 | irq_config = 0x41; | ||
258 | if (dev->vendor == PCI_VENDOR_ID_PANACOM || | ||
259 | dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) | ||
260 | irq_config = 0x43; | ||
261 | |||
262 | if ((dev->vendor == PCI_VENDOR_ID_PLX) && | ||
263 | (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) | ||
264 | /* | ||
265 | * As the megawolf cards have the int pins active | ||
266 | * high, and have 2 UART chips, both ints must be | ||
267 | * enabled on the 9050. Also, the UARTS are set in | ||
268 | * 16450 mode by default, so we have to enable the | ||
269 | * 16C950 'enhanced' mode so that we can use the | ||
270 | * deep FIFOs | ||
271 | */ | ||
272 | irq_config = 0x5b; | ||
273 | /* | ||
274 | * enable/disable interrupts | ||
275 | */ | ||
276 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); | ||
277 | if (p == NULL) | ||
278 | return -ENOMEM; | ||
279 | writel(irq_config, p + 0x4c); | ||
280 | |||
281 | /* | ||
282 | * Read the register back to ensure that it took effect. | ||
283 | */ | ||
284 | readl(p + 0x4c); | ||
285 | iounmap(p); | ||
286 | |||
287 | return 0; | ||
288 | } | ||
289 | |||
290 | static void __devexit pci_plx9050_exit(struct pci_dev *dev) | ||
291 | { | ||
292 | u8 __iomem *p; | ||
293 | |||
294 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) | ||
295 | return; | ||
296 | |||
297 | /* | ||
298 | * disable interrupts | ||
299 | */ | ||
300 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); | ||
301 | if (p != NULL) { | ||
302 | writel(0, p + 0x4c); | ||
303 | |||
304 | /* | ||
305 | * Read the register back to ensure that it took effect. | ||
306 | */ | ||
307 | readl(p + 0x4c); | ||
308 | iounmap(p); | ||
309 | } | ||
310 | } | ||
311 | |||
312 | #define NI8420_INT_ENABLE_REG 0x38 | ||
313 | #define NI8420_INT_ENABLE_BIT 0x2000 | ||
314 | |||
315 | static void __devexit pci_ni8420_exit(struct pci_dev *dev) | ||
316 | { | ||
317 | void __iomem *p; | ||
318 | unsigned long base, len; | ||
319 | unsigned int bar = 0; | ||
320 | |||
321 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | ||
322 | moan_device("no memory in bar", dev); | ||
323 | return; | ||
324 | } | ||
325 | |||
326 | base = pci_resource_start(dev, bar); | ||
327 | len = pci_resource_len(dev, bar); | ||
328 | p = ioremap_nocache(base, len); | ||
329 | if (p == NULL) | ||
330 | return; | ||
331 | |||
332 | /* Disable the CPU Interrupt */ | ||
333 | writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), | ||
334 | p + NI8420_INT_ENABLE_REG); | ||
335 | iounmap(p); | ||
336 | } | ||
337 | |||
338 | |||
339 | /* MITE registers */ | ||
340 | #define MITE_IOWBSR1 0xc4 | ||
341 | #define MITE_IOWCR1 0xf4 | ||
342 | #define MITE_LCIMR1 0x08 | ||
343 | #define MITE_LCIMR2 0x10 | ||
344 | |||
345 | #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) | ||
346 | |||
347 | static void __devexit pci_ni8430_exit(struct pci_dev *dev) | ||
348 | { | ||
349 | void __iomem *p; | ||
350 | unsigned long base, len; | ||
351 | unsigned int bar = 0; | ||
352 | |||
353 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | ||
354 | moan_device("no memory in bar", dev); | ||
355 | return; | ||
356 | } | ||
357 | |||
358 | base = pci_resource_start(dev, bar); | ||
359 | len = pci_resource_len(dev, bar); | ||
360 | p = ioremap_nocache(base, len); | ||
361 | if (p == NULL) | ||
362 | return; | ||
363 | |||
364 | /* Disable the CPU Interrupt */ | ||
365 | writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); | ||
366 | iounmap(p); | ||
367 | } | ||
368 | |||
369 | /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ | ||
370 | static int | ||
371 | sbs_setup(struct serial_private *priv, const struct pciserial_board *board, | ||
372 | struct uart_port *port, int idx) | ||
373 | { | ||
374 | unsigned int bar, offset = board->first_offset; | ||
375 | |||
376 | bar = 0; | ||
377 | |||
378 | if (idx < 4) { | ||
379 | /* first four channels map to 0, 0x100, 0x200, 0x300 */ | ||
380 | offset += idx * board->uart_offset; | ||
381 | } else if (idx < 8) { | ||
382 | /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ | ||
383 | offset += idx * board->uart_offset + 0xC00; | ||
384 | } else /* we have only 8 ports on PMC-OCTALPRO */ | ||
385 | return 1; | ||
386 | |||
387 | return setup_port(priv, port, bar, offset, board->reg_shift); | ||
388 | } | ||
389 | |||
390 | /* | ||
391 | * This does initialization for PMC OCTALPRO cards: | ||
392 | * maps the device memory, resets the UARTs (needed, bc | ||
393 | * if the module is removed and inserted again, the card | ||
394 | * is in the sleep mode) and enables global interrupt. | ||
395 | */ | ||
396 | |||
397 | /* global control register offset for SBS PMC-OctalPro */ | ||
398 | #define OCT_REG_CR_OFF 0x500 | ||
399 | |||
400 | static int sbs_init(struct pci_dev *dev) | ||
401 | { | ||
402 | u8 __iomem *p; | ||
403 | |||
404 | p = pci_ioremap_bar(dev, 0); | ||
405 | |||
406 | if (p == NULL) | ||
407 | return -ENOMEM; | ||
408 | /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ | ||
409 | writeb(0x10, p + OCT_REG_CR_OFF); | ||
410 | udelay(50); | ||
411 | writeb(0x0, p + OCT_REG_CR_OFF); | ||
412 | |||
413 | /* Set bit-2 (INTENABLE) of Control Register */ | ||
414 | writeb(0x4, p + OCT_REG_CR_OFF); | ||
415 | iounmap(p); | ||
416 | |||
417 | return 0; | ||
418 | } | ||
419 | |||
420 | /* | ||
421 | * Disables the global interrupt of PMC-OctalPro | ||
422 | */ | ||
423 | |||
424 | static void __devexit sbs_exit(struct pci_dev *dev) | ||
425 | { | ||
426 | u8 __iomem *p; | ||
427 | |||
428 | p = pci_ioremap_bar(dev, 0); | ||
429 | /* FIXME: What if resource_len < OCT_REG_CR_OFF */ | ||
430 | if (p != NULL) | ||
431 | writeb(0, p + OCT_REG_CR_OFF); | ||
432 | iounmap(p); | ||
433 | } | ||
434 | |||
435 | /* | ||
436 | * SIIG serial cards have an PCI interface chip which also controls | ||
437 | * the UART clocking frequency. Each UART can be clocked independently | ||
438 | * (except cards equipped with 4 UARTs) and initial clocking settings | ||
439 | * are stored in the EEPROM chip. It can cause problems because this | ||
440 | * version of serial driver doesn't support differently clocked UART's | ||
441 | * on single PCI card. To prevent this, initialization functions set | ||
442 | * high frequency clocking for all UART's on given card. It is safe (I | ||
443 | * hope) because it doesn't touch EEPROM settings to prevent conflicts | ||
444 | * with other OSes (like M$ DOS). | ||
445 | * | ||
446 | * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 | ||
447 | * | ||
448 | * There is two family of SIIG serial cards with different PCI | ||
449 | * interface chip and different configuration methods: | ||
450 | * - 10x cards have control registers in IO and/or memory space; | ||
451 | * - 20x cards have control registers in standard PCI configuration space. | ||
452 | * | ||
453 | * Note: all 10x cards have PCI device ids 0x10.. | ||
454 | * all 20x cards have PCI device ids 0x20.. | ||
455 | * | ||
456 | * There are also Quartet Serial cards which use Oxford Semiconductor | ||
457 | * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. | ||
458 | * | ||
459 | * Note: some SIIG cards are probed by the parport_serial object. | ||
460 | */ | ||
461 | |||
462 | #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) | ||
463 | #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) | ||
464 | |||
465 | static int pci_siig10x_init(struct pci_dev *dev) | ||
466 | { | ||
467 | u16 data; | ||
468 | void __iomem *p; | ||
469 | |||
470 | switch (dev->device & 0xfff8) { | ||
471 | case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ | ||
472 | data = 0xffdf; | ||
473 | break; | ||
474 | case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ | ||
475 | data = 0xf7ff; | ||
476 | break; | ||
477 | default: /* 1S1P, 4S */ | ||
478 | data = 0xfffb; | ||
479 | break; | ||
480 | } | ||
481 | |||
482 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); | ||
483 | if (p == NULL) | ||
484 | return -ENOMEM; | ||
485 | |||
486 | writew(readw(p + 0x28) & data, p + 0x28); | ||
487 | readw(p + 0x28); | ||
488 | iounmap(p); | ||
489 | return 0; | ||
490 | } | ||
491 | |||
492 | #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) | ||
493 | #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) | ||
494 | |||
495 | static int pci_siig20x_init(struct pci_dev *dev) | ||
496 | { | ||
497 | u8 data; | ||
498 | |||
499 | /* Change clock frequency for the first UART. */ | ||
500 | pci_read_config_byte(dev, 0x6f, &data); | ||
501 | pci_write_config_byte(dev, 0x6f, data & 0xef); | ||
502 | |||
503 | /* If this card has 2 UART, we have to do the same with second UART. */ | ||
504 | if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || | ||
505 | ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { | ||
506 | pci_read_config_byte(dev, 0x73, &data); | ||
507 | pci_write_config_byte(dev, 0x73, data & 0xef); | ||
508 | } | ||
509 | return 0; | ||
510 | } | ||
511 | |||
512 | static int pci_siig_init(struct pci_dev *dev) | ||
513 | { | ||
514 | unsigned int type = dev->device & 0xff00; | ||
515 | |||
516 | if (type == 0x1000) | ||
517 | return pci_siig10x_init(dev); | ||
518 | else if (type == 0x2000) | ||
519 | return pci_siig20x_init(dev); | ||
520 | |||
521 | moan_device("Unknown SIIG card", dev); | ||
522 | return -ENODEV; | ||
523 | } | ||
524 | |||
525 | static int pci_siig_setup(struct serial_private *priv, | ||
526 | const struct pciserial_board *board, | ||
527 | struct uart_port *port, int idx) | ||
528 | { | ||
529 | unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; | ||
530 | |||
531 | if (idx > 3) { | ||
532 | bar = 4; | ||
533 | offset = (idx - 4) * 8; | ||
534 | } | ||
535 | |||
536 | return setup_port(priv, port, bar, offset, 0); | ||
537 | } | ||
538 | |||
539 | /* | ||
540 | * Timedia has an explosion of boards, and to avoid the PCI table from | ||
541 | * growing *huge*, we use this function to collapse some 70 entries | ||
542 | * in the PCI table into one, for sanity's and compactness's sake. | ||
543 | */ | ||
544 | static const unsigned short timedia_single_port[] = { | ||
545 | 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 | ||
546 | }; | ||
547 | |||
548 | static const unsigned short timedia_dual_port[] = { | ||
549 | 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, | ||
550 | 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, | ||
551 | 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, | ||
552 | 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, | ||
553 | 0xD079, 0 | ||
554 | }; | ||
555 | |||
556 | static const unsigned short timedia_quad_port[] = { | ||
557 | 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, | ||
558 | 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, | ||
559 | 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, | ||
560 | 0xB157, 0 | ||
561 | }; | ||
562 | |||
563 | static const unsigned short timedia_eight_port[] = { | ||
564 | 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, | ||
565 | 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 | ||
566 | }; | ||
567 | |||
568 | static const struct timedia_struct { | ||
569 | int num; | ||
570 | const unsigned short *ids; | ||
571 | } timedia_data[] = { | ||
572 | { 1, timedia_single_port }, | ||
573 | { 2, timedia_dual_port }, | ||
574 | { 4, timedia_quad_port }, | ||
575 | { 8, timedia_eight_port } | ||
576 | }; | ||
577 | |||
578 | /* | ||
579 | * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of | ||
580 | * listing them individually, this driver merely grabs them all with | ||
581 | * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, | ||
582 | * and should be left free to be claimed by parport_serial instead. | ||
583 | */ | ||
584 | static int pci_timedia_probe(struct pci_dev *dev) | ||
585 | { | ||
586 | /* | ||
587 | * Check the third digit of the subdevice ID | ||
588 | * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) | ||
589 | */ | ||
590 | if ((dev->subsystem_device & 0x00f0) >= 0x70) { | ||
591 | dev_info(&dev->dev, | ||
592 | "ignoring Timedia subdevice %04x for parport_serial\n", | ||
593 | dev->subsystem_device); | ||
594 | return -ENODEV; | ||
595 | } | ||
596 | |||
597 | return 0; | ||
598 | } | ||
599 | |||
600 | static int pci_timedia_init(struct pci_dev *dev) | ||
601 | { | ||
602 | const unsigned short *ids; | ||
603 | int i, j; | ||
604 | |||
605 | for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { | ||
606 | ids = timedia_data[i].ids; | ||
607 | for (j = 0; ids[j]; j++) | ||
608 | if (dev->subsystem_device == ids[j]) | ||
609 | return timedia_data[i].num; | ||
610 | } | ||
611 | return 0; | ||
612 | } | ||
613 | |||
614 | /* | ||
615 | * Timedia/SUNIX uses a mixture of BARs and offsets | ||
616 | * Ugh, this is ugly as all hell --- TYT | ||
617 | */ | ||
618 | static int | ||
619 | pci_timedia_setup(struct serial_private *priv, | ||
620 | const struct pciserial_board *board, | ||
621 | struct uart_port *port, int idx) | ||
622 | { | ||
623 | unsigned int bar = 0, offset = board->first_offset; | ||
624 | |||
625 | switch (idx) { | ||
626 | case 0: | ||
627 | bar = 0; | ||
628 | break; | ||
629 | case 1: | ||
630 | offset = board->uart_offset; | ||
631 | bar = 0; | ||
632 | break; | ||
633 | case 2: | ||
634 | bar = 1; | ||
635 | break; | ||
636 | case 3: | ||
637 | offset = board->uart_offset; | ||
638 | /* FALLTHROUGH */ | ||
639 | case 4: /* BAR 2 */ | ||
640 | case 5: /* BAR 3 */ | ||
641 | case 6: /* BAR 4 */ | ||
642 | case 7: /* BAR 5 */ | ||
643 | bar = idx - 2; | ||
644 | } | ||
645 | |||
646 | return setup_port(priv, port, bar, offset, board->reg_shift); | ||
647 | } | ||
648 | |||
649 | /* | ||
650 | * Some Titan cards are also a little weird | ||
651 | */ | ||
652 | static int | ||
653 | titan_400l_800l_setup(struct serial_private *priv, | ||
654 | const struct pciserial_board *board, | ||
655 | struct uart_port *port, int idx) | ||
656 | { | ||
657 | unsigned int bar, offset = board->first_offset; | ||
658 | |||
659 | switch (idx) { | ||
660 | case 0: | ||
661 | bar = 1; | ||
662 | break; | ||
663 | case 1: | ||
664 | bar = 2; | ||
665 | break; | ||
666 | default: | ||
667 | bar = 4; | ||
668 | offset = (idx - 2) * board->uart_offset; | ||
669 | } | ||
670 | |||
671 | return setup_port(priv, port, bar, offset, board->reg_shift); | ||
672 | } | ||
673 | |||
674 | static int pci_xircom_init(struct pci_dev *dev) | ||
675 | { | ||
676 | msleep(100); | ||
677 | return 0; | ||
678 | } | ||
679 | |||
680 | static int pci_ni8420_init(struct pci_dev *dev) | ||
681 | { | ||
682 | void __iomem *p; | ||
683 | unsigned long base, len; | ||
684 | unsigned int bar = 0; | ||
685 | |||
686 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | ||
687 | moan_device("no memory in bar", dev); | ||
688 | return 0; | ||
689 | } | ||
690 | |||
691 | base = pci_resource_start(dev, bar); | ||
692 | len = pci_resource_len(dev, bar); | ||
693 | p = ioremap_nocache(base, len); | ||
694 | if (p == NULL) | ||
695 | return -ENOMEM; | ||
696 | |||
697 | /* Enable CPU Interrupt */ | ||
698 | writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, | ||
699 | p + NI8420_INT_ENABLE_REG); | ||
700 | |||
701 | iounmap(p); | ||
702 | return 0; | ||
703 | } | ||
704 | |||
705 | #define MITE_IOWBSR1_WSIZE 0xa | ||
706 | #define MITE_IOWBSR1_WIN_OFFSET 0x800 | ||
707 | #define MITE_IOWBSR1_WENAB (1 << 7) | ||
708 | #define MITE_LCIMR1_IO_IE_0 (1 << 24) | ||
709 | #define MITE_LCIMR2_SET_CPU_IE (1 << 31) | ||
710 | #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe | ||
711 | |||
712 | static int pci_ni8430_init(struct pci_dev *dev) | ||
713 | { | ||
714 | void __iomem *p; | ||
715 | unsigned long base, len; | ||
716 | u32 device_window; | ||
717 | unsigned int bar = 0; | ||
718 | |||
719 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | ||
720 | moan_device("no memory in bar", dev); | ||
721 | return 0; | ||
722 | } | ||
723 | |||
724 | base = pci_resource_start(dev, bar); | ||
725 | len = pci_resource_len(dev, bar); | ||
726 | p = ioremap_nocache(base, len); | ||
727 | if (p == NULL) | ||
728 | return -ENOMEM; | ||
729 | |||
730 | /* Set device window address and size in BAR0 */ | ||
731 | device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) | ||
732 | | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; | ||
733 | writel(device_window, p + MITE_IOWBSR1); | ||
734 | |||
735 | /* Set window access to go to RAMSEL IO address space */ | ||
736 | writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), | ||
737 | p + MITE_IOWCR1); | ||
738 | |||
739 | /* Enable IO Bus Interrupt 0 */ | ||
740 | writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); | ||
741 | |||
742 | /* Enable CPU Interrupt */ | ||
743 | writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); | ||
744 | |||
745 | iounmap(p); | ||
746 | return 0; | ||
747 | } | ||
748 | |||
749 | /* UART Port Control Register */ | ||
750 | #define NI8430_PORTCON 0x0f | ||
751 | #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) | ||
752 | |||
753 | static int | ||
754 | pci_ni8430_setup(struct serial_private *priv, | ||
755 | const struct pciserial_board *board, | ||
756 | struct uart_port *port, int idx) | ||
757 | { | ||
758 | void __iomem *p; | ||
759 | unsigned long base, len; | ||
760 | unsigned int bar, offset = board->first_offset; | ||
761 | |||
762 | if (idx >= board->num_ports) | ||
763 | return 1; | ||
764 | |||
765 | bar = FL_GET_BASE(board->flags); | ||
766 | offset += idx * board->uart_offset; | ||
767 | |||
768 | base = pci_resource_start(priv->dev, bar); | ||
769 | len = pci_resource_len(priv->dev, bar); | ||
770 | p = ioremap_nocache(base, len); | ||
771 | |||
772 | /* enable the transceiver */ | ||
773 | writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, | ||
774 | p + offset + NI8430_PORTCON); | ||
775 | |||
776 | iounmap(p); | ||
777 | |||
778 | return setup_port(priv, port, bar, offset, board->reg_shift); | ||
779 | } | ||
780 | |||
781 | static int pci_netmos_9900_setup(struct serial_private *priv, | ||
782 | const struct pciserial_board *board, | ||
783 | struct uart_port *port, int idx) | ||
784 | { | ||
785 | unsigned int bar; | ||
786 | |||
787 | if ((priv->dev->subsystem_device & 0xff00) == 0x3000) { | ||
788 | /* netmos apparently orders BARs by datasheet layout, so serial | ||
789 | * ports get BARs 0 and 3 (or 1 and 4 for memmapped) | ||
790 | */ | ||
791 | bar = 3 * idx; | ||
792 | |||
793 | return setup_port(priv, port, bar, 0, board->reg_shift); | ||
794 | } else { | ||
795 | return pci_default_setup(priv, board, port, idx); | ||
796 | } | ||
797 | } | ||
798 | |||
799 | /* the 99xx series comes with a range of device IDs and a variety | ||
800 | * of capabilities: | ||
801 | * | ||
802 | * 9900 has varying capabilities and can cascade to sub-controllers | ||
803 | * (cascading should be purely internal) | ||
804 | * 9904 is hardwired with 4 serial ports | ||
805 | * 9912 and 9922 are hardwired with 2 serial ports | ||
806 | */ | ||
807 | static int pci_netmos_9900_numports(struct pci_dev *dev) | ||
808 | { | ||
809 | unsigned int c = dev->class; | ||
810 | unsigned int pi; | ||
811 | unsigned short sub_serports; | ||
812 | |||
813 | pi = (c & 0xff); | ||
814 | |||
815 | if (pi == 2) { | ||
816 | return 1; | ||
817 | } else if ((pi == 0) && | ||
818 | (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { | ||
819 | /* two possibilities: 0x30ps encodes number of parallel and | ||
820 | * serial ports, or 0x1000 indicates *something*. This is not | ||
821 | * immediately obvious, since the 2s1p+4s configuration seems | ||
822 | * to offer all functionality on functions 0..2, while still | ||
823 | * advertising the same function 3 as the 4s+2s1p config. | ||
824 | */ | ||
825 | sub_serports = dev->subsystem_device & 0xf; | ||
826 | if (sub_serports > 0) { | ||
827 | return sub_serports; | ||
828 | } else { | ||
829 | printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); | ||
830 | return 0; | ||
831 | } | ||
832 | } | ||
833 | |||
834 | moan_device("unknown NetMos/Mostech program interface", dev); | ||
835 | return 0; | ||
836 | } | ||
837 | |||
838 | static int pci_netmos_init(struct pci_dev *dev) | ||
839 | { | ||
840 | /* subdevice 0x00PS means <P> parallel, <S> serial */ | ||
841 | unsigned int num_serial = dev->subsystem_device & 0xf; | ||
842 | |||
843 | if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || | ||
844 | (dev->device == PCI_DEVICE_ID_NETMOS_9865)) | ||
845 | return 0; | ||
846 | |||
847 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && | ||
848 | dev->subsystem_device == 0x0299) | ||
849 | return 0; | ||
850 | |||
851 | switch (dev->device) { /* FALLTHROUGH on all */ | ||
852 | case PCI_DEVICE_ID_NETMOS_9904: | ||
853 | case PCI_DEVICE_ID_NETMOS_9912: | ||
854 | case PCI_DEVICE_ID_NETMOS_9922: | ||
855 | case PCI_DEVICE_ID_NETMOS_9900: | ||
856 | num_serial = pci_netmos_9900_numports(dev); | ||
857 | break; | ||
858 | |||
859 | default: | ||
860 | if (num_serial == 0 ) { | ||
861 | moan_device("unknown NetMos/Mostech device", dev); | ||
862 | } | ||
863 | } | ||
864 | |||
865 | if (num_serial == 0) | ||
866 | return -ENODEV; | ||
867 | |||
868 | return num_serial; | ||
869 | } | ||
870 | |||
871 | /* | ||
872 | * These chips are available with optionally one parallel port and up to | ||
873 | * two serial ports. Unfortunately they all have the same product id. | ||
874 | * | ||
875 | * Basic configuration is done over a region of 32 I/O ports. The base | ||
876 | * ioport is called INTA or INTC, depending on docs/other drivers. | ||
877 | * | ||
878 | * The region of the 32 I/O ports is configured in POSIO0R... | ||
879 | */ | ||
880 | |||
881 | /* registers */ | ||
882 | #define ITE_887x_MISCR 0x9c | ||
883 | #define ITE_887x_INTCBAR 0x78 | ||
884 | #define ITE_887x_UARTBAR 0x7c | ||
885 | #define ITE_887x_PS0BAR 0x10 | ||
886 | #define ITE_887x_POSIO0 0x60 | ||
887 | |||
888 | /* I/O space size */ | ||
889 | #define ITE_887x_IOSIZE 32 | ||
890 | /* I/O space size (bits 26-24; 8 bytes = 011b) */ | ||
891 | #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) | ||
892 | /* I/O space size (bits 26-24; 32 bytes = 101b) */ | ||
893 | #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) | ||
894 | /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ | ||
895 | #define ITE_887x_POSIO_SPEED (3 << 29) | ||
896 | /* enable IO_Space bit */ | ||
897 | #define ITE_887x_POSIO_ENABLE (1 << 31) | ||
898 | |||
899 | static int pci_ite887x_init(struct pci_dev *dev) | ||
900 | { | ||
901 | /* inta_addr are the configuration addresses of the ITE */ | ||
902 | static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, | ||
903 | 0x200, 0x280, 0 }; | ||
904 | int ret, i, type; | ||
905 | struct resource *iobase = NULL; | ||
906 | u32 miscr, uartbar, ioport; | ||
907 | |||
908 | /* search for the base-ioport */ | ||
909 | i = 0; | ||
910 | while (inta_addr[i] && iobase == NULL) { | ||
911 | iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, | ||
912 | "ite887x"); | ||
913 | if (iobase != NULL) { | ||
914 | /* write POSIO0R - speed | size | ioport */ | ||
915 | pci_write_config_dword(dev, ITE_887x_POSIO0, | ||
916 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | | ||
917 | ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); | ||
918 | /* write INTCBAR - ioport */ | ||
919 | pci_write_config_dword(dev, ITE_887x_INTCBAR, | ||
920 | inta_addr[i]); | ||
921 | ret = inb(inta_addr[i]); | ||
922 | if (ret != 0xff) { | ||
923 | /* ioport connected */ | ||
924 | break; | ||
925 | } | ||
926 | release_region(iobase->start, ITE_887x_IOSIZE); | ||
927 | iobase = NULL; | ||
928 | } | ||
929 | i++; | ||
930 | } | ||
931 | |||
932 | if (!inta_addr[i]) { | ||
933 | printk(KERN_ERR "ite887x: could not find iobase\n"); | ||
934 | return -ENODEV; | ||
935 | } | ||
936 | |||
937 | /* start of undocumented type checking (see parport_pc.c) */ | ||
938 | type = inb(iobase->start + 0x18) & 0x0f; | ||
939 | |||
940 | switch (type) { | ||
941 | case 0x2: /* ITE8871 (1P) */ | ||
942 | case 0xa: /* ITE8875 (1P) */ | ||
943 | ret = 0; | ||
944 | break; | ||
945 | case 0xe: /* ITE8872 (2S1P) */ | ||
946 | ret = 2; | ||
947 | break; | ||
948 | case 0x6: /* ITE8873 (1S) */ | ||
949 | ret = 1; | ||
950 | break; | ||
951 | case 0x8: /* ITE8874 (2S) */ | ||
952 | ret = 2; | ||
953 | break; | ||
954 | default: | ||
955 | moan_device("Unknown ITE887x", dev); | ||
956 | ret = -ENODEV; | ||
957 | } | ||
958 | |||
959 | /* configure all serial ports */ | ||
960 | for (i = 0; i < ret; i++) { | ||
961 | /* read the I/O port from the device */ | ||
962 | pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), | ||
963 | &ioport); | ||
964 | ioport &= 0x0000FF00; /* the actual base address */ | ||
965 | pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), | ||
966 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | | ||
967 | ITE_887x_POSIO_IOSIZE_8 | ioport); | ||
968 | |||
969 | /* write the ioport to the UARTBAR */ | ||
970 | pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); | ||
971 | uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ | ||
972 | uartbar |= (ioport << (16 * i)); /* set the ioport */ | ||
973 | pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); | ||
974 | |||
975 | /* get current config */ | ||
976 | pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); | ||
977 | /* disable interrupts (UARTx_Routing[3:0]) */ | ||
978 | miscr &= ~(0xf << (12 - 4 * i)); | ||
979 | /* activate the UART (UARTx_En) */ | ||
980 | miscr |= 1 << (23 - i); | ||
981 | /* write new config with activated UART */ | ||
982 | pci_write_config_dword(dev, ITE_887x_MISCR, miscr); | ||
983 | } | ||
984 | |||
985 | if (ret <= 0) { | ||
986 | /* the device has no UARTs if we get here */ | ||
987 | release_region(iobase->start, ITE_887x_IOSIZE); | ||
988 | } | ||
989 | |||
990 | return ret; | ||
991 | } | ||
992 | |||
993 | static void __devexit pci_ite887x_exit(struct pci_dev *dev) | ||
994 | { | ||
995 | u32 ioport; | ||
996 | /* the ioport is bit 0-15 in POSIO0R */ | ||
997 | pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); | ||
998 | ioport &= 0xffff; | ||
999 | release_region(ioport, ITE_887x_IOSIZE); | ||
1000 | } | ||
1001 | |||
1002 | /* | ||
1003 | * Oxford Semiconductor Inc. | ||
1004 | * Check that device is part of the Tornado range of devices, then determine | ||
1005 | * the number of ports available on the device. | ||
1006 | */ | ||
1007 | static int pci_oxsemi_tornado_init(struct pci_dev *dev) | ||
1008 | { | ||
1009 | u8 __iomem *p; | ||
1010 | unsigned long deviceID; | ||
1011 | unsigned int number_uarts = 0; | ||
1012 | |||
1013 | /* OxSemi Tornado devices are all 0xCxxx */ | ||
1014 | if (dev->vendor == PCI_VENDOR_ID_OXSEMI && | ||
1015 | (dev->device & 0xF000) != 0xC000) | ||
1016 | return 0; | ||
1017 | |||
1018 | p = pci_iomap(dev, 0, 5); | ||
1019 | if (p == NULL) | ||
1020 | return -ENOMEM; | ||
1021 | |||
1022 | deviceID = ioread32(p); | ||
1023 | /* Tornado device */ | ||
1024 | if (deviceID == 0x07000200) { | ||
1025 | number_uarts = ioread8(p + 4); | ||
1026 | printk(KERN_DEBUG | ||
1027 | "%d ports detected on Oxford PCI Express device\n", | ||
1028 | number_uarts); | ||
1029 | } | ||
1030 | pci_iounmap(dev, p); | ||
1031 | return number_uarts; | ||
1032 | } | ||
1033 | |||
1034 | static int | ||
1035 | pci_default_setup(struct serial_private *priv, | ||
1036 | const struct pciserial_board *board, | ||
1037 | struct uart_port *port, int idx) | ||
1038 | { | ||
1039 | unsigned int bar, offset = board->first_offset, maxnr; | ||
1040 | |||
1041 | bar = FL_GET_BASE(board->flags); | ||
1042 | if (board->flags & FL_BASE_BARS) | ||
1043 | bar += idx; | ||
1044 | else | ||
1045 | offset += idx * board->uart_offset; | ||
1046 | |||
1047 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> | ||
1048 | (board->reg_shift + 3); | ||
1049 | |||
1050 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) | ||
1051 | return 1; | ||
1052 | |||
1053 | return setup_port(priv, port, bar, offset, board->reg_shift); | ||
1054 | } | ||
1055 | |||
1056 | static int | ||
1057 | ce4100_serial_setup(struct serial_private *priv, | ||
1058 | const struct pciserial_board *board, | ||
1059 | struct uart_port *port, int idx) | ||
1060 | { | ||
1061 | int ret; | ||
1062 | |||
1063 | ret = setup_port(priv, port, 0, 0, board->reg_shift); | ||
1064 | port->iotype = UPIO_MEM32; | ||
1065 | port->type = PORT_XSCALE; | ||
1066 | port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); | ||
1067 | port->regshift = 2; | ||
1068 | |||
1069 | return ret; | ||
1070 | } | ||
1071 | |||
1072 | static int | ||
1073 | pci_omegapci_setup(struct serial_private *priv, | ||
1074 | const struct pciserial_board *board, | ||
1075 | struct uart_port *port, int idx) | ||
1076 | { | ||
1077 | return setup_port(priv, port, 2, idx * 8, 0); | ||
1078 | } | ||
1079 | |||
1080 | static int skip_tx_en_setup(struct serial_private *priv, | ||
1081 | const struct pciserial_board *board, | ||
1082 | struct uart_port *port, int idx) | ||
1083 | { | ||
1084 | port->flags |= UPF_NO_TXEN_TEST; | ||
1085 | printk(KERN_DEBUG "serial8250: skipping TxEn test for device " | ||
1086 | "[%04x:%04x] subsystem [%04x:%04x]\n", | ||
1087 | priv->dev->vendor, | ||
1088 | priv->dev->device, | ||
1089 | priv->dev->subsystem_vendor, | ||
1090 | priv->dev->subsystem_device); | ||
1091 | |||
1092 | return pci_default_setup(priv, board, port, idx); | ||
1093 | } | ||
1094 | |||
1095 | static int pci_eg20t_init(struct pci_dev *dev) | ||
1096 | { | ||
1097 | #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) | ||
1098 | return -ENODEV; | ||
1099 | #else | ||
1100 | return 0; | ||
1101 | #endif | ||
1102 | } | ||
1103 | |||
1104 | /* This should be in linux/pci_ids.h */ | ||
1105 | #define PCI_VENDOR_ID_SBSMODULARIO 0x124B | ||
1106 | #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B | ||
1107 | #define PCI_DEVICE_ID_OCTPRO 0x0001 | ||
1108 | #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 | ||
1109 | #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 | ||
1110 | #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 | ||
1111 | #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 | ||
1112 | #define PCI_VENDOR_ID_ADVANTECH 0x13fe | ||
1113 | #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 | ||
1114 | #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 | ||
1115 | #define PCI_DEVICE_ID_TITAN_200I 0x8028 | ||
1116 | #define PCI_DEVICE_ID_TITAN_400I 0x8048 | ||
1117 | #define PCI_DEVICE_ID_TITAN_800I 0x8088 | ||
1118 | #define PCI_DEVICE_ID_TITAN_800EH 0xA007 | ||
1119 | #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 | ||
1120 | #define PCI_DEVICE_ID_TITAN_400EH 0xA009 | ||
1121 | #define PCI_DEVICE_ID_TITAN_100E 0xA010 | ||
1122 | #define PCI_DEVICE_ID_TITAN_200E 0xA012 | ||
1123 | #define PCI_DEVICE_ID_TITAN_400E 0xA013 | ||
1124 | #define PCI_DEVICE_ID_TITAN_800E 0xA014 | ||
1125 | #define PCI_DEVICE_ID_TITAN_200EI 0xA016 | ||
1126 | #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 | ||
1127 | #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 | ||
1128 | #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 | ||
1129 | #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 | ||
1130 | |||
1131 | /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ | ||
1132 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 | ||
1133 | |||
1134 | /* | ||
1135 | * Master list of serial port init/setup/exit quirks. | ||
1136 | * This does not describe the general nature of the port. | ||
1137 | * (ie, baud base, number and location of ports, etc) | ||
1138 | * | ||
1139 | * This list is ordered alphabetically by vendor then device. | ||
1140 | * Specific entries must come before more generic entries. | ||
1141 | */ | ||
1142 | static struct pci_serial_quirk pci_serial_quirks[] __refdata = { | ||
1143 | /* | ||
1144 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | ||
1145 | */ | ||
1146 | { | ||
1147 | .vendor = PCI_VENDOR_ID_ADDIDATA_OLD, | ||
1148 | .device = PCI_DEVICE_ID_ADDIDATA_APCI7800, | ||
1149 | .subvendor = PCI_ANY_ID, | ||
1150 | .subdevice = PCI_ANY_ID, | ||
1151 | .setup = addidata_apci7800_setup, | ||
1152 | }, | ||
1153 | /* | ||
1154 | * AFAVLAB cards - these may be called via parport_serial | ||
1155 | * It is not clear whether this applies to all products. | ||
1156 | */ | ||
1157 | { | ||
1158 | .vendor = PCI_VENDOR_ID_AFAVLAB, | ||
1159 | .device = PCI_ANY_ID, | ||
1160 | .subvendor = PCI_ANY_ID, | ||
1161 | .subdevice = PCI_ANY_ID, | ||
1162 | .setup = afavlab_setup, | ||
1163 | }, | ||
1164 | /* | ||
1165 | * HP Diva | ||
1166 | */ | ||
1167 | { | ||
1168 | .vendor = PCI_VENDOR_ID_HP, | ||
1169 | .device = PCI_DEVICE_ID_HP_DIVA, | ||
1170 | .subvendor = PCI_ANY_ID, | ||
1171 | .subdevice = PCI_ANY_ID, | ||
1172 | .init = pci_hp_diva_init, | ||
1173 | .setup = pci_hp_diva_setup, | ||
1174 | }, | ||
1175 | /* | ||
1176 | * Intel | ||
1177 | */ | ||
1178 | { | ||
1179 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1180 | .device = PCI_DEVICE_ID_INTEL_80960_RP, | ||
1181 | .subvendor = 0xe4bf, | ||
1182 | .subdevice = PCI_ANY_ID, | ||
1183 | .init = pci_inteli960ni_init, | ||
1184 | .setup = pci_default_setup, | ||
1185 | }, | ||
1186 | { | ||
1187 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1188 | .device = PCI_DEVICE_ID_INTEL_8257X_SOL, | ||
1189 | .subvendor = PCI_ANY_ID, | ||
1190 | .subdevice = PCI_ANY_ID, | ||
1191 | .setup = skip_tx_en_setup, | ||
1192 | }, | ||
1193 | { | ||
1194 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1195 | .device = PCI_DEVICE_ID_INTEL_82573L_SOL, | ||
1196 | .subvendor = PCI_ANY_ID, | ||
1197 | .subdevice = PCI_ANY_ID, | ||
1198 | .setup = skip_tx_en_setup, | ||
1199 | }, | ||
1200 | { | ||
1201 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1202 | .device = PCI_DEVICE_ID_INTEL_82573E_SOL, | ||
1203 | .subvendor = PCI_ANY_ID, | ||
1204 | .subdevice = PCI_ANY_ID, | ||
1205 | .setup = skip_tx_en_setup, | ||
1206 | }, | ||
1207 | { | ||
1208 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1209 | .device = PCI_DEVICE_ID_INTEL_CE4100_UART, | ||
1210 | .subvendor = PCI_ANY_ID, | ||
1211 | .subdevice = PCI_ANY_ID, | ||
1212 | .setup = ce4100_serial_setup, | ||
1213 | }, | ||
1214 | /* | ||
1215 | * ITE | ||
1216 | */ | ||
1217 | { | ||
1218 | .vendor = PCI_VENDOR_ID_ITE, | ||
1219 | .device = PCI_DEVICE_ID_ITE_8872, | ||
1220 | .subvendor = PCI_ANY_ID, | ||
1221 | .subdevice = PCI_ANY_ID, | ||
1222 | .init = pci_ite887x_init, | ||
1223 | .setup = pci_default_setup, | ||
1224 | .exit = __devexit_p(pci_ite887x_exit), | ||
1225 | }, | ||
1226 | /* | ||
1227 | * National Instruments | ||
1228 | */ | ||
1229 | { | ||
1230 | .vendor = PCI_VENDOR_ID_NI, | ||
1231 | .device = PCI_DEVICE_ID_NI_PCI23216, | ||
1232 | .subvendor = PCI_ANY_ID, | ||
1233 | .subdevice = PCI_ANY_ID, | ||
1234 | .init = pci_ni8420_init, | ||
1235 | .setup = pci_default_setup, | ||
1236 | .exit = __devexit_p(pci_ni8420_exit), | ||
1237 | }, | ||
1238 | { | ||
1239 | .vendor = PCI_VENDOR_ID_NI, | ||
1240 | .device = PCI_DEVICE_ID_NI_PCI2328, | ||
1241 | .subvendor = PCI_ANY_ID, | ||
1242 | .subdevice = PCI_ANY_ID, | ||
1243 | .init = pci_ni8420_init, | ||
1244 | .setup = pci_default_setup, | ||
1245 | .exit = __devexit_p(pci_ni8420_exit), | ||
1246 | }, | ||
1247 | { | ||
1248 | .vendor = PCI_VENDOR_ID_NI, | ||
1249 | .device = PCI_DEVICE_ID_NI_PCI2324, | ||
1250 | .subvendor = PCI_ANY_ID, | ||
1251 | .subdevice = PCI_ANY_ID, | ||
1252 | .init = pci_ni8420_init, | ||
1253 | .setup = pci_default_setup, | ||
1254 | .exit = __devexit_p(pci_ni8420_exit), | ||
1255 | }, | ||
1256 | { | ||
1257 | .vendor = PCI_VENDOR_ID_NI, | ||
1258 | .device = PCI_DEVICE_ID_NI_PCI2322, | ||
1259 | .subvendor = PCI_ANY_ID, | ||
1260 | .subdevice = PCI_ANY_ID, | ||
1261 | .init = pci_ni8420_init, | ||
1262 | .setup = pci_default_setup, | ||
1263 | .exit = __devexit_p(pci_ni8420_exit), | ||
1264 | }, | ||
1265 | { | ||
1266 | .vendor = PCI_VENDOR_ID_NI, | ||
1267 | .device = PCI_DEVICE_ID_NI_PCI2324I, | ||
1268 | .subvendor = PCI_ANY_ID, | ||
1269 | .subdevice = PCI_ANY_ID, | ||
1270 | .init = pci_ni8420_init, | ||
1271 | .setup = pci_default_setup, | ||
1272 | .exit = __devexit_p(pci_ni8420_exit), | ||
1273 | }, | ||
1274 | { | ||
1275 | .vendor = PCI_VENDOR_ID_NI, | ||
1276 | .device = PCI_DEVICE_ID_NI_PCI2322I, | ||
1277 | .subvendor = PCI_ANY_ID, | ||
1278 | .subdevice = PCI_ANY_ID, | ||
1279 | .init = pci_ni8420_init, | ||
1280 | .setup = pci_default_setup, | ||
1281 | .exit = __devexit_p(pci_ni8420_exit), | ||
1282 | }, | ||
1283 | { | ||
1284 | .vendor = PCI_VENDOR_ID_NI, | ||
1285 | .device = PCI_DEVICE_ID_NI_PXI8420_23216, | ||
1286 | .subvendor = PCI_ANY_ID, | ||
1287 | .subdevice = PCI_ANY_ID, | ||
1288 | .init = pci_ni8420_init, | ||
1289 | .setup = pci_default_setup, | ||
1290 | .exit = __devexit_p(pci_ni8420_exit), | ||
1291 | }, | ||
1292 | { | ||
1293 | .vendor = PCI_VENDOR_ID_NI, | ||
1294 | .device = PCI_DEVICE_ID_NI_PXI8420_2328, | ||
1295 | .subvendor = PCI_ANY_ID, | ||
1296 | .subdevice = PCI_ANY_ID, | ||
1297 | .init = pci_ni8420_init, | ||
1298 | .setup = pci_default_setup, | ||
1299 | .exit = __devexit_p(pci_ni8420_exit), | ||
1300 | }, | ||
1301 | { | ||
1302 | .vendor = PCI_VENDOR_ID_NI, | ||
1303 | .device = PCI_DEVICE_ID_NI_PXI8420_2324, | ||
1304 | .subvendor = PCI_ANY_ID, | ||
1305 | .subdevice = PCI_ANY_ID, | ||
1306 | .init = pci_ni8420_init, | ||
1307 | .setup = pci_default_setup, | ||
1308 | .exit = __devexit_p(pci_ni8420_exit), | ||
1309 | }, | ||
1310 | { | ||
1311 | .vendor = PCI_VENDOR_ID_NI, | ||
1312 | .device = PCI_DEVICE_ID_NI_PXI8420_2322, | ||
1313 | .subvendor = PCI_ANY_ID, | ||
1314 | .subdevice = PCI_ANY_ID, | ||
1315 | .init = pci_ni8420_init, | ||
1316 | .setup = pci_default_setup, | ||
1317 | .exit = __devexit_p(pci_ni8420_exit), | ||
1318 | }, | ||
1319 | { | ||
1320 | .vendor = PCI_VENDOR_ID_NI, | ||
1321 | .device = PCI_DEVICE_ID_NI_PXI8422_2324, | ||
1322 | .subvendor = PCI_ANY_ID, | ||
1323 | .subdevice = PCI_ANY_ID, | ||
1324 | .init = pci_ni8420_init, | ||
1325 | .setup = pci_default_setup, | ||
1326 | .exit = __devexit_p(pci_ni8420_exit), | ||
1327 | }, | ||
1328 | { | ||
1329 | .vendor = PCI_VENDOR_ID_NI, | ||
1330 | .device = PCI_DEVICE_ID_NI_PXI8422_2322, | ||
1331 | .subvendor = PCI_ANY_ID, | ||
1332 | .subdevice = PCI_ANY_ID, | ||
1333 | .init = pci_ni8420_init, | ||
1334 | .setup = pci_default_setup, | ||
1335 | .exit = __devexit_p(pci_ni8420_exit), | ||
1336 | }, | ||
1337 | { | ||
1338 | .vendor = PCI_VENDOR_ID_NI, | ||
1339 | .device = PCI_ANY_ID, | ||
1340 | .subvendor = PCI_ANY_ID, | ||
1341 | .subdevice = PCI_ANY_ID, | ||
1342 | .init = pci_ni8430_init, | ||
1343 | .setup = pci_ni8430_setup, | ||
1344 | .exit = __devexit_p(pci_ni8430_exit), | ||
1345 | }, | ||
1346 | /* | ||
1347 | * Panacom | ||
1348 | */ | ||
1349 | { | ||
1350 | .vendor = PCI_VENDOR_ID_PANACOM, | ||
1351 | .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, | ||
1352 | .subvendor = PCI_ANY_ID, | ||
1353 | .subdevice = PCI_ANY_ID, | ||
1354 | .init = pci_plx9050_init, | ||
1355 | .setup = pci_default_setup, | ||
1356 | .exit = __devexit_p(pci_plx9050_exit), | ||
1357 | }, | ||
1358 | { | ||
1359 | .vendor = PCI_VENDOR_ID_PANACOM, | ||
1360 | .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, | ||
1361 | .subvendor = PCI_ANY_ID, | ||
1362 | .subdevice = PCI_ANY_ID, | ||
1363 | .init = pci_plx9050_init, | ||
1364 | .setup = pci_default_setup, | ||
1365 | .exit = __devexit_p(pci_plx9050_exit), | ||
1366 | }, | ||
1367 | /* | ||
1368 | * PLX | ||
1369 | */ | ||
1370 | { | ||
1371 | .vendor = PCI_VENDOR_ID_PLX, | ||
1372 | .device = PCI_DEVICE_ID_PLX_9030, | ||
1373 | .subvendor = PCI_SUBVENDOR_ID_PERLE, | ||
1374 | .subdevice = PCI_ANY_ID, | ||
1375 | .setup = pci_default_setup, | ||
1376 | }, | ||
1377 | { | ||
1378 | .vendor = PCI_VENDOR_ID_PLX, | ||
1379 | .device = PCI_DEVICE_ID_PLX_9050, | ||
1380 | .subvendor = PCI_SUBVENDOR_ID_EXSYS, | ||
1381 | .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, | ||
1382 | .init = pci_plx9050_init, | ||
1383 | .setup = pci_default_setup, | ||
1384 | .exit = __devexit_p(pci_plx9050_exit), | ||
1385 | }, | ||
1386 | { | ||
1387 | .vendor = PCI_VENDOR_ID_PLX, | ||
1388 | .device = PCI_DEVICE_ID_PLX_9050, | ||
1389 | .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, | ||
1390 | .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, | ||
1391 | .init = pci_plx9050_init, | ||
1392 | .setup = pci_default_setup, | ||
1393 | .exit = __devexit_p(pci_plx9050_exit), | ||
1394 | }, | ||
1395 | { | ||
1396 | .vendor = PCI_VENDOR_ID_PLX, | ||
1397 | .device = PCI_DEVICE_ID_PLX_9050, | ||
1398 | .subvendor = PCI_VENDOR_ID_PLX, | ||
1399 | .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584, | ||
1400 | .init = pci_plx9050_init, | ||
1401 | .setup = pci_default_setup, | ||
1402 | .exit = __devexit_p(pci_plx9050_exit), | ||
1403 | }, | ||
1404 | { | ||
1405 | .vendor = PCI_VENDOR_ID_PLX, | ||
1406 | .device = PCI_DEVICE_ID_PLX_ROMULUS, | ||
1407 | .subvendor = PCI_VENDOR_ID_PLX, | ||
1408 | .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, | ||
1409 | .init = pci_plx9050_init, | ||
1410 | .setup = pci_default_setup, | ||
1411 | .exit = __devexit_p(pci_plx9050_exit), | ||
1412 | }, | ||
1413 | /* | ||
1414 | * SBS Technologies, Inc., PMC-OCTALPRO 232 | ||
1415 | */ | ||
1416 | { | ||
1417 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | ||
1418 | .device = PCI_DEVICE_ID_OCTPRO, | ||
1419 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | ||
1420 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, | ||
1421 | .init = sbs_init, | ||
1422 | .setup = sbs_setup, | ||
1423 | .exit = __devexit_p(sbs_exit), | ||
1424 | }, | ||
1425 | /* | ||
1426 | * SBS Technologies, Inc., PMC-OCTALPRO 422 | ||
1427 | */ | ||
1428 | { | ||
1429 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | ||
1430 | .device = PCI_DEVICE_ID_OCTPRO, | ||
1431 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | ||
1432 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, | ||
1433 | .init = sbs_init, | ||
1434 | .setup = sbs_setup, | ||
1435 | .exit = __devexit_p(sbs_exit), | ||
1436 | }, | ||
1437 | /* | ||
1438 | * SBS Technologies, Inc., P-Octal 232 | ||
1439 | */ | ||
1440 | { | ||
1441 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | ||
1442 | .device = PCI_DEVICE_ID_OCTPRO, | ||
1443 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | ||
1444 | .subdevice = PCI_SUBDEVICE_ID_POCTAL232, | ||
1445 | .init = sbs_init, | ||
1446 | .setup = sbs_setup, | ||
1447 | .exit = __devexit_p(sbs_exit), | ||
1448 | }, | ||
1449 | /* | ||
1450 | * SBS Technologies, Inc., P-Octal 422 | ||
1451 | */ | ||
1452 | { | ||
1453 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | ||
1454 | .device = PCI_DEVICE_ID_OCTPRO, | ||
1455 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | ||
1456 | .subdevice = PCI_SUBDEVICE_ID_POCTAL422, | ||
1457 | .init = sbs_init, | ||
1458 | .setup = sbs_setup, | ||
1459 | .exit = __devexit_p(sbs_exit), | ||
1460 | }, | ||
1461 | /* | ||
1462 | * SIIG cards - these may be called via parport_serial | ||
1463 | */ | ||
1464 | { | ||
1465 | .vendor = PCI_VENDOR_ID_SIIG, | ||
1466 | .device = PCI_ANY_ID, | ||
1467 | .subvendor = PCI_ANY_ID, | ||
1468 | .subdevice = PCI_ANY_ID, | ||
1469 | .init = pci_siig_init, | ||
1470 | .setup = pci_siig_setup, | ||
1471 | }, | ||
1472 | /* | ||
1473 | * Titan cards | ||
1474 | */ | ||
1475 | { | ||
1476 | .vendor = PCI_VENDOR_ID_TITAN, | ||
1477 | .device = PCI_DEVICE_ID_TITAN_400L, | ||
1478 | .subvendor = PCI_ANY_ID, | ||
1479 | .subdevice = PCI_ANY_ID, | ||
1480 | .setup = titan_400l_800l_setup, | ||
1481 | }, | ||
1482 | { | ||
1483 | .vendor = PCI_VENDOR_ID_TITAN, | ||
1484 | .device = PCI_DEVICE_ID_TITAN_800L, | ||
1485 | .subvendor = PCI_ANY_ID, | ||
1486 | .subdevice = PCI_ANY_ID, | ||
1487 | .setup = titan_400l_800l_setup, | ||
1488 | }, | ||
1489 | /* | ||
1490 | * Timedia cards | ||
1491 | */ | ||
1492 | { | ||
1493 | .vendor = PCI_VENDOR_ID_TIMEDIA, | ||
1494 | .device = PCI_DEVICE_ID_TIMEDIA_1889, | ||
1495 | .subvendor = PCI_VENDOR_ID_TIMEDIA, | ||
1496 | .subdevice = PCI_ANY_ID, | ||
1497 | .probe = pci_timedia_probe, | ||
1498 | .init = pci_timedia_init, | ||
1499 | .setup = pci_timedia_setup, | ||
1500 | }, | ||
1501 | { | ||
1502 | .vendor = PCI_VENDOR_ID_TIMEDIA, | ||
1503 | .device = PCI_ANY_ID, | ||
1504 | .subvendor = PCI_ANY_ID, | ||
1505 | .subdevice = PCI_ANY_ID, | ||
1506 | .setup = pci_timedia_setup, | ||
1507 | }, | ||
1508 | /* | ||
1509 | * Xircom cards | ||
1510 | */ | ||
1511 | { | ||
1512 | .vendor = PCI_VENDOR_ID_XIRCOM, | ||
1513 | .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, | ||
1514 | .subvendor = PCI_ANY_ID, | ||
1515 | .subdevice = PCI_ANY_ID, | ||
1516 | .init = pci_xircom_init, | ||
1517 | .setup = pci_default_setup, | ||
1518 | }, | ||
1519 | /* | ||
1520 | * Netmos cards - these may be called via parport_serial | ||
1521 | */ | ||
1522 | { | ||
1523 | .vendor = PCI_VENDOR_ID_NETMOS, | ||
1524 | .device = PCI_ANY_ID, | ||
1525 | .subvendor = PCI_ANY_ID, | ||
1526 | .subdevice = PCI_ANY_ID, | ||
1527 | .init = pci_netmos_init, | ||
1528 | .setup = pci_netmos_9900_setup, | ||
1529 | }, | ||
1530 | /* | ||
1531 | * For Oxford Semiconductor Tornado based devices | ||
1532 | */ | ||
1533 | { | ||
1534 | .vendor = PCI_VENDOR_ID_OXSEMI, | ||
1535 | .device = PCI_ANY_ID, | ||
1536 | .subvendor = PCI_ANY_ID, | ||
1537 | .subdevice = PCI_ANY_ID, | ||
1538 | .init = pci_oxsemi_tornado_init, | ||
1539 | .setup = pci_default_setup, | ||
1540 | }, | ||
1541 | { | ||
1542 | .vendor = PCI_VENDOR_ID_MAINPINE, | ||
1543 | .device = PCI_ANY_ID, | ||
1544 | .subvendor = PCI_ANY_ID, | ||
1545 | .subdevice = PCI_ANY_ID, | ||
1546 | .init = pci_oxsemi_tornado_init, | ||
1547 | .setup = pci_default_setup, | ||
1548 | }, | ||
1549 | { | ||
1550 | .vendor = PCI_VENDOR_ID_DIGI, | ||
1551 | .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, | ||
1552 | .subvendor = PCI_SUBVENDOR_ID_IBM, | ||
1553 | .subdevice = PCI_ANY_ID, | ||
1554 | .init = pci_oxsemi_tornado_init, | ||
1555 | .setup = pci_default_setup, | ||
1556 | }, | ||
1557 | { | ||
1558 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1559 | .device = 0x8811, | ||
1560 | .init = pci_eg20t_init, | ||
1561 | }, | ||
1562 | { | ||
1563 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1564 | .device = 0x8812, | ||
1565 | .init = pci_eg20t_init, | ||
1566 | }, | ||
1567 | { | ||
1568 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1569 | .device = 0x8813, | ||
1570 | .init = pci_eg20t_init, | ||
1571 | }, | ||
1572 | { | ||
1573 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1574 | .device = 0x8814, | ||
1575 | .init = pci_eg20t_init, | ||
1576 | }, | ||
1577 | { | ||
1578 | .vendor = 0x10DB, | ||
1579 | .device = 0x8027, | ||
1580 | .init = pci_eg20t_init, | ||
1581 | }, | ||
1582 | { | ||
1583 | .vendor = 0x10DB, | ||
1584 | .device = 0x8028, | ||
1585 | .init = pci_eg20t_init, | ||
1586 | }, | ||
1587 | { | ||
1588 | .vendor = 0x10DB, | ||
1589 | .device = 0x8029, | ||
1590 | .init = pci_eg20t_init, | ||
1591 | }, | ||
1592 | { | ||
1593 | .vendor = 0x10DB, | ||
1594 | .device = 0x800C, | ||
1595 | .init = pci_eg20t_init, | ||
1596 | }, | ||
1597 | { | ||
1598 | .vendor = 0x10DB, | ||
1599 | .device = 0x800D, | ||
1600 | .init = pci_eg20t_init, | ||
1601 | }, | ||
1602 | /* | ||
1603 | * Cronyx Omega PCI (PLX-chip based) | ||
1604 | */ | ||
1605 | { | ||
1606 | .vendor = PCI_VENDOR_ID_PLX, | ||
1607 | .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, | ||
1608 | .subvendor = PCI_ANY_ID, | ||
1609 | .subdevice = PCI_ANY_ID, | ||
1610 | .setup = pci_omegapci_setup, | ||
1611 | }, | ||
1612 | /* | ||
1613 | * Default "match everything" terminator entry | ||
1614 | */ | ||
1615 | { | ||
1616 | .vendor = PCI_ANY_ID, | ||
1617 | .device = PCI_ANY_ID, | ||
1618 | .subvendor = PCI_ANY_ID, | ||
1619 | .subdevice = PCI_ANY_ID, | ||
1620 | .setup = pci_default_setup, | ||
1621 | } | ||
1622 | }; | ||
1623 | |||
1624 | static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) | ||
1625 | { | ||
1626 | return quirk_id == PCI_ANY_ID || quirk_id == dev_id; | ||
1627 | } | ||
1628 | |||
1629 | static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) | ||
1630 | { | ||
1631 | struct pci_serial_quirk *quirk; | ||
1632 | |||
1633 | for (quirk = pci_serial_quirks; ; quirk++) | ||
1634 | if (quirk_id_matches(quirk->vendor, dev->vendor) && | ||
1635 | quirk_id_matches(quirk->device, dev->device) && | ||
1636 | quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && | ||
1637 | quirk_id_matches(quirk->subdevice, dev->subsystem_device)) | ||
1638 | break; | ||
1639 | return quirk; | ||
1640 | } | ||
1641 | |||
1642 | static inline int get_pci_irq(struct pci_dev *dev, | ||
1643 | const struct pciserial_board *board) | ||
1644 | { | ||
1645 | if (board->flags & FL_NOIRQ) | ||
1646 | return 0; | ||
1647 | else | ||
1648 | return dev->irq; | ||
1649 | } | ||
1650 | |||
1651 | /* | ||
1652 | * This is the configuration table for all of the PCI serial boards | ||
1653 | * which we support. It is directly indexed by the pci_board_num_t enum | ||
1654 | * value, which is encoded in the pci_device_id PCI probe table's | ||
1655 | * driver_data member. | ||
1656 | * | ||
1657 | * The makeup of these names are: | ||
1658 | * pbn_bn{_bt}_n_baud{_offsetinhex} | ||
1659 | * | ||
1660 | * bn = PCI BAR number | ||
1661 | * bt = Index using PCI BARs | ||
1662 | * n = number of serial ports | ||
1663 | * baud = baud rate | ||
1664 | * offsetinhex = offset for each sequential port (in hex) | ||
1665 | * | ||
1666 | * This table is sorted by (in order): bn, bt, baud, offsetindex, n. | ||
1667 | * | ||
1668 | * Please note: in theory if n = 1, _bt infix should make no difference. | ||
1669 | * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 | ||
1670 | */ | ||
1671 | enum pci_board_num_t { | ||
1672 | pbn_default = 0, | ||
1673 | |||
1674 | pbn_b0_1_115200, | ||
1675 | pbn_b0_2_115200, | ||
1676 | pbn_b0_4_115200, | ||
1677 | pbn_b0_5_115200, | ||
1678 | pbn_b0_8_115200, | ||
1679 | |||
1680 | pbn_b0_1_921600, | ||
1681 | pbn_b0_2_921600, | ||
1682 | pbn_b0_4_921600, | ||
1683 | |||
1684 | pbn_b0_2_1130000, | ||
1685 | |||
1686 | pbn_b0_4_1152000, | ||
1687 | |||
1688 | pbn_b0_2_1843200, | ||
1689 | pbn_b0_4_1843200, | ||
1690 | |||
1691 | pbn_b0_2_1843200_200, | ||
1692 | pbn_b0_4_1843200_200, | ||
1693 | pbn_b0_8_1843200_200, | ||
1694 | |||
1695 | pbn_b0_1_4000000, | ||
1696 | |||
1697 | pbn_b0_bt_1_115200, | ||
1698 | pbn_b0_bt_2_115200, | ||
1699 | pbn_b0_bt_4_115200, | ||
1700 | pbn_b0_bt_8_115200, | ||
1701 | |||
1702 | pbn_b0_bt_1_460800, | ||
1703 | pbn_b0_bt_2_460800, | ||
1704 | pbn_b0_bt_4_460800, | ||
1705 | |||
1706 | pbn_b0_bt_1_921600, | ||
1707 | pbn_b0_bt_2_921600, | ||
1708 | pbn_b0_bt_4_921600, | ||
1709 | pbn_b0_bt_8_921600, | ||
1710 | |||
1711 | pbn_b1_1_115200, | ||
1712 | pbn_b1_2_115200, | ||
1713 | pbn_b1_4_115200, | ||
1714 | pbn_b1_8_115200, | ||
1715 | pbn_b1_16_115200, | ||
1716 | |||
1717 | pbn_b1_1_921600, | ||
1718 | pbn_b1_2_921600, | ||
1719 | pbn_b1_4_921600, | ||
1720 | pbn_b1_8_921600, | ||
1721 | |||
1722 | pbn_b1_2_1250000, | ||
1723 | |||
1724 | pbn_b1_bt_1_115200, | ||
1725 | pbn_b1_bt_2_115200, | ||
1726 | pbn_b1_bt_4_115200, | ||
1727 | |||
1728 | pbn_b1_bt_2_921600, | ||
1729 | |||
1730 | pbn_b1_1_1382400, | ||
1731 | pbn_b1_2_1382400, | ||
1732 | pbn_b1_4_1382400, | ||
1733 | pbn_b1_8_1382400, | ||
1734 | |||
1735 | pbn_b2_1_115200, | ||
1736 | pbn_b2_2_115200, | ||
1737 | pbn_b2_4_115200, | ||
1738 | pbn_b2_8_115200, | ||
1739 | |||
1740 | pbn_b2_1_460800, | ||
1741 | pbn_b2_4_460800, | ||
1742 | pbn_b2_8_460800, | ||
1743 | pbn_b2_16_460800, | ||
1744 | |||
1745 | pbn_b2_1_921600, | ||
1746 | pbn_b2_4_921600, | ||
1747 | pbn_b2_8_921600, | ||
1748 | |||
1749 | pbn_b2_8_1152000, | ||
1750 | |||
1751 | pbn_b2_bt_1_115200, | ||
1752 | pbn_b2_bt_2_115200, | ||
1753 | pbn_b2_bt_4_115200, | ||
1754 | |||
1755 | pbn_b2_bt_2_921600, | ||
1756 | pbn_b2_bt_4_921600, | ||
1757 | |||
1758 | pbn_b3_2_115200, | ||
1759 | pbn_b3_4_115200, | ||
1760 | pbn_b3_8_115200, | ||
1761 | |||
1762 | pbn_b4_bt_2_921600, | ||
1763 | pbn_b4_bt_4_921600, | ||
1764 | pbn_b4_bt_8_921600, | ||
1765 | |||
1766 | /* | ||
1767 | * Board-specific versions. | ||
1768 | */ | ||
1769 | pbn_panacom, | ||
1770 | pbn_panacom2, | ||
1771 | pbn_panacom4, | ||
1772 | pbn_exsys_4055, | ||
1773 | pbn_plx_romulus, | ||
1774 | pbn_oxsemi, | ||
1775 | pbn_oxsemi_1_4000000, | ||
1776 | pbn_oxsemi_2_4000000, | ||
1777 | pbn_oxsemi_4_4000000, | ||
1778 | pbn_oxsemi_8_4000000, | ||
1779 | pbn_intel_i960, | ||
1780 | pbn_sgi_ioc3, | ||
1781 | pbn_computone_4, | ||
1782 | pbn_computone_6, | ||
1783 | pbn_computone_8, | ||
1784 | pbn_sbsxrsio, | ||
1785 | pbn_exar_XR17C152, | ||
1786 | pbn_exar_XR17C154, | ||
1787 | pbn_exar_XR17C158, | ||
1788 | pbn_exar_ibm_saturn, | ||
1789 | pbn_pasemi_1682M, | ||
1790 | pbn_ni8430_2, | ||
1791 | pbn_ni8430_4, | ||
1792 | pbn_ni8430_8, | ||
1793 | pbn_ni8430_16, | ||
1794 | pbn_ADDIDATA_PCIe_1_3906250, | ||
1795 | pbn_ADDIDATA_PCIe_2_3906250, | ||
1796 | pbn_ADDIDATA_PCIe_4_3906250, | ||
1797 | pbn_ADDIDATA_PCIe_8_3906250, | ||
1798 | pbn_ce4100_1_115200, | ||
1799 | pbn_omegapci, | ||
1800 | pbn_NETMOS9900_2s_115200, | ||
1801 | }; | ||
1802 | |||
1803 | /* | ||
1804 | * uart_offset - the space between channels | ||
1805 | * reg_shift - describes how the UART registers are mapped | ||
1806 | * to PCI memory by the card. | ||
1807 | * For example IER register on SBS, Inc. PMC-OctPro is located at | ||
1808 | * offset 0x10 from the UART base, while UART_IER is defined as 1 | ||
1809 | * in include/linux/serial_reg.h, | ||
1810 | * see first lines of serial_in() and serial_out() in 8250.c | ||
1811 | */ | ||
1812 | |||
1813 | static struct pciserial_board pci_boards[] __devinitdata = { | ||
1814 | [pbn_default] = { | ||
1815 | .flags = FL_BASE0, | ||
1816 | .num_ports = 1, | ||
1817 | .base_baud = 115200, | ||
1818 | .uart_offset = 8, | ||
1819 | }, | ||
1820 | [pbn_b0_1_115200] = { | ||
1821 | .flags = FL_BASE0, | ||
1822 | .num_ports = 1, | ||
1823 | .base_baud = 115200, | ||
1824 | .uart_offset = 8, | ||
1825 | }, | ||
1826 | [pbn_b0_2_115200] = { | ||
1827 | .flags = FL_BASE0, | ||
1828 | .num_ports = 2, | ||
1829 | .base_baud = 115200, | ||
1830 | .uart_offset = 8, | ||
1831 | }, | ||
1832 | [pbn_b0_4_115200] = { | ||
1833 | .flags = FL_BASE0, | ||
1834 | .num_ports = 4, | ||
1835 | .base_baud = 115200, | ||
1836 | .uart_offset = 8, | ||
1837 | }, | ||
1838 | [pbn_b0_5_115200] = { | ||
1839 | .flags = FL_BASE0, | ||
1840 | .num_ports = 5, | ||
1841 | .base_baud = 115200, | ||
1842 | .uart_offset = 8, | ||
1843 | }, | ||
1844 | [pbn_b0_8_115200] = { | ||
1845 | .flags = FL_BASE0, | ||
1846 | .num_ports = 8, | ||
1847 | .base_baud = 115200, | ||
1848 | .uart_offset = 8, | ||
1849 | }, | ||
1850 | [pbn_b0_1_921600] = { | ||
1851 | .flags = FL_BASE0, | ||
1852 | .num_ports = 1, | ||
1853 | .base_baud = 921600, | ||
1854 | .uart_offset = 8, | ||
1855 | }, | ||
1856 | [pbn_b0_2_921600] = { | ||
1857 | .flags = FL_BASE0, | ||
1858 | .num_ports = 2, | ||
1859 | .base_baud = 921600, | ||
1860 | .uart_offset = 8, | ||
1861 | }, | ||
1862 | [pbn_b0_4_921600] = { | ||
1863 | .flags = FL_BASE0, | ||
1864 | .num_ports = 4, | ||
1865 | .base_baud = 921600, | ||
1866 | .uart_offset = 8, | ||
1867 | }, | ||
1868 | |||
1869 | [pbn_b0_2_1130000] = { | ||
1870 | .flags = FL_BASE0, | ||
1871 | .num_ports = 2, | ||
1872 | .base_baud = 1130000, | ||
1873 | .uart_offset = 8, | ||
1874 | }, | ||
1875 | |||
1876 | [pbn_b0_4_1152000] = { | ||
1877 | .flags = FL_BASE0, | ||
1878 | .num_ports = 4, | ||
1879 | .base_baud = 1152000, | ||
1880 | .uart_offset = 8, | ||
1881 | }, | ||
1882 | |||
1883 | [pbn_b0_2_1843200] = { | ||
1884 | .flags = FL_BASE0, | ||
1885 | .num_ports = 2, | ||
1886 | .base_baud = 1843200, | ||
1887 | .uart_offset = 8, | ||
1888 | }, | ||
1889 | [pbn_b0_4_1843200] = { | ||
1890 | .flags = FL_BASE0, | ||
1891 | .num_ports = 4, | ||
1892 | .base_baud = 1843200, | ||
1893 | .uart_offset = 8, | ||
1894 | }, | ||
1895 | |||
1896 | [pbn_b0_2_1843200_200] = { | ||
1897 | .flags = FL_BASE0, | ||
1898 | .num_ports = 2, | ||
1899 | .base_baud = 1843200, | ||
1900 | .uart_offset = 0x200, | ||
1901 | }, | ||
1902 | [pbn_b0_4_1843200_200] = { | ||
1903 | .flags = FL_BASE0, | ||
1904 | .num_ports = 4, | ||
1905 | .base_baud = 1843200, | ||
1906 | .uart_offset = 0x200, | ||
1907 | }, | ||
1908 | [pbn_b0_8_1843200_200] = { | ||
1909 | .flags = FL_BASE0, | ||
1910 | .num_ports = 8, | ||
1911 | .base_baud = 1843200, | ||
1912 | .uart_offset = 0x200, | ||
1913 | }, | ||
1914 | [pbn_b0_1_4000000] = { | ||
1915 | .flags = FL_BASE0, | ||
1916 | .num_ports = 1, | ||
1917 | .base_baud = 4000000, | ||
1918 | .uart_offset = 8, | ||
1919 | }, | ||
1920 | |||
1921 | [pbn_b0_bt_1_115200] = { | ||
1922 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1923 | .num_ports = 1, | ||
1924 | .base_baud = 115200, | ||
1925 | .uart_offset = 8, | ||
1926 | }, | ||
1927 | [pbn_b0_bt_2_115200] = { | ||
1928 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1929 | .num_ports = 2, | ||
1930 | .base_baud = 115200, | ||
1931 | .uart_offset = 8, | ||
1932 | }, | ||
1933 | [pbn_b0_bt_4_115200] = { | ||
1934 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1935 | .num_ports = 4, | ||
1936 | .base_baud = 115200, | ||
1937 | .uart_offset = 8, | ||
1938 | }, | ||
1939 | [pbn_b0_bt_8_115200] = { | ||
1940 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1941 | .num_ports = 8, | ||
1942 | .base_baud = 115200, | ||
1943 | .uart_offset = 8, | ||
1944 | }, | ||
1945 | |||
1946 | [pbn_b0_bt_1_460800] = { | ||
1947 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1948 | .num_ports = 1, | ||
1949 | .base_baud = 460800, | ||
1950 | .uart_offset = 8, | ||
1951 | }, | ||
1952 | [pbn_b0_bt_2_460800] = { | ||
1953 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1954 | .num_ports = 2, | ||
1955 | .base_baud = 460800, | ||
1956 | .uart_offset = 8, | ||
1957 | }, | ||
1958 | [pbn_b0_bt_4_460800] = { | ||
1959 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1960 | .num_ports = 4, | ||
1961 | .base_baud = 460800, | ||
1962 | .uart_offset = 8, | ||
1963 | }, | ||
1964 | |||
1965 | [pbn_b0_bt_1_921600] = { | ||
1966 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1967 | .num_ports = 1, | ||
1968 | .base_baud = 921600, | ||
1969 | .uart_offset = 8, | ||
1970 | }, | ||
1971 | [pbn_b0_bt_2_921600] = { | ||
1972 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1973 | .num_ports = 2, | ||
1974 | .base_baud = 921600, | ||
1975 | .uart_offset = 8, | ||
1976 | }, | ||
1977 | [pbn_b0_bt_4_921600] = { | ||
1978 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1979 | .num_ports = 4, | ||
1980 | .base_baud = 921600, | ||
1981 | .uart_offset = 8, | ||
1982 | }, | ||
1983 | [pbn_b0_bt_8_921600] = { | ||
1984 | .flags = FL_BASE0|FL_BASE_BARS, | ||
1985 | .num_ports = 8, | ||
1986 | .base_baud = 921600, | ||
1987 | .uart_offset = 8, | ||
1988 | }, | ||
1989 | |||
1990 | [pbn_b1_1_115200] = { | ||
1991 | .flags = FL_BASE1, | ||
1992 | .num_ports = 1, | ||
1993 | .base_baud = 115200, | ||
1994 | .uart_offset = 8, | ||
1995 | }, | ||
1996 | [pbn_b1_2_115200] = { | ||
1997 | .flags = FL_BASE1, | ||
1998 | .num_ports = 2, | ||
1999 | .base_baud = 115200, | ||
2000 | .uart_offset = 8, | ||
2001 | }, | ||
2002 | [pbn_b1_4_115200] = { | ||
2003 | .flags = FL_BASE1, | ||
2004 | .num_ports = 4, | ||
2005 | .base_baud = 115200, | ||
2006 | .uart_offset = 8, | ||
2007 | }, | ||
2008 | [pbn_b1_8_115200] = { | ||
2009 | .flags = FL_BASE1, | ||
2010 | .num_ports = 8, | ||
2011 | .base_baud = 115200, | ||
2012 | .uart_offset = 8, | ||
2013 | }, | ||
2014 | [pbn_b1_16_115200] = { | ||
2015 | .flags = FL_BASE1, | ||
2016 | .num_ports = 16, | ||
2017 | .base_baud = 115200, | ||
2018 | .uart_offset = 8, | ||
2019 | }, | ||
2020 | |||
2021 | [pbn_b1_1_921600] = { | ||
2022 | .flags = FL_BASE1, | ||
2023 | .num_ports = 1, | ||
2024 | .base_baud = 921600, | ||
2025 | .uart_offset = 8, | ||
2026 | }, | ||
2027 | [pbn_b1_2_921600] = { | ||
2028 | .flags = FL_BASE1, | ||
2029 | .num_ports = 2, | ||
2030 | .base_baud = 921600, | ||
2031 | .uart_offset = 8, | ||
2032 | }, | ||
2033 | [pbn_b1_4_921600] = { | ||
2034 | .flags = FL_BASE1, | ||
2035 | .num_ports = 4, | ||
2036 | .base_baud = 921600, | ||
2037 | .uart_offset = 8, | ||
2038 | }, | ||
2039 | [pbn_b1_8_921600] = { | ||
2040 | .flags = FL_BASE1, | ||
2041 | .num_ports = 8, | ||
2042 | .base_baud = 921600, | ||
2043 | .uart_offset = 8, | ||
2044 | }, | ||
2045 | [pbn_b1_2_1250000] = { | ||
2046 | .flags = FL_BASE1, | ||
2047 | .num_ports = 2, | ||
2048 | .base_baud = 1250000, | ||
2049 | .uart_offset = 8, | ||
2050 | }, | ||
2051 | |||
2052 | [pbn_b1_bt_1_115200] = { | ||
2053 | .flags = FL_BASE1|FL_BASE_BARS, | ||
2054 | .num_ports = 1, | ||
2055 | .base_baud = 115200, | ||
2056 | .uart_offset = 8, | ||
2057 | }, | ||
2058 | [pbn_b1_bt_2_115200] = { | ||
2059 | .flags = FL_BASE1|FL_BASE_BARS, | ||
2060 | .num_ports = 2, | ||
2061 | .base_baud = 115200, | ||
2062 | .uart_offset = 8, | ||
2063 | }, | ||
2064 | [pbn_b1_bt_4_115200] = { | ||
2065 | .flags = FL_BASE1|FL_BASE_BARS, | ||
2066 | .num_ports = 4, | ||
2067 | .base_baud = 115200, | ||
2068 | .uart_offset = 8, | ||
2069 | }, | ||
2070 | |||
2071 | [pbn_b1_bt_2_921600] = { | ||
2072 | .flags = FL_BASE1|FL_BASE_BARS, | ||
2073 | .num_ports = 2, | ||
2074 | .base_baud = 921600, | ||
2075 | .uart_offset = 8, | ||
2076 | }, | ||
2077 | |||
2078 | [pbn_b1_1_1382400] = { | ||
2079 | .flags = FL_BASE1, | ||
2080 | .num_ports = 1, | ||
2081 | .base_baud = 1382400, | ||
2082 | .uart_offset = 8, | ||
2083 | }, | ||
2084 | [pbn_b1_2_1382400] = { | ||
2085 | .flags = FL_BASE1, | ||
2086 | .num_ports = 2, | ||
2087 | .base_baud = 1382400, | ||
2088 | .uart_offset = 8, | ||
2089 | }, | ||
2090 | [pbn_b1_4_1382400] = { | ||
2091 | .flags = FL_BASE1, | ||
2092 | .num_ports = 4, | ||
2093 | .base_baud = 1382400, | ||
2094 | .uart_offset = 8, | ||
2095 | }, | ||
2096 | [pbn_b1_8_1382400] = { | ||
2097 | .flags = FL_BASE1, | ||
2098 | .num_ports = 8, | ||
2099 | .base_baud = 1382400, | ||
2100 | .uart_offset = 8, | ||
2101 | }, | ||
2102 | |||
2103 | [pbn_b2_1_115200] = { | ||
2104 | .flags = FL_BASE2, | ||
2105 | .num_ports = 1, | ||
2106 | .base_baud = 115200, | ||
2107 | .uart_offset = 8, | ||
2108 | }, | ||
2109 | [pbn_b2_2_115200] = { | ||
2110 | .flags = FL_BASE2, | ||
2111 | .num_ports = 2, | ||
2112 | .base_baud = 115200, | ||
2113 | .uart_offset = 8, | ||
2114 | }, | ||
2115 | [pbn_b2_4_115200] = { | ||
2116 | .flags = FL_BASE2, | ||
2117 | .num_ports = 4, | ||
2118 | .base_baud = 115200, | ||
2119 | .uart_offset = 8, | ||
2120 | }, | ||
2121 | [pbn_b2_8_115200] = { | ||
2122 | .flags = FL_BASE2, | ||
2123 | .num_ports = 8, | ||
2124 | .base_baud = 115200, | ||
2125 | .uart_offset = 8, | ||
2126 | }, | ||
2127 | |||
2128 | [pbn_b2_1_460800] = { | ||
2129 | .flags = FL_BASE2, | ||
2130 | .num_ports = 1, | ||
2131 | .base_baud = 460800, | ||
2132 | .uart_offset = 8, | ||
2133 | }, | ||
2134 | [pbn_b2_4_460800] = { | ||
2135 | .flags = FL_BASE2, | ||
2136 | .num_ports = 4, | ||
2137 | .base_baud = 460800, | ||
2138 | .uart_offset = 8, | ||
2139 | }, | ||
2140 | [pbn_b2_8_460800] = { | ||
2141 | .flags = FL_BASE2, | ||
2142 | .num_ports = 8, | ||
2143 | .base_baud = 460800, | ||
2144 | .uart_offset = 8, | ||
2145 | }, | ||
2146 | [pbn_b2_16_460800] = { | ||
2147 | .flags = FL_BASE2, | ||
2148 | .num_ports = 16, | ||
2149 | .base_baud = 460800, | ||
2150 | .uart_offset = 8, | ||
2151 | }, | ||
2152 | |||
2153 | [pbn_b2_1_921600] = { | ||
2154 | .flags = FL_BASE2, | ||
2155 | .num_ports = 1, | ||
2156 | .base_baud = 921600, | ||
2157 | .uart_offset = 8, | ||
2158 | }, | ||
2159 | [pbn_b2_4_921600] = { | ||
2160 | .flags = FL_BASE2, | ||
2161 | .num_ports = 4, | ||
2162 | .base_baud = 921600, | ||
2163 | .uart_offset = 8, | ||
2164 | }, | ||
2165 | [pbn_b2_8_921600] = { | ||
2166 | .flags = FL_BASE2, | ||
2167 | .num_ports = 8, | ||
2168 | .base_baud = 921600, | ||
2169 | .uart_offset = 8, | ||
2170 | }, | ||
2171 | |||
2172 | [pbn_b2_8_1152000] = { | ||
2173 | .flags = FL_BASE2, | ||
2174 | .num_ports = 8, | ||
2175 | .base_baud = 1152000, | ||
2176 | .uart_offset = 8, | ||
2177 | }, | ||
2178 | |||
2179 | [pbn_b2_bt_1_115200] = { | ||
2180 | .flags = FL_BASE2|FL_BASE_BARS, | ||
2181 | .num_ports = 1, | ||
2182 | .base_baud = 115200, | ||
2183 | .uart_offset = 8, | ||
2184 | }, | ||
2185 | [pbn_b2_bt_2_115200] = { | ||
2186 | .flags = FL_BASE2|FL_BASE_BARS, | ||
2187 | .num_ports = 2, | ||
2188 | .base_baud = 115200, | ||
2189 | .uart_offset = 8, | ||
2190 | }, | ||
2191 | [pbn_b2_bt_4_115200] = { | ||
2192 | .flags = FL_BASE2|FL_BASE_BARS, | ||
2193 | .num_ports = 4, | ||
2194 | .base_baud = 115200, | ||
2195 | .uart_offset = 8, | ||
2196 | }, | ||
2197 | |||
2198 | [pbn_b2_bt_2_921600] = { | ||
2199 | .flags = FL_BASE2|FL_BASE_BARS, | ||
2200 | .num_ports = 2, | ||
2201 | .base_baud = 921600, | ||
2202 | .uart_offset = 8, | ||
2203 | }, | ||
2204 | [pbn_b2_bt_4_921600] = { | ||
2205 | .flags = FL_BASE2|FL_BASE_BARS, | ||
2206 | .num_ports = 4, | ||
2207 | .base_baud = 921600, | ||
2208 | .uart_offset = 8, | ||
2209 | }, | ||
2210 | |||
2211 | [pbn_b3_2_115200] = { | ||
2212 | .flags = FL_BASE3, | ||
2213 | .num_ports = 2, | ||
2214 | .base_baud = 115200, | ||
2215 | .uart_offset = 8, | ||
2216 | }, | ||
2217 | [pbn_b3_4_115200] = { | ||
2218 | .flags = FL_BASE3, | ||
2219 | .num_ports = 4, | ||
2220 | .base_baud = 115200, | ||
2221 | .uart_offset = 8, | ||
2222 | }, | ||
2223 | [pbn_b3_8_115200] = { | ||
2224 | .flags = FL_BASE3, | ||
2225 | .num_ports = 8, | ||
2226 | .base_baud = 115200, | ||
2227 | .uart_offset = 8, | ||
2228 | }, | ||
2229 | |||
2230 | [pbn_b4_bt_2_921600] = { | ||
2231 | .flags = FL_BASE4, | ||
2232 | .num_ports = 2, | ||
2233 | .base_baud = 921600, | ||
2234 | .uart_offset = 8, | ||
2235 | }, | ||
2236 | [pbn_b4_bt_4_921600] = { | ||
2237 | .flags = FL_BASE4, | ||
2238 | .num_ports = 4, | ||
2239 | .base_baud = 921600, | ||
2240 | .uart_offset = 8, | ||
2241 | }, | ||
2242 | [pbn_b4_bt_8_921600] = { | ||
2243 | .flags = FL_BASE4, | ||
2244 | .num_ports = 8, | ||
2245 | .base_baud = 921600, | ||
2246 | .uart_offset = 8, | ||
2247 | }, | ||
2248 | |||
2249 | /* | ||
2250 | * Entries following this are board-specific. | ||
2251 | */ | ||
2252 | |||
2253 | /* | ||
2254 | * Panacom - IOMEM | ||
2255 | */ | ||
2256 | [pbn_panacom] = { | ||
2257 | .flags = FL_BASE2, | ||
2258 | .num_ports = 2, | ||
2259 | .base_baud = 921600, | ||
2260 | .uart_offset = 0x400, | ||
2261 | .reg_shift = 7, | ||
2262 | }, | ||
2263 | [pbn_panacom2] = { | ||
2264 | .flags = FL_BASE2|FL_BASE_BARS, | ||
2265 | .num_ports = 2, | ||
2266 | .base_baud = 921600, | ||
2267 | .uart_offset = 0x400, | ||
2268 | .reg_shift = 7, | ||
2269 | }, | ||
2270 | [pbn_panacom4] = { | ||
2271 | .flags = FL_BASE2|FL_BASE_BARS, | ||
2272 | .num_ports = 4, | ||
2273 | .base_baud = 921600, | ||
2274 | .uart_offset = 0x400, | ||
2275 | .reg_shift = 7, | ||
2276 | }, | ||
2277 | |||
2278 | [pbn_exsys_4055] = { | ||
2279 | .flags = FL_BASE2, | ||
2280 | .num_ports = 4, | ||
2281 | .base_baud = 115200, | ||
2282 | .uart_offset = 8, | ||
2283 | }, | ||
2284 | |||
2285 | /* I think this entry is broken - the first_offset looks wrong --rmk */ | ||
2286 | [pbn_plx_romulus] = { | ||
2287 | .flags = FL_BASE2, | ||
2288 | .num_ports = 4, | ||
2289 | .base_baud = 921600, | ||
2290 | .uart_offset = 8 << 2, | ||
2291 | .reg_shift = 2, | ||
2292 | .first_offset = 0x03, | ||
2293 | }, | ||
2294 | |||
2295 | /* | ||
2296 | * This board uses the size of PCI Base region 0 to | ||
2297 | * signal now many ports are available | ||
2298 | */ | ||
2299 | [pbn_oxsemi] = { | ||
2300 | .flags = FL_BASE0|FL_REGION_SZ_CAP, | ||
2301 | .num_ports = 32, | ||
2302 | .base_baud = 115200, | ||
2303 | .uart_offset = 8, | ||
2304 | }, | ||
2305 | [pbn_oxsemi_1_4000000] = { | ||
2306 | .flags = FL_BASE0, | ||
2307 | .num_ports = 1, | ||
2308 | .base_baud = 4000000, | ||
2309 | .uart_offset = 0x200, | ||
2310 | .first_offset = 0x1000, | ||
2311 | }, | ||
2312 | [pbn_oxsemi_2_4000000] = { | ||
2313 | .flags = FL_BASE0, | ||
2314 | .num_ports = 2, | ||
2315 | .base_baud = 4000000, | ||
2316 | .uart_offset = 0x200, | ||
2317 | .first_offset = 0x1000, | ||
2318 | }, | ||
2319 | [pbn_oxsemi_4_4000000] = { | ||
2320 | .flags = FL_BASE0, | ||
2321 | .num_ports = 4, | ||
2322 | .base_baud = 4000000, | ||
2323 | .uart_offset = 0x200, | ||
2324 | .first_offset = 0x1000, | ||
2325 | }, | ||
2326 | [pbn_oxsemi_8_4000000] = { | ||
2327 | .flags = FL_BASE0, | ||
2328 | .num_ports = 8, | ||
2329 | .base_baud = 4000000, | ||
2330 | .uart_offset = 0x200, | ||
2331 | .first_offset = 0x1000, | ||
2332 | }, | ||
2333 | |||
2334 | |||
2335 | /* | ||
2336 | * EKF addition for i960 Boards form EKF with serial port. | ||
2337 | * Max 256 ports. | ||
2338 | */ | ||
2339 | [pbn_intel_i960] = { | ||
2340 | .flags = FL_BASE0, | ||
2341 | .num_ports = 32, | ||
2342 | .base_baud = 921600, | ||
2343 | .uart_offset = 8 << 2, | ||
2344 | .reg_shift = 2, | ||
2345 | .first_offset = 0x10000, | ||
2346 | }, | ||
2347 | [pbn_sgi_ioc3] = { | ||
2348 | .flags = FL_BASE0|FL_NOIRQ, | ||
2349 | .num_ports = 1, | ||
2350 | .base_baud = 458333, | ||
2351 | .uart_offset = 8, | ||
2352 | .reg_shift = 0, | ||
2353 | .first_offset = 0x20178, | ||
2354 | }, | ||
2355 | |||
2356 | /* | ||
2357 | * Computone - uses IOMEM. | ||
2358 | */ | ||
2359 | [pbn_computone_4] = { | ||
2360 | .flags = FL_BASE0, | ||
2361 | .num_ports = 4, | ||
2362 | .base_baud = 921600, | ||
2363 | .uart_offset = 0x40, | ||
2364 | .reg_shift = 2, | ||
2365 | .first_offset = 0x200, | ||
2366 | }, | ||
2367 | [pbn_computone_6] = { | ||
2368 | .flags = FL_BASE0, | ||
2369 | .num_ports = 6, | ||
2370 | .base_baud = 921600, | ||
2371 | .uart_offset = 0x40, | ||
2372 | .reg_shift = 2, | ||
2373 | .first_offset = 0x200, | ||
2374 | }, | ||
2375 | [pbn_computone_8] = { | ||
2376 | .flags = FL_BASE0, | ||
2377 | .num_ports = 8, | ||
2378 | .base_baud = 921600, | ||
2379 | .uart_offset = 0x40, | ||
2380 | .reg_shift = 2, | ||
2381 | .first_offset = 0x200, | ||
2382 | }, | ||
2383 | [pbn_sbsxrsio] = { | ||
2384 | .flags = FL_BASE0, | ||
2385 | .num_ports = 8, | ||
2386 | .base_baud = 460800, | ||
2387 | .uart_offset = 256, | ||
2388 | .reg_shift = 4, | ||
2389 | }, | ||
2390 | /* | ||
2391 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART | ||
2392 | * Only basic 16550A support. | ||
2393 | * XR17C15[24] are not tested, but they should work. | ||
2394 | */ | ||
2395 | [pbn_exar_XR17C152] = { | ||
2396 | .flags = FL_BASE0, | ||
2397 | .num_ports = 2, | ||
2398 | .base_baud = 921600, | ||
2399 | .uart_offset = 0x200, | ||
2400 | }, | ||
2401 | [pbn_exar_XR17C154] = { | ||
2402 | .flags = FL_BASE0, | ||
2403 | .num_ports = 4, | ||
2404 | .base_baud = 921600, | ||
2405 | .uart_offset = 0x200, | ||
2406 | }, | ||
2407 | [pbn_exar_XR17C158] = { | ||
2408 | .flags = FL_BASE0, | ||
2409 | .num_ports = 8, | ||
2410 | .base_baud = 921600, | ||
2411 | .uart_offset = 0x200, | ||
2412 | }, | ||
2413 | [pbn_exar_ibm_saturn] = { | ||
2414 | .flags = FL_BASE0, | ||
2415 | .num_ports = 1, | ||
2416 | .base_baud = 921600, | ||
2417 | .uart_offset = 0x200, | ||
2418 | }, | ||
2419 | |||
2420 | /* | ||
2421 | * PA Semi PWRficient PA6T-1682M on-chip UART | ||
2422 | */ | ||
2423 | [pbn_pasemi_1682M] = { | ||
2424 | .flags = FL_BASE0, | ||
2425 | .num_ports = 1, | ||
2426 | .base_baud = 8333333, | ||
2427 | }, | ||
2428 | /* | ||
2429 | * National Instruments 843x | ||
2430 | */ | ||
2431 | [pbn_ni8430_16] = { | ||
2432 | .flags = FL_BASE0, | ||
2433 | .num_ports = 16, | ||
2434 | .base_baud = 3686400, | ||
2435 | .uart_offset = 0x10, | ||
2436 | .first_offset = 0x800, | ||
2437 | }, | ||
2438 | [pbn_ni8430_8] = { | ||
2439 | .flags = FL_BASE0, | ||
2440 | .num_ports = 8, | ||
2441 | .base_baud = 3686400, | ||
2442 | .uart_offset = 0x10, | ||
2443 | .first_offset = 0x800, | ||
2444 | }, | ||
2445 | [pbn_ni8430_4] = { | ||
2446 | .flags = FL_BASE0, | ||
2447 | .num_ports = 4, | ||
2448 | .base_baud = 3686400, | ||
2449 | .uart_offset = 0x10, | ||
2450 | .first_offset = 0x800, | ||
2451 | }, | ||
2452 | [pbn_ni8430_2] = { | ||
2453 | .flags = FL_BASE0, | ||
2454 | .num_ports = 2, | ||
2455 | .base_baud = 3686400, | ||
2456 | .uart_offset = 0x10, | ||
2457 | .first_offset = 0x800, | ||
2458 | }, | ||
2459 | /* | ||
2460 | * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> | ||
2461 | */ | ||
2462 | [pbn_ADDIDATA_PCIe_1_3906250] = { | ||
2463 | .flags = FL_BASE0, | ||
2464 | .num_ports = 1, | ||
2465 | .base_baud = 3906250, | ||
2466 | .uart_offset = 0x200, | ||
2467 | .first_offset = 0x1000, | ||
2468 | }, | ||
2469 | [pbn_ADDIDATA_PCIe_2_3906250] = { | ||
2470 | .flags = FL_BASE0, | ||
2471 | .num_ports = 2, | ||
2472 | .base_baud = 3906250, | ||
2473 | .uart_offset = 0x200, | ||
2474 | .first_offset = 0x1000, | ||
2475 | }, | ||
2476 | [pbn_ADDIDATA_PCIe_4_3906250] = { | ||
2477 | .flags = FL_BASE0, | ||
2478 | .num_ports = 4, | ||
2479 | .base_baud = 3906250, | ||
2480 | .uart_offset = 0x200, | ||
2481 | .first_offset = 0x1000, | ||
2482 | }, | ||
2483 | [pbn_ADDIDATA_PCIe_8_3906250] = { | ||
2484 | .flags = FL_BASE0, | ||
2485 | .num_ports = 8, | ||
2486 | .base_baud = 3906250, | ||
2487 | .uart_offset = 0x200, | ||
2488 | .first_offset = 0x1000, | ||
2489 | }, | ||
2490 | [pbn_ce4100_1_115200] = { | ||
2491 | .flags = FL_BASE0, | ||
2492 | .num_ports = 1, | ||
2493 | .base_baud = 921600, | ||
2494 | .reg_shift = 2, | ||
2495 | }, | ||
2496 | [pbn_omegapci] = { | ||
2497 | .flags = FL_BASE0, | ||
2498 | .num_ports = 8, | ||
2499 | .base_baud = 115200, | ||
2500 | .uart_offset = 0x200, | ||
2501 | }, | ||
2502 | [pbn_NETMOS9900_2s_115200] = { | ||
2503 | .flags = FL_BASE0, | ||
2504 | .num_ports = 2, | ||
2505 | .base_baud = 115200, | ||
2506 | }, | ||
2507 | }; | ||
2508 | |||
2509 | static const struct pci_device_id softmodem_blacklist[] = { | ||
2510 | { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ | ||
2511 | { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ | ||
2512 | { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ | ||
2513 | }; | ||
2514 | |||
2515 | /* | ||
2516 | * Given a complete unknown PCI device, try to use some heuristics to | ||
2517 | * guess what the configuration might be, based on the pitiful PCI | ||
2518 | * serial specs. Returns 0 on success, 1 on failure. | ||
2519 | */ | ||
2520 | static int __devinit | ||
2521 | serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) | ||
2522 | { | ||
2523 | const struct pci_device_id *blacklist; | ||
2524 | int num_iomem, num_port, first_port = -1, i; | ||
2525 | |||
2526 | /* | ||
2527 | * If it is not a communications device or the programming | ||
2528 | * interface is greater than 6, give up. | ||
2529 | * | ||
2530 | * (Should we try to make guesses for multiport serial devices | ||
2531 | * later?) | ||
2532 | */ | ||
2533 | if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && | ||
2534 | ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || | ||
2535 | (dev->class & 0xff) > 6) | ||
2536 | return -ENODEV; | ||
2537 | |||
2538 | /* | ||
2539 | * Do not access blacklisted devices that are known not to | ||
2540 | * feature serial ports. | ||
2541 | */ | ||
2542 | for (blacklist = softmodem_blacklist; | ||
2543 | blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist); | ||
2544 | blacklist++) { | ||
2545 | if (dev->vendor == blacklist->vendor && | ||
2546 | dev->device == blacklist->device) | ||
2547 | return -ENODEV; | ||
2548 | } | ||
2549 | |||
2550 | num_iomem = num_port = 0; | ||
2551 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | ||
2552 | if (pci_resource_flags(dev, i) & IORESOURCE_IO) { | ||
2553 | num_port++; | ||
2554 | if (first_port == -1) | ||
2555 | first_port = i; | ||
2556 | } | ||
2557 | if (pci_resource_flags(dev, i) & IORESOURCE_MEM) | ||
2558 | num_iomem++; | ||
2559 | } | ||
2560 | |||
2561 | /* | ||
2562 | * If there is 1 or 0 iomem regions, and exactly one port, | ||
2563 | * use it. We guess the number of ports based on the IO | ||
2564 | * region size. | ||
2565 | */ | ||
2566 | if (num_iomem <= 1 && num_port == 1) { | ||
2567 | board->flags = first_port; | ||
2568 | board->num_ports = pci_resource_len(dev, first_port) / 8; | ||
2569 | return 0; | ||
2570 | } | ||
2571 | |||
2572 | /* | ||
2573 | * Now guess if we've got a board which indexes by BARs. | ||
2574 | * Each IO BAR should be 8 bytes, and they should follow | ||
2575 | * consecutively. | ||
2576 | */ | ||
2577 | first_port = -1; | ||
2578 | num_port = 0; | ||
2579 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | ||
2580 | if (pci_resource_flags(dev, i) & IORESOURCE_IO && | ||
2581 | pci_resource_len(dev, i) == 8 && | ||
2582 | (first_port == -1 || (first_port + num_port) == i)) { | ||
2583 | num_port++; | ||
2584 | if (first_port == -1) | ||
2585 | first_port = i; | ||
2586 | } | ||
2587 | } | ||
2588 | |||
2589 | if (num_port > 1) { | ||
2590 | board->flags = first_port | FL_BASE_BARS; | ||
2591 | board->num_ports = num_port; | ||
2592 | return 0; | ||
2593 | } | ||
2594 | |||
2595 | return -ENODEV; | ||
2596 | } | ||
2597 | |||
2598 | static inline int | ||
2599 | serial_pci_matches(const struct pciserial_board *board, | ||
2600 | const struct pciserial_board *guessed) | ||
2601 | { | ||
2602 | return | ||
2603 | board->num_ports == guessed->num_ports && | ||
2604 | board->base_baud == guessed->base_baud && | ||
2605 | board->uart_offset == guessed->uart_offset && | ||
2606 | board->reg_shift == guessed->reg_shift && | ||
2607 | board->first_offset == guessed->first_offset; | ||
2608 | } | ||
2609 | |||
2610 | struct serial_private * | ||
2611 | pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) | ||
2612 | { | ||
2613 | struct uart_port serial_port; | ||
2614 | struct serial_private *priv; | ||
2615 | struct pci_serial_quirk *quirk; | ||
2616 | int rc, nr_ports, i; | ||
2617 | |||
2618 | nr_ports = board->num_ports; | ||
2619 | |||
2620 | /* | ||
2621 | * Find an init and setup quirks. | ||
2622 | */ | ||
2623 | quirk = find_quirk(dev); | ||
2624 | |||
2625 | /* | ||
2626 | * Run the new-style initialization function. | ||
2627 | * The initialization function returns: | ||
2628 | * <0 - error | ||
2629 | * 0 - use board->num_ports | ||
2630 | * >0 - number of ports | ||
2631 | */ | ||
2632 | if (quirk->init) { | ||
2633 | rc = quirk->init(dev); | ||
2634 | if (rc < 0) { | ||
2635 | priv = ERR_PTR(rc); | ||
2636 | goto err_out; | ||
2637 | } | ||
2638 | if (rc) | ||
2639 | nr_ports = rc; | ||
2640 | } | ||
2641 | |||
2642 | priv = kzalloc(sizeof(struct serial_private) + | ||
2643 | sizeof(unsigned int) * nr_ports, | ||
2644 | GFP_KERNEL); | ||
2645 | if (!priv) { | ||
2646 | priv = ERR_PTR(-ENOMEM); | ||
2647 | goto err_deinit; | ||
2648 | } | ||
2649 | |||
2650 | priv->dev = dev; | ||
2651 | priv->quirk = quirk; | ||
2652 | |||
2653 | memset(&serial_port, 0, sizeof(struct uart_port)); | ||
2654 | serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | ||
2655 | serial_port.uartclk = board->base_baud * 16; | ||
2656 | serial_port.irq = get_pci_irq(dev, board); | ||
2657 | serial_port.dev = &dev->dev; | ||
2658 | |||
2659 | for (i = 0; i < nr_ports; i++) { | ||
2660 | if (quirk->setup(priv, board, &serial_port, i)) | ||
2661 | break; | ||
2662 | |||
2663 | #ifdef SERIAL_DEBUG_PCI | ||
2664 | printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n", | ||
2665 | serial_port.iobase, serial_port.irq, serial_port.iotype); | ||
2666 | #endif | ||
2667 | |||
2668 | priv->line[i] = serial8250_register_port(&serial_port); | ||
2669 | if (priv->line[i] < 0) { | ||
2670 | printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]); | ||
2671 | break; | ||
2672 | } | ||
2673 | } | ||
2674 | priv->nr = i; | ||
2675 | return priv; | ||
2676 | |||
2677 | err_deinit: | ||
2678 | if (quirk->exit) | ||
2679 | quirk->exit(dev); | ||
2680 | err_out: | ||
2681 | return priv; | ||
2682 | } | ||
2683 | EXPORT_SYMBOL_GPL(pciserial_init_ports); | ||
2684 | |||
2685 | void pciserial_remove_ports(struct serial_private *priv) | ||
2686 | { | ||
2687 | struct pci_serial_quirk *quirk; | ||
2688 | int i; | ||
2689 | |||
2690 | for (i = 0; i < priv->nr; i++) | ||
2691 | serial8250_unregister_port(priv->line[i]); | ||
2692 | |||
2693 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | ||
2694 | if (priv->remapped_bar[i]) | ||
2695 | iounmap(priv->remapped_bar[i]); | ||
2696 | priv->remapped_bar[i] = NULL; | ||
2697 | } | ||
2698 | |||
2699 | /* | ||
2700 | * Find the exit quirks. | ||
2701 | */ | ||
2702 | quirk = find_quirk(priv->dev); | ||
2703 | if (quirk->exit) | ||
2704 | quirk->exit(priv->dev); | ||
2705 | |||
2706 | kfree(priv); | ||
2707 | } | ||
2708 | EXPORT_SYMBOL_GPL(pciserial_remove_ports); | ||
2709 | |||
2710 | void pciserial_suspend_ports(struct serial_private *priv) | ||
2711 | { | ||
2712 | int i; | ||
2713 | |||
2714 | for (i = 0; i < priv->nr; i++) | ||
2715 | if (priv->line[i] >= 0) | ||
2716 | serial8250_suspend_port(priv->line[i]); | ||
2717 | } | ||
2718 | EXPORT_SYMBOL_GPL(pciserial_suspend_ports); | ||
2719 | |||
2720 | void pciserial_resume_ports(struct serial_private *priv) | ||
2721 | { | ||
2722 | int i; | ||
2723 | |||
2724 | /* | ||
2725 | * Ensure that the board is correctly configured. | ||
2726 | */ | ||
2727 | if (priv->quirk->init) | ||
2728 | priv->quirk->init(priv->dev); | ||
2729 | |||
2730 | for (i = 0; i < priv->nr; i++) | ||
2731 | if (priv->line[i] >= 0) | ||
2732 | serial8250_resume_port(priv->line[i]); | ||
2733 | } | ||
2734 | EXPORT_SYMBOL_GPL(pciserial_resume_ports); | ||
2735 | |||
2736 | /* | ||
2737 | * Probe one serial board. Unfortunately, there is no rhyme nor reason | ||
2738 | * to the arrangement of serial ports on a PCI card. | ||
2739 | */ | ||
2740 | static int __devinit | ||
2741 | pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) | ||
2742 | { | ||
2743 | struct pci_serial_quirk *quirk; | ||
2744 | struct serial_private *priv; | ||
2745 | const struct pciserial_board *board; | ||
2746 | struct pciserial_board tmp; | ||
2747 | int rc; | ||
2748 | |||
2749 | quirk = find_quirk(dev); | ||
2750 | if (quirk->probe) { | ||
2751 | rc = quirk->probe(dev); | ||
2752 | if (rc) | ||
2753 | return rc; | ||
2754 | } | ||
2755 | |||
2756 | if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { | ||
2757 | printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n", | ||
2758 | ent->driver_data); | ||
2759 | return -EINVAL; | ||
2760 | } | ||
2761 | |||
2762 | board = &pci_boards[ent->driver_data]; | ||
2763 | |||
2764 | rc = pci_enable_device(dev); | ||
2765 | pci_save_state(dev); | ||
2766 | if (rc) | ||
2767 | return rc; | ||
2768 | |||
2769 | if (ent->driver_data == pbn_default) { | ||
2770 | /* | ||
2771 | * Use a copy of the pci_board entry for this; | ||
2772 | * avoid changing entries in the table. | ||
2773 | */ | ||
2774 | memcpy(&tmp, board, sizeof(struct pciserial_board)); | ||
2775 | board = &tmp; | ||
2776 | |||
2777 | /* | ||
2778 | * We matched one of our class entries. Try to | ||
2779 | * determine the parameters of this board. | ||
2780 | */ | ||
2781 | rc = serial_pci_guess_board(dev, &tmp); | ||
2782 | if (rc) | ||
2783 | goto disable; | ||
2784 | } else { | ||
2785 | /* | ||
2786 | * We matched an explicit entry. If we are able to | ||
2787 | * detect this boards settings with our heuristic, | ||
2788 | * then we no longer need this entry. | ||
2789 | */ | ||
2790 | memcpy(&tmp, &pci_boards[pbn_default], | ||
2791 | sizeof(struct pciserial_board)); | ||
2792 | rc = serial_pci_guess_board(dev, &tmp); | ||
2793 | if (rc == 0 && serial_pci_matches(board, &tmp)) | ||
2794 | moan_device("Redundant entry in serial pci_table.", | ||
2795 | dev); | ||
2796 | } | ||
2797 | |||
2798 | priv = pciserial_init_ports(dev, board); | ||
2799 | if (!IS_ERR(priv)) { | ||
2800 | pci_set_drvdata(dev, priv); | ||
2801 | return 0; | ||
2802 | } | ||
2803 | |||
2804 | rc = PTR_ERR(priv); | ||
2805 | |||
2806 | disable: | ||
2807 | pci_disable_device(dev); | ||
2808 | return rc; | ||
2809 | } | ||
2810 | |||
2811 | static void __devexit pciserial_remove_one(struct pci_dev *dev) | ||
2812 | { | ||
2813 | struct serial_private *priv = pci_get_drvdata(dev); | ||
2814 | |||
2815 | pci_set_drvdata(dev, NULL); | ||
2816 | |||
2817 | pciserial_remove_ports(priv); | ||
2818 | |||
2819 | pci_disable_device(dev); | ||
2820 | } | ||
2821 | |||
2822 | #ifdef CONFIG_PM | ||
2823 | static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) | ||
2824 | { | ||
2825 | struct serial_private *priv = pci_get_drvdata(dev); | ||
2826 | |||
2827 | if (priv) | ||
2828 | pciserial_suspend_ports(priv); | ||
2829 | |||
2830 | pci_save_state(dev); | ||
2831 | pci_set_power_state(dev, pci_choose_state(dev, state)); | ||
2832 | return 0; | ||
2833 | } | ||
2834 | |||
2835 | static int pciserial_resume_one(struct pci_dev *dev) | ||
2836 | { | ||
2837 | int err; | ||
2838 | struct serial_private *priv = pci_get_drvdata(dev); | ||
2839 | |||
2840 | pci_set_power_state(dev, PCI_D0); | ||
2841 | pci_restore_state(dev); | ||
2842 | |||
2843 | if (priv) { | ||
2844 | /* | ||
2845 | * The device may have been disabled. Re-enable it. | ||
2846 | */ | ||
2847 | err = pci_enable_device(dev); | ||
2848 | /* FIXME: We cannot simply error out here */ | ||
2849 | if (err) | ||
2850 | printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n"); | ||
2851 | pciserial_resume_ports(priv); | ||
2852 | } | ||
2853 | return 0; | ||
2854 | } | ||
2855 | #endif | ||
2856 | |||
2857 | static struct pci_device_id serial_pci_tbl[] = { | ||
2858 | /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ | ||
2859 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, | ||
2860 | PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, | ||
2861 | pbn_b2_8_921600 }, | ||
2862 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | ||
2863 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2864 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | ||
2865 | pbn_b1_8_1382400 }, | ||
2866 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | ||
2867 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2868 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | ||
2869 | pbn_b1_4_1382400 }, | ||
2870 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | ||
2871 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2872 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | ||
2873 | pbn_b1_2_1382400 }, | ||
2874 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2875 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2876 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | ||
2877 | pbn_b1_8_1382400 }, | ||
2878 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2879 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2880 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | ||
2881 | pbn_b1_4_1382400 }, | ||
2882 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2883 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2884 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | ||
2885 | pbn_b1_2_1382400 }, | ||
2886 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2887 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2888 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, | ||
2889 | pbn_b1_8_921600 }, | ||
2890 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2891 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2892 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, | ||
2893 | pbn_b1_8_921600 }, | ||
2894 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2895 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2896 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, | ||
2897 | pbn_b1_4_921600 }, | ||
2898 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2899 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2900 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, | ||
2901 | pbn_b1_4_921600 }, | ||
2902 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2903 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2904 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, | ||
2905 | pbn_b1_2_921600 }, | ||
2906 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2907 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2908 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, | ||
2909 | pbn_b1_8_921600 }, | ||
2910 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2911 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2912 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, | ||
2913 | pbn_b1_8_921600 }, | ||
2914 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2915 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2916 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, | ||
2917 | pbn_b1_4_921600 }, | ||
2918 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | ||
2919 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2920 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, | ||
2921 | pbn_b1_2_1250000 }, | ||
2922 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | ||
2923 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2924 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, | ||
2925 | pbn_b0_2_1843200 }, | ||
2926 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | ||
2927 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2928 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, | ||
2929 | pbn_b0_4_1843200 }, | ||
2930 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | ||
2931 | PCI_VENDOR_ID_AFAVLAB, | ||
2932 | PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, | ||
2933 | pbn_b0_4_1152000 }, | ||
2934 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | ||
2935 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2936 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, | ||
2937 | pbn_b0_2_1843200_200 }, | ||
2938 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | ||
2939 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2940 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, | ||
2941 | pbn_b0_4_1843200_200 }, | ||
2942 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | ||
2943 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2944 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, | ||
2945 | pbn_b0_8_1843200_200 }, | ||
2946 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | ||
2947 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2948 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, | ||
2949 | pbn_b0_2_1843200_200 }, | ||
2950 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | ||
2951 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2952 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, | ||
2953 | pbn_b0_4_1843200_200 }, | ||
2954 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | ||
2955 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2956 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, | ||
2957 | pbn_b0_8_1843200_200 }, | ||
2958 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | ||
2959 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2960 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, | ||
2961 | pbn_b0_2_1843200_200 }, | ||
2962 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | ||
2963 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2964 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, | ||
2965 | pbn_b0_4_1843200_200 }, | ||
2966 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | ||
2967 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2968 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, | ||
2969 | pbn_b0_8_1843200_200 }, | ||
2970 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | ||
2971 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2972 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, | ||
2973 | pbn_b0_2_1843200_200 }, | ||
2974 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | ||
2975 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2976 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, | ||
2977 | pbn_b0_4_1843200_200 }, | ||
2978 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | ||
2979 | PCI_SUBVENDOR_ID_CONNECT_TECH, | ||
2980 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, | ||
2981 | pbn_b0_8_1843200_200 }, | ||
2982 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | ||
2983 | PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, | ||
2984 | 0, 0, pbn_exar_ibm_saturn }, | ||
2985 | |||
2986 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, | ||
2987 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
2988 | pbn_b2_bt_1_115200 }, | ||
2989 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, | ||
2990 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
2991 | pbn_b2_bt_2_115200 }, | ||
2992 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, | ||
2993 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
2994 | pbn_b2_bt_4_115200 }, | ||
2995 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, | ||
2996 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
2997 | pbn_b2_bt_2_115200 }, | ||
2998 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, | ||
2999 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3000 | pbn_b2_bt_4_115200 }, | ||
3001 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, | ||
3002 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3003 | pbn_b2_8_115200 }, | ||
3004 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, | ||
3005 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3006 | pbn_b2_8_460800 }, | ||
3007 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, | ||
3008 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3009 | pbn_b2_8_115200 }, | ||
3010 | |||
3011 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, | ||
3012 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3013 | pbn_b2_bt_2_115200 }, | ||
3014 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, | ||
3015 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3016 | pbn_b2_bt_2_921600 }, | ||
3017 | /* | ||
3018 | * VScom SPCOM800, from sl@s.pl | ||
3019 | */ | ||
3020 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, | ||
3021 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3022 | pbn_b2_8_921600 }, | ||
3023 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, | ||
3024 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3025 | pbn_b2_4_921600 }, | ||
3026 | /* Unknown card - subdevice 0x1584 */ | ||
3027 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3028 | PCI_VENDOR_ID_PLX, | ||
3029 | PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, | ||
3030 | pbn_b0_4_115200 }, | ||
3031 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3032 | PCI_SUBVENDOR_ID_KEYSPAN, | ||
3033 | PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, | ||
3034 | pbn_panacom }, | ||
3035 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, | ||
3036 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3037 | pbn_panacom4 }, | ||
3038 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, | ||
3039 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3040 | pbn_panacom2 }, | ||
3041 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | ||
3042 | PCI_VENDOR_ID_ESDGMBH, | ||
3043 | PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, | ||
3044 | pbn_b2_4_115200 }, | ||
3045 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3046 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | ||
3047 | PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, | ||
3048 | pbn_b2_4_460800 }, | ||
3049 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3050 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | ||
3051 | PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, | ||
3052 | pbn_b2_8_460800 }, | ||
3053 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3054 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | ||
3055 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, | ||
3056 | pbn_b2_16_460800 }, | ||
3057 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3058 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | ||
3059 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, | ||
3060 | pbn_b2_16_460800 }, | ||
3061 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3062 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | ||
3063 | PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, | ||
3064 | pbn_b2_4_460800 }, | ||
3065 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3066 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | ||
3067 | PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, | ||
3068 | pbn_b2_8_460800 }, | ||
3069 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | ||
3070 | PCI_SUBVENDOR_ID_EXSYS, | ||
3071 | PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, | ||
3072 | pbn_exsys_4055 }, | ||
3073 | /* | ||
3074 | * Megawolf Romulus PCI Serial Card, from Mike Hudson | ||
3075 | * (Exoray@isys.ca) | ||
3076 | */ | ||
3077 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, | ||
3078 | 0x10b5, 0x106a, 0, 0, | ||
3079 | pbn_plx_romulus }, | ||
3080 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, | ||
3081 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3082 | pbn_b1_4_115200 }, | ||
3083 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, | ||
3084 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3085 | pbn_b1_2_115200 }, | ||
3086 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, | ||
3087 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3088 | pbn_b1_8_115200 }, | ||
3089 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, | ||
3090 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3091 | pbn_b1_8_115200 }, | ||
3092 | { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, | ||
3093 | PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, | ||
3094 | 0, 0, | ||
3095 | pbn_b0_4_921600 }, | ||
3096 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | ||
3097 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, | ||
3098 | 0, 0, | ||
3099 | pbn_b0_4_1152000 }, | ||
3100 | { PCI_VENDOR_ID_OXSEMI, 0x9505, | ||
3101 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3102 | pbn_b0_bt_2_921600 }, | ||
3103 | |||
3104 | /* | ||
3105 | * The below card is a little controversial since it is the | ||
3106 | * subject of a PCI vendor/device ID clash. (See | ||
3107 | * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). | ||
3108 | * For now just used the hex ID 0x950a. | ||
3109 | */ | ||
3110 | { PCI_VENDOR_ID_OXSEMI, 0x950a, | ||
3111 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0, | ||
3112 | pbn_b0_2_115200 }, | ||
3113 | { PCI_VENDOR_ID_OXSEMI, 0x950a, | ||
3114 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3115 | pbn_b0_2_1130000 }, | ||
3116 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, | ||
3117 | PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, | ||
3118 | pbn_b0_1_921600 }, | ||
3119 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | ||
3120 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3121 | pbn_b0_4_115200 }, | ||
3122 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, | ||
3123 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3124 | pbn_b0_bt_2_921600 }, | ||
3125 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, | ||
3126 | PCI_ANY_ID , PCI_ANY_ID, 0, 0, | ||
3127 | pbn_b2_8_1152000 }, | ||
3128 | |||
3129 | /* | ||
3130 | * Oxford Semiconductor Inc. Tornado PCI express device range. | ||
3131 | */ | ||
3132 | { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ | ||
3133 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3134 | pbn_b0_1_4000000 }, | ||
3135 | { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ | ||
3136 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3137 | pbn_b0_1_4000000 }, | ||
3138 | { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ | ||
3139 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3140 | pbn_oxsemi_1_4000000 }, | ||
3141 | { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ | ||
3142 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3143 | pbn_oxsemi_1_4000000 }, | ||
3144 | { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ | ||
3145 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3146 | pbn_b0_1_4000000 }, | ||
3147 | { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ | ||
3148 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3149 | pbn_b0_1_4000000 }, | ||
3150 | { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ | ||
3151 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3152 | pbn_oxsemi_1_4000000 }, | ||
3153 | { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ | ||
3154 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3155 | pbn_oxsemi_1_4000000 }, | ||
3156 | { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ | ||
3157 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3158 | pbn_b0_1_4000000 }, | ||
3159 | { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ | ||
3160 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3161 | pbn_b0_1_4000000 }, | ||
3162 | { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ | ||
3163 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3164 | pbn_b0_1_4000000 }, | ||
3165 | { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ | ||
3166 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3167 | pbn_b0_1_4000000 }, | ||
3168 | { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ | ||
3169 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3170 | pbn_oxsemi_2_4000000 }, | ||
3171 | { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ | ||
3172 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3173 | pbn_oxsemi_2_4000000 }, | ||
3174 | { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ | ||
3175 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3176 | pbn_oxsemi_4_4000000 }, | ||
3177 | { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ | ||
3178 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3179 | pbn_oxsemi_4_4000000 }, | ||
3180 | { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ | ||
3181 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3182 | pbn_oxsemi_8_4000000 }, | ||
3183 | { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ | ||
3184 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3185 | pbn_oxsemi_8_4000000 }, | ||
3186 | { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ | ||
3187 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3188 | pbn_oxsemi_1_4000000 }, | ||
3189 | { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ | ||
3190 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3191 | pbn_oxsemi_1_4000000 }, | ||
3192 | { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ | ||
3193 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3194 | pbn_oxsemi_1_4000000 }, | ||
3195 | { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ | ||
3196 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3197 | pbn_oxsemi_1_4000000 }, | ||
3198 | { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ | ||
3199 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3200 | pbn_oxsemi_1_4000000 }, | ||
3201 | { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ | ||
3202 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3203 | pbn_oxsemi_1_4000000 }, | ||
3204 | { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ | ||
3205 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3206 | pbn_oxsemi_1_4000000 }, | ||
3207 | { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ | ||
3208 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3209 | pbn_oxsemi_1_4000000 }, | ||
3210 | { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ | ||
3211 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3212 | pbn_oxsemi_1_4000000 }, | ||
3213 | { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ | ||
3214 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3215 | pbn_oxsemi_1_4000000 }, | ||
3216 | { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ | ||
3217 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3218 | pbn_oxsemi_1_4000000 }, | ||
3219 | { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ | ||
3220 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3221 | pbn_oxsemi_1_4000000 }, | ||
3222 | { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ | ||
3223 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3224 | pbn_oxsemi_1_4000000 }, | ||
3225 | { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ | ||
3226 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3227 | pbn_oxsemi_1_4000000 }, | ||
3228 | { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ | ||
3229 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3230 | pbn_oxsemi_1_4000000 }, | ||
3231 | { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ | ||
3232 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3233 | pbn_oxsemi_1_4000000 }, | ||
3234 | { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ | ||
3235 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3236 | pbn_oxsemi_1_4000000 }, | ||
3237 | { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ | ||
3238 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3239 | pbn_oxsemi_1_4000000 }, | ||
3240 | { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ | ||
3241 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3242 | pbn_oxsemi_1_4000000 }, | ||
3243 | { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ | ||
3244 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3245 | pbn_oxsemi_1_4000000 }, | ||
3246 | { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ | ||
3247 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3248 | pbn_oxsemi_1_4000000 }, | ||
3249 | { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ | ||
3250 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3251 | pbn_oxsemi_1_4000000 }, | ||
3252 | { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ | ||
3253 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3254 | pbn_oxsemi_1_4000000 }, | ||
3255 | { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ | ||
3256 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3257 | pbn_oxsemi_1_4000000 }, | ||
3258 | { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ | ||
3259 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3260 | pbn_oxsemi_1_4000000 }, | ||
3261 | { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ | ||
3262 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3263 | pbn_oxsemi_1_4000000 }, | ||
3264 | /* | ||
3265 | * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado | ||
3266 | */ | ||
3267 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ | ||
3268 | PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, | ||
3269 | pbn_oxsemi_1_4000000 }, | ||
3270 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ | ||
3271 | PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, | ||
3272 | pbn_oxsemi_2_4000000 }, | ||
3273 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ | ||
3274 | PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, | ||
3275 | pbn_oxsemi_4_4000000 }, | ||
3276 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ | ||
3277 | PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, | ||
3278 | pbn_oxsemi_8_4000000 }, | ||
3279 | |||
3280 | /* | ||
3281 | * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado | ||
3282 | */ | ||
3283 | { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, | ||
3284 | PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, | ||
3285 | pbn_oxsemi_2_4000000 }, | ||
3286 | |||
3287 | /* | ||
3288 | * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, | ||
3289 | * from skokodyn@yahoo.com | ||
3290 | */ | ||
3291 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | ||
3292 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, | ||
3293 | pbn_sbsxrsio }, | ||
3294 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | ||
3295 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, | ||
3296 | pbn_sbsxrsio }, | ||
3297 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | ||
3298 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, | ||
3299 | pbn_sbsxrsio }, | ||
3300 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | ||
3301 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, | ||
3302 | pbn_sbsxrsio }, | ||
3303 | |||
3304 | /* | ||
3305 | * Digitan DS560-558, from jimd@esoft.com | ||
3306 | */ | ||
3307 | { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, | ||
3308 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3309 | pbn_b1_1_115200 }, | ||
3310 | |||
3311 | /* | ||
3312 | * Titan Electronic cards | ||
3313 | * The 400L and 800L have a custom setup quirk. | ||
3314 | */ | ||
3315 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, | ||
3316 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3317 | pbn_b0_1_921600 }, | ||
3318 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, | ||
3319 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3320 | pbn_b0_2_921600 }, | ||
3321 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, | ||
3322 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3323 | pbn_b0_4_921600 }, | ||
3324 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, | ||
3325 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3326 | pbn_b0_4_921600 }, | ||
3327 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, | ||
3328 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3329 | pbn_b1_1_921600 }, | ||
3330 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, | ||
3331 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3332 | pbn_b1_bt_2_921600 }, | ||
3333 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, | ||
3334 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3335 | pbn_b0_bt_4_921600 }, | ||
3336 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, | ||
3337 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3338 | pbn_b0_bt_8_921600 }, | ||
3339 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, | ||
3340 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3341 | pbn_b4_bt_2_921600 }, | ||
3342 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, | ||
3343 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3344 | pbn_b4_bt_4_921600 }, | ||
3345 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, | ||
3346 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3347 | pbn_b4_bt_8_921600 }, | ||
3348 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, | ||
3349 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3350 | pbn_b0_4_921600 }, | ||
3351 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, | ||
3352 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3353 | pbn_b0_4_921600 }, | ||
3354 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, | ||
3355 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3356 | pbn_b0_4_921600 }, | ||
3357 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, | ||
3358 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3359 | pbn_oxsemi_1_4000000 }, | ||
3360 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, | ||
3361 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3362 | pbn_oxsemi_2_4000000 }, | ||
3363 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, | ||
3364 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3365 | pbn_oxsemi_4_4000000 }, | ||
3366 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, | ||
3367 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3368 | pbn_oxsemi_8_4000000 }, | ||
3369 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, | ||
3370 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3371 | pbn_oxsemi_2_4000000 }, | ||
3372 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, | ||
3373 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3374 | pbn_oxsemi_2_4000000 }, | ||
3375 | |||
3376 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, | ||
3377 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3378 | pbn_b2_1_460800 }, | ||
3379 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, | ||
3380 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3381 | pbn_b2_1_460800 }, | ||
3382 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, | ||
3383 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3384 | pbn_b2_1_460800 }, | ||
3385 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, | ||
3386 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3387 | pbn_b2_bt_2_921600 }, | ||
3388 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, | ||
3389 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3390 | pbn_b2_bt_2_921600 }, | ||
3391 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, | ||
3392 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3393 | pbn_b2_bt_2_921600 }, | ||
3394 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, | ||
3395 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3396 | pbn_b2_bt_4_921600 }, | ||
3397 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, | ||
3398 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3399 | pbn_b2_bt_4_921600 }, | ||
3400 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, | ||
3401 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3402 | pbn_b2_bt_4_921600 }, | ||
3403 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, | ||
3404 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3405 | pbn_b0_1_921600 }, | ||
3406 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, | ||
3407 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3408 | pbn_b0_1_921600 }, | ||
3409 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, | ||
3410 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3411 | pbn_b0_1_921600 }, | ||
3412 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, | ||
3413 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3414 | pbn_b0_bt_2_921600 }, | ||
3415 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, | ||
3416 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3417 | pbn_b0_bt_2_921600 }, | ||
3418 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, | ||
3419 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3420 | pbn_b0_bt_2_921600 }, | ||
3421 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, | ||
3422 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3423 | pbn_b0_bt_4_921600 }, | ||
3424 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, | ||
3425 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3426 | pbn_b0_bt_4_921600 }, | ||
3427 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, | ||
3428 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3429 | pbn_b0_bt_4_921600 }, | ||
3430 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, | ||
3431 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3432 | pbn_b0_bt_8_921600 }, | ||
3433 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, | ||
3434 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3435 | pbn_b0_bt_8_921600 }, | ||
3436 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, | ||
3437 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3438 | pbn_b0_bt_8_921600 }, | ||
3439 | |||
3440 | /* | ||
3441 | * Computone devices submitted by Doug McNash dmcnash@computone.com | ||
3442 | */ | ||
3443 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | ||
3444 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, | ||
3445 | 0, 0, pbn_computone_4 }, | ||
3446 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | ||
3447 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, | ||
3448 | 0, 0, pbn_computone_8 }, | ||
3449 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | ||
3450 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, | ||
3451 | 0, 0, pbn_computone_6 }, | ||
3452 | |||
3453 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, | ||
3454 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3455 | pbn_oxsemi }, | ||
3456 | { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, | ||
3457 | PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, | ||
3458 | pbn_b0_bt_1_921600 }, | ||
3459 | |||
3460 | /* | ||
3461 | * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> | ||
3462 | */ | ||
3463 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, | ||
3464 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3465 | pbn_b0_bt_8_115200 }, | ||
3466 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, | ||
3467 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3468 | pbn_b0_bt_8_115200 }, | ||
3469 | |||
3470 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, | ||
3471 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3472 | pbn_b0_bt_2_115200 }, | ||
3473 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, | ||
3474 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3475 | pbn_b0_bt_2_115200 }, | ||
3476 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, | ||
3477 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3478 | pbn_b0_bt_2_115200 }, | ||
3479 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, | ||
3480 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3481 | pbn_b0_bt_2_115200 }, | ||
3482 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, | ||
3483 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3484 | pbn_b0_bt_2_115200 }, | ||
3485 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, | ||
3486 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3487 | pbn_b0_bt_4_460800 }, | ||
3488 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, | ||
3489 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3490 | pbn_b0_bt_4_460800 }, | ||
3491 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, | ||
3492 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3493 | pbn_b0_bt_2_460800 }, | ||
3494 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, | ||
3495 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3496 | pbn_b0_bt_2_460800 }, | ||
3497 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, | ||
3498 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3499 | pbn_b0_bt_2_460800 }, | ||
3500 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, | ||
3501 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3502 | pbn_b0_bt_1_115200 }, | ||
3503 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, | ||
3504 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3505 | pbn_b0_bt_1_460800 }, | ||
3506 | |||
3507 | /* | ||
3508 | * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). | ||
3509 | * Cards are identified by their subsystem vendor IDs, which | ||
3510 | * (in hex) match the model number. | ||
3511 | * | ||
3512 | * Note that JC140x are RS422/485 cards which require ox950 | ||
3513 | * ACR = 0x10, and as such are not currently fully supported. | ||
3514 | */ | ||
3515 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | ||
3516 | 0x1204, 0x0004, 0, 0, | ||
3517 | pbn_b0_4_921600 }, | ||
3518 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | ||
3519 | 0x1208, 0x0004, 0, 0, | ||
3520 | pbn_b0_4_921600 }, | ||
3521 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | ||
3522 | 0x1402, 0x0002, 0, 0, | ||
3523 | pbn_b0_2_921600 }, */ | ||
3524 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | ||
3525 | 0x1404, 0x0004, 0, 0, | ||
3526 | pbn_b0_4_921600 }, */ | ||
3527 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, | ||
3528 | 0x1208, 0x0004, 0, 0, | ||
3529 | pbn_b0_4_921600 }, | ||
3530 | |||
3531 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, | ||
3532 | 0x1204, 0x0004, 0, 0, | ||
3533 | pbn_b0_4_921600 }, | ||
3534 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, | ||
3535 | 0x1208, 0x0004, 0, 0, | ||
3536 | pbn_b0_4_921600 }, | ||
3537 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, | ||
3538 | 0x1208, 0x0004, 0, 0, | ||
3539 | pbn_b0_4_921600 }, | ||
3540 | /* | ||
3541 | * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com | ||
3542 | */ | ||
3543 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, | ||
3544 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3545 | pbn_b1_1_1382400 }, | ||
3546 | |||
3547 | /* | ||
3548 | * Dell Remote Access Card III - Tim_T_Murphy@Dell.com | ||
3549 | */ | ||
3550 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, | ||
3551 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3552 | pbn_b1_1_1382400 }, | ||
3553 | |||
3554 | /* | ||
3555 | * RAStel 2 port modem, gerg@moreton.com.au | ||
3556 | */ | ||
3557 | { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, | ||
3558 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3559 | pbn_b2_bt_2_115200 }, | ||
3560 | |||
3561 | /* | ||
3562 | * EKF addition for i960 Boards form EKF with serial port | ||
3563 | */ | ||
3564 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, | ||
3565 | 0xE4BF, PCI_ANY_ID, 0, 0, | ||
3566 | pbn_intel_i960 }, | ||
3567 | |||
3568 | /* | ||
3569 | * Xircom Cardbus/Ethernet combos | ||
3570 | */ | ||
3571 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, | ||
3572 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3573 | pbn_b0_1_115200 }, | ||
3574 | /* | ||
3575 | * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) | ||
3576 | */ | ||
3577 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, | ||
3578 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3579 | pbn_b0_1_115200 }, | ||
3580 | |||
3581 | /* | ||
3582 | * Untested PCI modems, sent in from various folks... | ||
3583 | */ | ||
3584 | |||
3585 | /* | ||
3586 | * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> | ||
3587 | */ | ||
3588 | { PCI_VENDOR_ID_ROCKWELL, 0x1004, | ||
3589 | 0x1048, 0x1500, 0, 0, | ||
3590 | pbn_b1_1_115200 }, | ||
3591 | |||
3592 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, | ||
3593 | 0xFF00, 0, 0, 0, | ||
3594 | pbn_sgi_ioc3 }, | ||
3595 | |||
3596 | /* | ||
3597 | * HP Diva card | ||
3598 | */ | ||
3599 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | ||
3600 | PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, | ||
3601 | pbn_b1_1_115200 }, | ||
3602 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | ||
3603 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3604 | pbn_b0_5_115200 }, | ||
3605 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, | ||
3606 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3607 | pbn_b2_1_115200 }, | ||
3608 | |||
3609 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, | ||
3610 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3611 | pbn_b3_2_115200 }, | ||
3612 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, | ||
3613 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3614 | pbn_b3_4_115200 }, | ||
3615 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, | ||
3616 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3617 | pbn_b3_8_115200 }, | ||
3618 | |||
3619 | /* | ||
3620 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART | ||
3621 | */ | ||
3622 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, | ||
3623 | PCI_ANY_ID, PCI_ANY_ID, | ||
3624 | 0, | ||
3625 | 0, pbn_exar_XR17C152 }, | ||
3626 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, | ||
3627 | PCI_ANY_ID, PCI_ANY_ID, | ||
3628 | 0, | ||
3629 | 0, pbn_exar_XR17C154 }, | ||
3630 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, | ||
3631 | PCI_ANY_ID, PCI_ANY_ID, | ||
3632 | 0, | ||
3633 | 0, pbn_exar_XR17C158 }, | ||
3634 | |||
3635 | /* | ||
3636 | * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) | ||
3637 | */ | ||
3638 | { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, | ||
3639 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3640 | pbn_b0_1_115200 }, | ||
3641 | /* | ||
3642 | * ITE | ||
3643 | */ | ||
3644 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, | ||
3645 | PCI_ANY_ID, PCI_ANY_ID, | ||
3646 | 0, 0, | ||
3647 | pbn_b1_bt_1_115200 }, | ||
3648 | |||
3649 | /* | ||
3650 | * IntaShield IS-200 | ||
3651 | */ | ||
3652 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, | ||
3653 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ | ||
3654 | pbn_b2_2_115200 }, | ||
3655 | /* | ||
3656 | * IntaShield IS-400 | ||
3657 | */ | ||
3658 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, | ||
3659 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ | ||
3660 | pbn_b2_4_115200 }, | ||
3661 | /* | ||
3662 | * Perle PCI-RAS cards | ||
3663 | */ | ||
3664 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | ||
3665 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, | ||
3666 | 0, 0, pbn_b2_4_921600 }, | ||
3667 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | ||
3668 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, | ||
3669 | 0, 0, pbn_b2_8_921600 }, | ||
3670 | |||
3671 | /* | ||
3672 | * Mainpine series cards: Fairly standard layout but fools | ||
3673 | * parts of the autodetect in some cases and uses otherwise | ||
3674 | * unmatched communications subclasses in the PCI Express case | ||
3675 | */ | ||
3676 | |||
3677 | { /* RockForceDUO */ | ||
3678 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3679 | PCI_VENDOR_ID_MAINPINE, 0x0200, | ||
3680 | 0, 0, pbn_b0_2_115200 }, | ||
3681 | { /* RockForceQUATRO */ | ||
3682 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3683 | PCI_VENDOR_ID_MAINPINE, 0x0300, | ||
3684 | 0, 0, pbn_b0_4_115200 }, | ||
3685 | { /* RockForceDUO+ */ | ||
3686 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3687 | PCI_VENDOR_ID_MAINPINE, 0x0400, | ||
3688 | 0, 0, pbn_b0_2_115200 }, | ||
3689 | { /* RockForceQUATRO+ */ | ||
3690 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3691 | PCI_VENDOR_ID_MAINPINE, 0x0500, | ||
3692 | 0, 0, pbn_b0_4_115200 }, | ||
3693 | { /* RockForce+ */ | ||
3694 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3695 | PCI_VENDOR_ID_MAINPINE, 0x0600, | ||
3696 | 0, 0, pbn_b0_2_115200 }, | ||
3697 | { /* RockForce+ */ | ||
3698 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3699 | PCI_VENDOR_ID_MAINPINE, 0x0700, | ||
3700 | 0, 0, pbn_b0_4_115200 }, | ||
3701 | { /* RockForceOCTO+ */ | ||
3702 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3703 | PCI_VENDOR_ID_MAINPINE, 0x0800, | ||
3704 | 0, 0, pbn_b0_8_115200 }, | ||
3705 | { /* RockForceDUO+ */ | ||
3706 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3707 | PCI_VENDOR_ID_MAINPINE, 0x0C00, | ||
3708 | 0, 0, pbn_b0_2_115200 }, | ||
3709 | { /* RockForceQUARTRO+ */ | ||
3710 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3711 | PCI_VENDOR_ID_MAINPINE, 0x0D00, | ||
3712 | 0, 0, pbn_b0_4_115200 }, | ||
3713 | { /* RockForceOCTO+ */ | ||
3714 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3715 | PCI_VENDOR_ID_MAINPINE, 0x1D00, | ||
3716 | 0, 0, pbn_b0_8_115200 }, | ||
3717 | { /* RockForceD1 */ | ||
3718 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3719 | PCI_VENDOR_ID_MAINPINE, 0x2000, | ||
3720 | 0, 0, pbn_b0_1_115200 }, | ||
3721 | { /* RockForceF1 */ | ||
3722 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3723 | PCI_VENDOR_ID_MAINPINE, 0x2100, | ||
3724 | 0, 0, pbn_b0_1_115200 }, | ||
3725 | { /* RockForceD2 */ | ||
3726 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3727 | PCI_VENDOR_ID_MAINPINE, 0x2200, | ||
3728 | 0, 0, pbn_b0_2_115200 }, | ||
3729 | { /* RockForceF2 */ | ||
3730 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3731 | PCI_VENDOR_ID_MAINPINE, 0x2300, | ||
3732 | 0, 0, pbn_b0_2_115200 }, | ||
3733 | { /* RockForceD4 */ | ||
3734 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3735 | PCI_VENDOR_ID_MAINPINE, 0x2400, | ||
3736 | 0, 0, pbn_b0_4_115200 }, | ||
3737 | { /* RockForceF4 */ | ||
3738 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3739 | PCI_VENDOR_ID_MAINPINE, 0x2500, | ||
3740 | 0, 0, pbn_b0_4_115200 }, | ||
3741 | { /* RockForceD8 */ | ||
3742 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3743 | PCI_VENDOR_ID_MAINPINE, 0x2600, | ||
3744 | 0, 0, pbn_b0_8_115200 }, | ||
3745 | { /* RockForceF8 */ | ||
3746 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3747 | PCI_VENDOR_ID_MAINPINE, 0x2700, | ||
3748 | 0, 0, pbn_b0_8_115200 }, | ||
3749 | { /* IQ Express D1 */ | ||
3750 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3751 | PCI_VENDOR_ID_MAINPINE, 0x3000, | ||
3752 | 0, 0, pbn_b0_1_115200 }, | ||
3753 | { /* IQ Express F1 */ | ||
3754 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3755 | PCI_VENDOR_ID_MAINPINE, 0x3100, | ||
3756 | 0, 0, pbn_b0_1_115200 }, | ||
3757 | { /* IQ Express D2 */ | ||
3758 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3759 | PCI_VENDOR_ID_MAINPINE, 0x3200, | ||
3760 | 0, 0, pbn_b0_2_115200 }, | ||
3761 | { /* IQ Express F2 */ | ||
3762 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3763 | PCI_VENDOR_ID_MAINPINE, 0x3300, | ||
3764 | 0, 0, pbn_b0_2_115200 }, | ||
3765 | { /* IQ Express D4 */ | ||
3766 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3767 | PCI_VENDOR_ID_MAINPINE, 0x3400, | ||
3768 | 0, 0, pbn_b0_4_115200 }, | ||
3769 | { /* IQ Express F4 */ | ||
3770 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3771 | PCI_VENDOR_ID_MAINPINE, 0x3500, | ||
3772 | 0, 0, pbn_b0_4_115200 }, | ||
3773 | { /* IQ Express D8 */ | ||
3774 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3775 | PCI_VENDOR_ID_MAINPINE, 0x3C00, | ||
3776 | 0, 0, pbn_b0_8_115200 }, | ||
3777 | { /* IQ Express F8 */ | ||
3778 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | ||
3779 | PCI_VENDOR_ID_MAINPINE, 0x3D00, | ||
3780 | 0, 0, pbn_b0_8_115200 }, | ||
3781 | |||
3782 | |||
3783 | /* | ||
3784 | * PA Semi PA6T-1682M on-chip UART | ||
3785 | */ | ||
3786 | { PCI_VENDOR_ID_PASEMI, 0xa004, | ||
3787 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3788 | pbn_pasemi_1682M }, | ||
3789 | |||
3790 | /* | ||
3791 | * National Instruments | ||
3792 | */ | ||
3793 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, | ||
3794 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3795 | pbn_b1_16_115200 }, | ||
3796 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, | ||
3797 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3798 | pbn_b1_8_115200 }, | ||
3799 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, | ||
3800 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3801 | pbn_b1_bt_4_115200 }, | ||
3802 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, | ||
3803 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3804 | pbn_b1_bt_2_115200 }, | ||
3805 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, | ||
3806 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3807 | pbn_b1_bt_4_115200 }, | ||
3808 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, | ||
3809 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3810 | pbn_b1_bt_2_115200 }, | ||
3811 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, | ||
3812 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3813 | pbn_b1_16_115200 }, | ||
3814 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, | ||
3815 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3816 | pbn_b1_8_115200 }, | ||
3817 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, | ||
3818 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3819 | pbn_b1_bt_4_115200 }, | ||
3820 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, | ||
3821 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3822 | pbn_b1_bt_2_115200 }, | ||
3823 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, | ||
3824 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3825 | pbn_b1_bt_4_115200 }, | ||
3826 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, | ||
3827 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3828 | pbn_b1_bt_2_115200 }, | ||
3829 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, | ||
3830 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3831 | pbn_ni8430_2 }, | ||
3832 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, | ||
3833 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3834 | pbn_ni8430_2 }, | ||
3835 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, | ||
3836 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3837 | pbn_ni8430_4 }, | ||
3838 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, | ||
3839 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3840 | pbn_ni8430_4 }, | ||
3841 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, | ||
3842 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3843 | pbn_ni8430_8 }, | ||
3844 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, | ||
3845 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3846 | pbn_ni8430_8 }, | ||
3847 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, | ||
3848 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3849 | pbn_ni8430_16 }, | ||
3850 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, | ||
3851 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3852 | pbn_ni8430_16 }, | ||
3853 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, | ||
3854 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3855 | pbn_ni8430_2 }, | ||
3856 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, | ||
3857 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3858 | pbn_ni8430_2 }, | ||
3859 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, | ||
3860 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3861 | pbn_ni8430_4 }, | ||
3862 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, | ||
3863 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
3864 | pbn_ni8430_4 }, | ||
3865 | |||
3866 | /* | ||
3867 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | ||
3868 | */ | ||
3869 | { PCI_VENDOR_ID_ADDIDATA, | ||
3870 | PCI_DEVICE_ID_ADDIDATA_APCI7500, | ||
3871 | PCI_ANY_ID, | ||
3872 | PCI_ANY_ID, | ||
3873 | 0, | ||
3874 | 0, | ||
3875 | pbn_b0_4_115200 }, | ||
3876 | |||
3877 | { PCI_VENDOR_ID_ADDIDATA, | ||
3878 | PCI_DEVICE_ID_ADDIDATA_APCI7420, | ||
3879 | PCI_ANY_ID, | ||
3880 | PCI_ANY_ID, | ||
3881 | 0, | ||
3882 | 0, | ||
3883 | pbn_b0_2_115200 }, | ||
3884 | |||
3885 | { PCI_VENDOR_ID_ADDIDATA, | ||
3886 | PCI_DEVICE_ID_ADDIDATA_APCI7300, | ||
3887 | PCI_ANY_ID, | ||
3888 | PCI_ANY_ID, | ||
3889 | 0, | ||
3890 | 0, | ||
3891 | pbn_b0_1_115200 }, | ||
3892 | |||
3893 | { PCI_VENDOR_ID_ADDIDATA_OLD, | ||
3894 | PCI_DEVICE_ID_ADDIDATA_APCI7800, | ||
3895 | PCI_ANY_ID, | ||
3896 | PCI_ANY_ID, | ||
3897 | 0, | ||
3898 | 0, | ||
3899 | pbn_b1_8_115200 }, | ||
3900 | |||
3901 | { PCI_VENDOR_ID_ADDIDATA, | ||
3902 | PCI_DEVICE_ID_ADDIDATA_APCI7500_2, | ||
3903 | PCI_ANY_ID, | ||
3904 | PCI_ANY_ID, | ||
3905 | 0, | ||
3906 | 0, | ||
3907 | pbn_b0_4_115200 }, | ||
3908 | |||
3909 | { PCI_VENDOR_ID_ADDIDATA, | ||
3910 | PCI_DEVICE_ID_ADDIDATA_APCI7420_2, | ||
3911 | PCI_ANY_ID, | ||
3912 | PCI_ANY_ID, | ||
3913 | 0, | ||
3914 | 0, | ||
3915 | pbn_b0_2_115200 }, | ||
3916 | |||
3917 | { PCI_VENDOR_ID_ADDIDATA, | ||
3918 | PCI_DEVICE_ID_ADDIDATA_APCI7300_2, | ||
3919 | PCI_ANY_ID, | ||
3920 | PCI_ANY_ID, | ||
3921 | 0, | ||
3922 | 0, | ||
3923 | pbn_b0_1_115200 }, | ||
3924 | |||
3925 | { PCI_VENDOR_ID_ADDIDATA, | ||
3926 | PCI_DEVICE_ID_ADDIDATA_APCI7500_3, | ||
3927 | PCI_ANY_ID, | ||
3928 | PCI_ANY_ID, | ||
3929 | 0, | ||
3930 | 0, | ||
3931 | pbn_b0_4_115200 }, | ||
3932 | |||
3933 | { PCI_VENDOR_ID_ADDIDATA, | ||
3934 | PCI_DEVICE_ID_ADDIDATA_APCI7420_3, | ||
3935 | PCI_ANY_ID, | ||
3936 | PCI_ANY_ID, | ||
3937 | 0, | ||
3938 | 0, | ||
3939 | pbn_b0_2_115200 }, | ||
3940 | |||
3941 | { PCI_VENDOR_ID_ADDIDATA, | ||
3942 | PCI_DEVICE_ID_ADDIDATA_APCI7300_3, | ||
3943 | PCI_ANY_ID, | ||
3944 | PCI_ANY_ID, | ||
3945 | 0, | ||
3946 | 0, | ||
3947 | pbn_b0_1_115200 }, | ||
3948 | |||
3949 | { PCI_VENDOR_ID_ADDIDATA, | ||
3950 | PCI_DEVICE_ID_ADDIDATA_APCI7800_3, | ||
3951 | PCI_ANY_ID, | ||
3952 | PCI_ANY_ID, | ||
3953 | 0, | ||
3954 | 0, | ||
3955 | pbn_b0_8_115200 }, | ||
3956 | |||
3957 | { PCI_VENDOR_ID_ADDIDATA, | ||
3958 | PCI_DEVICE_ID_ADDIDATA_APCIe7500, | ||
3959 | PCI_ANY_ID, | ||
3960 | PCI_ANY_ID, | ||
3961 | 0, | ||
3962 | 0, | ||
3963 | pbn_ADDIDATA_PCIe_4_3906250 }, | ||
3964 | |||
3965 | { PCI_VENDOR_ID_ADDIDATA, | ||
3966 | PCI_DEVICE_ID_ADDIDATA_APCIe7420, | ||
3967 | PCI_ANY_ID, | ||
3968 | PCI_ANY_ID, | ||
3969 | 0, | ||
3970 | 0, | ||
3971 | pbn_ADDIDATA_PCIe_2_3906250 }, | ||
3972 | |||
3973 | { PCI_VENDOR_ID_ADDIDATA, | ||
3974 | PCI_DEVICE_ID_ADDIDATA_APCIe7300, | ||
3975 | PCI_ANY_ID, | ||
3976 | PCI_ANY_ID, | ||
3977 | 0, | ||
3978 | 0, | ||
3979 | pbn_ADDIDATA_PCIe_1_3906250 }, | ||
3980 | |||
3981 | { PCI_VENDOR_ID_ADDIDATA, | ||
3982 | PCI_DEVICE_ID_ADDIDATA_APCIe7800, | ||
3983 | PCI_ANY_ID, | ||
3984 | PCI_ANY_ID, | ||
3985 | 0, | ||
3986 | 0, | ||
3987 | pbn_ADDIDATA_PCIe_8_3906250 }, | ||
3988 | |||
3989 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, | ||
3990 | PCI_VENDOR_ID_IBM, 0x0299, | ||
3991 | 0, 0, pbn_b0_bt_2_115200 }, | ||
3992 | |||
3993 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, | ||
3994 | 0xA000, 0x1000, | ||
3995 | 0, 0, pbn_b0_1_115200 }, | ||
3996 | |||
3997 | /* the 9901 is a rebranded 9912 */ | ||
3998 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, | ||
3999 | 0xA000, 0x1000, | ||
4000 | 0, 0, pbn_b0_1_115200 }, | ||
4001 | |||
4002 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, | ||
4003 | 0xA000, 0x1000, | ||
4004 | 0, 0, pbn_b0_1_115200 }, | ||
4005 | |||
4006 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, | ||
4007 | 0xA000, 0x1000, | ||
4008 | 0, 0, pbn_b0_1_115200 }, | ||
4009 | |||
4010 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, | ||
4011 | 0xA000, 0x1000, | ||
4012 | 0, 0, pbn_b0_1_115200 }, | ||
4013 | |||
4014 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, | ||
4015 | 0xA000, 0x3002, | ||
4016 | 0, 0, pbn_NETMOS9900_2s_115200 }, | ||
4017 | |||
4018 | /* | ||
4019 | * Best Connectivity and Rosewill PCI Multi I/O cards | ||
4020 | */ | ||
4021 | |||
4022 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | ||
4023 | 0xA000, 0x1000, | ||
4024 | 0, 0, pbn_b0_1_115200 }, | ||
4025 | |||
4026 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | ||
4027 | 0xA000, 0x3002, | ||
4028 | 0, 0, pbn_b0_bt_2_115200 }, | ||
4029 | |||
4030 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | ||
4031 | 0xA000, 0x3004, | ||
4032 | 0, 0, pbn_b0_bt_4_115200 }, | ||
4033 | /* Intel CE4100 */ | ||
4034 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, | ||
4035 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
4036 | pbn_ce4100_1_115200 }, | ||
4037 | |||
4038 | /* | ||
4039 | * Cronyx Omega PCI | ||
4040 | */ | ||
4041 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, | ||
4042 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
4043 | pbn_omegapci }, | ||
4044 | |||
4045 | /* | ||
4046 | * These entries match devices with class COMMUNICATION_SERIAL, | ||
4047 | * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL | ||
4048 | */ | ||
4049 | { PCI_ANY_ID, PCI_ANY_ID, | ||
4050 | PCI_ANY_ID, PCI_ANY_ID, | ||
4051 | PCI_CLASS_COMMUNICATION_SERIAL << 8, | ||
4052 | 0xffff00, pbn_default }, | ||
4053 | { PCI_ANY_ID, PCI_ANY_ID, | ||
4054 | PCI_ANY_ID, PCI_ANY_ID, | ||
4055 | PCI_CLASS_COMMUNICATION_MODEM << 8, | ||
4056 | 0xffff00, pbn_default }, | ||
4057 | { PCI_ANY_ID, PCI_ANY_ID, | ||
4058 | PCI_ANY_ID, PCI_ANY_ID, | ||
4059 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, | ||
4060 | 0xffff00, pbn_default }, | ||
4061 | { 0, } | ||
4062 | }; | ||
4063 | |||
4064 | static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, | ||
4065 | pci_channel_state_t state) | ||
4066 | { | ||
4067 | struct serial_private *priv = pci_get_drvdata(dev); | ||
4068 | |||
4069 | if (state == pci_channel_io_perm_failure) | ||
4070 | return PCI_ERS_RESULT_DISCONNECT; | ||
4071 | |||
4072 | if (priv) | ||
4073 | pciserial_suspend_ports(priv); | ||
4074 | |||
4075 | pci_disable_device(dev); | ||
4076 | |||
4077 | return PCI_ERS_RESULT_NEED_RESET; | ||
4078 | } | ||
4079 | |||
4080 | static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) | ||
4081 | { | ||
4082 | int rc; | ||
4083 | |||
4084 | rc = pci_enable_device(dev); | ||
4085 | |||
4086 | if (rc) | ||
4087 | return PCI_ERS_RESULT_DISCONNECT; | ||
4088 | |||
4089 | pci_restore_state(dev); | ||
4090 | pci_save_state(dev); | ||
4091 | |||
4092 | return PCI_ERS_RESULT_RECOVERED; | ||
4093 | } | ||
4094 | |||
4095 | static void serial8250_io_resume(struct pci_dev *dev) | ||
4096 | { | ||
4097 | struct serial_private *priv = pci_get_drvdata(dev); | ||
4098 | |||
4099 | if (priv) | ||
4100 | pciserial_resume_ports(priv); | ||
4101 | } | ||
4102 | |||
4103 | static struct pci_error_handlers serial8250_err_handler = { | ||
4104 | .error_detected = serial8250_io_error_detected, | ||
4105 | .slot_reset = serial8250_io_slot_reset, | ||
4106 | .resume = serial8250_io_resume, | ||
4107 | }; | ||
4108 | |||
4109 | static struct pci_driver serial_pci_driver = { | ||
4110 | .name = "serial", | ||
4111 | .probe = pciserial_init_one, | ||
4112 | .remove = __devexit_p(pciserial_remove_one), | ||
4113 | #ifdef CONFIG_PM | ||
4114 | .suspend = pciserial_suspend_one, | ||
4115 | .resume = pciserial_resume_one, | ||
4116 | #endif | ||
4117 | .id_table = serial_pci_tbl, | ||
4118 | .err_handler = &serial8250_err_handler, | ||
4119 | }; | ||
4120 | |||
4121 | static int __init serial8250_pci_init(void) | ||
4122 | { | ||
4123 | return pci_register_driver(&serial_pci_driver); | ||
4124 | } | ||
4125 | |||
4126 | static void __exit serial8250_pci_exit(void) | ||
4127 | { | ||
4128 | pci_unregister_driver(&serial_pci_driver); | ||
4129 | } | ||
4130 | |||
4131 | module_init(serial8250_pci_init); | ||
4132 | module_exit(serial8250_pci_exit); | ||
4133 | |||
4134 | MODULE_LICENSE("GPL"); | ||
4135 | MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); | ||
4136 | MODULE_DEVICE_TABLE(pci, serial_pci_tbl); | ||