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-rw-r--r--drivers/tty/serial/8250.c3452
1 files changed, 3452 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
new file mode 100644
index 00000000000..a3f966b3986
--- /dev/null
+++ b/drivers/tty/serial/8250.c
@@ -0,0 +1,3452 @@
1/*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/delay.h>
30#include <linux/platform_device.h>
31#include <linux/tty.h>
32#include <linux/ratelimit.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
38#include <linux/nmi.h>
39#include <linux/mutex.h>
40#include <linux/slab.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
51/*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
84#define PASS_LIMIT 512
85
86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
109#include <asm/serial.h>
110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
119static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
132struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
156};
157
158struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163};
164
165#define NR_IRQ_HASH 32 /* Can be adjusted later */
166static struct hlist_head irq_lists[NR_IRQ_HASH];
167static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169/*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
275 },
276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
289 },
290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
297 [PORT_U6_16550A] = {
298 .name = "U6_16550A",
299 .fifo_size = 64,
300 .tx_loadsz = 64,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE |
311 UART_CAP_HW_CTSRTS,
312 },
313};
314
315#if defined(CONFIG_MIPS_ALCHEMY)
316
317/* Au1x00 UART hardware has a weird register layout */
318static const u8 au_io_in_map[] = {
319 [UART_RX] = 0,
320 [UART_IER] = 2,
321 [UART_IIR] = 3,
322 [UART_LCR] = 5,
323 [UART_MCR] = 6,
324 [UART_LSR] = 7,
325 [UART_MSR] = 8,
326};
327
328static const u8 au_io_out_map[] = {
329 [UART_TX] = 1,
330 [UART_IER] = 2,
331 [UART_FCR] = 4,
332 [UART_LCR] = 5,
333 [UART_MCR] = 6,
334};
335
336/* sane hardware needs no mapping */
337static inline int map_8250_in_reg(struct uart_port *p, int offset)
338{
339 if (p->iotype != UPIO_AU)
340 return offset;
341 return au_io_in_map[offset];
342}
343
344static inline int map_8250_out_reg(struct uart_port *p, int offset)
345{
346 if (p->iotype != UPIO_AU)
347 return offset;
348 return au_io_out_map[offset];
349}
350
351#elif defined(CONFIG_SERIAL_8250_RM9K)
352
353static const u8
354 regmap_in[8] = {
355 [UART_RX] = 0x00,
356 [UART_IER] = 0x0c,
357 [UART_IIR] = 0x14,
358 [UART_LCR] = 0x1c,
359 [UART_MCR] = 0x20,
360 [UART_LSR] = 0x24,
361 [UART_MSR] = 0x28,
362 [UART_SCR] = 0x2c
363 },
364 regmap_out[8] = {
365 [UART_TX] = 0x04,
366 [UART_IER] = 0x0c,
367 [UART_FCR] = 0x18,
368 [UART_LCR] = 0x1c,
369 [UART_MCR] = 0x20,
370 [UART_LSR] = 0x24,
371 [UART_MSR] = 0x28,
372 [UART_SCR] = 0x2c
373 };
374
375static inline int map_8250_in_reg(struct uart_port *p, int offset)
376{
377 if (p->iotype != UPIO_RM9000)
378 return offset;
379 return regmap_in[offset];
380}
381
382static inline int map_8250_out_reg(struct uart_port *p, int offset)
383{
384 if (p->iotype != UPIO_RM9000)
385 return offset;
386 return regmap_out[offset];
387}
388
389#else
390
391/* sane hardware needs no mapping */
392#define map_8250_in_reg(up, offset) (offset)
393#define map_8250_out_reg(up, offset) (offset)
394
395#endif
396
397static unsigned int hub6_serial_in(struct uart_port *p, int offset)
398{
399 offset = map_8250_in_reg(p, offset) << p->regshift;
400 outb(p->hub6 - 1 + offset, p->iobase);
401 return inb(p->iobase + 1);
402}
403
404static void hub6_serial_out(struct uart_port *p, int offset, int value)
405{
406 offset = map_8250_out_reg(p, offset) << p->regshift;
407 outb(p->hub6 - 1 + offset, p->iobase);
408 outb(value, p->iobase + 1);
409}
410
411static unsigned int mem_serial_in(struct uart_port *p, int offset)
412{
413 offset = map_8250_in_reg(p, offset) << p->regshift;
414 return readb(p->membase + offset);
415}
416
417static void mem_serial_out(struct uart_port *p, int offset, int value)
418{
419 offset = map_8250_out_reg(p, offset) << p->regshift;
420 writeb(value, p->membase + offset);
421}
422
423static void mem32_serial_out(struct uart_port *p, int offset, int value)
424{
425 offset = map_8250_out_reg(p, offset) << p->regshift;
426 writel(value, p->membase + offset);
427}
428
429static unsigned int mem32_serial_in(struct uart_port *p, int offset)
430{
431 offset = map_8250_in_reg(p, offset) << p->regshift;
432 return readl(p->membase + offset);
433}
434
435static unsigned int au_serial_in(struct uart_port *p, int offset)
436{
437 offset = map_8250_in_reg(p, offset) << p->regshift;
438 return __raw_readl(p->membase + offset);
439}
440
441static void au_serial_out(struct uart_port *p, int offset, int value)
442{
443 offset = map_8250_out_reg(p, offset) << p->regshift;
444 __raw_writel(value, p->membase + offset);
445}
446
447static unsigned int tsi_serial_in(struct uart_port *p, int offset)
448{
449 unsigned int tmp;
450 offset = map_8250_in_reg(p, offset) << p->regshift;
451 if (offset == UART_IIR) {
452 tmp = readl(p->membase + (UART_IIR & ~3));
453 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
454 } else
455 return readb(p->membase + offset);
456}
457
458static void tsi_serial_out(struct uart_port *p, int offset, int value)
459{
460 offset = map_8250_out_reg(p, offset) << p->regshift;
461 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
462 writeb(value, p->membase + offset);
463}
464
465/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
466static inline void dwapb_save_out_value(struct uart_port *p, int offset,
467 int value)
468{
469 struct uart_8250_port *up =
470 container_of(p, struct uart_8250_port, port);
471
472 if (offset == UART_LCR)
473 up->lcr = value;
474}
475
476/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
477static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
478{
479 if (offset == UART_TX || offset == UART_IER)
480 p->serial_in(p, UART_IER);
481}
482
483static void dwapb_serial_out(struct uart_port *p, int offset, int value)
484{
485 int save_offset = offset;
486 offset = map_8250_out_reg(p, offset) << p->regshift;
487 dwapb_save_out_value(p, save_offset, value);
488 writeb(value, p->membase + offset);
489 dwapb_check_clear_ier(p, save_offset);
490}
491
492static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
493{
494 int save_offset = offset;
495 offset = map_8250_out_reg(p, offset) << p->regshift;
496 dwapb_save_out_value(p, save_offset, value);
497 writel(value, p->membase + offset);
498 dwapb_check_clear_ier(p, save_offset);
499}
500
501static unsigned int io_serial_in(struct uart_port *p, int offset)
502{
503 offset = map_8250_in_reg(p, offset) << p->regshift;
504 return inb(p->iobase + offset);
505}
506
507static void io_serial_out(struct uart_port *p, int offset, int value)
508{
509 offset = map_8250_out_reg(p, offset) << p->regshift;
510 outb(value, p->iobase + offset);
511}
512
513static void set_io_from_upio(struct uart_port *p)
514{
515 struct uart_8250_port *up =
516 container_of(p, struct uart_8250_port, port);
517 switch (p->iotype) {
518 case UPIO_HUB6:
519 p->serial_in = hub6_serial_in;
520 p->serial_out = hub6_serial_out;
521 break;
522
523 case UPIO_MEM:
524 p->serial_in = mem_serial_in;
525 p->serial_out = mem_serial_out;
526 break;
527
528 case UPIO_RM9000:
529 case UPIO_MEM32:
530 p->serial_in = mem32_serial_in;
531 p->serial_out = mem32_serial_out;
532 break;
533
534 case UPIO_AU:
535 p->serial_in = au_serial_in;
536 p->serial_out = au_serial_out;
537 break;
538
539 case UPIO_TSI:
540 p->serial_in = tsi_serial_in;
541 p->serial_out = tsi_serial_out;
542 break;
543
544 case UPIO_DWAPB:
545 p->serial_in = mem_serial_in;
546 p->serial_out = dwapb_serial_out;
547 break;
548
549 case UPIO_DWAPB32:
550 p->serial_in = mem32_serial_in;
551 p->serial_out = dwapb32_serial_out;
552 break;
553
554 default:
555 p->serial_in = io_serial_in;
556 p->serial_out = io_serial_out;
557 break;
558 }
559 /* Remember loaded iotype */
560 up->cur_iotype = p->iotype;
561}
562
563static void
564serial_out_sync(struct uart_8250_port *up, int offset, int value)
565{
566 struct uart_port *p = &up->port;
567 switch (p->iotype) {
568 case UPIO_MEM:
569 case UPIO_MEM32:
570 case UPIO_AU:
571 case UPIO_DWAPB:
572 case UPIO_DWAPB32:
573 p->serial_out(p, offset, value);
574 p->serial_in(p, UART_LCR); /* safe, no side-effects */
575 break;
576 default:
577 p->serial_out(p, offset, value);
578 }
579}
580
581#define serial_in(up, offset) \
582 (up->port.serial_in(&(up)->port, (offset)))
583#define serial_out(up, offset, value) \
584 (up->port.serial_out(&(up)->port, (offset), (value)))
585/*
586 * We used to support using pause I/O for certain machines. We
587 * haven't supported this for a while, but just in case it's badly
588 * needed for certain old 386 machines, I've left these #define's
589 * in....
590 */
591#define serial_inp(up, offset) serial_in(up, offset)
592#define serial_outp(up, offset, value) serial_out(up, offset, value)
593
594/* Uart divisor latch read */
595static inline int _serial_dl_read(struct uart_8250_port *up)
596{
597 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
598}
599
600/* Uart divisor latch write */
601static inline void _serial_dl_write(struct uart_8250_port *up, int value)
602{
603 serial_outp(up, UART_DLL, value & 0xff);
604 serial_outp(up, UART_DLM, value >> 8 & 0xff);
605}
606
607#if defined(CONFIG_MIPS_ALCHEMY)
608/* Au1x00 haven't got a standard divisor latch */
609static int serial_dl_read(struct uart_8250_port *up)
610{
611 if (up->port.iotype == UPIO_AU)
612 return __raw_readl(up->port.membase + 0x28);
613 else
614 return _serial_dl_read(up);
615}
616
617static void serial_dl_write(struct uart_8250_port *up, int value)
618{
619 if (up->port.iotype == UPIO_AU)
620 __raw_writel(value, up->port.membase + 0x28);
621 else
622 _serial_dl_write(up, value);
623}
624#elif defined(CONFIG_SERIAL_8250_RM9K)
625static int serial_dl_read(struct uart_8250_port *up)
626{
627 return (up->port.iotype == UPIO_RM9000) ?
628 (((__raw_readl(up->port.membase + 0x10) << 8) |
629 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
630 _serial_dl_read(up);
631}
632
633static void serial_dl_write(struct uart_8250_port *up, int value)
634{
635 if (up->port.iotype == UPIO_RM9000) {
636 __raw_writel(value, up->port.membase + 0x08);
637 __raw_writel(value >> 8, up->port.membase + 0x10);
638 } else {
639 _serial_dl_write(up, value);
640 }
641}
642#else
643#define serial_dl_read(up) _serial_dl_read(up)
644#define serial_dl_write(up, value) _serial_dl_write(up, value)
645#endif
646
647/*
648 * For the 16C950
649 */
650static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
651{
652 serial_out(up, UART_SCR, offset);
653 serial_out(up, UART_ICR, value);
654}
655
656static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
657{
658 unsigned int value;
659
660 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
661 serial_out(up, UART_SCR, offset);
662 value = serial_in(up, UART_ICR);
663 serial_icr_write(up, UART_ACR, up->acr);
664
665 return value;
666}
667
668/*
669 * FIFO support.
670 */
671static void serial8250_clear_fifos(struct uart_8250_port *p)
672{
673 if (p->capabilities & UART_CAP_FIFO) {
674 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
675 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
676 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
677 serial_outp(p, UART_FCR, 0);
678 }
679}
680
681/*
682 * IER sleep support. UARTs which have EFRs need the "extended
683 * capability" bit enabled. Note that on XR16C850s, we need to
684 * reset LCR to write to IER.
685 */
686static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
687{
688 if (p->capabilities & UART_CAP_SLEEP) {
689 if (p->capabilities & UART_CAP_EFR) {
690 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
691 serial_outp(p, UART_EFR, UART_EFR_ECB);
692 serial_outp(p, UART_LCR, 0);
693 }
694 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
695 if (p->capabilities & UART_CAP_EFR) {
696 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
697 serial_outp(p, UART_EFR, 0);
698 serial_outp(p, UART_LCR, 0);
699 }
700 }
701}
702
703#ifdef CONFIG_SERIAL_8250_RSA
704/*
705 * Attempts to turn on the RSA FIFO. Returns zero on failure.
706 * We set the port uart clock rate if we succeed.
707 */
708static int __enable_rsa(struct uart_8250_port *up)
709{
710 unsigned char mode;
711 int result;
712
713 mode = serial_inp(up, UART_RSA_MSR);
714 result = mode & UART_RSA_MSR_FIFO;
715
716 if (!result) {
717 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
718 mode = serial_inp(up, UART_RSA_MSR);
719 result = mode & UART_RSA_MSR_FIFO;
720 }
721
722 if (result)
723 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
724
725 return result;
726}
727
728static void enable_rsa(struct uart_8250_port *up)
729{
730 if (up->port.type == PORT_RSA) {
731 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
732 spin_lock_irq(&up->port.lock);
733 __enable_rsa(up);
734 spin_unlock_irq(&up->port.lock);
735 }
736 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
737 serial_outp(up, UART_RSA_FRR, 0);
738 }
739}
740
741/*
742 * Attempts to turn off the RSA FIFO. Returns zero on failure.
743 * It is unknown why interrupts were disabled in here. However,
744 * the caller is expected to preserve this behaviour by grabbing
745 * the spinlock before calling this function.
746 */
747static void disable_rsa(struct uart_8250_port *up)
748{
749 unsigned char mode;
750 int result;
751
752 if (up->port.type == PORT_RSA &&
753 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
754 spin_lock_irq(&up->port.lock);
755
756 mode = serial_inp(up, UART_RSA_MSR);
757 result = !(mode & UART_RSA_MSR_FIFO);
758
759 if (!result) {
760 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
761 mode = serial_inp(up, UART_RSA_MSR);
762 result = !(mode & UART_RSA_MSR_FIFO);
763 }
764
765 if (result)
766 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
767 spin_unlock_irq(&up->port.lock);
768 }
769}
770#endif /* CONFIG_SERIAL_8250_RSA */
771
772/*
773 * This is a quickie test to see how big the FIFO is.
774 * It doesn't work at all the time, more's the pity.
775 */
776static int size_fifo(struct uart_8250_port *up)
777{
778 unsigned char old_fcr, old_mcr, old_lcr;
779 unsigned short old_dl;
780 int count;
781
782 old_lcr = serial_inp(up, UART_LCR);
783 serial_outp(up, UART_LCR, 0);
784 old_fcr = serial_inp(up, UART_FCR);
785 old_mcr = serial_inp(up, UART_MCR);
786 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
787 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
788 serial_outp(up, UART_MCR, UART_MCR_LOOP);
789 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
790 old_dl = serial_dl_read(up);
791 serial_dl_write(up, 0x0001);
792 serial_outp(up, UART_LCR, 0x03);
793 for (count = 0; count < 256; count++)
794 serial_outp(up, UART_TX, count);
795 mdelay(20);/* FIXME - schedule_timeout */
796 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
797 (count < 256); count++)
798 serial_inp(up, UART_RX);
799 serial_outp(up, UART_FCR, old_fcr);
800 serial_outp(up, UART_MCR, old_mcr);
801 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
802 serial_dl_write(up, old_dl);
803 serial_outp(up, UART_LCR, old_lcr);
804
805 return count;
806}
807
808/*
809 * Read UART ID using the divisor method - set DLL and DLM to zero
810 * and the revision will be in DLL and device type in DLM. We
811 * preserve the device state across this.
812 */
813static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
814{
815 unsigned char old_dll, old_dlm, old_lcr;
816 unsigned int id;
817
818 old_lcr = serial_inp(p, UART_LCR);
819 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
820
821 old_dll = serial_inp(p, UART_DLL);
822 old_dlm = serial_inp(p, UART_DLM);
823
824 serial_outp(p, UART_DLL, 0);
825 serial_outp(p, UART_DLM, 0);
826
827 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
828
829 serial_outp(p, UART_DLL, old_dll);
830 serial_outp(p, UART_DLM, old_dlm);
831 serial_outp(p, UART_LCR, old_lcr);
832
833 return id;
834}
835
836/*
837 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
838 * When this function is called we know it is at least a StarTech
839 * 16650 V2, but it might be one of several StarTech UARTs, or one of
840 * its clones. (We treat the broken original StarTech 16650 V1 as a
841 * 16550, and why not? Startech doesn't seem to even acknowledge its
842 * existence.)
843 *
844 * What evil have men's minds wrought...
845 */
846static void autoconfig_has_efr(struct uart_8250_port *up)
847{
848 unsigned int id1, id2, id3, rev;
849
850 /*
851 * Everything with an EFR has SLEEP
852 */
853 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
854
855 /*
856 * First we check to see if it's an Oxford Semiconductor UART.
857 *
858 * If we have to do this here because some non-National
859 * Semiconductor clone chips lock up if you try writing to the
860 * LSR register (which serial_icr_read does)
861 */
862
863 /*
864 * Check for Oxford Semiconductor 16C950.
865 *
866 * EFR [4] must be set else this test fails.
867 *
868 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
869 * claims that it's needed for 952 dual UART's (which are not
870 * recommended for new designs).
871 */
872 up->acr = 0;
873 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
874 serial_out(up, UART_EFR, UART_EFR_ECB);
875 serial_out(up, UART_LCR, 0x00);
876 id1 = serial_icr_read(up, UART_ID1);
877 id2 = serial_icr_read(up, UART_ID2);
878 id3 = serial_icr_read(up, UART_ID3);
879 rev = serial_icr_read(up, UART_REV);
880
881 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
882
883 if (id1 == 0x16 && id2 == 0xC9 &&
884 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
885 up->port.type = PORT_16C950;
886
887 /*
888 * Enable work around for the Oxford Semiconductor 952 rev B
889 * chip which causes it to seriously miscalculate baud rates
890 * when DLL is 0.
891 */
892 if (id3 == 0x52 && rev == 0x01)
893 up->bugs |= UART_BUG_QUOT;
894 return;
895 }
896
897 /*
898 * We check for a XR16C850 by setting DLL and DLM to 0, and then
899 * reading back DLL and DLM. The chip type depends on the DLM
900 * value read back:
901 * 0x10 - XR16C850 and the DLL contains the chip revision.
902 * 0x12 - XR16C2850.
903 * 0x14 - XR16C854.
904 */
905 id1 = autoconfig_read_divisor_id(up);
906 DEBUG_AUTOCONF("850id=%04x ", id1);
907
908 id2 = id1 >> 8;
909 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
910 up->port.type = PORT_16850;
911 return;
912 }
913
914 /*
915 * It wasn't an XR16C850.
916 *
917 * We distinguish between the '654 and the '650 by counting
918 * how many bytes are in the FIFO. I'm using this for now,
919 * since that's the technique that was sent to me in the
920 * serial driver update, but I'm not convinced this works.
921 * I've had problems doing this in the past. -TYT
922 */
923 if (size_fifo(up) == 64)
924 up->port.type = PORT_16654;
925 else
926 up->port.type = PORT_16650V2;
927}
928
929/*
930 * We detected a chip without a FIFO. Only two fall into
931 * this category - the original 8250 and the 16450. The
932 * 16450 has a scratch register (accessible with LCR=0)
933 */
934static void autoconfig_8250(struct uart_8250_port *up)
935{
936 unsigned char scratch, status1, status2;
937
938 up->port.type = PORT_8250;
939
940 scratch = serial_in(up, UART_SCR);
941 serial_outp(up, UART_SCR, 0xa5);
942 status1 = serial_in(up, UART_SCR);
943 serial_outp(up, UART_SCR, 0x5a);
944 status2 = serial_in(up, UART_SCR);
945 serial_outp(up, UART_SCR, scratch);
946
947 if (status1 == 0xa5 && status2 == 0x5a)
948 up->port.type = PORT_16450;
949}
950
951static int broken_efr(struct uart_8250_port *up)
952{
953 /*
954 * Exar ST16C2550 "A2" devices incorrectly detect as
955 * having an EFR, and report an ID of 0x0201. See
956 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
957 */
958 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
959 return 1;
960
961 return 0;
962}
963
964static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
965{
966 unsigned char status;
967
968 status = serial_in(up, 0x04); /* EXCR2 */
969#define PRESL(x) ((x) & 0x30)
970 if (PRESL(status) == 0x10) {
971 /* already in high speed mode */
972 return 0;
973 } else {
974 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
975 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
976 serial_outp(up, 0x04, status);
977 }
978 return 1;
979}
980
981/*
982 * We know that the chip has FIFOs. Does it have an EFR? The
983 * EFR is located in the same register position as the IIR and
984 * we know the top two bits of the IIR are currently set. The
985 * EFR should contain zero. Try to read the EFR.
986 */
987static void autoconfig_16550a(struct uart_8250_port *up)
988{
989 unsigned char status1, status2;
990 unsigned int iersave;
991
992 up->port.type = PORT_16550A;
993 up->capabilities |= UART_CAP_FIFO;
994
995 /*
996 * Check for presence of the EFR when DLAB is set.
997 * Only ST16C650V1 UARTs pass this test.
998 */
999 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1000 if (serial_in(up, UART_EFR) == 0) {
1001 serial_outp(up, UART_EFR, 0xA8);
1002 if (serial_in(up, UART_EFR) != 0) {
1003 DEBUG_AUTOCONF("EFRv1 ");
1004 up->port.type = PORT_16650;
1005 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1006 } else {
1007 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1008 }
1009 serial_outp(up, UART_EFR, 0);
1010 return;
1011 }
1012
1013 /*
1014 * Maybe it requires 0xbf to be written to the LCR.
1015 * (other ST16C650V2 UARTs, TI16C752A, etc)
1016 */
1017 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1018 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1019 DEBUG_AUTOCONF("EFRv2 ");
1020 autoconfig_has_efr(up);
1021 return;
1022 }
1023
1024 /*
1025 * Check for a National Semiconductor SuperIO chip.
1026 * Attempt to switch to bank 2, read the value of the LOOP bit
1027 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1028 * switch back to bank 2, read it from EXCR1 again and check
1029 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1030 */
1031 serial_outp(up, UART_LCR, 0);
1032 status1 = serial_in(up, UART_MCR);
1033 serial_outp(up, UART_LCR, 0xE0);
1034 status2 = serial_in(up, 0x02); /* EXCR1 */
1035
1036 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1037 serial_outp(up, UART_LCR, 0);
1038 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1039 serial_outp(up, UART_LCR, 0xE0);
1040 status2 = serial_in(up, 0x02); /* EXCR1 */
1041 serial_outp(up, UART_LCR, 0);
1042 serial_outp(up, UART_MCR, status1);
1043
1044 if ((status2 ^ status1) & UART_MCR_LOOP) {
1045 unsigned short quot;
1046
1047 serial_outp(up, UART_LCR, 0xE0);
1048
1049 quot = serial_dl_read(up);
1050 quot <<= 3;
1051
1052 if (ns16550a_goto_highspeed(up))
1053 serial_dl_write(up, quot);
1054
1055 serial_outp(up, UART_LCR, 0);
1056
1057 up->port.uartclk = 921600*16;
1058 up->port.type = PORT_NS16550A;
1059 up->capabilities |= UART_NATSEMI;
1060 return;
1061 }
1062 }
1063
1064 /*
1065 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1066 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1067 * Try setting it with and without DLAB set. Cheap clones
1068 * set bit 5 without DLAB set.
1069 */
1070 serial_outp(up, UART_LCR, 0);
1071 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1072 status1 = serial_in(up, UART_IIR) >> 5;
1073 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1074 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1075 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1076 status2 = serial_in(up, UART_IIR) >> 5;
1077 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1078 serial_outp(up, UART_LCR, 0);
1079
1080 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1081
1082 if (status1 == 6 && status2 == 7) {
1083 up->port.type = PORT_16750;
1084 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1085 return;
1086 }
1087
1088 /*
1089 * Try writing and reading the UART_IER_UUE bit (b6).
1090 * If it works, this is probably one of the Xscale platform's
1091 * internal UARTs.
1092 * We're going to explicitly set the UUE bit to 0 before
1093 * trying to write and read a 1 just to make sure it's not
1094 * already a 1 and maybe locked there before we even start start.
1095 */
1096 iersave = serial_in(up, UART_IER);
1097 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1098 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1099 /*
1100 * OK it's in a known zero state, try writing and reading
1101 * without disturbing the current state of the other bits.
1102 */
1103 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1104 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1105 /*
1106 * It's an Xscale.
1107 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1108 */
1109 DEBUG_AUTOCONF("Xscale ");
1110 up->port.type = PORT_XSCALE;
1111 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1112 return;
1113 }
1114 } else {
1115 /*
1116 * If we got here we couldn't force the IER_UUE bit to 0.
1117 * Log it and continue.
1118 */
1119 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1120 }
1121 serial_outp(up, UART_IER, iersave);
1122
1123 /*
1124 * We distinguish between 16550A and U6 16550A by counting
1125 * how many bytes are in the FIFO.
1126 */
1127 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1128 up->port.type = PORT_U6_16550A;
1129 up->capabilities |= UART_CAP_AFE;
1130 }
1131}
1132
1133/*
1134 * This routine is called by rs_init() to initialize a specific serial
1135 * port. It determines what type of UART chip this serial port is
1136 * using: 8250, 16450, 16550, 16550A. The important question is
1137 * whether or not this UART is a 16550A or not, since this will
1138 * determine whether or not we can use its FIFO features or not.
1139 */
1140static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1141{
1142 unsigned char status1, scratch, scratch2, scratch3;
1143 unsigned char save_lcr, save_mcr;
1144 unsigned long flags;
1145
1146 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1147 return;
1148
1149 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1150 serial_index(&up->port), up->port.iobase, up->port.membase);
1151
1152 /*
1153 * We really do need global IRQs disabled here - we're going to
1154 * be frobbing the chips IRQ enable register to see if it exists.
1155 */
1156 spin_lock_irqsave(&up->port.lock, flags);
1157
1158 up->capabilities = 0;
1159 up->bugs = 0;
1160
1161 if (!(up->port.flags & UPF_BUGGY_UART)) {
1162 /*
1163 * Do a simple existence test first; if we fail this,
1164 * there's no point trying anything else.
1165 *
1166 * 0x80 is used as a nonsense port to prevent against
1167 * false positives due to ISA bus float. The
1168 * assumption is that 0x80 is a non-existent port;
1169 * which should be safe since include/asm/io.h also
1170 * makes this assumption.
1171 *
1172 * Note: this is safe as long as MCR bit 4 is clear
1173 * and the device is in "PC" mode.
1174 */
1175 scratch = serial_inp(up, UART_IER);
1176 serial_outp(up, UART_IER, 0);
1177#ifdef __i386__
1178 outb(0xff, 0x080);
1179#endif
1180 /*
1181 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1182 * 16C754B) allow only to modify them if an EFR bit is set.
1183 */
1184 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1185 serial_outp(up, UART_IER, 0x0F);
1186#ifdef __i386__
1187 outb(0, 0x080);
1188#endif
1189 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1190 serial_outp(up, UART_IER, scratch);
1191 if (scratch2 != 0 || scratch3 != 0x0F) {
1192 /*
1193 * We failed; there's nothing here
1194 */
1195 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1196 scratch2, scratch3);
1197 goto out;
1198 }
1199 }
1200
1201 save_mcr = serial_in(up, UART_MCR);
1202 save_lcr = serial_in(up, UART_LCR);
1203
1204 /*
1205 * Check to see if a UART is really there. Certain broken
1206 * internal modems based on the Rockwell chipset fail this
1207 * test, because they apparently don't implement the loopback
1208 * test mode. So this test is skipped on the COM 1 through
1209 * COM 4 ports. This *should* be safe, since no board
1210 * manufacturer would be stupid enough to design a board
1211 * that conflicts with COM 1-4 --- we hope!
1212 */
1213 if (!(up->port.flags & UPF_SKIP_TEST)) {
1214 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1215 status1 = serial_inp(up, UART_MSR) & 0xF0;
1216 serial_outp(up, UART_MCR, save_mcr);
1217 if (status1 != 0x90) {
1218 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1219 status1);
1220 goto out;
1221 }
1222 }
1223
1224 /*
1225 * We're pretty sure there's a port here. Lets find out what
1226 * type of port it is. The IIR top two bits allows us to find
1227 * out if it's 8250 or 16450, 16550, 16550A or later. This
1228 * determines what we test for next.
1229 *
1230 * We also initialise the EFR (if any) to zero for later. The
1231 * EFR occupies the same register location as the FCR and IIR.
1232 */
1233 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1234 serial_outp(up, UART_EFR, 0);
1235 serial_outp(up, UART_LCR, 0);
1236
1237 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1238 scratch = serial_in(up, UART_IIR) >> 6;
1239
1240 DEBUG_AUTOCONF("iir=%d ", scratch);
1241
1242 switch (scratch) {
1243 case 0:
1244 autoconfig_8250(up);
1245 break;
1246 case 1:
1247 up->port.type = PORT_UNKNOWN;
1248 break;
1249 case 2:
1250 up->port.type = PORT_16550;
1251 break;
1252 case 3:
1253 autoconfig_16550a(up);
1254 break;
1255 }
1256
1257#ifdef CONFIG_SERIAL_8250_RSA
1258 /*
1259 * Only probe for RSA ports if we got the region.
1260 */
1261 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1262 int i;
1263
1264 for (i = 0 ; i < probe_rsa_count; ++i) {
1265 if (probe_rsa[i] == up->port.iobase &&
1266 __enable_rsa(up)) {
1267 up->port.type = PORT_RSA;
1268 break;
1269 }
1270 }
1271 }
1272#endif
1273
1274 serial_outp(up, UART_LCR, save_lcr);
1275
1276 if (up->capabilities != uart_config[up->port.type].flags) {
1277 printk(KERN_WARNING
1278 "ttyS%d: detected caps %08x should be %08x\n",
1279 serial_index(&up->port), up->capabilities,
1280 uart_config[up->port.type].flags);
1281 }
1282
1283 up->port.fifosize = uart_config[up->port.type].fifo_size;
1284 up->capabilities = uart_config[up->port.type].flags;
1285 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1286
1287 if (up->port.type == PORT_UNKNOWN)
1288 goto out;
1289
1290 /*
1291 * Reset the UART.
1292 */
1293#ifdef CONFIG_SERIAL_8250_RSA
1294 if (up->port.type == PORT_RSA)
1295 serial_outp(up, UART_RSA_FRR, 0);
1296#endif
1297 serial_outp(up, UART_MCR, save_mcr);
1298 serial8250_clear_fifos(up);
1299 serial_in(up, UART_RX);
1300 if (up->capabilities & UART_CAP_UUE)
1301 serial_outp(up, UART_IER, UART_IER_UUE);
1302 else
1303 serial_outp(up, UART_IER, 0);
1304
1305 out:
1306 spin_unlock_irqrestore(&up->port.lock, flags);
1307 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1308}
1309
1310static void autoconfig_irq(struct uart_8250_port *up)
1311{
1312 unsigned char save_mcr, save_ier;
1313 unsigned char save_ICP = 0;
1314 unsigned int ICP = 0;
1315 unsigned long irqs;
1316 int irq;
1317
1318 if (up->port.flags & UPF_FOURPORT) {
1319 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1320 save_ICP = inb_p(ICP);
1321 outb_p(0x80, ICP);
1322 (void) inb_p(ICP);
1323 }
1324
1325 /* forget possible initially masked and pending IRQ */
1326 probe_irq_off(probe_irq_on());
1327 save_mcr = serial_inp(up, UART_MCR);
1328 save_ier = serial_inp(up, UART_IER);
1329 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1330
1331 irqs = probe_irq_on();
1332 serial_outp(up, UART_MCR, 0);
1333 udelay(10);
1334 if (up->port.flags & UPF_FOURPORT) {
1335 serial_outp(up, UART_MCR,
1336 UART_MCR_DTR | UART_MCR_RTS);
1337 } else {
1338 serial_outp(up, UART_MCR,
1339 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1340 }
1341 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1342 (void)serial_inp(up, UART_LSR);
1343 (void)serial_inp(up, UART_RX);
1344 (void)serial_inp(up, UART_IIR);
1345 (void)serial_inp(up, UART_MSR);
1346 serial_outp(up, UART_TX, 0xFF);
1347 udelay(20);
1348 irq = probe_irq_off(irqs);
1349
1350 serial_outp(up, UART_MCR, save_mcr);
1351 serial_outp(up, UART_IER, save_ier);
1352
1353 if (up->port.flags & UPF_FOURPORT)
1354 outb_p(save_ICP, ICP);
1355
1356 up->port.irq = (irq > 0) ? irq : 0;
1357}
1358
1359static inline void __stop_tx(struct uart_8250_port *p)
1360{
1361 if (p->ier & UART_IER_THRI) {
1362 p->ier &= ~UART_IER_THRI;
1363 serial_out(p, UART_IER, p->ier);
1364 }
1365}
1366
1367static void serial8250_stop_tx(struct uart_port *port)
1368{
1369 struct uart_8250_port *up =
1370 container_of(port, struct uart_8250_port, port);
1371
1372 __stop_tx(up);
1373
1374 /*
1375 * We really want to stop the transmitter from sending.
1376 */
1377 if (up->port.type == PORT_16C950) {
1378 up->acr |= UART_ACR_TXDIS;
1379 serial_icr_write(up, UART_ACR, up->acr);
1380 }
1381}
1382
1383static void transmit_chars(struct uart_8250_port *up);
1384
1385static void serial8250_start_tx(struct uart_port *port)
1386{
1387 struct uart_8250_port *up =
1388 container_of(port, struct uart_8250_port, port);
1389
1390 if (!(up->ier & UART_IER_THRI)) {
1391 up->ier |= UART_IER_THRI;
1392 serial_out(up, UART_IER, up->ier);
1393
1394 if (up->bugs & UART_BUG_TXEN) {
1395 unsigned char lsr;
1396 lsr = serial_in(up, UART_LSR);
1397 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1398 if ((up->port.type == PORT_RM9000) ?
1399 (lsr & UART_LSR_THRE) :
1400 (lsr & UART_LSR_TEMT))
1401 transmit_chars(up);
1402 }
1403 }
1404
1405 /*
1406 * Re-enable the transmitter if we disabled it.
1407 */
1408 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1409 up->acr &= ~UART_ACR_TXDIS;
1410 serial_icr_write(up, UART_ACR, up->acr);
1411 }
1412}
1413
1414static void serial8250_stop_rx(struct uart_port *port)
1415{
1416 struct uart_8250_port *up =
1417 container_of(port, struct uart_8250_port, port);
1418
1419 up->ier &= ~UART_IER_RLSI;
1420 up->port.read_status_mask &= ~UART_LSR_DR;
1421 serial_out(up, UART_IER, up->ier);
1422}
1423
1424static void serial8250_enable_ms(struct uart_port *port)
1425{
1426 struct uart_8250_port *up =
1427 container_of(port, struct uart_8250_port, port);
1428
1429 /* no MSR capabilities */
1430 if (up->bugs & UART_BUG_NOMSR)
1431 return;
1432
1433 up->ier |= UART_IER_MSI;
1434 serial_out(up, UART_IER, up->ier);
1435}
1436
1437/*
1438 * Clear the Tegra rx fifo after a break
1439 *
1440 * FIXME: This needs to become a port specific callback once we have a
1441 * framework for this
1442 */
1443static void clear_rx_fifo(struct uart_8250_port *up)
1444{
1445 unsigned int status, tmout = 10000;
1446 do {
1447 status = serial_in(up, UART_LSR);
1448 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1449 status = serial_in(up, UART_RX);
1450 else
1451 break;
1452 if (--tmout == 0)
1453 break;
1454 udelay(1);
1455 } while (1);
1456}
1457
1458static void
1459receive_chars(struct uart_8250_port *up, unsigned int *status)
1460{
1461 struct tty_struct *tty = up->port.state->port.tty;
1462 unsigned char ch, lsr = *status;
1463 int max_count = 256;
1464 char flag;
1465
1466 do {
1467 if (likely(lsr & UART_LSR_DR))
1468 ch = serial_inp(up, UART_RX);
1469 else
1470 /*
1471 * Intel 82571 has a Serial Over Lan device that will
1472 * set UART_LSR_BI without setting UART_LSR_DR when
1473 * it receives a break. To avoid reading from the
1474 * receive buffer without UART_LSR_DR bit set, we
1475 * just force the read character to be 0
1476 */
1477 ch = 0;
1478
1479 flag = TTY_NORMAL;
1480 up->port.icount.rx++;
1481
1482 lsr |= up->lsr_saved_flags;
1483 up->lsr_saved_flags = 0;
1484
1485 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1486 /*
1487 * For statistics only
1488 */
1489 if (lsr & UART_LSR_BI) {
1490 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1491 up->port.icount.brk++;
1492 /*
1493 * If tegra port then clear the rx fifo to
1494 * accept another break/character.
1495 */
1496 if (up->port.type == PORT_TEGRA)
1497 clear_rx_fifo(up);
1498
1499 /*
1500 * We do the SysRQ and SAK checking
1501 * here because otherwise the break
1502 * may get masked by ignore_status_mask
1503 * or read_status_mask.
1504 */
1505 if (uart_handle_break(&up->port))
1506 goto ignore_char;
1507 } else if (lsr & UART_LSR_PE)
1508 up->port.icount.parity++;
1509 else if (lsr & UART_LSR_FE)
1510 up->port.icount.frame++;
1511 if (lsr & UART_LSR_OE)
1512 up->port.icount.overrun++;
1513
1514 /*
1515 * Mask off conditions which should be ignored.
1516 */
1517 lsr &= up->port.read_status_mask;
1518
1519 if (lsr & UART_LSR_BI) {
1520 DEBUG_INTR("handling break....");
1521 flag = TTY_BREAK;
1522 } else if (lsr & UART_LSR_PE)
1523 flag = TTY_PARITY;
1524 else if (lsr & UART_LSR_FE)
1525 flag = TTY_FRAME;
1526 }
1527 if (uart_handle_sysrq_char(&up->port, ch))
1528 goto ignore_char;
1529
1530 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1531
1532ignore_char:
1533 lsr = serial_inp(up, UART_LSR);
1534 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1535 spin_unlock(&up->port.lock);
1536 tty_flip_buffer_push(tty);
1537 spin_lock(&up->port.lock);
1538 *status = lsr;
1539}
1540
1541static void transmit_chars(struct uart_8250_port *up)
1542{
1543 struct circ_buf *xmit = &up->port.state->xmit;
1544 int count;
1545
1546 if (up->port.x_char) {
1547 serial_outp(up, UART_TX, up->port.x_char);
1548 up->port.icount.tx++;
1549 up->port.x_char = 0;
1550 return;
1551 }
1552 if (uart_tx_stopped(&up->port)) {
1553 serial8250_stop_tx(&up->port);
1554 return;
1555 }
1556 if (uart_circ_empty(xmit)) {
1557 __stop_tx(up);
1558 return;
1559 }
1560
1561 count = up->tx_loadsz;
1562 do {
1563 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1564 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1565 up->port.icount.tx++;
1566 if (uart_circ_empty(xmit))
1567 break;
1568 } while (--count > 0);
1569
1570 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1571 uart_write_wakeup(&up->port);
1572
1573 DEBUG_INTR("THRE...");
1574
1575 if (uart_circ_empty(xmit))
1576 __stop_tx(up);
1577}
1578
1579static unsigned int check_modem_status(struct uart_8250_port *up)
1580{
1581 unsigned int status = serial_in(up, UART_MSR);
1582
1583 status |= up->msr_saved_flags;
1584 up->msr_saved_flags = 0;
1585 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1586 up->port.state != NULL) {
1587 if (status & UART_MSR_TERI)
1588 up->port.icount.rng++;
1589 if (status & UART_MSR_DDSR)
1590 up->port.icount.dsr++;
1591 if (status & UART_MSR_DDCD)
1592 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1593 if (status & UART_MSR_DCTS)
1594 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1595
1596 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1597 }
1598
1599 return status;
1600}
1601
1602/*
1603 * This handles the interrupt from one port.
1604 */
1605static void serial8250_handle_port(struct uart_8250_port *up)
1606{
1607 unsigned int status;
1608 unsigned long flags;
1609
1610 spin_lock_irqsave(&up->port.lock, flags);
1611
1612 status = serial_inp(up, UART_LSR);
1613
1614 DEBUG_INTR("status = %x...", status);
1615
1616 if (status & (UART_LSR_DR | UART_LSR_BI))
1617 receive_chars(up, &status);
1618 check_modem_status(up);
1619 if (status & UART_LSR_THRE)
1620 transmit_chars(up);
1621
1622 spin_unlock_irqrestore(&up->port.lock, flags);
1623}
1624
1625/*
1626 * This is the serial driver's interrupt routine.
1627 *
1628 * Arjan thinks the old way was overly complex, so it got simplified.
1629 * Alan disagrees, saying that need the complexity to handle the weird
1630 * nature of ISA shared interrupts. (This is a special exception.)
1631 *
1632 * In order to handle ISA shared interrupts properly, we need to check
1633 * that all ports have been serviced, and therefore the ISA interrupt
1634 * line has been de-asserted.
1635 *
1636 * This means we need to loop through all ports. checking that they
1637 * don't have an interrupt pending.
1638 */
1639static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1640{
1641 struct irq_info *i = dev_id;
1642 struct list_head *l, *end = NULL;
1643 int pass_counter = 0, handled = 0;
1644
1645 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1646
1647 spin_lock(&i->lock);
1648
1649 l = i->head;
1650 do {
1651 struct uart_8250_port *up;
1652 unsigned int iir;
1653
1654 up = list_entry(l, struct uart_8250_port, list);
1655
1656 iir = serial_in(up, UART_IIR);
1657 if (!(iir & UART_IIR_NO_INT)) {
1658 serial8250_handle_port(up);
1659
1660 handled = 1;
1661
1662 end = NULL;
1663 } else if ((up->port.iotype == UPIO_DWAPB ||
1664 up->port.iotype == UPIO_DWAPB32) &&
1665 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1666 /* The DesignWare APB UART has an Busy Detect (0x07)
1667 * interrupt meaning an LCR write attempt occurred while the
1668 * UART was busy. The interrupt must be cleared by reading
1669 * the UART status register (USR) and the LCR re-written. */
1670 unsigned int status;
1671 status = *(volatile u32 *)up->port.private_data;
1672 serial_out(up, UART_LCR, up->lcr);
1673
1674 handled = 1;
1675
1676 end = NULL;
1677 } else if (end == NULL)
1678 end = l;
1679
1680 l = l->next;
1681
1682 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1683 /* If we hit this, we're dead. */
1684 printk_ratelimited(KERN_ERR
1685 "serial8250: too much work for irq%d\n", irq);
1686 break;
1687 }
1688 } while (l != end);
1689
1690 spin_unlock(&i->lock);
1691
1692 DEBUG_INTR("end.\n");
1693
1694 return IRQ_RETVAL(handled);
1695}
1696
1697/*
1698 * To support ISA shared interrupts, we need to have one interrupt
1699 * handler that ensures that the IRQ line has been deasserted
1700 * before returning. Failing to do this will result in the IRQ
1701 * line being stuck active, and, since ISA irqs are edge triggered,
1702 * no more IRQs will be seen.
1703 */
1704static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1705{
1706 spin_lock_irq(&i->lock);
1707
1708 if (!list_empty(i->head)) {
1709 if (i->head == &up->list)
1710 i->head = i->head->next;
1711 list_del(&up->list);
1712 } else {
1713 BUG_ON(i->head != &up->list);
1714 i->head = NULL;
1715 }
1716 spin_unlock_irq(&i->lock);
1717 /* List empty so throw away the hash node */
1718 if (i->head == NULL) {
1719 hlist_del(&i->node);
1720 kfree(i);
1721 }
1722}
1723
1724static int serial_link_irq_chain(struct uart_8250_port *up)
1725{
1726 struct hlist_head *h;
1727 struct hlist_node *n;
1728 struct irq_info *i;
1729 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1730
1731 mutex_lock(&hash_mutex);
1732
1733 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1734
1735 hlist_for_each(n, h) {
1736 i = hlist_entry(n, struct irq_info, node);
1737 if (i->irq == up->port.irq)
1738 break;
1739 }
1740
1741 if (n == NULL) {
1742 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1743 if (i == NULL) {
1744 mutex_unlock(&hash_mutex);
1745 return -ENOMEM;
1746 }
1747 spin_lock_init(&i->lock);
1748 i->irq = up->port.irq;
1749 hlist_add_head(&i->node, h);
1750 }
1751 mutex_unlock(&hash_mutex);
1752
1753 spin_lock_irq(&i->lock);
1754
1755 if (i->head) {
1756 list_add(&up->list, i->head);
1757 spin_unlock_irq(&i->lock);
1758
1759 ret = 0;
1760 } else {
1761 INIT_LIST_HEAD(&up->list);
1762 i->head = &up->list;
1763 spin_unlock_irq(&i->lock);
1764 irq_flags |= up->port.irqflags;
1765 ret = request_irq(up->port.irq, serial8250_interrupt,
1766 irq_flags, "serial", i);
1767 if (ret < 0)
1768 serial_do_unlink(i, up);
1769 }
1770
1771 return ret;
1772}
1773
1774static void serial_unlink_irq_chain(struct uart_8250_port *up)
1775{
1776 struct irq_info *i;
1777 struct hlist_node *n;
1778 struct hlist_head *h;
1779
1780 mutex_lock(&hash_mutex);
1781
1782 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1783
1784 hlist_for_each(n, h) {
1785 i = hlist_entry(n, struct irq_info, node);
1786 if (i->irq == up->port.irq)
1787 break;
1788 }
1789
1790 BUG_ON(n == NULL);
1791 BUG_ON(i->head == NULL);
1792
1793 if (list_empty(i->head))
1794 free_irq(up->port.irq, i);
1795
1796 serial_do_unlink(i, up);
1797 mutex_unlock(&hash_mutex);
1798}
1799
1800/*
1801 * This function is used to handle ports that do not have an
1802 * interrupt. This doesn't work very well for 16450's, but gives
1803 * barely passable results for a 16550A. (Although at the expense
1804 * of much CPU overhead).
1805 */
1806static void serial8250_timeout(unsigned long data)
1807{
1808 struct uart_8250_port *up = (struct uart_8250_port *)data;
1809 unsigned int iir;
1810
1811 iir = serial_in(up, UART_IIR);
1812 if (!(iir & UART_IIR_NO_INT))
1813 serial8250_handle_port(up);
1814 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1815}
1816
1817static void serial8250_backup_timeout(unsigned long data)
1818{
1819 struct uart_8250_port *up = (struct uart_8250_port *)data;
1820 unsigned int iir, ier = 0, lsr;
1821 unsigned long flags;
1822
1823 spin_lock_irqsave(&up->port.lock, flags);
1824
1825 /*
1826 * Must disable interrupts or else we risk racing with the interrupt
1827 * based handler.
1828 */
1829 if (is_real_interrupt(up->port.irq)) {
1830 ier = serial_in(up, UART_IER);
1831 serial_out(up, UART_IER, 0);
1832 }
1833
1834 iir = serial_in(up, UART_IIR);
1835
1836 /*
1837 * This should be a safe test for anyone who doesn't trust the
1838 * IIR bits on their UART, but it's specifically designed for
1839 * the "Diva" UART used on the management processor on many HP
1840 * ia64 and parisc boxes.
1841 */
1842 lsr = serial_in(up, UART_LSR);
1843 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1844 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1845 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1846 (lsr & UART_LSR_THRE)) {
1847 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1848 iir |= UART_IIR_THRI;
1849 }
1850
1851 if (!(iir & UART_IIR_NO_INT))
1852 transmit_chars(up);
1853
1854 if (is_real_interrupt(up->port.irq))
1855 serial_out(up, UART_IER, ier);
1856
1857 spin_unlock_irqrestore(&up->port.lock, flags);
1858
1859 /* Standard timer interval plus 0.2s to keep the port running */
1860 mod_timer(&up->timer,
1861 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1862}
1863
1864static unsigned int serial8250_tx_empty(struct uart_port *port)
1865{
1866 struct uart_8250_port *up =
1867 container_of(port, struct uart_8250_port, port);
1868 unsigned long flags;
1869 unsigned int lsr;
1870
1871 spin_lock_irqsave(&up->port.lock, flags);
1872 lsr = serial_in(up, UART_LSR);
1873 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1874 spin_unlock_irqrestore(&up->port.lock, flags);
1875
1876 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1877}
1878
1879static unsigned int serial8250_get_mctrl(struct uart_port *port)
1880{
1881 struct uart_8250_port *up =
1882 container_of(port, struct uart_8250_port, port);
1883 unsigned int status;
1884 unsigned int ret;
1885
1886 status = check_modem_status(up);
1887
1888 ret = 0;
1889 if (status & UART_MSR_DCD)
1890 ret |= TIOCM_CAR;
1891 if (status & UART_MSR_RI)
1892 ret |= TIOCM_RNG;
1893 if (status & UART_MSR_DSR)
1894 ret |= TIOCM_DSR;
1895 if (status & UART_MSR_CTS)
1896 ret |= TIOCM_CTS;
1897 return ret;
1898}
1899
1900static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1901{
1902 struct uart_8250_port *up =
1903 container_of(port, struct uart_8250_port, port);
1904 unsigned char mcr = 0;
1905
1906 if (up->port.type == PORT_TEGRA) {
1907 if (mctrl & TIOCM_RTS)
1908 mcr |= UART_MCR_HW_RTS;
1909 } else {
1910 if (mctrl & TIOCM_RTS)
1911 mcr |= UART_MCR_RTS;
1912 }
1913 if (mctrl & TIOCM_DTR)
1914 mcr |= UART_MCR_DTR;
1915 if (mctrl & TIOCM_OUT1)
1916 mcr |= UART_MCR_OUT1;
1917 if (mctrl & TIOCM_OUT2)
1918 mcr |= UART_MCR_OUT2;
1919 if (mctrl & TIOCM_LOOP)
1920 mcr |= UART_MCR_LOOP;
1921
1922 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1923
1924 serial_out(up, UART_MCR, mcr);
1925}
1926
1927static void serial8250_break_ctl(struct uart_port *port, int break_state)
1928{
1929 struct uart_8250_port *up =
1930 container_of(port, struct uart_8250_port, port);
1931 unsigned long flags;
1932
1933 spin_lock_irqsave(&up->port.lock, flags);
1934 if (break_state == -1)
1935 up->lcr |= UART_LCR_SBC;
1936 else
1937 up->lcr &= ~UART_LCR_SBC;
1938 serial_out(up, UART_LCR, up->lcr);
1939 spin_unlock_irqrestore(&up->port.lock, flags);
1940}
1941
1942/*
1943 * Wait for transmitter & holding register to empty
1944 */
1945static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1946{
1947 unsigned int status, tmout = 10000;
1948
1949 /* Wait up to 10ms for the character(s) to be sent. */
1950 for (;;) {
1951 status = serial_in(up, UART_LSR);
1952
1953 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1954
1955 if ((status & bits) == bits)
1956 break;
1957 if (--tmout == 0)
1958 break;
1959 udelay(1);
1960 }
1961
1962 /* Wait up to 1s for flow control if necessary */
1963 if (up->port.flags & UPF_CONS_FLOW) {
1964 unsigned int tmout;
1965 for (tmout = 1000000; tmout; tmout--) {
1966 unsigned int msr = serial_in(up, UART_MSR);
1967 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1968 if (msr & UART_MSR_CTS)
1969 break;
1970 udelay(1);
1971 touch_nmi_watchdog();
1972 }
1973 }
1974}
1975
1976#ifdef CONFIG_CONSOLE_POLL
1977/*
1978 * Console polling routines for writing and reading from the uart while
1979 * in an interrupt or debug context.
1980 */
1981
1982static int serial8250_get_poll_char(struct uart_port *port)
1983{
1984 struct uart_8250_port *up =
1985 container_of(port, struct uart_8250_port, port);
1986 unsigned char lsr = serial_inp(up, UART_LSR);
1987
1988 if (!(lsr & UART_LSR_DR))
1989 return NO_POLL_CHAR;
1990
1991 return serial_inp(up, UART_RX);
1992}
1993
1994
1995static void serial8250_put_poll_char(struct uart_port *port,
1996 unsigned char c)
1997{
1998 unsigned int ier;
1999 struct uart_8250_port *up =
2000 container_of(port, struct uart_8250_port, port);
2001
2002 /*
2003 * First save the IER then disable the interrupts
2004 */
2005 ier = serial_in(up, UART_IER);
2006 if (up->capabilities & UART_CAP_UUE)
2007 serial_out(up, UART_IER, UART_IER_UUE);
2008 else
2009 serial_out(up, UART_IER, 0);
2010
2011 wait_for_xmitr(up, BOTH_EMPTY);
2012 /*
2013 * Send the character out.
2014 * If a LF, also do CR...
2015 */
2016 serial_out(up, UART_TX, c);
2017 if (c == 10) {
2018 wait_for_xmitr(up, BOTH_EMPTY);
2019 serial_out(up, UART_TX, 13);
2020 }
2021
2022 /*
2023 * Finally, wait for transmitter to become empty
2024 * and restore the IER
2025 */
2026 wait_for_xmitr(up, BOTH_EMPTY);
2027 serial_out(up, UART_IER, ier);
2028}
2029
2030#endif /* CONFIG_CONSOLE_POLL */
2031
2032static int serial8250_startup(struct uart_port *port)
2033{
2034 struct uart_8250_port *up =
2035 container_of(port, struct uart_8250_port, port);
2036 unsigned long flags;
2037 unsigned char lsr, iir;
2038 int retval;
2039
2040 up->port.fifosize = uart_config[up->port.type].fifo_size;
2041 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
2042 up->capabilities = uart_config[up->port.type].flags;
2043 up->mcr = 0;
2044
2045 if (up->port.iotype != up->cur_iotype)
2046 set_io_from_upio(port);
2047
2048 if (up->port.type == PORT_16C950) {
2049 /* Wake up and initialize UART */
2050 up->acr = 0;
2051 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2052 serial_outp(up, UART_EFR, UART_EFR_ECB);
2053 serial_outp(up, UART_IER, 0);
2054 serial_outp(up, UART_LCR, 0);
2055 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2056 serial_outp(up, UART_LCR, 0xBF);
2057 serial_outp(up, UART_EFR, UART_EFR_ECB);
2058 serial_outp(up, UART_LCR, 0);
2059 }
2060
2061#ifdef CONFIG_SERIAL_8250_RSA
2062 /*
2063 * If this is an RSA port, see if we can kick it up to the
2064 * higher speed clock.
2065 */
2066 enable_rsa(up);
2067#endif
2068
2069 /*
2070 * Clear the FIFO buffers and disable them.
2071 * (they will be reenabled in set_termios())
2072 */
2073 serial8250_clear_fifos(up);
2074
2075 /*
2076 * Clear the interrupt registers.
2077 */
2078 (void) serial_inp(up, UART_LSR);
2079 (void) serial_inp(up, UART_RX);
2080 (void) serial_inp(up, UART_IIR);
2081 (void) serial_inp(up, UART_MSR);
2082
2083 /*
2084 * At this point, there's no way the LSR could still be 0xff;
2085 * if it is, then bail out, because there's likely no UART
2086 * here.
2087 */
2088 if (!(up->port.flags & UPF_BUGGY_UART) &&
2089 (serial_inp(up, UART_LSR) == 0xff)) {
2090 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2091 serial_index(&up->port));
2092 return -ENODEV;
2093 }
2094
2095 /*
2096 * For a XR16C850, we need to set the trigger levels
2097 */
2098 if (up->port.type == PORT_16850) {
2099 unsigned char fctr;
2100
2101 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2102
2103 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2104 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2105 serial_outp(up, UART_TRG, UART_TRG_96);
2106 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2107 serial_outp(up, UART_TRG, UART_TRG_96);
2108
2109 serial_outp(up, UART_LCR, 0);
2110 }
2111
2112 if (is_real_interrupt(up->port.irq)) {
2113 unsigned char iir1;
2114 /*
2115 * Test for UARTs that do not reassert THRE when the
2116 * transmitter is idle and the interrupt has already
2117 * been cleared. Real 16550s should always reassert
2118 * this interrupt whenever the transmitter is idle and
2119 * the interrupt is enabled. Delays are necessary to
2120 * allow register changes to become visible.
2121 */
2122 spin_lock_irqsave(&up->port.lock, flags);
2123 if (up->port.irqflags & IRQF_SHARED)
2124 disable_irq_nosync(up->port.irq);
2125
2126 wait_for_xmitr(up, UART_LSR_THRE);
2127 serial_out_sync(up, UART_IER, UART_IER_THRI);
2128 udelay(1); /* allow THRE to set */
2129 iir1 = serial_in(up, UART_IIR);
2130 serial_out(up, UART_IER, 0);
2131 serial_out_sync(up, UART_IER, UART_IER_THRI);
2132 udelay(1); /* allow a working UART time to re-assert THRE */
2133 iir = serial_in(up, UART_IIR);
2134 serial_out(up, UART_IER, 0);
2135
2136 if (up->port.irqflags & IRQF_SHARED)
2137 enable_irq(up->port.irq);
2138 spin_unlock_irqrestore(&up->port.lock, flags);
2139
2140 /*
2141 * If the interrupt is not reasserted, setup a timer to
2142 * kick the UART on a regular basis.
2143 */
2144 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2145 up->bugs |= UART_BUG_THRE;
2146 pr_debug("ttyS%d - using backup timer\n",
2147 serial_index(port));
2148 }
2149 }
2150
2151 /*
2152 * The above check will only give an accurate result the first time
2153 * the port is opened so this value needs to be preserved.
2154 */
2155 if (up->bugs & UART_BUG_THRE) {
2156 up->timer.function = serial8250_backup_timeout;
2157 up->timer.data = (unsigned long)up;
2158 mod_timer(&up->timer, jiffies +
2159 uart_poll_timeout(port) + HZ / 5);
2160 }
2161
2162 /*
2163 * If the "interrupt" for this port doesn't correspond with any
2164 * hardware interrupt, we use a timer-based system. The original
2165 * driver used to do this with IRQ0.
2166 */
2167 if (!is_real_interrupt(up->port.irq)) {
2168 up->timer.data = (unsigned long)up;
2169 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2170 } else {
2171 retval = serial_link_irq_chain(up);
2172 if (retval)
2173 return retval;
2174 }
2175
2176 /*
2177 * Now, initialize the UART
2178 */
2179 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2180
2181 spin_lock_irqsave(&up->port.lock, flags);
2182 if (up->port.flags & UPF_FOURPORT) {
2183 if (!is_real_interrupt(up->port.irq))
2184 up->port.mctrl |= TIOCM_OUT1;
2185 } else
2186 /*
2187 * Most PC uarts need OUT2 raised to enable interrupts.
2188 */
2189 if (is_real_interrupt(up->port.irq))
2190 up->port.mctrl |= TIOCM_OUT2;
2191
2192 serial8250_set_mctrl(&up->port, up->port.mctrl);
2193
2194 /* Serial over Lan (SoL) hack:
2195 Intel 8257x Gigabit ethernet chips have a
2196 16550 emulation, to be used for Serial Over Lan.
2197 Those chips take a longer time than a normal
2198 serial device to signalize that a transmission
2199 data was queued. Due to that, the above test generally
2200 fails. One solution would be to delay the reading of
2201 iir. However, this is not reliable, since the timeout
2202 is variable. So, let's just don't test if we receive
2203 TX irq. This way, we'll never enable UART_BUG_TXEN.
2204 */
2205 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2206 goto dont_test_tx_en;
2207
2208 /*
2209 * Do a quick test to see if we receive an
2210 * interrupt when we enable the TX irq.
2211 */
2212 serial_outp(up, UART_IER, UART_IER_THRI);
2213 lsr = serial_in(up, UART_LSR);
2214 iir = serial_in(up, UART_IIR);
2215 serial_outp(up, UART_IER, 0);
2216
2217 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2218 if (!(up->bugs & UART_BUG_TXEN)) {
2219 up->bugs |= UART_BUG_TXEN;
2220 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2221 serial_index(port));
2222 }
2223 } else {
2224 up->bugs &= ~UART_BUG_TXEN;
2225 }
2226
2227dont_test_tx_en:
2228 spin_unlock_irqrestore(&up->port.lock, flags);
2229
2230 /*
2231 * Clear the interrupt registers again for luck, and clear the
2232 * saved flags to avoid getting false values from polling
2233 * routines or the previous session.
2234 */
2235 serial_inp(up, UART_LSR);
2236 serial_inp(up, UART_RX);
2237 serial_inp(up, UART_IIR);
2238 serial_inp(up, UART_MSR);
2239 up->lsr_saved_flags = 0;
2240 up->msr_saved_flags = 0;
2241
2242 /*
2243 * Finally, enable interrupts. Note: Modem status interrupts
2244 * are set via set_termios(), which will be occurring imminently
2245 * anyway, so we don't enable them here.
2246 */
2247 up->ier = UART_IER_RLSI | UART_IER_RDI;
2248 serial_outp(up, UART_IER, up->ier);
2249
2250 if (up->port.flags & UPF_FOURPORT) {
2251 unsigned int icp;
2252 /*
2253 * Enable interrupts on the AST Fourport board
2254 */
2255 icp = (up->port.iobase & 0xfe0) | 0x01f;
2256 outb_p(0x80, icp);
2257 (void) inb_p(icp);
2258 }
2259
2260 return 0;
2261}
2262
2263static void serial8250_shutdown(struct uart_port *port)
2264{
2265 struct uart_8250_port *up =
2266 container_of(port, struct uart_8250_port, port);
2267 unsigned long flags;
2268
2269 /*
2270 * Disable interrupts from this port
2271 */
2272 up->ier = 0;
2273 serial_outp(up, UART_IER, 0);
2274
2275 spin_lock_irqsave(&up->port.lock, flags);
2276 if (up->port.flags & UPF_FOURPORT) {
2277 /* reset interrupts on the AST Fourport board */
2278 inb((up->port.iobase & 0xfe0) | 0x1f);
2279 up->port.mctrl |= TIOCM_OUT1;
2280 } else
2281 up->port.mctrl &= ~TIOCM_OUT2;
2282
2283 serial8250_set_mctrl(&up->port, up->port.mctrl);
2284 spin_unlock_irqrestore(&up->port.lock, flags);
2285
2286 /*
2287 * Disable break condition and FIFOs
2288 */
2289 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2290 serial8250_clear_fifos(up);
2291
2292#ifdef CONFIG_SERIAL_8250_RSA
2293 /*
2294 * Reset the RSA board back to 115kbps compat mode.
2295 */
2296 disable_rsa(up);
2297#endif
2298
2299 /*
2300 * Read data port to reset things, and then unlink from
2301 * the IRQ chain.
2302 */
2303 (void) serial_in(up, UART_RX);
2304
2305 del_timer_sync(&up->timer);
2306 up->timer.function = serial8250_timeout;
2307 if (is_real_interrupt(up->port.irq))
2308 serial_unlink_irq_chain(up);
2309}
2310
2311static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2312{
2313 unsigned int quot;
2314
2315 /*
2316 * Handle magic divisors for baud rates above baud_base on
2317 * SMSC SuperIO chips.
2318 */
2319 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2320 baud == (port->uartclk/4))
2321 quot = 0x8001;
2322 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2323 baud == (port->uartclk/8))
2324 quot = 0x8002;
2325 else
2326 quot = uart_get_divisor(port, baud);
2327
2328 return quot;
2329}
2330
2331void
2332serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2333 struct ktermios *old)
2334{
2335 struct uart_8250_port *up =
2336 container_of(port, struct uart_8250_port, port);
2337 unsigned char cval, fcr = 0;
2338 unsigned long flags;
2339 unsigned int baud, quot;
2340
2341 switch (termios->c_cflag & CSIZE) {
2342 case CS5:
2343 cval = UART_LCR_WLEN5;
2344 break;
2345 case CS6:
2346 cval = UART_LCR_WLEN6;
2347 break;
2348 case CS7:
2349 cval = UART_LCR_WLEN7;
2350 break;
2351 default:
2352 case CS8:
2353 cval = UART_LCR_WLEN8;
2354 break;
2355 }
2356
2357 if (termios->c_cflag & CSTOPB)
2358 cval |= UART_LCR_STOP;
2359 if (termios->c_cflag & PARENB)
2360 cval |= UART_LCR_PARITY;
2361 if (!(termios->c_cflag & PARODD))
2362 cval |= UART_LCR_EPAR;
2363#ifdef CMSPAR
2364 if (termios->c_cflag & CMSPAR)
2365 cval |= UART_LCR_SPAR;
2366#endif
2367
2368 /*
2369 * Ask the core to calculate the divisor for us.
2370 */
2371 baud = uart_get_baud_rate(port, termios, old,
2372 port->uartclk / 16 / 0xffff,
2373 port->uartclk / 16);
2374 quot = serial8250_get_divisor(port, baud);
2375
2376 /*
2377 * Oxford Semi 952 rev B workaround
2378 */
2379 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2380 quot++;
2381
2382 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2383 if (baud < 2400)
2384 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2385 else
2386 fcr = uart_config[up->port.type].fcr;
2387 }
2388
2389 /*
2390 * MCR-based auto flow control. When AFE is enabled, RTS will be
2391 * deasserted when the receive FIFO contains more characters than
2392 * the trigger, or the MCR RTS bit is cleared. In the case where
2393 * the remote UART is not using CTS auto flow control, we must
2394 * have sufficient FIFO entries for the latency of the remote
2395 * UART to respond. IOW, at least 32 bytes of FIFO.
2396 */
2397 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2398 up->mcr &= ~UART_MCR_AFE;
2399 if (termios->c_cflag & CRTSCTS)
2400 up->mcr |= UART_MCR_AFE;
2401 }
2402
2403 /*
2404 * Ok, we're now changing the port state. Do it with
2405 * interrupts disabled.
2406 */
2407 spin_lock_irqsave(&up->port.lock, flags);
2408
2409 /*
2410 * Update the per-port timeout.
2411 */
2412 uart_update_timeout(port, termios->c_cflag, baud);
2413
2414 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2415 if (termios->c_iflag & INPCK)
2416 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2417 if (termios->c_iflag & (BRKINT | PARMRK))
2418 up->port.read_status_mask |= UART_LSR_BI;
2419
2420 /*
2421 * Characteres to ignore
2422 */
2423 up->port.ignore_status_mask = 0;
2424 if (termios->c_iflag & IGNPAR)
2425 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2426 if (termios->c_iflag & IGNBRK) {
2427 up->port.ignore_status_mask |= UART_LSR_BI;
2428 /*
2429 * If we're ignoring parity and break indicators,
2430 * ignore overruns too (for real raw support).
2431 */
2432 if (termios->c_iflag & IGNPAR)
2433 up->port.ignore_status_mask |= UART_LSR_OE;
2434 }
2435
2436 /*
2437 * ignore all characters if CREAD is not set
2438 */
2439 if ((termios->c_cflag & CREAD) == 0)
2440 up->port.ignore_status_mask |= UART_LSR_DR;
2441
2442 /*
2443 * CTS flow control flag and modem status interrupts
2444 */
2445 up->ier &= ~UART_IER_MSI;
2446 if (!(up->bugs & UART_BUG_NOMSR) &&
2447 UART_ENABLE_MS(&up->port, termios->c_cflag))
2448 up->ier |= UART_IER_MSI;
2449 if (up->capabilities & UART_CAP_UUE)
2450 up->ier |= UART_IER_UUE;
2451 if (up->capabilities & UART_CAP_RTOIE)
2452 up->ier |= UART_IER_RTOIE;
2453
2454 serial_out(up, UART_IER, up->ier);
2455
2456 if (up->capabilities & UART_CAP_EFR) {
2457 unsigned char efr = 0;
2458 /*
2459 * TI16C752/Startech hardware flow control. FIXME:
2460 * - TI16C752 requires control thresholds to be set.
2461 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2462 */
2463 if (termios->c_cflag & CRTSCTS)
2464 efr |= UART_EFR_CTS;
2465
2466 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2467 serial_outp(up, UART_EFR, efr);
2468 }
2469
2470 if (up->capabilities & UART_CAP_HW_CTSRTS) {
2471 unsigned char mcr = serial_inp(up, UART_MCR);
2472 /*
2473 * TEGRA UART core support the auto control of the RTS and CTS
2474 * flow control.
2475 */
2476 if (termios->c_cflag & CRTSCTS)
2477 mcr |= UART_MCR_HW_CTS;
2478 else
2479 mcr &= ~UART_MCR_HW_CTS;
2480 serial_outp(up, UART_MCR, mcr);
2481 }
2482
2483#ifdef CONFIG_ARCH_OMAP
2484 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2485 if (cpu_is_omap1510() && is_omap_port(up)) {
2486 if (baud == 115200) {
2487 quot = 1;
2488 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2489 } else
2490 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2491 }
2492#endif
2493
2494 if (up->capabilities & UART_NATSEMI) {
2495 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2496 serial_outp(up, UART_LCR, 0xe0);
2497 } else {
2498 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2499 }
2500
2501 serial_dl_write(up, quot);
2502
2503 /*
2504 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2505 * is written without DLAB set, this mode will be disabled.
2506 */
2507 if (up->port.type == PORT_16750)
2508 serial_outp(up, UART_FCR, fcr);
2509
2510 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2511 up->lcr = cval; /* Save LCR */
2512 if (up->port.type != PORT_16750) {
2513 if (fcr & UART_FCR_ENABLE_FIFO) {
2514 /* emulated UARTs (Lucent Venus 167x) need two steps */
2515 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2516 }
2517 serial_outp(up, UART_FCR, fcr); /* set fcr */
2518 }
2519 serial8250_set_mctrl(&up->port, up->port.mctrl);
2520 spin_unlock_irqrestore(&up->port.lock, flags);
2521 /* Don't rewrite B0 */
2522 if (tty_termios_baud_rate(termios))
2523 tty_termios_encode_baud_rate(termios, baud, baud);
2524}
2525EXPORT_SYMBOL(serial8250_do_set_termios);
2526
2527static void
2528serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2529 struct ktermios *old)
2530{
2531 if (port->set_termios)
2532 port->set_termios(port, termios, old);
2533 else
2534 serial8250_do_set_termios(port, termios, old);
2535}
2536
2537static void
2538serial8250_set_ldisc(struct uart_port *port, int new)
2539{
2540 if (new == N_PPS) {
2541 port->flags |= UPF_HARDPPS_CD;
2542 serial8250_enable_ms(port);
2543 } else
2544 port->flags &= ~UPF_HARDPPS_CD;
2545}
2546
2547
2548void serial8250_do_pm(struct uart_port *port, unsigned int state,
2549 unsigned int oldstate)
2550{
2551 struct uart_8250_port *p =
2552 container_of(port, struct uart_8250_port, port);
2553
2554 serial8250_set_sleep(p, state != 0);
2555}
2556EXPORT_SYMBOL(serial8250_do_pm);
2557
2558static void
2559serial8250_pm(struct uart_port *port, unsigned int state,
2560 unsigned int oldstate)
2561{
2562 if (port->pm)
2563 port->pm(port, state, oldstate);
2564 else
2565 serial8250_do_pm(port, state, oldstate);
2566}
2567
2568static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2569{
2570 if (pt->port.iotype == UPIO_AU)
2571 return 0x1000;
2572#ifdef CONFIG_ARCH_OMAP
2573 if (is_omap_port(pt))
2574 return 0x16 << pt->port.regshift;
2575#endif
2576 return 8 << pt->port.regshift;
2577}
2578
2579/*
2580 * Resource handling.
2581 */
2582static int serial8250_request_std_resource(struct uart_8250_port *up)
2583{
2584 unsigned int size = serial8250_port_size(up);
2585 int ret = 0;
2586
2587 switch (up->port.iotype) {
2588 case UPIO_AU:
2589 case UPIO_TSI:
2590 case UPIO_MEM32:
2591 case UPIO_MEM:
2592 case UPIO_DWAPB:
2593 case UPIO_DWAPB32:
2594 if (!up->port.mapbase)
2595 break;
2596
2597 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2598 ret = -EBUSY;
2599 break;
2600 }
2601
2602 if (up->port.flags & UPF_IOREMAP) {
2603 up->port.membase = ioremap_nocache(up->port.mapbase,
2604 size);
2605 if (!up->port.membase) {
2606 release_mem_region(up->port.mapbase, size);
2607 ret = -ENOMEM;
2608 }
2609 }
2610 break;
2611
2612 case UPIO_HUB6:
2613 case UPIO_PORT:
2614 if (!request_region(up->port.iobase, size, "serial"))
2615 ret = -EBUSY;
2616 break;
2617 }
2618 return ret;
2619}
2620
2621static void serial8250_release_std_resource(struct uart_8250_port *up)
2622{
2623 unsigned int size = serial8250_port_size(up);
2624
2625 switch (up->port.iotype) {
2626 case UPIO_AU:
2627 case UPIO_TSI:
2628 case UPIO_MEM32:
2629 case UPIO_MEM:
2630 case UPIO_DWAPB:
2631 case UPIO_DWAPB32:
2632 if (!up->port.mapbase)
2633 break;
2634
2635 if (up->port.flags & UPF_IOREMAP) {
2636 iounmap(up->port.membase);
2637 up->port.membase = NULL;
2638 }
2639
2640 release_mem_region(up->port.mapbase, size);
2641 break;
2642
2643 case UPIO_HUB6:
2644 case UPIO_PORT:
2645 release_region(up->port.iobase, size);
2646 break;
2647 }
2648}
2649
2650static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2651{
2652 unsigned long start = UART_RSA_BASE << up->port.regshift;
2653 unsigned int size = 8 << up->port.regshift;
2654 int ret = -EINVAL;
2655
2656 switch (up->port.iotype) {
2657 case UPIO_HUB6:
2658 case UPIO_PORT:
2659 start += up->port.iobase;
2660 if (request_region(start, size, "serial-rsa"))
2661 ret = 0;
2662 else
2663 ret = -EBUSY;
2664 break;
2665 }
2666
2667 return ret;
2668}
2669
2670static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2671{
2672 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2673 unsigned int size = 8 << up->port.regshift;
2674
2675 switch (up->port.iotype) {
2676 case UPIO_HUB6:
2677 case UPIO_PORT:
2678 release_region(up->port.iobase + offset, size);
2679 break;
2680 }
2681}
2682
2683static void serial8250_release_port(struct uart_port *port)
2684{
2685 struct uart_8250_port *up =
2686 container_of(port, struct uart_8250_port, port);
2687
2688 serial8250_release_std_resource(up);
2689 if (up->port.type == PORT_RSA)
2690 serial8250_release_rsa_resource(up);
2691}
2692
2693static int serial8250_request_port(struct uart_port *port)
2694{
2695 struct uart_8250_port *up =
2696 container_of(port, struct uart_8250_port, port);
2697 int ret = 0;
2698
2699 ret = serial8250_request_std_resource(up);
2700 if (ret == 0 && up->port.type == PORT_RSA) {
2701 ret = serial8250_request_rsa_resource(up);
2702 if (ret < 0)
2703 serial8250_release_std_resource(up);
2704 }
2705
2706 return ret;
2707}
2708
2709static void serial8250_config_port(struct uart_port *port, int flags)
2710{
2711 struct uart_8250_port *up =
2712 container_of(port, struct uart_8250_port, port);
2713 int probeflags = PROBE_ANY;
2714 int ret;
2715
2716 /*
2717 * Find the region that we can probe for. This in turn
2718 * tells us whether we can probe for the type of port.
2719 */
2720 ret = serial8250_request_std_resource(up);
2721 if (ret < 0)
2722 return;
2723
2724 ret = serial8250_request_rsa_resource(up);
2725 if (ret < 0)
2726 probeflags &= ~PROBE_RSA;
2727
2728 if (up->port.iotype != up->cur_iotype)
2729 set_io_from_upio(port);
2730
2731 if (flags & UART_CONFIG_TYPE)
2732 autoconfig(up, probeflags);
2733
2734 /* if access method is AU, it is a 16550 with a quirk */
2735 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2736 up->bugs |= UART_BUG_NOMSR;
2737
2738 if (up->port.type == PORT_TEGRA)
2739 up->bugs |= UART_BUG_NOMSR;
2740
2741 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2742 autoconfig_irq(up);
2743
2744 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2745 serial8250_release_rsa_resource(up);
2746 if (up->port.type == PORT_UNKNOWN)
2747 serial8250_release_std_resource(up);
2748}
2749
2750static int
2751serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2752{
2753 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2754 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2755 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2756 ser->type == PORT_STARTECH)
2757 return -EINVAL;
2758 return 0;
2759}
2760
2761static const char *
2762serial8250_type(struct uart_port *port)
2763{
2764 int type = port->type;
2765
2766 if (type >= ARRAY_SIZE(uart_config))
2767 type = 0;
2768 return uart_config[type].name;
2769}
2770
2771static struct uart_ops serial8250_pops = {
2772 .tx_empty = serial8250_tx_empty,
2773 .set_mctrl = serial8250_set_mctrl,
2774 .get_mctrl = serial8250_get_mctrl,
2775 .stop_tx = serial8250_stop_tx,
2776 .start_tx = serial8250_start_tx,
2777 .stop_rx = serial8250_stop_rx,
2778 .enable_ms = serial8250_enable_ms,
2779 .break_ctl = serial8250_break_ctl,
2780 .startup = serial8250_startup,
2781 .shutdown = serial8250_shutdown,
2782 .set_termios = serial8250_set_termios,
2783 .set_ldisc = serial8250_set_ldisc,
2784 .pm = serial8250_pm,
2785 .type = serial8250_type,
2786 .release_port = serial8250_release_port,
2787 .request_port = serial8250_request_port,
2788 .config_port = serial8250_config_port,
2789 .verify_port = serial8250_verify_port,
2790#ifdef CONFIG_CONSOLE_POLL
2791 .poll_get_char = serial8250_get_poll_char,
2792 .poll_put_char = serial8250_put_poll_char,
2793#endif
2794};
2795
2796static struct uart_8250_port serial8250_ports[UART_NR];
2797
2798static void (*serial8250_isa_config)(int port, struct uart_port *up,
2799 unsigned short *capabilities);
2800
2801void serial8250_set_isa_configurator(
2802 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2803{
2804 serial8250_isa_config = v;
2805}
2806EXPORT_SYMBOL(serial8250_set_isa_configurator);
2807
2808static void __init serial8250_isa_init_ports(void)
2809{
2810 struct uart_8250_port *up;
2811 static int first = 1;
2812 int i, irqflag = 0;
2813
2814 if (!first)
2815 return;
2816 first = 0;
2817
2818 for (i = 0; i < nr_uarts; i++) {
2819 struct uart_8250_port *up = &serial8250_ports[i];
2820
2821 up->port.line = i;
2822 spin_lock_init(&up->port.lock);
2823
2824 init_timer(&up->timer);
2825 up->timer.function = serial8250_timeout;
2826
2827 /*
2828 * ALPHA_KLUDGE_MCR needs to be killed.
2829 */
2830 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2831 up->mcr_force = ALPHA_KLUDGE_MCR;
2832
2833 up->port.ops = &serial8250_pops;
2834 }
2835
2836 if (share_irqs)
2837 irqflag = IRQF_SHARED;
2838
2839 for (i = 0, up = serial8250_ports;
2840 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2841 i++, up++) {
2842 up->port.iobase = old_serial_port[i].port;
2843 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2844 up->port.irqflags = old_serial_port[i].irqflags;
2845 up->port.uartclk = old_serial_port[i].baud_base * 16;
2846 up->port.flags = old_serial_port[i].flags;
2847 up->port.hub6 = old_serial_port[i].hub6;
2848 up->port.membase = old_serial_port[i].iomem_base;
2849 up->port.iotype = old_serial_port[i].io_type;
2850 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2851 set_io_from_upio(&up->port);
2852 up->port.irqflags |= irqflag;
2853 if (serial8250_isa_config != NULL)
2854 serial8250_isa_config(i, &up->port, &up->capabilities);
2855
2856 }
2857}
2858
2859static void
2860serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2861{
2862 up->port.type = type;
2863 up->port.fifosize = uart_config[type].fifo_size;
2864 up->capabilities = uart_config[type].flags;
2865 up->tx_loadsz = uart_config[type].tx_loadsz;
2866}
2867
2868static void __init
2869serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2870{
2871 int i;
2872
2873 for (i = 0; i < nr_uarts; i++) {
2874 struct uart_8250_port *up = &serial8250_ports[i];
2875 up->cur_iotype = 0xFF;
2876 }
2877
2878 serial8250_isa_init_ports();
2879
2880 for (i = 0; i < nr_uarts; i++) {
2881 struct uart_8250_port *up = &serial8250_ports[i];
2882
2883 up->port.dev = dev;
2884
2885 if (up->port.flags & UPF_FIXED_TYPE)
2886 serial8250_init_fixed_type_port(up, up->port.type);
2887
2888 uart_add_one_port(drv, &up->port);
2889 }
2890}
2891
2892#ifdef CONFIG_SERIAL_8250_CONSOLE
2893
2894static void serial8250_console_putchar(struct uart_port *port, int ch)
2895{
2896 struct uart_8250_port *up =
2897 container_of(port, struct uart_8250_port, port);
2898
2899 wait_for_xmitr(up, UART_LSR_THRE);
2900 serial_out(up, UART_TX, ch);
2901}
2902
2903/*
2904 * Print a string to the serial port trying not to disturb
2905 * any possible real use of the port...
2906 *
2907 * The console_lock must be held when we get here.
2908 */
2909static void
2910serial8250_console_write(struct console *co, const char *s, unsigned int count)
2911{
2912 struct uart_8250_port *up = &serial8250_ports[co->index];
2913 unsigned long flags;
2914 unsigned int ier;
2915 int locked = 1;
2916
2917 touch_nmi_watchdog();
2918
2919 local_irq_save(flags);
2920 if (up->port.sysrq) {
2921 /* serial8250_handle_port() already took the lock */
2922 locked = 0;
2923 } else if (oops_in_progress) {
2924 locked = spin_trylock(&up->port.lock);
2925 } else
2926 spin_lock(&up->port.lock);
2927
2928 /*
2929 * First save the IER then disable the interrupts
2930 */
2931 ier = serial_in(up, UART_IER);
2932
2933 if (up->capabilities & UART_CAP_UUE)
2934 serial_out(up, UART_IER, UART_IER_UUE);
2935 else
2936 serial_out(up, UART_IER, 0);
2937
2938 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2939
2940 /*
2941 * Finally, wait for transmitter to become empty
2942 * and restore the IER
2943 */
2944 wait_for_xmitr(up, BOTH_EMPTY);
2945 serial_out(up, UART_IER, ier);
2946
2947 /*
2948 * The receive handling will happen properly because the
2949 * receive ready bit will still be set; it is not cleared
2950 * on read. However, modem control will not, we must
2951 * call it if we have saved something in the saved flags
2952 * while processing with interrupts off.
2953 */
2954 if (up->msr_saved_flags)
2955 check_modem_status(up);
2956
2957 if (locked)
2958 spin_unlock(&up->port.lock);
2959 local_irq_restore(flags);
2960}
2961
2962static int __init serial8250_console_setup(struct console *co, char *options)
2963{
2964 struct uart_port *port;
2965 int baud = 9600;
2966 int bits = 8;
2967 int parity = 'n';
2968 int flow = 'n';
2969
2970 /*
2971 * Check whether an invalid uart number has been specified, and
2972 * if so, search for the first available port that does have
2973 * console support.
2974 */
2975 if (co->index >= nr_uarts)
2976 co->index = 0;
2977 port = &serial8250_ports[co->index].port;
2978 if (!port->iobase && !port->membase)
2979 return -ENODEV;
2980
2981 if (options)
2982 uart_parse_options(options, &baud, &parity, &bits, &flow);
2983
2984 return uart_set_options(port, co, baud, parity, bits, flow);
2985}
2986
2987static int serial8250_console_early_setup(void)
2988{
2989 return serial8250_find_port_for_earlycon();
2990}
2991
2992static struct console serial8250_console = {
2993 .name = "ttyS",
2994 .write = serial8250_console_write,
2995 .device = uart_console_device,
2996 .setup = serial8250_console_setup,
2997 .early_setup = serial8250_console_early_setup,
2998 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2999 .index = -1,
3000 .data = &serial8250_reg,
3001};
3002
3003static int __init serial8250_console_init(void)
3004{
3005 if (nr_uarts > UART_NR)
3006 nr_uarts = UART_NR;
3007
3008 serial8250_isa_init_ports();
3009 register_console(&serial8250_console);
3010 return 0;
3011}
3012console_initcall(serial8250_console_init);
3013
3014int serial8250_find_port(struct uart_port *p)
3015{
3016 int line;
3017 struct uart_port *port;
3018
3019 for (line = 0; line < nr_uarts; line++) {
3020 port = &serial8250_ports[line].port;
3021 if (uart_match_port(p, port))
3022 return line;
3023 }
3024 return -ENODEV;
3025}
3026
3027#define SERIAL8250_CONSOLE &serial8250_console
3028#else
3029#define SERIAL8250_CONSOLE NULL
3030#endif
3031
3032static struct uart_driver serial8250_reg = {
3033 .owner = THIS_MODULE,
3034 .driver_name = "serial",
3035 .dev_name = "ttyS",
3036 .major = TTY_MAJOR,
3037 .minor = 64,
3038 .cons = SERIAL8250_CONSOLE,
3039};
3040
3041/*
3042 * early_serial_setup - early registration for 8250 ports
3043 *
3044 * Setup an 8250 port structure prior to console initialisation. Use
3045 * after console initialisation will cause undefined behaviour.
3046 */
3047int __init early_serial_setup(struct uart_port *port)
3048{
3049 struct uart_port *p;
3050
3051 if (port->line >= ARRAY_SIZE(serial8250_ports))
3052 return -ENODEV;
3053
3054 serial8250_isa_init_ports();
3055 p = &serial8250_ports[port->line].port;
3056 p->iobase = port->iobase;
3057 p->membase = port->membase;
3058 p->irq = port->irq;
3059 p->irqflags = port->irqflags;
3060 p->uartclk = port->uartclk;
3061 p->fifosize = port->fifosize;
3062 p->regshift = port->regshift;
3063 p->iotype = port->iotype;
3064 p->flags = port->flags;
3065 p->mapbase = port->mapbase;
3066 p->private_data = port->private_data;
3067 p->type = port->type;
3068 p->line = port->line;
3069
3070 set_io_from_upio(p);
3071 if (port->serial_in)
3072 p->serial_in = port->serial_in;
3073 if (port->serial_out)
3074 p->serial_out = port->serial_out;
3075
3076 return 0;
3077}
3078
3079/**
3080 * serial8250_suspend_port - suspend one serial port
3081 * @line: serial line number
3082 *
3083 * Suspend one serial port.
3084 */
3085void serial8250_suspend_port(int line)
3086{
3087 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3088}
3089
3090/**
3091 * serial8250_resume_port - resume one serial port
3092 * @line: serial line number
3093 *
3094 * Resume one serial port.
3095 */
3096void serial8250_resume_port(int line)
3097{
3098 struct uart_8250_port *up = &serial8250_ports[line];
3099
3100 if (up->capabilities & UART_NATSEMI) {
3101 /* Ensure it's still in high speed mode */
3102 serial_outp(up, UART_LCR, 0xE0);
3103
3104 ns16550a_goto_highspeed(up);
3105
3106 serial_outp(up, UART_LCR, 0);
3107 up->port.uartclk = 921600*16;
3108 }
3109 uart_resume_port(&serial8250_reg, &up->port);
3110}
3111
3112/*
3113 * Register a set of serial devices attached to a platform device. The
3114 * list is terminated with a zero flags entry, which means we expect
3115 * all entries to have at least UPF_BOOT_AUTOCONF set.
3116 */
3117static int __devinit serial8250_probe(struct platform_device *dev)
3118{
3119 struct plat_serial8250_port *p = dev->dev.platform_data;
3120 struct uart_port port;
3121 int ret, i, irqflag = 0;
3122
3123 memset(&port, 0, sizeof(struct uart_port));
3124
3125 if (share_irqs)
3126 irqflag = IRQF_SHARED;
3127
3128 for (i = 0; p && p->flags != 0; p++, i++) {
3129 port.iobase = p->iobase;
3130 port.membase = p->membase;
3131 port.irq = p->irq;
3132 port.irqflags = p->irqflags;
3133 port.uartclk = p->uartclk;
3134 port.regshift = p->regshift;
3135 port.iotype = p->iotype;
3136 port.flags = p->flags;
3137 port.mapbase = p->mapbase;
3138 port.hub6 = p->hub6;
3139 port.private_data = p->private_data;
3140 port.type = p->type;
3141 port.serial_in = p->serial_in;
3142 port.serial_out = p->serial_out;
3143 port.set_termios = p->set_termios;
3144 port.pm = p->pm;
3145 port.dev = &dev->dev;
3146 port.irqflags |= irqflag;
3147 ret = serial8250_register_port(&port);
3148 if (ret < 0) {
3149 dev_err(&dev->dev, "unable to register port at index %d "
3150 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3151 p->iobase, (unsigned long long)p->mapbase,
3152 p->irq, ret);
3153 }
3154 }
3155 return 0;
3156}
3157
3158/*
3159 * Remove serial ports registered against a platform device.
3160 */
3161static int __devexit serial8250_remove(struct platform_device *dev)
3162{
3163 int i;
3164
3165 for (i = 0; i < nr_uarts; i++) {
3166 struct uart_8250_port *up = &serial8250_ports[i];
3167
3168 if (up->port.dev == &dev->dev)
3169 serial8250_unregister_port(i);
3170 }
3171 return 0;
3172}
3173
3174static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3175{
3176 int i;
3177
3178 for (i = 0; i < UART_NR; i++) {
3179 struct uart_8250_port *up = &serial8250_ports[i];
3180
3181 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3182 uart_suspend_port(&serial8250_reg, &up->port);
3183 }
3184
3185 return 0;
3186}
3187
3188static int serial8250_resume(struct platform_device *dev)
3189{
3190 int i;
3191
3192 for (i = 0; i < UART_NR; i++) {
3193 struct uart_8250_port *up = &serial8250_ports[i];
3194
3195 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3196 serial8250_resume_port(i);
3197 }
3198
3199 return 0;
3200}
3201
3202static struct platform_driver serial8250_isa_driver = {
3203 .probe = serial8250_probe,
3204 .remove = __devexit_p(serial8250_remove),
3205 .suspend = serial8250_suspend,
3206 .resume = serial8250_resume,
3207 .driver = {
3208 .name = "serial8250",
3209 .owner = THIS_MODULE,
3210 },
3211};
3212
3213/*
3214 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3215 * in the table in include/asm/serial.h
3216 */
3217static struct platform_device *serial8250_isa_devs;
3218
3219/*
3220 * serial8250_register_port and serial8250_unregister_port allows for
3221 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3222 * modems and PCI multiport cards.
3223 */
3224static DEFINE_MUTEX(serial_mutex);
3225
3226static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3227{
3228 int i;
3229
3230 /*
3231 * First, find a port entry which matches.
3232 */
3233 for (i = 0; i < nr_uarts; i++)
3234 if (uart_match_port(&serial8250_ports[i].port, port))
3235 return &serial8250_ports[i];
3236
3237 /*
3238 * We didn't find a matching entry, so look for the first
3239 * free entry. We look for one which hasn't been previously
3240 * used (indicated by zero iobase).
3241 */
3242 for (i = 0; i < nr_uarts; i++)
3243 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3244 serial8250_ports[i].port.iobase == 0)
3245 return &serial8250_ports[i];
3246
3247 /*
3248 * That also failed. Last resort is to find any entry which
3249 * doesn't have a real port associated with it.
3250 */
3251 for (i = 0; i < nr_uarts; i++)
3252 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3253 return &serial8250_ports[i];
3254
3255 return NULL;
3256}
3257
3258/**
3259 * serial8250_register_port - register a serial port
3260 * @port: serial port template
3261 *
3262 * Configure the serial port specified by the request. If the
3263 * port exists and is in use, it is hung up and unregistered
3264 * first.
3265 *
3266 * The port is then probed and if necessary the IRQ is autodetected
3267 * If this fails an error is returned.
3268 *
3269 * On success the port is ready to use and the line number is returned.
3270 */
3271int serial8250_register_port(struct uart_port *port)
3272{
3273 struct uart_8250_port *uart;
3274 int ret = -ENOSPC;
3275
3276 if (port->uartclk == 0)
3277 return -EINVAL;
3278
3279 mutex_lock(&serial_mutex);
3280
3281 uart = serial8250_find_match_or_unused(port);
3282 if (uart) {
3283 uart_remove_one_port(&serial8250_reg, &uart->port);
3284
3285 uart->port.iobase = port->iobase;
3286 uart->port.membase = port->membase;
3287 uart->port.irq = port->irq;
3288 uart->port.irqflags = port->irqflags;
3289 uart->port.uartclk = port->uartclk;
3290 uart->port.fifosize = port->fifosize;
3291 uart->port.regshift = port->regshift;
3292 uart->port.iotype = port->iotype;
3293 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3294 uart->port.mapbase = port->mapbase;
3295 uart->port.private_data = port->private_data;
3296 if (port->dev)
3297 uart->port.dev = port->dev;
3298
3299 if (port->flags & UPF_FIXED_TYPE)
3300 serial8250_init_fixed_type_port(uart, port->type);
3301
3302 set_io_from_upio(&uart->port);
3303 /* Possibly override default I/O functions. */
3304 if (port->serial_in)
3305 uart->port.serial_in = port->serial_in;
3306 if (port->serial_out)
3307 uart->port.serial_out = port->serial_out;
3308 /* Possibly override set_termios call */
3309 if (port->set_termios)
3310 uart->port.set_termios = port->set_termios;
3311 if (port->pm)
3312 uart->port.pm = port->pm;
3313
3314 if (serial8250_isa_config != NULL)
3315 serial8250_isa_config(0, &uart->port,
3316 &uart->capabilities);
3317
3318 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3319 if (ret == 0)
3320 ret = uart->port.line;
3321 }
3322 mutex_unlock(&serial_mutex);
3323
3324 return ret;
3325}
3326EXPORT_SYMBOL(serial8250_register_port);
3327
3328/**
3329 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3330 * @line: serial line number
3331 *
3332 * Remove one serial port. This may not be called from interrupt
3333 * context. We hand the port back to the our control.
3334 */
3335void serial8250_unregister_port(int line)
3336{
3337 struct uart_8250_port *uart = &serial8250_ports[line];
3338
3339 mutex_lock(&serial_mutex);
3340 uart_remove_one_port(&serial8250_reg, &uart->port);
3341 if (serial8250_isa_devs) {
3342 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3343 uart->port.type = PORT_UNKNOWN;
3344 uart->port.dev = &serial8250_isa_devs->dev;
3345 uart->capabilities = uart_config[uart->port.type].flags;
3346 uart_add_one_port(&serial8250_reg, &uart->port);
3347 } else {
3348 uart->port.dev = NULL;
3349 }
3350 mutex_unlock(&serial_mutex);
3351}
3352EXPORT_SYMBOL(serial8250_unregister_port);
3353
3354static int __init serial8250_init(void)
3355{
3356 int ret;
3357
3358 if (nr_uarts > UART_NR)
3359 nr_uarts = UART_NR;
3360
3361 printk(KERN_INFO "Serial: 8250/16550 driver, "
3362 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3363 share_irqs ? "en" : "dis");
3364
3365#ifdef CONFIG_SPARC
3366 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3367#else
3368 serial8250_reg.nr = UART_NR;
3369 ret = uart_register_driver(&serial8250_reg);
3370#endif
3371 if (ret)
3372 goto out;
3373
3374 serial8250_isa_devs = platform_device_alloc("serial8250",
3375 PLAT8250_DEV_LEGACY);
3376 if (!serial8250_isa_devs) {
3377 ret = -ENOMEM;
3378 goto unreg_uart_drv;
3379 }
3380
3381 ret = platform_device_add(serial8250_isa_devs);
3382 if (ret)
3383 goto put_dev;
3384
3385 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3386
3387 ret = platform_driver_register(&serial8250_isa_driver);
3388 if (ret == 0)
3389 goto out;
3390
3391 platform_device_del(serial8250_isa_devs);
3392put_dev:
3393 platform_device_put(serial8250_isa_devs);
3394unreg_uart_drv:
3395#ifdef CONFIG_SPARC
3396 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3397#else
3398 uart_unregister_driver(&serial8250_reg);
3399#endif
3400out:
3401 return ret;
3402}
3403
3404#ifdef MODULE
3405static void __exit serial8250_exit(void)
3406{
3407 struct platform_device *isa_dev = serial8250_isa_devs;
3408
3409 /*
3410 * This tells serial8250_unregister_port() not to re-register
3411 * the ports (thereby making serial8250_isa_driver permanently
3412 * in use.)
3413 */
3414 serial8250_isa_devs = NULL;
3415
3416 platform_driver_unregister(&serial8250_isa_driver);
3417 platform_device_unregister(isa_dev);
3418
3419#ifdef CONFIG_SPARC
3420 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3421#else
3422 uart_unregister_driver(&serial8250_reg);
3423#endif
3424}
3425
3426module_init(serial8250_init);
3427module_exit(serial8250_exit);
3428#else
3429postcore_initcall(serial8250_init);
3430#endif
3431
3432EXPORT_SYMBOL(serial8250_suspend_port);
3433EXPORT_SYMBOL(serial8250_resume_port);
3434
3435MODULE_LICENSE("GPL");
3436MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3437
3438module_param(share_irqs, uint, 0644);
3439MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3440 " (unsafe)");
3441
3442module_param(nr_uarts, uint, 0644);
3443MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3444
3445module_param(skip_txen_test, uint, 0644);
3446MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3447
3448#ifdef CONFIG_SERIAL_8250_RSA
3449module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3450MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3451#endif
3452MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 04:35:44 -0400