aboutsummaryrefslogtreecommitdiffstats
path: root/arch/tile/include/asm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/tile/include/asm')
-rw-r--r--arch/tile/include/asm/auxvec.h20
-rw-r--r--arch/tile/include/asm/bitsperlong.h26
-rw-r--r--arch/tile/include/asm/byteorder.h1
-rw-r--r--arch/tile/include/asm/memprof.h33
-rw-r--r--arch/tile/include/asm/mman.h41
-rw-r--r--arch/tile/include/asm/opcode-tile.h30
-rw-r--r--arch/tile/include/asm/opcode-tile_32.h1513
-rw-r--r--arch/tile/include/asm/opcode-tile_64.h1248
-rw-r--r--arch/tile/include/asm/opcode_constants.h26
-rw-r--r--arch/tile/include/asm/opcode_constants_32.h480
-rw-r--r--arch/tile/include/asm/opcode_constants_64.h609
-rw-r--r--arch/tile/include/asm/sigcontext.h35
-rw-r--r--arch/tile/include/asm/siginfo.h34
-rw-r--r--arch/tile/include/asm/stat.h4
-rw-r--r--arch/tile/include/asm/swab.h23
-rw-r--r--arch/tile/include/asm/system.h261
16 files changed, 4384 insertions, 0 deletions
diff --git a/arch/tile/include/asm/auxvec.h b/arch/tile/include/asm/auxvec.h
new file mode 100644
index 00000000000..1d393edb064
--- /dev/null
+++ b/arch/tile/include/asm/auxvec.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_AUXVEC_H
16#define _ASM_TILE_AUXVEC_H
17
18/* No extensions to auxvec */
19
20#endif /* _ASM_TILE_AUXVEC_H */
diff --git a/arch/tile/include/asm/bitsperlong.h b/arch/tile/include/asm/bitsperlong.h
new file mode 100644
index 00000000000..58c771f2af2
--- /dev/null
+++ b/arch/tile/include/asm/bitsperlong.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_BITSPERLONG_H
16#define _ASM_TILE_BITSPERLONG_H
17
18#ifdef __LP64__
19# define __BITS_PER_LONG 64
20#else
21# define __BITS_PER_LONG 32
22#endif
23
24#include <asm-generic/bitsperlong.h>
25
26#endif /* _ASM_TILE_BITSPERLONG_H */
diff --git a/arch/tile/include/asm/byteorder.h b/arch/tile/include/asm/byteorder.h
new file mode 100644
index 00000000000..9558416d578
--- /dev/null
+++ b/arch/tile/include/asm/byteorder.h
@@ -0,0 +1 @@
#include <linux/byteorder/little_endian.h>
diff --git a/arch/tile/include/asm/memprof.h b/arch/tile/include/asm/memprof.h
new file mode 100644
index 00000000000..359949be28c
--- /dev/null
+++ b/arch/tile/include/asm/memprof.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * The hypervisor's memory controller profiling infrastructure allows
15 * the programmer to find out what fraction of the available memory
16 * bandwidth is being consumed at each memory controller. The
17 * profiler provides start, stop, and clear operations to allows
18 * profiling over a specific time window, as well as an interface for
19 * reading the most recent profile values.
20 *
21 * This header declares IOCTL codes necessary to control memprof.
22 */
23#ifndef _ASM_TILE_MEMPROF_H
24#define _ASM_TILE_MEMPROF_H
25
26#include <linux/ioctl.h>
27
28#define MEMPROF_IOCTL_TYPE 0xB4
29#define MEMPROF_IOCTL_START _IO(MEMPROF_IOCTL_TYPE, 0)
30#define MEMPROF_IOCTL_STOP _IO(MEMPROF_IOCTL_TYPE, 1)
31#define MEMPROF_IOCTL_CLEAR _IO(MEMPROF_IOCTL_TYPE, 2)
32
33#endif /* _ASM_TILE_MEMPROF_H */
diff --git a/arch/tile/include/asm/mman.h b/arch/tile/include/asm/mman.h
new file mode 100644
index 00000000000..81b8fc348d6
--- /dev/null
+++ b/arch/tile/include/asm/mman.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_MMAN_H
16#define _ASM_TILE_MMAN_H
17
18#include <asm-generic/mman-common.h>
19#include <arch/chip.h>
20
21/* Standard Linux flags */
22
23#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x0080 /* do not block on IO */
25#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
26#define MAP_STACK MAP_GROWSDOWN /* provide convenience alias */
27#define MAP_LOCKED 0x0200 /* pages are locked */
28#define MAP_NORESERVE 0x0400 /* don't check for reservations */
29#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
30#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
31#define MAP_HUGETLB 0x4000 /* create a huge page mapping */
32
33
34/*
35 * Flags for mlockall
36 */
37#define MCL_CURRENT 1 /* lock all current mappings */
38#define MCL_FUTURE 2 /* lock all future mappings */
39
40
41#endif /* _ASM_TILE_MMAN_H */
diff --git a/arch/tile/include/asm/opcode-tile.h b/arch/tile/include/asm/opcode-tile.h
new file mode 100644
index 00000000000..ba38959137d
--- /dev/null
+++ b/arch/tile/include/asm/opcode-tile.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_OPCODE_TILE_H
16#define _ASM_TILE_OPCODE_TILE_H
17
18#include <arch/chip.h>
19
20#if CHIP_WORD_SIZE() == 64
21#include <asm/opcode-tile_64.h>
22#else
23#include <asm/opcode-tile_32.h>
24#endif
25
26/* These definitions are not correct for TILE64, so just avoid them. */
27#undef TILE_ELF_MACHINE_CODE
28#undef TILE_ELF_NAME
29
30#endif /* _ASM_TILE_OPCODE_TILE_H */
diff --git a/arch/tile/include/asm/opcode-tile_32.h b/arch/tile/include/asm/opcode-tile_32.h
new file mode 100644
index 00000000000..03df7b1e77b
--- /dev/null
+++ b/arch/tile/include/asm/opcode-tile_32.h
@@ -0,0 +1,1513 @@
1/* tile.h -- Header file for TILE opcode table
2 Copyright (C) 2005 Free Software Foundation, Inc.
3 Contributed by Tilera Corp. */
4
5#ifndef opcode_tile_h
6#define opcode_tile_h
7
8typedef unsigned long long tile_bundle_bits;
9
10
11enum
12{
13 TILE_MAX_OPERANDS = 5 /* mm */
14};
15
16typedef enum
17{
18 TILE_OPC_BPT,
19 TILE_OPC_INFO,
20 TILE_OPC_INFOL,
21 TILE_OPC_J,
22 TILE_OPC_JAL,
23 TILE_OPC_MOVE,
24 TILE_OPC_MOVE_SN,
25 TILE_OPC_MOVEI,
26 TILE_OPC_MOVEI_SN,
27 TILE_OPC_MOVELI,
28 TILE_OPC_MOVELI_SN,
29 TILE_OPC_MOVELIS,
30 TILE_OPC_PREFETCH,
31 TILE_OPC_RAISE,
32 TILE_OPC_ADD,
33 TILE_OPC_ADD_SN,
34 TILE_OPC_ADDB,
35 TILE_OPC_ADDB_SN,
36 TILE_OPC_ADDBS_U,
37 TILE_OPC_ADDBS_U_SN,
38 TILE_OPC_ADDH,
39 TILE_OPC_ADDH_SN,
40 TILE_OPC_ADDHS,
41 TILE_OPC_ADDHS_SN,
42 TILE_OPC_ADDI,
43 TILE_OPC_ADDI_SN,
44 TILE_OPC_ADDIB,
45 TILE_OPC_ADDIB_SN,
46 TILE_OPC_ADDIH,
47 TILE_OPC_ADDIH_SN,
48 TILE_OPC_ADDLI,
49 TILE_OPC_ADDLI_SN,
50 TILE_OPC_ADDLIS,
51 TILE_OPC_ADDS,
52 TILE_OPC_ADDS_SN,
53 TILE_OPC_ADIFFB_U,
54 TILE_OPC_ADIFFB_U_SN,
55 TILE_OPC_ADIFFH,
56 TILE_OPC_ADIFFH_SN,
57 TILE_OPC_AND,
58 TILE_OPC_AND_SN,
59 TILE_OPC_ANDI,
60 TILE_OPC_ANDI_SN,
61 TILE_OPC_AULI,
62 TILE_OPC_AVGB_U,
63 TILE_OPC_AVGB_U_SN,
64 TILE_OPC_AVGH,
65 TILE_OPC_AVGH_SN,
66 TILE_OPC_BBNS,
67 TILE_OPC_BBNS_SN,
68 TILE_OPC_BBNST,
69 TILE_OPC_BBNST_SN,
70 TILE_OPC_BBS,
71 TILE_OPC_BBS_SN,
72 TILE_OPC_BBST,
73 TILE_OPC_BBST_SN,
74 TILE_OPC_BGEZ,
75 TILE_OPC_BGEZ_SN,
76 TILE_OPC_BGEZT,
77 TILE_OPC_BGEZT_SN,
78 TILE_OPC_BGZ,
79 TILE_OPC_BGZ_SN,
80 TILE_OPC_BGZT,
81 TILE_OPC_BGZT_SN,
82 TILE_OPC_BITX,
83 TILE_OPC_BITX_SN,
84 TILE_OPC_BLEZ,
85 TILE_OPC_BLEZ_SN,
86 TILE_OPC_BLEZT,
87 TILE_OPC_BLEZT_SN,
88 TILE_OPC_BLZ,
89 TILE_OPC_BLZ_SN,
90 TILE_OPC_BLZT,
91 TILE_OPC_BLZT_SN,
92 TILE_OPC_BNZ,
93 TILE_OPC_BNZ_SN,
94 TILE_OPC_BNZT,
95 TILE_OPC_BNZT_SN,
96 TILE_OPC_BYTEX,
97 TILE_OPC_BYTEX_SN,
98 TILE_OPC_BZ,
99 TILE_OPC_BZ_SN,
100 TILE_OPC_BZT,
101 TILE_OPC_BZT_SN,
102 TILE_OPC_CLZ,
103 TILE_OPC_CLZ_SN,
104 TILE_OPC_CRC32_32,
105 TILE_OPC_CRC32_32_SN,
106 TILE_OPC_CRC32_8,
107 TILE_OPC_CRC32_8_SN,
108 TILE_OPC_CTZ,
109 TILE_OPC_CTZ_SN,
110 TILE_OPC_DRAIN,
111 TILE_OPC_DTLBPR,
112 TILE_OPC_DWORD_ALIGN,
113 TILE_OPC_DWORD_ALIGN_SN,
114 TILE_OPC_FINV,
115 TILE_OPC_FLUSH,
116 TILE_OPC_FNOP,
117 TILE_OPC_ICOH,
118 TILE_OPC_ILL,
119 TILE_OPC_INTHB,
120 TILE_OPC_INTHB_SN,
121 TILE_OPC_INTHH,
122 TILE_OPC_INTHH_SN,
123 TILE_OPC_INTLB,
124 TILE_OPC_INTLB_SN,
125 TILE_OPC_INTLH,
126 TILE_OPC_INTLH_SN,
127 TILE_OPC_INV,
128 TILE_OPC_IRET,
129 TILE_OPC_JALB,
130 TILE_OPC_JALF,
131 TILE_OPC_JALR,
132 TILE_OPC_JALRP,
133 TILE_OPC_JB,
134 TILE_OPC_JF,
135 TILE_OPC_JR,
136 TILE_OPC_JRP,
137 TILE_OPC_LB,
138 TILE_OPC_LB_SN,
139 TILE_OPC_LB_U,
140 TILE_OPC_LB_U_SN,
141 TILE_OPC_LBADD,
142 TILE_OPC_LBADD_SN,
143 TILE_OPC_LBADD_U,
144 TILE_OPC_LBADD_U_SN,
145 TILE_OPC_LH,
146 TILE_OPC_LH_SN,
147 TILE_OPC_LH_U,
148 TILE_OPC_LH_U_SN,
149 TILE_OPC_LHADD,
150 TILE_OPC_LHADD_SN,
151 TILE_OPC_LHADD_U,
152 TILE_OPC_LHADD_U_SN,
153 TILE_OPC_LNK,
154 TILE_OPC_LNK_SN,
155 TILE_OPC_LW,
156 TILE_OPC_LW_SN,
157 TILE_OPC_LW_NA,
158 TILE_OPC_LW_NA_SN,
159 TILE_OPC_LWADD,
160 TILE_OPC_LWADD_SN,
161 TILE_OPC_LWADD_NA,
162 TILE_OPC_LWADD_NA_SN,
163 TILE_OPC_MAXB_U,
164 TILE_OPC_MAXB_U_SN,
165 TILE_OPC_MAXH,
166 TILE_OPC_MAXH_SN,
167 TILE_OPC_MAXIB_U,
168 TILE_OPC_MAXIB_U_SN,
169 TILE_OPC_MAXIH,
170 TILE_OPC_MAXIH_SN,
171 TILE_OPC_MF,
172 TILE_OPC_MFSPR,
173 TILE_OPC_MINB_U,
174 TILE_OPC_MINB_U_SN,
175 TILE_OPC_MINH,
176 TILE_OPC_MINH_SN,
177 TILE_OPC_MINIB_U,
178 TILE_OPC_MINIB_U_SN,
179 TILE_OPC_MINIH,
180 TILE_OPC_MINIH_SN,
181 TILE_OPC_MM,
182 TILE_OPC_MNZ,
183 TILE_OPC_MNZ_SN,
184 TILE_OPC_MNZB,
185 TILE_OPC_MNZB_SN,
186 TILE_OPC_MNZH,
187 TILE_OPC_MNZH_SN,
188 TILE_OPC_MTSPR,
189 TILE_OPC_MULHH_SS,
190 TILE_OPC_MULHH_SS_SN,
191 TILE_OPC_MULHH_SU,
192 TILE_OPC_MULHH_SU_SN,
193 TILE_OPC_MULHH_UU,
194 TILE_OPC_MULHH_UU_SN,
195 TILE_OPC_MULHHA_SS,
196 TILE_OPC_MULHHA_SS_SN,
197 TILE_OPC_MULHHA_SU,
198 TILE_OPC_MULHHA_SU_SN,
199 TILE_OPC_MULHHA_UU,
200 TILE_OPC_MULHHA_UU_SN,
201 TILE_OPC_MULHHSA_UU,
202 TILE_OPC_MULHHSA_UU_SN,
203 TILE_OPC_MULHL_SS,
204 TILE_OPC_MULHL_SS_SN,
205 TILE_OPC_MULHL_SU,
206 TILE_OPC_MULHL_SU_SN,
207 TILE_OPC_MULHL_US,
208 TILE_OPC_MULHL_US_SN,
209 TILE_OPC_MULHL_UU,
210 TILE_OPC_MULHL_UU_SN,
211 TILE_OPC_MULHLA_SS,
212 TILE_OPC_MULHLA_SS_SN,
213 TILE_OPC_MULHLA_SU,
214 TILE_OPC_MULHLA_SU_SN,
215 TILE_OPC_MULHLA_US,
216 TILE_OPC_MULHLA_US_SN,
217 TILE_OPC_MULHLA_UU,
218 TILE_OPC_MULHLA_UU_SN,
219 TILE_OPC_MULHLSA_UU,
220 TILE_OPC_MULHLSA_UU_SN,
221 TILE_OPC_MULLL_SS,
222 TILE_OPC_MULLL_SS_SN,
223 TILE_OPC_MULLL_SU,
224 TILE_OPC_MULLL_SU_SN,
225 TILE_OPC_MULLL_UU,
226 TILE_OPC_MULLL_UU_SN,
227 TILE_OPC_MULLLA_SS,
228 TILE_OPC_MULLLA_SS_SN,
229 TILE_OPC_MULLLA_SU,
230 TILE_OPC_MULLLA_SU_SN,
231 TILE_OPC_MULLLA_UU,
232 TILE_OPC_MULLLA_UU_SN,
233 TILE_OPC_MULLLSA_UU,
234 TILE_OPC_MULLLSA_UU_SN,
235 TILE_OPC_MVNZ,
236 TILE_OPC_MVNZ_SN,
237 TILE_OPC_MVZ,
238 TILE_OPC_MVZ_SN,
239 TILE_OPC_MZ,
240 TILE_OPC_MZ_SN,
241 TILE_OPC_MZB,
242 TILE_OPC_MZB_SN,
243 TILE_OPC_MZH,
244 TILE_OPC_MZH_SN,
245 TILE_OPC_NAP,
246 TILE_OPC_NOP,
247 TILE_OPC_NOR,
248 TILE_OPC_NOR_SN,
249 TILE_OPC_OR,
250 TILE_OPC_OR_SN,
251 TILE_OPC_ORI,
252 TILE_OPC_ORI_SN,
253 TILE_OPC_PACKBS_U,
254 TILE_OPC_PACKBS_U_SN,
255 TILE_OPC_PACKHB,
256 TILE_OPC_PACKHB_SN,
257 TILE_OPC_PACKHS,
258 TILE_OPC_PACKHS_SN,
259 TILE_OPC_PACKLB,
260 TILE_OPC_PACKLB_SN,
261 TILE_OPC_PCNT,
262 TILE_OPC_PCNT_SN,
263 TILE_OPC_RL,
264 TILE_OPC_RL_SN,
265 TILE_OPC_RLI,
266 TILE_OPC_RLI_SN,
267 TILE_OPC_S1A,
268 TILE_OPC_S1A_SN,
269 TILE_OPC_S2A,
270 TILE_OPC_S2A_SN,
271 TILE_OPC_S3A,
272 TILE_OPC_S3A_SN,
273 TILE_OPC_SADAB_U,
274 TILE_OPC_SADAB_U_SN,
275 TILE_OPC_SADAH,
276 TILE_OPC_SADAH_SN,
277 TILE_OPC_SADAH_U,
278 TILE_OPC_SADAH_U_SN,
279 TILE_OPC_SADB_U,
280 TILE_OPC_SADB_U_SN,
281 TILE_OPC_SADH,
282 TILE_OPC_SADH_SN,
283 TILE_OPC_SADH_U,
284 TILE_OPC_SADH_U_SN,
285 TILE_OPC_SB,
286 TILE_OPC_SBADD,
287 TILE_OPC_SEQ,
288 TILE_OPC_SEQ_SN,
289 TILE_OPC_SEQB,
290 TILE_OPC_SEQB_SN,
291 TILE_OPC_SEQH,
292 TILE_OPC_SEQH_SN,
293 TILE_OPC_SEQI,
294 TILE_OPC_SEQI_SN,
295 TILE_OPC_SEQIB,
296 TILE_OPC_SEQIB_SN,
297 TILE_OPC_SEQIH,
298 TILE_OPC_SEQIH_SN,
299 TILE_OPC_SH,
300 TILE_OPC_SHADD,
301 TILE_OPC_SHL,
302 TILE_OPC_SHL_SN,
303 TILE_OPC_SHLB,
304 TILE_OPC_SHLB_SN,
305 TILE_OPC_SHLH,
306 TILE_OPC_SHLH_SN,
307 TILE_OPC_SHLI,
308 TILE_OPC_SHLI_SN,
309 TILE_OPC_SHLIB,
310 TILE_OPC_SHLIB_SN,
311 TILE_OPC_SHLIH,
312 TILE_OPC_SHLIH_SN,
313 TILE_OPC_SHR,
314 TILE_OPC_SHR_SN,
315 TILE_OPC_SHRB,
316 TILE_OPC_SHRB_SN,
317 TILE_OPC_SHRH,
318 TILE_OPC_SHRH_SN,
319 TILE_OPC_SHRI,
320 TILE_OPC_SHRI_SN,
321 TILE_OPC_SHRIB,
322 TILE_OPC_SHRIB_SN,
323 TILE_OPC_SHRIH,
324 TILE_OPC_SHRIH_SN,
325 TILE_OPC_SLT,
326 TILE_OPC_SLT_SN,
327 TILE_OPC_SLT_U,
328 TILE_OPC_SLT_U_SN,
329 TILE_OPC_SLTB,
330 TILE_OPC_SLTB_SN,
331 TILE_OPC_SLTB_U,
332 TILE_OPC_SLTB_U_SN,
333 TILE_OPC_SLTE,
334 TILE_OPC_SLTE_SN,
335 TILE_OPC_SLTE_U,
336 TILE_OPC_SLTE_U_SN,
337 TILE_OPC_SLTEB,
338 TILE_OPC_SLTEB_SN,
339 TILE_OPC_SLTEB_U,
340 TILE_OPC_SLTEB_U_SN,
341 TILE_OPC_SLTEH,
342 TILE_OPC_SLTEH_SN,
343 TILE_OPC_SLTEH_U,
344 TILE_OPC_SLTEH_U_SN,
345 TILE_OPC_SLTH,
346 TILE_OPC_SLTH_SN,
347 TILE_OPC_SLTH_U,
348 TILE_OPC_SLTH_U_SN,
349 TILE_OPC_SLTI,
350 TILE_OPC_SLTI_SN,
351 TILE_OPC_SLTI_U,
352 TILE_OPC_SLTI_U_SN,
353 TILE_OPC_SLTIB,
354 TILE_OPC_SLTIB_SN,
355 TILE_OPC_SLTIB_U,
356 TILE_OPC_SLTIB_U_SN,
357 TILE_OPC_SLTIH,
358 TILE_OPC_SLTIH_SN,
359 TILE_OPC_SLTIH_U,
360 TILE_OPC_SLTIH_U_SN,
361 TILE_OPC_SNE,
362 TILE_OPC_SNE_SN,
363 TILE_OPC_SNEB,
364 TILE_OPC_SNEB_SN,
365 TILE_OPC_SNEH,
366 TILE_OPC_SNEH_SN,
367 TILE_OPC_SRA,
368 TILE_OPC_SRA_SN,
369 TILE_OPC_SRAB,
370 TILE_OPC_SRAB_SN,
371 TILE_OPC_SRAH,
372 TILE_OPC_SRAH_SN,
373 TILE_OPC_SRAI,
374 TILE_OPC_SRAI_SN,
375 TILE_OPC_SRAIB,
376 TILE_OPC_SRAIB_SN,
377 TILE_OPC_SRAIH,
378 TILE_OPC_SRAIH_SN,
379 TILE_OPC_SUB,
380 TILE_OPC_SUB_SN,
381 TILE_OPC_SUBB,
382 TILE_OPC_SUBB_SN,
383 TILE_OPC_SUBBS_U,
384 TILE_OPC_SUBBS_U_SN,
385 TILE_OPC_SUBH,
386 TILE_OPC_SUBH_SN,
387 TILE_OPC_SUBHS,
388 TILE_OPC_SUBHS_SN,
389 TILE_OPC_SUBS,
390 TILE_OPC_SUBS_SN,
391 TILE_OPC_SW,
392 TILE_OPC_SWADD,
393 TILE_OPC_SWINT0,
394 TILE_OPC_SWINT1,
395 TILE_OPC_SWINT2,
396 TILE_OPC_SWINT3,
397 TILE_OPC_TBLIDXB0,
398 TILE_OPC_TBLIDXB0_SN,
399 TILE_OPC_TBLIDXB1,
400 TILE_OPC_TBLIDXB1_SN,
401 TILE_OPC_TBLIDXB2,
402 TILE_OPC_TBLIDXB2_SN,
403 TILE_OPC_TBLIDXB3,
404 TILE_OPC_TBLIDXB3_SN,
405 TILE_OPC_TNS,
406 TILE_OPC_TNS_SN,
407 TILE_OPC_WH64,
408 TILE_OPC_XOR,
409 TILE_OPC_XOR_SN,
410 TILE_OPC_XORI,
411 TILE_OPC_XORI_SN,
412 TILE_OPC_NONE
413} tile_mnemonic;
414
415/* 64-bit pattern for a { bpt ; nop } bundle. */
416#define TILE_BPT_BUNDLE 0x400b3cae70166000ULL
417
418
419#define TILE_ELF_MACHINE_CODE EM_TILEPRO
420
421#define TILE_ELF_NAME "elf32-tilepro"
422
423
424static __inline unsigned int
425get_BrOff_SN(tile_bundle_bits num)
426{
427 const unsigned int n = (unsigned int)num;
428 return (((n >> 0)) & 0x3ff);
429}
430
431static __inline unsigned int
432get_BrOff_X1(tile_bundle_bits n)
433{
434 return (((unsigned int)(n >> 43)) & 0x00007fff) |
435 (((unsigned int)(n >> 20)) & 0x00018000);
436}
437
438static __inline unsigned int
439get_BrType_X1(tile_bundle_bits n)
440{
441 return (((unsigned int)(n >> 31)) & 0xf);
442}
443
444static __inline unsigned int
445get_Dest_Imm8_X1(tile_bundle_bits n)
446{
447 return (((unsigned int)(n >> 31)) & 0x0000003f) |
448 (((unsigned int)(n >> 43)) & 0x000000c0);
449}
450
451static __inline unsigned int
452get_Dest_SN(tile_bundle_bits num)
453{
454 const unsigned int n = (unsigned int)num;
455 return (((n >> 2)) & 0x3);
456}
457
458static __inline unsigned int
459get_Dest_X0(tile_bundle_bits num)
460{
461 const unsigned int n = (unsigned int)num;
462 return (((n >> 0)) & 0x3f);
463}
464
465static __inline unsigned int
466get_Dest_X1(tile_bundle_bits n)
467{
468 return (((unsigned int)(n >> 31)) & 0x3f);
469}
470
471static __inline unsigned int
472get_Dest_Y0(tile_bundle_bits num)
473{
474 const unsigned int n = (unsigned int)num;
475 return (((n >> 0)) & 0x3f);
476}
477
478static __inline unsigned int
479get_Dest_Y1(tile_bundle_bits n)
480{
481 return (((unsigned int)(n >> 31)) & 0x3f);
482}
483
484static __inline unsigned int
485get_Imm16_X0(tile_bundle_bits num)
486{
487 const unsigned int n = (unsigned int)num;
488 return (((n >> 12)) & 0xffff);
489}
490
491static __inline unsigned int
492get_Imm16_X1(tile_bundle_bits n)
493{
494 return (((unsigned int)(n >> 43)) & 0xffff);
495}
496
497static __inline unsigned int
498get_Imm8_SN(tile_bundle_bits num)
499{
500 const unsigned int n = (unsigned int)num;
501 return (((n >> 0)) & 0xff);
502}
503
504static __inline unsigned int
505get_Imm8_X0(tile_bundle_bits num)
506{
507 const unsigned int n = (unsigned int)num;
508 return (((n >> 12)) & 0xff);
509}
510
511static __inline unsigned int
512get_Imm8_X1(tile_bundle_bits n)
513{
514 return (((unsigned int)(n >> 43)) & 0xff);
515}
516
517static __inline unsigned int
518get_Imm8_Y0(tile_bundle_bits num)
519{
520 const unsigned int n = (unsigned int)num;
521 return (((n >> 12)) & 0xff);
522}
523
524static __inline unsigned int
525get_Imm8_Y1(tile_bundle_bits n)
526{
527 return (((unsigned int)(n >> 43)) & 0xff);
528}
529
530static __inline unsigned int
531get_ImmOpcodeExtension_X0(tile_bundle_bits num)
532{
533 const unsigned int n = (unsigned int)num;
534 return (((n >> 20)) & 0x7f);
535}
536
537static __inline unsigned int
538get_ImmOpcodeExtension_X1(tile_bundle_bits n)
539{
540 return (((unsigned int)(n >> 51)) & 0x7f);
541}
542
543static __inline unsigned int
544get_ImmRROpcodeExtension_SN(tile_bundle_bits num)
545{
546 const unsigned int n = (unsigned int)num;
547 return (((n >> 8)) & 0x3);
548}
549
550static __inline unsigned int
551get_JOffLong_X1(tile_bundle_bits n)
552{
553 return (((unsigned int)(n >> 43)) & 0x00007fff) |
554 (((unsigned int)(n >> 20)) & 0x00018000) |
555 (((unsigned int)(n >> 14)) & 0x001e0000) |
556 (((unsigned int)(n >> 16)) & 0x07e00000) |
557 (((unsigned int)(n >> 31)) & 0x18000000);
558}
559
560static __inline unsigned int
561get_JOff_X1(tile_bundle_bits n)
562{
563 return (((unsigned int)(n >> 43)) & 0x00007fff) |
564 (((unsigned int)(n >> 20)) & 0x00018000) |
565 (((unsigned int)(n >> 14)) & 0x001e0000) |
566 (((unsigned int)(n >> 16)) & 0x07e00000) |
567 (((unsigned int)(n >> 31)) & 0x08000000);
568}
569
570static __inline unsigned int
571get_MF_Imm15_X1(tile_bundle_bits n)
572{
573 return (((unsigned int)(n >> 37)) & 0x00003fff) |
574 (((unsigned int)(n >> 44)) & 0x00004000);
575}
576
577static __inline unsigned int
578get_MMEnd_X0(tile_bundle_bits num)
579{
580 const unsigned int n = (unsigned int)num;
581 return (((n >> 18)) & 0x1f);
582}
583
584static __inline unsigned int
585get_MMEnd_X1(tile_bundle_bits n)
586{
587 return (((unsigned int)(n >> 49)) & 0x1f);
588}
589
590static __inline unsigned int
591get_MMStart_X0(tile_bundle_bits num)
592{
593 const unsigned int n = (unsigned int)num;
594 return (((n >> 23)) & 0x1f);
595}
596
597static __inline unsigned int
598get_MMStart_X1(tile_bundle_bits n)
599{
600 return (((unsigned int)(n >> 54)) & 0x1f);
601}
602
603static __inline unsigned int
604get_MT_Imm15_X1(tile_bundle_bits n)
605{
606 return (((unsigned int)(n >> 31)) & 0x0000003f) |
607 (((unsigned int)(n >> 37)) & 0x00003fc0) |
608 (((unsigned int)(n >> 44)) & 0x00004000);
609}
610
611static __inline unsigned int
612get_Mode(tile_bundle_bits n)
613{
614 return (((unsigned int)(n >> 63)) & 0x1);
615}
616
617static __inline unsigned int
618get_NoRegOpcodeExtension_SN(tile_bundle_bits num)
619{
620 const unsigned int n = (unsigned int)num;
621 return (((n >> 0)) & 0xf);
622}
623
624static __inline unsigned int
625get_Opcode_SN(tile_bundle_bits num)
626{
627 const unsigned int n = (unsigned int)num;
628 return (((n >> 10)) & 0x3f);
629}
630
631static __inline unsigned int
632get_Opcode_X0(tile_bundle_bits num)
633{
634 const unsigned int n = (unsigned int)num;
635 return (((n >> 28)) & 0x7);
636}
637
638static __inline unsigned int
639get_Opcode_X1(tile_bundle_bits n)
640{
641 return (((unsigned int)(n >> 59)) & 0xf);
642}
643
644static __inline unsigned int
645get_Opcode_Y0(tile_bundle_bits num)
646{
647 const unsigned int n = (unsigned int)num;
648 return (((n >> 27)) & 0xf);
649}
650
651static __inline unsigned int
652get_Opcode_Y1(tile_bundle_bits n)
653{
654 return (((unsigned int)(n >> 59)) & 0xf);
655}
656
657static __inline unsigned int
658get_Opcode_Y2(tile_bundle_bits n)
659{
660 return (((unsigned int)(n >> 56)) & 0x7);
661}
662
663static __inline unsigned int
664get_RROpcodeExtension_SN(tile_bundle_bits num)
665{
666 const unsigned int n = (unsigned int)num;
667 return (((n >> 4)) & 0xf);
668}
669
670static __inline unsigned int
671get_RRROpcodeExtension_X0(tile_bundle_bits num)
672{
673 const unsigned int n = (unsigned int)num;
674 return (((n >> 18)) & 0x1ff);
675}
676
677static __inline unsigned int
678get_RRROpcodeExtension_X1(tile_bundle_bits n)
679{
680 return (((unsigned int)(n >> 49)) & 0x1ff);
681}
682
683static __inline unsigned int
684get_RRROpcodeExtension_Y0(tile_bundle_bits num)
685{
686 const unsigned int n = (unsigned int)num;
687 return (((n >> 18)) & 0x3);
688}
689
690static __inline unsigned int
691get_RRROpcodeExtension_Y1(tile_bundle_bits n)
692{
693 return (((unsigned int)(n >> 49)) & 0x3);
694}
695
696static __inline unsigned int
697get_RouteOpcodeExtension_SN(tile_bundle_bits num)
698{
699 const unsigned int n = (unsigned int)num;
700 return (((n >> 0)) & 0x3ff);
701}
702
703static __inline unsigned int
704get_S_X0(tile_bundle_bits num)
705{
706 const unsigned int n = (unsigned int)num;
707 return (((n >> 27)) & 0x1);
708}
709
710static __inline unsigned int
711get_S_X1(tile_bundle_bits n)
712{
713 return (((unsigned int)(n >> 58)) & 0x1);
714}
715
716static __inline unsigned int
717get_ShAmt_X0(tile_bundle_bits num)
718{
719 const unsigned int n = (unsigned int)num;
720 return (((n >> 12)) & 0x1f);
721}
722
723static __inline unsigned int
724get_ShAmt_X1(tile_bundle_bits n)
725{
726 return (((unsigned int)(n >> 43)) & 0x1f);
727}
728
729static __inline unsigned int
730get_ShAmt_Y0(tile_bundle_bits num)
731{
732 const unsigned int n = (unsigned int)num;
733 return (((n >> 12)) & 0x1f);
734}
735
736static __inline unsigned int
737get_ShAmt_Y1(tile_bundle_bits n)
738{
739 return (((unsigned int)(n >> 43)) & 0x1f);
740}
741
742static __inline unsigned int
743get_SrcA_X0(tile_bundle_bits num)
744{
745 const unsigned int n = (unsigned int)num;
746 return (((n >> 6)) & 0x3f);
747}
748
749static __inline unsigned int
750get_SrcA_X1(tile_bundle_bits n)
751{
752 return (((unsigned int)(n >> 37)) & 0x3f);
753}
754
755static __inline unsigned int
756get_SrcA_Y0(tile_bundle_bits num)
757{
758 const unsigned int n = (unsigned int)num;
759 return (((n >> 6)) & 0x3f);
760}
761
762static __inline unsigned int
763get_SrcA_Y1(tile_bundle_bits n)
764{
765 return (((unsigned int)(n >> 37)) & 0x3f);
766}
767
768static __inline unsigned int
769get_SrcA_Y2(tile_bundle_bits n)
770{
771 return (((n >> 26)) & 0x00000001) |
772 (((unsigned int)(n >> 50)) & 0x0000003e);
773}
774
775static __inline unsigned int
776get_SrcBDest_Y2(tile_bundle_bits num)
777{
778 const unsigned int n = (unsigned int)num;
779 return (((n >> 20)) & 0x3f);
780}
781
782static __inline unsigned int
783get_SrcB_X0(tile_bundle_bits num)
784{
785 const unsigned int n = (unsigned int)num;
786 return (((n >> 12)) & 0x3f);
787}
788
789static __inline unsigned int
790get_SrcB_X1(tile_bundle_bits n)
791{
792 return (((unsigned int)(n >> 43)) & 0x3f);
793}
794
795static __inline unsigned int
796get_SrcB_Y0(tile_bundle_bits num)
797{
798 const unsigned int n = (unsigned int)num;
799 return (((n >> 12)) & 0x3f);
800}
801
802static __inline unsigned int
803get_SrcB_Y1(tile_bundle_bits n)
804{
805 return (((unsigned int)(n >> 43)) & 0x3f);
806}
807
808static __inline unsigned int
809get_Src_SN(tile_bundle_bits num)
810{
811 const unsigned int n = (unsigned int)num;
812 return (((n >> 0)) & 0x3);
813}
814
815static __inline unsigned int
816get_UnOpcodeExtension_X0(tile_bundle_bits num)
817{
818 const unsigned int n = (unsigned int)num;
819 return (((n >> 12)) & 0x1f);
820}
821
822static __inline unsigned int
823get_UnOpcodeExtension_X1(tile_bundle_bits n)
824{
825 return (((unsigned int)(n >> 43)) & 0x1f);
826}
827
828static __inline unsigned int
829get_UnOpcodeExtension_Y0(tile_bundle_bits num)
830{
831 const unsigned int n = (unsigned int)num;
832 return (((n >> 12)) & 0x1f);
833}
834
835static __inline unsigned int
836get_UnOpcodeExtension_Y1(tile_bundle_bits n)
837{
838 return (((unsigned int)(n >> 43)) & 0x1f);
839}
840
841static __inline unsigned int
842get_UnShOpcodeExtension_X0(tile_bundle_bits num)
843{
844 const unsigned int n = (unsigned int)num;
845 return (((n >> 17)) & 0x3ff);
846}
847
848static __inline unsigned int
849get_UnShOpcodeExtension_X1(tile_bundle_bits n)
850{
851 return (((unsigned int)(n >> 48)) & 0x3ff);
852}
853
854static __inline unsigned int
855get_UnShOpcodeExtension_Y0(tile_bundle_bits num)
856{
857 const unsigned int n = (unsigned int)num;
858 return (((n >> 17)) & 0x7);
859}
860
861static __inline unsigned int
862get_UnShOpcodeExtension_Y1(tile_bundle_bits n)
863{
864 return (((unsigned int)(n >> 48)) & 0x7);
865}
866
867
868static __inline int
869sign_extend(int n, int num_bits)
870{
871 int shift = (int)(sizeof(int) * 8 - num_bits);
872 return (n << shift) >> shift;
873}
874
875
876
877static __inline tile_bundle_bits
878create_BrOff_SN(int num)
879{
880 const unsigned int n = (unsigned int)num;
881 return ((n & 0x3ff) << 0);
882}
883
884static __inline tile_bundle_bits
885create_BrOff_X1(int num)
886{
887 const unsigned int n = (unsigned int)num;
888 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
889 (((tile_bundle_bits)(n & 0x00018000)) << 20);
890}
891
892static __inline tile_bundle_bits
893create_BrType_X1(int num)
894{
895 const unsigned int n = (unsigned int)num;
896 return (((tile_bundle_bits)(n & 0xf)) << 31);
897}
898
899static __inline tile_bundle_bits
900create_Dest_Imm8_X1(int num)
901{
902 const unsigned int n = (unsigned int)num;
903 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
904 (((tile_bundle_bits)(n & 0x000000c0)) << 43);
905}
906
907static __inline tile_bundle_bits
908create_Dest_SN(int num)
909{
910 const unsigned int n = (unsigned int)num;
911 return ((n & 0x3) << 2);
912}
913
914static __inline tile_bundle_bits
915create_Dest_X0(int num)
916{
917 const unsigned int n = (unsigned int)num;
918 return ((n & 0x3f) << 0);
919}
920
921static __inline tile_bundle_bits
922create_Dest_X1(int num)
923{
924 const unsigned int n = (unsigned int)num;
925 return (((tile_bundle_bits)(n & 0x3f)) << 31);
926}
927
928static __inline tile_bundle_bits
929create_Dest_Y0(int num)
930{
931 const unsigned int n = (unsigned int)num;
932 return ((n & 0x3f) << 0);
933}
934
935static __inline tile_bundle_bits
936create_Dest_Y1(int num)
937{
938 const unsigned int n = (unsigned int)num;
939 return (((tile_bundle_bits)(n & 0x3f)) << 31);
940}
941
942static __inline tile_bundle_bits
943create_Imm16_X0(int num)
944{
945 const unsigned int n = (unsigned int)num;
946 return ((n & 0xffff) << 12);
947}
948
949static __inline tile_bundle_bits
950create_Imm16_X1(int num)
951{
952 const unsigned int n = (unsigned int)num;
953 return (((tile_bundle_bits)(n & 0xffff)) << 43);
954}
955
956static __inline tile_bundle_bits
957create_Imm8_SN(int num)
958{
959 const unsigned int n = (unsigned int)num;
960 return ((n & 0xff) << 0);
961}
962
963static __inline tile_bundle_bits
964create_Imm8_X0(int num)
965{
966 const unsigned int n = (unsigned int)num;
967 return ((n & 0xff) << 12);
968}
969
970static __inline tile_bundle_bits
971create_Imm8_X1(int num)
972{
973 const unsigned int n = (unsigned int)num;
974 return (((tile_bundle_bits)(n & 0xff)) << 43);
975}
976
977static __inline tile_bundle_bits
978create_Imm8_Y0(int num)
979{
980 const unsigned int n = (unsigned int)num;
981 return ((n & 0xff) << 12);
982}
983
984static __inline tile_bundle_bits
985create_Imm8_Y1(int num)
986{
987 const unsigned int n = (unsigned int)num;
988 return (((tile_bundle_bits)(n & 0xff)) << 43);
989}
990
991static __inline tile_bundle_bits
992create_ImmOpcodeExtension_X0(int num)
993{
994 const unsigned int n = (unsigned int)num;
995 return ((n & 0x7f) << 20);
996}
997
998static __inline tile_bundle_bits
999create_ImmOpcodeExtension_X1(int num)
1000{
1001 const unsigned int n = (unsigned int)num;
1002 return (((tile_bundle_bits)(n & 0x7f)) << 51);
1003}
1004
1005static __inline tile_bundle_bits
1006create_ImmRROpcodeExtension_SN(int num)
1007{
1008 const unsigned int n = (unsigned int)num;
1009 return ((n & 0x3) << 8);
1010}
1011
1012static __inline tile_bundle_bits
1013create_JOffLong_X1(int num)
1014{
1015 const unsigned int n = (unsigned int)num;
1016 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1017 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1018 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1019 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1020 (((tile_bundle_bits)(n & 0x18000000)) << 31);
1021}
1022
1023static __inline tile_bundle_bits
1024create_JOff_X1(int num)
1025{
1026 const unsigned int n = (unsigned int)num;
1027 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1028 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1029 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1030 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1031 (((tile_bundle_bits)(n & 0x08000000)) << 31);
1032}
1033
1034static __inline tile_bundle_bits
1035create_MF_Imm15_X1(int num)
1036{
1037 const unsigned int n = (unsigned int)num;
1038 return (((tile_bundle_bits)(n & 0x00003fff)) << 37) |
1039 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1040}
1041
1042static __inline tile_bundle_bits
1043create_MMEnd_X0(int num)
1044{
1045 const unsigned int n = (unsigned int)num;
1046 return ((n & 0x1f) << 18);
1047}
1048
1049static __inline tile_bundle_bits
1050create_MMEnd_X1(int num)
1051{
1052 const unsigned int n = (unsigned int)num;
1053 return (((tile_bundle_bits)(n & 0x1f)) << 49);
1054}
1055
1056static __inline tile_bundle_bits
1057create_MMStart_X0(int num)
1058{
1059 const unsigned int n = (unsigned int)num;
1060 return ((n & 0x1f) << 23);
1061}
1062
1063static __inline tile_bundle_bits
1064create_MMStart_X1(int num)
1065{
1066 const unsigned int n = (unsigned int)num;
1067 return (((tile_bundle_bits)(n & 0x1f)) << 54);
1068}
1069
1070static __inline tile_bundle_bits
1071create_MT_Imm15_X1(int num)
1072{
1073 const unsigned int n = (unsigned int)num;
1074 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
1075 (((tile_bundle_bits)(n & 0x00003fc0)) << 37) |
1076 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1077}
1078
1079static __inline tile_bundle_bits
1080create_Mode(int num)
1081{
1082 const unsigned int n = (unsigned int)num;
1083 return (((tile_bundle_bits)(n & 0x1)) << 63);
1084}
1085
1086static __inline tile_bundle_bits
1087create_NoRegOpcodeExtension_SN(int num)
1088{
1089 const unsigned int n = (unsigned int)num;
1090 return ((n & 0xf) << 0);
1091}
1092
1093static __inline tile_bundle_bits
1094create_Opcode_SN(int num)
1095{
1096 const unsigned int n = (unsigned int)num;
1097 return ((n & 0x3f) << 10);
1098}
1099
1100static __inline tile_bundle_bits
1101create_Opcode_X0(int num)
1102{
1103 const unsigned int n = (unsigned int)num;
1104 return ((n & 0x7) << 28);
1105}
1106
1107static __inline tile_bundle_bits
1108create_Opcode_X1(int num)
1109{
1110 const unsigned int n = (unsigned int)num;
1111 return (((tile_bundle_bits)(n & 0xf)) << 59);
1112}
1113
1114static __inline tile_bundle_bits
1115create_Opcode_Y0(int num)
1116{
1117 const unsigned int n = (unsigned int)num;
1118 return ((n & 0xf) << 27);
1119}
1120
1121static __inline tile_bundle_bits
1122create_Opcode_Y1(int num)
1123{
1124 const unsigned int n = (unsigned int)num;
1125 return (((tile_bundle_bits)(n & 0xf)) << 59);
1126}
1127
1128static __inline tile_bundle_bits
1129create_Opcode_Y2(int num)
1130{
1131 const unsigned int n = (unsigned int)num;
1132 return (((tile_bundle_bits)(n & 0x7)) << 56);
1133}
1134
1135static __inline tile_bundle_bits
1136create_RROpcodeExtension_SN(int num)
1137{
1138 const unsigned int n = (unsigned int)num;
1139 return ((n & 0xf) << 4);
1140}
1141
1142static __inline tile_bundle_bits
1143create_RRROpcodeExtension_X0(int num)
1144{
1145 const unsigned int n = (unsigned int)num;
1146 return ((n & 0x1ff) << 18);
1147}
1148
1149static __inline tile_bundle_bits
1150create_RRROpcodeExtension_X1(int num)
1151{
1152 const unsigned int n = (unsigned int)num;
1153 return (((tile_bundle_bits)(n & 0x1ff)) << 49);
1154}
1155
1156static __inline tile_bundle_bits
1157create_RRROpcodeExtension_Y0(int num)
1158{
1159 const unsigned int n = (unsigned int)num;
1160 return ((n & 0x3) << 18);
1161}
1162
1163static __inline tile_bundle_bits
1164create_RRROpcodeExtension_Y1(int num)
1165{
1166 const unsigned int n = (unsigned int)num;
1167 return (((tile_bundle_bits)(n & 0x3)) << 49);
1168}
1169
1170static __inline tile_bundle_bits
1171create_RouteOpcodeExtension_SN(int num)
1172{
1173 const unsigned int n = (unsigned int)num;
1174 return ((n & 0x3ff) << 0);
1175}
1176
1177static __inline tile_bundle_bits
1178create_S_X0(int num)
1179{
1180 const unsigned int n = (unsigned int)num;
1181 return ((n & 0x1) << 27);
1182}
1183
1184static __inline tile_bundle_bits
1185create_S_X1(int num)
1186{
1187 const unsigned int n = (unsigned int)num;
1188 return (((tile_bundle_bits)(n & 0x1)) << 58);
1189}
1190
1191static __inline tile_bundle_bits
1192create_ShAmt_X0(int num)
1193{
1194 const unsigned int n = (unsigned int)num;
1195 return ((n & 0x1f) << 12);
1196}
1197
1198static __inline tile_bundle_bits
1199create_ShAmt_X1(int num)
1200{
1201 const unsigned int n = (unsigned int)num;
1202 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1203}
1204
1205static __inline tile_bundle_bits
1206create_ShAmt_Y0(int num)
1207{
1208 const unsigned int n = (unsigned int)num;
1209 return ((n & 0x1f) << 12);
1210}
1211
1212static __inline tile_bundle_bits
1213create_ShAmt_Y1(int num)
1214{
1215 const unsigned int n = (unsigned int)num;
1216 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1217}
1218
1219static __inline tile_bundle_bits
1220create_SrcA_X0(int num)
1221{
1222 const unsigned int n = (unsigned int)num;
1223 return ((n & 0x3f) << 6);
1224}
1225
1226static __inline tile_bundle_bits
1227create_SrcA_X1(int num)
1228{
1229 const unsigned int n = (unsigned int)num;
1230 return (((tile_bundle_bits)(n & 0x3f)) << 37);
1231}
1232
1233static __inline tile_bundle_bits
1234create_SrcA_Y0(int num)
1235{
1236 const unsigned int n = (unsigned int)num;
1237 return ((n & 0x3f) << 6);
1238}
1239
1240static __inline tile_bundle_bits
1241create_SrcA_Y1(int num)
1242{
1243 const unsigned int n = (unsigned int)num;
1244 return (((tile_bundle_bits)(n & 0x3f)) << 37);
1245}
1246
1247static __inline tile_bundle_bits
1248create_SrcA_Y2(int num)
1249{
1250 const unsigned int n = (unsigned int)num;
1251 return ((n & 0x00000001) << 26) |
1252 (((tile_bundle_bits)(n & 0x0000003e)) << 50);
1253}
1254
1255static __inline tile_bundle_bits
1256create_SrcBDest_Y2(int num)
1257{
1258 const unsigned int n = (unsigned int)num;
1259 return ((n & 0x3f) << 20);
1260}
1261
1262static __inline tile_bundle_bits
1263create_SrcB_X0(int num)
1264{
1265 const unsigned int n = (unsigned int)num;
1266 return ((n & 0x3f) << 12);
1267}
1268
1269static __inline tile_bundle_bits
1270create_SrcB_X1(int num)
1271{
1272 const unsigned int n = (unsigned int)num;
1273 return (((tile_bundle_bits)(n & 0x3f)) << 43);
1274}
1275
1276static __inline tile_bundle_bits
1277create_SrcB_Y0(int num)
1278{
1279 const unsigned int n = (unsigned int)num;
1280 return ((n & 0x3f) << 12);
1281}
1282
1283static __inline tile_bundle_bits
1284create_SrcB_Y1(int num)
1285{
1286 const unsigned int n = (unsigned int)num;
1287 return (((tile_bundle_bits)(n & 0x3f)) << 43);
1288}
1289
1290static __inline tile_bundle_bits
1291create_Src_SN(int num)
1292{
1293 const unsigned int n = (unsigned int)num;
1294 return ((n & 0x3) << 0);
1295}
1296
1297static __inline tile_bundle_bits
1298create_UnOpcodeExtension_X0(int num)
1299{
1300 const unsigned int n = (unsigned int)num;
1301 return ((n & 0x1f) << 12);
1302}
1303
1304static __inline tile_bundle_bits
1305create_UnOpcodeExtension_X1(int num)
1306{
1307 const unsigned int n = (unsigned int)num;
1308 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1309}
1310
1311static __inline tile_bundle_bits
1312create_UnOpcodeExtension_Y0(int num)
1313{
1314 const unsigned int n = (unsigned int)num;
1315 return ((n & 0x1f) << 12);
1316}
1317
1318static __inline tile_bundle_bits
1319create_UnOpcodeExtension_Y1(int num)
1320{
1321 const unsigned int n = (unsigned int)num;
1322 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1323}
1324
1325static __inline tile_bundle_bits
1326create_UnShOpcodeExtension_X0(int num)
1327{
1328 const unsigned int n = (unsigned int)num;
1329 return ((n & 0x3ff) << 17);
1330}
1331
1332static __inline tile_bundle_bits
1333create_UnShOpcodeExtension_X1(int num)
1334{
1335 const unsigned int n = (unsigned int)num;
1336 return (((tile_bundle_bits)(n & 0x3ff)) << 48);
1337}
1338
1339static __inline tile_bundle_bits
1340create_UnShOpcodeExtension_Y0(int num)
1341{
1342 const unsigned int n = (unsigned int)num;
1343 return ((n & 0x7) << 17);
1344}
1345
1346static __inline tile_bundle_bits
1347create_UnShOpcodeExtension_Y1(int num)
1348{
1349 const unsigned int n = (unsigned int)num;
1350 return (((tile_bundle_bits)(n & 0x7)) << 48);
1351}
1352
1353
1354
1355typedef enum
1356{
1357 TILE_PIPELINE_X0,
1358 TILE_PIPELINE_X1,
1359 TILE_PIPELINE_Y0,
1360 TILE_PIPELINE_Y1,
1361 TILE_PIPELINE_Y2,
1362} tile_pipeline;
1363
1364#define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1)
1365
1366typedef enum
1367{
1368 TILE_OP_TYPE_REGISTER,
1369 TILE_OP_TYPE_IMMEDIATE,
1370 TILE_OP_TYPE_ADDRESS,
1371 TILE_OP_TYPE_SPR
1372} tile_operand_type;
1373
1374/* This is the bit that determines if a bundle is in the Y encoding. */
1375#define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63)
1376
1377enum
1378{
1379 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
1380 TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
1381
1382 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
1383 TILE_NUM_PIPELINE_ENCODINGS = 5,
1384
1385 /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */
1386 TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
1387
1388 /* Instructions take this many bytes. */
1389 TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES,
1390
1391 /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */
1392 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
1393
1394 /* Bundles should be aligned modulo this number of bytes. */
1395 TILE_BUNDLE_ALIGNMENT_IN_BYTES =
1396 (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
1397
1398 /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */
1399 TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
1400
1401 /* Static network instructions take this many bytes. */
1402 TILE_SN_INSTRUCTION_SIZE_IN_BYTES =
1403 (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
1404
1405 /* Number of registers (some are magic, such as network I/O). */
1406 TILE_NUM_REGISTERS = 64,
1407
1408 /* Number of static network registers. */
1409 TILE_NUM_SN_REGISTERS = 4
1410};
1411
1412
1413struct tile_operand
1414{
1415 /* Is this operand a register, immediate or address? */
1416 tile_operand_type type;
1417
1418 /* The default relocation type for this operand. */
1419 signed int default_reloc : 16;
1420
1421 /* How many bits is this value? (used for range checking) */
1422 unsigned int num_bits : 5;
1423
1424 /* Is the value signed? (used for range checking) */
1425 unsigned int is_signed : 1;
1426
1427 /* Is this operand a source register? */
1428 unsigned int is_src_reg : 1;
1429
1430 /* Is this operand written? (i.e. is it a destination register) */
1431 unsigned int is_dest_reg : 1;
1432
1433 /* Is this operand PC-relative? */
1434 unsigned int is_pc_relative : 1;
1435
1436 /* By how many bits do we right shift the value before inserting? */
1437 unsigned int rightshift : 2;
1438
1439 /* Return the bits for this operand to be ORed into an existing bundle. */
1440 tile_bundle_bits (*insert) (int op);
1441
1442 /* Extract this operand and return it. */
1443 unsigned int (*extract) (tile_bundle_bits bundle);
1444};
1445
1446
1447extern const struct tile_operand tile_operands[];
1448
1449/* One finite-state machine per pipe for rapid instruction decoding. */
1450extern const unsigned short * const
1451tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS];
1452
1453
1454struct tile_opcode
1455{
1456 /* The opcode mnemonic, e.g. "add" */
1457 const char *name;
1458
1459 /* The enum value for this mnemonic. */
1460 tile_mnemonic mnemonic;
1461
1462 /* A bit mask of which of the five pipes this instruction
1463 is compatible with:
1464 X0 0x01
1465 X1 0x02
1466 Y0 0x04
1467 Y1 0x08
1468 Y2 0x10 */
1469 unsigned char pipes;
1470
1471 /* How many operands are there? */
1472 unsigned char num_operands;
1473
1474 /* Which register does this write implicitly, or TREG_ZERO if none? */
1475 unsigned char implicitly_written_register;
1476
1477 /* Can this be bundled with other instructions (almost always true). */
1478 unsigned char can_bundle;
1479
1480 /* The description of the operands. Each of these is an
1481 * index into the tile_operands[] table. */
1482 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS];
1483
1484};
1485
1486extern const struct tile_opcode tile_opcodes[];
1487
1488
1489/* Used for non-textual disassembly into structs. */
1490struct tile_decoded_instruction
1491{
1492 const struct tile_opcode *opcode;
1493 const struct tile_operand *operands[TILE_MAX_OPERANDS];
1494 int operand_values[TILE_MAX_OPERANDS];
1495};
1496
1497
1498/* Disassemble a bundle into a struct for machine processing. */
1499extern int parse_insn_tile(tile_bundle_bits bits,
1500 unsigned int pc,
1501 struct tile_decoded_instruction
1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
1503
1504
1505/* Given a set of bundle bits and a specific pipe, returns which
1506 * instruction the bundle contains in that pipe.
1507 */
1508extern const struct tile_opcode *
1509find_opcode(tile_bundle_bits bits, tile_pipeline pipe);
1510
1511
1512
1513#endif /* opcode_tile_h */
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h
new file mode 100644
index 00000000000..c0633466cd5
--- /dev/null
+++ b/arch/tile/include/asm/opcode-tile_64.h
@@ -0,0 +1,1248 @@
1/* tile.h -- Header file for TILE opcode table
2 Copyright (C) 2005 Free Software Foundation, Inc.
3 Contributed by Tilera Corp. */
4
5#ifndef opcode_tile_h
6#define opcode_tile_h
7
8typedef unsigned long long tilegx_bundle_bits;
9
10
11enum
12{
13 TILEGX_MAX_OPERANDS = 4 /* bfexts */
14};
15
16typedef enum
17{
18 TILEGX_OPC_BPT,
19 TILEGX_OPC_INFO,
20 TILEGX_OPC_INFOL,
21 TILEGX_OPC_MOVE,
22 TILEGX_OPC_MOVEI,
23 TILEGX_OPC_MOVELI,
24 TILEGX_OPC_PREFETCH,
25 TILEGX_OPC_PREFETCH_ADD_L1,
26 TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
27 TILEGX_OPC_PREFETCH_ADD_L2,
28 TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
29 TILEGX_OPC_PREFETCH_ADD_L3,
30 TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
31 TILEGX_OPC_PREFETCH_L1,
32 TILEGX_OPC_PREFETCH_L1_FAULT,
33 TILEGX_OPC_PREFETCH_L2,
34 TILEGX_OPC_PREFETCH_L2_FAULT,
35 TILEGX_OPC_PREFETCH_L3,
36 TILEGX_OPC_PREFETCH_L3_FAULT,
37 TILEGX_OPC_RAISE,
38 TILEGX_OPC_ADD,
39 TILEGX_OPC_ADDI,
40 TILEGX_OPC_ADDLI,
41 TILEGX_OPC_ADDX,
42 TILEGX_OPC_ADDXI,
43 TILEGX_OPC_ADDXLI,
44 TILEGX_OPC_ADDXSC,
45 TILEGX_OPC_AND,
46 TILEGX_OPC_ANDI,
47 TILEGX_OPC_BEQZ,
48 TILEGX_OPC_BEQZT,
49 TILEGX_OPC_BFEXTS,
50 TILEGX_OPC_BFEXTU,
51 TILEGX_OPC_BFINS,
52 TILEGX_OPC_BGEZ,
53 TILEGX_OPC_BGEZT,
54 TILEGX_OPC_BGTZ,
55 TILEGX_OPC_BGTZT,
56 TILEGX_OPC_BLBC,
57 TILEGX_OPC_BLBCT,
58 TILEGX_OPC_BLBS,
59 TILEGX_OPC_BLBST,
60 TILEGX_OPC_BLEZ,
61 TILEGX_OPC_BLEZT,
62 TILEGX_OPC_BLTZ,
63 TILEGX_OPC_BLTZT,
64 TILEGX_OPC_BNEZ,
65 TILEGX_OPC_BNEZT,
66 TILEGX_OPC_CLZ,
67 TILEGX_OPC_CMOVEQZ,
68 TILEGX_OPC_CMOVNEZ,
69 TILEGX_OPC_CMPEQ,
70 TILEGX_OPC_CMPEQI,
71 TILEGX_OPC_CMPEXCH,
72 TILEGX_OPC_CMPEXCH4,
73 TILEGX_OPC_CMPLES,
74 TILEGX_OPC_CMPLEU,
75 TILEGX_OPC_CMPLTS,
76 TILEGX_OPC_CMPLTSI,
77 TILEGX_OPC_CMPLTU,
78 TILEGX_OPC_CMPLTUI,
79 TILEGX_OPC_CMPNE,
80 TILEGX_OPC_CMUL,
81 TILEGX_OPC_CMULA,
82 TILEGX_OPC_CMULAF,
83 TILEGX_OPC_CMULF,
84 TILEGX_OPC_CMULFR,
85 TILEGX_OPC_CMULH,
86 TILEGX_OPC_CMULHR,
87 TILEGX_OPC_CRC32_32,
88 TILEGX_OPC_CRC32_8,
89 TILEGX_OPC_CTZ,
90 TILEGX_OPC_DBLALIGN,
91 TILEGX_OPC_DBLALIGN2,
92 TILEGX_OPC_DBLALIGN4,
93 TILEGX_OPC_DBLALIGN6,
94 TILEGX_OPC_DRAIN,
95 TILEGX_OPC_DTLBPR,
96 TILEGX_OPC_EXCH,
97 TILEGX_OPC_EXCH4,
98 TILEGX_OPC_FDOUBLE_ADD_FLAGS,
99 TILEGX_OPC_FDOUBLE_ADDSUB,
100 TILEGX_OPC_FDOUBLE_MUL_FLAGS,
101 TILEGX_OPC_FDOUBLE_PACK1,
102 TILEGX_OPC_FDOUBLE_PACK2,
103 TILEGX_OPC_FDOUBLE_SUB_FLAGS,
104 TILEGX_OPC_FDOUBLE_UNPACK_MAX,
105 TILEGX_OPC_FDOUBLE_UNPACK_MIN,
106 TILEGX_OPC_FETCHADD,
107 TILEGX_OPC_FETCHADD4,
108 TILEGX_OPC_FETCHADDGEZ,
109 TILEGX_OPC_FETCHADDGEZ4,
110 TILEGX_OPC_FETCHAND,
111 TILEGX_OPC_FETCHAND4,
112 TILEGX_OPC_FETCHOR,
113 TILEGX_OPC_FETCHOR4,
114 TILEGX_OPC_FINV,
115 TILEGX_OPC_FLUSH,
116 TILEGX_OPC_FLUSHWB,
117 TILEGX_OPC_FNOP,
118 TILEGX_OPC_FSINGLE_ADD1,
119 TILEGX_OPC_FSINGLE_ADDSUB2,
120 TILEGX_OPC_FSINGLE_MUL1,
121 TILEGX_OPC_FSINGLE_MUL2,
122 TILEGX_OPC_FSINGLE_PACK1,
123 TILEGX_OPC_FSINGLE_PACK2,
124 TILEGX_OPC_FSINGLE_SUB1,
125 TILEGX_OPC_ICOH,
126 TILEGX_OPC_ILL,
127 TILEGX_OPC_INV,
128 TILEGX_OPC_IRET,
129 TILEGX_OPC_J,
130 TILEGX_OPC_JAL,
131 TILEGX_OPC_JALR,
132 TILEGX_OPC_JALRP,
133 TILEGX_OPC_JR,
134 TILEGX_OPC_JRP,
135 TILEGX_OPC_LD,
136 TILEGX_OPC_LD1S,
137 TILEGX_OPC_LD1S_ADD,
138 TILEGX_OPC_LD1U,
139 TILEGX_OPC_LD1U_ADD,
140 TILEGX_OPC_LD2S,
141 TILEGX_OPC_LD2S_ADD,
142 TILEGX_OPC_LD2U,
143 TILEGX_OPC_LD2U_ADD,
144 TILEGX_OPC_LD4S,
145 TILEGX_OPC_LD4S_ADD,
146 TILEGX_OPC_LD4U,
147 TILEGX_OPC_LD4U_ADD,
148 TILEGX_OPC_LD_ADD,
149 TILEGX_OPC_LDNA,
150 TILEGX_OPC_LDNA_ADD,
151 TILEGX_OPC_LDNT,
152 TILEGX_OPC_LDNT1S,
153 TILEGX_OPC_LDNT1S_ADD,
154 TILEGX_OPC_LDNT1U,
155 TILEGX_OPC_LDNT1U_ADD,
156 TILEGX_OPC_LDNT2S,
157 TILEGX_OPC_LDNT2S_ADD,
158 TILEGX_OPC_LDNT2U,
159 TILEGX_OPC_LDNT2U_ADD,
160 TILEGX_OPC_LDNT4S,
161 TILEGX_OPC_LDNT4S_ADD,
162 TILEGX_OPC_LDNT4U,
163 TILEGX_OPC_LDNT4U_ADD,
164 TILEGX_OPC_LDNT_ADD,
165 TILEGX_OPC_LNK,
166 TILEGX_OPC_MF,
167 TILEGX_OPC_MFSPR,
168 TILEGX_OPC_MM,
169 TILEGX_OPC_MNZ,
170 TILEGX_OPC_MTSPR,
171 TILEGX_OPC_MUL_HS_HS,
172 TILEGX_OPC_MUL_HS_HU,
173 TILEGX_OPC_MUL_HS_LS,
174 TILEGX_OPC_MUL_HS_LU,
175 TILEGX_OPC_MUL_HU_HU,
176 TILEGX_OPC_MUL_HU_LS,
177 TILEGX_OPC_MUL_HU_LU,
178 TILEGX_OPC_MUL_LS_LS,
179 TILEGX_OPC_MUL_LS_LU,
180 TILEGX_OPC_MUL_LU_LU,
181 TILEGX_OPC_MULA_HS_HS,
182 TILEGX_OPC_MULA_HS_HU,
183 TILEGX_OPC_MULA_HS_LS,
184 TILEGX_OPC_MULA_HS_LU,
185 TILEGX_OPC_MULA_HU_HU,
186 TILEGX_OPC_MULA_HU_LS,
187 TILEGX_OPC_MULA_HU_LU,
188 TILEGX_OPC_MULA_LS_LS,
189 TILEGX_OPC_MULA_LS_LU,
190 TILEGX_OPC_MULA_LU_LU,
191 TILEGX_OPC_MULAX,
192 TILEGX_OPC_MULX,
193 TILEGX_OPC_MZ,
194 TILEGX_OPC_NAP,
195 TILEGX_OPC_NOP,
196 TILEGX_OPC_NOR,
197 TILEGX_OPC_OR,
198 TILEGX_OPC_ORI,
199 TILEGX_OPC_PCNT,
200 TILEGX_OPC_REVBITS,
201 TILEGX_OPC_REVBYTES,
202 TILEGX_OPC_ROTL,
203 TILEGX_OPC_ROTLI,
204 TILEGX_OPC_SHL,
205 TILEGX_OPC_SHL16INSLI,
206 TILEGX_OPC_SHL1ADD,
207 TILEGX_OPC_SHL1ADDX,
208 TILEGX_OPC_SHL2ADD,
209 TILEGX_OPC_SHL2ADDX,
210 TILEGX_OPC_SHL3ADD,
211 TILEGX_OPC_SHL3ADDX,
212 TILEGX_OPC_SHLI,
213 TILEGX_OPC_SHLX,
214 TILEGX_OPC_SHLXI,
215 TILEGX_OPC_SHRS,
216 TILEGX_OPC_SHRSI,
217 TILEGX_OPC_SHRU,
218 TILEGX_OPC_SHRUI,
219 TILEGX_OPC_SHRUX,
220 TILEGX_OPC_SHRUXI,
221 TILEGX_OPC_SHUFFLEBYTES,
222 TILEGX_OPC_ST,
223 TILEGX_OPC_ST1,
224 TILEGX_OPC_ST1_ADD,
225 TILEGX_OPC_ST2,
226 TILEGX_OPC_ST2_ADD,
227 TILEGX_OPC_ST4,
228 TILEGX_OPC_ST4_ADD,
229 TILEGX_OPC_ST_ADD,
230 TILEGX_OPC_STNT,
231 TILEGX_OPC_STNT1,
232 TILEGX_OPC_STNT1_ADD,
233 TILEGX_OPC_STNT2,
234 TILEGX_OPC_STNT2_ADD,
235 TILEGX_OPC_STNT4,
236 TILEGX_OPC_STNT4_ADD,
237 TILEGX_OPC_STNT_ADD,
238 TILEGX_OPC_SUB,
239 TILEGX_OPC_SUBX,
240 TILEGX_OPC_SUBXSC,
241 TILEGX_OPC_SWINT0,
242 TILEGX_OPC_SWINT1,
243 TILEGX_OPC_SWINT2,
244 TILEGX_OPC_SWINT3,
245 TILEGX_OPC_TBLIDXB0,
246 TILEGX_OPC_TBLIDXB1,
247 TILEGX_OPC_TBLIDXB2,
248 TILEGX_OPC_TBLIDXB3,
249 TILEGX_OPC_V1ADD,
250 TILEGX_OPC_V1ADDI,
251 TILEGX_OPC_V1ADDUC,
252 TILEGX_OPC_V1ADIFFU,
253 TILEGX_OPC_V1AVGU,
254 TILEGX_OPC_V1CMPEQ,
255 TILEGX_OPC_V1CMPEQI,
256 TILEGX_OPC_V1CMPLES,
257 TILEGX_OPC_V1CMPLEU,
258 TILEGX_OPC_V1CMPLTS,
259 TILEGX_OPC_V1CMPLTSI,
260 TILEGX_OPC_V1CMPLTU,
261 TILEGX_OPC_V1CMPLTUI,
262 TILEGX_OPC_V1CMPNE,
263 TILEGX_OPC_V1DDOTPU,
264 TILEGX_OPC_V1DDOTPUA,
265 TILEGX_OPC_V1DDOTPUS,
266 TILEGX_OPC_V1DDOTPUSA,
267 TILEGX_OPC_V1DOTP,
268 TILEGX_OPC_V1DOTPA,
269 TILEGX_OPC_V1DOTPU,
270 TILEGX_OPC_V1DOTPUA,
271 TILEGX_OPC_V1DOTPUS,
272 TILEGX_OPC_V1DOTPUSA,
273 TILEGX_OPC_V1INT_H,
274 TILEGX_OPC_V1INT_L,
275 TILEGX_OPC_V1MAXU,
276 TILEGX_OPC_V1MAXUI,
277 TILEGX_OPC_V1MINU,
278 TILEGX_OPC_V1MINUI,
279 TILEGX_OPC_V1MNZ,
280 TILEGX_OPC_V1MULTU,
281 TILEGX_OPC_V1MULU,
282 TILEGX_OPC_V1MULUS,
283 TILEGX_OPC_V1MZ,
284 TILEGX_OPC_V1SADAU,
285 TILEGX_OPC_V1SADU,
286 TILEGX_OPC_V1SHL,
287 TILEGX_OPC_V1SHLI,
288 TILEGX_OPC_V1SHRS,
289 TILEGX_OPC_V1SHRSI,
290 TILEGX_OPC_V1SHRU,
291 TILEGX_OPC_V1SHRUI,
292 TILEGX_OPC_V1SUB,
293 TILEGX_OPC_V1SUBUC,
294 TILEGX_OPC_V2ADD,
295 TILEGX_OPC_V2ADDI,
296 TILEGX_OPC_V2ADDSC,
297 TILEGX_OPC_V2ADIFFS,
298 TILEGX_OPC_V2AVGS,
299 TILEGX_OPC_V2CMPEQ,
300 TILEGX_OPC_V2CMPEQI,
301 TILEGX_OPC_V2CMPLES,
302 TILEGX_OPC_V2CMPLEU,
303 TILEGX_OPC_V2CMPLTS,
304 TILEGX_OPC_V2CMPLTSI,
305 TILEGX_OPC_V2CMPLTU,
306 TILEGX_OPC_V2CMPLTUI,
307 TILEGX_OPC_V2CMPNE,
308 TILEGX_OPC_V2DOTP,
309 TILEGX_OPC_V2DOTPA,
310 TILEGX_OPC_V2INT_H,
311 TILEGX_OPC_V2INT_L,
312 TILEGX_OPC_V2MAXS,
313 TILEGX_OPC_V2MAXSI,
314 TILEGX_OPC_V2MINS,
315 TILEGX_OPC_V2MINSI,
316 TILEGX_OPC_V2MNZ,
317 TILEGX_OPC_V2MULFSC,
318 TILEGX_OPC_V2MULS,
319 TILEGX_OPC_V2MULTS,
320 TILEGX_OPC_V2MZ,
321 TILEGX_OPC_V2PACKH,
322 TILEGX_OPC_V2PACKL,
323 TILEGX_OPC_V2PACKUC,
324 TILEGX_OPC_V2SADAS,
325 TILEGX_OPC_V2SADAU,
326 TILEGX_OPC_V2SADS,
327 TILEGX_OPC_V2SADU,
328 TILEGX_OPC_V2SHL,
329 TILEGX_OPC_V2SHLI,
330 TILEGX_OPC_V2SHLSC,
331 TILEGX_OPC_V2SHRS,
332 TILEGX_OPC_V2SHRSI,
333 TILEGX_OPC_V2SHRU,
334 TILEGX_OPC_V2SHRUI,
335 TILEGX_OPC_V2SUB,
336 TILEGX_OPC_V2SUBSC,
337 TILEGX_OPC_V4ADD,
338 TILEGX_OPC_V4ADDSC,
339 TILEGX_OPC_V4INT_H,
340 TILEGX_OPC_V4INT_L,
341 TILEGX_OPC_V4PACKSC,
342 TILEGX_OPC_V4SHL,
343 TILEGX_OPC_V4SHLSC,
344 TILEGX_OPC_V4SHRS,
345 TILEGX_OPC_V4SHRU,
346 TILEGX_OPC_V4SUB,
347 TILEGX_OPC_V4SUBSC,
348 TILEGX_OPC_WH64,
349 TILEGX_OPC_XOR,
350 TILEGX_OPC_XORI,
351 TILEGX_OPC_NONE
352} tilegx_mnemonic;
353
354/* 64-bit pattern for a { bpt ; nop } bundle. */
355#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
356
357
358#define TILE_ELF_MACHINE_CODE EM_TILE64
359
360#define TILE_ELF_NAME "elf32-tile64"
361
362
363static __inline unsigned int
364get_BFEnd_X0(tilegx_bundle_bits num)
365{
366 const unsigned int n = (unsigned int)num;
367 return (((n >> 12)) & 0x3f);
368}
369
370static __inline unsigned int
371get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
372{
373 const unsigned int n = (unsigned int)num;
374 return (((n >> 24)) & 0xf);
375}
376
377static __inline unsigned int
378get_BFStart_X0(tilegx_bundle_bits num)
379{
380 const unsigned int n = (unsigned int)num;
381 return (((n >> 18)) & 0x3f);
382}
383
384static __inline unsigned int
385get_BrOff_X1(tilegx_bundle_bits n)
386{
387 return (((unsigned int)(n >> 31)) & 0x0000003f) |
388 (((unsigned int)(n >> 37)) & 0x0001ffc0);
389}
390
391static __inline unsigned int
392get_BrType_X1(tilegx_bundle_bits n)
393{
394 return (((unsigned int)(n >> 54)) & 0x1f);
395}
396
397static __inline unsigned int
398get_Dest_Imm8_X1(tilegx_bundle_bits n)
399{
400 return (((unsigned int)(n >> 31)) & 0x0000003f) |
401 (((unsigned int)(n >> 43)) & 0x000000c0);
402}
403
404static __inline unsigned int
405get_Dest_X0(tilegx_bundle_bits num)
406{
407 const unsigned int n = (unsigned int)num;
408 return (((n >> 0)) & 0x3f);
409}
410
411static __inline unsigned int
412get_Dest_X1(tilegx_bundle_bits n)
413{
414 return (((unsigned int)(n >> 31)) & 0x3f);
415}
416
417static __inline unsigned int
418get_Dest_Y0(tilegx_bundle_bits num)
419{
420 const unsigned int n = (unsigned int)num;
421 return (((n >> 0)) & 0x3f);
422}
423
424static __inline unsigned int
425get_Dest_Y1(tilegx_bundle_bits n)
426{
427 return (((unsigned int)(n >> 31)) & 0x3f);
428}
429
430static __inline unsigned int
431get_Imm16_X0(tilegx_bundle_bits num)
432{
433 const unsigned int n = (unsigned int)num;
434 return (((n >> 12)) & 0xffff);
435}
436
437static __inline unsigned int
438get_Imm16_X1(tilegx_bundle_bits n)
439{
440 return (((unsigned int)(n >> 43)) & 0xffff);
441}
442
443static __inline unsigned int
444get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
445{
446 const unsigned int n = (unsigned int)num;
447 return (((n >> 20)) & 0xff);
448}
449
450static __inline unsigned int
451get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
452{
453 return (((unsigned int)(n >> 51)) & 0xff);
454}
455
456static __inline unsigned int
457get_Imm8_X0(tilegx_bundle_bits num)
458{
459 const unsigned int n = (unsigned int)num;
460 return (((n >> 12)) & 0xff);
461}
462
463static __inline unsigned int
464get_Imm8_X1(tilegx_bundle_bits n)
465{
466 return (((unsigned int)(n >> 43)) & 0xff);
467}
468
469static __inline unsigned int
470get_Imm8_Y0(tilegx_bundle_bits num)
471{
472 const unsigned int n = (unsigned int)num;
473 return (((n >> 12)) & 0xff);
474}
475
476static __inline unsigned int
477get_Imm8_Y1(tilegx_bundle_bits n)
478{
479 return (((unsigned int)(n >> 43)) & 0xff);
480}
481
482static __inline unsigned int
483get_JumpOff_X1(tilegx_bundle_bits n)
484{
485 return (((unsigned int)(n >> 31)) & 0x7ffffff);
486}
487
488static __inline unsigned int
489get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
490{
491 return (((unsigned int)(n >> 58)) & 0x1);
492}
493
494static __inline unsigned int
495get_MF_Imm14_X1(tilegx_bundle_bits n)
496{
497 return (((unsigned int)(n >> 37)) & 0x3fff);
498}
499
500static __inline unsigned int
501get_MT_Imm14_X1(tilegx_bundle_bits n)
502{
503 return (((unsigned int)(n >> 31)) & 0x0000003f) |
504 (((unsigned int)(n >> 37)) & 0x00003fc0);
505}
506
507static __inline unsigned int
508get_Mode(tilegx_bundle_bits n)
509{
510 return (((unsigned int)(n >> 62)) & 0x3);
511}
512
513static __inline unsigned int
514get_Opcode_X0(tilegx_bundle_bits num)
515{
516 const unsigned int n = (unsigned int)num;
517 return (((n >> 28)) & 0x7);
518}
519
520static __inline unsigned int
521get_Opcode_X1(tilegx_bundle_bits n)
522{
523 return (((unsigned int)(n >> 59)) & 0x7);
524}
525
526static __inline unsigned int
527get_Opcode_Y0(tilegx_bundle_bits num)
528{
529 const unsigned int n = (unsigned int)num;
530 return (((n >> 27)) & 0xf);
531}
532
533static __inline unsigned int
534get_Opcode_Y1(tilegx_bundle_bits n)
535{
536 return (((unsigned int)(n >> 58)) & 0xf);
537}
538
539static __inline unsigned int
540get_Opcode_Y2(tilegx_bundle_bits n)
541{
542 return (((n >> 26)) & 0x00000001) |
543 (((unsigned int)(n >> 56)) & 0x00000002);
544}
545
546static __inline unsigned int
547get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
548{
549 const unsigned int n = (unsigned int)num;
550 return (((n >> 18)) & 0x3ff);
551}
552
553static __inline unsigned int
554get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
555{
556 return (((unsigned int)(n >> 49)) & 0x3ff);
557}
558
559static __inline unsigned int
560get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
561{
562 const unsigned int n = (unsigned int)num;
563 return (((n >> 18)) & 0x3);
564}
565
566static __inline unsigned int
567get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
568{
569 return (((unsigned int)(n >> 49)) & 0x3);
570}
571
572static __inline unsigned int
573get_ShAmt_X0(tilegx_bundle_bits num)
574{
575 const unsigned int n = (unsigned int)num;
576 return (((n >> 12)) & 0x3f);
577}
578
579static __inline unsigned int
580get_ShAmt_X1(tilegx_bundle_bits n)
581{
582 return (((unsigned int)(n >> 43)) & 0x3f);
583}
584
585static __inline unsigned int
586get_ShAmt_Y0(tilegx_bundle_bits num)
587{
588 const unsigned int n = (unsigned int)num;
589 return (((n >> 12)) & 0x3f);
590}
591
592static __inline unsigned int
593get_ShAmt_Y1(tilegx_bundle_bits n)
594{
595 return (((unsigned int)(n >> 43)) & 0x3f);
596}
597
598static __inline unsigned int
599get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
600{
601 const unsigned int n = (unsigned int)num;
602 return (((n >> 18)) & 0x3ff);
603}
604
605static __inline unsigned int
606get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
607{
608 return (((unsigned int)(n >> 49)) & 0x3ff);
609}
610
611static __inline unsigned int
612get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
613{
614 const unsigned int n = (unsigned int)num;
615 return (((n >> 18)) & 0x3);
616}
617
618static __inline unsigned int
619get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
620{
621 return (((unsigned int)(n >> 49)) & 0x3);
622}
623
624static __inline unsigned int
625get_SrcA_X0(tilegx_bundle_bits num)
626{
627 const unsigned int n = (unsigned int)num;
628 return (((n >> 6)) & 0x3f);
629}
630
631static __inline unsigned int
632get_SrcA_X1(tilegx_bundle_bits n)
633{
634 return (((unsigned int)(n >> 37)) & 0x3f);
635}
636
637static __inline unsigned int
638get_SrcA_Y0(tilegx_bundle_bits num)
639{
640 const unsigned int n = (unsigned int)num;
641 return (((n >> 6)) & 0x3f);
642}
643
644static __inline unsigned int
645get_SrcA_Y1(tilegx_bundle_bits n)
646{
647 return (((unsigned int)(n >> 37)) & 0x3f);
648}
649
650static __inline unsigned int
651get_SrcA_Y2(tilegx_bundle_bits num)
652{
653 const unsigned int n = (unsigned int)num;
654 return (((n >> 20)) & 0x3f);
655}
656
657static __inline unsigned int
658get_SrcBDest_Y2(tilegx_bundle_bits n)
659{
660 return (((unsigned int)(n >> 51)) & 0x3f);
661}
662
663static __inline unsigned int
664get_SrcB_X0(tilegx_bundle_bits num)
665{
666 const unsigned int n = (unsigned int)num;
667 return (((n >> 12)) & 0x3f);
668}
669
670static __inline unsigned int
671get_SrcB_X1(tilegx_bundle_bits n)
672{
673 return (((unsigned int)(n >> 43)) & 0x3f);
674}
675
676static __inline unsigned int
677get_SrcB_Y0(tilegx_bundle_bits num)
678{
679 const unsigned int n = (unsigned int)num;
680 return (((n >> 12)) & 0x3f);
681}
682
683static __inline unsigned int
684get_SrcB_Y1(tilegx_bundle_bits n)
685{
686 return (((unsigned int)(n >> 43)) & 0x3f);
687}
688
689static __inline unsigned int
690get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
691{
692 const unsigned int n = (unsigned int)num;
693 return (((n >> 12)) & 0x3f);
694}
695
696static __inline unsigned int
697get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
698{
699 return (((unsigned int)(n >> 43)) & 0x3f);
700}
701
702static __inline unsigned int
703get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
704{
705 const unsigned int n = (unsigned int)num;
706 return (((n >> 12)) & 0x3f);
707}
708
709static __inline unsigned int
710get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
711{
712 return (((unsigned int)(n >> 43)) & 0x3f);
713}
714
715
716static __inline int
717sign_extend(int n, int num_bits)
718{
719 int shift = (int)(sizeof(int) * 8 - num_bits);
720 return (n << shift) >> shift;
721}
722
723
724
725static __inline tilegx_bundle_bits
726create_BFEnd_X0(int num)
727{
728 const unsigned int n = (unsigned int)num;
729 return ((n & 0x3f) << 12);
730}
731
732static __inline tilegx_bundle_bits
733create_BFOpcodeExtension_X0(int num)
734{
735 const unsigned int n = (unsigned int)num;
736 return ((n & 0xf) << 24);
737}
738
739static __inline tilegx_bundle_bits
740create_BFStart_X0(int num)
741{
742 const unsigned int n = (unsigned int)num;
743 return ((n & 0x3f) << 18);
744}
745
746static __inline tilegx_bundle_bits
747create_BrOff_X1(int num)
748{
749 const unsigned int n = (unsigned int)num;
750 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
751 (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
752}
753
754static __inline tilegx_bundle_bits
755create_BrType_X1(int num)
756{
757 const unsigned int n = (unsigned int)num;
758 return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
759}
760
761static __inline tilegx_bundle_bits
762create_Dest_Imm8_X1(int num)
763{
764 const unsigned int n = (unsigned int)num;
765 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
766 (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
767}
768
769static __inline tilegx_bundle_bits
770create_Dest_X0(int num)
771{
772 const unsigned int n = (unsigned int)num;
773 return ((n & 0x3f) << 0);
774}
775
776static __inline tilegx_bundle_bits
777create_Dest_X1(int num)
778{
779 const unsigned int n = (unsigned int)num;
780 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
781}
782
783static __inline tilegx_bundle_bits
784create_Dest_Y0(int num)
785{
786 const unsigned int n = (unsigned int)num;
787 return ((n & 0x3f) << 0);
788}
789
790static __inline tilegx_bundle_bits
791create_Dest_Y1(int num)
792{
793 const unsigned int n = (unsigned int)num;
794 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
795}
796
797static __inline tilegx_bundle_bits
798create_Imm16_X0(int num)
799{
800 const unsigned int n = (unsigned int)num;
801 return ((n & 0xffff) << 12);
802}
803
804static __inline tilegx_bundle_bits
805create_Imm16_X1(int num)
806{
807 const unsigned int n = (unsigned int)num;
808 return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
809}
810
811static __inline tilegx_bundle_bits
812create_Imm8OpcodeExtension_X0(int num)
813{
814 const unsigned int n = (unsigned int)num;
815 return ((n & 0xff) << 20);
816}
817
818static __inline tilegx_bundle_bits
819create_Imm8OpcodeExtension_X1(int num)
820{
821 const unsigned int n = (unsigned int)num;
822 return (((tilegx_bundle_bits)(n & 0xff)) << 51);
823}
824
825static __inline tilegx_bundle_bits
826create_Imm8_X0(int num)
827{
828 const unsigned int n = (unsigned int)num;
829 return ((n & 0xff) << 12);
830}
831
832static __inline tilegx_bundle_bits
833create_Imm8_X1(int num)
834{
835 const unsigned int n = (unsigned int)num;
836 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
837}
838
839static __inline tilegx_bundle_bits
840create_Imm8_Y0(int num)
841{
842 const unsigned int n = (unsigned int)num;
843 return ((n & 0xff) << 12);
844}
845
846static __inline tilegx_bundle_bits
847create_Imm8_Y1(int num)
848{
849 const unsigned int n = (unsigned int)num;
850 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
851}
852
853static __inline tilegx_bundle_bits
854create_JumpOff_X1(int num)
855{
856 const unsigned int n = (unsigned int)num;
857 return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
858}
859
860static __inline tilegx_bundle_bits
861create_JumpOpcodeExtension_X1(int num)
862{
863 const unsigned int n = (unsigned int)num;
864 return (((tilegx_bundle_bits)(n & 0x1)) << 58);
865}
866
867static __inline tilegx_bundle_bits
868create_MF_Imm14_X1(int num)
869{
870 const unsigned int n = (unsigned int)num;
871 return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
872}
873
874static __inline tilegx_bundle_bits
875create_MT_Imm14_X1(int num)
876{
877 const unsigned int n = (unsigned int)num;
878 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
879 (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
880}
881
882static __inline tilegx_bundle_bits
883create_Mode(int num)
884{
885 const unsigned int n = (unsigned int)num;
886 return (((tilegx_bundle_bits)(n & 0x3)) << 62);
887}
888
889static __inline tilegx_bundle_bits
890create_Opcode_X0(int num)
891{
892 const unsigned int n = (unsigned int)num;
893 return ((n & 0x7) << 28);
894}
895
896static __inline tilegx_bundle_bits
897create_Opcode_X1(int num)
898{
899 const unsigned int n = (unsigned int)num;
900 return (((tilegx_bundle_bits)(n & 0x7)) << 59);
901}
902
903static __inline tilegx_bundle_bits
904create_Opcode_Y0(int num)
905{
906 const unsigned int n = (unsigned int)num;
907 return ((n & 0xf) << 27);
908}
909
910static __inline tilegx_bundle_bits
911create_Opcode_Y1(int num)
912{
913 const unsigned int n = (unsigned int)num;
914 return (((tilegx_bundle_bits)(n & 0xf)) << 58);
915}
916
917static __inline tilegx_bundle_bits
918create_Opcode_Y2(int num)
919{
920 const unsigned int n = (unsigned int)num;
921 return ((n & 0x00000001) << 26) |
922 (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
923}
924
925static __inline tilegx_bundle_bits
926create_RRROpcodeExtension_X0(int num)
927{
928 const unsigned int n = (unsigned int)num;
929 return ((n & 0x3ff) << 18);
930}
931
932static __inline tilegx_bundle_bits
933create_RRROpcodeExtension_X1(int num)
934{
935 const unsigned int n = (unsigned int)num;
936 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
937}
938
939static __inline tilegx_bundle_bits
940create_RRROpcodeExtension_Y0(int num)
941{
942 const unsigned int n = (unsigned int)num;
943 return ((n & 0x3) << 18);
944}
945
946static __inline tilegx_bundle_bits
947create_RRROpcodeExtension_Y1(int num)
948{
949 const unsigned int n = (unsigned int)num;
950 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
951}
952
953static __inline tilegx_bundle_bits
954create_ShAmt_X0(int num)
955{
956 const unsigned int n = (unsigned int)num;
957 return ((n & 0x3f) << 12);
958}
959
960static __inline tilegx_bundle_bits
961create_ShAmt_X1(int num)
962{
963 const unsigned int n = (unsigned int)num;
964 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
965}
966
967static __inline tilegx_bundle_bits
968create_ShAmt_Y0(int num)
969{
970 const unsigned int n = (unsigned int)num;
971 return ((n & 0x3f) << 12);
972}
973
974static __inline tilegx_bundle_bits
975create_ShAmt_Y1(int num)
976{
977 const unsigned int n = (unsigned int)num;
978 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
979}
980
981static __inline tilegx_bundle_bits
982create_ShiftOpcodeExtension_X0(int num)
983{
984 const unsigned int n = (unsigned int)num;
985 return ((n & 0x3ff) << 18);
986}
987
988static __inline tilegx_bundle_bits
989create_ShiftOpcodeExtension_X1(int num)
990{
991 const unsigned int n = (unsigned int)num;
992 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
993}
994
995static __inline tilegx_bundle_bits
996create_ShiftOpcodeExtension_Y0(int num)
997{
998 const unsigned int n = (unsigned int)num;
999 return ((n & 0x3) << 18);
1000}
1001
1002static __inline tilegx_bundle_bits
1003create_ShiftOpcodeExtension_Y1(int num)
1004{
1005 const unsigned int n = (unsigned int)num;
1006 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1007}
1008
1009static __inline tilegx_bundle_bits
1010create_SrcA_X0(int num)
1011{
1012 const unsigned int n = (unsigned int)num;
1013 return ((n & 0x3f) << 6);
1014}
1015
1016static __inline tilegx_bundle_bits
1017create_SrcA_X1(int num)
1018{
1019 const unsigned int n = (unsigned int)num;
1020 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1021}
1022
1023static __inline tilegx_bundle_bits
1024create_SrcA_Y0(int num)
1025{
1026 const unsigned int n = (unsigned int)num;
1027 return ((n & 0x3f) << 6);
1028}
1029
1030static __inline tilegx_bundle_bits
1031create_SrcA_Y1(int num)
1032{
1033 const unsigned int n = (unsigned int)num;
1034 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1035}
1036
1037static __inline tilegx_bundle_bits
1038create_SrcA_Y2(int num)
1039{
1040 const unsigned int n = (unsigned int)num;
1041 return ((n & 0x3f) << 20);
1042}
1043
1044static __inline tilegx_bundle_bits
1045create_SrcBDest_Y2(int num)
1046{
1047 const unsigned int n = (unsigned int)num;
1048 return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
1049}
1050
1051static __inline tilegx_bundle_bits
1052create_SrcB_X0(int num)
1053{
1054 const unsigned int n = (unsigned int)num;
1055 return ((n & 0x3f) << 12);
1056}
1057
1058static __inline tilegx_bundle_bits
1059create_SrcB_X1(int num)
1060{
1061 const unsigned int n = (unsigned int)num;
1062 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1063}
1064
1065static __inline tilegx_bundle_bits
1066create_SrcB_Y0(int num)
1067{
1068 const unsigned int n = (unsigned int)num;
1069 return ((n & 0x3f) << 12);
1070}
1071
1072static __inline tilegx_bundle_bits
1073create_SrcB_Y1(int num)
1074{
1075 const unsigned int n = (unsigned int)num;
1076 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1077}
1078
1079static __inline tilegx_bundle_bits
1080create_UnaryOpcodeExtension_X0(int num)
1081{
1082 const unsigned int n = (unsigned int)num;
1083 return ((n & 0x3f) << 12);
1084}
1085
1086static __inline tilegx_bundle_bits
1087create_UnaryOpcodeExtension_X1(int num)
1088{
1089 const unsigned int n = (unsigned int)num;
1090 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1091}
1092
1093static __inline tilegx_bundle_bits
1094create_UnaryOpcodeExtension_Y0(int num)
1095{
1096 const unsigned int n = (unsigned int)num;
1097 return ((n & 0x3f) << 12);
1098}
1099
1100static __inline tilegx_bundle_bits
1101create_UnaryOpcodeExtension_Y1(int num)
1102{
1103 const unsigned int n = (unsigned int)num;
1104 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1105}
1106
1107
1108typedef enum
1109{
1110 TILEGX_PIPELINE_X0,
1111 TILEGX_PIPELINE_X1,
1112 TILEGX_PIPELINE_Y0,
1113 TILEGX_PIPELINE_Y1,
1114 TILEGX_PIPELINE_Y2,
1115} tilegx_pipeline;
1116
1117#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
1118
1119typedef enum
1120{
1121 TILEGX_OP_TYPE_REGISTER,
1122 TILEGX_OP_TYPE_IMMEDIATE,
1123 TILEGX_OP_TYPE_ADDRESS,
1124 TILEGX_OP_TYPE_SPR
1125} tilegx_operand_type;
1126
1127/* These are the bits that determine if a bundle is in the X encoding. */
1128#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
1129
1130enum
1131{
1132 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
1133 TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
1134
1135 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
1136 TILEGX_NUM_PIPELINE_ENCODINGS = 5,
1137
1138 /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
1139 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
1140
1141 /* Instructions take this many bytes. */
1142 TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
1143
1144 /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
1145 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
1146
1147 /* Bundles should be aligned modulo this number of bytes. */
1148 TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
1149 (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
1150
1151 /* Number of registers (some are magic, such as network I/O). */
1152 TILEGX_NUM_REGISTERS = 64,
1153};
1154
1155
1156struct tilegx_operand
1157{
1158 /* Is this operand a register, immediate or address? */
1159 tilegx_operand_type type;
1160
1161 /* The default relocation type for this operand. */
1162 signed int default_reloc : 16;
1163
1164 /* How many bits is this value? (used for range checking) */
1165 unsigned int num_bits : 5;
1166
1167 /* Is the value signed? (used for range checking) */
1168 unsigned int is_signed : 1;
1169
1170 /* Is this operand a source register? */
1171 unsigned int is_src_reg : 1;
1172
1173 /* Is this operand written? (i.e. is it a destination register) */
1174 unsigned int is_dest_reg : 1;
1175
1176 /* Is this operand PC-relative? */
1177 unsigned int is_pc_relative : 1;
1178
1179 /* By how many bits do we right shift the value before inserting? */
1180 unsigned int rightshift : 2;
1181
1182 /* Return the bits for this operand to be ORed into an existing bundle. */
1183 tilegx_bundle_bits (*insert) (int op);
1184
1185 /* Extract this operand and return it. */
1186 unsigned int (*extract) (tilegx_bundle_bits bundle);
1187};
1188
1189
1190extern const struct tilegx_operand tilegx_operands[];
1191
1192/* One finite-state machine per pipe for rapid instruction decoding. */
1193extern const unsigned short * const
1194tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
1195
1196
1197struct tilegx_opcode
1198{
1199 /* The opcode mnemonic, e.g. "add" */
1200 const char *name;
1201
1202 /* The enum value for this mnemonic. */
1203 tilegx_mnemonic mnemonic;
1204
1205 /* A bit mask of which of the five pipes this instruction
1206 is compatible with:
1207 X0 0x01
1208 X1 0x02
1209 Y0 0x04
1210 Y1 0x08
1211 Y2 0x10 */
1212 unsigned char pipes;
1213
1214 /* How many operands are there? */
1215 unsigned char num_operands;
1216
1217 /* Which register does this write implicitly, or TREG_ZERO if none? */
1218 unsigned char implicitly_written_register;
1219
1220 /* Can this be bundled with other instructions (almost always true). */
1221 unsigned char can_bundle;
1222
1223 /* The description of the operands. Each of these is an
1224 * index into the tilegx_operands[] table. */
1225 unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
1226
1227};
1228
1229extern const struct tilegx_opcode tilegx_opcodes[];
1230
1231/* Used for non-textual disassembly into structs. */
1232struct tilegx_decoded_instruction
1233{
1234 const struct tilegx_opcode *opcode;
1235 const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
1236 long long operand_values[TILEGX_MAX_OPERANDS];
1237};
1238
1239
1240/* Disassemble a bundle into a struct for machine processing. */
1241extern int parse_insn_tilegx(tilegx_bundle_bits bits,
1242 unsigned long long pc,
1243 struct tilegx_decoded_instruction
1244 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
1245
1246
1247
1248#endif /* opcode_tilegx_h */
diff --git a/arch/tile/include/asm/opcode_constants.h b/arch/tile/include/asm/opcode_constants.h
new file mode 100644
index 00000000000..37a9f2958cb
--- /dev/null
+++ b/arch/tile/include/asm/opcode_constants.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_OPCODE_CONSTANTS_H
16#define _ASM_TILE_OPCODE_CONSTANTS_H
17
18#include <arch/chip.h>
19
20#if CHIP_WORD_SIZE() == 64
21#include <asm/opcode_constants_64.h>
22#else
23#include <asm/opcode_constants_32.h>
24#endif
25
26#endif /* _ASM_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/opcode_constants_32.h b/arch/tile/include/asm/opcode_constants_32.h
new file mode 100644
index 00000000000..227d033b180
--- /dev/null
+++ b/arch/tile/include/asm/opcode_constants_32.h
@@ -0,0 +1,480 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* This file is machine-generated; DO NOT EDIT! */
16
17
18#ifndef _TILE_OPCODE_CONSTANTS_H
19#define _TILE_OPCODE_CONSTANTS_H
20enum
21{
22 ADDBS_U_SPECIAL_0_OPCODE_X0 = 98,
23 ADDBS_U_SPECIAL_0_OPCODE_X1 = 68,
24 ADDB_SPECIAL_0_OPCODE_X0 = 1,
25 ADDB_SPECIAL_0_OPCODE_X1 = 1,
26 ADDHS_SPECIAL_0_OPCODE_X0 = 99,
27 ADDHS_SPECIAL_0_OPCODE_X1 = 69,
28 ADDH_SPECIAL_0_OPCODE_X0 = 2,
29 ADDH_SPECIAL_0_OPCODE_X1 = 2,
30 ADDIB_IMM_0_OPCODE_X0 = 1,
31 ADDIB_IMM_0_OPCODE_X1 = 1,
32 ADDIH_IMM_0_OPCODE_X0 = 2,
33 ADDIH_IMM_0_OPCODE_X1 = 2,
34 ADDI_IMM_0_OPCODE_X0 = 3,
35 ADDI_IMM_0_OPCODE_X1 = 3,
36 ADDI_IMM_1_OPCODE_SN = 1,
37 ADDI_OPCODE_Y0 = 9,
38 ADDI_OPCODE_Y1 = 7,
39 ADDLIS_OPCODE_X0 = 1,
40 ADDLIS_OPCODE_X1 = 2,
41 ADDLI_OPCODE_X0 = 2,
42 ADDLI_OPCODE_X1 = 3,
43 ADDS_SPECIAL_0_OPCODE_X0 = 96,
44 ADDS_SPECIAL_0_OPCODE_X1 = 66,
45 ADD_SPECIAL_0_OPCODE_X0 = 3,
46 ADD_SPECIAL_0_OPCODE_X1 = 3,
47 ADD_SPECIAL_0_OPCODE_Y0 = 0,
48 ADD_SPECIAL_0_OPCODE_Y1 = 0,
49 ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4,
50 ADIFFH_SPECIAL_0_OPCODE_X0 = 5,
51 ANDI_IMM_0_OPCODE_X0 = 1,
52 ANDI_IMM_0_OPCODE_X1 = 4,
53 ANDI_OPCODE_Y0 = 10,
54 ANDI_OPCODE_Y1 = 8,
55 AND_SPECIAL_0_OPCODE_X0 = 6,
56 AND_SPECIAL_0_OPCODE_X1 = 4,
57 AND_SPECIAL_2_OPCODE_Y0 = 0,
58 AND_SPECIAL_2_OPCODE_Y1 = 0,
59 AULI_OPCODE_X0 = 3,
60 AULI_OPCODE_X1 = 4,
61 AVGB_U_SPECIAL_0_OPCODE_X0 = 7,
62 AVGH_SPECIAL_0_OPCODE_X0 = 8,
63 BBNST_BRANCH_OPCODE_X1 = 15,
64 BBNS_BRANCH_OPCODE_X1 = 14,
65 BBNS_OPCODE_SN = 63,
66 BBST_BRANCH_OPCODE_X1 = 13,
67 BBS_BRANCH_OPCODE_X1 = 12,
68 BBS_OPCODE_SN = 62,
69 BGEZT_BRANCH_OPCODE_X1 = 7,
70 BGEZ_BRANCH_OPCODE_X1 = 6,
71 BGEZ_OPCODE_SN = 61,
72 BGZT_BRANCH_OPCODE_X1 = 5,
73 BGZ_BRANCH_OPCODE_X1 = 4,
74 BGZ_OPCODE_SN = 58,
75 BITX_UN_0_SHUN_0_OPCODE_X0 = 1,
76 BITX_UN_0_SHUN_0_OPCODE_Y0 = 1,
77 BLEZT_BRANCH_OPCODE_X1 = 11,
78 BLEZ_BRANCH_OPCODE_X1 = 10,
79 BLEZ_OPCODE_SN = 59,
80 BLZT_BRANCH_OPCODE_X1 = 9,
81 BLZ_BRANCH_OPCODE_X1 = 8,
82 BLZ_OPCODE_SN = 60,
83 BNZT_BRANCH_OPCODE_X1 = 3,
84 BNZ_BRANCH_OPCODE_X1 = 2,
85 BNZ_OPCODE_SN = 57,
86 BPT_NOREG_RR_IMM_0_OPCODE_SN = 1,
87 BRANCH_OPCODE_X1 = 5,
88 BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2,
89 BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2,
90 BZT_BRANCH_OPCODE_X1 = 1,
91 BZ_BRANCH_OPCODE_X1 = 0,
92 BZ_OPCODE_SN = 56,
93 CLZ_UN_0_SHUN_0_OPCODE_X0 = 3,
94 CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3,
95 CRC32_32_SPECIAL_0_OPCODE_X0 = 9,
96 CRC32_8_SPECIAL_0_OPCODE_X0 = 10,
97 CTZ_UN_0_SHUN_0_OPCODE_X0 = 4,
98 CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4,
99 DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1,
100 DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2,
101 DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95,
102 FINV_UN_0_SHUN_0_OPCODE_X1 = 3,
103 FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4,
104 FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3,
105 FNOP_UN_0_SHUN_0_OPCODE_X0 = 5,
106 FNOP_UN_0_SHUN_0_OPCODE_X1 = 5,
107 FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5,
108 FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1,
109 HALT_NOREG_RR_IMM_0_OPCODE_SN = 0,
110 ICOH_UN_0_SHUN_0_OPCODE_X1 = 6,
111 ILL_UN_0_SHUN_0_OPCODE_X1 = 7,
112 ILL_UN_0_SHUN_0_OPCODE_Y1 = 2,
113 IMM_0_OPCODE_SN = 0,
114 IMM_0_OPCODE_X0 = 4,
115 IMM_0_OPCODE_X1 = 6,
116 IMM_1_OPCODE_SN = 1,
117 IMM_OPCODE_0_X0 = 5,
118 INTHB_SPECIAL_0_OPCODE_X0 = 11,
119 INTHB_SPECIAL_0_OPCODE_X1 = 5,
120 INTHH_SPECIAL_0_OPCODE_X0 = 12,
121 INTHH_SPECIAL_0_OPCODE_X1 = 6,
122 INTLB_SPECIAL_0_OPCODE_X0 = 13,
123 INTLB_SPECIAL_0_OPCODE_X1 = 7,
124 INTLH_SPECIAL_0_OPCODE_X0 = 14,
125 INTLH_SPECIAL_0_OPCODE_X1 = 8,
126 INV_UN_0_SHUN_0_OPCODE_X1 = 8,
127 IRET_UN_0_SHUN_0_OPCODE_X1 = 9,
128 JALB_OPCODE_X1 = 13,
129 JALF_OPCODE_X1 = 12,
130 JALRP_SPECIAL_0_OPCODE_X1 = 9,
131 JALRR_IMM_1_OPCODE_SN = 3,
132 JALR_RR_IMM_0_OPCODE_SN = 5,
133 JALR_SPECIAL_0_OPCODE_X1 = 10,
134 JB_OPCODE_X1 = 11,
135 JF_OPCODE_X1 = 10,
136 JRP_SPECIAL_0_OPCODE_X1 = 11,
137 JRR_IMM_1_OPCODE_SN = 2,
138 JR_RR_IMM_0_OPCODE_SN = 4,
139 JR_SPECIAL_0_OPCODE_X1 = 12,
140 LBADD_IMM_0_OPCODE_X1 = 22,
141 LBADD_U_IMM_0_OPCODE_X1 = 23,
142 LB_OPCODE_Y2 = 0,
143 LB_UN_0_SHUN_0_OPCODE_X1 = 10,
144 LB_U_OPCODE_Y2 = 1,
145 LB_U_UN_0_SHUN_0_OPCODE_X1 = 11,
146 LHADD_IMM_0_OPCODE_X1 = 24,
147 LHADD_U_IMM_0_OPCODE_X1 = 25,
148 LH_OPCODE_Y2 = 2,
149 LH_UN_0_SHUN_0_OPCODE_X1 = 12,
150 LH_U_OPCODE_Y2 = 3,
151 LH_U_UN_0_SHUN_0_OPCODE_X1 = 13,
152 LNK_SPECIAL_0_OPCODE_X1 = 13,
153 LWADD_IMM_0_OPCODE_X1 = 26,
154 LWADD_NA_IMM_0_OPCODE_X1 = 27,
155 LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24,
156 LW_OPCODE_Y2 = 4,
157 LW_UN_0_SHUN_0_OPCODE_X1 = 14,
158 MAXB_U_SPECIAL_0_OPCODE_X0 = 15,
159 MAXB_U_SPECIAL_0_OPCODE_X1 = 14,
160 MAXH_SPECIAL_0_OPCODE_X0 = 16,
161 MAXH_SPECIAL_0_OPCODE_X1 = 15,
162 MAXIB_U_IMM_0_OPCODE_X0 = 4,
163 MAXIB_U_IMM_0_OPCODE_X1 = 5,
164 MAXIH_IMM_0_OPCODE_X0 = 5,
165 MAXIH_IMM_0_OPCODE_X1 = 6,
166 MFSPR_IMM_0_OPCODE_X1 = 7,
167 MF_UN_0_SHUN_0_OPCODE_X1 = 15,
168 MINB_U_SPECIAL_0_OPCODE_X0 = 17,
169 MINB_U_SPECIAL_0_OPCODE_X1 = 16,
170 MINH_SPECIAL_0_OPCODE_X0 = 18,
171 MINH_SPECIAL_0_OPCODE_X1 = 17,
172 MINIB_U_IMM_0_OPCODE_X0 = 6,
173 MINIB_U_IMM_0_OPCODE_X1 = 8,
174 MINIH_IMM_0_OPCODE_X0 = 7,
175 MINIH_IMM_0_OPCODE_X1 = 9,
176 MM_OPCODE_X0 = 6,
177 MM_OPCODE_X1 = 7,
178 MNZB_SPECIAL_0_OPCODE_X0 = 19,
179 MNZB_SPECIAL_0_OPCODE_X1 = 18,
180 MNZH_SPECIAL_0_OPCODE_X0 = 20,
181 MNZH_SPECIAL_0_OPCODE_X1 = 19,
182 MNZ_SPECIAL_0_OPCODE_X0 = 21,
183 MNZ_SPECIAL_0_OPCODE_X1 = 20,
184 MNZ_SPECIAL_1_OPCODE_Y0 = 0,
185 MNZ_SPECIAL_1_OPCODE_Y1 = 1,
186 MOVEI_IMM_1_OPCODE_SN = 0,
187 MOVE_RR_IMM_0_OPCODE_SN = 8,
188 MTSPR_IMM_0_OPCODE_X1 = 10,
189 MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22,
190 MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0,
191 MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23,
192 MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24,
193 MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1,
194 MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25,
195 MULHH_SS_SPECIAL_0_OPCODE_X0 = 26,
196 MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0,
197 MULHH_SU_SPECIAL_0_OPCODE_X0 = 27,
198 MULHH_UU_SPECIAL_0_OPCODE_X0 = 28,
199 MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1,
200 MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29,
201 MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30,
202 MULHLA_US_SPECIAL_0_OPCODE_X0 = 31,
203 MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32,
204 MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33,
205 MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0,
206 MULHL_SS_SPECIAL_0_OPCODE_X0 = 34,
207 MULHL_SU_SPECIAL_0_OPCODE_X0 = 35,
208 MULHL_US_SPECIAL_0_OPCODE_X0 = 36,
209 MULHL_UU_SPECIAL_0_OPCODE_X0 = 37,
210 MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38,
211 MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2,
212 MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39,
213 MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40,
214 MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3,
215 MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41,
216 MULLL_SS_SPECIAL_0_OPCODE_X0 = 42,
217 MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2,
218 MULLL_SU_SPECIAL_0_OPCODE_X0 = 43,
219 MULLL_UU_SPECIAL_0_OPCODE_X0 = 44,
220 MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3,
221 MVNZ_SPECIAL_0_OPCODE_X0 = 45,
222 MVNZ_SPECIAL_1_OPCODE_Y0 = 1,
223 MVZ_SPECIAL_0_OPCODE_X0 = 46,
224 MVZ_SPECIAL_1_OPCODE_Y0 = 2,
225 MZB_SPECIAL_0_OPCODE_X0 = 47,
226 MZB_SPECIAL_0_OPCODE_X1 = 21,
227 MZH_SPECIAL_0_OPCODE_X0 = 48,
228 MZH_SPECIAL_0_OPCODE_X1 = 22,
229 MZ_SPECIAL_0_OPCODE_X0 = 49,
230 MZ_SPECIAL_0_OPCODE_X1 = 23,
231 MZ_SPECIAL_1_OPCODE_Y0 = 3,
232 MZ_SPECIAL_1_OPCODE_Y1 = 2,
233 NAP_UN_0_SHUN_0_OPCODE_X1 = 16,
234 NOP_NOREG_RR_IMM_0_OPCODE_SN = 2,
235 NOP_UN_0_SHUN_0_OPCODE_X0 = 6,
236 NOP_UN_0_SHUN_0_OPCODE_X1 = 17,
237 NOP_UN_0_SHUN_0_OPCODE_Y0 = 6,
238 NOP_UN_0_SHUN_0_OPCODE_Y1 = 3,
239 NOREG_RR_IMM_0_OPCODE_SN = 0,
240 NOR_SPECIAL_0_OPCODE_X0 = 50,
241 NOR_SPECIAL_0_OPCODE_X1 = 24,
242 NOR_SPECIAL_2_OPCODE_Y0 = 1,
243 NOR_SPECIAL_2_OPCODE_Y1 = 1,
244 ORI_IMM_0_OPCODE_X0 = 8,
245 ORI_IMM_0_OPCODE_X1 = 11,
246 ORI_OPCODE_Y0 = 11,
247 ORI_OPCODE_Y1 = 9,
248 OR_SPECIAL_0_OPCODE_X0 = 51,
249 OR_SPECIAL_0_OPCODE_X1 = 25,
250 OR_SPECIAL_2_OPCODE_Y0 = 2,
251 OR_SPECIAL_2_OPCODE_Y1 = 2,
252 PACKBS_U_SPECIAL_0_OPCODE_X0 = 103,
253 PACKBS_U_SPECIAL_0_OPCODE_X1 = 73,
254 PACKHB_SPECIAL_0_OPCODE_X0 = 52,
255 PACKHB_SPECIAL_0_OPCODE_X1 = 26,
256 PACKHS_SPECIAL_0_OPCODE_X0 = 102,
257 PACKHS_SPECIAL_0_OPCODE_X1 = 72,
258 PACKLB_SPECIAL_0_OPCODE_X0 = 53,
259 PACKLB_SPECIAL_0_OPCODE_X1 = 27,
260 PCNT_UN_0_SHUN_0_OPCODE_X0 = 7,
261 PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7,
262 RLI_SHUN_0_OPCODE_X0 = 1,
263 RLI_SHUN_0_OPCODE_X1 = 1,
264 RLI_SHUN_0_OPCODE_Y0 = 1,
265 RLI_SHUN_0_OPCODE_Y1 = 1,
266 RL_SPECIAL_0_OPCODE_X0 = 54,
267 RL_SPECIAL_0_OPCODE_X1 = 28,
268 RL_SPECIAL_3_OPCODE_Y0 = 0,
269 RL_SPECIAL_3_OPCODE_Y1 = 0,
270 RR_IMM_0_OPCODE_SN = 0,
271 S1A_SPECIAL_0_OPCODE_X0 = 55,
272 S1A_SPECIAL_0_OPCODE_X1 = 29,
273 S1A_SPECIAL_0_OPCODE_Y0 = 1,
274 S1A_SPECIAL_0_OPCODE_Y1 = 1,
275 S2A_SPECIAL_0_OPCODE_X0 = 56,
276 S2A_SPECIAL_0_OPCODE_X1 = 30,
277 S2A_SPECIAL_0_OPCODE_Y0 = 2,
278 S2A_SPECIAL_0_OPCODE_Y1 = 2,
279 S3A_SPECIAL_0_OPCODE_X0 = 57,
280 S3A_SPECIAL_0_OPCODE_X1 = 31,
281 S3A_SPECIAL_5_OPCODE_Y0 = 1,
282 S3A_SPECIAL_5_OPCODE_Y1 = 1,
283 SADAB_U_SPECIAL_0_OPCODE_X0 = 58,
284 SADAH_SPECIAL_0_OPCODE_X0 = 59,
285 SADAH_U_SPECIAL_0_OPCODE_X0 = 60,
286 SADB_U_SPECIAL_0_OPCODE_X0 = 61,
287 SADH_SPECIAL_0_OPCODE_X0 = 62,
288 SADH_U_SPECIAL_0_OPCODE_X0 = 63,
289 SBADD_IMM_0_OPCODE_X1 = 28,
290 SB_OPCODE_Y2 = 5,
291 SB_SPECIAL_0_OPCODE_X1 = 32,
292 SEQB_SPECIAL_0_OPCODE_X0 = 64,
293 SEQB_SPECIAL_0_OPCODE_X1 = 33,
294 SEQH_SPECIAL_0_OPCODE_X0 = 65,
295 SEQH_SPECIAL_0_OPCODE_X1 = 34,
296 SEQIB_IMM_0_OPCODE_X0 = 9,
297 SEQIB_IMM_0_OPCODE_X1 = 12,
298 SEQIH_IMM_0_OPCODE_X0 = 10,
299 SEQIH_IMM_0_OPCODE_X1 = 13,
300 SEQI_IMM_0_OPCODE_X0 = 11,
301 SEQI_IMM_0_OPCODE_X1 = 14,
302 SEQI_OPCODE_Y0 = 12,
303 SEQI_OPCODE_Y1 = 10,
304 SEQ_SPECIAL_0_OPCODE_X0 = 66,
305 SEQ_SPECIAL_0_OPCODE_X1 = 35,
306 SEQ_SPECIAL_5_OPCODE_Y0 = 2,
307 SEQ_SPECIAL_5_OPCODE_Y1 = 2,
308 SHADD_IMM_0_OPCODE_X1 = 29,
309 SHL8II_IMM_0_OPCODE_SN = 3,
310 SHLB_SPECIAL_0_OPCODE_X0 = 67,
311 SHLB_SPECIAL_0_OPCODE_X1 = 36,
312 SHLH_SPECIAL_0_OPCODE_X0 = 68,
313 SHLH_SPECIAL_0_OPCODE_X1 = 37,
314 SHLIB_SHUN_0_OPCODE_X0 = 2,
315 SHLIB_SHUN_0_OPCODE_X1 = 2,
316 SHLIH_SHUN_0_OPCODE_X0 = 3,
317 SHLIH_SHUN_0_OPCODE_X1 = 3,
318 SHLI_SHUN_0_OPCODE_X0 = 4,
319 SHLI_SHUN_0_OPCODE_X1 = 4,
320 SHLI_SHUN_0_OPCODE_Y0 = 2,
321 SHLI_SHUN_0_OPCODE_Y1 = 2,
322 SHL_SPECIAL_0_OPCODE_X0 = 69,
323 SHL_SPECIAL_0_OPCODE_X1 = 38,
324 SHL_SPECIAL_3_OPCODE_Y0 = 1,
325 SHL_SPECIAL_3_OPCODE_Y1 = 1,
326 SHR1_RR_IMM_0_OPCODE_SN = 9,
327 SHRB_SPECIAL_0_OPCODE_X0 = 70,
328 SHRB_SPECIAL_0_OPCODE_X1 = 39,
329 SHRH_SPECIAL_0_OPCODE_X0 = 71,
330 SHRH_SPECIAL_0_OPCODE_X1 = 40,
331 SHRIB_SHUN_0_OPCODE_X0 = 5,
332 SHRIB_SHUN_0_OPCODE_X1 = 5,
333 SHRIH_SHUN_0_OPCODE_X0 = 6,
334 SHRIH_SHUN_0_OPCODE_X1 = 6,
335 SHRI_SHUN_0_OPCODE_X0 = 7,
336 SHRI_SHUN_0_OPCODE_X1 = 7,
337 SHRI_SHUN_0_OPCODE_Y0 = 3,
338 SHRI_SHUN_0_OPCODE_Y1 = 3,
339 SHR_SPECIAL_0_OPCODE_X0 = 72,
340 SHR_SPECIAL_0_OPCODE_X1 = 41,
341 SHR_SPECIAL_3_OPCODE_Y0 = 2,
342 SHR_SPECIAL_3_OPCODE_Y1 = 2,
343 SHUN_0_OPCODE_X0 = 7,
344 SHUN_0_OPCODE_X1 = 8,
345 SHUN_0_OPCODE_Y0 = 13,
346 SHUN_0_OPCODE_Y1 = 11,
347 SH_OPCODE_Y2 = 6,
348 SH_SPECIAL_0_OPCODE_X1 = 42,
349 SLTB_SPECIAL_0_OPCODE_X0 = 73,
350 SLTB_SPECIAL_0_OPCODE_X1 = 43,
351 SLTB_U_SPECIAL_0_OPCODE_X0 = 74,
352 SLTB_U_SPECIAL_0_OPCODE_X1 = 44,
353 SLTEB_SPECIAL_0_OPCODE_X0 = 75,
354 SLTEB_SPECIAL_0_OPCODE_X1 = 45,
355 SLTEB_U_SPECIAL_0_OPCODE_X0 = 76,
356 SLTEB_U_SPECIAL_0_OPCODE_X1 = 46,
357 SLTEH_SPECIAL_0_OPCODE_X0 = 77,
358 SLTEH_SPECIAL_0_OPCODE_X1 = 47,
359 SLTEH_U_SPECIAL_0_OPCODE_X0 = 78,
360 SLTEH_U_SPECIAL_0_OPCODE_X1 = 48,
361 SLTE_SPECIAL_0_OPCODE_X0 = 79,
362 SLTE_SPECIAL_0_OPCODE_X1 = 49,
363 SLTE_SPECIAL_4_OPCODE_Y0 = 0,
364 SLTE_SPECIAL_4_OPCODE_Y1 = 0,
365 SLTE_U_SPECIAL_0_OPCODE_X0 = 80,
366 SLTE_U_SPECIAL_0_OPCODE_X1 = 50,
367 SLTE_U_SPECIAL_4_OPCODE_Y0 = 1,
368 SLTE_U_SPECIAL_4_OPCODE_Y1 = 1,
369 SLTH_SPECIAL_0_OPCODE_X0 = 81,
370 SLTH_SPECIAL_0_OPCODE_X1 = 51,
371 SLTH_U_SPECIAL_0_OPCODE_X0 = 82,
372 SLTH_U_SPECIAL_0_OPCODE_X1 = 52,
373 SLTIB_IMM_0_OPCODE_X0 = 12,
374 SLTIB_IMM_0_OPCODE_X1 = 15,
375 SLTIB_U_IMM_0_OPCODE_X0 = 13,
376 SLTIB_U_IMM_0_OPCODE_X1 = 16,
377 SLTIH_IMM_0_OPCODE_X0 = 14,
378 SLTIH_IMM_0_OPCODE_X1 = 17,
379 SLTIH_U_IMM_0_OPCODE_X0 = 15,
380 SLTIH_U_IMM_0_OPCODE_X1 = 18,
381 SLTI_IMM_0_OPCODE_X0 = 16,
382 SLTI_IMM_0_OPCODE_X1 = 19,
383 SLTI_OPCODE_Y0 = 14,
384 SLTI_OPCODE_Y1 = 12,
385 SLTI_U_IMM_0_OPCODE_X0 = 17,
386 SLTI_U_IMM_0_OPCODE_X1 = 20,
387 SLTI_U_OPCODE_Y0 = 15,
388 SLTI_U_OPCODE_Y1 = 13,
389 SLT_SPECIAL_0_OPCODE_X0 = 83,
390 SLT_SPECIAL_0_OPCODE_X1 = 53,
391 SLT_SPECIAL_4_OPCODE_Y0 = 2,
392 SLT_SPECIAL_4_OPCODE_Y1 = 2,
393 SLT_U_SPECIAL_0_OPCODE_X0 = 84,
394 SLT_U_SPECIAL_0_OPCODE_X1 = 54,
395 SLT_U_SPECIAL_4_OPCODE_Y0 = 3,
396 SLT_U_SPECIAL_4_OPCODE_Y1 = 3,
397 SNEB_SPECIAL_0_OPCODE_X0 = 85,
398 SNEB_SPECIAL_0_OPCODE_X1 = 55,
399 SNEH_SPECIAL_0_OPCODE_X0 = 86,
400 SNEH_SPECIAL_0_OPCODE_X1 = 56,
401 SNE_SPECIAL_0_OPCODE_X0 = 87,
402 SNE_SPECIAL_0_OPCODE_X1 = 57,
403 SNE_SPECIAL_5_OPCODE_Y0 = 3,
404 SNE_SPECIAL_5_OPCODE_Y1 = 3,
405 SPECIAL_0_OPCODE_X0 = 0,
406 SPECIAL_0_OPCODE_X1 = 1,
407 SPECIAL_0_OPCODE_Y0 = 1,
408 SPECIAL_0_OPCODE_Y1 = 1,
409 SPECIAL_1_OPCODE_Y0 = 2,
410 SPECIAL_1_OPCODE_Y1 = 2,
411 SPECIAL_2_OPCODE_Y0 = 3,
412 SPECIAL_2_OPCODE_Y1 = 3,
413 SPECIAL_3_OPCODE_Y0 = 4,
414 SPECIAL_3_OPCODE_Y1 = 4,
415 SPECIAL_4_OPCODE_Y0 = 5,
416 SPECIAL_4_OPCODE_Y1 = 5,
417 SPECIAL_5_OPCODE_Y0 = 6,
418 SPECIAL_5_OPCODE_Y1 = 6,
419 SPECIAL_6_OPCODE_Y0 = 7,
420 SPECIAL_7_OPCODE_Y0 = 8,
421 SRAB_SPECIAL_0_OPCODE_X0 = 88,
422 SRAB_SPECIAL_0_OPCODE_X1 = 58,
423 SRAH_SPECIAL_0_OPCODE_X0 = 89,
424 SRAH_SPECIAL_0_OPCODE_X1 = 59,
425 SRAIB_SHUN_0_OPCODE_X0 = 8,
426 SRAIB_SHUN_0_OPCODE_X1 = 8,
427 SRAIH_SHUN_0_OPCODE_X0 = 9,
428 SRAIH_SHUN_0_OPCODE_X1 = 9,
429 SRAI_SHUN_0_OPCODE_X0 = 10,
430 SRAI_SHUN_0_OPCODE_X1 = 10,
431 SRAI_SHUN_0_OPCODE_Y0 = 4,
432 SRAI_SHUN_0_OPCODE_Y1 = 4,
433 SRA_SPECIAL_0_OPCODE_X0 = 90,
434 SRA_SPECIAL_0_OPCODE_X1 = 60,
435 SRA_SPECIAL_3_OPCODE_Y0 = 3,
436 SRA_SPECIAL_3_OPCODE_Y1 = 3,
437 SUBBS_U_SPECIAL_0_OPCODE_X0 = 100,
438 SUBBS_U_SPECIAL_0_OPCODE_X1 = 70,
439 SUBB_SPECIAL_0_OPCODE_X0 = 91,
440 SUBB_SPECIAL_0_OPCODE_X1 = 61,
441 SUBHS_SPECIAL_0_OPCODE_X0 = 101,
442 SUBHS_SPECIAL_0_OPCODE_X1 = 71,
443 SUBH_SPECIAL_0_OPCODE_X0 = 92,
444 SUBH_SPECIAL_0_OPCODE_X1 = 62,
445 SUBS_SPECIAL_0_OPCODE_X0 = 97,
446 SUBS_SPECIAL_0_OPCODE_X1 = 67,
447 SUB_SPECIAL_0_OPCODE_X0 = 93,
448 SUB_SPECIAL_0_OPCODE_X1 = 63,
449 SUB_SPECIAL_0_OPCODE_Y0 = 3,
450 SUB_SPECIAL_0_OPCODE_Y1 = 3,
451 SWADD_IMM_0_OPCODE_X1 = 30,
452 SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18,
453 SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19,
454 SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20,
455 SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21,
456 SW_OPCODE_Y2 = 7,
457 SW_SPECIAL_0_OPCODE_X1 = 64,
458 TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8,
459 TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8,
460 TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9,
461 TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9,
462 TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10,
463 TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10,
464 TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11,
465 TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11,
466 TNS_UN_0_SHUN_0_OPCODE_X1 = 22,
467 UN_0_SHUN_0_OPCODE_X0 = 11,
468 UN_0_SHUN_0_OPCODE_X1 = 11,
469 UN_0_SHUN_0_OPCODE_Y0 = 5,
470 UN_0_SHUN_0_OPCODE_Y1 = 5,
471 WH64_UN_0_SHUN_0_OPCODE_X1 = 23,
472 XORI_IMM_0_OPCODE_X0 = 2,
473 XORI_IMM_0_OPCODE_X1 = 21,
474 XOR_SPECIAL_0_OPCODE_X0 = 94,
475 XOR_SPECIAL_0_OPCODE_X1 = 65,
476 XOR_SPECIAL_2_OPCODE_Y0 = 3,
477 XOR_SPECIAL_2_OPCODE_Y1 = 3
478};
479
480#endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/opcode_constants_64.h b/arch/tile/include/asm/opcode_constants_64.h
new file mode 100644
index 00000000000..71019286947
--- /dev/null
+++ b/arch/tile/include/asm/opcode_constants_64.h
@@ -0,0 +1,609 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* This file is machine-generated; DO NOT EDIT! */
16
17
18#ifndef _TILE_OPCODE_CONSTANTS_H
19#define _TILE_OPCODE_CONSTANTS_H
20enum
21{
22 ADDI_IMM8_OPCODE_X0 = 1,
23 ADDI_IMM8_OPCODE_X1 = 1,
24 ADDI_OPCODE_Y0 = 0,
25 ADDI_OPCODE_Y1 = 1,
26 ADDLI_OPCODE_X0 = 1,
27 ADDLI_OPCODE_X1 = 0,
28 ADDXI_IMM8_OPCODE_X0 = 2,
29 ADDXI_IMM8_OPCODE_X1 = 2,
30 ADDXI_OPCODE_Y0 = 1,
31 ADDXI_OPCODE_Y1 = 2,
32 ADDXLI_OPCODE_X0 = 2,
33 ADDXLI_OPCODE_X1 = 1,
34 ADDXSC_RRR_0_OPCODE_X0 = 1,
35 ADDXSC_RRR_0_OPCODE_X1 = 1,
36 ADDX_RRR_0_OPCODE_X0 = 2,
37 ADDX_RRR_0_OPCODE_X1 = 2,
38 ADDX_RRR_0_OPCODE_Y0 = 0,
39 ADDX_SPECIAL_0_OPCODE_Y1 = 0,
40 ADD_RRR_0_OPCODE_X0 = 3,
41 ADD_RRR_0_OPCODE_X1 = 3,
42 ADD_RRR_0_OPCODE_Y0 = 1,
43 ADD_SPECIAL_0_OPCODE_Y1 = 1,
44 ANDI_IMM8_OPCODE_X0 = 3,
45 ANDI_IMM8_OPCODE_X1 = 3,
46 ANDI_OPCODE_Y0 = 2,
47 ANDI_OPCODE_Y1 = 3,
48 AND_RRR_0_OPCODE_X0 = 4,
49 AND_RRR_0_OPCODE_X1 = 4,
50 AND_RRR_5_OPCODE_Y0 = 0,
51 AND_RRR_5_OPCODE_Y1 = 0,
52 BEQZT_BRANCH_OPCODE_X1 = 16,
53 BEQZ_BRANCH_OPCODE_X1 = 17,
54 BFEXTS_BF_OPCODE_X0 = 4,
55 BFEXTU_BF_OPCODE_X0 = 5,
56 BFINS_BF_OPCODE_X0 = 6,
57 BF_OPCODE_X0 = 3,
58 BGEZT_BRANCH_OPCODE_X1 = 18,
59 BGEZ_BRANCH_OPCODE_X1 = 19,
60 BGTZT_BRANCH_OPCODE_X1 = 20,
61 BGTZ_BRANCH_OPCODE_X1 = 21,
62 BLBCT_BRANCH_OPCODE_X1 = 22,
63 BLBC_BRANCH_OPCODE_X1 = 23,
64 BLBST_BRANCH_OPCODE_X1 = 24,
65 BLBS_BRANCH_OPCODE_X1 = 25,
66 BLEZT_BRANCH_OPCODE_X1 = 26,
67 BLEZ_BRANCH_OPCODE_X1 = 27,
68 BLTZT_BRANCH_OPCODE_X1 = 28,
69 BLTZ_BRANCH_OPCODE_X1 = 29,
70 BNEZT_BRANCH_OPCODE_X1 = 30,
71 BNEZ_BRANCH_OPCODE_X1 = 31,
72 BRANCH_OPCODE_X1 = 2,
73 CMOVEQZ_RRR_0_OPCODE_X0 = 5,
74 CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
75 CMOVNEZ_RRR_0_OPCODE_X0 = 6,
76 CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
77 CMPEQI_IMM8_OPCODE_X0 = 4,
78 CMPEQI_IMM8_OPCODE_X1 = 4,
79 CMPEQI_OPCODE_Y0 = 3,
80 CMPEQI_OPCODE_Y1 = 4,
81 CMPEQ_RRR_0_OPCODE_X0 = 7,
82 CMPEQ_RRR_0_OPCODE_X1 = 5,
83 CMPEQ_RRR_3_OPCODE_Y0 = 0,
84 CMPEQ_RRR_3_OPCODE_Y1 = 2,
85 CMPEXCH4_RRR_0_OPCODE_X1 = 6,
86 CMPEXCH_RRR_0_OPCODE_X1 = 7,
87 CMPLES_RRR_0_OPCODE_X0 = 8,
88 CMPLES_RRR_0_OPCODE_X1 = 8,
89 CMPLES_RRR_2_OPCODE_Y0 = 0,
90 CMPLES_RRR_2_OPCODE_Y1 = 0,
91 CMPLEU_RRR_0_OPCODE_X0 = 9,
92 CMPLEU_RRR_0_OPCODE_X1 = 9,
93 CMPLEU_RRR_2_OPCODE_Y0 = 1,
94 CMPLEU_RRR_2_OPCODE_Y1 = 1,
95 CMPLTSI_IMM8_OPCODE_X0 = 5,
96 CMPLTSI_IMM8_OPCODE_X1 = 5,
97 CMPLTSI_OPCODE_Y0 = 4,
98 CMPLTSI_OPCODE_Y1 = 5,
99 CMPLTS_RRR_0_OPCODE_X0 = 10,
100 CMPLTS_RRR_0_OPCODE_X1 = 10,
101 CMPLTS_RRR_2_OPCODE_Y0 = 2,
102 CMPLTS_RRR_2_OPCODE_Y1 = 2,
103 CMPLTUI_IMM8_OPCODE_X0 = 6,
104 CMPLTUI_IMM8_OPCODE_X1 = 6,
105 CMPLTU_RRR_0_OPCODE_X0 = 11,
106 CMPLTU_RRR_0_OPCODE_X1 = 11,
107 CMPLTU_RRR_2_OPCODE_Y0 = 3,
108 CMPLTU_RRR_2_OPCODE_Y1 = 3,
109 CMPNE_RRR_0_OPCODE_X0 = 12,
110 CMPNE_RRR_0_OPCODE_X1 = 12,
111 CMPNE_RRR_3_OPCODE_Y0 = 1,
112 CMPNE_RRR_3_OPCODE_Y1 = 3,
113 CMULAF_RRR_0_OPCODE_X0 = 13,
114 CMULA_RRR_0_OPCODE_X0 = 14,
115 CMULFR_RRR_0_OPCODE_X0 = 15,
116 CMULF_RRR_0_OPCODE_X0 = 16,
117 CMULHR_RRR_0_OPCODE_X0 = 17,
118 CMULH_RRR_0_OPCODE_X0 = 18,
119 CMUL_RRR_0_OPCODE_X0 = 19,
120 CNTLZ_UNARY_OPCODE_X0 = 1,
121 CNTLZ_UNARY_OPCODE_Y0 = 1,
122 CNTTZ_UNARY_OPCODE_X0 = 2,
123 CNTTZ_UNARY_OPCODE_Y0 = 2,
124 CRC32_32_RRR_0_OPCODE_X0 = 20,
125 CRC32_8_RRR_0_OPCODE_X0 = 21,
126 DBLALIGN2_RRR_0_OPCODE_X0 = 22,
127 DBLALIGN2_RRR_0_OPCODE_X1 = 13,
128 DBLALIGN4_RRR_0_OPCODE_X0 = 23,
129 DBLALIGN4_RRR_0_OPCODE_X1 = 14,
130 DBLALIGN6_RRR_0_OPCODE_X0 = 24,
131 DBLALIGN6_RRR_0_OPCODE_X1 = 15,
132 DBLALIGN_RRR_0_OPCODE_X0 = 25,
133 DRAIN_UNARY_OPCODE_X1 = 1,
134 DTLBPR_UNARY_OPCODE_X1 = 2,
135 EXCH4_RRR_0_OPCODE_X1 = 16,
136 EXCH_RRR_0_OPCODE_X1 = 17,
137 FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
138 FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
139 FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
140 FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
141 FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
142 FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
143 FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
144 FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
145 FETCHADD4_RRR_0_OPCODE_X1 = 18,
146 FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
147 FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
148 FETCHADD_RRR_0_OPCODE_X1 = 21,
149 FETCHAND4_RRR_0_OPCODE_X1 = 22,
150 FETCHAND_RRR_0_OPCODE_X1 = 23,
151 FETCHOR4_RRR_0_OPCODE_X1 = 24,
152 FETCHOR_RRR_0_OPCODE_X1 = 25,
153 FINV_UNARY_OPCODE_X1 = 3,
154 FLUSHWB_UNARY_OPCODE_X1 = 4,
155 FLUSH_UNARY_OPCODE_X1 = 5,
156 FNOP_UNARY_OPCODE_X0 = 3,
157 FNOP_UNARY_OPCODE_X1 = 6,
158 FNOP_UNARY_OPCODE_Y0 = 3,
159 FNOP_UNARY_OPCODE_Y1 = 8,
160 FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
161 FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
162 FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
163 FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
164 FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
165 FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
166 FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
167 FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
168 ICOH_UNARY_OPCODE_X1 = 7,
169 ILL_UNARY_OPCODE_X1 = 8,
170 ILL_UNARY_OPCODE_Y1 = 9,
171 IMM8_OPCODE_X0 = 4,
172 IMM8_OPCODE_X1 = 3,
173 INV_UNARY_OPCODE_X1 = 9,
174 IRET_UNARY_OPCODE_X1 = 10,
175 JALRP_UNARY_OPCODE_X1 = 11,
176 JALRP_UNARY_OPCODE_Y1 = 10,
177 JALR_UNARY_OPCODE_X1 = 12,
178 JALR_UNARY_OPCODE_Y1 = 11,
179 JAL_JUMP_OPCODE_X1 = 0,
180 JRP_UNARY_OPCODE_X1 = 13,
181 JRP_UNARY_OPCODE_Y1 = 12,
182 JR_UNARY_OPCODE_X1 = 14,
183 JR_UNARY_OPCODE_Y1 = 13,
184 JUMP_OPCODE_X1 = 4,
185 J_JUMP_OPCODE_X1 = 1,
186 LD1S_ADD_IMM8_OPCODE_X1 = 7,
187 LD1S_OPCODE_Y2 = 0,
188 LD1S_UNARY_OPCODE_X1 = 15,
189 LD1U_ADD_IMM8_OPCODE_X1 = 8,
190 LD1U_OPCODE_Y2 = 1,
191 LD1U_UNARY_OPCODE_X1 = 16,
192 LD2S_ADD_IMM8_OPCODE_X1 = 9,
193 LD2S_OPCODE_Y2 = 2,
194 LD2S_UNARY_OPCODE_X1 = 17,
195 LD2U_ADD_IMM8_OPCODE_X1 = 10,
196 LD2U_OPCODE_Y2 = 3,
197 LD2U_UNARY_OPCODE_X1 = 18,
198 LD4S_ADD_IMM8_OPCODE_X1 = 11,
199 LD4S_OPCODE_Y2 = 1,
200 LD4S_UNARY_OPCODE_X1 = 19,
201 LD4U_ADD_IMM8_OPCODE_X1 = 12,
202 LD4U_OPCODE_Y2 = 2,
203 LD4U_UNARY_OPCODE_X1 = 20,
204 LDNA_UNARY_OPCODE_X1 = 21,
205 LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
206 LDNT1S_UNARY_OPCODE_X1 = 22,
207 LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
208 LDNT1U_UNARY_OPCODE_X1 = 23,
209 LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
210 LDNT2S_UNARY_OPCODE_X1 = 24,
211 LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
212 LDNT2U_UNARY_OPCODE_X1 = 25,
213 LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
214 LDNT4S_UNARY_OPCODE_X1 = 26,
215 LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
216 LDNT4U_UNARY_OPCODE_X1 = 27,
217 LDNT_ADD_IMM8_OPCODE_X1 = 19,
218 LDNT_UNARY_OPCODE_X1 = 28,
219 LD_ADD_IMM8_OPCODE_X1 = 20,
220 LD_OPCODE_Y2 = 3,
221 LD_UNARY_OPCODE_X1 = 29,
222 LNK_UNARY_OPCODE_X1 = 30,
223 LNK_UNARY_OPCODE_Y1 = 14,
224 LWNA_ADD_IMM8_OPCODE_X1 = 21,
225 MFSPR_IMM8_OPCODE_X1 = 22,
226 MF_UNARY_OPCODE_X1 = 31,
227 MM_BF_OPCODE_X0 = 7,
228 MNZ_RRR_0_OPCODE_X0 = 40,
229 MNZ_RRR_0_OPCODE_X1 = 26,
230 MNZ_RRR_4_OPCODE_Y0 = 2,
231 MNZ_RRR_4_OPCODE_Y1 = 2,
232 MODE_OPCODE_YA2 = 1,
233 MODE_OPCODE_YB2 = 2,
234 MODE_OPCODE_YC2 = 3,
235 MTSPR_IMM8_OPCODE_X1 = 23,
236 MULAX_RRR_0_OPCODE_X0 = 41,
237 MULAX_RRR_3_OPCODE_Y0 = 2,
238 MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
239 MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
240 MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
241 MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
242 MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
243 MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
244 MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
245 MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
246 MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
247 MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
248 MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
249 MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
250 MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
251 MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
252 MULX_RRR_0_OPCODE_X0 = 52,
253 MULX_RRR_3_OPCODE_Y0 = 3,
254 MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
255 MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
256 MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
257 MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
258 MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
259 MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
260 MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
261 MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
262 MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
263 MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
264 MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
265 MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
266 MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
267 MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
268 MZ_RRR_0_OPCODE_X0 = 63,
269 MZ_RRR_0_OPCODE_X1 = 27,
270 MZ_RRR_4_OPCODE_Y0 = 3,
271 MZ_RRR_4_OPCODE_Y1 = 3,
272 NAP_UNARY_OPCODE_X1 = 32,
273 NOP_UNARY_OPCODE_X0 = 5,
274 NOP_UNARY_OPCODE_X1 = 33,
275 NOP_UNARY_OPCODE_Y0 = 5,
276 NOP_UNARY_OPCODE_Y1 = 15,
277 NOR_RRR_0_OPCODE_X0 = 64,
278 NOR_RRR_0_OPCODE_X1 = 28,
279 NOR_RRR_5_OPCODE_Y0 = 1,
280 NOR_RRR_5_OPCODE_Y1 = 1,
281 ORI_IMM8_OPCODE_X0 = 7,
282 ORI_IMM8_OPCODE_X1 = 24,
283 OR_RRR_0_OPCODE_X0 = 65,
284 OR_RRR_0_OPCODE_X1 = 29,
285 OR_RRR_5_OPCODE_Y0 = 2,
286 OR_RRR_5_OPCODE_Y1 = 2,
287 PCNT_UNARY_OPCODE_X0 = 6,
288 PCNT_UNARY_OPCODE_Y0 = 6,
289 REVBITS_UNARY_OPCODE_X0 = 7,
290 REVBITS_UNARY_OPCODE_Y0 = 7,
291 REVBYTES_UNARY_OPCODE_X0 = 8,
292 REVBYTES_UNARY_OPCODE_Y0 = 8,
293 ROTLI_SHIFT_OPCODE_X0 = 1,
294 ROTLI_SHIFT_OPCODE_X1 = 1,
295 ROTLI_SHIFT_OPCODE_Y0 = 0,
296 ROTLI_SHIFT_OPCODE_Y1 = 0,
297 ROTL_RRR_0_OPCODE_X0 = 66,
298 ROTL_RRR_0_OPCODE_X1 = 30,
299 ROTL_RRR_6_OPCODE_Y0 = 0,
300 ROTL_RRR_6_OPCODE_Y1 = 0,
301 RRR_0_OPCODE_X0 = 5,
302 RRR_0_OPCODE_X1 = 5,
303 RRR_0_OPCODE_Y0 = 5,
304 RRR_0_OPCODE_Y1 = 6,
305 RRR_1_OPCODE_Y0 = 6,
306 RRR_1_OPCODE_Y1 = 7,
307 RRR_2_OPCODE_Y0 = 7,
308 RRR_2_OPCODE_Y1 = 8,
309 RRR_3_OPCODE_Y0 = 8,
310 RRR_3_OPCODE_Y1 = 9,
311 RRR_4_OPCODE_Y0 = 9,
312 RRR_4_OPCODE_Y1 = 10,
313 RRR_5_OPCODE_Y0 = 10,
314 RRR_5_OPCODE_Y1 = 11,
315 RRR_6_OPCODE_Y0 = 11,
316 RRR_6_OPCODE_Y1 = 12,
317 RRR_7_OPCODE_Y0 = 12,
318 RRR_7_OPCODE_Y1 = 13,
319 RRR_8_OPCODE_Y0 = 13,
320 RRR_9_OPCODE_Y0 = 14,
321 SHIFT_OPCODE_X0 = 6,
322 SHIFT_OPCODE_X1 = 6,
323 SHIFT_OPCODE_Y0 = 15,
324 SHIFT_OPCODE_Y1 = 14,
325 SHL16INSLI_OPCODE_X0 = 7,
326 SHL16INSLI_OPCODE_X1 = 7,
327 SHL1ADDX_RRR_0_OPCODE_X0 = 67,
328 SHL1ADDX_RRR_0_OPCODE_X1 = 31,
329 SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
330 SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
331 SHL1ADD_RRR_0_OPCODE_X0 = 68,
332 SHL1ADD_RRR_0_OPCODE_X1 = 32,
333 SHL1ADD_RRR_1_OPCODE_Y0 = 0,
334 SHL1ADD_RRR_1_OPCODE_Y1 = 0,
335 SHL2ADDX_RRR_0_OPCODE_X0 = 69,
336 SHL2ADDX_RRR_0_OPCODE_X1 = 33,
337 SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
338 SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
339 SHL2ADD_RRR_0_OPCODE_X0 = 70,
340 SHL2ADD_RRR_0_OPCODE_X1 = 34,
341 SHL2ADD_RRR_1_OPCODE_Y0 = 1,
342 SHL2ADD_RRR_1_OPCODE_Y1 = 1,
343 SHL3ADDX_RRR_0_OPCODE_X0 = 71,
344 SHL3ADDX_RRR_0_OPCODE_X1 = 35,
345 SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
346 SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
347 SHL3ADD_RRR_0_OPCODE_X0 = 72,
348 SHL3ADD_RRR_0_OPCODE_X1 = 36,
349 SHL3ADD_RRR_1_OPCODE_Y0 = 2,
350 SHL3ADD_RRR_1_OPCODE_Y1 = 2,
351 SHLI_SHIFT_OPCODE_X0 = 2,
352 SHLI_SHIFT_OPCODE_X1 = 2,
353 SHLI_SHIFT_OPCODE_Y0 = 1,
354 SHLI_SHIFT_OPCODE_Y1 = 1,
355 SHLXI_SHIFT_OPCODE_X0 = 3,
356 SHLXI_SHIFT_OPCODE_X1 = 3,
357 SHLX_RRR_0_OPCODE_X0 = 73,
358 SHLX_RRR_0_OPCODE_X1 = 37,
359 SHL_RRR_0_OPCODE_X0 = 74,
360 SHL_RRR_0_OPCODE_X1 = 38,
361 SHL_RRR_6_OPCODE_Y0 = 1,
362 SHL_RRR_6_OPCODE_Y1 = 1,
363 SHRSI_SHIFT_OPCODE_X0 = 4,
364 SHRSI_SHIFT_OPCODE_X1 = 4,
365 SHRSI_SHIFT_OPCODE_Y0 = 2,
366 SHRSI_SHIFT_OPCODE_Y1 = 2,
367 SHRS_RRR_0_OPCODE_X0 = 75,
368 SHRS_RRR_0_OPCODE_X1 = 39,
369 SHRS_RRR_6_OPCODE_Y0 = 2,
370 SHRS_RRR_6_OPCODE_Y1 = 2,
371 SHRUI_SHIFT_OPCODE_X0 = 5,
372 SHRUI_SHIFT_OPCODE_X1 = 5,
373 SHRUI_SHIFT_OPCODE_Y0 = 3,
374 SHRUI_SHIFT_OPCODE_Y1 = 3,
375 SHRUXI_SHIFT_OPCODE_X0 = 6,
376 SHRUXI_SHIFT_OPCODE_X1 = 6,
377 SHRUX_RRR_0_OPCODE_X0 = 76,
378 SHRUX_RRR_0_OPCODE_X1 = 40,
379 SHRU_RRR_0_OPCODE_X0 = 77,
380 SHRU_RRR_0_OPCODE_X1 = 41,
381 SHRU_RRR_6_OPCODE_Y0 = 3,
382 SHRU_RRR_6_OPCODE_Y1 = 3,
383 SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
384 ST1_ADD_IMM8_OPCODE_X1 = 25,
385 ST1_OPCODE_Y2 = 0,
386 ST1_RRR_0_OPCODE_X1 = 42,
387 ST2_ADD_IMM8_OPCODE_X1 = 26,
388 ST2_OPCODE_Y2 = 1,
389 ST2_RRR_0_OPCODE_X1 = 43,
390 ST4_ADD_IMM8_OPCODE_X1 = 27,
391 ST4_OPCODE_Y2 = 2,
392 ST4_RRR_0_OPCODE_X1 = 44,
393 STNT1_ADD_IMM8_OPCODE_X1 = 28,
394 STNT1_RRR_0_OPCODE_X1 = 45,
395 STNT2_ADD_IMM8_OPCODE_X1 = 29,
396 STNT2_RRR_0_OPCODE_X1 = 46,
397 STNT4_ADD_IMM8_OPCODE_X1 = 30,
398 STNT4_RRR_0_OPCODE_X1 = 47,
399 STNT_ADD_IMM8_OPCODE_X1 = 31,
400 STNT_RRR_0_OPCODE_X1 = 48,
401 ST_ADD_IMM8_OPCODE_X1 = 32,
402 ST_OPCODE_Y2 = 3,
403 ST_RRR_0_OPCODE_X1 = 49,
404 SUBXSC_RRR_0_OPCODE_X0 = 79,
405 SUBXSC_RRR_0_OPCODE_X1 = 50,
406 SUBX_RRR_0_OPCODE_X0 = 80,
407 SUBX_RRR_0_OPCODE_X1 = 51,
408 SUBX_RRR_0_OPCODE_Y0 = 2,
409 SUBX_RRR_0_OPCODE_Y1 = 2,
410 SUB_RRR_0_OPCODE_X0 = 81,
411 SUB_RRR_0_OPCODE_X1 = 52,
412 SUB_RRR_0_OPCODE_Y0 = 3,
413 SUB_RRR_0_OPCODE_Y1 = 3,
414 SWINT0_UNARY_OPCODE_X1 = 34,
415 SWINT1_UNARY_OPCODE_X1 = 35,
416 SWINT2_UNARY_OPCODE_X1 = 36,
417 SWINT3_UNARY_OPCODE_X1 = 37,
418 TBLIDXB0_UNARY_OPCODE_X0 = 9,
419 TBLIDXB0_UNARY_OPCODE_Y0 = 9,
420 TBLIDXB1_UNARY_OPCODE_X0 = 10,
421 TBLIDXB1_UNARY_OPCODE_Y0 = 10,
422 TBLIDXB2_UNARY_OPCODE_X0 = 11,
423 TBLIDXB2_UNARY_OPCODE_Y0 = 11,
424 TBLIDXB3_UNARY_OPCODE_X0 = 12,
425 TBLIDXB3_UNARY_OPCODE_Y0 = 12,
426 UNARY_RRR_0_OPCODE_X0 = 82,
427 UNARY_RRR_0_OPCODE_X1 = 53,
428 UNARY_RRR_1_OPCODE_Y0 = 3,
429 UNARY_RRR_1_OPCODE_Y1 = 3,
430 V1ADDI_IMM8_OPCODE_X0 = 8,
431 V1ADDI_IMM8_OPCODE_X1 = 33,
432 V1ADDUC_RRR_0_OPCODE_X0 = 83,
433 V1ADDUC_RRR_0_OPCODE_X1 = 54,
434 V1ADD_RRR_0_OPCODE_X0 = 84,
435 V1ADD_RRR_0_OPCODE_X1 = 55,
436 V1ADIFFU_RRR_0_OPCODE_X0 = 85,
437 V1AVGU_RRR_0_OPCODE_X0 = 86,
438 V1CMPEQI_IMM8_OPCODE_X0 = 9,
439 V1CMPEQI_IMM8_OPCODE_X1 = 34,
440 V1CMPEQ_RRR_0_OPCODE_X0 = 87,
441 V1CMPEQ_RRR_0_OPCODE_X1 = 56,
442 V1CMPLES_RRR_0_OPCODE_X0 = 88,
443 V1CMPLES_RRR_0_OPCODE_X1 = 57,
444 V1CMPLEU_RRR_0_OPCODE_X0 = 89,
445 V1CMPLEU_RRR_0_OPCODE_X1 = 58,
446 V1CMPLTSI_IMM8_OPCODE_X0 = 10,
447 V1CMPLTSI_IMM8_OPCODE_X1 = 35,
448 V1CMPLTS_RRR_0_OPCODE_X0 = 90,
449 V1CMPLTS_RRR_0_OPCODE_X1 = 59,
450 V1CMPLTUI_IMM8_OPCODE_X0 = 11,
451 V1CMPLTUI_IMM8_OPCODE_X1 = 36,
452 V1CMPLTU_RRR_0_OPCODE_X0 = 91,
453 V1CMPLTU_RRR_0_OPCODE_X1 = 60,
454 V1CMPNE_RRR_0_OPCODE_X0 = 92,
455 V1CMPNE_RRR_0_OPCODE_X1 = 61,
456 V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
457 V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
458 V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
459 V1DDOTPU_RRR_0_OPCODE_X0 = 162,
460 V1DOTPA_RRR_0_OPCODE_X0 = 95,
461 V1DOTPUA_RRR_0_OPCODE_X0 = 163,
462 V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
463 V1DOTPUS_RRR_0_OPCODE_X0 = 97,
464 V1DOTPU_RRR_0_OPCODE_X0 = 164,
465 V1DOTP_RRR_0_OPCODE_X0 = 98,
466 V1INT_H_RRR_0_OPCODE_X0 = 99,
467 V1INT_H_RRR_0_OPCODE_X1 = 62,
468 V1INT_L_RRR_0_OPCODE_X0 = 100,
469 V1INT_L_RRR_0_OPCODE_X1 = 63,
470 V1MAXUI_IMM8_OPCODE_X0 = 12,
471 V1MAXUI_IMM8_OPCODE_X1 = 37,
472 V1MAXU_RRR_0_OPCODE_X0 = 101,
473 V1MAXU_RRR_0_OPCODE_X1 = 64,
474 V1MINUI_IMM8_OPCODE_X0 = 13,
475 V1MINUI_IMM8_OPCODE_X1 = 38,
476 V1MINU_RRR_0_OPCODE_X0 = 102,
477 V1MINU_RRR_0_OPCODE_X1 = 65,
478 V1MNZ_RRR_0_OPCODE_X0 = 103,
479 V1MNZ_RRR_0_OPCODE_X1 = 66,
480 V1MULTU_RRR_0_OPCODE_X0 = 104,
481 V1MULUS_RRR_0_OPCODE_X0 = 105,
482 V1MULU_RRR_0_OPCODE_X0 = 106,
483 V1MZ_RRR_0_OPCODE_X0 = 107,
484 V1MZ_RRR_0_OPCODE_X1 = 67,
485 V1SADAU_RRR_0_OPCODE_X0 = 108,
486 V1SADU_RRR_0_OPCODE_X0 = 109,
487 V1SHLI_SHIFT_OPCODE_X0 = 7,
488 V1SHLI_SHIFT_OPCODE_X1 = 7,
489 V1SHL_RRR_0_OPCODE_X0 = 110,
490 V1SHL_RRR_0_OPCODE_X1 = 68,
491 V1SHRSI_SHIFT_OPCODE_X0 = 8,
492 V1SHRSI_SHIFT_OPCODE_X1 = 8,
493 V1SHRS_RRR_0_OPCODE_X0 = 111,
494 V1SHRS_RRR_0_OPCODE_X1 = 69,
495 V1SHRUI_SHIFT_OPCODE_X0 = 9,
496 V1SHRUI_SHIFT_OPCODE_X1 = 9,
497 V1SHRU_RRR_0_OPCODE_X0 = 112,
498 V1SHRU_RRR_0_OPCODE_X1 = 70,
499 V1SUBUC_RRR_0_OPCODE_X0 = 113,
500 V1SUBUC_RRR_0_OPCODE_X1 = 71,
501 V1SUB_RRR_0_OPCODE_X0 = 114,
502 V1SUB_RRR_0_OPCODE_X1 = 72,
503 V2ADDI_IMM8_OPCODE_X0 = 14,
504 V2ADDI_IMM8_OPCODE_X1 = 39,
505 V2ADDSC_RRR_0_OPCODE_X0 = 115,
506 V2ADDSC_RRR_0_OPCODE_X1 = 73,
507 V2ADD_RRR_0_OPCODE_X0 = 116,
508 V2ADD_RRR_0_OPCODE_X1 = 74,
509 V2ADIFFS_RRR_0_OPCODE_X0 = 117,
510 V2AVGS_RRR_0_OPCODE_X0 = 118,
511 V2CMPEQI_IMM8_OPCODE_X0 = 15,
512 V2CMPEQI_IMM8_OPCODE_X1 = 40,
513 V2CMPEQ_RRR_0_OPCODE_X0 = 119,
514 V2CMPEQ_RRR_0_OPCODE_X1 = 75,
515 V2CMPLES_RRR_0_OPCODE_X0 = 120,
516 V2CMPLES_RRR_0_OPCODE_X1 = 76,
517 V2CMPLEU_RRR_0_OPCODE_X0 = 121,
518 V2CMPLEU_RRR_0_OPCODE_X1 = 77,
519 V2CMPLTSI_IMM8_OPCODE_X0 = 16,
520 V2CMPLTSI_IMM8_OPCODE_X1 = 41,
521 V2CMPLTS_RRR_0_OPCODE_X0 = 122,
522 V2CMPLTS_RRR_0_OPCODE_X1 = 78,
523 V2CMPLTUI_IMM8_OPCODE_X0 = 17,
524 V2CMPLTUI_IMM8_OPCODE_X1 = 42,
525 V2CMPLTU_RRR_0_OPCODE_X0 = 123,
526 V2CMPLTU_RRR_0_OPCODE_X1 = 79,
527 V2CMPNE_RRR_0_OPCODE_X0 = 124,
528 V2CMPNE_RRR_0_OPCODE_X1 = 80,
529 V2DOTPA_RRR_0_OPCODE_X0 = 125,
530 V2DOTP_RRR_0_OPCODE_X0 = 126,
531 V2INT_H_RRR_0_OPCODE_X0 = 127,
532 V2INT_H_RRR_0_OPCODE_X1 = 81,
533 V2INT_L_RRR_0_OPCODE_X0 = 128,
534 V2INT_L_RRR_0_OPCODE_X1 = 82,
535 V2MAXSI_IMM8_OPCODE_X0 = 18,
536 V2MAXSI_IMM8_OPCODE_X1 = 43,
537 V2MAXS_RRR_0_OPCODE_X0 = 129,
538 V2MAXS_RRR_0_OPCODE_X1 = 83,
539 V2MINSI_IMM8_OPCODE_X0 = 19,
540 V2MINSI_IMM8_OPCODE_X1 = 44,
541 V2MINS_RRR_0_OPCODE_X0 = 130,
542 V2MINS_RRR_0_OPCODE_X1 = 84,
543 V2MNZ_RRR_0_OPCODE_X0 = 131,
544 V2MNZ_RRR_0_OPCODE_X1 = 85,
545 V2MULFSC_RRR_0_OPCODE_X0 = 132,
546 V2MULS_RRR_0_OPCODE_X0 = 133,
547 V2MULTS_RRR_0_OPCODE_X0 = 134,
548 V2MZ_RRR_0_OPCODE_X0 = 135,
549 V2MZ_RRR_0_OPCODE_X1 = 86,
550 V2PACKH_RRR_0_OPCODE_X0 = 136,
551 V2PACKH_RRR_0_OPCODE_X1 = 87,
552 V2PACKL_RRR_0_OPCODE_X0 = 137,
553 V2PACKL_RRR_0_OPCODE_X1 = 88,
554 V2PACKUC_RRR_0_OPCODE_X0 = 138,
555 V2PACKUC_RRR_0_OPCODE_X1 = 89,
556 V2SADAS_RRR_0_OPCODE_X0 = 139,
557 V2SADAU_RRR_0_OPCODE_X0 = 140,
558 V2SADS_RRR_0_OPCODE_X0 = 141,
559 V2SADU_RRR_0_OPCODE_X0 = 142,
560 V2SHLI_SHIFT_OPCODE_X0 = 10,
561 V2SHLI_SHIFT_OPCODE_X1 = 10,
562 V2SHLSC_RRR_0_OPCODE_X0 = 143,
563 V2SHLSC_RRR_0_OPCODE_X1 = 90,
564 V2SHL_RRR_0_OPCODE_X0 = 144,
565 V2SHL_RRR_0_OPCODE_X1 = 91,
566 V2SHRSI_SHIFT_OPCODE_X0 = 11,
567 V2SHRSI_SHIFT_OPCODE_X1 = 11,
568 V2SHRS_RRR_0_OPCODE_X0 = 145,
569 V2SHRS_RRR_0_OPCODE_X1 = 92,
570 V2SHRUI_SHIFT_OPCODE_X0 = 12,
571 V2SHRUI_SHIFT_OPCODE_X1 = 12,
572 V2SHRU_RRR_0_OPCODE_X0 = 146,
573 V2SHRU_RRR_0_OPCODE_X1 = 93,
574 V2SUBSC_RRR_0_OPCODE_X0 = 147,
575 V2SUBSC_RRR_0_OPCODE_X1 = 94,
576 V2SUB_RRR_0_OPCODE_X0 = 148,
577 V2SUB_RRR_0_OPCODE_X1 = 95,
578 V4ADDSC_RRR_0_OPCODE_X0 = 149,
579 V4ADDSC_RRR_0_OPCODE_X1 = 96,
580 V4ADD_RRR_0_OPCODE_X0 = 150,
581 V4ADD_RRR_0_OPCODE_X1 = 97,
582 V4INT_H_RRR_0_OPCODE_X0 = 151,
583 V4INT_H_RRR_0_OPCODE_X1 = 98,
584 V4INT_L_RRR_0_OPCODE_X0 = 152,
585 V4INT_L_RRR_0_OPCODE_X1 = 99,
586 V4PACKSC_RRR_0_OPCODE_X0 = 153,
587 V4PACKSC_RRR_0_OPCODE_X1 = 100,
588 V4SHLSC_RRR_0_OPCODE_X0 = 154,
589 V4SHLSC_RRR_0_OPCODE_X1 = 101,
590 V4SHL_RRR_0_OPCODE_X0 = 155,
591 V4SHL_RRR_0_OPCODE_X1 = 102,
592 V4SHRS_RRR_0_OPCODE_X0 = 156,
593 V4SHRS_RRR_0_OPCODE_X1 = 103,
594 V4SHRU_RRR_0_OPCODE_X0 = 157,
595 V4SHRU_RRR_0_OPCODE_X1 = 104,
596 V4SUBSC_RRR_0_OPCODE_X0 = 158,
597 V4SUBSC_RRR_0_OPCODE_X1 = 105,
598 V4SUB_RRR_0_OPCODE_X0 = 159,
599 V4SUB_RRR_0_OPCODE_X1 = 106,
600 WH64_UNARY_OPCODE_X1 = 38,
601 XORI_IMM8_OPCODE_X0 = 20,
602 XORI_IMM8_OPCODE_X1 = 45,
603 XOR_RRR_0_OPCODE_X0 = 160,
604 XOR_RRR_0_OPCODE_X1 = 107,
605 XOR_RRR_5_OPCODE_Y0 = 3,
606 XOR_RRR_5_OPCODE_Y1 = 3
607};
608
609#endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/sigcontext.h b/arch/tile/include/asm/sigcontext.h
new file mode 100644
index 00000000000..5e2d03336f5
--- /dev/null
+++ b/arch/tile/include/asm/sigcontext.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SIGCONTEXT_H
16#define _ASM_TILE_SIGCONTEXT_H
17
18#include <arch/abi.h>
19
20/*
21 * struct sigcontext has the same shape as struct pt_regs,
22 * but is simplified since we know the fault is from userspace.
23 */
24struct sigcontext {
25 uint_reg_t gregs[53]; /* General-purpose registers. */
26 uint_reg_t tp; /* Aliases gregs[TREG_TP]. */
27 uint_reg_t sp; /* Aliases gregs[TREG_SP]. */
28 uint_reg_t lr; /* Aliases gregs[TREG_LR]. */
29 uint_reg_t pc; /* Program counter. */
30 uint_reg_t ics; /* In Interrupt Critical Section? */
31 uint_reg_t faultnum; /* Fault number. */
32 uint_reg_t pad[5];
33};
34
35#endif /* _ASM_TILE_SIGCONTEXT_H */
diff --git a/arch/tile/include/asm/siginfo.h b/arch/tile/include/asm/siginfo.h
new file mode 100644
index 00000000000..56d661bb010
--- /dev/null
+++ b/arch/tile/include/asm/siginfo.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SIGINFO_H
16#define _ASM_TILE_SIGINFO_H
17
18#define __ARCH_SI_TRAPNO
19
20#ifdef __LP64__
21# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
22#endif
23
24#include <asm-generic/siginfo.h>
25
26/*
27 * Additional Tile-specific SIGILL si_codes
28 */
29#define ILL_DBLFLT (__SI_FAULT|9) /* double fault */
30#define ILL_HARDWALL (__SI_FAULT|10) /* user networks hardwall violation */
31#undef NSIGILL
32#define NSIGILL 10
33
34#endif /* _ASM_TILE_SIGINFO_H */
diff --git a/arch/tile/include/asm/stat.h b/arch/tile/include/asm/stat.h
new file mode 100644
index 00000000000..c0db34d56be
--- /dev/null
+++ b/arch/tile/include/asm/stat.h
@@ -0,0 +1,4 @@
1#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
2#define __ARCH_WANT_STAT64 /* Used for compat_sys_stat64() etc. */
3#endif
4#include <asm-generic/stat.h>
diff --git a/arch/tile/include/asm/swab.h b/arch/tile/include/asm/swab.h
new file mode 100644
index 00000000000..7c37b38f6c8
--- /dev/null
+++ b/arch/tile/include/asm/swab.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SWAB_H
16#define _ASM_TILE_SWAB_H
17
18/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
19#define __arch_swab32(x) __builtin_bswap32(x)
20#define __arch_swab64(x) __builtin_bswap64(x)
21#define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
22
23#endif /* _ASM_TILE_SWAB_H */
diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h
new file mode 100644
index 00000000000..23d1842f483
--- /dev/null
+++ b/arch/tile/include/asm/system.h
@@ -0,0 +1,261 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SYSTEM_H
16#define _ASM_TILE_SYSTEM_H
17
18#ifndef __ASSEMBLY__
19
20#include <linux/types.h>
21#include <linux/irqflags.h>
22
23/* NOTE: we can't include <linux/ptrace.h> due to #include dependencies. */
24#include <asm/ptrace.h>
25
26#include <arch/chip.h>
27#include <arch/sim_def.h>
28#include <arch/spr_def.h>
29
30/*
31 * read_barrier_depends - Flush all pending reads that subsequents reads
32 * depend on.
33 *
34 * No data-dependent reads from memory-like regions are ever reordered
35 * over this barrier. All reads preceding this primitive are guaranteed
36 * to access memory (but not necessarily other CPUs' caches) before any
37 * reads following this primitive that depend on the data return by
38 * any of the preceding reads. This primitive is much lighter weight than
39 * rmb() on most CPUs, and is never heavier weight than is
40 * rmb().
41 *
42 * These ordering constraints are respected by both the local CPU
43 * and the compiler.
44 *
45 * Ordering is not guaranteed by anything other than these primitives,
46 * not even by data dependencies. See the documentation for
47 * memory_barrier() for examples and URLs to more information.
48 *
49 * For example, the following code would force ordering (the initial
50 * value of "a" is zero, "b" is one, and "p" is "&a"):
51 *
52 * <programlisting>
53 * CPU 0 CPU 1
54 *
55 * b = 2;
56 * memory_barrier();
57 * p = &b; q = p;
58 * read_barrier_depends();
59 * d = *q;
60 * </programlisting>
61 *
62 * because the read of "*q" depends on the read of "p" and these
63 * two reads are separated by a read_barrier_depends(). However,
64 * the following code, with the same initial values for "a" and "b":
65 *
66 * <programlisting>
67 * CPU 0 CPU 1
68 *
69 * a = 2;
70 * memory_barrier();
71 * b = 3; y = b;
72 * read_barrier_depends();
73 * x = a;
74 * </programlisting>
75 *
76 * does not enforce ordering, since there is no data dependency between
77 * the read of "a" and the read of "b". Therefore, on some CPUs, such
78 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
79 * in cases like this where there are no data dependencies.
80 */
81
82#define read_barrier_depends() do { } while (0)
83
84#define __sync() __insn_mf()
85
86#if CHIP_HAS_SPLIT_CYCLE()
87#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW)
88#else
89#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
90#endif
91
92#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
93#include <hv/syscall_public.h>
94/*
95 * Issue an uncacheable load to each memory controller, then
96 * wait until those loads have completed.
97 */
98static inline void __mb_incoherent(void)
99{
100 long clobber_r10;
101 asm volatile("swint2"
102 : "=R10" (clobber_r10)
103 : "R10" (HV_SYS_fence_incoherent)
104 : "r0", "r1", "r2", "r3", "r4",
105 "r5", "r6", "r7", "r8", "r9",
106 "r11", "r12", "r13", "r14",
107 "r15", "r16", "r17", "r18", "r19",
108 "r20", "r21", "r22", "r23", "r24",
109 "r25", "r26", "r27", "r28", "r29");
110}
111#endif
112
113/* Fence to guarantee visibility of stores to incoherent memory. */
114static inline void
115mb_incoherent(void)
116{
117 __insn_mf();
118
119#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
120 {
121#if CHIP_HAS_TILE_WRITE_PENDING()
122 const unsigned long WRITE_TIMEOUT_CYCLES = 400;
123 unsigned long start = get_cycles_low();
124 do {
125 if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
126 return;
127 } while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
128#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
129 (void) __mb_incoherent();
130 }
131#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */
132}
133
134#define fast_wmb() __sync()
135#define fast_rmb() __sync()
136#define fast_mb() __sync()
137#define fast_iob() mb_incoherent()
138
139#define wmb() fast_wmb()
140#define rmb() fast_rmb()
141#define mb() fast_mb()
142#define iob() fast_iob()
143
144#ifdef CONFIG_SMP
145#define smp_mb() mb()
146#define smp_rmb() rmb()
147#define smp_wmb() wmb()
148#define smp_read_barrier_depends() read_barrier_depends()
149#else
150#define smp_mb() barrier()
151#define smp_rmb() barrier()
152#define smp_wmb() barrier()
153#define smp_read_barrier_depends() do { } while (0)
154#endif
155
156#define set_mb(var, value) \
157 do { var = value; mb(); } while (0)
158
159/*
160 * Pause the DMA engine and static network before task switching.
161 */
162#define prepare_arch_switch(next) _prepare_arch_switch(next)
163void _prepare_arch_switch(struct task_struct *next);
164
165
166/*
167 * switch_to(n) should switch tasks to task nr n, first
168 * checking that n isn't the current task, in which case it does nothing.
169 * The number of callee-saved registers saved on the kernel stack
170 * is defined here for use in copy_thread() and must agree with __switch_to().
171 */
172#endif /* !__ASSEMBLY__ */
173#define CALLEE_SAVED_FIRST_REG 30
174#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */
175#ifndef __ASSEMBLY__
176struct task_struct;
177#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next)))
178extern struct task_struct *_switch_to(struct task_struct *prev,
179 struct task_struct *next);
180
181/* Helper function for _switch_to(). */
182extern struct task_struct *__switch_to(struct task_struct *prev,
183 struct task_struct *next,
184 unsigned long new_system_save_k_0);
185
186/* Address that switched-away from tasks are at. */
187extern unsigned long get_switch_to_pc(void);
188
189/*
190 * On SMP systems, when the scheduler does migration-cost autodetection,
191 * it needs a way to flush as much of the CPU's caches as possible:
192 *
193 * TODO: fill this in!
194 */
195static inline void sched_cacheflush(void)
196{
197}
198
199#define arch_align_stack(x) (x)
200
201/*
202 * Is the kernel doing fixups of unaligned accesses? If <0, no kernel
203 * intervention occurs and SIGBUS is delivered with no data address
204 * info. If 0, the kernel single-steps the instruction to discover
205 * the data address to provide with the SIGBUS. If 1, the kernel does
206 * a fixup.
207 */
208extern int unaligned_fixup;
209
210/* Is the kernel printing on each unaligned fixup? */
211extern int unaligned_printk;
212
213/* Number of unaligned fixups performed */
214extern unsigned int unaligned_fixup_count;
215
216/* Init-time routine to do tile-specific per-cpu setup. */
217void setup_cpu(int boot);
218
219/* User-level DMA management functions */
220void grant_dma_mpls(void);
221void restrict_dma_mpls(void);
222
223#ifdef CONFIG_HARDWALL
224/* User-level network management functions */
225void reset_network_state(void);
226void grant_network_mpls(void);
227void restrict_network_mpls(void);
228int hardwall_deactivate(struct task_struct *task);
229
230/* Hook hardwall code into changes in affinity. */
231#define arch_set_cpus_allowed(p, new_mask) do { \
232 if (p->thread.hardwall && !cpumask_equal(&p->cpus_allowed, new_mask)) \
233 hardwall_deactivate(p); \
234} while (0)
235#endif
236
237/*
238 * Kernel threads can check to see if they need to migrate their
239 * stack whenever they return from a context switch; for user
240 * threads, we defer until they are returning to user-space.
241 */
242#define finish_arch_switch(prev) do { \
243 if (unlikely((prev)->state == TASK_DEAD)) \
244 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
245 ((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
246 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
247 (current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
248 if (current->mm == NULL && !kstack_hash && \
249 current_thread_info()->homecache_cpu != smp_processor_id()) \
250 homecache_migrate_kthread(); \
251} while (0)
252
253/* Support function for forking a new task. */
254void ret_from_fork(void);
255
256/* Called from ret_from_fork() when a new process starts up. */
257struct task_struct *sim_notify_fork(struct task_struct *prev);
258
259#endif /* !__ASSEMBLY__ */
260
261#endif /* _ASM_TILE_SYSTEM_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 21:43:06 -0400