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-rw-r--r--arch/tile/include/arch/abi.h96
-rw-r--r--arch/tile/include/arch/chip.h23
-rw-r--r--arch/tile/include/arch/chip_tile64.h258
-rw-r--r--arch/tile/include/arch/chip_tilegx.h258
-rw-r--r--arch/tile/include/arch/chip_tilepro.h258
-rw-r--r--arch/tile/include/arch/icache.h93
-rw-r--r--arch/tile/include/arch/interrupts.h19
-rw-r--r--arch/tile/include/arch/interrupts_32.h307
-rw-r--r--arch/tile/include/arch/interrupts_64.h276
-rw-r--r--arch/tile/include/arch/sim.h643
-rw-r--r--arch/tile/include/arch/sim_def.h505
-rw-r--r--arch/tile/include/arch/spr_def_32.h201
-rw-r--r--arch/tile/include/arch/spr_def_64.h173
-rw-r--r--arch/tile/include/asm/auxvec.h20
-rw-r--r--arch/tile/include/asm/bitsperlong.h26
-rw-r--r--arch/tile/include/asm/byteorder.h1
-rw-r--r--arch/tile/include/asm/memprof.h33
-rw-r--r--arch/tile/include/asm/mman.h41
-rw-r--r--arch/tile/include/asm/opcode-tile.h30
-rw-r--r--arch/tile/include/asm/opcode-tile_32.h1513
-rw-r--r--arch/tile/include/asm/opcode-tile_64.h1248
-rw-r--r--arch/tile/include/asm/opcode_constants.h26
-rw-r--r--arch/tile/include/asm/opcode_constants_32.h480
-rw-r--r--arch/tile/include/asm/opcode_constants_64.h609
-rw-r--r--arch/tile/include/asm/sigcontext.h35
-rw-r--r--arch/tile/include/asm/siginfo.h34
-rw-r--r--arch/tile/include/asm/stat.h4
-rw-r--r--arch/tile/include/asm/swab.h23
-rw-r--r--arch/tile/include/asm/system.h261
-rw-r--r--arch/tile/kernel/init_task.c59
-rw-r--r--arch/tile/kernel/relocate_kernel.S280
31 files changed, 7833 insertions, 0 deletions
diff --git a/arch/tile/include/arch/abi.h b/arch/tile/include/arch/abi.h
new file mode 100644
index 00000000000..8affc76f771
--- /dev/null
+++ b/arch/tile/include/arch/abi.h
@@ -0,0 +1,96 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file
17 *
18 * ABI-related register definitions helpful when writing assembly code.
19 */
20
21#ifndef __ARCH_ABI_H__
22#define __ARCH_ABI_H__
23
24#include <arch/chip.h>
25
26/* Registers 0 - 55 are "normal", but some perform special roles. */
27
28#define TREG_FP 52 /**< Frame pointer. */
29#define TREG_TP 53 /**< Thread pointer. */
30#define TREG_SP 54 /**< Stack pointer. */
31#define TREG_LR 55 /**< Link to calling function PC. */
32
33/** Index of last normal general-purpose register. */
34#define TREG_LAST_GPR 55
35
36/* Registers 56 - 62 are "special" network registers. */
37
38#define TREG_SN 56 /**< Static network access. */
39#define TREG_IDN0 57 /**< IDN demux 0 access. */
40#define TREG_IDN1 58 /**< IDN demux 1 access. */
41#define TREG_UDN0 59 /**< UDN demux 0 access. */
42#define TREG_UDN1 60 /**< UDN demux 1 access. */
43#define TREG_UDN2 61 /**< UDN demux 2 access. */
44#define TREG_UDN3 62 /**< UDN demux 3 access. */
45
46/* Register 63 is the "special" zero register. */
47
48#define TREG_ZERO 63 /**< "Zero" register; always reads as "0". */
49
50
51/** By convention, this register is used to hold the syscall number. */
52#define TREG_SYSCALL_NR 10
53
54/** Name of register that holds the syscall number, for use in assembly. */
55#define TREG_SYSCALL_NR_NAME r10
56
57
58/**
59 * The ABI requires callers to allocate a caller state save area of
60 * this many bytes at the bottom of each stack frame.
61 */
62#define C_ABI_SAVE_AREA_SIZE (2 * (CHIP_WORD_SIZE() / 8))
63
64/**
65 * The operand to an 'info' opcode directing the backtracer to not
66 * try to find the calling frame.
67 */
68#define INFO_OP_CANNOT_BACKTRACE 2
69
70#ifndef __ASSEMBLER__
71#if CHIP_WORD_SIZE() > 32
72
73/** Unsigned type that can hold a register. */
74typedef unsigned long long uint_reg_t;
75
76/** Signed type that can hold a register. */
77typedef long long int_reg_t;
78
79/** String prefix to use for printf(). */
80#define INT_REG_FMT "ll"
81
82#elif !defined(__LP64__) /* avoid confusion with LP64 cross-build tools */
83
84/** Unsigned type that can hold a register. */
85typedef unsigned long uint_reg_t;
86
87/** Signed type that can hold a register. */
88typedef long int_reg_t;
89
90/** String prefix to use for printf(). */
91#define INT_REG_FMT "l"
92
93#endif
94#endif /* __ASSEMBLER__ */
95
96#endif /* !__ARCH_ABI_H__ */
diff --git a/arch/tile/include/arch/chip.h b/arch/tile/include/arch/chip.h
new file mode 100644
index 00000000000..926d3db0e91
--- /dev/null
+++ b/arch/tile/include/arch/chip.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#if __tile_chip__ == 0
16#include <arch/chip_tile64.h>
17#elif __tile_chip__ == 1
18#include <arch/chip_tilepro.h>
19#elif defined(__tilegx__)
20#include <arch/chip_tilegx.h>
21#else
22#error Unexpected Tilera chip type
23#endif
diff --git a/arch/tile/include/arch/chip_tile64.h b/arch/tile/include/arch/chip_tile64.h
new file mode 100644
index 00000000000..261aaba092d
--- /dev/null
+++ b/arch/tile/include/arch/chip_tile64.h
@@ -0,0 +1,258 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 * @file
17 * Global header file.
18 * This header file specifies defines for TILE64.
19 */
20
21#ifndef __ARCH_CHIP_H__
22#define __ARCH_CHIP_H__
23
24/** Specify chip version.
25 * When possible, prefer the CHIP_xxx symbols below for future-proofing.
26 * This is intended for cross-compiling; native compilation should
27 * use the predefined __tile_chip__ symbol.
28 */
29#define TILE_CHIP 0
30
31/** Specify chip revision.
32 * This provides for the case of a respin of a particular chip type;
33 * the normal value for this symbol is "0".
34 * This is intended for cross-compiling; native compilation should
35 * use the predefined __tile_chip_rev__ symbol.
36 */
37#define TILE_CHIP_REV 0
38
39/** The name of this architecture. */
40#define CHIP_ARCH_NAME "tile64"
41
42/** The ELF e_machine type for binaries for this chip. */
43#define CHIP_ELF_TYPE() EM_TILE64
44
45/** The alternate ELF e_machine type for binaries for this chip. */
46#define CHIP_COMPAT_ELF_TYPE() 0x2506
47
48/** What is the native word size of the machine? */
49#define CHIP_WORD_SIZE() 32
50
51/** How many bits of a virtual address are used. Extra bits must be
52 * the sign extension of the low bits.
53 */
54#define CHIP_VA_WIDTH() 32
55
56/** How many bits are in a physical address? */
57#define CHIP_PA_WIDTH() 36
58
59/** Size of the L2 cache, in bytes. */
60#define CHIP_L2_CACHE_SIZE() 65536
61
62/** Log size of an L2 cache line in bytes. */
63#define CHIP_L2_LOG_LINE_SIZE() 6
64
65/** Size of an L2 cache line, in bytes. */
66#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
67
68/** Associativity of the L2 cache. */
69#define CHIP_L2_ASSOC() 2
70
71/** Size of the L1 data cache, in bytes. */
72#define CHIP_L1D_CACHE_SIZE() 8192
73
74/** Log size of an L1 data cache line in bytes. */
75#define CHIP_L1D_LOG_LINE_SIZE() 4
76
77/** Size of an L1 data cache line, in bytes. */
78#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
79
80/** Associativity of the L1 data cache. */
81#define CHIP_L1D_ASSOC() 2
82
83/** Size of the L1 instruction cache, in bytes. */
84#define CHIP_L1I_CACHE_SIZE() 8192
85
86/** Log size of an L1 instruction cache line in bytes. */
87#define CHIP_L1I_LOG_LINE_SIZE() 6
88
89/** Size of an L1 instruction cache line, in bytes. */
90#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
91
92/** Associativity of the L1 instruction cache. */
93#define CHIP_L1I_ASSOC() 1
94
95/** Stride with which flush instructions must be issued. */
96#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
97
98/** Stride with which inv instructions must be issued. */
99#define CHIP_INV_STRIDE() CHIP_L1D_LINE_SIZE()
100
101/** Stride with which finv instructions must be issued. */
102#define CHIP_FINV_STRIDE() CHIP_L1D_LINE_SIZE()
103
104/** Can the local cache coherently cache data that is homed elsewhere? */
105#define CHIP_HAS_COHERENT_LOCAL_CACHE() 0
106
107/** How many simultaneous outstanding victims can the L2 cache have? */
108#define CHIP_MAX_OUTSTANDING_VICTIMS() 2
109
110/** Does the TLB support the NC and NOALLOC bits? */
111#define CHIP_HAS_NC_AND_NOALLOC_BITS() 0
112
113/** Does the chip support hash-for-home caching? */
114#define CHIP_HAS_CBOX_HOME_MAP() 0
115
116/** Number of entries in the chip's home map tables. */
117/* #define CHIP_CBOX_HOME_MAP_SIZE() -- does not apply to chip 0 */
118
119/** Do uncacheable requests miss in the cache regardless of whether
120 * there is matching data? */
121#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 0
122
123/** Does the mf instruction wait for victims? */
124#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 1
125
126/** Does the chip have an "inv" instruction that doesn't also flush? */
127#define CHIP_HAS_INV() 0
128
129/** Does the chip have a "wh64" instruction? */
130#define CHIP_HAS_WH64() 0
131
132/** Does this chip have a 'dword_align' instruction? */
133#define CHIP_HAS_DWORD_ALIGN() 0
134
135/** Number of performance counters. */
136#define CHIP_PERFORMANCE_COUNTERS() 2
137
138/** Does this chip have auxiliary performance counters? */
139#define CHIP_HAS_AUX_PERF_COUNTERS() 0
140
141/** Is the CBOX_MSR1 SPR supported? */
142#define CHIP_HAS_CBOX_MSR1() 0
143
144/** Is the TILE_RTF_HWM SPR supported? */
145#define CHIP_HAS_TILE_RTF_HWM() 0
146
147/** Is the TILE_WRITE_PENDING SPR supported? */
148#define CHIP_HAS_TILE_WRITE_PENDING() 0
149
150/** Is the PROC_STATUS SPR supported? */
151#define CHIP_HAS_PROC_STATUS_SPR() 0
152
153/** Is the DSTREAM_PF SPR supported? */
154#define CHIP_HAS_DSTREAM_PF() 0
155
156/** Log of the number of mshims we have. */
157#define CHIP_LOG_NUM_MSHIMS() 2
158
159/** Are the bases of the interrupt vector areas fixed? */
160#define CHIP_HAS_FIXED_INTVEC_BASE() 1
161
162/** Are the interrupt masks split up into 2 SPRs? */
163#define CHIP_HAS_SPLIT_INTR_MASK() 1
164
165/** Is the cycle count split up into 2 SPRs? */
166#define CHIP_HAS_SPLIT_CYCLE() 1
167
168/** Does the chip have a static network? */
169#define CHIP_HAS_SN() 1
170
171/** Does the chip have a static network processor? */
172#define CHIP_HAS_SN_PROC() 1
173
174/** Size of the L1 static network processor instruction cache, in bytes. */
175#define CHIP_L1SNI_CACHE_SIZE() 2048
176
177/** Does the chip have DMA support in each tile? */
178#define CHIP_HAS_TILE_DMA() 1
179
180/** Does the chip have the second revision of the directly accessible
181 * dynamic networks? This encapsulates a number of characteristics,
182 * including the absence of the catch-all, the absence of inline message
183 * tags, the absence of support for network context-switching, and so on.
184 */
185#define CHIP_HAS_REV1_XDN() 0
186
187/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
188#define CHIP_HAS_CMPEXCH() 0
189
190/** Does the chip have memory-mapped I/O support? */
191#define CHIP_HAS_MMIO() 0
192
193/** Does the chip have post-completion interrupts? */
194#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0
195
196/** Does the chip have native single step support? */
197#define CHIP_HAS_SINGLE_STEP() 0
198
199#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
200
201/** How many entries are present in the instruction TLB? */
202#define CHIP_ITLB_ENTRIES() 8
203
204/** How many entries are present in the data TLB? */
205#define CHIP_DTLB_ENTRIES() 16
206
207/** How many MAF entries does the XAUI shim have? */
208#define CHIP_XAUI_MAF_ENTRIES() 16
209
210/** Does the memory shim have a source-id table? */
211#define CHIP_HAS_MSHIM_SRCID_TABLE() 1
212
213/** Does the L1 instruction cache clear on reset? */
214#define CHIP_HAS_L1I_CLEAR_ON_RESET() 0
215
216/** Does the chip come out of reset with valid coordinates on all tiles?
217 * Note that if defined, this also implies that the upper left is 1,1.
218 */
219#define CHIP_HAS_VALID_TILE_COORD_RESET() 0
220
221/** Does the chip have unified packet formats? */
222#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 0
223
224/** Does the chip support write reordering? */
225#define CHIP_HAS_WRITE_REORDERING() 0
226
227/** Does the chip support Y-X routing as well as X-Y? */
228#define CHIP_HAS_Y_X_ROUTING() 0
229
230/** Is INTCTRL_3 managed with the correct MPL? */
231#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 0
232
233/** Is it possible to configure the chip to be big-endian? */
234#define CHIP_HAS_BIG_ENDIAN_CONFIG() 0
235
236/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
237#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
238
239/** Is the DIAG_TRACE_WAY SPR supported? */
240#define CHIP_HAS_DIAG_TRACE_WAY() 0
241
242/** Is the MEM_STRIPE_CONFIG SPR supported? */
243#define CHIP_HAS_MEM_STRIPE_CONFIG() 0
244
245/** Are the TLB_PERF SPRs supported? */
246#define CHIP_HAS_TLB_PERF() 0
247
248/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
249#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
250
251/** Does the chip support rev1 DMA packets? */
252#define CHIP_HAS_REV1_DMA_PACKETS() 0
253
254/** Does the chip have an IPI shim? */
255#define CHIP_HAS_IPI() 0
256
257#endif /* !__OPEN_SOURCE__ */
258#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/arch/chip_tilegx.h b/arch/tile/include/arch/chip_tilegx.h
new file mode 100644
index 00000000000..ea8e4f2c948
--- /dev/null
+++ b/arch/tile/include/arch/chip_tilegx.h
@@ -0,0 +1,258 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 * @file
17 * Global header file.
18 * This header file specifies defines for TILE-Gx.
19 */
20
21#ifndef __ARCH_CHIP_H__
22#define __ARCH_CHIP_H__
23
24/** Specify chip version.
25 * When possible, prefer the CHIP_xxx symbols below for future-proofing.
26 * This is intended for cross-compiling; native compilation should
27 * use the predefined __tile_chip__ symbol.
28 */
29#define TILE_CHIP 10
30
31/** Specify chip revision.
32 * This provides for the case of a respin of a particular chip type;
33 * the normal value for this symbol is "0".
34 * This is intended for cross-compiling; native compilation should
35 * use the predefined __tile_chip_rev__ symbol.
36 */
37#define TILE_CHIP_REV 0
38
39/** The name of this architecture. */
40#define CHIP_ARCH_NAME "tilegx"
41
42/** The ELF e_machine type for binaries for this chip. */
43#define CHIP_ELF_TYPE() EM_TILEGX
44
45/** The alternate ELF e_machine type for binaries for this chip. */
46#define CHIP_COMPAT_ELF_TYPE() 0x2597
47
48/** What is the native word size of the machine? */
49#define CHIP_WORD_SIZE() 64
50
51/** How many bits of a virtual address are used. Extra bits must be
52 * the sign extension of the low bits.
53 */
54#define CHIP_VA_WIDTH() 42
55
56/** How many bits are in a physical address? */
57#define CHIP_PA_WIDTH() 40
58
59/** Size of the L2 cache, in bytes. */
60#define CHIP_L2_CACHE_SIZE() 262144
61
62/** Log size of an L2 cache line in bytes. */
63#define CHIP_L2_LOG_LINE_SIZE() 6
64
65/** Size of an L2 cache line, in bytes. */
66#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
67
68/** Associativity of the L2 cache. */
69#define CHIP_L2_ASSOC() 8
70
71/** Size of the L1 data cache, in bytes. */
72#define CHIP_L1D_CACHE_SIZE() 32768
73
74/** Log size of an L1 data cache line in bytes. */
75#define CHIP_L1D_LOG_LINE_SIZE() 6
76
77/** Size of an L1 data cache line, in bytes. */
78#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
79
80/** Associativity of the L1 data cache. */
81#define CHIP_L1D_ASSOC() 2
82
83/** Size of the L1 instruction cache, in bytes. */
84#define CHIP_L1I_CACHE_SIZE() 32768
85
86/** Log size of an L1 instruction cache line in bytes. */
87#define CHIP_L1I_LOG_LINE_SIZE() 6
88
89/** Size of an L1 instruction cache line, in bytes. */
90#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
91
92/** Associativity of the L1 instruction cache. */
93#define CHIP_L1I_ASSOC() 2
94
95/** Stride with which flush instructions must be issued. */
96#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
97
98/** Stride with which inv instructions must be issued. */
99#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
100
101/** Stride with which finv instructions must be issued. */
102#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
103
104/** Can the local cache coherently cache data that is homed elsewhere? */
105#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
106
107/** How many simultaneous outstanding victims can the L2 cache have? */
108#define CHIP_MAX_OUTSTANDING_VICTIMS() 128
109
110/** Does the TLB support the NC and NOALLOC bits? */
111#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
112
113/** Does the chip support hash-for-home caching? */
114#define CHIP_HAS_CBOX_HOME_MAP() 1
115
116/** Number of entries in the chip's home map tables. */
117#define CHIP_CBOX_HOME_MAP_SIZE() 128
118
119/** Do uncacheable requests miss in the cache regardless of whether
120 * there is matching data? */
121#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
122
123/** Does the mf instruction wait for victims? */
124#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
125
126/** Does the chip have an "inv" instruction that doesn't also flush? */
127#define CHIP_HAS_INV() 1
128
129/** Does the chip have a "wh64" instruction? */
130#define CHIP_HAS_WH64() 1
131
132/** Does this chip have a 'dword_align' instruction? */
133#define CHIP_HAS_DWORD_ALIGN() 0
134
135/** Number of performance counters. */
136#define CHIP_PERFORMANCE_COUNTERS() 4
137
138/** Does this chip have auxiliary performance counters? */
139#define CHIP_HAS_AUX_PERF_COUNTERS() 1
140
141/** Is the CBOX_MSR1 SPR supported? */
142#define CHIP_HAS_CBOX_MSR1() 0
143
144/** Is the TILE_RTF_HWM SPR supported? */
145#define CHIP_HAS_TILE_RTF_HWM() 1
146
147/** Is the TILE_WRITE_PENDING SPR supported? */
148#define CHIP_HAS_TILE_WRITE_PENDING() 0
149
150/** Is the PROC_STATUS SPR supported? */
151#define CHIP_HAS_PROC_STATUS_SPR() 1
152
153/** Is the DSTREAM_PF SPR supported? */
154#define CHIP_HAS_DSTREAM_PF() 1
155
156/** Log of the number of mshims we have. */
157#define CHIP_LOG_NUM_MSHIMS() 2
158
159/** Are the bases of the interrupt vector areas fixed? */
160#define CHIP_HAS_FIXED_INTVEC_BASE() 0
161
162/** Are the interrupt masks split up into 2 SPRs? */
163#define CHIP_HAS_SPLIT_INTR_MASK() 0
164
165/** Is the cycle count split up into 2 SPRs? */
166#define CHIP_HAS_SPLIT_CYCLE() 0
167
168/** Does the chip have a static network? */
169#define CHIP_HAS_SN() 0
170
171/** Does the chip have a static network processor? */
172#define CHIP_HAS_SN_PROC() 0
173
174/** Size of the L1 static network processor instruction cache, in bytes. */
175/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */
176
177/** Does the chip have DMA support in each tile? */
178#define CHIP_HAS_TILE_DMA() 0
179
180/** Does the chip have the second revision of the directly accessible
181 * dynamic networks? This encapsulates a number of characteristics,
182 * including the absence of the catch-all, the absence of inline message
183 * tags, the absence of support for network context-switching, and so on.
184 */
185#define CHIP_HAS_REV1_XDN() 1
186
187/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
188#define CHIP_HAS_CMPEXCH() 1
189
190/** Does the chip have memory-mapped I/O support? */
191#define CHIP_HAS_MMIO() 1
192
193/** Does the chip have post-completion interrupts? */
194#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1
195
196/** Does the chip have native single step support? */
197#define CHIP_HAS_SINGLE_STEP() 1
198
199#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
200
201/** How many entries are present in the instruction TLB? */
202#define CHIP_ITLB_ENTRIES() 16
203
204/** How many entries are present in the data TLB? */
205#define CHIP_DTLB_ENTRIES() 32
206
207/** How many MAF entries does the XAUI shim have? */
208#define CHIP_XAUI_MAF_ENTRIES() 32
209
210/** Does the memory shim have a source-id table? */
211#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
212
213/** Does the L1 instruction cache clear on reset? */
214#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
215
216/** Does the chip come out of reset with valid coordinates on all tiles?
217 * Note that if defined, this also implies that the upper left is 1,1.
218 */
219#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
220
221/** Does the chip have unified packet formats? */
222#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
223
224/** Does the chip support write reordering? */
225#define CHIP_HAS_WRITE_REORDERING() 1
226
227/** Does the chip support Y-X routing as well as X-Y? */
228#define CHIP_HAS_Y_X_ROUTING() 1
229
230/** Is INTCTRL_3 managed with the correct MPL? */
231#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
232
233/** Is it possible to configure the chip to be big-endian? */
234#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
235
236/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
237#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
238
239/** Is the DIAG_TRACE_WAY SPR supported? */
240#define CHIP_HAS_DIAG_TRACE_WAY() 0
241
242/** Is the MEM_STRIPE_CONFIG SPR supported? */
243#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
244
245/** Are the TLB_PERF SPRs supported? */
246#define CHIP_HAS_TLB_PERF() 1
247
248/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
249#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
250
251/** Does the chip support rev1 DMA packets? */
252#define CHIP_HAS_REV1_DMA_PACKETS() 1
253
254/** Does the chip have an IPI shim? */
255#define CHIP_HAS_IPI() 1
256
257#endif /* !__OPEN_SOURCE__ */
258#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/arch/chip_tilepro.h b/arch/tile/include/arch/chip_tilepro.h
new file mode 100644
index 00000000000..70017699a74
--- /dev/null
+++ b/arch/tile/include/arch/chip_tilepro.h
@@ -0,0 +1,258 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 * @file
17 * Global header file.
18 * This header file specifies defines for TILEPro.
19 */
20
21#ifndef __ARCH_CHIP_H__
22#define __ARCH_CHIP_H__
23
24/** Specify chip version.
25 * When possible, prefer the CHIP_xxx symbols below for future-proofing.
26 * This is intended for cross-compiling; native compilation should
27 * use the predefined __tile_chip__ symbol.
28 */
29#define TILE_CHIP 1
30
31/** Specify chip revision.
32 * This provides for the case of a respin of a particular chip type;
33 * the normal value for this symbol is "0".
34 * This is intended for cross-compiling; native compilation should
35 * use the predefined __tile_chip_rev__ symbol.
36 */
37#define TILE_CHIP_REV 0
38
39/** The name of this architecture. */
40#define CHIP_ARCH_NAME "tilepro"
41
42/** The ELF e_machine type for binaries for this chip. */
43#define CHIP_ELF_TYPE() EM_TILEPRO
44
45/** The alternate ELF e_machine type for binaries for this chip. */
46#define CHIP_COMPAT_ELF_TYPE() 0x2507
47
48/** What is the native word size of the machine? */
49#define CHIP_WORD_SIZE() 32
50
51/** How many bits of a virtual address are used. Extra bits must be
52 * the sign extension of the low bits.
53 */
54#define CHIP_VA_WIDTH() 32
55
56/** How many bits are in a physical address? */
57#define CHIP_PA_WIDTH() 36
58
59/** Size of the L2 cache, in bytes. */
60#define CHIP_L2_CACHE_SIZE() 65536
61
62/** Log size of an L2 cache line in bytes. */
63#define CHIP_L2_LOG_LINE_SIZE() 6
64
65/** Size of an L2 cache line, in bytes. */
66#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
67
68/** Associativity of the L2 cache. */
69#define CHIP_L2_ASSOC() 4
70
71/** Size of the L1 data cache, in bytes. */
72#define CHIP_L1D_CACHE_SIZE() 8192
73
74/** Log size of an L1 data cache line in bytes. */
75#define CHIP_L1D_LOG_LINE_SIZE() 4
76
77/** Size of an L1 data cache line, in bytes. */
78#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
79
80/** Associativity of the L1 data cache. */
81#define CHIP_L1D_ASSOC() 2
82
83/** Size of the L1 instruction cache, in bytes. */
84#define CHIP_L1I_CACHE_SIZE() 16384
85
86/** Log size of an L1 instruction cache line in bytes. */
87#define CHIP_L1I_LOG_LINE_SIZE() 6
88
89/** Size of an L1 instruction cache line, in bytes. */
90#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
91
92/** Associativity of the L1 instruction cache. */
93#define CHIP_L1I_ASSOC() 1
94
95/** Stride with which flush instructions must be issued. */
96#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
97
98/** Stride with which inv instructions must be issued. */
99#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
100
101/** Stride with which finv instructions must be issued. */
102#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
103
104/** Can the local cache coherently cache data that is homed elsewhere? */
105#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
106
107/** How many simultaneous outstanding victims can the L2 cache have? */
108#define CHIP_MAX_OUTSTANDING_VICTIMS() 4
109
110/** Does the TLB support the NC and NOALLOC bits? */
111#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
112
113/** Does the chip support hash-for-home caching? */
114#define CHIP_HAS_CBOX_HOME_MAP() 1
115
116/** Number of entries in the chip's home map tables. */
117#define CHIP_CBOX_HOME_MAP_SIZE() 64
118
119/** Do uncacheable requests miss in the cache regardless of whether
120 * there is matching data? */
121#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
122
123/** Does the mf instruction wait for victims? */
124#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
125
126/** Does the chip have an "inv" instruction that doesn't also flush? */
127#define CHIP_HAS_INV() 1
128
129/** Does the chip have a "wh64" instruction? */
130#define CHIP_HAS_WH64() 1
131
132/** Does this chip have a 'dword_align' instruction? */
133#define CHIP_HAS_DWORD_ALIGN() 1
134
135/** Number of performance counters. */
136#define CHIP_PERFORMANCE_COUNTERS() 4
137
138/** Does this chip have auxiliary performance counters? */
139#define CHIP_HAS_AUX_PERF_COUNTERS() 1
140
141/** Is the CBOX_MSR1 SPR supported? */
142#define CHIP_HAS_CBOX_MSR1() 1
143
144/** Is the TILE_RTF_HWM SPR supported? */
145#define CHIP_HAS_TILE_RTF_HWM() 1
146
147/** Is the TILE_WRITE_PENDING SPR supported? */
148#define CHIP_HAS_TILE_WRITE_PENDING() 1
149
150/** Is the PROC_STATUS SPR supported? */
151#define CHIP_HAS_PROC_STATUS_SPR() 1
152
153/** Is the DSTREAM_PF SPR supported? */
154#define CHIP_HAS_DSTREAM_PF() 0
155
156/** Log of the number of mshims we have. */
157#define CHIP_LOG_NUM_MSHIMS() 2
158
159/** Are the bases of the interrupt vector areas fixed? */
160#define CHIP_HAS_FIXED_INTVEC_BASE() 1
161
162/** Are the interrupt masks split up into 2 SPRs? */
163#define CHIP_HAS_SPLIT_INTR_MASK() 1
164
165/** Is the cycle count split up into 2 SPRs? */
166#define CHIP_HAS_SPLIT_CYCLE() 1
167
168/** Does the chip have a static network? */
169#define CHIP_HAS_SN() 1
170
171/** Does the chip have a static network processor? */
172#define CHIP_HAS_SN_PROC() 0
173
174/** Size of the L1 static network processor instruction cache, in bytes. */
175/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 1 */
176
177/** Does the chip have DMA support in each tile? */
178#define CHIP_HAS_TILE_DMA() 1
179
180/** Does the chip have the second revision of the directly accessible
181 * dynamic networks? This encapsulates a number of characteristics,
182 * including the absence of the catch-all, the absence of inline message
183 * tags, the absence of support for network context-switching, and so on.
184 */
185#define CHIP_HAS_REV1_XDN() 0
186
187/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
188#define CHIP_HAS_CMPEXCH() 0
189
190/** Does the chip have memory-mapped I/O support? */
191#define CHIP_HAS_MMIO() 0
192
193/** Does the chip have post-completion interrupts? */
194#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0
195
196/** Does the chip have native single step support? */
197#define CHIP_HAS_SINGLE_STEP() 0
198
199#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
200
201/** How many entries are present in the instruction TLB? */
202#define CHIP_ITLB_ENTRIES() 16
203
204/** How many entries are present in the data TLB? */
205#define CHIP_DTLB_ENTRIES() 16
206
207/** How many MAF entries does the XAUI shim have? */
208#define CHIP_XAUI_MAF_ENTRIES() 32
209
210/** Does the memory shim have a source-id table? */
211#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
212
213/** Does the L1 instruction cache clear on reset? */
214#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
215
216/** Does the chip come out of reset with valid coordinates on all tiles?
217 * Note that if defined, this also implies that the upper left is 1,1.
218 */
219#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
220
221/** Does the chip have unified packet formats? */
222#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
223
224/** Does the chip support write reordering? */
225#define CHIP_HAS_WRITE_REORDERING() 1
226
227/** Does the chip support Y-X routing as well as X-Y? */
228#define CHIP_HAS_Y_X_ROUTING() 1
229
230/** Is INTCTRL_3 managed with the correct MPL? */
231#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
232
233/** Is it possible to configure the chip to be big-endian? */
234#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
235
236/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
237#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 1
238
239/** Is the DIAG_TRACE_WAY SPR supported? */
240#define CHIP_HAS_DIAG_TRACE_WAY() 1
241
242/** Is the MEM_STRIPE_CONFIG SPR supported? */
243#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
244
245/** Are the TLB_PERF SPRs supported? */
246#define CHIP_HAS_TLB_PERF() 1
247
248/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
249#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 1
250
251/** Does the chip support rev1 DMA packets? */
252#define CHIP_HAS_REV1_DMA_PACKETS() 1
253
254/** Does the chip have an IPI shim? */
255#define CHIP_HAS_IPI() 0
256
257#endif /* !__OPEN_SOURCE__ */
258#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/arch/icache.h b/arch/tile/include/arch/icache.h
new file mode 100644
index 00000000000..762eafa8a11
--- /dev/null
+++ b/arch/tile/include/arch/icache.h
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16/**
17 * @file
18 *
19 * Support for invalidating bytes in the instruction cache.
20 */
21
22#ifndef __ARCH_ICACHE_H__
23#define __ARCH_ICACHE_H__
24
25#include <arch/chip.h>
26
27
28/**
29 * Invalidate the instruction cache for the given range of memory.
30 *
31 * @param addr The start of memory to be invalidated.
32 * @param size The number of bytes to be invalidated.
33 * @param page_size The system's page size, e.g. getpagesize() in userspace.
34 * This value must be a power of two no larger than the page containing
35 * the code to be invalidated. If the value is smaller than the actual page
36 * size, this function will still work, but may run slower than necessary.
37 */
38static __inline void
39invalidate_icache(const void* addr, unsigned long size,
40 unsigned long page_size)
41{
42 const unsigned long cache_way_size =
43 CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC();
44 unsigned long max_useful_size;
45 const char* start, *end;
46 long num_passes;
47
48 if (__builtin_expect(size == 0, 0))
49 return;
50
51#ifdef __tilegx__
52 /* Limit the number of bytes visited to avoid redundant iterations. */
53 max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size;
54
55 /* No PA aliasing is possible, so one pass always suffices. */
56 num_passes = 1;
57#else
58 /* Limit the number of bytes visited to avoid redundant iterations. */
59 max_useful_size = cache_way_size;
60
61 /*
62 * Compute how many passes we need (we'll treat 0 as if it were 1).
63 * This works because we know the page size is a power of two.
64 */
65 num_passes = cache_way_size >> __builtin_ctzl(page_size);
66#endif
67
68 if (__builtin_expect(size > max_useful_size, 0))
69 size = max_useful_size;
70
71 /* Locate the first and last bytes to be invalidated. */
72 start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE());
73 end = (const char*)addr + size - 1;
74
75 __insn_mf();
76
77 do
78 {
79 const char* p;
80
81 for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE())
82 __insn_icoh(p);
83
84 start += page_size;
85 end += page_size;
86 }
87 while (--num_passes > 0);
88
89 __insn_drain();
90}
91
92
93#endif /* __ARCH_ICACHE_H__ */
diff --git a/arch/tile/include/arch/interrupts.h b/arch/tile/include/arch/interrupts.h
new file mode 100644
index 00000000000..20f8f07d2de
--- /dev/null
+++ b/arch/tile/include/arch/interrupts.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifdef __tilegx__
16#include <arch/interrupts_64.h>
17#else
18#include <arch/interrupts_32.h>
19#endif
diff --git a/arch/tile/include/arch/interrupts_32.h b/arch/tile/include/arch/interrupts_32.h
new file mode 100644
index 00000000000..96b5710505b
--- /dev/null
+++ b/arch/tile/include/arch/interrupts_32.h
@@ -0,0 +1,307 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __ARCH_INTERRUPTS_H__
16#define __ARCH_INTERRUPTS_H__
17
18/** Mask for an interrupt. */
19/* Note: must handle breaking interrupts into high and low words manually. */
20#define INT_MASK_LO(intno) (1 << (intno))
21#define INT_MASK_HI(intno) (1 << ((intno) - 32))
22
23#ifndef __ASSEMBLER__
24#define INT_MASK(intno) (1ULL << (intno))
25#endif
26
27
28/** Where a given interrupt executes */
29#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
30
31/** Where to store a vector for a given interrupt. */
32#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
33
34/** The base address of user-level interrupts. */
35#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
36
37
38/** Additional synthetic interrupt. */
39#define INT_BREAKPOINT (63)
40
41#define INT_ITLB_MISS 0
42#define INT_MEM_ERROR 1
43#define INT_ILL 2
44#define INT_GPV 3
45#define INT_SN_ACCESS 4
46#define INT_IDN_ACCESS 5
47#define INT_UDN_ACCESS 6
48#define INT_IDN_REFILL 7
49#define INT_UDN_REFILL 8
50#define INT_IDN_COMPLETE 9
51#define INT_UDN_COMPLETE 10
52#define INT_SWINT_3 11
53#define INT_SWINT_2 12
54#define INT_SWINT_1 13
55#define INT_SWINT_0 14
56#define INT_UNALIGN_DATA 15
57#define INT_DTLB_MISS 16
58#define INT_DTLB_ACCESS 17
59#define INT_DMATLB_MISS 18
60#define INT_DMATLB_ACCESS 19
61#define INT_SNITLB_MISS 20
62#define INT_SN_NOTIFY 21
63#define INT_SN_FIREWALL 22
64#define INT_IDN_FIREWALL 23
65#define INT_UDN_FIREWALL 24
66#define INT_TILE_TIMER 25
67#define INT_IDN_TIMER 26
68#define INT_UDN_TIMER 27
69#define INT_DMA_NOTIFY 28
70#define INT_IDN_CA 29
71#define INT_UDN_CA 30
72#define INT_IDN_AVAIL 31
73#define INT_UDN_AVAIL 32
74#define INT_PERF_COUNT 33
75#define INT_INTCTRL_3 34
76#define INT_INTCTRL_2 35
77#define INT_INTCTRL_1 36
78#define INT_INTCTRL_0 37
79#define INT_BOOT_ACCESS 38
80#define INT_WORLD_ACCESS 39
81#define INT_I_ASID 40
82#define INT_D_ASID 41
83#define INT_DMA_ASID 42
84#define INT_SNI_ASID 43
85#define INT_DMA_CPL 44
86#define INT_SN_CPL 45
87#define INT_DOUBLE_FAULT 46
88#define INT_SN_STATIC_ACCESS 47
89#define INT_AUX_PERF_COUNT 48
90
91#define NUM_INTERRUPTS 49
92
93#ifndef __ASSEMBLER__
94#define QUEUED_INTERRUPTS ( \
95 INT_MASK(INT_MEM_ERROR) | \
96 INT_MASK(INT_DMATLB_MISS) | \
97 INT_MASK(INT_DMATLB_ACCESS) | \
98 INT_MASK(INT_SNITLB_MISS) | \
99 INT_MASK(INT_SN_NOTIFY) | \
100 INT_MASK(INT_SN_FIREWALL) | \
101 INT_MASK(INT_IDN_FIREWALL) | \
102 INT_MASK(INT_UDN_FIREWALL) | \
103 INT_MASK(INT_TILE_TIMER) | \
104 INT_MASK(INT_IDN_TIMER) | \
105 INT_MASK(INT_UDN_TIMER) | \
106 INT_MASK(INT_DMA_NOTIFY) | \
107 INT_MASK(INT_IDN_CA) | \
108 INT_MASK(INT_UDN_CA) | \
109 INT_MASK(INT_IDN_AVAIL) | \
110 INT_MASK(INT_UDN_AVAIL) | \
111 INT_MASK(INT_PERF_COUNT) | \
112 INT_MASK(INT_INTCTRL_3) | \
113 INT_MASK(INT_INTCTRL_2) | \
114 INT_MASK(INT_INTCTRL_1) | \
115 INT_MASK(INT_INTCTRL_0) | \
116 INT_MASK(INT_BOOT_ACCESS) | \
117 INT_MASK(INT_WORLD_ACCESS) | \
118 INT_MASK(INT_I_ASID) | \
119 INT_MASK(INT_D_ASID) | \
120 INT_MASK(INT_DMA_ASID) | \
121 INT_MASK(INT_SNI_ASID) | \
122 INT_MASK(INT_DMA_CPL) | \
123 INT_MASK(INT_SN_CPL) | \
124 INT_MASK(INT_DOUBLE_FAULT) | \
125 INT_MASK(INT_AUX_PERF_COUNT) | \
126 0)
127#define NONQUEUED_INTERRUPTS ( \
128 INT_MASK(INT_ITLB_MISS) | \
129 INT_MASK(INT_ILL) | \
130 INT_MASK(INT_GPV) | \
131 INT_MASK(INT_SN_ACCESS) | \
132 INT_MASK(INT_IDN_ACCESS) | \
133 INT_MASK(INT_UDN_ACCESS) | \
134 INT_MASK(INT_IDN_REFILL) | \
135 INT_MASK(INT_UDN_REFILL) | \
136 INT_MASK(INT_IDN_COMPLETE) | \
137 INT_MASK(INT_UDN_COMPLETE) | \
138 INT_MASK(INT_SWINT_3) | \
139 INT_MASK(INT_SWINT_2) | \
140 INT_MASK(INT_SWINT_1) | \
141 INT_MASK(INT_SWINT_0) | \
142 INT_MASK(INT_UNALIGN_DATA) | \
143 INT_MASK(INT_DTLB_MISS) | \
144 INT_MASK(INT_DTLB_ACCESS) | \
145 INT_MASK(INT_SN_STATIC_ACCESS) | \
146 0)
147#define CRITICAL_MASKED_INTERRUPTS ( \
148 INT_MASK(INT_MEM_ERROR) | \
149 INT_MASK(INT_DMATLB_MISS) | \
150 INT_MASK(INT_DMATLB_ACCESS) | \
151 INT_MASK(INT_SNITLB_MISS) | \
152 INT_MASK(INT_SN_NOTIFY) | \
153 INT_MASK(INT_SN_FIREWALL) | \
154 INT_MASK(INT_IDN_FIREWALL) | \
155 INT_MASK(INT_UDN_FIREWALL) | \
156 INT_MASK(INT_TILE_TIMER) | \
157 INT_MASK(INT_IDN_TIMER) | \
158 INT_MASK(INT_UDN_TIMER) | \
159 INT_MASK(INT_DMA_NOTIFY) | \
160 INT_MASK(INT_IDN_CA) | \
161 INT_MASK(INT_UDN_CA) | \
162 INT_MASK(INT_IDN_AVAIL) | \
163 INT_MASK(INT_UDN_AVAIL) | \
164 INT_MASK(INT_PERF_COUNT) | \
165 INT_MASK(INT_INTCTRL_3) | \
166 INT_MASK(INT_INTCTRL_2) | \
167 INT_MASK(INT_INTCTRL_1) | \
168 INT_MASK(INT_INTCTRL_0) | \
169 INT_MASK(INT_AUX_PERF_COUNT) | \
170 0)
171#define CRITICAL_UNMASKED_INTERRUPTS ( \
172 INT_MASK(INT_ITLB_MISS) | \
173 INT_MASK(INT_ILL) | \
174 INT_MASK(INT_GPV) | \
175 INT_MASK(INT_SN_ACCESS) | \
176 INT_MASK(INT_IDN_ACCESS) | \
177 INT_MASK(INT_UDN_ACCESS) | \
178 INT_MASK(INT_IDN_REFILL) | \
179 INT_MASK(INT_UDN_REFILL) | \
180 INT_MASK(INT_IDN_COMPLETE) | \
181 INT_MASK(INT_UDN_COMPLETE) | \
182 INT_MASK(INT_SWINT_3) | \
183 INT_MASK(INT_SWINT_2) | \
184 INT_MASK(INT_SWINT_1) | \
185 INT_MASK(INT_SWINT_0) | \
186 INT_MASK(INT_UNALIGN_DATA) | \
187 INT_MASK(INT_DTLB_MISS) | \
188 INT_MASK(INT_DTLB_ACCESS) | \
189 INT_MASK(INT_BOOT_ACCESS) | \
190 INT_MASK(INT_WORLD_ACCESS) | \
191 INT_MASK(INT_I_ASID) | \
192 INT_MASK(INT_D_ASID) | \
193 INT_MASK(INT_DMA_ASID) | \
194 INT_MASK(INT_SNI_ASID) | \
195 INT_MASK(INT_DMA_CPL) | \
196 INT_MASK(INT_SN_CPL) | \
197 INT_MASK(INT_DOUBLE_FAULT) | \
198 INT_MASK(INT_SN_STATIC_ACCESS) | \
199 0)
200#define MASKABLE_INTERRUPTS ( \
201 INT_MASK(INT_MEM_ERROR) | \
202 INT_MASK(INT_IDN_REFILL) | \
203 INT_MASK(INT_UDN_REFILL) | \
204 INT_MASK(INT_IDN_COMPLETE) | \
205 INT_MASK(INT_UDN_COMPLETE) | \
206 INT_MASK(INT_DMATLB_MISS) | \
207 INT_MASK(INT_DMATLB_ACCESS) | \
208 INT_MASK(INT_SNITLB_MISS) | \
209 INT_MASK(INT_SN_NOTIFY) | \
210 INT_MASK(INT_SN_FIREWALL) | \
211 INT_MASK(INT_IDN_FIREWALL) | \
212 INT_MASK(INT_UDN_FIREWALL) | \
213 INT_MASK(INT_TILE_TIMER) | \
214 INT_MASK(INT_IDN_TIMER) | \
215 INT_MASK(INT_UDN_TIMER) | \
216 INT_MASK(INT_DMA_NOTIFY) | \
217 INT_MASK(INT_IDN_CA) | \
218 INT_MASK(INT_UDN_CA) | \
219 INT_MASK(INT_IDN_AVAIL) | \
220 INT_MASK(INT_UDN_AVAIL) | \
221 INT_MASK(INT_PERF_COUNT) | \
222 INT_MASK(INT_INTCTRL_3) | \
223 INT_MASK(INT_INTCTRL_2) | \
224 INT_MASK(INT_INTCTRL_1) | \
225 INT_MASK(INT_INTCTRL_0) | \
226 INT_MASK(INT_AUX_PERF_COUNT) | \
227 0)
228#define UNMASKABLE_INTERRUPTS ( \
229 INT_MASK(INT_ITLB_MISS) | \
230 INT_MASK(INT_ILL) | \
231 INT_MASK(INT_GPV) | \
232 INT_MASK(INT_SN_ACCESS) | \
233 INT_MASK(INT_IDN_ACCESS) | \
234 INT_MASK(INT_UDN_ACCESS) | \
235 INT_MASK(INT_SWINT_3) | \
236 INT_MASK(INT_SWINT_2) | \
237 INT_MASK(INT_SWINT_1) | \
238 INT_MASK(INT_SWINT_0) | \
239 INT_MASK(INT_UNALIGN_DATA) | \
240 INT_MASK(INT_DTLB_MISS) | \
241 INT_MASK(INT_DTLB_ACCESS) | \
242 INT_MASK(INT_BOOT_ACCESS) | \
243 INT_MASK(INT_WORLD_ACCESS) | \
244 INT_MASK(INT_I_ASID) | \
245 INT_MASK(INT_D_ASID) | \
246 INT_MASK(INT_DMA_ASID) | \
247 INT_MASK(INT_SNI_ASID) | \
248 INT_MASK(INT_DMA_CPL) | \
249 INT_MASK(INT_SN_CPL) | \
250 INT_MASK(INT_DOUBLE_FAULT) | \
251 INT_MASK(INT_SN_STATIC_ACCESS) | \
252 0)
253#define SYNC_INTERRUPTS ( \
254 INT_MASK(INT_ITLB_MISS) | \
255 INT_MASK(INT_ILL) | \
256 INT_MASK(INT_GPV) | \
257 INT_MASK(INT_SN_ACCESS) | \
258 INT_MASK(INT_IDN_ACCESS) | \
259 INT_MASK(INT_UDN_ACCESS) | \
260 INT_MASK(INT_IDN_REFILL) | \
261 INT_MASK(INT_UDN_REFILL) | \
262 INT_MASK(INT_IDN_COMPLETE) | \
263 INT_MASK(INT_UDN_COMPLETE) | \
264 INT_MASK(INT_SWINT_3) | \
265 INT_MASK(INT_SWINT_2) | \
266 INT_MASK(INT_SWINT_1) | \
267 INT_MASK(INT_SWINT_0) | \
268 INT_MASK(INT_UNALIGN_DATA) | \
269 INT_MASK(INT_DTLB_MISS) | \
270 INT_MASK(INT_DTLB_ACCESS) | \
271 INT_MASK(INT_SN_STATIC_ACCESS) | \
272 0)
273#define NON_SYNC_INTERRUPTS ( \
274 INT_MASK(INT_MEM_ERROR) | \
275 INT_MASK(INT_DMATLB_MISS) | \
276 INT_MASK(INT_DMATLB_ACCESS) | \
277 INT_MASK(INT_SNITLB_MISS) | \
278 INT_MASK(INT_SN_NOTIFY) | \
279 INT_MASK(INT_SN_FIREWALL) | \
280 INT_MASK(INT_IDN_FIREWALL) | \
281 INT_MASK(INT_UDN_FIREWALL) | \
282 INT_MASK(INT_TILE_TIMER) | \
283 INT_MASK(INT_IDN_TIMER) | \
284 INT_MASK(INT_UDN_TIMER) | \
285 INT_MASK(INT_DMA_NOTIFY) | \
286 INT_MASK(INT_IDN_CA) | \
287 INT_MASK(INT_UDN_CA) | \
288 INT_MASK(INT_IDN_AVAIL) | \
289 INT_MASK(INT_UDN_AVAIL) | \
290 INT_MASK(INT_PERF_COUNT) | \
291 INT_MASK(INT_INTCTRL_3) | \
292 INT_MASK(INT_INTCTRL_2) | \
293 INT_MASK(INT_INTCTRL_1) | \
294 INT_MASK(INT_INTCTRL_0) | \
295 INT_MASK(INT_BOOT_ACCESS) | \
296 INT_MASK(INT_WORLD_ACCESS) | \
297 INT_MASK(INT_I_ASID) | \
298 INT_MASK(INT_D_ASID) | \
299 INT_MASK(INT_DMA_ASID) | \
300 INT_MASK(INT_SNI_ASID) | \
301 INT_MASK(INT_DMA_CPL) | \
302 INT_MASK(INT_SN_CPL) | \
303 INT_MASK(INT_DOUBLE_FAULT) | \
304 INT_MASK(INT_AUX_PERF_COUNT) | \
305 0)
306#endif /* !__ASSEMBLER__ */
307#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/arch/interrupts_64.h b/arch/tile/include/arch/interrupts_64.h
new file mode 100644
index 00000000000..5bb58b2e4e6
--- /dev/null
+++ b/arch/tile/include/arch/interrupts_64.h
@@ -0,0 +1,276 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __ARCH_INTERRUPTS_H__
16#define __ARCH_INTERRUPTS_H__
17
18/** Mask for an interrupt. */
19#ifdef __ASSEMBLER__
20/* Note: must handle breaking interrupts into high and low words manually. */
21#define INT_MASK(intno) (1 << (intno))
22#else
23#define INT_MASK(intno) (1ULL << (intno))
24#endif
25
26
27/** Where a given interrupt executes */
28#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
29
30/** Where to store a vector for a given interrupt. */
31#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
32
33/** The base address of user-level interrupts. */
34#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
35
36
37/** Additional synthetic interrupt. */
38#define INT_BREAKPOINT (63)
39
40#define INT_MEM_ERROR 0
41#define INT_SINGLE_STEP_3 1
42#define INT_SINGLE_STEP_2 2
43#define INT_SINGLE_STEP_1 3
44#define INT_SINGLE_STEP_0 4
45#define INT_IDN_COMPLETE 5
46#define INT_UDN_COMPLETE 6
47#define INT_ITLB_MISS 7
48#define INT_ILL 8
49#define INT_GPV 9
50#define INT_IDN_ACCESS 10
51#define INT_UDN_ACCESS 11
52#define INT_SWINT_3 12
53#define INT_SWINT_2 13
54#define INT_SWINT_1 14
55#define INT_SWINT_0 15
56#define INT_ILL_TRANS 16
57#define INT_UNALIGN_DATA 17
58#define INT_DTLB_MISS 18
59#define INT_DTLB_ACCESS 19
60#define INT_IDN_FIREWALL 20
61#define INT_UDN_FIREWALL 21
62#define INT_TILE_TIMER 22
63#define INT_AUX_TILE_TIMER 23
64#define INT_IDN_TIMER 24
65#define INT_UDN_TIMER 25
66#define INT_IDN_AVAIL 26
67#define INT_UDN_AVAIL 27
68#define INT_IPI_3 28
69#define INT_IPI_2 29
70#define INT_IPI_1 30
71#define INT_IPI_0 31
72#define INT_PERF_COUNT 32
73#define INT_AUX_PERF_COUNT 33
74#define INT_INTCTRL_3 34
75#define INT_INTCTRL_2 35
76#define INT_INTCTRL_1 36
77#define INT_INTCTRL_0 37
78#define INT_BOOT_ACCESS 38
79#define INT_WORLD_ACCESS 39
80#define INT_I_ASID 40
81#define INT_D_ASID 41
82#define INT_DOUBLE_FAULT 42
83
84#define NUM_INTERRUPTS 43
85
86#ifndef __ASSEMBLER__
87#define QUEUED_INTERRUPTS ( \
88 INT_MASK(INT_MEM_ERROR) | \
89 INT_MASK(INT_IDN_COMPLETE) | \
90 INT_MASK(INT_UDN_COMPLETE) | \
91 INT_MASK(INT_IDN_FIREWALL) | \
92 INT_MASK(INT_UDN_FIREWALL) | \
93 INT_MASK(INT_TILE_TIMER) | \
94 INT_MASK(INT_AUX_TILE_TIMER) | \
95 INT_MASK(INT_IDN_TIMER) | \
96 INT_MASK(INT_UDN_TIMER) | \
97 INT_MASK(INT_IDN_AVAIL) | \
98 INT_MASK(INT_UDN_AVAIL) | \
99 INT_MASK(INT_IPI_3) | \
100 INT_MASK(INT_IPI_2) | \
101 INT_MASK(INT_IPI_1) | \
102 INT_MASK(INT_IPI_0) | \
103 INT_MASK(INT_PERF_COUNT) | \
104 INT_MASK(INT_AUX_PERF_COUNT) | \
105 INT_MASK(INT_INTCTRL_3) | \
106 INT_MASK(INT_INTCTRL_2) | \
107 INT_MASK(INT_INTCTRL_1) | \
108 INT_MASK(INT_INTCTRL_0) | \
109 INT_MASK(INT_BOOT_ACCESS) | \
110 INT_MASK(INT_WORLD_ACCESS) | \
111 INT_MASK(INT_I_ASID) | \
112 INT_MASK(INT_D_ASID) | \
113 INT_MASK(INT_DOUBLE_FAULT) | \
114 0)
115#define NONQUEUED_INTERRUPTS ( \
116 INT_MASK(INT_SINGLE_STEP_3) | \
117 INT_MASK(INT_SINGLE_STEP_2) | \
118 INT_MASK(INT_SINGLE_STEP_1) | \
119 INT_MASK(INT_SINGLE_STEP_0) | \
120 INT_MASK(INT_ITLB_MISS) | \
121 INT_MASK(INT_ILL) | \
122 INT_MASK(INT_GPV) | \
123 INT_MASK(INT_IDN_ACCESS) | \
124 INT_MASK(INT_UDN_ACCESS) | \
125 INT_MASK(INT_SWINT_3) | \
126 INT_MASK(INT_SWINT_2) | \
127 INT_MASK(INT_SWINT_1) | \
128 INT_MASK(INT_SWINT_0) | \
129 INT_MASK(INT_ILL_TRANS) | \
130 INT_MASK(INT_UNALIGN_DATA) | \
131 INT_MASK(INT_DTLB_MISS) | \
132 INT_MASK(INT_DTLB_ACCESS) | \
133 0)
134#define CRITICAL_MASKED_INTERRUPTS ( \
135 INT_MASK(INT_MEM_ERROR) | \
136 INT_MASK(INT_SINGLE_STEP_3) | \
137 INT_MASK(INT_SINGLE_STEP_2) | \
138 INT_MASK(INT_SINGLE_STEP_1) | \
139 INT_MASK(INT_SINGLE_STEP_0) | \
140 INT_MASK(INT_IDN_COMPLETE) | \
141 INT_MASK(INT_UDN_COMPLETE) | \
142 INT_MASK(INT_IDN_FIREWALL) | \
143 INT_MASK(INT_UDN_FIREWALL) | \
144 INT_MASK(INT_TILE_TIMER) | \
145 INT_MASK(INT_AUX_TILE_TIMER) | \
146 INT_MASK(INT_IDN_TIMER) | \
147 INT_MASK(INT_UDN_TIMER) | \
148 INT_MASK(INT_IDN_AVAIL) | \
149 INT_MASK(INT_UDN_AVAIL) | \
150 INT_MASK(INT_IPI_3) | \
151 INT_MASK(INT_IPI_2) | \
152 INT_MASK(INT_IPI_1) | \
153 INT_MASK(INT_IPI_0) | \
154 INT_MASK(INT_PERF_COUNT) | \
155 INT_MASK(INT_AUX_PERF_COUNT) | \
156 INT_MASK(INT_INTCTRL_3) | \
157 INT_MASK(INT_INTCTRL_2) | \
158 INT_MASK(INT_INTCTRL_1) | \
159 INT_MASK(INT_INTCTRL_0) | \
160 0)
161#define CRITICAL_UNMASKED_INTERRUPTS ( \
162 INT_MASK(INT_ITLB_MISS) | \
163 INT_MASK(INT_ILL) | \
164 INT_MASK(INT_GPV) | \
165 INT_MASK(INT_IDN_ACCESS) | \
166 INT_MASK(INT_UDN_ACCESS) | \
167 INT_MASK(INT_SWINT_3) | \
168 INT_MASK(INT_SWINT_2) | \
169 INT_MASK(INT_SWINT_1) | \
170 INT_MASK(INT_SWINT_0) | \
171 INT_MASK(INT_ILL_TRANS) | \
172 INT_MASK(INT_UNALIGN_DATA) | \
173 INT_MASK(INT_DTLB_MISS) | \
174 INT_MASK(INT_DTLB_ACCESS) | \
175 INT_MASK(INT_BOOT_ACCESS) | \
176 INT_MASK(INT_WORLD_ACCESS) | \
177 INT_MASK(INT_I_ASID) | \
178 INT_MASK(INT_D_ASID) | \
179 INT_MASK(INT_DOUBLE_FAULT) | \
180 0)
181#define MASKABLE_INTERRUPTS ( \
182 INT_MASK(INT_MEM_ERROR) | \
183 INT_MASK(INT_SINGLE_STEP_3) | \
184 INT_MASK(INT_SINGLE_STEP_2) | \
185 INT_MASK(INT_SINGLE_STEP_1) | \
186 INT_MASK(INT_SINGLE_STEP_0) | \
187 INT_MASK(INT_IDN_COMPLETE) | \
188 INT_MASK(INT_UDN_COMPLETE) | \
189 INT_MASK(INT_IDN_FIREWALL) | \
190 INT_MASK(INT_UDN_FIREWALL) | \
191 INT_MASK(INT_TILE_TIMER) | \
192 INT_MASK(INT_AUX_TILE_TIMER) | \
193 INT_MASK(INT_IDN_TIMER) | \
194 INT_MASK(INT_UDN_TIMER) | \
195 INT_MASK(INT_IDN_AVAIL) | \
196 INT_MASK(INT_UDN_AVAIL) | \
197 INT_MASK(INT_IPI_3) | \
198 INT_MASK(INT_IPI_2) | \
199 INT_MASK(INT_IPI_1) | \
200 INT_MASK(INT_IPI_0) | \
201 INT_MASK(INT_PERF_COUNT) | \
202 INT_MASK(INT_AUX_PERF_COUNT) | \
203 INT_MASK(INT_INTCTRL_3) | \
204 INT_MASK(INT_INTCTRL_2) | \
205 INT_MASK(INT_INTCTRL_1) | \
206 INT_MASK(INT_INTCTRL_0) | \
207 0)
208#define UNMASKABLE_INTERRUPTS ( \
209 INT_MASK(INT_ITLB_MISS) | \
210 INT_MASK(INT_ILL) | \
211 INT_MASK(INT_GPV) | \
212 INT_MASK(INT_IDN_ACCESS) | \
213 INT_MASK(INT_UDN_ACCESS) | \
214 INT_MASK(INT_SWINT_3) | \
215 INT_MASK(INT_SWINT_2) | \
216 INT_MASK(INT_SWINT_1) | \
217 INT_MASK(INT_SWINT_0) | \
218 INT_MASK(INT_ILL_TRANS) | \
219 INT_MASK(INT_UNALIGN_DATA) | \
220 INT_MASK(INT_DTLB_MISS) | \
221 INT_MASK(INT_DTLB_ACCESS) | \
222 INT_MASK(INT_BOOT_ACCESS) | \
223 INT_MASK(INT_WORLD_ACCESS) | \
224 INT_MASK(INT_I_ASID) | \
225 INT_MASK(INT_D_ASID) | \
226 INT_MASK(INT_DOUBLE_FAULT) | \
227 0)
228#define SYNC_INTERRUPTS ( \
229 INT_MASK(INT_SINGLE_STEP_3) | \
230 INT_MASK(INT_SINGLE_STEP_2) | \
231 INT_MASK(INT_SINGLE_STEP_1) | \
232 INT_MASK(INT_SINGLE_STEP_0) | \
233 INT_MASK(INT_IDN_COMPLETE) | \
234 INT_MASK(INT_UDN_COMPLETE) | \
235 INT_MASK(INT_ITLB_MISS) | \
236 INT_MASK(INT_ILL) | \
237 INT_MASK(INT_GPV) | \
238 INT_MASK(INT_IDN_ACCESS) | \
239 INT_MASK(INT_UDN_ACCESS) | \
240 INT_MASK(INT_SWINT_3) | \
241 INT_MASK(INT_SWINT_2) | \
242 INT_MASK(INT_SWINT_1) | \
243 INT_MASK(INT_SWINT_0) | \
244 INT_MASK(INT_ILL_TRANS) | \
245 INT_MASK(INT_UNALIGN_DATA) | \
246 INT_MASK(INT_DTLB_MISS) | \
247 INT_MASK(INT_DTLB_ACCESS) | \
248 0)
249#define NON_SYNC_INTERRUPTS ( \
250 INT_MASK(INT_MEM_ERROR) | \
251 INT_MASK(INT_IDN_FIREWALL) | \
252 INT_MASK(INT_UDN_FIREWALL) | \
253 INT_MASK(INT_TILE_TIMER) | \
254 INT_MASK(INT_AUX_TILE_TIMER) | \
255 INT_MASK(INT_IDN_TIMER) | \
256 INT_MASK(INT_UDN_TIMER) | \
257 INT_MASK(INT_IDN_AVAIL) | \
258 INT_MASK(INT_UDN_AVAIL) | \
259 INT_MASK(INT_IPI_3) | \
260 INT_MASK(INT_IPI_2) | \
261 INT_MASK(INT_IPI_1) | \
262 INT_MASK(INT_IPI_0) | \
263 INT_MASK(INT_PERF_COUNT) | \
264 INT_MASK(INT_AUX_PERF_COUNT) | \
265 INT_MASK(INT_INTCTRL_3) | \
266 INT_MASK(INT_INTCTRL_2) | \
267 INT_MASK(INT_INTCTRL_1) | \
268 INT_MASK(INT_INTCTRL_0) | \
269 INT_MASK(INT_BOOT_ACCESS) | \
270 INT_MASK(INT_WORLD_ACCESS) | \
271 INT_MASK(INT_I_ASID) | \
272 INT_MASK(INT_D_ASID) | \
273 INT_MASK(INT_DOUBLE_FAULT) | \
274 0)
275#endif /* !__ASSEMBLER__ */
276#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/arch/sim.h b/arch/tile/include/arch/sim.h
new file mode 100644
index 00000000000..e54b7b0527f
--- /dev/null
+++ b/arch/tile/include/arch/sim.h
@@ -0,0 +1,643 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file
17 *
18 * Provides an API for controlling the simulator at runtime.
19 */
20
21/**
22 * @addtogroup arch_sim
23 * @{
24 *
25 * An API for controlling the simulator at runtime.
26 *
27 * The simulator's behavior can be modified while it is running.
28 * For example, human-readable trace output can be enabled and disabled
29 * around code of interest.
30 *
31 * There are two ways to modify simulator behavior:
32 * programmatically, by calling various sim_* functions, and
33 * interactively, by entering commands like "sim set functional true"
34 * at the tile-monitor prompt. Typing "sim help" at that prompt provides
35 * a list of interactive commands.
36 *
37 * All interactive commands can also be executed programmatically by
38 * passing a string to the sim_command function.
39 */
40
41#ifndef __ARCH_SIM_H__
42#define __ARCH_SIM_H__
43
44#include <arch/sim_def.h>
45#include <arch/abi.h>
46
47#ifndef __ASSEMBLER__
48
49#include <arch/spr_def.h>
50
51
52/**
53 * Return true if the current program is running under a simulator,
54 * rather than on real hardware. If running on hardware, other "sim_xxx()"
55 * calls have no useful effect.
56 */
57static inline int
58sim_is_simulator(void)
59{
60 return __insn_mfspr(SPR_SIM_CONTROL) != 0;
61}
62
63
64/**
65 * Checkpoint the simulator state to a checkpoint file.
66 *
67 * The checkpoint file name is either the default or the name specified
68 * on the command line with "--checkpoint-file".
69 */
70static __inline void
71sim_checkpoint(void)
72{
73 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_CHECKPOINT);
74}
75
76
77/**
78 * Report whether or not various kinds of simulator tracing are enabled.
79 *
80 * @return The bitwise OR of these values:
81 *
82 * SIM_TRACE_CYCLES (--trace-cycles),
83 * SIM_TRACE_ROUTER (--trace-router),
84 * SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
85 * SIM_TRACE_DISASM (--trace-disasm),
86 * SIM_TRACE_STALL_INFO (--trace-stall-info)
87 * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
88 * SIM_TRACE_L2_CACHE (--trace-l2)
89 * SIM_TRACE_LINES (--trace-lines)
90 */
91static __inline unsigned int
92sim_get_tracing(void)
93{
94 return __insn_mfspr(SPR_SIM_CONTROL) & SIM_TRACE_FLAG_MASK;
95}
96
97
98/**
99 * Turn on or off different kinds of simulator tracing.
100 *
101 * @param mask Either one of these special values:
102 *
103 * SIM_TRACE_NONE (turns off tracing),
104 * SIM_TRACE_ALL (turns on all possible tracing).
105 *
106 * or the bitwise OR of these values:
107 *
108 * SIM_TRACE_CYCLES (--trace-cycles),
109 * SIM_TRACE_ROUTER (--trace-router),
110 * SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
111 * SIM_TRACE_DISASM (--trace-disasm),
112 * SIM_TRACE_STALL_INFO (--trace-stall-info)
113 * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
114 * SIM_TRACE_L2_CACHE (--trace-l2)
115 * SIM_TRACE_LINES (--trace-lines)
116 */
117static __inline void
118sim_set_tracing(unsigned int mask)
119{
120 __insn_mtspr(SPR_SIM_CONTROL, SIM_TRACE_SPR_ARG(mask));
121}
122
123
124/**
125 * Request dumping of different kinds of simulator state.
126 *
127 * @param mask Either this special value:
128 *
129 * SIM_DUMP_ALL (dump all known state)
130 *
131 * or the bitwise OR of these values:
132 *
133 * SIM_DUMP_REGS (the register file),
134 * SIM_DUMP_SPRS (the SPRs),
135 * SIM_DUMP_ITLB (the iTLB),
136 * SIM_DUMP_DTLB (the dTLB),
137 * SIM_DUMP_L1I (the L1 I-cache),
138 * SIM_DUMP_L1D (the L1 D-cache),
139 * SIM_DUMP_L2 (the L2 cache),
140 * SIM_DUMP_SNREGS (the switch register file),
141 * SIM_DUMP_SNITLB (the switch iTLB),
142 * SIM_DUMP_SNL1I (the switch L1 I-cache),
143 * SIM_DUMP_BACKTRACE (the current backtrace)
144 */
145static __inline void
146sim_dump(unsigned int mask)
147{
148 __insn_mtspr(SPR_SIM_CONTROL, SIM_DUMP_SPR_ARG(mask));
149}
150
151
152/**
153 * Print a string to the simulator stdout.
154 *
155 * @param str The string to be written.
156 */
157static __inline void
158sim_print(const char* str)
159{
160 for ( ; *str != '\0'; str++)
161 {
162 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
163 (*str << _SIM_CONTROL_OPERATOR_BITS));
164 }
165 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
166 (SIM_PUTC_FLUSH_BINARY << _SIM_CONTROL_OPERATOR_BITS));
167}
168
169
170/**
171 * Print a string to the simulator stdout.
172 *
173 * @param str The string to be written (a newline is automatically added).
174 */
175static __inline void
176sim_print_string(const char* str)
177{
178 for ( ; *str != '\0'; str++)
179 {
180 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
181 (*str << _SIM_CONTROL_OPERATOR_BITS));
182 }
183 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
184 (SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS));
185}
186
187
188/**
189 * Execute a simulator command string.
190 *
191 * Type 'sim help' at the tile-monitor prompt to learn what commands
192 * are available. Note the use of the tile-monitor "sim" command to
193 * pass commands to the simulator.
194 *
195 * The argument to sim_command() does not include the leading "sim"
196 * prefix used at the tile-monitor prompt; for example, you might call
197 * sim_command("trace disasm").
198 */
199static __inline void
200sim_command(const char* str)
201{
202 int c;
203 do
204 {
205 c = *str++;
206 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_COMMAND |
207 (c << _SIM_CONTROL_OPERATOR_BITS));
208 }
209 while (c);
210}
211
212
213
214#ifndef __DOXYGEN__
215
216/**
217 * The underlying implementation of "_sim_syscall()".
218 *
219 * We use extra "and" instructions to ensure that all the values
220 * we are passing to the simulator are actually valid in the registers
221 * (i.e. returned from memory) prior to the SIM_CONTROL spr.
222 */
223static __inline long _sim_syscall0(int val)
224{
225 long result;
226 __asm__ __volatile__ ("mtspr SIM_CONTROL, r0"
227 : "=R00" (result) : "R00" (val));
228 return result;
229}
230
231static __inline long _sim_syscall1(int val, long arg1)
232{
233 long result;
234 __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
235 : "=R00" (result) : "R00" (val), "R01" (arg1));
236 return result;
237}
238
239static __inline long _sim_syscall2(int val, long arg1, long arg2)
240{
241 long result;
242 __asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
243 : "=R00" (result)
244 : "R00" (val), "R01" (arg1), "R02" (arg2));
245 return result;
246}
247
248/* Note that _sim_syscall3() and higher are technically at risk of
249 receiving an interrupt right before the mtspr bundle, in which case
250 the register values for arguments 3 and up may still be in flight
251 to the core from a stack frame reload. */
252
253static __inline long _sim_syscall3(int val, long arg1, long arg2, long arg3)
254{
255 long result;
256 __asm__ __volatile__ ("{ and zero, r3, r3 };"
257 "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
258 : "=R00" (result)
259 : "R00" (val), "R01" (arg1), "R02" (arg2),
260 "R03" (arg3));
261 return result;
262}
263
264static __inline long _sim_syscall4(int val, long arg1, long arg2, long arg3,
265 long arg4)
266{
267 long result;
268 __asm__ __volatile__ ("{ and zero, r3, r4 };"
269 "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
270 : "=R00" (result)
271 : "R00" (val), "R01" (arg1), "R02" (arg2),
272 "R03" (arg3), "R04" (arg4));
273 return result;
274}
275
276static __inline long _sim_syscall5(int val, long arg1, long arg2, long arg3,
277 long arg4, long arg5)
278{
279 long result;
280 __asm__ __volatile__ ("{ and zero, r3, r4; and zero, r5, r5 };"
281 "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
282 : "=R00" (result)
283 : "R00" (val), "R01" (arg1), "R02" (arg2),
284 "R03" (arg3), "R04" (arg4), "R05" (arg5));
285 return result;
286}
287
288/**
289 * Make a special syscall to the simulator itself, if running under
290 * simulation. This is used as the implementation of other functions
291 * and should not be used outside this file.
292 *
293 * @param syscall_num The simulator syscall number.
294 * @param nr The number of additional arguments provided.
295 *
296 * @return Varies by syscall.
297 */
298#define _sim_syscall(syscall_num, nr, args...) \
299 _sim_syscall##nr( \
300 ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, \
301 ##args)
302
303
304/* Values for the "access_mask" parameters below. */
305#define SIM_WATCHPOINT_READ 1
306#define SIM_WATCHPOINT_WRITE 2
307#define SIM_WATCHPOINT_EXECUTE 4
308
309
310static __inline int
311sim_add_watchpoint(unsigned int process_id,
312 unsigned long address,
313 unsigned long size,
314 unsigned int access_mask,
315 unsigned long user_data)
316{
317 return _sim_syscall(SIM_SYSCALL_ADD_WATCHPOINT, 5, process_id,
318 address, size, access_mask, user_data);
319}
320
321
322static __inline int
323sim_remove_watchpoint(unsigned int process_id,
324 unsigned long address,
325 unsigned long size,
326 unsigned int access_mask,
327 unsigned long user_data)
328{
329 return _sim_syscall(SIM_SYSCALL_REMOVE_WATCHPOINT, 5, process_id,
330 address, size, access_mask, user_data);
331}
332
333
334/**
335 * Return value from sim_query_watchpoint.
336 */
337struct SimQueryWatchpointStatus
338{
339 /**
340 * 0 if a watchpoint fired, 1 if no watchpoint fired, or -1 for
341 * error (meaning a bad process_id).
342 */
343 int syscall_status;
344
345 /**
346 * The address of the watchpoint that fired (this is the address
347 * passed to sim_add_watchpoint, not an address within that range
348 * that actually triggered the watchpoint).
349 */
350 unsigned long address;
351
352 /** The arbitrary user_data installed by sim_add_watchpoint. */
353 unsigned long user_data;
354};
355
356
357static __inline struct SimQueryWatchpointStatus
358sim_query_watchpoint(unsigned int process_id)
359{
360 struct SimQueryWatchpointStatus status;
361 long val = SIM_CONTROL_SYSCALL |
362 (SIM_SYSCALL_QUERY_WATCHPOINT << _SIM_CONTROL_OPERATOR_BITS);
363 __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
364 : "=R00" (status.syscall_status),
365 "=R01" (status.address),
366 "=R02" (status.user_data)
367 : "R00" (val), "R01" (process_id));
368 return status;
369}
370
371
372/* On the simulator, confirm lines have been evicted everywhere. */
373static __inline void
374sim_validate_lines_evicted(unsigned long long pa, unsigned long length)
375{
376#ifdef __LP64__
377 _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 2, pa, length);
378#else
379 _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 4,
380 0 /* dummy */, (long)(pa), (long)(pa >> 32), length);
381#endif
382}
383
384
385/* Return the current CPU speed in cycles per second. */
386static __inline long
387sim_query_cpu_speed(void)
388{
389 return _sim_syscall(SIM_SYSCALL_QUERY_CPU_SPEED, 0);
390}
391
392#endif /* !__DOXYGEN__ */
393
394
395
396
397/**
398 * Modify the shaping parameters of a shim.
399 *
400 * @param shim The shim to modify. One of:
401 * SIM_CONTROL_SHAPING_GBE_0
402 * SIM_CONTROL_SHAPING_GBE_1
403 * SIM_CONTROL_SHAPING_GBE_2
404 * SIM_CONTROL_SHAPING_GBE_3
405 * SIM_CONTROL_SHAPING_XGBE_0
406 * SIM_CONTROL_SHAPING_XGBE_1
407 *
408 * @param type The type of shaping. This should be the same type of
409 * shaping that is already in place on the shim. One of:
410 * SIM_CONTROL_SHAPING_MULTIPLIER
411 * SIM_CONTROL_SHAPING_PPS
412 * SIM_CONTROL_SHAPING_BPS
413 *
414 * @param units The magnitude of the rate. One of:
415 * SIM_CONTROL_SHAPING_UNITS_SINGLE
416 * SIM_CONTROL_SHAPING_UNITS_KILO
417 * SIM_CONTROL_SHAPING_UNITS_MEGA
418 * SIM_CONTROL_SHAPING_UNITS_GIGA
419 *
420 * @param rate The rate to which to change it. This must fit in
421 * SIM_CONTROL_SHAPING_RATE_BITS bits or a warning is issued and
422 * the shaping is not changed.
423 *
424 * @return 0 if no problems were detected in the arguments to sim_set_shaping
425 * or 1 if problems were detected (for example, rate does not fit in 17 bits).
426 */
427static __inline int
428sim_set_shaping(unsigned shim,
429 unsigned type,
430 unsigned units,
431 unsigned rate)
432{
433 if ((rate & ~((1 << SIM_CONTROL_SHAPING_RATE_BITS) - 1)) != 0)
434 return 1;
435
436 __insn_mtspr(SPR_SIM_CONTROL, SIM_SHAPING_SPR_ARG(shim, type, units, rate));
437 return 0;
438}
439
440#ifdef __tilegx__
441
442/** Enable a set of mPIPE links. Pass a -1 link_mask to enable all links. */
443static __inline void
444sim_enable_mpipe_links(unsigned mpipe, unsigned long link_mask)
445{
446 __insn_mtspr(SPR_SIM_CONTROL,
447 (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
448 (mpipe << 8) | (1 << 16) | ((uint_reg_t)link_mask << 32)));
449}
450
451/** Disable a set of mPIPE links. Pass a -1 link_mask to disable all links. */
452static __inline void
453sim_disable_mpipe_links(unsigned mpipe, unsigned long link_mask)
454{
455 __insn_mtspr(SPR_SIM_CONTROL,
456 (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
457 (mpipe << 8) | (0 << 16) | ((uint_reg_t)link_mask << 32)));
458}
459
460#endif /* __tilegx__ */
461
462
463/*
464 * An API for changing "functional" mode.
465 */
466
467#ifndef __DOXYGEN__
468
469#define sim_enable_functional() \
470 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_ENABLE_FUNCTIONAL)
471
472#define sim_disable_functional() \
473 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_DISABLE_FUNCTIONAL)
474
475#endif /* __DOXYGEN__ */
476
477
478/*
479 * Profiler support.
480 */
481
482/**
483 * Turn profiling on for the current task.
484 *
485 * Note that this has no effect if run in an environment without
486 * profiling support (thus, the proper flags to the simulator must
487 * be supplied).
488 */
489static __inline void
490sim_profiler_enable(void)
491{
492 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_ENABLE);
493}
494
495
496/** Turn profiling off for the current task. */
497static __inline void
498sim_profiler_disable(void)
499{
500 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_DISABLE);
501}
502
503
504/**
505 * Turn profiling on or off for the current task.
506 *
507 * @param enabled If true, turns on profiling. If false, turns it off.
508 *
509 * Note that this has no effect if run in an environment without
510 * profiling support (thus, the proper flags to the simulator must
511 * be supplied).
512 */
513static __inline void
514sim_profiler_set_enabled(int enabled)
515{
516 int val =
517 enabled ? SIM_CONTROL_PROFILER_ENABLE : SIM_CONTROL_PROFILER_DISABLE;
518 __insn_mtspr(SPR_SIM_CONTROL, val);
519}
520
521
522/**
523 * Return true if and only if profiling is currently enabled
524 * for the current task.
525 *
526 * This returns false even if sim_profiler_enable() was called
527 * if the current execution environment does not support profiling.
528 */
529static __inline int
530sim_profiler_is_enabled(void)
531{
532 return ((__insn_mfspr(SPR_SIM_CONTROL) & SIM_PROFILER_ENABLED_MASK) != 0);
533}
534
535
536/**
537 * Reset profiling counters to zero for the current task.
538 *
539 * Resetting can be done while profiling is enabled. It does not affect
540 * the chip-wide profiling counters.
541 */
542static __inline void
543sim_profiler_clear(void)
544{
545 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_CLEAR);
546}
547
548
549/**
550 * Enable specified chip-level profiling counters.
551 *
552 * Does not affect the per-task profiling counters.
553 *
554 * @param mask Either this special value:
555 *
556 * SIM_CHIP_ALL (enables all chip-level components).
557 *
558 * or the bitwise OR of these values:
559 *
560 * SIM_CHIP_MEMCTL (enable all memory controllers)
561 * SIM_CHIP_XAUI (enable all XAUI controllers)
562 * SIM_CHIP_MPIPE (enable all MPIPE controllers)
563 */
564static __inline void
565sim_profiler_chip_enable(unsigned int mask)
566{
567 __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask));
568}
569
570
571/**
572 * Disable specified chip-level profiling counters.
573 *
574 * Does not affect the per-task profiling counters.
575 *
576 * @param mask Either this special value:
577 *
578 * SIM_CHIP_ALL (disables all chip-level components).
579 *
580 * or the bitwise OR of these values:
581 *
582 * SIM_CHIP_MEMCTL (disable all memory controllers)
583 * SIM_CHIP_XAUI (disable all XAUI controllers)
584 * SIM_CHIP_MPIPE (disable all MPIPE controllers)
585 */
586static __inline void
587sim_profiler_chip_disable(unsigned int mask)
588{
589 __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask));
590}
591
592
593/**
594 * Reset specified chip-level profiling counters to zero.
595 *
596 * Does not affect the per-task profiling counters.
597 *
598 * @param mask Either this special value:
599 *
600 * SIM_CHIP_ALL (clears all chip-level components).
601 *
602 * or the bitwise OR of these values:
603 *
604 * SIM_CHIP_MEMCTL (clear all memory controllers)
605 * SIM_CHIP_XAUI (clear all XAUI controllers)
606 * SIM_CHIP_MPIPE (clear all MPIPE controllers)
607 */
608static __inline void
609sim_profiler_chip_clear(unsigned int mask)
610{
611 __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask));
612}
613
614
615/*
616 * Event support.
617 */
618
619#ifndef __DOXYGEN__
620
621static __inline void
622sim_event_begin(unsigned int x)
623{
624#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
625 __insn_mtspr(SPR_EVENT_BEGIN, x);
626#endif
627}
628
629static __inline void
630sim_event_end(unsigned int x)
631{
632#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
633 __insn_mtspr(SPR_EVENT_END, x);
634#endif
635}
636
637#endif /* !__DOXYGEN__ */
638
639#endif /* !__ASSEMBLER__ */
640
641#endif /* !__ARCH_SIM_H__ */
642
643/** @} */
diff --git a/arch/tile/include/arch/sim_def.h b/arch/tile/include/arch/sim_def.h
new file mode 100644
index 00000000000..4b44a2b6a09
--- /dev/null
+++ b/arch/tile/include/arch/sim_def.h
@@ -0,0 +1,505 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file
17 *
18 * Some low-level simulator definitions.
19 */
20
21#ifndef __ARCH_SIM_DEF_H__
22#define __ARCH_SIM_DEF_H__
23
24
25/**
26 * Internal: the low bits of the SIM_CONTROL_* SPR values specify
27 * the operation to perform, and the remaining bits are
28 * an operation-specific parameter (often unused).
29 */
30#define _SIM_CONTROL_OPERATOR_BITS 8
31
32
33/*
34 * Values which can be written to SPR_SIM_CONTROL.
35 */
36
37/** If written to SPR_SIM_CONTROL, stops profiling. */
38#define SIM_CONTROL_PROFILER_DISABLE 0
39
40/** If written to SPR_SIM_CONTROL, starts profiling. */
41#define SIM_CONTROL_PROFILER_ENABLE 1
42
43/** If written to SPR_SIM_CONTROL, clears profiling counters. */
44#define SIM_CONTROL_PROFILER_CLEAR 2
45
46/** If written to SPR_SIM_CONTROL, checkpoints the simulator. */
47#define SIM_CONTROL_CHECKPOINT 3
48
49/**
50 * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
51 * sets the tracing mask to the given mask. See "sim_set_tracing()".
52 */
53#define SIM_CONTROL_SET_TRACING 4
54
55/**
56 * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
57 * dumps the requested items of machine state to the log.
58 */
59#define SIM_CONTROL_DUMP 5
60
61/** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */
62#define SIM_CONTROL_PROFILER_CHIP_CLEAR 6
63
64/** If written to SPR_SIM_CONTROL, disables chip-level profiling. */
65#define SIM_CONTROL_PROFILER_CHIP_DISABLE 7
66
67/** If written to SPR_SIM_CONTROL, enables chip-level profiling. */
68#define SIM_CONTROL_PROFILER_CHIP_ENABLE 8
69
70/** If written to SPR_SIM_CONTROL, enables chip-level functional mode */
71#define SIM_CONTROL_ENABLE_FUNCTIONAL 9
72
73/** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */
74#define SIM_CONTROL_DISABLE_FUNCTIONAL 10
75
76/**
77 * If written to SPR_SIM_CONTROL, enables chip-level functional mode.
78 * All tiles must perform this write for functional mode to be enabled.
79 * Ignored in naked boot mode unless --functional is specified.
80 * WARNING: Only the hypervisor startup code should use this!
81 */
82#define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11
83
84/**
85 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
86 * writes a string directly to the simulator output. Written to once for
87 * each character in the string, plus a final NUL. Instead of NUL,
88 * you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY".
89 */
90/* ISSUE: Document the meaning of "newline", and the handling of NUL. */
91#define SIM_CONTROL_PUTC 12
92
93/**
94 * If written to SPR_SIM_CONTROL, clears the --grind-coherence state for
95 * this core. This is intended to be used before a loop that will
96 * invalidate the cache by loading new data and evicting all current data.
97 * Generally speaking, this API should only be used by system code.
98 */
99#define SIM_CONTROL_GRINDER_CLEAR 13
100
101/** If written to SPR_SIM_CONTROL, shuts down the simulator. */
102#define SIM_CONTROL_SHUTDOWN 14
103
104/**
105 * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
106 * indicates that a fork syscall just created the given process.
107 */
108#define SIM_CONTROL_OS_FORK 15
109
110/**
111 * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
112 * indicates that an exit syscall was just executed by the given process.
113 */
114#define SIM_CONTROL_OS_EXIT 16
115
116/**
117 * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
118 * indicates that the OS just switched to the given process.
119 */
120#define SIM_CONTROL_OS_SWITCH 17
121
122/**
123 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
124 * indicates that an exec syscall was just executed. Written to once for
125 * each character in the executable name, plus a final NUL.
126 */
127#define SIM_CONTROL_OS_EXEC 18
128
129/**
130 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
131 * indicates that an interpreter (PT_INTERP) was loaded. Written to once
132 * for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a
133 * hex load address starting with "0x", and "PATH" is the executable name.
134 */
135#define SIM_CONTROL_OS_INTERP 19
136
137/**
138 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
139 * indicates that a dll was loaded. Written to once for each character
140 * in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load
141 * address starting with "0x", and "PATH" is the executable name.
142 */
143#define SIM_CONTROL_DLOPEN 20
144
145/**
146 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
147 * indicates that a dll was unloaded. Written to once for each character
148 * in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load
149 * address starting with "0x".
150 */
151#define SIM_CONTROL_DLCLOSE 21
152
153/**
154 * If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8),
155 * indicates whether to allow data reads to remotely-cached
156 * dirty cache lines to be cached locally without grinder warnings or
157 * assertions (used by Linux kernel fast memcpy).
158 */
159#define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22
160
161/** If written to SPR_SIM_CONTROL, enables memory tracing. */
162#define SIM_CONTROL_ENABLE_MEM_LOGGING 23
163
164/** If written to SPR_SIM_CONTROL, disables memory tracing. */
165#define SIM_CONTROL_DISABLE_MEM_LOGGING 24
166
167/**
168 * If written to SPR_SIM_CONTROL, changes the shaping parameters of one of
169 * the gbe or xgbe shims. Must specify the shim id, the type, the units, and
170 * the rate, as defined in SIM_SHAPING_SPR_ARG.
171 */
172#define SIM_CONTROL_SHAPING 25
173
174/**
175 * If written to SPR_SIM_CONTROL, combined with character (shifted by 8),
176 * requests that a simulator command be executed. Written to once for each
177 * character in the command, plus a final NUL.
178 */
179#define SIM_CONTROL_COMMAND 26
180
181/**
182 * If written to SPR_SIM_CONTROL, indicates that the simulated system
183 * is panicking, to allow debugging via --debug-on-panic.
184 */
185#define SIM_CONTROL_PANIC 27
186
187/**
188 * If written to SPR_SIM_CONTROL, triggers a simulator syscall.
189 * See "sim_syscall()" for more info.
190 */
191#define SIM_CONTROL_SYSCALL 32
192
193/**
194 * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
195 * provides the pid that subsequent SIM_CONTROL_OS_FORK writes should
196 * use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH.
197 */
198#define SIM_CONTROL_OS_FORK_PARENT 33
199
200/**
201 * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
202 * (shifted by 8), clears the pending magic data section. The cleared
203 * pending magic data section and any subsequently appended magic bytes
204 * will only take effect when the classifier blast programmer is run.
205 */
206#define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34
207
208/**
209 * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
210 * (shifted by 8) and a byte of data (shifted by 16), appends that byte
211 * to the shim's pending magic data section. The pending magic data
212 * section takes effect when the classifier blast programmer is run.
213 */
214#define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35
215
216/**
217 * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
218 * (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a
219 * mask of links (shifted by 32), enable or disable the corresponding
220 * mPIPE links.
221 */
222#define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36
223
224
225/*
226 * Syscall numbers for use with "sim_syscall()".
227 */
228
229/** Syscall number for sim_add_watchpoint(). */
230#define SIM_SYSCALL_ADD_WATCHPOINT 2
231
232/** Syscall number for sim_remove_watchpoint(). */
233#define SIM_SYSCALL_REMOVE_WATCHPOINT 3
234
235/** Syscall number for sim_query_watchpoint(). */
236#define SIM_SYSCALL_QUERY_WATCHPOINT 4
237
238/**
239 * Syscall number that asserts that the cache lines whose 64-bit PA
240 * is passed as the second argument to sim_syscall(), and over a
241 * range passed as the third argument, are no longer in cache.
242 * The simulator raises an error if this is not the case.
243 */
244#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
245
246/** Syscall number for sim_query_cpu_speed(). */
247#define SIM_SYSCALL_QUERY_CPU_SPEED 6
248
249
250/*
251 * Bit masks which can be shifted by 8, combined with
252 * SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL.
253 */
254
255/**
256 * @addtogroup arch_sim
257 * @{
258 */
259
260/** Enable --trace-cycle when passed to simulator_set_tracing(). */
261#define SIM_TRACE_CYCLES 0x01
262
263/** Enable --trace-router when passed to simulator_set_tracing(). */
264#define SIM_TRACE_ROUTER 0x02
265
266/** Enable --trace-register-writes when passed to simulator_set_tracing(). */
267#define SIM_TRACE_REGISTER_WRITES 0x04
268
269/** Enable --trace-disasm when passed to simulator_set_tracing(). */
270#define SIM_TRACE_DISASM 0x08
271
272/** Enable --trace-stall-info when passed to simulator_set_tracing(). */
273#define SIM_TRACE_STALL_INFO 0x10
274
275/** Enable --trace-memory-controller when passed to simulator_set_tracing(). */
276#define SIM_TRACE_MEMORY_CONTROLLER 0x20
277
278/** Enable --trace-l2 when passed to simulator_set_tracing(). */
279#define SIM_TRACE_L2_CACHE 0x40
280
281/** Enable --trace-lines when passed to simulator_set_tracing(). */
282#define SIM_TRACE_LINES 0x80
283
284/** Turn off all tracing when passed to simulator_set_tracing(). */
285#define SIM_TRACE_NONE 0
286
287/** Turn on all tracing when passed to simulator_set_tracing(). */
288#define SIM_TRACE_ALL (-1)
289
290/** @} */
291
292/** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */
293#define SIM_TRACE_SPR_ARG(mask) \
294 (SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
295
296
297/*
298 * Bit masks which can be shifted by 8, combined with
299 * SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL.
300 */
301
302/**
303 * @addtogroup arch_sim
304 * @{
305 */
306
307/** Dump the general-purpose registers. */
308#define SIM_DUMP_REGS 0x001
309
310/** Dump the SPRs. */
311#define SIM_DUMP_SPRS 0x002
312
313/** Dump the ITLB. */
314#define SIM_DUMP_ITLB 0x004
315
316/** Dump the DTLB. */
317#define SIM_DUMP_DTLB 0x008
318
319/** Dump the L1 I-cache. */
320#define SIM_DUMP_L1I 0x010
321
322/** Dump the L1 D-cache. */
323#define SIM_DUMP_L1D 0x020
324
325/** Dump the L2 cache. */
326#define SIM_DUMP_L2 0x040
327
328/** Dump the switch registers. */
329#define SIM_DUMP_SNREGS 0x080
330
331/** Dump the switch ITLB. */
332#define SIM_DUMP_SNITLB 0x100
333
334/** Dump the switch L1 I-cache. */
335#define SIM_DUMP_SNL1I 0x200
336
337/** Dump the current backtrace. */
338#define SIM_DUMP_BACKTRACE 0x400
339
340/** Only dump valid lines in caches. */
341#define SIM_DUMP_VALID_LINES 0x800
342
343/** Dump everything that is dumpable. */
344#define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES)
345
346/** @} */
347
348/** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */
349#define SIM_DUMP_SPR_ARG(mask) \
350 (SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
351
352
353/*
354 * Bit masks which can be shifted by 8, combined with
355 * SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL.
356 */
357
358/**
359 * @addtogroup arch_sim
360 * @{
361 */
362
363/** Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
364#define SIM_CHIP_MEMCTL 0x001
365
366/** Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
367#define SIM_CHIP_XAUI 0x002
368
369/** Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
370#define SIM_CHIP_PCIE 0x004
371
372/** Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
373#define SIM_CHIP_MPIPE 0x008
374
375/** Use with with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
376#define SIM_CHIP_TRIO 0x010
377
378/** Reference all chip devices. */
379#define SIM_CHIP_ALL (-1)
380
381/** @} */
382
383/** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */
384#define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \
385 (SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
386
387/** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/
388#define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \
389 (SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
390
391/** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */
392#define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \
393 (SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
394
395
396
397/* Shim bitrate controls. */
398
399/** The number of bits used to store the shim id. */
400#define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3
401
402/**
403 * @addtogroup arch_sim
404 * @{
405 */
406
407/** Change the gbe 0 bitrate. */
408#define SIM_CONTROL_SHAPING_GBE_0 0x0
409
410/** Change the gbe 1 bitrate. */
411#define SIM_CONTROL_SHAPING_GBE_1 0x1
412
413/** Change the gbe 2 bitrate. */
414#define SIM_CONTROL_SHAPING_GBE_2 0x2
415
416/** Change the gbe 3 bitrate. */
417#define SIM_CONTROL_SHAPING_GBE_3 0x3
418
419/** Change the xgbe 0 bitrate. */
420#define SIM_CONTROL_SHAPING_XGBE_0 0x4
421
422/** Change the xgbe 1 bitrate. */
423#define SIM_CONTROL_SHAPING_XGBE_1 0x5
424
425/** The type of shaping to do. */
426#define SIM_CONTROL_SHAPING_TYPE_BITS 2
427
428/** Control the multiplier. */
429#define SIM_CONTROL_SHAPING_MULTIPLIER 0
430
431/** Control the PPS. */
432#define SIM_CONTROL_SHAPING_PPS 1
433
434/** Control the BPS. */
435#define SIM_CONTROL_SHAPING_BPS 2
436
437/** The number of bits for the units for the shaping parameter. */
438#define SIM_CONTROL_SHAPING_UNITS_BITS 2
439
440/** Provide a number in single units. */
441#define SIM_CONTROL_SHAPING_UNITS_SINGLE 0
442
443/** Provide a number in kilo units. */
444#define SIM_CONTROL_SHAPING_UNITS_KILO 1
445
446/** Provide a number in mega units. */
447#define SIM_CONTROL_SHAPING_UNITS_MEGA 2
448
449/** Provide a number in giga units. */
450#define SIM_CONTROL_SHAPING_UNITS_GIGA 3
451
452/** @} */
453
454/** How many bits are available for the rate. */
455#define SIM_CONTROL_SHAPING_RATE_BITS \
456 (32 - (_SIM_CONTROL_OPERATOR_BITS + \
457 SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
458 SIM_CONTROL_SHAPING_TYPE_BITS + \
459 SIM_CONTROL_SHAPING_UNITS_BITS))
460
461/** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */
462#define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \
463 (SIM_CONTROL_SHAPING | \
464 ((shim) | \
465 ((type) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS)) | \
466 ((units) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
467 SIM_CONTROL_SHAPING_TYPE_BITS)) | \
468 ((rate) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
469 SIM_CONTROL_SHAPING_TYPE_BITS + \
470 SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS)
471
472
473/*
474 * Values returned when reading SPR_SIM_CONTROL.
475 * ISSUE: These names should share a longer common prefix.
476 */
477
478/**
479 * When reading SPR_SIM_CONTROL, the mask of simulator tracing bits
480 * (SIM_TRACE_xxx values).
481 */
482#define SIM_TRACE_FLAG_MASK 0xFFFF
483
484/** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */
485#define SIM_PROFILER_ENABLED_MASK 0x10000
486
487
488/*
489 * Special arguments for "SIM_CONTROL_PUTC".
490 */
491
492/**
493 * Flag value for forcing a PUTC string-flush, including
494 * coordinate/cycle prefix and newline.
495 */
496#define SIM_PUTC_FLUSH_STRING 0x100
497
498/**
499 * Flag value for forcing a PUTC binary-data-flush, which skips the
500 * prefix and does not append a newline.
501 */
502#define SIM_PUTC_FLUSH_BINARY 0x101
503
504
505#endif /* __ARCH_SIM_DEF_H__ */
diff --git a/arch/tile/include/arch/spr_def_32.h b/arch/tile/include/arch/spr_def_32.h
new file mode 100644
index 00000000000..bbc1f4c924e
--- /dev/null
+++ b/arch/tile/include/arch/spr_def_32.h
@@ -0,0 +1,201 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __DOXYGEN__
16
17#ifndef __ARCH_SPR_DEF_H__
18#define __ARCH_SPR_DEF_H__
19
20#define SPR_AUX_PERF_COUNT_0 0x6005
21#define SPR_AUX_PERF_COUNT_1 0x6006
22#define SPR_AUX_PERF_COUNT_CTL 0x6007
23#define SPR_AUX_PERF_COUNT_STS 0x6008
24#define SPR_CYCLE_HIGH 0x4e06
25#define SPR_CYCLE_LOW 0x4e07
26#define SPR_DMA_BYTE 0x3900
27#define SPR_DMA_CHUNK_SIZE 0x3901
28#define SPR_DMA_CTR 0x3902
29#define SPR_DMA_CTR__REQUEST_MASK 0x1
30#define SPR_DMA_CTR__SUSPEND_MASK 0x2
31#define SPR_DMA_DST_ADDR 0x3903
32#define SPR_DMA_DST_CHUNK_ADDR 0x3904
33#define SPR_DMA_SRC_ADDR 0x3905
34#define SPR_DMA_SRC_CHUNK_ADDR 0x3906
35#define SPR_DMA_STATUS__DONE_MASK 0x1
36#define SPR_DMA_STATUS__BUSY_MASK 0x2
37#define SPR_DMA_STATUS__RUNNING_MASK 0x10
38#define SPR_DMA_STRIDE 0x3907
39#define SPR_DMA_USER_STATUS 0x3908
40#define SPR_DONE 0x4e08
41#define SPR_EVENT_BEGIN 0x4e0d
42#define SPR_EVENT_END 0x4e0e
43#define SPR_EX_CONTEXT_0_0 0x4a05
44#define SPR_EX_CONTEXT_0_1 0x4a06
45#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
46#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
47#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
48#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
49#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
50#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
51#define SPR_EX_CONTEXT_1_0 0x4805
52#define SPR_EX_CONTEXT_1_1 0x4806
53#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
54#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
55#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
56#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
57#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
58#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
59#define SPR_EX_CONTEXT_2_0 0x4605
60#define SPR_EX_CONTEXT_2_1 0x4606
61#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
62#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
63#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
64#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
65#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
66#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
67#define SPR_FAIL 0x4e09
68#define SPR_INTCTRL_0_STATUS 0x4a07
69#define SPR_INTCTRL_1_STATUS 0x4807
70#define SPR_INTCTRL_2_STATUS 0x4607
71#define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a
72#define SPR_INTERRUPT_MASK_0_0 0x4a08
73#define SPR_INTERRUPT_MASK_0_1 0x4a09
74#define SPR_INTERRUPT_MASK_1_0 0x4809
75#define SPR_INTERRUPT_MASK_1_1 0x480a
76#define SPR_INTERRUPT_MASK_2_0 0x4608
77#define SPR_INTERRUPT_MASK_2_1 0x4609
78#define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a
79#define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b
80#define SPR_INTERRUPT_MASK_RESET_1_0 0x480b
81#define SPR_INTERRUPT_MASK_RESET_1_1 0x480c
82#define SPR_INTERRUPT_MASK_RESET_2_0 0x460a
83#define SPR_INTERRUPT_MASK_RESET_2_1 0x460b
84#define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c
85#define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d
86#define SPR_INTERRUPT_MASK_SET_1_0 0x480d
87#define SPR_INTERRUPT_MASK_SET_1_1 0x480e
88#define SPR_INTERRUPT_MASK_SET_2_0 0x460c
89#define SPR_INTERRUPT_MASK_SET_2_1 0x460d
90#define SPR_MPL_DMA_CPL_SET_0 0x5800
91#define SPR_MPL_DMA_CPL_SET_1 0x5801
92#define SPR_MPL_DMA_CPL_SET_2 0x5802
93#define SPR_MPL_DMA_NOTIFY_SET_0 0x3800
94#define SPR_MPL_DMA_NOTIFY_SET_1 0x3801
95#define SPR_MPL_DMA_NOTIFY_SET_2 0x3802
96#define SPR_MPL_INTCTRL_0_SET_0 0x4a00
97#define SPR_MPL_INTCTRL_0_SET_1 0x4a01
98#define SPR_MPL_INTCTRL_0_SET_2 0x4a02
99#define SPR_MPL_INTCTRL_1_SET_0 0x4800
100#define SPR_MPL_INTCTRL_1_SET_1 0x4801
101#define SPR_MPL_INTCTRL_1_SET_2 0x4802
102#define SPR_MPL_INTCTRL_2_SET_0 0x4600
103#define SPR_MPL_INTCTRL_2_SET_1 0x4601
104#define SPR_MPL_INTCTRL_2_SET_2 0x4602
105#define SPR_MPL_SN_ACCESS_SET_0 0x0800
106#define SPR_MPL_SN_ACCESS_SET_1 0x0801
107#define SPR_MPL_SN_ACCESS_SET_2 0x0802
108#define SPR_MPL_SN_CPL_SET_0 0x5a00
109#define SPR_MPL_SN_CPL_SET_1 0x5a01
110#define SPR_MPL_SN_CPL_SET_2 0x5a02
111#define SPR_MPL_SN_FIREWALL_SET_0 0x2c00
112#define SPR_MPL_SN_FIREWALL_SET_1 0x2c01
113#define SPR_MPL_SN_FIREWALL_SET_2 0x2c02
114#define SPR_MPL_SN_NOTIFY_SET_0 0x2a00
115#define SPR_MPL_SN_NOTIFY_SET_1 0x2a01
116#define SPR_MPL_SN_NOTIFY_SET_2 0x2a02
117#define SPR_MPL_UDN_ACCESS_SET_0 0x0c00
118#define SPR_MPL_UDN_ACCESS_SET_1 0x0c01
119#define SPR_MPL_UDN_ACCESS_SET_2 0x0c02
120#define SPR_MPL_UDN_AVAIL_SET_0 0x4000
121#define SPR_MPL_UDN_AVAIL_SET_1 0x4001
122#define SPR_MPL_UDN_AVAIL_SET_2 0x4002
123#define SPR_MPL_UDN_CA_SET_0 0x3c00
124#define SPR_MPL_UDN_CA_SET_1 0x3c01
125#define SPR_MPL_UDN_CA_SET_2 0x3c02
126#define SPR_MPL_UDN_COMPLETE_SET_0 0x1400
127#define SPR_MPL_UDN_COMPLETE_SET_1 0x1401
128#define SPR_MPL_UDN_COMPLETE_SET_2 0x1402
129#define SPR_MPL_UDN_FIREWALL_SET_0 0x3000
130#define SPR_MPL_UDN_FIREWALL_SET_1 0x3001
131#define SPR_MPL_UDN_FIREWALL_SET_2 0x3002
132#define SPR_MPL_UDN_REFILL_SET_0 0x1000
133#define SPR_MPL_UDN_REFILL_SET_1 0x1001
134#define SPR_MPL_UDN_REFILL_SET_2 0x1002
135#define SPR_MPL_UDN_TIMER_SET_0 0x3600
136#define SPR_MPL_UDN_TIMER_SET_1 0x3601
137#define SPR_MPL_UDN_TIMER_SET_2 0x3602
138#define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00
139#define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01
140#define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02
141#define SPR_PASS 0x4e0b
142#define SPR_PERF_COUNT_0 0x4205
143#define SPR_PERF_COUNT_1 0x4206
144#define SPR_PERF_COUNT_CTL 0x4207
145#define SPR_PERF_COUNT_DN_CTL 0x4210
146#define SPR_PERF_COUNT_STS 0x4208
147#define SPR_PROC_STATUS 0x4f00
148#define SPR_SIM_CONTROL 0x4e0c
149#define SPR_SNCTL 0x0805
150#define SPR_SNCTL__FRZFABRIC_MASK 0x1
151#define SPR_SNCTL__FRZPROC_MASK 0x2
152#define SPR_SNPC 0x080b
153#define SPR_SNSTATIC 0x080c
154#define SPR_SYSTEM_SAVE_0_0 0x4b00
155#define SPR_SYSTEM_SAVE_0_1 0x4b01
156#define SPR_SYSTEM_SAVE_0_2 0x4b02
157#define SPR_SYSTEM_SAVE_0_3 0x4b03
158#define SPR_SYSTEM_SAVE_1_0 0x4900
159#define SPR_SYSTEM_SAVE_1_1 0x4901
160#define SPR_SYSTEM_SAVE_1_2 0x4902
161#define SPR_SYSTEM_SAVE_1_3 0x4903
162#define SPR_SYSTEM_SAVE_2_0 0x4700
163#define SPR_SYSTEM_SAVE_2_1 0x4701
164#define SPR_SYSTEM_SAVE_2_2 0x4702
165#define SPR_SYSTEM_SAVE_2_3 0x4703
166#define SPR_TILE_COORD 0x4c17
167#define SPR_TILE_RTF_HWM 0x4e10
168#define SPR_TILE_TIMER_CONTROL 0x3205
169#define SPR_TILE_WRITE_PENDING 0x4e0f
170#define SPR_UDN_AVAIL_EN 0x4005
171#define SPR_UDN_CA_DATA 0x0d00
172#define SPR_UDN_DATA_AVAIL 0x0d03
173#define SPR_UDN_DEADLOCK_TIMEOUT 0x3606
174#define SPR_UDN_DEMUX_CA_COUNT 0x0c05
175#define SPR_UDN_DEMUX_COUNT_0 0x0c06
176#define SPR_UDN_DEMUX_COUNT_1 0x0c07
177#define SPR_UDN_DEMUX_COUNT_2 0x0c08
178#define SPR_UDN_DEMUX_COUNT_3 0x0c09
179#define SPR_UDN_DEMUX_CTL 0x0c0a
180#define SPR_UDN_DEMUX_QUEUE_SEL 0x0c0c
181#define SPR_UDN_DEMUX_STATUS 0x0c0d
182#define SPR_UDN_DEMUX_WRITE_FIFO 0x0c0e
183#define SPR_UDN_DIRECTION_PROTECT 0x3005
184#define SPR_UDN_REFILL_EN 0x1005
185#define SPR_UDN_SP_FIFO_DATA 0x0c11
186#define SPR_UDN_SP_FIFO_SEL 0x0c12
187#define SPR_UDN_SP_FREEZE 0x0c13
188#define SPR_UDN_SP_FREEZE__SP_FRZ_MASK 0x1
189#define SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
190#define SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
191#define SPR_UDN_SP_STATE 0x0c14
192#define SPR_UDN_TAG_0 0x0c15
193#define SPR_UDN_TAG_1 0x0c16
194#define SPR_UDN_TAG_2 0x0c17
195#define SPR_UDN_TAG_3 0x0c18
196#define SPR_UDN_TAG_VALID 0x0c19
197#define SPR_UDN_TILE_COORD 0x0c1a
198
199#endif /* !defined(__ARCH_SPR_DEF_H__) */
200
201#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/arch/spr_def_64.h b/arch/tile/include/arch/spr_def_64.h
new file mode 100644
index 00000000000..cd3e5f95d5f
--- /dev/null
+++ b/arch/tile/include/arch/spr_def_64.h
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __DOXYGEN__
16
17#ifndef __ARCH_SPR_DEF_H__
18#define __ARCH_SPR_DEF_H__
19
20#define SPR_AUX_PERF_COUNT_0 0x2105
21#define SPR_AUX_PERF_COUNT_1 0x2106
22#define SPR_AUX_PERF_COUNT_CTL 0x2107
23#define SPR_AUX_PERF_COUNT_STS 0x2108
24#define SPR_CMPEXCH_VALUE 0x2780
25#define SPR_CYCLE 0x2781
26#define SPR_DONE 0x2705
27#define SPR_DSTREAM_PF 0x2706
28#define SPR_EVENT_BEGIN 0x2782
29#define SPR_EVENT_END 0x2783
30#define SPR_EX_CONTEXT_0_0 0x2580
31#define SPR_EX_CONTEXT_0_1 0x2581
32#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
33#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
34#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
35#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
36#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
37#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
38#define SPR_EX_CONTEXT_1_0 0x2480
39#define SPR_EX_CONTEXT_1_1 0x2481
40#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
41#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
42#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
43#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
44#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
45#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
46#define SPR_EX_CONTEXT_2_0 0x2380
47#define SPR_EX_CONTEXT_2_1 0x2381
48#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
49#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
50#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
51#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
52#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
53#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
54#define SPR_FAIL 0x2707
55#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
56#define SPR_INTCTRL_0_STATUS 0x2505
57#define SPR_INTCTRL_1_STATUS 0x2405
58#define SPR_INTCTRL_2_STATUS 0x2305
59#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
60#define SPR_INTERRUPT_MASK_0 0x2506
61#define SPR_INTERRUPT_MASK_1 0x2406
62#define SPR_INTERRUPT_MASK_2 0x2306
63#define SPR_INTERRUPT_MASK_RESET_0 0x2507
64#define SPR_INTERRUPT_MASK_RESET_1 0x2407
65#define SPR_INTERRUPT_MASK_RESET_2 0x2307
66#define SPR_INTERRUPT_MASK_SET_0 0x2508
67#define SPR_INTERRUPT_MASK_SET_1 0x2408
68#define SPR_INTERRUPT_MASK_SET_2 0x2308
69#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
70#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
71#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
72#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
73#define SPR_IPI_EVENT_0 0x1f05
74#define SPR_IPI_EVENT_1 0x1e05
75#define SPR_IPI_EVENT_2 0x1d05
76#define SPR_IPI_EVENT_RESET_0 0x1f06
77#define SPR_IPI_EVENT_RESET_1 0x1e06
78#define SPR_IPI_EVENT_RESET_2 0x1d06
79#define SPR_IPI_EVENT_SET_0 0x1f07
80#define SPR_IPI_EVENT_SET_1 0x1e07
81#define SPR_IPI_EVENT_SET_2 0x1d07
82#define SPR_IPI_MASK_0 0x1f08
83#define SPR_IPI_MASK_1 0x1e08
84#define SPR_IPI_MASK_2 0x1d08
85#define SPR_IPI_MASK_RESET_0 0x1f09
86#define SPR_IPI_MASK_RESET_1 0x1e09
87#define SPR_IPI_MASK_RESET_2 0x1d09
88#define SPR_IPI_MASK_SET_0 0x1f0a
89#define SPR_IPI_MASK_SET_1 0x1e0a
90#define SPR_IPI_MASK_SET_2 0x1d0a
91#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
92#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
93#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
94#define SPR_MPL_INTCTRL_0_SET_0 0x2500
95#define SPR_MPL_INTCTRL_0_SET_1 0x2501
96#define SPR_MPL_INTCTRL_0_SET_2 0x2502
97#define SPR_MPL_INTCTRL_1_SET_0 0x2400
98#define SPR_MPL_INTCTRL_1_SET_1 0x2401
99#define SPR_MPL_INTCTRL_1_SET_2 0x2402
100#define SPR_MPL_INTCTRL_2_SET_0 0x2300
101#define SPR_MPL_INTCTRL_2_SET_1 0x2301
102#define SPR_MPL_INTCTRL_2_SET_2 0x2302
103#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
104#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
105#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
106#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
107#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
108#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
109#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
110#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
111#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
112#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
113#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
114#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
115#define SPR_MPL_UDN_TIMER_SET_0 0x1900
116#define SPR_MPL_UDN_TIMER_SET_1 0x1901
117#define SPR_MPL_UDN_TIMER_SET_2 0x1902
118#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
119#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
120#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
121#define SPR_PASS 0x2709
122#define SPR_PERF_COUNT_0 0x2005
123#define SPR_PERF_COUNT_1 0x2006
124#define SPR_PERF_COUNT_CTL 0x2007
125#define SPR_PERF_COUNT_DN_CTL 0x2008
126#define SPR_PERF_COUNT_STS 0x2009
127#define SPR_PROC_STATUS 0x2784
128#define SPR_SIM_CONTROL 0x2785
129#define SPR_SINGLE_STEP_CONTROL_0 0x0405
130#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
131#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
132#define SPR_SINGLE_STEP_CONTROL_1 0x0305
133#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
134#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
135#define SPR_SINGLE_STEP_CONTROL_2 0x0205
136#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
137#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
138#define SPR_SINGLE_STEP_EN_0_0 0x250a
139#define SPR_SINGLE_STEP_EN_0_1 0x240a
140#define SPR_SINGLE_STEP_EN_0_2 0x230a
141#define SPR_SINGLE_STEP_EN_1_0 0x250b
142#define SPR_SINGLE_STEP_EN_1_1 0x240b
143#define SPR_SINGLE_STEP_EN_1_2 0x230b
144#define SPR_SINGLE_STEP_EN_2_0 0x250c
145#define SPR_SINGLE_STEP_EN_2_1 0x240c
146#define SPR_SINGLE_STEP_EN_2_2 0x230c
147#define SPR_SYSTEM_SAVE_0_0 0x2582
148#define SPR_SYSTEM_SAVE_0_1 0x2583
149#define SPR_SYSTEM_SAVE_0_2 0x2584
150#define SPR_SYSTEM_SAVE_0_3 0x2585
151#define SPR_SYSTEM_SAVE_1_0 0x2482
152#define SPR_SYSTEM_SAVE_1_1 0x2483
153#define SPR_SYSTEM_SAVE_1_2 0x2484
154#define SPR_SYSTEM_SAVE_1_3 0x2485
155#define SPR_SYSTEM_SAVE_2_0 0x2382
156#define SPR_SYSTEM_SAVE_2_1 0x2383
157#define SPR_SYSTEM_SAVE_2_2 0x2384
158#define SPR_SYSTEM_SAVE_2_3 0x2385
159#define SPR_TILE_COORD 0x270b
160#define SPR_TILE_RTF_HWM 0x270c
161#define SPR_TILE_TIMER_CONTROL 0x1605
162#define SPR_UDN_AVAIL_EN 0x1b05
163#define SPR_UDN_DATA_AVAIL 0x0b80
164#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
165#define SPR_UDN_DEMUX_COUNT_0 0x0b05
166#define SPR_UDN_DEMUX_COUNT_1 0x0b06
167#define SPR_UDN_DEMUX_COUNT_2 0x0b07
168#define SPR_UDN_DEMUX_COUNT_3 0x0b08
169#define SPR_UDN_DIRECTION_PROTECT 0x1505
170
171#endif /* !defined(__ARCH_SPR_DEF_H__) */
172
173#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/asm/auxvec.h b/arch/tile/include/asm/auxvec.h
new file mode 100644
index 00000000000..1d393edb064
--- /dev/null
+++ b/arch/tile/include/asm/auxvec.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_AUXVEC_H
16#define _ASM_TILE_AUXVEC_H
17
18/* No extensions to auxvec */
19
20#endif /* _ASM_TILE_AUXVEC_H */
diff --git a/arch/tile/include/asm/bitsperlong.h b/arch/tile/include/asm/bitsperlong.h
new file mode 100644
index 00000000000..58c771f2af2
--- /dev/null
+++ b/arch/tile/include/asm/bitsperlong.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_BITSPERLONG_H
16#define _ASM_TILE_BITSPERLONG_H
17
18#ifdef __LP64__
19# define __BITS_PER_LONG 64
20#else
21# define __BITS_PER_LONG 32
22#endif
23
24#include <asm-generic/bitsperlong.h>
25
26#endif /* _ASM_TILE_BITSPERLONG_H */
diff --git a/arch/tile/include/asm/byteorder.h b/arch/tile/include/asm/byteorder.h
new file mode 100644
index 00000000000..9558416d578
--- /dev/null
+++ b/arch/tile/include/asm/byteorder.h
@@ -0,0 +1 @@
#include <linux/byteorder/little_endian.h>
diff --git a/arch/tile/include/asm/memprof.h b/arch/tile/include/asm/memprof.h
new file mode 100644
index 00000000000..359949be28c
--- /dev/null
+++ b/arch/tile/include/asm/memprof.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * The hypervisor's memory controller profiling infrastructure allows
15 * the programmer to find out what fraction of the available memory
16 * bandwidth is being consumed at each memory controller. The
17 * profiler provides start, stop, and clear operations to allows
18 * profiling over a specific time window, as well as an interface for
19 * reading the most recent profile values.
20 *
21 * This header declares IOCTL codes necessary to control memprof.
22 */
23#ifndef _ASM_TILE_MEMPROF_H
24#define _ASM_TILE_MEMPROF_H
25
26#include <linux/ioctl.h>
27
28#define MEMPROF_IOCTL_TYPE 0xB4
29#define MEMPROF_IOCTL_START _IO(MEMPROF_IOCTL_TYPE, 0)
30#define MEMPROF_IOCTL_STOP _IO(MEMPROF_IOCTL_TYPE, 1)
31#define MEMPROF_IOCTL_CLEAR _IO(MEMPROF_IOCTL_TYPE, 2)
32
33#endif /* _ASM_TILE_MEMPROF_H */
diff --git a/arch/tile/include/asm/mman.h b/arch/tile/include/asm/mman.h
new file mode 100644
index 00000000000..81b8fc348d6
--- /dev/null
+++ b/arch/tile/include/asm/mman.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_MMAN_H
16#define _ASM_TILE_MMAN_H
17
18#include <asm-generic/mman-common.h>
19#include <arch/chip.h>
20
21/* Standard Linux flags */
22
23#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x0080 /* do not block on IO */
25#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
26#define MAP_STACK MAP_GROWSDOWN /* provide convenience alias */
27#define MAP_LOCKED 0x0200 /* pages are locked */
28#define MAP_NORESERVE 0x0400 /* don't check for reservations */
29#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
30#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
31#define MAP_HUGETLB 0x4000 /* create a huge page mapping */
32
33
34/*
35 * Flags for mlockall
36 */
37#define MCL_CURRENT 1 /* lock all current mappings */
38#define MCL_FUTURE 2 /* lock all future mappings */
39
40
41#endif /* _ASM_TILE_MMAN_H */
diff --git a/arch/tile/include/asm/opcode-tile.h b/arch/tile/include/asm/opcode-tile.h
new file mode 100644
index 00000000000..ba38959137d
--- /dev/null
+++ b/arch/tile/include/asm/opcode-tile.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_OPCODE_TILE_H
16#define _ASM_TILE_OPCODE_TILE_H
17
18#include <arch/chip.h>
19
20#if CHIP_WORD_SIZE() == 64
21#include <asm/opcode-tile_64.h>
22#else
23#include <asm/opcode-tile_32.h>
24#endif
25
26/* These definitions are not correct for TILE64, so just avoid them. */
27#undef TILE_ELF_MACHINE_CODE
28#undef TILE_ELF_NAME
29
30#endif /* _ASM_TILE_OPCODE_TILE_H */
diff --git a/arch/tile/include/asm/opcode-tile_32.h b/arch/tile/include/asm/opcode-tile_32.h
new file mode 100644
index 00000000000..03df7b1e77b
--- /dev/null
+++ b/arch/tile/include/asm/opcode-tile_32.h
@@ -0,0 +1,1513 @@
1/* tile.h -- Header file for TILE opcode table
2 Copyright (C) 2005 Free Software Foundation, Inc.
3 Contributed by Tilera Corp. */
4
5#ifndef opcode_tile_h
6#define opcode_tile_h
7
8typedef unsigned long long tile_bundle_bits;
9
10
11enum
12{
13 TILE_MAX_OPERANDS = 5 /* mm */
14};
15
16typedef enum
17{
18 TILE_OPC_BPT,
19 TILE_OPC_INFO,
20 TILE_OPC_INFOL,
21 TILE_OPC_J,
22 TILE_OPC_JAL,
23 TILE_OPC_MOVE,
24 TILE_OPC_MOVE_SN,
25 TILE_OPC_MOVEI,
26 TILE_OPC_MOVEI_SN,
27 TILE_OPC_MOVELI,
28 TILE_OPC_MOVELI_SN,
29 TILE_OPC_MOVELIS,
30 TILE_OPC_PREFETCH,
31 TILE_OPC_RAISE,
32 TILE_OPC_ADD,
33 TILE_OPC_ADD_SN,
34 TILE_OPC_ADDB,
35 TILE_OPC_ADDB_SN,
36 TILE_OPC_ADDBS_U,
37 TILE_OPC_ADDBS_U_SN,
38 TILE_OPC_ADDH,
39 TILE_OPC_ADDH_SN,
40 TILE_OPC_ADDHS,
41 TILE_OPC_ADDHS_SN,
42 TILE_OPC_ADDI,
43 TILE_OPC_ADDI_SN,
44 TILE_OPC_ADDIB,
45 TILE_OPC_ADDIB_SN,
46 TILE_OPC_ADDIH,
47 TILE_OPC_ADDIH_SN,
48 TILE_OPC_ADDLI,
49 TILE_OPC_ADDLI_SN,
50 TILE_OPC_ADDLIS,
51 TILE_OPC_ADDS,
52 TILE_OPC_ADDS_SN,
53 TILE_OPC_ADIFFB_U,
54 TILE_OPC_ADIFFB_U_SN,
55 TILE_OPC_ADIFFH,
56 TILE_OPC_ADIFFH_SN,
57 TILE_OPC_AND,
58 TILE_OPC_AND_SN,
59 TILE_OPC_ANDI,
60 TILE_OPC_ANDI_SN,
61 TILE_OPC_AULI,
62 TILE_OPC_AVGB_U,
63 TILE_OPC_AVGB_U_SN,
64 TILE_OPC_AVGH,
65 TILE_OPC_AVGH_SN,
66 TILE_OPC_BBNS,
67 TILE_OPC_BBNS_SN,
68 TILE_OPC_BBNST,
69 TILE_OPC_BBNST_SN,
70 TILE_OPC_BBS,
71 TILE_OPC_BBS_SN,
72 TILE_OPC_BBST,
73 TILE_OPC_BBST_SN,
74 TILE_OPC_BGEZ,
75 TILE_OPC_BGEZ_SN,
76 TILE_OPC_BGEZT,
77 TILE_OPC_BGEZT_SN,
78 TILE_OPC_BGZ,
79 TILE_OPC_BGZ_SN,
80 TILE_OPC_BGZT,
81 TILE_OPC_BGZT_SN,
82 TILE_OPC_BITX,
83 TILE_OPC_BITX_SN,
84 TILE_OPC_BLEZ,
85 TILE_OPC_BLEZ_SN,
86 TILE_OPC_BLEZT,
87 TILE_OPC_BLEZT_SN,
88 TILE_OPC_BLZ,
89 TILE_OPC_BLZ_SN,
90 TILE_OPC_BLZT,
91 TILE_OPC_BLZT_SN,
92 TILE_OPC_BNZ,
93 TILE_OPC_BNZ_SN,
94 TILE_OPC_BNZT,
95 TILE_OPC_BNZT_SN,
96 TILE_OPC_BYTEX,
97 TILE_OPC_BYTEX_SN,
98 TILE_OPC_BZ,
99 TILE_OPC_BZ_SN,
100 TILE_OPC_BZT,
101 TILE_OPC_BZT_SN,
102 TILE_OPC_CLZ,
103 TILE_OPC_CLZ_SN,
104 TILE_OPC_CRC32_32,
105 TILE_OPC_CRC32_32_SN,
106 TILE_OPC_CRC32_8,
107 TILE_OPC_CRC32_8_SN,
108 TILE_OPC_CTZ,
109 TILE_OPC_CTZ_SN,
110 TILE_OPC_DRAIN,
111 TILE_OPC_DTLBPR,
112 TILE_OPC_DWORD_ALIGN,
113 TILE_OPC_DWORD_ALIGN_SN,
114 TILE_OPC_FINV,
115 TILE_OPC_FLUSH,
116 TILE_OPC_FNOP,
117 TILE_OPC_ICOH,
118 TILE_OPC_ILL,
119 TILE_OPC_INTHB,
120 TILE_OPC_INTHB_SN,
121 TILE_OPC_INTHH,
122 TILE_OPC_INTHH_SN,
123 TILE_OPC_INTLB,
124 TILE_OPC_INTLB_SN,
125 TILE_OPC_INTLH,
126 TILE_OPC_INTLH_SN,
127 TILE_OPC_INV,
128 TILE_OPC_IRET,
129 TILE_OPC_JALB,
130 TILE_OPC_JALF,
131 TILE_OPC_JALR,
132 TILE_OPC_JALRP,
133 TILE_OPC_JB,
134 TILE_OPC_JF,
135 TILE_OPC_JR,
136 TILE_OPC_JRP,
137 TILE_OPC_LB,
138 TILE_OPC_LB_SN,
139 TILE_OPC_LB_U,
140 TILE_OPC_LB_U_SN,
141 TILE_OPC_LBADD,
142 TILE_OPC_LBADD_SN,
143 TILE_OPC_LBADD_U,
144 TILE_OPC_LBADD_U_SN,
145 TILE_OPC_LH,
146 TILE_OPC_LH_SN,
147 TILE_OPC_LH_U,
148 TILE_OPC_LH_U_SN,
149 TILE_OPC_LHADD,
150 TILE_OPC_LHADD_SN,
151 TILE_OPC_LHADD_U,
152 TILE_OPC_LHADD_U_SN,
153 TILE_OPC_LNK,
154 TILE_OPC_LNK_SN,
155 TILE_OPC_LW,
156 TILE_OPC_LW_SN,
157 TILE_OPC_LW_NA,
158 TILE_OPC_LW_NA_SN,
159 TILE_OPC_LWADD,
160 TILE_OPC_LWADD_SN,
161 TILE_OPC_LWADD_NA,
162 TILE_OPC_LWADD_NA_SN,
163 TILE_OPC_MAXB_U,
164 TILE_OPC_MAXB_U_SN,
165 TILE_OPC_MAXH,
166 TILE_OPC_MAXH_SN,
167 TILE_OPC_MAXIB_U,
168 TILE_OPC_MAXIB_U_SN,
169 TILE_OPC_MAXIH,
170 TILE_OPC_MAXIH_SN,
171 TILE_OPC_MF,
172 TILE_OPC_MFSPR,
173 TILE_OPC_MINB_U,
174 TILE_OPC_MINB_U_SN,
175 TILE_OPC_MINH,
176 TILE_OPC_MINH_SN,
177 TILE_OPC_MINIB_U,
178 TILE_OPC_MINIB_U_SN,
179 TILE_OPC_MINIH,
180 TILE_OPC_MINIH_SN,
181 TILE_OPC_MM,
182 TILE_OPC_MNZ,
183 TILE_OPC_MNZ_SN,
184 TILE_OPC_MNZB,
185 TILE_OPC_MNZB_SN,
186 TILE_OPC_MNZH,
187 TILE_OPC_MNZH_SN,
188 TILE_OPC_MTSPR,
189 TILE_OPC_MULHH_SS,
190 TILE_OPC_MULHH_SS_SN,
191 TILE_OPC_MULHH_SU,
192 TILE_OPC_MULHH_SU_SN,
193 TILE_OPC_MULHH_UU,
194 TILE_OPC_MULHH_UU_SN,
195 TILE_OPC_MULHHA_SS,
196 TILE_OPC_MULHHA_SS_SN,
197 TILE_OPC_MULHHA_SU,
198 TILE_OPC_MULHHA_SU_SN,
199 TILE_OPC_MULHHA_UU,
200 TILE_OPC_MULHHA_UU_SN,
201 TILE_OPC_MULHHSA_UU,
202 TILE_OPC_MULHHSA_UU_SN,
203 TILE_OPC_MULHL_SS,
204 TILE_OPC_MULHL_SS_SN,
205 TILE_OPC_MULHL_SU,
206 TILE_OPC_MULHL_SU_SN,
207 TILE_OPC_MULHL_US,
208 TILE_OPC_MULHL_US_SN,
209 TILE_OPC_MULHL_UU,
210 TILE_OPC_MULHL_UU_SN,
211 TILE_OPC_MULHLA_SS,
212 TILE_OPC_MULHLA_SS_SN,
213 TILE_OPC_MULHLA_SU,
214 TILE_OPC_MULHLA_SU_SN,
215 TILE_OPC_MULHLA_US,
216 TILE_OPC_MULHLA_US_SN,
217 TILE_OPC_MULHLA_UU,
218 TILE_OPC_MULHLA_UU_SN,
219 TILE_OPC_MULHLSA_UU,
220 TILE_OPC_MULHLSA_UU_SN,
221 TILE_OPC_MULLL_SS,
222 TILE_OPC_MULLL_SS_SN,
223 TILE_OPC_MULLL_SU,
224 TILE_OPC_MULLL_SU_SN,
225 TILE_OPC_MULLL_UU,
226 TILE_OPC_MULLL_UU_SN,
227 TILE_OPC_MULLLA_SS,
228 TILE_OPC_MULLLA_SS_SN,
229 TILE_OPC_MULLLA_SU,
230 TILE_OPC_MULLLA_SU_SN,
231 TILE_OPC_MULLLA_UU,
232 TILE_OPC_MULLLA_UU_SN,
233 TILE_OPC_MULLLSA_UU,
234 TILE_OPC_MULLLSA_UU_SN,
235 TILE_OPC_MVNZ,
236 TILE_OPC_MVNZ_SN,
237 TILE_OPC_MVZ,
238 TILE_OPC_MVZ_SN,
239 TILE_OPC_MZ,
240 TILE_OPC_MZ_SN,
241 TILE_OPC_MZB,
242 TILE_OPC_MZB_SN,
243 TILE_OPC_MZH,
244 TILE_OPC_MZH_SN,
245 TILE_OPC_NAP,
246 TILE_OPC_NOP,
247 TILE_OPC_NOR,
248 TILE_OPC_NOR_SN,
249 TILE_OPC_OR,
250 TILE_OPC_OR_SN,
251 TILE_OPC_ORI,
252 TILE_OPC_ORI_SN,
253 TILE_OPC_PACKBS_U,
254 TILE_OPC_PACKBS_U_SN,
255 TILE_OPC_PACKHB,
256 TILE_OPC_PACKHB_SN,
257 TILE_OPC_PACKHS,
258 TILE_OPC_PACKHS_SN,
259 TILE_OPC_PACKLB,
260 TILE_OPC_PACKLB_SN,
261 TILE_OPC_PCNT,
262 TILE_OPC_PCNT_SN,
263 TILE_OPC_RL,
264 TILE_OPC_RL_SN,
265 TILE_OPC_RLI,
266 TILE_OPC_RLI_SN,
267 TILE_OPC_S1A,
268 TILE_OPC_S1A_SN,
269 TILE_OPC_S2A,
270 TILE_OPC_S2A_SN,
271 TILE_OPC_S3A,
272 TILE_OPC_S3A_SN,
273 TILE_OPC_SADAB_U,
274 TILE_OPC_SADAB_U_SN,
275 TILE_OPC_SADAH,
276 TILE_OPC_SADAH_SN,
277 TILE_OPC_SADAH_U,
278 TILE_OPC_SADAH_U_SN,
279 TILE_OPC_SADB_U,
280 TILE_OPC_SADB_U_SN,
281 TILE_OPC_SADH,
282 TILE_OPC_SADH_SN,
283 TILE_OPC_SADH_U,
284 TILE_OPC_SADH_U_SN,
285 TILE_OPC_SB,
286 TILE_OPC_SBADD,
287 TILE_OPC_SEQ,
288 TILE_OPC_SEQ_SN,
289 TILE_OPC_SEQB,
290 TILE_OPC_SEQB_SN,
291 TILE_OPC_SEQH,
292 TILE_OPC_SEQH_SN,
293 TILE_OPC_SEQI,
294 TILE_OPC_SEQI_SN,
295 TILE_OPC_SEQIB,
296 TILE_OPC_SEQIB_SN,
297 TILE_OPC_SEQIH,
298 TILE_OPC_SEQIH_SN,
299 TILE_OPC_SH,
300 TILE_OPC_SHADD,
301 TILE_OPC_SHL,
302 TILE_OPC_SHL_SN,
303 TILE_OPC_SHLB,
304 TILE_OPC_SHLB_SN,
305 TILE_OPC_SHLH,
306 TILE_OPC_SHLH_SN,
307 TILE_OPC_SHLI,
308 TILE_OPC_SHLI_SN,
309 TILE_OPC_SHLIB,
310 TILE_OPC_SHLIB_SN,
311 TILE_OPC_SHLIH,
312 TILE_OPC_SHLIH_SN,
313 TILE_OPC_SHR,
314 TILE_OPC_SHR_SN,
315 TILE_OPC_SHRB,
316 TILE_OPC_SHRB_SN,
317 TILE_OPC_SHRH,
318 TILE_OPC_SHRH_SN,
319 TILE_OPC_SHRI,
320 TILE_OPC_SHRI_SN,
321 TILE_OPC_SHRIB,
322 TILE_OPC_SHRIB_SN,
323 TILE_OPC_SHRIH,
324 TILE_OPC_SHRIH_SN,
325 TILE_OPC_SLT,
326 TILE_OPC_SLT_SN,
327 TILE_OPC_SLT_U,
328 TILE_OPC_SLT_U_SN,
329 TILE_OPC_SLTB,
330 TILE_OPC_SLTB_SN,
331 TILE_OPC_SLTB_U,
332 TILE_OPC_SLTB_U_SN,
333 TILE_OPC_SLTE,
334 TILE_OPC_SLTE_SN,
335 TILE_OPC_SLTE_U,
336 TILE_OPC_SLTE_U_SN,
337 TILE_OPC_SLTEB,
338 TILE_OPC_SLTEB_SN,
339 TILE_OPC_SLTEB_U,
340 TILE_OPC_SLTEB_U_SN,
341 TILE_OPC_SLTEH,
342 TILE_OPC_SLTEH_SN,
343 TILE_OPC_SLTEH_U,
344 TILE_OPC_SLTEH_U_SN,
345 TILE_OPC_SLTH,
346 TILE_OPC_SLTH_SN,
347 TILE_OPC_SLTH_U,
348 TILE_OPC_SLTH_U_SN,
349 TILE_OPC_SLTI,
350 TILE_OPC_SLTI_SN,
351 TILE_OPC_SLTI_U,
352 TILE_OPC_SLTI_U_SN,
353 TILE_OPC_SLTIB,
354 TILE_OPC_SLTIB_SN,
355 TILE_OPC_SLTIB_U,
356 TILE_OPC_SLTIB_U_SN,
357 TILE_OPC_SLTIH,
358 TILE_OPC_SLTIH_SN,
359 TILE_OPC_SLTIH_U,
360 TILE_OPC_SLTIH_U_SN,
361 TILE_OPC_SNE,
362 TILE_OPC_SNE_SN,
363 TILE_OPC_SNEB,
364 TILE_OPC_SNEB_SN,
365 TILE_OPC_SNEH,
366 TILE_OPC_SNEH_SN,
367 TILE_OPC_SRA,
368 TILE_OPC_SRA_SN,
369 TILE_OPC_SRAB,
370 TILE_OPC_SRAB_SN,
371 TILE_OPC_SRAH,
372 TILE_OPC_SRAH_SN,
373 TILE_OPC_SRAI,
374 TILE_OPC_SRAI_SN,
375 TILE_OPC_SRAIB,
376 TILE_OPC_SRAIB_SN,
377 TILE_OPC_SRAIH,
378 TILE_OPC_SRAIH_SN,
379 TILE_OPC_SUB,
380 TILE_OPC_SUB_SN,
381 TILE_OPC_SUBB,
382 TILE_OPC_SUBB_SN,
383 TILE_OPC_SUBBS_U,
384 TILE_OPC_SUBBS_U_SN,
385 TILE_OPC_SUBH,
386 TILE_OPC_SUBH_SN,
387 TILE_OPC_SUBHS,
388 TILE_OPC_SUBHS_SN,
389 TILE_OPC_SUBS,
390 TILE_OPC_SUBS_SN,
391 TILE_OPC_SW,
392 TILE_OPC_SWADD,
393 TILE_OPC_SWINT0,
394 TILE_OPC_SWINT1,
395 TILE_OPC_SWINT2,
396 TILE_OPC_SWINT3,
397 TILE_OPC_TBLIDXB0,
398 TILE_OPC_TBLIDXB0_SN,
399 TILE_OPC_TBLIDXB1,
400 TILE_OPC_TBLIDXB1_SN,
401 TILE_OPC_TBLIDXB2,
402 TILE_OPC_TBLIDXB2_SN,
403 TILE_OPC_TBLIDXB3,
404 TILE_OPC_TBLIDXB3_SN,
405 TILE_OPC_TNS,
406 TILE_OPC_TNS_SN,
407 TILE_OPC_WH64,
408 TILE_OPC_XOR,
409 TILE_OPC_XOR_SN,
410 TILE_OPC_XORI,
411 TILE_OPC_XORI_SN,
412 TILE_OPC_NONE
413} tile_mnemonic;
414
415/* 64-bit pattern for a { bpt ; nop } bundle. */
416#define TILE_BPT_BUNDLE 0x400b3cae70166000ULL
417
418
419#define TILE_ELF_MACHINE_CODE EM_TILEPRO
420
421#define TILE_ELF_NAME "elf32-tilepro"
422
423
424static __inline unsigned int
425get_BrOff_SN(tile_bundle_bits num)
426{
427 const unsigned int n = (unsigned int)num;
428 return (((n >> 0)) & 0x3ff);
429}
430
431static __inline unsigned int
432get_BrOff_X1(tile_bundle_bits n)
433{
434 return (((unsigned int)(n >> 43)) & 0x00007fff) |
435 (((unsigned int)(n >> 20)) & 0x00018000);
436}
437
438static __inline unsigned int
439get_BrType_X1(tile_bundle_bits n)
440{
441 return (((unsigned int)(n >> 31)) & 0xf);
442}
443
444static __inline unsigned int
445get_Dest_Imm8_X1(tile_bundle_bits n)
446{
447 return (((unsigned int)(n >> 31)) & 0x0000003f) |
448 (((unsigned int)(n >> 43)) & 0x000000c0);
449}
450
451static __inline unsigned int
452get_Dest_SN(tile_bundle_bits num)
453{
454 const unsigned int n = (unsigned int)num;
455 return (((n >> 2)) & 0x3);
456}
457
458static __inline unsigned int
459get_Dest_X0(tile_bundle_bits num)
460{
461 const unsigned int n = (unsigned int)num;
462 return (((n >> 0)) & 0x3f);
463}
464
465static __inline unsigned int
466get_Dest_X1(tile_bundle_bits n)
467{
468 return (((unsigned int)(n >> 31)) & 0x3f);
469}
470
471static __inline unsigned int
472get_Dest_Y0(tile_bundle_bits num)
473{
474 const unsigned int n = (unsigned int)num;
475 return (((n >> 0)) & 0x3f);
476}
477
478static __inline unsigned int
479get_Dest_Y1(tile_bundle_bits n)
480{
481 return (((unsigned int)(n >> 31)) & 0x3f);
482}
483
484static __inline unsigned int
485get_Imm16_X0(tile_bundle_bits num)
486{
487 const unsigned int n = (unsigned int)num;
488 return (((n >> 12)) & 0xffff);
489}
490
491static __inline unsigned int
492get_Imm16_X1(tile_bundle_bits n)
493{
494 return (((unsigned int)(n >> 43)) & 0xffff);
495}
496
497static __inline unsigned int
498get_Imm8_SN(tile_bundle_bits num)
499{
500 const unsigned int n = (unsigned int)num;
501 return (((n >> 0)) & 0xff);
502}
503
504static __inline unsigned int
505get_Imm8_X0(tile_bundle_bits num)
506{
507 const unsigned int n = (unsigned int)num;
508 return (((n >> 12)) & 0xff);
509}
510
511static __inline unsigned int
512get_Imm8_X1(tile_bundle_bits n)
513{
514 return (((unsigned int)(n >> 43)) & 0xff);
515}
516
517static __inline unsigned int
518get_Imm8_Y0(tile_bundle_bits num)
519{
520 const unsigned int n = (unsigned int)num;
521 return (((n >> 12)) & 0xff);
522}
523
524static __inline unsigned int
525get_Imm8_Y1(tile_bundle_bits n)
526{
527 return (((unsigned int)(n >> 43)) & 0xff);
528}
529
530static __inline unsigned int
531get_ImmOpcodeExtension_X0(tile_bundle_bits num)
532{
533 const unsigned int n = (unsigned int)num;
534 return (((n >> 20)) & 0x7f);
535}
536
537static __inline unsigned int
538get_ImmOpcodeExtension_X1(tile_bundle_bits n)
539{
540 return (((unsigned int)(n >> 51)) & 0x7f);
541}
542
543static __inline unsigned int
544get_ImmRROpcodeExtension_SN(tile_bundle_bits num)
545{
546 const unsigned int n = (unsigned int)num;
547 return (((n >> 8)) & 0x3);
548}
549
550static __inline unsigned int
551get_JOffLong_X1(tile_bundle_bits n)
552{
553 return (((unsigned int)(n >> 43)) & 0x00007fff) |
554 (((unsigned int)(n >> 20)) & 0x00018000) |
555 (((unsigned int)(n >> 14)) & 0x001e0000) |
556 (((unsigned int)(n >> 16)) & 0x07e00000) |
557 (((unsigned int)(n >> 31)) & 0x18000000);
558}
559
560static __inline unsigned int
561get_JOff_X1(tile_bundle_bits n)
562{
563 return (((unsigned int)(n >> 43)) & 0x00007fff) |
564 (((unsigned int)(n >> 20)) & 0x00018000) |
565 (((unsigned int)(n >> 14)) & 0x001e0000) |
566 (((unsigned int)(n >> 16)) & 0x07e00000) |
567 (((unsigned int)(n >> 31)) & 0x08000000);
568}
569
570static __inline unsigned int
571get_MF_Imm15_X1(tile_bundle_bits n)
572{
573 return (((unsigned int)(n >> 37)) & 0x00003fff) |
574 (((unsigned int)(n >> 44)) & 0x00004000);
575}
576
577static __inline unsigned int
578get_MMEnd_X0(tile_bundle_bits num)
579{
580 const unsigned int n = (unsigned int)num;
581 return (((n >> 18)) & 0x1f);
582}
583
584static __inline unsigned int
585get_MMEnd_X1(tile_bundle_bits n)
586{
587 return (((unsigned int)(n >> 49)) & 0x1f);
588}
589
590static __inline unsigned int
591get_MMStart_X0(tile_bundle_bits num)
592{
593 const unsigned int n = (unsigned int)num;
594 return (((n >> 23)) & 0x1f);
595}
596
597static __inline unsigned int
598get_MMStart_X1(tile_bundle_bits n)
599{
600 return (((unsigned int)(n >> 54)) & 0x1f);
601}
602
603static __inline unsigned int
604get_MT_Imm15_X1(tile_bundle_bits n)
605{
606 return (((unsigned int)(n >> 31)) & 0x0000003f) |
607 (((unsigned int)(n >> 37)) & 0x00003fc0) |
608 (((unsigned int)(n >> 44)) & 0x00004000);
609}
610
611static __inline unsigned int
612get_Mode(tile_bundle_bits n)
613{
614 return (((unsigned int)(n >> 63)) & 0x1);
615}
616
617static __inline unsigned int
618get_NoRegOpcodeExtension_SN(tile_bundle_bits num)
619{
620 const unsigned int n = (unsigned int)num;
621 return (((n >> 0)) & 0xf);
622}
623
624static __inline unsigned int
625get_Opcode_SN(tile_bundle_bits num)
626{
627 const unsigned int n = (unsigned int)num;
628 return (((n >> 10)) & 0x3f);
629}
630
631static __inline unsigned int
632get_Opcode_X0(tile_bundle_bits num)
633{
634 const unsigned int n = (unsigned int)num;
635 return (((n >> 28)) & 0x7);
636}
637
638static __inline unsigned int
639get_Opcode_X1(tile_bundle_bits n)
640{
641 return (((unsigned int)(n >> 59)) & 0xf);
642}
643
644static __inline unsigned int
645get_Opcode_Y0(tile_bundle_bits num)
646{
647 const unsigned int n = (unsigned int)num;
648 return (((n >> 27)) & 0xf);
649}
650
651static __inline unsigned int
652get_Opcode_Y1(tile_bundle_bits n)
653{
654 return (((unsigned int)(n >> 59)) & 0xf);
655}
656
657static __inline unsigned int
658get_Opcode_Y2(tile_bundle_bits n)
659{
660 return (((unsigned int)(n >> 56)) & 0x7);
661}
662
663static __inline unsigned int
664get_RROpcodeExtension_SN(tile_bundle_bits num)
665{
666 const unsigned int n = (unsigned int)num;
667 return (((n >> 4)) & 0xf);
668}
669
670static __inline unsigned int
671get_RRROpcodeExtension_X0(tile_bundle_bits num)
672{
673 const unsigned int n = (unsigned int)num;
674 return (((n >> 18)) & 0x1ff);
675}
676
677static __inline unsigned int
678get_RRROpcodeExtension_X1(tile_bundle_bits n)
679{
680 return (((unsigned int)(n >> 49)) & 0x1ff);
681}
682
683static __inline unsigned int
684get_RRROpcodeExtension_Y0(tile_bundle_bits num)
685{
686 const unsigned int n = (unsigned int)num;
687 return (((n >> 18)) & 0x3);
688}
689
690static __inline unsigned int
691get_RRROpcodeExtension_Y1(tile_bundle_bits n)
692{
693 return (((unsigned int)(n >> 49)) & 0x3);
694}
695
696static __inline unsigned int
697get_RouteOpcodeExtension_SN(tile_bundle_bits num)
698{
699 const unsigned int n = (unsigned int)num;
700 return (((n >> 0)) & 0x3ff);
701}
702
703static __inline unsigned int
704get_S_X0(tile_bundle_bits num)
705{
706 const unsigned int n = (unsigned int)num;
707 return (((n >> 27)) & 0x1);
708}
709
710static __inline unsigned int
711get_S_X1(tile_bundle_bits n)
712{
713 return (((unsigned int)(n >> 58)) & 0x1);
714}
715
716static __inline unsigned int
717get_ShAmt_X0(tile_bundle_bits num)
718{
719 const unsigned int n = (unsigned int)num;
720 return (((n >> 12)) & 0x1f);
721}
722
723static __inline unsigned int
724get_ShAmt_X1(tile_bundle_bits n)
725{
726 return (((unsigned int)(n >> 43)) & 0x1f);
727}
728
729static __inline unsigned int
730get_ShAmt_Y0(tile_bundle_bits num)
731{
732 const unsigned int n = (unsigned int)num;
733 return (((n >> 12)) & 0x1f);
734}
735
736static __inline unsigned int
737get_ShAmt_Y1(tile_bundle_bits n)
738{
739 return (((unsigned int)(n >> 43)) & 0x1f);
740}
741
742static __inline unsigned int
743get_SrcA_X0(tile_bundle_bits num)
744{
745 const unsigned int n = (unsigned int)num;
746 return (((n >> 6)) & 0x3f);
747}
748
749static __inline unsigned int
750get_SrcA_X1(tile_bundle_bits n)
751{
752 return (((unsigned int)(n >> 37)) & 0x3f);
753}
754
755static __inline unsigned int
756get_SrcA_Y0(tile_bundle_bits num)
757{
758 const unsigned int n = (unsigned int)num;
759 return (((n >> 6)) & 0x3f);
760}
761
762static __inline unsigned int
763get_SrcA_Y1(tile_bundle_bits n)
764{
765 return (((unsigned int)(n >> 37)) & 0x3f);
766}
767
768static __inline unsigned int
769get_SrcA_Y2(tile_bundle_bits n)
770{
771 return (((n >> 26)) & 0x00000001) |
772 (((unsigned int)(n >> 50)) & 0x0000003e);
773}
774
775static __inline unsigned int
776get_SrcBDest_Y2(tile_bundle_bits num)
777{
778 const unsigned int n = (unsigned int)num;
779 return (((n >> 20)) & 0x3f);
780}
781
782static __inline unsigned int
783get_SrcB_X0(tile_bundle_bits num)
784{
785 const unsigned int n = (unsigned int)num;
786 return (((n >> 12)) & 0x3f);
787}
788
789static __inline unsigned int
790get_SrcB_X1(tile_bundle_bits n)
791{
792 return (((unsigned int)(n >> 43)) & 0x3f);
793}
794
795static __inline unsigned int
796get_SrcB_Y0(tile_bundle_bits num)
797{
798 const unsigned int n = (unsigned int)num;
799 return (((n >> 12)) & 0x3f);
800}
801
802static __inline unsigned int
803get_SrcB_Y1(tile_bundle_bits n)
804{
805 return (((unsigned int)(n >> 43)) & 0x3f);
806}
807
808static __inline unsigned int
809get_Src_SN(tile_bundle_bits num)
810{
811 const unsigned int n = (unsigned int)num;
812 return (((n >> 0)) & 0x3);
813}
814
815static __inline unsigned int
816get_UnOpcodeExtension_X0(tile_bundle_bits num)
817{
818 const unsigned int n = (unsigned int)num;
819 return (((n >> 12)) & 0x1f);
820}
821
822static __inline unsigned int
823get_UnOpcodeExtension_X1(tile_bundle_bits n)
824{
825 return (((unsigned int)(n >> 43)) & 0x1f);
826}
827
828static __inline unsigned int
829get_UnOpcodeExtension_Y0(tile_bundle_bits num)
830{
831 const unsigned int n = (unsigned int)num;
832 return (((n >> 12)) & 0x1f);
833}
834
835static __inline unsigned int
836get_UnOpcodeExtension_Y1(tile_bundle_bits n)
837{
838 return (((unsigned int)(n >> 43)) & 0x1f);
839}
840
841static __inline unsigned int
842get_UnShOpcodeExtension_X0(tile_bundle_bits num)
843{
844 const unsigned int n = (unsigned int)num;
845 return (((n >> 17)) & 0x3ff);
846}
847
848static __inline unsigned int
849get_UnShOpcodeExtension_X1(tile_bundle_bits n)
850{
851 return (((unsigned int)(n >> 48)) & 0x3ff);
852}
853
854static __inline unsigned int
855get_UnShOpcodeExtension_Y0(tile_bundle_bits num)
856{
857 const unsigned int n = (unsigned int)num;
858 return (((n >> 17)) & 0x7);
859}
860
861static __inline unsigned int
862get_UnShOpcodeExtension_Y1(tile_bundle_bits n)
863{
864 return (((unsigned int)(n >> 48)) & 0x7);
865}
866
867
868static __inline int
869sign_extend(int n, int num_bits)
870{
871 int shift = (int)(sizeof(int) * 8 - num_bits);
872 return (n << shift) >> shift;
873}
874
875
876
877static __inline tile_bundle_bits
878create_BrOff_SN(int num)
879{
880 const unsigned int n = (unsigned int)num;
881 return ((n & 0x3ff) << 0);
882}
883
884static __inline tile_bundle_bits
885create_BrOff_X1(int num)
886{
887 const unsigned int n = (unsigned int)num;
888 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
889 (((tile_bundle_bits)(n & 0x00018000)) << 20);
890}
891
892static __inline tile_bundle_bits
893create_BrType_X1(int num)
894{
895 const unsigned int n = (unsigned int)num;
896 return (((tile_bundle_bits)(n & 0xf)) << 31);
897}
898
899static __inline tile_bundle_bits
900create_Dest_Imm8_X1(int num)
901{
902 const unsigned int n = (unsigned int)num;
903 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
904 (((tile_bundle_bits)(n & 0x000000c0)) << 43);
905}
906
907static __inline tile_bundle_bits
908create_Dest_SN(int num)
909{
910 const unsigned int n = (unsigned int)num;
911 return ((n & 0x3) << 2);
912}
913
914static __inline tile_bundle_bits
915create_Dest_X0(int num)
916{
917 const unsigned int n = (unsigned int)num;
918 return ((n & 0x3f) << 0);
919}
920
921static __inline tile_bundle_bits
922create_Dest_X1(int num)
923{
924 const unsigned int n = (unsigned int)num;
925 return (((tile_bundle_bits)(n & 0x3f)) << 31);
926}
927
928static __inline tile_bundle_bits
929create_Dest_Y0(int num)
930{
931 const unsigned int n = (unsigned int)num;
932 return ((n & 0x3f) << 0);
933}
934
935static __inline tile_bundle_bits
936create_Dest_Y1(int num)
937{
938 const unsigned int n = (unsigned int)num;
939 return (((tile_bundle_bits)(n & 0x3f)) << 31);
940}
941
942static __inline tile_bundle_bits
943create_Imm16_X0(int num)
944{
945 const unsigned int n = (unsigned int)num;
946 return ((n & 0xffff) << 12);
947}
948
949static __inline tile_bundle_bits
950create_Imm16_X1(int num)
951{
952 const unsigned int n = (unsigned int)num;
953 return (((tile_bundle_bits)(n & 0xffff)) << 43);
954}
955
956static __inline tile_bundle_bits
957create_Imm8_SN(int num)
958{
959 const unsigned int n = (unsigned int)num;
960 return ((n & 0xff) << 0);
961}
962
963static __inline tile_bundle_bits
964create_Imm8_X0(int num)
965{
966 const unsigned int n = (unsigned int)num;
967 return ((n & 0xff) << 12);
968}
969
970static __inline tile_bundle_bits
971create_Imm8_X1(int num)
972{
973 const unsigned int n = (unsigned int)num;
974 return (((tile_bundle_bits)(n & 0xff)) << 43);
975}
976
977static __inline tile_bundle_bits
978create_Imm8_Y0(int num)
979{
980 const unsigned int n = (unsigned int)num;
981 return ((n & 0xff) << 12);
982}
983
984static __inline tile_bundle_bits
985create_Imm8_Y1(int num)
986{
987 const unsigned int n = (unsigned int)num;
988 return (((tile_bundle_bits)(n & 0xff)) << 43);
989}
990
991static __inline tile_bundle_bits
992create_ImmOpcodeExtension_X0(int num)
993{
994 const unsigned int n = (unsigned int)num;
995 return ((n & 0x7f) << 20);
996}
997
998static __inline tile_bundle_bits
999create_ImmOpcodeExtension_X1(int num)
1000{
1001 const unsigned int n = (unsigned int)num;
1002 return (((tile_bundle_bits)(n & 0x7f)) << 51);
1003}
1004
1005static __inline tile_bundle_bits
1006create_ImmRROpcodeExtension_SN(int num)
1007{
1008 const unsigned int n = (unsigned int)num;
1009 return ((n & 0x3) << 8);
1010}
1011
1012static __inline tile_bundle_bits
1013create_JOffLong_X1(int num)
1014{
1015 const unsigned int n = (unsigned int)num;
1016 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1017 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1018 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1019 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1020 (((tile_bundle_bits)(n & 0x18000000)) << 31);
1021}
1022
1023static __inline tile_bundle_bits
1024create_JOff_X1(int num)
1025{
1026 const unsigned int n = (unsigned int)num;
1027 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1028 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1029 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1030 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1031 (((tile_bundle_bits)(n & 0x08000000)) << 31);
1032}
1033
1034static __inline tile_bundle_bits
1035create_MF_Imm15_X1(int num)
1036{
1037 const unsigned int n = (unsigned int)num;
1038 return (((tile_bundle_bits)(n & 0x00003fff)) << 37) |
1039 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1040}
1041
1042static __inline tile_bundle_bits
1043create_MMEnd_X0(int num)
1044{
1045 const unsigned int n = (unsigned int)num;
1046 return ((n & 0x1f) << 18);
1047}
1048
1049static __inline tile_bundle_bits
1050create_MMEnd_X1(int num)
1051{
1052 const unsigned int n = (unsigned int)num;
1053 return (((tile_bundle_bits)(n & 0x1f)) << 49);
1054}
1055
1056static __inline tile_bundle_bits
1057create_MMStart_X0(int num)
1058{
1059 const unsigned int n = (unsigned int)num;
1060 return ((n & 0x1f) << 23);
1061}
1062
1063static __inline tile_bundle_bits
1064create_MMStart_X1(int num)
1065{
1066 const unsigned int n = (unsigned int)num;
1067 return (((tile_bundle_bits)(n & 0x1f)) << 54);
1068}
1069
1070static __inline tile_bundle_bits
1071create_MT_Imm15_X1(int num)
1072{
1073 const unsigned int n = (unsigned int)num;
1074 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
1075 (((tile_bundle_bits)(n & 0x00003fc0)) << 37) |
1076 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1077}
1078
1079static __inline tile_bundle_bits
1080create_Mode(int num)
1081{
1082 const unsigned int n = (unsigned int)num;
1083 return (((tile_bundle_bits)(n & 0x1)) << 63);
1084}
1085
1086static __inline tile_bundle_bits
1087create_NoRegOpcodeExtension_SN(int num)
1088{
1089 const unsigned int n = (unsigned int)num;
1090 return ((n & 0xf) << 0);
1091}
1092
1093static __inline tile_bundle_bits
1094create_Opcode_SN(int num)
1095{
1096 const unsigned int n = (unsigned int)num;
1097 return ((n & 0x3f) << 10);
1098}
1099
1100static __inline tile_bundle_bits
1101create_Opcode_X0(int num)
1102{
1103 const unsigned int n = (unsigned int)num;
1104 return ((n & 0x7) << 28);
1105}
1106
1107static __inline tile_bundle_bits
1108create_Opcode_X1(int num)
1109{
1110 const unsigned int n = (unsigned int)num;
1111 return (((tile_bundle_bits)(n & 0xf)) << 59);
1112}
1113
1114static __inline tile_bundle_bits
1115create_Opcode_Y0(int num)
1116{
1117 const unsigned int n = (unsigned int)num;
1118 return ((n & 0xf) << 27);
1119}
1120
1121static __inline tile_bundle_bits
1122create_Opcode_Y1(int num)
1123{
1124 const unsigned int n = (unsigned int)num;
1125 return (((tile_bundle_bits)(n & 0xf)) << 59);
1126}
1127
1128static __inline tile_bundle_bits
1129create_Opcode_Y2(int num)
1130{
1131 const unsigned int n = (unsigned int)num;
1132 return (((tile_bundle_bits)(n & 0x7)) << 56);
1133}
1134
1135static __inline tile_bundle_bits
1136create_RROpcodeExtension_SN(int num)
1137{
1138 const unsigned int n = (unsigned int)num;
1139 return ((n & 0xf) << 4);
1140}
1141
1142static __inline tile_bundle_bits
1143create_RRROpcodeExtension_X0(int num)
1144{
1145 const unsigned int n = (unsigned int)num;
1146 return ((n & 0x1ff) << 18);
1147}
1148
1149static __inline tile_bundle_bits
1150create_RRROpcodeExtension_X1(int num)
1151{
1152 const unsigned int n = (unsigned int)num;
1153 return (((tile_bundle_bits)(n & 0x1ff)) << 49);
1154}
1155
1156static __inline tile_bundle_bits
1157create_RRROpcodeExtension_Y0(int num)
1158{
1159 const unsigned int n = (unsigned int)num;
1160 return ((n & 0x3) << 18);
1161}
1162
1163static __inline tile_bundle_bits
1164create_RRROpcodeExtension_Y1(int num)
1165{
1166 const unsigned int n = (unsigned int)num;
1167 return (((tile_bundle_bits)(n & 0x3)) << 49);
1168}
1169
1170static __inline tile_bundle_bits
1171create_RouteOpcodeExtension_SN(int num)
1172{
1173 const unsigned int n = (unsigned int)num;
1174 return ((n & 0x3ff) << 0);
1175}
1176
1177static __inline tile_bundle_bits
1178create_S_X0(int num)
1179{
1180 const unsigned int n = (unsigned int)num;
1181 return ((n & 0x1) << 27);
1182}
1183
1184static __inline tile_bundle_bits
1185create_S_X1(int num)
1186{
1187 const unsigned int n = (unsigned int)num;
1188 return (((tile_bundle_bits)(n & 0x1)) << 58);
1189}
1190
1191static __inline tile_bundle_bits
1192create_ShAmt_X0(int num)
1193{
1194 const unsigned int n = (unsigned int)num;
1195 return ((n & 0x1f) << 12);
1196}
1197
1198static __inline tile_bundle_bits
1199create_ShAmt_X1(int num)
1200{
1201 const unsigned int n = (unsigned int)num;
1202 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1203}
1204
1205static __inline tile_bundle_bits
1206create_ShAmt_Y0(int num)
1207{
1208 const unsigned int n = (unsigned int)num;
1209 return ((n & 0x1f) << 12);
1210}
1211
1212static __inline tile_bundle_bits
1213create_ShAmt_Y1(int num)
1214{
1215 const unsigned int n = (unsigned int)num;
1216 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1217}
1218
1219static __inline tile_bundle_bits
1220create_SrcA_X0(int num)
1221{
1222 const unsigned int n = (unsigned int)num;
1223 return ((n & 0x3f) << 6);
1224}
1225
1226static __inline tile_bundle_bits
1227create_SrcA_X1(int num)
1228{
1229 const unsigned int n = (unsigned int)num;
1230 return (((tile_bundle_bits)(n & 0x3f)) << 37);
1231}
1232
1233static __inline tile_bundle_bits
1234create_SrcA_Y0(int num)
1235{
1236 const unsigned int n = (unsigned int)num;
1237 return ((n & 0x3f) << 6);
1238}
1239
1240static __inline tile_bundle_bits
1241create_SrcA_Y1(int num)
1242{
1243 const unsigned int n = (unsigned int)num;
1244 return (((tile_bundle_bits)(n & 0x3f)) << 37);
1245}
1246
1247static __inline tile_bundle_bits
1248create_SrcA_Y2(int num)
1249{
1250 const unsigned int n = (unsigned int)num;
1251 return ((n & 0x00000001) << 26) |
1252 (((tile_bundle_bits)(n & 0x0000003e)) << 50);
1253}
1254
1255static __inline tile_bundle_bits
1256create_SrcBDest_Y2(int num)
1257{
1258 const unsigned int n = (unsigned int)num;
1259 return ((n & 0x3f) << 20);
1260}
1261
1262static __inline tile_bundle_bits
1263create_SrcB_X0(int num)
1264{
1265 const unsigned int n = (unsigned int)num;
1266 return ((n & 0x3f) << 12);
1267}
1268
1269static __inline tile_bundle_bits
1270create_SrcB_X1(int num)
1271{
1272 const unsigned int n = (unsigned int)num;
1273 return (((tile_bundle_bits)(n & 0x3f)) << 43);
1274}
1275
1276static __inline tile_bundle_bits
1277create_SrcB_Y0(int num)
1278{
1279 const unsigned int n = (unsigned int)num;
1280 return ((n & 0x3f) << 12);
1281}
1282
1283static __inline tile_bundle_bits
1284create_SrcB_Y1(int num)
1285{
1286 const unsigned int n = (unsigned int)num;
1287 return (((tile_bundle_bits)(n & 0x3f)) << 43);
1288}
1289
1290static __inline tile_bundle_bits
1291create_Src_SN(int num)
1292{
1293 const unsigned int n = (unsigned int)num;
1294 return ((n & 0x3) << 0);
1295}
1296
1297static __inline tile_bundle_bits
1298create_UnOpcodeExtension_X0(int num)
1299{
1300 const unsigned int n = (unsigned int)num;
1301 return ((n & 0x1f) << 12);
1302}
1303
1304static __inline tile_bundle_bits
1305create_UnOpcodeExtension_X1(int num)
1306{
1307 const unsigned int n = (unsigned int)num;
1308 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1309}
1310
1311static __inline tile_bundle_bits
1312create_UnOpcodeExtension_Y0(int num)
1313{
1314 const unsigned int n = (unsigned int)num;
1315 return ((n & 0x1f) << 12);
1316}
1317
1318static __inline tile_bundle_bits
1319create_UnOpcodeExtension_Y1(int num)
1320{
1321 const unsigned int n = (unsigned int)num;
1322 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1323}
1324
1325static __inline tile_bundle_bits
1326create_UnShOpcodeExtension_X0(int num)
1327{
1328 const unsigned int n = (unsigned int)num;
1329 return ((n & 0x3ff) << 17);
1330}
1331
1332static __inline tile_bundle_bits
1333create_UnShOpcodeExtension_X1(int num)
1334{
1335 const unsigned int n = (unsigned int)num;
1336 return (((tile_bundle_bits)(n & 0x3ff)) << 48);
1337}
1338
1339static __inline tile_bundle_bits
1340create_UnShOpcodeExtension_Y0(int num)
1341{
1342 const unsigned int n = (unsigned int)num;
1343 return ((n & 0x7) << 17);
1344}
1345
1346static __inline tile_bundle_bits
1347create_UnShOpcodeExtension_Y1(int num)
1348{
1349 const unsigned int n = (unsigned int)num;
1350 return (((tile_bundle_bits)(n & 0x7)) << 48);
1351}
1352
1353
1354
1355typedef enum
1356{
1357 TILE_PIPELINE_X0,
1358 TILE_PIPELINE_X1,
1359 TILE_PIPELINE_Y0,
1360 TILE_PIPELINE_Y1,
1361 TILE_PIPELINE_Y2,
1362} tile_pipeline;
1363
1364#define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1)
1365
1366typedef enum
1367{
1368 TILE_OP_TYPE_REGISTER,
1369 TILE_OP_TYPE_IMMEDIATE,
1370 TILE_OP_TYPE_ADDRESS,
1371 TILE_OP_TYPE_SPR
1372} tile_operand_type;
1373
1374/* This is the bit that determines if a bundle is in the Y encoding. */
1375#define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63)
1376
1377enum
1378{
1379 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
1380 TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
1381
1382 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
1383 TILE_NUM_PIPELINE_ENCODINGS = 5,
1384
1385 /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */
1386 TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
1387
1388 /* Instructions take this many bytes. */
1389 TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES,
1390
1391 /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */
1392 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
1393
1394 /* Bundles should be aligned modulo this number of bytes. */
1395 TILE_BUNDLE_ALIGNMENT_IN_BYTES =
1396 (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
1397
1398 /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */
1399 TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
1400
1401 /* Static network instructions take this many bytes. */
1402 TILE_SN_INSTRUCTION_SIZE_IN_BYTES =
1403 (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
1404
1405 /* Number of registers (some are magic, such as network I/O). */
1406 TILE_NUM_REGISTERS = 64,
1407
1408 /* Number of static network registers. */
1409 TILE_NUM_SN_REGISTERS = 4
1410};
1411
1412
1413struct tile_operand
1414{
1415 /* Is this operand a register, immediate or address? */
1416 tile_operand_type type;
1417
1418 /* The default relocation type for this operand. */
1419 signed int default_reloc : 16;
1420
1421 /* How many bits is this value? (used for range checking) */
1422 unsigned int num_bits : 5;
1423
1424 /* Is the value signed? (used for range checking) */
1425 unsigned int is_signed : 1;
1426
1427 /* Is this operand a source register? */
1428 unsigned int is_src_reg : 1;
1429
1430 /* Is this operand written? (i.e. is it a destination register) */
1431 unsigned int is_dest_reg : 1;
1432
1433 /* Is this operand PC-relative? */
1434 unsigned int is_pc_relative : 1;
1435
1436 /* By how many bits do we right shift the value before inserting? */
1437 unsigned int rightshift : 2;
1438
1439 /* Return the bits for this operand to be ORed into an existing bundle. */
1440 tile_bundle_bits (*insert) (int op);
1441
1442 /* Extract this operand and return it. */
1443 unsigned int (*extract) (tile_bundle_bits bundle);
1444};
1445
1446
1447extern const struct tile_operand tile_operands[];
1448
1449/* One finite-state machine per pipe for rapid instruction decoding. */
1450extern const unsigned short * const
1451tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS];
1452
1453
1454struct tile_opcode
1455{
1456 /* The opcode mnemonic, e.g. "add" */
1457 const char *name;
1458
1459 /* The enum value for this mnemonic. */
1460 tile_mnemonic mnemonic;
1461
1462 /* A bit mask of which of the five pipes this instruction
1463 is compatible with:
1464 X0 0x01
1465 X1 0x02
1466 Y0 0x04
1467 Y1 0x08
1468 Y2 0x10 */
1469 unsigned char pipes;
1470
1471 /* How many operands are there? */
1472 unsigned char num_operands;
1473
1474 /* Which register does this write implicitly, or TREG_ZERO if none? */
1475 unsigned char implicitly_written_register;
1476
1477 /* Can this be bundled with other instructions (almost always true). */
1478 unsigned char can_bundle;
1479
1480 /* The description of the operands. Each of these is an
1481 * index into the tile_operands[] table. */
1482 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS];
1483
1484};
1485
1486extern const struct tile_opcode tile_opcodes[];
1487
1488
1489/* Used for non-textual disassembly into structs. */
1490struct tile_decoded_instruction
1491{
1492 const struct tile_opcode *opcode;
1493 const struct tile_operand *operands[TILE_MAX_OPERANDS];
1494 int operand_values[TILE_MAX_OPERANDS];
1495};
1496
1497
1498/* Disassemble a bundle into a struct for machine processing. */
1499extern int parse_insn_tile(tile_bundle_bits bits,
1500 unsigned int pc,
1501 struct tile_decoded_instruction
1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
1503
1504
1505/* Given a set of bundle bits and a specific pipe, returns which
1506 * instruction the bundle contains in that pipe.
1507 */
1508extern const struct tile_opcode *
1509find_opcode(tile_bundle_bits bits, tile_pipeline pipe);
1510
1511
1512
1513#endif /* opcode_tile_h */
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h
new file mode 100644
index 00000000000..c0633466cd5
--- /dev/null
+++ b/arch/tile/include/asm/opcode-tile_64.h
@@ -0,0 +1,1248 @@
1/* tile.h -- Header file for TILE opcode table
2 Copyright (C) 2005 Free Software Foundation, Inc.
3 Contributed by Tilera Corp. */
4
5#ifndef opcode_tile_h
6#define opcode_tile_h
7
8typedef unsigned long long tilegx_bundle_bits;
9
10
11enum
12{
13 TILEGX_MAX_OPERANDS = 4 /* bfexts */
14};
15
16typedef enum
17{
18 TILEGX_OPC_BPT,
19 TILEGX_OPC_INFO,
20 TILEGX_OPC_INFOL,
21 TILEGX_OPC_MOVE,
22 TILEGX_OPC_MOVEI,
23 TILEGX_OPC_MOVELI,
24 TILEGX_OPC_PREFETCH,
25 TILEGX_OPC_PREFETCH_ADD_L1,
26 TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
27 TILEGX_OPC_PREFETCH_ADD_L2,
28 TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
29 TILEGX_OPC_PREFETCH_ADD_L3,
30 TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
31 TILEGX_OPC_PREFETCH_L1,
32 TILEGX_OPC_PREFETCH_L1_FAULT,
33 TILEGX_OPC_PREFETCH_L2,
34 TILEGX_OPC_PREFETCH_L2_FAULT,
35 TILEGX_OPC_PREFETCH_L3,
36 TILEGX_OPC_PREFETCH_L3_FAULT,
37 TILEGX_OPC_RAISE,
38 TILEGX_OPC_ADD,
39 TILEGX_OPC_ADDI,
40 TILEGX_OPC_ADDLI,
41 TILEGX_OPC_ADDX,
42 TILEGX_OPC_ADDXI,
43 TILEGX_OPC_ADDXLI,
44 TILEGX_OPC_ADDXSC,
45 TILEGX_OPC_AND,
46 TILEGX_OPC_ANDI,
47 TILEGX_OPC_BEQZ,
48 TILEGX_OPC_BEQZT,
49 TILEGX_OPC_BFEXTS,
50 TILEGX_OPC_BFEXTU,
51 TILEGX_OPC_BFINS,
52 TILEGX_OPC_BGEZ,
53 TILEGX_OPC_BGEZT,
54 TILEGX_OPC_BGTZ,
55 TILEGX_OPC_BGTZT,
56 TILEGX_OPC_BLBC,
57 TILEGX_OPC_BLBCT,
58 TILEGX_OPC_BLBS,
59 TILEGX_OPC_BLBST,
60 TILEGX_OPC_BLEZ,
61 TILEGX_OPC_BLEZT,
62 TILEGX_OPC_BLTZ,
63 TILEGX_OPC_BLTZT,
64 TILEGX_OPC_BNEZ,
65 TILEGX_OPC_BNEZT,
66 TILEGX_OPC_CLZ,
67 TILEGX_OPC_CMOVEQZ,
68 TILEGX_OPC_CMOVNEZ,
69 TILEGX_OPC_CMPEQ,
70 TILEGX_OPC_CMPEQI,
71 TILEGX_OPC_CMPEXCH,
72 TILEGX_OPC_CMPEXCH4,
73 TILEGX_OPC_CMPLES,
74 TILEGX_OPC_CMPLEU,
75 TILEGX_OPC_CMPLTS,
76 TILEGX_OPC_CMPLTSI,
77 TILEGX_OPC_CMPLTU,
78 TILEGX_OPC_CMPLTUI,
79 TILEGX_OPC_CMPNE,
80 TILEGX_OPC_CMUL,
81 TILEGX_OPC_CMULA,
82 TILEGX_OPC_CMULAF,
83 TILEGX_OPC_CMULF,
84 TILEGX_OPC_CMULFR,
85 TILEGX_OPC_CMULH,
86 TILEGX_OPC_CMULHR,
87 TILEGX_OPC_CRC32_32,
88 TILEGX_OPC_CRC32_8,
89 TILEGX_OPC_CTZ,
90 TILEGX_OPC_DBLALIGN,
91 TILEGX_OPC_DBLALIGN2,
92 TILEGX_OPC_DBLALIGN4,
93 TILEGX_OPC_DBLALIGN6,
94 TILEGX_OPC_DRAIN,
95 TILEGX_OPC_DTLBPR,
96 TILEGX_OPC_EXCH,
97 TILEGX_OPC_EXCH4,
98 TILEGX_OPC_FDOUBLE_ADD_FLAGS,
99 TILEGX_OPC_FDOUBLE_ADDSUB,
100 TILEGX_OPC_FDOUBLE_MUL_FLAGS,
101 TILEGX_OPC_FDOUBLE_PACK1,
102 TILEGX_OPC_FDOUBLE_PACK2,
103 TILEGX_OPC_FDOUBLE_SUB_FLAGS,
104 TILEGX_OPC_FDOUBLE_UNPACK_MAX,
105 TILEGX_OPC_FDOUBLE_UNPACK_MIN,
106 TILEGX_OPC_FETCHADD,
107 TILEGX_OPC_FETCHADD4,
108 TILEGX_OPC_FETCHADDGEZ,
109 TILEGX_OPC_FETCHADDGEZ4,
110 TILEGX_OPC_FETCHAND,
111 TILEGX_OPC_FETCHAND4,
112 TILEGX_OPC_FETCHOR,
113 TILEGX_OPC_FETCHOR4,
114 TILEGX_OPC_FINV,
115 TILEGX_OPC_FLUSH,
116 TILEGX_OPC_FLUSHWB,
117 TILEGX_OPC_FNOP,
118 TILEGX_OPC_FSINGLE_ADD1,
119 TILEGX_OPC_FSINGLE_ADDSUB2,
120 TILEGX_OPC_FSINGLE_MUL1,
121 TILEGX_OPC_FSINGLE_MUL2,
122 TILEGX_OPC_FSINGLE_PACK1,
123 TILEGX_OPC_FSINGLE_PACK2,
124 TILEGX_OPC_FSINGLE_SUB1,
125 TILEGX_OPC_ICOH,
126 TILEGX_OPC_ILL,
127 TILEGX_OPC_INV,
128 TILEGX_OPC_IRET,
129 TILEGX_OPC_J,
130 TILEGX_OPC_JAL,
131 TILEGX_OPC_JALR,
132 TILEGX_OPC_JALRP,
133 TILEGX_OPC_JR,
134 TILEGX_OPC_JRP,
135 TILEGX_OPC_LD,
136 TILEGX_OPC_LD1S,
137 TILEGX_OPC_LD1S_ADD,
138 TILEGX_OPC_LD1U,
139 TILEGX_OPC_LD1U_ADD,
140 TILEGX_OPC_LD2S,
141 TILEGX_OPC_LD2S_ADD,
142 TILEGX_OPC_LD2U,
143 TILEGX_OPC_LD2U_ADD,
144 TILEGX_OPC_LD4S,
145 TILEGX_OPC_LD4S_ADD,
146 TILEGX_OPC_LD4U,
147 TILEGX_OPC_LD4U_ADD,
148 TILEGX_OPC_LD_ADD,
149 TILEGX_OPC_LDNA,
150 TILEGX_OPC_LDNA_ADD,
151 TILEGX_OPC_LDNT,
152 TILEGX_OPC_LDNT1S,
153 TILEGX_OPC_LDNT1S_ADD,
154 TILEGX_OPC_LDNT1U,
155 TILEGX_OPC_LDNT1U_ADD,
156 TILEGX_OPC_LDNT2S,
157 TILEGX_OPC_LDNT2S_ADD,
158 TILEGX_OPC_LDNT2U,
159 TILEGX_OPC_LDNT2U_ADD,
160 TILEGX_OPC_LDNT4S,
161 TILEGX_OPC_LDNT4S_ADD,
162 TILEGX_OPC_LDNT4U,
163 TILEGX_OPC_LDNT4U_ADD,
164 TILEGX_OPC_LDNT_ADD,
165 TILEGX_OPC_LNK,
166 TILEGX_OPC_MF,
167 TILEGX_OPC_MFSPR,
168 TILEGX_OPC_MM,
169 TILEGX_OPC_MNZ,
170 TILEGX_OPC_MTSPR,
171 TILEGX_OPC_MUL_HS_HS,
172 TILEGX_OPC_MUL_HS_HU,
173 TILEGX_OPC_MUL_HS_LS,
174 TILEGX_OPC_MUL_HS_LU,
175 TILEGX_OPC_MUL_HU_HU,
176 TILEGX_OPC_MUL_HU_LS,
177 TILEGX_OPC_MUL_HU_LU,
178 TILEGX_OPC_MUL_LS_LS,
179 TILEGX_OPC_MUL_LS_LU,
180 TILEGX_OPC_MUL_LU_LU,
181 TILEGX_OPC_MULA_HS_HS,
182 TILEGX_OPC_MULA_HS_HU,
183 TILEGX_OPC_MULA_HS_LS,
184 TILEGX_OPC_MULA_HS_LU,
185 TILEGX_OPC_MULA_HU_HU,
186 TILEGX_OPC_MULA_HU_LS,
187 TILEGX_OPC_MULA_HU_LU,
188 TILEGX_OPC_MULA_LS_LS,
189 TILEGX_OPC_MULA_LS_LU,
190 TILEGX_OPC_MULA_LU_LU,
191 TILEGX_OPC_MULAX,
192 TILEGX_OPC_MULX,
193 TILEGX_OPC_MZ,
194 TILEGX_OPC_NAP,
195 TILEGX_OPC_NOP,
196 TILEGX_OPC_NOR,
197 TILEGX_OPC_OR,
198 TILEGX_OPC_ORI,
199 TILEGX_OPC_PCNT,
200 TILEGX_OPC_REVBITS,
201 TILEGX_OPC_REVBYTES,
202 TILEGX_OPC_ROTL,
203 TILEGX_OPC_ROTLI,
204 TILEGX_OPC_SHL,
205 TILEGX_OPC_SHL16INSLI,
206 TILEGX_OPC_SHL1ADD,
207 TILEGX_OPC_SHL1ADDX,
208 TILEGX_OPC_SHL2ADD,
209 TILEGX_OPC_SHL2ADDX,
210 TILEGX_OPC_SHL3ADD,
211 TILEGX_OPC_SHL3ADDX,
212 TILEGX_OPC_SHLI,
213 TILEGX_OPC_SHLX,
214 TILEGX_OPC_SHLXI,
215 TILEGX_OPC_SHRS,
216 TILEGX_OPC_SHRSI,
217 TILEGX_OPC_SHRU,
218 TILEGX_OPC_SHRUI,
219 TILEGX_OPC_SHRUX,
220 TILEGX_OPC_SHRUXI,
221 TILEGX_OPC_SHUFFLEBYTES,
222 TILEGX_OPC_ST,
223 TILEGX_OPC_ST1,
224 TILEGX_OPC_ST1_ADD,
225 TILEGX_OPC_ST2,
226 TILEGX_OPC_ST2_ADD,
227 TILEGX_OPC_ST4,
228 TILEGX_OPC_ST4_ADD,
229 TILEGX_OPC_ST_ADD,
230 TILEGX_OPC_STNT,
231 TILEGX_OPC_STNT1,
232 TILEGX_OPC_STNT1_ADD,
233 TILEGX_OPC_STNT2,
234 TILEGX_OPC_STNT2_ADD,
235 TILEGX_OPC_STNT4,
236 TILEGX_OPC_STNT4_ADD,
237 TILEGX_OPC_STNT_ADD,
238 TILEGX_OPC_SUB,
239 TILEGX_OPC_SUBX,
240 TILEGX_OPC_SUBXSC,
241 TILEGX_OPC_SWINT0,
242 TILEGX_OPC_SWINT1,
243 TILEGX_OPC_SWINT2,
244 TILEGX_OPC_SWINT3,
245 TILEGX_OPC_TBLIDXB0,
246 TILEGX_OPC_TBLIDXB1,
247 TILEGX_OPC_TBLIDXB2,
248 TILEGX_OPC_TBLIDXB3,
249 TILEGX_OPC_V1ADD,
250 TILEGX_OPC_V1ADDI,
251 TILEGX_OPC_V1ADDUC,
252 TILEGX_OPC_V1ADIFFU,
253 TILEGX_OPC_V1AVGU,
254 TILEGX_OPC_V1CMPEQ,
255 TILEGX_OPC_V1CMPEQI,
256 TILEGX_OPC_V1CMPLES,
257 TILEGX_OPC_V1CMPLEU,
258 TILEGX_OPC_V1CMPLTS,
259 TILEGX_OPC_V1CMPLTSI,
260 TILEGX_OPC_V1CMPLTU,
261 TILEGX_OPC_V1CMPLTUI,
262 TILEGX_OPC_V1CMPNE,
263 TILEGX_OPC_V1DDOTPU,
264 TILEGX_OPC_V1DDOTPUA,
265 TILEGX_OPC_V1DDOTPUS,
266 TILEGX_OPC_V1DDOTPUSA,
267 TILEGX_OPC_V1DOTP,
268 TILEGX_OPC_V1DOTPA,
269 TILEGX_OPC_V1DOTPU,
270 TILEGX_OPC_V1DOTPUA,
271 TILEGX_OPC_V1DOTPUS,
272 TILEGX_OPC_V1DOTPUSA,
273 TILEGX_OPC_V1INT_H,
274 TILEGX_OPC_V1INT_L,
275 TILEGX_OPC_V1MAXU,
276 TILEGX_OPC_V1MAXUI,
277 TILEGX_OPC_V1MINU,
278 TILEGX_OPC_V1MINUI,
279 TILEGX_OPC_V1MNZ,
280 TILEGX_OPC_V1MULTU,
281 TILEGX_OPC_V1MULU,
282 TILEGX_OPC_V1MULUS,
283 TILEGX_OPC_V1MZ,
284 TILEGX_OPC_V1SADAU,
285 TILEGX_OPC_V1SADU,
286 TILEGX_OPC_V1SHL,
287 TILEGX_OPC_V1SHLI,
288 TILEGX_OPC_V1SHRS,
289 TILEGX_OPC_V1SHRSI,
290 TILEGX_OPC_V1SHRU,
291 TILEGX_OPC_V1SHRUI,
292 TILEGX_OPC_V1SUB,
293 TILEGX_OPC_V1SUBUC,
294 TILEGX_OPC_V2ADD,
295 TILEGX_OPC_V2ADDI,
296 TILEGX_OPC_V2ADDSC,
297 TILEGX_OPC_V2ADIFFS,
298 TILEGX_OPC_V2AVGS,
299 TILEGX_OPC_V2CMPEQ,
300 TILEGX_OPC_V2CMPEQI,
301 TILEGX_OPC_V2CMPLES,
302 TILEGX_OPC_V2CMPLEU,
303 TILEGX_OPC_V2CMPLTS,
304 TILEGX_OPC_V2CMPLTSI,
305 TILEGX_OPC_V2CMPLTU,
306 TILEGX_OPC_V2CMPLTUI,
307 TILEGX_OPC_V2CMPNE,
308 TILEGX_OPC_V2DOTP,
309 TILEGX_OPC_V2DOTPA,
310 TILEGX_OPC_V2INT_H,
311 TILEGX_OPC_V2INT_L,
312 TILEGX_OPC_V2MAXS,
313 TILEGX_OPC_V2MAXSI,
314 TILEGX_OPC_V2MINS,
315 TILEGX_OPC_V2MINSI,
316 TILEGX_OPC_V2MNZ,
317 TILEGX_OPC_V2MULFSC,
318 TILEGX_OPC_V2MULS,
319 TILEGX_OPC_V2MULTS,
320 TILEGX_OPC_V2MZ,
321 TILEGX_OPC_V2PACKH,
322 TILEGX_OPC_V2PACKL,
323 TILEGX_OPC_V2PACKUC,
324 TILEGX_OPC_V2SADAS,
325 TILEGX_OPC_V2SADAU,
326 TILEGX_OPC_V2SADS,
327 TILEGX_OPC_V2SADU,
328 TILEGX_OPC_V2SHL,
329 TILEGX_OPC_V2SHLI,
330 TILEGX_OPC_V2SHLSC,
331 TILEGX_OPC_V2SHRS,
332 TILEGX_OPC_V2SHRSI,
333 TILEGX_OPC_V2SHRU,
334 TILEGX_OPC_V2SHRUI,
335 TILEGX_OPC_V2SUB,
336 TILEGX_OPC_V2SUBSC,
337 TILEGX_OPC_V4ADD,
338 TILEGX_OPC_V4ADDSC,
339 TILEGX_OPC_V4INT_H,
340 TILEGX_OPC_V4INT_L,
341 TILEGX_OPC_V4PACKSC,
342 TILEGX_OPC_V4SHL,
343 TILEGX_OPC_V4SHLSC,
344 TILEGX_OPC_V4SHRS,
345 TILEGX_OPC_V4SHRU,
346 TILEGX_OPC_V4SUB,
347 TILEGX_OPC_V4SUBSC,
348 TILEGX_OPC_WH64,
349 TILEGX_OPC_XOR,
350 TILEGX_OPC_XORI,
351 TILEGX_OPC_NONE
352} tilegx_mnemonic;
353
354/* 64-bit pattern for a { bpt ; nop } bundle. */
355#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
356
357
358#define TILE_ELF_MACHINE_CODE EM_TILE64
359
360#define TILE_ELF_NAME "elf32-tile64"
361
362
363static __inline unsigned int
364get_BFEnd_X0(tilegx_bundle_bits num)
365{
366 const unsigned int n = (unsigned int)num;
367 return (((n >> 12)) & 0x3f);
368}
369
370static __inline unsigned int
371get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
372{
373 const unsigned int n = (unsigned int)num;
374 return (((n >> 24)) & 0xf);
375}
376
377static __inline unsigned int
378get_BFStart_X0(tilegx_bundle_bits num)
379{
380 const unsigned int n = (unsigned int)num;
381 return (((n >> 18)) & 0x3f);
382}
383
384static __inline unsigned int
385get_BrOff_X1(tilegx_bundle_bits n)
386{
387 return (((unsigned int)(n >> 31)) & 0x0000003f) |
388 (((unsigned int)(n >> 37)) & 0x0001ffc0);
389}
390
391static __inline unsigned int
392get_BrType_X1(tilegx_bundle_bits n)
393{
394 return (((unsigned int)(n >> 54)) & 0x1f);
395}
396
397static __inline unsigned int
398get_Dest_Imm8_X1(tilegx_bundle_bits n)
399{
400 return (((unsigned int)(n >> 31)) & 0x0000003f) |
401 (((unsigned int)(n >> 43)) & 0x000000c0);
402}
403
404static __inline unsigned int
405get_Dest_X0(tilegx_bundle_bits num)
406{
407 const unsigned int n = (unsigned int)num;
408 return (((n >> 0)) & 0x3f);
409}
410
411static __inline unsigned int
412get_Dest_X1(tilegx_bundle_bits n)
413{
414 return (((unsigned int)(n >> 31)) & 0x3f);
415}
416
417static __inline unsigned int
418get_Dest_Y0(tilegx_bundle_bits num)
419{
420 const unsigned int n = (unsigned int)num;
421 return (((n >> 0)) & 0x3f);
422}
423
424static __inline unsigned int
425get_Dest_Y1(tilegx_bundle_bits n)
426{
427 return (((unsigned int)(n >> 31)) & 0x3f);
428}
429
430static __inline unsigned int
431get_Imm16_X0(tilegx_bundle_bits num)
432{
433 const unsigned int n = (unsigned int)num;
434 return (((n >> 12)) & 0xffff);
435}
436
437static __inline unsigned int
438get_Imm16_X1(tilegx_bundle_bits n)
439{
440 return (((unsigned int)(n >> 43)) & 0xffff);
441}
442
443static __inline unsigned int
444get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
445{
446 const unsigned int n = (unsigned int)num;
447 return (((n >> 20)) & 0xff);
448}
449
450static __inline unsigned int
451get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
452{
453 return (((unsigned int)(n >> 51)) & 0xff);
454}
455
456static __inline unsigned int
457get_Imm8_X0(tilegx_bundle_bits num)
458{
459 const unsigned int n = (unsigned int)num;
460 return (((n >> 12)) & 0xff);
461}
462
463static __inline unsigned int
464get_Imm8_X1(tilegx_bundle_bits n)
465{
466 return (((unsigned int)(n >> 43)) & 0xff);
467}
468
469static __inline unsigned int
470get_Imm8_Y0(tilegx_bundle_bits num)
471{
472 const unsigned int n = (unsigned int)num;
473 return (((n >> 12)) & 0xff);
474}
475
476static __inline unsigned int
477get_Imm8_Y1(tilegx_bundle_bits n)
478{
479 return (((unsigned int)(n >> 43)) & 0xff);
480}
481
482static __inline unsigned int
483get_JumpOff_X1(tilegx_bundle_bits n)
484{
485 return (((unsigned int)(n >> 31)) & 0x7ffffff);
486}
487
488static __inline unsigned int
489get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
490{
491 return (((unsigned int)(n >> 58)) & 0x1);
492}
493
494static __inline unsigned int
495get_MF_Imm14_X1(tilegx_bundle_bits n)
496{
497 return (((unsigned int)(n >> 37)) & 0x3fff);
498}
499
500static __inline unsigned int
501get_MT_Imm14_X1(tilegx_bundle_bits n)
502{
503 return (((unsigned int)(n >> 31)) & 0x0000003f) |
504 (((unsigned int)(n >> 37)) & 0x00003fc0);
505}
506
507static __inline unsigned int
508get_Mode(tilegx_bundle_bits n)
509{
510 return (((unsigned int)(n >> 62)) & 0x3);
511}
512
513static __inline unsigned int
514get_Opcode_X0(tilegx_bundle_bits num)
515{
516 const unsigned int n = (unsigned int)num;
517 return (((n >> 28)) & 0x7);
518}
519
520static __inline unsigned int
521get_Opcode_X1(tilegx_bundle_bits n)
522{
523 return (((unsigned int)(n >> 59)) & 0x7);
524}
525
526static __inline unsigned int
527get_Opcode_Y0(tilegx_bundle_bits num)
528{
529 const unsigned int n = (unsigned int)num;
530 return (((n >> 27)) & 0xf);
531}
532
533static __inline unsigned int
534get_Opcode_Y1(tilegx_bundle_bits n)
535{
536 return (((unsigned int)(n >> 58)) & 0xf);
537}
538
539static __inline unsigned int
540get_Opcode_Y2(tilegx_bundle_bits n)
541{
542 return (((n >> 26)) & 0x00000001) |
543 (((unsigned int)(n >> 56)) & 0x00000002);
544}
545
546static __inline unsigned int
547get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
548{
549 const unsigned int n = (unsigned int)num;
550 return (((n >> 18)) & 0x3ff);
551}
552
553static __inline unsigned int
554get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
555{
556 return (((unsigned int)(n >> 49)) & 0x3ff);
557}
558
559static __inline unsigned int
560get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
561{
562 const unsigned int n = (unsigned int)num;
563 return (((n >> 18)) & 0x3);
564}
565
566static __inline unsigned int
567get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
568{
569 return (((unsigned int)(n >> 49)) & 0x3);
570}
571
572static __inline unsigned int
573get_ShAmt_X0(tilegx_bundle_bits num)
574{
575 const unsigned int n = (unsigned int)num;
576 return (((n >> 12)) & 0x3f);
577}
578
579static __inline unsigned int
580get_ShAmt_X1(tilegx_bundle_bits n)
581{
582 return (((unsigned int)(n >> 43)) & 0x3f);
583}
584
585static __inline unsigned int
586get_ShAmt_Y0(tilegx_bundle_bits num)
587{
588 const unsigned int n = (unsigned int)num;
589 return (((n >> 12)) & 0x3f);
590}
591
592static __inline unsigned int
593get_ShAmt_Y1(tilegx_bundle_bits n)
594{
595 return (((unsigned int)(n >> 43)) & 0x3f);
596}
597
598static __inline unsigned int
599get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
600{
601 const unsigned int n = (unsigned int)num;
602 return (((n >> 18)) & 0x3ff);
603}
604
605static __inline unsigned int
606get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
607{
608 return (((unsigned int)(n >> 49)) & 0x3ff);
609}
610
611static __inline unsigned int
612get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
613{
614 const unsigned int n = (unsigned int)num;
615 return (((n >> 18)) & 0x3);
616}
617
618static __inline unsigned int
619get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
620{
621 return (((unsigned int)(n >> 49)) & 0x3);
622}
623
624static __inline unsigned int
625get_SrcA_X0(tilegx_bundle_bits num)
626{
627 const unsigned int n = (unsigned int)num;
628 return (((n >> 6)) & 0x3f);
629}
630
631static __inline unsigned int
632get_SrcA_X1(tilegx_bundle_bits n)
633{
634 return (((unsigned int)(n >> 37)) & 0x3f);
635}
636
637static __inline unsigned int
638get_SrcA_Y0(tilegx_bundle_bits num)
639{
640 const unsigned int n = (unsigned int)num;
641 return (((n >> 6)) & 0x3f);
642}
643
644static __inline unsigned int
645get_SrcA_Y1(tilegx_bundle_bits n)
646{
647 return (((unsigned int)(n >> 37)) & 0x3f);
648}
649
650static __inline unsigned int
651get_SrcA_Y2(tilegx_bundle_bits num)
652{
653 const unsigned int n = (unsigned int)num;
654 return (((n >> 20)) & 0x3f);
655}
656
657static __inline unsigned int
658get_SrcBDest_Y2(tilegx_bundle_bits n)
659{
660 return (((unsigned int)(n >> 51)) & 0x3f);
661}
662
663static __inline unsigned int
664get_SrcB_X0(tilegx_bundle_bits num)
665{
666 const unsigned int n = (unsigned int)num;
667 return (((n >> 12)) & 0x3f);
668}
669
670static __inline unsigned int
671get_SrcB_X1(tilegx_bundle_bits n)
672{
673 return (((unsigned int)(n >> 43)) & 0x3f);
674}
675
676static __inline unsigned int
677get_SrcB_Y0(tilegx_bundle_bits num)
678{
679 const unsigned int n = (unsigned int)num;
680 return (((n >> 12)) & 0x3f);
681}
682
683static __inline unsigned int
684get_SrcB_Y1(tilegx_bundle_bits n)
685{
686 return (((unsigned int)(n >> 43)) & 0x3f);
687}
688
689static __inline unsigned int
690get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
691{
692 const unsigned int n = (unsigned int)num;
693 return (((n >> 12)) & 0x3f);
694}
695
696static __inline unsigned int
697get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
698{
699 return (((unsigned int)(n >> 43)) & 0x3f);
700}
701
702static __inline unsigned int
703get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
704{
705 const unsigned int n = (unsigned int)num;
706 return (((n >> 12)) & 0x3f);
707}
708
709static __inline unsigned int
710get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
711{
712 return (((unsigned int)(n >> 43)) & 0x3f);
713}
714
715
716static __inline int
717sign_extend(int n, int num_bits)
718{
719 int shift = (int)(sizeof(int) * 8 - num_bits);
720 return (n << shift) >> shift;
721}
722
723
724
725static __inline tilegx_bundle_bits
726create_BFEnd_X0(int num)
727{
728 const unsigned int n = (unsigned int)num;
729 return ((n & 0x3f) << 12);
730}
731
732static __inline tilegx_bundle_bits
733create_BFOpcodeExtension_X0(int num)
734{
735 const unsigned int n = (unsigned int)num;
736 return ((n & 0xf) << 24);
737}
738
739static __inline tilegx_bundle_bits
740create_BFStart_X0(int num)
741{
742 const unsigned int n = (unsigned int)num;
743 return ((n & 0x3f) << 18);
744}
745
746static __inline tilegx_bundle_bits
747create_BrOff_X1(int num)
748{
749 const unsigned int n = (unsigned int)num;
750 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
751 (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
752}
753
754static __inline tilegx_bundle_bits
755create_BrType_X1(int num)
756{
757 const unsigned int n = (unsigned int)num;
758 return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
759}
760
761static __inline tilegx_bundle_bits
762create_Dest_Imm8_X1(int num)
763{
764 const unsigned int n = (unsigned int)num;
765 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
766 (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
767}
768
769static __inline tilegx_bundle_bits
770create_Dest_X0(int num)
771{
772 const unsigned int n = (unsigned int)num;
773 return ((n & 0x3f) << 0);
774}
775
776static __inline tilegx_bundle_bits
777create_Dest_X1(int num)
778{
779 const unsigned int n = (unsigned int)num;
780 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
781}
782
783static __inline tilegx_bundle_bits
784create_Dest_Y0(int num)
785{
786 const unsigned int n = (unsigned int)num;
787 return ((n & 0x3f) << 0);
788}
789
790static __inline tilegx_bundle_bits
791create_Dest_Y1(int num)
792{
793 const unsigned int n = (unsigned int)num;
794 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
795}
796
797static __inline tilegx_bundle_bits
798create_Imm16_X0(int num)
799{
800 const unsigned int n = (unsigned int)num;
801 return ((n & 0xffff) << 12);
802}
803
804static __inline tilegx_bundle_bits
805create_Imm16_X1(int num)
806{
807 const unsigned int n = (unsigned int)num;
808 return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
809}
810
811static __inline tilegx_bundle_bits
812create_Imm8OpcodeExtension_X0(int num)
813{
814 const unsigned int n = (unsigned int)num;
815 return ((n & 0xff) << 20);
816}
817
818static __inline tilegx_bundle_bits
819create_Imm8OpcodeExtension_X1(int num)
820{
821 const unsigned int n = (unsigned int)num;
822 return (((tilegx_bundle_bits)(n & 0xff)) << 51);
823}
824
825static __inline tilegx_bundle_bits
826create_Imm8_X0(int num)
827{
828 const unsigned int n = (unsigned int)num;
829 return ((n & 0xff) << 12);
830}
831
832static __inline tilegx_bundle_bits
833create_Imm8_X1(int num)
834{
835 const unsigned int n = (unsigned int)num;
836 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
837}
838
839static __inline tilegx_bundle_bits
840create_Imm8_Y0(int num)
841{
842 const unsigned int n = (unsigned int)num;
843 return ((n & 0xff) << 12);
844}
845
846static __inline tilegx_bundle_bits
847create_Imm8_Y1(int num)
848{
849 const unsigned int n = (unsigned int)num;
850 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
851}
852
853static __inline tilegx_bundle_bits
854create_JumpOff_X1(int num)
855{
856 const unsigned int n = (unsigned int)num;
857 return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
858}
859
860static __inline tilegx_bundle_bits
861create_JumpOpcodeExtension_X1(int num)
862{
863 const unsigned int n = (unsigned int)num;
864 return (((tilegx_bundle_bits)(n & 0x1)) << 58);
865}
866
867static __inline tilegx_bundle_bits
868create_MF_Imm14_X1(int num)
869{
870 const unsigned int n = (unsigned int)num;
871 return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
872}
873
874static __inline tilegx_bundle_bits
875create_MT_Imm14_X1(int num)
876{
877 const unsigned int n = (unsigned int)num;
878 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
879 (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
880}
881
882static __inline tilegx_bundle_bits
883create_Mode(int num)
884{
885 const unsigned int n = (unsigned int)num;
886 return (((tilegx_bundle_bits)(n & 0x3)) << 62);
887}
888
889static __inline tilegx_bundle_bits
890create_Opcode_X0(int num)
891{
892 const unsigned int n = (unsigned int)num;
893 return ((n & 0x7) << 28);
894}
895
896static __inline tilegx_bundle_bits
897create_Opcode_X1(int num)
898{
899 const unsigned int n = (unsigned int)num;
900 return (((tilegx_bundle_bits)(n & 0x7)) << 59);
901}
902
903static __inline tilegx_bundle_bits
904create_Opcode_Y0(int num)
905{
906 const unsigned int n = (unsigned int)num;
907 return ((n & 0xf) << 27);
908}
909
910static __inline tilegx_bundle_bits
911create_Opcode_Y1(int num)
912{
913 const unsigned int n = (unsigned int)num;
914 return (((tilegx_bundle_bits)(n & 0xf)) << 58);
915}
916
917static __inline tilegx_bundle_bits
918create_Opcode_Y2(int num)
919{
920 const unsigned int n = (unsigned int)num;
921 return ((n & 0x00000001) << 26) |
922 (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
923}
924
925static __inline tilegx_bundle_bits
926create_RRROpcodeExtension_X0(int num)
927{
928 const unsigned int n = (unsigned int)num;
929 return ((n & 0x3ff) << 18);
930}
931
932static __inline tilegx_bundle_bits
933create_RRROpcodeExtension_X1(int num)
934{
935 const unsigned int n = (unsigned int)num;
936 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
937}
938
939static __inline tilegx_bundle_bits
940create_RRROpcodeExtension_Y0(int num)
941{
942 const unsigned int n = (unsigned int)num;
943 return ((n & 0x3) << 18);
944}
945
946static __inline tilegx_bundle_bits
947create_RRROpcodeExtension_Y1(int num)
948{
949 const unsigned int n = (unsigned int)num;
950 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
951}
952
953static __inline tilegx_bundle_bits
954create_ShAmt_X0(int num)
955{
956 const unsigned int n = (unsigned int)num;
957 return ((n & 0x3f) << 12);
958}
959
960static __inline tilegx_bundle_bits
961create_ShAmt_X1(int num)
962{
963 const unsigned int n = (unsigned int)num;
964 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
965}
966
967static __inline tilegx_bundle_bits
968create_ShAmt_Y0(int num)
969{
970 const unsigned int n = (unsigned int)num;
971 return ((n & 0x3f) << 12);
972}
973
974static __inline tilegx_bundle_bits
975create_ShAmt_Y1(int num)
976{
977 const unsigned int n = (unsigned int)num;
978 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
979}
980
981static __inline tilegx_bundle_bits
982create_ShiftOpcodeExtension_X0(int num)
983{
984 const unsigned int n = (unsigned int)num;
985 return ((n & 0x3ff) << 18);
986}
987
988static __inline tilegx_bundle_bits
989create_ShiftOpcodeExtension_X1(int num)
990{
991 const unsigned int n = (unsigned int)num;
992 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
993}
994
995static __inline tilegx_bundle_bits
996create_ShiftOpcodeExtension_Y0(int num)
997{
998 const unsigned int n = (unsigned int)num;
999 return ((n & 0x3) << 18);
1000}
1001
1002static __inline tilegx_bundle_bits
1003create_ShiftOpcodeExtension_Y1(int num)
1004{
1005 const unsigned int n = (unsigned int)num;
1006 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1007}
1008
1009static __inline tilegx_bundle_bits
1010create_SrcA_X0(int num)
1011{
1012 const unsigned int n = (unsigned int)num;
1013 return ((n & 0x3f) << 6);
1014}
1015
1016static __inline tilegx_bundle_bits
1017create_SrcA_X1(int num)
1018{
1019 const unsigned int n = (unsigned int)num;
1020 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1021}
1022
1023static __inline tilegx_bundle_bits
1024create_SrcA_Y0(int num)
1025{
1026 const unsigned int n = (unsigned int)num;
1027 return ((n & 0x3f) << 6);
1028}
1029
1030static __inline tilegx_bundle_bits
1031create_SrcA_Y1(int num)
1032{
1033 const unsigned int n = (unsigned int)num;
1034 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1035}
1036
1037static __inline tilegx_bundle_bits
1038create_SrcA_Y2(int num)
1039{
1040 const unsigned int n = (unsigned int)num;
1041 return ((n & 0x3f) << 20);
1042}
1043
1044static __inline tilegx_bundle_bits
1045create_SrcBDest_Y2(int num)
1046{
1047 const unsigned int n = (unsigned int)num;
1048 return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
1049}
1050
1051static __inline tilegx_bundle_bits
1052create_SrcB_X0(int num)
1053{
1054 const unsigned int n = (unsigned int)num;
1055 return ((n & 0x3f) << 12);
1056}
1057
1058static __inline tilegx_bundle_bits
1059create_SrcB_X1(int num)
1060{
1061 const unsigned int n = (unsigned int)num;
1062 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1063}
1064
1065static __inline tilegx_bundle_bits
1066create_SrcB_Y0(int num)
1067{
1068 const unsigned int n = (unsigned int)num;
1069 return ((n & 0x3f) << 12);
1070}
1071
1072static __inline tilegx_bundle_bits
1073create_SrcB_Y1(int num)
1074{
1075 const unsigned int n = (unsigned int)num;
1076 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1077}
1078
1079static __inline tilegx_bundle_bits
1080create_UnaryOpcodeExtension_X0(int num)
1081{
1082 const unsigned int n = (unsigned int)num;
1083 return ((n & 0x3f) << 12);
1084}
1085
1086static __inline tilegx_bundle_bits
1087create_UnaryOpcodeExtension_X1(int num)
1088{
1089 const unsigned int n = (unsigned int)num;
1090 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1091}
1092
1093static __inline tilegx_bundle_bits
1094create_UnaryOpcodeExtension_Y0(int num)
1095{
1096 const unsigned int n = (unsigned int)num;
1097 return ((n & 0x3f) << 12);
1098}
1099
1100static __inline tilegx_bundle_bits
1101create_UnaryOpcodeExtension_Y1(int num)
1102{
1103 const unsigned int n = (unsigned int)num;
1104 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1105}
1106
1107
1108typedef enum
1109{
1110 TILEGX_PIPELINE_X0,
1111 TILEGX_PIPELINE_X1,
1112 TILEGX_PIPELINE_Y0,
1113 TILEGX_PIPELINE_Y1,
1114 TILEGX_PIPELINE_Y2,
1115} tilegx_pipeline;
1116
1117#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
1118
1119typedef enum
1120{
1121 TILEGX_OP_TYPE_REGISTER,
1122 TILEGX_OP_TYPE_IMMEDIATE,
1123 TILEGX_OP_TYPE_ADDRESS,
1124 TILEGX_OP_TYPE_SPR
1125} tilegx_operand_type;
1126
1127/* These are the bits that determine if a bundle is in the X encoding. */
1128#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
1129
1130enum
1131{
1132 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
1133 TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
1134
1135 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
1136 TILEGX_NUM_PIPELINE_ENCODINGS = 5,
1137
1138 /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
1139 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
1140
1141 /* Instructions take this many bytes. */
1142 TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
1143
1144 /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
1145 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
1146
1147 /* Bundles should be aligned modulo this number of bytes. */
1148 TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
1149 (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
1150
1151 /* Number of registers (some are magic, such as network I/O). */
1152 TILEGX_NUM_REGISTERS = 64,
1153};
1154
1155
1156struct tilegx_operand
1157{
1158 /* Is this operand a register, immediate or address? */
1159 tilegx_operand_type type;
1160
1161 /* The default relocation type for this operand. */
1162 signed int default_reloc : 16;
1163
1164 /* How many bits is this value? (used for range checking) */
1165 unsigned int num_bits : 5;
1166
1167 /* Is the value signed? (used for range checking) */
1168 unsigned int is_signed : 1;
1169
1170 /* Is this operand a source register? */
1171 unsigned int is_src_reg : 1;
1172
1173 /* Is this operand written? (i.e. is it a destination register) */
1174 unsigned int is_dest_reg : 1;
1175
1176 /* Is this operand PC-relative? */
1177 unsigned int is_pc_relative : 1;
1178
1179 /* By how many bits do we right shift the value before inserting? */
1180 unsigned int rightshift : 2;
1181
1182 /* Return the bits for this operand to be ORed into an existing bundle. */
1183 tilegx_bundle_bits (*insert) (int op);
1184
1185 /* Extract this operand and return it. */
1186 unsigned int (*extract) (tilegx_bundle_bits bundle);
1187};
1188
1189
1190extern const struct tilegx_operand tilegx_operands[];
1191
1192/* One finite-state machine per pipe for rapid instruction decoding. */
1193extern const unsigned short * const
1194tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
1195
1196
1197struct tilegx_opcode
1198{
1199 /* The opcode mnemonic, e.g. "add" */
1200 const char *name;
1201
1202 /* The enum value for this mnemonic. */
1203 tilegx_mnemonic mnemonic;
1204
1205 /* A bit mask of which of the five pipes this instruction
1206 is compatible with:
1207 X0 0x01
1208 X1 0x02
1209 Y0 0x04
1210 Y1 0x08
1211 Y2 0x10 */
1212 unsigned char pipes;
1213
1214 /* How many operands are there? */
1215 unsigned char num_operands;
1216
1217 /* Which register does this write implicitly, or TREG_ZERO if none? */
1218 unsigned char implicitly_written_register;
1219
1220 /* Can this be bundled with other instructions (almost always true). */
1221 unsigned char can_bundle;
1222
1223 /* The description of the operands. Each of these is an
1224 * index into the tilegx_operands[] table. */
1225 unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
1226
1227};
1228
1229extern const struct tilegx_opcode tilegx_opcodes[];
1230
1231/* Used for non-textual disassembly into structs. */
1232struct tilegx_decoded_instruction
1233{
1234 const struct tilegx_opcode *opcode;
1235 const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
1236 long long operand_values[TILEGX_MAX_OPERANDS];
1237};
1238
1239
1240/* Disassemble a bundle into a struct for machine processing. */
1241extern int parse_insn_tilegx(tilegx_bundle_bits bits,
1242 unsigned long long pc,
1243 struct tilegx_decoded_instruction
1244 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
1245
1246
1247
1248#endif /* opcode_tilegx_h */
diff --git a/arch/tile/include/asm/opcode_constants.h b/arch/tile/include/asm/opcode_constants.h
new file mode 100644
index 00000000000..37a9f2958cb
--- /dev/null
+++ b/arch/tile/include/asm/opcode_constants.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_OPCODE_CONSTANTS_H
16#define _ASM_TILE_OPCODE_CONSTANTS_H
17
18#include <arch/chip.h>
19
20#if CHIP_WORD_SIZE() == 64
21#include <asm/opcode_constants_64.h>
22#else
23#include <asm/opcode_constants_32.h>
24#endif
25
26#endif /* _ASM_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/opcode_constants_32.h b/arch/tile/include/asm/opcode_constants_32.h
new file mode 100644
index 00000000000..227d033b180
--- /dev/null
+++ b/arch/tile/include/asm/opcode_constants_32.h
@@ -0,0 +1,480 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* This file is machine-generated; DO NOT EDIT! */
16
17
18#ifndef _TILE_OPCODE_CONSTANTS_H
19#define _TILE_OPCODE_CONSTANTS_H
20enum
21{
22 ADDBS_U_SPECIAL_0_OPCODE_X0 = 98,
23 ADDBS_U_SPECIAL_0_OPCODE_X1 = 68,
24 ADDB_SPECIAL_0_OPCODE_X0 = 1,
25 ADDB_SPECIAL_0_OPCODE_X1 = 1,
26 ADDHS_SPECIAL_0_OPCODE_X0 = 99,
27 ADDHS_SPECIAL_0_OPCODE_X1 = 69,
28 ADDH_SPECIAL_0_OPCODE_X0 = 2,
29 ADDH_SPECIAL_0_OPCODE_X1 = 2,
30 ADDIB_IMM_0_OPCODE_X0 = 1,
31 ADDIB_IMM_0_OPCODE_X1 = 1,
32 ADDIH_IMM_0_OPCODE_X0 = 2,
33 ADDIH_IMM_0_OPCODE_X1 = 2,
34 ADDI_IMM_0_OPCODE_X0 = 3,
35 ADDI_IMM_0_OPCODE_X1 = 3,
36 ADDI_IMM_1_OPCODE_SN = 1,
37 ADDI_OPCODE_Y0 = 9,
38 ADDI_OPCODE_Y1 = 7,
39 ADDLIS_OPCODE_X0 = 1,
40 ADDLIS_OPCODE_X1 = 2,
41 ADDLI_OPCODE_X0 = 2,
42 ADDLI_OPCODE_X1 = 3,
43 ADDS_SPECIAL_0_OPCODE_X0 = 96,
44 ADDS_SPECIAL_0_OPCODE_X1 = 66,
45 ADD_SPECIAL_0_OPCODE_X0 = 3,
46 ADD_SPECIAL_0_OPCODE_X1 = 3,
47 ADD_SPECIAL_0_OPCODE_Y0 = 0,
48 ADD_SPECIAL_0_OPCODE_Y1 = 0,
49 ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4,
50 ADIFFH_SPECIAL_0_OPCODE_X0 = 5,
51 ANDI_IMM_0_OPCODE_X0 = 1,
52 ANDI_IMM_0_OPCODE_X1 = 4,
53 ANDI_OPCODE_Y0 = 10,
54 ANDI_OPCODE_Y1 = 8,
55 AND_SPECIAL_0_OPCODE_X0 = 6,
56 AND_SPECIAL_0_OPCODE_X1 = 4,
57 AND_SPECIAL_2_OPCODE_Y0 = 0,
58 AND_SPECIAL_2_OPCODE_Y1 = 0,
59 AULI_OPCODE_X0 = 3,
60 AULI_OPCODE_X1 = 4,
61 AVGB_U_SPECIAL_0_OPCODE_X0 = 7,
62 AVGH_SPECIAL_0_OPCODE_X0 = 8,
63 BBNST_BRANCH_OPCODE_X1 = 15,
64 BBNS_BRANCH_OPCODE_X1 = 14,
65 BBNS_OPCODE_SN = 63,
66 BBST_BRANCH_OPCODE_X1 = 13,
67 BBS_BRANCH_OPCODE_X1 = 12,
68 BBS_OPCODE_SN = 62,
69 BGEZT_BRANCH_OPCODE_X1 = 7,
70 BGEZ_BRANCH_OPCODE_X1 = 6,
71 BGEZ_OPCODE_SN = 61,
72 BGZT_BRANCH_OPCODE_X1 = 5,
73 BGZ_BRANCH_OPCODE_X1 = 4,
74 BGZ_OPCODE_SN = 58,
75 BITX_UN_0_SHUN_0_OPCODE_X0 = 1,
76 BITX_UN_0_SHUN_0_OPCODE_Y0 = 1,
77 BLEZT_BRANCH_OPCODE_X1 = 11,
78 BLEZ_BRANCH_OPCODE_X1 = 10,
79 BLEZ_OPCODE_SN = 59,
80 BLZT_BRANCH_OPCODE_X1 = 9,
81 BLZ_BRANCH_OPCODE_X1 = 8,
82 BLZ_OPCODE_SN = 60,
83 BNZT_BRANCH_OPCODE_X1 = 3,
84 BNZ_BRANCH_OPCODE_X1 = 2,
85 BNZ_OPCODE_SN = 57,
86 BPT_NOREG_RR_IMM_0_OPCODE_SN = 1,
87 BRANCH_OPCODE_X1 = 5,
88 BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2,
89 BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2,
90 BZT_BRANCH_OPCODE_X1 = 1,
91 BZ_BRANCH_OPCODE_X1 = 0,
92 BZ_OPCODE_SN = 56,
93 CLZ_UN_0_SHUN_0_OPCODE_X0 = 3,
94 CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3,
95 CRC32_32_SPECIAL_0_OPCODE_X0 = 9,
96 CRC32_8_SPECIAL_0_OPCODE_X0 = 10,
97 CTZ_UN_0_SHUN_0_OPCODE_X0 = 4,
98 CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4,
99 DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1,
100 DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2,
101 DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95,
102 FINV_UN_0_SHUN_0_OPCODE_X1 = 3,
103 FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4,
104 FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3,
105 FNOP_UN_0_SHUN_0_OPCODE_X0 = 5,
106 FNOP_UN_0_SHUN_0_OPCODE_X1 = 5,
107 FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5,
108 FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1,
109 HALT_NOREG_RR_IMM_0_OPCODE_SN = 0,
110 ICOH_UN_0_SHUN_0_OPCODE_X1 = 6,
111 ILL_UN_0_SHUN_0_OPCODE_X1 = 7,
112 ILL_UN_0_SHUN_0_OPCODE_Y1 = 2,
113 IMM_0_OPCODE_SN = 0,
114 IMM_0_OPCODE_X0 = 4,
115 IMM_0_OPCODE_X1 = 6,
116 IMM_1_OPCODE_SN = 1,
117 IMM_OPCODE_0_X0 = 5,
118 INTHB_SPECIAL_0_OPCODE_X0 = 11,
119 INTHB_SPECIAL_0_OPCODE_X1 = 5,
120 INTHH_SPECIAL_0_OPCODE_X0 = 12,
121 INTHH_SPECIAL_0_OPCODE_X1 = 6,
122 INTLB_SPECIAL_0_OPCODE_X0 = 13,
123 INTLB_SPECIAL_0_OPCODE_X1 = 7,
124 INTLH_SPECIAL_0_OPCODE_X0 = 14,
125 INTLH_SPECIAL_0_OPCODE_X1 = 8,
126 INV_UN_0_SHUN_0_OPCODE_X1 = 8,
127 IRET_UN_0_SHUN_0_OPCODE_X1 = 9,
128 JALB_OPCODE_X1 = 13,
129 JALF_OPCODE_X1 = 12,
130 JALRP_SPECIAL_0_OPCODE_X1 = 9,
131 JALRR_IMM_1_OPCODE_SN = 3,
132 JALR_RR_IMM_0_OPCODE_SN = 5,
133 JALR_SPECIAL_0_OPCODE_X1 = 10,
134 JB_OPCODE_X1 = 11,
135 JF_OPCODE_X1 = 10,
136 JRP_SPECIAL_0_OPCODE_X1 = 11,
137 JRR_IMM_1_OPCODE_SN = 2,
138 JR_RR_IMM_0_OPCODE_SN = 4,
139 JR_SPECIAL_0_OPCODE_X1 = 12,
140 LBADD_IMM_0_OPCODE_X1 = 22,
141 LBADD_U_IMM_0_OPCODE_X1 = 23,
142 LB_OPCODE_Y2 = 0,
143 LB_UN_0_SHUN_0_OPCODE_X1 = 10,
144 LB_U_OPCODE_Y2 = 1,
145 LB_U_UN_0_SHUN_0_OPCODE_X1 = 11,
146 LHADD_IMM_0_OPCODE_X1 = 24,
147 LHADD_U_IMM_0_OPCODE_X1 = 25,
148 LH_OPCODE_Y2 = 2,
149 LH_UN_0_SHUN_0_OPCODE_X1 = 12,
150 LH_U_OPCODE_Y2 = 3,
151 LH_U_UN_0_SHUN_0_OPCODE_X1 = 13,
152 LNK_SPECIAL_0_OPCODE_X1 = 13,
153 LWADD_IMM_0_OPCODE_X1 = 26,
154 LWADD_NA_IMM_0_OPCODE_X1 = 27,
155 LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24,
156 LW_OPCODE_Y2 = 4,
157 LW_UN_0_SHUN_0_OPCODE_X1 = 14,
158 MAXB_U_SPECIAL_0_OPCODE_X0 = 15,
159 MAXB_U_SPECIAL_0_OPCODE_X1 = 14,
160 MAXH_SPECIAL_0_OPCODE_X0 = 16,
161 MAXH_SPECIAL_0_OPCODE_X1 = 15,
162 MAXIB_U_IMM_0_OPCODE_X0 = 4,
163 MAXIB_U_IMM_0_OPCODE_X1 = 5,
164 MAXIH_IMM_0_OPCODE_X0 = 5,
165 MAXIH_IMM_0_OPCODE_X1 = 6,
166 MFSPR_IMM_0_OPCODE_X1 = 7,
167 MF_UN_0_SHUN_0_OPCODE_X1 = 15,
168 MINB_U_SPECIAL_0_OPCODE_X0 = 17,
169 MINB_U_SPECIAL_0_OPCODE_X1 = 16,
170 MINH_SPECIAL_0_OPCODE_X0 = 18,
171 MINH_SPECIAL_0_OPCODE_X1 = 17,
172 MINIB_U_IMM_0_OPCODE_X0 = 6,
173 MINIB_U_IMM_0_OPCODE_X1 = 8,
174 MINIH_IMM_0_OPCODE_X0 = 7,
175 MINIH_IMM_0_OPCODE_X1 = 9,
176 MM_OPCODE_X0 = 6,
177 MM_OPCODE_X1 = 7,
178 MNZB_SPECIAL_0_OPCODE_X0 = 19,
179 MNZB_SPECIAL_0_OPCODE_X1 = 18,
180 MNZH_SPECIAL_0_OPCODE_X0 = 20,
181 MNZH_SPECIAL_0_OPCODE_X1 = 19,
182 MNZ_SPECIAL_0_OPCODE_X0 = 21,
183 MNZ_SPECIAL_0_OPCODE_X1 = 20,
184 MNZ_SPECIAL_1_OPCODE_Y0 = 0,
185 MNZ_SPECIAL_1_OPCODE_Y1 = 1,
186 MOVEI_IMM_1_OPCODE_SN = 0,
187 MOVE_RR_IMM_0_OPCODE_SN = 8,
188 MTSPR_IMM_0_OPCODE_X1 = 10,
189 MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22,
190 MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0,
191 MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23,
192 MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24,
193 MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1,
194 MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25,
195 MULHH_SS_SPECIAL_0_OPCODE_X0 = 26,
196 MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0,
197 MULHH_SU_SPECIAL_0_OPCODE_X0 = 27,
198 MULHH_UU_SPECIAL_0_OPCODE_X0 = 28,
199 MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1,
200 MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29,
201 MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30,
202 MULHLA_US_SPECIAL_0_OPCODE_X0 = 31,
203 MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32,
204 MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33,
205 MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0,
206 MULHL_SS_SPECIAL_0_OPCODE_X0 = 34,
207 MULHL_SU_SPECIAL_0_OPCODE_X0 = 35,
208 MULHL_US_SPECIAL_0_OPCODE_X0 = 36,
209 MULHL_UU_SPECIAL_0_OPCODE_X0 = 37,
210 MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38,
211 MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2,
212 MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39,
213 MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40,
214 MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3,
215 MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41,
216 MULLL_SS_SPECIAL_0_OPCODE_X0 = 42,
217 MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2,
218 MULLL_SU_SPECIAL_0_OPCODE_X0 = 43,
219 MULLL_UU_SPECIAL_0_OPCODE_X0 = 44,
220 MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3,
221 MVNZ_SPECIAL_0_OPCODE_X0 = 45,
222 MVNZ_SPECIAL_1_OPCODE_Y0 = 1,
223 MVZ_SPECIAL_0_OPCODE_X0 = 46,
224 MVZ_SPECIAL_1_OPCODE_Y0 = 2,
225 MZB_SPECIAL_0_OPCODE_X0 = 47,
226 MZB_SPECIAL_0_OPCODE_X1 = 21,
227 MZH_SPECIAL_0_OPCODE_X0 = 48,
228 MZH_SPECIAL_0_OPCODE_X1 = 22,
229 MZ_SPECIAL_0_OPCODE_X0 = 49,
230 MZ_SPECIAL_0_OPCODE_X1 = 23,
231 MZ_SPECIAL_1_OPCODE_Y0 = 3,
232 MZ_SPECIAL_1_OPCODE_Y1 = 2,
233 NAP_UN_0_SHUN_0_OPCODE_X1 = 16,
234 NOP_NOREG_RR_IMM_0_OPCODE_SN = 2,
235 NOP_UN_0_SHUN_0_OPCODE_X0 = 6,
236 NOP_UN_0_SHUN_0_OPCODE_X1 = 17,
237 NOP_UN_0_SHUN_0_OPCODE_Y0 = 6,
238 NOP_UN_0_SHUN_0_OPCODE_Y1 = 3,
239 NOREG_RR_IMM_0_OPCODE_SN = 0,
240 NOR_SPECIAL_0_OPCODE_X0 = 50,
241 NOR_SPECIAL_0_OPCODE_X1 = 24,
242 NOR_SPECIAL_2_OPCODE_Y0 = 1,
243 NOR_SPECIAL_2_OPCODE_Y1 = 1,
244 ORI_IMM_0_OPCODE_X0 = 8,
245 ORI_IMM_0_OPCODE_X1 = 11,
246 ORI_OPCODE_Y0 = 11,
247 ORI_OPCODE_Y1 = 9,
248 OR_SPECIAL_0_OPCODE_X0 = 51,
249 OR_SPECIAL_0_OPCODE_X1 = 25,
250 OR_SPECIAL_2_OPCODE_Y0 = 2,
251 OR_SPECIAL_2_OPCODE_Y1 = 2,
252 PACKBS_U_SPECIAL_0_OPCODE_X0 = 103,
253 PACKBS_U_SPECIAL_0_OPCODE_X1 = 73,
254 PACKHB_SPECIAL_0_OPCODE_X0 = 52,
255 PACKHB_SPECIAL_0_OPCODE_X1 = 26,
256 PACKHS_SPECIAL_0_OPCODE_X0 = 102,
257 PACKHS_SPECIAL_0_OPCODE_X1 = 72,
258 PACKLB_SPECIAL_0_OPCODE_X0 = 53,
259 PACKLB_SPECIAL_0_OPCODE_X1 = 27,
260 PCNT_UN_0_SHUN_0_OPCODE_X0 = 7,
261 PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7,
262 RLI_SHUN_0_OPCODE_X0 = 1,
263 RLI_SHUN_0_OPCODE_X1 = 1,
264 RLI_SHUN_0_OPCODE_Y0 = 1,
265 RLI_SHUN_0_OPCODE_Y1 = 1,
266 RL_SPECIAL_0_OPCODE_X0 = 54,
267 RL_SPECIAL_0_OPCODE_X1 = 28,
268 RL_SPECIAL_3_OPCODE_Y0 = 0,
269 RL_SPECIAL_3_OPCODE_Y1 = 0,
270 RR_IMM_0_OPCODE_SN = 0,
271 S1A_SPECIAL_0_OPCODE_X0 = 55,
272 S1A_SPECIAL_0_OPCODE_X1 = 29,
273 S1A_SPECIAL_0_OPCODE_Y0 = 1,
274 S1A_SPECIAL_0_OPCODE_Y1 = 1,
275 S2A_SPECIAL_0_OPCODE_X0 = 56,
276 S2A_SPECIAL_0_OPCODE_X1 = 30,
277 S2A_SPECIAL_0_OPCODE_Y0 = 2,
278 S2A_SPECIAL_0_OPCODE_Y1 = 2,
279 S3A_SPECIAL_0_OPCODE_X0 = 57,
280 S3A_SPECIAL_0_OPCODE_X1 = 31,
281 S3A_SPECIAL_5_OPCODE_Y0 = 1,
282 S3A_SPECIAL_5_OPCODE_Y1 = 1,
283 SADAB_U_SPECIAL_0_OPCODE_X0 = 58,
284 SADAH_SPECIAL_0_OPCODE_X0 = 59,
285 SADAH_U_SPECIAL_0_OPCODE_X0 = 60,
286 SADB_U_SPECIAL_0_OPCODE_X0 = 61,
287 SADH_SPECIAL_0_OPCODE_X0 = 62,
288 SADH_U_SPECIAL_0_OPCODE_X0 = 63,
289 SBADD_IMM_0_OPCODE_X1 = 28,
290 SB_OPCODE_Y2 = 5,
291 SB_SPECIAL_0_OPCODE_X1 = 32,
292 SEQB_SPECIAL_0_OPCODE_X0 = 64,
293 SEQB_SPECIAL_0_OPCODE_X1 = 33,
294 SEQH_SPECIAL_0_OPCODE_X0 = 65,
295 SEQH_SPECIAL_0_OPCODE_X1 = 34,
296 SEQIB_IMM_0_OPCODE_X0 = 9,
297 SEQIB_IMM_0_OPCODE_X1 = 12,
298 SEQIH_IMM_0_OPCODE_X0 = 10,
299 SEQIH_IMM_0_OPCODE_X1 = 13,
300 SEQI_IMM_0_OPCODE_X0 = 11,
301 SEQI_IMM_0_OPCODE_X1 = 14,
302 SEQI_OPCODE_Y0 = 12,
303 SEQI_OPCODE_Y1 = 10,
304 SEQ_SPECIAL_0_OPCODE_X0 = 66,
305 SEQ_SPECIAL_0_OPCODE_X1 = 35,
306 SEQ_SPECIAL_5_OPCODE_Y0 = 2,
307 SEQ_SPECIAL_5_OPCODE_Y1 = 2,
308 SHADD_IMM_0_OPCODE_X1 = 29,
309 SHL8II_IMM_0_OPCODE_SN = 3,
310 SHLB_SPECIAL_0_OPCODE_X0 = 67,
311 SHLB_SPECIAL_0_OPCODE_X1 = 36,
312 SHLH_SPECIAL_0_OPCODE_X0 = 68,
313 SHLH_SPECIAL_0_OPCODE_X1 = 37,
314 SHLIB_SHUN_0_OPCODE_X0 = 2,
315 SHLIB_SHUN_0_OPCODE_X1 = 2,
316 SHLIH_SHUN_0_OPCODE_X0 = 3,
317 SHLIH_SHUN_0_OPCODE_X1 = 3,
318 SHLI_SHUN_0_OPCODE_X0 = 4,
319 SHLI_SHUN_0_OPCODE_X1 = 4,
320 SHLI_SHUN_0_OPCODE_Y0 = 2,
321 SHLI_SHUN_0_OPCODE_Y1 = 2,
322 SHL_SPECIAL_0_OPCODE_X0 = 69,
323 SHL_SPECIAL_0_OPCODE_X1 = 38,
324 SHL_SPECIAL_3_OPCODE_Y0 = 1,
325 SHL_SPECIAL_3_OPCODE_Y1 = 1,
326 SHR1_RR_IMM_0_OPCODE_SN = 9,
327 SHRB_SPECIAL_0_OPCODE_X0 = 70,
328 SHRB_SPECIAL_0_OPCODE_X1 = 39,
329 SHRH_SPECIAL_0_OPCODE_X0 = 71,
330 SHRH_SPECIAL_0_OPCODE_X1 = 40,
331 SHRIB_SHUN_0_OPCODE_X0 = 5,
332 SHRIB_SHUN_0_OPCODE_X1 = 5,
333 SHRIH_SHUN_0_OPCODE_X0 = 6,
334 SHRIH_SHUN_0_OPCODE_X1 = 6,
335 SHRI_SHUN_0_OPCODE_X0 = 7,
336 SHRI_SHUN_0_OPCODE_X1 = 7,
337 SHRI_SHUN_0_OPCODE_Y0 = 3,
338 SHRI_SHUN_0_OPCODE_Y1 = 3,
339 SHR_SPECIAL_0_OPCODE_X0 = 72,
340 SHR_SPECIAL_0_OPCODE_X1 = 41,
341 SHR_SPECIAL_3_OPCODE_Y0 = 2,
342 SHR_SPECIAL_3_OPCODE_Y1 = 2,
343 SHUN_0_OPCODE_X0 = 7,
344 SHUN_0_OPCODE_X1 = 8,
345 SHUN_0_OPCODE_Y0 = 13,
346 SHUN_0_OPCODE_Y1 = 11,
347 SH_OPCODE_Y2 = 6,
348 SH_SPECIAL_0_OPCODE_X1 = 42,
349 SLTB_SPECIAL_0_OPCODE_X0 = 73,
350 SLTB_SPECIAL_0_OPCODE_X1 = 43,
351 SLTB_U_SPECIAL_0_OPCODE_X0 = 74,
352 SLTB_U_SPECIAL_0_OPCODE_X1 = 44,
353 SLTEB_SPECIAL_0_OPCODE_X0 = 75,
354 SLTEB_SPECIAL_0_OPCODE_X1 = 45,
355 SLTEB_U_SPECIAL_0_OPCODE_X0 = 76,
356 SLTEB_U_SPECIAL_0_OPCODE_X1 = 46,
357 SLTEH_SPECIAL_0_OPCODE_X0 = 77,
358 SLTEH_SPECIAL_0_OPCODE_X1 = 47,
359 SLTEH_U_SPECIAL_0_OPCODE_X0 = 78,
360 SLTEH_U_SPECIAL_0_OPCODE_X1 = 48,
361 SLTE_SPECIAL_0_OPCODE_X0 = 79,
362 SLTE_SPECIAL_0_OPCODE_X1 = 49,
363 SLTE_SPECIAL_4_OPCODE_Y0 = 0,
364 SLTE_SPECIAL_4_OPCODE_Y1 = 0,
365 SLTE_U_SPECIAL_0_OPCODE_X0 = 80,
366 SLTE_U_SPECIAL_0_OPCODE_X1 = 50,
367 SLTE_U_SPECIAL_4_OPCODE_Y0 = 1,
368 SLTE_U_SPECIAL_4_OPCODE_Y1 = 1,
369 SLTH_SPECIAL_0_OPCODE_X0 = 81,
370 SLTH_SPECIAL_0_OPCODE_X1 = 51,
371 SLTH_U_SPECIAL_0_OPCODE_X0 = 82,
372 SLTH_U_SPECIAL_0_OPCODE_X1 = 52,
373 SLTIB_IMM_0_OPCODE_X0 = 12,
374 SLTIB_IMM_0_OPCODE_X1 = 15,
375 SLTIB_U_IMM_0_OPCODE_X0 = 13,
376 SLTIB_U_IMM_0_OPCODE_X1 = 16,
377 SLTIH_IMM_0_OPCODE_X0 = 14,
378 SLTIH_IMM_0_OPCODE_X1 = 17,
379 SLTIH_U_IMM_0_OPCODE_X0 = 15,
380 SLTIH_U_IMM_0_OPCODE_X1 = 18,
381 SLTI_IMM_0_OPCODE_X0 = 16,
382 SLTI_IMM_0_OPCODE_X1 = 19,
383 SLTI_OPCODE_Y0 = 14,
384 SLTI_OPCODE_Y1 = 12,
385 SLTI_U_IMM_0_OPCODE_X0 = 17,
386 SLTI_U_IMM_0_OPCODE_X1 = 20,
387 SLTI_U_OPCODE_Y0 = 15,
388 SLTI_U_OPCODE_Y1 = 13,
389 SLT_SPECIAL_0_OPCODE_X0 = 83,
390 SLT_SPECIAL_0_OPCODE_X1 = 53,
391 SLT_SPECIAL_4_OPCODE_Y0 = 2,
392 SLT_SPECIAL_4_OPCODE_Y1 = 2,
393 SLT_U_SPECIAL_0_OPCODE_X0 = 84,
394 SLT_U_SPECIAL_0_OPCODE_X1 = 54,
395 SLT_U_SPECIAL_4_OPCODE_Y0 = 3,
396 SLT_U_SPECIAL_4_OPCODE_Y1 = 3,
397 SNEB_SPECIAL_0_OPCODE_X0 = 85,
398 SNEB_SPECIAL_0_OPCODE_X1 = 55,
399 SNEH_SPECIAL_0_OPCODE_X0 = 86,
400 SNEH_SPECIAL_0_OPCODE_X1 = 56,
401 SNE_SPECIAL_0_OPCODE_X0 = 87,
402 SNE_SPECIAL_0_OPCODE_X1 = 57,
403 SNE_SPECIAL_5_OPCODE_Y0 = 3,
404 SNE_SPECIAL_5_OPCODE_Y1 = 3,
405 SPECIAL_0_OPCODE_X0 = 0,
406 SPECIAL_0_OPCODE_X1 = 1,
407 SPECIAL_0_OPCODE_Y0 = 1,
408 SPECIAL_0_OPCODE_Y1 = 1,
409 SPECIAL_1_OPCODE_Y0 = 2,
410 SPECIAL_1_OPCODE_Y1 = 2,
411 SPECIAL_2_OPCODE_Y0 = 3,
412 SPECIAL_2_OPCODE_Y1 = 3,
413 SPECIAL_3_OPCODE_Y0 = 4,
414 SPECIAL_3_OPCODE_Y1 = 4,
415 SPECIAL_4_OPCODE_Y0 = 5,
416 SPECIAL_4_OPCODE_Y1 = 5,
417 SPECIAL_5_OPCODE_Y0 = 6,
418 SPECIAL_5_OPCODE_Y1 = 6,
419 SPECIAL_6_OPCODE_Y0 = 7,
420 SPECIAL_7_OPCODE_Y0 = 8,
421 SRAB_SPECIAL_0_OPCODE_X0 = 88,
422 SRAB_SPECIAL_0_OPCODE_X1 = 58,
423 SRAH_SPECIAL_0_OPCODE_X0 = 89,
424 SRAH_SPECIAL_0_OPCODE_X1 = 59,
425 SRAIB_SHUN_0_OPCODE_X0 = 8,
426 SRAIB_SHUN_0_OPCODE_X1 = 8,
427 SRAIH_SHUN_0_OPCODE_X0 = 9,
428 SRAIH_SHUN_0_OPCODE_X1 = 9,
429 SRAI_SHUN_0_OPCODE_X0 = 10,
430 SRAI_SHUN_0_OPCODE_X1 = 10,
431 SRAI_SHUN_0_OPCODE_Y0 = 4,
432 SRAI_SHUN_0_OPCODE_Y1 = 4,
433 SRA_SPECIAL_0_OPCODE_X0 = 90,
434 SRA_SPECIAL_0_OPCODE_X1 = 60,
435 SRA_SPECIAL_3_OPCODE_Y0 = 3,
436 SRA_SPECIAL_3_OPCODE_Y1 = 3,
437 SUBBS_U_SPECIAL_0_OPCODE_X0 = 100,
438 SUBBS_U_SPECIAL_0_OPCODE_X1 = 70,
439 SUBB_SPECIAL_0_OPCODE_X0 = 91,
440 SUBB_SPECIAL_0_OPCODE_X1 = 61,
441 SUBHS_SPECIAL_0_OPCODE_X0 = 101,
442 SUBHS_SPECIAL_0_OPCODE_X1 = 71,
443 SUBH_SPECIAL_0_OPCODE_X0 = 92,
444 SUBH_SPECIAL_0_OPCODE_X1 = 62,
445 SUBS_SPECIAL_0_OPCODE_X0 = 97,
446 SUBS_SPECIAL_0_OPCODE_X1 = 67,
447 SUB_SPECIAL_0_OPCODE_X0 = 93,
448 SUB_SPECIAL_0_OPCODE_X1 = 63,
449 SUB_SPECIAL_0_OPCODE_Y0 = 3,
450 SUB_SPECIAL_0_OPCODE_Y1 = 3,
451 SWADD_IMM_0_OPCODE_X1 = 30,
452 SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18,
453 SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19,
454 SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20,
455 SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21,
456 SW_OPCODE_Y2 = 7,
457 SW_SPECIAL_0_OPCODE_X1 = 64,
458 TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8,
459 TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8,
460 TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9,
461 TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9,
462 TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10,
463 TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10,
464 TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11,
465 TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11,
466 TNS_UN_0_SHUN_0_OPCODE_X1 = 22,
467 UN_0_SHUN_0_OPCODE_X0 = 11,
468 UN_0_SHUN_0_OPCODE_X1 = 11,
469 UN_0_SHUN_0_OPCODE_Y0 = 5,
470 UN_0_SHUN_0_OPCODE_Y1 = 5,
471 WH64_UN_0_SHUN_0_OPCODE_X1 = 23,
472 XORI_IMM_0_OPCODE_X0 = 2,
473 XORI_IMM_0_OPCODE_X1 = 21,
474 XOR_SPECIAL_0_OPCODE_X0 = 94,
475 XOR_SPECIAL_0_OPCODE_X1 = 65,
476 XOR_SPECIAL_2_OPCODE_Y0 = 3,
477 XOR_SPECIAL_2_OPCODE_Y1 = 3
478};
479
480#endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/opcode_constants_64.h b/arch/tile/include/asm/opcode_constants_64.h
new file mode 100644
index 00000000000..71019286947
--- /dev/null
+++ b/arch/tile/include/asm/opcode_constants_64.h
@@ -0,0 +1,609 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* This file is machine-generated; DO NOT EDIT! */
16
17
18#ifndef _TILE_OPCODE_CONSTANTS_H
19#define _TILE_OPCODE_CONSTANTS_H
20enum
21{
22 ADDI_IMM8_OPCODE_X0 = 1,
23 ADDI_IMM8_OPCODE_X1 = 1,
24 ADDI_OPCODE_Y0 = 0,
25 ADDI_OPCODE_Y1 = 1,
26 ADDLI_OPCODE_X0 = 1,
27 ADDLI_OPCODE_X1 = 0,
28 ADDXI_IMM8_OPCODE_X0 = 2,
29 ADDXI_IMM8_OPCODE_X1 = 2,
30 ADDXI_OPCODE_Y0 = 1,
31 ADDXI_OPCODE_Y1 = 2,
32 ADDXLI_OPCODE_X0 = 2,
33 ADDXLI_OPCODE_X1 = 1,
34 ADDXSC_RRR_0_OPCODE_X0 = 1,
35 ADDXSC_RRR_0_OPCODE_X1 = 1,
36 ADDX_RRR_0_OPCODE_X0 = 2,
37 ADDX_RRR_0_OPCODE_X1 = 2,
38 ADDX_RRR_0_OPCODE_Y0 = 0,
39 ADDX_SPECIAL_0_OPCODE_Y1 = 0,
40 ADD_RRR_0_OPCODE_X0 = 3,
41 ADD_RRR_0_OPCODE_X1 = 3,
42 ADD_RRR_0_OPCODE_Y0 = 1,
43 ADD_SPECIAL_0_OPCODE_Y1 = 1,
44 ANDI_IMM8_OPCODE_X0 = 3,
45 ANDI_IMM8_OPCODE_X1 = 3,
46 ANDI_OPCODE_Y0 = 2,
47 ANDI_OPCODE_Y1 = 3,
48 AND_RRR_0_OPCODE_X0 = 4,
49 AND_RRR_0_OPCODE_X1 = 4,
50 AND_RRR_5_OPCODE_Y0 = 0,
51 AND_RRR_5_OPCODE_Y1 = 0,
52 BEQZT_BRANCH_OPCODE_X1 = 16,
53 BEQZ_BRANCH_OPCODE_X1 = 17,
54 BFEXTS_BF_OPCODE_X0 = 4,
55 BFEXTU_BF_OPCODE_X0 = 5,
56 BFINS_BF_OPCODE_X0 = 6,
57 BF_OPCODE_X0 = 3,
58 BGEZT_BRANCH_OPCODE_X1 = 18,
59 BGEZ_BRANCH_OPCODE_X1 = 19,
60 BGTZT_BRANCH_OPCODE_X1 = 20,
61 BGTZ_BRANCH_OPCODE_X1 = 21,
62 BLBCT_BRANCH_OPCODE_X1 = 22,
63 BLBC_BRANCH_OPCODE_X1 = 23,
64 BLBST_BRANCH_OPCODE_X1 = 24,
65 BLBS_BRANCH_OPCODE_X1 = 25,
66 BLEZT_BRANCH_OPCODE_X1 = 26,
67 BLEZ_BRANCH_OPCODE_X1 = 27,
68 BLTZT_BRANCH_OPCODE_X1 = 28,
69 BLTZ_BRANCH_OPCODE_X1 = 29,
70 BNEZT_BRANCH_OPCODE_X1 = 30,
71 BNEZ_BRANCH_OPCODE_X1 = 31,
72 BRANCH_OPCODE_X1 = 2,
73 CMOVEQZ_RRR_0_OPCODE_X0 = 5,
74 CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
75 CMOVNEZ_RRR_0_OPCODE_X0 = 6,
76 CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
77 CMPEQI_IMM8_OPCODE_X0 = 4,
78 CMPEQI_IMM8_OPCODE_X1 = 4,
79 CMPEQI_OPCODE_Y0 = 3,
80 CMPEQI_OPCODE_Y1 = 4,
81 CMPEQ_RRR_0_OPCODE_X0 = 7,
82 CMPEQ_RRR_0_OPCODE_X1 = 5,
83 CMPEQ_RRR_3_OPCODE_Y0 = 0,
84 CMPEQ_RRR_3_OPCODE_Y1 = 2,
85 CMPEXCH4_RRR_0_OPCODE_X1 = 6,
86 CMPEXCH_RRR_0_OPCODE_X1 = 7,
87 CMPLES_RRR_0_OPCODE_X0 = 8,
88 CMPLES_RRR_0_OPCODE_X1 = 8,
89 CMPLES_RRR_2_OPCODE_Y0 = 0,
90 CMPLES_RRR_2_OPCODE_Y1 = 0,
91 CMPLEU_RRR_0_OPCODE_X0 = 9,
92 CMPLEU_RRR_0_OPCODE_X1 = 9,
93 CMPLEU_RRR_2_OPCODE_Y0 = 1,
94 CMPLEU_RRR_2_OPCODE_Y1 = 1,
95 CMPLTSI_IMM8_OPCODE_X0 = 5,
96 CMPLTSI_IMM8_OPCODE_X1 = 5,
97 CMPLTSI_OPCODE_Y0 = 4,
98 CMPLTSI_OPCODE_Y1 = 5,
99 CMPLTS_RRR_0_OPCODE_X0 = 10,
100 CMPLTS_RRR_0_OPCODE_X1 = 10,
101 CMPLTS_RRR_2_OPCODE_Y0 = 2,
102 CMPLTS_RRR_2_OPCODE_Y1 = 2,
103 CMPLTUI_IMM8_OPCODE_X0 = 6,
104 CMPLTUI_IMM8_OPCODE_X1 = 6,
105 CMPLTU_RRR_0_OPCODE_X0 = 11,
106 CMPLTU_RRR_0_OPCODE_X1 = 11,
107 CMPLTU_RRR_2_OPCODE_Y0 = 3,
108 CMPLTU_RRR_2_OPCODE_Y1 = 3,
109 CMPNE_RRR_0_OPCODE_X0 = 12,
110 CMPNE_RRR_0_OPCODE_X1 = 12,
111 CMPNE_RRR_3_OPCODE_Y0 = 1,
112 CMPNE_RRR_3_OPCODE_Y1 = 3,
113 CMULAF_RRR_0_OPCODE_X0 = 13,
114 CMULA_RRR_0_OPCODE_X0 = 14,
115 CMULFR_RRR_0_OPCODE_X0 = 15,
116 CMULF_RRR_0_OPCODE_X0 = 16,
117 CMULHR_RRR_0_OPCODE_X0 = 17,
118 CMULH_RRR_0_OPCODE_X0 = 18,
119 CMUL_RRR_0_OPCODE_X0 = 19,
120 CNTLZ_UNARY_OPCODE_X0 = 1,
121 CNTLZ_UNARY_OPCODE_Y0 = 1,
122 CNTTZ_UNARY_OPCODE_X0 = 2,
123 CNTTZ_UNARY_OPCODE_Y0 = 2,
124 CRC32_32_RRR_0_OPCODE_X0 = 20,
125 CRC32_8_RRR_0_OPCODE_X0 = 21,
126 DBLALIGN2_RRR_0_OPCODE_X0 = 22,
127 DBLALIGN2_RRR_0_OPCODE_X1 = 13,
128 DBLALIGN4_RRR_0_OPCODE_X0 = 23,
129 DBLALIGN4_RRR_0_OPCODE_X1 = 14,
130 DBLALIGN6_RRR_0_OPCODE_X0 = 24,
131 DBLALIGN6_RRR_0_OPCODE_X1 = 15,
132 DBLALIGN_RRR_0_OPCODE_X0 = 25,
133 DRAIN_UNARY_OPCODE_X1 = 1,
134 DTLBPR_UNARY_OPCODE_X1 = 2,
135 EXCH4_RRR_0_OPCODE_X1 = 16,
136 EXCH_RRR_0_OPCODE_X1 = 17,
137 FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
138 FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
139 FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
140 FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
141 FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
142 FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
143 FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
144 FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
145 FETCHADD4_RRR_0_OPCODE_X1 = 18,
146 FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
147 FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
148 FETCHADD_RRR_0_OPCODE_X1 = 21,
149 FETCHAND4_RRR_0_OPCODE_X1 = 22,
150 FETCHAND_RRR_0_OPCODE_X1 = 23,
151 FETCHOR4_RRR_0_OPCODE_X1 = 24,
152 FETCHOR_RRR_0_OPCODE_X1 = 25,
153 FINV_UNARY_OPCODE_X1 = 3,
154 FLUSHWB_UNARY_OPCODE_X1 = 4,
155 FLUSH_UNARY_OPCODE_X1 = 5,
156 FNOP_UNARY_OPCODE_X0 = 3,
157 FNOP_UNARY_OPCODE_X1 = 6,
158 FNOP_UNARY_OPCODE_Y0 = 3,
159 FNOP_UNARY_OPCODE_Y1 = 8,
160 FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
161 FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
162 FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
163 FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
164 FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
165 FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
166 FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
167 FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
168 ICOH_UNARY_OPCODE_X1 = 7,
169 ILL_UNARY_OPCODE_X1 = 8,
170 ILL_UNARY_OPCODE_Y1 = 9,
171 IMM8_OPCODE_X0 = 4,
172 IMM8_OPCODE_X1 = 3,
173 INV_UNARY_OPCODE_X1 = 9,
174 IRET_UNARY_OPCODE_X1 = 10,
175 JALRP_UNARY_OPCODE_X1 = 11,
176 JALRP_UNARY_OPCODE_Y1 = 10,
177 JALR_UNARY_OPCODE_X1 = 12,
178 JALR_UNARY_OPCODE_Y1 = 11,
179 JAL_JUMP_OPCODE_X1 = 0,
180 JRP_UNARY_OPCODE_X1 = 13,
181 JRP_UNARY_OPCODE_Y1 = 12,
182 JR_UNARY_OPCODE_X1 = 14,
183 JR_UNARY_OPCODE_Y1 = 13,
184 JUMP_OPCODE_X1 = 4,
185 J_JUMP_OPCODE_X1 = 1,
186 LD1S_ADD_IMM8_OPCODE_X1 = 7,
187 LD1S_OPCODE_Y2 = 0,
188 LD1S_UNARY_OPCODE_X1 = 15,
189 LD1U_ADD_IMM8_OPCODE_X1 = 8,
190 LD1U_OPCODE_Y2 = 1,
191 LD1U_UNARY_OPCODE_X1 = 16,
192 LD2S_ADD_IMM8_OPCODE_X1 = 9,
193 LD2S_OPCODE_Y2 = 2,
194 LD2S_UNARY_OPCODE_X1 = 17,
195 LD2U_ADD_IMM8_OPCODE_X1 = 10,
196 LD2U_OPCODE_Y2 = 3,
197 LD2U_UNARY_OPCODE_X1 = 18,
198 LD4S_ADD_IMM8_OPCODE_X1 = 11,
199 LD4S_OPCODE_Y2 = 1,
200 LD4S_UNARY_OPCODE_X1 = 19,
201 LD4U_ADD_IMM8_OPCODE_X1 = 12,
202 LD4U_OPCODE_Y2 = 2,
203 LD4U_UNARY_OPCODE_X1 = 20,
204 LDNA_UNARY_OPCODE_X1 = 21,
205 LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
206 LDNT1S_UNARY_OPCODE_X1 = 22,
207 LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
208 LDNT1U_UNARY_OPCODE_X1 = 23,
209 LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
210 LDNT2S_UNARY_OPCODE_X1 = 24,
211 LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
212 LDNT2U_UNARY_OPCODE_X1 = 25,
213 LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
214 LDNT4S_UNARY_OPCODE_X1 = 26,
215 LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
216 LDNT4U_UNARY_OPCODE_X1 = 27,
217 LDNT_ADD_IMM8_OPCODE_X1 = 19,
218 LDNT_UNARY_OPCODE_X1 = 28,
219 LD_ADD_IMM8_OPCODE_X1 = 20,
220 LD_OPCODE_Y2 = 3,
221 LD_UNARY_OPCODE_X1 = 29,
222 LNK_UNARY_OPCODE_X1 = 30,
223 LNK_UNARY_OPCODE_Y1 = 14,
224 LWNA_ADD_IMM8_OPCODE_X1 = 21,
225 MFSPR_IMM8_OPCODE_X1 = 22,
226 MF_UNARY_OPCODE_X1 = 31,
227 MM_BF_OPCODE_X0 = 7,
228 MNZ_RRR_0_OPCODE_X0 = 40,
229 MNZ_RRR_0_OPCODE_X1 = 26,
230 MNZ_RRR_4_OPCODE_Y0 = 2,
231 MNZ_RRR_4_OPCODE_Y1 = 2,
232 MODE_OPCODE_YA2 = 1,
233 MODE_OPCODE_YB2 = 2,
234 MODE_OPCODE_YC2 = 3,
235 MTSPR_IMM8_OPCODE_X1 = 23,
236 MULAX_RRR_0_OPCODE_X0 = 41,
237 MULAX_RRR_3_OPCODE_Y0 = 2,
238 MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
239 MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
240 MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
241 MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
242 MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
243 MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
244 MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
245 MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
246 MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
247 MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
248 MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
249 MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
250 MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
251 MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
252 MULX_RRR_0_OPCODE_X0 = 52,
253 MULX_RRR_3_OPCODE_Y0 = 3,
254 MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
255 MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
256 MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
257 MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
258 MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
259 MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
260 MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
261 MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
262 MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
263 MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
264 MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
265 MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
266 MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
267 MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
268 MZ_RRR_0_OPCODE_X0 = 63,
269 MZ_RRR_0_OPCODE_X1 = 27,
270 MZ_RRR_4_OPCODE_Y0 = 3,
271 MZ_RRR_4_OPCODE_Y1 = 3,
272 NAP_UNARY_OPCODE_X1 = 32,
273 NOP_UNARY_OPCODE_X0 = 5,
274 NOP_UNARY_OPCODE_X1 = 33,
275 NOP_UNARY_OPCODE_Y0 = 5,
276 NOP_UNARY_OPCODE_Y1 = 15,
277 NOR_RRR_0_OPCODE_X0 = 64,
278 NOR_RRR_0_OPCODE_X1 = 28,
279 NOR_RRR_5_OPCODE_Y0 = 1,
280 NOR_RRR_5_OPCODE_Y1 = 1,
281 ORI_IMM8_OPCODE_X0 = 7,
282 ORI_IMM8_OPCODE_X1 = 24,
283 OR_RRR_0_OPCODE_X0 = 65,
284 OR_RRR_0_OPCODE_X1 = 29,
285 OR_RRR_5_OPCODE_Y0 = 2,
286 OR_RRR_5_OPCODE_Y1 = 2,
287 PCNT_UNARY_OPCODE_X0 = 6,
288 PCNT_UNARY_OPCODE_Y0 = 6,
289 REVBITS_UNARY_OPCODE_X0 = 7,
290 REVBITS_UNARY_OPCODE_Y0 = 7,
291 REVBYTES_UNARY_OPCODE_X0 = 8,
292 REVBYTES_UNARY_OPCODE_Y0 = 8,
293 ROTLI_SHIFT_OPCODE_X0 = 1,
294 ROTLI_SHIFT_OPCODE_X1 = 1,
295 ROTLI_SHIFT_OPCODE_Y0 = 0,
296 ROTLI_SHIFT_OPCODE_Y1 = 0,
297 ROTL_RRR_0_OPCODE_X0 = 66,
298 ROTL_RRR_0_OPCODE_X1 = 30,
299 ROTL_RRR_6_OPCODE_Y0 = 0,
300 ROTL_RRR_6_OPCODE_Y1 = 0,
301 RRR_0_OPCODE_X0 = 5,
302 RRR_0_OPCODE_X1 = 5,
303 RRR_0_OPCODE_Y0 = 5,
304 RRR_0_OPCODE_Y1 = 6,
305 RRR_1_OPCODE_Y0 = 6,
306 RRR_1_OPCODE_Y1 = 7,
307 RRR_2_OPCODE_Y0 = 7,
308 RRR_2_OPCODE_Y1 = 8,
309 RRR_3_OPCODE_Y0 = 8,
310 RRR_3_OPCODE_Y1 = 9,
311 RRR_4_OPCODE_Y0 = 9,
312 RRR_4_OPCODE_Y1 = 10,
313 RRR_5_OPCODE_Y0 = 10,
314 RRR_5_OPCODE_Y1 = 11,
315 RRR_6_OPCODE_Y0 = 11,
316 RRR_6_OPCODE_Y1 = 12,
317 RRR_7_OPCODE_Y0 = 12,
318 RRR_7_OPCODE_Y1 = 13,
319 RRR_8_OPCODE_Y0 = 13,
320 RRR_9_OPCODE_Y0 = 14,
321 SHIFT_OPCODE_X0 = 6,
322 SHIFT_OPCODE_X1 = 6,
323 SHIFT_OPCODE_Y0 = 15,
324 SHIFT_OPCODE_Y1 = 14,
325 SHL16INSLI_OPCODE_X0 = 7,
326 SHL16INSLI_OPCODE_X1 = 7,
327 SHL1ADDX_RRR_0_OPCODE_X0 = 67,
328 SHL1ADDX_RRR_0_OPCODE_X1 = 31,
329 SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
330 SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
331 SHL1ADD_RRR_0_OPCODE_X0 = 68,
332 SHL1ADD_RRR_0_OPCODE_X1 = 32,
333 SHL1ADD_RRR_1_OPCODE_Y0 = 0,
334 SHL1ADD_RRR_1_OPCODE_Y1 = 0,
335 SHL2ADDX_RRR_0_OPCODE_X0 = 69,
336 SHL2ADDX_RRR_0_OPCODE_X1 = 33,
337 SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
338 SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
339 SHL2ADD_RRR_0_OPCODE_X0 = 70,
340 SHL2ADD_RRR_0_OPCODE_X1 = 34,
341 SHL2ADD_RRR_1_OPCODE_Y0 = 1,
342 SHL2ADD_RRR_1_OPCODE_Y1 = 1,
343 SHL3ADDX_RRR_0_OPCODE_X0 = 71,
344 SHL3ADDX_RRR_0_OPCODE_X1 = 35,
345 SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
346 SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
347 SHL3ADD_RRR_0_OPCODE_X0 = 72,
348 SHL3ADD_RRR_0_OPCODE_X1 = 36,
349 SHL3ADD_RRR_1_OPCODE_Y0 = 2,
350 SHL3ADD_RRR_1_OPCODE_Y1 = 2,
351 SHLI_SHIFT_OPCODE_X0 = 2,
352 SHLI_SHIFT_OPCODE_X1 = 2,
353 SHLI_SHIFT_OPCODE_Y0 = 1,
354 SHLI_SHIFT_OPCODE_Y1 = 1,
355 SHLXI_SHIFT_OPCODE_X0 = 3,
356 SHLXI_SHIFT_OPCODE_X1 = 3,
357 SHLX_RRR_0_OPCODE_X0 = 73,
358 SHLX_RRR_0_OPCODE_X1 = 37,
359 SHL_RRR_0_OPCODE_X0 = 74,
360 SHL_RRR_0_OPCODE_X1 = 38,
361 SHL_RRR_6_OPCODE_Y0 = 1,
362 SHL_RRR_6_OPCODE_Y1 = 1,
363 SHRSI_SHIFT_OPCODE_X0 = 4,
364 SHRSI_SHIFT_OPCODE_X1 = 4,
365 SHRSI_SHIFT_OPCODE_Y0 = 2,
366 SHRSI_SHIFT_OPCODE_Y1 = 2,
367 SHRS_RRR_0_OPCODE_X0 = 75,
368 SHRS_RRR_0_OPCODE_X1 = 39,
369 SHRS_RRR_6_OPCODE_Y0 = 2,
370 SHRS_RRR_6_OPCODE_Y1 = 2,
371 SHRUI_SHIFT_OPCODE_X0 = 5,
372 SHRUI_SHIFT_OPCODE_X1 = 5,
373 SHRUI_SHIFT_OPCODE_Y0 = 3,
374 SHRUI_SHIFT_OPCODE_Y1 = 3,
375 SHRUXI_SHIFT_OPCODE_X0 = 6,
376 SHRUXI_SHIFT_OPCODE_X1 = 6,
377 SHRUX_RRR_0_OPCODE_X0 = 76,
378 SHRUX_RRR_0_OPCODE_X1 = 40,
379 SHRU_RRR_0_OPCODE_X0 = 77,
380 SHRU_RRR_0_OPCODE_X1 = 41,
381 SHRU_RRR_6_OPCODE_Y0 = 3,
382 SHRU_RRR_6_OPCODE_Y1 = 3,
383 SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
384 ST1_ADD_IMM8_OPCODE_X1 = 25,
385 ST1_OPCODE_Y2 = 0,
386 ST1_RRR_0_OPCODE_X1 = 42,
387 ST2_ADD_IMM8_OPCODE_X1 = 26,
388 ST2_OPCODE_Y2 = 1,
389 ST2_RRR_0_OPCODE_X1 = 43,
390 ST4_ADD_IMM8_OPCODE_X1 = 27,
391 ST4_OPCODE_Y2 = 2,
392 ST4_RRR_0_OPCODE_X1 = 44,
393 STNT1_ADD_IMM8_OPCODE_X1 = 28,
394 STNT1_RRR_0_OPCODE_X1 = 45,
395 STNT2_ADD_IMM8_OPCODE_X1 = 29,
396 STNT2_RRR_0_OPCODE_X1 = 46,
397 STNT4_ADD_IMM8_OPCODE_X1 = 30,
398 STNT4_RRR_0_OPCODE_X1 = 47,
399 STNT_ADD_IMM8_OPCODE_X1 = 31,
400 STNT_RRR_0_OPCODE_X1 = 48,
401 ST_ADD_IMM8_OPCODE_X1 = 32,
402 ST_OPCODE_Y2 = 3,
403 ST_RRR_0_OPCODE_X1 = 49,
404 SUBXSC_RRR_0_OPCODE_X0 = 79,
405 SUBXSC_RRR_0_OPCODE_X1 = 50,
406 SUBX_RRR_0_OPCODE_X0 = 80,
407 SUBX_RRR_0_OPCODE_X1 = 51,
408 SUBX_RRR_0_OPCODE_Y0 = 2,
409 SUBX_RRR_0_OPCODE_Y1 = 2,
410 SUB_RRR_0_OPCODE_X0 = 81,
411 SUB_RRR_0_OPCODE_X1 = 52,
412 SUB_RRR_0_OPCODE_Y0 = 3,
413 SUB_RRR_0_OPCODE_Y1 = 3,
414 SWINT0_UNARY_OPCODE_X1 = 34,
415 SWINT1_UNARY_OPCODE_X1 = 35,
416 SWINT2_UNARY_OPCODE_X1 = 36,
417 SWINT3_UNARY_OPCODE_X1 = 37,
418 TBLIDXB0_UNARY_OPCODE_X0 = 9,
419 TBLIDXB0_UNARY_OPCODE_Y0 = 9,
420 TBLIDXB1_UNARY_OPCODE_X0 = 10,
421 TBLIDXB1_UNARY_OPCODE_Y0 = 10,
422 TBLIDXB2_UNARY_OPCODE_X0 = 11,
423 TBLIDXB2_UNARY_OPCODE_Y0 = 11,
424 TBLIDXB3_UNARY_OPCODE_X0 = 12,
425 TBLIDXB3_UNARY_OPCODE_Y0 = 12,
426 UNARY_RRR_0_OPCODE_X0 = 82,
427 UNARY_RRR_0_OPCODE_X1 = 53,
428 UNARY_RRR_1_OPCODE_Y0 = 3,
429 UNARY_RRR_1_OPCODE_Y1 = 3,
430 V1ADDI_IMM8_OPCODE_X0 = 8,
431 V1ADDI_IMM8_OPCODE_X1 = 33,
432 V1ADDUC_RRR_0_OPCODE_X0 = 83,
433 V1ADDUC_RRR_0_OPCODE_X1 = 54,
434 V1ADD_RRR_0_OPCODE_X0 = 84,
435 V1ADD_RRR_0_OPCODE_X1 = 55,
436 V1ADIFFU_RRR_0_OPCODE_X0 = 85,
437 V1AVGU_RRR_0_OPCODE_X0 = 86,
438 V1CMPEQI_IMM8_OPCODE_X0 = 9,
439 V1CMPEQI_IMM8_OPCODE_X1 = 34,
440 V1CMPEQ_RRR_0_OPCODE_X0 = 87,
441 V1CMPEQ_RRR_0_OPCODE_X1 = 56,
442 V1CMPLES_RRR_0_OPCODE_X0 = 88,
443 V1CMPLES_RRR_0_OPCODE_X1 = 57,
444 V1CMPLEU_RRR_0_OPCODE_X0 = 89,
445 V1CMPLEU_RRR_0_OPCODE_X1 = 58,
446 V1CMPLTSI_IMM8_OPCODE_X0 = 10,
447 V1CMPLTSI_IMM8_OPCODE_X1 = 35,
448 V1CMPLTS_RRR_0_OPCODE_X0 = 90,
449 V1CMPLTS_RRR_0_OPCODE_X1 = 59,
450 V1CMPLTUI_IMM8_OPCODE_X0 = 11,
451 V1CMPLTUI_IMM8_OPCODE_X1 = 36,
452 V1CMPLTU_RRR_0_OPCODE_X0 = 91,
453 V1CMPLTU_RRR_0_OPCODE_X1 = 60,
454 V1CMPNE_RRR_0_OPCODE_X0 = 92,
455 V1CMPNE_RRR_0_OPCODE_X1 = 61,
456 V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
457 V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
458 V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
459 V1DDOTPU_RRR_0_OPCODE_X0 = 162,
460 V1DOTPA_RRR_0_OPCODE_X0 = 95,
461 V1DOTPUA_RRR_0_OPCODE_X0 = 163,
462 V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
463 V1DOTPUS_RRR_0_OPCODE_X0 = 97,
464 V1DOTPU_RRR_0_OPCODE_X0 = 164,
465 V1DOTP_RRR_0_OPCODE_X0 = 98,
466 V1INT_H_RRR_0_OPCODE_X0 = 99,
467 V1INT_H_RRR_0_OPCODE_X1 = 62,
468 V1INT_L_RRR_0_OPCODE_X0 = 100,
469 V1INT_L_RRR_0_OPCODE_X1 = 63,
470 V1MAXUI_IMM8_OPCODE_X0 = 12,
471 V1MAXUI_IMM8_OPCODE_X1 = 37,
472 V1MAXU_RRR_0_OPCODE_X0 = 101,
473 V1MAXU_RRR_0_OPCODE_X1 = 64,
474 V1MINUI_IMM8_OPCODE_X0 = 13,
475 V1MINUI_IMM8_OPCODE_X1 = 38,
476 V1MINU_RRR_0_OPCODE_X0 = 102,
477 V1MINU_RRR_0_OPCODE_X1 = 65,
478 V1MNZ_RRR_0_OPCODE_X0 = 103,
479 V1MNZ_RRR_0_OPCODE_X1 = 66,
480 V1MULTU_RRR_0_OPCODE_X0 = 104,
481 V1MULUS_RRR_0_OPCODE_X0 = 105,
482 V1MULU_RRR_0_OPCODE_X0 = 106,
483 V1MZ_RRR_0_OPCODE_X0 = 107,
484 V1MZ_RRR_0_OPCODE_X1 = 67,
485 V1SADAU_RRR_0_OPCODE_X0 = 108,
486 V1SADU_RRR_0_OPCODE_X0 = 109,
487 V1SHLI_SHIFT_OPCODE_X0 = 7,
488 V1SHLI_SHIFT_OPCODE_X1 = 7,
489 V1SHL_RRR_0_OPCODE_X0 = 110,
490 V1SHL_RRR_0_OPCODE_X1 = 68,
491 V1SHRSI_SHIFT_OPCODE_X0 = 8,
492 V1SHRSI_SHIFT_OPCODE_X1 = 8,
493 V1SHRS_RRR_0_OPCODE_X0 = 111,
494 V1SHRS_RRR_0_OPCODE_X1 = 69,
495 V1SHRUI_SHIFT_OPCODE_X0 = 9,
496 V1SHRUI_SHIFT_OPCODE_X1 = 9,
497 V1SHRU_RRR_0_OPCODE_X0 = 112,
498 V1SHRU_RRR_0_OPCODE_X1 = 70,
499 V1SUBUC_RRR_0_OPCODE_X0 = 113,
500 V1SUBUC_RRR_0_OPCODE_X1 = 71,
501 V1SUB_RRR_0_OPCODE_X0 = 114,
502 V1SUB_RRR_0_OPCODE_X1 = 72,
503 V2ADDI_IMM8_OPCODE_X0 = 14,
504 V2ADDI_IMM8_OPCODE_X1 = 39,
505 V2ADDSC_RRR_0_OPCODE_X0 = 115,
506 V2ADDSC_RRR_0_OPCODE_X1 = 73,
507 V2ADD_RRR_0_OPCODE_X0 = 116,
508 V2ADD_RRR_0_OPCODE_X1 = 74,
509 V2ADIFFS_RRR_0_OPCODE_X0 = 117,
510 V2AVGS_RRR_0_OPCODE_X0 = 118,
511 V2CMPEQI_IMM8_OPCODE_X0 = 15,
512 V2CMPEQI_IMM8_OPCODE_X1 = 40,
513 V2CMPEQ_RRR_0_OPCODE_X0 = 119,
514 V2CMPEQ_RRR_0_OPCODE_X1 = 75,
515 V2CMPLES_RRR_0_OPCODE_X0 = 120,
516 V2CMPLES_RRR_0_OPCODE_X1 = 76,
517 V2CMPLEU_RRR_0_OPCODE_X0 = 121,
518 V2CMPLEU_RRR_0_OPCODE_X1 = 77,
519 V2CMPLTSI_IMM8_OPCODE_X0 = 16,
520 V2CMPLTSI_IMM8_OPCODE_X1 = 41,
521 V2CMPLTS_RRR_0_OPCODE_X0 = 122,
522 V2CMPLTS_RRR_0_OPCODE_X1 = 78,
523 V2CMPLTUI_IMM8_OPCODE_X0 = 17,
524 V2CMPLTUI_IMM8_OPCODE_X1 = 42,
525 V2CMPLTU_RRR_0_OPCODE_X0 = 123,
526 V2CMPLTU_RRR_0_OPCODE_X1 = 79,
527 V2CMPNE_RRR_0_OPCODE_X0 = 124,
528 V2CMPNE_RRR_0_OPCODE_X1 = 80,
529 V2DOTPA_RRR_0_OPCODE_X0 = 125,
530 V2DOTP_RRR_0_OPCODE_X0 = 126,
531 V2INT_H_RRR_0_OPCODE_X0 = 127,
532 V2INT_H_RRR_0_OPCODE_X1 = 81,
533 V2INT_L_RRR_0_OPCODE_X0 = 128,
534 V2INT_L_RRR_0_OPCODE_X1 = 82,
535 V2MAXSI_IMM8_OPCODE_X0 = 18,
536 V2MAXSI_IMM8_OPCODE_X1 = 43,
537 V2MAXS_RRR_0_OPCODE_X0 = 129,
538 V2MAXS_RRR_0_OPCODE_X1 = 83,
539 V2MINSI_IMM8_OPCODE_X0 = 19,
540 V2MINSI_IMM8_OPCODE_X1 = 44,
541 V2MINS_RRR_0_OPCODE_X0 = 130,
542 V2MINS_RRR_0_OPCODE_X1 = 84,
543 V2MNZ_RRR_0_OPCODE_X0 = 131,
544 V2MNZ_RRR_0_OPCODE_X1 = 85,
545 V2MULFSC_RRR_0_OPCODE_X0 = 132,
546 V2MULS_RRR_0_OPCODE_X0 = 133,
547 V2MULTS_RRR_0_OPCODE_X0 = 134,
548 V2MZ_RRR_0_OPCODE_X0 = 135,
549 V2MZ_RRR_0_OPCODE_X1 = 86,
550 V2PACKH_RRR_0_OPCODE_X0 = 136,
551 V2PACKH_RRR_0_OPCODE_X1 = 87,
552 V2PACKL_RRR_0_OPCODE_X0 = 137,
553 V2PACKL_RRR_0_OPCODE_X1 = 88,
554 V2PACKUC_RRR_0_OPCODE_X0 = 138,
555 V2PACKUC_RRR_0_OPCODE_X1 = 89,
556 V2SADAS_RRR_0_OPCODE_X0 = 139,
557 V2SADAU_RRR_0_OPCODE_X0 = 140,
558 V2SADS_RRR_0_OPCODE_X0 = 141,
559 V2SADU_RRR_0_OPCODE_X0 = 142,
560 V2SHLI_SHIFT_OPCODE_X0 = 10,
561 V2SHLI_SHIFT_OPCODE_X1 = 10,
562 V2SHLSC_RRR_0_OPCODE_X0 = 143,
563 V2SHLSC_RRR_0_OPCODE_X1 = 90,
564 V2SHL_RRR_0_OPCODE_X0 = 144,
565 V2SHL_RRR_0_OPCODE_X1 = 91,
566 V2SHRSI_SHIFT_OPCODE_X0 = 11,
567 V2SHRSI_SHIFT_OPCODE_X1 = 11,
568 V2SHRS_RRR_0_OPCODE_X0 = 145,
569 V2SHRS_RRR_0_OPCODE_X1 = 92,
570 V2SHRUI_SHIFT_OPCODE_X0 = 12,
571 V2SHRUI_SHIFT_OPCODE_X1 = 12,
572 V2SHRU_RRR_0_OPCODE_X0 = 146,
573 V2SHRU_RRR_0_OPCODE_X1 = 93,
574 V2SUBSC_RRR_0_OPCODE_X0 = 147,
575 V2SUBSC_RRR_0_OPCODE_X1 = 94,
576 V2SUB_RRR_0_OPCODE_X0 = 148,
577 V2SUB_RRR_0_OPCODE_X1 = 95,
578 V4ADDSC_RRR_0_OPCODE_X0 = 149,
579 V4ADDSC_RRR_0_OPCODE_X1 = 96,
580 V4ADD_RRR_0_OPCODE_X0 = 150,
581 V4ADD_RRR_0_OPCODE_X1 = 97,
582 V4INT_H_RRR_0_OPCODE_X0 = 151,
583 V4INT_H_RRR_0_OPCODE_X1 = 98,
584 V4INT_L_RRR_0_OPCODE_X0 = 152,
585 V4INT_L_RRR_0_OPCODE_X1 = 99,
586 V4PACKSC_RRR_0_OPCODE_X0 = 153,
587 V4PACKSC_RRR_0_OPCODE_X1 = 100,
588 V4SHLSC_RRR_0_OPCODE_X0 = 154,
589 V4SHLSC_RRR_0_OPCODE_X1 = 101,
590 V4SHL_RRR_0_OPCODE_X0 = 155,
591 V4SHL_RRR_0_OPCODE_X1 = 102,
592 V4SHRS_RRR_0_OPCODE_X0 = 156,
593 V4SHRS_RRR_0_OPCODE_X1 = 103,
594 V4SHRU_RRR_0_OPCODE_X0 = 157,
595 V4SHRU_RRR_0_OPCODE_X1 = 104,
596 V4SUBSC_RRR_0_OPCODE_X0 = 158,
597 V4SUBSC_RRR_0_OPCODE_X1 = 105,
598 V4SUB_RRR_0_OPCODE_X0 = 159,
599 V4SUB_RRR_0_OPCODE_X1 = 106,
600 WH64_UNARY_OPCODE_X1 = 38,
601 XORI_IMM8_OPCODE_X0 = 20,
602 XORI_IMM8_OPCODE_X1 = 45,
603 XOR_RRR_0_OPCODE_X0 = 160,
604 XOR_RRR_0_OPCODE_X1 = 107,
605 XOR_RRR_5_OPCODE_Y0 = 3,
606 XOR_RRR_5_OPCODE_Y1 = 3
607};
608
609#endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/sigcontext.h b/arch/tile/include/asm/sigcontext.h
new file mode 100644
index 00000000000..5e2d03336f5
--- /dev/null
+++ b/arch/tile/include/asm/sigcontext.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SIGCONTEXT_H
16#define _ASM_TILE_SIGCONTEXT_H
17
18#include <arch/abi.h>
19
20/*
21 * struct sigcontext has the same shape as struct pt_regs,
22 * but is simplified since we know the fault is from userspace.
23 */
24struct sigcontext {
25 uint_reg_t gregs[53]; /* General-purpose registers. */
26 uint_reg_t tp; /* Aliases gregs[TREG_TP]. */
27 uint_reg_t sp; /* Aliases gregs[TREG_SP]. */
28 uint_reg_t lr; /* Aliases gregs[TREG_LR]. */
29 uint_reg_t pc; /* Program counter. */
30 uint_reg_t ics; /* In Interrupt Critical Section? */
31 uint_reg_t faultnum; /* Fault number. */
32 uint_reg_t pad[5];
33};
34
35#endif /* _ASM_TILE_SIGCONTEXT_H */
diff --git a/arch/tile/include/asm/siginfo.h b/arch/tile/include/asm/siginfo.h
new file mode 100644
index 00000000000..56d661bb010
--- /dev/null
+++ b/arch/tile/include/asm/siginfo.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SIGINFO_H
16#define _ASM_TILE_SIGINFO_H
17
18#define __ARCH_SI_TRAPNO
19
20#ifdef __LP64__
21# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
22#endif
23
24#include <asm-generic/siginfo.h>
25
26/*
27 * Additional Tile-specific SIGILL si_codes
28 */
29#define ILL_DBLFLT (__SI_FAULT|9) /* double fault */
30#define ILL_HARDWALL (__SI_FAULT|10) /* user networks hardwall violation */
31#undef NSIGILL
32#define NSIGILL 10
33
34#endif /* _ASM_TILE_SIGINFO_H */
diff --git a/arch/tile/include/asm/stat.h b/arch/tile/include/asm/stat.h
new file mode 100644
index 00000000000..c0db34d56be
--- /dev/null
+++ b/arch/tile/include/asm/stat.h
@@ -0,0 +1,4 @@
1#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
2#define __ARCH_WANT_STAT64 /* Used for compat_sys_stat64() etc. */
3#endif
4#include <asm-generic/stat.h>
diff --git a/arch/tile/include/asm/swab.h b/arch/tile/include/asm/swab.h
new file mode 100644
index 00000000000..7c37b38f6c8
--- /dev/null
+++ b/arch/tile/include/asm/swab.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SWAB_H
16#define _ASM_TILE_SWAB_H
17
18/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
19#define __arch_swab32(x) __builtin_bswap32(x)
20#define __arch_swab64(x) __builtin_bswap64(x)
21#define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
22
23#endif /* _ASM_TILE_SWAB_H */
diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h
new file mode 100644
index 00000000000..23d1842f483
--- /dev/null
+++ b/arch/tile/include/asm/system.h
@@ -0,0 +1,261 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SYSTEM_H
16#define _ASM_TILE_SYSTEM_H
17
18#ifndef __ASSEMBLY__
19
20#include <linux/types.h>
21#include <linux/irqflags.h>
22
23/* NOTE: we can't include <linux/ptrace.h> due to #include dependencies. */
24#include <asm/ptrace.h>
25
26#include <arch/chip.h>
27#include <arch/sim_def.h>
28#include <arch/spr_def.h>
29
30/*
31 * read_barrier_depends - Flush all pending reads that subsequents reads
32 * depend on.
33 *
34 * No data-dependent reads from memory-like regions are ever reordered
35 * over this barrier. All reads preceding this primitive are guaranteed
36 * to access memory (but not necessarily other CPUs' caches) before any
37 * reads following this primitive that depend on the data return by
38 * any of the preceding reads. This primitive is much lighter weight than
39 * rmb() on most CPUs, and is never heavier weight than is
40 * rmb().
41 *
42 * These ordering constraints are respected by both the local CPU
43 * and the compiler.
44 *
45 * Ordering is not guaranteed by anything other than these primitives,
46 * not even by data dependencies. See the documentation for
47 * memory_barrier() for examples and URLs to more information.
48 *
49 * For example, the following code would force ordering (the initial
50 * value of "a" is zero, "b" is one, and "p" is "&a"):
51 *
52 * <programlisting>
53 * CPU 0 CPU 1
54 *
55 * b = 2;
56 * memory_barrier();
57 * p = &b; q = p;
58 * read_barrier_depends();
59 * d = *q;
60 * </programlisting>
61 *
62 * because the read of "*q" depends on the read of "p" and these
63 * two reads are separated by a read_barrier_depends(). However,
64 * the following code, with the same initial values for "a" and "b":
65 *
66 * <programlisting>
67 * CPU 0 CPU 1
68 *
69 * a = 2;
70 * memory_barrier();
71 * b = 3; y = b;
72 * read_barrier_depends();
73 * x = a;
74 * </programlisting>
75 *
76 * does not enforce ordering, since there is no data dependency between
77 * the read of "a" and the read of "b". Therefore, on some CPUs, such
78 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
79 * in cases like this where there are no data dependencies.
80 */
81
82#define read_barrier_depends() do { } while (0)
83
84#define __sync() __insn_mf()
85
86#if CHIP_HAS_SPLIT_CYCLE()
87#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW)
88#else
89#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
90#endif
91
92#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
93#include <hv/syscall_public.h>
94/*
95 * Issue an uncacheable load to each memory controller, then
96 * wait until those loads have completed.
97 */
98static inline void __mb_incoherent(void)
99{
100 long clobber_r10;
101 asm volatile("swint2"
102 : "=R10" (clobber_r10)
103 : "R10" (HV_SYS_fence_incoherent)
104 : "r0", "r1", "r2", "r3", "r4",
105 "r5", "r6", "r7", "r8", "r9",
106 "r11", "r12", "r13", "r14",
107 "r15", "r16", "r17", "r18", "r19",
108 "r20", "r21", "r22", "r23", "r24",
109 "r25", "r26", "r27", "r28", "r29");
110}
111#endif
112
113/* Fence to guarantee visibility of stores to incoherent memory. */
114static inline void
115mb_incoherent(void)
116{
117 __insn_mf();
118
119#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
120 {
121#if CHIP_HAS_TILE_WRITE_PENDING()
122 const unsigned long WRITE_TIMEOUT_CYCLES = 400;
123 unsigned long start = get_cycles_low();
124 do {
125 if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
126 return;
127 } while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
128#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
129 (void) __mb_incoherent();
130 }
131#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */
132}
133
134#define fast_wmb() __sync()
135#define fast_rmb() __sync()
136#define fast_mb() __sync()
137#define fast_iob() mb_incoherent()
138
139#define wmb() fast_wmb()
140#define rmb() fast_rmb()
141#define mb() fast_mb()
142#define iob() fast_iob()
143
144#ifdef CONFIG_SMP
145#define smp_mb() mb()
146#define smp_rmb() rmb()
147#define smp_wmb() wmb()
148#define smp_read_barrier_depends() read_barrier_depends()
149#else
150#define smp_mb() barrier()
151#define smp_rmb() barrier()
152#define smp_wmb() barrier()
153#define smp_read_barrier_depends() do { } while (0)
154#endif
155
156#define set_mb(var, value) \
157 do { var = value; mb(); } while (0)
158
159/*
160 * Pause the DMA engine and static network before task switching.
161 */
162#define prepare_arch_switch(next) _prepare_arch_switch(next)
163void _prepare_arch_switch(struct task_struct *next);
164
165
166/*
167 * switch_to(n) should switch tasks to task nr n, first
168 * checking that n isn't the current task, in which case it does nothing.
169 * The number of callee-saved registers saved on the kernel stack
170 * is defined here for use in copy_thread() and must agree with __switch_to().
171 */
172#endif /* !__ASSEMBLY__ */
173#define CALLEE_SAVED_FIRST_REG 30
174#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */
175#ifndef __ASSEMBLY__
176struct task_struct;
177#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next)))
178extern struct task_struct *_switch_to(struct task_struct *prev,
179 struct task_struct *next);
180
181/* Helper function for _switch_to(). */
182extern struct task_struct *__switch_to(struct task_struct *prev,
183 struct task_struct *next,
184 unsigned long new_system_save_k_0);
185
186/* Address that switched-away from tasks are at. */
187extern unsigned long get_switch_to_pc(void);
188
189/*
190 * On SMP systems, when the scheduler does migration-cost autodetection,
191 * it needs a way to flush as much of the CPU's caches as possible:
192 *
193 * TODO: fill this in!
194 */
195static inline void sched_cacheflush(void)
196{
197}
198
199#define arch_align_stack(x) (x)
200
201/*
202 * Is the kernel doing fixups of unaligned accesses? If <0, no kernel
203 * intervention occurs and SIGBUS is delivered with no data address
204 * info. If 0, the kernel single-steps the instruction to discover
205 * the data address to provide with the SIGBUS. If 1, the kernel does
206 * a fixup.
207 */
208extern int unaligned_fixup;
209
210/* Is the kernel printing on each unaligned fixup? */
211extern int unaligned_printk;
212
213/* Number of unaligned fixups performed */
214extern unsigned int unaligned_fixup_count;
215
216/* Init-time routine to do tile-specific per-cpu setup. */
217void setup_cpu(int boot);
218
219/* User-level DMA management functions */
220void grant_dma_mpls(void);
221void restrict_dma_mpls(void);
222
223#ifdef CONFIG_HARDWALL
224/* User-level network management functions */
225void reset_network_state(void);
226void grant_network_mpls(void);
227void restrict_network_mpls(void);
228int hardwall_deactivate(struct task_struct *task);
229
230/* Hook hardwall code into changes in affinity. */
231#define arch_set_cpus_allowed(p, new_mask) do { \
232 if (p->thread.hardwall && !cpumask_equal(&p->cpus_allowed, new_mask)) \
233 hardwall_deactivate(p); \
234} while (0)
235#endif
236
237/*
238 * Kernel threads can check to see if they need to migrate their
239 * stack whenever they return from a context switch; for user
240 * threads, we defer until they are returning to user-space.
241 */
242#define finish_arch_switch(prev) do { \
243 if (unlikely((prev)->state == TASK_DEAD)) \
244 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
245 ((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
246 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
247 (current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
248 if (current->mm == NULL && !kstack_hash && \
249 current_thread_info()->homecache_cpu != smp_processor_id()) \
250 homecache_migrate_kthread(); \
251} while (0)
252
253/* Support function for forking a new task. */
254void ret_from_fork(void);
255
256/* Called from ret_from_fork() when a new process starts up. */
257struct task_struct *sim_notify_fork(struct task_struct *prev);
258
259#endif /* !__ASSEMBLY__ */
260
261#endif /* _ASM_TILE_SYSTEM_H */
diff --git a/arch/tile/kernel/init_task.c b/arch/tile/kernel/init_task.c
new file mode 100644
index 00000000000..928b3187066
--- /dev/null
+++ b/arch/tile/kernel/init_task.c
@@ -0,0 +1,59 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/mm.h>
16#include <linux/fs.h>
17#include <linux/init_task.h>
18#include <linux/mqueue.h>
19#include <linux/module.h>
20#include <linux/start_kernel.h>
21#include <linux/uaccess.h>
22
23static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
24static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
25
26/*
27 * Initial thread structure.
28 *
29 * We need to make sure that this is THREAD_SIZE aligned due to the
30 * way process stacks are handled. This is done by having a special
31 * "init_task" linker map entry..
32 */
33union thread_union init_thread_union __init_task_data = {
34 INIT_THREAD_INFO(init_task)
35};
36
37/*
38 * Initial task structure.
39 *
40 * All other task structs will be allocated on slabs in fork.c
41 */
42struct task_struct init_task = INIT_TASK(init_task);
43EXPORT_SYMBOL(init_task);
44
45/*
46 * per-CPU stack and boot info.
47 */
48DEFINE_PER_CPU(unsigned long, boot_sp) =
49 (unsigned long)init_stack + THREAD_SIZE;
50
51#ifdef CONFIG_SMP
52DEFINE_PER_CPU(unsigned long, boot_pc) = (unsigned long)start_kernel;
53#else
54/*
55 * The variable must be __initdata since it references __init code.
56 * With CONFIG_SMP it is per-cpu data, which is exempt from validation.
57 */
58unsigned long __initdata boot_pc = (unsigned long)start_kernel;
59#endif
diff --git a/arch/tile/kernel/relocate_kernel.S b/arch/tile/kernel/relocate_kernel.S
new file mode 100644
index 00000000000..010b418515f
--- /dev/null
+++ b/arch/tile/kernel/relocate_kernel.S
@@ -0,0 +1,280 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * copy new kernel into place and then call hv_reexec
15 *
16 */
17
18#include <linux/linkage.h>
19#include <arch/chip.h>
20#include <asm/page.h>
21#include <hv/hypervisor.h>
22
23#define ___hvb MEM_SV_INTRPT + HV_GLUE_START_CPA
24
25#define ___hv_dispatch(f) (___hvb + (HV_DISPATCH_ENTRY_SIZE * f))
26
27#define ___hv_console_putc ___hv_dispatch(HV_DISPATCH_CONSOLE_PUTC)
28#define ___hv_halt ___hv_dispatch(HV_DISPATCH_HALT)
29#define ___hv_reexec ___hv_dispatch(HV_DISPATCH_REEXEC)
30#define ___hv_flush_remote ___hv_dispatch(HV_DISPATCH_FLUSH_REMOTE)
31
32#undef RELOCATE_NEW_KERNEL_VERBOSE
33
34STD_ENTRY(relocate_new_kernel)
35
36 move r30, r0 /* page list */
37 move r31, r1 /* address of page we are on */
38 move r32, r2 /* start address of new kernel */
39
40 shri r1, r1, PAGE_SHIFT
41 addi r1, r1, 1
42 shli sp, r1, PAGE_SHIFT
43 addi sp, sp, -8
44 /* we now have a stack (whether we need one or not) */
45
46 moveli r40, lo16(___hv_console_putc)
47 auli r40, r40, ha16(___hv_console_putc)
48
49#ifdef RELOCATE_NEW_KERNEL_VERBOSE
50 moveli r0, 'r'
51 jalr r40
52
53 moveli r0, '_'
54 jalr r40
55
56 moveli r0, 'n'
57 jalr r40
58
59 moveli r0, '_'
60 jalr r40
61
62 moveli r0, 'k'
63 jalr r40
64
65 moveli r0, '\n'
66 jalr r40
67#endif
68
69 /*
70 * Throughout this code r30 is pointer to the element of page
71 * list we are working on.
72 *
73 * Normally we get to the next element of the page list by
74 * incrementing r30 by four. The exception is if the element
75 * on the page list is an IND_INDIRECTION in which case we use
76 * the element with the low bits masked off as the new value
77 * of r30.
78 *
79 * To get this started, we need the value passed to us (which
80 * will always be an IND_INDIRECTION) in memory somewhere with
81 * r30 pointing at it. To do that, we push the value passed
82 * to us on the stack and make r30 point to it.
83 */
84
85 sw sp, r30
86 move r30, sp
87 addi sp, sp, -8
88
89#if CHIP_HAS_CBOX_HOME_MAP()
90 /*
91 * On TILEPro, we need to flush all tiles' caches, since we may
92 * have been doing hash-for-home caching there. Note that we
93 * must do this _after_ we're completely done modifying any memory
94 * other than our output buffer (which we know is locally cached).
95 * We want the caches to be fully clean when we do the reexec,
96 * because the hypervisor is going to do this flush again at that
97 * point, and we don't want that second flush to overwrite any memory.
98 */
99 {
100 move r0, zero /* cache_pa */
101 move r1, zero
102 }
103 {
104 auli r2, zero, ha16(HV_FLUSH_EVICT_L2) /* cache_control */
105 movei r3, -1 /* cache_cpumask; -1 means all client tiles */
106 }
107 {
108 move r4, zero /* tlb_va */
109 move r5, zero /* tlb_length */
110 }
111 {
112 move r6, zero /* tlb_pgsize */
113 move r7, zero /* tlb_cpumask */
114 }
115 {
116 move r8, zero /* asids */
117 moveli r20, lo16(___hv_flush_remote)
118 }
119 {
120 move r9, zero /* asidcount */
121 auli r20, r20, ha16(___hv_flush_remote)
122 }
123
124 jalr r20
125#endif
126
127 /* r33 is destination pointer, default to zero */
128
129 moveli r33, 0
130
131.Lloop: lw r10, r30
132
133 andi r9, r10, 0xf /* low 4 bits tell us what type it is */
134 xor r10, r10, r9 /* r10 is now value with low 4 bits stripped */
135
136 seqi r0, r9, 0x1 /* IND_DESTINATION */
137 bzt r0, .Ltry2
138
139 move r33, r10
140
141#ifdef RELOCATE_NEW_KERNEL_VERBOSE
142 moveli r0, 'd'
143 jalr r40
144#endif
145
146 addi r30, r30, 4
147 j .Lloop
148
149.Ltry2:
150 seqi r0, r9, 0x2 /* IND_INDIRECTION */
151 bzt r0, .Ltry4
152
153 move r30, r10
154
155#ifdef RELOCATE_NEW_KERNEL_VERBOSE
156 moveli r0, 'i'
157 jalr r40
158#endif
159
160 j .Lloop
161
162.Ltry4:
163 seqi r0, r9, 0x4 /* IND_DONE */
164 bzt r0, .Ltry8
165
166 mf
167
168#ifdef RELOCATE_NEW_KERNEL_VERBOSE
169 moveli r0, 'D'
170 jalr r40
171 moveli r0, '\n'
172 jalr r40
173#endif
174
175 move r0, r32
176 moveli r1, 0 /* arg to hv_reexec is 64 bits */
177
178 moveli r41, lo16(___hv_reexec)
179 auli r41, r41, ha16(___hv_reexec)
180
181 jalr r41
182
183 /* we should not get here */
184
185 moveli r0, '?'
186 jalr r40
187 moveli r0, '\n'
188 jalr r40
189
190 j .Lhalt
191
192.Ltry8: seqi r0, r9, 0x8 /* IND_SOURCE */
193 bz r0, .Lerr /* unknown type */
194
195 /* copy page at r10 to page at r33 */
196
197 move r11, r33
198
199 moveli r0, lo16(PAGE_SIZE)
200 auli r0, r0, ha16(PAGE_SIZE)
201 add r33, r33, r0
202
203 /* copy word at r10 to word at r11 until r11 equals r33 */
204
205 /* We know page size must be multiple of 16, so we can unroll
206 * 16 times safely without any edge case checking.
207 *
208 * Issue a flush of the destination every 16 words to avoid
209 * incoherence when starting the new kernel. (Now this is
210 * just good paranoia because the hv_reexec call will also
211 * take care of this.)
212 */
213
2141:
215 { lw r0, r10; addi r10, r10, 4 }
216 { sw r11, r0; addi r11, r11, 4 }
217 { lw r0, r10; addi r10, r10, 4 }
218 { sw r11, r0; addi r11, r11, 4 }
219 { lw r0, r10; addi r10, r10, 4 }
220 { sw r11, r0; addi r11, r11, 4 }
221 { lw r0, r10; addi r10, r10, 4 }
222 { sw r11, r0; addi r11, r11, 4 }
223 { lw r0, r10; addi r10, r10, 4 }
224 { sw r11, r0; addi r11, r11, 4 }
225 { lw r0, r10; addi r10, r10, 4 }
226 { sw r11, r0; addi r11, r11, 4 }
227 { lw r0, r10; addi r10, r10, 4 }
228 { sw r11, r0; addi r11, r11, 4 }
229 { lw r0, r10; addi r10, r10, 4 }
230 { sw r11, r0; addi r11, r11, 4 }
231 { lw r0, r10; addi r10, r10, 4 }
232 { sw r11, r0; addi r11, r11, 4 }
233 { lw r0, r10; addi r10, r10, 4 }
234 { sw r11, r0; addi r11, r11, 4 }
235 { lw r0, r10; addi r10, r10, 4 }
236 { sw r11, r0; addi r11, r11, 4 }
237 { lw r0, r10; addi r10, r10, 4 }
238 { sw r11, r0; addi r11, r11, 4 }
239 { lw r0, r10; addi r10, r10, 4 }
240 { sw r11, r0; addi r11, r11, 4 }
241 { lw r0, r10; addi r10, r10, 4 }
242 { sw r11, r0; addi r11, r11, 4 }
243 { lw r0, r10; addi r10, r10, 4 }
244 { sw r11, r0; addi r11, r11, 4 }
245 { lw r0, r10; addi r10, r10, 4 }
246 { sw r11, r0 }
247 { flush r11 ; addi r11, r11, 4 }
248
249 seq r0, r33, r11
250 bzt r0, 1b
251
252#ifdef RELOCATE_NEW_KERNEL_VERBOSE
253 moveli r0, 's'
254 jalr r40
255#endif
256
257 addi r30, r30, 4
258 j .Lloop
259
260
261.Lerr: moveli r0, 'e'
262 jalr r40
263 moveli r0, 'r'
264 jalr r40
265 moveli r0, 'r'
266 jalr r40
267 moveli r0, '\n'
268 jalr r40
269.Lhalt:
270 moveli r41, lo16(___hv_halt)
271 auli r41, r41, ha16(___hv_halt)
272
273 jalr r41
274 STD_ENDPROC(relocate_new_kernel)
275
276 .section .rodata,"a"
277
278 .globl relocate_new_kernel_size
279relocate_new_kernel_size:
280 .long .Lend_relocate_new_kernel - relocate_new_kernel